From f9162b15c12c009e882574c58457cd31d163dcae Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Fri, 29 Jan 2016 15:16:40 -0500
Subject: arm: imx: Add support for GE Bx50v3 boards

Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index c72a150..dc0894a 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -60,6 +60,18 @@ config TARGET_CM_FX6
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 
+config TARGET_GE_B450V3
+	bool "General Electric B450v3"
+	select MX6Q
+
+config TARGET_GE_B650V3
+	bool "General Electric B650v3"
+	select MX6Q
+
+config TARGET_GE_B850V3
+	bool "General Electric B850v3"
+	select MX6Q
+
 config TARGET_GW_VENTANA
 	bool "gw_ventana"
 	select SUPPORT_SPL
@@ -158,6 +170,7 @@ endchoice
 config SYS_SOC
 	default "mx6"
 
+source "board/ge/bx50v3/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"
diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
new file mode 100644
index 0000000..d50dece
--- /dev/null
+++ b/board/ge/bx50v3/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+
+config IMX_CONFIG
+	default "board/ge/bx50v3/bx50v3.cfg"
+
+config SYS_BOARD
+	default "bx50v3"
+
+config SYS_VENDOR
+	default "ge"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "ge_bx50v3"
+
+endif
diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS
new file mode 100644
index 0000000..8e60791
--- /dev/null
+++ b/board/ge/bx50v3/MAINTAINERS
@@ -0,0 +1,8 @@
+GE_BX50V3 BOARD
+M:	Martin Donnelly <martin.donnelly@ge.com>
+S:	Maintained
+F:	board/ge/bx50v3/
+F:	include/configs/ge_bx50v3.h
+F:	configs/ge_b450v3_defconfig
+F:	configs/ge_b650v3_defconfig
+F:	configs/ge_b850v3_defconfig
diff --git a/board/ge/bx50v3/Makefile b/board/ge/bx50v3/Makefile
new file mode 100644
index 0000000..bcd149f
--- /dev/null
+++ b/board/ge/bx50v3/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2015 Timesys Corporation
+# Copyright 2015 General Electric Company
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := bx50v3.o
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
new file mode 100644
index 0000000..70c298d
--- /dev/null
+++ b/board/ge/bx50v3/bx50v3.c
@@ -0,0 +1,533 @@
+/*
+ * Copyright 2015 Timesys Corporation
+ * Copyright 2015 General Electric Company
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	/* AR8033 PHY Reset */
+	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset AR8033 PHY */
+	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
+		.gp = IMX_GPIO_NR(5, 26)
+	}
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info i2c_pad_info3 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+static iomux_v3_cfg_t const pcie_pads[] = {
+	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_pcie(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
+#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = 1; /* eMMC is always present */
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = !gpio_get_value(USDHC4_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_direction_input(USDHC2_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 2:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			gpio_direction_input(USDHC4_CD_GPIO);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers\n"
+			       "(%d) then supported by the board (%d)\n",
+			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
+	/* set device address 0x7 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	/* offset 0x8016: CLK_25M Clock Select */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	/* enable register write, no post increment, address 0x7 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+	/* set to 125 MHz from local PLL source */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
+
+	/* rgmii tx clock delay enable */
+	/* set debug port address: SerDes Test and System Mode Control */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	/* enable rgmii tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Power for LVDS Display */
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
+	/* Backlight enable for LVDS display */
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+int board_cfb_skip(void)
+{
+	gpio_direction_output(LVDS_POWER_GP, 1);
+
+	return 0;
+}
+
+static int detect_baseboard(struct display_info_t const *dev)
+{
+	if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
+	    IS_ENABLED(CONFIG_TARGET_GE_B650V3))
+		return 1;
+
+	return 0;
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= -1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_baseboard,
+	.enable	= NULL,
+	.mode	= {
+		.name           = "G121X1-L03",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 20,
+		.right_margin   = 300,
+		.upper_margin   = 30,
+		.lower_margin   = 8,
+		.hsync_len      = 1,
+		.vsync_len      = 1,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 3,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+	     | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		       IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+		       IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlights off until needed */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	gpio_direction_input(LVDS_POWER_GP);
+	gpio_direction_input(LVDS_BACKLIGHT_GP);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+	setup_pcie();
+
+	return cpu_eth_init(bis);
+}
+
+static iomux_v3_cfg_t const misc_pads[] = {
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
+#define WIFI_EN	IMX_GPIO_NR(6, 14)
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(misc_pads,
+					 ARRAY_SIZE(misc_pads));
+
+	setup_iomux_uart();
+
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gpio_direction_output(SUS_S3_OUT, 1);
+	gpio_direction_output(WIFI_EN, 1);
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	/* We need at least 200ms between power on and backlight on
+	 * as per specifications from CHI MEI */
+	mdelay(250);
+
+	/* Backlight Power */
+	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
diff --git a/board/ge/bx50v3/bx50v3.cfg b/board/ge/bx50v3/bx50v3.cfg
new file mode 100644
index 0000000..de88769
--- /dev/null
+++ b/board/ge/bx50v3/bx50v3.cfg
@@ -0,0 +1,151 @@
+/*
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* DDR IO */
+DATA 4, MX6_IOM_GRP_DDR_TYPE,	0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE,	0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1,	0x00000030
+DATA 4, MX6_IOM_DRAM_CAS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RAS,	0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS,	0x00000030
+DATA 4, MX6_IOM_DRAM_RESET,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2,	0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1,	0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS,	0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL,	0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6,	0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7,	0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE,	0x00020000
+DATA 4, MX6_IOM_GRP_B0DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B1DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B2DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B3DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B4DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B5DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B6DS,	0x00000030
+DATA 4, MX6_IOM_GRP_B7DS,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6,	0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7,	0x00000030
+
+/* Calibrations */
+/* ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/* Read DQS Gating calibration */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0,	0x45380544
+DATA 4, MX6_MMDC_P0_MPDGCTRL1,	0x05280530
+DATA 4, MX6_MMDC_P1_MPDGCTRL0,	0x4530053C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1,	0x0530050C
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL,	0x36303032
+DATA 4, MX6_MMDC_P1_MPRDDLCTL,	0x38363042
+/* Write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL,	0x3A3A423E
+DATA 4, MX6_MMDC_P1_MPWRDLCTL,	0x4A38483E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800
+
+/* MMDC init */
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC,	0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0,	0x8A8F79A4
+DATA 4, MX6_MMDC_P0_MDCFG1,	0xDB538E64
+DATA 4, MX6_MMDC_P0_MDCFG2,	0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC,	0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD,	0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR,	0x008F1023
+DATA 4, MX6_MMDC_P0_MDASP,	0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL,	0x841a0000
+
+/* Initialize Micron MT41J128M */
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR,	0x0408803a
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR,	0x0000803b
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00408031
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00408039
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR,	0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR,	0x04008048
+DATA 4, MX6_MMDC_P0_MDREF,	0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL,	0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL,	0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC,	0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR,	0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR,	0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  1	   --> CKO1 enabled
+ * cko1_div 111  --> divide by 8
+ * cko1_sel 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
new file mode 100644
index 0000000..02873ce
--- /dev/null
+++ b/configs/ge_b450v3_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_B450V3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
new file mode 100644
index 0000000..3d10b35
--- /dev/null
+++ b/configs/ge_b650v3_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_B650V3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
new file mode 100644
index 0000000..e3f4a0a
--- /dev/null
+++ b/configs/ge_b850v3_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_B850V3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
new file mode 100644
index 0000000..6fa4a9a
--- /dev/null
+++ b/include/configs/ge_bx50v3.h
@@ -0,0 +1,349 @@
+/*
+ * Copyright (C) 2015 Timesys Corporation
+ * Copyright (C) 2015 General Electric Company
+ * Copyright (C) 2014 Advantech
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the GE MX6Q Bx50v3 boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GE_BX50V3_CONFIG_H
+#define __GE_BX50V3_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#if defined(CONFIG_TARGET_GE_B450V3)
+#define CONFIG_BOARD_NAME	"General Electric B450v3"
+#define CONFIG_DEFAULT_FDT_FILE	"/boot/imx6q-b450v3.dtb"
+#elif defined(CONFIG_TARGET_GE_B650V3)
+#define CONFIG_BOARD_NAME	"General Electric B650v3"
+#define CONFIG_DEFAULT_FDT_FILE	"/boot/imx6q-b650v3.dtb"
+#elif defined(CONFIG_TARGET_GE_B850V3)
+#define CONFIG_BOARD_NAME	"General Electric B850v3"
+#define CONFIG_DEFAULT_FDT_FILE	"/boot/imx6q-b850v3.dtb"
+#else
+#define CONFIG_BOARD_NAME	"General Electric BA16 Generic"
+#define CONFIG_DEFAULT_FDT_FILE	"/boot/imx6q-ba16.dtb"
+#endif
+
+#define CONFIG_MXC_UART_BASE	UART3_BASE
+#define CONFIG_CONSOLE_DEV	"ttymxc2"
+
+#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+#define CONFIG_BOOTDELAY               1
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* SATA Configs */
+#define CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_G_DNL_VENDOR_NUM   0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM  0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Advantech"
+
+/* Networking Configs */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME		"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		4
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* Serial Flash */
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED	20000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+
+/* Command definition */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_LOADADDR	0x12000000
+#define CONFIG_SYS_TEXT_BASE	0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=/boot/uImage\0" \
+	"uboot=u-boot.imx\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=yes\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONFIG_CONSOLE_DEV "\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"sddev=0\0" \
+	"emmcdev=1\0" \
+	"partnum=1\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"update_sf_uboot=" \
+		"if tftp $loadaddr $uboot; then " \
+			"sf probe; " \
+			"sf erase 0 0xC0000; " \
+			"sf write $loadaddr 0x400 $filesize; " \
+			"echo 'U-Boot upgraded. Please reset'; " \
+		"fi\0" \
+	"setargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/${rootdev} rw rootwait cma=128M\0" \
+	"loadbootscript=" \
+		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
+		" source\0" \
+	"loadimage=" \
+		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+	"loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
+	"tryboot=" \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run doboot; " \
+			"fi; " \
+		"fi;\0" \
+	"doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+		"run setargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"usb start; " \
+	"setenv dev usb; " \
+	"setenv devnum 0; " \
+	"setenv rootdev sda1; " \
+	"run tryboot; " \
+	\
+	"setenv dev mmc; " \
+	"setenv rootdev mmcblk0p1; " \
+	\
+	"setenv devnum ${sddev}; " \
+	"if mmc dev ${devnum}; then " \
+		"run tryboot; " \
+		"setenv rootdev mmcblk1p1; " \
+	"fi; " \
+	\
+	"setenv devnum ${emmcdev}; " \
+	"if mmc dev ${devnum}; then " \
+		"run tryboot; " \
+	"fi; " \
+	\
+	"bmode usb; " \
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE		(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#undef CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(1, 5)
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+
+#endif	/* __GE_BX50V3_CONFIG_H */
-- 
cgit v0.10.2


From bf393998c7644c456b339c5071c55cacf95d2141 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 22 Feb 2016 18:41:47 -0300
Subject: mx7_common: Remove unexisting options

CONFIG_IMX_FIXED_IVT_OFFSET and CONFIG_FSL_CLK are not used
anywhere, so just remove them.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index fac7c3f..b2a8756 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -27,7 +27,6 @@
 
 /* Enable iomux-lpsr support */
 #define CONFIG_IOMUX_LPSR
-#define CONFIG_IMX_FIXED_IVT_OFFSET
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN           (32 * SZ_1M)
@@ -38,8 +37,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_FSL_CLK
-
 #define CONFIG_LOADADDR                 0x80800000
 #define CONFIG_SYS_TEXT_BASE            0x87800000
 
-- 
cgit v0.10.2


From 5d69269deed053d2733bdd0fe537fcba663c0826 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 22 Feb 2016 18:41:48 -0300
Subject: mx7dsabresd: Define serial port locally

CONFIG_MXC_UART_BASE should not be defined in mx7_common.h as
the console port can vary from board to board.

Define CONFIG_MXC_UART_BASE locally instead.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index b2a8756..bfad696 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -77,7 +77,6 @@
 
 /* UART */
 #define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
 
 /* MMC */
 #define CONFIG_MMC
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 2c981e0..b8b5b45 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -14,6 +14,8 @@
 #define CONFIG_DBG_MONITOR
 #define PHYS_SDRAM_SIZE			SZ_1G
 
+#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
+
 /* Uncomment to enable secure boot support */
 /* #define CONFIG_SECURE_BOOT */
 #define CONFIG_CSF_SIZE			0x4000
-- 
cgit v0.10.2


From e25a0656bac63c5fcd20ef4313dc09c409fc512d Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sun, 28 Feb 2016 12:33:17 -0300
Subject: mx7: Distinguish between dual and solo versions

Read the number of cores in the fuses to distinguish between
the dual and solo versions.

Tested on a mx7d sabresd and on a mx7solo warp7.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index ba6cfb9..073bbc6 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -165,6 +165,21 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 	return val;
 }
 
+static bool is_mx7d(void)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+	int val;
+
+	val = readl(&fuse->tester4);
+	if (val & 1)
+		return false;
+	else
+		return true;
+}
+
 u32 get_cpu_rev(void)
 {
 	struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
@@ -172,6 +187,9 @@ u32 get_cpu_rev(void)
 	u32 reg = readl(&ccm_anatop->digprog);
 	u32 type = (reg >> 16) & 0xff;
 
+	if (!is_mx7d())
+		type = MXC_CPU_MX7S;
+
 	reg &= 0xff;
 	return (type << 12) | reg;
 }
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 656bb60..5fb3ed8 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -137,6 +137,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX7S:
+		return "7SOLO";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
 		return "7D";	/* Dual-core version of the mx7 */
 	case MXC_CPU_MX6QP:
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 8a75902..7c63c13 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -21,6 +21,7 @@
 #define MXC_CPU_MX6D		0x67
 #define MXC_CPU_MX6DP		0x68
 #define MXC_CPU_MX6QP		0x69
+#define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
 
-- 
cgit v0.10.2


From b777789ebd193587a8e4700dce656523df821370 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Wed, 9 Mar 2016 16:13:48 +0800
Subject: imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 91a3deb..bdd41b0 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+	else
+		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }
 
-- 
cgit v0.10.2


From e4dc3fc0681bd205b1db6336b0ea3849b5c683e9 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 9 Mar 2016 16:44:36 +0800
Subject: imx: mx6ul: skip setting ahb rate

To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bdd41b0..f29901f 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -328,13 +328,18 @@ int arch_cpu_init(void)
 	 */
 	init_bandgap();
 
-	/*
-	 * When low freq boot is enabled, ROM will not set AHB
-	 * freq, so we need to ensure AHB freq is 132MHz in such
-	 * scenario.
-	 */
-	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
-		set_ahb_rate(132000000);
+	if (!IS_ENABLED(CONFIG_MX6UL)) {
+		/*
+		 * When low freq boot is enabled, ROM will not set AHB
+		 * freq, so we need to ensure AHB freq is 132MHz in such
+		 * scenario.
+		 *
+		 * To i.MX6UL, when power up, default ARM core and
+		 * AHB rate is 396M and 132M.
+		 */
+		if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+			set_ahb_rate(132000000);
+	}
 
 		/* Set perclk to source from OSC 24MHz */
 #if defined(CONFIG_MX6SL)
-- 
cgit v0.10.2


From 7082d879164fe7af549ca911a7b675ce698186e1 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 9 Mar 2016 16:44:37 +0800
Subject: imx: mx6ul configure the PMIC_STBY_REQ pin as open drain

Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f29901f..d4b22ad 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -341,7 +341,17 @@ int arch_cpu_init(void)
 			set_ahb_rate(132000000);
 	}
 
-		/* Set perclk to source from OSC 24MHz */
+	if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
+		/*
+		 * According to the design team's requirement on i.MX6UL,
+		 * the PMIC_STBY_REQ PAD should be configured as open
+		 * drain 100K (0x0000b8a0).
+		 * Only exists on TO1.0
+		 */
+		writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+	}
+
+	/* Set perclk to source from OSC 24MHz */
 #if defined(CONFIG_MX6SL)
 	set_preclk_from_osc();
 #endif
-- 
cgit v0.10.2


From d78e7f2794f7ae380c0c25027b7872d4f4cca322 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 9 Mar 2016 16:44:38 +0800
Subject: imx: print ARM clock for clocks command

Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=> clocks
PLL_SYS         792 MHz
PLL_BUS         528 MHz
PLL_OTG         480 MHz
PLL_NET          50 MHz

ARM          396000 kHz
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 88380a6..3b53842 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1183,6 +1183,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("PLL_NET    %8d MHz\n", freq / 1000000);
 
 	printf("\n");
+	printf("ARM        %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 #ifdef CONFIG_MXC_SPI
-- 
cgit v0.10.2


From 08cb448315755f4d5b18f667b1076a1c30a0e388 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 20 Mar 2016 17:53:53 +0100
Subject: arm: mx5: Enable NAND TrimFFS on M53EVK

Enable NAND TrimFFS support in M53EVK, since it is convenient when
installing UBI images to NAND.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 1efe48c..dc85768 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -41,6 +41,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
 #define CONFIG_CMD_USB
-- 
cgit v0.10.2


From b10d93ee9e56ff1848aaf739d19dd9bd43af4ce9 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 2 Mar 2016 14:49:51 +0100
Subject: arm: imx6: Switch DDR3 calibration to wait_for_bit()

Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index e457feb..1e7ae28 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -12,40 +12,20 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/types.h>
+#include <wait_bit.h>
 
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
-	unsigned int timeout = 1000;
-	u32 val;
-
-	while (--timeout) {
-		val = readl(reg);
-		if (!set)
-			val = ~val;
-
-		if ((val & mask) == mask)
-			return 0;
-
-		udelay(1);
-	}
-
-	printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
-	      __func__, reg, mask, set);
-	hang();	/* DRAM couldn't be calibrated, game over :-( */
-}
-
 static void reset_read_data_fifos(void)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 
 	/* Reset data FIFOs twice. */
 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-	wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 
 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-	wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 }
 
 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
@@ -60,12 +40,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable)
 	 */
 	if (cs0_enable) { /* CS0 */
 		writel(0x04008050, &mmdc0->mdscr);
-		wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+		wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
 	}
 
 	if (cs1_enable) { /* CS1 */
 		writel(0x04008058, &mmdc0->mdscr);
-		wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+		wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
 	}
 }
 
@@ -164,7 +144,7 @@ int mmdc_do_write_level_calibration(void)
 	 * 7. Upon completion of this process the MMDC de-asserts
 	 * the MPWLGCR[HW_WL_EN]
 	 */
-	wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0);
+	wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
 
 	/*
 	 * 8. check for any errors: check both PHYs for x64 configuration,
@@ -289,7 +269,7 @@ int mmdc_do_dqs_calibration(void)
 		writel(0x00008028, &mmdc0->mdscr);
 
 	/* poll to make sure the con_ack bit was asserted */
-	wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+	wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
 
 	/*
 	 * Check MDMISC register CALIB_PER_CS to see which CS calibration
@@ -327,7 +307,7 @@ int mmdc_do_dqs_calibration(void)
 	 * this bit until it clears to indicate completion of the write access.
 	 */
 	setbits_le32(&mmdc0->mpswdar0, 1);
-	wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0);
+	wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
 
 	/* Set the RD_DL_ABS# bits to their default values
 	 * (will be calibrated later in the read delay-line calibration).
@@ -372,7 +352,7 @@ int mmdc_do_dqs_calibration(void)
 	setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
 
 	/* Poll for completion.  MPDGCTRL0[HW_DG_EN] should be 0 */
-	wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0);
+	wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
 
 	/*
 	 * Check to see if any errors were encountered during calibration
@@ -431,7 +411,7 @@ int mmdc_do_dqs_calibration(void)
 	 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0.   Also, ensure that
 	 * no error bits were set.
 	 */
-	wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0);
+	wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
 
 	/* check both PHYs for x64 configuration, if x32, check only PHY0 */
 	if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
@@ -484,7 +464,7 @@ int mmdc_do_dqs_calibration(void)
 	 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
 	 * Also, ensure that no error bits were set.
 	 */
-	wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0);
+	wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
 
 	/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
 	if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
@@ -532,7 +512,7 @@ int mmdc_do_dqs_calibration(void)
 	writel(0x0, &mmdc0->mdscr);	/* CS0 */
 
 	/* Poll to make sure the con_ack bit is clear */
-	wait_for_bit(&mmdc0->mdscr, 1 << 14, 0);
+	wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
 
 	/*
 	 * Print out the registers that were updated as a result
-- 
cgit v0.10.2


From 8fb9eea5653796fea69a45b82cacb6d378a569f0 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 21 Mar 2016 11:00:53 -0300
Subject: mx6sabre_common: Fix U-Boot corruption after 'saveenv'

Booting mx6qp sabreauto board and then doing:

=> saveenv
=> reset

, causes a system hang.

This happens because the size of the U-Boot binary is larger than
CONFIG_ENV_OFFSET.

Fix this problem by increasing CONFIG_ENV_OFFSET, so that the U-boot binary
and the environment variables region do not overlap.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index a6d821b..112f187 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -209,7 +209,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 
 #if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_ENV_OFFSET		(8 * 64 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
 #endif
 
 /* Framebuffer */
-- 
cgit v0.10.2


From f7440928e609734f6d24d6769927539762270e1e Mon Sep 17 00:00:00 2001
From: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Date: Sun, 20 Mar 2016 14:10:55 +0100
Subject: mx27: 16-bit wide watchdog registers

Make the watchdog registers 16-bit wide, as they are according to TRM.

Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c
index f7b4a1c..e764986 100644
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx27/reset.c
@@ -27,14 +27,14 @@ void reset_cpu(ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
-	writel(0x00000000, &regs->wcr);
+	writew(0x0000, &regs->wcr);
 
 	/* Write Service Sequence */
-	writel(0x00005555, &regs->wsr);
-	writel(0x0000AAAA, &regs->wsr);
+	writew(0x5555, &regs->wsr);
+	writew(0xAAAA, &regs->wsr);
 
 	/* Enable watchdog */
-	writel(WCR_WDE, &regs->wcr);
+	writew(WCR_WDE, &regs->wcr);
 
 	while (1);
 	/*NOTREACHED*/
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index baf1d29..40b76d2 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -106,9 +106,9 @@ struct esdramc_regs {
 
 /* Watchdog Registers*/
 struct wdog_regs {
-	u32 wcr;
-	u32 wsr;
-	u32 wstr;
+	u16 wcr;
+	u16 wsr;
+	u16 wstr;
 };
 
 /* PLL registers */
-- 
cgit v0.10.2


From 779594d3356f313541c82dd9aa05900a22984982 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Wed, 16 Mar 2016 12:55:03 -0300
Subject: mx6sabresd: Use VESA 1024x768 timings

VESA 1024x768 results in much more accurate timings.

Based on the patch from Soeren Moch for the tbs2910 board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index e9d9664..727334a 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -386,13 +386,13 @@ struct display_info_t const displays[] = {{
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
@@ -406,13 +406,13 @@ struct display_info_t const displays[] = {{
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
-- 
cgit v0.10.2


From 227c59a856fd2d3cd2f571baf5fdf53103b55a3a Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 29 Feb 2016 09:33:21 -0300
Subject: mx7_common: Put early/late init configs into board file

CONFIG_BOARD_EARLY_INIT_F and CONFIG_BOARD_LATE_INIT should not be
placed into mx7_common because not all boards need these options.

Move them to the board file instead.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index dcc53f0..5034464 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -31,9 +31,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN           (32 * SZ_1M)
 
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index b8b5b45..988d363 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -16,6 +16,9 @@
 
 #define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
 
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
 /* Uncomment to enable secure boot support */
 /* #define CONFIG_SECURE_BOOT */
 #define CONFIG_CSF_SIZE			0x4000
-- 
cgit v0.10.2


From 47173483a322078cb2dbb7f49a614c98b67e3339 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 29 Feb 2016 09:33:22 -0300
Subject: warp7: Add initial support

Add the basic support for Warp7 board.

For more information about this reference design, please visit:

https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index 97d6238..8e1ddcd 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -18,11 +18,18 @@ config TARGET_MX7DSABRESD
 	select DM
 	select DM_THERMAL
 
+config TARGET_WARP7
+	bool "warp7"
+	select MX7D
+	select DM
+	select DM_THERMAL
+
 endchoice
 
 config SYS_SOC
 	default "mx7"
 
 source "board/freescale/mx7dsabresd/Kconfig"
+source "board/warp7/Kconfig"
 
 endif
diff --git a/board/warp7/Kconfig b/board/warp7/Kconfig
new file mode 100644
index 0000000..61c33fb
--- /dev/null
+++ b/board/warp7/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_WARP7
+
+config SYS_BOARD
+	default "warp7"
+
+config SYS_CONFIG_NAME
+	default "warp7"
+
+endif
diff --git a/board/warp7/MAINTAINERS b/board/warp7/MAINTAINERS
new file mode 100644
index 0000000..1d3ee29
--- /dev/null
+++ b/board/warp7/MAINTAINERS
@@ -0,0 +1,6 @@
+WARP7 BOARD
+M:	Fabio Estevam <fabio.estevam@nxp.com>
+S:	Maintained
+F:	board/warp7/
+F:	include/configs/warp7.h
+F:	configs/warp7_defconfig
diff --git a/board/warp7/Makefile b/board/warp7/Makefile
new file mode 100644
index 0000000..f39d1d8
--- /dev/null
+++ b/board/warp7/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 NXP Semiconductors
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := warp7.o
diff --git a/board/warp7/imximage.cfg b/board/warp7/imximage.cfg
new file mode 100644
index 0000000..e7b6d30
--- /dev/null
+++ b/board/warp7/imximage.cfg
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION	2
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000015
+DATA 4 0x307a0204 0x00161616
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f0f0404
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x00000d6e
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+DATA 4 0x307900c0 0x0e4c7304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
new file mode 100644
index 0000000..8c5bf9a
--- /dev/null
+++ b/board/warp7/warp7.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ * Author: Fabio Estevam <fabio.estevam@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/crm_regs.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
+			PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW |	\
+			PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+		/* Assume uSDHC3 emmc is always present */
+		return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: WARP7\n");
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_DEVICE;
+}
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
new file mode 100644
index 0000000..f37c9f5
--- /dev/null
+++ b/configs/warp7_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_TARGET_WARP7=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
new file mode 100644
index 0000000..0798671
--- /dev/null
+++ b/include/configs/warp7.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * Configuration settings for the i.MX7S Warp board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __WARP7_CONFIG_H
+#define __WARP7_CONFIG_H
+
+#define CONFIG_BOOTDELAY                1
+#include "mx7_common.h"
+
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=image raw 0 0x800000;"\
+		"u-boot raw 0 0x4000;"\
+		"bootimg part 0 1;"\
+		"rootfs part 0 2\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_DFU_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx7d-warp.dtb\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi"
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX7
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"FSL"
+
+/* USB Device Firmware Update support */
+#define CONFIG_CMD_DFU
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+#endif
-- 
cgit v0.10.2


From 51560f0b04fa147f135d160eb655c8ec9e41462c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 10 Feb 2016 11:41:25 +0100
Subject: arm: mx6: Add UART8 base address for i.MX6UL

Add the base address for the i.MX6UL so that this UART can be used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f3c26dc..53488be 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -162,6 +162,7 @@
 #endif
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
-- 
cgit v0.10.2


From a7f480d92df8a7e525a4b619b09f40f73222647f Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 10 Feb 2016 11:41:26 +0100
Subject: arm: mx6: Add CCV xPress board support

This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:

- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB

This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index dc0894a..31b1175 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -165,6 +165,13 @@ config TARGET_WANDBOARD
 config TARGET_WARP
 	bool "WaRP"
 
+config TARGET_XPRESS
+	bool "CCV xPress"
+	select MX6UL
+	select DM
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 endchoice
 
 config SYS_SOC
@@ -176,6 +183,7 @@ source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
+source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/embest/mx6boards/Kconfig"
diff --git a/board/ccv/xpress/Kconfig b/board/ccv/xpress/Kconfig
new file mode 100644
index 0000000..9157013
--- /dev/null
+++ b/board/ccv/xpress/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPRESS
+
+config SYS_BOARD
+	default "xpress"
+
+config SYS_VENDOR
+	default "ccv"
+
+config SYS_CONFIG_NAME
+	default "xpress"
+
+endif
diff --git a/board/ccv/xpress/MAINTAINERS b/board/ccv/xpress/MAINTAINERS
new file mode 100644
index 0000000..e242bfb
--- /dev/null
+++ b/board/ccv/xpress/MAINTAINERS
@@ -0,0 +1,7 @@
+CCV XPRESS BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/ccv/xpress/
+F:	include/configs/xpress.h
+F:	configs/xpress_defconfig
+F:	configs/xpress_spl_defconfig
diff --git a/board/ccv/xpress/Makefile b/board/ccv/xpress/Makefile
new file mode 100644
index 0000000..0d444b6
--- /dev/null
+++ b/board/ccv/xpress/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := xpress.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
new file mode 100644
index 0000000..92167c9
--- /dev/null
+++ b/board/ccv/xpress/imximage.cfg
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* ddr io type */
+DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+/* clock */
+DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+/* control and address */
+DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
+				configured using Group Control Register:
+				IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+/* data strobes */
+DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+/* data */
+DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer:  IM
+ * Device Part Number:  IME1G16D3EEBG-15EI
+ * Clock Freq.:   400MHz
+ * Density per CS in Gb: 1
+ * Chip Selects used: 1
+ * Number of Banks: 8
+ * Row address:     13
+ * Column address:  10
+ * Data bus width 16
+ */
+DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
+				during MMDC set up */
+
+/*
+ * Calibration setup
+ */
+DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
+				periodic HW ZQ calibration. */
+
+/*
+ * For target board, may need to run write leveling calibration to fine tune
+ * these settings.
+ */
+DATA 4 0x021b080c 0x00000000
+
+/* Read DQS Gating calibration */
+DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
+
+/* Read calibration */
+DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
+
+/* Write calibration */
+DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
+
+/*
+ * read data bit delay: (3 is the reccommended default value, although out of
+ * reset value is 0)
+ */
+DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
+DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
+DATA 4 0x021b082c 0xF3333333
+DATA 4 0x021b0830 0xF3333333
+
+DATA 4 0x021b08c0 0x00921012
+
+/* Clock Fine Tuning */
+DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
+
+/* Complete calibration by forced measurement: */
+DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
+/*
+ * Calibration setup end
+ */
+
+/* MMDC init: */
+DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
+DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
+DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
+DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
+DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
+
+/*
+ * MDMISC: RALAT kept to the high level of 5.
+ * MDMISC: consider reducing RALAT if your 528MHz board design allow that.
+ * Lower RALAT benefits:
+ * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
+ *    to 3
+ * b. Small performence improvment
+ */
+DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
+
+DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
+				during MMDC set up */
+
+DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
+DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
+DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
+DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
+
+/* Mode register writes */
+DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
+DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
+DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
+DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
+DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
+				device on CS0 */
+
+DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
+DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
+DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
+DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
+				enter automatically to self-refresh while the
+				number of idle cycle reached. */
+DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
+				the configuration bit as initialization is
+				complete) */
diff --git a/board/ccv/xpress/spl.c b/board/ccv/xpress/spl.c
new file mode 100644
index 0000000..d15b842
--- /dev/null
+++ b/board/ccv/xpress/spl.c
@@ -0,0 +1,116 @@
+/*
+ * SPL specific code for CCV xPress
+ *
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/crm_regs.h>
+
+/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x4164015C,
+	.p0_mprddlctl = 0x40404446,
+	.p0_mpwrdlctl = 0x40405A52,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* Setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* Setup iomux and i2c */
+	board_early_init_f();
+
+	/* Setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c
new file mode 100644
index 0000000..6fc76cd
--- /dev/null
+++ b/board/ccv/xpress/xpress.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                  \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
+	PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+static struct i2c_pads_info i2c_pad_info4 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
+		.gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
+		.gp = IMX_GPIO_NR(1, 20),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
+		.gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
+		.gp = IMX_GPIO_NR(1, 21),
+	},
+};
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart8_pads[] = {
+	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+	imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
+}
+
+/* eMMC on USDHC2 */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*
+	 * RST_B
+	 */
+	MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC2_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(1, 9)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eMMC is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OTG1 */
+	MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* ENET1 reset */
+	MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* ENET1 interrupt */
+	MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	/* Reset LAN8742 PHY */
+	ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
+	if (!ret)
+		gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+	mdelay(10);
+	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+	mdelay(10);
+
+	return cpu_eth_init(bis);
+}
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+
+	setup_fec(CONFIG_FEC_ENET_DEV);
+
+	setup_usb();
+
+	return 0;
+}
+
+static const struct boot_mode board_boot_modes[] = {
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
+	{ NULL, 0 },
+};
+
+int board_late_init(void)
+{
+	add_board_boot_modes(board_boot_modes);
+	setenv("board_name", "xpress");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: CCV-EVA xPress\n");
+
+	return 0;
+}
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
new file mode 100644
index 0000000..033d32b
--- /dev/null
+++ b/configs/xpress_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_XPRESS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
new file mode 100644
index 0000000..c2b1075
--- /dev/null
+++ b/configs/xpress_spl_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_XPRESS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
new file mode 100644
index 0000000..9bc536b
--- /dev/null
+++ b/include/configs/xpress.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the CCV xPress board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __XPRESS_CONFIG_H
+#define __XPRESS_CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+/* SPL options */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 << 20)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Miscellaneous configurable options */
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(128 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Environment is in stored in the eMMC boot partition */
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		1	/* boot parition */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC2 */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_CACHE
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_ENET_DEV		0
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_UBOOT_SECTOR_START	0x2
+#define CONFIG_UBOOT_SECTOR_COUNT	0x3fe
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"uboot=ccv/u-boot.imx\0"					\
+	"uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0"	\
+	"uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0"		\
+	"update_uboot=if tftp ${uboot}; then "				\
+		"if itest ${filesize} > 0; then "			\
+			"mmc dev 0 1;"					\
+			"setexpr blkc ${filesize} / 0x200;"		\
+			"setexpr blkc ${blkc} + 1;"			\
+			"if itest ${blkc} <= ${uboot_size}; then "	\
+				"mmc write ${loadaddr} ${uboot_start} "	\
+					"${blkc};"			\
+			"fi;"						\
+		"fi; fi;"						\
+		"setenv filesize; setenv blkc\0"			\
+	"update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0"
+
+#endif /* __XPRESS_CONFIG_H */
-- 
cgit v0.10.2


From 9131c18cfa23c1eae8d77b6fcfa2f5e16698d949 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Thu, 3 Mar 2016 15:56:01 +0800
Subject: imx: mx6sx: move MX6SX to Kconfig entry

If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 31b1175..1bcd399 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -104,12 +104,14 @@ config TARGET_MX6SLEVK
 
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
+	select MX6SX
 	select SUPPORT_SPL
 	select DM
 	select DM_THERMAL
 
 config TARGET_MX6SXSABREAUTO
         bool "mx6sxsabreauto"
+	select MX6SX
         select DM
         select DM_THERMAL
 
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index d9e35df..631a998 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABREAUTO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index f4e88f2..2ea5c89 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 2713a4b..548adf6 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-- 
cgit v0.10.2


From 7abeec2234a81ba7880be6f0a6952dec3411bbe7 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Thu, 3 Mar 2016 15:56:02 +0800
Subject: imx: mx7d: move MX7D to Kconfig entry

If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
 will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX7D" to boards using i.MX7 Dual.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index 8e1ddcd..ecfa4a2 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -15,6 +15,7 @@ choice
 
 config TARGET_MX7DSABRESD
 	bool "mx7dsabresd"
+	select MX7D
 	select DM
 	select DM_THERMAL
 
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 40b0e7e..f43f2c1 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -3,7 +3,7 @@ CONFIG_ARCH_MX7=y
 CONFIG_TARGET_MX7DSABRESD=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From a473122c48d14560a4f7d8983e965de7b6e30d8f Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 24 Mar 2016 00:57:05 +0100
Subject: arm: mxs: Update MX28EVK config

Enable FIT image support, EXT4 support and generic FS support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index d0e413d..bb900ff 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index a52c8c9..4d86c13 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -23,7 +23,10 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
-- 
cgit v0.10.2


From 30ba8eb0d3c1fd5a071f14d82258d9f6100cfa8a Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Fri, 25 Mar 2016 11:37:04 -0300
Subject: mx6sabresd: Remove unneeded enable_lvds() function

enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set
previously inside setup_display().

We can safely remove enable_lvds() then.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 727334a..2319354 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -365,22 +365,12 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 	imx_enable_hdmi_phy();
 }
 
-static void enable_lvds(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)
-				IOMUXC_BASE_ADDR;
-	u32 reg = readl(&iomux->gpr[2]);
-	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
-	writel(reg, &iomux->gpr[2]);
-}
-
 struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB666,
 	.detect	= NULL,
-	.enable	= enable_lvds,
+	.enable	= NULL,
 	.mode	= {
 		.name           = "Hannstar-XGA",
 		.refresh        = 60,
-- 
cgit v0.10.2


From 01f512bc1196507eee3e6b4e7b5af551a8006fd3 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 26 Mar 2016 13:30:48 -0300
Subject: warp7: Pass the UART base definition

Since commit 5d69269deed0 ("mx7dsabresd: Define serial port locally")
we need to specify the UART base address in each board config
file, so do this to avoid a build error.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 0798671..5ea5512 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -14,6 +14,8 @@
 
 #define PHYS_SDRAM_SIZE			SZ_512M
 
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* MMC Config*/
-- 
cgit v0.10.2


From 6baa261615d3e3e05e2967120b6c329634791530 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 26 Mar 2016 13:30:49 -0300
Subject: mx7_common: Define CONFIG_SYS_MALLOC_LEN in the board file

Having CONFIG_SYS_MALLOC_LEN in mx7_common.h is not a good idea,
because the malloc() pool size is board dependent.

For example: if a certain board has support for splashscreen or DFU,
it may be necessary to adjust CONFIG_SYS_MALLOC_LEN to a larger value.

So define CONFIG_SYS_MALLOC_LEN in each board config file.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 5034464..9bd6114 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -28,9 +28,6 @@
 /* Enable iomux-lpsr support */
 #define CONFIG_IOMUX_LPSR
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN           (32 * SZ_1M)
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 988d363..25ed29d 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -16,6 +16,9 @@
 
 #define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
 
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 5ea5512..d1404b2 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -16,6 +16,10 @@
 
 #define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
 
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* MMC Config*/
-- 
cgit v0.10.2


From 2249b5a55a2c1dcf16884200eba28322116814a1 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 1 Apr 2016 17:54:50 -0400
Subject: mx6qarm2: imximage_mx6dl.cfg update to fix tINIT3 violation

Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured.  The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2.

Cc: Jason Liu <jason.hui.liu@nxp.com>
Cc: Ye Li <ye.li@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
index ae8dcc6..1f5a0a5 100644
--- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg
+++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
@@ -234,7 +234,7 @@ DATA 4 0x021b0018 0x0000174C
 /* MMDC0_MDRWD;*/
 DATA 4 0x021b002c 0x0f9f26d2
 /* MMDC0_MDOR */
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 /* MMDC0_MDCFG3LP */
 DATA 4 0x021b0038 0x00190778
 /* MMDC0_MDOTC */
@@ -263,7 +263,7 @@ DATA 4 0x021b4018 0x0000174C
 /* MMDC1_MDRWD;*/
 DATA 4 0x021b402c 0x0f9f26d2
 /* MMDC1_MDOR */
-DATA 4 0x021b4030 0x0000020e
+DATA 4 0x021b4030 0x009f0e10
 /* MMDC1_MDCFG3LP */
 DATA 4 0x021b4038 0x00190778
 /* MMDC1_MDOTC */
-- 
cgit v0.10.2


From 59c9e9b408014025cfa158a98aeafbcf33aa2d3d Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 1 Apr 2016 17:54:51 -0400
Subject: mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured.  The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2.  There was also a tIH-CA violation and this was
resolved by writing the default value in rather than what the script
here uses.

Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
index 16ea597..c77bbde 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b085c 0x1b4700c7
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
@@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82
 DATA 4 0x021b0014 0x00000093
 DATA 4 0x021b0018 0x00001688
 DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f
-- 
cgit v0.10.2


From 9fc56631a4f784ecaf860ae822d48580cd4317ed Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 11 Feb 2016 11:37:38 +0100
Subject: spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU

Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h
index 526fea6..78869a2 100644
--- a/arch/arm/include/asm/arch-mvebu/spi.h
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
@@ -35,13 +35,15 @@ struct kwspi_registers {
 #define SCK_MPP10	(1 << 1)
 #define MISO_MPP11	(1 << 2)
 
+/* Control Register */
+#define KWSPI_CSN_ACT		(1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT		2	/* chip select shift */
+#define KWSPI_CS_MASK		0x7	/* chip select mask */
+
+/* Configuration Register */
 #define KWSPI_CLKPRESCL_MASK	0x1f
 #define KWSPI_CLKPRESCL_MIN	0x12
-#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
 #define KWSPI_XFERLEN_1BYTE	0
 #define KWSPI_XFERLEN_2BYTE	(1 << 5)
 #define KWSPI_XFERLEN_MASK	(1 << 5)
@@ -50,6 +52,11 @@ struct kwspi_registers {
 #define KWSPI_ADRLEN_3BYTE	(2 << 8)
 #define KWSPI_ADRLEN_4BYTE	(3 << 8)
 #define KWSPI_ADRLEN_MASK	(3 << 8)
+
+#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
+
 #define KWSPI_TIMEOUT		10000
 
 #endif /* __KW_SPI_H__ */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 80cdbd0..6851ba9 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -283,6 +283,19 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
 }
 
+static int mvebu_spi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+
+	/* Configure the chip-select in the CTRL register */
+	clrsetbits_le32(&plat->spireg->ctrl,
+			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
+			spi_chip_select(dev) << KWSPI_CS_SHIFT);
+
+	return 0;
+}
+
 static int mvebu_spi_probe(struct udevice *bus)
 {
 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
@@ -305,6 +318,7 @@ static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
 }
 
 static const struct dm_spi_ops mvebu_spi_ops = {
+	.claim_bus	= mvebu_spi_claim_bus,
 	.xfer		= mvebu_spi_xfer,
 	.set_speed	= mvebu_spi_set_speed,
 	.set_mode	= mvebu_spi_set_mode,
-- 
cgit v0.10.2


From 46a16bd895144617575c788d9c2554aeef76ac44 Mon Sep 17 00:00:00 2001
From: Chris Packham <judge.packham@gmail.com>
Date: Tue, 2 Feb 2016 12:35:09 +1300
Subject: kirkwood_nand: claim MPP pins on the fly

Claim the MPP pins for the NAND flash controller only when it's actually
being used. This allows the pins to be shared with the SPI interface
which already supports an equivalent on-access MPP reconfiguration.

Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index 4fc34d6..d734113 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
 #include <nand.h>
 
 /* NAND Flash Soc registers */
@@ -22,6 +23,8 @@ struct kwnandf_registers {
 static struct kwnandf_registers *nf_reg =
 	(struct kwnandf_registers *)KW_NANDF_BASE;
 
+static u32 nand_mpp_backup[9] = { 0 };
+
 /*
  * hardware specific access to control-lines/bits
  */
@@ -49,6 +52,22 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 void kw_nand_select_chip(struct mtd_info *mtd, int chip)
 {
 	u32 data;
+	static const u32 nand_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		0
+	};
+
+	if (chip >= 0)
+		kirkwood_mpp_conf(nand_config, nand_mpp_backup);
+	else
+		kirkwood_mpp_conf(nand_mpp_backup, NULL);
 
 	data = readl(&nf_reg->ctrl);
 	data |= NAND_ACTCEBOOT_BIT;
-- 
cgit v0.10.2


From 4c1ceb6954d3e2defabe5633567ad1335f2ac730 Mon Sep 17 00:00:00 2001
From: Codrin Ciubotariu <codrin.ciubotariu@nxp.com>
Date: Mon, 14 Mar 2016 13:46:51 +0200
Subject: powerpc: t1040qds: Use generic ethsw commands

The commands for the VSC9953 l2 switch from T1040 became generic in
patch https://patchwork.ozlabs.org/patch/499748/ and the define
was renamed.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index aa0f802..f52889d 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -677,7 +677,7 @@ unsigned long get_board_ddr_clk(void);
 
 /* Enable VSC9953 L2 Switch driver */
 #define CONFIG_VSC9953
-#define CONFIG_VSC9953_CMD
+#define CONFIG_CMD_ETHSW
 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x14
 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x18
 
-- 
cgit v0.10.2


From b39d1213e30717c435c8ed43411d573d435557cb Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Wed, 6 Apr 2016 13:22:10 -0700
Subject: powerpc: Replace CONFIG_SYS_INIT_RAM_END with
 CONFIG_SYS_INIT_RAM_SIZE

CONFIG_SYS_INIT_RAM_SIZE may be used out of the board header file.
Some boards use CONFIG_SYS_INIT_RAM_END for the same purpose. To
unify the macros, use CONFIG_SYS_INIT_RAM_SIZE for all.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mario Six <mario.six@gdsys.cc>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>

diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 9c32a01..e870ffe 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -215,9 +215,9 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END		0x00004000/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* End of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
 						- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 9f7ceb8..108e924 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -396,9 +396,9 @@ combinations. this should be removed later
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END		0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
 						- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 4cbc9ad..a7a5e8e 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -329,9 +329,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
-#define CONFIG_SYS_INIT_RAM_END		0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
 						- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 81af871..249e11b 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -555,9 +555,9 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END		0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
 						- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index cf931a6..31348da 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -141,9 +141,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index 750d8ff..57421c6 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -289,9 +289,9 @@
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 9f9bcb8..bbeed76 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -238,10 +238,10 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
 
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/io.h b/include/configs/io.h
index 1213fe2..f05eb0a 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -196,10 +196,10 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
 
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 8bc89a0..f75ca76 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -249,10 +249,10 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
 
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 73a44a7..4ffab8a 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -253,13 +253,13 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
 /* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-- 
cgit v0.10.2


From 50689461205e0125759eb1a43787383a3fa09b48 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Tue, 5 Apr 2016 15:05:37 +0200
Subject: powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx

To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 235a635..aa519b0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -82,7 +82,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -90,17 +89,13 @@ void cpu_init_early_f(void *fdt)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
+	int i;
 #endif
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
+	/* gd area was zeroed during startup */
 
 #ifdef CONFIG_QEMU_E500
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d867e2a..82a151a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1152,6 +1152,36 @@ _start_cont:
 	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
 	lis	r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
 	ori	r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+	/* Leave 16+ byte for back chain termination and NULL return address */
+	subi	r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+#endif
+
+	/* End of RAM */
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+	li	r0,0
+
+1: 	subi 	r4,r4,4
+	stw 	r0,0(r4)
+	cmplw 	r4,r3
+	bne	1b
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	lis	r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	addi	r3,r3,16	/* Pre-relocation malloc area */
+	stw	r3,GD_MALLOC_BASE(r4)
+	subi	r3,r3,16
+#endif
 	li	r0,0
 	stw	r0,0(r3)	/* Terminate Back Chain */
 	stw	r0,+4(r3)	/* NULL return address. */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index ba166eb..379c493 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -263,12 +263,14 @@
 	b	transfer_to_handler
 
 #define STD_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(SRR0, SRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
 	EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY)	\
 
 #define CRIT_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
@@ -276,6 +278,7 @@ label:								\
 	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
 
 #define MCK_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
 label:								\
 	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
 	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
-- 
cgit v0.10.2


From f968467785b8dc04e86b1249b5109cc410ae30c5 Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Mon, 21 Mar 2016 13:05:40 +0530
Subject: arm: add missing writes[bwql], reads[bwql].

ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 75773bd..9d185a6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -284,6 +284,13 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define insw_p(port,to,len)		insw(port,to,len)
 #define insl_p(port,to,len)		insl(port,to,len)
 
+#define writesl(a, d, s)	__raw_writesl((unsigned long)a, d, s)
+#define readsl(a, d, s)		__raw_readsl((unsigned long)a, d, s)
+#define writesw(a, d, s)	__raw_writesw((unsigned long)a, d, s)
+#define readsw(a, d, s)		__raw_readsw((unsigned long)a, d, s)
+#define writesb(a, d, s)	__raw_writesb((unsigned long)a, d, s)
+#define readsb(a, d, s)		__raw_readsb((unsigned long)a, d, s)
+
 /*
  * ioremap and friends.
  *
-- 
cgit v0.10.2


From 6d9481047efcf2928ad9ff5bd883345b70cd0ca6 Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Mon, 21 Mar 2016 13:05:41 +0530
Subject: drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.

Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from driver to fix re-definition error

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9392742..d529467 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -19,14 +19,6 @@
 
 #include "pxa3xx_nand.h"
 
-/* Some U-Boot compatibility macros */
-#define writesl(a, d, s)	__raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s)		__raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s)	__raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s)		__raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s)	__raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s)		__raw_readsb((unsigned long)a, d, s)
-
 #define TIMEOUT_DRAIN_FIFO	5	/* in ms */
 #define	CHIP_DELAY_TIMEOUT	200
 #define NAND_STOP_DELAY		40
diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h
index 1fc9391..9244977 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -13,13 +13,6 @@
 		printf(fmt, ##args);		\
 	ret_warn; })
 
-#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s)
-#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s)
-#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s)
-#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s)
-#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
-#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
-
 #define device_init_wakeup(dev, a) do {} while (0)
 
 #define platform_data device_data
-- 
cgit v0.10.2


From 03b8e04632cac41e4000daed70d6987d118bf3d7 Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Mon, 21 Mar 2016 13:05:42 +0530
Subject: drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG
 controller.

This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.

Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>

diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6a6cb93..4e8a543 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -15,6 +15,13 @@ config USB_MUSB_GADGET
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
 
+config USB_MUSB_PIC32
+	bool "Enable Microchip PIC32 DRC USB controller"
+	depends on DM_USB && MACH_PIC32
+	help
+	  Say y to enable PIC32 USB DRC controller support
+	  if it is available on your Microchip PIC32 platform.
+
 config USB_MUSB_SUNXI
 	bool "Enable sunxi OTG / DRC USB controller"
 	depends on ARCH_SUNXI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 072d516..df1c3c8 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o
 obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
 obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
 obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index a6d6af6..dd0443c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -259,7 +259,7 @@ void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
 	}
 }
 
-#if !defined(CONFIG_USB_MUSB_AM35X)
+#if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
 /*
  * Unload an endpoint's FIFO
  */
diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c
new file mode 100644
index 0000000..c888c64
--- /dev/null
+++ b/drivers/usb/musb-new/pic32.c
@@ -0,0 +1,288 @@
+/*
+ * Microchip PIC32 MUSB "glue layer"
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ *  Cristian Birsan <cristian.birsan@microchip.com>
+ *  Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ * Based on the dsps "glue layer" code.
+ */
+
+#include <common.h>
+#include <linux/usb/musb.h>
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PIC32_TX_EP_MASK	0x0f		/* EP0 + 7 Tx EPs */
+#define PIC32_RX_EP_MASK	0x0e		/* 7 Rx EPs */
+
+#define MUSB_SOFTRST		0x7f
+#define  MUSB_SOFTRST_NRST	BIT(0)
+#define  MUSB_SOFTRST_NRSTX	BIT(1)
+
+#define USBCRCON		0
+#define  USBCRCON_USBWKUPEN	BIT(0)  /* Enable Wakeup Interrupt */
+#define  USBCRCON_USBRIE	BIT(1)  /* Enable Remote resume Interrupt */
+#define  USBCRCON_USBIE		BIT(2)  /* Enable USB General interrupt */
+#define  USBCRCON_SENDMONEN	BIT(3)  /* Enable Session End VBUS monitoring */
+#define  USBCRCON_BSVALMONEN	BIT(4)  /* Enable B-Device VBUS monitoring */
+#define  USBCRCON_ASVALMONEN	BIT(5)  /* Enable A-Device VBUS monitoring */
+#define  USBCRCON_VBUSMONEN	BIT(6)  /* Enable VBUS monitoring */
+#define  USBCRCON_PHYIDEN	BIT(7)  /* PHY ID monitoring enable */
+#define  USBCRCON_USBIDVAL	BIT(8)  /* USB ID value */
+#define  USBCRCON_USBIDOVEN	BIT(9)  /* USB ID override enable */
+#define  USBCRCON_USBWK		BIT(24) /* USB Wakeup Status */
+#define  USBCRCON_USBRF		BIT(25) /* USB Resume Status */
+#define  USBCRCON_USBIF		BIT(26) /* USB General Interrupt Status */
+
+/* PIC32 controller data */
+struct pic32_musb_data {
+	struct musb_host_data mdata;
+	struct device dev;
+	void __iomem *musb_glue;
+};
+
+#define to_pic32_musb_data(d)	\
+	container_of(d, struct pic32_musb_data, dev)
+
+static void pic32_musb_disable(struct musb *musb)
+{
+	/* no way to shut the controller */
+}
+
+static int pic32_musb_enable(struct musb *musb)
+{
+	/* soft reset by NRSTx */
+	musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+	/* set mode */
+	musb_platform_set_mode(musb, musb->board_mode);
+
+	return 0;
+}
+
+static irqreturn_t pic32_interrupt(int irq, void *hci)
+{
+	struct musb  *musb = hci;
+	irqreturn_t ret = IRQ_NONE;
+	u32 epintr, usbintr;
+
+	/* ack usb core interrupts */
+	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+	if (musb->int_usb)
+		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+
+	/* ack endpoint interrupts */
+	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
+	if (musb->int_rx)
+		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
+
+	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
+	if (musb->int_tx)
+		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
+
+	/* drop spurious RX and TX if device is disconnected */
+	if (musb->int_usb & MUSB_INTR_DISCONNECT) {
+		musb->int_tx = 0;
+		musb->int_rx = 0;
+	}
+
+	if (musb->int_tx || musb->int_rx || musb->int_usb)
+		ret = musb_interrupt(musb);
+
+	return ret;
+}
+
+static int pic32_musb_set_mode(struct musb *musb, u8 mode)
+{
+	struct device *dev = musb->controller;
+	struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
+
+	switch (mode) {
+	case MUSB_HOST:
+		clrsetbits_le32(pdata->musb_glue + USBCRCON,
+				USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
+		break;
+	case MUSB_PERIPHERAL:
+		setbits_le32(pdata->musb_glue + USBCRCON,
+			     USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
+		break;
+	case MUSB_OTG:
+		dev_err(dev, "support for OTG is unimplemented\n");
+		break;
+	default:
+		dev_err(dev, "unsupported mode %d\n", mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int pic32_musb_init(struct musb *musb)
+{
+	struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
+	u32 ctrl, hwvers;
+	u8 power;
+
+	/* Returns zero if not clocked */
+	hwvers = musb_read_hwvers(musb->mregs);
+	if (!hwvers)
+		return -ENODEV;
+
+	/* Reset the musb */
+	power = musb_readb(musb->mregs, MUSB_POWER);
+	power = power | MUSB_POWER_RESET;
+	musb_writeb(musb->mregs, MUSB_POWER, power);
+	mdelay(100);
+
+	/* Start the on-chip PHY and its PLL. */
+	power = power & ~MUSB_POWER_RESET;
+	musb_writeb(musb->mregs, MUSB_POWER, power);
+
+	musb->isr = pic32_interrupt;
+
+	ctrl =  USBCRCON_USBIF | USBCRCON_USBRF |
+		USBCRCON_USBWK | USBCRCON_USBIDOVEN |
+		USBCRCON_PHYIDEN | USBCRCON_USBIE |
+		USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
+		USBCRCON_VBUSMONEN;
+	writel(ctrl, pdata->musb_glue + USBCRCON);
+
+	return 0;
+}
+
+/* PIC32 supports only 32bit read operation */
+void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+{
+	void __iomem *fifo = hw_ep->fifo;
+	u32 val, rem = len % 4;
+
+	/* USB stack ensures dst is always 32bit aligned. */
+	readsl(fifo, dst, len / 4);
+	if (rem) {
+		dst += len & ~0x03;
+		val = musb_readl(fifo, 0);
+		memcpy(dst, &val, rem);
+	}
+}
+
+const struct musb_platform_ops pic32_musb_ops = {
+	.init		= pic32_musb_init,
+	.set_mode	= pic32_musb_set_mode,
+	.disable	= pic32_musb_disable,
+	.enable		= pic32_musb_enable,
+};
+
+/* PIC32 default FIFO config - fits in 8KB */
+static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
+	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
+	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
+	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
+	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
+	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
+	{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
+	{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
+	{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
+};
+
+static struct musb_hdrc_config pic32_musb_config = {
+	.fifo_cfg	= pic32_musb_fifo_config,
+	.fifo_cfg_size	= ARRAY_SIZE(pic32_musb_fifo_config),
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 8,
+	.ram_bits       = 11,
+};
+
+/* PIC32 has one MUSB controller which can be host or gadget */
+static struct musb_hdrc_platform_data pic32_musb_plat = {
+	.mode           = MUSB_HOST,
+	.config         = &pic32_musb_config,
+	.power          = 250,		/* 500mA */
+	.platform_ops	= &pic32_musb_ops,
+};
+
+static int musb_usb_probe(struct udevice *dev)
+{
+	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+	struct pic32_musb_data *pdata = dev_get_priv(dev);
+	struct musb_host_data *mdata = &pdata->mdata;
+	struct fdt_resource mc, glue;
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	void __iomem *mregs;
+	int ret;
+
+	priv->desc_before_addr = true;
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "mc", &mc);
+	if (ret < 0) {
+		printf("pic32-musb: resource \"mc\" not found\n");
+		return ret;
+	}
+
+	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+				     "control", &glue);
+	if (ret < 0) {
+		printf("pic32-musb: resource \"control\" not found\n");
+		return ret;
+	}
+
+	mregs = ioremap(mc.start, fdt_resource_size(&mc));
+	pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
+
+	/* init controller */
+#ifdef CONFIG_USB_MUSB_HOST
+	mdata->host = musb_init_controller(&pic32_musb_plat,
+					   &pdata->dev, mregs);
+	if (!mdata->host)
+		return -EIO;
+
+	ret = musb_lowlevel_init(mdata);
+#else
+	pic32_musb_plat.mode = MUSB_PERIPHERAL;
+	ret = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
+#endif
+	if (ret == 0)
+		printf("PIC32 MUSB OTG\n");
+
+	return ret;
+}
+
+static int musb_usb_remove(struct udevice *dev)
+{
+	struct pic32_musb_data *pdata = dev_get_priv(dev);
+
+	musb_stop(pdata->mdata.host);
+
+	return 0;
+}
+
+static const struct udevice_id pic32_musb_ids[] = {
+	{ .compatible = "microchip,pic32mzda-usb" },
+	{ }
+};
+
+U_BOOT_DRIVER(usb_musb) = {
+	.name		= "pic32-musb",
+	.id		= UCLASS_USB,
+	.of_match	= pic32_musb_ids,
+	.probe		= musb_usb_probe,
+	.remove		= musb_usb_remove,
+#ifdef CONFIG_USB_MUSB_HOST
+	.ops		= &musb_usb_ops,
+#endif
+	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
+	.priv_auto_alloc_size = sizeof(struct pic32_musb_data),
+};
-- 
cgit v0.10.2


From ac7eef716e6298feea81a927904b25efe1f492ac Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Mon, 21 Mar 2016 13:05:43 +0530
Subject: board: pic32mzda: enable USB-host, USB-storage support.

Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 7d180d9..8a554f9 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -171,4 +171,16 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 	};
+
+	usb: musb@1f8e3000 {
+		compatible = "microchip,pic32mzda-usb";
+		reg = <0x1f8e3000 0x1000>,
+		      <0x1f884000 0x1000>;
+		reg-names = "mc", "control";
+		interrupts = <132 IRQ_TYPE_EDGE_RISING>,
+			     <133 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clock PB5CLK>;
+		clock-names = "usb_clk";
+		status = "disabled";
+	};
 };
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index e5ce0bd..0a7847e 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -52,4 +52,8 @@
 	ethernet_phy: lan8740_phy@0 {
 		reg = <0>;
 	};
+};
+
+&usb {
+	status = "okay";
 };
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 4017983..eba6cd5 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -14,6 +14,7 @@ CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
@@ -30,5 +31,10 @@ CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_PIC32=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 3ea1194..78faaec 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -105,6 +105,12 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC
 
+/*--------------------------------------------------
+ * USB Configuration
+ */
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
 /*-----------------------------------------------------------------------
  * File System Configuration
  */
@@ -153,6 +159,7 @@
 
 #define BOOT_TARGET_DEVICES(func)	\
 	func(MMC, mmc, 0)		\
+	func(USB, usb, 0)		\
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>
-- 
cgit v0.10.2


From cfb3f1cd0e022711d69ff040884357b8410865ef Mon Sep 17 00:00:00 2001
From: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Date: Sun, 3 Apr 2016 13:38:26 +0200
Subject: usb: ehci-hcd: Fix crash when no ops are provided to ehci_register()

This commit fixes crash on BananaPi (and possibly others)
casued by 3f9f8a5b83f8aec40c9f4ee496046a695e333c45.

Crash reason:
When no ops were passed to ehci_register(), USB host driver caused
NULL pointer dereference.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 598f444..fa5d584 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1615,8 +1615,8 @@ int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
 	if (ret)
 		goto err;
 
-	if (ops->init_after_reset) {
-		ret = ops->init_after_reset(ctrl);
+	if (ctrl->ops.init_after_reset) {
+		ret = ctrl->ops.init_after_reset(ctrl);
 		if (ret)
 			goto err;
 	}
-- 
cgit v0.10.2


From 9a80e714350a959caadfd6e2405cd1f7e8ea86d3 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 3 Apr 2016 09:18:53 +0200
Subject: usb: kbd: Do not deregister usbkbd twice when using dm

The dm usb_kbd_remove function() will deregister the usb keyboard for
us on a "usb reset" / "usb stop" so there is no need to manually call
usb_kbd_deregister() in the dm case.

This commit removes usb_kbd_deregister() in the dm case fixing the
following "usb reset" errors:

usb_kbd_remove: warning, ret=-6
device_remove: Device 'usb_kbd' failed to remove, but children are gone

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/cmd/usb.c b/cmd/usb.c
index 9ed5dc6..97dd6f0 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -541,7 +541,7 @@ static int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 static int do_usb_stop_keyboard(int force)
 {
-#ifdef CONFIG_USB_KEYBOARD
+#if !defined CONFIG_DM_USB && defined CONFIG_USB_KEYBOARD
 	if (usb_kbd_deregister(force) != 0) {
 		printf("USB not stopped: usbkbd still using USB\n");
 		return 1;
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index d84865f..97f79f8 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -566,7 +566,6 @@ int drv_usb_kbd_init(void)
 	/* No USB Keyboard found */
 	return -1;
 }
-#endif
 
 /* Deregister the keyboard. */
 int usb_kbd_deregister(int force)
@@ -599,6 +598,8 @@ int usb_kbd_deregister(int force)
 #endif
 }
 
+#endif
+
 #ifdef CONFIG_DM_USB
 
 static int usb_kbd_probe(struct udevice *dev)
-- 
cgit v0.10.2


From 93eb8f39d27074846b04d8b889fd1b02d7489e8d Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Tue, 5 Apr 2016 14:41:19 +0530
Subject: drivers:usb:common:fsl-dt-fixup: Move device-tree fixup framework to
 common file

Move usb device-tree fixup framework from ehci-fsl.c to common place so
that it can be used by other drivers as well (xhci-fsl.c).

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/Makefile b/Makefile
index 25ef3c1..ea7fd00 100644
--- a/Makefile
+++ b/Makefile
@@ -648,6 +648,7 @@ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
+libs-y += drivers/usb/common/
 libs-y += drivers/usb/emul/
 libs-y += drivers/usb/eth/
 libs-y += drivers/usb/gadget/
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
new file mode 100644
index 0000000..a38ee4a
--- /dev/null
+++ b/drivers/usb/common/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
new file mode 100644
index 0000000..92adb46
--- /dev/null
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
+ *
+ * Author: Tor Krill tor@excito.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fsl_usb.h>
+#include <fdt_support.h>
+
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+				       const char *phy_type, int start_offset)
+{
+	const char *compat_dr = "fsl-usb2-dr";
+	const char *compat_mph = "fsl-usb2-mph";
+	const char *prop_mode = "dr_mode";
+	const char *prop_type = "phy_type";
+	const char *node_type = NULL;
+	int node_offset;
+	int err;
+
+	node_offset = fdt_node_offset_by_compatible(blob,
+						    start_offset, compat_mph);
+	if (node_offset < 0) {
+		node_offset = fdt_node_offset_by_compatible(blob,
+							    start_offset,
+							    compat_dr);
+		if (node_offset < 0) {
+			printf("WARNING: could not find compatible node: %s",
+			       fdt_strerror(node_offset));
+			return -1;
+		}
+		node_type = compat_dr;
+	} else {
+		node_type = compat_mph;
+	}
+
+	if (mode) {
+		err = fdt_setprop(blob, node_offset, prop_mode, mode,
+				  strlen(mode) + 1);
+		if (err < 0)
+			printf("WARNING: could not set %s for %s: %s.\n",
+			       prop_mode, node_type, fdt_strerror(err));
+	}
+
+	if (phy_type) {
+		err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+				  strlen(phy_type) + 1);
+		if (err < 0)
+			printf("WARNING: could not set %s for %s: %s.\n",
+			       prop_type, node_type, fdt_strerror(err));
+	}
+
+	return node_offset;
+}
+
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+					 int *node_offset)
+{
+	const char *compat_dr = "fsl-usb2-dr";
+	const char *compat_mph = "fsl-usb2-mph";
+	const char *node_type = NULL;
+
+	*node_offset = fdt_node_offset_by_compatible(blob, start_offset,
+						     compat_mph);
+	if (*node_offset < 0) {
+		*node_offset = fdt_node_offset_by_compatible(blob,
+							     start_offset,
+							     compat_dr);
+		if (*node_offset < 0) {
+			printf("ERROR: could not find compatible node: %s\n",
+			       fdt_strerror(*node_offset));
+		} else {
+			node_type = compat_dr;
+		}
+	} else {
+		node_type = compat_mph;
+	}
+
+	return node_type;
+}
+
+static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+				 int start_offset)
+{
+	int node_offset, err;
+	const char *node_type = NULL;
+
+	node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
+	if (!node_type)
+		return -1;
+
+	err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
+	if (err < 0) {
+		printf("ERROR: could not set %s for %s: %s.\n",
+		       prop_erratum, node_type, fdt_strerror(err));
+	}
+
+	return node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+	static const char * const modes[] = { "host", "peripheral", "otg" };
+	static const char * const phys[] = { "ulpi", "utmi", "utmi_dual" };
+	int usb_erratum_a006261_off = -1;
+	int usb_erratum_a007075_off = -1;
+	int usb_erratum_a007792_off = -1;
+	int usb_erratum_a005697_off = -1;
+	int usb_mode_off = -1;
+	int usb_phy_off = -1;
+	char str[5];
+	int i, j;
+
+	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+		const char *dr_mode_type = NULL;
+		const char *dr_phy_type = NULL;
+		int mode_idx = -1, phy_idx = -1;
+
+		snprintf(str, 5, "%s%d", "usb", i);
+		if (hwconfig(str)) {
+			for (j = 0; j < ARRAY_SIZE(modes); j++) {
+				if (hwconfig_subarg_cmp(str, "dr_mode",
+							modes[j])) {
+					mode_idx = j;
+					break;
+				}
+			}
+
+			for (j = 0; j < ARRAY_SIZE(phys); j++) {
+				if (hwconfig_subarg_cmp(str, "phy_type",
+							phys[j])) {
+					phy_idx = j;
+					break;
+				}
+			}
+
+			if (mode_idx < 0 && phy_idx < 0) {
+				printf("WARNING: invalid phy or mode\n");
+				return;
+			}
+
+			if (mode_idx > -1)
+				dr_mode_type = modes[mode_idx];
+
+			if (phy_idx > -1)
+				dr_phy_type = phys[phy_idx];
+		}
+
+		if (has_dual_phy())
+			dr_phy_type = phys[2];
+
+		usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+							   dr_mode_type, NULL,
+							   usb_mode_off);
+
+		if (usb_mode_off < 0)
+			return;
+
+		usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+							  NULL, dr_phy_type,
+							  usb_phy_off);
+
+		if (usb_phy_off < 0)
+			return;
+
+		if (has_erratum_a006261()) {
+			usb_erratum_a006261_off =  fdt_fixup_usb_erratum
+						   (blob,
+						    "fsl,usb-erratum-a006261",
+						    usb_erratum_a006261_off);
+			if (usb_erratum_a006261_off < 0)
+				return;
+		}
+
+		if (has_erratum_a007075()) {
+			usb_erratum_a007075_off =  fdt_fixup_usb_erratum
+						   (blob,
+						    "fsl,usb-erratum-a007075",
+						    usb_erratum_a007075_off);
+			if (usb_erratum_a007075_off < 0)
+				return;
+		}
+
+		if (has_erratum_a007792()) {
+			usb_erratum_a007792_off =  fdt_fixup_usb_erratum
+						   (blob,
+						    "fsl,usb-erratum-a007792",
+						    usb_erratum_a007792_off);
+			if (usb_erratum_a007792_off < 0)
+				return;
+		}
+		if (has_erratum_a005697()) {
+			usb_erratum_a005697_off =  fdt_fixup_usb_erratum
+						   (blob,
+						    "fsl,usb-erratum-a005697",
+						    usb_erratum_a005697_off);
+			if (usb_erratum_a005697_off < 0)
+				return;
+		}
+	}
+}
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 4bcea9d..a43d37d 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -173,198 +173,3 @@ static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
 	cmd |= TXFIFO_THRESH(txfifo_thresh);
 	ehci_writel(&ehci->txfilltuning, cmd);
 }
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
-				       const char *phy_type, int start_offset)
-{
-	const char *compat_dr = "fsl-usb2-dr";
-	const char *compat_mph = "fsl-usb2-mph";
-	const char *prop_mode = "dr_mode";
-	const char *prop_type = "phy_type";
-	const char *node_type = NULL;
-	int node_offset;
-	int err;
-
-	node_offset = fdt_node_offset_by_compatible(blob,
-						    start_offset, compat_mph);
-	if (node_offset < 0) {
-		node_offset = fdt_node_offset_by_compatible(blob,
-							    start_offset,
-							    compat_dr);
-		if (node_offset < 0) {
-			printf("WARNING: could not find compatible node: %s",
-			       fdt_strerror(node_offset));
-			return -1;
-		}
-		node_type = compat_dr;
-	} else {
-		node_type = compat_mph;
-	}
-
-	if (mode) {
-		err = fdt_setprop(blob, node_offset, prop_mode, mode,
-				  strlen(mode) + 1);
-		if (err < 0)
-			printf("WARNING: could not set %s for %s: %s.\n",
-			       prop_mode, node_type, fdt_strerror(err));
-	}
-
-	if (phy_type) {
-		err = fdt_setprop(blob, node_offset, prop_type, phy_type,
-				  strlen(phy_type) + 1);
-		if (err < 0)
-			printf("WARNING: could not set %s for %s: %s.\n",
-			       prop_type, node_type, fdt_strerror(err));
-	}
-
-	return node_offset;
-}
-
-static const char *fdt_usb_get_node_type(void *blob, int start_offset,
-					 int *node_offset)
-{
-	const char *compat_dr = "fsl-usb2-dr";
-	const char *compat_mph = "fsl-usb2-mph";
-	const char *node_type = NULL;
-
-	*node_offset = fdt_node_offset_by_compatible(blob, start_offset,
-						     compat_mph);
-	if (*node_offset < 0) {
-		*node_offset = fdt_node_offset_by_compatible(blob,
-							     start_offset,
-							     compat_dr);
-		if (*node_offset < 0) {
-			printf("ERROR: could not find compatible node: %s\n",
-			       fdt_strerror(*node_offset));
-		} else {
-			node_type = compat_dr;
-		}
-	} else {
-		node_type = compat_mph;
-	}
-
-	return node_type;
-}
-
-static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
-				 int start_offset)
-{
-	int node_offset, err;
-	const char *node_type = NULL;
-
-	node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
-	if (!node_type)
-		return -1;
-
-	err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
-	if (err < 0) {
-		printf("ERROR: could not set %s for %s: %s.\n",
-		       prop_erratum, node_type, fdt_strerror(err));
-	}
-
-	return node_offset;
-}
-
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
-	static const char * const modes[] = { "host", "peripheral", "otg" };
-	static const char * const phys[] = { "ulpi", "utmi", "utmi_dual" };
-	int usb_erratum_a006261_off = -1;
-	int usb_erratum_a007075_off = -1;
-	int usb_erratum_a007792_off = -1;
-	int usb_erratum_a005697_off = -1;
-	int usb_mode_off = -1;
-	int usb_phy_off = -1;
-	char str[5];
-	int i, j;
-
-	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
-		const char *dr_mode_type = NULL;
-		const char *dr_phy_type = NULL;
-		int mode_idx = -1, phy_idx = -1;
-
-		snprintf(str, 5, "%s%d", "usb", i);
-		if (hwconfig(str)) {
-			for (j = 0; j < ARRAY_SIZE(modes); j++) {
-				if (hwconfig_subarg_cmp(str, "dr_mode",
-							modes[j])) {
-					mode_idx = j;
-					break;
-				}
-			}
-
-			for (j = 0; j < ARRAY_SIZE(phys); j++) {
-				if (hwconfig_subarg_cmp(str, "phy_type",
-							phys[j])) {
-					phy_idx = j;
-					break;
-				}
-			}
-
-			if (mode_idx < 0 && phy_idx < 0) {
-				printf("WARNING: invalid phy or mode\n");
-				return;
-			}
-
-			if (mode_idx > -1)
-				dr_mode_type = modes[mode_idx];
-
-			if (phy_idx > -1)
-				dr_phy_type = phys[phy_idx];
-		}
-
-		if (has_dual_phy())
-			dr_phy_type = phys[2];
-
-		usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
-							   dr_mode_type, NULL,
-							   usb_mode_off);
-
-		if (usb_mode_off < 0)
-			return;
-
-		usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
-							  NULL, dr_phy_type,
-							  usb_phy_off);
-
-		if (usb_phy_off < 0)
-			return;
-
-		if (has_erratum_a006261()) {
-			usb_erratum_a006261_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a006261",
-						    usb_erratum_a006261_off);
-			if (usb_erratum_a006261_off < 0)
-				return;
-		}
-
-		if (has_erratum_a007075()) {
-			usb_erratum_a007075_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a007075",
-						    usb_erratum_a007075_off);
-			if (usb_erratum_a007075_off < 0)
-				return;
-		}
-
-		if (has_erratum_a007792()) {
-			usb_erratum_a007792_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a007792",
-						    usb_erratum_a007792_off);
-			if (usb_erratum_a007792_off < 0)
-				return;
-		}
-		if (has_erratum_a005697()) {
-			usb_erratum_a005697_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a005697",
-						    usb_erratum_a005697_off);
-			if (usb_erratum_a005697_off < 0)
-				return;
-		}
-	}
-}
-#endif
-- 
cgit v0.10.2


From 469e72bc5d982de1117a801c6f61b16853da2f28 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Tue, 5 Apr 2016 14:41:20 +0530
Subject: drivers:usb:common:fsl-dt-fixup: Remove code duplication for
 fdt_usb_get_node_type

Call fdt_usb_get_node_type() from fdt_fixup_usb_mode_phy_type() to
avoid code duplication.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 92adb46..eb13f12 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -19,33 +19,45 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 #endif
 
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
-				       const char *phy_type, int start_offset)
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+					 int *node_offset)
 {
 	const char *compat_dr = "fsl-usb2-dr";
 	const char *compat_mph = "fsl-usb2-mph";
-	const char *prop_mode = "dr_mode";
-	const char *prop_type = "phy_type";
 	const char *node_type = NULL;
-	int node_offset;
-	int err;
 
-	node_offset = fdt_node_offset_by_compatible(blob,
-						    start_offset, compat_mph);
-	if (node_offset < 0) {
-		node_offset = fdt_node_offset_by_compatible(blob,
-							    start_offset,
-							    compat_dr);
-		if (node_offset < 0) {
-			printf("WARNING: could not find compatible node: %s",
-			       fdt_strerror(node_offset));
-			return -1;
+	*node_offset = fdt_node_offset_by_compatible(blob, start_offset,
+						     compat_mph);
+	if (*node_offset < 0) {
+		*node_offset = fdt_node_offset_by_compatible(blob,
+							     start_offset,
+							     compat_dr);
+		if (*node_offset < 0) {
+			printf("ERROR: could not find compatible node: %s\n",
+			       fdt_strerror(*node_offset));
+		} else {
+			node_type = compat_dr;
 		}
-		node_type = compat_dr;
 	} else {
 		node_type = compat_mph;
 	}
 
+	return node_type;
+}
+
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+				       const char *phy_type, int start_offset)
+{
+	const char *prop_mode = "dr_mode";
+	const char *prop_type = "phy_type";
+	const char *node_type = NULL;
+	int node_offset;
+	int err;
+
+	node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
+	if (!node_type)
+		return -1;
+
 	if (mode) {
 		err = fdt_setprop(blob, node_offset, prop_mode, mode,
 				  strlen(mode) + 1);
@@ -65,32 +77,6 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 	return node_offset;
 }
 
-static const char *fdt_usb_get_node_type(void *blob, int start_offset,
-					 int *node_offset)
-{
-	const char *compat_dr = "fsl-usb2-dr";
-	const char *compat_mph = "fsl-usb2-mph";
-	const char *node_type = NULL;
-
-	*node_offset = fdt_node_offset_by_compatible(blob, start_offset,
-						     compat_mph);
-	if (*node_offset < 0) {
-		*node_offset = fdt_node_offset_by_compatible(blob,
-							     start_offset,
-							     compat_dr);
-		if (*node_offset < 0) {
-			printf("ERROR: could not find compatible node: %s\n",
-			       fdt_strerror(*node_offset));
-		} else {
-			node_type = compat_dr;
-		}
-	} else {
-		node_type = compat_mph;
-	}
-
-	return node_type;
-}
-
 static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
 				 int start_offset)
 {
-- 
cgit v0.10.2


From b9f6786a885ef5da741176b0b3411434b57e5019 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Tue, 5 Apr 2016 14:41:21 +0530
Subject: drivers:usb:common:fsl-dt-fixup: Add device-tree fixup support for
 xhci controller

Enables usb device-tree fixup code to incorporate xhci controller

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>

diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index a38ee4a..2f3d43d 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
+obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index eb13f12..46488dc 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -19,27 +19,27 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 #endif
 
+static const char * const compat_usb_fsl[] = {
+	"fsl-usb2-mph",
+	"fsl-usb2-dr",
+	"snps,dwc3",
+	NULL
+};
+
 static const char *fdt_usb_get_node_type(void *blob, int start_offset,
 					 int *node_offset)
 {
-	const char *compat_dr = "fsl-usb2-dr";
-	const char *compat_mph = "fsl-usb2-mph";
 	const char *node_type = NULL;
-
-	*node_offset = fdt_node_offset_by_compatible(blob, start_offset,
-						     compat_mph);
-	if (*node_offset < 0) {
-		*node_offset = fdt_node_offset_by_compatible(blob,
-							     start_offset,
-							     compat_dr);
-		if (*node_offset < 0) {
-			printf("ERROR: could not find compatible node: %s\n",
-			       fdt_strerror(*node_offset));
-		} else {
-			node_type = compat_dr;
+	int i;
+
+	for (i = 0; compat_usb_fsl[i]; i++) {
+		*node_offset = fdt_node_offset_by_compatible
+					(blob, start_offset,
+					 compat_usb_fsl[i]);
+		if (*node_offset >= 0) {
+			node_type = compat_usb_fsl[i];
+			break;
 		}
-	} else {
-		node_type = compat_mph;
 	}
 
 	return node_type;
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 296add0..d34e959 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -113,11 +113,11 @@ void fdt_fixup_qe_firmware(void *fdt);
  */
 int fdt_fixup_display(void *blob, const char *path, const char *display);
 
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#if defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL)
 void fdt_fixup_dr_usb(void *blob, bd_t *bd);
 #else
 static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
+#endif /* defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) */
 
 #if defined(CONFIG_SYS_FSL_SEC_COMPAT)
 void fdt_fixup_crypto_node(void *blob, int sec_rev);
-- 
cgit v0.10.2


From 47435e5b18e3dd780a37e39a5f34e6d46e1e2126 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Tue, 5 Apr 2016 14:41:22 +0530
Subject: drivers:usb:common:fsl-dt-fixup: fix return value of
 fdt_usb_get_node_type

Changes the return type of fdt_usb_get_node_type from char* to int

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 46488dc..6f31932 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -26,23 +26,24 @@ static const char * const compat_usb_fsl[] = {
 	NULL
 };
 
-static const char *fdt_usb_get_node_type(void *blob, int start_offset,
-					 int *node_offset)
+static int fdt_usb_get_node_type(void *blob, int start_offset,
+				 int *node_offset, const char **node_type)
 {
-	const char *node_type = NULL;
 	int i;
+	int ret = -ENOENT;
 
 	for (i = 0; compat_usb_fsl[i]; i++) {
 		*node_offset = fdt_node_offset_by_compatible
 					(blob, start_offset,
 					 compat_usb_fsl[i]);
 		if (*node_offset >= 0) {
-			node_type = compat_usb_fsl[i];
+			*node_type = compat_usb_fsl[i];
+			ret = 0;
 			break;
 		}
 	}
 
-	return node_type;
+	return ret;
 }
 
 static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
@@ -54,9 +55,10 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 	int node_offset;
 	int err;
 
-	node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
-	if (!node_type)
-		return -1;
+	err = fdt_usb_get_node_type(blob, start_offset,
+				    &node_offset, &node_type);
+	if (err < 0)
+		return err;
 
 	if (mode) {
 		err = fdt_setprop(blob, node_offset, prop_mode, mode,
@@ -83,9 +85,10 @@ static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
 	int node_offset, err;
 	const char *node_type = NULL;
 
-	node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
-	if (!node_type)
-		return -1;
+	err = fdt_usb_get_node_type(blob, start_offset,
+				    &node_offset, &node_type);
+	if (err < 0)
+		return err;
 
 	err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
 	if (err < 0) {
-- 
cgit v0.10.2


From cf1254738537b24308699a4ea0081e52723933b0 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Mon, 4 Apr 2016 12:59:43 -0700
Subject: usb: bcm_udc_otg: enable clocks

Turn on the USB OTG clocks.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c
index 10b2e13..877f162 100644
--- a/drivers/usb/gadget/bcm_udc_otg_phy.c
+++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
@@ -8,12 +8,16 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
 
 #include "dwc2_udc_otg_priv.h"
 #include "bcm_udc_otg.h"
 
 void otg_phy_init(struct dwc2_udc *dev)
 {
+	/* turn on the USB OTG clocks */
+	clk_usb_otg_enable((void *)HSOTG_BASE_ADDR);
+
 	/* set Phy to driving mode */
 	wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
 		   HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
-- 
cgit v0.10.2


From 38b4a3e14397582549b3bb1b301fd9b5c7fc89d2 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 2 Apr 2016 20:46:09 +0200
Subject: musb: sunxi: Do not allocate musb struct multiple times

The probe function of the musb host driver can be called multiple
times. The code assumes that it can save the pointer to the allocated
musb struct in the driver model priv_auto_alloc data, but this data
gets free-ed on a probe failure or on removal, so we must save the
pointer elsewhere.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index be1d2ec..3081afc 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -201,6 +201,7 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
 
 /* musb_core does not call enable / disable in a balanced manner <sigh> */
 static bool enabled = false;
+static struct musb *sunxi_musb;
 
 static int sunxi_musb_enable(struct musb *musb)
 {
@@ -320,13 +321,15 @@ int musb_usb_probe(struct udevice *dev)
 
 	priv->desc_before_addr = true;
 
-	if (!host->host) {
-		host->host = musb_init_controller(&musb_plat, NULL,
+	if (!sunxi_musb) {
+		sunxi_musb = musb_init_controller(&musb_plat, NULL,
 						  (void *)SUNXI_USB0_BASE);
-		if (!host->host)
-			return -EIO;
 	}
 
+	host->host = sunxi_musb;
+	if (!host->host)
+		return -EIO;
+
 	ret = musb_lowlevel_init(host);
 	if (ret == 0)
 		printf("MUSB OTG\n");
-- 
cgit v0.10.2


From bf313230642ca6ce1e5cb67d49f6cc72a6d752ae Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 2 Apr 2016 20:46:10 +0200
Subject: musb: Properly call musb_stop() on probe failure

musb_lowlevelinit(): if no device is plugged in / detected call
musb_stop() to undo the preceding musb_start() call.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 233a0e4..6ce528c 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -237,8 +237,10 @@ int musb_lowlevel_init(struct musb_host_data *host)
 		if (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_HM)
 			break;
 	} while (get_timer(0) < timeout);
-	if (get_timer(0) >= timeout)
+	if (get_timer(0) >= timeout) {
+		musb_stop(host->host);
 		return -ENODEV;
+	}
 
 	_musb_reset_root_port(host, NULL);
 	host->host->is_active = 1;
-- 
cgit v0.10.2


From 192eab9357473e09218e0a4448b220d691d9d886 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 3 Apr 2016 00:04:39 +0200
Subject: dm: usb: Do not reprobe usb hosts on "usb tree" command

Some usb hosts may have failed to probe on "usb start", i.e. an otg
host without an otg-host cable plugged in.

"usb tree" would cause the probe method of these hosts to get called
again, something which should only happen on "usb reset".

This commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/cmd/usb.c b/cmd/usb.c
index 97dd6f0..f1a7deb 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -15,6 +15,7 @@
 #include <command.h>
 #include <console.h>
 #include <dm.h>
+#include <dm/uclass-internal.h>
 #include <memalign.h>
 #include <asm/byteorder.h>
 #include <asm/unaligned.h>
@@ -442,12 +443,15 @@ void usb_show_tree(void)
 #ifdef CONFIG_DM_USB
 	struct udevice *bus;
 
-	for (uclass_first_device(UCLASS_USB, &bus);
+	for (uclass_find_first_device(UCLASS_USB, &bus);
 		bus;
-		uclass_next_device(&bus)) {
+		uclass_find_next_device(&bus)) {
 		struct usb_device *udev;
 		struct udevice *dev;
 
+		if (!device_active(bus))
+			continue;
+
 		device_find_first_child(bus, &dev);
 		if (dev && device_active(dev)) {
 			udev = dev_get_parent_priv(dev);
-- 
cgit v0.10.2


From 5f79d008408dfe46172f46f8532e5ef6b3616067 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 21 Mar 2016 13:38:11 +0100
Subject: arm: socfpga: Handle phy-mode OF property for GMACs

Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.

This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ce3ff0a..5f988e3 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -77,7 +77,8 @@ void v7_outer_cache_disable(void)
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id)
+static void dwmac_deassert_reset(const unsigned int of_reset_id,
+				 const u32 phymode)
 {
 	u32 physhift, reset;
 
@@ -98,16 +99,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
 
 	/* configure to PHY interface select choosed */
 	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
-		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+		     phymode << physhift);
 
 	/* Release the EMAC controller from reset */
 	socfpga_per_reset(reset, 0);
 }
 
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+	if (!phymode)
+		return -EINVAL;
+
+	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rgmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 static int socfpga_eth_reset(void)
 {
 	const void *fdt = gd->fdt_blob;
 	struct fdtdec_phandle_args args;
+	const char *phy_mode;
+	u32 phy_modereg;
 	int nodes[2];	/* Max. two GMACs */
 	int ret, count;
 	int i, node;
@@ -132,7 +158,14 @@ static int socfpga_eth_reset(void)
 			continue;
 		}
 
-		dwmac_deassert_reset(args.args[0]);
+		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+		if (ret) {
+			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+			continue;
+		}
+
+		dwmac_deassert_reset(args.args[0], phy_modereg);
 	}
 
 	return 0;
-- 
cgit v0.10.2


From 4d74c02724668c5068519fa37639de2d94aad505 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 20 Mar 2016 18:02:44 +0100
Subject: arm: socfpga: sockit: Use more relaxed DRAM timings

The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h
index 83b1093..51b262b 100644
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
 	0x00001000,
 	0xA0000034,
 	0x0D000001,
-	0x40680208,
-	0x41034051,
-	0x12481A00,
-	0x802080D0,
-	0x34051406,
-	0x01A02490,
-	0x080D0000,
-	0x51406802,
-	0x02490340,
+	0xE0680B2C,
+	0x20834038,
+	0x11441A00,
+	0x80B2C0D0,
+	0x34038E06,
+	0x01A00208,
+	0x2C0D0000,
+	0x38E0680B,
+	0x00208340,
 	0xD000001A,
-	0x0680A280,
+	0x0680B2C0,
 	0x10040000,
 	0x00200000,
 	0x10040000,
@@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
 	0x00001000,
 	0xA0000034,
 	0x0D000001,
-	0x40680208,
-	0x49034051,
-	0x12481A02,
-	0x80A280D0,
-	0x34030C06,
+	0xE0680B2C,
+	0x20834038,
+	0x11441A00,
+	0x80B2C0D0,
+	0x34038E06,
 	0x01A00040,
-	0x280D0002,
-	0x5140680A,
-	0x02490340,
-	0xD012481A,
-	0x0680A280,
+	0x2C0D0002,
+	0x38E0680B,
+	0x00208340,
+	0xD001041A,
+	0x0680B2C0,
 	0x10040000,
 	0x00200000,
 	0x10040000,
@@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
 	0x14F3690D,
 	0x1A041414,
 	0x00D00000,
-	0x04864000,
-	0x59647A01,
-	0xD32CA3DE,
-	0xF551451E,
-	0x034CD348,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
 	0x821A0000,
 	0x0000D000,
-	0x05140680,
-	0xD669A47A,
-	0x1ED32CA3,
-	0x48F55E79,
-	0x00034C92,
+	0x05960680,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
 	0x00080200,
 	0x00001000,
 	0x00080200,
@@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
 	0x14F3690D,
 	0x1A041414,
 	0x00D00000,
-	0x14864000,
-	0x59647A05,
-	0x9228A3DE,
-	0xF65E791E,
-	0x034CD348,
-	0x821A0186,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
+	0x821A01C7,
 	0x0000D000,
 	0x00000680,
-	0xD669A47A,
-	0x1E9228A3,
-	0x48F65E79,
-	0x00034CD3,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
 	0x00080200,
 	0x00001000,
 	0x00080200,
@@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
 	0x14F3690D,
 	0x1A041414,
 	0x00D00000,
-	0x0C864000,
-	0x79E47A03,
-	0xB2AAA3D1,
-	0xF551451E,
-	0x035CD348,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
 	0x821A0000,
 	0x0000D000,
 	0x00000680,
-	0xD159647A,
-	0x1ED32CA3,
-	0x48F55145,
-	0x00035CD3,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
 	0x00080200,
 	0x00001000,
 	0x00080200,
@@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
 	0x14F1690D,
 	0x1A041414,
 	0x00D00000,
-	0x04864000,
-	0x69A47A01,
-	0x9228A3D6,
-	0xF65E791E,
-	0x034C9248,
+	0x18864000,
+	0x49247A06,
+	0xABCF23D7,
+	0xF7DE791E,
+	0x0356E388,
 	0x821A0000,
 	0x0000D000,
 	0x00000680,
-	0xDE59647A,
-	0x1ED32CA3,
-	0x48F55E79,
-	0x00034CD3,
+	0xD749247A,
+	0x1EABCF23,
+	0x88F7DE79,
+	0x000356E3,
 	0x00080200,
 	0x00001000,
 	0x00080200,
diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h
index 0ecccbf..820b9ff 100644
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -10,13 +10,13 @@
 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
@@ -61,7 +61,7 @@
 #define CONFIG_HPS_CLK_OSC2_HZ 25000000
 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
 #define CONFIG_HPS_CLK_EMAC0_HZ 1953125
@@ -69,7 +69,7 @@
 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
 #define CONFIG_HPS_CLK_NAND_HZ 50000000
 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
 #define CONFIG_HPS_CLK_CAN0_HZ 12500000
 #define CONFIG_HPS_CLK_CAN1_HZ 12500000
@@ -78,8 +78,8 @@
 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
 
 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 81c7d8e..769aa77 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -32,11 +32,11 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			11
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			12
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
@@ -46,7 +46,7 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
@@ -127,8 +127,8 @@
 
 /* Sequencer defines configuration */
 #define AFI_RATE_RATIO	1
-#define CALIB_LFIFO_OFFSET	8
-#define CALIB_VFIFO_OFFSET	6
+#define CALIB_LFIFO_OFFSET	12
+#define CALIB_VFIFO_OFFSET	10
 #define ENABLE_SUPER_QUICK_CALIBRATION	0
 #define IO_DELAY_PER_DCHAIN_TAP	25
 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
@@ -147,7 +147,7 @@
 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
 #define MAX_LATENCY_COUNT_WIDTH	5
 #define READ_VALID_FIFO_SIZE	16
-#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048d
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048c
 #define RW_MGR_MEM_ADDRESS_MIRRORING	0
 #define RW_MGR_MEM_DATA_MASK_WIDTH	4
 #define RW_MGR_MEM_DATA_WIDTH	32
@@ -171,16 +171,16 @@
 const u32 ac_rom_init[] = {
 	0x20700000,
 	0x20780000,
-	0x10080431,
-	0x10080530,
-	0x10090044,
-	0x100a0008,
+	0x10080471,
+	0x10080570,
+	0x10090006,
+	0x100a0218,
 	0x100b0000,
 	0x10380400,
-	0x10080449,
-	0x100804c8,
-	0x100a0024,
-	0x10090010,
+	0x10080469,
+	0x100804e8,
+	0x100a0006,
+	0x10090218,
 	0x100b0000,
 	0x30780000,
 	0x38780000,
-- 
cgit v0.10.2


From 723a72af29e95982940bdba7a4ec4b22047d62d8 Mon Sep 17 00:00:00 2001
From: Denis Bakhvalov <dendibakh@gmail.com>
Date: Thu, 24 Mar 2016 22:39:09 +0100
Subject: arm: socfpga: migration of CONFIG_SPI_FLASH_BAR

CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
and placed in socfpga_*_defconfig because it is Kconfig symbol.

Signed-off-by: Denis Bakhvalov <dendibakh@gmail.com>
Reported-by: Denis Bakhvalov <dendibakh@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index d93600b..087d6f1 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index f77e124..cef644e 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 9c341b6..c0ffad2 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -19,6 +19,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 48c7012..e01282c 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -19,6 +19,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 6a13504..8feb5a3 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 0860707..1b3c3df 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 2842fba..ec57746 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -17,6 +17,7 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 07519c1..3e50892 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -93,7 +93,6 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		30000000
-#define CONFIG_SPI_FLASH_BAR
 /*
  * The base address is configurable in QSys, each board must specify the
  * base address based on it's particular FPGA configuration. Please note
@@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 #define CONFIG_CQSPI_DECODER		0
 #define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
 
 /*
  * Designware SPI support
-- 
cgit v0.10.2


From dafd5792a8d91e6d616d7efa53bf336b0a12f12b Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 19 Mar 2016 18:59:11 +0100
Subject: arm: socfpga: Nuke useless include

The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/arch/arm/mach-socfpga/include/mach/dwmmc.h b/arch/arm/mach-socfpga/include/mach/dwmmc.h
deleted file mode 100644
index e8ba901..0000000
--- a/arch/arm/mach-socfpga/include/mach/dwmmc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	_SOCFPGA_DWMMC_H_
-#define	_SOCFPGA_DWMMC_H_
-
-int socfpga_dwmmc_init(const void *blob);
-
-#endif /* _SOCFPGA_SDMMC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5f988e3..dd05e14 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -16,7 +16,6 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/system_manager.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/arch/nic301.h>
 #include <asm/arch/scu.h>
 #include <asm/pl310.h>
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 43a7e7e..097db81 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,7 +6,6 @@
 
 #include <common.h>
 #include <asm/arch/clock_manager.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/arch/system_manager.h>
 #include <dm.h>
 #include <dwmmc.h>
-- 
cgit v0.10.2


From f6060ce4bb0673bed8331441e985620b1b24adbd Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 3 Apr 2016 19:11:12 +0200
Subject: arm: socfpga: Drop space after 'loadaddr=' in extra env

There is an incorrect space after loadaddr= in the extra environment,
so drop it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index a0161bc..153f9f8 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -56,7 +56,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
-	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index c4c4ecb..d7c339e 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -56,7 +56,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
-	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index cbc7396..314b9bf 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -51,7 +51,7 @@
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 95e7ba6..07cfcbf 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -52,7 +52,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
-	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index c32a40a..02ea0c5 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -52,7 +52,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
-	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 6414eeb..e43b5cf 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -55,7 +55,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
-	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=zImage\0" \
-- 
cgit v0.10.2


From d3bafe32ca47bc3872837c1fe7874f9913de103f Mon Sep 17 00:00:00 2001
From: Jeffy Chen <jeffy.chen@rock-chips.com>
Date: Wed, 3 Feb 2016 18:13:55 +0800
Subject: fastboot: sparse: fix sparse blocks calculation

It may overflow in sparse_block_size_to_storage, use uint64_t instead in
the calculation.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>

diff --git a/common/image-sparse.c b/common/image-sparse.c
index dffe844..2433192 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -64,7 +64,8 @@ static unsigned int sparse_block_size_to_storage(unsigned int size,
 						 sparse_storage_t *storage,
 						 sparse_header_t *sparse)
 {
-	return size * sparse->blk_sz / storage->block_sz;
+	return (unsigned int)lldiv((uint64_t)size * sparse->blk_sz,
+				   storage->block_sz);
 }
 
 static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
-- 
cgit v0.10.2


From c00c29d8f70533b8b59e48be207027e58c735d2b Mon Sep 17 00:00:00 2001
From: Guy Thouret <guy.thouret@wems.co.uk>
Date: Fri, 11 Mar 2016 13:31:39 +0000
Subject: env_eeprom invalidates gd->env_addr by setting it to an offset value

Patch to fix boot hang when using env on i2c eeprom caused by invalid gd->env_addr

Signed-off-by: Guy Thouret <guy.thouret@wems.co.uk>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/common/env_eeprom.c b/common/env_eeprom.c
index 72b1373..5f63a6c 100644
--- a/common/env_eeprom.c
+++ b/common/env_eeprom.c
@@ -145,11 +145,6 @@ void env_relocate_spec(void)
 			gd->env_valid = 1;
 	}
 
-	if (gd->env_valid == 2)
-		gd->env_addr = off_env[1] + offsetof(env_t, data);
-	else if (gd->env_valid == 1)
-		gd->env_addr = off_env[0] + offsetof(env_t, data);
-
 #else /* CONFIG_ENV_OFFSET_REDUND */
 	ulong crc, len, new;
 	uchar rdbuf[64];
@@ -175,10 +170,8 @@ void env_relocate_spec(void)
 	}
 
 	if (crc == new) {
-		gd->env_addr	= offsetof(env_t, data);
 		gd->env_valid	= 1;
 	} else {
-		gd->env_addr	= 0;
 		gd->env_valid	= 0;
 	}
 #endif /* CONFIG_ENV_OFFSET_REDUND */
-- 
cgit v0.10.2


From 4861be7e68e6cf1359389837be174dbb40d07533 Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Fri, 1 Apr 2016 21:27:50 +0300
Subject: arm: socfpga: sr1500: Remove USB_GADGET

"buildman" tool revealed that USB_GADGET was enabled by mistake for this
board in process of moving that option to Kconfig. Remove it to bring
things back to correct state.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Stefan Roese <sr@denx.de>

diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index ec57746..83eada3 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -22,5 +22,3 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_GADGET=y
-- 
cgit v0.10.2


From 7439b4399b14242e6c41b86734baa3fe31c4517f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Fri, 1 Apr 2016 21:14:14 -0600
Subject: ARM: allow CONFIG_GICV* not to be defined

There are ARM SoCs (such as the BCM2837) do not contain an ARM GIC. Fix
the ARMv8 CPU startup code to compile in this case.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 67b166c..dceedd7 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -202,14 +202,14 @@ WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
 #ifndef CONFIG_ARMV8_MULTIENTRY
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	/*
 	 * For single-entry systems the lowlevel init is very simple.
 	 */
 	ldr	x0, =GICD_BASE
 	bl	gic_init_secure
-
+#endif
 #else /* CONFIG_ARMV8_MULTIENTRY is set */
-
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	branch_if_slave x0, 1f
 	ldr	x0, =GICD_BASE
-- 
cgit v0.10.2


From d22a765755ba318ce162a976f51d44000a201394 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Fri, 1 Apr 2016 21:14:15 -0600
Subject: ARM: add Raspberry Pi 3 64-bit config

On all Pis so far, the VC FW provides a short stub to set up the ARM CPU
before entering the kernel (a/k/a U-Boot for us). This feature is not
currently supported by the VC FW when booting in 64-bit mode. However,
this feature will likely appear in the near future, and this U-Boot port
assumes that such a feature is in place. Without that feature, or a
temporary workaround described below, U-Boot will not boot.

Once the VC FW does provide the ARM stub, u-boot.bin built for rpi_3 can
be used drectly as kernel7.img, in the same way as any other RPi port. The
following config.txt is required:

    # Fix mini UART input frequency, and setup/enable up the UART.
    # Without this option, U-Boot will not boot, even if you don't care
    # about the serial console. This option will always be required for
    # all RPi3 use-cases, unless the PL011 UART is used, which is not
    # yet supported by rpi_3* builds of U-Boot.
    enable_uart=1
    # Boot in AArch64 (64-bit) mode.
    # It is possible that a future VC FW will remove the need for this
    # option, instead auto-setting 32-/64-bit mode based on the "kernel"
    # filename present on the SD card.
    arm_control=0x200

Prior to the VC FW providing the ARM boot stub, you can use the following
steps to build an equivalent stub into the U-Boot binary:

git clone https://github.com/swarren/rpi-3-aarch64-demo.git \
    ../rpi-3-aarch64-demo
(cd ../rpi-3-aarch64-demo && ./build.sh)
Build U-Boot for rpi_3 in the usual way
cat ../rpi-3-aarch64-demo/armstub64.bin u-boot.bin > u-boot.bin.stubbed
Use u-boot.bin.stubbed as kernel7.img on the Pi SD card.

In this case, the following additional entries are required in config.txt:

    # Tell the FW to load the kernel image at address 0, the reset vector.
    kernel_old=1

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index a4d291d..a1ad1a4 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -70,12 +70,18 @@ config TARGET_RPI_3_32B
 	select BCM2837
 	select CPU_V7
 
+config TARGET_RPI_3
+	bool "Raspberry Pi 3 64-bit build"
+	select ARM64
+	select BCM2837
+
 endchoice
 
 config SYS_BOARD
 	default "rpi" if TARGET_RPI
 	default "rpi_2" if TARGET_RPI_2
 	default "rpi_3_32b" if TARGET_RPI_3_32B
+	default "rpi_3" if TARGET_RPI_3
 
 config SYS_VENDOR
 	default "raspberrypi"
@@ -87,5 +93,6 @@ config SYS_CONFIG_NAME
 	default "rpi" if TARGET_RPI
 	default "rpi_2" if TARGET_RPI_2
 	default "rpi_3_32b" if TARGET_RPI_3_32B
+	default "rpi_3" if TARGET_RPI_3
 
 endmenu
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 20b5cf4..c45ddb1 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -19,6 +19,9 @@
 #include <asm/global_data.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include <dm/platform_data/serial_bcm283x_mu.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -228,6 +231,28 @@ static uint32_t rev_scheme;
 static uint32_t rev_type;
 static const struct rpi_model *model;
 
+#ifdef CONFIG_ARM64
+static struct mm_region bcm2837_mem_map[] = {
+	{
+		.base = 0x00000000UL,
+		.size = 0x3f000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0x3f000000UL,
+		.size = 0x01000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = bcm2837_mem_map;
+#endif
+
 int dram_init(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
diff --git a/board/raspberrypi/rpi_3/MAINTAINERS b/board/raspberrypi/rpi_3/MAINTAINERS
new file mode 100644
index 0000000..26ecd99
--- /dev/null
+++ b/board/raspberrypi/rpi_3/MAINTAINERS
@@ -0,0 +1,6 @@
+RPI_3_BOARD
+M:	Stephen Warren <swarren@wwwdotorg.org>
+S:	Maintained
+F:	board/raspberrypi/rpi_3/
+F:	include/configs/rpi_3.h
+F:	configs/rpi_3_defconfig
diff --git a/board/raspberrypi/rpi_3/Makefile b/board/raspberrypi/rpi_3/Makefile
new file mode 100644
index 0000000..78e2874
--- /dev/null
+++ b/board/raspberrypi/rpi_3/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= ../rpi/rpi.o
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
new file mode 100644
index 0000000..417836b
--- /dev/null
+++ b/configs/rpi_3_defconfig
@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 5904a32..645c361 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -13,9 +13,12 @@
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARCH_CPU_INIT
 
+/* Use SoC timer for AArch32, but architected timer for AArch64 */
+#ifndef CONFIG_ARM64
 #define CONFIG_SYS_TIMER_RATE		1000000
 #define CONFIG_SYS_TIMER_COUNTER	\
 	(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
+#endif
 
 /*
  * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
diff --git a/include/configs/rpi_3.h b/include/configs/rpi_3.h
new file mode 100644
index 0000000..0dd9e7e
--- /dev/null
+++ b/include/configs/rpi_3.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_CACHELINE_SIZE		64
+
+#include "rpi-common.h"
+
+#endif
-- 
cgit v0.10.2


From 158c9c78a50f7f04f4498abe36f8c1be83fafb75 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Fri, 1 Apr 2016 21:38:04 -0600
Subject: ARM: rpi: add some missing Kconfig help text

Add notes re: enabling the UART to the RPi 3 32-bit help text. Fully
describe the RPi 3 64-bit board option.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index a1ad1a4..f4c9502 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -63,7 +63,9 @@ config TARGET_RPI_3_32B
 	  This option assumes the VideoCore firmware is configured to use the
 	  mini UART (rather than PL011) for the serial console. This is the
 	  default on the RPi 3. To enable the UART console, the following non-
-	  default option must be present in config.txt: enable_uart=1.
+	  default option must be present in config.txt: enable_uart=1. This is
+	  required for U-Boot to operate correctly, even if you only care
+	  about the HDMI/usbkbd console.
 
 	  This option creates a build targetting the ARMv7/AArch32 ISA.
 	select ARMV7_LPAE
@@ -72,6 +74,30 @@ config TARGET_RPI_3_32B
 
 config TARGET_RPI_3
 	bool "Raspberry Pi 3 64-bit build"
+	help
+	  Support for all BCM2837-based Raspberry Pi variants, such as
+	  the RPi 3 model B, in AArch64 (64-bit) mode.
+
+	  This option assumes the VideoCore firmware is configured to use the
+	  mini UART (rather than PL011) for the serial console. This is the
+	  default on the RPi 3. To enable the UART console, the following non-
+	  default option must be present in config.txt: enable_uart=1. This is
+	  required for U-Boot to operate correctly, even if you only care
+	  about the HDMI/usbkbd console.
+
+	  At the time of writing, the VC FW requires a non-default option in
+	  config.txt to request the ARM CPU boot in 64-bit mode:
+	  arm_control=0x200
+
+	  The VC FW typically provides ARM "stub" code to set up the CPU and
+	  quiesce secondary SMP CPUs. This is not currently true in 64-bit
+	  mode. In order to boot U-Boot before the VC FW is enhanced, please
+	  see the commit description for the commit which added RPi3 support
+	  for a workaround. Since the instructions are temporary, they are not
+	  duplicated here. The VC FW enhancement is tracked in
+	  https://github.com/raspberrypi/firmware/issues/579.
+
+	  This option creates a build targetting the ARMv8/AArch64 ISA.
 	select ARM64
 	select BCM2837
 
-- 
cgit v0.10.2


From 7e8721467da2e7cf0076533be9b2050cdc22ab1e Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Sat, 2 Apr 2016 07:37:12 -0700
Subject: cmd: blkcache: remove indentation from output of 'show'

Signed-off-by: Eric Nelson <eric@nelint.com>

diff --git a/cmd/blkcache.c b/cmd/blkcache.c
index 9a619e2..a3dd549 100644
--- a/cmd/blkcache.c
+++ b/cmd/blkcache.c
@@ -16,11 +16,11 @@ static int blkc_show(cmd_tbl_t *cmdtp, int flag,
 	struct block_cache_stats stats;
 	blkcache_stats(&stats);
 
-	printf("    hits: %u\n"
-	       "    misses: %u\n"
-	       "    entries: %u\n"
-	       "    max blocks/entry: %u\n"
-	       "    max cache entries: %u\n",
+	printf("hits: %u\n"
+	       "misses: %u\n"
+	       "entries: %u\n"
+	       "max blocks/entry: %u\n"
+	       "max cache entries: %u\n",
 	       stats.hits, stats.misses, stats.entries,
 	       stats.max_blocks_per_entry, stats.max_entries);
 	return 0;
-- 
cgit v0.10.2


From 195c94a24071fa6be913219e0d98bb210b06ccb5 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Sat, 2 Apr 2016 07:37:13 -0700
Subject: cmd: blkcache: simplify sub-command handling

Signed-off-by: Eric Nelson <eric@nelint.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/cmd/blkcache.c b/cmd/blkcache.c
index a3dd549..d7afe3e 100644
--- a/cmd/blkcache.c
+++ b/cmd/blkcache.c
@@ -73,12 +73,10 @@ static int do_blkcache(cmd_tbl_t *cmdtp, int flag,
 
 	c = find_cmd_tbl(argv[0], &cmd_blkc_sub[0], ARRAY_SIZE(cmd_blkc_sub));
 
-	if (c)
-		return c->cmd(cmdtp, flag, argc, argv);
-	else
+	if (!c)
 		return CMD_RET_USAGE;
 
-	return 0;
+	return c->cmd(cmdtp, flag, argc, argv);
 }
 
 U_BOOT_CMD(
-- 
cgit v0.10.2


From c8e4d2a8b90cfb2a19c274ba7e5525b2757dab77 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Sat, 2 Apr 2016 07:37:14 -0700
Subject: drivers: block: fix placement of parameters

Signed-off-by: Eric Nelson <eric@nelint.com>

diff --git a/include/blk.h b/include/blk.h
index 263a791..f624671 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -96,10 +96,9 @@ struct blk_desc {
  *
  * @return - '1' if block returned from cache, '0' otherwise.
  */
-int blkcache_read
-	(int iftype, int dev,
-	 lbaint_t start, lbaint_t blkcnt,
-	 unsigned long blksz, void *buffer);
+int blkcache_read(int iftype, int dev,
+		  lbaint_t start, lbaint_t blkcnt,
+		  unsigned long blksz, void *buffer);
 
 /**
  * blkcache_fill() - make data read from a block device available
@@ -113,10 +112,9 @@ int blkcache_read
  * @param buf - buffer containing data to cache
  *
  */
-void blkcache_fill
-	(int iftype, int dev,
-	 lbaint_t start, lbaint_t blkcnt,
-	 unsigned long blksz, void const *buffer);
+void blkcache_fill(int iftype, int dev,
+		   lbaint_t start, lbaint_t blkcnt,
+		   unsigned long blksz, void const *buffer);
 
 /**
  * blkcache_invalidate() - discard the cache for a set of blocks
@@ -125,8 +123,7 @@ void blkcache_fill
  * @param iftype - IF_TYPE_x for type of device
  * @param dev - device index of particular type
  */
-void blkcache_invalidate
-	(int iftype, int dev);
+void blkcache_invalidate(int iftype, int dev);
 
 /**
  * blkcache_configure() - configure block cache
@@ -156,21 +153,18 @@ void blkcache_stats(struct block_cache_stats *stats);
 
 #else
 
-static inline int blkcache_read
-	(int iftype, int dev,
-	 lbaint_t start, lbaint_t blkcnt,
-	 unsigned long blksz, void *buffer)
+static inline int blkcache_read(int iftype, int dev,
+				lbaint_t start, lbaint_t blkcnt,
+				unsigned long blksz, void *buffer)
 {
 	return 0;
 }
 
-static inline void blkcache_fill
-	(int iftype, int dev,
-	 lbaint_t start, lbaint_t blkcnt,
-	 unsigned long blksz, void const *buffer) {}
+static inline void blkcache_fill(int iftype, int dev,
+				 lbaint_t start, lbaint_t blkcnt,
+				 unsigned long blksz, void const *buffer) {}
 
-static inline void blkcache_invalidate
-	(int iftype, int dev) {}
+static inline void blkcache_invalidate(int iftype, int dev) {}
 
 #endif
 
-- 
cgit v0.10.2


From 8eca9439eaac7a1d0742c11879fd1b2d8f8e1375 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 2 Apr 2016 11:53:18 -0300
Subject: README: Specify the full path for README.video

It is clearer to specify the full path to access the
doc/README.video file.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/README b/README
index 597d615..88ff837 100644
--- a/README
+++ b/README
@@ -1802,7 +1802,7 @@ CBFS (Coreboot Filesystem) support
 
 		The DIU driver will look for the 'video-mode' environment
 		variable, and if defined, enable the DIU as a console during
-		boot.  See the documentation file README.video for a
+		boot.  See the documentation file doc/README.video for a
 		description of this variable.
 
 - LCD Support:	CONFIG_LCD
-- 
cgit v0.10.2


From 8b15010b1fc6a0da76db0b5d96d12ffe69990dbe Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Sat, 20 Feb 2016 11:30:19 +0300
Subject: arc: get rid of running_on_hw

ISS is obsolete now and nSIM is used for simulation instead.
In its turn nSIM properly handles baud-rate settings so get rid
of now useless check.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
index d644e80..e25b966 100644
--- a/arch/arc/include/asm/global_data.h
+++ b/arch/arc/include/asm/global_data.h
@@ -9,7 +9,6 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
-	int running_on_hw;
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 4e4dd74..d1f10ab 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -14,12 +14,6 @@ int arch_cpu_init(void)
 {
 	timer_init();
 
-/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
-	if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
-		gd->arch.running_on_hw = 0;
-	else
-		gd->arch.running_on_hw = 1;
-
 	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
index 6292eb1..326a536 100644
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -42,23 +42,7 @@ static int arc_serial_setbrg(struct udevice *dev, int baudrate)
 	int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1;
 
 	writeb(arc_console_baud & 0xff, &regs->baudl);
-
-#ifdef CONFIG_ARC
-	/*
-	 * UART ISS(Instruction Set simulator) emulation has a subtle bug:
-	 * A existing value of Baudh = 0 is used as a indication to startup
-	 * it's internal state machine.
-	 * Thus if baudh is set to 0, 2 times, it chokes.
-	 * This happens with BAUD=115200 and the formaula above
-	 * Until that is fixed, when running on ISS, we will set baudh to !0
-	 */
-	if (gd->arch.running_on_hw)
-		writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
-	else
-		writeb(1, &regs->baudh);
-#else
 	writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
-#endif
 
 	return 0;
 }
-- 
cgit v0.10.2


From 53637c911b7a2397b50690cd67b7d59145bcae9c Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Fri, 8 Apr 2016 09:21:12 -0700
Subject: arc: Add virt_to_phys() stub

Commit cf7c93cdd755 "usb: ehci: Implement V2P mapping"
introduced usage of virt_to_phys() in ehci-hcd.

Since there was no implementation of virt_to_phys() for ARC
compilation of the ehci-generic driver failed.

This change adds virt_to_phys() stub for ARC so now
USB driver for AXS101 board could be built again.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 281682c..b6f7724 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -239,4 +239,9 @@ static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
 #define setbits_8(addr, set) setbits(8, addr, set)
 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)((unsigned long)vaddr);
+}
+
 #endif	/* __ASM_ARC_IO_H */
-- 
cgit v0.10.2


From c3333ded03b4868c42b0eefd4a3e97c14e0d1f57 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Mon, 4 Apr 2016 10:53:31 +0300
Subject: board: ti: am57xx: Prevent init_sata() from being called twice

init_sata() is done as part of scsi_init() in
arch/arm/cpu/armv7/omap-common/sata.c so no need to duplicate
it here.

This seems to fix SATA problems in the kernel when CONFIG_TI_PIPE3 is
configured as loadable module.

Cc: Cooper Jr., Franklin <fcooper@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 18416ef..a5f02e6 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -324,7 +324,6 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	init_sata(0);
 	setup_board_eeprom_env();
 
 	/*
-- 
cgit v0.10.2


From eed095da30bb6f464c24db81fb6406f7ba1cc16b Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 4 Apr 2016 11:04:50 -0600
Subject: test/py: pass -v option when executing sandbox

This shows more output, such as the internal output generated by the unit
test ("ut") command, which makes it easier to debug issues.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py
index 3de0fe4..04654ae 100644
--- a/test/py/u_boot_console_sandbox.py
+++ b/test/py/u_boot_console_sandbox.py
@@ -44,6 +44,7 @@ class ConsoleSandbox(ConsoleBase):
             cmd += ['gdbserver', self.config.gdbserver]
         cmd += [
             self.config.build_dir + '/u-boot',
+            '-v',
             '-d',
             self.config.build_dir + '/arch/sandbox/dts/test.dtb'
         ]
-- 
cgit v0.10.2


From aafa64827f30a7d2aa2c2cc2a60906eabd0272b8 Mon Sep 17 00:00:00 2001
From: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Date: Mon, 4 Apr 2016 19:55:58 +0200
Subject: spmi: Fix sandbox spmi driver memory corruption

There is off-by-one error in sandbox_emul_gpio that causes
segfault of certain tests.

EMUL_GPIO_REG_END is the address of last valid (emulated) register.
This patch fixed this (by adding one more element to emulated register array).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/spmi/spmi-sandbox.c b/drivers/spmi/spmi-sandbox.c
index 2f0fea0..980aff2 100644
--- a/drivers/spmi/spmi-sandbox.c
+++ b/drivers/spmi/spmi-sandbox.c
@@ -35,7 +35,8 @@ struct sandbox_emul_fake_regs {
 };
 
 struct sandbox_emul_gpio {
-	struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END]; /* Fake registers */
+	/* Fake registers - need one more entry as REG_END is valid address. */
+	struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END + 1];
 };
 
 struct sandbox_spmi_priv {
-- 
cgit v0.10.2


From 3ba1352b97999546610cc9b8708281b60d660e48 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 4 Apr 2016 20:06:14 +0200
Subject: test/py: Add support for loading image via tftp to specified location

For example this setting:

env__net_tftp_readable_file = {
    "fn": "ep108/image.ub",
    "addr": 0x10000000,
    "size": 25846296,
    "crc32": "b726f9de",
}

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index 07393eb..4ab58b4 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -43,6 +43,7 @@ env__net_static_env_vars = [
 # may be omitted or set to None if TFTP testing is not possible or desired.
 env__net_tftp_readable_file = {
     "fn": "ubtest-readable.bin",
+    "addr": 0x10000000,
     "size": 5058624,
     "crc32": "c2244b26",
 }
@@ -135,7 +136,10 @@ def test_net_tftpboot(u_boot_console):
     if not f:
         pytest.skip('No TFTP readable file to read')
 
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+    addr = f.get('addr', None)
+    if not addr:
+        addr = u_boot_utils.find_ram_base(u_boot_console)
+
     fn = f['fn']
     output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
     expected_text = 'Bytes transferred = '
-- 
cgit v0.10.2


From 9082517a85930740f59966fcf13293c38792afe8 Mon Sep 17 00:00:00 2001
From: Vikas Manocha <vikas.manocha@st.com>
Date: Mon, 4 Apr 2016 16:49:02 -0700
Subject: stm32: stm32_flash: add memory barrier during flash write

After writing data to flash space, next instruction is checking if flash
controller is busy writing to the flash memory. Memory barrier is required here
to avoid transaction re-ordering for data write and busy status check.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c
index 71f4854..e16b6cd 100644
--- a/drivers/mtd/stm32_flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -137,6 +137,10 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	/* To make things simple use byte writes only */
 	for (i = 0; i < cnt; i++) {
 		*(uchar *)(addr + i) = src[i];
+		/*  avoid re-ordering flash data write and busy status
+		 *  check as flash memory space attributes are generally Normal
+		 */
+		mb();
 		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
 			;
 	}
-- 
cgit v0.10.2


From fe84ebf0214cfc1766fb467268f056bed32a08ab Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Mon, 4 Apr 2016 20:00:41 -0600
Subject: rpi: remove redundant board files

Now that rpi_*defconfig and Kconfig (rather than the config header file)
provide the identity of the build, we don't need to separate config
headers and board directories for each RPi variant. Set CONFIG_SYS_BOARD
and CONFIG_SYS_CONFIG_NAME so that we can get rid of the duplication. This
requires a tiny number of extra ifdefs in the config header.

The only disadvantage of this approach is that the $board/$board_name
environment variables aren't as descriptive as they used to be. This isn't
really an issue because those only exist to allow scripts to create DTB
filenames at runtime. However, the RPi board code already sets $fdtfile to
something more accurate based on FW-reported board ID anyway.

While at it, unify some Kconfig select options, and add a MAINTAINERS
entry for bcm283x too.

Partially-suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 87e0c2e..383a4ff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -78,6 +78,16 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 
+ARM BROADCOM BCM283X
+M:	Stephen Warren <swarren@wwwdotorg.org>
+S:	Maintained
+F:	arch/arm/mach-bcm283x/
+F:	drivers/gpio/bcm2835_gpio.c
+F:	drivers/mmc/bcm2835_sdhci.c
+F:	drivers/serial/serial_bcm283x_mu.c
+F:	drivers/video/bcm2835.c
+F:	include/dm/platform_data/serial_bcm283x_mu.h
+
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
 S:	Maintained
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index f4c9502..69f7a46 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -1,15 +1,31 @@
 config BCM2835
 	bool "Broadcom BCM2835 SoC support"
 	depends on ARCH_BCM283X
+	select CPU_ARM1176
 
 config BCM2836
 	bool "Broadcom BCM2836 SoC support"
 	depends on ARCH_BCM283X
+	select ARMV7_LPAE
+	select CPU_V7
 
 config BCM2837
 	bool "Broadcom BCM2837 SoC support"
 	depends on ARCH_BCM283X
 
+config BCM2837_32B
+	bool "Broadcom BCM2837 SoC 32-bit support"
+	depends on ARCH_BCM283X
+	select BCM2837
+	select ARMV7_LPAE
+	select CPU_V7
+
+config BCM2837_64B
+	bool "Broadcom BCM2837 SoC 64-bit support"
+	depends on ARCH_BCM283X
+	select BCM2837
+	select ARM64
+
 menu "Broadcom BCM283X family"
 	depends on ARCH_BCM283X
 
@@ -27,7 +43,6 @@ config TARGET_RPI
 
 	  This option creates a build targetting the ARM1176 ISA.
 	select BCM2835
-	select CPU_ARM1176
 
 config TARGET_RPI_2
 	bool "Raspberry Pi 2"
@@ -50,9 +65,7 @@ config TARGET_RPI_2
 	  https://github.com/raspberrypi/firmware/issues/572".
 
 	  This option creates a build targetting the ARMv7/AArch32 ISA.
-	select ARMV7_LPAE
 	select BCM2836
-	select CPU_V7
 
 config TARGET_RPI_3_32B
 	bool "Raspberry Pi 3 32-bit build"
@@ -68,9 +81,7 @@ config TARGET_RPI_3_32B
 	  about the HDMI/usbkbd console.
 
 	  This option creates a build targetting the ARMv7/AArch32 ISA.
-	select ARMV7_LPAE
-	select BCM2837
-	select CPU_V7
+	select BCM2837_32B
 
 config TARGET_RPI_3
 	bool "Raspberry Pi 3 64-bit build"
@@ -98,16 +109,12 @@ config TARGET_RPI_3
 	  https://github.com/raspberrypi/firmware/issues/579.
 
 	  This option creates a build targetting the ARMv8/AArch64 ISA.
-	select ARM64
-	select BCM2837
+	select BCM2837_64B
 
 endchoice
 
 config SYS_BOARD
-	default "rpi" if TARGET_RPI
-	default "rpi_2" if TARGET_RPI_2
-	default "rpi_3_32b" if TARGET_RPI_3_32B
-	default "rpi_3" if TARGET_RPI_3
+	default "rpi"
 
 config SYS_VENDOR
 	default "raspberrypi"
@@ -116,9 +123,6 @@ config SYS_SOC
 	default "bcm283x"
 
 config SYS_CONFIG_NAME
-	default "rpi" if TARGET_RPI
-	default "rpi_2" if TARGET_RPI_2
-	default "rpi_3_32b" if TARGET_RPI_3_32B
-	default "rpi_3" if TARGET_RPI_3
+	default "rpi"
 
 endmenu
diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile
index f0dadd0..5cb1b2f 100644
--- a/arch/arm/mach-bcm283x/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0
 #
 
-obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o
+obj-$(CONFIG_BCM2835) += lowlevel_init.o
 obj-y	+= init.o reset.o mbox.o phys2bus.o
diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS
index 6dcb7bd..98c3758 100644
--- a/board/raspberrypi/rpi/MAINTAINERS
+++ b/board/raspberrypi/rpi/MAINTAINERS
@@ -3,4 +3,4 @@ M:	Stephen Warren <swarren@wwwdotorg.org>
 S:	Maintained
 F:	board/raspberrypi/rpi/
 F:	include/configs/rpi.h
-F:	configs/rpi_defconfig
+F:	configs/rpi_*defconfig
diff --git a/board/raspberrypi/rpi_2/MAINTAINERS b/board/raspberrypi/rpi_2/MAINTAINERS
deleted file mode 100644
index 85a480c..0000000
--- a/board/raspberrypi/rpi_2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RPI_2 BOARD
-M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Maintained
-F:	board/raspberrypi/rpi_2/
-F:	include/configs/rpi_2.h
-F:	configs/rpi_2_defconfig
diff --git a/board/raspberrypi/rpi_2/Makefile b/board/raspberrypi/rpi_2/Makefile
deleted file mode 100644
index d82cd21..0000000
--- a/board/raspberrypi/rpi_2/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2012,2015 Stephen Warren
-#
-# SPDX-License-Identifier:	GPL-2.0
-#
-
-obj-y	:= ../rpi/rpi.o
diff --git a/board/raspberrypi/rpi_3/MAINTAINERS b/board/raspberrypi/rpi_3/MAINTAINERS
deleted file mode 100644
index 26ecd99..0000000
--- a/board/raspberrypi/rpi_3/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RPI_3_BOARD
-M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Maintained
-F:	board/raspberrypi/rpi_3/
-F:	include/configs/rpi_3.h
-F:	configs/rpi_3_defconfig
diff --git a/board/raspberrypi/rpi_3/Makefile b/board/raspberrypi/rpi_3/Makefile
deleted file mode 100644
index 78e2874..0000000
--- a/board/raspberrypi/rpi_3/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
-#
-# SPDX-License-Identifier:	GPL-2.0
-#
-
-obj-y	:= ../rpi/rpi.o
diff --git a/board/raspberrypi/rpi_3_32b/MAINTAINERS b/board/raspberrypi/rpi_3_32b/MAINTAINERS
deleted file mode 100644
index bc9df87..0000000
--- a/board/raspberrypi/rpi_3_32b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RPI_3_32B BOARD
-M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Maintained
-F:	board/raspberrypi/rpi_3_32b/
-F:	include/configs/rpi_3_32b.h
-F:	configs/rpi_3_32b_defconfig
diff --git a/board/raspberrypi/rpi_3_32b/Makefile b/board/raspberrypi/rpi_3_32b/Makefile
deleted file mode 100644
index 78e2874..0000000
--- a/board/raspberrypi/rpi_3_32b/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
-#
-# SPDX-License-Identifier:	GPL-2.0
-#
-
-obj-y	:= ../rpi/rpi.o
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
deleted file mode 100644
index 645c361..0000000
--- a/include/configs/rpi-common.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2012-2016 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _RPI_COMMON_H_
-#define _RPI_COMMON_H_
-
-#include <linux/sizes.h>
-#include <asm/arch/timer.h>
-
-/* Architecture, CPU, etc.*/
-#define CONFIG_ARCH_CPU_INIT
-
-/* Use SoC timer for AArch32, but architected timer for AArch64 */
-#ifndef CONFIG_ARM64
-#define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	\
-	(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
-#endif
-
-/*
- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
- * so 2708 has historically been used rather than a dedicated 2835 ID.
- *
- * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
- * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
- * rather than obtaining a valid ID:-/
- *
- * For the bcm2837, hopefully a machine type is not needed, since everything
- * is DT.
- */
-#ifdef CONFIG_BCM2835
-#define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
-#endif
-
-/* Memory layout */
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_TEXT_BASE		0x00008000
-#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
-/*
- * The board really has 256M. However, the VC (VideoCore co-processor) shares
- * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
- * smaller amount of RAM is present in order to avoid stomping on the area
- * the VC uses.
- */
-#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_SDRAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN		SZ_4M
-#define CONFIG_SYS_MEMTEST_START	0x00100000
-#define CONFIG_SYS_MEMTEST_END		0x00200000
-#define CONFIG_LOADADDR			0x00200000
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH
-
-/* Devices */
-/* GPIO */
-#define CONFIG_BCM2835_GPIO
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_LCD_DT_SIMPLEFB
-#define LCD_BPP				LCD_COLOR16
-/*
- * Prevent allocation of RAM for FB; the real FB address is queried
- * dynamically from the VideoCore co-processor, and comes from RAM
- * not owned by the ARM CPU.
- */
-#define CONFIG_FB_ADDR			0
-#define CONFIG_VIDEO_BCM2835
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES	10
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS
-#define CONFIG_BCM2835_SDHCI
-
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#ifndef CONFIG_BCM2835
-#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
-#else
-#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
-#endif
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_MISC_INIT_R
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_SYS_STDIO_DEREGISTER
-#endif
-
-/* Console UART */
-#ifdef CONFIG_BCM2837
-#define CONFIG_BCM283X_MU_SERIAL
-#else
-#define CONFIG_PL01X_SERIAL
-#endif
-#define CONFIG_CONS_INDEX		0
-#define CONFIG_BAUDRATE			115200
-
-/* Console configuration */
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
-					 sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Environment */
-#define CONFIG_ENV_SIZE			SZ_16K
-#define CONFIG_ENV_IS_IN_FAT
-#define FAT_ENV_INTERFACE		"mmc"
-#define FAT_ENV_DEVICE_AND_PART		"0:1"
-#define FAT_ENV_FILE			"uboot.env"
-#define CONFIG_FAT_WRITE
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_SYS_LOAD_ADDR		0x1000000
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_PREBOOT			"usb start"
-
-/* Shell */
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_COMMAND_HISTORY
-
-/* Commands */
-#define CONFIG_CMD_MMC
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
-/* ATAGs support for bootm/bootz */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-#include <config_distro_defaults.h>
-
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define ENV_DEVICE_SETTINGS \
-	"stdin=serial,usbkbd\0" \
-	"stdout=serial,lcd\0" \
-	"stderr=serial,lcd\0"
-
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
- *
- * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
- *   binary firmware loads a DT to address 0x100, so we choose this address to
- *   match it. This allows custom boot scripts to pass this DT on to Linux
- *   simply by not over-writing the data at this address. When using U-Boot,
- *   U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
- *   and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
- *
- * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
- *   something else. Put it low in memory to avoid conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- *   should not overlap that area, or the kernel will have to copy itself
- *   somewhere else before decompression. Similarly, the address of any other
- *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
- *   this up to 16M allows for a sizable kernel to be decompressed below the
- *   compressed load address.
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- *   else. Choosing 32M allows for the compressed kernel to be up to 16M.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- *   for any boot script to be up to 1M, which is hopefully plenty.
- */
-#define ENV_MEM_LAYOUT_SETTINGS \
-	"fdt_high=ffffffff\0" \
-	"initrd_high=ffffffff\0" \
-	"fdt_addr_r=0x00000100\0" \
-	"pxefile_addr_r=0x00100000\0" \
-	"kernel_addr_r=0x01000000\0" \
-	"scriptaddr=0x02000000\0" \
-	"ramdisk_addr_r=0x02100000\0" \
-
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(USB, usb, 0) \
-	func(PXE, pxe, na) \
-	func(DHCP, dhcp, na)
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	ENV_DEVICE_SETTINGS \
-	ENV_MEM_LAYOUT_SETTINGS \
-	BOOTENV
-
-#define CONFIG_BOOTDELAY 2
-
-#endif
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 86422e3..b83d622 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2012,2015 Stephen Warren
+ * (C) Copyright 2012-2016 Stephen Warren
  *
  * SPDX-License-Identifier:	GPL-2.0
  */
@@ -7,8 +7,210 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <linux/sizes.h>
+#include <asm/arch/timer.h>
+
+#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifdef CONFIG_BCM2835
 #define CONFIG_SYS_CACHELINE_SIZE		32
+#else
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#endif
+
+/* Architecture, CPU, etc.*/
+#define CONFIG_ARCH_CPU_INIT
+
+/* Use SoC timer for AArch32, but architected timer for AArch64 */
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
+#endif
+
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ *
+ * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
+ * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
+ * rather than obtaining a valid ID:-/
+ *
+ * For the bcm2837, hopefully a machine type is not needed, since everything
+ * is DT.
+ */
+#ifdef CONFIG_BCM2835
+#define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
+#endif
+
+/* Memory layout */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_TEXT_BASE		0x00008000
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x00200000
+#define CONFIG_LOADADDR			0x00200000
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_LCD_DT_SIMPLEFB
+#define LCD_BPP				LCD_COLOR16
+/*
+ * Prevent allocation of RAM for FB; the real FB address is queried
+ * dynamically from the VideoCore co-processor, and comes from RAM
+ * not owned by the ARM CPU.
+ */
+#define CONFIG_FB_ADDR			0
+#define CONFIG_VIDEO_BCM2835
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_BCM2835_SDHCI
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#ifndef CONFIG_BCM2835
+#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
+#else
+#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
+#endif
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MISC_INIT_R
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_STDIO_DEREGISTER
+#endif
+
+/* Console UART */
+#ifdef CONFIG_BCM2837
+#define CONFIG_BCM283X_MU_SERIAL
+#else
+#define CONFIG_PL01X_SERIAL
+#endif
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Environment */
+#define CONFIG_ENV_SIZE			SZ_16K
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE		"mmc"
+#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_FILE			"uboot.env"
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_SYS_LOAD_ADDR		0x1000000
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT			"usb start"
+
+/* Shell */
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_COMMAND_HISTORY
+
+/* Commands */
+#define CONFIG_CMD_MMC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#include <config_distro_defaults.h>
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial,usbkbd\0" \
+	"stdout=serial,lcd\0" \
+	"stderr=serial,lcd\0"
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
+ *   binary firmware loads a DT to address 0x100, so we choose this address to
+ *   match it. This allows custom boot scripts to pass this DT on to Linux
+ *   simply by not over-writing the data at this address. When using U-Boot,
+ *   U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
+ *   and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it low in memory to avoid conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Choosing 32M allows for the compressed kernel to be up to 16M.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for any boot script to be up to 1M, which is hopefully plenty.
+ */
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_high=ffffffff\0" \
+	"initrd_high=ffffffff\0" \
+	"fdt_addr_r=0x00000100\0" \
+	"pxefile_addr_r=0x00100000\0" \
+	"kernel_addr_r=0x01000000\0" \
+	"scriptaddr=0x02000000\0" \
+	"ramdisk_addr_r=0x02100000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
+	ENV_DEVICE_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV
 
-#include "rpi-common.h"
+#define CONFIG_BOOTDELAY 2
 
 #endif
diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h
deleted file mode 100644
index 0917e86..0000000
--- a/include/configs/rpi_2.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_CACHELINE_SIZE		64
-
-#include "rpi-common.h"
-
-#endif
diff --git a/include/configs/rpi_3.h b/include/configs/rpi_3.h
deleted file mode 100644
index 0dd9e7e..0000000
--- a/include/configs/rpi_3.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_CACHELINE_SIZE		64
-
-#include "rpi-common.h"
-
-#endif
diff --git a/include/configs/rpi_3_32b.h b/include/configs/rpi_3_32b.h
deleted file mode 100644
index c00379b..0000000
--- a/include/configs/rpi_3_32b.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_CACHELINE_SIZE		64
-
-#include "rpi-common.h"
-
-#endif
-- 
cgit v0.10.2


From 7f961c90d76a485e16b2c52f6f66e58c909a5545 Mon Sep 17 00:00:00 2001
From: "Vogt, Christof" <Christof.Vogt@comsoft.de>
Date: Tue, 5 Apr 2016 10:56:57 +0200
Subject: am33xx changed BOOT_DEVICE_SPI to correct value

Changed BOOT_DEVICE Code for SPI on AM33xx.
According AM335x reference manual page 4960
(SPRUH73L-October 2011-Revised February 2015)
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 4ed8597..43401d0 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -43,7 +43,7 @@
 #define BOOT_DEVICE_NAND_I2C	0x06
 #define BOOT_DEVICE_MMC1	0x08
 #define BOOT_DEVICE_MMC2	0x09
-#define BOOT_DEVICE_SPI		0x15
+#define BOOT_DEVICE_SPI		0x0B
 #define BOOT_DEVICE_UART	0x41
 #define BOOT_DEVICE_USBETH	0x44
 #define BOOT_DEVICE_CPGMAC	0x46
-- 
cgit v0.10.2


From d9b2678e0a5e5781b37487ccb943ddcbf0623bb0 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 5 Apr 2016 13:34:20 +0200
Subject: disk: part: Enable get_info pointer for CONFIG_SPL_FAT_SUPPORT

The patch "dm: part: Convert partition API use to linker lists"
(sha1: 96e5b03c8ab749b6547f6a3ceb4d4b9f274211aa) is adding new
dependency for enabling SPL_EXT_SUPPORT to be able to get
information about DOS partition.
get_info is also required for FAT support only which is used on Xilinx
Zynq boards.

Reported-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/include/part.h b/include/part.h
index dc8e72e..e3811c6 100644
--- a/include/part.h
+++ b/include/part.h
@@ -207,7 +207,7 @@ static inline int blk_get_device_part_str(const char *ifname,
  */
 #ifdef CONFIG_SPL_BUILD
 # define part_print_ptr(x)	NULL
-# if defined(CONFIG_SPL_EXT_SUPPORT) || \
+# if defined(CONFIG_SPL_EXT_SUPPORT) || defined(CONFIG_SPL_FAT_SUPPORT) || \
 	defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
 #  define part_get_info_ptr(x)	x
 # else
-- 
cgit v0.10.2


From 20adda4cf8980a9df1d966bd7bec918ac3e4e5d6 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 6 Apr 2016 11:02:22 +0200
Subject: bootcounter_ram: Flush dcache after data is written into SDRAM

This patch adds a call to flush_dcache_range() to bootcount_store() to
make sure, that the bootcounter data (including the patterns) is
written to memory. Without this, platforms with dcache enabled may not
have the bootcounter updated upon reset.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>

diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c
index 5bdabcd..e0d2669 100644
--- a/drivers/bootcount/bootcount_ram.c
+++ b/drivers/bootcount/bootcount_ram.c
@@ -35,6 +35,9 @@ void bootcount_store(ulong a)
 		writel(patterns[i % NBR_OF_PATTERNS],
 			&save_addr[i + OFFS_PATTERN]);
 
+	/* Make sure the data is written to RAM */
+	flush_dcache_range((ulong)&save_addr[0],
+			   (ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN]);
 }
 
 ulong bootcount_load(void)
-- 
cgit v0.10.2


From 5b2beab5cdf6209e5b4027312d8f9e2a13f1ce46 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 6 Apr 2016 11:46:59 -0600
Subject: test/py: README: link to example hook scripts

When implementing test/py hook scripts, it's helpful to read some working
examples. Provide a link to some. The link was mentioned in the commit
message which first added test/py, but not in any documentation file.

Suggested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/test/py/README.md b/test/py/README.md
index ba1674c..829c7ef 100644
--- a/test/py/README.md
+++ b/test/py/README.md
@@ -246,6 +246,12 @@ to download the U-Boot binary directly into RAM and execute it. This would
 avoid the need for `u-boot-test-flash` to actually write U-Boot to flash, thus
 saving wear on the flash chip(s).
 
+#### Examples
+
+https://github.com/swarren/uboot-test-hooks contains some working example hook
+scripts, and may be useful as a reference when implementing hook scripts for
+your platform. These scripts are not considered part of U-Boot itself.
+
 ### Board-type-specific configuration
 
 Each board has a different configuration and behaviour. Many of these
-- 
cgit v0.10.2


From 456ecd08ec026e67a17a77baa3778c9f1b8e474d Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 8 Apr 2016 15:56:29 +0200
Subject: lib/crc8: Add crc start value

To make the usage of this function more flexible, lets add the CRC start
value as parameter to this function. This way it can be used by other
functions requiring different start values than 0 as well.

For non-zero CRC start values to work, I've reworked the function a bit.
The new implementation is copied from the Linux version in
drivers/i2c/i2c-core.c / i2c_smbus_pec(). Which supports non-zero
CRC stating values.

I've double-checked that the results for zero starting values are
identical to the results from the original version of this function.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c
index 9ea9807..4aade56 100644
--- a/drivers/tpm/tpm_tis_sandbox.c
+++ b/drivers/tpm/tpm_tis_sandbox.c
@@ -217,7 +217,7 @@ static int sandbox_tpm_xfer(struct udevice *dev, const uint8_t *sendbuf,
 			rsk.struct_version = 2;
 			rsk.uid = ROLLBACK_SPACE_KERNEL_UID;
 			rsk.kernel_versions = 0;
-			rsk.crc8 = crc8((unsigned char *)&rsk,
+			rsk.crc8 = crc8(0, (unsigned char *)&rsk,
 					offsetof(struct rollback_space_kernel,
 						 crc8));
 			memcpy(data, &rsk, sizeof(rsk));
diff --git a/include/linux/crc8.h b/include/linux/crc8.h
index b5fd2ac..f7c300a 100644
--- a/include/linux/crc8.h
+++ b/include/linux/crc8.h
@@ -14,10 +14,11 @@
  * This uses an x^8 + x^2 + x + 1 polynomial.  A table-based algorithm would
  * be faster, but for only a few bytes it isn't worth the code size
  *
+ * @crc_start: CRC8 start value
  * @vptr: Buffer to checksum
  * @len: Length of buffer in bytes
  * @return CRC8 checksum
  */
-unsigned int crc8(const unsigned char *vptr, int len);
+unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
 
 #endif
diff --git a/lib/crc8.c b/lib/crc8.c
index 8b68a29..51d540f 100644
--- a/lib/crc8.c
+++ b/lib/crc8.c
@@ -6,20 +6,27 @@
 
 #include "linux/crc8.h"
 
-unsigned int crc8(const unsigned char *vptr, int len)
+#define POLY	(0x1070U << 3)
+
+static unsigned char _crc8(unsigned short data)
 {
-	const unsigned char *data = vptr;
-	unsigned int crc = 0;
-	int i, j;
-
-	for (j = len; j; j--, data++) {
-		crc ^= (*data << 8);
-		for (i = 8; i; i--) {
-			if (crc & 0x8000)
-				crc ^= (0x1070 << 3);
-			crc <<= 1;
-		}
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		if (data & 0x8000)
+			data = data ^ POLY;
+		data = data << 1;
 	}
 
-	return (crc >> 8) & 0xff;
+	return (unsigned char)(data >> 8);
+}
+
+unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		crc = _crc8((crc ^ vptr[i]) << 8);
+
+	return crc;
 }
-- 
cgit v0.10.2


From c09d29057ab0b04db0857d319c6bff74de31b9c3 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Apr 2016 13:53:48 +0200
Subject: arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with
 asm code

v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788

While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.

This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.

Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
 to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.

Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.

This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 45f346c..328c4b1 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -7,7 +7,7 @@
 
 extra-y	:= start.o
 
-obj-y	+= cache_v7.o
+obj-y	+= cache_v7.o cache_v7_asm.o
 
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 94ff488..dd07ba1 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -16,6 +16,10 @@
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+
+/* Asm functions from cache_v7_asm.S */
+void v7_flush_dcache_all(void);
+
 static int check_cache_range(unsigned long start, unsigned long stop)
 {
 	int ok = 1;
@@ -88,34 +92,6 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
 	DSB;
 }
 
-static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
-					       u32 num_ways, u32 way_shift,
-					       u32 log2_line_len)
-{
-	int way, set;
-	u32 setway;
-
-	/*
-	 * For optimal assembly code:
-	 *	a. count down
-	 *	b. have bigger loop inside
-	 */
-	for (way = num_ways - 1; way >= 0 ; way--) {
-		for (set = num_sets - 1; set >= 0; set--) {
-			setway = (level << 1) | (set << log2_line_len) |
-				 (way << way_shift);
-			/*
-			 * Clean & Invalidate data/unified
-			 * cache line by set/way
-			 */
-			asm volatile ("	mcr p15, 0, %0, c7, c14, 2"
-					: : "r" (setway));
-		}
-	}
-	/* DSB to make sure the operation is complete */
-	DSB;
-}
-
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
 {
 	u32 ccsidr;
@@ -142,13 +118,8 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation)
 	log2_num_ways = log_2_n_round_up(num_ways);
 
 	way_shift = (32 - log2_num_ways);
-	if (operation == ARMV7_DCACHE_INVAL_ALL) {
-		v7_inval_dcache_level_setway(level, num_sets, num_ways,
+	v7_inval_dcache_level_setway(level, num_sets, num_ways,
 				      way_shift, log2_line_len);
-	} else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
-		v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
-						   way_shift, log2_line_len);
-	}
 }
 
 static void v7_maint_dcache_all(u32 operation)
@@ -263,7 +234,7 @@ void invalidate_dcache_all(void)
  */
 void flush_dcache_all(void)
 {
-	v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
+	v7_flush_dcache_all();
 
 	v7_outer_cache_flush_all();
 }
diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S
new file mode 100644
index 0000000..2e4629f
--- /dev/null
+++ b/arch/arm/cpu/armv7/cache_v7_asm.S
@@ -0,0 +1,84 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <linux/sizes.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SYS_THUMB_BUILD
+#define ARM(x...)
+#define THUMB(x...)	x
+#else
+#define ARM(x...)	x
+#define THUMB(x...)
+#endif
+
+/*
+ *	v7_flush_dcache_all()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ *	Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(__v7_flush_dcache_all)
+	dmb					@ ensure ordering with previous memory accesses
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	mov	r3, r0, lsr #23			@ move LoC into position
+	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
+	beq	finished			@ if loc is 0, then no need to clean
+start_flush_levels:
+	mov	r10, #0				@ start clean at cache level 0
+flush_levels:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+	and	r1, r1, #7			@ mask of the bits for current cache only
+	cmp	r1, #2				@ see what cache we have at this level
+	blt	skip				@ skip if no cache, or just i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	isb					@ isb to sych the new cssr&csidr
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	movw	r4, #0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+	clz	r5, r4				@ find bit position of way size increment
+	movw	r7, #0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+loop1:
+	mov	r9, r7				@ create working copy of max index
+loop2:
+ ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
+ THUMB(	lsl	r6, r4, r5		)
+ THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
+ ARM(	orr	r11, r11, r9, lsl r2	)	@ factor index number into r11
+ THUMB(	lsl	r6, r9, r2		)
+ THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
+	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
+	subs	r9, r9, #1			@ decrement the index
+	bge	loop2
+	subs	r4, r4, #1			@ decrement the way
+	bge	loop1
+skip:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	flush_levels
+finished:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	dsb	st
+	isb
+	bx	lr
+ENDPROC(__v7_flush_dcache_all)
+
+ENTRY(v7_flush_dcache_all)
+ ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
+	bl	__v7_flush_dcache_all
+ ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
+	bx	lr
+ENDPROC(v7_flush_dcache_all)
diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index dd03ad8..e2bb1fc 100644
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -38,7 +38,7 @@ ENTRY(lowlevel_init)
 	 * to do next is to create a page table and switch over to it.
 	 */
 	bl	create_page_table
-	bl	v7_flush_dcache_all
+	bl	__v7_flush_dcache_all
 
 	/* Disable MMU and Dcache before switching Page Table */
 	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
@@ -140,68 +140,3 @@ ENTRY(create_page_table)
 	str	r0, [r12, #4]		@ mark the second section as Normal
 	mov	pc, lr
 ENDPROC(create_page_table)
-
-/* We don't use Thumb instructions for now */
-#define ARM(x...)	x
-#define THUMB(x...)
-
-/*
- *	v7_flush_dcache_all()
- *
- *	Flush the whole D-cache.
- *
- *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
- *
- *	- mm    - mm_struct describing address space
- *
- *	Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
- */
-ENTRY(v7_flush_dcache_all)
-	dmb					@ ensure ordering with previous memory accesses
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	mov	r3, r0, lsr #23			@ move LoC into position
-	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
-	beq	finished			@ if loc is 0, then no need to clean
-start_flush_levels:
-	mov	r10, #0				@ start clean at cache level 0
-flush_levels:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
-	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
-	and	r1, r1, #7			@ mask of the bits for current cache only
-	cmp	r1, #2				@ see what cache we have at this level
-	blt	skip				@ skip if no cache, or just i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	isb					@ isb to sych the new cssr&csidr
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	movw	r4, #0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
-	clz	r5, r4				@ find bit position of way size increment
-	movw	r7, #0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
-loop1:
-	mov	r9, r7				@ create working copy of max index
-loop2:
- ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
- THUMB(	lsl	r6, r4, r5		)
- THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
- ARM(	orr	r11, r11, r9, lsl r2	)	@ factor index number into r11
- THUMB(	lsl	r6, r9, r2		)
- THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
-	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
-	subs	r9, r9, #1			@ decrement the index
-	bge	loop2
-	subs	r4, r4, #1			@ decrement the way
-	bge	loop1
-skip:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	flush_levels
-finished:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	dsb	st
-	isb
-	mov	pc, lr
-ENDPROC(v7_flush_dcache_all)
-- 
cgit v0.10.2


From df120142f36b6ff8b12187b8860269763b2b3203 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Apr 2016 13:53:49 +0200
Subject: arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm
 code

Lets be consistent and also replace v7_maint_dcache_all()
with asm code for the invalidate case.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index dd07ba1..dc309da 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -10,15 +10,14 @@
 #include <asm/armv7.h>
 #include <asm/utils.h>
 
-#define ARMV7_DCACHE_INVAL_ALL		1
-#define ARMV7_DCACHE_CLEAN_INVAL_ALL	2
-#define ARMV7_DCACHE_INVAL_RANGE	3
-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
+#define ARMV7_DCACHE_INVAL_RANGE	1
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE	2
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 
 /* Asm functions from cache_v7_asm.S */
 void v7_flush_dcache_all(void);
+void v7_invalidate_dcache_all(void);
 
 static int check_cache_range(unsigned long start, unsigned long stop)
 {
@@ -37,18 +36,6 @@ static int check_cache_range(unsigned long start, unsigned long stop)
 	return ok;
 }
 
-/*
- * Write the level and type you want to Cache Size Selection Register(CSSELR)
- * to get size details from Current Cache Size ID Register(CCSIDR)
- */
-static void set_csselr(u32 level, u32 type)
-{
-	u32 csselr = level << 1 | type;
-
-	/* Write to Cache Size Selection Register(CSSELR) */
-	asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
-}
-
 static u32 get_ccsidr(void)
 {
 	u32 ccsidr;
@@ -58,85 +45,6 @@ static u32 get_ccsidr(void)
 	return ccsidr;
 }
 
-static u32 get_clidr(void)
-{
-	u32 clidr;
-
-	/* Read current CP15 Cache Level ID Register */
-	asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
-	return clidr;
-}
-
-static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
-					 u32 num_ways, u32 way_shift,
-					 u32 log2_line_len)
-{
-	int way, set;
-	u32 setway;
-
-	/*
-	 * For optimal assembly code:
-	 *	a. count down
-	 *	b. have bigger loop inside
-	 */
-	for (way = num_ways - 1; way >= 0 ; way--) {
-		for (set = num_sets - 1; set >= 0; set--) {
-			setway = (level << 1) | (set << log2_line_len) |
-				 (way << way_shift);
-			/* Invalidate data/unified cache line by set/way */
-			asm volatile ("	mcr p15, 0, %0, c7, c6, 2"
-					: : "r" (setway));
-		}
-	}
-	/* DSB to make sure the operation is complete */
-	DSB;
-}
-
-static void v7_maint_dcache_level_setway(u32 level, u32 operation)
-{
-	u32 ccsidr;
-	u32 num_sets, num_ways, log2_line_len, log2_num_ways;
-	u32 way_shift;
-
-	set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
-
-	ccsidr = get_ccsidr();
-
-	log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
-				CCSIDR_LINE_SIZE_OFFSET) + 2;
-	/* Converting from words to bytes */
-	log2_line_len += 2;
-
-	num_ways  = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
-			CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
-	num_sets  = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
-			CCSIDR_NUM_SETS_OFFSET) + 1;
-	/*
-	 * According to ARMv7 ARM number of sets and number of ways need
-	 * not be a power of 2
-	 */
-	log2_num_ways = log_2_n_round_up(num_ways);
-
-	way_shift = (32 - log2_num_ways);
-	v7_inval_dcache_level_setway(level, num_sets, num_ways,
-				      way_shift, log2_line_len);
-}
-
-static void v7_maint_dcache_all(u32 operation)
-{
-	u32 level, cache_type, level_start_bit = 0;
-	u32 clidr = get_clidr();
-
-	for (level = 0; level < 7; level++) {
-		cache_type = (clidr >> level_start_bit) & 0x7;
-		if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
-		    (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
-		    (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
-			v7_maint_dcache_level_setway(level, operation);
-		level_start_bit += 3;
-	}
-}
-
 static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
 {
 	u32 mva;
@@ -223,7 +131,7 @@ static void v7_inval_tlb(void)
 
 void invalidate_dcache_all(void)
 {
-	v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+	v7_invalidate_dcache_all();
 
 	v7_outer_cache_inval_all();
 }
diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S
index 2e4629f..a433628 100644
--- a/arch/arm/cpu/armv7/cache_v7_asm.S
+++ b/arch/arm/cpu/armv7/cache_v7_asm.S
@@ -82,3 +82,73 @@ ENTRY(v7_flush_dcache_all)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bx	lr
 ENDPROC(v7_flush_dcache_all)
+
+/*
+ *	v7_invalidate_dcache_all()
+ *
+ *	Invalidate the whole D-cache.
+ *
+ *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ *	Note: copied from __v7_flush_dcache_all above with
+ *	mcr     p15, 0, r11, c7, c14, 2
+ *	Replaced with:
+ *	mcr     p15, 0, r11, c7, c6, 2
+ */
+ENTRY(__v7_invalidate_dcache_all)
+	dmb					@ ensure ordering with previous memory accesses
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	mov	r3, r0, lsr #23			@ move LoC into position
+	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
+	beq	inval_finished			@ if loc is 0, then no need to clean
+	mov	r10, #0				@ start clean at cache level 0
+inval_levels:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+	and	r1, r1, #7			@ mask of the bits for current cache only
+	cmp	r1, #2				@ see what cache we have at this level
+	blt	inval_skip			@ skip if no cache, or just i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	isb					@ isb to sych the new cssr&csidr
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	movw	r4, #0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+	clz	r5, r4				@ find bit position of way size increment
+	movw	r7, #0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+inval_loop1:
+	mov	r9, r7				@ create working copy of max index
+inval_loop2:
+ ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
+ THUMB(	lsl	r6, r4, r5		)
+ THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
+ ARM(	orr	r11, r11, r9, lsl r2	)	@ factor index number into r11
+ THUMB(	lsl	r6, r9, r2		)
+ THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
+	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
+	subs	r9, r9, #1			@ decrement the index
+	bge	inval_loop2
+	subs	r4, r4, #1			@ decrement the way
+	bge	inval_loop1
+inval_skip:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	inval_levels
+inval_finished:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	dsb	st
+	isb
+	bx	lr
+ENDPROC(__v7_invalidate_dcache_all)
+
+ENTRY(v7_invalidate_dcache_all)
+ ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
+	bl	__v7_invalidate_dcache_all
+ ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
+ THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
+	bx	lr
+ENDPROC(v7_invalidate_dcache_all)
-- 
cgit v0.10.2


From 811906aebcb81c14c1a836a5ae97f49f1cc9b7ec Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 11 Apr 2016 15:24:50 +0530
Subject: spl: mmc: raw: Try to load u-boot if Linux image is not found

If CONFIG_SPL_OS_BOOT is enabled and Linux image is not flashed at
RAW_MODE_KERNEL_SECTOR in MMC, spl still assumes that Linux is
available and tries to boot it and hangs. In order to avoid this,
adding a check to verify if parsed image header is of type IH_OS_LINUX.
If it fails then fall back to load u-boot image.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 7d3bfc6..1a10c55 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -178,6 +178,7 @@ static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
 static int mmc_load_image_raw_os(struct mmc *mmc)
 {
 	unsigned long count;
+	int ret;
 
 	count = mmc->block_dev.block_read(&mmc->block_dev,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
@@ -190,8 +191,17 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
 		return -1;
 	}
 
-	return mmc_load_image_raw_sector(mmc,
+	ret = mmc_load_image_raw_sector(mmc,
 		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
+	if (ret)
+		return ret;
+
+	if (spl_image.os != IH_OS_LINUX) {
+		puts("Expected Linux image is not found. Trying to start U-boot\n");
+		return -ENOENT;
+	}
+
+	return 0;
 }
 #else
 int spl_start_uboot(void)
-- 
cgit v0.10.2


From c7529dbad1722bd6d6ef2a0af0e818902a296d64 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 9 Feb 2016 11:19:10 -0800
Subject: fastboot: sparse: fix block addressing for don't care chunk type

When 7bfc3b1 (sparse: Refactor chunk parsing function) was implemented,
it dropped 9981945 (aboot: fix block addressing for don't care chunk type).

This re-implements the required fix for the "don't care chunk type"...

Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/common/image-sparse.c b/common/image-sparse.c
index 2433192..e0d8761 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -331,9 +331,13 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 		 * and go on parsing the rest of the chunks
 		 */
 		if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) {
-			skipped += sparse_block_size_to_storage(chunk_header->chunk_sz,
-								storage,
-								sparse_header);
+			blkcnt = sparse_block_size_to_storage(chunk_header->chunk_sz,
+							      storage,
+							      sparse_header);
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+			total_blocks += blkcnt;
+#endif
+			skipped += blkcnt;
 			continue;
 		}
 
@@ -381,7 +385,7 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 	printf("........ wrote %d blocks to '%s'\n", total_blocks,
 	       storage->name);
 
-	if ((total_blocks + skipped) !=
+	if (total_blocks !=
 	    sparse_block_size_to_storage(sparse_header->total_blks,
 					 storage, sparse_header)) {
 		printf("sparse image write failure\n");
-- 
cgit v0.10.2


From e3793541b15d631476e91343a21c5b23b19c9da8 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 9 Feb 2016 11:19:11 -0800
Subject: fastboot: sparse: remove unnecessary logging

remove logging of the 'skipped' blocks

Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/common/image-sparse.c b/common/image-sparse.c
index e0d8761..2bf737b 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -276,7 +276,6 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 	sparse_buffer_t *buffer;
 	uint32_t start;
 	uint32_t total_blocks = 0;
-	uint32_t skipped = 0;
 	int i;
 
 	debug("=== Storage ===\n");
@@ -337,7 +336,6 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
 			total_blocks += blkcnt;
 #endif
-			skipped += blkcnt;
 			continue;
 		}
 
@@ -378,8 +376,8 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 		sparse_put_data_buffer(buffer);
 	}
 
-	debug("Wrote %d blocks, skipped %d, expected to write %d blocks\n",
-	      total_blocks, skipped,
+	debug("Wrote %d blocks, expected to write %d blocks\n",
+	      total_blocks,
 	      sparse_block_size_to_storage(sparse_header->total_blks,
 					   storage, sparse_header));
 	printf("........ wrote %d blocks to '%s'\n", total_blocks,
-- 
cgit v0.10.2


From bbf8bef196ae52517284a0a2e2ffc94a4ff89f5f Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 11 Apr 2016 22:22:25 -0400
Subject: Prepare v2016.05-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index ea7fd00..c35a277 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
 #
 
 VERSION = 2016
-PATCHLEVEL = 03
+PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From 2c3c3ecb596c3b15b5269c56c5e20f39c2c59102 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 1 Apr 2016 22:39:26 +0200
Subject: sunxi: Add INITIAL_USB_SCAN_DELAY Kconfig option

Some boards have on board usb devices which need longer than the USB
spec's 1 second to connect from board powerup. Add a config option which
when non 0 adds an extra delay before the first usb bus scan.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index b258ce4..f9993d2 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -85,6 +85,8 @@ static struct sunxi_usb_phy {
 #endif
 };
 
+static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
+
 static int get_vbus_gpio(int index)
 {
 	switch (index) {
@@ -269,6 +271,11 @@ void sunxi_usb_phy_power_on(int index)
 {
 	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
 
+	if (initial_usb_scan_delay) {
+		mdelay(initial_usb_scan_delay);
+		initial_usb_scan_delay = 0;
+	}
+
 	phy->power_on_count++;
 	if (phy->power_on_count != 1)
 		return;
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 464fa0f..fa78720 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -312,6 +312,15 @@ config MMC_SUNXI_SLOT_EXTRA
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
 
+config INITIAL_USB_SCAN_DELAY
+	int "delay initial usb scan by x ms to allow builtin devices to init"
+	default 0
+	---help---
+	Some boards have on board usb devices which need longer than the
+	USB spec's 1 second to connect from board powerup. Set this config
+	option to a non 0 value to add an extra delay before the first usb
+	bus scan.
+
 config USB0_VBUS_PIN
 	string "Vbus enable pin for usb0 (otg)"
 	default ""
-- 
cgit v0.10.2


From e6c9cec4ca0f3009858c96d57f05ccab557e8a34 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 1 Apr 2016 12:53:20 +0200
Subject: sunxi: Set DCDC1 to 3.3V on the Sinovoip BPI M3

This is the value used in the fex file of the manufacturer images,
and also the DCDC1 default. Sometimes lower values are used to save
battery power, but that does not apply to a SBC.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index ffb9b7a..3c7f167 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -12,5 +12,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_AXP_DCDC1_VOLT=3000
 CONFIG_AXP_DCDC5_VOLT=1200
-- 
cgit v0.10.2


From b24f7f008d6d29d7fb70d42ef40bb51001f3ab0f Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 1 Apr 2016 12:55:08 +0200
Subject: sunxi: Enable usb ports on the Sinovoip BPI M3

DLDO3 is used to provide Port-D power and PD is used for the
usb-hub / sata-5v enable pins. The 2.5V comes from the schematic
and matches the factory image fex file.

The dts changes are the minimal changes needed for u-boot to
pick-up the usb host controllers. The upstream kernel does not
(yet) have usb host support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts b/arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts
index 91ff3a9..dfc16a0 100644
--- a/arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts
+++ b/arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -57,8 +57,16 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_b>;
 	status = "okay";
 };
+
+&usb_otg {
+	status = "okay";
+};
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 3c7f167..d3fd857 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -5,6 +5,11 @@ CONFIG_DRAM_TYPE=7
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
+CONFIG_INITIAL_USB_SCAN_DELAY=500
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH11"
+CONFIG_USB1_VBUS_PIN="PD24"
 CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -13,3 +18,7 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_AXP_DCDC5_VOLT=1200
+CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
-- 
cgit v0.10.2


From 88bb800ddf80fd301c3201596f174b0a82f1da3b Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 3 Apr 2016 09:41:44 +0200
Subject: sunxi: Enable CMD_GPIO on all sunxi boards

We have CONFIG_CMD_GPIO=y in almost all sunxi boards, but after
its Kconfig conversion it has ended up missing on some recently
added boards.

Simply select it for ARCH_SUNXI, so that we get it on all
sunxi boards for both a consistent user experience and simpler
defconfig files.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f18dbe6..2b899b8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -538,6 +538,7 @@ config TARGET_CM_T43
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
+	select CMD_GPIO
 	select CMD_USB
 	select DM
 	select DM_ETH
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 25b48d9..8cb7ac7 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -12,7 +12,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index cba2cfd..6a0d815 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -13,6 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 45cc5ab..a790856 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -17,6 +17,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 45ec575..37ce923 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -19,7 +19,6 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 419cdfb..cc5858e 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -12,7 +12,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 151a0a3..7b0309c 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -10,7 +10,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 03481f6..9507b87 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -13,6 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 1603b6f..40f8c98 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -15,7 +15,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 67bea5a..fc1be7d 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 82e01ba..8262be5 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -19,5 +19,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 8f1be3e..44f3982 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -11,6 +11,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 434b007..9d5365d 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -9,6 +9,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 6cbb76c..d9b1bd6 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -11,7 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 646cb2a..496c20e 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -13,7 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO4_VOLT=2500
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index f6346de..13a8f32 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index e027a47..1cb010d 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -11,7 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index dedf772..3257aae 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index feaeb98..2ce8cb1 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -21,7 +21,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 2f5e75d..4b9d722 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -10,6 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index a45fbb0..c884115 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -10,5 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 0599472..8c4fcf3 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -15,7 +15,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index d625c21..255f35d 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -18,7 +18,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 5973fbf..5f01760 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -20,5 +20,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 83f2004..02bcdbf 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -13,7 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 45739cd..fef3685 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -18,5 +18,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index fab5f34..90dd734 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -11,6 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index d460c32..d2111c6 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -11,6 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUN
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index ca3b1dd..378abce 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -12,6 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 1f245e7..c3f0421 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -10,6 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 7e2f942..9d8d325 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -10,5 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 32c65fb..49bb26a 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -8,5 +8,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 73fd4e8..5559444 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -13,4 +13,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 11f3203..3d71bf5 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 806fb64..cef9794 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -8,6 +8,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index 6127098..b3f825e 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -11,7 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 93707e4..f076e30 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -10,5 +10,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index bfe2a29..eccf372 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -11,7 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 0ed5da1..d72dcc0 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -13,6 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index fdb5ba4..0d1ba15 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -12,6 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index da76226..f0b4384 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -11,7 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 1eb8094..53e023a 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -11,4 +11,3 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 8013359..53f9bfe 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -9,6 +9,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 330ee47..00c671b 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -14,6 +14,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 4156c35..a865255 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -16,6 +16,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 20d3f93..013c35e 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -9,4 +9,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index a5f8e6a..181e1e2 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -11,7 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index dc71dde..d36a5dc 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -23,6 +23,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index a01b4c1..5f3d624 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -16,6 +16,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index c3ceedb..bfc8cba 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -15,6 +15,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index eb1b531..fc43cc5 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -10,5 +10,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index cdde2bc..65c1d8e 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -22,5 +22,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 26f5923..958104e 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -19,6 +19,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index ce4a584..1cfb380 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -13,6 +13,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 5958d334..ae67c37 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO2_VOLT=1800
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 8fc6532..c76af0e 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -19,5 +19,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 029ca89..242158e 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -18,5 +18,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 09ad330..34e74af 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -21,7 +21,6 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index a8d339c..a14de0d 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index a15a15a..54fa819 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -10,6 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 3f1624c..7ec54a7 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 6c4cd56..5e68769 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 00e1458..3dea793 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -16,5 +16,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 1c68293..a8b32cb 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -17,6 +17,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a7b3a9f..0b03e16 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -16,5 +16,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index c0c6cb2..27b5019 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -19,5 +19,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 0a17cf7..153450f 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -16,5 +16,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 443a1c7..9cb8b1d 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -11,6 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 07865d8..ce81309 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -12,7 +12,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 03e58cd..720aefa 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -10,6 +10,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 922f8c3..d38bc7f 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -9,6 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index 2a359be..de1b73f 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -7,5 +7,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index ff9ac09..2a32e04 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -12,7 +12,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB1_VBUS_PIN="PG13"
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 4e9051d..8d78b47 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -11,7 +11,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB1_VBUS_PIN=""
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index ff124bd..e96a273 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -13,7 +13,6 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB1_VBUS_PIN="PG13"
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index c37d378..45bf9b3 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -9,4 +9,3 @@ CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 019f6da..04c99b9 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index d9b3b45..9aa5280 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -17,5 +17,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 205359e..b467b62 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -19,5 +19,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 927ab2a..7391464 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 755f4ee..16f8600 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index a8dfa0d..6378918 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -20,6 +20,5 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index d6387fc..9d9d4bf 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -9,6 +9,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index d3de194..6d39dec 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -14,5 +14,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
 CONFIG_USB_EHCI_HCD=y
-- 
cgit v0.10.2


From fb3bfbb24a72a495f3fb1716d386fb4bbe5990fa Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Apr 2016 15:00:52 +0200
Subject: sunxi: H3: Do not clear usb companion clk-gate / reset on remove

On the H3 we need to enable the clk and de-assert the reset of the
companion to be able to talk to the actual usb host controller.

Before this commit we were also disabling the companion clk-gate /
asserting its reset on remove, causing the later remove callback of
the companion itself to (sometimes) fail with:

ERROR: USB HC reset timed out!

This commit fixes this by not disabling the companion's clk-gate nor
asserting its reset on remove.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index d5eb492..f2d83e3 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -38,6 +38,7 @@ static int ehci_usb_probe(struct udevice *dev)
 	struct ehci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
 	struct ehci_hcor *hcor;
+	int extra_ahb_gate_mask = 0;
 
 	/*
 	 * This should go away once we've moved to the driver model for
@@ -45,15 +46,18 @@ static int ehci_usb_probe(struct udevice *dev)
 	 */
 	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #ifdef CONFIG_MACH_SUN8I_H3
-	priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
+	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 #endif
 	priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
 	priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
 	priv->phy_index++; /* Non otg phys start at 1 */
 
-	setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+	setbits_le32(&ccm->ahb_gate0,
+		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
+	setbits_le32(&ccm->ahb_reset0_cfg,
+		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 #endif
 
 	sunxi_usb_phy_init(priv->phy_index);
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 6f3f4ce..2a1e8bf 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -38,6 +38,7 @@ static int ohci_usb_probe(struct udevice *dev)
 	struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
+	int extra_ahb_gate_mask = 0;
 
 	bus_priv->companion = true;
 
@@ -47,18 +48,21 @@ static int ohci_usb_probe(struct udevice *dev)
 	 */
 	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 #ifdef CONFIG_MACH_SUN8I_H3
-	priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
+	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
 	priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
 	priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
 	priv->usb_gate_mask <<= priv->phy_index;
 	priv->phy_index++; /* Non otg phys start at 1 */
 
-	setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+	setbits_le32(&ccm->ahb_gate0,
+		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 	setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
+	setbits_le32(&ccm->ahb_reset0_cfg,
+		     priv->ahb_gate_mask | extra_ahb_gate_mask);
 #endif
 
 	sunxi_usb_phy_init(priv->phy_index);
-- 
cgit v0.10.2


From ec770dba89533ca49b1bdc7d2c49c2d01fcdf406 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Apr 2016 15:02:24 +0200
Subject: sunxi: Add defconfig and dts file for Orange Pi One SBC

The Orange Pi One SBC, is a stripped down version of the popular
Orange Pi PC. The one is a H3 based SBC, with 512M of RAM,
micro-sd slot, 1 host usb, 1 otg usb, hdmi and 100Mbit ethernet.

The dts is identical to the dts submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 01cf030..0915e05 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -207,6 +207,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-sinovoip-bpi-m3.dtb
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-2.dtb \
+	sun8i-h3-orangepi-one.dtb \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts
new file mode 100644
index 0000000..0adf932
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi One";
+	compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+		pwr_led {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		status_led {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	r_gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sw_r_opc>;
+
+		sw4 {
+			label = "sw4";
+			linux,code = <BTN_0>;
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pio {
+	leds_opc: led_pins@0 {
+		allwinner,pins = "PA15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	leds_r_opc: led_pins@0 {
+		allwinner,pins = "PL10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	sw_r_opc: key_pins@0 {
+		allwinner,pins = "PL3";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	/* USB VBUS is always on */
+	status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 430d770..2cb8a75 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -55,6 +55,7 @@ F:	include/configs/sun8i.h
 F:	configs/ga10h_v1_1_defconfig
 F:	configs/gt90h_v4_defconfig
 F:	configs/orangepi_2_defconfig
+F:	configs/orangepi_one_defconfig
 F:	configs/orangepi_pc_defconfig
 F:	configs/orangepi_plus_defconfig
 F:	configs/polaroid_mid2809pxe04_defconfig
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
new file mode 100644
index 0000000..207189a
--- /dev/null
+++ b/configs/orangepi_one_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
-- 
cgit v0.10.2


From b23005cec3b23a4ac8f7336a427febdddc6451e7 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 7 Apr 2016 07:41:00 +0200
Subject: gpio: mvebu_gpio: Add missing out value set to
 gpio_direction_output()

This patch adds the missing configuration of the output value to the
gpio_direction_output() function. Without this, calling
gpio_direction_output() does not set the out-value at all and only
configures the gpio as output.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Reviewed-by: Kevin Smith <kevin.smith@elecsyscorp.com>

diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c
index 9564ce2..75dc73e 100644
--- a/drivers/gpio/mvebu_gpio.c
+++ b/drivers/gpio/mvebu_gpio.c
@@ -43,6 +43,10 @@ static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio,
 	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
 	struct mvebu_gpio_regs *regs = priv->regs;
 
+	if (value)
+		setbits_le32(&regs->data_out, BIT(gpio));
+	else
+		clrbits_le32(&regs->data_out, BIT(gpio));
 	clrbits_le32(&regs->io_conf, BIT(gpio));
 
 	return 0;
-- 
cgit v0.10.2


From ced0d849d8c9614981961ca028207acdcfa2b39c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 7 Apr 2016 10:48:13 +0200
Subject: arm: mvebu: theadorable: Add USB power toggle and tweak USB PHY
 register

This patch adds an USB power toggle for theadorable. Additionally, the
USB PHY RX Channel Control 0 Register is changed to fix some issues
noticed while accessing some specific USB sticks.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index ee88a98..0756f18 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
@@ -19,6 +20,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
+#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
+	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
+
 #define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
 #define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
 #define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))
@@ -27,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
 #define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000
 
+#define GPIO_USB0_PWR_ON		18
+#define GPIO_USB1_PWR_ON		19
+
 /* DDR3 static configuration */
 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
 	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
@@ -135,6 +143,8 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	int ret;
+
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
@@ -147,6 +157,28 @@ int board_init(void)
 	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
 			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
 
+	/*
+	 * Set RX Channel Control 0 Register:
+	 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
+	 * to 3 (1/1) results in a more stable USB connection.
+	 */
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
+
+	/* Toggle USB power */
+	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
+	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
+	mdelay(1);
+	gpio_set_value(GPIO_USB0_PWR_ON, 1);
+	gpio_set_value(GPIO_USB1_PWR_ON, 1);
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From 28226b9a2ccdc8181d1887e03e9fc7501b885e40 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 7 Apr 2016 10:48:14 +0200
Subject: arm: mvebu: theadorable: Add bootcounter support

This patch adds bootcount support to the MVEBU theadorable board. Since
no reset-safe registers seem to be available, it uses the last 4KiB
of SDRAM for the bootcounter location.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index a4bcf21..20a44c9 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -120,6 +120,14 @@
 #define CONFIG_FPGA_STRATIX_V
 
 /*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_RAM
+/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
+#define BOOTCOUNT_ADDR			0x1000
+
+/*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
  */
-- 
cgit v0.10.2


From d9cb860d30077479b52eb22eedcb7b0b52dafca6 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 8 Apr 2016 15:58:28 +0200
Subject: arm: mvebu: Add base address for 2nd I2C controller

Add MVEBU_TWSI1_BASE define so that the 2nd I2C controller on e.g. AXP
can be used.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a12be2a..13c9f29 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -55,6 +55,7 @@
 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
 #define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
-- 
cgit v0.10.2


From 8ac71da94d63368136baf352e543ba9790db2610 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 8 Apr 2016 15:58:29 +0200
Subject: arm: mvebu: theadorable: Enable 2nd I2C controller

This patch enables the 2nd I2C controller on the Armada XP theadorable
board.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 20a44c9..05a248e 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -51,6 +51,7 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 
-- 
cgit v0.10.2


From 169a85501715d39f8a4af810e51df1300920fae9 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 8 Apr 2016 15:58:30 +0200
Subject: arm: mvebu: theadorable: Add PEX-switch detection and reset code

Sometimes the PCIe link for the PEX-switch will not come-up. In this case,
the board is not in a usable state. This patch makes sure that in this
case a soft-reset is issued. If this soft-reset does not result in the
PEX-switch being detected after some soft-reset cycles, an I2C message
is sent to the uC to issue a complete power-cycle of the board.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index 0756f18..b8b0148 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -5,10 +5,13 @@
  */
 
 #include <common.h>
+#include <i2c.h>
+#include <pci.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <linux/crc8.h>
 #include <linux/mbus.h>
 #ifdef CONFIG_NET
 #include <netdev.h>
@@ -35,6 +38,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_USB0_PWR_ON		18
 #define GPIO_USB1_PWR_ON		19
 
+#define PEX_SWITCH_NOT_FOUNT_LIMIT	3
+
+#define STM_I2C_BUS	1
+#define STM_I2C_ADDR	0x27
+#define REBOOT_DELAY	1000		/* reboot-delay in ms */
+
 /* DDR3 static configuration */
 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
 	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
@@ -214,3 +223,63 @@ int board_video_init(void)
 
 	return mvebu_lcd_register_init(&lcd_info);
 }
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	pci_dev_t bdf;
+	ulong bootcount;
+
+	/*
+	 * Check if the PEX switch is detected (somtimes its not available
+	 * on the PCIe bus). In this case, try to recover by issuing a
+	 * soft-reset or even a power-cycle, depending on the bootcounter
+	 * value.
+	 */
+	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
+	if (bdf == -1) {
+		u8 i2c_buf[8];
+		int ret;
+
+		/* PEX switch not found! */
+		bootcount = bootcount_load();
+		printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
+		       bootcount);
+		if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
+			printf("Issuing power-switch via uC!\n");
+
+			printf("Issuing power-switch via uC!\n");
+			i2c_set_bus_num(STM_I2C_BUS);
+			i2c_buf[0] = STM_I2C_ADDR << 1;
+			i2c_buf[1] = 0xc5;	/* cmd */
+			i2c_buf[2] = 0x01;	/* enable */
+			/* Delay before reboot */
+			i2c_buf[3] = REBOOT_DELAY & 0x00ff;
+			i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
+			/* Delay before shutdown */
+			i2c_buf[5] = 0x00;
+			i2c_buf[6] = 0x00;
+			i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
+
+			ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
+			if (ret) {
+				printf("I2C write error (ret=%d)\n", ret);
+				printf("Issuing soft-reset...\n");
+				/* default handling: SOFT reset */
+				do_reset(NULL, 0, 0, NULL);
+			}
+
+			/* Wait for power-cycle to occur... */
+			printf("Waiting for power-cycle via uC...\n");
+			while (1)
+				;
+		} else {
+			printf("Issuing soft-reset...\n");
+			/* default handling: SOFT reset */
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 05a248e..5864f27 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -104,6 +104,7 @@
 #define CONFIG_PCI
 #define CONFIG_PCI_MVEBU
 #define CONFIG_PCI_PNP
+#define CONFIG_BOARD_LATE_INIT		/* for PEX switch test */
 #endif
 #endif
 
-- 
cgit v0.10.2


From aca84a214d70953505d56b7c9717d1a7c019902c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 8 Apr 2016 16:09:39 +0200
Subject: arm: mvebu: theadorable: Remove Board name output in checkboard

This line is not needed, as the board supports DT based probing. And
here the "Model:" is already printed:

Model: Marvell Armada XP theadorable
Board: theadorable

One line for the board name is enough.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index b8b0148..c1db289 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -193,8 +193,6 @@ int board_init(void)
 
 int checkboard(void)
 {
-	puts("Board: theadorable\n");
-
 	board_fpga_add();
 
 	return 0;
-- 
cgit v0.10.2


From 7570a0cc7524ed5818b92a35f00a3fd10b33bc65 Mon Sep 17 00:00:00 2001
From: Rouven Behr <u-boot@behr-iss.de>
Date: Sun, 10 Apr 2016 13:38:13 +0200
Subject: mtd: cfi: Unlock current sector instead of sector 0 before buffered
 write

Unlock current sector instead of sector 0 before buffered write.

[Patch subject and commit text slightly reworded, Stefan]

Signed-off-by: Rouven Behr <u-boot@behr-iss.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 18831c6..8ccaff0 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -979,7 +979,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 
 	case CFI_CMDSET_AMD_STANDARD:
 	case CFI_CMDSET_AMD_EXTENDED:
-		flash_unlock_seq(info,0);
+		flash_unlock_seq(info, sector);
 
 #ifdef CONFIG_FLASH_SPANSION_S29WS_N
 		offset = ((unsigned long)dst - info->start[sector]) >> shift;
-- 
cgit v0.10.2


From 58fab4cd9ceb9556eaa7c18a2390b321c35d05aa Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 10:54:08 +0200
Subject: ARM: zynq: Add interrupt-controller property to gpio nodes

GPIO driver supports an input interrupt that's why gpio node itself can
be labeled as interrupt controller.

Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 2d786f0..a352bc8 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -96,8 +96,10 @@
 		gpio0: gpio@e000a000 {
 			compatible = "xlnx,zynq-gpio-1.0";
 			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
 			clocks = <&clkc 42>;
 			gpio-controller;
+			interrupt-controller;
 			interrupt-parent = <&intc>;
 			interrupts = <0 20 4>;
 			reg = <0xe000a000 0x1000>;
-- 
cgit v0.10.2


From 4c987271b388cb14a57a1bbc7068b18eebf7967a Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Thu, 30 Jul 2015 18:13:55 -0700
Subject: ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset
 controller.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a352bc8..55eae61 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -272,6 +272,13 @@
 				reg = <0x100 0x100>;
 			};
 
+			rstc: rstc@200 {
+				compatible = "xlnx,zynq-reset";
+				reg = <0x200 0x48>;
+				#reset-cells = <1>;
+				syscon = <&slcr>;
+			};
+
 			pinctrl0: pinctrl@700 {
 				compatible = "xlnx,pinctrl-zynq";
 				reg = <0x700 0x200>;
-- 
cgit v0.10.2


From 20fe3f1791fa836de8c0e9991dde40362350b1a0 Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Mon, 22 Jun 2015 23:18:44 -0700
Subject: ARM: dts: Updated devicetree bindings for Zynq 7000 platform

Added addtional bindings required for FPGA Manager operation
of the Xilinx Zynq Devc configuration interface.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 55eae61..aff65f2 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -307,6 +307,7 @@
 		devcfg: devcfg@f8007000 {
 			compatible = "xlnx,zynq-devcfg-1.0";
 			reg = <0xf8007000 0x100>;
+			syscon = <&slcr>;
 		};
 
 		global_timer: timer@f8f00200 {
-- 
cgit v0.10.2


From 77bb73decb2bdf948a8a5f98273a7504c452baee Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 11:00:37 +0200
Subject: ARM: zynq: Align devcfg node

- Have compatible string as the first property
- Sync with Linux kernel dtsi
- Add missing interrupt properties

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index aff65f2..a327557 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -306,7 +306,11 @@
 
 		devcfg: devcfg@f8007000 {
 			compatible = "xlnx,zynq-devcfg-1.0";
+			interrupt-parent = <&intc>;
+			interrupts = <0 8 4>;
 			reg = <0xf8007000 0x100>;
+			clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
+			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
 			syscon = <&slcr>;
 		};
 
-- 
cgit v0.10.2


From 936bbc5d161923283135dcc84e6af1fcd31f848a Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 11:15:00 +0200
Subject: ARM: zynq: Fix bootargs in board dtsi

- Sync with Linux kernel
- Remove rootfs
- Remove earlyprintk

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 528cd27..eba7037 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -27,7 +27,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 1610520..bf996ad 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -27,7 +27,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index b6982c0..6dc7c89 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -21,7 +21,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 4fed221..858d0e2 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -18,7 +18,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 8d69f0e..6cab832 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -20,7 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 77fdfcc..40a3601 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -20,7 +20,7 @@
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram rw earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index ec9b2f7..b262d83 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -26,7 +26,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index d04e962..acc6e42 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -26,7 +26,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "";
 		stdout-path = "serial0:115200n8";
 	};
 
-- 
cgit v0.10.2


From c9132b1e4489b394a87555d17c059b4d681ed0cf Mon Sep 17 00:00:00 2001
From: Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>
Date: Wed, 3 Feb 2016 15:27:18 +0530
Subject: ARM: zynq: DT: Add ethernet phy reset information

Added phy reset gpio information for gem0.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index eba7037..ee050aa 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -91,6 +91,8 @@
 	phy-handle = <&ethernet_phy>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem0_default>;
+	phy-reset-gpio = <&gpio0 11 0>;
+	phy-reset-active-low;
 
 	ethernet_phy: ethernet-phy@7 {
 		reg = <7>;
-- 
cgit v0.10.2


From 169050e4f59000c5c169bbf3855d8c013b161a6b Mon Sep 17 00:00:00 2001
From: Christian Kohn <christian.kohn@xilinx.com>
Date: Thu, 12 Nov 2015 15:53:35 -0800
Subject: ARM: zynq: zc702: Add adv7511 on i2c bus

Add bindings for adv7511.

Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index ee050aa..8ad1db2 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -130,6 +130,21 @@
 			};
 		};
 
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			adv7511: hdmi-tx@39 {
+				compatible = "adi,adv7511";
+				reg = <0x39>;
+				adi,input-depth = <8>;
+				adi,input-colorspace = "yuv422";
+				adi,input-clock = "1x";
+				adi,input-style = <3>;
+				adi,input-justification = "right";
+			};
+		};
+
 		i2c@2 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
cgit v0.10.2


From ac2c40749037acbeafcc5329194e6776450e870b Mon Sep 17 00:00:00 2001
From: Christian Kohn <christian.kohn@xilinx.com>
Date: Thu, 12 Nov 2015 15:53:36 -0800
Subject: ARM: zynq: zc706: Add adv7511 on i2c bus

Add missing adv7511 and configure to match Base TRD.

Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Reviewed-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index bf996ad..cefee25 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -84,6 +84,21 @@
 			};
 		};
 
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			adv7511: hdmi-tx@39 {
+				compatible = "adi,adv7511";
+				reg = <0x39>;
+				adi,input-depth = <8>;
+				adi,input-colorspace = "yuv422";
+				adi,input-clock = "1x";
+				adi,input-style = <3>;
+				adi,input-justification = "evenly";
+			};
+		};
+
 		i2c@2 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
cgit v0.10.2


From a95d54b49074985e2429f2af42c6d746c63285c0 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 13:04:15 +0200
Subject: ARM: zynq: Align spi and qspi node locations

Keep nodes alphabelitally sorted.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Nathan Rossi <nathan@nathanrossi.com>

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 8ad1db2..6585010 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -387,6 +387,11 @@
 	};
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
@@ -401,11 +406,6 @@
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
 &usb0 {
 	status = "okay";
 	dr_mode = "host";
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index cefee25..d04880a 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -306,6 +306,11 @@
 	};
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
 &sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
@@ -320,11 +325,6 @@
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
-&qspi {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
 &usb0 {
 	status = "okay";
 	dr_mode = "host";
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 6dc7c89..33524cb 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -36,27 +36,6 @@
 	};
 };
 
-&spi1 {
-	status = "okay";
-	num-cs = <4>;
-	is-decoded-cs = <0>;
-	flash@0 {
-		compatible = "sst25wf080";
-		reg = <1>;
-		spi-max-frequency = <1000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@test {
-			label = "spi-flash";
-			reg = <0x0 0x100000>;
-		};
-	};
-};
-
-&qspi {
-	status = "okay";
-};
-
 &can0 {
 	status = "okay";
 };
@@ -82,10 +61,31 @@
 
 };
 
+&qspi {
+	status = "okay";
+};
+
 &sdhci0 {
 	status = "okay";
 };
 
+&spi1 {
+	status = "okay";
+	num-cs = <4>;
+	is-decoded-cs = <0>;
+	flash@0 {
+		compatible = "sst25wf080";
+		reg = <1>;
+		spi-max-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@test {
+			label = "spi-flash";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
 &uart1 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index b262d83..4363a4f 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -50,17 +50,17 @@
 	};
 };
 
-&sdhci0 {
+&qspi {
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
-&uart1 {
+&sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
-&qspi {
+&uart1 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index acc6e42..f32923f 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -51,17 +51,17 @@
 	};
 };
 
-&sdhci0 {
+&qspi {
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
-&uart1 {
+&sdhci0 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 
-&qspi {
+&uart1 {
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
-- 
cgit v0.10.2


From b347c14426d63f7172c870b10af3db35760ae280 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 15:24:08 +0200
Subject: ARM: zynq: Create empty line below headers

Sync with others zynq DTS files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index 858d0e2..463b14b 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -7,6 +7,7 @@
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
+
 / {
 	compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
 	model = "Xilinx Zynq";
-- 
cgit v0.10.2


From 74720dc39532d743b24a1ddd6ead94b66d0a29b0 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 13:08:35 +0200
Subject: ARM: zynq: Add missing qspi for xm013

Add missing qspi node and make qspi as spi0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 40a3601..d5bb4ef 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -16,7 +16,8 @@
 		ethernet0 = &gem1;
 		i2c0 = &i2c1;
 		serial0 = &uart0;
-		spi0 = &spi0;
+		spi0 = &qspi;
+		spi1 = &spi0;
 	};
 
 	chosen {
@@ -58,6 +59,10 @@
 	};
 };
 
+&qspi {
+	status = "okay";
+};
+
 &spi0 {
 	status = "okay";
 	num-cs = <4>;
-- 
cgit v0.10.2


From 371fc580d244aa81dd315c3bf16bca6c3607cae6 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 12 Jan 2016 08:06:36 +0100
Subject: ARM: zynq: Extend microzed board support

Add missing DT nodes and enable USB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Nathan Rossi <nathan@nathanrossi.com>

diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index 793ab44..cb238cd 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -1,7 +1,7 @@
 /*
  * Xilinx MicroZED board DTS
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2016 Xilinx, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -15,12 +15,27 @@
 	aliases {
 		serial0 = &uart1;
 		spi0 = &qspi;
+		mmc0 = &sdhci0;
 	};
 
 	memory {
 		device_type = "memory";
 		reg = <0 0x40000000>;
 	};
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
 };
 
 &qspi {
@@ -32,3 +47,24 @@
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 1d70e43..bd261c1 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -21,3 +21,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
index e66088d..ec7bb1c 100644
--- a/include/configs/zynq_microzed.h
+++ b/include/configs/zynq_microzed.h
@@ -12,6 +12,8 @@
 
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_ZYNQ_USB
+
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_MICROZED_H */
-- 
cgit v0.10.2


From a195ed335978d31121c4c41d1164ffab62abad49 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 14:42:53 +0200
Subject: ARM: zynq: Fix usb phy node for Zybo

Compatible property should be the first.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index f32923f..f8dcf1d 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -31,8 +31,8 @@
 	};
 
 	usb_phy0: phy0 {
-		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 		reset-gpios = <&gpio0 46 1>;
 	};
 };
-- 
cgit v0.10.2


From c1584e2a2190756d73d1f96e0e431da30870d208 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 1 Apr 2016 16:04:14 +0200
Subject: ARM: zynq: Use memory initialization based on DTS file

Remove hardcoded memory sizes. Use information from DT memory node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index d8e3fa4..aac1e2b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -278,14 +278,14 @@
 #define CONFIG_SYS_TEXT_BASE		0x4000000
 
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_SDRAM_BASE		0
 
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		0x1000
 
 #define CONFIG_SYS_MALLOC_LEN		0x1400000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
-- 
cgit v0.10.2


From 758f29d0f805ccd6ca1354a9562dab3bacf52310 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 1 Apr 2016 15:56:33 +0200
Subject: ARM: zynq: Support systems with more memory banks

This is example how to change u-boot to support more memory banks read
from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 4c20450..183f642 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 	return 0;
 }
 
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+			       const u32 *cell, int n)
+{
+	int i = 0, b, banks;
+	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+	int address_cells = fdt_address_cells(fdt, parent_offset);
+	int size_cells = fdt_size_cells(fdt, parent_offset);
+	char *p = buf;
+	u64 val;
+	u64 vals;
+
+	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+	      __func__, address_cells, size_cells, buf, cell);
+
+	/* Check memory bank setup */
+	banks = n % (address_cells + size_cells);
+	if (banks)
+		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+		      n, address_cells, size_cells);
+
+	banks = n / (address_cells + size_cells);
+
+	for (b = 0; b < banks; b++) {
+		debug("%s: Bank #%d:\n", __func__, b);
+		if (address_cells == 2) {
+			val = cell[i + 1];
+			val <<= 32;
+			val |= cell[i];
+			val = fdt64_to_cpu(val);
+			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+			      __func__, val, p, &cell[i]);
+			*(phys_addr_t *)p = val;
+		} else {
+			debug("%s: addr32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_addr_t);
+		i += address_cells;
+
+		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+		      sizeof(phys_addr_t));
+
+		if (size_cells == 2) {
+			vals = cell[i + 1];
+			vals <<= 32;
+			vals |= cell[i];
+			vals = fdt64_to_cpu(vals);
+
+			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+			      __func__, vals, p, &cell[i]);
+			*(phys_size_t *)p = vals;
+		} else {
+			debug("%s: size32=%x, ptr=%p\n",
+			      __func__, fdt32_to_cpu(cell[i]), p);
+			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+		}
+		p += sizeof(phys_size_t);
+		i += size_cells;
+
+		debug("%s: ps=%p, i=%x, size=%zu\n",
+		      __func__, p, i, sizeof(phys_size_t));
+	}
+
+	/* Return the first address size */
+	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+	int bank;
+
+	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		debug("Bank #%d: start %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].start);
+		debug("Bank #%d: size %llx\n", bank,
+		      (unsigned long long)gd->bd->bi_dram[bank].size);
+	}
+}
+
 int dram_init(void)
 {
-	int node;
-	fdt_addr_t addr;
-	fdt_size_t size;
+	int node, len;
 	const void *blob = gd->fdt_blob;
+	const u32 *cell;
 
-	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
-					     "memory", 7);
-	if (node == -FDT_ERR_NOTFOUND) {
-		debug("ZYNQ DRAM: Can't get memory node\n");
-		return -1;
+	memset(&tmp, 0, sizeof(tmp));
+
+	/* find or create "/memory" node. */
+	node = fdt_subnode_offset(blob, 0, "memory");
+	if (node < 0) {
+		printf("%s: Can't get memory node\n", __func__);
+		return node;
 	}
-	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
-	if (addr == FDT_ADDR_T_NONE || size == 0) {
-		debug("ZYNQ DRAM: Can't get base address or size\n");
+
+	/* Get pointer to cells and lenght of it */
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell) {
+		printf("%s: Can't get reg property\n", __func__);
 		return -1;
 	}
-	gd->ram_size = size;
+
+	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
 	zynq_ddrc_init();
 
 	return 0;
 }
+#endif
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index aac1e2b..2d941a7 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -277,7 +277,9 @@
 /* Physical Memory map */
 #define CONFIG_SYS_TEXT_BASE		0x4000000
 
-#define CONFIG_NR_DRAM_BANKS		1
+#ifndef CONFIG_NR_DRAM_BANKS
+# define CONFIG_NR_DRAM_BANKS		1
+#endif
 
 #define CONFIG_SYS_MEMTEST_START	0
 #define CONFIG_SYS_MEMTEST_END		0x1000
-- 
cgit v0.10.2


From 1e8d3830f38e7782bf7ece63003beea29a1d1cab Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 18:55:11 +0200
Subject: ARM: zynq: Do not perform reset at the end of thor

Setup reset off for lthor.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 2d941a7..c96b9c5 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -114,6 +114,7 @@
 # define CONFIG_USB_CABLE_CHECK
 # define CONFIG_CMD_DFU
 # define CONFIG_CMD_THOR_DOWNLOAD
+# define CONFIG_THOR_RESET_OFF
 # define CONFIG_USB_FUNCTION_THOR
 # define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
-- 
cgit v0.10.2


From 407b76f9704f9e01d1a5c0fb4c28dd81992019ec Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Mon, 2 Nov 2015 19:45:35 +0530
Subject: ARM64: zynqmp: Move kernel and fdt offsets and sizes to board config
 file

Move kernel and fdt offsets and sizes to board config file
as the flash size varies across boards

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 8cea610..a603255 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -165,8 +165,7 @@
 	"kernel_addr=0x80000\0" \
 	"fdt_addr=0x7000000\0" \
 	"fdt_high=0x10000000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
+	CONFIG_KERNEL_FDT_OFST_SIZE \
 	"sdbootdev=0\0"\
 	"sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
 		"load mmc $sdbootdev:$partid $kernel_addr Image && " \
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index aa58b62..4a83eee 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -24,6 +24,13 @@
 
 #define COUNTER_FREQUENCY	4000000
 
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+	"kernel_offset=0x400000\0" \
+	"fdt_offset=0x2400000\0" \
+	"kernel_size=0x2000000\0" \
+	"fdt_size=0x80000\0" \
+	"board=ep108\0"
+
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_EP_H */
-- 
cgit v0.10.2


From 02e782c6cdc74928b021282aea4273ceba5c9f4b Mon Sep 17 00:00:00 2001
From: Alistair Francis <alistair.francis@xilinx.com>
Date: Thu, 25 Feb 2016 09:30:03 -0800
Subject: ARM64: zynqmp: Use C pre-processor for includes in dts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change the dtsi include code to use the C pre-processor #include instead
of the device tree /include/. This brings all ZynqMP device trees inline
with each other.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index 754604e..d952de1 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -10,8 +10,8 @@
 
 /dts-v1/;
 
-/include/ "zynqmp.dtsi"
-/include/ "zynqmp-ep108-clk.dtsi"
+#include "zynqmp.dtsi"
+#include "zynqmp-ep108-clk.dtsi"
 
 / {
 	model = "ZynqMP EP108";
-- 
cgit v0.10.2


From beaf7955b7fbac721fb7428109fbdcb400f18daa Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 23 Feb 2016 09:30:15 +0100
Subject: ARM64: zynqmp: Add missing mmc aliases

Add missing mmc aliases.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index d952de1..f34555a 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -17,6 +17,8 @@
 	model = "ZynqMP EP108";
 
 	aliases {
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
 		serial0 = &uart0;
 		spi0 = &qspi;
 		spi1 = &spi0;
-- 
cgit v0.10.2


From eaae2b5d0cf87bb6d1ec61288331a0a6e5853e27 Mon Sep 17 00:00:00 2001
From: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Date: Wed, 2 Dec 2015 10:06:58 +0530
Subject: ARM64: zynqmp: dt: Change qspi node compatible string

This patch makes compatible string as "m25p80" for qspi node in
ep108 device tree file

Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index f34555a..b6d30e8 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -74,7 +74,7 @@
 &qspi {
 	status = "okay";
 	flash@0 {
-		compatible = "n25q512a11";
+		compatible = "m25p80";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-- 
cgit v0.10.2


From b8bf55399273a7aba597b5687ef2180ec1d24122 Mon Sep 17 00:00:00 2001
From: P L Sai Krishna <lakshmi.sai.krishna.potthuri@xilinx.com>
Date: Thu, 7 Jan 2016 14:57:27 +0530
Subject: ARM64: zynqmp: Add 8-bit bus width property.

This patch add 8-bit bus width property to eMMC node.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index b6d30e8..ee9d0fe 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -107,6 +107,7 @@
 
 &sdhci0 {
 	status = "okay";
+	bus-width = <8>;
 };
 
 &sdhci1 {
-- 
cgit v0.10.2


From 88a85aac9fe71b5fdcd2bba4ee38829bdc53e4cc Mon Sep 17 00:00:00 2001
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Date: Thu, 26 Nov 2015 14:12:19 +0100
Subject: ARM64: zynqmp: Correct IRQ nr for the SMMU

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 8733604..4cfecec 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -454,11 +454,11 @@
 			reg = <0x0 0xfd800000 0x20000>;
 			#global-interrupts = <1>;
 			interrupt-parent = <&gic>;
-			interrupts = <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
-				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
+			interrupts = <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
+				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 		};
 
 		spi0: spi@ff040000 {
-- 
cgit v0.10.2


From 7f1d7d974bf6a969447212c2c9bc65d77dcf7d67 Mon Sep 17 00:00:00 2001
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Date: Thu, 26 Nov 2015 14:12:20 +0100
Subject: ARM64: zynqmp: Hook up the GEMs to the SMMU

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 4cfecec..66abe6f 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -310,6 +310,7 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
 			jumbo-max-len = <10240>;
 			jumbo-supported;
 		};
@@ -323,6 +324,7 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
 			jumbo-max-len = <10240>;
 			jumbo-supported;
 		};
@@ -336,6 +338,7 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
 			jumbo-max-len = <10240>;
 			jumbo-supported;
 		};
@@ -349,6 +352,7 @@
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
 			jumbo-max-len = <10240>;
 			jumbo-supported;
 		};
@@ -459,6 +463,10 @@
 				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
+			mmu-masters = < &gem0 0x874
+					&gem1 0x875
+					&gem2 0x876
+					&gem3 0x877 >;
 		};
 
 		spi0: spi@ff040000 {
-- 
cgit v0.10.2


From da2ad7843cedc1b9d2d056b1eb7a67a153b76cc4 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 11 Feb 2016 15:26:46 +0100
Subject: ARM64: zynqmp: Sync GEM nodes with Linux

Remove jumbo properties which are handled in the driver directly
and use mainline compatible string which is already handled by the
driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 66abe6f..7ac21f2 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -302,7 +302,7 @@
 		};
 
 		gem0: ethernet@ff0b0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 57 4>, <0 57 4>;
@@ -311,12 +311,10 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
 		};
 
 		gem1: ethernet@ff0c0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 59 4>, <0 59 4>;
@@ -325,12 +323,10 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
 		};
 
 		gem2: ethernet@ff0d0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 61 4>, <0 61 4>;
@@ -339,12 +335,10 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
 		};
 
 		gem3: ethernet@ff0e0000 {
-			compatible = "cdns,gem";
+			compatible = "cdns,zynqmp-gem";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 63 4>, <0 63 4>;
@@ -353,8 +347,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
-			jumbo-max-len = <10240>;
-			jumbo-supported;
 		};
 
 		gpio: gpio@ff0a0000 {
-- 
cgit v0.10.2


From bd750e7a6c515c081b72d4ef108a2bfa691a3fd1 Mon Sep 17 00:00:00 2001
From: P L Sai Krishna <lakshmi.sai.krishna.potthuri@xilinx.com>
Date: Tue, 19 Jan 2016 19:01:10 +0530
Subject: ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes

This patch adds broken-tuning property to SD and
eMMC nodes.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 7ac21f2..0e6d404 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -434,6 +434,7 @@
 			interrupts = <0 48 4>;
 			reg = <0x0 0xff160000 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
+			broken-tuning;
 		};
 
 		sdhci1: sdhci@ff170000 {
@@ -443,6 +444,7 @@
 			interrupts = <0 49 4>;
 			reg = <0x0 0xff170000 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
+			broken-tuning;
 		};
 
 		smmu: smmu@fd800000 {
-- 
cgit v0.10.2


From 8f4e3972a01a2ac47154fbd737b63b386900315c Mon Sep 17 00:00:00 2001
From: Soren Brinkmann <soren.brinkmann@xilinx.com>
Date: Mon, 11 Jan 2016 15:34:42 -0800
Subject: ARM64: zynqmp: DT: Add power domains

Add power-domains to the DT and attach devices to them.
The power-domains are all logical domains as understood by firmware.
Each PD is identified by a unique identifier that the platform firmware
understands.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 0e6d404..9a53ad6 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -45,6 +45,176 @@
 		};
 	};
 
+	power-domains {
+		compatible = "xlnx,zynqmp-genpd";
+
+		pd_usb0: pd-usb0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x16>;
+		};
+
+		pd_usb1: pd-usb1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x17>;
+		};
+
+		pd_sata: pd-sata {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1c>;
+		};
+
+		pd_spi0: pd-spi0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x23>;
+		};
+
+		pd_spi1: pd-spi1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x24>;
+		};
+
+		pd_uart0: pd-uart0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x21>;
+		};
+
+		pd_uart1: pd-uart1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x22>;
+		};
+
+		pd_eth0: pd-eth0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1d>;
+		};
+
+		pd_eth1: pd-eth1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1e>;
+		};
+
+		pd_eth2: pd-eth2 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1f>;
+		};
+
+		pd_eth3: pd-eth3 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x20>;
+		};
+
+		pd_i2c0: pd-i2c0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x25>;
+		};
+
+		pd_i2c1: pd-i2c1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x26>;
+		};
+
+		pd_dp: pd-dp {
+			/* fixme: what to attach to */
+			#power-domain-cells = <0x0>;
+			pd-id = <0x29>;
+		};
+
+		pd_gdma: pd-gdma {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2a>;
+		};
+
+		pd_adma: pd-adma {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2b>;
+		};
+
+		pd_ttc0: pd-ttc0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x18>;
+		};
+
+		pd_ttc1: pd-ttc1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x19>;
+		};
+
+		pd_ttc2: pd-ttc2 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1a>;
+		};
+
+		pd_ttc3: pd-ttc3 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x1b>;
+		};
+
+		pd_sd0: pd-sd0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x27>;
+		};
+
+		pd_sd1: pd-sd1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x28>;
+		};
+
+		pd_nand: pd-nand {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2c>;
+		};
+
+		pd_qspi: pd-qspi {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2d>;
+		};
+
+		pd_gpio: pd-gpio {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2e>;
+		};
+
+		pd_can0: pd-can0 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x2f>;
+		};
+
+		pd_can1: pd-can1 {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x30>;
+		};
+
+		pd_ddr: pd-ddr {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x37>;
+		};
+
+		pd_apll: pd-apll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x32>;
+		};
+
+		pd_vpll: pd-vpll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x33>;
+		};
+
+		pd_dpll: pd-dpll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x34>;
+		};
+
+		pd_rpll: pd-rpll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x35>;
+		};
+
+		pd_iopll: pd-iopll {
+			#power-domain-cells = <0x0>;
+			pd-id = <0x36>;
+		};
+	};
+
 	pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <0 143 4>,
@@ -106,6 +276,7 @@
 			interrupt-parent = <&gic>;
 			tx-fifo-depth = <0x40>;
 			rx-fifo-depth = <0x40>;
+			power-domains = <&pd_can0>;
 		};
 
 		can1: can@ff070000 {
@@ -117,6 +288,7 @@
 			interrupt-parent = <&gic>;
 			tx-fifo-depth = <0x40>;
 			rx-fifo-depth = <0x40>;
+			power-domains = <&pd_can1>;
 		};
 
 		/* GDMA */
@@ -128,6 +300,7 @@
 			interrupts = <0 124 4>;
 			xlnx,id = <0>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan2: dma@fd510000 {
@@ -138,6 +311,7 @@
 			interrupts = <0 125 4>;
 			xlnx,id = <1>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan3: dma@fd520000 {
@@ -148,6 +322,7 @@
 			interrupts = <0 126 4>;
 			xlnx,id = <2>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan4: dma@fd530000 {
@@ -158,6 +333,7 @@
 			interrupts = <0 127 4>;
 			xlnx,id = <3>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan5: dma@fd540000 {
@@ -168,6 +344,7 @@
 			interrupts = <0 128 4>;
 			xlnx,id = <4>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan6: dma@fd550000 {
@@ -178,6 +355,7 @@
 			interrupts = <0 129 4>;
 			xlnx,id = <5>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan7: dma@fd560000 {
@@ -188,6 +366,7 @@
 			interrupts = <0 130 4>;
 			xlnx,id = <6>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		fpd_dma_chan8: dma@fd570000 {
@@ -198,6 +377,7 @@
 			interrupts = <0 131 4>;
 			xlnx,id = <7>;
 			xlnx,bus-width = <128>;
+			power-domains = <&pd_gdma>;
 		};
 
 		gpu: gpu@fd4b0000 {
@@ -218,6 +398,7 @@
 			interrupts = <0 77 4>;
 			xlnx,id = <0>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan2: dma@ffa90000 {
@@ -228,6 +409,7 @@
 			interrupts = <0 78 4>;
 			xlnx,id = <1>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan3: dma@ffaa0000 {
@@ -238,6 +420,7 @@
 			interrupts = <0 79 4>;
 			xlnx,id = <2>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan4: dma@ffab0000 {
@@ -248,6 +431,7 @@
 			interrupts = <0 80 4>;
 			xlnx,id = <3>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan5: dma@ffac0000 {
@@ -258,6 +442,7 @@
 			interrupts = <0 81 4>;
 			xlnx,id = <4>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan6: dma@ffad0000 {
@@ -268,6 +453,7 @@
 			interrupts = <0 82 4>;
 			xlnx,id = <5>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan7: dma@ffae0000 {
@@ -278,6 +464,7 @@
 			interrupts = <0 83 4>;
 			xlnx,id = <6>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		lpd_dma_chan8: dma@ffaf0000 {
@@ -288,6 +475,7 @@
 			interrupts = <0 84 4>;
 			xlnx,id = <7>;
 			xlnx,bus-width = <64>;
+			power-domains = <&pd_adma>;
 		};
 
 		nand0: nand@ff100000 {
@@ -299,6 +487,7 @@
 			interrupts = <0 14 4>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			power-domains = <&pd_nand>;
 		};
 
 		gem0: ethernet@ff0b0000 {
@@ -311,6 +500,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
+			power-domains = <&pd_eth0>;
 		};
 
 		gem1: ethernet@ff0c0000 {
@@ -323,6 +513,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
+			power-domains = <&pd_eth1>;
 		};
 
 		gem2: ethernet@ff0d0000 {
@@ -335,6 +526,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
+			power-domains = <&pd_eth2>;
 		};
 
 		gem3: ethernet@ff0e0000 {
@@ -347,6 +539,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#stream-id-cells = <1>;
+			power-domains = <&pd_eth3>;
 		};
 
 		gpio: gpio@ff0a0000 {
@@ -356,6 +549,7 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 16 4>;
 			reg = <0x0 0xff0a0000 0x1000>;
+			power-domains = <&pd_gpio>;
 		};
 
 		i2c0: i2c@ff020000 {
@@ -366,6 +560,7 @@
 			reg = <0x0 0xff020000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_i2c0>;
 		};
 
 		i2c1: i2c@ff030000 {
@@ -376,6 +571,7 @@
 			reg = <0x0 0xff030000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_i2c1>;
 		};
 
 		pcie: pcie@fd0e0000 {
@@ -408,6 +604,7 @@
 			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_qspi>;
 		};
 
 		rtc: rtc@ffa60000 {
@@ -425,6 +622,7 @@
 			reg = <0x0 0xfd0c0000 0x2000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
+			power-domains = <&pd_sata>;
 		};
 
 		sdhci0: sdhci@ff160000 {
@@ -435,6 +633,7 @@
 			reg = <0x0 0xff160000 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
 			broken-tuning;
+			power-domains = <&pd_sd0>;
 		};
 
 		sdhci1: sdhci@ff170000 {
@@ -445,6 +644,7 @@
 			reg = <0x0 0xff170000 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
 			broken-tuning;
+			power-domains = <&pd_sd1>;
 		};
 
 		smmu: smmu@fd800000 {
@@ -472,6 +672,7 @@
 			clock-names = "ref_clk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_spi0>;
 		};
 
 		spi1: spi@ff050000 {
@@ -483,6 +684,7 @@
 			clock-names = "ref_clk", "pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&pd_spi1>;
 		};
 
 		ttc0: timer@ff110000 {
@@ -492,6 +694,7 @@
 			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 			reg = <0x0 0xff110000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc0>;
 		};
 
 		ttc1: timer@ff120000 {
@@ -501,6 +704,7 @@
 			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 			reg = <0x0 0xff120000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc1>;
 		};
 
 		ttc2: timer@ff130000 {
@@ -510,6 +714,7 @@
 			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 			reg = <0x0 0xff130000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc2>;
 		};
 
 		ttc3: timer@ff140000 {
@@ -519,6 +724,7 @@
 			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 			reg = <0x0 0xff140000 0x1000>;
 			timer-width = <32>;
+			power-domains = <&pd_ttc3>;
 		};
 
 		uart0: serial@ff000000 {
@@ -528,6 +734,7 @@
 			interrupts = <0 21 4>;
 			reg = <0x0 0xff000000 0x1000>;
 			clock-names = "uart_clk", "pclk";
+			power-domains = <&pd_uart0>;
 		};
 
 		uart1: serial@ff010000 {
@@ -537,6 +744,7 @@
 			interrupts = <0 22 4>;
 			reg = <0x0 0xff010000 0x1000>;
 			clock-names = "uart_clk", "pclk";
+			power-domains = <&pd_uart1>;
 		};
 
 		usb0: usb@fe200000 {
@@ -546,6 +754,7 @@
 			interrupts = <0 65 4>;
 			reg = <0x0 0xfe200000 0x40000>;
 			clock-names = "clk_xin", "clk_ahb";
+			power-domains = <&pd_usb0>;
 		};
 
 		usb1: usb@fe300000 {
@@ -555,6 +764,7 @@
 			interrupts = <0 70 4>;
 			reg = <0x0 0xfe300000 0x40000>;
 			clock-names = "clk_xin", "clk_ahb";
+			power-domains = <&pd_usb1>;
 		};
 
 		watchdog0: watchdog@fd4d0000 {
-- 
cgit v0.10.2


From 14cd9eabb871b693b2f6ca30f2f594baa5e99884 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 15:28:33 +0200
Subject: ARM64: zynqmp: Add missing interrupt-parent to PMU node

ZynqMP is not using global interrupt-parent setting that's why
it has to be listed in every node separately. PMU node missed it and
this patch is adding it.

Reported-by: John Linn <John.Linn@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 9a53ad6..a09bbbf 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -217,6 +217,7 @@
 
 	pmu {
 		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <&gic>;
 		interrupts = <0 143 4>,
 			     <0 144 4>,
 			     <0 145 4>,
-- 
cgit v0.10.2


From ff50d21bd23b4d8a579100a790f5db81498e2d07 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 26 Nov 2015 11:21:25 +0100
Subject: ARM64: zynqmp: Add CCI-400 node

Add CCI-400 node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index a09bbbf..48505fa 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -292,6 +292,25 @@
 			power-domains = <&pd_can1>;
 		};
 
+		cci: cci@fd6e0000 {
+			compatible = "arm,cci-400";
+			reg = <0x0 0xfd6e0000 0x9000>;
+			ranges = <0x0 0x0 0xfd6e0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 123 4>,
+					     <0 123 4>,
+					     <0 123 4>,
+					     <0 123 4>,
+					     <0 123 4>;
+			};
+		};
+
 		/* GDMA */
 		fpd_dma_chan1: dma@fd500000 {
 			status = "disabled";
-- 
cgit v0.10.2


From b34d11de188186e8ca39de6b4f7453823ab20820 Mon Sep 17 00:00:00 2001
From: VNSL Durga <vnsl.durga.challa@xilinx.com>
Date: Thu, 24 Mar 2016 22:45:12 +0530
Subject: ARM64: zynqmp: Added clocks to DT

ZynqMP DMA's main clock and apb clock are added
in zynqmp DT.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 48505fa..4520930 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -318,6 +318,7 @@
 			reg = <0x0 0xfd500000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 124 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <0>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -329,6 +330,7 @@
 			reg = <0x0 0xfd510000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 125 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <1>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -340,6 +342,7 @@
 			reg = <0x0 0xfd520000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 126 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <2>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -351,6 +354,7 @@
 			reg = <0x0 0xfd530000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 127 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <3>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -362,6 +366,7 @@
 			reg = <0x0 0xfd540000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 128 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <4>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -373,6 +378,7 @@
 			reg = <0x0 0xfd550000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 129 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <5>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -384,6 +390,7 @@
 			reg = <0x0 0xfd560000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 130 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <6>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
@@ -395,6 +402,7 @@
 			reg = <0x0 0xfd570000 0x1000>;
 			interrupt-parent = <&gic>;
 			interrupts = <0 131 4>;
+			clock-names = "clk_main", "clk_apb";
 			xlnx,id = <7>;
 			xlnx,bus-width = <128>;
 			power-domains = <&pd_gdma>;
-- 
cgit v0.10.2


From 908690098c1836055ee98bde045308ca2ae5d56e Mon Sep 17 00:00:00 2001
From: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Date: Fri, 11 Mar 2016 13:10:26 +0530
Subject: ARM64: zynqmp: Add ddrc node in dts

This patch adds ddrc memory controller node in dts.
size mentioned in dts is 0x30000, because we need to access DDR_QOS
INTR registers located at fd090208 from this driver.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 4520930..b68fb1a 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -506,6 +506,13 @@
 			power-domains = <&pd_adma>;
 		};
 
+		mc: memory-controller@fd070000 {
+			compatible = "xlnx,zynqmp-ddrc-2.40a";
+			reg = <0x0 0xfd070000 0x30000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 112 4>;
+		};
+
 		nand0: nand@ff100000 {
 			compatible = "arasan,nfc-v3p10";
 			status = "disabled";
-- 
cgit v0.10.2


From 7c38ca36cbfd149e6b9c970c0c6fd39b73ee24a6 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 23 Nov 2015 13:26:15 +0100
Subject: ARM64: zynqmp: Add interrupt-controller property to gpio nodes

GPIO driver supports an input interrupt that's why gpio node itself can
be labeled as interrupt controller.

Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b68fb1a..4850608 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -581,6 +581,8 @@
 			compatible = "xlnx,zynqmp-gpio-1.0";
 			status = "disabled";
 			#gpio-cells = <0x2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <0 16 4>;
 			reg = <0x0 0xff0a0000 0x1000>;
-- 
cgit v0.10.2


From 33aec51742702e3a141973f485905a0f008c3dc6 Mon Sep 17 00:00:00 2001
From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date: Mon, 15 Feb 2016 21:18:58 +0530
Subject: ARM64: zynqmp: Extend pcie node to support legacy interrupts

Modifying device tree node to support legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 4850608..ec6fc6a 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -629,6 +629,16 @@
 			      <0x0 0xe0000000 0x1000000>;
 			reg-names = "breg", "pcireg", "cfg";
 			ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+			pcie_intc: legacy-interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
 		};
 
 		qspi: spi@ff0f0000 {
-- 
cgit v0.10.2


From 91a8b0ee69bde3a97e299bfa12828e4005512074 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 20 Jan 2016 12:59:23 +0100
Subject: ARM64: zynqmp: Fix coding style for pcie

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index ec6fc6a..98c07dc 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -619,10 +619,10 @@
 			#interrupt-cells = <1>;
 			device_type = "pci";
 			interrupt-parent = <&gic>;
-			interrupts = < 0 118 4>,
-				     < 0 116 4>,
-				     < 0 115 4>,	/* MSI_1 [63...32] */
-				     < 0 114 4 >;	/* MSI_0 [31...0] */
+			interrupts = <0 118 4>,
+				     <0 116 4>,
+				     <0 115 4>,	/* MSI_1 [63...32] */
+				     <0 114 4>;	/* MSI_0 [31...0] */
 			interrupt-names = "misc", "intx", "msi_1", "msi_0";
 			reg = <0x0 0xfd0e0000 0x1000>,
 			      <0x0 0xfd480000 0x1000>,
-- 
cgit v0.10.2


From ca2f5878d6e6333fb78783662e004032e77f5577 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 27 Nov 2015 13:22:58 +0100
Subject: ARM64: zynqmp: Add backward compatible string for uart

Mainline kernel has no r1p12 compatible string that's why console stops
to work with the latest DTS files. Append generic compatible string.
Keep in your mind that using this generic compatible string not all uart
features will be available.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 98c07dc..f9249aa 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -775,7 +775,7 @@
 		};
 
 		uart0: serial@ff000000 {
-			compatible = "cdns,uart-r1p12";
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 21 4>;
@@ -785,7 +785,7 @@
 		};
 
 		uart1: serial@ff010000 {
-			compatible = "cdns,uart-r1p12";
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
 			interrupts = <0 22 4>;
-- 
cgit v0.10.2


From 4e31d27b9c2904144c5af6ed1975a8a1a31d93d3 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 27 Jan 2016 19:04:56 +0100
Subject: ARM64: zynqmp: Align node address with parent node for dpdma

Use right addresses for channel names

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index f9249aa..2690aa2 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -904,22 +904,22 @@
 			clock-names = "axi_clk";
 			dma-channels = <6>;
 			#dma-cells = <1>;
-			dma-video0channel@43c10000 {
+			dma-video0channel@fd4c0000 {
 				compatible = "xlnx,video0";
 			};
-			dma-video1channel@43c10000 {
+			dma-video1channel@fd4c0000 {
 				compatible = "xlnx,video1";
 			};
-			dma-video2channel@43c10000 {
+			dma-video2channel@fd4c0000 {
 				compatible = "xlnx,video2";
 			};
-			dma-graphicschannel@43c10000 {
+			dma-graphicschannel@fd4c0000 {
 				compatible = "xlnx,graphics";
 			};
-			dma-audio0channel@43c10000 {
+			dma-audio0channel@fd4c0000 {
 				compatible = "xlnx,audio0";
 			};
-			dma-audio1channel@43c10000 {
+			dma-audio1channel@fd4c0000 {
 				compatible = "xlnx,audio1";
 			};
 		};
-- 
cgit v0.10.2


From 695d75a122e48b95f4ccfffcbc39cb14be382b10 Mon Sep 17 00:00:00 2001
From: Hyun Kwon <hyun.kwon@xilinx.com>
Date: Mon, 23 Nov 2015 17:12:54 -0800
Subject: ARM64: zynqmp: Use correct addresses in node names

Reflect actual silicon addresses in DT node names.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 2690aa2..5001ccc 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -842,7 +842,7 @@
 			};
 		};
 
-		xlnx_dp: dp@43c00000 {
+		xlnx_dp: dp@fd4a0000 {
 			compatible = "xlnx,v-dp";
 			status = "disabled";
 			reg = <0x0 0xfd4a0000 0x1000>;
@@ -887,7 +887,7 @@
 			dma-names = "tx";
 		};
 
-		xlnx_dp_sub: dp_sub@43c0a000 {
+		xlnx_dp_sub: dp_sub@fd4aa000 {
 			compatible = "xlnx,dp-sub";
 			status = "disabled";
 			reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
-- 
cgit v0.10.2


From 939cfeafec767ce0708ac10c1eaaa8e4227fcaa5 Mon Sep 17 00:00:00 2001
From: Hyun Kwon <hyun.kwon@xilinx.com>
Date: Mon, 23 Nov 2015 17:12:55 -0800
Subject: ARM64: zynqmp: dp: Add default properties to zynqmp.dtsi

Add some default properties to zynqmp.dtsi.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 5001ccc..a1804b8 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -858,6 +858,7 @@
 			xlnx,bpc = <8>;
 			xlnx,audio-chan = <2>;
 			xlnx,dp-sub = <&xlnx_dp_sub>;
+			xlnx,max-pclock-frequency = <300000>;
 		};
 
 		xlnx_dp_snd_card: dp_snd_card {
@@ -893,6 +894,8 @@
 			reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
 			reg-names = "blend", "av_buf", "aud";
 			xlnx,output-fmt = "rgb";
+			xlnx,vid-fmt = "yuyv";
+			xlnx,gfx-fmt = "rgb565";
 		};
 
 		xlnx_dpdma: dma@fd4c0000 {
-- 
cgit v0.10.2


From c588d1544405cba91572583621f5faaa1d56f49a Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 15:01:33 +0200
Subject: ARM64: zynqmp: Align register description

Separate register space and put it on more lines.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index a1804b8..e2f7b53 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -648,7 +648,8 @@
 			interrupts = <0 15 4>;
 			interrupt-parent = <&gic>;
 			num-cs = <1>;
-			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+			reg = <0x0 0xff0f0000 0x1000>,
+			      <0x0 0xc0000000 0x8000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			power-domains = <&pd_qspi>;
@@ -891,7 +892,9 @@
 		xlnx_dp_sub: dp_sub@fd4aa000 {
 			compatible = "xlnx,dp-sub";
 			status = "disabled";
-			reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
+			reg = <0x0 0xfd4aa000 0x1000>,
+			      <0x0 0xfd4ab000 0x1000>,
+			      <0x0 0xfd4ac000 0x1000>;
 			reg-names = "blend", "av_buf", "aud";
 			xlnx,output-fmt = "rgb";
 			xlnx,vid-fmt = "yuyv";
-- 
cgit v0.10.2


From 786db82bd5bf09cc8f78c8b14445e843d7566b1c Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 27 Jan 2016 19:02:37 +0100
Subject: ARM64: zynqmp: Add serdes address space dp driver

For run time serdes adjustment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index e2f7b53..324d71b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -846,7 +846,8 @@
 		xlnx_dp: dp@fd4a0000 {
 			compatible = "xlnx,v-dp";
 			status = "disabled";
-			reg = <0x0 0xfd4a0000 0x1000>;
+			reg = <0x0 0xfd4a0000 0x1000>,
+			      <0x0 0xfd400000 0x20000>;
 			interrupts = <0 119 4>;
 			interrupt-parent = <&gic>;
 			clock-names = "aclk", "aud_clk";
-- 
cgit v0.10.2


From a84de48e7585cd4ebf8f353fb5b81d252be6e2e6 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 15:06:07 +0200
Subject: ARM64: zynqmp: Fix DWC3 binding with the kernel

Use the same binding as is used in mainline Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index ee9d0fe..1928b0b 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -23,6 +23,8 @@
 		spi0 = &qspi;
 		spi1 = &spi0;
 		spi2 = &spi1;
+		usb0 = &usb0;
+		usb1 = &usb1;
 	};
 
 	chosen {
@@ -154,12 +156,20 @@
 
 &usb0 {
 	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
 	dr_mode = "peripheral";
 	maximum-speed = "high-speed";
 };
 
 &usb1 {
 	status = "okay";
+};
+
+&dwc3_1 {
+	status = "okay";
 	dr_mode = "host";
 	maximum-speed = "high-speed";
 };
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 324d71b..8413f16 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -796,23 +796,45 @@
 		};
 
 		usb0: usb@fe200000 {
-			compatible = "snps,dwc3";
+			#address-cells = <2>;
+			#size-cells = <1>;
 			status = "disabled";
-			interrupt-parent = <&gic>;
-			interrupts = <0 65 4>;
-			reg = <0x0 0xfe200000 0x40000>;
-			clock-names = "clk_xin", "clk_ahb";
+			compatible = "xlnx,zynqmp-dwc3";
+			clock-names = "bus_clk", "ref_clk";
+			clocks = <&clk125>, <&clk125>;
 			power-domains = <&pd_usb0>;
+			ranges;
+
+			dwc3_0: dwc3@fe200000 {
+				compatible = "snps,dwc3";
+				status = "disabled";
+				reg = <0x0 0xfe200000 0x40000>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 65 4>;
+				/* snps,quirk-frame-length-adjustment = <0x20>; */
+				snps,refclk_fladj;
+			};
 		};
 
 		usb1: usb@fe300000 {
-			compatible = "snps,dwc3";
+			#address-cells = <2>;
+			#size-cells = <1>;
 			status = "disabled";
-			interrupt-parent = <&gic>;
-			interrupts = <0 70 4>;
-			reg = <0x0 0xfe300000 0x40000>;
-			clock-names = "clk_xin", "clk_ahb";
+			compatible = "xlnx,zynqmp-dwc3";
+			clock-names = "bus_clk", "ref_clk";
+			clocks = <&clk125>, <&clk125>;
 			power-domains = <&pd_usb1>;
+			ranges;
+
+			dwc3_1: dwc3@fe300000 {
+				compatible = "snps,dwc3";
+				status = "disabled";
+				reg = <0x0 0xfe300000 0x40000>;
+				interrupt-parent = <&gic>;
+				interrupts = <0 70 4>;
+				/* snps,quirk-frame-length-adjustment = <0x20>; */
+				snps,refclk_fladj;
+			};
 		};
 
 		watchdog0: watchdog@fd4d0000 {
-- 
cgit v0.10.2


From 85d1142eb6cf1bc7f89fdbf67ba228896e158e0d Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 15:07:38 +0200
Subject: ARM64: zynqmp: Use 64bit size cell format for memory node

Enable option to support more then 4GB memories in single size block.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index 1928b0b..7fa0694 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -33,7 +33,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x0 0x0 0x40000000>;
+		reg = <0x0 0x0 0x0 0x40000000>;
 	};
 };
 
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 8413f16..fb95b48 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -10,7 +10,7 @@
 / {
 	compatible = "xlnx,zynqmp";
 	#address-cells = <2>;
-	#size-cells = <1>;
+	#size-cells = <2>;
 
 	cpus {
 		#address-cells = <1>;
@@ -247,7 +247,7 @@
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		ranges;
+		ranges = <0 0 0 0 0xffffffff>;
 
 		gic: interrupt-controller@f9010000 {
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
@@ -266,7 +266,7 @@
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		ranges;
+		ranges = <0 0 0 0 0xffffffff>;
 
 		can0: can@ff060000 {
 			compatible = "xlnx,zynq-can-1.0";
-- 
cgit v0.10.2


From ac8f6913c4269663f3d61e1a4b9b52b2d9b1bb31 Mon Sep 17 00:00:00 2001
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Date: Thu, 5 Nov 2015 17:21:37 +0530
Subject: ARM64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts

This patch adds the sata port phy OOB timing values in the sata
device-tree node.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index 7fa0694..e48a360 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -105,6 +105,15 @@
 &sata {
 	status = "okay";
 	ceva,broken-gen2;
+	/* SATA Phy OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+	ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+	ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+	ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+	ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+	ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 };
 
 &sdhci0 {
-- 
cgit v0.10.2


From 4521202760d78533025fe3df4c7580f8bc97ae40 Mon Sep 17 00:00:00 2001
From: Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>
Date: Thu, 5 Nov 2015 22:21:14 +0530
Subject: ARM64: zynqmp: Add missing nand node for ep108

Add missing nand node for ep108.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
index f864526..48bb426 100644
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi
@@ -62,6 +62,10 @@
 	clocks = <&i2c_clk>;
 };
 
+&nand0 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
 &qspi {
 	clocks = <&misc_clk &misc_clk>;
 };
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
index e48a360..0bbf9a7 100644
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ b/arch/arm/dts/zynqmp-ep108.dts
@@ -73,6 +73,37 @@
 	};
 };
 
+&nand0 {
+	status = "okay";
+	arasan,has-mdma;
+	num-cs = <1>;
+
+	partition@0 {	/* for testing purpose */
+		label = "nand-fsbl-uboot";
+		reg = <0x0 0x0 0x400000>;
+	};
+	partition@1 {	/* for testing purpose */
+		label = "nand-linux";
+		reg = <0x0 0x400000 0x1400000>;
+	};
+	partition@2 {	/* for testing purpose */
+		label = "nand-device-tree";
+		reg = <0x0 0x1800000 0x400000>;
+	};
+	partition@3 {	/* for testing purpose */
+		label = "nand-rootfs";
+		reg = <0x0 0x1C00000 0x1400000>;
+	};
+	partition@4 {	/* for testing purpose */
+		label = "nand-bitstream";
+		reg = <0x0 0x3000000 0x400000>;
+	};
+	partition@5 {	/* for testing purpose */
+		label = "nand-misc";
+		reg = <0x0 0x3400000 0xFCC00000>;
+	};
+};
+
 &qspi {
 	status = "okay";
 	flash@0 {
-- 
cgit v0.10.2


From 885581a56bcf508cca87e3d6afe8987010fdcb6b Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 4 Apr 2016 15:32:20 +0200
Subject: ARM64: zynqmp: Do not setup DM_ETH/GPIO/MMC by default for all boards

There are mini configurations which need to be fit to OCM that's why
these options shouldn't be enabled by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f18dbe6..c8e0337 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -591,8 +591,6 @@ config ARCH_ZYNQMP
 	select ARM64
 	select DM
 	select OF_CONTROL
-	select DM_ETH
-	select DM_MMC
 	select DM_SERIAL
 
 config TEGRA
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 91ae10a..c6e75d4 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -26,8 +26,10 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
+CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
-- 
cgit v0.10.2


From aa5b52f56c9fcafb485c930319a36f68692af30d Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 22 Feb 2016 10:01:27 +0100
Subject: ARM64: zynqmp: Extend early malloc space to be able to run DM drivers

DM drivers need more malloc space for early DM models allocation.
Use 4k instead of 1k.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index c6e75d4..9f72aba 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
-- 
cgit v0.10.2


From 658b3a563983281b6617f57b6bf2aee2c92a2101 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 1 Apr 2016 15:55:47 +0200
Subject: ARM64: zynqmp: Make DDR detection code work on 32bit system

Define u64 types to be usable on 32bit system because of 64bit address
and size cells and 32bit shifts in the code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 087578c..529476b 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -63,8 +63,8 @@ static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
 	int address_cells = fdt_address_cells(fdt, parent_offset);
 	int size_cells = fdt_size_cells(fdt, parent_offset);
 	char *p = buf;
-	phys_addr_t val;
-	phys_size_t vals;
+	u64 val;
+	u64 vals;
 
 	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
 	      __func__, address_cells, size_cells, buf, cell);
@@ -166,7 +166,7 @@ int dram_init(void)
 
 	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
 
-	debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
 
 	return 0;
 }
-- 
cgit v0.10.2


From 52be5c05a06fc533655f63f1d1dd37b3b9e71231 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 11 Apr 2016 11:44:40 +0200
Subject: ARM64: zynqmp: Remove netdev.h from board file
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Including netdev.h is causing compilation warning:
+ int fecmxc_register_mii_postcall(struct eth_device *dev, int
(*cb)(int));
+                                         ^
w+In file included from ../board/xilinx/zynqmp/zynqmp.c:9:0:
w+../include/netdev.h:204:41: warning: ‘struct eth_device’ declared
inside parameter list [enabled by default]
w+../include/netdev.h:204:41: warning: its scope is only this definition
or declaration, which is probably not what you want [enabled by default]

This patch removes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 529476b..132d724 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -6,7 +6,6 @@
  */
 
 #include <common.h>
-#include <netdev.h>
 #include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
-- 
cgit v0.10.2


From 1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 15:58:23 +0200
Subject: ARM64: zynqmp: Add support for ZCU102 platform

Add new board support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 01cf030..da3be70 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -81,7 +81,9 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
-	zynqmp-ep108.dtb
+	zynqmp-ep108.dtb			\
+	zynqmp-zcu102.dtb			\
+	zynqmp-zcu102-revB.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
new file mode 100644
index 0000000..3418909
--- /dev/null
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -0,0 +1,202 @@
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+&amba {
+	clk100: clk100 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk125: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clk200: clk200 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	clk250: clk250 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
+
+	clk300: clk300 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <300000000>;
+	};
+
+	clk600: clk600 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <600000000>;
+	};
+
+	dp_aclk: clock0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-accuracy = <100>;
+	};
+
+	dp_aud_clk: clock1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+		clock-accuracy = <100>;
+	};
+
+	dpdma_clk: dpdma_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <533000000>;
+	};
+
+	drm_clock: drm_clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <262750000>;
+		clock-accuracy = <0x64>;
+	};
+};
+
+&can0 {
+	clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+	clocks = <&clk100 &clk100>;
+};
+
+&fpd_dma_chan1 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&nand0 {
+	clocks = <&clk100 &clk100>;
+};
+
+&gem0 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem1 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem2 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem3 {
+	clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gpio {
+	clocks = <&clk100>;
+};
+
+&i2c0 {
+	clocks = <&clk100>;
+};
+
+&i2c1 {
+	clocks = <&clk100>;
+};
+
+&qspi {
+	clocks = <&clk300 &clk300>;
+};
+
+&sata {
+	clocks = <&clk250>;
+};
+
+&sdhci0 {
+	clocks = <&clk200 &clk200>;
+};
+
+&sdhci1 {
+	clocks = <&clk200 &clk200>;
+};
+
+&spi0 {
+	clocks = <&clk200 &clk200>;
+};
+
+&spi1 {
+	clocks = <&clk200 &clk200>;
+};
+
+&uart0 {
+	clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+	clocks = <&clk100 &clk100>;
+};
+
+&usb0 {
+	clocks = <&clk250>, <&clk250>;
+};
+
+&usb1 {
+	clocks = <&clk250>, <&clk250>;
+};
+
+&xilinx_drm {
+	clocks = <&drm_clock>;
+};
+
+&xlnx_dp {
+	clocks = <&dp_aclk>, <&dp_aud_clk>;
+};
+
+&xlnx_dpdma {
+	clocks = <&dpdma_clk>;
+};
+
+&xlnx_dp_snd_codec0 {
+	clocks = <&dp_aud_clk>;
+};
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
new file mode 100644
index 0000000..765108e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -0,0 +1,42 @@
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevB
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "zynqmp-zcu102.dts"
+
+/ {
+	model = "ZynqMP ZCU102 RevB";
+};
+
+&gem3 {
+	phy-handle = <&phyc>;
+	phyc: phy@c {
+		reg = <0xc>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+	};
+	/* Cleanup from RevA */
+	/delete-node/ phy@21;
+};
+
+/* Different qspi 512Mbit version */
+
+/* Fix collision with u61 */
+&i2c0 {
+	i2cswitch@75 {
+		i2c@2 {
+			max15303@1b { /* u8 */
+				compatible = "max15303";
+				reg = <0x1b>;
+			};
+			/delete-node/ max15303@20;
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts
new file mode 100644
index 0000000..de99602
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zcu102.dts
@@ -0,0 +1,631 @@
+/*
+ * dts file for Xilinx ZynqMP ZCU102
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP ZCU102 RevA";
+	compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&can1 {
+	status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem3 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@21 {
+		reg = <21>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tca6416_u97: gpio@20 {
+		/*
+		 * Enable all GTs to out from U-Boot
+		 * i2c mw 20 6 0  - setup IO to output
+		 * i2c mw 20 2 ef - setup output values on pins 0-7
+		 * i2c mw 20 3 ff - setup output values on pins 10-17
+		 */
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * IRQ not connected
+		 * Lines:
+		 * 0 - PS_GTR_LAN_SEL0
+		 * 1 - PS_GTR_LAN_SEL1
+		 * 2 - PS_GTR_LAN_SEL2
+		 * 3 - PS_GTR_LAN_SEL3
+		 * 4 - PCI_CLK_DIR_SEL
+		 * 5 - IIC_MUX_RESET_B
+		 * 6 - GEM3_EXP_RESET_B
+		 * 7, 10 - 17 - not connected
+		 */
+
+		gtr_sel0 {
+			gpio-hog;
+			gpios = <0 0>;
+			output-high; /* PCIE = 0, DP = 1 */
+			line-name = "sel0";
+		};
+		gtr_sel1 {
+			gpio-hog;
+			gpios = <1 0>;
+			output-high; /* PCIE = 0, DP = 1 */
+			line-name = "sel1";
+		};
+		gtr_sel2 {
+			gpio-hog;
+			gpios = <2 0>;
+			output-high; /* PCIE = 0, USB0 = 1 */
+			line-name = "sel2";
+		};
+		gtr_sel3 {
+			gpio-hog;
+			gpios = <3 0>;
+			output-high; /* PCIE = 0, SATA = 1 */
+			line-name = "sel3";
+		};
+	};
+
+	tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * IRQ not connected
+		 * Lines:
+		 * 0 - VCCPSPLL_EN
+		 * 1 - MGTRAVCC_EN
+		 * 2 - MGTRAVTT_EN
+		 * 3 - VCCPSDDRPLL_EN
+		 * 4 - MIO26_PMU_INPUT_LS
+		 * 5 - PL_PMBUS_ALERT
+		 * 6 - PS_PMBUS_ALERT
+		 * 7 - MAXIM_PMBUS_ALERT
+		 * 10 - PL_DDR4_VTERM_EN
+		 * 11 - PL_DDR4_VPP_2V5_EN
+		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+		 * 13 - PS_DIMM_SUSPEND_EN
+		 * 14 - PS_DDR4_VTERM_EN
+		 * 15 - PS_DDR4_VPP_2V5_EN
+		 * 16 - 17 - not connected
+		 */
+	};
+
+	i2cswitch@75 { /* u60 */
+		compatible = "nxp,pca9544";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+		i2c@0 { /* i2c mw 75 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* PS_PMBUS */
+			ina226@40 { /* u76 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <5000>;
+			};
+			ina226@41 { /* u77 */
+				compatible = "ti,ina226";
+				reg = <0x41>;
+				shunt-resistor = <5000>;
+			};
+			ina226@42 { /* u78 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			ina226@43 { /* u87 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			ina226@44 { /* u85 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <5000>;
+			};
+			ina226@45 { /* u86 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			ina226@46 { /* u93 */
+				compatible = "ti,ina226";
+				reg = <0x46>;
+				shunt-resistor = <5000>;
+			};
+			ina226@47 { /* u88 */
+				compatible = "ti,ina226";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+			ina226@4a { /* u15 */
+				compatible = "ti,ina226";
+				reg = <0x4a>;
+				shunt-resistor = <5000>;
+			};
+			ina226@4b { /* u92 */
+				compatible = "ti,ina226";
+				reg = <0x4b>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@1 { /* i2c mw 75 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* PL_PMBUS */
+			ina226@40 { /* u79 */
+				compatible = "ti,ina226";
+				reg = <0x40>;
+				shunt-resistor = <2000>;
+			};
+			ina226@41 { /* u81 */
+				compatible = "ti,ina226";
+				reg = <0x41>;
+				shunt-resistor = <5000>;
+			};
+			ina226@42 { /* u80 */
+				compatible = "ti,ina226";
+				reg = <0x42>;
+				shunt-resistor = <5000>;
+			};
+			ina226@43 { /* u84 */
+				compatible = "ti,ina226";
+				reg = <0x43>;
+				shunt-resistor = <5000>;
+			};
+			ina226@44 { /* u16 */
+				compatible = "ti,ina226";
+				reg = <0x44>;
+				shunt-resistor = <5000>;
+			};
+			ina226@45 { /* u65 */
+				compatible = "ti,ina226";
+				reg = <0x45>;
+				shunt-resistor = <5000>;
+			};
+			ina226@46 { /* u74 */
+				compatible = "ti,ina226";
+				reg = <0x46>;
+				shunt-resistor = <5000>;
+			};
+			ina226@47 { /* u75 */
+				compatible = "ti,ina226";
+				reg = <0x47>;
+				shunt-resistor = <5000>;
+			};
+		};
+		i2c@2 { /* i2c mw 75 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* MAXIM_PMBUS - 00 */
+			max15301@a { /* u46 */
+				compatible = "max15301";
+				reg = <0xa>;
+			};
+			max15303@b { /* u4 */
+				compatible = "max15303";
+				reg = <0xb>;
+			};
+			max15303@10 { /* u13 */
+				compatible = "max15303";
+				reg = <0x10>;
+			};
+			max15301@13 { /* u47 */
+				compatible = "max15301";
+				reg = <0x13>;
+			};
+			max15303@14 { /* u7 */
+				compatible = "max15303";
+				reg = <0x14>;
+			};
+			max15303@15 { /* u6 */
+				compatible = "max15303";
+				reg = <0x15>;
+			};
+			max15303@16 { /* u10 */
+				compatible = "max15303";
+				reg = <0x16>;
+			};
+			max15303@17 { /* u9 */
+				compatible = "max15303";
+				reg = <0x17>;
+			};
+			max15301@18 { /* u63 */
+				compatible = "max15301";
+				reg = <0x18>;
+			};
+			max15303@1a { /* u49 */
+				compatible = "max15303";
+				reg = <0x1a>;
+			};
+			max15303@1d { /* u18 */
+				compatible = "max15303";
+				reg = <0x1d>;
+			};
+			max15303@20 { /* u8 */
+				compatible = "max15303";
+				status = "disabled"; /* unreachable */
+				reg = <0x20>;
+			};
+
+/*			drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
+drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
+*/
+			max20751@72 { /* u95 FIXME - not detected */
+				compatible = "max20751";
+				reg = <0x72>;
+			};
+			max20751@73 { /* u96 FIXME - not detected */
+				compatible = "max20751";
+				reg = <0x73>;
+			};
+		};
+		/* Bus 3 is not connected */
+	};
+
+	/* FIXME PL connection - u55 , PMOD - j160 */
+	/* FIXME MSP430F - u41 - not detected */
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+	/* FIXME PL i2c via PCA9306 - u45 */
+	/* FIXME MSP430 - u41 - not detected */
+	i2cswitch@74 { /* u34 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		i2c@0 { /* i2c mw 74 0 1 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/*
+			 * IIC_EEPROM 1kB memory which uses 256B blocks
+			 * where every block has different address.
+			 *    0 - 256B address 0x54
+			 * 256B - 512B address 0x55
+			 * 512B - 768B address 0x56
+			 * 768B - 1024B address 0x57
+			 */
+			eeprom@54 { /* u23 */
+				compatible = "at,24c08";
+				reg = <0x54>;
+			};
+		};
+		i2c@1 { /* i2c mw 74 0 2 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			si5341: clock-generator1@36 { /* SI5341 - u69 */
+				compatible = "si5341";
+				reg = <0x36>;
+			};
+
+		};
+		i2c@2 { /* i2c mw 74 0 4 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <300000000>;
+				clock-frequency = <300000000>;
+			};
+		};
+		i2c@3 { /* i2c mw 74 0 8 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>; /* copy from zc702 */
+				factory-fout = <156250000>;
+				clock-frequency = <148500000>;
+			};
+		};
+		i2c@4 { /* i2c mw 74 0 10 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			si5328: clock-generator4@69 {/* SI5328 - u20 */
+				compatible = "silabs,si5328";
+				reg = <0x69>;
+			};
+		};
+		/* 5 - 7 unconnected */
+	};
+
+	i2cswitch@75 {
+		compatible = "nxp,pca9548"; /* u135 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/* HPC0_IIC */
+		};
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			/* HPC1_IIC */
+		};
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			/* SYSMON */
+		};
+		i2c@3 { /* i2c mw 75 0 8 */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			/* DDR4 SODIMM */
+			dev@19 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x19>;
+			};
+			dev@30 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x30>;
+			};
+			dev@35 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x35>;
+			};
+			dev@36 { /* u-boot detection */
+				compatible = "xxx";
+				reg = <0x36>;
+			};
+			dev@51 { /* u-boot detection - maybe SPD */
+				compatible = "xxx";
+				reg = <0x51>;
+			};
+		};
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			/* SEP 3 */
+		};
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			/* SEP 2 */
+		};
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			/* SEP 1 */
+		};
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+			/* SEP 0 */
+		};
+	};
+};
+
+&pcie {
+/*	status = "okay"; */
+};
+
+&qspi {
+	status = "okay";
+	is-dual = <1>;
+	flash@0 {
+		compatible = "m25p80"; /* 32MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+		spi-max-frequency = <108000000>; /* Based on DC1 spec */
+		partition@qspi-fsbl-uboot { /* for testing purpose */
+			label = "qspi-fsbl-uboot";
+			reg = <0x0 0x100000>;
+		};
+		partition@qspi-linux { /* for testing purpose */
+			label = "qspi-linux";
+			reg = <0x100000 0x500000>;
+		};
+		partition@qspi-device-tree { /* for testing purpose */
+			label = "qspi-device-tree";
+			reg = <0x600000 0x20000>;
+		};
+		partition@qspi-rootfs { /* for testing purpose */
+			label = "qspi-rootfs";
+			reg = <0x620000 0x5E0000>;
+		};
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+	/* SATA OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+	status = "okay";
+	no-1-8-v;	/* for 1.0 silicon */
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&xilinx_drm {
+	status = "okay";
+	clocks = <&si570_1>;
+};
+
+&xlnx_dp {
+	status = "okay";
+};
+
+&xlnx_dp_sub {
+	status = "okay";
+	xlnx,vid-clk-pl;
+};
+
+&xlnx_dp_snd_pcm0 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_pcm1 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_card {
+	status = "okay";
+};
+
+&xlnx_dp_snd_codec0 {
+	status = "okay";
+};
+
+&xlnx_dpdma {
+	status = "okay";
+};
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
new file mode 100644
index 0000000..50a957c
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_GPIO=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
new file mode 100644
index 0000000..4f58020
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -0,0 +1,56 @@
+/*
+ * Configuration for Xilinx ZynqMP zcu102
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZCU102_H
+#define __CONFIG_ZYNQMP_ZCU102_H
+
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_NUM_I2C_BUSES	18
+#define CONFIG_SYS_I2C_BUSES	{ \
+				{0, {I2C_NULL_HOP} }, \
+				{0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
+				{0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
+				{0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
+				{1, {I2C_NULL_HOP} }, \
+				{1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
+				{1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
+				}
+
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_AHCI
+#define CONFIG_SATA_CEVA
+
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
+
+#define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZCU102"
+
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+	"kernel_offset=0x180000\0" \
+	"fdt_offset=0x100000\0" \
+	"kernel_size=0x1e00000\0" \
+	"fdt_size=0x80000\0" \
+	"board=zcu102\0"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZCU102_H */
-- 
cgit v0.10.2


From da81db61d562e473765bbe902f5ba21f1fd4806b Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 11 Apr 2016 08:07:07 +0200
Subject: ARM64: zynqmp: Add defconfig for zcu102 revB board

Support natively revB board. Till now support for revB was done via
zcu102 defconfig where device-tree was changed to revB.
This patch is adding direct defconfig for RevB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
new file mode 100644
index 0000000..5bd8248
--- /dev/null
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_GPIO=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
-- 
cgit v0.10.2


From 6c0c958de8259d1163afd5f3b20206a0b6f61c54 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 16:00:11 +0200
Subject: ARM64: zynqmp: Add support for zc1751 with DC cards

Support ZynqMP zc1751 with DC cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index da3be70..54a318a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -83,7 +83,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-ep108.dtb			\
 	zynqmp-zcu102.dtb			\
-	zynqmp-zcu102-revB.dtb
+	zynqmp-zcu102-revB.dtb			\
+	zynqmp-zc1751-xm015-dc1.dtb		\
+	zynqmp-zc1751-xm016-dc2.dtb		\
+	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 0000000..c68a41b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,211 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP zc1751-xm015-dc1 RevA";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c1;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem3 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@0 {
+		reg = <0>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+	eeprom@55 {
+		compatible = "at,24c64"; /* 24AA64 */
+		reg = <0x55>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>; /* Based on DC1 spec */
+		partition@qspi-fsbl-uboot { /* for testing purpose */
+			label = "qspi-fsbl-uboot";
+			reg = <0x0 0x100000>;
+		};
+		partition@qspi-linux { /* for testing purpose */
+			label = "qspi-linux";
+			reg = <0x100000 0x500000>;
+		};
+		partition@qspi-device-tree { /* for testing purpose */
+			label = "qspi-device-tree";
+			reg = <0x600000 0x20000>;
+		};
+		partition@qspi-rootfs { /* for testing purpose */
+			label = "qspi-rootfs";
+			reg = <0x620000 0x5E0000>;
+		};
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+	/* SATA phy OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+	status = "okay";
+	bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+	status = "okay";
+	no-1-8-v;       /* for 1.0 silicon */
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&xilinx_drm {
+	status = "okay";
+};
+
+&xlnx_dp {
+	status = "okay";
+};
+
+&xlnx_dp_sub {
+	status = "okay";
+	xlnx,vid-clk-pl;
+};
+
+&xlnx_dp_snd_pcm0 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_pcm1 {
+	status = "okay";
+};
+
+&xlnx_dp_snd_card {
+	status = "okay";
+};
+
+&xlnx_dp_snd_codec0 {
+	status = "okay";
+};
+
+&xlnx_dpdma {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
new file mode 100644
index 0000000..3fdfcc8
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -0,0 +1,236 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP zc1751-xm016-dc2 RevA";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		can0 = &can0;
+		can1 = &can1;
+		ethernet0 = &gem2;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		usb0 = &usb1;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem2 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@5 {
+		reg = <5>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tca6416_u26: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/* IRQ not connected */
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&nand0 {
+	status = "okay";
+	arasan,has-mdma;
+	num-cs = <2>;
+
+	partition@0 {	/* for testing purpose */
+		label = "nand-fsbl-uboot";
+		reg = <0x0 0x0 0x400000>;
+	};
+	partition@1 {	/* for testing purpose */
+		label = "nand-linux";
+		reg = <0x0 0x400000 0x1400000>;
+	};
+	partition@2 {	/* for testing purpose */
+		label = "nand-device-tree";
+		reg = <0x0 0x1800000 0x400000>;
+	};
+	partition@3 {	/* for testing purpose */
+		label = "nand-rootfs";
+		reg = <0x0 0x1C00000 0x1400000>;
+	};
+	partition@4 {	/* for testing purpose */
+		label = "nand-bitstream";
+		reg = <0x0 0x3000000 0x400000>;
+	};
+	partition@5 {	/* for testing purpose */
+		label = "nand-misc";
+		reg = <0x0 0x3400000 0xFCC00000>;
+	};
+
+	partition@6 {	/* for testing purpose */
+		label = "nand1-fsbl-uboot";
+		reg = <0x1 0x0 0x400000>;
+	};
+	partition@7 {	/* for testing purpose */
+		label = "nand1-linux";
+		reg = <0x1 0x400000 0x1400000>;
+	};
+	partition@8 {	/* for testing purpose */
+		label = "nand1-device-tree";
+		reg = <0x1 0x1800000 0x400000>;
+	};
+	partition@9 {	/* for testing purpose */
+		label = "nand1-rootfs";
+		reg = <0x1 0x1C00000 0x1400000>;
+	};
+	partition@10 {	/* for testing purpose */
+		label = "nand1-bitstream";
+		reg = <0x1 0x3000000 0x400000>;
+	};
+	partition@11 {	/* for testing purpose */
+		label = "nand1-misc";
+		reg = <0x1 0x3400000 0xFCC00000>;
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	num-cs = <1>;
+	spi0_flash0: spi0_flash0@0 {
+		compatible = "m25p80";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+
+		spi0_flash0@00000000 {
+			label = "spi0_flash0";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
+&spi1 {
+	status = "okay";
+	num-cs = <1>;
+	spi1_flash0: spi1_flash0@0 {
+		compatible = "mtd_dataflash";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+
+		spi1_flash0@00000000 {
+			label = "spi1_flash0";
+			reg = <0x0 0x84000>;
+		};
+	};
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644
index 0000000..d754f9f
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,121 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+/ {
+	model = "ZynqMP zc1751-xm019-dc5 RevA";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem1;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&gem1 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: phy@0 {
+		reg = <0>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+/* FIXME: Add device */
+&i2c0 {
+	status = "okay";
+};
+
+/* FIXME: Add device */
+&i2c1 {
+	status = "okay";
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
new file mode 100644
index 0000000..4a62a86
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_GPIO=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
new file mode 100644
index 0000000..c4da7b1
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_GPIO=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
+CONFIG_NAND_ARASAN=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
new file mode 100644
index 0000000..8bbee1b
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_ETH=y
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
new file mode 100644
index 0000000..7aa9936
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -0,0 +1,31 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM015 DC1
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
+#define __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_SDHCI1
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_AHCI
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
+
+#define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm015 dc1"
+
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+	"kernel_offset=0x400000\0" \
+	"fdt_offset=0x2400000\0" \
+	"kernel_size=0x2000000\0" \
+	"fdt_size=0x80000\0" \
+	"board=zc1751-dc1\0"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
new file mode 100644
index 0000000..2727dc6
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -0,0 +1,28 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM016 DC2
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
+#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
+
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
+
+#define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm016 dc2"
+
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+	"kernel_offset=0x400000\0" \
+	"fdt_offset=0x2400000\0" \
+	"kernel_size=0x2000000\0" \
+	"fdt_size=0x80000\0" \
+	"board=zc1751-dc2\0"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
new file mode 100644
index 0000000..d9409ba
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -0,0 +1,30 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM019 DC5
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
+#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_ZYNQ
+
+#define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm019 dc5"
+
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+	"kernel_offset=0x400000\0" \
+	"fdt_offset=0x2400000\0" \
+	"kernel_size=0x2000000\0" \
+	"fdt_size=0x80000\0" \
+	"board=zc1751-dc5\0"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
-- 
cgit v0.10.2


From 08afaf1b4068772fd30ac50e570d6e490fdb3619 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 16:25:35 +0200
Subject: ARM64: zynqmp: Clean header after moving stuff to Kconfig

Moving stuff to Kconfig by script is keep some empty lines
or comment in the file. Remove them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index a603255..f7b4643 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -17,7 +17,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-
 /* Generic Interrupt Controller Definitions */
 #define CONFIG_GICV2
 #define GICD_BASE	0xF9010000
@@ -44,8 +43,6 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
 
-/* Flat Device Tree Definitions */
-
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
 # define COUNTER_FREQUENCY		100000000
-- 
cgit v0.10.2


From 68c7026e8d410295bc281128d8c14edef291461d Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 10 Mar 2016 16:27:38 +0530
Subject: gpio: zynq: Convert Zynq GPIO to driver model

Convert Zynq GPIO driver to driver model

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 83a2c46..92c9f0e 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -14,6 +14,17 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
+#ifdef CONFIG_DM_GPIO
+#include <dm.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct zynq_gpio_privdata {
+	phys_addr_t base;
+};
+#endif
+
 /**
  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
  * for a given pin in the GPIO device
@@ -68,6 +79,7 @@ static int check_gpio(unsigned gpio)
 	return 0;
 }
 
+#ifndef CONFIG_DM_GPIO
 /**
  * gpio_get_value - Get the state of the specified pin of GPIO device
  * @gpio:	gpio pin number within the device
@@ -218,3 +230,142 @@ int gpio_free(unsigned gpio)
 {
 	return 0;
 }
+#else
+static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+	u32 data;
+	unsigned int bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	data = readl(priv->base +
+			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
+
+	return (data >> bank_pin_num) & 1;
+}
+
+static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
+{
+	unsigned int reg_offset, bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
+		/* only 16 data bits in bit maskable reg */
+		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
+		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
+	} else {
+		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
+	}
+
+	/*
+	 * get the 32 bit value to be written to the mask/data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data
+	 */
+	value = !!value;
+	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
+		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
+
+	writel(value, priv->base + reg_offset);
+
+	return 0;
+}
+
+static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
+	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
+		return -1;
+
+	/* clear the bit in direction mode reg to set the pin as input */
+	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg &= ~BIT(bank_pin_num);
+	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+
+	return 0;
+}
+
+static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
+				      int value)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	/* set the GPIO pin as output */
+	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg |= BIT(bank_pin_num);
+	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+
+	/* configure the output enable reg for the pin */
+	reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+	reg |= BIT(bank_pin_num);
+	writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+
+	/* set the state of the pin */
+	gpio_set_value(gpio, value);
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_zynq_ops = {
+	.direction_input	= zynq_gpio_direction_input,
+	.direction_output	= zynq_gpio_direction_output,
+	.get_value		= zynq_gpio_get_value,
+	.set_value		= zynq_gpio_set_value,
+};
+
+static int zynq_gpio_probe(struct udevice *dev)
+{
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	priv->base = dev_get_addr(dev);
+
+	return 0;
+}
+
+static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS;
+
+	return 0;
+}
+
+static const struct udevice_id zynq_gpio_ids[] = {
+	{ .compatible = "xlnx,zynq-gpio-1.0" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_zynq) = {
+	.name	= "gpio_zynq",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_zynq_ops,
+	.of_match = zynq_gpio_ids,
+	.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
+	.probe	= zynq_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
+};
+#endif
-- 
cgit v0.10.2


From 2978ae23fa252659ccfae9c794105a5d7e1ffc76 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 10 Mar 2016 16:27:39 +0530
Subject: gpio: Kconfig: Enable Zynq GPIO driver using kconfig

Enable DM GPIO and ZYNQ GPIO using kconfig instead of the board
config file.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c8e0337..802d3b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -579,6 +579,7 @@ config ARCH_ZYNQ
 	select SPL_OF_CONTROL if SPL
 	select DM
 	select DM_ETH
+	select DM_GPIO
 	select SPL_DM if SPL
 	select DM_MMC
 	select DM_SPI
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f56a606..4d2cc50 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -136,4 +136,11 @@ config MVEBU_GPIO
 	help
 	  Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
 
+config ZYNQ_GPIO
+	bool "Zynq GPIO driver"
+	depends on DM_GPIO && ARCH_ZYNQ
+	default y
+	help
+	  Supports GPIO access on Zynq SoC.
+
 endmenu
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index c96b9c5..49d9fd0 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -39,8 +39,6 @@
 #define CONFIG_ARM_DCC
 #define CONFIG_ZYNQ_SERIAL
 
-#define CONFIG_ZYNQ_GPIO
-
 /* Ethernet driver */
 #if defined(CONFIG_ZYNQ_GEM)
 # define CONFIG_MII
-- 
cgit v0.10.2


From de77a03bf22431297e968fd276a27e753ee2a603 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 10 Mar 2016 16:27:40 +0530
Subject: gpio: zynq: Remove non driver model code

Remove non driver model support as it moved
to driver model. Dont need non driver model
anymore.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h
index 0789c49..956492b 100644
--- a/arch/arm/mach-zynq/include/mach/gpio.h
+++ b/arch/arm/mach-zynq/include/mach/gpio.h
@@ -8,8 +8,6 @@
 #ifndef _ZYNQ_GPIO_H
 #define _ZYNQ_GPIO_H
 
-#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
-
 /* Maximum banks */
 #define ZYNQ_GPIO_MAX_BANK	4
 
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 92c9f0e..07c2eb5 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -13,8 +13,6 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-
-#ifdef CONFIG_DM_GPIO
 #include <dm.h>
 #include <fdtdec.h>
 
@@ -23,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
 struct zynq_gpio_privdata {
 	phys_addr_t base;
 };
-#endif
 
 /**
  * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
@@ -65,7 +62,7 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 	}
 }
 
-int gpio_is_valid(unsigned gpio)
+static int gpio_is_valid(unsigned gpio)
 {
 	return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
 }
@@ -79,158 +76,6 @@ static int check_gpio(unsigned gpio)
 	return 0;
 }
 
-#ifndef CONFIG_DM_GPIO
-/**
- * gpio_get_value - Get the state of the specified pin of GPIO device
- * @gpio:	gpio pin number within the device
- *
- * This function reads the state of the specified pin of the GPIO device.
- *
- * Return: 0 if the pin is low, 1 if pin is high.
- */
-int gpio_get_value(unsigned gpio)
-{
-	u32 data;
-	unsigned int bank_num, bank_pin_num;
-
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
-
-	data = readl(ZYNQ_GPIO_BASE_ADDRESS +
-			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
-
-	return (data >> bank_pin_num) & 1;
-}
-
-/**
- * gpio_set_value - Modify the value of the pin with specified value
- * @gpio:	gpio pin number within the device
- * @value:	value used to modify the value of the specified pin
- *
- * This function calculates the register offset (i.e to lower 16 bits or
- * upper 16 bits) based on the given pin number and sets the value of a
- * gpio pin to the specified value. The value is either 0 or non-zero.
- */
-int gpio_set_value(unsigned gpio, int value)
-{
-	unsigned int reg_offset, bank_num, bank_pin_num;
-
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
-
-	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
-		/* only 16 data bits in bit maskable reg */
-		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
-		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
-	} else {
-		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
-	}
-
-	/*
-	 * get the 32 bit value to be written to the mask/data register where
-	 * the upper 16 bits is the mask and lower 16 bits is the data
-	 */
-	value = !!value;
-	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
-		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
-
-	writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset);
-
-	return 0;
-}
-
-/**
- * gpio_direction_input - Set the direction of the specified GPIO pin as input
- * @gpio:	gpio pin number within the device
- *
- * This function uses the read-modify-write sequence to set the direction of
- * the gpio pin as input.
- *
- * Return: -1 if invalid gpio specified, 0 if successul
- */
-int gpio_direction_input(unsigned gpio)
-{
-	u32 reg;
-	unsigned int bank_num, bank_pin_num;
-
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
-
-	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
-	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
-		return -1;
-
-	/* clear the bit in direction mode reg to set the pin as input */
-	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
-	reg &= ~BIT(bank_pin_num);
-	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
-
-	return 0;
-}
-
-/**
- * gpio_direction_output - Set the direction of the specified GPIO pin as output
- * @gpio:	gpio pin number within the device
- * @value:	value to be written to specified pin
- *
- * This function sets the direction of specified GPIO pin as output, configures
- * the Output Enable register for the pin and uses zynq_gpio_set to set
- * the value of the pin to the value specified.
- *
- * Return: 0 always
- */
-int gpio_direction_output(unsigned gpio, int value)
-{
-	u32 reg;
-	unsigned int bank_num, bank_pin_num;
-
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
-
-	/* set the GPIO pin as output */
-	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
-	reg |= BIT(bank_pin_num);
-	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
-
-	/* configure the output enable reg for the pin */
-	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
-	reg |= BIT(bank_pin_num);
-	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
-
-	/* set the state of the pin */
-	gpio_set_value(gpio, value);
-	return 0;
-}
-
-/**
- * Request a gpio before using it.
- *
- * NOTE: Argument 'label' is unused.
- */
-int gpio_request(unsigned gpio, const char *label)
-{
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	return 0;
-}
-
-/**
- * Reset and free the gpio after using it.
- */
-int gpio_free(unsigned gpio)
-{
-	return 0;
-}
-#else
 static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
 {
 	u32 data;
@@ -368,4 +213,3 @@ U_BOOT_DRIVER(gpio_zynq) = {
 	.probe	= zynq_gpio_probe,
 	.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
 };
-#endif
-- 
cgit v0.10.2


From f17abcaedb8f2ed37b7e9361d4171f03ba25279a Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 10 Mar 2016 16:27:42 +0530
Subject: gpio: zynq: Move the definitions to driver file

Move all the gpio definitions to driver file as
there is no use of them in other files.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h
index 956492b..f3dfd65 100644
--- a/arch/arm/mach-zynq/include/mach/gpio.h
+++ b/arch/arm/mach-zynq/include/mach/gpio.h
@@ -8,65 +8,4 @@
 #ifndef _ZYNQ_GPIO_H
 #define _ZYNQ_GPIO_H
 
-/* Maximum banks */
-#define ZYNQ_GPIO_MAX_BANK	4
-
-#define ZYNQ_GPIO_BANK0_NGPIO	32
-#define ZYNQ_GPIO_BANK1_NGPIO	22
-#define ZYNQ_GPIO_BANK2_NGPIO	32
-#define ZYNQ_GPIO_BANK3_NGPIO	32
-
-#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
-				 ZYNQ_GPIO_BANK1_NGPIO + \
-				 ZYNQ_GPIO_BANK2_NGPIO + \
-				 ZYNQ_GPIO_BANK3_NGPIO)
-
-#define ZYNQ_GPIO_BANK0_PIN_MIN	0
-#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
-					ZYNQ_GPIO_BANK0_NGPIO - 1)
-#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
-					ZYNQ_GPIO_BANK1_NGPIO - 1)
-#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
-					ZYNQ_GPIO_BANK2_NGPIO - 1)
-#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
-					ZYNQ_GPIO_BANK3_NGPIO - 1)
-
-/* Register offsets for the GPIO device */
-/* LSW Mask & Data -WO */
-#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
-/* MSW Mask & Data -WO */
-#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
-/* Data Register-RW */
-#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
-/* Direction mode reg-RW */
-#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
-/* Output enable reg-RW */
-#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
-/* Interrupt mask reg-RO */
-#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
-/* Interrupt enable reg-WO */
-#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
-/* Interrupt disable reg-WO */
-#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
-/* Interrupt status reg-RO */
-#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
-/* Interrupt type reg-RW */
-#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
-/* Interrupt polarity reg-RW */
-#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
-/* Interrupt on any, reg-RW */
-#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
-
-/* Disable all interrupts mask */
-#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
-
-/* Mid pin number of a bank */
-#define ZYNQ_GPIO_MID_PIN_NUM 16
-
-/* GPIO upper 16 bit mask */
-#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-
 #endif /* _ZYNQ_GPIO_H */
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 07c2eb5..05de9c5 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -18,6 +18,67 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Maximum banks */
+#define ZYNQ_GPIO_MAX_BANK	4
+
+#define ZYNQ_GPIO_BANK0_NGPIO	32
+#define ZYNQ_GPIO_BANK1_NGPIO	22
+#define ZYNQ_GPIO_BANK2_NGPIO	32
+#define ZYNQ_GPIO_BANK3_NGPIO	32
+
+#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
+				 ZYNQ_GPIO_BANK1_NGPIO + \
+				 ZYNQ_GPIO_BANK2_NGPIO + \
+				 ZYNQ_GPIO_BANK3_NGPIO)
+
+#define ZYNQ_GPIO_BANK0_PIN_MIN	0
+#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
+					ZYNQ_GPIO_BANK0_NGPIO - 1)
+#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
+					ZYNQ_GPIO_BANK1_NGPIO - 1)
+#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
+					ZYNQ_GPIO_BANK2_NGPIO - 1)
+#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
+					ZYNQ_GPIO_BANK3_NGPIO - 1)
+
+/* Register offsets for the GPIO device */
+/* LSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
+/* MSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
+/* Data Register-RW */
+#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
+/* Direction mode reg-RW */
+#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
+/* Output enable reg-RW */
+#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
+/* Interrupt mask reg-RO */
+#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
+/* Interrupt enable reg-WO */
+#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
+/* Interrupt disable reg-WO */
+#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
+/* Interrupt status reg-RO */
+#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
+/* Interrupt type reg-RW */
+#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
+/* Interrupt polarity reg-RW */
+#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
+/* Interrupt on any, reg-RW */
+#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
+
+/* Disable all interrupts mask */
+#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
+
+/* Mid pin number of a bank */
+#define ZYNQ_GPIO_MID_PIN_NUM 16
+
+/* GPIO upper 16 bit mask */
+#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
+
 struct zynq_gpio_privdata {
 	phys_addr_t base;
 };
-- 
cgit v0.10.2


From 404a00c7c9fff1ef2ba5e33c585ff3c950757f34 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 10 Mar 2016 16:27:43 +0530
Subject: gpio: zynqmp: Add GPIO driver support for ZynqMP

Add GPIO driver support for ZynqMP platform

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 05de9c5..3a995f6 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -31,18 +31,35 @@ DECLARE_GLOBAL_DATA_PTR;
 				 ZYNQ_GPIO_BANK2_NGPIO + \
 				 ZYNQ_GPIO_BANK3_NGPIO)
 
-#define ZYNQ_GPIO_BANK0_PIN_MIN	0
-#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
-					ZYNQ_GPIO_BANK0_NGPIO - 1)
-#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
-					ZYNQ_GPIO_BANK1_NGPIO - 1)
-#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
-					ZYNQ_GPIO_BANK2_NGPIO - 1)
-#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
-					ZYNQ_GPIO_BANK3_NGPIO - 1)
+#define ZYNQMP_GPIO_MAX_BANK	6
+
+#define ZYNQMP_GPIO_BANK0_NGPIO	26
+#define ZYNQMP_GPIO_BANK1_NGPIO	26
+#define ZYNQMP_GPIO_BANK2_NGPIO	26
+#define ZYNQMP_GPIO_BANK3_NGPIO	32
+#define ZYNQMP_GPIO_BANK4_NGPIO	32
+#define ZYNQMP_GPIO_BANK5_NGPIO	32
+
+#define ZYNQMP_GPIO_NR_GPIOS	174
+
+#define ZYNQ_GPIO_BANK0_PIN_MIN(str)	0
+#define ZYNQ_GPIO_BANK0_PIN_MAX(str)	(ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
+					ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
+#define ZYNQ_GPIO_BANK1_PIN_MIN(str)	(ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
+#define ZYNQ_GPIO_BANK1_PIN_MAX(str)	(ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
+					ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
+#define ZYNQ_GPIO_BANK2_PIN_MIN(str)	(ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
+#define ZYNQ_GPIO_BANK2_PIN_MAX(str)	(ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
+					ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
+#define ZYNQ_GPIO_BANK3_PIN_MIN(str)	(ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
+#define ZYNQ_GPIO_BANK3_PIN_MAX(str)	(ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
+					ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
+#define ZYNQ_GPIO_BANK4_PIN_MIN(str)	(ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
+#define ZYNQ_GPIO_BANK4_PIN_MAX(str)	(ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
+					ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
+#define ZYNQ_GPIO_BANK5_PIN_MIN(str)	(ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
+#define ZYNQ_GPIO_BANK5_PIN_MAX(str)	(ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
+					ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
 
 /* Register offsets for the GPIO device */
 /* LSW Mask & Data -WO */
@@ -81,6 +98,55 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct zynq_gpio_privdata {
 	phys_addr_t base;
+	const struct zynq_platform_data *p_data;
+};
+
+/**
+ * struct zynq_platform_data -  zynq gpio platform data structure
+ * @label:	string to store in gpio->label
+ * @ngpio:	max number of gpio pins
+ * @max_bank:	maximum number of gpio banks
+ * @bank_min:	this array represents bank's min pin
+ * @bank_max:	this array represents bank's max pin
+ */
+struct zynq_platform_data {
+	const char *label;
+	u16 ngpio;
+	int max_bank;
+	int bank_min[ZYNQMP_GPIO_MAX_BANK];
+	int bank_max[ZYNQMP_GPIO_MAX_BANK];
+};
+
+static const struct zynq_platform_data zynqmp_gpio_def = {
+	.label = "zynqmp_gpio",
+	.ngpio = ZYNQMP_GPIO_NR_GPIOS,
+	.max_bank = ZYNQMP_GPIO_MAX_BANK,
+	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
+	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
+	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
+	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
+	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
+	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
+	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
+	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
+	.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
+	.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
+	.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
+	.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
+};
+
+static const struct zynq_platform_data zynq_gpio_def = {
+	.label = "zynq_gpio",
+	.ngpio = ZYNQ_GPIO_NR_GPIOS,
+	.max_bank = ZYNQ_GPIO_MAX_BANK,
+	.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
+	.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
+	.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
+	.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
+	.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
+	.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
+	.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
+	.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
 };
 
 /**
@@ -96,41 +162,39 @@ struct zynq_gpio_privdata {
  */
 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 					  unsigned int *bank_num,
-					  unsigned int *bank_pin_num)
+					  unsigned int *bank_pin_num,
+					  struct udevice *dev)
 {
-	switch (pin_num) {
-	case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
-		*bank_num = 0;
-		*bank_pin_num = pin_num;
-		break;
-	case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
-		*bank_num = 1;
-		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
-		break;
-	case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
-		*bank_num = 2;
-		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
-		break;
-	case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
-		*bank_num = 3;
-		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
-		break;
-	default:
-		printf("invalid GPIO pin number: %u\n", pin_num);
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	int bank;
+
+	for (bank = 0; bank < priv->p_data->max_bank; bank++) {
+		if ((pin_num >= priv->p_data->bank_min[bank]) &&
+		    (pin_num <= priv->p_data->bank_max[bank])) {
+				*bank_num = bank;
+				*bank_pin_num = pin_num -
+						priv->p_data->bank_min[bank];
+				return;
+		}
+	}
+
+	if (bank >= priv->p_data->max_bank) {
+		printf("Inavlid bank and pin num\n");
 		*bank_num = 0;
 		*bank_pin_num = 0;
-		break;
 	}
 }
 
-static int gpio_is_valid(unsigned gpio)
+static int gpio_is_valid(unsigned gpio, struct udevice *dev)
 {
-	return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	return (gpio >= 0) && (gpio < priv->p_data->ngpio);
 }
 
-static int check_gpio(unsigned gpio)
+static int check_gpio(unsigned gpio, struct udevice *dev)
 {
-	if (!gpio_is_valid(gpio)) {
+	if (!gpio_is_valid(gpio, dev)) {
 		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
 		return -1;
 	}
@@ -143,10 +207,10 @@ static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
 	unsigned int bank_num, bank_pin_num;
 	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
 
-	if (check_gpio(gpio) < 0)
+	if (check_gpio(gpio, dev) < 0)
 		return -1;
 
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
 
 	data = readl(priv->base +
 			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
@@ -159,10 +223,10 @@ static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
 	unsigned int reg_offset, bank_num, bank_pin_num;
 	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
 
-	if (check_gpio(gpio) < 0)
+	if (check_gpio(gpio, dev) < 0)
 		return -1;
 
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
 
 	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
 		/* only 16 data bits in bit maskable reg */
@@ -191,10 +255,10 @@ static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
 	unsigned int bank_num, bank_pin_num;
 	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
 
-	if (check_gpio(gpio) < 0)
+	if (check_gpio(gpio, dev) < 0)
 		return -1;
 
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
 
 	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
 	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
@@ -215,10 +279,10 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
 	unsigned int bank_num, bank_pin_num;
 	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
 
-	if (check_gpio(gpio) < 0)
+	if (check_gpio(gpio, dev) < 0)
 		return -1;
 
-	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
 
 	/* set the GPIO pin as output */
 	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
@@ -242,29 +306,59 @@ static const struct dm_gpio_ops gpio_zynq_ops = {
 	.set_value		= zynq_gpio_set_value,
 };
 
+static const struct udevice_id zynq_gpio_ids[] = {
+	{ .compatible = "xlnx,zynq-gpio-1.0",
+	  .data = (ulong)&zynq_gpio_def},
+	{ .compatible = "xlnx,zynqmp-gpio-1.0",
+	  .data = (ulong)&zynqmp_gpio_def},
+	{ }
+};
+
+static void zynq_gpio_getplat_data(struct udevice *dev)
+{
+	const struct udevice_id *of_match = zynq_gpio_ids;
+	int ret;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	while (of_match->compatible) {
+		ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+						    of_match->compatible);
+		if (ret >= 0) {
+			priv->p_data =
+				    (struct zynq_platform_data *)of_match->data;
+			break;
+		} else  {
+			of_match++;
+			continue;
+		}
+	}
+
+	if (!priv->p_data)
+		printf("No Platform data found\n");
+}
+
 static int zynq_gpio_probe(struct udevice *dev)
 {
 	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
-	priv->base = dev_get_addr(dev);
+	zynq_gpio_getplat_data(dev);
+
+	if (priv->p_data)
+		uc_priv->gpio_count = priv->p_data->ngpio;
 
 	return 0;
 }
 
 static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
 {
-	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
 
-	uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS;
+	priv->base = dev_get_addr(dev);
 
 	return 0;
 }
 
-static const struct udevice_id zynq_gpio_ids[] = {
-	{ .compatible = "xlnx,zynq-gpio-1.0" },
-	{ }
-};
-
 U_BOOT_DRIVER(gpio_zynq) = {
 	.name	= "gpio_zynq",
 	.id	= UCLASS_GPIO,
-- 
cgit v0.10.2


From 251ab06d26da25bb003117df219288f8e57cabac Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 10 Mar 2016 16:27:44 +0530
Subject: zynqmp: Kconfig: Enable ZYNQ_GPIO for ZynqMP

Enable ZYNQ_GPIO for ZynqMP using Kconfig. It enables the GPIO
driver support for ZynqMP.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 4d2cc50..2b4624d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -138,7 +138,7 @@ config MVEBU_GPIO
 
 config ZYNQ_GPIO
 	bool "Zynq GPIO driver"
-	depends on DM_GPIO && ARCH_ZYNQ
+	depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
 	default y
 	help
 	  Supports GPIO access on Zynq SoC.
-- 
cgit v0.10.2


From f746b4cfd0aa6ccf7fd2c821d6813eed3f88d427 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 11 Apr 2016 11:33:26 +0200
Subject: ARM64: zynqmp: Enable CMD_GPIO and DM_GPIO for ep108

Enable missing GPIO options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 9f72aba..b45c7f2 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
@@ -17,6 +18,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
-- 
cgit v0.10.2


From 01b2a69907a259642be2ff625008b5b9a65a9996 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 11 Apr 2016 13:51:26 +0200
Subject: GPIO: pca953x: Remove compilation warnings on arm64
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Warnings:
w+../drivers/gpio/pca953x.c: In function ‘do_pca953x’:
w+../drivers/gpio/pca953x.c:220:5: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
w+../drivers/gpio/pca953x.c:233:10: warning: cast from pointer to
integer of different size [-Wpointer-to-int-cast]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index 932dfe9..238e028 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -217,7 +217,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	/* All commands but "device" require 'maxargs' arguments */
 	if (!c || !((argc == (c->maxargs)) ||
-		(((int)c->cmd == PCA953X_CMD_DEVICE) &&
+		(((long)c->cmd == PCA953X_CMD_DEVICE) &&
 		 (argc == (c->maxargs - 1))))) {
 		return CMD_RET_USAGE;
 	}
@@ -230,7 +230,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (argc > 3)
 		ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1;
 
-	switch ((int)c->cmd) {
+	switch ((long)c->cmd) {
 #ifdef CONFIG_CMD_PCA953X_INFO
 	case PCA953X_CMD_INFO:
 		ret = pca953x_info(chip);
-- 
cgit v0.10.2


From ff9bd8e9cadd4a8362684fabea6e6a0b4fed63a5 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 11 Apr 2016 13:48:32 +0200
Subject: ARM64: zynqmp: Enable pca953x driver for zcu102

zcu102 has two pca953x on i2c bus 0. Chips 0x20 and 0x21.
Enable option to work with these two chips.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 4f58020..30db2e4 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -37,6 +37,10 @@
 				}
 
 #define CONFIG_SYS_I2C_ZYNQ
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
 #define CONFIG_AHCI
 #define CONFIG_SATA_CEVA
 
-- 
cgit v0.10.2


From 17573c2791a76acd71fa82db513f31e965aa641b Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Mon, 28 Dec 2015 09:47:10 -0800
Subject: i2c: Describe Cadence I2C devicetree bindings

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/doc/device-tree-bindings/i2c/i2c-cdns.txt b/doc/device-tree-bindings/i2c/i2c-cdns.txt
new file mode 100644
index 0000000..202e0b7
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/i2c-cdns.txt
@@ -0,0 +1,20 @@
+Cadence I2C controller Device Tree Bindings
+-------------------------------------------
+
+Required properties:
+- compatible		: Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10".
+- reg			: Physical base address and size of I2C registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clocks		: Clock phandles (see clock bindings for details).
+
+Example:
+	i2c0: i2c@e0004000 {
+		compatible = "cdns,i2c-r1p10";
+		reg = <0xe0004000 0x1000>;
+		clocks = <&clkc 38>;
+		interrupts = <0 25 4>;
+		interrupt-parent = <&intc>;
+		status = "disabled";
+	};
-- 
cgit v0.10.2


From fdec2d21ef8e27dbb01177da53b2bf5167a3dd97 Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Mon, 28 Dec 2015 09:47:11 -0800
Subject: dm: i2c: Add driver for Cadence I2C IP

This is a possible drop in replacement for drivers/i2c/zynq-i2c.c

Since this is cadence IP it has been renamed to cdns-i2c,
to make sense with the compatible string.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 46b83e7..9324c6c 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,13 @@ config DM_I2C_GPIO
 	  bindings are supported.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_CADENCE
+	tristate "Cadence I2C Controller"
+	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
+	help
+	  Say yes here to select Cadence I2C Host Controller. This controller is
+	  e.g. used by Xilinx Zynq.
+
 config SYS_I2C_INTEL
 	bool "Intel I2C/SMBUS driver"
 	depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index c75c579..167424d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
 obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
new file mode 100644
index 0000000..909cea2
--- /dev/null
+++ b/drivers/i2c/i2c-cdns.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
+ * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
+ *
+ * This file is based on: drivers/i2c/zynq_i2c.c,
+ * with added driver-model support and code cleanup.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/errno.h>
+#include <dm/device.h>
+#include <dm/root.h>
+#include <i2c.h>
+#include <fdtdec.h>
+#include <mapmem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* i2c register set */
+struct cdns_i2c_regs {
+	u32 control;
+	u32 status;
+	u32 address;
+	u32 data;
+	u32 interrupt_status;
+	u32 transfer_size;
+	u32 slave_mon_pause;
+	u32 time_out;
+	u32 interrupt_mask;
+	u32 interrupt_enable;
+	u32 interrupt_disable;
+};
+
+/* Control register fields */
+#define CDNS_I2C_CONTROL_RW		0x00000001
+#define CDNS_I2C_CONTROL_MS		0x00000002
+#define CDNS_I2C_CONTROL_NEA		0x00000004
+#define CDNS_I2C_CONTROL_ACKEN		0x00000008
+#define CDNS_I2C_CONTROL_HOLD		0x00000010
+#define CDNS_I2C_CONTROL_SLVMON		0x00000020
+#define CDNS_I2C_CONTROL_CLR_FIFO	0x00000040
+#define CDNS_I2C_CONTROL_DIV_B_SHIFT	8
+#define CDNS_I2C_CONTROL_DIV_B_MASK	0x00003F00
+#define CDNS_I2C_CONTROL_DIV_A_SHIFT	14
+#define CDNS_I2C_CONTROL_DIV_A_MASK	0x0000C000
+
+/* Status register values */
+#define CDNS_I2C_STATUS_RXDV	0x00000020
+#define CDNS_I2C_STATUS_TXDV	0x00000040
+#define CDNS_I2C_STATUS_RXOVF	0x00000080
+#define CDNS_I2C_STATUS_BA	0x00000100
+
+/* Interrupt register fields */
+#define CDNS_I2C_INTERRUPT_COMP		0x00000001
+#define CDNS_I2C_INTERRUPT_DATA		0x00000002
+#define CDNS_I2C_INTERRUPT_NACK		0x00000004
+#define CDNS_I2C_INTERRUPT_TO		0x00000008
+#define CDNS_I2C_INTERRUPT_SLVRDY	0x00000010
+#define CDNS_I2C_INTERRUPT_RXOVF	0x00000020
+#define CDNS_I2C_INTERRUPT_TXOVF	0x00000040
+#define CDNS_I2C_INTERRUPT_RXUNF	0x00000080
+#define CDNS_I2C_INTERRUPT_ARBLOST	0x00000200
+
+#define CDNS_I2C_FIFO_DEPTH		16
+#define CDNS_I2C_TRANSFER_SIZE_MAX	255 /* Controller transfer limit */
+
+#ifdef DEBUG
+static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
+{
+	int int_status;
+	int status;
+	int_status = readl(&cdns_i2c->interrupt_status);
+
+	status = readl(&cdns_i2c->status);
+	if (int_status || status) {
+		debug("Status: ");
+		if (int_status & CDNS_I2C_INTERRUPT_COMP)
+			debug("COMP ");
+		if (int_status & CDNS_I2C_INTERRUPT_DATA)
+			debug("DATA ");
+		if (int_status & CDNS_I2C_INTERRUPT_NACK)
+			debug("NACK ");
+		if (int_status & CDNS_I2C_INTERRUPT_TO)
+			debug("TO ");
+		if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
+			debug("SLVRDY ");
+		if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
+			debug("RXOVF ");
+		if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
+			debug("TXOVF ");
+		if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
+			debug("RXUNF ");
+		if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
+			debug("ARBLOST ");
+		if (status & CDNS_I2C_STATUS_RXDV)
+			debug("RXDV ");
+		if (status & CDNS_I2C_STATUS_TXDV)
+			debug("TXDV ");
+		if (status & CDNS_I2C_STATUS_RXOVF)
+			debug("RXOVF ");
+		if (status & CDNS_I2C_STATUS_BA)
+			debug("BA ");
+		debug("TS%d ", readl(&cdns_i2c->transfer_size));
+		debug("\n");
+	}
+}
+#endif
+
+struct i2c_cdns_bus {
+	int id;
+	struct cdns_i2c_regs __iomem *regs;	/* register base */
+};
+
+
+/** cdns_i2c_probe() - Probe method
+ * @dev: udevice pointer
+ *
+ * DM callback called when device is probed
+ */
+static int cdns_i2c_probe(struct udevice *dev)
+{
+	struct i2c_cdns_bus *bus = dev_get_priv(dev);
+
+	bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
+	if (!bus->regs)
+		return -ENOMEM;
+
+	/* TODO: Calculate dividers based on CPU_CLK_1X */
+	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
+	writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+		(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+
+	/* Enable master mode, ack, and 7-bit addressing */
+	setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
+		CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
+
+	debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
+
+	return 0;
+}
+
+static int cdns_i2c_remove(struct udevice *dev)
+{
+	struct i2c_cdns_bus *bus = dev_get_priv(dev);
+
+	debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
+
+	unmap_sysmem(bus->regs);
+
+	return 0;
+}
+
+/* Wait for an interrupt */
+static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
+{
+	int timeout, int_status;
+
+	for (timeout = 0; timeout < 100; timeout++) {
+		udelay(100);
+		int_status = readl(&cdns_i2c->interrupt_status);
+		if (int_status & mask)
+			break;
+	}
+
+	/* Clear interrupt status flags */
+	writel(int_status & mask, &cdns_i2c->interrupt_status);
+
+	return int_status & mask;
+}
+
+static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+{
+	if (speed != 100000) {
+		printf("%s, failed to set clock speed to %u\n", __func__,
+		       speed);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Probe to see if a chip is present. */
+static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+				uint chip_flags)
+{
+	struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
+	struct cdns_i2c_regs *regs = i2c_bus->regs;
+
+	/* Attempt to read a byte */
+	setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
+		CDNS_I2C_CONTROL_RW);
+	clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
+	writel(0xFF, &regs->interrupt_status);
+	writel(chip_addr, &regs->address);
+	writel(1, &regs->transfer_size);
+
+	return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
+		CDNS_I2C_INTERRUPT_NACK) &
+		CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
+}
+
+static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
+			       u32 len, bool next_is_read)
+{
+	u8 *cur_data = data;
+
+	struct cdns_i2c_regs *regs = i2c_bus->regs;
+
+	setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
+		CDNS_I2C_CONTROL_HOLD);
+
+	/* if next is a read, we need to clear HOLD, doesn't work */
+	if (next_is_read)
+		clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
+
+	clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
+
+	writel(0xFF, &regs->interrupt_status);
+	writel(addr, &regs->address);
+
+	while (len--) {
+		writel(*(cur_data++), &regs->data);
+		if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
+			if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
+				/* Release the bus */
+				clrbits_le32(&regs->control,
+					     CDNS_I2C_CONTROL_HOLD);
+				return -ETIMEDOUT;
+			}
+		}
+	}
+
+	/* All done... release the bus */
+	clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
+	/* Wait for the address and data to be sent */
+	if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
+		return -ETIMEDOUT;
+	return 0;
+}
+
+static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
+			      u32 len)
+{
+	u32 status;
+	u32 i = 0;
+	u8 *cur_data = data;
+
+	/* TODO: Fix this */
+	struct cdns_i2c_regs *regs = i2c_bus->regs;
+
+	/* Check the hardware can handle the requested bytes */
+	if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+		return -EINVAL;
+
+	setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
+		CDNS_I2C_CONTROL_RW);
+
+	/* Start reading data */
+	writel(addr, &regs->address);
+	writel(len, &regs->transfer_size);
+
+	/* Wait for data */
+	do {
+		status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
+			CDNS_I2C_INTERRUPT_DATA);
+		if (!status) {
+			/* Release the bus */
+			clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
+			return -ETIMEDOUT;
+		}
+		debug("Read %d bytes\n",
+		      len - readl(&regs->transfer_size));
+		for (; i < len - readl(&regs->transfer_size); i++)
+			*(cur_data++) = readl(&regs->data);
+	} while (readl(&regs->transfer_size) != 0);
+	/* All done... release the bus */
+	clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
+
+#ifdef DEBUG
+	cdns_i2c_debug_status(regs);
+#endif
+	return 0;
+}
+
+static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
+			 int nmsgs)
+{
+	struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
+	int ret;
+
+	debug("i2c_xfer: %d messages\n", nmsgs);
+	for (; nmsgs > 0; nmsgs--, msg++) {
+		bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
+
+		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+		if (msg->flags & I2C_M_RD) {
+			ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
+						 msg->len);
+		} else {
+			ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
+						  msg->len, next_is_read);
+		}
+		if (ret) {
+			debug("i2c_write: error sending\n");
+			return -EREMOTEIO;
+		}
+	}
+
+	return 0;
+}
+
+static const struct dm_i2c_ops cdns_i2c_ops = {
+	.xfer = cdns_i2c_xfer,
+	.probe_chip = cdns_i2c_probe_chip,
+	.set_bus_speed = cdns_i2c_set_bus_speed,
+};
+
+static const struct udevice_id cdns_i2c_of_match[] = {
+	{ .compatible = "cdns,i2c-r1p10" },
+	{ /* end of table */ }
+};
+
+U_BOOT_DRIVER(cdns_i2c) = {
+	.name = "i2c-cdns",
+	.id = UCLASS_I2C,
+	.of_match = cdns_i2c_of_match,
+	.probe = cdns_i2c_probe,
+	.remove = cdns_i2c_remove,
+	.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
+	.ops = &cdns_i2c_ops,
+};
-- 
cgit v0.10.2


From 58ed7f66939cbfb6e48656b3925aefd9f180a1a3 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 13 Apr 2016 08:49:03 +0200
Subject: ARM64: zynqmp: Use i2c cadence DM driver

Use i2c cadence DM driver for all zynqmp targets except ZCU102
because I2C muxes and PCA953x are not supported in the tree yet.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index b45c7f2..daafb61 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
@@ -17,6 +18,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
@@ -29,6 +31,7 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 4a62a86..366aba2 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
@@ -11,6 +12,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
@@ -19,6 +21,7 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index c4da7b1..6197ad5 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
@@ -11,6 +12,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
@@ -19,6 +21,7 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 8bbee1b..a9b68de 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
@@ -10,12 +11,14 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_OF_EMBED=y
+CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_DM_ETH=y
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 4a83eee..9506355 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -15,8 +15,6 @@
 
 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ	52000000
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ	(CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
-#define CONFIG_ZYNQ_I2C0
-#define CONFIG_SYS_I2C_ZYNQ
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_AHCI
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index 7aa9936..3c0ba88 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -12,8 +12,6 @@
 
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_SDHCI1
-#define CONFIG_ZYNQ_I2C1
-#define CONFIG_SYS_I2C_ZYNQ
 #define CONFIG_AHCI
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
 
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
index 2727dc6..83ea624 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
 #define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
 
-#define CONFIG_ZYNQ_I2C0
-#define CONFIG_SYS_I2C_ZYNQ
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm016 dc2"
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index d9409ba..4f8f5c1 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -12,9 +12,6 @@
 #define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
 
 #define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_ZYNQ_I2C0
-#define CONFIG_ZYNQ_I2C1
-#define CONFIG_SYS_I2C_ZYNQ
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm019 dc5"
 
-- 
cgit v0.10.2


From ff6552e8cc13c9b2283002144e297d63b30ac400 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Wed, 13 Apr 2016 15:45:50 -0400
Subject: xpress: Update <usb/ehci-fsl.h> include

This has been renamed to <usb/ehci-ci.h> some time ago but was missed
here.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c
index 6fc76cd..3193abf 100644
--- a/board/ccv/xpress/xpress.c
+++ b/board/ccv/xpress/xpress.c
@@ -23,7 +23,7 @@
 #include <mmc.h>
 #include <netdev.h>
 #include <usb.h>
-#include <usb/ehci-fsl.h>
+#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
cgit v0.10.2


From 3af65c3f55442f5a48e1657ec9e3fafffd7be0bc Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawnguo@kernel.org>
Date: Fri, 8 Apr 2016 11:06:42 +0800
Subject: odroid: Update README with correct firmware link and XU4 support

The firmware from link [1] only works with U-Boot image that is no
bigger than 328KiB.  Using it with the default mainline U-Boot today
which is already around 500KiB is just not working.  Correct the link
to be hardkernel_1mb_uboot one [2], so that users can get mainline
U-Boot work out of box.

While at it, the README is updated to include XU4 support, like DTB file
name.

[1] https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel
[2] https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel_1mb_uboot

Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/doc/README.odroid b/doc/README.odroid
index ef243d1..c088ec4 100644
--- a/doc/README.odroid
+++ b/doc/README.odroid
@@ -1,11 +1,11 @@
- U-Boot for Odroid X2/U3/XU3
+ U-Boot for Odroid X2/U3/XU3/XU4
 ========================
 
 1. Summary
 ==========
 This is a quick instruction for setup Odroid boards.
 Board config: odroid_config for X2/U3
-Board config: odroid-xu3_config for XU3
+Board config: odroid-xu3_config for XU3/XU4
 
 2. Supported devices
 ====================
@@ -14,6 +14,7 @@ This U-BOOT config can be used on three boards:
 - Odroid X2
 with CPU Exynos 4412 rev 2.0 and 2GB of RAM
 - Odroid XU3
+- Odroid XU4
 with CPU Exynos5422 and 2GB of RAM
 
 3. Boot sequence
@@ -29,9 +30,9 @@ http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&value=boo
 or here:
 http://odroid.in/guides/ubuntu-lfs/boot.tar.gz
 
-<< XU3 >>
+<< XU3/XU4 >>
 It can be downloaded from:
-https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel
+https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel_1mb_uboot
 
 
 4. Boot media layout
@@ -120,6 +121,7 @@ Supported fdt files are:
 - exynos4412-odroidx2.dtb
 - exynos4412-odroidu3.dtb
 - exynos5422-odroidxu3.dtb
+- exynos5422-odroidxu4.dtb
 
 Supported kernel files are:
 - Image.itb
-- 
cgit v0.10.2


From 4ecad8a62942a460b177f34f1eea7326614025f4 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 10 Mar 2016 14:18:44 +0100
Subject: exynos: Set CNTFRQ

Commit 73a1cb27 moved the check whether we should set the architected
timer frequency from CONFIG_SYS_CLK_FREQ to CONFIG_TIMER_CLK_FREQ, but
did not update all users of it.

The one where I (finally) realized why KVM didn't work is the Arndale
board, so this patch adds the respective define to it.

Signed-off-by: Alexander Graf <agraf@suse.de>
Fixes: 73a1cb27
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 852829c..b61f889 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -31,6 +31,7 @@
 
 /* input clock of PLL: 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
+#define CONFIG_TIMER_CLK_FREQ		CONFIG_SYS_CLK_FREQ
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
-- 
cgit v0.10.2


From c3ab985362188ba24847be2dc61dcdcf7b4ce049 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Sat, 12 Mar 2016 13:17:38 +0800
Subject: dm: core: device: set pinctrl state for pinctrl device

We may have pinmux settings for pinctrl device, like the following
example:
"
&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;
	imx6ul-evk {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
				MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x80000000
			>;
		};
	[......]
};
"

We should not only select pinctrl state for non pinctrl devices, we
need also to handle pin mux settings such as pinctrl_log for pinctrl
devices.

So at the end of probing process of pinctrl device, select the default
state of pinctrl device.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index cb24a61..6b1ba22 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -332,6 +332,9 @@ int device_probe(struct udevice *dev)
 	if (ret)
 		goto fail_uclass;
 
+	if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL)
+		pinctrl_select_state(dev, "default");
+
 	return 0;
 fail_uclass:
 	if (device_remove(dev)) {
-- 
cgit v0.10.2


From 2ae67aec5e283e6ccdc43b9432a6077c8af2c27e Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Tue, 15 Mar 2016 16:15:32 -0500
Subject: dm: part: fix missing driver name in debug print
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fixes the following warning with PART_DEBUG enabled:
disk/part.c: In function ‘get_partition_info’:
disk/part.c:372:3: warning: format ‘%s’ expects a matching ‘char *’ argument [-Wformat]

Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/disk/part.c b/disk/part.c
index 0aff954..543cab8 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -365,7 +365,8 @@ int part_get_info(struct blk_desc *dev_desc, int part,
 		return -EPROTONOSUPPORT;
 	}
 	if (!drv->get_info) {
-		PRINTF("## Driver %s does not have the get_info() method\n");
+		PRINTF("## Driver %s does not have the get_info() method\n",
+		       drv->name);
 		return -ENOSYS;
 	}
 	if (drv->get_info(dev_desc, part, info) == 0) {
-- 
cgit v0.10.2


From 770eb30ed971204ab4972b7609ea30beef025a18 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 16 Mar 2016 09:58:01 +0100
Subject: dm: device.c: Minor coding-style fix

Fix multi-line comment indentation in device_bind()

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6b1ba22..9d0c100 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -66,12 +66,12 @@ int device_bind(struct udevice *parent, const struct driver *drv,
 	dev->req_seq = -1;
 	if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) {
 		/*
-		* Some devices, such as a SPI bus, I2C bus and serial ports
-		* are numbered using aliases.
-		*
-		* This is just a 'requested' sequence, and will be
-		* resolved (and ->seq updated) when the device is probed.
-		*/
+		 * Some devices, such as a SPI bus, I2C bus and serial ports
+		 * are numbered using aliases.
+		 *
+		 * This is just a 'requested' sequence, and will be
+		 * resolved (and ->seq updated) when the device is probed.
+		 */
 		if (uc->uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS) {
 			if (uc->uc_drv->name && of_offset != -1) {
 				fdtdec_get_alias_seq(gd->fdt_blob,
-- 
cgit v0.10.2


From e57f9c8eef9ea44b3dd079375a64fef727a8fbcb Mon Sep 17 00:00:00 2001
From: Jagan Teki <jteki@openedev.com>
Date: Thu, 17 Mar 2016 12:23:18 +0530
Subject: doc: driver-model: Update dm tests run using test.py

Since all the tests are implemented in pytest infrastructure,
So update the dm tests with the same instead of ./test/dm/test-dm.sh

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>

diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index b891e84..7a24552 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -90,110 +90,137 @@ The intent with driver model is that the core portion has 100% test coverage
 in sandbox, and every uclass has its own test. As a move towards this, tests
 are provided in test/dm. To run them, try:
 
-   ./test/dm/test-dm.sh
+   ./test/py/test.py --bd sandbox --build -k ut_dm -v
 
 You should see something like this:
 
-    <...U-Boot banner...>
-    Running 53 driver model tests
-    Test: dm_test_autobind
-    Test: dm_test_autoprobe
-    Test: dm_test_bus_child_post_bind
-    Test: dm_test_bus_child_post_bind_uclass
-    Test: dm_test_bus_child_pre_probe_uclass
-    Test: dm_test_bus_children
-    Device 'c-test@0': seq 0 is in use by 'd-test'
-    Device 'c-test@1': seq 1 is in use by 'f-test'
-    Test: dm_test_bus_children_funcs
-    Test: dm_test_bus_children_iterators
-    Test: dm_test_bus_parent_data
-    Test: dm_test_bus_parent_data_uclass
-    Test: dm_test_bus_parent_ops
-    Test: dm_test_bus_parent_platdata
-    Test: dm_test_bus_parent_platdata_uclass
-    Test: dm_test_children
-    Test: dm_test_device_get_uclass_id
-    Test: dm_test_eth
-    Using eth@10002000 device
-    Using eth@10003000 device
-    Using eth@10004000 device
-    Test: dm_test_eth_alias
-    Using eth@10002000 device
-    Using eth@10004000 device
-    Using eth@10002000 device
-    Using eth@10003000 device
-    Test: dm_test_eth_prime
-    Using eth@10003000 device
-    Using eth@10002000 device
-    Test: dm_test_eth_rotate
-
-    Error: eth@10004000 address not set.
-
-    Error: eth@10004000 address not set.
-    Using eth@10002000 device
-
-    Error: eth@10004000 address not set.
-
-    Error: eth@10004000 address not set.
-    Using eth@10004000 device
-    Test: dm_test_fdt
-    Test: dm_test_fdt_offset
-    Test: dm_test_fdt_pre_reloc
-    Test: dm_test_fdt_uclass_seq
-    Test: dm_test_gpio
-    extra-gpios: get_value: error: gpio b5 not reserved
-    Test: dm_test_gpio_anon
-    Test: dm_test_gpio_copy
-    Test: dm_test_gpio_leak
-    extra-gpios: get_value: error: gpio b5 not reserved
-    Test: dm_test_gpio_phandles
-    Test: dm_test_gpio_requestf
-    Test: dm_test_i2c_bytewise
-    Test: dm_test_i2c_find
-    Test: dm_test_i2c_offset
-    Test: dm_test_i2c_offset_len
-    Test: dm_test_i2c_probe_empty
-    Test: dm_test_i2c_read_write
-    Test: dm_test_i2c_speed
-    Test: dm_test_leak
-    Test: dm_test_lifecycle
-    Test: dm_test_net_retry
-    Using eth@10004000 device
-    Using eth@10002000 device
-    Using eth@10004000 device
-    Test: dm_test_operations
-    Test: dm_test_ordering
-    Test: dm_test_pci_base
-    Test: dm_test_pci_swapcase
-    Test: dm_test_platdata
-    Test: dm_test_pre_reloc
-    Test: dm_test_remove
-    Test: dm_test_spi_find
-    Invalid chip select 0:0 (err=-19)
-    SF: Failed to get idcodes
-    SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
-    Test: dm_test_spi_flash
-    2097152 bytes written in 0 ms
-    SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
-    SPI flash test:
-    0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    Test passed
-    0 erase: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    1 check: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    2 write: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    3 read: 0 ticks, 65536000 KiB/s 524288.000 Mbps
-    Test: dm_test_spi_xfer
-    SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB
-    Test: dm_test_uclass
-    Test: dm_test_uclass_before_ready
-    Test: dm_test_usb_base
-    Test: dm_test_usb_flash
-    USB-1:   scanning bus 1 for devices... 2 USB Device(s) found
-    Failures: 0
-
+(venv)$ ./test/py/test.py --bd sandbox --build -k ut_dm -v
++make O=/root/u-boot/build-sandbox -s sandbox_defconfig
++make O=/root/u-boot/build-sandbox -s -j8
+============================= test session starts ==============================
+platform linux2 -- Python 2.7.5, pytest-2.9.0, py-1.4.31, pluggy-0.3.1 -- /root/u-boot/venv/bin/python
+cachedir: .cache
+rootdir: /root/u-boot, inifile:
+collected 199 items
+
+test/py/tests/test_ut.py::test_ut_dm_init PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_bind] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_conversion] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_shot] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_conversion] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_shot] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_supply] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_adc_wrong_channel_selection] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_autobind] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_alloc] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_valid] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_autoprobe] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_bind] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_post_bind_uclass] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_child_pre_probe_uclass] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_children] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_funcs] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_children_iterators] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_data_uclass] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_ops] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_bus_parent_platdata_uclass] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_children] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_clk_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_clk_periph] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_device_get_uclass_id] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_eth] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_eth_act] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_eth_alias] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_eth_prime] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_eth_rotate] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_fdt] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_fdt_offset] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_fdt_pre_reloc] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_fdt_uclass_seq] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_gpio] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_gpio_anon] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_gpio_copy] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_gpio_leak] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_gpio_phandles] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_gpio_requestf] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_bytewise] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_find] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_offset_len] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_probe_empty] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_read_write] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_i2c_speed] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_leak] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_led_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_led_gpio] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_led_label] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_lifecycle] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_mmc_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_net_retry] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_operations] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_ordering] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_pci_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_pci_busnum] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_pci_swapcase] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_platdata] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_get] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_pmic_io] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_autoset_list] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_get] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_current] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_enable] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_mode] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_power_regulator_set_get_voltage] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_pre_reloc] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_ram_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_regmap_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_regmap_syscon] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_remoteproc_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_remove] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_reset_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_reset_walk] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_rtc_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_rtc_dual] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_rtc_reset] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_rtc_set_get] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_spi_find] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_spi_flash] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_spi_xfer] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_syscon_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_syscon_by_driver_data] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_timer_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_uclass] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_uclass_before_ready] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_find] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_find_by_name] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_get] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_uclass_devices_get_by_name] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_flash] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_keyb] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_multi] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_remove] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_tree] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_tree_remove] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_usb_tree_reorder] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_base] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_bmp] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_bmp_comp] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_chars] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_context] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation1] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation2] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_rotation3] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_text] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype_bs] PASSED
+test/py/tests/test_ut.py::test_ut[ut_dm_video_truetype_scroll] PASSED
+
+======================= 84 tests deselected by '-kut_dm' =======================
+================== 115 passed, 84 deselected in 3.77 seconds ===================
 
 What is going on?
 -----------------
-- 
cgit v0.10.2


From 7b3dc45ea5179b377c01c8f878c1633d707186c8 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jteki@openedev.com>
Date: Thu, 17 Mar 2016 12:23:19 +0530
Subject: board: README.sandbox: Update dm test command

Update dm test command with pytest instead of ./test/dm/test-dm.sh

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>

diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index 08489e3..fa1842b 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -349,7 +349,8 @@ directory. These include:
      - Unit tests for U-Boot's compression algorithms, useful for
        security checking. It supports gzip, bzip2, lzma and lzo.
   driver model
-     - test/dm/test-dm.sh to run these.
+     - Run this pytest
+	  ./test/py/test.py --bd sandbox --build -k ut_dm -v
   image
      - Unit tests for images:
           test/image/test-imagetools.sh - multi-file images
-- 
cgit v0.10.2


From f09144a220ce71d628830f7ccadeacd0cfdf6d76 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Sun, 20 Mar 2016 10:10:28 -0400
Subject: test/dm/core.c: Make pre-reloc test use pre-reloc struct

LLVM 3.5 noted:
test/dm/core.c:41:35: warning: unused variable 'test_pdata_pre_reloc' [-Wunused-const-variable]
static const struct dm_test_pdata test_pdata_pre_reloc = {

And the correct fix here is that the driver_info_pre_reloc test should
use the test_pdata_pre_reloc not test_pdata_manual variable

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/test/dm/core.c b/test/dm/core.c
index 9fbc70d..70bf4d0 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -64,7 +64,7 @@ static struct driver_info driver_info_manual = {
 
 static struct driver_info driver_info_pre_reloc = {
 	.name = "test_pre_reloc_drv",
-	.platdata = &test_pdata_manual,
+	.platdata = &test_pdata_pre_reloc,
 };
 
 void dm_leak_check_start(struct unit_test_state *uts)
-- 
cgit v0.10.2


From 690d8a92c1f74115f954202023443d6869bac738 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Tue, 15 Mar 2016 13:20:23 -0400
Subject: sandbox: Enable many more commands

- Set CONFIG_SYS_CACHELINE_SIZE to ARCH_DMA_MINALIGN as that should be
  good enough.
- Make <asm/io.h> include <asm/types.h> like other arches do
- Enable many many more drivers in sandbox_defconfig so that we can get
  more build-time testing on this platform.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/include/asm/cache.h b/arch/sandbox/include/asm/cache.h
index ffbb984..a545e4b 100644
--- a/arch/sandbox/include/asm/cache.h
+++ b/arch/sandbox/include/asm/cache.h
@@ -20,5 +20,6 @@
 #else
 #define ARCH_DMA_MINALIGN	16
 #endif
+#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
 
 #endif /* __SANDBOX_CACHE_H__ */
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 5b87fde..b87ee19 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -57,5 +57,6 @@ void outw(unsigned int value, unsigned int addr);
 void outb(unsigned int value, unsigned int addr);
 
 #include <iotrace.h>
+#include <asm/types.h>
 
 #endif
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index bfc8b61..f5281b3 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,44 +1,79 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_I8042_KEYB=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_FDT=y
+CONFIG_BOOTSTAGE_STASH=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
+CONFIG_LOOPW=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DEMO=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
 CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y
+CONFIG_NETCONSOLE=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_DEVRES=y
+CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_BLK=y
 CONFIG_CLK=y
-CONFIG_SANDBOX_GPIO=y
+CONFIG_CPU=y
+CONFIG_DM_DEMO=y
+CONFIG_DM_DEMO_SIMPLE=y
+CONFIG_DM_DEMO_SHAPE=y
 CONFIG_PM8916_GPIO=y
+CONFIG_SANDBOX_GPIO=y
+CONFIG_DM_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_SANDBOX=y
+CONFIG_I2C_MUX=y
+CONFIG_SPL_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_LPC=y
 CONFIG_CROS_EC_SANDBOX=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_SPL_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
@@ -57,14 +92,28 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
+CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_PMIC_MAX77686=y
 CONFIG_PMIC_PM8916=y
-CONFIG_SPMI=y
-CONFIG_SPMI_SANDBOX=y
+CONFIG_PMIC_RK808=y
+CONFIG_PMIC_S2MPS11=y
+CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_S5M8767=y
+CONFIG_PMIC_TPS65090=y
 CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_MAX77686=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S5M8767=y
 CONFIG_DM_REGULATOR_SANDBOX=y
+CONFIG_REGULATOR_TPS65090=y
 CONFIG_RAM=y
 CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RTC=y
@@ -72,6 +121,8 @@ CONFIG_SANDBOX_SERIAL=y
 CONFIG_SOUND=y
 CONFIG_SOUND_SANDBOX=y
 CONFIG_SANDBOX_SPI=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
 CONFIG_TIMER=y
 CONFIG_TIMER_EARLY=y
 CONFIG_SANDBOX_TIMER=y
-- 
cgit v0.10.2


From 43c4d44e3330fd21679c0790fa2176075d0e69bf Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 6 Apr 2016 12:49:19 -0600
Subject: fdt: implement dev_get_addr_name()

This function parses the reg property based on an index found in the
reg-names property. This is required for bindings that are written
using reg-names rather than hard-coding indices in reg.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 9d0c100..269087a 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -652,6 +652,22 @@ fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
 #endif
 }
 
+fdt_addr_t dev_get_addr_name(struct udevice *dev, const char *name)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	int index;
+
+	index = fdt_find_string(gd->fdt_blob, dev->parent->of_offset,
+				"reg-names", name);
+	if (index < 0)
+		return index;
+
+	return dev_get_addr_index(dev, index);
+#else
+	return FDT_ADDR_T_NONE;
+#endif
+}
+
 fdt_addr_t dev_get_addr(struct udevice *dev)
 {
 	return dev_get_addr_index(dev, 0);
diff --git a/include/dm/device.h b/include/dm/device.h
index 1cf8150..dad7591 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -465,6 +465,18 @@ fdt_addr_t dev_get_addr(struct udevice *dev);
 fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
 
 /**
+ * dev_get_addr_name() - Get the reg property of a device, indexed by name
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_name(struct udevice *dev, const char *name);
+
+/**
  * device_has_children() - check if a device has any children
  *
  * @dev:	Device to check
-- 
cgit v0.10.2


From 7e019daf7ab9dca3bf782d6de866b36d44ede95e Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Tue, 12 Apr 2016 15:11:22 -0400
Subject: drivers/tpm/tpm_tis_sandbox.c: Fix uninitialized variable use

In rollback_space_kernel we were not initializing the reserved fields
which should be for safety sake, and doing memset here means we don't
need to set the version field specifically either.

Reported-by: Coverity (CID: 143917)
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c
index 4aade56..e7746dc 100644
--- a/drivers/tpm/tpm_tis_sandbox.c
+++ b/drivers/tpm/tpm_tis_sandbox.c
@@ -214,9 +214,9 @@ static int sandbox_tpm_xfer(struct udevice *dev, const uint8_t *sendbuf,
 
 			data = recvbuf + TPM_RESPONSE_HEADER_LENGTH +
 					sizeof(uint32_t);
+			memset(&rsk, 0, sizeof(struct rollback_space_kernel));
 			rsk.struct_version = 2;
 			rsk.uid = ROLLBACK_SPACE_KERNEL_UID;
-			rsk.kernel_versions = 0;
 			rsk.crc8 = crc8(0, (unsigned char *)&rsk,
 					offsetof(struct rollback_space_kernel,
 						 crc8));
-- 
cgit v0.10.2


From 108f8418597350bd98357f25acaa8ab8a0435779 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Fri, 15 Apr 2016 20:42:59 -0600
Subject: ARM: rpi: fix 64-bit CONFIG_SYS_TEXT_BASE

The Pi firmware has changed the default "kernel" load address for 64-bit
mode. The authors have confirmed that this is a deliberate and long-term
change. Adapt U-Boot to the new value.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index b83d622..19ca606 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -48,7 +48,11 @@
 /* Memory layout */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
+#ifdef CONFIG_ARM64
+#define CONFIG_SYS_TEXT_BASE		0x00080000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x00008000
+#endif
 #define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
 /*
  * The board really has 256M. However, the VC (VideoCore co-processor) shares
-- 
cgit v0.10.2


From 125d193c4f3895f772a3463996cc8a2554d0b36e Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Sun, 3 Apr 2016 21:52:13 +0800
Subject: common: env: support sata device

Introduce env support for sata device.
1. Implement write_env/read_env/env_relocate_spec/saveenv/sata_get_env_dev
2. If want to enable this feature, define CONFIG_ENV_IS_IN_SATA, and
   define CONFIG_SYS_SATA_ENV_DEV or implement your own sata_get_ev_dev.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stuart Longland <stuartl@vrt.com.au>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 9cf884e..b67563b 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -49,12 +49,13 @@ DECLARE_GLOBAL_DATA_PTR;
 	!defined(CONFIG_ENV_IS_IN_NAND)		&& \
 	!defined(CONFIG_ENV_IS_IN_NVRAM)	&& \
 	!defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
+	!defined(CONFIG_ENV_IS_IN_SATA)		&& \
 	!defined(CONFIG_ENV_IS_IN_SPI_FLASH)	&& \
 	!defined(CONFIG_ENV_IS_IN_REMOTE)	&& \
 	!defined(CONFIG_ENV_IS_IN_UBI)		&& \
 	!defined(CONFIG_ENV_IS_NOWHERE)
 # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
 #endif
 
 /*
diff --git a/common/Makefile b/common/Makefile
index 9a4b817..b23f312 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
 obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
 obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
+obj-$(CONFIG_ENV_IS_IN_SATA) += env_sata.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
 obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
diff --git a/common/env_sata.c b/common/env_sata.c
new file mode 100644
index 0000000..b0cee35
--- /dev/null
+++ b/common/env_sata.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2010-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <errno.h>
+#include <memalign.h>
+#include <sata.h>
+#include <search.h>
+
+#if defined(CONFIG_ENV_SIZE_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+#error ENV REDUND not supported
+#endif
+
+#if !defined(CONFIG_ENV_OFFSET) || !defined(CONFIG_ENV_SIZE)
+#error CONFIG_ENV_OFFSET or CONFIG_ENV_SIZE not defined
+#endif
+
+char *env_name_spec = "SATA";
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int sata_get_env_dev(void)
+{
+	return CONFIG_SYS_SATA_ENV_DEV;
+}
+
+int env_init(void)
+{
+	/* use default */
+	gd->env_addr = (ulong)&default_environment[0];
+	gd->env_valid = 1;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+static inline int write_env(struct blk_desc *sata, unsigned long size,
+			    unsigned long offset, void *buffer)
+{
+	uint blk_start, blk_cnt, n;
+
+	blk_start = ALIGN(offset, sata->blksz) / sata->blksz;
+	blk_cnt   = ALIGN(size, sata->blksz) / sata->blksz;
+
+	n = blk_dwrite(sata, blk_start, blk_cnt, buffer);
+
+	return (n == blk_cnt) ? 0 : -1;
+}
+
+int saveenv(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
+	struct blk_desc *sata = NULL;
+	int env_sata, ret;
+
+	if (sata_initialize())
+		return 1;
+
+	env_sata = sata_get_env_dev();
+
+	sata = sata_get_dev(env_sata);
+	if (sata == NULL) {
+		printf("Unknown SATA(%d) device for environment!\n",
+		       env_sata);
+		return 1;
+	}
+
+	ret = env_export(env_new);
+	if (ret)
+		return 1;
+
+	printf("Writing to SATA(%d)...", env_sata);
+	if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, &env_new)) {
+		puts("failed\n");
+		return 1;
+	}
+
+	puts("done\n");
+	return 0;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+static inline int read_env(struct blk_desc *sata, unsigned long size,
+			   unsigned long offset, void *buffer)
+{
+	uint blk_start, blk_cnt, n;
+
+	blk_start = ALIGN(offset, sata->blksz) / sata->blksz;
+	blk_cnt   = ALIGN(size, sata->blksz) / sata->blksz;
+
+	n = blk_dread(sata, blk_start, blk_cnt, buffer);
+
+	return (n == blk_cnt) ? 0 : -1;
+}
+
+void env_relocate_spec(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+	struct blk_desc *sata = NULL;
+	int env_sata;
+
+	if (sata_initialize())
+		return;
+
+	env_sata = sata_get_env_dev();
+
+	sata = sata_get_dev(env_sata);
+	if (sata == NULL) {
+		printf("Unknown SATA(%d) device for environment!\n",
+		       env_sata);
+		return;
+	}
+
+	if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf))
+		return set_default_env(NULL);
+
+	env_import(buf, 1);
+}
-- 
cgit v0.10.2


From 4bc5e19e124636c695459ffe3f654513ba93105a Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 4 Apr 2016 15:22:49 +0530
Subject: drivers: mmc: omap_hsmmc: Fix conversion of address to a pointer
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

omap_hsmmc driver directly typecasts fdt_addr_t to a pointer.
This is not strictly correct, as it gives a build warning when
fdt_addr_t is u64. So, use map_physmem for a proper typecasts.

This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address
instead of a pointer for the uart base")

drivers/mmc/omap_hsmmc.c: In function ‘omap_hsmmc_ofdata_to_platdata’:
drivers/mmc/omap_hsmmc.c:776:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  priv->base_addr = (struct hsmmc *)dev_get_addr(dev);
                      ^

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afe0b06..1071314 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -773,7 +773,8 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 	struct mmc_config *cfg;
 	int val;
 
-	priv->base_addr = (struct hsmmc *)dev_get_addr(dev);
+	priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
+				      MAP_NOCACHE);
 	cfg = &priv->cfg;
 
 	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
-- 
cgit v0.10.2


From 5cc6a2458e33bb1b99b323ef1f69b5446820d8d7 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 4 Apr 2016 17:28:01 +0530
Subject: drivers: mmc: omap_hsmmc: request cd and wp gpios when DM_MMC is
 defined

Add request gpio for CD and WP gpios, so that the gpio can be
used for the respective purposes.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 1071314..85a832b 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -820,6 +820,11 @@ static int omap_hsmmc_probe(struct udevice *dev)
 	if (mmc == NULL)
 		return -1;
 
+#ifdef OMAP_HSMMC_USE_GPIO
+	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+#endif
+
 	upriv->mmc = mmc;
 
 	return 0;
-- 
cgit v0.10.2


From 103afa2abfe2775797073df1538363952a1a960d Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 4 Apr 2016 17:28:02 +0530
Subject: ARM: dts: am43xx: fix cd-gpios definition as per hardware design and
 dt binding docs

As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.

In AM43xx the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index 8e23b96..142bfc5 100644
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -573,7 +573,7 @@
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &mmc3 {
diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index 260edb9..927d8d3 100644
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -536,7 +536,7 @@
 
 	vmmc-supply = <&dcdc4>;
 	bus-width = <4>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &usb2_phy1 {
-- 
cgit v0.10.2


From e36142143005e86d2d083d9549836c32bb3a6120 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 4 Apr 2016 17:28:03 +0530
Subject: ARM: dts: dra7xx: am57xx: fix cd-gpios definition as per hardware
 design and dt binding docs

As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.

In DRA72x and AM57xx EVMs the card detect gpio is designed as
active low gpio. So correcting the dt card detect gpio
definition.

Also adding card-detect gpio for DRA74x EVM.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts
index e424562..38b266a 100644
--- a/arch/arm/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/dts/am57xx-beagle-x15.dts
@@ -586,7 +586,7 @@
 	vmmc_aux-supply = <&vdd_3v3>;
 	pbias-supply = <&pbias_mmc_reg>;
 	bus-width = <4>;
-	cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
 };
 
 &mmc2 {
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 242fd53..08ef04e 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -469,6 +469,11 @@
 	status = "okay";
 	vmmc-supply = <&ldo1_reg>;
 	bus-width = <4>;
+	/*
+	 * SDCD signal is not being used here - using the fact that GPIO mode
+	 * is always hardwired.
+	 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 };
 
 &mmc2 {
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index fc2d167..205103e 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -503,7 +503,7 @@
 	 * SDCD signal is not being used here - using the fact that GPIO mode
 	 * is a viable alternative
 	 */
-	cd-gpios = <&gpio6 27 0>;
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 };
 
 &mmc2 {
-- 
cgit v0.10.2


From 4965919496f57b348f5ccd85154d7813827d7cb2 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 4 Apr 2016 17:28:04 +0530
Subject: configs: dra72_evm: enable mmc driver model

enable mmc driver model for dra72 evm as omap_hsmmc
supports driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index da24992..6626a1e 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -25,3 +25,4 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_DM_MMC=y
-- 
cgit v0.10.2


From f0ad6e361df4d588c6a4a601e41b6a4804ea7f6d Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 4 Apr 2016 17:28:05 +0530
Subject: configs: dra74_evm: enable mmc driver model

enable mmc driver model for dra74 evm as omap_hsmmc
supports driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 9039b15..5f50004 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -24,3 +24,4 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_DM_MMC=y
-- 
cgit v0.10.2


From efe8d89943123b9386785a21c0ef906b79f8f2dc Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Mon, 4 Apr 2016 12:59:44 -0700
Subject: bcm281xx: enable CONFIG_OF_LIBFDT

set the Kconfig parameter: CONFIG_OF_LIBFDT

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index ba57944..538647d 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -9,3 +9,4 @@ CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_OF_LIBFDT=y
-- 
cgit v0.10.2


From 30b0195a4e0f30117cd9dd36bedde6cae0d9e210 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Mon, 4 Apr 2016 12:59:45 -0700
Subject: bcm281xx: save ENV to MMC

Enable saving ENV to MMC for the bcm281xx boards.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index cf25bde..052a1fa 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -88,8 +88,11 @@
 
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_ENV_SIZE			0x10000
-#define CONFIG_ENV_IS_NOWHERE
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(0x00011a00 * 512)
+#define CONFIG_ENV_SIZE			(8 * 512)
 
 #define CONFIG_SYS_NO_FLASH	/* Not using NAND/NOR unmanaged flash */
 
-- 
cgit v0.10.2


From 5375389fe33cc55b6c5813a9fd665f6eee52aff9 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 6 Apr 2016 20:28:03 +0200
Subject: kconfig: Move CONFIG_OF_LIBFDT to Kconfig

This patch follows work done by:
"Move CONFIG_OF_LIBFDT to Kconfig"
(sha1: 69e173eb57d1f4848f070c83456096ba5d2ba1b4)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Add xpress* to the patch]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index d838baa..22fd057 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -10,3 +10,5 @@ CONFIG_AUTOBOOT_STOP_STR="l"
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index 39ce550..1448514 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -12,3 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 7cfed4a..07aa874 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -7,3 +7,5 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 033d32b..fb2e7b2 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -4,3 +4,4 @@ CONFIG_TARGET_XPRESS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index c2b1075..4ac7ef0 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -5,3 +5,4 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index 2977ccc..d2fa63d 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -1,7 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ZIPITZ2=y
+CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 79fa3c4..0bc9d2d 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -160,7 +160,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
 #define CONFIG_MX_CYCLIC
-#define CONFIG_OF_LIBFDT
 
 /*
  * Linux Information
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index e061a10..8a80b95 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -150,7 +150,6 @@
 #define CONFIG_LOADADDR		0x20800000
 #define CONFIG_BOOTCOMMAND	"run mmc_mmc"
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
-#define CONFIG_OF_LIBFDT
 
 /*
  * Extra Environments
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 78faaec..fccfb48 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -92,11 +92,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-/*
- * Handover flattened device tree (dtb file) to Linux kernel
- */
-#define CONFIG_OF_LIBFDT	1
-
 /*-----------------------------------------------------------------------
  * SDHC Configuration
  */
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 807ab65..e94812b 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -11,7 +11,6 @@
 #define CONFIG_SYS_THUMB_BUILD
 /*#define CONFIG_SYS_NO_FLASH*/
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_SYS_FLASH_BASE		0x08000000
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index d01d88b..831b940 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -101,7 +101,6 @@
 #define CONFIG_SYS_NO_FLASH
 #endif
 
-#define CONFIG_OF_LIBFDT       1
 #define CONFIG_BAUDRATE			115200
 /* The following table includes the supported baudrates */
 # define CONFIG_SYS_BAUDRATE_TABLE \
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 9bc536b..dc7a75b 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -77,7 +77,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		1	/* boot parition */
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC2 */
 
-#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_BMODE
 #define CONFIG_CMD_CACHE
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 5200e02..46836d5 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -45,7 +45,6 @@
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_SYS_TEXT_BASE		0x0
 #define	CONFIG_LZMA			/* LZMA compression support */
-#define	CONFIG_OF_LIBFDT
 
 /*
  * Serial Console Configuration
-- 
cgit v0.10.2


From 23922e2676ba901c0fd574a7e8df5eed0e084a97 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 6 Apr 2016 20:28:04 +0200
Subject: cmd: fdt: Use separate CMD_FDT Kconfig entry instead of OF_LIBFDT

Create CMD_FDT Kconfig entry to have an option to disable fdt command
which is not required for small configuration which requires libfdt
only.
Enable it by default for all targets which enables OF_LIBFDT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Fixup flea3/sandbox/id8313/siemens-am33xx/smartweb]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/Kconfig b/cmd/Kconfig
index fe8b4f0..8703cdb 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -173,6 +173,13 @@ config CMD_ELF
 	help
 	  Boot an ELF/vxWorks image from the memory.
 
+config CMD_FDT
+	bool "Flattened Device Tree utility commands"
+	default y
+	depends on OF_LIBFDT
+	help
+	  Do FDT related setup before booting into the Operating System.
+
 config CMD_GO
 	bool "go"
 	default y
diff --git a/cmd/Makefile b/cmd/Makefile
index ba04197..f95759e 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -54,7 +54,7 @@ obj-$(CONFIG_CMD_EXT4) += ext4.o
 obj-$(CONFIG_CMD_EXT2) += ext2.o
 obj-$(CONFIG_CMD_FAT) += fat.o
 obj-$(CONFIG_CMD_FDC) += fdc.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_CMD_FDT) += fdt.o
 obj-$(CONFIG_CMD_FITUPD) += fitupd.o
 obj-$(CONFIG_CMD_FLASH) += flash.o
 ifdef CONFIG_FPGA
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 3e4aaf6..15905b9 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -250,7 +250,4 @@
 		"else echo U-Boot not downloaded..exiting;fi\0"		\
 	"bootcmd=run net_nfs\0"
 
-/* Enable FIT images support */
-#define CONFIG_CMD_FDT
-
 #endif				/* __CONFIG_H */
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 5855d81..de51d10 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -559,7 +559,6 @@
 #define CONFIG_VERSION_VARIABLE
 
 #define CONFIG_IMAGE_FORMAT_LEGACY
-#define CONFIG_CMD_FDT
 #define CONFIG_CMD_HASH
 #define CONFIG_SHA1
 #define CONFIG_SHA256
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index cc22467..2dd7fc0 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -29,7 +29,6 @@
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
 
 #define CONFIG_LMB
-#define CONFIG_CMD_FDT
 #define CONFIG_ANDROID_BOOT_IMAGE
 
 #define CONFIG_CMD_PCI
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index df2a514..8ea31a6 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -623,7 +623,4 @@
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_BOOTCOUNT_ENV
 
-/* Enable Device-Tree (FDT) support */
-#define CONFIG_CMD_FDT
-
 #endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index db820ba..7dcb82b 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -240,8 +240,6 @@
 # undef CONFIG_CMD_NFS
 #endif /* CONFIG_MACB */
 
-#define CONFIG_CMD_FDT
-
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_INIT_SP_ADDR		0x301000
 #define CONFIG_SPL_STACK_R
-- 
cgit v0.10.2


From 7e52e11f3537809e48a6e337c392a1289a692061 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Wed, 6 Apr 2016 21:59:34 -0500
Subject: am57x: Move CONS_INDEX to Kconfig

- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and
      into Kconfig proper.
    - Edit the relevant am57x configs to remove the now unneeded
      CONFIG_SYS_EXTRA_OPTIONS.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig
index 17745ff..87654f9 100644
--- a/board/ti/am57xx/Kconfig
+++ b/board/ti/am57xx/Kconfig
@@ -9,6 +9,15 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "am57xx_evm"
 
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 3
+        help
+          The AM57x (and DRA7xx) SoC has a total of 6 UARTs available to it.
+          Depending on your specific board you may want something other than UART3
+          here.
+
 source "board/ti/common/Kconfig"
 
 endif
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 1090287..e40c24a 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -7,7 +7,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 7641db5..cb91719 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_BEAGLE_X15=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
-- 
cgit v0.10.2


From 5f405e7fa0c4baf4cc57a82d2fcddb86789cfaed Mon Sep 17 00:00:00 2001
From: Schuyler Patton <spatton@ti.com>
Date: Fri, 8 Apr 2016 16:53:44 -0500
Subject: board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

Update EMIF data based on recommendations from the now standard TI
EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
data sheet

Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different
bank, minus 1.

Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
clocks cycles for which SDRAM must remain in self refresh, minus 1.

Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index a5f02e6..02925f6 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -131,9 +131,9 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36ab,
+	.sdram_tim1		= 0xcccf36b3,
 	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x409f88a8,
+	.sdram_tim3		= 0x407f88a8,
 	.read_idle_ctrl		= 0x00050000,
 	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
-- 
cgit v0.10.2


From c020d355c45ed40fe12af72ae5487527167fafd5 Mon Sep 17 00:00:00 2001
From: Steve Kipisz <s-kipisz2@ti.com>
Date: Fri, 8 Apr 2016 17:01:29 -0500
Subject: board: ti: am57xx: Add support for am572x idk in SPL

The AM572x-IDK board (Industrial Dev Kit) is a board based on TI's AM5728x
SOC which has a dual core 1.5GHz A15 processor. This board is a development
platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector

The link to the data sheet and TRM can be found here:

http://www.ti.com/product/AM5728

NOTE: DT support is still pending upstream kernel acceptance but we
should be able to get the base system support with this patch.

Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 02925f6..1762089 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -35,6 +35,7 @@
 
 #define board_is_x15()		board_ti_is("BBRDX15_")
 #define board_is_am572x_evm()	board_ti_is("AM572PM_")
+#define board_is_am572x_idk()	board_ti_is("AM572IDK")
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
@@ -278,6 +279,8 @@ void do_board_detect(void)
 		bname = "BeagleBoard X15";
 	else if (board_is_am572x_evm())
 		bname = "AM572x EVM";
+	else if (board_is_am572x_idk())
+		bname = "AM572x IDK";
 
 	if (bname)
 		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
@@ -296,6 +299,8 @@ static void setup_board_eeprom_env(void)
 
 	if (board_is_am572x_evm())
 		name = "am57xx_evm";
+	else if (board_is_am572x_idk())
+		name = "am572x_idk";
 	else
 		printf("Unidentified board claims %s in eeprom header\n",
 		       board_ti_get_name());
@@ -343,9 +348,24 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_IODELAY_RECALIBRATION
 void recalibrate_iodelay(void)
 {
-	__recalibrate_iodelay(core_padconf_array_essential,
-			      ARRAY_SIZE(core_padconf_array_essential),
-			      iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
+	const struct pad_conf_entry *pconf;
+	const struct iodelay_cfg_entry *iod;
+	int pconf_sz, iod_sz;
+
+	if (board_is_am572x_idk()) {
+		pconf = core_padconf_array_essential_am572x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
+		iod = iodelay_cfg_array_am572x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+	} else {
+		/* Common for X15/GPEVM */
+		pconf = core_padconf_array_essential_x15;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
+		iod = iodelay_cfg_array_x15;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
+	}
+
+	__recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 }
 #endif
 
@@ -605,6 +625,12 @@ int board_eth_init(bd_t *bis)
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
 
+	/* The phy address for the AM572x IDK are different than x15 */
+	if (board_is_am572x_idk()) {
+		cpsw_data.slave_data[0].phy_addr = 0;
+		cpsw_data.slave_data[1].phy_addr = 1;
+	}
+
 	ret = cpsw_register(&cpsw_data);
 	if (ret < 0)
 		printf("Error %d registering CPSW switch\n", ret);
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index 3c007b7..b5ea8ad 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -12,7 +12,7 @@
 
 #include <asm/arch/mux_dra7xx.h>
 
-const struct pad_conf_entry core_padconf_array_essential[] = {
+const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
 	{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
 	{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
@@ -264,6 +264,222 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RTCK, (M0 | PIN_INPUT_PULLDOWN)},	/* rtck.rtck */
 };
 
+const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
+	{GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin4b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a1.vin4b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin4b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin4b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin4b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a5.vin4b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin4b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin4b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a8.vin4b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin4b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin4b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin4b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a12.vin4b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d8.gpio3_12 */
+	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
+	{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d13.gpio3_17 */
+	{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d15.gpio3_19 */
+	{VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d17.gpio3_21 */
+	{VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d18.gpio3_22 */
+	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
+	{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.ecap1 */
+	{VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.gpio4_4 */
+	{VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.gpio4_5 */
+	{VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.pr1_pru1_gpo2 */
+	{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.pr1_mii_mt1_clk */
+	{VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.pr1_mii_mii1_txen */
+	{VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.pr1_mii_mii1_txd3 */
+	{VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.pr1_mii_mii1_txd2 */
+	{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT)},		/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT)},		/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_INPUT)},		/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT)},		/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT)},		/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT)},		/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT)},		/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT)},		/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT)},		/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT)},		/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT)},		/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT)},		/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT)},		/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT)},		/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT)},		/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT)},		/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT)},		/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT)},		/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT)},		/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT)},		/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT)},		/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT)},		/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT)},		/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT)},		/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT)},		/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT)},		/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT)},		/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP)},	/* mdio_d.mdio_d */
+	{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)},	/* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
+	{UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.pr1_mii0_rxdv */
+	{UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.rp1_mii_mr0_clk */
+	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)},  /* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0  | PIN_OUTPUT_PULLUP)},  /* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)},	/* gpio6_16.gpio6)_16 */
+	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.i6_19 */
+	{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.gpio5_1 */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
+	{MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.pr2_pru1_gpo1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.pr2_pru1_gpo3 */
+	{MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr1.pr2_pru1_gpo4 */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
+	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},		/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs1.gpio7_11 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_OUTPUT)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
+	{UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart1_rxd.gpio7_22 */
+	{UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.gpio7_23 */
+	{I2C2_SDA, (M1 | PIN_INPUT)},		/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},		/* i2c2_scl.hdmi1_ddc_sda */
+	{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_INPUT_PULLUP)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT_PULLDOWN)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_INPUT)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT_PULLUP)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT_PULLUP)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_OUTPUT_PULLUP)},	/* resetn.resetn */
+	{RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rstoutn.rstoutn */
+};
+
 const struct pad_conf_entry early_padconf[] = {
 	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
 	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
@@ -272,7 +488,7 @@ const struct pad_conf_entry early_padconf[] = {
 };
 
 #ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
 	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
 	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
 	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
@@ -326,5 +542,53 @@ const struct iodelay_cfg_entry iodelay_cfg_array[] = {
 	{0x0AEC, 232, 1278},	/* CFG_VIN2A_D22_IN */
 	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
 };
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
+	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
+	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
+	{0x0138, 2605, 45},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},		/* CFG_GPMC_A13_IN */
+	{0x0150, 1976, 1389},	/* CFG_GPMC_A14_IN */
+	{0x015C, 1872, 1408},	/* CFG_GPMC_A15_IN */
+	{0x0168, 1914, 1506},	/* CFG_GPMC_A16_IN */
+	{0x0170, 57, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 1904, 1471},	/* CFG_GPMC_A17_IN */
+	{0x0188, 1690, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 2917, 0},	/* CFG_GPMC_A1_IN */
+	{0x0204, 3156, 178},	/* CFG_GPMC_A2_IN */
+	{0x0210, 3109, 246},	/* CFG_GPMC_A3_IN */
+	{0x021C, 3142, 100},	/* CFG_GPMC_A4_IN */
+	{0x0228, 3084, 33},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2778, 0},	/* CFG_GPMC_A6_IN */
+	{0x0240, 3110, 0},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2874, 0},	/* CFG_GPMC_A8_IN */
+	{0x0258, 3072, 0},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},		/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 201, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 229, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 141, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 495, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 660, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 65, 70},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 125, 70},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 0, 70},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 70},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 65, 70},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},		/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 612, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 4, 927},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 136, 1340},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 130, 1450},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 144, 1269},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1330},	/* CFG_VIN2A_D23_IN */
+};
 #endif
 #endif /* _MUX_DATA_BEAGLE_X15_H_ */
-- 
cgit v0.10.2


From ef9e6de5409535bde164f087c31ac865800cbf14 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:14 +0200
Subject: iso: Make little endian and 64bit safe

The iso partition table implementation has a few endian and 64bit
problems. Clean it up a bit to become endian and bitness safe.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/disk/part_iso.c b/disk/part_iso.c
index 2114faf..b7a5381 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -58,11 +58,9 @@ int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 				ppr->stand_ident, dev_desc->devnum, part_num);
 		return (-1);
 	}
-	lastsect= ((ppr->firstsek_LEpathtab1_LE & 0x000000ff)<<24) +
-		  ((ppr->firstsek_LEpathtab1_LE & 0x0000ff00)<< 8) +
-		  ((ppr->firstsek_LEpathtab1_LE & 0x00ff0000)>> 8) +
-		  ((ppr->firstsek_LEpathtab1_LE & 0xff000000)>>24) ;
-	info->blksz=ppr->secsize_BE; /* assuming same block size for all entries */
+	lastsect = le32_to_cpu(ppr->firstsek_LEpathtab1_LE);
+	/* assuming same block size for all entries */
+	info->blksz = be16_to_cpu(ppr->secsize_BE);
 	PRINTF(" Lastsect:%08lx\n",lastsect);
 	for(i=blkaddr;i<lastsect;i++) {
 		PRINTF("Reading block %d\n", i);
@@ -95,7 +93,7 @@ int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 	chksum=0;
 	chksumbuf = (unsigned short *)tmpbuf;
 	for(i=0;i<0x10;i++)
-		chksum+=((chksumbuf[i] &0xff)<<8)+((chksumbuf[i] &0xff00)>>8);
+		chksum += le16_to_cpu(chksumbuf[i]);
 	if(chksum!=0) {
 		if(verb)
 			printf("** Checksum Error in booting catalog validation entry on %d:%d **\n",
diff --git a/disk/part_iso.h b/disk/part_iso.h
index dace0f8..045784f 100644
--- a/disk/part_iso.h
+++ b/disk/part_iso.h
@@ -29,8 +29,8 @@ typedef struct iso_pri_rec {
 	char					sysid[32];		/* system Identifier */
 	char					volid[32];		/* volume Identifier */
 	unsigned char zeros1[8];		/* unused */
-	unsigned long volsiz_LE;		/* volume size Little Endian */
-	unsigned long volsiz_BE;		/* volume size Big Endian */
+	unsigned int volsiz_LE;		/* volume size Little Endian */
+	unsigned int volsiz_BE;		/* volume size Big Endian */
 	unsigned char zeros2[32];		/* unused */
 	unsigned short setsize_LE;	/* volume set size LE */
 	unsigned short setsize_BE;	/* volume set size BE */
@@ -38,12 +38,12 @@ typedef struct iso_pri_rec {
 	unsigned short seqnum_BE;		/* volume sequence number BE */
 	unsigned short secsize_LE;	/* sector size LE */
 	unsigned short secsize_BE;	/* sector size BE */
-	unsigned long pathtablen_LE;/* Path Table size LE */
-	unsigned long pathtablen_BE;/* Path Table size BE */
-	unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
-	unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
-	unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
-	unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
+	unsigned int pathtablen_LE;/* Path Table size LE */
+	unsigned int pathtablen_BE;/* Path Table size BE */
+	unsigned int firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
+	unsigned int firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
+	unsigned int firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
+	unsigned int firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
 	unsigned char rootdir[34];	/* directory record for root dir */
 	char					volsetid[128];/* Volume set identifier */
 	char					pubid[128];		/* Publisher identifier */
@@ -67,8 +67,8 @@ typedef struct iso_sup_rec {
 	char					sysid[32];		/* system Identifier */
 	char					volid[32];		/* volume Identifier */
 	unsigned char zeros1[8];		/* unused */
-	unsigned long volsiz_LE;		/* volume size Little Endian */
-	unsigned long volsiz_BE;		/* volume size Big Endian */
+	unsigned int volsiz_LE;		/* volume size Little Endian */
+	unsigned int volsiz_BE;		/* volume size Big Endian */
 	unsigned char escapeseq[32];/* Escape sequences */
 	unsigned short setsize_LE;	/* volume set size LE */
 	unsigned short setsize_BE;	/* volume set size BE */
@@ -76,12 +76,12 @@ typedef struct iso_sup_rec {
 	unsigned short seqnum_BE;		/* volume sequence number BE */
 	unsigned short secsize_LE;	/* sector size LE */
 	unsigned short secsize_BE;	/* sector size BE */
-	unsigned long pathtablen_LE;/* Path Table size LE */
-	unsigned long pathtablen_BE;/* Path Table size BE */
-	unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
-	unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
-	unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
-	unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
+	unsigned int pathtablen_LE;/* Path Table size LE */
+	unsigned int pathtablen_BE;/* Path Table size BE */
+	unsigned int firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
+	unsigned int firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
+	unsigned int firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
+	unsigned int firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
 	unsigned char rootdir[34];	/* directory record for root dir */
 	char					volsetid[128];/* Volume set identifier */
 	char					pubid[128];		/* Publisher identifier */
@@ -104,10 +104,10 @@ typedef struct iso_part_rec {
 	unsigned char unused;
 	char					sysid[32];		 /* system Identifier */
 	char					volid[32];		/* volume partition Identifier */
-	unsigned long partloc_LE;		/* volume partition location LE */
-	unsigned long partloc_BE;		/* volume partition location BE */
-	unsigned long partsiz_LE;		/* volume partition size LE */
-	unsigned long partsiz_BE;		/* volume partition size BE */
+	unsigned int partloc_LE;		/* volume partition location LE */
+	unsigned int partloc_BE;		/* volume partition location BE */
+	unsigned int partsiz_LE;		/* volume partition size LE */
+	unsigned int partsiz_BE;		/* volume partition size BE */
 }iso_part_rec_t;
 
 
-- 
cgit v0.10.2


From 2579c67478b9606ae7ff1370165e9f222fe19950 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:15 +0200
Subject: iso: Start with partition 1

The generic partition code treats partition 0 as "whole disk". So
we should start with partition 1 as the first partition in the iso
partition table.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/disk/part_iso.c b/disk/part_iso.c
index b7a5381..5adb349 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -115,7 +115,7 @@ int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 	}
 #endif
 	/* the validation entry seems to be ok, now search the "partition" */
-	entry_num=0;
+	entry_num=1;
 	offset=0x20;
 	strcpy((char *)info->type, "U-Boot");
 	switch(dev_desc->if_type) {
@@ -225,7 +225,7 @@ static int part_test_iso(struct blk_desc *dev_desc)
 {
 	disk_partition_t info;
 
-	return part_get_info_iso_verb(dev_desc, 0, &info, 0);
+	return part_get_info_iso_verb(dev_desc, 1, &info, 1);
 }
 
 U_BOOT_PART_TYPE(iso) = {
-- 
cgit v0.10.2


From a2adb173ec1551ce8a2081085d20d82162f7900d Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:16 +0200
Subject: iso: Allow 512 byte sector size

Real CD-ROMs are pretty obsolete these days. Usually people still keep
iso files around, but just put them on USB sticks or SD cards and expect
them to "just work".

To support this use case with El Torito images, add support for 512 byte
sector size to the iso parsing code.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/disk/part_iso.c b/disk/part_iso.c
index 5adb349..9f5c50c 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -26,6 +26,25 @@
 
 static unsigned char tmpbuf[CD_SECTSIZE];
 
+unsigned long iso_dread(struct blk_desc *block_dev, lbaint_t start,
+                        lbaint_t blkcnt, void *buffer)
+{
+	unsigned long ret;
+
+	if (block_dev->blksz == 512) {
+		/* Convert from 2048 to 512 sector size */
+		start *= 4;
+		blkcnt *= 4;
+	}
+
+	ret = blk_dread(block_dev, start, blkcnt, buffer);
+
+	if (block_dev->blksz == 512)
+		ret /= 4;
+
+	return ret;
+}
+
 /* only boot records will be listed as valid partitions */
 int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 			   disk_partition_t *info, int verb)
@@ -39,12 +58,12 @@ int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 	iso_val_entry_t *pve = (iso_val_entry_t *)tmpbuf;
 	iso_init_def_entry_t *pide;
 
-	if (dev_desc->blksz != CD_SECTSIZE)
+	if ((dev_desc->blksz != CD_SECTSIZE) && (dev_desc->blksz != 512))
 		return -1;
 
 	/* the first sector (sector 0x10) must be a primary volume desc */
 	blkaddr=PVD_OFFSET;
-	if (blk_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+	if (iso_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
 		return -1;
 	if(ppr->desctype!=0x01) {
 		if(verb)
@@ -64,7 +83,7 @@ int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 	PRINTF(" Lastsect:%08lx\n",lastsect);
 	for(i=blkaddr;i<lastsect;i++) {
 		PRINTF("Reading block %d\n", i);
-		if (blk_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+		if (iso_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
 			return -1;
 		if(ppr->desctype==0x00)
 			break; /* boot entry found */
@@ -84,7 +103,7 @@ int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
 	}
 	bootaddr = get_unaligned_le32(pbr->pointer);
 	PRINTF(" Boot Entry at: %08lX\n",bootaddr);
-	if (blk_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
+	if (iso_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
 		if(verb)
 			printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
 				bootaddr, dev_desc->devnum, part_num);
@@ -192,7 +211,14 @@ found:
 	}
 	newblkaddr = get_unaligned_le32(pide->rel_block_addr);
 	info->start=newblkaddr;
-	PRINTF(" part %d found @ %lx size %lx\n",part_num,newblkaddr,info->size);
+
+	if (dev_desc->blksz == 512) {
+		info->size *= 4;
+		info->start *= 4;
+		info->blksz = 512;
+	}
+
+	PRINTF(" part %d found @ %lx size %lx\n",part_num,info->start,info->size);
 	return 0;
 }
 
-- 
cgit v0.10.2


From 4a12a97c14217a5b02791040e464449f779fce43 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:17 +0200
Subject: efi_loader: Split drive add into function

The snippet of code to add a drive to our drive list needs to
get called from 2 places in the future. Split it into a separate
function.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index aaff947..e30e728 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -138,6 +138,52 @@ static const struct efi_block_io block_io_disk_template = {
 	.flush_blocks = &efi_disk_flush_blocks,
 };
 
+static void efi_disk_add_dev(char *name,
+			     const struct block_drvr *cur_drvr,
+			     const struct blk_desc *desc,
+			     int dev_index,
+			     lbaint_t offset)
+{
+	struct efi_disk_obj *diskobj;
+	struct efi_device_path_file_path *dp;
+	int objlen = sizeof(*diskobj) + (sizeof(*dp) * 2);
+
+	diskobj = calloc(1, objlen);
+
+	/* Fill in object data */
+	diskobj->parent.protocols[0].guid = &efi_block_io_guid;
+	diskobj->parent.protocols[0].open = efi_disk_open_block;
+	diskobj->parent.protocols[1].guid = &efi_guid_device_path;
+	diskobj->parent.protocols[1].open = efi_disk_open_dp;
+	diskobj->parent.handle = diskobj;
+	diskobj->ops = block_io_disk_template;
+	diskobj->ifname = cur_drvr->name;
+	diskobj->dev_index = dev_index;
+
+	/* Fill in EFI IO Media info (for read/write callbacks) */
+	diskobj->media.removable_media = desc->removable;
+	diskobj->media.media_present = 1;
+	diskobj->media.block_size = desc->blksz;
+	diskobj->media.io_align = desc->blksz;
+	diskobj->media.last_block = desc->lba;
+	diskobj->ops.media = &diskobj->media;
+
+	/* Fill in device path */
+	dp = (void*)&diskobj[1];
+	diskobj->dp = dp;
+	dp[0].dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
+	dp[0].dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH;
+	dp[0].dp.length = sizeof(*dp);
+	ascii2unicode(dp[0].str, name);
+
+	dp[1].dp.type = DEVICE_PATH_TYPE_END;
+	dp[1].dp.sub_type = DEVICE_PATH_SUB_TYPE_END;
+	dp[1].dp.length = sizeof(*dp);
+
+	/* Hook up to the device list */
+	list_add_tail(&diskobj->parent.link, &efi_obj_list);
+}
+
 /*
  * U-Boot doesn't have a list of all online disk devices. So when running our
  * EFI payload, we scan through all of the potentially available ones and
@@ -156,9 +202,6 @@ int efi_disk_register(void)
 		printf("Scanning disks on %s...\n", cur_drvr->name);
 		for (i = 0; i < 4; i++) {
 			struct blk_desc *desc;
-			struct efi_disk_obj *diskobj;
-			struct efi_device_path_file_path *dp;
-			int objlen = sizeof(*diskobj) + (sizeof(*dp) * 2);
 			char devname[16] = { 0 }; /* dp->str is u16[16] long */
 
 			desc = blk_get_dev(cur_drvr->name, i);
@@ -167,42 +210,9 @@ int efi_disk_register(void)
 			if (desc->type == DEV_TYPE_UNKNOWN)
 				continue;
 
-			diskobj = calloc(1, objlen);
-
-			/* Fill in object data */
-			diskobj->parent.protocols[0].guid = &efi_block_io_guid;
-			diskobj->parent.protocols[0].open = efi_disk_open_block;
-			diskobj->parent.protocols[1].guid = &efi_guid_device_path;
-			diskobj->parent.protocols[1].open = efi_disk_open_dp;
-			diskobj->parent.handle = diskobj;
-			diskobj->ops = block_io_disk_template;
-			diskobj->ifname = cur_drvr->name;
-			diskobj->dev_index = i;
-
-			/* Fill in EFI IO Media info (for read/write callbacks) */
-			diskobj->media.removable_media = desc->removable;
-			diskobj->media.media_present = 1;
-			diskobj->media.block_size = desc->blksz;
-			diskobj->media.io_align = desc->blksz;
-			diskobj->media.last_block = desc->lba;
-			diskobj->ops.media = &diskobj->media;
-
-			/* Fill in device path */
-			dp = (void*)&diskobj[1];
-			diskobj->dp = dp;
-			dp[0].dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
-			dp[0].dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH;
-			dp[0].dp.length = sizeof(*dp);
 			snprintf(devname, sizeof(devname), "%s%d",
 				 cur_drvr->name, i);
-			ascii2unicode(dp[0].str, devname);
-
-			dp[1].dp.type = DEVICE_PATH_TYPE_END;
-			dp[1].dp.sub_type = DEVICE_PATH_SUB_TYPE_END;
-			dp[1].dp.length = sizeof(*dp);
-
-			/* Hook up to the device list */
-			list_add_tail(&diskobj->parent.link, &efi_obj_list);
+			efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
 			disks++;
 		}
 	}
-- 
cgit v0.10.2


From 8c3df0bf2e530c6e6f592f5144ef4f456c9e0260 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:18 +0200
Subject: efi_loader: Add el torito support

When loading an el torito image, uEFI exposes said image as a raw
block device to the payload.

Let's do the same by creating new block devices with added offsets for
the respective el torito partitions.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 3add632..0d09aa1 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -194,12 +194,26 @@ U_BOOT_CMD(
 
 void efi_set_bootdev(const char *dev, const char *devnr)
 {
+	__maybe_unused struct blk_desc *desc;
 	char devname[16] = { 0 }; /* dp->str is u16[16] long */
 	char *colon;
 
 	/* Assemble the condensed device name we use in efi_disk.c */
 	snprintf(devname, sizeof(devname), "%s%s", dev, devnr);
 	colon = strchr(devname, ':');
+
+#ifdef CONFIG_ISO_PARTITION
+	/* For ISOs we create partition block devices */
+	desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
+	if (desc && (desc->type != DEV_TYPE_UNKNOWN) &&
+	    (desc->part_type == PART_TYPE_ISO)) {
+		if (!colon)
+			snprintf(devname, sizeof(devname), "%s%s:1", dev,
+				 devnr);
+		colon = NULL;
+	}
+#endif
+
 	if (colon)
 		*colon = '\0';
 
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index e30e728..b3d56a8 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -27,6 +27,8 @@ struct efi_disk_obj {
 	struct efi_block_io_media media;
 	/* EFI device path to this block device */
 	struct efi_device_path_file_path *dp;
+	/* Offset into disk for simple partitions */
+	lbaint_t offset;
 };
 
 static efi_status_t efi_disk_open_block(void *handle, efi_guid_t *protocol,
@@ -81,6 +83,7 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 	blksz = desc->blksz;
 	blocks = buffer_size / blksz;
+	lba += diskobj->offset;
 
 #ifdef DEBUG_EFI
 	printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
@@ -159,6 +162,7 @@ static void efi_disk_add_dev(char *name,
 	diskobj->ops = block_io_disk_template;
 	diskobj->ifname = cur_drvr->name;
 	diskobj->dev_index = dev_index;
+	diskobj->offset = offset;
 
 	/* Fill in EFI IO Media info (for read/write callbacks) */
 	diskobj->media.removable_media = desc->removable;
@@ -184,6 +188,31 @@ static void efi_disk_add_dev(char *name,
 	list_add_tail(&diskobj->parent.link, &efi_obj_list);
 }
 
+static int efi_disk_create_eltorito(struct blk_desc *desc,
+				    const struct block_drvr *cur_drvr,
+				    int diskid)
+{
+	int disks = 0;
+#ifdef CONFIG_ISO_PARTITION
+	char devname[16] = { 0 }; /* dp->str is u16[16] long */
+	disk_partition_t info;
+	int part = 1;
+
+	if (desc->part_type != PART_TYPE_ISO)
+		return 0;
+
+	while (!part_get_info(desc, part, &info)) {
+		snprintf(devname, sizeof(devname), "%s%d:%d", cur_drvr->name,
+			 diskid, part);
+		efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
+		part++;
+		disks++;
+	}
+#endif
+
+	return disks;
+}
+
 /*
  * U-Boot doesn't have a list of all online disk devices. So when running our
  * EFI payload, we scan through all of the potentially available ones and
@@ -214,6 +243,12 @@ int efi_disk_register(void)
 				 cur_drvr->name, i);
 			efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
 			disks++;
+
+			/*
+			 * El Torito images show up as block devices
+			 * in an EFI world, so let's create them here
+			 */
+			disks += efi_disk_create_eltorito(desc, cur_drvr, i);
 		}
 	}
 	printf("Found %d disks\n", disks);
-- 
cgit v0.10.2


From c07ad7c03588ab7b8f87b6567ac9202cf32b9bbe Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:19 +0200
Subject: efi_loader: Pass file path to payload

The payload gets information on where it got loaded from. This includes
the device as well as file path.

So far we've treated both as the same thing and always gave it the device
name. However, in some situations grub2 actually wants to find its loading
path to find its configuration file.

So let's split the two semantically separte bits into separate structs and
pass the loaded file name into our payload when we load it using "load".

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 0d09aa1..adcf645 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -34,17 +34,30 @@ static struct efi_device_path_file_path bootefi_image_path[] = {
 	}
 };
 
+static struct efi_device_path_file_path bootefi_device_path[] = {
+	{
+		.dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+		.dp.length = sizeof(bootefi_image_path[0]),
+		.str = { 'b','o','o','t','e','f','i' },
+	}, {
+		.dp.type = DEVICE_PATH_TYPE_END,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+		.dp.length = sizeof(bootefi_image_path[0]),
+	}
+};
+
 static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
 			void **protocol_interface, void *agent_handle,
 			void *controller_handle, uint32_t attributes)
 {
-	*protocol_interface = bootefi_image_path;
+	*protocol_interface = bootefi_device_path;
 	return EFI_SUCCESS;
 }
 
 /* The EFI loaded_image interface for the image executed via "bootefi" */
 static struct efi_loaded_image loaded_image_info = {
-	.device_handle = bootefi_image_path,
+	.device_handle = bootefi_device_path,
 	.file_path = bootefi_image_path,
 };
 
@@ -63,7 +76,7 @@ static struct efi_object loaded_image_info_obj = {
 		{
 			/*
 			 * When asking for the device path interface, return
-			 * bootefi_image_path
+			 * bootefi_device_path
 			 */
 			.guid = &efi_guid_device_path,
 			.open = &bootefi_open_dp,
@@ -73,11 +86,11 @@ static struct efi_object loaded_image_info_obj = {
 
 /* The EFI object struct for the device the "bootefi" image was loaded from */
 static struct efi_object bootefi_device_obj = {
-	.handle = bootefi_image_path,
+	.handle = bootefi_device_path,
 	.protocols = {
 		{
 			/* When asking for the device path interface, return
-			 * bootefi_image_path */
+			 * bootefi_device_path */
 			.guid = &efi_guid_device_path,
 			.open = &bootefi_open_dp,
 		}
@@ -192,7 +205,7 @@ U_BOOT_CMD(
 	bootefi_help_text
 );
 
-void efi_set_bootdev(const char *dev, const char *devnr)
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
 {
 	__maybe_unused struct blk_desc *desc;
 	char devname[16] = { 0 }; /* dp->str is u16[16] long */
@@ -217,7 +230,12 @@ void efi_set_bootdev(const char *dev, const char *devnr)
 	if (colon)
 		*colon = '\0';
 
-	/* Patch the bootefi_image_path to the target device */
+	/* Patch bootefi_device_path to the target device */
+	memset(bootefi_device_path[0].str, 0, sizeof(bootefi_device_path[0].str));
+	ascii2unicode(bootefi_device_path[0].str, devname);
+
+	/* Patch bootefi_image_path to the target file path */
 	memset(bootefi_image_path[0].str, 0, sizeof(bootefi_image_path[0].str));
+	snprintf(devname, sizeof(devname), "%s", path);
 	ascii2unicode(bootefi_image_path[0].str, devname);
 }
diff --git a/cmd/fs.c b/cmd/fs.c
index be8f289..abfe5be 100644
--- a/cmd/fs.c
+++ b/cmd/fs.c
@@ -27,7 +27,8 @@ U_BOOT_CMD(
 static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
 				char * const argv[])
 {
-	efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "");
+	efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
+			(argc > 4) ? argv[4] : "");
 	return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
 }
 
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 9f61fc4..88b8149 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -112,7 +112,7 @@ efi_status_t efi_exit_func(efi_status_t ret);
 /* Call this to relocate the runtime section to an address space */
 void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
 /* Call this to set the current device name */
-void efi_set_bootdev(const char *dev, const char *devnr);
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
 
 /* Generic EFI memory allocator, call this to get memory */
 void *efi_alloc(uint64_t len, int memory_type);
@@ -155,6 +155,7 @@ static inline void ascii2unicode(u16 *unicode, char *ascii)
 
 /* No loader configured, stub out EFI_ENTRY */
 static inline void efi_restore_gd(void) { }
-static inline void efi_set_bootdev(const char *dev, const char *devnr) { }
+static inline void efi_set_bootdev(const char *dev, const char *devnr,
+				   const char *path) { }
 
 #endif
-- 
cgit v0.10.2


From ecbe1a07c507d37aeb5f0f9ce1c4cc20c70fec64 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:20 +0200
Subject: efi_loader: Increase path string to 32 characters

Whenever we want to tell our payload about a path, we limit ourselves
to a reasonable amount of characters. So far we only passed in device
names - exceeding 16 chars was unlikely there.

However by now we also pass real file path information, so let's increase
the limit to 32 characters. That way common paths like "boot/efi/bootaa64.efi"
fit just fine.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index adcf645..f502996 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -208,7 +208,7 @@ U_BOOT_CMD(
 void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
 {
 	__maybe_unused struct blk_desc *desc;
-	char devname[16] = { 0 }; /* dp->str is u16[16] long */
+	char devname[32] = { 0 }; /* dp->str is u16[32] long */
 	char *colon;
 
 	/* Assemble the condensed device name we use in efi_disk.c */
diff --git a/include/efi_api.h b/include/efi_api.h
index 6960448..51d7586 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -259,7 +259,7 @@ struct efi_device_path {
 
 struct efi_device_path_file_path {
 	struct efi_device_path dp;
-	u16 str[16];
+	u16 str[32];
 };
 
 #define BLOCK_IO_GUID \
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index b3d56a8..28e5b7f 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -194,7 +194,7 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
 {
 	int disks = 0;
 #ifdef CONFIG_ISO_PARTITION
-	char devname[16] = { 0 }; /* dp->str is u16[16] long */
+	char devname[32] = { 0 }; /* dp->str is u16[32] long */
 	disk_partition_t info;
 	int part = 1;
 
@@ -231,7 +231,7 @@ int efi_disk_register(void)
 		printf("Scanning disks on %s...\n", cur_drvr->name);
 		for (i = 0; i < 4; i++) {
 			struct blk_desc *desc;
-			char devname[16] = { 0 }; /* dp->str is u16[16] long */
+			char devname[32] = { 0 }; /* dp->str is u16[32] long */
 
 			desc = blk_get_dev(cur_drvr->name, i);
 			if (!desc)
-- 
cgit v0.10.2


From 578ec3b1fb3f4e85d8243d442f66f308c94b791d Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:16:21 +0200
Subject: distro: Enable iso partition code

Now that we can properly boot EFI payloads from iso el torito
images, let's enable support for isos by default in the distro
header.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 2ba7cf4..076be4d 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -62,6 +62,7 @@
 #define CONFIG_MENU
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
+#define CONFIG_ISO_PARTITION
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_SYS_HUSH_PARSER
 
-- 
cgit v0.10.2


From 0d9d501f359d82c19fc1d5a800888feadc82c1fe Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 16:55:26 +0200
Subject: efi_loader: Use system fdt as fallback
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When the user did not pass any device tree or the boot script
didn't find any, let's use the system device tree as last resort
to get something the payload (Linux) may understand.

This means that on systems that use the same device tree for U-Boot
and Linux we can just share it and there's no need to manually provide
a device tree in the target image.

While at it, also copy and pad the device tree by 64kb to give us
space for modifications.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Andreas Färber <afaerber@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index f502996..9b8af65 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -12,6 +12,10 @@
 #include <errno.h>
 #include <libfdt.h>
 #include <libfdt_env.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * When booting using the "bootefi" command, we don't know which
@@ -97,6 +101,21 @@ static struct efi_object bootefi_device_obj = {
 	},
 };
 
+static void *copy_fdt(void *fdt)
+{
+	u64 fdt_size = fdt_totalsize(fdt);
+	void *new_fdt;
+
+	/* Give us 64kb breathing room */
+	fdt_size += 64 * 1024;
+
+	new_fdt = malloc(fdt_size);
+	memcpy(new_fdt, fdt, fdt_totalsize(fdt));
+	fdt_set_totalsize(new_fdt, fdt_size);
+
+	return new_fdt;
+}
+
 /*
  * Load an EFI payload into a newly allocated piece of memory, register all
  * EFI objects it would want to access and jump to it.
@@ -106,6 +125,7 @@ static unsigned long do_bootefi_exec(void *efi)
 	ulong (*entry)(void *image_handle, struct efi_system_table *st);
 	ulong fdt_pages, fdt_size, fdt_start, fdt_end;
 	bootm_headers_t img = { 0 };
+	void *fdt = working_fdt;
 
 	/*
 	 * gd lives in a fixed register which may get clobbered while we execute
@@ -115,28 +135,33 @@ static unsigned long do_bootefi_exec(void *efi)
 
 	/* Update system table to point to our currently loaded FDT */
 
-	if (working_fdt) {
+	/* Fall back to included fdt if none was manually loaded */
+	if (!fdt && gd->fdt_blob)
+		fdt = (void *)gd->fdt_blob;
+
+	if (fdt) {
 		/* Prepare fdt for payload */
-		if (image_setup_libfdt(&img, working_fdt, 0, NULL)) {
+		fdt = copy_fdt(fdt);
+
+		if (image_setup_libfdt(&img, fdt, 0, NULL)) {
 			printf("ERROR: Failed to process device tree\n");
 			return -EINVAL;
 		}
 
 		/* Link to it in the efi tables */
 		systab.tables[0].guid = EFI_FDT_GUID;
-		systab.tables[0].table = working_fdt;
+		systab.tables[0].table = fdt;
 		systab.nr_tables = 1;
 
 		/* And reserve the space in the memory map */
-		fdt_start = ((ulong)working_fdt) & ~EFI_PAGE_MASK;
-		fdt_end = ((ulong)working_fdt) + fdt_totalsize(working_fdt);
+		fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
+		fdt_end = ((ulong)fdt) + fdt_totalsize(fdt);
 		fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
 		fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
 		/* Give a bootloader the chance to modify the device tree */
 		fdt_pages += 2;
 		efi_add_memory_map(fdt_start, fdt_pages,
 				   EFI_BOOT_SERVICES_DATA, true);
-
 	} else {
 		printf("WARNING: No device tree loaded, expect boot to fail\n");
 		systab.nr_tables = 0;
-- 
cgit v0.10.2


From 50c5d43cb4f5611dda478f3f53f68fc991c0bef2 Mon Sep 17 00:00:00 2001
From: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Date: Mon, 11 Apr 2016 22:45:46 +0200
Subject: dragonboard410c: Add CONFIG_SYS_CACHELINE_SIZE
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add missing define to board header file.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>

diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index a63440f..26f95a7 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -27,6 +27,8 @@
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
 #define CONFIG_SYS_BOOTM_LEN		0x1000000 /* 16MB max kernel size */
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* UART */
 #define CONFIG_BAUDRATE			115200
 
-- 
cgit v0.10.2


From 36c37a8481551a6958fd91ccafc6936bf81e00f3 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 23:20:39 +0200
Subject: efi_loader: Always flush in cache line size granularity
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The cache line flush helpers only work properly when they get aligned
start and end addresses. Round our flush range to cache line size. It's
safe because we're guaranteed to flush within a single page which has the
same cache attributes.

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: Andreas Färber <afaerber@suse.de>

diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 22bcd08..3ee27ca 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -20,6 +20,13 @@ static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_unimplemented(void);
 static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_device_error(void);
 static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_invalid_parameter(void);
 
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+#else
+/* Just use the greatest cache flush alignment requirement I'm aware of */
+#define EFI_CACHELINE_SIZE 128
+#endif
+
 #if defined(CONFIG_ARM64)
 #define R_RELATIVE	1027
 #define R_MASK		0xffffffffULL
@@ -194,7 +201,8 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
 #endif
 
 		*p = newaddr;
-		flush_dcache_range((ulong)p, (ulong)&p[1]);
+		flush_dcache_range((ulong)p & ~(EFI_CACHELINE_SIZE - 1),
+			ALIGN((ulong)&p[1], EFI_CACHELINE_SIZE));
 	}
 
 #ifndef IS_RELA
-- 
cgit v0.10.2


From ad0c1a3d2cea03011091b07e9e066bf261d1556e Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 23:51:01 +0200
Subject: efi_loader: Put fdt into convenient location
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The uEFI spec doesn't dictate where the device tree should live at, but
legacy 32bit ARM grub2 has some assumptions that it may stay at its place
when it's already loaded by the firmware.

So let's put it somewhere where Linux that comes after would happily find
it - around the recommended 128MB line.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Andreas Färber <afaerber@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 9b8af65..b213ef1 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -12,7 +12,7 @@
 #include <errno.h>
 #include <libfdt.h>
 #include <libfdt_env.h>
-#include <malloc.h>
+#include <memalign.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -104,12 +104,34 @@ static struct efi_object bootefi_device_obj = {
 static void *copy_fdt(void *fdt)
 {
 	u64 fdt_size = fdt_totalsize(fdt);
+	unsigned long fdt_ram_start = -1L, fdt_pages;
+	u64 new_fdt_addr;
 	void *new_fdt;
+	int i;
 
-	/* Give us 64kb breathing room */
-	fdt_size += 64 * 1024;
+        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+                u64 ram_start = gd->bd->bi_dram[i].start;
+                u64 ram_size = gd->bd->bi_dram[i].size;
 
-	new_fdt = malloc(fdt_size);
+		if (!ram_size)
+			continue;
+
+		if (ram_start < fdt_ram_start)
+			fdt_ram_start = ram_start;
+	}
+
+	/* Give us at least 4kb breathing room */
+	fdt_size = ALIGN(fdt_size + 4096, 4096);
+	fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
+
+	/* Safe fdt location is at 128MB */
+	new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size;
+	if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+			       &new_fdt_addr) != EFI_SUCCESS) {
+		/* If we can't put it there, put it somewhere */
+		new_fdt_addr = (ulong)memalign(4096, fdt_size);
+	}
+	new_fdt = (void*)(ulong)new_fdt_addr;
 	memcpy(new_fdt, fdt, fdt_totalsize(fdt));
 	fdt_set_totalsize(new_fdt, fdt_size);
 
-- 
cgit v0.10.2


From cee752fa8dcf3b589baf7141011675a0c3f2ded6 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 11 Apr 2016 23:51:02 +0200
Subject: efi_loader: Expose ascending efi memory map
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The EFI memory map does not need to be in a strict order, but 32bit
grub2 does expect it to be ascending. If it's not, it may try to
allocate memory inside the U-Boot data memory region.

We already sort the memory map in descending order, so let's just
reverse it when we pass it to a payload.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Andreas Färber <afaerber@suse.de>

diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 8a1e249..df99585 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -286,10 +286,13 @@ efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
 			       uint32_t *descriptor_version)
 {
 	ulong map_size = 0;
+	int map_entries = 0;
 	struct list_head *lhandle;
 
 	list_for_each(lhandle, &efi_mem)
-		map_size += sizeof(struct efi_mem_desc);
+		map_entries++;
+
+	map_size = map_entries * sizeof(struct efi_mem_desc);
 
 	*memory_map_size = map_size;
 
@@ -301,12 +304,14 @@ efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
 
 	/* Copy list into array */
 	if (memory_map) {
+		/* Return the list in ascending order */
+		memory_map = &memory_map[map_entries - 1];
 		list_for_each(lhandle, &efi_mem) {
 			struct efi_mem_list *lmem;
 
 			lmem = list_entry(lhandle, struct efi_mem_list, link);
 			*memory_map = lmem->desc;
-			memory_map++;
+			memory_map--;
 		}
 	}
 
-- 
cgit v0.10.2


From 6a3bf3e57149dcfdb447590049ef6cad6cf7258b Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Mon, 11 Apr 2016 15:21:37 -0700
Subject: gunzip.c: use block layer for writes

Call blk_dwrite to ensure that the block cache is notified
if enabled and remove build breakage when CONFIG_BLK is enabled.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/lib/gunzip.c b/lib/gunzip.c
index 6d65ccc..bc746d6 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -232,9 +232,8 @@ int gzwrite(unsigned char *src, int len,
 			gzwrite_progress(iteration++,
 					 totalfilled,
 					 szexpected);
-			blocks_written = dev->block_write(dev, outblock,
-							  writeblocks,
-							  writebuf);
+			blocks_written = blk_dwrite(dev, outblock,
+						    writeblocks, writebuf);
 			outblock += blocks_written;
 			if (ctrlc()) {
 				puts("abort\n");
-- 
cgit v0.10.2


From 55ac54c4a0acbdc786b16dc1b12a661f9dbdb305 Mon Sep 17 00:00:00 2001
From: "angelo@sysam.it" <angelo@sysam.it>
Date: Tue, 12 Apr 2016 00:30:59 +0200
Subject: m68k: fix broken buildman m68k

fix 19/48 broken board compilations, due to a now too smal 16-bit
relative jump

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 8a23e72..1702f98 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -141,8 +141,12 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 8a59496..4af691f 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -198,8 +198,12 @@ _after_flashbar_copy:
 
 	move.l #__got_start, %a5		/* put relocation table address to a5 */
 
-	bsr cpu_init_f				/* run low-level CPU init code (from flash) */
-	bsr board_init_f			/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 3b9ede0..131ad6e 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -155,8 +155,12 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index ae261b1..f50f147 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -664,8 +664,12 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level CPU init code (from flash) */
+	move.l #cpu_init_f, %a1
+	jsr (%a1)
+	/* run low-level board init code (from flash) */
+	move.l #board_init_f, %a1
+	jsr (%a1)
 
 	/* board_init_f() does not return */
 
-- 
cgit v0.10.2


From aa997d1d774416b3525d44779ee7ff9914b6abcb Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Tue, 12 Apr 2016 15:11:23 -0400
Subject: drivers/gpio/pm8916_gpio.c: Make pid be uint32_t

If get_dev_addr fails it will return FDT_ADDR_T_NONE and:
>>>     "priv->pid == 4294967295U" is always false regardless of the values of its operands. This occurs as the logical operand of if.

Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reported-by: Coverity (CID: 143913)
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c
index 1abab7f..0b61975 100644
--- a/drivers/gpio/pm8916_gpio.c
+++ b/drivers/gpio/pm8916_gpio.c
@@ -50,7 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define REG_EN_CTL_ENABLE      (1 << 7)
 
 struct pm8916_gpio_bank {
-	uint16_t pid; /* Peripheral ID on SPMI bus */
+	uint32_t pid; /* Peripheral ID on SPMI bus */
 };
 
 static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
-- 
cgit v0.10.2


From 3bfc8152b2c09d81fb00f4d3990e5dfd59682b96 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Tue, 12 Apr 2016 15:11:24 -0400
Subject: drivers/power/pmic/pm8916.c: Make usid be uint32_t

If get_dev_addr fails it will return FDT_ADDR_T_NONE and:
>>>     "priv->usid == 4294967295U" is always false regardless of the values of its operands. This occurs as the logical operand of if.

Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reported-by: Coverity (CID: 143914)
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/power/pmic/pm8916.c b/drivers/power/pmic/pm8916.c
index 9acf5f5..d4c7d4a 100644
--- a/drivers/power/pmic/pm8916.c
+++ b/drivers/power/pmic/pm8916.c
@@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define REG_MASK 0xFF
 
 struct pm8916_priv {
-	uint16_t usid; /* Slave ID on SPMI bus */
+	uint32_t usid; /* Slave ID on SPMI bus */
 };
 
 static int pm8916_reg_count(struct udevice *dev)
-- 
cgit v0.10.2


From 8f69523213a2929fda1fb62fe018684444586c1b Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Wed, 13 Apr 2016 09:50:59 +0530
Subject: memory: Move TI_AEMIF config to KCONFIG

Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
platforms with AEMIF controller.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index e16669d..9e8ad93 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -20,6 +20,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TI_AEMIF)
 static struct aemif_config aemif_configs[] = {
 	{			/* CS0 */
 		.mode		= AEMIF_MODE_NAND,
@@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = {
 		.width		= AEMIF_WIDTH_8,
 	},
 };
+#endif
 
 int dram_init(void)
 {
@@ -42,7 +44,10 @@ int dram_init(void)
 
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
 	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
 	if (ddr3_size)
 		ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
 	return 0;
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index a3fa758..f45bce0 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_TI_AEMIF=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 83efcbb..56b3fe4 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_TI_AEMIF=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index d2ebb1d..3863c56 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_TI_AEMIF=y
diff --git a/drivers/Kconfig b/drivers/Kconfig
index c82a94b..118b66e 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -30,6 +30,8 @@ source "drivers/input/Kconfig"
 
 source "drivers/led/Kconfig"
 
+source "drivers/memory/Kconfig"
+
 source "drivers/misc/Kconfig"
 
 source "drivers/mmc/Kconfig"
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
new file mode 100644
index 0000000..4fbb5aa
--- /dev/null
+++ b/drivers/memory/Kconfig
@@ -0,0 +1,18 @@
+#
+# Memory devices
+#
+
+menu "Memory Controller drivers"
+
+config TI_AEMIF
+	tristate "Texas Instruments AEMIF driver"
+	depends on ARCH_KEYSTONE
+	help
+	  This driver is for the AEMIF module available in Texas Instruments
+	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
+	  is intended to provide a glue-less interface to a variety of
+	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
+	  of 256M bytes of any of these memories can be accessed at a given
+	  time via four chip selects with 64M byte access per chip select.
+
+endmenu
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 41185a1..61c7174 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -145,8 +145,6 @@
 /* SerDes */
 #define CONFIG_TI_KEYSTONE_SERDES
 
-/* AEMIF */
-#define CONFIG_TI_AEMIF
 #define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
 
 /* I2C Configuration */
-- 
cgit v0.10.2


From c1f2057cee092255474705a476c3b986bd72ed41 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Wed, 13 Apr 2016 09:51:00 +0530
Subject: configs: ks2: move CMD_NAND to defconfigs

NAND is not yet enabled on all Keystone2 platforms. So enabled
CMD_NAND in the respective defconfigs only if available.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index f45bce0..c843508 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_AEMIF=y
+CONFIG_CMD_NAND=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 56b3fe4..1627065 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_AEMIF=y
+CONFIG_CMD_NAND=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 3863c56..255f6d1 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_AEMIF=y
+CONFIG_CMD_NAND=y
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 61c7174..be3c299 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -208,7 +208,6 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
-#define CONFIG_CMD_NAND
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_SF
-- 
cgit v0.10.2


From bd716dd03d8f22fe91924e43f4d1f69733570e60 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Wed, 13 Apr 2016 09:57:04 +0530
Subject: ARM: AM43xx: Fix BOOT_DEVICE_USB ID

commit 62c5674ea136a ("omap: SPL boot devices cleanup and completion")
cleans up the boot device ids for amx3xx soc. But mistakenly updates wrong
device IDs for AM43xx USB. Fixing the same here.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 43401d0..f744ab0 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -56,8 +56,9 @@
 #define BOOT_DEVICE_MMC1	0x07
 #define BOOT_DEVICE_MMC2	0x08
 #define BOOT_DEVICE_SPI		0x0A
+#define BOOT_DEVICE_USB		0x0D
 #define BOOT_DEVICE_UART	0x41
-#define BOOT_DEVICE_USB		0x45
+#define BOOT_DEVICE_USBETH	0x45
 #define BOOT_DEVICE_CPGMAC	0x47
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
-- 
cgit v0.10.2


From dede284d1ce9f9d9e79a5114fe7eb814fec07679 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Wed, 13 Apr 2016 14:04:38 +0200
Subject: efi_loader: Handle memory overflows
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

jetson-tk1 has 2 GB of RAM at 0x80000000, causing gd->ram_top to be zero.
Handle this by either avoiding ram_top or by using the same type as
ram_top to reverse the overflow effect.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>

diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index df99585..71a3d19 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -220,7 +220,7 @@ efi_status_t efi_allocate_pages(int type, int memory_type,
 	switch (type) {
 	case 0:
 		/* Any page */
-		addr = efi_find_free_memory(len, gd->ram_top);
+		addr = efi_find_free_memory(len, gd->start_addr_sp);
 		if (!addr) {
 			r = EFI_NOT_FOUND;
 			break;
@@ -320,9 +320,9 @@ efi_status_t efi_get_memory_map(unsigned long *memory_map_size,
 
 int efi_memory_init(void)
 {
-	uint64_t runtime_start, runtime_end, runtime_pages;
-	uint64_t uboot_start, uboot_pages;
-	uint64_t uboot_stack_size = 16 * 1024 * 1024;
+	unsigned long runtime_start, runtime_end, runtime_pages;
+	unsigned long uboot_start, uboot_pages;
+	unsigned long uboot_stack_size = 16 * 1024 * 1024;
 	int i;
 
 	/* Add RAM */
-- 
cgit v0.10.2


From 093685a9cbb6956c6c3b56b8e46cb5a5f286bedc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Wed, 13 Apr 2016 14:16:22 +0200
Subject: dragonboard410c: Fix environment variables
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some variables for the distro boot commands were missing, using some
custom name instead. Rename them.

Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>

diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index 26f95a7..edf8cfb 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -128,10 +128,10 @@ REFLASH(dragonboard/u-boot.img, 8)\
 	"fdt_high=0xffffffffffffffff\0" \
 	"initrd_high=0xffffffffffffffff\0" \
 	"linux_image=Image\0" \
-	"linux_addr=0x81000000\0"\
-	"fdt_image=apq8016-sbc.dtb\0" \
-	"fdt_addr=0x83000000\0"\
-	"ramdisk_addr=0x84000000\0"\
+	"kernel_addr_r=0x81000000\0"\
+	"fdtfile=apq8016-sbc.dtb\0" \
+	"fdt_addr_r=0x83000000\0"\
+	"ramdisk_addr_r=0x84000000\0"\
 	BOOTENV
 
 #define CONFIG_ENV_IS_NOWHERE
-- 
cgit v0.10.2


From 3349ed3faa5409e4b2f6206518659c8014313c81 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Wed, 13 Apr 2016 11:40:01 -0400
Subject: Remove references to CONFIG_CMD_EXT3, no such command

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 7f57a54..8cf15d2 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -72,7 +72,6 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT3
 #define CONFIG_CMD_EXT4
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 0bc9d2d..b6d4a79 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -240,7 +240,6 @@
  */
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT3
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MMC
-- 
cgit v0.10.2


From 28983f4b1a62f94e1d0ba01958f42364abccc925 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Wed, 13 Apr 2016 18:30:16 -0400
Subject: doc: Updated README.ext4

Clean up the ext4 README file.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/doc/README.ext4 b/doc/README.ext4
index 9a2de50..2b0eab5 100644
--- a/doc/README.ext4
+++ b/doc/README.ext4
@@ -1,53 +1,77 @@
-This patch series adds support for ext4 ls,load and write features in uboot
-Journaling is supported for write feature.
+U-Boot supports access of both ext2 and ext4 filesystems, either in read-only
+mode or in read-write mode.
 
-To enable support for the ext4 (and ext2) filesystem implementation,
-#define CONFIG_FS_EXT4
+First, to enable support for both ext4 (and, automatically, ext2 as well),
+but without selecting the corresponding commands, use one of:
 
-If you want write support,
-#define CONFIG_EXT4_WRITE
+  #define CONFIG_FS_EXT4	(for read-only)
+  #define CONFIG_EXT4_WRITE	(for read-write)
 
-To Enable ext2 ls and load commands, modify the board specific config file with
-#define CONFIG_CMD_EXT2
-This automatically defines CONFIG_FS_EXT4 for you.
+Next, to select the ext2-related commands:
 
-To Enable ext4 ls and load commands, modify the board specific config file with
-#define CONFIG_CMD_EXT4
-This automatically defines CONFIG_FS_EXT4 for you.
+  * ext2ls
+  * ext2load
 
-To enable ext4 write command, modify the board specific config file with
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-These automatically define CONFIG_FS_EXT4 and CONFIG_EXT4_WRITE for you.
+or ext4-related commands:
 
-Also relevant are the generic filesystem commands,
-#define CONFIG_CMD_FS_GENERIC
-This does not automatically enable EXT4 support for you.
+  * ext4size
+  * ext4ls
+  * ext4load
 
-Steps to test:
+use one or both of:
 
-1. After applying the patch, ext4 specific commands can be seen
-   in the boot loader prompt using
-	UBOOT #help
+  #define CONFIG_CMD_EXT2
+  #define CONFIG_CMD_EXT4
+
+Selecting either of the above automatically defines CONFIG_FS_EXT4 if it
+wasn't defined already.
+
+In addition, to get the write access command "ext4write", use:
+
+  #define CONFIG_CMD_EXT4_WRITE
+
+which automatically defines CONFIG_EXT4_WRITE if it wasn't defined
+already.
+
+Also relevant are the generic filesystem commands, selected by:
+
+  #define CONFIG_CMD_FS_GENERIC
+
+This does not automatically enable EXT4 support for you, you still need
+to do that yourself.
+
+Some sample commands to test ext4 support:
 
+1. Check that the commands can be seen in the output of U-Boot help:
+
+	UBOOT #help
+	...
 	ext4load- load binary file from a Ext4 file system
 	ext4ls  - list files in a directory (default /)
+	ext4size - determine a file's size
 	ext4write- create a file in ext4 formatted partition
+	...
+
+2. To list the files in an ext4-formatted partition, run:
 
-2. To list the files in ext4 formatted partition, execute
 	ext4ls <interface> <dev[:part]> [directory]
+
 	For example:
 	UBOOT #ext4ls mmc 0:5 /usr/lib
 
-3. To read and load a file from an ext4 formatted partition to RAM, execute
+3. To read and load a file from an ext4-formatted partition to RAM, run:
+
 	ext4load <interface> <dev[:part]> [addr] [filename] [bytes]
+
 	For example:
 	UBOOT #ext4load mmc 2:2 0x30007fc0 uImage
 
-4. To write a file to a ext4 formatted partition.
+4. To write a file to an ext4-formatted partition.
+
 	a) First load a file to RAM at a particular address for example 0x30007fc0.
-	Now execute ext4write command
+	Now execute ext4write command:
 	ext4write <interface> <dev[:part]> [filename] [Address] [sizebytes]
+
 	For example:
 	UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120
 	(here 6183120 is the size of the file to be written)
-- 
cgit v0.10.2


From e3a46e3ee22876606254560ec4c10903074475c2 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Wed, 13 Apr 2016 22:29:52 -0600
Subject: serial: bcm283x_mu: make pending values more explicit

dm_serial_ops.pending should return the number of characters, not just a
valid C Boolean integer value. The existing code does already does this,
but only as an accident since BCM283X_MU_LSR_RX_READY happens to be
BIT(0). Enhance the code to be more explicit about the values it returns.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>

diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
index fc36bc0..7357bbf 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -116,9 +116,9 @@ static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
 
 	if (input) {
 		WATCHDOG_RESET();
-		return lsr & BCM283X_MU_LSR_RX_READY;
+		return (lsr & BCM283X_MU_LSR_RX_READY) ? 1 : 0;
 	} else {
-		return !(lsr & BCM283X_MU_LSR_TX_IDLE);
+		return (lsr & BCM283X_MU_LSR_TX_IDLE) ? 0 : 1;
 	}
 }
 
-- 
cgit v0.10.2


From 75e14b1ac87564f1f2f7401828c3fefd316e818f Mon Sep 17 00:00:00 2001
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Date: Thu, 14 Apr 2016 16:21:00 +0800
Subject: ahci: flush dcache before issuing command

Ensure data the following sata command used is flushed out of dcache
and written to physical memory or timeout error may happen.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>

diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index d29642b..e3e783a 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -1061,6 +1061,7 @@ static int ata_io_flush(u8 port)
 
 	memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
 	ahci_fill_cmd_slot(pp, cmd_fis_len);
+	ahci_dcache_flush_sata_cmd(pp);
 	writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
 
 	if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
-- 
cgit v0.10.2


From 1d15eb01ae6b037321848c3cb5d018e6cf94e6d0 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Thu, 14 Apr 2016 06:15:07 -0400
Subject: board: Remove overlooked vestiges of "dave" board.

Apparently, all "dave"-related vendor content was removed in commit
5344cc1a82fcc2817d4671696b3939b0dfa4323e; remove remaining directory
board/dave/, which consists solely of board/dave/common/flash.c.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c
deleted file mode 100644
index f05adf9..0000000
--- a/board/dave/common/flash.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-	short n;
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
-		/* set sector offsets for bottom boot block type	*/
-		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
-			info->start[i] = base;
-			base += 8 << 10;
-		}
-		while (i < info->sector_count) {	/* 64k regular sectors	*/
-			info->start[i] = base;
-			base += 64 << 10;
-			++i;
-		}
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("ST  ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
-				break;
-	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
-				break;
-	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
-				break;
-	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_STMW320DT:	printf ("M29W320DT (32 M, top sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count-1))
-		  size = info->start[i+1] - info->start[i];
-		else
-		  size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++)
-		  {
-		    if (*flash++ != 0xffffffff)
-		      {
-			erased = 0;
-			break;
-		      }
-		  }
-
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		/* print empty and read-only info */
-		printf (" %08lX%s%s",
-			info->start[i],
-			erased ? " E" : "  ",
-			info->protect[i] ? "RO " : "   ");
-#else
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-#endif
-
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	short n;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
-
-	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
-
-	value = addr2[CONFIG_SYS_FLASH_READ0];
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
-		info->flash_id += FLASH_STMW320DT;
-		info->sector_count = 67;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
-		info->flash_id += FLASH_AMDL322T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
-		info->flash_id += FLASH_AMDL322B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
-		info->flash_id += FLASH_AMDL323T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
-		info->flash_id += FLASH_AMDL323B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
-		info->flash_id += FLASH_AM640U;
-		info->sector_count = 128;
-		info->size = 0x00800000;  break;	/* => 8 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 16;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
-		info->flash_id += FLASH_SST160A;
-		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
-		/* set sector offsets for bottom boot block type	*/
-		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
-			info->start[i] = base;
-			base += 8 << 10;
-		}
-		while (i < info->sector_count) {	/* 64k regular sectors	*/
-			info->start[i] = base;
-			base += 64 << 10;
-			++i;
-		}
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		/*  1 x 16k boot sector */
-		base -= 16 << 10;
-		--i;
-		info->start[i] = base;
-		/*  2 x 8k  boot sectors */
-		for (n=0; n<2; ++n) {
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		/*  1 x 32k boot sector */
-		base -= 32 << 10;
-		--i;
-		info->start[i] = base;
-
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-		  info->protect[i] = 0;
-		else
-		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
-		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
-			for (i=0; i<50; i++)
-			  udelay(1000);  /* wait 1 ms */
-		    } else {
-			if (sect == s_first) {
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			}
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-		    }
-		    l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-#ifdef CONFIG_B2
-			data = data | ((*(uchar *)cp)<<(8*i));
-#else
-			data = (data << 8) | (*(uchar *)cp);
-#endif
-		}
-		for (; i<4 && cnt>0; ++i) {
-#ifdef CONFIG_B2
-			data = data  | ((*src++)<<(8*i));
-#else
-			data = (data << 8) | *src++;
-#endif
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-#ifdef CONFIG_B2
-			data = data | ((*(uchar *)cp)<<(8*i));
-#else
-			data = (data << 8) | (*(uchar *)cp);
-#endif
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-#ifdef CONFIG_B2
-		data = (*(ulong*)src);
-		src += 4;
-#else
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-#endif
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-#ifdef CONFIG_B2
-		data = data  | ((*src++)<<(8*i));
-#else
-		data = (data << 8) | *src++;
-#endif
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-#ifdef CONFIG_B2
-		data = data | ((*(uchar *)cp)<<(8*i));
-#else
-		data = (data << 8) | (*(uchar *)cp);
-#endif
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	ulong *data_ptr = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
-	ulong start;
-	int flag;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile ulong *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
-	  {
-	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
-
-	    dest2[i] = data2[i];
-
-	    /* re-enable interrupts if necessary */
-	    if (flag)
-	      enable_interrupts();
-
-	    /* data polling for D7 */
-	    start = get_timer (0);
-	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
-		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-		return (1);
-	      }
-	    }
-	  }
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-- 
cgit v0.10.2


From 0c4b3880c1113276c6949effdd88d28578ab8ed5 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 18 Apr 2016 13:57:42 -0400
Subject: sandbox: Set CONFIG_SYS_CPU

Give a valid value here as well to allow things which want
CONFIG_ENV_VARS_UBOOT_CONFIG to build

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 25e316c..a8a90cb 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -7,6 +7,9 @@ config SYS_ARCH
 config SYS_BOARD
 	default "sandbox"
 
+config SYS_CPU
+	default "sandbox"
+
 config SYS_CONFIG_NAME
 	default "sandbox"
 
-- 
cgit v0.10.2


From 1c39809b92c217877e160ee91a82743c9d4f3ed1 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 14 Apr 2016 16:07:53 +0200
Subject: efi_loader: Pass fdt address directly to bootefi cmd
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The bootefi cmd today fetches its device tree pointer from either the
location appointed by "fdt addr" with a fallback to the U-Boot control
fdt.

This integration is unusual for U-Boot and diverges from the way we
usually handle parameters to boot commands. So let's pass the fdt
directly into the bootefi command instead and move the control fdt
logic into the distro boot script.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index b213ef1..7f552fc 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -142,12 +142,11 @@ static void *copy_fdt(void *fdt)
  * Load an EFI payload into a newly allocated piece of memory, register all
  * EFI objects it would want to access and jump to it.
  */
-static unsigned long do_bootefi_exec(void *efi)
+static unsigned long do_bootefi_exec(void *efi, void *fdt)
 {
 	ulong (*entry)(void *image_handle, struct efi_system_table *st);
 	ulong fdt_pages, fdt_size, fdt_start, fdt_end;
 	bootm_headers_t img = { 0 };
-	void *fdt = working_fdt;
 
 	/*
 	 * gd lives in a fixed register which may get clobbered while we execute
@@ -155,13 +154,7 @@ static unsigned long do_bootefi_exec(void *efi)
 	 */
 	efi_save_gd();
 
-	/* Update system table to point to our currently loaded FDT */
-
-	/* Fall back to included fdt if none was manually loaded */
-	if (!fdt && gd->fdt_blob)
-		fdt = (void *)gd->fdt_blob;
-
-	if (fdt) {
+	if (fdt && !fdt_check_header(fdt)) {
 		/* Prepare fdt for payload */
 		fdt = copy_fdt(fdt);
 
@@ -185,7 +178,7 @@ static unsigned long do_bootefi_exec(void *efi)
 		efi_add_memory_map(fdt_start, fdt_pages,
 				   EFI_BOOT_SERVICES_DATA, true);
 	} else {
-		printf("WARNING: No device tree loaded, expect boot to fail\n");
+		printf("WARNING: Invalid device tree, expect boot to fail\n");
 		systab.nr_tables = 0;
 	}
 
@@ -216,8 +209,8 @@ static unsigned long do_bootefi_exec(void *efi)
 /* Interpreter command to boot an arbitrary EFI image from memory */
 static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	char *saddr;
-	unsigned long addr;
+	char *saddr, *sfdt;
+	unsigned long addr, fdt_addr = 0;
 	int r = 0;
 
 	if (argc < 2)
@@ -226,8 +219,13 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	addr = simple_strtoul(saddr, NULL, 16);
 
+	if (argc > 2) {
+		sfdt = argv[2];
+		fdt_addr = simple_strtoul(sfdt, NULL, 16);
+	}
+
 	printf("## Starting EFI application at 0x%08lx ...\n", addr);
-	r = do_bootefi_exec((void *)addr);
+	r = do_bootefi_exec((void *)addr, (void*)fdt_addr);
 	printf("## Application terminated, r = %d\n", r);
 
 	if (r != 0)
@@ -238,16 +236,14 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #ifdef CONFIG_SYS_LONGHELP
 static char bootefi_help_text[] =
-	"<image address>\n"
-	"  - boot EFI payload stored at address <image address>\n"
-	"\n"
-	"Since most EFI payloads want to have a device tree provided, please\n"
-	"make sure you load a device tree using the fdt addr command before\n"
-	"executing bootefi.\n";
+	"<image address> [fdt address]\n"
+	"  - boot EFI payload stored at address <image address>.\n"
+	"    If specified, the device tree located at <fdt address> gets\n"
+	"    exposed as EFI configuration table.\n";
 #endif
 
 U_BOOT_CMD(
-	bootefi, 2, 0, do_bootefi,
+	bootefi, 3, 0, do_bootefi,
 	"Boots an EFI payload from memory\n",
 	bootefi_help_text
 );
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index ad9045e..dddebc3 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -103,12 +103,15 @@
 	"boot_efi_binary="                                                \
 		"load ${devtype} ${devnum}:${distro_bootpart} "           \
 			"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "      \
-		"bootefi ${kernel_addr_r}\0"                              \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r};"         \
+		"else"                                                    \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi\0"                                                    \
 	\
 	"load_efi_dtb="                                                   \
 		"load ${devtype} ${devnum}:${distro_bootpart} "           \
-			"${fdt_addr_r} ${prefix}${fdtfile}; "             \
-		"fdt addr ${fdt_addr_r}\0"                                \
+			"${fdt_addr_r} ${prefix}${fdtfile}\0"             \
 	\
 	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"                        \
 	"scan_dev_for_efi="                                               \
-- 
cgit v0.10.2


From ff2545ab78212717b5d81bc0fb6a91fd393f3cb1 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 14 Apr 2016 16:07:54 +0200
Subject: efi_loader: Fall back to fdtfile naming convention
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When there is no $fdtfile variable set, we still have a good chance
that on 32bit arm the fdtfile really is just called $soc-$board.dtb.

Enable the exports for $soc and $board in our distr defaults and make
use of them in the efi boot script.

Reported-by: Andreas Faerber <afaerber@suse.de>
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index dddebc3..7f67344 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -99,6 +99,21 @@
 #endif
 
 #ifdef BOOTEFI_NAME
+#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+/*
+ * On 32bit ARM systems there is a reasonable number of systems that follow
+ * the $soc-$board$boardver.dtb name scheme for their device trees. Use that
+ * scheme if we don't have an explicit fdtfile variable.
+ */
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then "               \
+	  "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; "           \
+	"fi; "
+#else
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
+#endif
+
+
 #define BOOTENV_SHARED_EFI                                                \
 	"boot_efi_binary="                                                \
 		"load ${devtype} ${devnum}:${distro_bootpart} "           \
@@ -111,14 +126,16 @@
 	\
 	"load_efi_dtb="                                                   \
 		"load ${devtype} ${devnum}:${distro_bootpart} "           \
-			"${fdt_addr_r} ${prefix}${fdtfile}\0"             \
+			"${fdt_addr_r} ${prefix}${efi_fdtfile}\0"         \
 	\
 	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"                        \
 	"scan_dev_for_efi="                                               \
+		"setenv efi_fdtfile ${fdtfile}; "                         \
+		BOOTENV_EFI_SET_FDTFILE_FALLBACK                          \
 		"for prefix in ${efi_dtb_prefixes}; do "                  \
 			"if test -e ${devtype} "                          \
 					"${devnum}:${distro_bootpart} "   \
-					"${prefix}${fdtfile}; then "      \
+					"${prefix}${efi_fdtfile}; then "  \
 				"run load_efi_dtb; "                      \
 			"fi;"                                             \
 		"done;"                                                   \
@@ -128,7 +145,8 @@
 					"efi/boot/"BOOTEFI_NAME"; "       \
 				"run boot_efi_binary; "                   \
 				"echo EFI LOAD FAILED: continuing...; "   \
-		"fi; \0"
+		"fi; "                                                    \
+		"setenv efi_fdtfile\0"
 #define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
 #else
 #define BOOTENV_SHARED_EFI
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 076be4d..5cc2af8 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -65,5 +65,6 @@
 #define CONFIG_ISO_PARTITION
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
 
 #endif	/* _CONFIG_CMD_DISTRO_DEFAULTS_H */
-- 
cgit v0.10.2


From e1acaa67679ebdb9caf4f1bf9a6f3ec8ebebf91b Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Thu, 14 Apr 2016 13:55:08 -0400
Subject: bx50v3: Enable CONFIG_OF_LIBFDT in defconfig

As of commit 69e173eb57d1f4848f070c83456096ba5d2ba1b4, CONFIG_OF_LIBFDT
needs to be selected in defconfig instead of board specific header file.
Hence enable CONFIG_OF_LIBFDT in defconfig.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>

diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 02873ce..24ef9e8 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -6,3 +6,4 @@ CONFIG_TARGET_GE_B450V3=y
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index 3d10b35..75c49c0 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -6,3 +6,4 @@ CONFIG_TARGET_GE_B650V3=y
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index e3f4a0a..85140cd 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -6,3 +6,4 @@ CONFIG_TARGET_GE_B850V3=y
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 6fa4a9a..3a9739e 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -302,8 +302,6 @@
 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
 
-#define CONFIG_OF_LIBFDT
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 #define CONFIG_CMD_CACHE
 #endif
-- 
cgit v0.10.2


From 724219a65f55894413c098be06263960c399c323 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 15 Apr 2016 14:40:37 -0600
Subject: ARM: always perform per-CPU GIC init

The current code in ARMv8's lowlevel_init() skips the per-CPU GIC
initialization ifndef CONFIG_ARMV8_MULTIENTRY. However, the per-CPU init
should always occur; it's just the one-time init that should only happen
on the master.

Once this consideration is taken into account, the only difference between
the paths when CONFIG_ARMV8_MULTIENTRY is undefined/defined is the use of
branch_if_slave. Naively, any unified code would need to invoke this
conditionally upon ifdef CONFIG_ARMV8_MULTIENTRY. However, branch_if_slave
already checks CONFIG_ARMV8_MULTIENTRY and does nothing if it isn't
defined, so we don't even need that ifdef at the call site.

Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index dceedd7..deb44a8 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -201,15 +201,6 @@ ENDPROC(apply_core_errata)
 WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
-#ifndef CONFIG_ARMV8_MULTIENTRY
-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-	/*
-	 * For single-entry systems the lowlevel init is very simple.
-	 */
-	ldr	x0, =GICD_BASE
-	bl	gic_init_secure
-#endif
-#else /* CONFIG_ARMV8_MULTIENTRY is set */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	branch_if_slave x0, 1f
 	ldr	x0, =GICD_BASE
@@ -223,7 +214,6 @@ WEAK(lowlevel_init)
 	ldr	x1, =GICC_BASE
 	bl	gic_init_secure_percpu
 #endif
-#endif
 
 	branch_if_master x0, x1, 2f
 
-- 
cgit v0.10.2


From 59d7c34bfcd919f46d4bec41ecbc054aaea4adf6 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Sat, 16 Apr 2016 05:53:07 -0400
Subject: Kconfig: Simple aesthetic/grammar fixes to top-level Kconfig

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/Kconfig b/Kconfig
index e7002ed..f53759a 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1,6 +1,7 @@
 #
 # For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
+# see the file Documentation/kbuild/kconfig-language.txt in the
+# Linux kernel source tree.
 #
 mainmenu "U-Boot $UBOOTVERSION Configuration"
 
@@ -17,7 +18,7 @@ config LOCALVERSION
 	string "Local version - append to U-Boot release"
 	help
 	  Append an extra string to the end of your U-Boot version.
-	  This will show up on your boot log, for example.
+	  This will show up in your boot log, for example.
 	  The string you set here will be appended after the contents of
 	  any files with a filename matching localversion* in your
 	  object and source tree, in that order.  Your total string can
@@ -28,11 +29,11 @@ config LOCALVERSION_AUTO
 	default y
 	help
 	  This will try to automatically determine if the current tree is a
-	  release tree by looking for git tags that belong to the current
+	  release tree by looking for Git tags that belong to the current
 	  top of tree revision.
 
 	  A string of the format -gxxxxxxxx will be added to the localversion
-	  if a git-based tree is found.  The string generated by this will be
+	  if a Git-based tree is found.  The string generated by this will be
 	  appended after any matching localversion* files, and after the value
 	  set in CONFIG_LOCALVERSION.
 
@@ -56,7 +57,7 @@ config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
 	default y if DM
 	help
-	  Before relocation memory is very limited on many platforms. Still,
+	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
@@ -66,7 +67,7 @@ config SYS_MALLOC_F_LEN
 	depends on SYS_MALLOC_F
 	default 0x400
 	help
-	  Before relocation memory is very limited on many platforms. Still,
+	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
@@ -78,7 +79,7 @@ menuconfig EXPERT
 	  This option allows certain base U-Boot options and settings
 	  to be disabled or tweaked. This is for specialized
 	  environments which can tolerate a "non-standard" U-Boot.
-	  Only use this if you really know what you are doing.
+	  Use this only if you really know what you are doing.
 
 if EXPERT
 	config SYS_MALLOC_CLEAR_ON_INIT
@@ -95,7 +96,7 @@ if EXPERT
 	  Then the boot time can be significantly reduced.
 	  Warning:
 	  When disabling this, please check if malloc calls, maybe
-	  should be replaced by calloc - if expects zeroed memory.
+	  should be replaced by calloc - if one expects zeroed memory.
 endif
 endmenu		# General setup
 
@@ -117,10 +118,10 @@ config SPL
 config SPL_SYS_MALLOC_SIMPLE
 	bool
 	depends on SPL
-	prompt "Only use malloc_simple functions in the spl"
+	prompt "Only use malloc_simple functions in the SPL"
 	help
 	  Say Y here to only use the *_simple malloc functions from
-	  malloc_simple.c, rather then using the versions from dlmalloc.c
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
 	  this will make the SPL binary smaller at the cost of more heap
 	  usage as the *_simple malloc functions do not re-use free-ed mem.
 
-- 
cgit v0.10.2


From fdff5b0598c73767c2cad097c66a82a705463452 Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Mon, 18 Apr 2016 18:31:38 +0530
Subject: MIPS: bootm: Add fixup of '/memory' node.

MIPS arch do not update 'reg' property of /memory node.
As a result Linux bootup will not work unless board.dts
file contains right /memory offset-size information or
board implements required memory fixup.
Fixing by renaming (unused) _arch_fixup_memory_node_ to
_arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index eed159c..aa0475a 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -9,6 +9,7 @@
 #include <image.h>
 #include <fdt_support.h>
 #include <asm/addrspace.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -252,10 +253,10 @@ static int boot_reloc_fdt(bootm_headers_t *images)
 #endif
 }
 
-int arch_fixup_memory_node(void *blob)
+int arch_fixup_fdt(void *blob)
 {
 #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
-	u64 mem_start = 0;
+	u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
 	u64 mem_size = gd->ram_size;
 
 	return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);
-- 
cgit v0.10.2


From 7d0b8cfeaa930b5946b993373a21b41ea0746be0 Mon Sep 17 00:00:00 2001
From: Justin Waters <justin.waters@timesys.com>
Date: Wed, 13 Apr 2016 17:03:18 -0400
Subject: board: ge: bx50v3: Disable unused pins

Certain pins are not used on the i.MX6, and should have a neutral
pad configuration in order to reduce electrical interference on
the board. This commit defines these pins with a default value
rather than relying on the system defaults.

Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 70c298d..3cf5105 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -27,6 +27,10 @@
 #include <i2c.h>
 DECLARE_GLOBAL_DATA_PTR;
 
+#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_HYS)
+
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
@@ -467,6 +471,12 @@ int board_eth_init(bd_t *bis)
 
 static iomux_v3_cfg_t const misc_pads[] = {
 	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
+	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
 };
 #define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
 #define WIFI_EN	IMX_GPIO_NR(6, 14)
-- 
cgit v0.10.2


From 0297bd1106bc59f46ba4401bb50a0cdc9afc9faa Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 5 Apr 2016 10:54:06 +0200
Subject: arm: mx5: Fix NAND image generation

The echo -ne "\xNN" does not work in certain bourne-compatible shells, like
dash. The recommended way of hex->char conversion is using printf(1), but
there is a pitfall here. The GNU printf does support "\xNN" format, but
according to the opengroup documentation, this is not part of POSIX. The
POSIX printf only defines "\NNN" where N is octal. Thus, for the sake of
compatibility, we use that.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 30e66ba..c208628 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -86,7 +86,7 @@ u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
 	$(call if_changed,pad_cat)
 
 quiet_cmd_u-boot-nand-spl_imx = GEN     $@
-cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
 	dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
 
 spl/u-boot-nand-spl.imx: SPL FORCE
-- 
cgit v0.10.2


From 90d7cc42b31251548b3cfb0e65a266020159784d Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Tue, 12 Apr 2016 18:13:56 -0400
Subject: imx: mx6: Fix procedure to switch the parent of LDB_DI_CLK

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.

This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d

NXP errata number: ERR009219, EB821

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 3b53842..e6f2275 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1217,6 +1217,157 @@ void enable_ipu_clock(void)
 	}
 }
 #endif
+
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
+	defined(CONFIG_MX6S)
+static void disable_ldb_di_clock_sources(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	/* Make sure PFDs are disabled at boot. */
+	reg = readl(&mxc_ccm->analog_pfd_528);
+	/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
+	if (is_cpu_type(MXC_CPU_MX6DL))
+		reg |= 0x80008080;
+	else
+		reg |= 0x80808080;
+	writel(reg, &mxc_ccm->analog_pfd_528);
+
+	/* Disable PLL3 PFDs */
+	reg = readl(&mxc_ccm->analog_pfd_480);
+	reg |= 0x80808080;
+	writel(reg, &mxc_ccm->analog_pfd_480);
+
+	/* Disable PLL5 */
+	reg = readl(&mxc_ccm->analog_pll_video);
+	reg &= ~(1 << 13);
+	writel(reg, &mxc_ccm->analog_pll_video);
+}
+
+static void enable_ldb_di_clock_sources(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	reg = readl(&mxc_ccm->analog_pfd_528);
+	if (is_cpu_type(MXC_CPU_MX6DL))
+		reg &= ~(0x80008080);
+	else
+		reg &= ~(0x80808080);
+	writel(reg, &mxc_ccm->analog_pfd_528);
+
+	reg = readl(&mxc_ccm->analog_pfd_480);
+	reg &= ~(0x80808080);
+	writel(reg, &mxc_ccm->analog_pfd_480);
+}
+
+/*
+ * Try call this function as early in the boot process as possible since the
+ * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
+ */
+void select_ldb_di_clock_source(enum ldb_di_clock clk)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	/*
+	 * Need to follow a strict procedure when changing the LDB
+	 * clock, else we can introduce a glitch. Things to keep in
+	 * mind:
+	 * 1. The current and new parent clocks must be disabled.
+	 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
+	 * no CG bit.
+	 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
+	 * the top four options are in one mux and the PLL3 option along
+	 * with another option is in the second mux. There is third mux
+	 * used to decide between the first and second mux.
+	 * The code below switches the parent to the bottom mux first
+	 * and then manipulates the top mux. This ensures that no glitch
+	 * will enter the divider.
+	 *
+	 * Need to disable MMDC_CH1 clock manually as there is no CG bit
+	 * for this clock. The only way to disable this clock is to move
+	 * it to pll3_sw_clk and then to disable pll3_sw_clk
+	 * Make sure periph2_clk2_sel is set to pll3_sw_clk
+	 */
+
+	/* Disable all ldb_di clock parents */
+	disable_ldb_di_clock_sources();
+
+	/* Set MMDC_CH1 mask bit */
+	reg = readl(&mxc_ccm->ccdr);
+	reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+	writel(reg, &mxc_ccm->ccdr);
+
+	/* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
+	reg = readl(&mxc_ccm->cbcmr);
+	reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
+	writel(reg, &mxc_ccm->cbcmr);
+
+	/*
+	 * Set the periph2_clk_sel to the top mux so that
+	 * mmdc_ch1 is from pll3_sw_clk.
+	 */
+	reg = readl(&mxc_ccm->cbcdr);
+	reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+	writel(reg, &mxc_ccm->cbcdr);
+
+	/* Wait for the clock switch */
+	while (readl(&mxc_ccm->cdhipr))
+		;
+	/* Disable pll3_sw_clk by selecting bypass clock source */
+	reg = readl(&mxc_ccm->ccsr);
+	reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+	writel(reg, &mxc_ccm->ccsr);
+
+	/* Set the ldb_di0_clk and ldb_di1_clk to 111b */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	/* Set the ldb_di0_clk and ldb_di1_clk to 100b */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+	      | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+	reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	/* Set the ldb_di0_clk and ldb_di1_clk to desired source */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+	      | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+	reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	/* Unbypass pll3_sw_clk */
+	reg = readl(&mxc_ccm->ccsr);
+	reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+	writel(reg, &mxc_ccm->ccsr);
+
+	/*
+	 * Set the periph2_clk_sel back to the bottom mux so that
+	 * mmdc_ch1 is from its original parent.
+	 */
+	reg = readl(&mxc_ccm->cbcdr);
+	reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+	writel(reg, &mxc_ccm->cbcdr);
+
+	/* Wait for the clock switch */
+	while (readl(&mxc_ccm->cdhipr))
+		;
+	/* Clear MMDC_CH1 mask bit */
+	reg = readl(&mxc_ccm->ccdr);
+	reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+	writel(reg, &mxc_ccm->ccdr);
+
+	enable_ldb_di_clock_sources();
+}
+#endif
+
 /***************************************************/
 
 U_BOOT_CMD(
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 1450523..82f9f92 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -42,6 +42,14 @@ enum mxc_clock {
 	MXC_I2C_CLK,
 };
 
+enum ldb_di_clock {
+	MXC_PLL5_CLK = 0,
+	MXC_PLL2_PFD0_CLK,
+	MXC_PLL2_PFD2_CLK,
+	MXC_MMDC_CH1_CLK,
+	MXC_PLL3_SW_CLK,
+};
+
 enum enet_freq {
 	ENET_25MHZ,
 	ENET_50MHZ,
@@ -70,4 +78,5 @@ int enable_lcdif_clock(u32 base_addr);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
+void select_ldb_di_clock_source(enum ldb_di_clock clk);
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
cgit v0.10.2


From de708da0e87f39d99f902a5434702d6ba0f4c5e0 Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Tue, 12 Apr 2016 18:13:57 -0400
Subject: board: ge: bx50v3: Split display setup function

B450v3/B650v3 uses single channel LVDS and does not support HDMI.
B850v3 uses dual channel LVDS and supports HDMI. Hence split the display
setup into two different functions.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 3cf5105..83d97d7 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -394,55 +394,75 @@ struct display_info_t const displays[] = {{
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 
-static void setup_display(void)
+static void setup_display_b850v3(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int reg;
 
-	enable_ipu_clock();
+	/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
+	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
 	imx_setup_hdmi();
 
-	reg = readl(&mxc_ccm->CCGR3);
-	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
-	writel(reg, &mxc_ccm->CCGR3);
-
-	reg = readl(&mxc_ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->cs2cdr);
-
-	reg = readl(&mxc_ccm->cscmr2);
-	reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-	writel(reg, &mxc_ccm->cscmr2);
-
-	reg = readl(&mxc_ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-	     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
-	     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
-	     | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
-	     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	     | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
-	     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
-	     | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-		       IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
-		       IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
-	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-	       << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
-	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-	       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	enable_ipu_clock();
+
+	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrbits_le32(&iomux->gpr[3],
+		     IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		     IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+		     IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+}
+
+static void setup_display_bx50v3(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
+	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	/* Set LDB_DI0 as clock source for IPU_DI0 */
+	clrsetbits_le32(&mxc_ccm->chsccdr,
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+			(CHSCCDR_CLK_SEL_LDB_DI0 <<
+			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+	/* Turn on IPU LDB DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	enable_ipu_clock();
+
+	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3],
+			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 
 	/* backlights off until needed */
 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
@@ -488,7 +508,6 @@ int board_early_init_f(void)
 
 	setup_iomux_uart();
 
-
 	return 0;
 }
 
@@ -497,7 +516,10 @@ int board_init(void)
 	gpio_direction_output(SUS_S3_OUT, 1);
 	gpio_direction_output(WIFI_EN, 1);
 #if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
+	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+		setup_display_b850v3();
+	else
+		setup_display_bx50v3();
 #endif
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-- 
cgit v0.10.2


From 494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3 Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Tue, 12 Apr 2016 18:13:58 -0400
Subject: board: ge: bx50v3: Setup LDB_DI_CLK source

To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 83d97d7..3acd4fa 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -394,11 +394,46 @@ struct display_info_t const displays[] = {{
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 
+static void enable_videopll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	s32 timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	/* set video pll to 910MHz (24MHz * (37+11/12))
+	* video pll post div to 910/4 = 227.5MHz
+	*/
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
 static void setup_display_b850v3(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
+	enable_videopll();
+
 	/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
 	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 
@@ -508,6 +543,14 @@ int board_early_init_f(void)
 
 	setup_iomux_uart();
 
+#if defined(CONFIG_VIDEO_IPUV3)
+	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+		/* Set LDB clock to Video PLL */
+		select_ldb_di_clock_source(MXC_PLL5_CLK);
+	else
+		/* Set LDB clock to USB PLL */
+		select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
+#endif
 	return 0;
 }
 
-- 
cgit v0.10.2


From 54971ac6de20b8834882efb69dc6ad5c1d4a9915 Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Tue, 12 Apr 2016 18:13:59 -0400
Subject: board: ge: bx50v3: Use pwm for display backlight

Setup the LCD backlight brightness control pin to use PWM

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 3acd4fa..dcf51dd 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -25,6 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <pwm.h>
 DECLARE_GLOBAL_DATA_PTR;
 
 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
@@ -328,6 +329,8 @@ static iomux_v3_cfg_t const backlight_pads[] = {
 	/* Backlight enable for LVDS display */
 	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
+	/* backlight PWM brightness control */
+	MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void do_enable_hdmi(struct display_info_t const *dev)
@@ -595,9 +598,17 @@ int board_late_init(void)
 	 * as per specifications from CHI MEI */
 	mdelay(250);
 
+	/* enable backlight PWM 1 */
+	pwm_init(0, 0, 0);
+
+	/* duty cycle 5000000ns, period: 5000000ns */
+	pwm_config(0, 5000000, 5000000);
+
 	/* Backlight Power */
 	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 
+	pwm_enable(0);
+
 	return 0;
 }
 
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 6fa4a9a..e37cd33 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -327,6 +327,9 @@
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK	66000000
+
 #undef CONFIG_CMD_PCI
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI
-- 
cgit v0.10.2


From 8d293f49b419dd394cdf4b7a501ad86b782efc3f Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Tue, 12 Apr 2016 18:14:00 -0400
Subject: board: ge: bx50v3: Fix to meet LVDS display power on timing

On a reset/reboot, the display power needs to be off for atleast 500ms
before turning it back on. So add a delay to the boot process to meet
the display timing requirement.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index dcf51dd..ff8f4d7 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -476,6 +476,13 @@ static void setup_display_bx50v3(void)
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
+	/* When a reset/reboot is performed the display power needs to be turned
+	 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
+	 * an additional 200ms here. Unfortunately we use external PMIC for
+	 * doing the reset, so can not differentiate between POR vs soft reset
+	 */
+	mdelay(200);
+
 	/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
 	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 
-- 
cgit v0.10.2


From 9999fc0957fc0b962cb71423b79e7145dacd6c45 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 18 Apr 2016 09:56:15 -0300
Subject: MX6UL: Add definition for UART6 base address

Define the UART6_BASE_ADDR for MX6UL.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 53488be..3ab04bf 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -274,6 +274,7 @@
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 #ifdef CONFIG_MX6UL
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-- 
cgit v0.10.2


From 69cc7dbf1f62492788ab810db7d8444a623c23c2 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 18 Apr 2016 09:56:16 -0300
Subject: Add initial support for Technexion's PICO-IMX6UL-EMMC board

Add support for Technexion's PICO-IMX6UL-EMMC board.

For information about this board, please visit:
http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc

Signed-off-by: Richard Hu <richard.hu@technexion.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 1bcd399..663f970 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -136,6 +136,10 @@ config TARGET_OT1200
 	bool "Bachmann OT1200"
 	select SUPPORT_SPL
 
+config TARGET_PICO_IMX6UL
+	bool "PICO-IMX6UL-EMMC"
+	select MX6UL
+
 config TARGET_PLATINUM_PICON
 	bool "platinum-picon"
 	select SUPPORT_SPL
@@ -200,6 +204,7 @@ source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/udoo/Kconfig"
diff --git a/board/technexion/pico-imx6ul/Kconfig b/board/technexion/pico-imx6ul/Kconfig
new file mode 100644
index 0000000..81acd61
--- /dev/null
+++ b/board/technexion/pico-imx6ul/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PICO_IMX6UL
+
+config SYS_BOARD
+	default "pico-imx6ul"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "pico-imx6ul"
+
+endif
diff --git a/board/technexion/pico-imx6ul/MAINTAINERS b/board/technexion/pico-imx6ul/MAINTAINERS
new file mode 100644
index 0000000..594a883
--- /dev/null
+++ b/board/technexion/pico-imx6ul/MAINTAINERS
@@ -0,0 +1,7 @@
+Technexion PICO-IMX6UL board
+M:	Richard Hu <richard.hu@technexion.com>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
+S:	Maintained
+F:	board/technexion/pico-imx6ul/
+F:	include/configs/pico-imx6ul.h
+F:	configs/pico-imx6ul_defconfig
diff --git a/board/technexion/pico-imx6ul/Makefile b/board/technexion/pico-imx6ul/Makefile
new file mode 100644
index 0000000..ac8ff9e
--- /dev/null
+++ b/board/technexion/pico-imx6ul/Makefile
@@ -0,0 +1,7 @@
+# (C) Copyright 2015 Technexion Ltd.
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pico-imx6ul.o
diff --git a/board/technexion/pico-imx6ul/imximage.cfg b/board/technexion/pico-imx6ul/imximage.cfg
new file mode 100644
index 0000000..9145b44
--- /dev/null
+++ b/board/technexion/pico-imx6ul/imximage.cfg
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x01380134
+DATA 4 0x021B0848 0x40404244
+DATA 4 0x021B0850 0x40405050
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x00333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D8B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x00000047
+DATA 4 0x021B0000 0x83180000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c
new file mode 100644
index 0000000..c038d43
--- /dev/null
+++ b/board/technexion/pico-imx6ul/pico-imx6ul.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ *
+ * Author: Richard Hu <richard.hu@technexion.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart6_pads[] = {
+	MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_otg_pad[] = {
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
+}
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_DEVICE;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_usb();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: PICO-IMX6UL-EMMC\n");
+
+	return 0;
+}
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
new file mode 100644
index 0000000..9157faa
--- /dev/null
+++ b/configs/pico-imx6ul_defconfig
@@ -0,0 +1,5 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_TARGET_PICO_IMX6UL=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
new file mode 100644
index 0000000..3e37815
--- /dev/null
+++ b/include/configs/pico-imx6ul.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ *
+ * Configuration settings for the Technexion PICO-IMX6UL-EMMC board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __PICO_IMX6UL_CONFIG_H
+#define __PICO_IMX6UL_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART6_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_USDHC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Only OTG1 port enabled */
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"FSL"
+
+#define CONFIG_G_DNL_VENDOR_NUM		0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER	"FSL"
+
+#define CONFIG_DEFAULT_FDT_FILE		"imx6ul-pico-hobbit.dtb"
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"image=zImage\0" \
+	"console=ttymxc5\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if run loadfdt; then " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"echo WARN: Cannot load the DT; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "if mmc rescan; then " \
+		   "if run loadimage; then " \
+			   "run mmcboot; " \
+		   "else run netboot; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + SZ_128M
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+
+#endif /* __PICO_IMX6UL_CONFIG_H */
-- 
cgit v0.10.2


From abaf83619cb1bcb095400c4117bdd3ebbc764905 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 16:07:11 +0200
Subject: ddr: altera: Replace ad-hoc constant with macro

The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 79c265f..34b1aa7 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3486,7 +3486,7 @@ static int run_mem_calibrate(void)
 	writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
 
 	/* Stop tracking manager. */
-	clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+	clrbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
 
 	phy_mgr_initialize();
 	rw_mgr_mem_initialize();
@@ -3507,7 +3507,7 @@ static int run_mem_calibrate(void)
 	writel(0x2, &phy_mgr_cfg->mux_sel);
 
 	/* Start tracking manager. */
-	setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+	setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
 
 	return pass;
 }
-- 
cgit v0.10.2


From bba7711092a48ef2af00832213c3cb6c2d5f171c Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 5 Apr 2016 23:41:56 +0200
Subject: ddr: altera: Tweak DQS tracking enable handling

In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 34b1aa7..bf74b4e 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3479,6 +3479,7 @@ grp_failed:		/* A group failed, increment the counter. */
 static int run_mem_calibrate(void)
 {
 	int pass;
+	u32 ctrl_cfg;
 
 	debug("%s:%d\n", __func__, __LINE__);
 
@@ -3486,7 +3487,9 @@ static int run_mem_calibrate(void)
 	writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
 
 	/* Stop tracking manager. */
-	clrbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
+	ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
+	writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
+	       &sdr_ctrl->ctrl_cfg);
 
 	phy_mgr_initialize();
 	rw_mgr_mem_initialize();
@@ -3507,7 +3510,7 @@ static int run_mem_calibrate(void)
 	writel(0x2, &phy_mgr_cfg->mux_sel);
 
 	/* Start tracking manager. */
-	setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK);
+	writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 
 	return pass;
 }
-- 
cgit v0.10.2


From 8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 17:28:16 +0200
Subject: ddr: altera: Fix scc_mgr_set() argument order

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index bf74b4e..3859e66 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -279,7 +279,7 @@ static void scc_mgr_initialize(void)
 	for (i = 0; i < 16; i++) {
 		debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 			   __func__, __LINE__, i);
-		scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
+		scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
 	}
 }
 
-- 
cgit v0.10.2


From 164eb23f4923c62ce3d8ebff6d4efb1f12570950 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 17:52:21 +0200
Subject: ddr: altera: Fix DRAM end value in protection rule

The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 2996942..7e4606d 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -118,7 +118,7 @@ static void sdram_set_rule(struct sdram_prot_rule *prule)
 
 	/* Obtain the address bits */
 	lo_addr_bits = prule->sdram_start >> 20ULL;
-	hi_addr_bits = prule->sdram_end >> 20ULL;
+	hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 
 	debug("sdram set rule start %x, %d\n", lo_addr_bits,
 	      prule->sdram_start);
-- 
cgit v0.10.2


From f5f8c411de0c1971475069ac011c858ca914eae7 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 18:41:53 +0200
Subject: ddr: altera: Remove unnecessary update of the SCC

Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 3859e66..6bf75ba 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -424,7 +424,6 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
 	 */
 	scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 			      read_group, delay, 1);
-	writel(0, &sdr_scc_mgr->update);
 }
 
 /**
-- 
cgit v0.10.2


From f3f777cdf00433866b1178e23a9a99e2eaf7d89e Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 19:10:12 +0200
Subject: ddr: altera: Remove unnecessary ODT mode config

There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6bf75ba..254b130 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1207,7 +1207,6 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
 			   *bit_chk == param->write_correct_mask);
 		return *bit_chk == param->write_correct_mask;
 	} else {
-		set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
 		debug_cond(DLEVEL == 2,
 			   "write_test(%u,%u,ONE) : %u != %i => %i\n",
 			   write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
-- 
cgit v0.10.2


From 70ed80af46e58a25d472362fe5552e1e49eaf25b Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 21:16:18 +0200
Subject: ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 254b130..0321e3b 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -303,15 +303,22 @@ static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
 	scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 }
 
+static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+{
+	scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+}
+
 static void scc_mgr_set_dqs_io_in_delay(u32 delay)
 {
 	scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
 		    delay);
 }
 
-static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
 {
-	scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+	scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
+		    rwcfg->mem_dq_per_write_dqs + 1 + dm,
+		    delay);
 }
 
 static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
@@ -584,8 +591,11 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 		writel(0xff, &sdr_scc_mgr->dq_ena);
 
 		/* Zero all DM config settings. */
-		for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
+		for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+			if (!out_only)
+				scc_mgr_set_dm_in_delay(i, 0);
 			scc_mgr_set_dm_out1_delay(i, 0);
+		}
 
 		/* Multicast to all DM enables. */
 		writel(0xff, &sdr_scc_mgr->dm_ena);
-- 
cgit v0.10.2


From ea9aa2414e5c443e14ef7bef93210c17f629b7d6 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 21:21:05 +0200
Subject: ddr: altera: Make DLEVEL behavior inclusive

Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 0321e3b..c41555f 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -277,7 +277,7 @@ static void scc_mgr_initialize(void)
 	int i;
 
 	for (i = 0; i < 16; i++) {
-		debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
+		debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
 			   __func__, __LINE__, i);
 		scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
 	}
@@ -479,10 +479,10 @@ static void scc_mgr_set_hhp_extras(void)
 			 SCC_MGR_HHP_GLOBALS_OFFSET |
 			 SCC_MGR_HHP_EXTRAS_OFFSET;
 
-	debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
+	debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
 		   __func__, __LINE__);
 	writel(value, addr);
-	debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+	debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
 		   __func__, __LINE__);
 }
 
@@ -693,7 +693,7 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 	/* DQS shift */
 	new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 	if (new_delay > iocfg->io_out2_delay_max) {
-		debug_cond(DLEVEL == 1,
+		debug_cond(DLEVEL >= 1,
 			   "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 			   __func__, __LINE__, write_group, delay, new_delay,
 			   iocfg->io_out2_delay_max,
@@ -707,7 +707,7 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 	/* OCT shift */
 	new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 	if (new_delay > iocfg->io_out2_delay_max) {
-		debug_cond(DLEVEL == 1,
+		debug_cond(DLEVEL >= 1,
 			   "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 			   __func__, __LINE__, write_group, delay,
 			   new_delay, iocfg->io_out2_delay_max,
@@ -1210,14 +1210,14 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
 
 	set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
 	if (all_correct) {
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "write_test(%u,%u,ALL) : %u == %u => %i\n",
 			   write_group, use_dm, *bit_chk,
 			   param->write_correct_mask,
 			   *bit_chk == param->write_correct_mask);
 		return *bit_chk == param->write_correct_mask;
 	} else {
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "write_test(%u,%u,ONE) : %u != %i => %i\n",
 			   write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
 		return *bit_chk != 0x00;
@@ -1292,7 +1292,7 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
 	if (bit_chk != param->read_correct_mask)
 		ret = -EIO;
 
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
 		   __func__, __LINE__, group, bit_chk,
 		   param->read_correct_mask, ret);
@@ -1453,13 +1453,13 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
 
 	if (all_correct) {
 		ret = (*bit_chk == param->read_correct_mask);
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
 			   __func__, __LINE__, group, all_groups, *bit_chk,
 			   param->read_correct_mask, ret);
 	} else	{
 		ret = (*bit_chk != 0x00);
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
 			   __func__, __LINE__, group, all_groups, *bit_chk,
 			   0, ret);
@@ -1523,7 +1523,7 @@ static int find_vfifo_failing_read(const u32 grp)
 	u32 v, ret, fail_cnt = 0;
 
 	for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
-		debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
+		debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
 			   __func__, __LINE__, v);
 		ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
 						PASS_ONE_BIT, 0);
@@ -1539,7 +1539,7 @@ static int find_vfifo_failing_read(const u32 grp)
 	}
 
 	/* No failing read found! Something must have gone wrong. */
-	debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
+	debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
 	return 0;
 }
 
@@ -1646,7 +1646,7 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
 	}
 
 	/* Cannot find working solution */
-	debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
+	debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
 		   __func__, __LINE__);
 	return -EINVAL;
 }
@@ -1722,7 +1722,7 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
 	ret = sdr_find_phase(0, grp, work_end, i, p);
 	if (ret) {
 		/* Cannot see edge of failing read. */
-		debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
+		debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
 			   __func__, __LINE__);
 	}
 
@@ -1746,21 +1746,21 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
 
 	work_mid = (work_bgn + work_end) / 2;
 
-	debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
+	debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
 		   work_bgn, work_end, work_mid);
 	/* Get the middle delay to be less than a VFIFO delay */
 	tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
 
-	debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
+	debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
 	work_mid %= tmp_delay;
-	debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
+	debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
 
 	tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
 	if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
 		tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
 	p = tmp_delay / iocfg->delay_per_opa_tap;
 
-	debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
+	debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
 
 	d = DIV_ROUND_UP(work_mid - tmp_delay,
 			 iocfg->delay_per_dqs_en_dchain_tap);
@@ -1768,7 +1768,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
 		d = iocfg->dqs_en_delay_max;
 	tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
 
-	debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
+	debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
 
 	scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
 	scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
@@ -1778,11 +1778,11 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
 	 * because the largest possible margin in 1 VFIFO cycle.
 	 */
 	for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
-		debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
+		debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
 		if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
 							     PASS_ONE_BIT,
 							     0)) {
-			debug_cond(DLEVEL == 2,
+			debug_cond(DLEVEL >= 2,
 				   "%s:%d center: found: ptap=%u dtap=%u\n",
 				   __func__, __LINE__, p, d);
 			return 0;
@@ -1792,7 +1792,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
 		rw_mgr_incr_vfifo(grp);
 	}
 
-	debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+	debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
 		   __func__, __LINE__);
 	return -EINVAL;
 }
@@ -1868,7 +1868,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
 
 		d = 0;
 
-		debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
+		debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
 			   __func__, __LINE__, p);
 	}
 
@@ -1880,18 +1880,18 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
 	if (d != 0)
 		work_end -= iocfg->delay_per_dqs_en_dchain_tap;
 
-	debug_cond(DLEVEL == 2,
+	debug_cond(DLEVEL >= 2,
 		   "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
 		   __func__, __LINE__, p, d - 1, work_end);
 
 	if (work_end < work_bgn) {
 		/* nil range */
-		debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
+		debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
 			   __func__, __LINE__);
 		return -EINVAL;
 	}
 
-	debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
+	debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
 		   __func__, __LINE__, work_bgn, work_end);
 
 	/*
@@ -1899,18 +1899,18 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
 	 * To do that we'll back up a ptap and re-find the edge of the
 	 * window using dtaps
 	 */
-	debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
+	debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
 		   __func__, __LINE__);
 
 	/* Special case code for backing up a phase */
 	if (p == 0) {
 		p = iocfg->dqs_en_phase_max;
 		rw_mgr_decr_vfifo(grp);
-		debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
+		debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
 			   __func__, __LINE__, p);
 	} else {
 		p = p - 1;
-		debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
+		debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
 			   __func__, __LINE__, p);
 	}
 
@@ -1923,7 +1923,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
 	 */
 
 	/* Find a passing read. */
-	debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
+	debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
 		   __func__, __LINE__);
 
 	initial_failing_dtap = d;
@@ -1931,13 +1931,13 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
 	found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
 	if (found_passing_read) {
 		/* Find a failing read. */
-		debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
+		debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
 			   __func__, __LINE__);
 		d++;
 		found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
 							   &d);
 	} else {
-		debug_cond(DLEVEL == 1,
+		debug_cond(DLEVEL >= 1,
 			   "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
 			   __func__, __LINE__);
 	}
@@ -1952,7 +1952,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
 		dtaps_per_ptap = d - initial_failing_dtap;
 
 	writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
-	debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
+	debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
 		   __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
 
 	/* Step 6: Find the centre of the window. */
@@ -2008,7 +2008,7 @@ static u32 search_stop_check(const int write, const int d, const int rank_bgn,
 	}
 	*sticky_bit_chk = *sticky_bit_chk | *bit_chk;
 	ret = ret && (*sticky_bit_chk == correct_mask);
-	debug_cond(DLEVEL == 2,
+	debug_cond(DLEVEL >= 2,
 		   "%s:%d center(left): dtap=%u => %u == %u && %u",
 		   __func__, __LINE__, d,
 		   *sticky_bit_chk, correct_mask, ret);
@@ -2087,7 +2087,7 @@ static void search_left_edge(const int write, const int rank_bgn,
 
 	*sticky_bit_chk = 0;
 	for (i = per_dqs - 1; i >= 0; i--) {
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
 			   __func__, __LINE__, i, left_edge[i],
 			   i, right_edge[i]);
@@ -2100,7 +2100,7 @@ static void search_left_edge(const int write, const int rank_bgn,
 		if ((left_edge[i] == delay_max + 1) &&
 		    (right_edge[i] != delay_max + 1)) {
 			right_edge[i] = delay_max + 1;
-			debug_cond(DLEVEL == 2,
+			debug_cond(DLEVEL >= 2,
 				   "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
 				   __func__, __LINE__, i, right_edge[i]);
 		}
@@ -2230,12 +2230,12 @@ static int search_right_edge(const int write, const int rank_bgn,
 				}
 			}
 
-			debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
+			debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
 				   __func__, __LINE__, d);
-			debug_cond(DLEVEL == 2,
+			debug_cond(DLEVEL >= 2,
 				   "bit_chk_test=%i left_edge[%u]: %d ",
 				   bit_chk & 1, i, left_edge[i]);
-			debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+			debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
 				   right_edge[i]);
 			bit_chk >>= 1;
 		}
@@ -2243,7 +2243,7 @@ static int search_right_edge(const int write, const int rank_bgn,
 
 	/* Check that all bits have a window */
 	for (i = 0; i < per_dqs; i++) {
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
 			   __func__, __LINE__, i, left_edge[i],
 			   i, right_edge[i]);
@@ -2292,7 +2292,7 @@ static int get_window_mid_index(const int write, int *left_edge,
 		(*mid_min)++;
 	*mid_min = *mid_min / 2;
 
-	debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
+	debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
 		   __func__, __LINE__, *mid_min, min_index);
 	return min_index;
 }
@@ -2338,7 +2338,7 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
 			(left_edge[min_index] - right_edge[min_index]))/2  +
 			(orig_mid_min - mid_min);
 
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "vfifo_center: before: shift_dq[%u]=%d\n",
 			   i, shift_dq);
 
@@ -2350,7 +2350,7 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
 		else if (shift_dq + temp_dq_io_delay1 < 0)
 			shift_dq = -temp_dq_io_delay1;
 
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "vfifo_center: after: shift_dq[%u]=%d\n",
 			   i, shift_dq);
 
@@ -2363,7 +2363,7 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
 
 		scc_mgr_load_dq(p);
 
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "vfifo_center: margin[%u]=[%d,%d]\n", i,
 			   left_edge[i] - shift_dq + (-mid_min),
 			   right_edge[i] + shift_dq - (-mid_min));
@@ -2445,7 +2445,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
 		scc_mgr_load_dqs(rw_group);
 		writel(0, &sdr_scc_mgr->update);
 
-		debug_cond(DLEVEL == 1,
+		debug_cond(DLEVEL >= 1,
 			   "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
 			   __func__, __LINE__, i, left_edge[i], right_edge[i]);
 		if (use_read_test) {
@@ -2473,7 +2473,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
 		new_dqs = 0;
 
 	mid_min = start_dqs - new_dqs;
-	debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
+	debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
 		   mid_min, new_dqs);
 
 	if (iocfg->shift_dqs_en_when_shift_dqs) {
@@ -2485,7 +2485,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
 	}
 	new_dqs = start_dqs - mid_min;
 
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
 		   start_dqs,
 		   iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
@@ -2505,7 +2505,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
 	/* Move DQS */
 	scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
 	scc_mgr_load_dqs(rw_group);
-	debug_cond(DLEVEL == 2,
+	debug_cond(DLEVEL >= 2,
 		   "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
 		   __func__, __LINE__, dq_margin, dqs_margin);
 
@@ -2538,7 +2538,7 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
 	/* Set a particular DQ/DQS phase. */
 	scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
 
-	debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
+	debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
 		   __func__, __LINE__, rw_group, phase);
 
 	/*
@@ -2557,7 +2557,7 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
 	 */
 	ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
 	if (ret)
-		debug_cond(DLEVEL == 1,
+		debug_cond(DLEVEL >= 1,
 			   "%s:%d Guaranteed read test failed: g=%u p=%u\n",
 			   __func__, __LINE__, rw_group, phase);
 	return ret;
@@ -2593,7 +2593,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
 		for (i = 0, p = test_bgn, d = 0;
 		     i < rwcfg->mem_dq_per_read_dqs;
 		     i++, p++, d += delay_step) {
-			debug_cond(DLEVEL == 1,
+			debug_cond(DLEVEL >= 1,
 				   "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
 				   __func__, __LINE__, rw_group, r, i, p, d);
 
@@ -2610,7 +2610,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
 	 */
 	ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
 
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
 		   __func__, __LINE__, rw_group, !ret);
 
@@ -2816,7 +2816,7 @@ static u32 rw_mgr_mem_calibrate_lfifo(void)
 
 	do {
 		writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
-		debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
+		debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
 			   __func__, __LINE__, gbl->curr_read_lat);
 
 		if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
@@ -2838,14 +2838,14 @@ static u32 rw_mgr_mem_calibrate_lfifo(void)
 		/* Add a fudge factor to the read latency that was determined */
 		gbl->curr_read_lat += 2;
 		writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "%s:%d lfifo: success: using read_lat=%u\n",
 			   __func__, __LINE__, gbl->curr_read_lat);
 	} else {
 		set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
 					CAL_SUBSTAGE_READ_LATENCY);
 
-		debug_cond(DLEVEL == 2,
+		debug_cond(DLEVEL >= 2,
 			   "%s:%d lfifo: failed at initial read_lat=%u\n",
 			   __func__, __LINE__, gbl->curr_read_lat);
 	}
@@ -3008,7 +3008,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 	orig_mid_min = mid_min;
 	new_dqs = start_dqs;
 	mid_min = 0;
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
 		   __func__, __LINE__, start_dqs, new_dqs, mid_min);
 
@@ -3021,7 +3021,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 	writel(0, &sdr_scc_mgr->update);
 
 	/* Centre DM */
-	debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
+	debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
 
 	/*
 	 * Set the left and right edge of each bit to an illegal value.
@@ -3055,7 +3055,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 	left_edge[0] = -1 * bgn_best;
 	right_edge[0] = end_best;
 
-	debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
+	debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
 		   __func__, __LINE__, left_edge[0], right_edge[0]);
 
 	/* Move DQS (back to orig). */
@@ -3079,14 +3079,14 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 	scc_mgr_apply_group_dm_out1_delay(mid);
 	writel(0, &sdr_scc_mgr->update);
 
-	debug_cond(DLEVEL == 2,
+	debug_cond(DLEVEL >= 2,
 		   "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
 		   __func__, __LINE__, left_edge[0], right_edge[0],
 		   mid, dm_margin);
 	/* Export values. */
 	gbl->fom_out += dq_margin + dqs_margin;
 
-	debug_cond(DLEVEL == 2,
+	debug_cond(DLEVEL >= 2,
 		   "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
 		   __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
 
@@ -3745,27 +3745,27 @@ int sdram_calibration_full(void)
 	printf("%s: Preparing to start memory calibration\n", __FILE__);
 
 	debug("%s:%d\n", __func__, __LINE__);
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
 		   rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
 		   rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
 		   rwcfg->mem_virtual_groups_per_read_dqs,
 		   rwcfg->mem_virtual_groups_per_write_dqs);
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
 		   rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
 		   rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
 		   iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
-	debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
+	debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
 		   iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
-	debug_cond(DLEVEL == 1,
+	debug_cond(DLEVEL >= 1,
 		   "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
 		   iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
 		   iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
-	debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
+	debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
 		   iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
 		   iocfg->io_out2_delay_max);
-	debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
+	debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
 		   iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
 
 	hc_initialize_rom_data();
-- 
cgit v0.10.2


From 85f76628a05539699a4aeb0a511109d322293033 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 5 Apr 2016 11:18:38 +0200
Subject: ddr: altera: Staticize global variables

Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c41555f..5ea53ad 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -57,7 +57,7 @@ const struct socfpga_sdram_misc_config *misccfg;
 	STATIC_SKIP_DELAY_LOOPS)
 
 /* calibration steps requested by the rtl */
-u16 dyn_calib_steps;
+static u16 dyn_calib_steps;
 
 /*
  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
@@ -68,13 +68,13 @@ u16 dyn_calib_steps;
  * zero when skipping
  */
 
-u16 skip_delay_mask;	/* mask off bits when skipping/not-skipping */
+static u16 skip_delay_mask;	/* mask off bits when skipping/not-skipping */
 
 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
 	((non_skip_value) & skip_delay_mask)
 
-struct gbl_type *gbl;
-struct param_type *param;
+static struct gbl_type *gbl;
+static struct param_type *param;
 
 static void set_failing_group_stage(u32 group, u32 stage,
 	u32 substage)
-- 
cgit v0.10.2


From e026b984e68cac45a8e18fc55dd48f1b75f91298 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 5 Apr 2016 23:17:35 +0200
Subject: ddr: altera: Repair DQ window centering code

The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 5ea53ad..6c6bd90 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2316,15 +2316,15 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
 			      const int min_index, const int test_bgn,
 			      int *dq_margin, int *dqs_margin)
 {
-	const u32 delay_max = write ? iocfg->io_out1_delay_max :
+	const s32 delay_max = write ? iocfg->io_out1_delay_max :
 				      iocfg->io_in_delay_max;
-	const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+	const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
 				    rwcfg->mem_dq_per_read_dqs;
-	const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
+	const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
 				      SCC_MGR_IO_IN_DELAY_OFFSET;
-	const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
+	const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
 
-	u32 temp_dq_io_delay1, temp_dq_io_delay2;
+	s32 temp_dq_io_delay1;
 	int shift_dq, i, p;
 
 	/* Initialize data for export structures */
@@ -2342,11 +2342,10 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
 			   "vfifo_center: before: shift_dq[%u]=%d\n",
 			   i, shift_dq);
 
-		temp_dq_io_delay1 = readl(addr + (p << 2));
-		temp_dq_io_delay2 = readl(addr + (i << 2));
+		temp_dq_io_delay1 = readl(addr + (i << 2));
 
 		if (shift_dq + temp_dq_io_delay1 > delay_max)
-			shift_dq = delay_max - temp_dq_io_delay2;
+			shift_dq = delay_max - temp_dq_io_delay1;
 		else if (shift_dq + temp_dq_io_delay1 < 0)
 			shift_dq = -temp_dq_io_delay1;
 
-- 
cgit v0.10.2


From 84f841c5b973d9f69e9fe3574ee37926c7914432 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 18 Apr 2016 14:22:04 +0200
Subject: arm: socfpga: Fix typos in DT files (environmnet -> environment)

Fix a small typo in some of the SoCFPGA dts files that has spread via
copy-and-paste.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 9ac48a1..7265058 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -21,7 +21,7 @@
 	};
 
 	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
+		/* this allow the ethaddr uboot environment variable contents
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index da13435..d4df1a1 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -21,7 +21,7 @@
 	};
 
 	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
+		/* this allow the ethaddr uboot environment variable contents
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 32c6aad..739bbb7 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -16,7 +16,7 @@
 
 	aliases {
 		/*
-		 * This allows the ethaddr uboot environmnet variable
+		 * This allows the ethaddr uboot environment variable
 		 * contents to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
-- 
cgit v0.10.2


From 43809cfa1baefb90958a17fa0d1ec67f6f9edaac Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 18 Apr 2016 14:22:05 +0200
Subject: arm: socfpga: socrates: Add eth0 alias to enable ethernet

This enables full ethernet usage, including U-Boot to write the board
specific MAC address (ethaddr) into the DT blob before passing it to
Linux.

Without this, the ethaddr is not detected in U-Boot at all, resulting
in this error upon bootup:

...
Model: EBV SOCrates
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 591d96c..d2ab3b3 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -15,6 +15,11 @@
 	};
 
 	aliases {
+		/*
+		 * This allows the ethaddr uboot environment variable
+		 * contents to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
 		udc0 = &usb1;
 	};
 
-- 
cgit v0.10.2


From 5b718407ed937fdcd1beeab9f62e42158dee9fa6 Mon Sep 17 00:00:00 2001
From: John Tobias <john.tobias.ph@gmail.com>
Date: Thu, 7 Apr 2016 16:49:03 -0700
Subject: USB: g_dnl: Change device class

The USB Mass Storage (ums) works in Windows, Linux and OS X (EL Capitan).
But, not in OS X (Yosemite). By applying the said patch, it extends
the ums support.

Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>

Test HW: Odroid XU3 (./test/py UMS + DFU tests)

Tested-by: John Tobias <john.tobias.ph@gmail.com>

Linux:
    - Run ums to expose all my eMMC partition - shows all correctly
    - Run ums to expose only 1 partition of my eMMC - show correctly

Windows:
    - Run ums to expose all my eMMC partition - it detects but it prompts,
    if I want to format it (due to a non windows partition)
    - Run ums to expose only the FAT32 partition - it show the partition
      correctly.

diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index 2fa6da4..bd3aad9 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -58,8 +58,8 @@ static struct usb_device_descriptor device_desc = {
 	.bDescriptorType = USB_DT_DEVICE,
 
 	.bcdUSB = __constant_cpu_to_le16(0x0200),
-	.bDeviceClass = USB_CLASS_COMM,
-	.bDeviceSubClass = 0x02, /*0x02:CDC-modem , 0x00:CDC-serial*/
+	.bDeviceClass = USB_CLASS_PER_INTERFACE,
+	.bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/
 
 	.idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM),
 	.idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM),
-- 
cgit v0.10.2


From a2e3a1d86c17b457056a4b65d8c045d98a75ba0f Mon Sep 17 00:00:00 2001
From: John Tobias <john.tobias.ph@gmail.com>
Date: Wed, 13 Apr 2016 12:06:51 -0700
Subject: usb: ums - expose selected partition/s

By applying this patch, it will give us some flexibility to expose
a selected partition/s.

e.g:
1. To expose several partitions
ums 0 mmc 0:1,0:6

2. To expose the all partitions
ums 0 mmc 0:0

3. To expose multiple partititions on several devices
ums 0 mmc 0:1,1:6

4. It support legacy format
ums 0 mmc 0

Signed-off-by: John Tobias <john.tobias.ph@gmail.com>

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 14eed98..ac53a73 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -50,14 +50,16 @@ static void ums_fini(void)
 
 #define UMS_NAME_LEN 16
 
-static int ums_init(const char *devtype, const char *devnums)
+static int ums_init(const char *devtype, const char *devnums_part_str)
 {
-	char *s, *t, *devnum, *name;
+	char *s, *t, *devnum_part_str, *name;
 	struct blk_desc *block_dev;
+	disk_partition_t info;
+	int partnum;
 	int ret;
 	struct ums *ums_new;
 
-	s = strdup(devnums);
+	s = strdup(devnums_part_str);
 	if (!s)
 		return -1;
 
@@ -65,14 +67,23 @@ static int ums_init(const char *devtype, const char *devnums)
 	ums_count = 0;
 
 	for (;;) {
-		devnum = strsep(&t, ",");
-		if (!devnum)
+		devnum_part_str = strsep(&t, ",");
+		if (!devnum_part_str)
 			break;
 
-		ret = blk_get_device_by_str(devtype, devnum, &block_dev);
-		if (ret < 0)
+		partnum = blk_get_device_part_str(devtype, devnum_part_str,
+					&block_dev, &info, 1);
+
+		if (partnum < 0)
 			goto cleanup;
 
+		/* Check if the argument is in legacy format. If yes,
+		 * expose all partitions by setting the partnum = 0
+		 * e.g. ums 0 mmc 0
+		 */
+		if (!strchr(devnum_part_str, ':'))
+			partnum = 0;
+
 		/* f_mass_storage.c assumes SECTOR_SIZE sectors */
 		if (block_dev->blksz != SECTOR_SIZE) {
 			ret = -1;
@@ -86,10 +97,18 @@ static int ums_init(const char *devtype, const char *devnums)
 		}
 		ums = ums_new;
 
+		/* if partnum = 0, expose all partitions */
+		if (partnum == 0) {
+			ums[ums_count].start_sector = 0;
+			ums[ums_count].num_sectors = block_dev->lba;
+		} else {
+			ums[ums_count].start_sector = info.start;
+			ums[ums_count].num_sectors = info.size;
+		}
+
 		ums[ums_count].read_sector = ums_read_sector;
 		ums[ums_count].write_sector = ums_write_sector;
-		ums[ums_count].start_sector = 0;
-		ums[ums_count].num_sectors = block_dev->lba;
+
 		name = malloc(UMS_NAME_LEN);
 		if (!name) {
 			ret = -1;
@@ -230,6 +249,6 @@ cleanup_ums_init:
 
 U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
 	"Use the UMS [USB Mass Storage]",
-	"<USB_controller> [<devtype>] <devnum>  e.g. ums 0 mmc 0\n"
+	"<USB_controller> [<devtype>] <dev[:part]>  e.g. ums 0 mmc 0\n"
 	"    devtype defaults to mmc"
 );
-- 
cgit v0.10.2


From a59a77f86318550168d5ceec36a7ca0add42d778 Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:24 +0300
Subject: usb: gadget: Move CONFIG_USB_GADGET_VBUS_DRAW to Kconfig

The description was borrowed from kernel. Definitions were added to
defconfig files in a way that "make savedefconfig" generates exactly
the same file as used defconfig.

Boards using 0 mA as CONFIG_USB_GADGET_VBUS_DRAW value were moved to use
2 mA (as minimal allowed by Kconfig).

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index f4698f4..cfd8ce8 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -33,3 +33,24 @@ menuconfig USB_GADGET
 	   a USB peripheral device.  Configure one hardware driver for your
 	   peripheral/device side bus controller, and a "gadget driver" for
 	   your peripheral protocol.
+
+if USB_GADGET
+
+config USB_GADGET_VBUS_DRAW
+	int "Maximum VBUS Power usage (2-500 mA)"
+	range 2 500
+	default 2
+	help
+	   Some devices need to draw power from USB when they are
+	   configured, perhaps to operate circuitry or to recharge
+	   batteries.  This is in addition to any local power supply,
+	   such as an AC adapter or batteries.
+
+	   Enter the maximum power your device draws through USB, in
+	   milliAmperes.  The permitted range of values is 2 - 500 mA;
+	   0 mA would be legal, but can make some hosts misbehave.
+
+	   This value will be used except for system-specific gadget
+	   drivers that have more specific information.
+
+endif # USB_GADGET
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 29b693a..8d68d60 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -290,7 +290,6 @@
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index fd3f6a7..0dd9c7a7 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -122,6 +122,10 @@
 #endif
 
 /* USB GADGET */
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#endif
+
 #if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
 #define CONFIG_USB_DWC3_PHY_OMAP
@@ -130,7 +134,6 @@
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index bfe3fa3..529cf1c 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -276,7 +276,6 @@
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 6c860a6..82bf92a 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -441,7 +441,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index cf25bde..387895b 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -139,7 +139,6 @@
 #define CONFIG_FASTBOOT_BUF_SIZE	(CONFIG_SYS_SDRAM_SIZE - SZ_1M)
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 #define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
 #define CONFIG_USB_GADGET_DOWNLOAD
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 63e3b94..3f3b69d 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -93,7 +93,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 7f57a54..63dbe12 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -235,7 +235,6 @@
 /* USB Client Support */
 #define CONFIG_CI_UDC
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW      2
 #define CONFIG_TRDX_VID                  0x1B67
 #define CONFIG_TRDX_PID_COLIBRI_VF50     0x0016
 #define CONFIG_TRDX_PID_COLIBRI_VF61     0x0017
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index fcf2bd6..b8c441e 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -125,7 +125,6 @@
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 7734e8d..e9facae 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -233,7 +233,6 @@
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM 0xd022
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 008d24c..c8e5397 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -53,7 +53,6 @@
 #define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 793b3fb..62f3468 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -196,7 +196,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW    2
 
 /* Netchip IDs */
 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index ee7d9ce..d8aa182 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -185,7 +185,6 @@
 #define CONFIG_USB_MUSB_OMAP2PLUS
 
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 
 /*
  * Download
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 3e1b760..f097176 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -241,7 +241,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index da1d26f..f9977a2 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -264,7 +264,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 3604e44..a50829e 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -333,7 +333,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 /* Netchip IDs */
 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 01d08dc..e4986b0 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -54,7 +54,6 @@
 
 /* USB gadget */
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 /* Downloader */
 #define CONFIG_G_DNL_VENDOR_NUM		0x04E8
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 2112d9f..17d8a86 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -66,7 +66,6 @@
 #define CONFIG_TWL4030_USB		1
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM	0xd022
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 304e1ce..7e802e9 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -85,7 +85,6 @@
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM	0xd022
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index a5cfa0c..09beb74 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -106,7 +106,6 @@
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 1a670cb..ec3fcba 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -200,7 +200,6 @@
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 07a5134..919c60e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -273,7 +273,6 @@
 #define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index df2a514..df4e734 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -225,7 +225,6 @@
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #undef CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USB_MUSB_HOST
 
 #define CONFIG_AM335X_USB0
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index db820ba..0586aec 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -176,7 +176,6 @@
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 18a379d..12090a3 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -202,7 +202,6 @@
 #define CONFIG_TWL4030_USB
 
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 
 /*
  * Download
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 3e50892..bdb06e7 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -252,7 +252,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 #define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 /* USB Composite download gadget - g_dnl */
 #define CONFIG_USB_GADGET_DOWNLOAD
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 8f11eb9..b5d05cd 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -343,7 +343,6 @@ extern int soft_i2c_gpio_scl;
 
 #ifdef CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 5b190f6..0b04b3a 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -140,7 +140,6 @@
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 1b5046a..715994c 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -132,7 +132,6 @@
 #define CONFIG_USBD_HS
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	0
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index c3a0151..ec034a1 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -10,7 +10,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* USB gadget mode support*/
-#define CONFIG_USB_GADGET_VBUS_DRAW    2
 #define CONFIG_CI_UDC
 #define CONFIG_CI_UDC_HAS_HOSTPC
 #define CONFIG_USB_GADGET_DUALSPEED
diff --git a/include/configs/warp.h b/include/configs/warp.h
index cb93629..80c4e38 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -81,7 +81,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index f7b4643..9493843 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -127,7 +127,6 @@
 
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 49d9fd0..e4d1111 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -105,7 +105,6 @@
 # define DFU_DEFAULT_POLL_TIMEOUT	300
 # define CONFIG_USB_FUNCTION_DFU
 # define CONFIG_DFU_RAM
-# define CONFIG_USB_GADGET_VBUS_DRAW	2
 # define CONFIG_G_DNL_VENDOR_NUM	0x03FD
 # define CONFIG_G_DNL_PRODUCT_NUM	0x0300
 # define CONFIG_G_DNL_MANUFACTURER	"Xilinx"
-- 
cgit v0.10.2


From 3457bbaf22a8fb6884d52fc3af997c187e930f06 Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:25 +0300
Subject: usb: gadget: Move CONFIG_USB_GADGET_DUALSPEED to Kconfig

Move CONFIG_USB_GADGET_DUALSPEED option to Kconfig and
make all UDC controllers select USB_GADGET_DUALSPEED:
  - add next options to Kconfig selecting USB_GADGET_DUALSPEED:
    - USB_GADGET_ATMEL_USBA
    - USB_GADGET_DWC2_OTG
    - USB_DWC3
    - CI_UDC
  - make USB_MUSB_GADGET select USB_GADGET_DUALSPEED

While at it, make some related fixes:
  - remove DUALSPEED from configs that don't enable gadget support:
    - kwb.h
    - tseries.h
  - add missing USB_GADGET option to next configs:
    - novena_defconfig
    - pcm051_rev*_defconfig
    - xfi3_defconfig

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index bda8727..3562e58 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -13,5 +13,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 8b6fa20..46ac471 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -18,5 +18,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 70fc5d7..8208b3c 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -25,4 +25,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 8eaa123..b59ff81 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 85a0ba9..9458fd1 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index f3a26c3..5a84150 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -10,5 +10,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 92eb46c..c9e0761 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 453714b..e8b2b91 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 0c7eda7..f888211 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -19,5 +19,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_RSA=y
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 356f6fd..e628bd4 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -21,4 +21,5 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 2e2827f..d556a7f 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -25,4 +25,5 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index cc83006..9b746bf 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -12,5 +12,6 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index a720c14..30a344c 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -11,5 +11,6 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 6db389b..75c75dc 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -10,5 +10,6 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index cbaf5a5..9c2234f 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -11,5 +11,6 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 152d06f..a8b4621 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -18,4 +18,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index 222c319..11d20c0 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -10,3 +10,4 @@ CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 7e1e682..b7336b4 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -10,3 +10,4 @@ CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index ba57944..15d3b8f 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -9,3 +9,4 @@ CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 36849d5..d06130ce 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -10,3 +10,4 @@ CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 9e01f31..1ab24bd 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -22,4 +22,5 @@ CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 2a81ded..807c945 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -12,5 +12,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index d2b35cd..f923cfd 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -12,5 +12,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 20b1492..c734725 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -10,4 +10,5 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 3813e96..6f93f1c 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -18,9 +18,10 @@ CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 6fd877b..74f90db 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -16,4 +16,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 267a453..ccba59b 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -19,3 +19,4 @@ CONFIG_FSL_LPUART=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 3a9e4d7..9f38c37 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -12,4 +12,5 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 5e696a1..5b54e75 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -20,4 +20,5 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index da24992..47fb0d7 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -24,4 +24,5 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 9039b15..a15b65b 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -23,4 +23,5 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 9be4c2d..2d504a5 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -14,5 +14,6 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index b77c7c3..6af9619 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -14,5 +14,6 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index 1a1fb6d..80ae9dd 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -15,5 +15,6 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index ec33985..be3ec0a 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 196950d..e0790ab 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -18,3 +18,4 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 788ba9d..5228c84 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -18,4 +18,5 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 5e87624..3078386 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -22,4 +22,5 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index 39ce550..1b2b722 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index ba53017..27ace90 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 7a67bf5..d085ef7 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index c27aa38..4273a32 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -7,4 +7,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 7699cbb..60262cd 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 324f46f..917362a 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -11,4 +11,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 6c9e27e..333eb67 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 131bd21..2e0363f 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 137369c..d106d89 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -14,4 +14,5 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 54f11e9..7ba591a 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index f2ea841..3b46fb6 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index cf654d7..6049891 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index de8bb22..ce5b61f 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 6030afc..2e264f2 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index fef827e..39b381f 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -9,4 +9,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 9217823..f28d884 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -7,4 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index de7e9eb..dc965cc 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -35,6 +35,7 @@ CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index a5f25cd..4548cf0 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -19,6 +19,7 @@ CONFIG_PMIC_S2MPS11=y
 CONFIG_DM_REGULATOR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 1634ed6..dbdbf96 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -24,4 +24,5 @@ CONFIG_DM_REGULATOR_MAX77686=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 798a7e5..ab3cac4 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -8,5 +8,6 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 02202d5..fefe209 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -12,5 +12,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # "
 CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 50d8372..3fc75df 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -8,5 +8,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index eda2225..2ce71d4 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -14,3 +14,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index b6f2954..4cff742 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -19,3 +19,4 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index f7cc8e0..cd0d325 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -21,3 +21,4 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 4d0986f..65d788a 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -19,3 +19,4 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index b74b372..b7c5466 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -9,4 +9,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 18be2a0..cb39392 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -9,4 +9,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 237b4c7..90ca1d2 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -7,5 +7,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 88d75b5..13e27b5 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -14,5 +14,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 8c3c735..6f92d84 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 2fb5c4c..d9367b3 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -14,5 +14,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index eb0604e..89c1195 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -13,3 +13,4 @@ CONFIG_SYS_PROMPT="Goni # "
 # CONFIG_CMD_MISC is not set
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 7f27b4c..dfcf4b7 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -13,3 +13,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 7f89698..b77c2b5 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -12,4 +12,5 @@ CONFIG_CMD_SF=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 28318fa..5b942b5 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -12,4 +12,5 @@ CONFIG_CMD_SF=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index f8cb309..969fb4b 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 3a7cc7d..6e242e0 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index e562f5a..2cceb57 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index c0c0416..e26bb59 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 96aefc7..b2067b9 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index b9d1c3c..53ff55b 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 2a17e20..2b6f4ac 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index f92fe50..190a8e9 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index c5a3431..9b5faa0 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index b8949aa..78df0ac 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -5,4 +5,7 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 087d6f1..372b312 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -28,3 +28,4 @@ CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index cef644e..b4de001 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -28,3 +28,4 @@ CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index c0ffad2..a03d161 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -23,3 +23,4 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index e01282c..d5d5a5c 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -23,3 +23,4 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 8feb5a3..52d1d18 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -28,3 +28,4 @@ CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 1b3c3df..902b4d2 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -27,3 +27,4 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index d0fda48..dc8be76 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -10,4 +10,5 @@ CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 39c8595..95d516f 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 24656ef..60fbab9 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -16,3 +16,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index e48fae8..079233a 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -15,3 +15,4 @@ CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index a7515ab..49ff533 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -20,4 +20,5 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index a16f376..565577d 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -13,3 +13,4 @@ CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index e37158c..c7d185c 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -10,4 +10,5 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NFS is not set
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 437e018..652e443 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -5,4 +5,7 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index daafb61..86d65dc 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -38,5 +38,6 @@ CONFIG_NAND_ARASAN=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
 # CONFIG_REGEX is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index c730f3c..28fbd26 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -13,6 +13,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index e8d28e4..e561784 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -25,6 +25,7 @@ CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index d19108f..d3a0f23 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -22,6 +22,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index b13de10..63512dd 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -22,6 +22,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index d2f8110..e397acb 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -24,6 +24,7 @@ CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index bccf43e..da3ec2f 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -49,6 +49,8 @@ config DM_USB
 
 source "drivers/usb/host/Kconfig"
 
+source "drivers/usb/dwc3/Kconfig"
+
 source "drivers/usb/musb-new/Kconfig"
 
 source "drivers/usb/emul/Kconfig"
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
new file mode 100644
index 0000000..debc74b
--- /dev/null
+++ b/drivers/usb/dwc3/Kconfig
@@ -0,0 +1,7 @@
+config USB_DWC3
+	bool "DesignWare USB3 DRD Core Support"
+	depends on (USB && USB_GADGET)
+	select USB_GADGET_DUALSPEED
+	help
+	  Say Y here if your system has a Dual Role SuperSpeed
+	  USB controller based on the DesignWare USB3 IP Core.
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index cfd8ce8..5838d6e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -36,6 +36,29 @@ menuconfig USB_GADGET
 
 if USB_GADGET
 
+config USB_GADGET_ATMEL_USBA
+	bool "Atmel USBA"
+	select USB_GADGET_DUALSPEED
+	help
+	  USBA is the integrated high-speed USB Device controller on
+	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
+
+config USB_GADGET_DWC2_OTG
+	bool "DesignWare USB2.0 HS OTG controller (gadget mode)"
+	select USB_GADGET_DUALSPEED
+	help
+	  The Designware USB2.0 high-speed gadget controller
+	  integrated into many SoCs. Select this option if you want the
+	  driver to operate in Peripheral mode. This option requires
+	  USB_GADGET to be enabled.
+
+config CI_UDC
+	bool "ChipIdea device controller"
+	select USB_GADGET_DUALSPEED
+	help
+	  Say Y here to enable device controller functionality of the
+	  ChipIdea driver.
+
 config USB_GADGET_VBUS_DRAW
 	int "Maximum VBUS Power usage (2-500 mA)"
 	range 2 500
@@ -53,4 +76,8 @@ config USB_GADGET_VBUS_DRAW
 	   This value will be used except for system-specific gadget
 	   drivers that have more specific information.
 
+# Selected by UDC drivers that support high-speed operation.
+config USB_GADGET_DUALSPEED
+	bool
+
 endif # USB_GADGET
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 4e8a543..c264859 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -10,6 +10,7 @@ config USB_MUSB_HOST
 
 config USB_MUSB_GADGET
 	bool "MUSB gadget mode support"
+	select USB_GADGET_DUALSPEED
 	help
 	  Enables the MUSB USB dual-role controller in gadget mode.
 
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 8d68d60..f0e13b8 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -285,11 +285,9 @@
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index fae8138..75fe558 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -113,7 +113,6 @@
 #endif /* CONFIG_USB_MUSB_HOST */
 
 #ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #endif /* CONFIG_USB_MUSB_GADGET */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 0dd9c7a7..8bea4c2 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -123,21 +123,22 @@
 
 /* USB GADGET */
 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+#undef CONFIG_USB_DWC3
+
 #undef CONFIG_USB_GADGET_VBUS_DRAW
+#undef CONFIG_USB_GADGET_DUALSPEED
 #endif
 
 #if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_USB_GADGET_DUALSPEED
 #endif
 
 /*
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 529cf1c..8280e60 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -271,11 +271,9 @@
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 82bf92a..c223931 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -436,11 +436,9 @@ DEFAULT_LINUX_BOOT_ENV \
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 387895b..b431781 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -138,8 +138,6 @@
 #define CONFIG_SYS_CACHELINE_SIZE	64
 #define CONFIG_FASTBOOT_BUF_SIZE	(CONFIG_SYS_SDRAM_SIZE - SZ_1M)
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USBID_ADDR		0x34052c46
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 3f3b69d..db207b9 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -86,9 +86,7 @@
 #define CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 63dbe12..3652d61 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -233,8 +233,6 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
 /* USB Client Support */
-#define CONFIG_CI_UDC
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_TRDX_VID                  0x1B67
 #define CONFIG_TRDX_PID_COLIBRI_VF50     0x0016
 #define CONFIG_TRDX_PID_COLIBRI_VF61     0x0017
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index b8c441e..81ebda4 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -117,9 +117,6 @@
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
-
 /* DFU class support */
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index e9facae..a230896 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -229,14 +229,12 @@
 /* USB GADGET */
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_USB_GADGET_DUALSPEED
 
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index c8e5397..7973991 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -50,9 +50,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
-#define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 62f3468..711777c 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -184,9 +184,7 @@
 #define CONFIG_MXC_USB_PORTSC     (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS      0
 #define CONFIG_USB_KEYBOARD
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_CDC
 #define CONFIG_NETCONSOLE
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index d8aa182..6a487f2 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -184,8 +184,6 @@
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_OMAP2PLUS
 
-#define CONFIG_USB_GADGET_DUALSPEED
-
 /*
  * Download
  */
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 1f2d2a4..4ec4e33 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -122,8 +122,6 @@ BUR_COMMON_ENV \
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-/* attention! not only for gadget, enables also highspeed in hostmode */
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index e061a10..324f1ce 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -131,8 +131,6 @@
 #define CONFIG_USB_STORAGE
 
 /* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_MANUFACTURER      "DENX"
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index f097176..249554c 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -234,9 +234,7 @@
 #define CONFIG_IMX_VIDEO_SKIP
 
 #ifndef CONFIG_SPL
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index f9977a2..fb47a6c 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -257,9 +257,7 @@
 
 #define CONFIG_IMX_THERMAL
 
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index a50829e..38e38ca 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -19,9 +19,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_CDC
 #define CONFIG_NETCONSOLE
diff --git a/include/configs/novena.h b/include/configs/novena.h
index d11cdc3..d58c95f 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -165,9 +165,7 @@
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
 /* Gadget part */
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_CDC
 #define CONFIG_NETCONSOLE
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index e4986b0..e704bb4 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -48,13 +48,9 @@
 #define CONFIG_USB_EHCI_EXYNOS
 
 /* DWC3 */
-#define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 #define CONFIG_USB_DWC3_PHY_SAMSUNG
 
-/* USB gadget */
-#define CONFIG_USB_GADGET_DUALSPEED
-
 /* Downloader */
 #define CONFIG_G_DNL_VENDOR_NUM		0x04E8
 #define CONFIG_G_DNL_PRODUCT_NUM	0x6601
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 17d8a86..276429e 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -59,10 +59,8 @@
 #define CONFIG_SYS_I2C_NOPROBES		{{0x0, 0x0}}
 
 /* USB */
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_OMAP2PLUS
 #define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_TWL4030_USB		1
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 7e802e9..b083d57 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -79,10 +79,8 @@
 #define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
 
 /* USB */
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_OMAP2PLUS
 #define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
 #define CONFIG_USB_GADGET_DOWNLOAD
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 09beb74..85e46b4 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -102,14 +102,12 @@
 /* USB GADGET */
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_USB_GADGET_DUALSPEED
 
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 45c140d..3e66c19 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -141,9 +141,7 @@
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index ec3fcba..8977115 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -196,10 +196,8 @@
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 919c60e..e22818e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -270,9 +270,7 @@
 #define CONFIG_SYS_I2C_INIT_BOARD
 
 #define CONFIG_SYS_MAX_I2C_BUS	7
-#define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index ed5365a..25aedc2 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -176,9 +176,7 @@
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX8998
 
-#define CONFIG_USB_GADGET_DWC2_OTG
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_USB_GADGET_DUALSPEED
 
 /*
  * SPI Settings
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index 1225aa8..427fed9 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -74,8 +74,6 @@
 #endif
 
 /* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2 XPlained"
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index ed6bafb..2567502 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -140,8 +140,6 @@
 #endif
 
 /* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index d89609b..e310ee3 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -83,8 +83,6 @@
 #endif
 
 /* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D4EK"
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 3981c23..8af3033 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -83,8 +83,6 @@
 #endif
 
 /* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D4EK"
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index 8088359..c8f4542 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -54,9 +54,6 @@
 #define CONFIG_EHCI_MXS_PORT0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 
-#define CONFIG_CI_UDC		/* ChipIdea CI13xxx UDC */
-#define CONFIG_USB_GADGET_DUALSPEED
-
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_CDC
 #define CONFIG_NETCONSOLE
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index df4e734..3dbe343 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -221,7 +221,6 @@
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #undef CONFIG_USB_GADGET_DUALSPEED
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 12090a3..6c8b00e 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -201,8 +201,6 @@
 #define CONFIG_USB_MUSB_OMAP2PLUS
 #define CONFIG_TWL4030_USB
 
-#define CONFIG_USB_GADGET_DUALSPEED
-
 /*
  * Download
  */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index bdb06e7..8494486 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -250,9 +250,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * USB Gadget (DFU, UMS)
  */
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_USB_GADGET_DWC2_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-
 /* USB Composite download gadget - g_dnl */
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b5d05cd..805ae09 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -342,7 +342,6 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 715994c..110c494 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -128,10 +128,8 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB_MASS_STORAGE
 #ifdef CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index ec034a1..45db9f1 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -10,9 +10,7 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* USB gadget mode support*/
-#define CONFIG_CI_UDC
 #define CONFIG_CI_UDC_HAS_HOSTPC
-#define CONFIG_USB_GADGET_DUALSPEED
 #ifndef CONFIG_G_DNL_VENDOR_NUM
 #define CONFIG_G_DNL_VENDOR_NUM 0x0955
 #endif
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 901dfd7..e73bc83 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -249,8 +249,6 @@ MMCARGS
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-/* attention! not only for gadget, enables also highspeed in hostmode */
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index 5073b9c..69cb63f 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -86,8 +86,6 @@
 #endif
 
 /* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_MANUFACTURER      "L+G VInCo"
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 80c4e38..4e3e202 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -74,9 +74,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Only OTG2 port enabled */
 #endif
 
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index aa49c9e..83c18f0 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -53,9 +53,6 @@
 #define CONFIG_EHCI_MXS_PORT0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 
-#define CONFIG_CI_UDC		/* ChipIdea CI13xxx UDC */
-#define CONFIG_USB_GADGET_DUALSPEED
-
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_CDC
 #define CONFIG_NETCONSOLE
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 9493843..c09b746 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -122,11 +122,9 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_XHCI_ZYNQMP
 
-#define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index e4d1111..513b527 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -98,8 +98,6 @@
 # define CONFIG_EHCI_IS_TDI
 # define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
-# define CONFIG_CI_UDC           /* ChipIdea CI13xxx UDC */
-# define CONFIG_USB_GADGET_DUALSPEED
 # define CONFIG_USB_GADGET_DOWNLOAD
 # define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x600000
 # define DFU_DEFAULT_POLL_TIMEOUT	300
-- 
cgit v0.10.2


From aaa4a9e313ee6e5d30c1476ad754e0b907e34217 Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:26 +0300
Subject: usb: gadget: Move CONFIG_USB_GADGET_DOWNLOAD to Kconfig

While at it, remove obsolete CONFIG_USBDOWNLOAD_GADGET option from some
config headers. This is also probably fixes am335x_baltos board.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 37ce923..e46efc6 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -22,3 +22,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 13a8f32..4fc1a31 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -13,3 +13,4 @@ CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 8c4fcf3..2ec2928 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -19,3 +19,4 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 3562e58..c0c7468 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 46ac471..8f781c8 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -20,4 +20,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 8208b3c..8e252ff 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -27,3 +27,4 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index b59ff81..426ddc5 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -19,4 +19,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 9458fd1..264fe36 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 5a84150..222fe82 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -12,4 +12,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index c9e0761..917128b 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index e8b2b91..81b3d27 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index f888211..a06f722 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -21,4 +21,5 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_RSA=y
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index e628bd4..b02f8ad 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -23,3 +23,4 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index d556a7f..1960429 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -27,3 +27,4 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 9b746bf..942a6a0 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -14,4 +14,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 30a344c..114d10f 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -13,4 +13,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 75c75dc..52265c3 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -12,4 +12,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 9c2234f..9166848 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -13,4 +13,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index a8b4621..882a21e 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -19,4 +19,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index 11d20c0..74a2881 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -11,3 +11,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index b7336b4..9c66669 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -11,3 +11,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 15d3b8f..50a6a30 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -10,3 +10,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index d06130ce..cd6a190 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -11,3 +11,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 1ab24bd..04ecab9 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -23,4 +23,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 807c945..d9a58ad 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -14,4 +14,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index f923cfd..e605ac6 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -14,4 +14,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index c734725..d21e3e9 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -11,4 +11,5 @@ CONFIG_CMD_GPIO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 6f93f1c..30d8b2b 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -22,6 +22,7 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 74f90db..81258a7 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -17,4 +17,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index ccba59b..ba6ee38 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -20,3 +20,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 9f38c37..534a31b 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -13,4 +13,5 @@ CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 5b54e75..ccfc6ba 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -21,4 +21,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 47fb0d7..b2276a9 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -26,3 +26,4 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index a15b65b..7aa8233 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -25,3 +25,4 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 2d504a5..160ce93 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -16,4 +16,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 6af9619..4b4fd27 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -16,4 +16,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index 80ae9dd..c86cedc 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -17,4 +17,5 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index be3ec0a..48ae025 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index e0790ab..845e6d3 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -19,3 +19,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 5228c84..0afc696 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -19,4 +19,5 @@ CONFIG_E1000=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 3078386..eefe971 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -23,4 +23,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index 06698b8..351da87 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -13,4 +13,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 27ace90..350ca68 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index d085ef7..4f46753 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 4273a32..47843f1 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -8,4 +8,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 60262cd..f719673 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 917362a..d6f76cc 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -12,4 +12,5 @@ CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 333eb67..6d6afd8 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 2e0363f..078a362 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -11,4 +11,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index d106d89..4e4252d 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -15,4 +15,5 @@ CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 7ba591a..338911a 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 3b46fb6..0c38e92 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 6049891..710fdef 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index ce5b61f..0563ff3 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 2e264f2..56c4b15 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 39b381f..0229eaa 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -10,4 +10,5 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index dc965cc..8ce1c2f 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -36,6 +36,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 4548cf0..da92b2d 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -21,5 +21,6 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index dbdbf96..2aea8c6 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -25,4 +25,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index ab3cac4..fdce13c 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -10,4 +10,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index fefe209..ccb9686 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -14,4 +14,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 3fc75df..024de72 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -10,4 +10,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 2ce71d4..17141fd 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -15,3 +15,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 4cff742..d258c7c 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -20,3 +20,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index cd0d325..26765d6 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 65d788a..68abec1 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -20,3 +20,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 13e27b5..f274784 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -16,4 +16,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 6f92d84..508ee47 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index d9367b3..0363980 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -16,4 +16,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 89c1195..47cf3af 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -14,3 +14,4 @@ CONFIG_SYS_PROMPT="Goni # "
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index dfcf4b7..9927012 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -14,3 +14,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 84ba329..6d25479 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -10,4 +10,5 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 313c489..6816d5a 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -13,4 +13,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 372b312..fbf7266 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -29,3 +29,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b4de001..da323db 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -29,3 +29,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index a03d161..c5efba5 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -24,3 +24,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index d5d5a5c..f1ae006 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -24,3 +24,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 52d1d18..730d9fc 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -29,3 +29,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 902b4d2..1cf2ce0 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -28,3 +28,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 8a6b337..8cdbb89 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -15,5 +15,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index dc8be76..5dca48f 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -11,4 +11,5 @@ CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 95d516f..0fd57e6 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -15,4 +15,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 60fbab9..d7f8405 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -17,3 +17,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 079233a..b5431e5 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -16,3 +16,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 49ff533..0d20697 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -21,4 +21,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index c7d185c..c51516c 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -11,4 +11,5 @@ CONFIG_CMD_GPIO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 86d65dc..81f5945 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -40,4 +40,5 @@ CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_REGEX is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 28fbd26..3bd6fca 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -17,3 +17,4 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index e561784..81d211f 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -29,3 +29,4 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index d3a0f23..75d5101 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -26,3 +26,4 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 63512dd..51b2788 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -26,3 +26,4 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index e397acb..01ca5d2 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -28,3 +28,4 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 5838d6e..969873c 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -80,4 +80,10 @@ config USB_GADGET_VBUS_DRAW
 config USB_GADGET_DUALSPEED
 	bool
 
+config USB_GADGET_DOWNLOAD
+	bool "Enable USB download gadget"
+	help
+	  Composite USB download gadget support (g_dnl) for download functions.
+	  This code works on top of composite gadget.
+
 endif # USB_GADGET
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index f0e13b8..cd78a06 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -287,7 +287,6 @@
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 8bea4c2..3643489 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -125,6 +125,7 @@
 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
 #undef CONFIG_USB_DWC3
 
+#undef CONFIG_USB_GADGET_DOWNLOAD
 #undef CONFIG_USB_GADGET_VBUS_DRAW
 #undef CONFIG_USB_GADGET_DUALSPEED
 #endif
@@ -135,7 +136,6 @@
 #define CONFIG_USB_DWC3_OMAP
 #define CONFIG_USB_DWC3_GADGET
 
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 8280e60..96a17dd 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -273,7 +273,6 @@
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index c223931..b466d48 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -438,7 +438,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index b431781..680ef16 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -139,7 +139,6 @@
 #define CONFIG_FASTBOOT_BUF_SIZE	(CONFIG_SYS_SDRAM_SIZE - SZ_1M)
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USBID_ADDR		0x34052c46
 #define CONFIG_G_DNL_VENDOR_NUM		0x18d1	/* google */
 #define CONFIG_G_DNL_PRODUCT_NUM	0x0d02	/* nexus one */
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index db207b9..403de84 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -90,7 +90,6 @@
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 3652d61..74a3874 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -243,7 +243,6 @@
 #define CONFIG_G_DNL_PRODUCT_NUM         CONFIG_TRDX_PID_COLIBRI_VF50
 
 /* USB DFU */
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 81ebda4..0b28529 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -121,7 +121,6 @@
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index a230896..70c25bf 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -231,7 +231,6 @@
 #define CONFIG_USB_DWC3_OMAP
 #define CONFIG_USB_DWC3_GADGET
 
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM 0xd022
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 7973991..a0f4aa8 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -27,9 +27,6 @@
 #define CONFIG_CMD_DFU
 #define CONFIG_CMD_GPT
 
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET_DOWNLOAD
-
 /* TIZEN THOR downloader support */
 #define CONFIG_CMD_THOR_DOWNLOAD
 #define CONFIG_USB_FUNCTION_THOR
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 711777c..0921093 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -193,7 +193,6 @@
 /* USB Mass Storage Gadget */
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 /* Netchip IDs */
 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 6a487f2..ab4cbab 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -188,8 +188,6 @@
  * Download
  */
 
-#define CONFIG_USB_GADGET_DOWNLOAD
-
 #define CONFIG_G_DNL_VENDOR_NUM		0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM	0xd022
 #define CONFIG_G_DNL_MANUFACTURER	"Texas Instruments"
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 249554c..8d8612d 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -238,7 +238,6 @@
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index fb47a6c..f62e1d4 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -261,7 +261,6 @@
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 38e38ca..f906bf2 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -330,7 +330,6 @@
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 /* Netchip IDs */
 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index e704bb4..7e91f61 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -55,7 +55,6 @@
 #define CONFIG_G_DNL_VENDOR_NUM		0x04E8
 #define CONFIG_G_DNL_PRODUCT_NUM	0x6601
 #define CONFIG_G_DNL_MANUFACTURER	"Samsung"
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 /* DFU */
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 276429e..aec8352 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -64,7 +64,6 @@
 #define CONFIG_TWL4030_USB		1
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM	0xd022
 #define CONFIG_G_DNL_MANUFACTURER	"TI"
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index b083d57..9337b89 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -83,7 +83,6 @@
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM	0xd022
 #define CONFIG_G_DNL_MANUFACTURER	"TI"
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 85e46b4..8a98934 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -104,7 +104,6 @@
 #define CONFIG_USB_DWC3_OMAP
 #define CONFIG_USB_DWC3_GADGET
 
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index e22818e..d101cf2 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -70,7 +70,6 @@
 #define CONFIG_CMD_GPT
 
 /* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 3dbe343..d630f04 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -241,8 +241,6 @@
 #define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
 #endif /* CONFIG_USB_MUSB_GADGET */
 
-#define CONFIG_USB_GADGET_DOWNLOAD
-
 /* USB DRACO ID as default */
 #define CONFIG_USBD_HS
 #define CONFIG_G_DNL_VENDOR_NUM 0x0908
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 0586aec..bafa8e3 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -175,7 +175,6 @@
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 6c8b00e..e61b115 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -205,8 +205,6 @@
  * Download
  */
 
-#define CONFIG_USB_GADGET_DOWNLOAD
-
 #define CONFIG_G_DNL_VENDOR_NUM		0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM	0xd022
 #define CONFIG_G_DNL_MANUFACTURER	"Texas Instruments"
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8494486..2da40f3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -250,8 +250,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * USB Gadget (DFU, UMS)
  */
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 805ae09..6e880a7 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -342,17 +342,12 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_USB_MUSB_GADGET
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_USB_FUNCTION_FASTBOOT
-#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#endif
-
-#ifdef CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x1f3a
 #define CONFIG_G_DNL_PRODUCT_NUM	0x1010
 #define CONFIG_G_DNL_MANUFACTURER	"Allwinner Technology"
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
 #endif
 
 #ifdef CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 0b04b3a..422b7a1 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -139,7 +139,6 @@
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 110c494..19f35bb 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -130,7 +130,6 @@
 #ifdef CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USBD_HS
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
 #define CONFIG_G_DNL_MANUFACTURER	"TBS"
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index 45db9f1..6b1247c 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -20,7 +20,6 @@
 #ifndef CONFIG_G_DNL_MANUFACTURER
 #define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
 #endif
-#define CONFIG_USB_GADGET_DOWNLOAD
 /* USB mass storage protocol */
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_CMD_USB_MASS_STORAGE
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 4e3e202..11ebbeb 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -78,7 +78,6 @@
 
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index c09b746..d572b81 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -124,8 +124,6 @@
 
 #define CONFIG_USB_DWC3_GADGET
 
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 513b527..450d487 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -98,7 +98,6 @@
 # define CONFIG_EHCI_IS_TDI
 # define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
-# define CONFIG_USB_GADGET_DOWNLOAD
 # define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x600000
 # define DFU_DEFAULT_POLL_TIMEOUT	300
 # define CONFIG_USB_FUNCTION_DFU
-- 
cgit v0.10.2


From 65403f3010ff71968197821ff693d960269785b1 Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:27 +0300
Subject: usb: dwc3: Move CONFIG_USB_DWC3_GADGET/HOST to Kconfig

Description was borrowed from kernel dwc3 Kconfig.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index b02f8ad..8dc905e 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -22,5 +22,6 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 1960429..33cc903 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -26,5 +26,6 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 942a6a0..5406beb 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 114d10f..fa01c75 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 52265c3..76d2e72 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 9166848..c437b3a 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index b2276a9..9fdd842 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -25,5 +25,6 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 7aa8233..810db5b 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -24,5 +24,6 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 160ce93..88bf379 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 4b4fd27..80961f7 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index c86cedc..f187083 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index da92b2d..cb6035b 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -20,6 +20,7 @@ CONFIG_DM_REGULATOR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 024de72..5ab2b9d 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -9,6 +9,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 81f5945..3bab31c 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -39,6 +39,7 @@ CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 # CONFIG_REGEX is not set
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index debc74b..c0251b1 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -5,3 +5,26 @@ config USB_DWC3
 	help
 	  Say Y here if your system has a Dual Role SuperSpeed
 	  USB controller based on the DesignWare USB3 IP Core.
+
+if USB_DWC3
+
+choice
+	bool "DWC3 Mode Selection"
+
+config USB_DWC3_HOST
+	bool "Host only mode"
+	depends on USB
+	help
+	  Select this when you want to use DWC3 in host mode only,
+	  thereby the gadget feature will be regressed.
+
+config USB_DWC3_GADGET
+	bool "Gadget only mode"
+	depends on USB_GADGET
+	help
+	  Select this when you want to use DWC3 in gadget mode only,
+	  thereby the host feature will be regressed.
+
+endchoice
+
+endif
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 3643489..5e0f65d 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -124,6 +124,7 @@
 /* USB GADGET */
 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
 #undef CONFIG_USB_DWC3
+#undef CONFIG_USB_DWC3_GADGET
 
 #undef CONFIG_USB_GADGET_DOWNLOAD
 #undef CONFIG_USB_GADGET_VBUS_DRAW
@@ -134,7 +135,6 @@
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 70c25bf..3fb97e8 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -229,7 +229,6 @@
 /* USB GADGET */
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 7e91f61..57e20e7 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -48,7 +48,6 @@
 #define CONFIG_USB_EHCI_EXYNOS
 
 /* DWC3 */
-#define CONFIG_USB_DWC3_GADGET
 #define CONFIG_USB_DWC3_PHY_SAMSUNG
 
 /* Downloader */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 8a98934..6853260 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -102,7 +102,6 @@
 /* USB GADGET */
 #define CONFIG_USB_DWC3_PHY_OMAP
 #define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3_GADGET
 
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index d572b81..63165df 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -122,8 +122,6 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_XHCI_ZYNQMP
 
-#define CONFIG_USB_DWC3_GADGET
-
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #define CONFIG_USB_FUNCTION_DFU
-- 
cgit v0.10.2


From c16bf621d5100a1f5c64becc82b5620810565f3e Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:28 +0300
Subject: usb: dwc3: Move CONFIG_USB_DWC3_OMAP to Kconfig

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 8dc905e..ce16f93 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -23,5 +23,6 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 33cc903..ee956a0 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -27,5 +27,6 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 5406beb..0940351 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -14,6 +14,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index fa01c75..dc25719 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -13,6 +13,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 76d2e72..4cd48c3 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -12,6 +12,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index c437b3a..6371d54 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -13,6 +13,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 9fdd842..040412d 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -26,5 +26,6 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 810db5b..28646b0 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -25,5 +25,6 @@ CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 88bf379..a460897 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -16,6 +16,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 80961f7..56a5965 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -16,6 +16,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index f187083..1121289 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -17,6 +17,7 @@ CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 5ab2b9d..9a5b91b 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index c0251b1..0bb862a 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -27,4 +27,14 @@ config USB_DWC3_GADGET
 
 endchoice
 
+comment "Platform Glue Driver Support"
+
+config USB_DWC3_OMAP
+	bool "Texas Instruments OMAP5 and similar Platforms"
+	help
+	  Some platforms from Texas Instruments like OMAP5, DRA7xxx and
+	  AM437x use this IP for USB2/3 functionality.
+
+	  Say 'Y' here if you have one such device
+
 endif
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5e0f65d..b330f1b 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -123,6 +123,7 @@
 
 /* USB GADGET */
 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+#undef CONFIG_USB_DWC3_OMAP
 #undef CONFIG_USB_DWC3
 #undef CONFIG_USB_DWC3_GADGET
 
@@ -134,7 +135,6 @@
 #if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
 #define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
 
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 3fb97e8..118bf91 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -228,7 +228,6 @@
 
 /* USB GADGET */
 #define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
 
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 6853260..533ac7b 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -101,7 +101,6 @@
 
 /* USB GADGET */
 #define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
 
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
-- 
cgit v0.10.2


From b142729d03d7295076f2c276da5694b46e511e89 Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:29 +0300
Subject: usb: dwc3: Move CONFIG_USB_DWC3_PHY_* to Kconfig

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index ce16f93..c1b26e0 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -24,5 +24,6 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index ee956a0..80ff4da 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -28,5 +28,6 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 0940351..97ea209 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -15,6 +15,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index dc25719..5963437 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -14,6 +14,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 4cd48c3..02ce1ef 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -13,6 +13,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 6371d54..9ac5c99 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -14,6 +14,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 040412d..1b8d2b9 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -27,5 +27,6 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 28646b0..2abf81e 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -26,5 +26,6 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index a460897..4dc339c 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -17,6 +17,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 56a5965..828a862 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -17,6 +17,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index 1121289..c5ff5a9 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -18,6 +18,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index cb6035b..32f6dec 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -21,6 +21,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_PHY_SAMSUNG=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 9a5b91b..7fe4fe5 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -11,6 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT=y
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 0bb862a..e93398f 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -37,4 +37,21 @@ config USB_DWC3_OMAP
 
 	  Say 'Y' here if you have one such device
 
+menu "PHY Subsystem"
+
+config USB_DWC3_PHY_OMAP
+	bool "TI OMAP SoC series USB DRD PHY driver"
+	help
+	  Enable single driver for both USB2 PHY programming and USB3 PHY
+	  programming for TI SoCs.
+
+config USB_DWC3_PHY_SAMSUNG
+	bool "Exynos5 SoC series USB DRD PHY driver"
+	help
+	  Enable USB DRD PHY support for Exynos 5 SoC series.
+	  This driver provides PHY interface for USB 3.0 DRD controller
+	  present on Exynos5 SoC series.
+
+endmenu
+
 endif
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index b330f1b..7586019 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -123,6 +123,7 @@
 
 /* USB GADGET */
 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+#undef CONFIG_USB_DWC3_PHY_OMAP
 #undef CONFIG_USB_DWC3_OMAP
 #undef CONFIG_USB_DWC3
 #undef CONFIG_USB_DWC3_GADGET
@@ -134,8 +135,6 @@
 
 #if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
-#define CONFIG_USB_DWC3_PHY_OMAP
-
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 118bf91..8d820f4 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -227,8 +227,6 @@
 #define CONFIG_OMAP_USB2PHY2_HOST
 
 /* USB GADGET */
-#define CONFIG_USB_DWC3_PHY_OMAP
-
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0451
 #define CONFIG_G_DNL_PRODUCT_NUM 0xd022
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 57e20e7..76131cd 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -47,9 +47,6 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
 
-/* DWC3 */
-#define CONFIG_USB_DWC3_PHY_SAMSUNG
-
 /* Downloader */
 #define CONFIG_G_DNL_VENDOR_NUM		0x04E8
 #define CONFIG_G_DNL_PRODUCT_NUM	0x6601
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 533ac7b..bf92212 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -100,8 +100,6 @@
 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
 
 /* USB GADGET */
-#define CONFIG_USB_DWC3_PHY_OMAP
-
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-- 
cgit v0.10.2


From e6c0bc0643e5a4387fecbcf83080d0b796eb067c Mon Sep 17 00:00:00 2001
From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 13 Apr 2016 14:20:30 +0300
Subject: usb: gadget Move: CONFIG_G_DNL_* to Kconfig

And also reformat defconfigs using "make savedefconfig" rule.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index e46efc6..77a1228 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -23,3 +23,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 4fc1a31..5a38c19 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -14,3 +14,6 @@ CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 2ec2928..5a037a9 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -20,3 +20,6 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index c0c7468..e43a121 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 8f781c8..d8e793f 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -21,4 +21,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 8e252ff..10d4311 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -28,3 +28,6 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 426ddc5..5ca0f24 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -20,4 +20,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 264fe36..bc84100 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 222fe82..4a724aa 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -13,4 +13,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 917128b..5428941 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 81b3d27..7f7a55d 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index a06f722..1ee07c9 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -22,4 +22,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_RSA=y
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index c1b26e0..69f5ac7 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -27,3 +27,6 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 80ff4da..c7a9fbe 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -31,3 +31,6 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 97ea209..d6a1c3c 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -18,4 +18,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 5963437..67a9d49 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -17,4 +17,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 02ce1ef..2194b16 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 9ac5c99..6840453 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -17,4 +17,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 882a21e..0686129 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -20,4 +20,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index 74a2881..a1fc989 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -12,3 +12,6 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 9c66669..a49b3dc 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -12,3 +12,6 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 50a6a30..8076c4f 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -11,3 +11,6 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index cd6a190..25c8ff6 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -12,3 +12,6 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 04ecab9..a67d803 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -24,4 +24,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index d9a58ad..5828e2b 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -15,4 +15,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index e605ac6..bbefb55 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -15,4 +15,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index d21e3e9..ad6f093 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -12,4 +12,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Congatec"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 30d8b2b..57e0eb5 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -23,6 +23,9 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 81258a7..583de25 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -18,4 +18,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index ba6ee38..5481f04 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -21,3 +21,6 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x0016
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 534a31b..bae8a05 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -14,4 +14,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index ccfc6ba..a1e2a73 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -22,4 +22,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 1b8d2b9..0d63986 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -30,3 +30,6 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 2abf81e..8ce544e 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -29,3 +29,6 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 4dc339c..1b1c0be 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -20,4 +20,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 828a862..0130188 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -20,4 +20,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index c5ff5a9..ca80077 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -21,4 +21,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 48ae025..7c3f828 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 845e6d3..38c085a 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -20,3 +20,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 0afc696..49ee273 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -20,4 +20,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Gateworks"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index eefe971..bf509c2 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -24,4 +24,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index 351da87..a9643cf 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -14,4 +14,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 350ca68..561e886 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 4f46753..870e403 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 47843f1..61f0a75 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -9,4 +9,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index f719673..49aa619 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index d6f76cc..84faa2f 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -13,4 +13,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 6d6afd8..7b69de1 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 078a362..540a822 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -12,4 +12,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 4e4252d..fe7e55d 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 338911a..34ddff9 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 0c38e92..c2bea2e 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 710fdef..0ce35b0 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 0563ff3..ef2f0e2 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 56c4b15..0aac630 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 0229eaa..d6280df 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 8ce1c2f..d86a55c 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -37,6 +37,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 32f6dec..bb0576a 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -24,5 +24,8 @@ CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_PHY_SAMSUNG=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 2aea8c6..a92bbe1 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -26,4 +26,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
 CONFIG_ERRNO_STR=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index fdce13c..ab54570 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -11,4 +11,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="TI"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index ccb9686..dfbd180 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -15,4 +15,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="TI"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 7fe4fe5..135c89d 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -14,4 +14,7 @@ CONFIG_USB_DWC3_OMAP=y
 CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 17141fd..de4a816 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -16,3 +16,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index d258c7c..c9f7be2 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -21,3 +21,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 26765d6..086a294 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -23,3 +23,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 68abec1..f7596a5 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -21,3 +21,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index f274784..7a53016 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -17,4 +17,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 508ee47..e3bb5ae 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 0363980..035fd1e 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -17,4 +17,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 47cf3af..8c1438d 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -15,3 +15,6 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 9927012..d91b433 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -15,3 +15,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 6d25479..ce514c2 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -11,4 +11,7 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 6816d5a..6a31771 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -14,4 +14,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index fbf7266..9c8671c 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -30,3 +30,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index da323db..b68b298 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -30,3 +30,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index c5efba5..d813dc9 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -25,3 +25,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="terasic"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index f1ae006..5fe6238 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -25,3 +25,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="denx"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 730d9fc..8894e09 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -30,3 +30,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="terasic"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 1cf2ce0..562052c 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -29,3 +29,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="ebv"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 8cdbb89..b5ab8b4 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -16,5 +16,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 5dca48f..9f6aa8d 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -12,4 +12,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="TBS"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 0fd57e6..047dc69 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -16,4 +16,7 @@ CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index d7f8405..14bdc6a 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -18,3 +18,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index b5431e5..c3b82bb 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -17,3 +17,6 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 0d20697..75e7579 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -22,4 +22,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index c51516c..b9e4648 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -12,4 +12,7 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 3bab31c..834cc45 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -42,4 +42,7 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
 # CONFIG_REGEX is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 3bd6fca..ffbc73d 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -18,3 +18,6 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 81d211f..5d9136c 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -30,3 +30,6 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 75d5101..d7c1b96 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -27,3 +27,6 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 51b2788..bc3af09 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -27,3 +27,6 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 01ca5d2..1895f95 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -29,3 +29,6 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 969873c..a35a1c7 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -86,4 +86,17 @@ config USB_GADGET_DOWNLOAD
 	  Composite USB download gadget support (g_dnl) for download functions.
 	  This code works on top of composite gadget.
 
+if USB_GADGET_DOWNLOAD
+
+config G_DNL_MANUFACTURER
+	string "Vendor name of USB device"
+
+config G_DNL_VENDOR_NUM
+	hex "Vendor ID of USB device"
+
+config G_DNL_PRODUCT_NUM
+	hex "Product ID of USB device"
+
+endif # USB_GADGET_DOWNLOAD
+
 endif # USB_GADGET
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index bd3aad9..45a484c 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -27,7 +27,7 @@
  * CONFIG_G_DNL_VENDOR_NUM
  * CONFIG_G_DNL_PRODUCT_NUM
  * CONFIG_G_DNL_MANUFACTURER
- * at e.g. ./include/configs/<board>.h
+ * at e.g. ./configs/<board>_defconfig
  */
 
 #define STRING_MANUFACTURER 25
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index cd78a06..1b1684d 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -318,11 +318,6 @@
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
 #endif /* CONFIG_DM_ETH */
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #endif /* CONFIG_USB_MUSB_GADGET */
 
 /*
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 7586019..5d5ae5e 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -121,7 +121,6 @@
 #define CONFIG_AM437X_USB2PHY2_HOST
 #endif
 
-/* USB GADGET */
 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
 #undef CONFIG_USB_DWC3_PHY_OMAP
 #undef CONFIG_USB_DWC3_OMAP
@@ -130,16 +129,12 @@
 
 #undef CONFIG_USB_GADGET_DOWNLOAD
 #undef CONFIG_USB_GADGET_VBUS_DRAW
+#undef CONFIG_G_DNL_MANUFACTURER
+#undef CONFIG_G_DNL_VENDOR_NUM
+#undef CONFIG_G_DNL_PRODUCT_NUM
 #undef CONFIG_USB_GADGET_DUALSPEED
 #endif
 
-#if !defined(CONFIG_SPL_BUILD) || \
-	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#endif
-
 /*
  * Disable MMC DM for SPL build and can be re-enabled after adding
  * DM support in SPL
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 96a17dd..48d0613 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -288,11 +288,6 @@
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #endif /* CONFIG_USB_MUSB_GADGET */
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index b466d48..2c0ec9d 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -465,11 +465,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #ifdef CONFIG_USB_MUSB_GADGET
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #endif /* CONFIG_USB_MUSB_GADGET */
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 680ef16..bd83aab 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -140,8 +140,5 @@
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
 #define CONFIG_USBID_ADDR		0x34052c46
-#define CONFIG_G_DNL_VENDOR_NUM		0x18d1	/* google */
-#define CONFIG_G_DNL_PRODUCT_NUM	0x0d02	/* nexus one */
-#define CONFIG_G_DNL_MANUFACTURER	"Broadcom Corporation"
 
 #endif /* __BCM28155_AP_H */
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 403de84..1ac9dca 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -91,10 +91,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"Congatec"
-
 /* USB Device Firmware Update support */
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 74a3874..227519f 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -238,9 +238,6 @@
 #define CONFIG_TRDX_PID_COLIBRI_VF61     0x0017
 #define CONFIG_TRDX_PID_COLIBRI_VF61IT   0x0018
 #define CONFIG_TRDX_PID_COLIBRI_VF50IT   0x0019
-#define CONFIG_G_DNL_MANUFACTURER        "Toradex"
-#define CONFIG_G_DNL_VENDOR_NUM          CONFIG_TRDX_VID
-#define CONFIG_G_DNL_PRODUCT_NUM         CONFIG_TRDX_PID_COLIBRI_VF50
 
 /* USB DFU */
 #define CONFIG_CMD_DFU
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 0b28529..a525555 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -124,11 +124,6 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
-/* USB DFU IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
-
 #define CONFIG_SYS_CACHELINE_SIZE	SZ_8K
 #define CONFIG_SYS_LOAD_ADDR	ATMEL_BASE_CS6
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d820f4..d2d16a6 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -226,11 +226,6 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_OMAP_USB2PHY2_HOST
 
-/* USB GADGET */
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index a0f4aa8..8522a79 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -37,13 +37,10 @@
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
 /* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
 #define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
 
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 0921093..747eafc 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -194,11 +194,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-/* Netchip IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "Gateworks"
-
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index ab4cbab..6cbafdd 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -185,14 +185,6 @@
 #define CONFIG_USB_MUSB_OMAP2PLUS
 
 /*
- * Download
- */
-
-#define CONFIG_G_DNL_VENDOR_NUM		0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM	0xd022
-#define CONFIG_G_DNL_MANUFACTURER	"Texas Instruments"
-
-/*
  * Fastboot
  */
 
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 8d8612d..87bbf2e 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -239,10 +239,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"FSL"
-
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_CMD_FASTBOOT
 #define CONFIG_ANDROID_BOOT_IMAGE
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index f62e1d4..ad87b24 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -262,10 +262,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"FSL"
-
 /* USB Device Firmware Update support */
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index f906bf2..cb249c0 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -331,11 +331,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-/* Netchip IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "Boundary"
-
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_CMD_FASTBOOT
 #define CONFIG_ANDROID_BOOT_IMAGE
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 76131cd..e52d7ba 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -47,11 +47,6 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
 
-/* Downloader */
-#define CONFIG_G_DNL_VENDOR_NUM		0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM	0x6601
-#define CONFIG_G_DNL_MANUFACTURER	"Samsung"
-
 /* DFU */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index aec8352..3fa8d7e 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -64,9 +64,6 @@
 #define CONFIG_TWL4030_USB		1
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_G_DNL_VENDOR_NUM		0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM	0xd022
-#define CONFIG_G_DNL_MANUFACTURER	"TI"
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_CMD_FASTBOOT
 #define CONFIG_ANDROID_BOOT_IMAGE
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 9337b89..0cb62e9 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -83,9 +83,6 @@
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_G_DNL_VENDOR_NUM		0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM	0xd022
-#define CONFIG_G_DNL_MANUFACTURER	"TI"
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_CMD_FASTBOOT
 #define CONFIG_ANDROID_BOOT_IMAGE
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index bf92212..10b97a0 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -99,11 +99,6 @@
 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
 
-/* USB GADGET */
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index d101cf2..8520423 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -80,13 +80,11 @@
 #define CONFIG_USB_FUNCTION_THOR
 
 /* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+
+#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
 #define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
 
 /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
 #define MTDIDS_DEFAULT		"onenand0=samsung-onenand"
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index d630f04..5b94fad 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -243,9 +243,6 @@
 
 /* USB DRACO ID as default */
 #define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
 
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index bafa8e3..0352379 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -178,11 +178,6 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
-/* USB DFU IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
-
 #define CONFIG_SYS_CACHELINE_SIZE	0x2000
 #endif
 
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index e61b115..2d82a66 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -202,14 +202,6 @@
 #define CONFIG_TWL4030_USB
 
 /*
- * Download
- */
-
-#define CONFIG_G_DNL_VENDOR_NUM		0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM	0xd022
-#define CONFIG_G_DNL_MANUFACTURER	"Texas Instruments"
-
-/*
  * Fastboot
  */
 
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2da40f3..0c94bac 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -260,13 +260,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 
 /* USB IDs */
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525	/* NetChip */
-#define CONFIG_G_DNL_PRODUCT_NUM	0xA4A5	/* Linux-USB File-backed Storage Gadget */
-#define CONFIG_G_DNL_UMS_VENDOR_NUM	CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_UMS_PRODUCT_NUM	CONFIG_G_DNL_PRODUCT_NUM
-#ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER	CONFIG_SYS_VENDOR
-#endif
+#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
 #endif
 
 /*
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 6e880a7..9c6c9b6 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -342,9 +342,6 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_G_DNL_VENDOR_NUM		0x1f3a
-#define CONFIG_G_DNL_PRODUCT_NUM	0x1010
-#define CONFIG_G_DNL_MANUFACTURER	"Allwinner Technology"
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 422b7a1..405ed72 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -142,11 +142,6 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
-/* USB DFU IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
-
 #define CONFIG_SYS_CACHELINE_SIZE	SZ_8K
 #endif
 
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 19f35bb..d0734a7 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -130,9 +130,6 @@
 #ifdef CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USBD_HS
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"TBS"
 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
 #define CONFIG_USB_KEYBOARD
 #ifdef CONFIG_USB_KEYBOARD
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index 6b1247c..18851ca 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -11,15 +11,6 @@
 #ifndef CONFIG_SPL_BUILD
 /* USB gadget mode support*/
 #define CONFIG_CI_UDC_HAS_HOSTPC
-#ifndef CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_VENDOR_NUM 0x0955
-#endif
-#ifndef CONFIG_G_DNL_PRODUCT_NUM
-#define CONFIG_G_DNL_PRODUCT_NUM 0x701A
-#endif
-#ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
-#endif
 /* USB mass storage protocol */
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_CMD_USB_MASS_STORAGE
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 11ebbeb..4c3df1d 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -79,10 +79,6 @@
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"FSL"
-
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 63165df..980fcb2 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -126,9 +126,6 @@
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
-#define CONFIG_G_DNL_VENDOR_NUM		0x03FD
-#define CONFIG_G_DNL_PRODUCT_NUM	0x0300
-#define CONFIG_G_DNL_MANUFACTURER	"Xilinx"
 #define CONFIG_USB_CABLE_CHECK
 #define CONFIG_CMD_DFU
 #define CONFIG_CMD_THOR_DOWNLOAD
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 450d487..23b1b2d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -102,9 +102,6 @@
 # define DFU_DEFAULT_POLL_TIMEOUT	300
 # define CONFIG_USB_FUNCTION_DFU
 # define CONFIG_DFU_RAM
-# define CONFIG_G_DNL_VENDOR_NUM	0x03FD
-# define CONFIG_G_DNL_PRODUCT_NUM	0x0300
-# define CONFIG_G_DNL_MANUFACTURER	"Xilinx"
 # define CONFIG_USB_CABLE_CHECK
 # define CONFIG_CMD_DFU
 # define CONFIG_CMD_THOR_DOWNLOAD
-- 
cgit v0.10.2


From a238b0dacffd305f78fc23b2151521cce2384311 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Wed, 20 Apr 2016 10:59:32 -0400
Subject: cmd/usb_mass_storage.c: Rework ums_init() ret logic slightly

Previously, ret could be used uninitialized if
blk_get_device_part_str() failed.  Default to ret being set to -1 so
that we always return an err up if we have a problem and then invert the
logic on testing ums_count as when that is non-zero is the time we can
return 0.

Cc: John Tobias <john.tobias.ph@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index ac53a73..b05913a 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -56,7 +56,7 @@ static int ums_init(const char *devtype, const char *devnums_part_str)
 	struct blk_desc *block_dev;
 	disk_partition_t info;
 	int partnum;
-	int ret;
+	int ret = -1;
 	struct ums *ums_new;
 
 	s = strdup(devnums_part_str);
@@ -85,16 +85,12 @@ static int ums_init(const char *devtype, const char *devnums_part_str)
 			partnum = 0;
 
 		/* f_mass_storage.c assumes SECTOR_SIZE sectors */
-		if (block_dev->blksz != SECTOR_SIZE) {
-			ret = -1;
+		if (block_dev->blksz != SECTOR_SIZE)
 			goto cleanup;
-		}
 
 		ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
-		if (!ums_new) {
-			ret = -1;
+		if (!ums_new)
 			goto cleanup;
-		}
 		ums = ums_new;
 
 		/* if partnum = 0, expose all partitions */
@@ -110,10 +106,8 @@ static int ums_init(const char *devtype, const char *devnums_part_str)
 		ums[ums_count].write_sector = ums_write_sector;
 
 		name = malloc(UMS_NAME_LEN);
-		if (!name) {
-			ret = -1;
+		if (!name)
 			goto cleanup;
-		}
 		snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
 		ums[ums_count].name = name;
 		ums[ums_count].block_dev = *block_dev;
@@ -127,9 +121,7 @@ static int ums_init(const char *devtype, const char *devnums_part_str)
 		ums_count++;
 	}
 
-	if (!ums_count)
-		ret = -1;
-	else
+	if (ums_count)
 		ret = 0;
 
 cleanup:
-- 
cgit v0.10.2


From 748c4a572804d882022cec3626b0e50870c8b449 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Wed, 20 Apr 2016 15:33:05 -0400
Subject: configs: Update some Xilinx configs

As part of 3457bba these configs didn't get updated.  Update them now.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 366aba2..7249495 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -32,6 +32,12 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 6197ad5..b4b1119 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -30,6 +30,12 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 50a957c..eb89b12 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -29,6 +29,12 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 5bd8248..bfbe053 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -29,6 +29,12 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index bd261c1..e325317 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -25,3 +25,8 @@ CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
-- 
cgit v0.10.2


From ee8b25fa354da7cfaafe0e6781e873c74c29bbad Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Thu, 21 Apr 2016 09:37:33 -0400
Subject: Prepare v2016.05-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index c35a277..66a0163 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From 2a8382c6fe7ddf0e15791b3ffa5f390a674a212b Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Sat, 16 Apr 2016 15:28:30 +0300
Subject: arc/cache: really do flush_dcache_all() even if IOC exists

flush_dcache_all() is used in the very end of U-Boot self relocation
to write back all copied and then patched code and data to their
new location in the very end of available memory space.

Since that has nothing to do with IO (i.e. no external DMA happens
here) IOC won't help here and we need to write back data cache contents
manually.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 56988dd..d1fb661 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -430,13 +430,10 @@ void invalidate_dcache_all(void)
 
 void flush_dcache_all(void)
 {
-#ifdef CONFIG_ISA_ARCV2
-	if (!ioc_exists)
-#endif
-		__dc_entire_op(OP_FLUSH);
+	__dc_entire_op(OP_FLUSH);
 
 #ifdef CONFIG_ISA_ARCV2
-	if (slc_exists && !ioc_exists)
+	if (slc_exists)
 		__slc_entire_op(OP_FLUSH);
 #endif
 }
-- 
cgit v0.10.2


From 697ec431469ce0a4c2fc2c02d8685d907491af84 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 13 Apr 2016 00:52:49 -0700
Subject: x86: qemu: Drop our own ACPI implementation

Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set)
does not build anymore after x86 has been fully converted to DM PCI.
Instead of trying to fix the build errors, given we now have the ACPI
support via QEMU's fw_cfg interface, which is a more reliable way to
generate correct ACPI tables than by ourselves, hence drop our own
ACPI implementation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 801413a..6eeddf1 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -8,6 +8,3 @@ ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
 obj-y += cpu.o fw_cfg.o qemu.o
-ifndef CONFIG_QEMU_ACPI_TABLE
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
-endif
diff --git a/arch/x86/cpu/qemu/acpi.c b/arch/x86/cpu/qemu/acpi.c
deleted file mode 100644
index 7752f80..0000000
--- a/arch/x86/cpu/qemu/acpi.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
- *
- * SPDX-License-Identifier:   GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/acpi_table.h>
-#include <asm/ioapic.h>
-#include <asm/tables.h>
-
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-		      void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase;
-
-	pci_dev_t bdf = PCI_BDF(0, 0x1f, 0);
-	pci_read_config_word(bdf, 0x40, &pmbase);
-
-	/*
-	 * TODO(saket.sinha89@gmail.com): wrong value
-	 * of pmbase by above function. Hard-coding it to
-	 * correct value. Since no PCI register is
-	 * programmed Power Management Interface is
-	 * not working
-	 */
-	pmbase = 0x0600;
-
-	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(struct acpi_fadt);
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
-	fadt->model = 0x00;
-	fadt->preferred_pm_profile = PM_MOBILE;
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0;
-	fadt->acpi_disable = 0;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0;
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x20;
-	fadt->gpe1_blk = 0;
-	fadt->pm1_evt_len = 4;
-	/*
-	 * Upper word is reserved and
-	 * Linux complains about 32 bit
-	 */
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 16;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 0x39;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x32;
-	fadt->iapc_boot_arch = 0x00;
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
-			ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER |
-			ACPI_FADT_PLATFORM_CLOCK;
-	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-	fadt->reset_value = 0x06;
-	/*
-	 * Set X_FIRMWARE_CTRL only if FACS is
-	 * above 4GB. If X_FIRMWARE_CTRL is set,
-	 * then FIRMWARE_CTRL must be zero
-	 */
-	fadt->x_firmware_ctl_l = 0;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (unsigned long)dsdt;
-	fadt->x_dsdt_h = 0;
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-	fadt->x_pm1b_evt_blk.space_id = 0;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	/*
-	 * Upper word is reserved and
-	 * Linux complains about 32 bit
-	 */
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-	fadt->x_pm1b_cnt_blk.space_id = 0;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 128;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
-	fadt->x_gpe0_blk.addrh = 0x0;
-	fadt->x_gpe1_blk.space_id = 0;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = table_compute_checksum((void *)fadt, header->length);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/*
-	 * TODO(saket.sinha89@gmail.com): get these
-	 * IRQ values from device tree
-	 */
-	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
-					   2, IO_APIC_ADDR, 0);
-	current += acpi_create_madt_irqoverride(
-		(struct acpi_madt_irqoverride *)current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride(
-		(struct acpi_madt_irqoverride *)current, 0, 9, 9, 0xd);
-	current += acpi_create_madt_irqoverride(
-		(struct acpi_madt_irqoverride *)current, 0, 0xd, 0xd, 0xd);
-	acpi_create_madt_lapic_nmi(
-		(struct acpi_madt_lapic_nmi *)current, 0, 0, 0);
-
-	return current;
-}
diff --git a/arch/x86/cpu/qemu/acpi/cpu-hotplug.asl b/arch/x86/cpu/qemu/acpi/cpu-hotplug.asl
deleted file mode 100644
index a290a4c..0000000
--- a/arch/x86/cpu/qemu/acpi/cpu-hotplug.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/* CPU hotplug */
-
-Scope(\_SB) {
-    /* Objects filled in by run-time generated SSDT */
-    External(NTFY, MethodObj)
-    External(CPON, PkgObj)
-
-    /* Methods called by run-time generated SSDT Processor objects */
-    Method(CPMA, 1, NotSerialized) {
-	    /*
-	     * _MAT method - create an madt apic buffer
-	     * Arg0 = Processor ID = Local APIC ID
-	     * Local0 = CPON flag for this cpu
-	     */
-        Store(DerefOf(Index(CPON, Arg0)), Local0)
-        /* Local1 = Buffer (in madt apic form) to return */
-        Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
-        /* Update the processor id, lapic id, and enable/disable status */
-        Store(Arg0, Index(Local1, 2))
-        Store(Arg0, Index(Local1, 3))
-        Store(Local0, Index(Local1, 4))
-        Return (Local1)
-    }
-    Method(CPST, 1, NotSerialized) {
-	    /*
-	     * _STA method - return ON status of cpu
-	     * Arg0 = Processor ID = Local APIC ID
-	     * Local0 = CPON flag for this cpu
-	     */
-        Store(DerefOf(Index(CPON, Arg0)), Local0)
-        If (Local0) {
-            Return (0xf)
-        } Else {
-            Return (0x0)
-        }
-    }
-    Method(CPEJ, 2, NotSerialized) {
-        /* _EJ0 method - eject callback */
-        Sleep(200)
-    }
-
-    /* CPU hotplug notify method */
-    OperationRegion(PRST, SystemIO, 0xaf00, 32)
-    Field(PRST, ByteAcc, NoLock, Preserve) {
-        PRS, 256
-    }
-    Method(PRSC, 0) {
-        /* Local5 = active cpu bitmap */
-        Store(PRS, Local5)
-        /* Local2 = last read byte from bitmap */
-        Store(Zero, Local2)
-        /* Local0 = Processor ID / APIC ID iterator */
-        Store(Zero, Local0)
-        While (LLess(Local0, SizeOf(CPON))) {
-            /* Local1 = CPON flag for this cpu */
-            Store(DerefOf(Index(CPON, Local0)), Local1)
-            If (And(Local0, 0x07)) {
-                /* Shift down previously read bitmap byte */
-                ShiftRight(Local2, 1, Local2)
-            } Else {
-                /* Read next byte from cpu bitmap */
-                Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
-            }
-            /* Local3 = active state for this cpu */
-            Store(And(Local2, 1), Local3)
-
-            If (LNotEqual(Local1, Local3)) {
-                /* State change - update CPON with new state */
-                Store(Local3, Index(CPON, Local0))
-                /* Do CPU notify */
-                If (LEqual(Local3, 1)) {
-                    NTFY(Local0, 1)
-                } Else {
-                    NTFY(Local0, 3)
-                }
-            }
-            Increment(Local0)
-        }
-    }
-}
diff --git a/arch/x86/cpu/qemu/acpi/dbug.asl b/arch/x86/cpu/qemu/acpi/dbug.asl
deleted file mode 100644
index 38a6526..0000000
--- a/arch/x86/cpu/qemu/acpi/dbug.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Debugging */
-
-Scope(\) {
-    /* Debug Output */
-    OperationRegion(DBG, SystemIO, 0x0402, 0x01)
-    Field(DBG, ByteAcc, NoLock, Preserve) {
-        DBGB,   8,
-    }
-	/*
-	 * Debug method - use this method to send output to the QEMU
-	 * BIOS debug port.  This method handles strings, integers,
-	 * and buffers.  For example: DBUG("abc") DBUG(0x123)
-	 */
-    Method(DBUG, 1) {
-        ToHexString(Arg0, Local0)
-        ToBuffer(Local0, Local0)
-        Subtract(SizeOf(Local0), 1, Local1)
-        Store(Zero, Local2)
-        While (LLess(Local2, Local1)) {
-            Store(DerefOf(Index(Local0, Local2)), DBGB)
-            Increment(Local2)
-        }
-        Store(0x0a, dbgb)
-    }
-}
diff --git a/arch/x86/cpu/qemu/acpi/hpet.asl b/arch/x86/cpu/qemu/acpi/hpet.asl
deleted file mode 100644
index 983151e..0000000
--- a/arch/x86/cpu/qemu/acpi/hpet.asl
+++ /dev/null
@@ -1,31 +0,0 @@
-/* HPET */
-
-Scope(\_SB) {
-    Device(HPET) {
-        Name(_HID, EISAID("PNP0103"))
-        Name(_UID, 0)
-        OperationRegion(HPTM, SystemMemory, 0xfed00000, 0x400)
-        Field(HPTM, DWordAcc, Lock, Preserve) {
-            VEND, 32,
-            PRD, 32,
-        }
-        Method(_STA, 0, NotSerialized) {
-            Store(VEND, Local0)
-            Store(PRD, Local1)
-            ShiftRight(Local0, 16, Local0)
-            If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
-                Return (0x0)
-            }
-            If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) {
-                Return (0x0)
-            }
-            Return (0x0f)
-        }
-        Name(_CRS, ResourceTemplate() {
-            Memory32Fixed(ReadOnly,
-                0xfed00000,         /* Address Base */
-                0x00000400,         /* Address Length */
-                )
-        })
-    }
-}
diff --git a/arch/x86/cpu/qemu/acpi/isa.asl b/arch/x86/cpu/qemu/acpi/isa.asl
deleted file mode 100644
index d6b3d9b..0000000
--- a/arch/x86/cpu/qemu/acpi/isa.asl
+++ /dev/null
@@ -1,102 +0,0 @@
-/* Common legacy ISA style devices. */
-Scope(\_SB.PCI0.ISA) {
-
-    Device(RTC) {
-        Name(_HID, EisaId("PNP0B00"))
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
-            IRQNoFlags() { 8 }
-            IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
-        })
-    }
-
-    Device(KBD) {
-        Name(_HID, EisaId("PNP0303"))
-        Method(_STA, 0, NotSerialized) {
-            Return (0x0f)
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
-            IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
-            IRQNoFlags() { 1 }
-        })
-    }
-
-    Device(MOU) {
-        Name(_HID, EisaId("PNP0F13"))
-        Method(_STA, 0, NotSerialized) {
-            Return (0x0f)
-        }
-        Name(_CRS, ResourceTemplate() {
-            IRQNoFlags() { 12 }
-        })
-    }
-
-    Device(FDC0) {
-        Name(_HID, EisaId("PNP0700"))
-        Method(_STA, 0, NotSerialized) {
-            Store(FDEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x03f2, 0x03f2, 0x00, 0x04)
-            IO(Decode16, 0x03f7, 0x03f7, 0x00, 0x01)
-            IRQNoFlags() { 6 }
-            DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
-        })
-    }
-
-    Device(LPT) {
-        Name(_HID, EisaId("PNP0400"))
-        Method(_STA, 0, NotSerialized) {
-            Store(LPEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
-            IRQNoFlags() { 7 }
-        })
-    }
-
-    Device(COM1) {
-        Name(_HID, EisaId("PNP0501"))
-        Name(_UID, 0x01)
-        Method(_STA, 0, NotSerialized) {
-            Store(CAEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x03f8, 0x03f8, 0x00, 0x08)
-            IRQNoFlags() { 4 }
-        })
-    }
-
-    Device(COM2) {
-        Name(_HID, EisaId("PNP0501"))
-        Name(_UID, 0x02)
-        Method(_STA, 0, NotSerialized) {
-            Store(CBEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x02f8, 0x02f8, 0x00, 0x08)
-            IRQNoFlags() { 3 }
-        })
-    }
-}
diff --git a/arch/x86/cpu/qemu/acpi/pci-crs.asl b/arch/x86/cpu/qemu/acpi/pci-crs.asl
deleted file mode 100644
index a336dce..0000000
--- a/arch/x86/cpu/qemu/acpi/pci-crs.asl
+++ /dev/null
@@ -1,61 +0,0 @@
-/* PCI CRS (current resources) definition. */
-Scope(\_SB.PCI0) {
-
-    Name(CRES, ResourceTemplate() {
-        WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
-            0x0000,             /* Address Space Granularity */
-            0x0000,             /* Address Range Minimum */
-            0x00ff,             /* Address Range Maximum */
-            0x0000,             /* Address Translation Offset */
-            0x0100,             /* Address Length */
-            ,, )
-        IO(Decode16,
-            0x0cf8,             /* Address Range Minimum */
-            0x0cf8,             /* Address Range Maximum */
-            0x01,               /* Address Alignment */
-            0x08,               /* Address Length */
-            )
-        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-            0x0000,             /* Address Space Granularity */
-            0x0000,             /* Address Range Minimum */
-            0x0cf7,             /* Address Range Maximum */
-            0x0000,             /* Address Translation Offset */
-            0x0cf8,             /* Address Length */
-            ,, , TypeStatic)
-        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-            0x0000,             /* Address Space Granularity */
-            0x0d00,             /* Address Range Minimum */
-            0xffff,             /* Address Range Maximum */
-            0x0000,             /* Address Translation Offset */
-            0xf300,             /* Address Length */
-            ,, , TypeStatic)
-        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-            0x00000000,         /* Address Space Granularity */
-            0x000a0000,         /* Address Range Minimum */
-            0x000bffff,         /* Address Range Maximum */
-            0x00000000,         /* Address Translation Offset */
-            0x00020000,         /* Address Length */
-            ,, , AddressRangeMemory, TypeStatic)
-        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
-            0x00000000,         /* Address Space Granularity */
-            0xe0000000,         /* Address Range Minimum */
-            0xfebfffff,         /* Address Range Maximum */
-            0x00000000,         /* Address Translation Offset */
-            0x1ec00000,         /* Address Length */
-            ,, PW32, AddressRangeMemory, TypeStatic)
-    })
-
-    Name(CR64, ResourceTemplate() {
-        QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-            0x00000000,          /* Address Space Granularity */
-            0x80000000,        /* Address Range Minimum */
-            0xffffffff,        /* Address Range Maximum */
-            0x00000000,          /* Address Translation Offset */
-            0x80000000,        /* Address Length */
-            ,, PW64, AddressRangeMemory, TypeStatic)
-    })
-
-    Method(_CRS, 0) {
-        Return (CRES)
-    }
-}
diff --git a/arch/x86/cpu/qemu/dsdt.asl b/arch/x86/cpu/qemu/dsdt.asl
deleted file mode 100644
index 2b10f90..0000000
--- a/arch/x86/cpu/qemu/dsdt.asl
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * QEMU ACPI DSDT ASL definition
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Copyright (c) 2010 Isaku Yamahata
- *                    yamahata at valinux co jp
- * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
- */
-
-DefinitionBlock (
-    "dsdt.aml",         /* Output Filename */
-    "DSDT",             /* Signature */
-    0x01,               /* DSDT Compliance Revision */
-    "UBOO",             /* OEMID */
-    "UBOOT   ",         /* TABLE ID */
-    0x2                 /* OEM Revision */
-    )
-{
-
-#include "acpi/dbug.asl"
-
-    Scope(\_SB) {
-        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
-        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
-        Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
-            PCIB, 8,
-        }
-    }
-
-
-/* PCI Bus definition */
-
-    Scope(\_SB) {
-        Device(PCI0) {
-            Name(_HID, EisaId("PNP0A08"))
-            Name(_CID, EisaId("PNP0A03"))
-            Name(_ADR, 0x00)
-            Name(_UID, 1)
-
-            /* _OSC: based on sample of ACPI3.0b spec */
-            Name(SUPP, 0) /* PCI _OSC Support Field value */
-            Name(CTRL, 0) /* PCI _OSC Control Field value */
-            Method(_OSC, 4) {
-                /* Create DWORD-addressable fields from Capabilities Buffer */
-                CreateDWordField(Arg3, 0, CDW1)
-
-                /* Check for proper UUID */
-                If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
-			 {
-                /* Create DWORD-addressable fields from Capabilities Buffer */
-                    CreateDWordField(Arg3, 4, CDW2)
-                    CreateDWordField(Arg3, 8, CDW3)
-
-                    /* Save Capabilities DWORD2 & 3 */
-                    Store(CDW2, SUPP)
-                    Store(CDW3, CTRL)
-
-				/*
-				 * Always allow native PME, AER (no dependencies)
-				 * Never allow SHPC (no SHPC controller in this system)
-				 */
-                    And(CTRL, 0x1d, CTRL)
-
-                    If (LNotEqual(Arg1, One)) {
-                        /* Unknown revision */
-                        Or(CDW1, 0x08, CDW1)
-                    }
-                    If (LNotEqual(CDW3, CTRL)) {
-                        /* Capabilities bits were masked */
-                        Or(CDW1, 0x10, CDW1)
-                    }
-                    /* Update DWORD3 in the buffer */
-                    Store(CTRL, CDW3)
-                } Else {
-                    Or(CDW1, 4, CDW1) /* Unrecognized UUID */
-                }
-                Return (Arg3)
-            }
-        }
-    }
-
-#include "acpi/pci-crs.asl"
-#include "acpi/hpet.asl"
-
-
-/* VGA */
-
-    Scope(\_SB.PCI0) {
-        Device(VGA) {
-            Name(_ADR, 0x00010000)
-            Method(_S1D, 0, NotSerialized) {
-                Return (0x00)
-            }
-            Method(_S2D, 0, NotSerialized) {
-                Return (0x00)
-            }
-            Method(_S3D, 0, NotSerialized) {
-                Return (0x00)
-            }
-        }
-    }
-
-
-/* LPC ISA bridge */
-
-    Scope(\_SB.PCI0) {
-        /* PCI D31:f0 LPC ISA bridge */
-        Device(ISA) {
-            /* PCI D31:f0 */
-            Name(_ADR, 0x001f0000)
-
-            /* ICH9 PCI to ISA irq remapping */
-            OperationRegion(PIRQ, PCI_Config, 0x60, 0x0c)
-
-            OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
-            Field(LPCD, AnyAcc, NoLock, Preserve) {
-                COMA,   3,
-                    ,   1,
-                COMB,   3,
-
-                Offset(0x01),
-                LPTD,   2,
-                    ,   2,
-                FDCD,   2
-            }
-            OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
-            Field(LPCE, AnyAcc, NoLock, Preserve) {
-                CAEN,   1,
-                CBEN,   1,
-                LPEN,   1,
-                FDEN,   1
-            }
-        }
-    }
-
-#include "acpi/isa.asl"
-
-
-/* PCI IRQs */
-
-    /* Zero => PIC mode, One => APIC Mode */
-    Name(\PICF, Zero)
-    Method(\_PIC, 1, NotSerialized) {
-        Store(Arg0, \PICF)
-    }
-
-    Scope(\_SB) {
-        Scope(PCI0) {
-#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
-    Package() { nr##ffff, 0, lnk0, 0 },           \
-    Package() { nr##ffff, 1, lnk1, 0 },           \
-    Package() { nr##ffff, 2, lnk2, 0 },           \
-    Package() { nr##ffff, 3, lnk3, 0 }
-
-#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
-#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
-
-#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
-#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
-#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
-#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
-
-            Name(PRTP, Package() {
-                prt_slot_lnkE(0x0000),
-                prt_slot_lnkF(0x0001),
-                prt_slot_lnkG(0x0002),
-                prt_slot_lnkH(0x0003),
-                prt_slot_lnkE(0x0004),
-                prt_slot_lnkF(0x0005),
-                prt_slot_lnkG(0x0006),
-                prt_slot_lnkH(0x0007),
-                prt_slot_lnkE(0x0008),
-                prt_slot_lnkF(0x0009),
-                prt_slot_lnkG(0x000a),
-                prt_slot_lnkH(0x000b),
-                prt_slot_lnkE(0x000c),
-                prt_slot_lnkF(0x000d),
-                prt_slot_lnkG(0x000e),
-                prt_slot_lnkH(0x000f),
-                prt_slot_lnkE(0x0010),
-                prt_slot_lnkF(0x0011),
-                prt_slot_lnkG(0x0012),
-                prt_slot_lnkH(0x0013),
-                prt_slot_lnkE(0x0014),
-                prt_slot_lnkF(0x0015),
-                prt_slot_lnkG(0x0016),
-                prt_slot_lnkH(0x0017),
-                prt_slot_lnkE(0x0018),
-
-                /* INTA -> PIRQA for slot 25 - 31
-                   see the default value of D<N>IR */
-                prt_slot_lnkA(0x0019),
-                prt_slot_lnkA(0x001a),
-                prt_slot_lnkA(0x001b),
-                prt_slot_lnkA(0x001c),
-                prt_slot_lnkA(0x001d),
-
-                /* PCIe->PCI bridge. use PIRQ[E-H] */
-                prt_slot_lnkE(0x001e),
-
-                prt_slot_lnkA(0x001f)
-            })
-
-#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
-    Package() { nr##ffff, 0, gsi0, 0 },           \
-    Package() { nr##ffff, 1, gsi1, 0 },           \
-    Package() { nr##ffff, 2, gsi2, 0 },           \
-    Package() { nr##ffff, 3, gsi3, 0 }
-
-#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
-#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
-#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
-#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
-
-#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
-#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
-#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
-#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
-
-            Name(PRTA, Package() {
-                prt_slot_gsiE(0x0000),
-                prt_slot_gsiF(0x0001),
-                prt_slot_gsiG(0x0002),
-                prt_slot_gsiH(0x0003),
-                prt_slot_gsiE(0x0004),
-                prt_slot_gsiF(0x0005),
-                prt_slot_gsiG(0x0006),
-                prt_slot_gsiH(0x0007),
-                prt_slot_gsiE(0x0008),
-                prt_slot_gsiF(0x0009),
-                prt_slot_gsiG(0x000a),
-                prt_slot_gsiH(0x000b),
-                prt_slot_gsiE(0x000c),
-                prt_slot_gsiF(0x000d),
-                prt_slot_gsiG(0x000e),
-                prt_slot_gsiH(0x000f),
-                prt_slot_gsiE(0x0010),
-                prt_slot_gsiF(0x0011),
-                prt_slot_gsiG(0x0012),
-                prt_slot_gsiH(0x0013),
-                prt_slot_gsiE(0x0014),
-                prt_slot_gsiF(0x0015),
-                prt_slot_gsiG(0x0016),
-                prt_slot_gsiH(0x0017),
-                prt_slot_gsiE(0x0018),
-
-			/*
-			 * INTA -> PIRQA for slot 25 - 31, but 30
-			 * see the default value of D<N>IR
-			 */
-                prt_slot_gsiA(0x0019),
-                prt_slot_gsiA(0x001a),
-                prt_slot_gsiA(0x001b),
-                prt_slot_gsiA(0x001c),
-                prt_slot_gsiA(0x001d),
-
-                /* PCIe->PCI bridge. use PIRQ[E-H] */
-                prt_slot_gsiE(0x001e),
-
-                prt_slot_gsiA(0x001f)
-            })
-
-            Method(_PRT, 0, NotSerialized) {
-			  /*
-			   * PCI IRQ routing table,
-			   * example from ACPI 2.0a
-			   * specification, section 6.2.8.1
-			   * Note: we provide the same info
-			   * as the PCI routing table
-			   * of the Bochs BIOS
-			   */
-                If (LEqual(\PICF, Zero)) {
-                    Return (PRTP)
-                } Else {
-                    Return (PRTA)
-                }
-            }
-        }
-
-        Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
-            PRQA,   8,
-            PRQB,   8,
-            PRQC,   8,
-            PRQD,   8,
-
-            Offset(0x08),
-            PRQE,   8,
-            PRQF,   8,
-            PRQG,   8,
-            PRQH,   8
-        }
-
-        Method(IQST, 1, NotSerialized) {
-            /* _STA method - get status */
-            If (And(0x80, Arg0)) {
-                Return (0x09)
-            }
-            Return (0x0b)
-        }
-        Method(IQCR, 1, NotSerialized) {
-            /* _CRS method - get current settings */
-            Name(PRR0, ResourceTemplate() {
-                Interrupt(, Level, ActiveHigh, Shared) { 0 }
-            })
-            CreateDWordField(PRR0, 0x05, PRRI)
-            Store(And(Arg0, 0x0f), PRRI)
-            Return (PRR0)
-        }
-
-#define define_link(link, uid, reg)                             \
-        Device(link) {                                          \
-            Name(_HID, EISAID("PNP0C0F"))                       \
-            Name(_UID, uid)                                     \
-            Name(_PRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    5, 10, 11                                   \
-                }                                               \
-            })                                                  \
-            Method(_STA, 0, NotSerialized) {                    \
-                Return (IQST(reg))                              \
-            }                                                   \
-            Method(_DIS, 0, NotSerialized) {                    \
-                Or(reg, 0x80, reg)                              \
-            }                                                   \
-            Method(_CRS, 0, NotSerialized) {                    \
-                Return (IQCR(reg))                              \
-            }                                                   \
-            Method(_SRS, 1, NotSerialized) {                    \
-                CreateDWordField(Arg0, 0x05, PRRI)              \
-                Store(PRRI, reg)                                \
-            }                                                   \
-        }
-
-        define_link(LNKA, 0, PRQA)
-        define_link(LNKB, 1, PRQB)
-        define_link(LNKC, 2, PRQC)
-        define_link(LNKD, 3, PRQD)
-        define_link(LNKE, 4, PRQE)
-        define_link(LNKF, 5, PRQF)
-        define_link(LNKG, 6, PRQG)
-        define_link(LNKH, 7, PRQH)
-
-#define define_gsi_link(link, uid, gsi)                         \
-        Device(link) {                                          \
-            Name(_HID, EISAID("PNP0C0F"))                       \
-            Name(_UID, uid)                                     \
-            Name(_PRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    gsi                                         \
-                }                                               \
-            })                                                  \
-            Name(_CRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    gsi                                         \
-                }                                               \
-            })                                                  \
-            Method(_SRS, 1, NotSerialized) {                    \
-            }                                                   \
-        }
-
-        define_gsi_link(GSIA, 0, 0x10)
-        define_gsi_link(GSIB, 0, 0x11)
-        define_gsi_link(GSIC, 0, 0x12)
-        define_gsi_link(GSID, 0, 0x13)
-        define_gsi_link(GSIE, 0, 0x14)
-        define_gsi_link(GSIF, 0, 0x15)
-        define_gsi_link(GSIG, 0, 0x16)
-        define_gsi_link(GSIH, 0, 0x17)
-    }
-
-/* General purpose events */
-
-    Scope(\_GPE) {
-        Name(_HID, "ACPI0006")
-
-        Method(_L00) {
-        }
-        Method(_L01) {
-        }
-        Method(_L02) {
-        }
-        Method(_L03) {
-        }
-        Method(_L04) {
-        }
-        Method(_L05) {
-        }
-        Method(_L06) {
-        }
-        Method(_L07) {
-        }
-        Method(_L08) {
-        }
-        Method(_L09) {
-        }
-        Method(_L0A) {
-        }
-        Method(_L0B) {
-        }
-        Method(_L0C) {
-        }
-        Method(_L0D) {
-        }
-        Method(_L0E) {
-        }
-        Method(_L0F) {
-        }
-    }
-}
-- 
cgit v0.10.2


From 7b63b1832b6e7671c4009bc084045a19cd86c87c Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 13 Apr 2016 01:00:51 -0700
Subject: x86: Correct typo of Miao Yan's email address

Miao Yan's email address is wrong in fw_cfg.c. Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
index a0a3d08..2e2794e 100644
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ b/arch/x86/cpu/qemu/fw_cfg.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com>
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-- 
cgit v0.10.2


From 68fc449033732e7eb2aa022f9ef1b292f6871b8c Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 2 Feb 2016 11:54:35 +0100
Subject: mtd, ubi: set free_count to zero before walking through erase list

Set free_count to zero before walking through ai->erase list
in wl_init().

As U-Boot has no workqueue/threads, it immediately calls
erase_worker(), which increase for each erased block
free_count. Without this patch, free_count gets after
this initialized to zero in wl_init(), so the free_count
variable always has the maybe wrong value 0.

Detected this behaviour on the dxr2 board, where the
UBI fastmap gets not written when attaching/dettaching
on an empty NAND. It drops instead the error message:

could not find any anchor PEB

With this patch, fastmap gets written on dettach.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index 507b091..e823ca5 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -1528,6 +1528,7 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 		INIT_LIST_HEAD(&ubi->pq[i]);
 	ubi->pq_head = 0;
 
+	ubi->free_count = 0;
 	list_for_each_entry_safe(aeb, tmp, &ai->erase, u.list) {
 		cond_resched();
 
@@ -1546,7 +1547,6 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 		found_pebs++;
 	}
 
-	ubi->free_count = 0;
 	list_for_each_entry(aeb, &ai->free, u.list) {
 		cond_resched();
 
-- 
cgit v0.10.2


From b1d6590d357bde2332cb699e2fd2efc7a7c64f38 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Thu, 21 Apr 2016 12:16:58 +0200
Subject: ubifs: fix memory corruption in super.c

In list "super_blocks" ubifs collects allocated super_block
structs. U-Boot frees on unmount the allocated struct,
so the pointer stored in this list is free after the umount.
On a new ubifs mount, the new allocated super_block struct
get inserted into the super_blocks list ... which contains
now a freed pointer, and the list_add_tail() corrupts the
freed memory ...

2 solutions are possible:
- remove the super_block from the super_blocks list
  on umount

- as U-Boot does not use the super_blocks list ...
  remove it complete for U-Boot.

Both solutions should not introduce problems for porting
to newer linux version, so this patch removes the unused
super_blocks list, as it saves code size and execution
time.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index dcf3a47..effa8d9 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -48,7 +48,6 @@ struct vfsmount;
 #define INODE_LOCKED_MAX	64
 
 struct super_block *ubifs_sb;
-LIST_HEAD(super_blocks);
 
 static struct inode *inodes_locked_down[INODE_LOCKED_MAX];
 
@@ -2425,10 +2424,10 @@ retry:
 	s->s_type = type;
 #ifndef __UBOOT__
 	strlcpy(s->s_id, type->name, sizeof(s->s_id));
+	list_add_tail(&s->s_list, &super_blocks);
 #else
 	strncpy(s->s_id, type->name, sizeof(s->s_id));
 #endif
-	list_add_tail(&s->s_list, &super_blocks);
 	hlist_add_head(&s->s_instances, &type->fs_supers);
 #ifndef __UBOOT__
 	spin_unlock(&sb_lock);
-- 
cgit v0.10.2


From ac13ce49a4cb9e7629d6c151b754bb15b2ba33da Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:10 +0900
Subject: pinctrl: uniphier: rename function/array names

Make function/array names match the file names for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 8f7574e..ca66dee 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -9,7 +9,7 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = {
+static const struct uniphier_pinctrl_pin uniphier_ld4_pins[] = {
 	UNIPHIER_PINCTRL_PIN(53, 0),
 	UNIPHIER_PINCTRL_PIN(54, 0),
 	UNIPHIER_PINCTRL_PIN(55, 0),
@@ -62,7 +62,7 @@ static const unsigned usb2_muxvals[] = {4, 4};
 static const unsigned usb2b_pins[] = {67, 68};
 static const unsigned usb2b_muxvals[] = {23, 23};
 
-static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
@@ -83,7 +83,7 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb2b),
 };
 
-static const char * const ph1_ld4_functions[] = {
+static const char * const uniphier_ld4_functions[] = {
 	"emmc",
 	"i2c0",
 	"i2c1",
@@ -100,30 +100,30 @@ static const char * const ph1_ld4_functions[] = {
 	"usb2",
 };
 
-static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = {
-	.pins = ph1_ld4_pins,
-	.pins_count = ARRAY_SIZE(ph1_ld4_pins),
-	.groups = ph1_ld4_groups,
-	.groups_count = ARRAY_SIZE(ph1_ld4_groups),
-	.functions = ph1_ld4_functions,
-	.functions_count = ARRAY_SIZE(ph1_ld4_functions),
+static struct uniphier_pinctrl_socdata uniphier_ld4_pinctrl_socdata = {
+	.pins = uniphier_ld4_pins,
+	.pins_count = ARRAY_SIZE(uniphier_ld4_pins),
+	.groups = uniphier_ld4_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld4_groups),
+	.functions = uniphier_ld4_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld4_functions),
 };
 
-static int ph1_ld4_pinctrl_probe(struct udevice *dev)
+static int uniphier_ld4_pinctrl_probe(struct udevice *dev)
 {
-	return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata);
+	return uniphier_pinctrl_probe(dev, &uniphier_ld4_pinctrl_socdata);
 }
 
-static const struct udevice_id ph1_ld4_pinctrl_match[] = {
+static const struct udevice_id uniphier_ld4_pinctrl_match[] = {
 	{ .compatible = "socionext,ph1-ld4-pinctrl" },
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(ph1_ld4_pinctrl) = {
-	.name = "ph1-ld4-pinctrl",
+U_BOOT_DRIVER(uniphier_ld4_pinctrl) = {
+	.name = "uniphier-ld4-pinctrl",
 	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(ph1_ld4_pinctrl_match),
-	.probe = ph1_ld4_pinctrl_probe,
+	.of_match = of_match_ptr(uniphier_ld4_pinctrl_match),
+	.probe = uniphier_ld4_pinctrl_probe,
 	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 2a5d5f3..0fd4dc4 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -9,7 +9,7 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = {
+static const struct uniphier_pinctrl_pin uniphier_ld6b_pins[] = {
 	UNIPHIER_PINCTRL_PIN(113, 0),
 	UNIPHIER_PINCTRL_PIN(114, 0),
 	UNIPHIER_PINCTRL_PIN(115, 0),
@@ -61,7 +61,7 @@ static const unsigned usb2_muxvals[] = {0, 0};
 static const unsigned usb3_pins[] = {62, 63};
 static const unsigned usb3_muxvals[] = {0, 0};
 
-static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
@@ -83,7 +83,7 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb3),
 };
 
-static const char * const ph1_ld6b_functions[] = {
+static const char * const uniphier_ld6b_functions[] = {
 	"emmc",
 	"i2c0",
 	"i2c1",
@@ -100,30 +100,30 @@ static const char * const ph1_ld6b_functions[] = {
 	"usb3",
 };
 
-static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = {
-	.pins = ph1_ld6b_pins,
-	.pins_count = ARRAY_SIZE(ph1_ld6b_pins),
-	.groups = ph1_ld6b_groups,
-	.groups_count = ARRAY_SIZE(ph1_ld6b_groups),
-	.functions = ph1_ld6b_functions,
-	.functions_count = ARRAY_SIZE(ph1_ld6b_functions),
+static struct uniphier_pinctrl_socdata uniphier_ld6b_pinctrl_socdata = {
+	.pins = uniphier_ld6b_pins,
+	.pins_count = ARRAY_SIZE(uniphier_ld6b_pins),
+	.groups = uniphier_ld6b_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld6b_groups),
+	.functions = uniphier_ld6b_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld6b_functions),
 };
 
-static int ph1_ld6b_pinctrl_probe(struct udevice *dev)
+static int uniphier_ld6b_pinctrl_probe(struct udevice *dev)
 {
-	return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata);
+	return uniphier_pinctrl_probe(dev, &uniphier_ld6b_pinctrl_socdata);
 }
 
-static const struct udevice_id ph1_ld6b_pinctrl_match[] = {
+static const struct udevice_id uniphier_ld6b_pinctrl_match[] = {
 	{ .compatible = "socionext,ph1-ld6b-pinctrl" },
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(ph1_ld6b_pinctrl) = {
-	.name = "ph1-ld6b-pinctrl",
+U_BOOT_DRIVER(uniphier_ld6b_pinctrl) = {
+	.name = "uniphier-ld6b-pinctrl",
 	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(ph1_ld6b_pinctrl_match),
-	.probe = ph1_ld6b_pinctrl_probe,
+	.of_match = of_match_ptr(uniphier_ld6b_pinctrl_match),
+	.probe = uniphier_ld6b_pinctrl_probe,
 	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index 60fbbaf..9ed7c74 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -9,7 +9,7 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = {
+static const struct uniphier_pinctrl_pin uniphier_pro4_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
@@ -54,7 +54,7 @@ static const unsigned usb2_muxvals[] = {0, 0};
 static const unsigned usb3_pins[] = {186, 187};
 static const unsigned usb3_muxvals[] = {0, 0};
 
-static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
@@ -76,7 +76,7 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb3),
 };
 
-static const char * const ph1_pro4_functions[] = {
+static const char * const uniphier_pro4_functions[] = {
 	"emmc",
 	"i2c0",
 	"i2c1",
@@ -96,31 +96,31 @@ static const char * const ph1_pro4_functions[] = {
 	"usb3",
 };
 
-static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = {
-	.pins = ph1_pro4_pins,
-	.pins_count = ARRAY_SIZE(ph1_pro4_pins),
-	.groups = ph1_pro4_groups,
-	.groups_count = ARRAY_SIZE(ph1_pro4_groups),
-	.functions = ph1_pro4_functions,
-	.functions_count = ARRAY_SIZE(ph1_pro4_functions),
+static struct uniphier_pinctrl_socdata uniphier_pro4_pinctrl_socdata = {
+	.pins = uniphier_pro4_pins,
+	.pins_count = ARRAY_SIZE(uniphier_pro4_pins),
+	.groups = uniphier_pro4_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pro4_groups),
+	.functions = uniphier_pro4_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pro4_functions),
 	.caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
 };
 
-static int ph1_pro4_pinctrl_probe(struct udevice *dev)
+static int uniphier_pro4_pinctrl_probe(struct udevice *dev)
 {
-	return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata);
+	return uniphier_pinctrl_probe(dev, &uniphier_pro4_pinctrl_socdata);
 }
 
-static const struct udevice_id ph1_pro4_pinctrl_match[] = {
+static const struct udevice_id uniphier_pro4_pinctrl_match[] = {
 	{ .compatible = "socionext,ph1-pro4-pinctrl" },
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(ph1_pro4_pinctrl) = {
-	.name = "ph1-pro4-pinctrl",
+U_BOOT_DRIVER(uniphier_pro4_pinctrl) = {
+	.name = "uniphier-pro4-pinctrl",
 	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(ph1_pro4_pinctrl_match),
-	.probe = ph1_pro4_pinctrl_probe,
+	.of_match = of_match_ptr(uniphier_pro4_pinctrl_match),
+	.probe = uniphier_pro4_pinctrl_probe,
 	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 30c9b4d..6597f1c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -9,7 +9,7 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = {
+static const struct uniphier_pinctrl_pin uniphier_pro5_pins[] = {
 	UNIPHIER_PINCTRL_PIN(47, 0),
 	UNIPHIER_PINCTRL_PIN(48, 0),
 	UNIPHIER_PINCTRL_PIN(49, 0),
@@ -67,7 +67,7 @@ static const unsigned usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {128, 129};
 static const unsigned usb2_muxvals[] = {0, 0};
 
-static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
@@ -91,7 +91,7 @@ static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb2),
 };
 
-static const char * const ph1_pro5_functions[] = {
+static const char * const uniphier_pro5_functions[] = {
 	"emmc",
 	"i2c0",
 	"i2c1",
@@ -110,31 +110,31 @@ static const char * const ph1_pro5_functions[] = {
 	"usb2",
 };
 
-static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = {
-	.pins = ph1_pro5_pins,
-	.pins_count = ARRAY_SIZE(ph1_pro5_pins),
-	.groups = ph1_pro5_groups,
-	.groups_count = ARRAY_SIZE(ph1_pro5_groups),
-	.functions = ph1_pro5_functions,
-	.functions_count = ARRAY_SIZE(ph1_pro5_functions),
+static struct uniphier_pinctrl_socdata uniphier_pro5_pinctrl_socdata = {
+	.pins = uniphier_pro5_pins,
+	.pins_count = ARRAY_SIZE(uniphier_pro5_pins),
+	.groups = uniphier_pro5_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pro5_groups),
+	.functions = uniphier_pro5_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pro5_functions),
 	.caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
 };
 
-static int ph1_pro5_pinctrl_probe(struct udevice *dev)
+static int uniphier_pro5_pinctrl_probe(struct udevice *dev)
 {
-	return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata);
+	return uniphier_pinctrl_probe(dev, &uniphier_pro5_pinctrl_socdata);
 }
 
-static const struct udevice_id ph1_pro5_pinctrl_match[] = {
+static const struct udevice_id uniphier_pro5_pinctrl_match[] = {
 	{ .compatible = "socionext,ph1-pro5-pinctrl" },
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(ph1_pro5_pinctrl) = {
-	.name = "ph1-pro5-pinctrl",
+U_BOOT_DRIVER(uniphier_pro5_pinctrl) = {
+	.name = "uniphier-pro5-pinctrl",
 	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(ph1_pro5_pinctrl_match),
-	.probe = ph1_pro5_pinctrl_probe,
+	.of_match = of_match_ptr(uniphier_pro5_pinctrl_match),
+	.probe = uniphier_pro5_pinctrl_probe,
 	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 976bb2f..cfec877 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -9,7 +9,7 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin proxstream2_pins[] = {
+static const struct uniphier_pinctrl_pin uniphier_pxs2_pins[] = {
 	UNIPHIER_PINCTRL_PIN(113, 0),
 	UNIPHIER_PINCTRL_PIN(114, 0),
 	UNIPHIER_PINCTRL_PIN(115, 0),
@@ -61,7 +61,7 @@ static const unsigned usb2_muxvals[] = {8, 8};
 static const unsigned usb3_pins[] = {62, 63};
 static const unsigned usb3_muxvals[] = {8, 8};
 
-static const struct uniphier_pinctrl_group proxstream2_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
@@ -85,7 +85,7 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb3),
 };
 
-static const char * const proxstream2_functions[] = {
+static const char * const uniphier_pxs2_functions[] = {
 	"emmc",
 	"i2c0",
 	"i2c1",
@@ -107,30 +107,30 @@ static const char * const proxstream2_functions[] = {
 	"usb3",
 };
 
-static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = {
-	.pins = proxstream2_pins,
-	.pins_count = ARRAY_SIZE(proxstream2_pins),
-	.groups = proxstream2_groups,
-	.groups_count = ARRAY_SIZE(proxstream2_groups),
-	.functions = proxstream2_functions,
-	.functions_count = ARRAY_SIZE(proxstream2_functions),
+static struct uniphier_pinctrl_socdata uniphier_pxs2_pinctrl_socdata = {
+	.pins = uniphier_pxs2_pins,
+	.pins_count = ARRAY_SIZE(uniphier_pxs2_pins),
+	.groups = uniphier_pxs2_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pxs2_groups),
+	.functions = uniphier_pxs2_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pxs2_functions),
 };
 
-static int proxstream2_pinctrl_probe(struct udevice *dev)
+static int uniphier_pxs2_pinctrl_probe(struct udevice *dev)
 {
-	return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata);
+	return uniphier_pinctrl_probe(dev, &uniphier_pxs2_pinctrl_socdata);
 }
 
-static const struct udevice_id proxstream2_pinctrl_match[] = {
+static const struct udevice_id uniphier_pxs2_pinctrl_match[] = {
 	{ .compatible = "socionext,proxstream2-pinctrl" },
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(proxstream2_pinctrl) = {
-	.name = "proxstream2-pinctrl",
+U_BOOT_DRIVER(uniphier_pxs2_pinctrl) = {
+	.name = "uniphier-pxs2-pinctrl",
 	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(proxstream2_pinctrl_match),
-	.probe = proxstream2_pinctrl_probe,
+	.of_match = of_match_ptr(uniphier_pxs2_pinctrl_match),
+	.probe = uniphier_pxs2_pinctrl_probe,
 	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index 6cbf215..5a733b3 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -9,7 +9,7 @@
 
 #include "pinctrl-uniphier.h"
 
-static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = {
+static const struct uniphier_pinctrl_pin uniphier_sld8_pins[] = {
 	UNIPHIER_PINCTRL_PIN(32, 8),
 	UNIPHIER_PINCTRL_PIN(33, 8),
 	UNIPHIER_PINCTRL_PIN(34, 8),
@@ -72,7 +72,7 @@ static const unsigned usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {114, 115};
 static const unsigned usb2_muxvals[] = {1, 1};
 
-static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
@@ -91,7 +91,7 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb2),
 };
 
-static const char * const ph1_sld8_functions[] = {
+static const char * const uniphier_sld8_functions[] = {
 	"emmc",
 	"i2c0",
 	"i2c1",
@@ -108,30 +108,30 @@ static const char * const ph1_sld8_functions[] = {
 	"usb2",
 };
 
-static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
-	.pins = ph1_sld8_pins,
-	.pins_count = ARRAY_SIZE(ph1_sld8_pins),
-	.groups = ph1_sld8_groups,
-	.groups_count = ARRAY_SIZE(ph1_sld8_groups),
-	.functions = ph1_sld8_functions,
-	.functions_count = ARRAY_SIZE(ph1_sld8_functions),
+static struct uniphier_pinctrl_socdata uniphier_sld8_pinctrl_socdata = {
+	.pins = uniphier_sld8_pins,
+	.pins_count = ARRAY_SIZE(uniphier_sld8_pins),
+	.groups = uniphier_sld8_groups,
+	.groups_count = ARRAY_SIZE(uniphier_sld8_groups),
+	.functions = uniphier_sld8_functions,
+	.functions_count = ARRAY_SIZE(uniphier_sld8_functions),
 };
 
-static int ph1_sld8_pinctrl_probe(struct udevice *dev)
+static int uniphier_sld8_pinctrl_probe(struct udevice *dev)
 {
-	return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata);
+	return uniphier_pinctrl_probe(dev, &uniphier_sld8_pinctrl_socdata);
 }
 
-static const struct udevice_id ph1_sld8_pinctrl_match[] = {
+static const struct udevice_id uniphier_sld8_pinctrl_match[] = {
 	{ .compatible = "socionext,ph1-sld8-pinctrl" },
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(ph1_sld8_pinctrl) = {
-	.name = "ph1-sld8-pinctrl",
+U_BOOT_DRIVER(uniphier_sld8_pinctrl) = {
+	.name = "uniphier-sld8-pinctrl",
 	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(ph1_sld8_pinctrl_match),
-	.probe = ph1_sld8_pinctrl_probe,
+	.of_match = of_match_ptr(uniphier_sld8_pinctrl_match),
+	.probe = uniphier_sld8_pinctrl_probe,
 	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
-- 
cgit v0.10.2


From 740314326dd49888647bf84ed44106faf2f161cd Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:11 +0900
Subject: pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20

I found many mistakes in the initial version.

Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 3d5ac5f..fe154b7 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -22,13 +22,13 @@ static const unsigned i2c3_muxvals[] = {1, 1};
 static const unsigned i2c4_pins[] = {61, 62};
 static const unsigned i2c4_muxvals[] = {1, 1};
 static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
-				     15, 16};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0};
+				     15, 16, 17};
+static const unsigned nand_muxvals[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+					2, 2, 2};
 static const unsigned nand_cs1_pins[] = {};
 static const unsigned nand_cs1_muxvals[] = {};
 static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
-static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8};  /* No SDVOLC */
+static const unsigned sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3};  /* No SDVOLC */
 static const unsigned uart0_pins[] = {54, 55};
 static const unsigned uart0_muxvals[] = {0, 0};
 static const unsigned uart1_pins[] = {58, 59};
-- 
cgit v0.10.2


From 7b3a032dd37e1cb541a7f5b3b53964481ab11201 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:12 +0900
Subject: ARM: uniphier: avoid unaligned access to DT on 64bit SoC

Because DT properties are 4-byte aligned, the pointer access
*(fdt64_t *) in this code causes unaligned access.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index 815f243..ef0e2e8 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <libfdt.h>
+#include <fdtdec.h>
 #include <linux/err.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,8 +41,7 @@ int dram_init(void)
 
 	val += ac;
 
-	gd->ram_size = sc == 2 ? fdt64_to_cpu(*(fdt64_t *)val) :
-							fdt32_to_cpu(*val);
+	gd->ram_size = fdtdec_get_number(val, sc);
 
 	debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
 
@@ -71,11 +71,9 @@ void dram_init_banksize(void)
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
 	     i++, len -= cells) {
-		gd->bd->bi_dram[i].start = ac == 2 ?
-			fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val);
+		gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
 		val += ac;
-		gd->bd->bi_dram[i].size = sc == 2 ?
-			fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val);
+		gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
 		val += sc;
 
 		debug("DRAM bank %d: start = %08lx, size = %08lx\n",
-- 
cgit v0.10.2


From 1222addb3f7077309c5fc13b75bf7d1f40bec549 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:13 +0900
Subject: ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref board

This makes the EEPROM device on the Reference Daughter board
available.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
index 108adeb..1af2ebe 100644
--- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 /include/ "uniphier-ph1-ld20.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
 /include/ "uniphier-support-card.dtsi"
 
 / {
-- 
cgit v0.10.2


From 6c64d50e47cbb9f68f53cc67f178d1a09f63b369 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:14 +0900
Subject: ARM: dts: uniphier: move aliases node up to satisfy fdtgrep

Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb
and uniphier-ph1-ld11-ref.dtb unless the aliases node comes
the first in the root node.

$ make -s uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref
  [snip]
  LDS     spl/u-boot-spl.lds
  LD      spl/u-boot-spl
  OBJCOPY spl/u-boot-spl-nodtb.bin
  FDTGREP spl/u-boot-spl.dtb
Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT
/aliases node must come before all other nodes
Error: FDT_ERR_BADMAGIC
make[1]: *** [spl/u-boot-spl.dtb] Error 1
make: *** [spl/u-boot-spl] Error 2

This commit moves the aliases node as the error message from the
fdtgrep tool suggests, although this requirement does not sound
reasonable to me.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index a624a49..88e7f53 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -14,15 +14,6 @@
 	model = "UniPhier PH1-LD11 Reference Board";
 	compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
 
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x40000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	aliases {
 		serial0 = &serial0;
 		serial1 = &serial1;
@@ -35,6 +26,15 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &ethsc {
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
index 1af2ebe..3049016 100644
--- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
@@ -15,15 +15,6 @@
 	model = "UniPhier PH1-LD20 Reference Board";
 	compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
 
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0xc0000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	aliases {
 		serial0 = &serial0;
 		serial1 = &serial1;
@@ -36,6 +27,15 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xc0000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &ethsc {
-- 
cgit v0.10.2


From 612ccd90012d7c77bbe67ec65f770b9e82fe4a35 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:15 +0900
Subject: ARM: uniphier: add sg_set_iectrl_range()

For PH1-LD20 or later, per-pin input-enable control is supported,
that is, we need to set-up IECTRL registers for a group of pins.
This helper function will be useful for a bunch of register settings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 2cdc2db..4044245 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -126,6 +126,14 @@ static inline void sg_set_iectrl(unsigned pin)
 	writel(tmp, reg);
 }
 
+static inline void sg_set_iectrl_range(unsigned min, unsigned max)
+{
+	int i;
+
+	for (i = min; i <= max; i++)
+		sg_set_iectrl(i);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* ARCH_SG_REGS_H */
-- 
cgit v0.10.2


From d90b9745ea1b0972e920605673e5895fb09cf3e7 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:16 +0900
Subject: ARM: uniphier: carry on booting for Unknown boot mode

No need to stop booting U-Boot even if boot mode is unknown.
Setting the "bootmode" environment is only useful for booting
Linux Kernel.  Anyway, U-Boot has already booted by this point.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 6e2008c..591b972 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -85,8 +85,8 @@ int board_late_init(void)
 		setenv("bootmode", "usbboot");
 		break;
 	default:
-		printf("Unsupported Boot Mode\n");
-		return -1;
+		printf("Unknown\n");
+		break;
 	}
 
 	uniphier_set_fdt_file();
-- 
cgit v0.10.2


From 881aa5a79a94a65500959428328f348a18d3d9fe Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:17 +0900
Subject: ARM: uniphier: rework uniphier_set_fdt_file()

The current table look-up for the DTB file name turned out bothersome
in terms of maintainability; I ended up adding a new entry every time
a new board is supported.

There is a common pattern between the DT compatible string and the
corresponding file name; drop the vendor prefix "socionext," and
prefix it with "uniphier-" and suffix it with ".dtb".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 591b972..845f047 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -28,38 +28,37 @@ static void nand_denali_wp_disable(void)
 #endif
 }
 
-struct uniphier_fdt_file {
-	const char *compatible;
-	const char *file_name;
-};
-
-static const struct uniphier_fdt_file uniphier_fdt_files[] = {
-	{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
-	{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
-	{ "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
-	{ "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", },
-	{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
-	{ "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", },
-	{ "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
-	{ "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
-	{ "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
-	{ "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
-	{ "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
-};
-
-static void uniphier_set_fdt_file(void)
+#define VENDOR_PREFIX		"socionext,"
+#define DTB_FILE_PREFIX		"uniphier-"
+
+static int uniphier_set_fdt_file(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	int i;
-
-	/* lookup DTB file name based on the compatible string */
-	for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) {
-		if (!fdt_node_check_compatible(gd->fdt_blob, 0,
-					uniphier_fdt_files[i].compatible)) {
-			setenv("fdt_file", uniphier_fdt_files[i].file_name);
-			return;
-		}
-	}
+	const char *compat;
+	char dtb_name[256];
+	int buf_len = 256;
+	int ret;
+
+	ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat);
+	if (ret)
+		return -EINVAL;
+
+	if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX)))
+		return -EINVAL;
+
+	compat += strlen(VENDOR_PREFIX);
+
+	strncat(dtb_name, DTB_FILE_PREFIX, buf_len);
+	buf_len -= strlen(DTB_FILE_PREFIX);
+
+	strncat(dtb_name, compat, buf_len);
+	buf_len -= strlen(compat);
+
+	strncat(dtb_name, ".dtb", buf_len);
+
+	setenv("fdt_file", dtb_name);
+
+	return 0;
 }
 
 int board_late_init(void)
@@ -89,7 +88,8 @@ int board_late_init(void)
 		break;
 	}
 
-	uniphier_set_fdt_file();
+	if (uniphier_set_fdt_file())
+		printf("fdt_file environment was not set correctly\n");
 
 	return 0;
 }
-- 
cgit v0.10.2


From 9d0c2ceb35be7016977560a92fc67e3e704e5c9f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:18 +0900
Subject: ARM: uniphier: add PH1-LD20 SoC support

This is the first ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 4724af5..87d1675 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
 	bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
 	select CPU_V7
 
+config ARCH_UNIPHIER_LD20
+	bool "UniPhier PH1-LD20 SoC"
+	select ARM64
+	select SPL_SEPARATE_BSS
+
 endchoice
 
 config ARCH_UNIPHIER_LD4
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 35edca1..774ea99 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
 
 obj-$(CONFIG_CPU_V7) += arm32/
+obj-$(CONFIG_ARM64) += arm64/
diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile
new file mode 100644
index 0000000..5ed030a
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += timer.o
+else
+obj-y += mem_map.o smp.o smp_kick_cpus.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
+endif
diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
new file mode 100644
index 0000000..607f96a
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -0,0 +1,41 @@
+/*
+ * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CCI500_BASE			0x5FD00000
+#define CCI500_SLAVE_OFFSET		0x1000
+
+#define CCI500_SNOOP_CTRL
+#define   CCI500_SNOOP_CTRL_EN_DVM	BIT(1)
+#define   CCI500_SNOOP_CTRL_EN_SNOOP	BIT(0)
+
+void cci500_init(unsigned int nr_slaves)
+{
+	unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
+	int i;
+
+	for (i = 0; i < nr_slaves; i++) {
+		void __iomem *base;
+		u32 tmp;
+
+		base = map_sysmem(slave_base, SZ_4K);
+
+		tmp = readl(base);
+		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
+		writel(tmp, base);
+
+		unmap_sysmem(base);
+
+		slave_base += CCI500_SLAVE_OFFSET;
+	}
+}
diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c
new file mode 100644
index 0000000..74ef919
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/mem_map.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region uniphier_mem_map[] = {
+	{
+		.base = 0x00000000,
+		.size = 0x80000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.base = 0x80000000,
+		.size = 0xc0000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+	{ /* sentinel */ }
+};
+
+struct mm_region *mem_map = uniphier_mem_map;
diff --git a/arch/arm/mach-uniphier/arm64/smp.S b/arch/arm/mach-uniphier/arm64/smp.S
new file mode 100644
index 0000000..9348ec9
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/smp.S
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(uniphier_smp_setup)
+	mrs	x0, s3_1_c15_c2_1	/* CPUECTLR_EL1 */
+	orr	x0, x0, #(1 << 6)	/* SMPEN */
+	msr	s3_1_c15_c2_1, x0
+	ret
+ENDPROC(uniphier_smp_setup)
+
+ENTRY(uniphier_secondary_startup)
+	bl	uniphier_smp_setup
+	b	_start
+ENDPROC(uniphier_secondary_startup)
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
new file mode 100644
index 0000000..64412e0
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define UNIPHIER_SMPCTRL_ROM_RSV0	0x59801200
+
+void uniphier_smp_setup(void);
+void uniphier_secondary_startup(void);
+
+void uniphier_smp_kick_all_cpus(void)
+{
+	void __iomem *rom_boot_rsv0;
+
+	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
+
+	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
+	readq(rom_boot_rsv0);	/* relax */
+
+	unmap_sysmem(rom_boot_rsv0);
+
+	uniphier_smp_setup();
+
+	asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+}
diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c
new file mode 100644
index 0000000..4beab9d
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/timer.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CNT_CONTROL_BASE	0x60E00000
+
+#define CNTCR			0x000
+#define   CNTCR_EN			BIT(0)
+
+/* setup ARMv8 Generic Timer */
+int timer_init(void)
+{
+	void __iomem *base;
+	u32 tmp;
+
+	base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
+
+	/*
+	 * Note:
+	 * In a system that implements both Secure and Non-secure states,
+	 * this register is only writable in Secure state.
+	 */
+	tmp = readl(base + CNTCR);
+	tmp |= CNTCR_EN;
+	writel(tmp, base + CNTCR);
+
+	unmap_sysmem(base);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c
index 020ffca..330d690 100644
--- a/arch/arm/mach-uniphier/board_common.c
+++ b/arch/arm/mach-uniphier/board_common.c
@@ -8,9 +8,13 @@
 
 #include "micro-support-card.h"
 
+void uniphier_smp_kick_all_cpus(void);
+
 int board_init(void)
 {
 	led_puts("Uboo");
-
+#ifdef CONFIG_ARM64
+	uniphier_smp_kick_all_cpus();
+#endif
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 6f2adf1..2a7ae1b 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -62,6 +62,14 @@ int board_early_init_f(void)
 		uniphier_pxs2_clk_init();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_pin_init();
+		led_puts("U1");
+		uniphier_ld20_clk_init();
+		cci500_init(2);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 0d2b94d..f0547c3 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+static const struct uniphier_board_data uniphier_ld20_data = {
+	.dram_freq = 1866,
+	.dram_nr_ch = 3,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[1] = {
+		.base = 0xc0000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[2] = {
+		.base = 0x100000000UL,
+		.size = 0x40000000,
+		.width = 32,
+	},
+};
+#endif
+
 struct uniphier_board_id {
 	const char *compatible;
 	const struct uniphier_board_data *param;
@@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
+#endif
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 278df64..6cd096e 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-mode-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-mode-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-mode-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
 
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h
index 2e05a47..bd44d73 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h
@@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void);
 u32 uniphier_ld4_boot_device(void);
 u32 uniphier_pro5_boot_device(void);
 u32 uniphier_pxs2_boot_device(void);
+u32 uniphier_ld20_boot_device(void);
 
 void uniphier_sld3_boot_mode_show(void);
 void uniphier_ld4_boot_mode_show(void);
 void uniphier_pro5_boot_mode_show(void);
 void uniphier_pxs2_boot_mode_show(void);
+void uniphier_ld20_boot_mode_show(void);
 
 u32 spl_boot_device_raw(void);
 
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
new file mode 100644
index 0000000..100275e
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI             Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI             Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI             Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI             Addr 5)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+	return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_ld20_boot_device(void)
+{
+	int boot_mode;
+
+	if (~readl(SG_PINMON0) & 0x00000780)
+		return BOOT_DEVICE_USB;
+
+	boot_mode = get_boot_mode_sel();
+
+	return boot_device_table[boot_mode].type;
+}
+
+void uniphier_ld20_boot_mode_show(void)
+{
+	int mode_sel, i;
+
+	mode_sel = get_boot_mode_sel();
+
+	puts("Boot Mode Pin:\n");
+
+	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+		       boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index b08cd6c..48e478c 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -39,6 +39,10 @@ u32 spl_boot_device_raw(void)
 	case SOC_UNIPHIER_LD6B:
 		return uniphier_pxs2_boot_device();
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		return uniphier_ld20_boot_device();
+#endif
 	default:
 		return BOOT_DEVICE_NONE;
 	}
diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
index bccab62..fa97dc5 100644
--- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
@@ -39,6 +39,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		uniphier_pxs2_boot_mode_show();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_boot_mode_show();
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 1d736a5..93e9d91 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c
new file mode 100644
index 0000000..556a30a
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+void uniphier_ld20_clk_init(void)
+{
+}
diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c
index aae8d1f..f9646c0 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -48,7 +48,7 @@ int print_cpuinfo(void)
 		puts("PH1-LD11 ()");
 		break;
 	case 0x32:
-		puts("PH1-LD20 ()");
+		puts("PH1-LD20 (SC1401AJ1)");
 		break;
 	default:
 		printf("Unknown Processor ID (0x%x)\n", revision);
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 615ba2c..41aa53b 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= umc-sld8.o \
 					   ddrphy-training.o ddrphy-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= umc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= umc-ld20.o
 
 else
 
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
new file mode 100644
index 0000000..b1b4cb0
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef _DDRPHY_LD20_REGS_H
+#define _DDRPHY_LD20_REGS_H
+
+#define PHY_SCL_DATA_0			0x00000104
+#define PHY_SCL_DATA_1			0x00000108
+#define PHY_SCL_LATENCY			0x0000010C
+#define PHY_SCL_START			0x00000100
+#define PHY_SCL_CONFIG_1		0x00000118
+#define PHY_SCL_CONFIG_2		0x0000011C
+#define PHY_PAD_CTRL			0x00000120
+#define PHY_DLL_RECALIB			0x00000124
+#define PHY_DLL_ADRCTRL			0x00000128
+#define PHY_LANE_SEL			0x0000012C
+#define PHY_DLL_TRIM_1			0x00000130
+#define PHY_DLL_TRIM_2			0x00000134
+#define PHY_DLL_TRIM_3			0x00000138
+#define PHY_SCL_MAIN_CLK_DELTA		0x00000140
+#define PHY_WRLVL_AUTOINC_TRIM		0x0000014C
+#define PHY_WRLVL_DYN_ODT		0x00000150
+#define PHY_WRLVL_ON_OFF		0x00000154
+#define PHY_UNQ_ANALOG_DLL_1		0x0000015C
+#define PHY_DLL_INCR_TRIM_1		0x00000164
+#define PHY_DLL_INCR_TRIM_3		0x00000168
+#define PHY_SCL_CONFIG_3		0x0000016C
+#define PHY_UNIQUIFY_TSMC_IO_1		0x00000170
+#define PHY_SCL_START_ADDR		0x00000188
+#define PHY_DSCL_CNT		        0x0000019C
+#define PHY_DLL_TRIM_CLK		0x000001A4
+#define PHY_DYNAMIC_BIT_LVL		0x000001AC
+#define PHY_SCL_WINDOW_TRIM		0x000001B4
+#define PHY_DISABLE_GATING_FOR_SCL	0x000001B8
+#define PHY_SCL_CONFIG_4		0x000001BC
+#define PHY_DYNAMIC_WRITE_BIT_LVL	0x000001C0
+#define PHY_VREF_TRAINING		0x000001C8
+#define PHY_SCL_GATE_TIMING		0x000001E0
+
+#endif /* _DDRPHY_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
new file mode 100644
index 0000000..46e513c
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef UMC_LD20_REGS_H
+#define UMC_LD20_REGS_H
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_CMDCTLC		0x00000008
+#define UMC_INITCTLA		0x00000020
+#define UMC_INITCTLB		0x00000024
+#define UMC_INITCTLC		0x00000028
+#define UMC_DRMMR0		0x00000030
+#define UMC_DRMMR1		0x00000034
+#define UMC_DRMMR2		0x00000038
+#define UMC_DRMMR3		0x0000003C
+#define UMC_INITSET		0x00000040
+#define UMC_INITSTAT		0x00000044
+#define UMC_CMDCTLE		0x00000050
+#define UMC_SPCSETB		0x00000084
+#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
+#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
+#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
+#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
+#define UMC_ACSCTLA		0x000000C0
+#define UMC_ACSSETA		0x000000C4
+#define UMC_MEMCONF0A		0x00000200
+#define UMC_MEMCONF0B		0x00000204
+#define UMC_MEMCONFCH		0x00000240
+#define UMC_MEMMAPSET		0x00000250
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_ODTCTL_D0		0x00000618
+#define UMC_ODTCTL_D1		0x0000061C
+#define UMC_RESPCTL		0x00000624
+#define UMC_DIRECTBUSCTRLA	0x00000680
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_ERRMASKA		0x00000958
+#define UMC_ERRMASKB		0x0000095C
+#define UMC_BSICMAPSET		0x00000988
+#define UMC_DIOCTLA		0x00000C00
+#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
+#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
+#define UMC_DFISTCTLC		0x00000C18
+#define UMC_DFICUPDCTLA		0x00000C20
+#define UMC_DFIPUPDCTLA		0x00000C30
+#define UMC_DFICSOVRRD		0x00000C84
+#define UMC_DFITURNOFF          0x00000C88
+
+/* UM registers */
+#define UMC_MBUS0		0x00080004
+#define UMC_MBUS1		0x00081004
+#define UMC_MBUS2		0x00082004
+#define UMC_MBUS3		0x00000C78
+#define UMC_MBUS4		0x00000CF8
+#define UMC_MBUS5		0x00000E78
+#define UMC_MBUS6		0x00000EF8
+#define UMC_MBUS7		0x00001278
+#define UMC_MBUS8		0x000012F8
+#define UMC_MBUS9		0x00002478
+#define UMC_MBUS10		0x000024F8
+
+#endif /* UMC_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
new file mode 100644
index 0000000..4614dac
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-ld20-regs.h"
+#include "umc-ld20-regs.h"
+
+#define DRAM_CH_NR	3
+
+enum dram_freq {
+	DRAM_FREQ_1866M,
+	DRAM_FREQ_NR,
+};
+
+enum dram_size {
+	DRAM_SZ_256M,
+	DRAM_SZ_512M,
+	DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
+static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
+static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
+static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
+static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
+
+static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
+static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+	{0x0049071D, 0x0078071D},
+};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+
+static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
+static u32 umc_directbusctrla[DRAM_CH_NR] = {
+	0x00000000, 0x00000001, 0x00000001
+};
+
+/* DDR PHY */
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
+{
+	writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+	while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
+	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
+	writel(0x00000000, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000006, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x0000000c, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000012, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
+	writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
+	writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
+	writel(0x00000070, phy_base + PHY_VREF_TRAINING);
+	writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
+	writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
+	writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
+	writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
+	writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
+	writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
+	writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
+	writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
+	writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
+	writel(0x00000000, phy_base + PHY_LANE_SEL);
+	writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
+	writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
+	writel(0x00005076, phy_base + PHY_SCL_LATENCY);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+	writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
+	writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
+	writel(0x50000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+	writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
+	writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
+	writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
+	writel(0x11000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
+	writel(0x30500000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+	writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
+	writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
+	writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
+	writel(0x11000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x34000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+
+	return 0;
+}
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+		       unsigned long size, int ch)
+{
+	enum dram_size size_e;
+
+	switch (size) {
+	case 0:
+		return 0;
+	case SZ_256M:
+		size_e = DRAM_SZ_256M;
+		break;
+	case SZ_512M:
+		size_e = DRAM_SZ_512M;
+		break;
+	default:
+		pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
+		       size, ch);
+		return -EINVAL;
+	}
+
+	/* Wait for PHY Init Complete */
+	while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
+		cpu_relax();
+
+	writel(0x00000001, dc_base + UMC_DFICSOVRRD);
+	writel(0x00000000, dc_base + UMC_DFITURNOFF);
+
+	writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
+	writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
+	writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
+
+	writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
+	writel(0x00000004, dc_base + UMC_DRMMR1);
+	writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
+	writel(0x00000000, dc_base + UMC_DRMMR3);
+
+	writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
+	writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
+	writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+	writel(0x00000008, dc_base + UMC_MEMMAPSET);
+
+	writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+	writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+	writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+	writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
+
+	writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+	writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+	writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+	writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+	writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+	writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+	writel(umc_dataset[freq], dc_base + UMC_DATASET);
+
+	writel(0x00400020, dc_base + UMC_DCCGCTL);
+	writel(0x00000003, dc_base + UMC_ACSCTLA);
+	writel(0x00000103, dc_base + UMC_FLOWCTLG);
+	writel(0x00010200, dc_base + UMC_ACSSETA);
+
+	writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
+	writel(0x00004444, dc_base + UMC_FLOWCTLC);
+	writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
+
+	writel(0x00202000, dc_base + UMC_FLOWCTLB);
+	writel(0x00000000, dc_base + UMC_BSICMAPSET);
+	writel(0x00000000, dc_base + UMC_ERRMASKA);
+	writel(0x00000000, dc_base + UMC_ERRMASKB);
+
+	writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
+
+	writel(0x00000001, dc_base + UMC_INITSET);
+	/* Wait for PHY Init Complete */
+	while (readl(dc_base + UMC_INITSTAT) & BIT(0))
+		cpu_relax();
+
+	writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
+	writel(0x00000000, dc_base + UMC_DFICSOVRRD);
+
+	return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
+		       enum dram_freq freq, unsigned long size, int ch)
+{
+	void __iomem *dc_base = umc_ch_base + 0x00011000;
+	void __iomem *phy_base = phy_ch_base;
+	int ret;
+
+	/* PHY Update Mode (ON) */
+	writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
+
+	/* deassert PHY reset signals */
+	writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+	       dc_base + UMC_DIOCTLA);
+
+	ddrphy_init(phy_base, freq);
+
+	ret = umc_dc_init(dc_base, freq, size, ch);
+	if (ret)
+		return ret;
+
+	ret = ddrphy_training(phy_base);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+	writel(0x000000ff, um_base + UMC_MBUS0);
+	writel(0x000000ff, um_base + UMC_MBUS1);
+	writel(0x000000ff, um_base + UMC_MBUS2);
+	writel(0x00000001, um_base + UMC_MBUS3);
+	writel(0x00000001, um_base + UMC_MBUS4);
+	writel(0x00000001, um_base + UMC_MBUS5);
+	writel(0x00000001, um_base + UMC_MBUS6);
+	writel(0x00000001, um_base + UMC_MBUS7);
+	writel(0x00000001, um_base + UMC_MBUS8);
+	writel(0x00000001, um_base + UMC_MBUS9);
+	writel(0x00000001, um_base + UMC_MBUS10);
+}
+
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
+{
+	void __iomem *um_base = (void __iomem *)0x5b600000;
+	void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
+	void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
+	enum dram_freq freq;
+	int ch, ret;
+
+	switch (bd->dram_freq) {
+	case 1866:
+		freq = DRAM_FREQ_1866M;
+		break;
+	default:
+		pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+		return -EINVAL;
+	}
+
+	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+		unsigned long size = bd->dram_ch[ch].size;
+		unsigned int width = bd->dram_ch[ch].width;
+
+		ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
+				  size / (width / 16), ch);
+		if (ret) {
+			pr_err("failed to initialize UMC ch%d\n", ch);
+			return ret;
+		}
+
+		umc_ch_base += 0x00200000;
+		phy_ch_base += 0x00004000;
+	}
+
+	um_init(um_base);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 59058cd..9242b41 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
new file mode 100644
index 0000000..37adb37
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL7);
+	tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 |
+		SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 |
+		SC_RSTCTRL7_UMC30;
+	writel(tmp, SC_RSTCTRL7);
+
+	/* provide clocks */
+	tmp = readl(SC_CLKCTRL7);
+	tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
+							SC_CLKCTRL7_UMC30;
+	writel(tmp, SC_CLKCTRL7);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 3abf4aa..f5b3fa8 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
@@ -86,6 +87,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
 
@@ -93,6 +95,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
 
 void uniphier_sld3_pin_init(void);
 void uniphier_ld4_pin_init(void);
@@ -101,11 +104,15 @@ void uniphier_sld8_pin_init(void);
 void uniphier_pro5_pin_init(void);
 void uniphier_pxs2_pin_init(void);
 void uniphier_ld6b_pin_init(void);
+void uniphier_ld20_pin_init(void);
 
 void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
+void uniphier_ld20_clk_init(void);
+
+void cci500_init(int nr_slaves);
 
 #define pr_err(fmt, args...)	printf(fmt, ##args)
 
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index 34b15e3..b58e6c8 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= init-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= init-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= init-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= init-ld20.o
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
new file mode 100644
index 0000000..0ad264c
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld20_init(const struct uniphier_board_data *bd)
+{
+	uniphier_sbc_init_savepin(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+	uniphier_pxs2_memconf_init(bd);
+
+	led_puts("L1");
+
+	uniphier_ld20_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	{
+		int res;
+
+		res = uniphier_ld20_umc_init(bd);
+		if (res < 0) {
+			while (1)
+				;
+		}
+	}
+
+	led_puts("L5");
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index c56c44c..15a53ce 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -55,6 +55,11 @@ void spl_board_init(void)
 		uniphier_pxs2_init(param);
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_init(param);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile
index 78bb677..6ed1419 100644
--- a/arch/arm/mach-uniphier/memconf/Makefile
+++ b/arch/arm/mach-uniphier/memconf/Makefile
@@ -6,3 +6,4 @@ obj-y					+= memconf.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= memconf-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= memconf-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= memconf-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= memconf-pxs2.o
diff --git a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
index bf14d0d..e98eb48 100644
--- a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
+++ b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c
@@ -49,6 +49,9 @@ int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
 	case SZ_512M:
 		tmp |= SG_MEMCONF_CH2_SZ_512M;
 		break;
+	case SZ_1G:
+		tmp |= SG_MEMCONF_CH2_SZ_1G;
+		break;
 	default:
 		pr_err("error: unsupported DRAM Ch2 size\n");
 		return -EINVAL;
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index 5504c24..b579cb0 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pinctrl-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= pinctrl-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= pinctrl-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
new file mode 100644
index 0000000..6066b16
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld20_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(3, 0, 8, 4);	/* XNFWP   -> XNFWP */
+	sg_set_pinsel(4, 0, 8, 4);	/* XNFCE0  -> XNFCE0 */
+	sg_set_pinsel(5, 0, 8, 4);	/* NFRYBY0 -> NFRYBY0 */
+	sg_set_pinsel(6, 0, 8, 4);	/* XNFRE   -> XNFRE */
+	sg_set_pinsel(7, 0, 8, 4);	/* XNFWE   -> XNFWE */
+	sg_set_pinsel(8, 0, 8, 4);	/* NFALE   -> NFALE */
+	sg_set_pinsel(9, 0, 8, 4);	/* NFCLE   -> NFCLE */
+	sg_set_pinsel(10, 0, 8, 4);	/* NFD0    -> NFD0 */
+	sg_set_pinsel(11, 0, 8, 4);	/* NFD1    -> NFD1 */
+	sg_set_pinsel(12, 0, 8, 4);	/* NFD2    -> NFD2 */
+	sg_set_pinsel(13, 0, 8, 4);	/* NFD3    -> NFD3 */
+	sg_set_pinsel(14, 0, 8, 4);	/* NFD4    -> NFD4 */
+	sg_set_pinsel(15, 0, 8, 4);	/* NFD5    -> NFD5 */
+	sg_set_pinsel(16, 0, 8, 4);	/* NFD6    -> NFD6 */
+	sg_set_pinsel(17, 0, 8, 4);	/* NFD7    -> NFD7 */
+	sg_set_iectrl_range(3, 17);
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(46, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(47, 0, 8, 4);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(48, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(49, 0, 8, 4);	/* USB1OD   -> USB1OD */
+	sg_set_pinsel(50, 0, 8, 4);	/* USB2VBUS -> USB2VBUS */
+	sg_set_pinsel(51, 0, 8, 4);	/* USB2OD   -> USB2OD */
+	sg_set_pinsel(52, 0, 8, 4);	/* USB3VBUS -> USB3VBUS */
+	sg_set_pinsel(53, 0, 8, 4);	/* USB3OD   -> USB3OD */
+	sg_set_iectrl_range(46, 53);
+#endif
+}
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index e515af9..3c1e92a 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 4044245..1d71ce8 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -50,10 +50,11 @@
 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
+/* PH1-LD6b, ProXstream2, PH1-LD20 only */
 #define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
 
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
new file mode 100644
index 0000000..3a5bf02
--- /dev/null
+++ b/configs/uniphier_ld20_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_LD20=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index c6fc90f..fb405a9 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -71,8 +71,7 @@
 /* serial console configuration */
 #define CONFIG_BAUDRATE			115200
 
-
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
 #define CONFIG_USE_ARCH_MEMSET
 #define CONFIG_USE_ARCH_MEMCPY
 #endif
@@ -99,8 +98,18 @@
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_SYS_MMC_ENV_PART		1
 
+#ifdef CONFIG_ARM64
+#define CONFIG_ARMV8_MULTIENTRY
+#define CPU_RELEASE_ADDR			0x80000100
+#define COUNTER_FREQUENCY			50000000
+#define CONFIG_GICV3
+#define GICD_BASE				0x5fe00000
+#define GICR_BASE				0x5fe80000
+#else
 /* Time clock 1MHz */
 #define CONFIG_SYS_TIMER_RATE			1000000
+#endif
+
 
 #define CONFIG_SYS_MAX_NAND_DEVICE			1
 #define CONFIG_SYS_NAND_MAX_CHIPS			2
@@ -176,21 +185,34 @@
 		"bootm $fit_addr_r\0" \
 	"__nfsboot=run tftpboot\0"
 #else
+#ifdef CONFIG_ARM64
+#define CONFIG_CMD_BOOTI
+#define CONFIG_BOOTFILE			"Image"
+#define LINUXBOOT_CMD			"booti"
+#define KERNEL_ADDR_R			"kernel_addr_r=0x80080000\0"
+#define KERNEL_SIZE			"kernel_size=0x00c00000\0"
+#define RAMDISK_ADDR			"ramdisk_addr=0x00e00000\0"
+#else
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTFILE			"zImage"
+#define LINUXBOOT_CMD			"bootz"
+#define KERNEL_ADDR_R			"kernel_addr_r=0x80208000\0"
+#define KERNEL_SIZE			"kernel_size=0x00800000\0"
+#define RAMDISK_ADDR			"ramdisk_addr=0x00a00000\0"
+#endif
 #define LINUXBOOT_ENV_SETTINGS \
 	"fdt_addr=0x00100000\0" \
 	"fdt_addr_r=0x84100000\0" \
 	"fdt_size=0x00008000\0" \
 	"kernel_addr=0x00200000\0" \
-	"kernel_addr_r=0x80208000\0" \
-	"kernel_size=0x00800000\0" \
-	"ramdisk_addr=0x00a00000\0" \
+	KERNEL_ADDR_R \
+	KERNEL_SIZE \
+	RAMDISK_ADDR \
 	"ramdisk_addr_r=0x84a00000\0" \
 	"ramdisk_size=0x00600000\0" \
 	"ramdisk_file=rootfs.cpio.uboot\0" \
 	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
-		"bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+		LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
 	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
 		"cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
 		"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
@@ -238,14 +260,21 @@
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_NR_DRAM_BANKS		2
 
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \
+#if defined(CONFIG_ARM64)
+#define CONFIG_SPL_TEXT_BASE		0x30000000
+#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
+	defined(CONFIG_ARCH_UNIPHIER_LD4) || \
 	defined(CONFIG_ARCH_UNIPHIER_SLD8)
 #define CONFIG_SPL_TEXT_BASE		0x00040000
 #else
 #define CONFIG_SPL_TEXT_BASE		0x00100000
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#define CONFIG_SPL_STACK		(0x3001c000)
+#else
 #define CONFIG_SPL_STACK		(0x00100000)
+#endif
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)
 
 #define CONFIG_PANIC_HANG
@@ -253,8 +282,10 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NOR_SUPPORT
+#ifndef CONFIG_ARM64
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
+#endif
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -270,5 +301,7 @@
 #define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
 #define CONFIG_SPL_MAX_FOOTPRINT		0x10000
 #define CONFIG_SPL_MAX_SIZE			0x10000
+#define CONFIG_SPL_BSS_START_ADDR		0x30016000
+#define CONFIG_SPL_BSS_MAX_SIZE			0x2000
 
 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */
-- 
cgit v0.10.2


From 2386969808c1694bb633804aff010294cb7e8573 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:19 +0900
Subject: ARM: uniphier: reserve the last 64 byte of SDRAM

The last 64 byte of each DDR channel of PH1-LD20 is periodically
used as a scratch area for the DDR PHY training.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index fb405a9..a25ac8d 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -259,6 +259,8 @@
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_NR_DRAM_BANKS		2
+/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
+#define CONFIG_SYS_MEM_TOP_HIDE		64
 
 #if defined(CONFIG_ARM64)
 #define CONFIG_SPL_TEXT_BASE		0x30000000
-- 
cgit v0.10.2


From 3d970876db14ca81b8fc66803f4473e719ad1350 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:20 +0900
Subject: ARM: dts: uniphier: add SD controller node for PH1-LD20

PH1-LD20 does not support 1.8V signaling for SD card; only Default
Speed and High Speed (up to 50MHz) with 3.3V signaling is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index fc1c6bf..f9cc3c4 100644
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -226,6 +226,23 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		mio: mioctrl@59810000 {
+			compatible = "socionext,ph1-ld20-mioctrl";
+			reg = <0x59810000 0x800>;
+			#clock-cells = <1>;
+		};
+
+		sd: sdhc@5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x800>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_sd>;
+			clocks = <&mio 0>;
+			bus-width = <4>;
+		};
+
 		pinctrl: pinctrl@5f801000 {
 			compatible = "socionext,ph1-ld20-pinctrl", "syscon";
 			reg = <0x5f801000 0xe00>;
-- 
cgit v0.10.2


From 306d37e949ed63b6d937589793f0ed0659f58adf Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:21 +0900
Subject: clk: uniphier: add Media I/O clock driver support for PH1-LD20

PH1-LD20 needs this for its SD card controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index d91ae34..a2b0e80 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -164,6 +164,10 @@ static const struct udevice_id uniphier_mio_clk_match[] = {
 		.compatible = "socionext,proxstream2-mioctrl",
 		.data = (ulong)&uniphier_mio_clk_data,
 	},
+	{
+		.compatible = "socionext,ph1-ld20-mioctrl",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
 	{ /* sentinel */ }
 };
 
-- 
cgit v0.10.2


From b75e072c1c53cade2c3944433d852d7d6046661b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Apr 2016 14:43:22 +0900
Subject: ARM: uniphier: speed up loading kernel image from NOR device

Copy the kernel image double-word-wise rather than byte-wise.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index a25ac8d..8ecfc6f 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -214,7 +214,8 @@
 	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
 		LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
 	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
-		"cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
+		"setexpr kernel_size $kernel_size / 4 &&" \
+		"cp $kernel_addr $kernel_addr_r $kernel_size &&" \
 		"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
 		"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
 		"run boot_common\0" \
-- 
cgit v0.10.2


From 28027521be95d27fcb83669e09ce3563bb4dd977 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 07:11:34 +0200
Subject: dm: core: Add dev_get_addr_ptr() to return a pointer to the reg
 address

On some platforms (e.g. x86), the return value of dev_get_addr() can't
be assigned to a pointer type variable directly. As there might be a
difference between the size of fdt_addr_t and the pointer type. On
x86 for example, "fdt_addr_t" is 64bit but "void *" only 32bit. So
assigning the register base directly in dev_get_addr() results in this
compilation warning:
  warning: cast to pointer from integer of different size

This patch introduces the new function dev_get_addr_ptr() that
returns a pointer to the 'reg' address that can be used by drivers
in this case.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 269087a..1322991 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -673,6 +673,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
 	return dev_get_addr_index(dev, 0);
 }
 
+void *dev_get_addr_ptr(struct udevice *dev)
+{
+	return (void *)(uintptr_t)dev_get_addr_index(dev, 0);
+}
+
 bool device_has_children(struct udevice *dev)
 {
 	return !list_empty(&dev->child_head);
diff --git a/include/dm/device.h b/include/dm/device.h
index dad7591..8970fc0 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -454,6 +454,16 @@ int device_find_next_child(struct udevice **devp);
 fdt_addr_t dev_get_addr(struct udevice *dev);
 
 /**
+ * dev_get_addr_ptr() - Return pointer to the address of the reg property
+ *                      of a device
+ *
+ * @dev: Pointer to a device
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *dev_get_addr_ptr(struct udevice *dev);
+
+/**
  * dev_get_addr_index() - Get the indexed reg property of a device
  *
  * @dev: Pointer to a device
-- 
cgit v0.10.2


From e209828cbd4b8d896380c710bac82c5f7bd1ad72 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 08:19:37 +0200
Subject: i2c: designware_i2c: Add ic_enable_status to ic_regs struct

Add the ic_enable_status register to the i2c_regs struct. Additionally
the register offsets are added, to better check, if the offset matches
the register description in the datasheet.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 19b09df..270c29c 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -9,39 +9,41 @@
 #define __DW_I2C_H_
 
 struct i2c_regs {
-	u32 ic_con;
-	u32 ic_tar;
-	u32 ic_sar;
-	u32 ic_hs_maddr;
-	u32 ic_cmd_data;
-	u32 ic_ss_scl_hcnt;
-	u32 ic_ss_scl_lcnt;
-	u32 ic_fs_scl_hcnt;
-	u32 ic_fs_scl_lcnt;
-	u32 ic_hs_scl_hcnt;
-	u32 ic_hs_scl_lcnt;
-	u32 ic_intr_stat;
-	u32 ic_intr_mask;
-	u32 ic_raw_intr_stat;
-	u32 ic_rx_tl;
-	u32 ic_tx_tl;
-	u32 ic_clr_intr;
-	u32 ic_clr_rx_under;
-	u32 ic_clr_rx_over;
-	u32 ic_clr_tx_over;
-	u32 ic_clr_rd_req;
-	u32 ic_clr_tx_abrt;
-	u32 ic_clr_rx_done;
-	u32 ic_clr_activity;
-	u32 ic_clr_stop_det;
-	u32 ic_clr_start_det;
-	u32 ic_clr_gen_call;
-	u32 ic_enable;
-	u32 ic_status;
-	u32 ic_txflr;
-	u32 ix_rxflr;
-	u32 reserved_1;
-	u32 ic_tx_abrt_source;
+	u32 ic_con;		/* 0x00 */
+	u32 ic_tar;		/* 0x04 */
+	u32 ic_sar;		/* 0x08 */
+	u32 ic_hs_maddr;	/* 0x0c */
+	u32 ic_cmd_data;	/* 0x10 */
+	u32 ic_ss_scl_hcnt;	/* 0x14 */
+	u32 ic_ss_scl_lcnt;	/* 0x18 */
+	u32 ic_fs_scl_hcnt;	/* 0x1c */
+	u32 ic_fs_scl_lcnt;	/* 0x20 */
+	u32 ic_hs_scl_hcnt;	/* 0x24 */
+	u32 ic_hs_scl_lcnt;	/* 0x28 */
+	u32 ic_intr_stat;	/* 0x2c */
+	u32 ic_intr_mask;	/* 0x30 */
+	u32 ic_raw_intr_stat;	/* 0x34 */
+	u32 ic_rx_tl;		/* 0x38 */
+	u32 ic_tx_tl;		/* 0x3c */
+	u32 ic_clr_intr;	/* 0x40 */
+	u32 ic_clr_rx_under;	/* 0x44 */
+	u32 ic_clr_rx_over;	/* 0x48 */
+	u32 ic_clr_tx_over;	/* 0x4c */
+	u32 ic_clr_rd_req;	/* 0x50 */
+	u32 ic_clr_tx_abrt;	/* 0x54 */
+	u32 ic_clr_rx_done;	/* 0x58 */
+	u32 ic_clr_activity;	/* 0x5c */
+	u32 ic_clr_stop_det;	/* 0x60 */
+	u32 ic_clr_start_det;	/* 0x64 */
+	u32 ic_clr_gen_call;	/* 0x68 */
+	u32 ic_enable;		/* 0x6c */
+	u32 ic_status;		/* 0x70 */
+	u32 ic_txflr;		/* 0x74 */
+	u32 ic_rxflr;		/* 0x78 */
+	u32 ic_sda_hold;	/* 0x7c */
+	u32 ic_tx_abrt_source;	/* 0x80 */
+	u8 res1[0x18];		/* 0x84 */
+	u32 ic_enable_status;	/* 0x9c */
 };
 
 #if !defined(IC_CLK)
-- 
cgit v0.10.2


From 1c8b089b45cddeef6fb76d9abb8d48601ec5e0a1 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 08:19:38 +0200
Subject: i2c: designware_i2c: Add dw_i2c_enable() helper function

dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes
sense to add such a function, as the controller is dis-/en-abled
multiple times in the code. Additionally, this function now checks,
if the controller is really dis-/en-abled. This code is copied
from the Linux I2C driver version.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index e768cde..d5b3e29 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -34,6 +34,27 @@ static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 	return NULL;
 }
 
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+{
+	u32 ena = enable ? IC_ENABLE_0B : 0;
+	int timeout = 100;
+
+	do {
+		writel(ena, &i2c_base->ic_enable);
+		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
+			return;
+
+		/*
+		 * Wait 10 times the signaling period of the highest I2C
+		 * transfer supported by the driver (for 400KHz this is
+		 * 25us) as described in the DesignWare I2C databook.
+		 */
+		udelay(25);
+	} while (timeout--);
+
+	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
+}
+
 /*
  * set_speed - Set the i2c speed mode (standard, high, fast)
  * @i2c_spd:	required i2c speed mode
@@ -45,12 +66,9 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd)
 	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned int cntl;
 	unsigned int hcnt, lcnt;
-	unsigned int enbl;
 
 	/* to set speed cltr must be disabled */
-	enbl = readl(&i2c_base->ic_enable);
-	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_base->ic_enable);
+	dw_i2c_enable(i2c_base, false);
 
 	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 
@@ -84,8 +102,7 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd)
 	writel(cntl, &i2c_base->ic_con);
 
 	/* Enable back i2c now speed set */
-	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_base->ic_enable);
+	dw_i2c_enable(i2c_base, true);
 }
 
 /*
@@ -123,12 +140,9 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed,
 			int slaveaddr)
 {
 	struct i2c_regs *i2c_base = i2c_get_base(adap);
-	unsigned int enbl;
 
 	/* Disable i2c */
-	enbl = readl(&i2c_base->ic_enable);
-	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_base->ic_enable);
+	dw_i2c_enable(i2c_base, false);
 
 	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
 	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
@@ -138,9 +152,7 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed,
 	writel(slaveaddr, &i2c_base->ic_sar);
 
 	/* Enable i2c */
-	enbl = readl(&i2c_base->ic_enable);
-	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_base->ic_enable);
+	dw_i2c_enable(i2c_base, true);
 }
 
 /*
@@ -152,19 +164,14 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed,
 static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
 {
 	struct i2c_regs *i2c_base = i2c_get_base(adap);
-	unsigned int enbl;
 
 	/* Disable i2c */
-	enbl = readl(&i2c_base->ic_enable);
-	enbl &= ~IC_ENABLE_0B;
-	writel(enbl, &i2c_base->ic_enable);
+	dw_i2c_enable(i2c_base, false);
 
 	writel(i2c_addr, &i2c_base->ic_tar);
 
 	/* Enable i2c */
-	enbl = readl(&i2c_base->ic_enable);
-	enbl |= IC_ENABLE_0B;
-	writel(enbl, &i2c_base->ic_enable);
+	dw_i2c_enable(i2c_base, true);
 }
 
 /*
-- 
cgit v0.10.2


From 11b544ab419971bb829135743dab3397fb43db21 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 08:19:39 +0200
Subject: i2c: designware_i2c: Integrate set_speed() into
 dw_i2c_set_bus_speed()

Integrating set_speed() into dw_i2c_set_bus_speed() will make the
conversion to DM easier for this driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index d5b3e29..035bf23 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -56,16 +56,25 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 }
 
 /*
- * set_speed - Set the i2c speed mode (standard, high, fast)
- * @i2c_spd:	required i2c speed mode
+ * i2c_set_bus_speed - Set the i2c speed
+ * @speed:	required i2c speed
  *
- * Set the i2c speed mode (standard, high, fast)
+ * Set the i2c speed.
  */
-static void set_speed(struct i2c_adapter *adap, int i2c_spd)
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+					 unsigned int speed)
 {
 	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned int cntl;
 	unsigned int hcnt, lcnt;
+	int i2c_spd;
+
+	if (speed >= I2C_MAX_SPEED)
+		i2c_spd = IC_SPEED_MODE_MAX;
+	else if (speed >= I2C_FAST_SPEED)
+		i2c_spd = IC_SPEED_MODE_FAST;
+	else
+		i2c_spd = IC_SPEED_MODE_STANDARD;
 
 	/* to set speed cltr must be disabled */
 	dw_i2c_enable(i2c_base, false);
@@ -103,27 +112,7 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd)
 
 	/* Enable back i2c now speed set */
 	dw_i2c_enable(i2c_base, true);
-}
-
-/*
- * i2c_set_bus_speed - Set the i2c speed
- * @speed:	required i2c speed
- *
- * Set the i2c speed.
- */
-static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
-					 unsigned int speed)
-{
-	int i2c_spd;
-
-	if (speed >= I2C_MAX_SPEED)
-		i2c_spd = IC_SPEED_MODE_MAX;
-	else if (speed >= I2C_FAST_SPEED)
-		i2c_spd = IC_SPEED_MODE_FAST;
-	else
-		i2c_spd = IC_SPEED_MODE_STANDARD;
 
-	set_speed(adap, i2c_spd);
 	adap->speed = speed;
 
 	return 0;
-- 
cgit v0.10.2


From 3f4358da8d42e407a3fb583b7b3ea7033090e0cd Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 08:19:40 +0200
Subject: i2c: designware_i2c: Prepare for DM driver conversion

This patch prepares the designware I2C driver for the DM conversion.
This is mainly done by removing struct i2c_adapter from the functions
that shall be used by the DM driver version as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 035bf23..2adc36e 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -10,30 +10,6 @@
 #include <asm/io.h>
 #include "designware_i2c.h"
 
-static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
-{
-	switch (adap->hwadapnr) {
-#if CONFIG_SYS_I2C_BUS_MAX >= 4
-	case 3:
-		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
-#endif
-#if CONFIG_SYS_I2C_BUS_MAX >= 3
-	case 2:
-		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
-#endif
-#if CONFIG_SYS_I2C_BUS_MAX >= 2
-	case 1:
-		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
-#endif
-	case 0:
-		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
-	default:
-		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
-	}
-
-	return NULL;
-}
-
 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
 	u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -61,10 +37,9 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  *
  * Set the i2c speed.
  */
-static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
-					 unsigned int speed)
+static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
+					   unsigned int speed)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned int cntl;
 	unsigned int hcnt, lcnt;
 	int i2c_spd;
@@ -113,47 +88,17 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 	/* Enable back i2c now speed set */
 	dw_i2c_enable(i2c_base, true);
 
-	adap->speed = speed;
-
 	return 0;
 }
 
 /*
- * i2c_init - Init function
- * @speed:	required i2c speed
- * @slaveaddr:	slave address for the device
- *
- * Initialization function.
- */
-static void dw_i2c_init(struct i2c_adapter *adap, int speed,
-			int slaveaddr)
-{
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
-
-	/* Disable i2c */
-	dw_i2c_enable(i2c_base, false);
-
-	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
-	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
-	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
-	dw_i2c_set_bus_speed(adap, speed);
-	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
-	writel(slaveaddr, &i2c_base->ic_sar);
-
-	/* Enable i2c */
-	dw_i2c_enable(i2c_base, true);
-}
-
-/*
  * i2c_setaddress - Sets the target slave address
  * @i2c_addr:	target i2c address
  *
  * Sets the target slave address.
  */
-static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
+static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
-
 	/* Disable i2c */
 	dw_i2c_enable(i2c_base, false);
 
@@ -168,10 +113,8 @@ static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
  *
  * Flushes the i2c RX FIFO
  */
-static void i2c_flush_rxfifo(struct i2c_adapter *adap)
+static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
-
 	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 		readl(&i2c_base->ic_cmd_data);
 }
@@ -181,9 +124,8 @@ static void i2c_flush_rxfifo(struct i2c_adapter *adap)
  *
  * Waits for bus busy
  */
-static int i2c_wait_for_bb(struct i2c_adapter *adap)
+static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned long start_time_bb = get_timer(0);
 
 	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
@@ -197,15 +139,13 @@ static int i2c_wait_for_bb(struct i2c_adapter *adap)
 	return 0;
 }
 
-static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
+static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 			 int alen)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
-
-	if (i2c_wait_for_bb(adap))
+	if (i2c_wait_for_bb(i2c_base))
 		return 1;
 
-	i2c_setaddress(adap, chip);
+	i2c_setaddress(i2c_base, chip);
 	while (alen) {
 		alen--;
 		/* high byte address going out first */
@@ -215,9 +155,8 @@ static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
 	return 0;
 }
 
-static int i2c_xfer_finish(struct i2c_adapter *adap)
+static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	ulong start_stop_det = get_timer(0);
 
 	while (1) {
@@ -229,12 +168,12 @@ static int i2c_xfer_finish(struct i2c_adapter *adap)
 		}
 	}
 
-	if (i2c_wait_for_bb(adap)) {
+	if (i2c_wait_for_bb(i2c_base)) {
 		printf("Timed out waiting for bus\n");
 		return 1;
 	}
 
-	i2c_flush_rxfifo(adap);
+	i2c_flush_rxfifo(i2c_base);
 
 	return 0;
 }
@@ -249,10 +188,9 @@ static int i2c_xfer_finish(struct i2c_adapter *adap)
  *
  * Read from i2c memory.
  */
-static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
-		       int alen, u8 *buffer, int len)
+static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
+			 int alen, u8 *buffer, int len)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	unsigned long start_time_rx;
 
 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
@@ -274,7 +212,7 @@ static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 	      addr);
 #endif
 
-	if (i2c_xfer_init(adap, dev, addr, alen))
+	if (i2c_xfer_init(i2c_base, dev, addr, alen))
 		return 1;
 
 	start_time_rx = get_timer(0);
@@ -294,7 +232,7 @@ static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 		}
 	}
 
-	return i2c_xfer_finish(adap);
+	return i2c_xfer_finish(i2c_base);
 }
 
 /*
@@ -307,10 +245,9 @@ static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
  *
  * Write to i2c memory.
  */
-static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
-			int alen, u8 *buffer, int len)
+static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
+			  int alen, u8 *buffer, int len)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	int nb = len;
 	unsigned long start_time_tx;
 
@@ -333,7 +270,7 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 	      addr);
 #endif
 
-	if (i2c_xfer_init(adap, dev, addr, alen))
+	if (i2c_xfer_init(i2c_base, dev, addr, alen))
 		return 1;
 
 	start_time_tx = get_timer(0);
@@ -354,7 +291,76 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 		}
 	}
 
-	return i2c_xfer_finish(adap);
+	return i2c_xfer_finish(i2c_base);
+}
+
+static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
+{
+	switch (adap->hwadapnr) {
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+	case 3:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+	case 2:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+	case 1:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
+#endif
+	case 0:
+		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+	default:
+		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
+	}
+
+	return NULL;
+}
+
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+					 unsigned int speed)
+{
+	adap->speed = speed;
+	return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed);
+}
+
+/*
+ * i2c_init - Init function
+ * @speed:	required i2c speed
+ * @slaveaddr:	slave address for the device
+ *
+ * Initialization function.
+ */
+static void dw_i2c_init(struct i2c_adapter *adap, int speed,
+			int slaveaddr)
+{
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
+
+	/* Disable i2c */
+	dw_i2c_enable(i2c_base, false);
+
+	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
+	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
+	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
+	dw_i2c_set_bus_speed(adap, speed);
+	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
+	writel(slaveaddr, &i2c_base->ic_sar);
+
+	/* Enable i2c */
+	dw_i2c_enable(i2c_base, true);
+}
+
+static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+		       int alen, u8 *buffer, int len)
+{
+	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
+}
+
+static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+			int alen, u8 *buffer, int len)
+{
+	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 }
 
 /*
@@ -362,13 +368,14 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
  */
 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 {
+	struct i2c_regs *i2c_base = i2c_get_base(adap);
 	u32 tmp;
 	int ret;
 
 	/*
 	 * Try to read the first location of the chip.
 	 */
-	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
+	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 	if (ret)
 		dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 
-- 
cgit v0.10.2


From 334b9b004c61f9a3f195968e6107f5362a29ce47 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 08:19:41 +0200
Subject: i2c: designware_i2c: Add DM support

This patch adds DM support to the designware I2C driver. It currently
supports DM and the legacy I2C support. The legacy support should be
removed, once all platforms using it have DM enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 2adc36e..d653eff 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -6,10 +6,15 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include "designware_i2c.h"
 
+struct dw_i2c {
+	struct i2c_regs *regs;
+};
+
 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
 	u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -294,6 +299,36 @@ static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 	return i2c_xfer_finish(i2c_base);
 }
 
+/*
+ * __dw_i2c_init - Init function
+ * @speed:	required i2c speed
+ * @slaveaddr:	slave address for the device
+ *
+ * Initialization function.
+ */
+static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
+{
+	/* Disable i2c */
+	dw_i2c_enable(i2c_base, false);
+
+	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
+	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
+	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
+	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
+#ifndef CONFIG_DM_I2C
+	__dw_i2c_set_bus_speed(i2c_base, speed);
+	writel(slaveaddr, &i2c_base->ic_sar);
+#endif
+
+	/* Enable i2c */
+	dw_i2c_enable(i2c_base, true);
+}
+
+#ifndef CONFIG_DM_I2C
+/*
+ * The legacy I2C functions. These need to get removed once
+ * all users of this driver are converted to DM.
+ */
 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 {
 	switch (adap->hwadapnr) {
@@ -325,30 +360,9 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 	return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed);
 }
 
-/*
- * i2c_init - Init function
- * @speed:	required i2c speed
- * @slaveaddr:	slave address for the device
- *
- * Initialization function.
- */
-static void dw_i2c_init(struct i2c_adapter *adap, int speed,
-			int slaveaddr)
+static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 {
-	struct i2c_regs *i2c_base = i2c_get_base(adap);
-
-	/* Disable i2c */
-	dw_i2c_enable(i2c_base, false);
-
-	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
-	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
-	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
-	dw_i2c_set_bus_speed(adap, speed);
-	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
-	writel(slaveaddr, &i2c_base->ic_sar);
-
-	/* Enable i2c */
-	dw_i2c_enable(i2c_base, true);
+	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 }
 
 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
@@ -363,9 +377,7 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 }
 
-/*
- * i2c_probe - Probe the i2c chip
- */
+/* dw_i2c_probe - Probe the i2c chip */
 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 {
 	struct i2c_regs *i2c_base = i2c_get_base(adap);
@@ -403,3 +415,88 @@ U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 			 dw_i2c_write, dw_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 #endif
+
+#else /* CONFIG_DM_I2C */
+/* The DM I2C functions */
+
+static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+			       int nmsgs)
+{
+	struct dw_i2c *i2c = dev_get_priv(bus);
+	int ret;
+
+	debug("i2c_xfer: %d messages\n", nmsgs);
+	for (; nmsgs > 0; nmsgs--, msg++) {
+		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+		if (msg->flags & I2C_M_RD) {
+			ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
+					    msg->buf, msg->len);
+		} else {
+			ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
+					     msg->buf, msg->len);
+		}
+		if (ret) {
+			debug("i2c_write: error sending\n");
+			return -EREMOTEIO;
+		}
+	}
+
+	return 0;
+}
+
+static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	struct dw_i2c *i2c = dev_get_priv(bus);
+
+	return __dw_i2c_set_bus_speed(i2c->regs, speed);
+}
+
+static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+				     uint chip_flags)
+{
+	struct dw_i2c *i2c = dev_get_priv(bus);
+	struct i2c_regs *i2c_base = i2c->regs;
+	u32 tmp;
+	int ret;
+
+	/* Try to read the first location of the chip */
+	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
+	if (ret)
+		__dw_i2c_init(i2c_base, 0, 0);
+
+	return ret;
+}
+
+static int designware_i2c_probe(struct udevice *bus)
+{
+	struct dw_i2c *priv = dev_get_priv(bus);
+
+	/* Save base address from device-tree */
+	priv->regs = (struct i2c_regs *)dev_get_addr(bus);
+
+	__dw_i2c_init(priv->regs, 0, 0);
+
+	return 0;
+}
+
+static const struct dm_i2c_ops designware_i2c_ops = {
+	.xfer		= designware_i2c_xfer,
+	.probe_chip	= designware_i2c_probe_chip,
+	.set_bus_speed	= designware_i2c_set_bus_speed,
+};
+
+static const struct udevice_id designware_i2c_ids[] = {
+	{ .compatible = "snps,designware-i2c" },
+	{ }
+};
+
+U_BOOT_DRIVER(i2c_designware) = {
+	.name	= "i2c_designware",
+	.id	= UCLASS_I2C,
+	.of_match = designware_i2c_ids,
+	.probe	= designware_i2c_probe,
+	.priv_auto_alloc_size = sizeof(struct dw_i2c),
+	.ops	= &designware_i2c_ops,
+};
+
+#endif /* CONFIG_DM_I2C */
-- 
cgit v0.10.2


From ba5da550ae1d955e53691e51cd74a27331ca3b3c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 21 Apr 2016 08:19:42 +0200
Subject: i2c: designware_i2c: Add support for PCI(e) based I2C cores (x86)

This patch adds support for the PCI(e) based I2C cores. Which can be
found for example on the Intel Bay Trail SoC. It has 7 I2C controllers
implemented as PCI devices.

This patch also adds the fixed values for the timing registers for
BayTrail which are taken from the Linux designware I2C driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index d653eff..0c7cd0b 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -8,11 +8,32 @@
 #include <common.h>
 #include <dm.h>
 #include <i2c.h>
+#include <pci.h>
 #include <asm/io.h>
 #include "designware_i2c.h"
 
+struct dw_scl_sda_cfg {
+	u32 ss_hcnt;
+	u32 fs_hcnt;
+	u32 ss_lcnt;
+	u32 fs_lcnt;
+	u32 sda_hold;
+};
+
+#ifdef CONFIG_X86
+/* BayTrail HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg byt_config = {
+	.ss_hcnt = 0x200,
+	.fs_hcnt = 0x55,
+	.ss_lcnt = 0x200,
+	.fs_lcnt = 0x99,
+	.sda_hold = 0x6,
+};
+#endif
+
 struct dw_i2c {
 	struct i2c_regs *regs;
+	struct dw_scl_sda_cfg *scl_sda_cfg;
 };
 
 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
@@ -43,6 +64,7 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  * Set the i2c speed.
  */
 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
+					   struct dw_scl_sda_cfg *scl_sda_cfg,
 					   unsigned int speed)
 {
 	unsigned int cntl;
@@ -62,34 +84,55 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
 	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 
 	switch (i2c_spd) {
+#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
 	case IC_SPEED_MODE_MAX:
-		cntl |= IC_CON_SPD_HS;
-		hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+		cntl |= IC_CON_SPD_SS;
+		if (scl_sda_cfg) {
+			hcnt = scl_sda_cfg->fs_hcnt;
+			lcnt = scl_sda_cfg->fs_lcnt;
+		} else {
+			hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+			lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
+		}
 		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
-		lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
 		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
 		break;
+#endif
 
 	case IC_SPEED_MODE_STANDARD:
 		cntl |= IC_CON_SPD_SS;
-		hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+		if (scl_sda_cfg) {
+			hcnt = scl_sda_cfg->ss_hcnt;
+			lcnt = scl_sda_cfg->ss_lcnt;
+		} else {
+			hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+			lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
+		}
 		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
-		lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
 		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 		break;
 
 	case IC_SPEED_MODE_FAST:
 	default:
 		cntl |= IC_CON_SPD_FS;
-		hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+		if (scl_sda_cfg) {
+			hcnt = scl_sda_cfg->fs_hcnt;
+			lcnt = scl_sda_cfg->fs_lcnt;
+		} else {
+			hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+			lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+		}
 		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
-		lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
 		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 		break;
 	}
 
 	writel(cntl, &i2c_base->ic_con);
 
+	/* Configure SDA Hold Time if required */
+	if (scl_sda_cfg)
+		writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
+
 	/* Enable back i2c now speed set */
 	dw_i2c_enable(i2c_base, true);
 
@@ -316,7 +359,7 @@ static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 #ifndef CONFIG_DM_I2C
-	__dw_i2c_set_bus_speed(i2c_base, speed);
+	__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
 	writel(slaveaddr, &i2c_base->ic_sar);
 #endif
 
@@ -357,7 +400,7 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 					 unsigned int speed)
 {
 	adap->speed = speed;
-	return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed);
+	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
 }
 
 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
@@ -448,7 +491,7 @@ static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 {
 	struct dw_i2c *i2c = dev_get_priv(bus);
 
-	return __dw_i2c_set_bus_speed(i2c->regs, speed);
+	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
 }
 
 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
@@ -471,14 +514,48 @@ static int designware_i2c_probe(struct udevice *bus)
 {
 	struct dw_i2c *priv = dev_get_priv(bus);
 
-	/* Save base address from device-tree */
-	priv->regs = (struct i2c_regs *)dev_get_addr(bus);
+	if (device_is_on_pci_bus(bus)) {
+#ifdef CONFIG_DM_PCI
+		/* Save base address from PCI BAR */
+		priv->regs = (struct i2c_regs *)
+			dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+#ifdef CONFIG_X86
+		/* Use BayTrail specific timing values */
+		priv->scl_sda_cfg = &byt_config;
+#endif
+#endif
+	} else {
+		priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
+	}
 
 	__dw_i2c_init(priv->regs, 0, 0);
 
 	return 0;
 }
 
+static int designware_i2c_bind(struct udevice *dev)
+{
+	static int num_cards;
+	char name[20];
+
+	/* Create a unique device name for PCI type devices */
+	if (device_is_on_pci_bus(dev)) {
+		/*
+		 * ToDo:
+		 * Setting req_seq in the driver is probably not recommended.
+		 * But without a DT alias the number is not configured. And
+		 * using this driver is impossible for PCIe I2C devices.
+		 * This can be removed, once a better (correct) way for this
+		 * is found and implemented.
+		 */
+		dev->req_seq = num_cards;
+		sprintf(name, "i2c_designware#%u", num_cards++);
+		device_set_name(dev, name);
+	}
+
+	return 0;
+}
+
 static const struct dm_i2c_ops designware_i2c_ops = {
 	.xfer		= designware_i2c_xfer,
 	.probe_chip	= designware_i2c_probe_chip,
@@ -494,9 +571,26 @@ U_BOOT_DRIVER(i2c_designware) = {
 	.name	= "i2c_designware",
 	.id	= UCLASS_I2C,
 	.of_match = designware_i2c_ids,
+	.bind	= designware_i2c_bind,
 	.probe	= designware_i2c_probe,
 	.priv_auto_alloc_size = sizeof(struct dw_i2c),
 	.ops	= &designware_i2c_ops,
 };
 
+#ifdef CONFIG_X86
+static struct pci_device_id designware_pci_supported[] = {
+	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
+	{ PCI_VDEVICE(INTEL, 0x0f41) },
+	{ PCI_VDEVICE(INTEL, 0x0f42) },
+	{ PCI_VDEVICE(INTEL, 0x0f43) },
+	{ PCI_VDEVICE(INTEL, 0x0f44) },
+	{ PCI_VDEVICE(INTEL, 0x0f45) },
+	{ PCI_VDEVICE(INTEL, 0x0f46) },
+	{ PCI_VDEVICE(INTEL, 0x0f47) },
+	{},
+};
+
+U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
+#endif
+
 #endif /* CONFIG_DM_I2C */
-- 
cgit v0.10.2


From c6eb899c4d0f8311f8a9d6c991344a27b8f9d4db Mon Sep 17 00:00:00 2001
From: Lukasz Majewski <l.majewski@samsung.com>
Date: Wed, 20 Apr 2016 10:36:32 +0200
Subject: tests: py: dfu: Add variables to store dfu alt numbers for test and
 dummy files

This patch replaces hardcoded (i.e. 0 and 1) values passed to dfu_{read|write}
with variables.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
Changes for v3:
- Replace per module global variables with ones defined inside a function
Changes for v2:
- None

diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 093e8d0..2e6cd7b 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -99,6 +99,10 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
         Nothing.
     """
 
+    # Default alt settings for test and dummy files
+    alt_setting_test_file = 0
+    alt_setting_dummy_file = 1
+
     def start_dfu():
         """Start U-Boot's dfu shell command.
 
@@ -229,15 +233,15 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
 
         u_boot_console.log.action('Writing test data to DFU primary ' +
             'altsetting')
-        dfu_write(0, test_f.abs_fn)
+        dfu_write(alt_setting_test_file, test_f.abs_fn)
 
         u_boot_console.log.action('Writing dummy data to DFU secondary ' +
             'altsetting to clear DFU buffers')
-        dfu_write(1, dummy_f.abs_fn)
+        dfu_write(alt_setting_dummy_file, dummy_f.abs_fn)
 
         u_boot_console.log.action('Reading DFU primary altsetting for ' +
             'comparison')
-        dfu_read(0, readback_fn)
+        dfu_read(alt_setting_test_file, readback_fn)
 
         u_boot_console.log.action('Comparing written and read data')
         written_hash = test_f.content_hash
@@ -266,7 +270,7 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
 
         u_boot_console.log.action(
             'Overwriting DFU primary altsetting with dummy data')
-        dfu_write(0, dummy_f.abs_fn)
+        dfu_write(alt_setting_test_file, dummy_f.abs_fn)
 
         for size in sizes:
             with u_boot_console.log.section('Data size %d' % size):
-- 
cgit v0.10.2


From 8eb37524468efa6f90dd00862aeaabe934557a5a Mon Sep 17 00:00:00 2001
From: Lukasz Majewski <l.majewski@samsung.com>
Date: Mon, 18 Apr 2016 17:01:15 +0200
Subject: tests: py: dfu: Add functionality to set different u-boot's dfu env
 variable

By default (on almost all systems) the dfu env variable, which defines
available alt settings, is named as "dfu_alt_info".

However on some platforms (i.e. Odroid XU3), the 'dfu_alt_info' is concatenated
from other variables - namely 'dfu_alt_boot' and 'dfu_alt_system' at run time
(when one types 'dfu 0 mmc 0' for first time).

'dfu_alt_boot' describes alt settings which depend on boot medium - for example
boot loader's LBA sectors which are different on eMMC and SD card because of e.g.
MBR/GPT.

'dfu_alt_system' describes board agnostic alt settings - like rootfs, kernel.
On such system we can only append/modify this env variable.

Because of the above, we must have way to modify other than "dfu_ale_info"
variable to perform tests.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
Changes for v3:
- None

Changes for v2:
- Rewrite of "alt_info_env_name" variable description
- Use of get() method on python's dictionary to easily obtain default
  value

diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 2e6cd7b..0442af8 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -44,6 +44,14 @@ env__dfu_configs = (
         # configurations, but don't want to test every single transfer size
         # on each, to avoid bloating the overall time taken by testing.
         "test_sizes": (63, 64, 65),
+        # This value is optional.
+        # The name of the environment variable that the the dfu command reads
+        # alt info from. If unspecified, this defaults to dfu_alt_info, which is
+        # valid for most systems. Some systems use a different variable name.
+        # One example is the Odroid XU3,  which automatically generates
+        # $dfu_alt_info, each time the dfu command is run, by concatenating
+        # $dfu_alt_boot and $dfu_alt_system.
+        "alt_info_env_name": "dfu_alt_system",
     },
 )
 
@@ -124,7 +132,11 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
         u_boot_console.log.action(
             'Starting long-running U-Boot dfu shell command')
 
-        cmd = 'setenv dfu_alt_info "%s"' % env__dfu_config['alt_info']
+        dfu_alt_info_env = env__dfu_config.get('alt_info_env_name', \
+	                                               'dfu_alt_info')
+
+        cmd = 'setenv "%s" "%s"' % (dfu_alt_info_env,
+                                    env__dfu_config['alt_info'])
         u_boot_console.run_command(cmd)
 
         cmd = 'dfu 0 ' + env__dfu_config['cmd_params']
-- 
cgit v0.10.2


From f3a87f5b79a8f1957753131b09b539027913c731 Mon Sep 17 00:00:00 2001
From: Lukasz Majewski <l.majewski@samsung.com>
Date: Wed, 20 Apr 2016 10:57:08 +0200
Subject: tests: py: dfu: Provide functionality to set test and dummy files alt
 settings

After concatenation of "dfu_alt_info" variable from "dfu_alt_boot" and
"dfu_alt_system" it may happen that test and dummy files alt settings
are different than default 0 and 1.

This patch provides the ability to set different values for them.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
---
Changes for v3:
- replace variables declarations with ones read from configuration file
- remove not necessary str() conversion at DFU host command generation

Changes for v2:
- generate "alt_info" automatically
- use file names as alt settings instead of numerical values
- extend in-code documentation

diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 0442af8..8649d87 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -30,6 +30,13 @@ env__usb_dev_ports = (
     },
 )
 
+# Optional entries (required only when "alt_id_test_file" and
+# "alt_id_dummy_file" are specified).
+test_file_name = "/dfu_test.bin"
+dummy_file_name = "/dfu_dummy.bin"
+# Above files are used to generate proper "alt_info" entry
+"alt_info": "/%s ext4 0 2;/%s ext4 0 2" % (test_file_name, dummy_file_name),
+
 env__dfu_configs = (
     # eMMC, partition 1
     {
@@ -52,6 +59,16 @@ env__dfu_configs = (
         # $dfu_alt_info, each time the dfu command is run, by concatenating
         # $dfu_alt_boot and $dfu_alt_system.
         "alt_info_env_name": "dfu_alt_system",
+        # This value is optional.
+        # For boards which require the "test file" alt setting number other than
+        # default (0) it is possible to specify exact file name to be used as
+        # this parameter.
+        "alt_id_test_file": test_file_name,
+        # This value is optional.
+        # For boards which require the "dummy file" alt setting number other
+        # than default (1) it is possible to specify exact file name to be used
+        # as this parameter.
+        "alt_id_dummy_file": dummy_file_name,
     },
 )
 
@@ -107,10 +124,6 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
         Nothing.
     """
 
-    # Default alt settings for test and dummy files
-    alt_setting_test_file = 0
-    alt_setting_dummy_file = 1
-
     def start_dfu():
         """Start U-Boot's dfu shell command.
 
@@ -188,7 +201,7 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
             Nothing.
         """
 
-        cmd = ['dfu-util', '-a', str(alt_setting), up_dn_load_arg, fn]
+        cmd = ['dfu-util', '-a', alt_setting, up_dn_load_arg, fn]
         if 'host_usb_port_path' in env__usb_dev_port:
             cmd += ['-p', env__usb_dev_port['host_usb_port_path']]
         u_boot_utils.run_and_log(u_boot_console, cmd)
@@ -276,6 +289,9 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
     dummy_f = u_boot_utils.PersistentRandomFile(u_boot_console,
         'dfu_dummy.bin', 1024)
 
+    alt_setting_test_file = env__dfu_config.get('alt_id_test_file', '0')
+    alt_setting_dummy_file = env__dfu_config.get('alt_id_dummy_file', '1')
+
     ignore_cleanup_errors = True
     try:
         start_dfu()
-- 
cgit v0.10.2


From 718156ad0ab076f94fbfc5f2628e6b43d1f5a127 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Tue, 12 Apr 2016 15:51:48 +0300
Subject: fastboot: Fix wMaxPacketSize for High-Speed IN endpoint

wMaxPacketSize for IN endpoing in High-Speed must be 512 and not 64.
While fixing that we do some clean ups like

- use cpu_to_le16(decimal_length) instead of hexadecimal length.
- No need to initialize bInterval to 0. Static variables are 0 initialized.
- Move descriptor setting from fastboot_add to to fastboot_bind.
- check for dual speed configuration before setting the high speed descriptors.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <srae@broadcom.com>
Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm235xx board]

diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 2e87fee..e1038ea 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -64,8 +64,7 @@ static struct usb_endpoint_descriptor fs_ep_in = {
 	.bDescriptorType    = USB_DT_ENDPOINT,
 	.bEndpointAddress   = USB_DIR_IN,
 	.bmAttributes       = USB_ENDPOINT_XFER_BULK,
-	.wMaxPacketSize     = TX_ENDPOINT_MAXIMUM_PACKET_SIZE,
-	.bInterval          = 0x00,
+	.wMaxPacketSize     = cpu_to_le16(64),
 };
 
 static struct usb_endpoint_descriptor fs_ep_out = {
@@ -73,8 +72,15 @@ static struct usb_endpoint_descriptor fs_ep_out = {
 	.bDescriptorType	= USB_DT_ENDPOINT,
 	.bEndpointAddress	= USB_DIR_OUT,
 	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
-	.wMaxPacketSize		= RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1,
-	.bInterval		= 0x00,
+	.wMaxPacketSize		= cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor hs_ep_in = {
+	.bLength		= USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType	= USB_DT_ENDPOINT,
+	.bEndpointAddress	= USB_DIR_IN,
+	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize		= cpu_to_le16(512),
 };
 
 static struct usb_endpoint_descriptor hs_ep_out = {
@@ -82,8 +88,7 @@ static struct usb_endpoint_descriptor hs_ep_out = {
 	.bDescriptorType	= USB_DT_ENDPOINT,
 	.bEndpointAddress	= USB_DIR_OUT,
 	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
-	.wMaxPacketSize		= RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0,
-	.bInterval		= 0x00,
+	.wMaxPacketSize		= cpu_to_le16(512),
 };
 
 static struct usb_interface_descriptor interface_desc = {
@@ -97,9 +102,15 @@ static struct usb_interface_descriptor interface_desc = {
 	.bInterfaceProtocol	= FASTBOOT_INTERFACE_PROTOCOL,
 };
 
-static struct usb_descriptor_header *fb_runtime_descs[] = {
+static struct usb_descriptor_header *fb_fs_function[] = {
 	(struct usb_descriptor_header *)&interface_desc,
 	(struct usb_descriptor_header *)&fs_ep_in,
+	(struct usb_descriptor_header *)&fs_ep_out,
+};
+
+static struct usb_descriptor_header *fb_hs_function[] = {
+	(struct usb_descriptor_header *)&interface_desc,
+	(struct usb_descriptor_header *)&hs_ep_in,
 	(struct usb_descriptor_header *)&hs_ep_out,
 	NULL,
 };
@@ -177,7 +188,15 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f)
 		return -ENODEV;
 	f_fb->out_ep->driver_data = c->cdev;
 
-	hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+	f->descriptors = fb_fs_function;
+
+	if (gadget_is_dualspeed(gadget)) {
+		/* Assume endpoint addresses are the same for both speeds */
+		hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress;
+		hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+		/* copy HS descriptors */
+		f->hs_descriptors = fb_hs_function;
+	}
 
 	s = getenv("serial#");
 	if (s)
@@ -302,7 +321,6 @@ static int fastboot_add(struct usb_configuration *c)
 	}
 
 	f_fb->usb_function.name = "f_fastboot";
-	f_fb->usb_function.hs_descriptors = fb_runtime_descs;
 	f_fb->usb_function.bind = fastboot_bind;
 	f_fb->usb_function.unbind = fastboot_unbind;
 	f_fb->usb_function.set_alt = fastboot_set_alt;
-- 
cgit v0.10.2


From 8b704a0e3d71ca8d1610ae0a877aa42dfdd8de82 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Wed, 13 Apr 2016 11:30:00 +0300
Subject: fastboot: Enable the respective speed endpoints at runtime

In a dual speed configuration we need to check at runtime if
we want to enable the Full-Speed or High-Speed endpoint.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Steve Rae <srae@broadcom.com>
[Test HW: bcm235xx board]

diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index e1038ea..7961231 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -115,6 +115,15 @@ static struct usb_descriptor_header *fb_hs_function[] = {
 	NULL,
 };
 
+static struct usb_endpoint_descriptor *
+fb_ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *fs,
+	    struct usb_endpoint_descriptor *hs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
 /*
  * static strings, in UTF-8
  */
@@ -255,18 +264,18 @@ static int fastboot_set_alt(struct usb_function *f,
 	struct usb_composite_dev *cdev = f->config->cdev;
 	struct usb_gadget *gadget = cdev->gadget;
 	struct f_fastboot *f_fb = func_to_fastboot(f);
+	const struct usb_endpoint_descriptor *d;
 
 	debug("%s: func: %s intf: %d alt: %d\n",
 	      __func__, f->name, interface, alt);
 
-	/* make sure we don't enable the ep twice */
-	if (gadget->speed == USB_SPEED_HIGH) {
-		ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out);
+	if (gadget->speed == USB_SPEED_HIGH)
 		is_high_speed = true;
-	} else {
-		ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out);
+	else
 		is_high_speed = false;
-	}
+
+	d = fb_ep_desc(gadget, &fs_ep_out, &hs_ep_out);
+	ret = usb_ep_enable(f_fb->out_ep, d);
 	if (ret) {
 		puts("failed to enable out ep\n");
 		return ret;
@@ -280,7 +289,8 @@ static int fastboot_set_alt(struct usb_function *f,
 	}
 	f_fb->out_req->complete = rx_handler_command;
 
-	ret = usb_ep_enable(f_fb->in_ep, &fs_ep_in);
+	d = fb_ep_desc(gadget, &fs_ep_in, &hs_ep_in);
+	ret = usb_ep_enable(f_fb->in_ep, d);
 	if (ret) {
 		puts("failed to enable in ep\n");
 		goto err;
-- 
cgit v0.10.2


From ac484c5a6a5745503a5c1b83a3d4c1808b677ebf Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Tue, 19 Apr 2016 10:16:59 +0300
Subject: fastboot: Clean up bulk-out logic

Just use ep->maxpacket to get the maxpacket size
and simplify the bulk-out maxpacket alignment.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <srae@broadcom.com>

diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 7961231..28b244a 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -39,6 +39,11 @@
 #define TX_ENDPOINT_MAXIMUM_PACKET_SIZE      (0x0040)
 
 #define EP_BUFFER_SIZE			4096
+/*
+ * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size
+ * (64 or 512 or 1024), else we break on certain controllers like DWC3
+ * that expect bulk OUT requests to be divisible by maxpacket size.
+ */
 
 struct f_fastboot {
 	struct usb_function usb_function;
@@ -57,7 +62,6 @@ static struct f_fastboot *fastboot_func;
 static unsigned int fastboot_flash_session_id;
 static unsigned int download_size;
 static unsigned int download_bytes;
-static bool is_high_speed;
 
 static struct usb_endpoint_descriptor fs_ep_in = {
 	.bLength            = USB_DT_ENDPOINT_SIZE,
@@ -269,11 +273,6 @@ static int fastboot_set_alt(struct usb_function *f,
 	debug("%s: func: %s intf: %d alt: %d\n",
 	      __func__, f->name, interface, alt);
 
-	if (gadget->speed == USB_SPEED_HIGH)
-		is_high_speed = true;
-	else
-		is_high_speed = false;
-
 	d = fb_ep_desc(gadget, &fs_ep_out, &hs_ep_out);
 	ret = usb_ep_enable(f_fb->out_ep, d);
 	if (ret) {
@@ -455,20 +454,27 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 	fastboot_tx_write_str(response);
 }
 
-static unsigned int rx_bytes_expected(unsigned int maxpacket)
+static unsigned int rx_bytes_expected(struct usb_ep *ep)
 {
 	int rx_remain = download_size - download_bytes;
-	int rem = 0;
-	if (rx_remain < 0)
+	unsigned int rem;
+	unsigned int maxpacket = ep->maxpacket;
+
+	if (rx_remain <= 0)
 		return 0;
-	if (rx_remain > EP_BUFFER_SIZE)
+	else if (rx_remain > EP_BUFFER_SIZE)
 		return EP_BUFFER_SIZE;
-	if (rx_remain < maxpacket) {
-		rx_remain = maxpacket;
-	} else if (rx_remain % maxpacket != 0) {
-		rem = rx_remain % maxpacket;
+
+	/*
+	 * Some controllers e.g. DWC3 don't like OUT transfers to be
+	 * not ending in maxpacket boundary. So just make them happy by
+	 * always requesting for integral multiple of maxpackets.
+	 * This shouldn't bother controllers that don't care about it.
+	 */
+	rem = rx_remain % maxpacket;
+	if (rem > 0)
 		rx_remain = rx_remain + (maxpacket - rem);
-	}
+
 	return rx_remain;
 }
 
@@ -480,7 +486,6 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
 	const unsigned char *buffer = req->buf;
 	unsigned int buffer_size = req->actual;
 	unsigned int pre_dot_num, now_dot_num;
-	unsigned int max;
 
 	if (req->status != 0) {
 		printf("Bad status: %d\n", req->status);
@@ -518,11 +523,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
 
 		printf("\ndownloading of %d bytes finished\n", download_bytes);
 	} else {
-		max = is_high_speed ? hs_ep_out.wMaxPacketSize :
-				fs_ep_out.wMaxPacketSize;
-		req->length = rx_bytes_expected(max);
-		if (req->length < ep->maxpacket)
-			req->length = ep->maxpacket;
+		req->length = rx_bytes_expected(ep);
 	}
 
 	req->actual = 0;
@@ -533,7 +534,6 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req)
 {
 	char *cmd = req->buf;
 	char response[FASTBOOT_RESPONSE_LEN];
-	unsigned int max;
 
 	strsep(&cmd, ":");
 	download_size = simple_strtoul(cmd, NULL, 16);
@@ -549,11 +549,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req)
 	} else {
 		sprintf(response, "DATA%08x", download_size);
 		req->complete = rx_handler_dl_image;
-		max = is_high_speed ? hs_ep_out.wMaxPacketSize :
-			fs_ep_out.wMaxPacketSize;
-		req->length = rx_bytes_expected(max);
-		if (req->length < ep->maxpacket)
-			req->length = ep->maxpacket;
+		req->length = rx_bytes_expected(ep);
 	}
 	fastboot_tx_write_str(response);
 }
-- 
cgit v0.10.2


From 842769ea51d849fee3f6c03939cabd3971e75cfd Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Tue, 19 Apr 2016 15:20:39 +0300
Subject: usb: s3c-otg: Fix short packet for request size > ep.maxpacket

Request size can be greater than ep.packet and still end in a
short packet. We need to tackle this case as end of transfer
(if short_not_ok is not set) as indicated in USB 2.0 Specification [1],
else we get stuck up on certain protocols like fastboot.

[1] - USB2.0 Specification, Section 5.3.2 Pipes

Reported-by: Steve Rae <steve.rae@broadcom.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <steve.rae@broadcom.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>

diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index bce9c30..9aa0f33 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -229,7 +229,7 @@ static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
 				ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
 
 	req->req.actual += min(xfer_size, req->req.length - req->req.actual);
-	is_short = (xfer_size < ep->ep.maxpacket);
+	is_short = !!(xfer_size % ep->ep.maxpacket);
 
 	debug_cond(DEBUG_OUT_EP != 0,
 		   "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
-- 
cgit v0.10.2


From 4d5b63784317821650f614c9bf9a9b9c6949baee Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Fri, 22 Apr 2016 11:02:06 +0200
Subject: usb: s3c-otg: Fix remaining bytes in debug messages

Remaining bytes means bytes that are not yet transferred
and not the bytes that were transferred in the last transfer.

Reported-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <srae@broadcom.com>
[Test HW: bcm28155_ap board]

diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 9aa0f33..12f5c85 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -235,7 +235,7 @@ static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
 		   "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 		   "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 		   __func__, ep_num, req->req.actual, req->req.length,
-		   is_short, ep_tsr, xfer_size);
+		   is_short, ep_tsr, req->req.length - req->req.actual);
 
 	if (is_short || req->req.actual == req->req.length) {
 		if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
@@ -292,7 +292,7 @@ static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
 		"%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 		"is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 		__func__, ep_num, req->req.actual, req->req.length,
-		is_short, ep_tsr, xfer_size);
+		is_short, ep_tsr, req->req.length - req->req.actual);
 
 	if (ep_num == 0) {
 		if (dev->ep0state == DATA_STATE_XMIT) {
-- 
cgit v0.10.2


From e1b0f6fe3d0a0317486fb879e83dc1440cac3029 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Fri, 22 Apr 2016 14:19:25 +0530
Subject: drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info
 env

U-Boot crashes when an invalid dfu_alt_info is set and tried
using dfu command. Fixing this as it is handled in dfu-mmc.

=> dfu 0 ram 0
data abort
pc : [<9ff893d6>]          lr : [<9ff6edb9>]
reloc pc : [<808323d6>]    lr : [<80817db9>]
sp : 9ef36cf0  ip : 00000158     fp : 9ffbc0b8
r10: 9ffbc0b8  r9 : 9ef36ed8     r8 : 00000000
r7 : 00000000  r6 : 9ffbc0c8     r5 : 9ef36cfc  r4 : 9ef392c8
r3 : 00000004  r2 : 00000000     r1 : 9ff9a985  r0 : ffffffff
Flags: Nzcv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...

resetting ...

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c
index e094a94..1391a0d 100644
--- a/drivers/dfu/dfu_ram.c
+++ b/drivers/dfu/dfu_ram.c
@@ -54,19 +54,26 @@ static int dfu_read_medium_ram(struct dfu_entity *dfu, u64 offset,
 
 int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s)
 {
-	char *st;
+	const char *argv[3];
+	const char **parg = argv;
+
+	for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) {
+		*parg = strsep(&s, " ");
+		if (*parg == NULL) {
+			error("Invalid number of arguments.\n");
+			return -ENODEV;
+		}
+	}
 
 	dfu->dev_type = DFU_DEV_RAM;
-	st = strsep(&s, " ");
-	if (strcmp(st, "ram")) {
-		error("unsupported device: %s\n", st);
+	if (strcmp(argv[0], "ram")) {
+		error("unsupported device: %s\n", argv[0]);
 		return -ENODEV;
 	}
 
 	dfu->layout = DFU_RAM_ADDR;
-	dfu->data.ram.start = (void *)simple_strtoul(s, &s, 16);
-	s++;
-	dfu->data.ram.size = simple_strtoul(s, &s, 16);
+	dfu->data.ram.start = (void *)simple_strtoul(argv[1], NULL, 0);
+	dfu->data.ram.size = simple_strtoul(argv[2], NULL, 0);
 
 	dfu->write_medium = dfu_write_medium_ram;
 	dfu->get_medium_size = dfu_get_medium_size_ram;
-- 
cgit v0.10.2


From 3517de6d26de7baeddb2c9e9bf145456c35885e1 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 22 Apr 2016 13:34:16 -0600
Subject: dfu: ram: fix number base of RAM entity parameters

U-Boot typically interprets unprefixed numbers as base 16, and DFU RAM
entity parsing has historically done so. Reverse the change to default
to base 10, so that values in previously working command-lines aren't
mis-parsed, causing RAM corruption, crashes, hangs, etc.

Fixes: 6aeb877afef0 ("drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info env")

Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
[Test HW: AM335x BBB]

diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c
index 1391a0d..c1b0021 100644
--- a/drivers/dfu/dfu_ram.c
+++ b/drivers/dfu/dfu_ram.c
@@ -72,8 +72,8 @@ int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s)
 	}
 
 	dfu->layout = DFU_RAM_ADDR;
-	dfu->data.ram.start = (void *)simple_strtoul(argv[1], NULL, 0);
-	dfu->data.ram.size = simple_strtoul(argv[2], NULL, 0);
+	dfu->data.ram.start = (void *)simple_strtoul(argv[1], NULL, 16);
+	dfu->data.ram.size = simple_strtoul(argv[2], NULL, 16);
 
 	dfu->write_medium = dfu_write_medium_ram;
 	dfu->get_medium_size = dfu_get_medium_size_ram;
-- 
cgit v0.10.2


From adad96e60d0eb1bbc4d0b96c89decf385a426e42 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Thu, 21 Apr 2016 21:37:19 -0400
Subject: configs: Re-sync HUSH options

Move all cases of CONFIG_SYS_HUSH_PARSER out of the config.h files.  Remove
all cases of CONFIG_SYS_PROMPT_HUSH_PS2 as everyone uses the default.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 8cb7ac7..f034f1f 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 6a0d815..6679b04 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index a790856..be6ff9f 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 77a1228..1934cf8 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index cc5858e..5d6da22 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 7b0309c..58748a7 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 9507b87..e01d722 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 40f8c98..e19f872 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index fc1be7d..486baed 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 8262be5..ce34985 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 44f3982..bea5100 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 9d5365d..6f0362f 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,6 +6,7 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index 0e2b0a8..d9804d7 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 9875191..66da74e 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index c2f903b..1b97a6a 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 5533cb3..ff76dae 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 051dccb..d26fe6e 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index e6807df..b0faa7f 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index b7832db..a63686c 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index e68c19f..a29ab17 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index a199806..f8ccf4a 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 1f2d2b8..b30132e 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index e9c3723..7b5cea5 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index f46c0ca..9258040 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index b3829f5..db01bbb 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index 88f2ade..c59d2e5 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index 568470b..e5364bf 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 58bf069..3688646 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index 13e8325..3b75bb4 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index 92c4e28..822c14b 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 291c879..53e5626 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index bb49265..bd8cf10 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 076a99e..23d7138 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index 3e21ef4..27dda3a 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 5c4ba30..f3febf6 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index 047f315..ecd0ddb 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index 1aa92e5..91cadef 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index 66500e7..9b612f8 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 3531479..0eb8f15 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index 7ceec10..a40bd6c 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index d9b1bd6..054d7ce 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 496c20e..b3b36ac 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index bea850f..6b455b1 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index c6e5e08..93eea63 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index 53889f1..5bf96b8 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index e236129..3597dbb 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 214aff7..7c6f233 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 5a38c19..0e72d2c 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -8,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index 1cb010d..d0a2bd2 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 3257aae..393f337 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 2ce8cb1..85322d4 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -18,6 +18,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 4b9d722..26c770c 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index c884115..22372ef 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 5a037a9..ea7cc0c 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 255f35d..608ee14 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -5,16 +5,17 @@ CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC0_CD_PIN="PF6"
-CONFIG_I2C0_ENABLE=y
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
 CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
 CONFIG_USB1_VBUS_PIN="PD29"
 CONFIG_USB2_VBUS_PIN="PL6"
+CONFIG_I2C0_ENABLE=y
 CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index 999eb32..a7c8897 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_NETDEVICES=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 310bedf..2618a72 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_NETDEVICES=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 5f01760..12f74df 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 02bcdbf..cbe8341 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index fef3685..883edd9 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 90dd734..2209cbf 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -7,7 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-#CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index d2111c6..96a876c 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 378abce..718aba5 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index c3f0421..0e95c76 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 9d8d325..9af4db9 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index 62cebda..19f8983 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index de73e30..bc6f63a 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index 139811c..a42f603 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index a3cf48b..a6c595d 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index ad29d52..bdfa3b4 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index 62cebda..19f8983 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54418TWR=y
 CONFIG_SYS_TEXT_BASE=0x47E00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig
index 799a1b6..641fa06 100644
--- a/configs/MIP405T_defconfig
+++ b/configs/MIP405T_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
 CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig
index 3a012e7..2250011 100644
--- a/configs/MIP405_defconfig
+++ b/configs/MIP405_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 49bb26a..a363004 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 4ab53dd..546e7c7 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 4fa6a8c..ca1cfcd 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index beca636..9d4db2a 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index af4d66a..0df5e8b 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index 1c01c61..8913a18 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index 429a125..f6d7c0f 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8315ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index a611fae..3d13b8f 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8323ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index 2ae7298..e573e0d 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 100734d..c32e0e9 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index abfceac..2247e38 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index caa57c5..a4b4257 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 98aa648..efc6555 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index cd43a7c..ab992fc 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 0fd62ba..64a8241 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 717d75a..61f9e79 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index bc49a39..90a0df5 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index fd6721c..eb1a597 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index eaee581..99ff225 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index a135f0a..f0bd789 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index af1ea37..957c102 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index b91b4e4..2eb8873 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index 9163118..b551c80 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index ff5f90b..60b944b 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
index c1923f0..6efbbc5 100644
--- a/configs/MPC8540ADS_defconfig
+++ b/configs/MPC8540ADS_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8540ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index 99a1f8c..dde5a24 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index f79c2f2..1ab88f6 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index 8937682..fd64677 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8544DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_RTL8139=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index dd4b9d0..5bdf2cc 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 1cddf9e..00595c4 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 8ac3360..a95ea81 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index 0d183db..e4ab923 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index 0a31799..12364d1 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig
index 6f33234..11100c3 100644
--- a/configs/MPC8560ADS_defconfig
+++ b/configs/MPC8560ADS_defconfig
@@ -3,4 +3,5 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8560ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 3efd2e5..7d4b01c 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8568MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index 193561a..597dad7 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="ATM"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index e5467ab..adcbf49 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index c260aee..9dc690f 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 5e000ea..76b9d25 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index 515edb5..2b4cc3a 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8610HPCD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index cfe26ea..e1fb77f 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -4,7 +4,7 @@ CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_RTL8139=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index b745f8b..9b2a697 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -3,7 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_RTL8139=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 5559444..2f4e024 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,6 +10,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 3d71bf5..7cf7b9d 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index cef9794..041baab 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index b3f825e..e49be8a 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index f076e30..3dab55c 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index eccf372..0d1c90e 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index d72dcc0..fb88d94 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 0d1ba15..1db614f 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index f0b4384..7291022 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 53e023a..3003c3e 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH18"
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 53f9bfe..bf88df6 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,6 +6,7 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index 6b999ed..f393019 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index 5bb5a44..bc211aa 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D300=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index 8865937..210da9a 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="++++++++++"
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index 9364366..8cbf6eb 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="++++++++++"
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index d57021f..f33191b 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index 7c3ff8c..14b940f 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2I=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index 9a38f11..6c9eeb4 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index a60bfdd..84e4243 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index 8037be4..00c516f 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index 60666bd..55ff0fa 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index 053e048..9556964 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O3DNT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 00c671b..6f502db 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index a865255..c07d25e 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index 70140f4..d91e4d3 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index a0a8d06..6af298f 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index ef2c1ef..72dac9f 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 7df594d..b0410b0 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 6d6710f..14b9511 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 775ed29..1036eb4 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 60f736f..ac8ca85 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index 406334a..e668725 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 1dd5cef..f99039d 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index d969d0e..8af53af 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index fefbf64..01ae04c 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index e5f29c0..cb50efb 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 5540a61..f536056 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index d551d3f..540dc07 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index a8fbfaa..0f3d4bc 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 627d953..8777721 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index 2215969..ee28938 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 980cf7c..3518769 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index f98ccb3..1aa52d0 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 2fd6c47..76d1191 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 33bff1f..0be70bf 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 2cfc763..cd7fd1a 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index c9c6de9..216f9c60 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index 29ae621..dbe5ac5 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 5fa7e72..47799fa 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 4379db5..d65c724 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 1b478e4..3712bc2 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index f92483f..ab7e97f 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index fd24450..b3b21c2 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 83f7f76..540c7ec 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index a128d0c..b3fa9d4 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 4e4de4b..f079220 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 7817039..42021ce 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index f2aae6e..be8cdd6 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index b54ab14..2d94d7b 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index aec845c..6d04758 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 6a2affe..3d6e980 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 4ebb430..d118293 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 91aed54..526e65a 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index a6fb793..450dbd5 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 3cfe779..5a3d66e 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 7d8f0db..8fcbccf 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 486ff91..77b4b6e 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 69930fe..a0e5bc3 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index d2cac5b..6d2c02f 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index da1d409..26b7697 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index 9028763..b79b65a 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 8e42e59..6f8615a 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index 1a9e1a8..059f9f2 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 4487d01..e54d751 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index f0cd301..e331a8d 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index f2dcdeb..6d83700 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index c14adaf..03795da 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 21b154a..01fb7ff 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 61f56e1..80dcc12 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index 2b4c7e7..3d339e0 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index 2a83e6a..3f4f413 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 34b61f4..3cdbb8d 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index c9b06fe..bf4b56e 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index fe781aa..c94b53b 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index 5f8c788..98f2c03 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 3072c16..b08b27a 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index e6eac27..5ec0151 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index dfe7696..f444513 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index 5a8966f..32871bb 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 6c3e547..bfd47ee 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index ee181de..4ca3893 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index b874f55..d63a6dc 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 8e8c1af..dc3cdc9 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index d0e363c..312e2e2 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index aff4ae0..a3adca6 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index 8b0fdd9..c394d41 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 7d39a34..7bd725e 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 945d51f..56e4d87 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index 176cd74..56f0b65 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index e6ebb61..4edf2e3 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index d4f00e6..c3d47fc 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index ac345f6..a700fcd 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index e8e56b6..1fb4331 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 641784b..fc63360 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 1484ac2..1c6e99f 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 2226979..f14e444 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 09416fb..eccf03a 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index c9eb16a..ec04df9 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 036fd70..02b94e9 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 2896693..890e100 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index f488251..9553ab5 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index 0afbd0c..1eb8835 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index c234c71..887ff28 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index da81767..4684fc9 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index db083a0..c238729 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 43a7c59..a7995c3 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index b9bdac0..f3037ea 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 8b861d3..9bbce6e 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index c341b51..7499ff8 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 3cc04a9..291c3d1 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 492910b..febb822 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 760194c..66dea95 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index ae2e13a..4774147 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index baf548e..3aebc39 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index e2b96c3..aec0624 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index cb57053..99b3932 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index a9ea36b..f70a45c 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index fb7bda6..448b489 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 9d9ff67..298ee59 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index bc6c190..8ac8a9e 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index a7d32bc..abbe15d 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index 00731af..5c272bb 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 229cd56..84df506 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index eeff54d..1a91eca 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 6fafb44..72629a4 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 9e35593..79b9f62 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 28230ad..f71423d 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 388c1c0..2f2628e 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig
index 046a5d8..2bac731 100644
--- a/configs/PIP405_defconfig
+++ b/configs/PIP405_defconfig
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PIP405=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index ae1f1e8..02fa5e4 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 013c35e..ce1a70e 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,6 +6,7 @@ CONFIG_DRAM_ZQ=15291
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index 181e1e2..174de08 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index d3fd857..4b69996 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -14,6 +14,8 @@ CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
@@ -21,4 +23,3 @@ CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
-CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 28d7e1f..48511ec 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index ce3bc30..aabd1a3 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 0030f8d..16b3066 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 7b9c518..4b7ad52 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index d3131cb..d79763a 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index c4b2f1a..f15855b 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 7a7cf65..dac71a9 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 308e009..5adfe02 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index c12abf4..7748356 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index bd96807..447283b 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 8874033..3c68c9f 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index 42b9552..9a1d324 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index e2e9373..5f34727 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index c68982c..474ae53 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 9f29bbf..1eba789 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 712eec4..c4918a7 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index b1f5549..9878b65 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index b2fe48a..b27dd6c 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index f93b541..67cdc3a 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 1e1c5cc..3c7296d 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index ee68bf7..94aea4f 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index 744e37d..d5513f5 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 6a4332a..5d54cb5 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index 46fed6d..fb37784 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 5b1ddb6..5d02f71 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 7198bb2..6512dad 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index a60420b..a878194 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 7bc8872..9570b7b 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index 3492c83..82e8f0f 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index 17cdce3..fa6bbfc 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 99e6723..9c09bf0 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 9101b9b..2b8f5de 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 9764c1d..906b243 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 1d1799b..1025ce4 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 56f9f4e..0ad874a 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index f079ccb..a37117f 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index b78eb28..4d5ca01 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 11df100..0de0b4c 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index dd4a2cc..99cdd37 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 65d51c7..41ad0e2 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 421ebd6..cedd085 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 55463a6..9025458 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 4074a65..572da36 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 7beaad7..a2d3df4 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 7c7b131..b4bd589 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index e30048a..75c7860 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index a2236e1..dd2343d 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 9753814..8f7e7ee 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 75d33c5..325dbfa 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 33f7d5f..261e027 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 07a5b06..b7287b0 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index c1549c1..e72878d 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index ab5453c..abe0d2b 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 6275d27..16b38ec 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index 9c805d0..cd25ea9 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 2cef3ec..63cfc78 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index b8bb371..5048d46 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index f8488b6..d73d8f2 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 255ae58..27c4543 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index c74aecf..a283293 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index f430c34..80c3318 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 191370f..015f85d 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 1ffecc3..d0979b1 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index 8bd2174..c8e3a9b 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index fa4f1dd..30cbeb9 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 2737244..6e19e3a 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 10513aa..4c8932c 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index a6525aa..e374328 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index a124477..b8589b6 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index fc622c9..c622fa6 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index c7c0931..71b4592 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index cb1119b..960cc3c 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index 30327a9..14afa02 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index d21c148..c49fc53 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index 1f88448..fcd8b35 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index 7803ea1..bb04df5 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index 74cdec6..285e773 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -3,5 +3,6 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 08d1af6..5148764 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index 666a339..8f6b674 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 26ddc10..af4a72d 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_TQM834X=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 2d78e79..646c552 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index 4c66cc1..63941ac 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index 6bebf60..869a7d3 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index e600cd0..8022398 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index 2295e42..7b24eeb 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index 81e5fbf..672ad4c 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index 41dd2fd..af57396 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index 9915cc9..cd76e95 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index ef1f78c..403ec90 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM866M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index 7fbdd86..f9d8610 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM885D=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index ade4fa8..a58e0aa 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -3,5 +3,6 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 199ebf1..31db63d 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
index 52750f4..f2b833d 100644
--- a/configs/UCP1020_SPIFLASH_defconfig
+++ b/configs/UCP1020_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b"
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index 0633752..c94c3b7 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="B$ "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index d36a5dc..bf17a63 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,6 +20,7 @@ CONFIG_VIDEO_LCD_TL059WV5C0=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
index 927967d..0996af0 100644
--- a/configs/VCMA9_defconfig
+++ b/configs/VCMA9_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
 CONFIG_TARGET_VCMA9=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VCMA9 # "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 5f3d624..cdcd4eb 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index bfc8cba..5d0f327 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index fc43cc5..cb21222 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB1_VBUS_PIN="PG12"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 65c1d8e..2f2c26b 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,6 +19,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 958104e..a5b215f 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index 0662d40..abc6241 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_A3M071=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_LIB_RAND=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig
index bbc140d..f9ac1fc 100644
--- a/configs/a4m072_defconfig
+++ b/configs/a4m072_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_A4M072=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="asdfg"
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index dbc5de8..356949e 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_LIB_RAND=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index 6434f4b..4a985cc 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ACADIA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index e43a121..51cabb4 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index d8e793f..7e0dcf5 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 10d4311..e5daa94 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 5ca0f24..d40a9e6 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index bc84100..aebfb58 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 4a724aa..bc4f667 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_AM335X_EVM=y
 CONFIG_NOR=y
 CONFIG_NOR_BOOT=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 5428941..346def4 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 7f7a55d..c457f6f 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 1ee07c9..554af51 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index 5d448c3..3d0d215 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_AM335X_IGEP0033=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 0b6c11f..2eca61c 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index 72172cf..b9115af 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_AM3517_CRANE=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_CRANE # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 6a38f98..b9edf0d 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AM3517_EVM=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_EVM # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 69f5ac7..742e148 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index c7a9fbe..276d14a 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index d6a1c3c..aee1584 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 67a9d49..b435ea7 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 2194b16..81afd7b 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 6840453..218b524 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index e40c24a..3b1fed2 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index cb91719..375c10c 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_BEAGLE_X15=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 0686129..79031d2 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA30=y
 CONFIG_TARGET_APALIS_T30=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Apalis T30 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 3d6fe7b..5143e26 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_APF27=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="BIOS> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index e69fce2..8352247 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_APX4DEVKIT=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index 9a2cf6d..69b0c6b 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_ARCHES=y
 CONFIG_DEFAULT_DEVICE_TREE="arches"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index 5848709..19f1c41 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_ARIA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 7e2c026..0e16206 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS2=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 88670df..aa3f357 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS2B=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index e808c21..9eca59a 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index b323e98..3fe7e97 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ARNDALE # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index f787bb7..c616eb4 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -1,5 +1,6 @@
 CONFIG_M68K=y
 CONFIG_TARGET_ASTRO_MCF5373L=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="URMEL > "
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index 7c99aa0..bba7e5d 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 96a4536..3868ac1 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 1ca4f46..332dc73 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 1ca4f46..332dc73 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index 15306e6..ebcb08d 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 2cf8cb9..0109a17 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index abb044c..66a6ec3 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index c4d3962..0eea74b 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 4d42256..276479a 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 6f45120..9c8aa32 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index df099b2..600a370 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 20cf592..71446cf 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index b6154da..fce9c5e 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index b782e25..f1c6dfa 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 66be263..7e660d7 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 0eba857..8a2aadd 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 1cfb380..43733ac 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index a5491cf..c8f39c9 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BAMBOO=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index dfafb0b..30c65fa 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -12,6 +12,7 @@ CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index a1fc989..f7de603 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index a49b3dc..754499f 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 969c5bc..f3ec577 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 25c8ff6..d32e533 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index c1b41eb..fc78fc0 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index ed1dea5..a9c1d31 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index 8fcde6c..584ce17 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index 670b57f..6aebcb0 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index 8fcde6c..584ce17 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index 8fcde6c..584ce17 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index 4a24da2..60ad272 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCMNSP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
index 7cc0e4e..bd0acfa 100644
--- a/configs/bct-brettl2_defconfig
+++ b/configs/bct-brettl2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BCT_BRETTL2=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index a67d803..bf22c7a 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA30=y
 CONFIG_TARGET_BEAVER=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index c11617a..92c3ee7 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BG0900=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 5828e2b..1e22f5c 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -4,6 +4,7 @@ CONFIG_BAV_VERSION=1
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index bbefb55..c024d03 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -4,6 +4,7 @@ CONFIG_BAV_VERSION=2
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index 5316aa2..6dcb95a 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BUBINGA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index db05c09..13b57ca 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index e421fe1..5da27d2 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_CAIRO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Cairo # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index 374023e..a2ba4b0 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_CALIMAIN=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Calimain > "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR="\x0b"
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index 8815005..3d643f5 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index 8c5c9cd..99af7ce 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index 360ee6e..a2e27be 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_CANYONLANDS=y
 CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index eba46e7..c4a0580 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA30=y
 CONFIG_TARGET_CARDHU=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index ad6f093..ffc4d7c 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_CGTQMX6EVAL=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index 7732c29..7e50cfc 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CHARON=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index b00e2bf..1fef01e 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -9,6 +9,7 @@ CONFIG_DM_KEYBOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 9cf7b0e..667d0ae 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -11,6 +11,7 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index fd1d9ca..11f25a4 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -10,6 +10,7 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 3d79502..ba03f7d 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -8,6 +8,7 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index c37442d..13612f7 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CM_FX6=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-FX6 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 1cabf0e..7fe6be3 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_CM_T335=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T335 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 054a1c9..ea3e492 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T3517=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3517 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 71a9005..2f9f228 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T35=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3x # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index c03a553..f44ee68 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_CM_T43=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T43 # "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index 439302c..496a3d3 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP54XX=y
 CONFIG_TARGET_CM_T54=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T54 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index d1de116..2dead77 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_COLIBRI_PXA270=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 57e0eb5..70da60c 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_COLIBRI_T20=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri T20 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 583de25..4f25973 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA30=y
 CONFIG_TARGET_COLIBRI_T30=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri T30 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 5481f04..bcafd59 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SPI=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri VFxx # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_SPI=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index ae67c37..ac83103 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 24a927d..83d477e 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -12,6 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index b46f4cc..b5b6e7c 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_TPM=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index 25eb520..0590c8a 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_TPM=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index a1c7df7..ff5c22e 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_COREBOOT=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index bae8a05..3318221 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_CORVUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 71028cf..8bf4e14 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -2,6 +2,7 @@ CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
 CONFIG_TARGET_COUGARCANYON2=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index b4e1876..8ea281e 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -10,6 +10,7 @@ CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index b2d2aeb..1b2fbfd 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index 870186c..b4820cf 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 6d7f984..605aba7 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 7aba5c4..fdf6786 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index a1e2a73..59835a7 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA114=y
 CONFIG_TARGET_DALMORE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index ffdf8d7..8d1b786 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_INTIP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 57894da..d7e9235 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_DEVKIT8000=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index c76af0e..b8e04f3 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
index ad424dd..4ac8bda 100644
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
index ce9cbf0..e43a910 100644
--- a/configs/digsy_mtc_defconfig
+++ b/configs/digsy_mtc_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR=" "
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
index 0fc08d8..be8b855 100644
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
index 9a9d215..67a8f2a 100644
--- a/configs/digsy_mtc_rev5_defconfig
+++ b/configs/digsy_mtc_rev5_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index dd98059..1f4c633 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION_10G=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index c6fee13..dd673b0 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index ed83019..493da5b 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DNS325=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 4aa76b1..287a6bd 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 64ab406..99db387 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 1b1c0be..b039719 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DRA7XX_EVM=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 0130188..3f9724b 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index ca80077..6161057 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 7c3f828..abbc636 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DRACO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 2f33a8a..b64941f 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SNAPDRAGON=y
 CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="dragonboard410c => "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 242158e..2648ccc 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN4I=y
-CONFIG_DRAM_CLK=360
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
@@ -15,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 30e5255..3312dda 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP44XX=y
 CONFIG_TARGET_DUOVERO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="duovero # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 38c085a..6ce9de5 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -3,6 +3,7 @@ CONFIG_TEGRA=y
 CONFIG_TEGRA210=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index 6fe19c7..cdcfdf6 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_EA20=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ea20 > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 27535df..63fd75b 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_ECO5PK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ECO5-PK # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
index 452bf0d..8a76405 100644
--- a/configs/edb9315a_defconfig
+++ b/configs/edb9315a_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_EDB93XX=y
 CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index 6ed785f..e58a65d 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ORION5X=y
 CONFIG_TARGET_EDMINIV2=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="EDMiniV2> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index 7d83445..6f2967b 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_EFI=y
 CONFIG_DEFAULT_DEVICE_TREE="efi"
 CONFIG_TARGET_EFI=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 04d8611..d25c225 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_ETHERNUT5=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 0689e97..fc40b1d 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_EVB_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_REGMAP=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index cb394cd..64cc90a 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 5e35601..94f283a 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_FLEA3=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="flea3 U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index db979ec..ae90d45 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="FO300"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 34e74af..da8e2fe 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -18,6 +18,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 6620a85..e613074 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -7,6 +7,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index 695d860..98a0dcc 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_GDPPC440ETX=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_SYS_NS16550=y
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 24ef9e8..3f134cc 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B450V3=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index 75c49c0..067858d 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B650V3=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 85140cd..5205152 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B850V3=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 1943882..3517348 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index c7b5b76..7069c28 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig
index 6c5c9e3..5e8bd8b 100644
--- a/configs/grasshopper_defconfig
+++ b/configs/grasshopper_defconfig
@@ -1,5 +1,6 @@
 CONFIG_AVR32=y
 CONFIG_TARGET_GRASSHOPPER=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index a14de0d..0e53cc5 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 49ee273..029fee0 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Ventana > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig
index 0fadc90..57f157a 100644
--- a/configs/h2200_defconfig
+++ b/configs/h2200_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_H2200=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index e04d96b..a2e6a1c 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -11,6 +11,7 @@ CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index 77de58a..9d6a3aa 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index d4aafe9..00dc37d 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_HARMONY=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
@@ -19,8 +20,8 @@ CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index b44763e..a91f420 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 8b75642..3f1f928 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index b7ef33b..45241b4 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 13cf81d..1d3d9b2 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -6,5 +6,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 54fa819..1d5bb33 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 7ec54a7..71cfb75 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 5e68769..ccd01f5 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 3dea793..3c4d960 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index 548a07e..7fe6bf0 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index 39b5185..a55bbdb 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ICON=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index f962d7d..3bf051e 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
 CONFIG_AUTOBOOT_DELAY_STR="ids"
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 2731e94..6f6c539 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig
index dec1f8d..d8ffa00 100644
--- a/configs/igep0020_nand_defconfig
+++ b/configs/igep0020_nand_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
index 73b02e9..0ebf508 100644
--- a/configs/igep0030_defconfig
+++ b/configs/igep0030_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig
index ab65213..b0c4700 100644
--- a/configs/igep0030_nand_defconfig
+++ b/configs/igep0030_nand_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index a779d47..3a751c5 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index a8b32cb..8d24877 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index 0b03e16..446e841 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index 27b5019..d701617 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 153450f..c5a6c65 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 6e49081..4f68833 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
index 6291139..e6b0bc4 100644
--- a/configs/integratorap_cm720t_defconfig
+++ b/configs/integratorap_cm720t_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM720T=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
index 7132607..4afd0e6 100644
--- a/configs/integratorap_cm920t_defconfig
+++ b/configs/integratorap_cm920t_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM920T=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
index f58e256..0cfbbf3 100644
--- a/configs/integratorap_cm926ejs_defconfig
+++ b/configs/integratorap_cm926ejs_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM926EJ_S=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
index b32512d..f25c5ba 100644
--- a/configs/integratorap_cm946es_defconfig
+++ b/configs/integratorap_cm946es_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM946ES=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig
index 76c8998..36e8ad7 100644
--- a/configs/integratorcp_cm1136_defconfig
+++ b/configs/integratorcp_cm1136_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM1136=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig
index ca7beb3..817544a 100644
--- a/configs/integratorcp_cm920t_defconfig
+++ b/configs/integratorcp_cm920t_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM920T=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig
index 71ca032..ae69cee 100644
--- a/configs/integratorcp_cm926ejs_defconfig
+++ b/configs/integratorcp_cm926ejs_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM926EJ_S=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig
index d4d11b8..85086a5 100644
--- a/configs/integratorcp_cm946es_defconfig
+++ b/configs/integratorcp_cm946es_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM946ES=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index 48f1bdb..fea4d10 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="INTIB"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_SYS_NS16550=y
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index 083d94a..01378b3 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_IO64=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_SYS_NS16550=y
diff --git a/configs/io_defconfig b/configs/io_defconfig
index de2749e..03a2898 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_IO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index 069db16..aa51065 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_IOCON=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index b02b496..6b46da0 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_IPAM390=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 9cb8b1d..666b7a8 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index bf509c2..a2be6f5 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA124=y
 CONFIG_TARGET_JETSON_TK1=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig
index a3c259f..072633c 100644
--- a/configs/jupiter_defconfig
+++ b/configs/jupiter_defconfig
@@ -1,4 +1,5 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_JUPITER=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index c843508..efddf9f 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -5,15 +5,16 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2e-evm"
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="K2E EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_TI_AEMIF=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
-CONFIG_TI_AEMIF=y
-CONFIG_CMD_NAND=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 0545812..2f9b5a0 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_REMOTEPROC=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 1627065..a5bd073 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -5,15 +5,16 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm"
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="K2HK EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_TI_AEMIF=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
-CONFIG_TI_AEMIF=y
-CONFIG_CMD_NAND=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 255f6d1..3437dc4 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -5,15 +5,16 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="k2l-evm"
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="K2L EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_TI_AEMIF=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
-CONFIG_TI_AEMIF=y
-CONFIG_CMD_NAND=y
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index b242d81..08a8fd0 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_KATMAI=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index a9643cf..7bf5858 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP44XX=y
 CONFIG_TARGET_KC1=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="kc1 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index e6e6e0a..401fd4f 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index 349651d..b58ab6a 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index 9a0d85c..9b81c53 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index d2c488e..0da9e21 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 49e1c9b..29eba85 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 6d9a6fa..f8e7f15 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_KM8360=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index b390e3e..05b5259 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 03cfffb..f3c0115 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_KM8360=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index 12d0131..e263b85 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 3a1aa69..5b391be 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 1d29c87..e339b8a 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_TUXX1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index bc9aaec..11022f3 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index dda73be..bac694b 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_TUXX1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index 0a16c04..d8f0d7c 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index b28070b..7ac4cc3 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_SUVD3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index dbe0d22..61c943f 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_TUXX1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index 9dd6894..fcf52f9 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_SUVD3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 2cc9de4..787c020 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_REGMAP=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 22fd057..97b81ef 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_LEGOEV3=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
 CONFIG_AUTOBOOT_STOP_STR="l"
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index b858de9..68172c9 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 70b4a10..224fd8b 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index a24923e..7fa9daa 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index b7e3cd7..cfc31a6 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_LS1021AQDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 70a3445..300ec9c 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index a633393..3b9243a 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 025fd4e..208a1bc 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index e283f69..9d196e1 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 127b8b4..382cd11 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index eff4966..f81e12b 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_LS1021ATWR=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index f25e6e2..c4b1cba 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 74f0445..ebf2466 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index c94581e..67917b2 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 03363a7..6f8666c 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index a44988a..4253f8c 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index c1a6736..a97654c 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 7468c1b..c85039b 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 1694458..41e5104 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index a90c4ad..1ad2801 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 2536821..f339096 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 07b3edc..2823524 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 9967973..fbb3611 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index c25c3c1..86f3f1a 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 97f224d..5423853 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index a273331..7209d8d 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 50f4955..1e27b7f 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index eca5265..679fb87 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 7540c4b..a4055ab 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 408d1ee..961262e 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index a16a6d5..9cc9784 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index b5a64f0..15e4850 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index dde3311..d95774e 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index f8f54e7..860e93c 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 0c90869..67481cb 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index f33cda6..9db98bb 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 9f3fde5..aa5f841 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index 6995819..f9b7f06 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_LUAN=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index b317937..98ecb88 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_LWMON5=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index b587617..55ad865 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_M28EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 4e0368b..2f17ddc 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_M53EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index f7973ed..f7ad872 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MA5D4EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index 79c13cf..d0ab4f1 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MAKALU=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index 2ebd58b..ee3e9ea 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,5 +1,6 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index d24d217..ca28d92 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
 CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 4bdbb6d..a873b61 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index 9c9d51a..5a9247a 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_MCX=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mcx # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
@@ -11,7 +12,7 @@ CONFIG_SYS_PROMPT="mcx # "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
+CONFIG_USB_ULPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index 86d7c3f..15f45df 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MECP5123=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 95bb570..4d9161e 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_MEDCOM_WIDE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
 CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index f207428..64108a7 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index 8931357..3024f52 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig
index dc91157..b7b2fdb 100644
--- a/configs/mgcoge3ne_defconfig
+++ b/configs/mgcoge3ne_defconfig
@@ -4,4 +4,5 @@ CONFIG_TARGET_KM82XX=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index f1e8fd7..5143214 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig
index 86200fa..9d6adea 100644
--- a/configs/mgcoge_defconfig
+++ b/configs/mgcoge_defconfig
@@ -4,4 +4,5 @@ CONFIG_TARGET_KM82XX=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MGCOGE"
+CONFIG_HUSH_PARSER=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index efb9c1e..6689104 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -12,6 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index ce81309..89a52a2 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 720aefa..7bc54d6 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB1_VBUS_PIN="PB10"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index d38bc7f..98a73c2 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index de1b73f..0786fcf 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig
index ea2b28a..100f898 100644
--- a/configs/motionpro_defconfig
+++ b/configs/motionpro_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_MOTIONPRO=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index 865b97b..62bd8e7 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 6fe22b3..5d99cb3 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -3,5 +3,6 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index af76130..21a3b20 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308_P1M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 45913d4..ea4eb55 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -3,13 +3,14 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_MT_VENTOUX=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mt_ventoux => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
+CONFIG_USB_ULPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 4582cce..30de97a 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX23_OLINUXINO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 43e3d0a..dc14b21 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX23EVK=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index 5a4bd57..10d6385 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX25PDK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index f4c934f..5cc051f 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index bb900ff..f93c49a 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 0f76bde..bd6a6e6 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index ad939ca..d91822c 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 699d929..2b98931 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX35PDK=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 0bb0c61..4dd2f78 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX51EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index e8a211a..1580003 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 1c4da22..e9f8f9a 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 273ce16..a572231 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53LOCO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 92e9f63..1285d13 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53SMD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 58e297a..4dfd4e1 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6CUBOXI=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index 60e5dd6..20873c7 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index 01a682f..5fdc267 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 561e886..eb30b16 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 870e403..44db02f 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 7aa7916..4684a3f 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index 5920430..1d0d109 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 61f0a75..25f81fc 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 49aa619..40f9012 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 84faa2f..6ad6fd8 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 7b69de1..595f8d8 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 540a822..0ecc91f 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 2d24622..38cd927 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 65b5e9d..73d9e46 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index fee352c..995f8d1 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 631a998..f194432 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 2ea5c89..bf4d972 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 548adf6..4822d25 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 77d78e7..660b815 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index a6dd96b..b062757 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index fe7e55d..c8894e9 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MX7DSABRESD=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index ab9ebba..34c3b74 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NAS220=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nas220> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index 0366da1..0a6d2eb 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_NEO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index c0aee31..07bc0d4 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index eb26f88..b9ebf04 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index e37523e..f642175 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index e847123..acb1aa2 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 01a6f7e..37c150a 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 34ddff9..6471694 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index c2bea2e..ec15581 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 0ce35b0..69fc732 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index ef2f0e2..2b9689b 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 0aac630..50aef70 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index d6280df..d2f2e0b 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index d7eb39a..f2658cd 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Nokia RX-51 # "
 CONFIG_AUTOBOOT_KEYED=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index f28d884..cdf841c 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index d86a55c..a14a531 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index bb0576a..16d3ad1 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ODROID-XU3 # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index a92bbe1..5f3503f 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Odroid # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index ab54570..ed790f7 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_BEAGLE=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 89fdf80..9efa8d3 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 5fc4bfc..9c294c3 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TAO3530=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index dfbd180..8efd71e 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_OMAP3_LOGIC=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP Logic # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index 2958e24..acb86ee 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_OVERO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Overo # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index e565d65..ed80de0 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_PANDORA=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Pandora # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
index 70f0fdb..cdb91bc 100644
--- a/configs/omap3_zoom1_defconfig
+++ b/configs/omap3_zoom1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_ZOOM1=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index c6ff836..12a4683 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP44XX=y
 CONFIG_TARGET_OMAP4_PANDA=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index d42fc47..1d5dfa2 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP44XX=y
 CONFIG_TARGET_OMAP4_SDP4430=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 135c89d..f9c7de3 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_OMAP5_UEVM=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 8b97508..40165da 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_OMAPL138_LCDK=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 2a32e04..97333c6 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -5,13 +5,14 @@ CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_USB1_VBUS_PIN="PG13"
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB1_VBUS_PIN="PG13"
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 207189a..26ef10e 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -9,8 +9,8 @@ CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB1_VBUS_PIN=""
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 8d78b47..df9d0a2 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -8,11 +8,9 @@ CONFIG_DRAM_ODT_EN=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
-CONFIG_USB3_VBUS_PIN=""
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index e96a273..fa12937 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -6,14 +6,15 @@ CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB1_VBUS_PIN="PG13"
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB1_VBUS_PIN="PG13"
-CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index de4a816..9b85b0e 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_ORIGEN=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ORIGEN # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index 5e8671f..627eae5 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_OT1200=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 2d37d8b..0283ff0 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_OT1200=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index c9f7be2..2683a79 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -4,6 +4,7 @@ CONFIG_TEGRA210=y
 CONFIG_TARGET_P2371_0000=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 086a294..61742c1 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -4,6 +4,7 @@ CONFIG_TEGRA210=y
 CONFIG_TARGET_P2371_2180=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index f7596a5..73a9f4f 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -4,6 +4,7 @@ CONFIG_TEGRA210=y
 CONFIG_TARGET_P2571=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 4d5c758..66eb1ee 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_PAZ00=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index b7c5466..ee729b1 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_PCM051=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="REV1"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index cb39392..632e764 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_PCM051=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="REV3"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 49159ce..c47dc01 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="pcm052"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index 1b9de3d..c94c499 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_PDM360NG=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 23b9762..6132a92 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Peach-Pi # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index adde56f..0427142 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Peach-Pit # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 90ca1d2..d04471b 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_PENGWYN=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 7073739..88a672f 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_PEPPER=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="pepper# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index eba6cd5..750fefd 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -30,11 +30,11 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_PIC32=y
 CONFIG_USB_STORAGE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 687e69b..34d21de 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PICOSAM9G45=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 45bf9b3..a778736 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -6,6 +6,7 @@ CONFIG_DRAM_ZQ=3881915
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index b7e5d7c..e070b79 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PLATINUM_PICON=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="picon > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index cb38895..2218131 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PLATINUM_TITANIUM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="titanium > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 85fe61d..7af9fd4 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_PLUTUX=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
 CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 5a70de1..c43901b 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9G45=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 04c99b9..2c3c7bb 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
index 37c9ddb..07a5507 100644
--- a/configs/portl2_defconfig
+++ b/configs/portl2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 9aa5280..59b6249 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 7a53016..95ab0a3 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_PXM2=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index b467b62..c9c4adc 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 7391464..a107c1b 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 16f8600..27c2c58 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 6378918..93d1086 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 21493aa..0d2d5f7 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_NETDEVICES=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index bb9c6cd..12a7403 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -8,6 +8,7 @@ CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
index 2bc92a5..17efc24 100644
--- a/configs/qemu_mips64_defconfig
+++ b/configs/qemu_mips64_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_CPU_MIPS64_R1=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
index d8a9c71..a8f1912 100644
--- a/configs/qemu_mips64el_defconfig
+++ b/configs/qemu_mips64el_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R1=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
index e855906..69ce12d 100644
--- a/configs/qemu_mips_defconfig
+++ b/configs/qemu_mips_defconfig
@@ -1,5 +1,6 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
index d851075..c1edee7 100644
--- a/configs/qemu_mipsel_defconfig
+++ b/configs/qemu_mipsel_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index ddb184b..cca0156 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -1,5 +1,4 @@
 CONFIG_SH=y
 CONFIG_TARGET_R2DPLUS=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_RTL8139=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 9d9d4bf..343e917 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,6 +6,7 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index abbd67f..095f7c1 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 519e796..56eb3f3 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index e3bb5ae..c6a1130 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RASTABAN=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index ef83153..0b3610f 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_REDWOOD=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 35b96a3..52fe27f 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 5f4c093..3abe68f 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PMIC=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index ff515fd..7cd1e8a 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_2=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 71a0c28..1f189d4 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_3_32B=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 417836b..d52f0b1 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI_3=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index e343c66..59e4e6b 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_BCM283X=y
 CONFIG_TARGET_RPI=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 035fd1e..d7b47e2 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_RUT=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 8c1438d..2e2cc2a 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_TARGET_S5P_GONI=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Goni # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index d91b433..bd2675f 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_S5PC210_UNIVERSAL=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Universal # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index b77c2b5..9abc136 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 5b942b5..f1aff9e 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 1133892..a3377a6 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index e4f577b..dd32e4b 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 969fb4b..1c936c0 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 6e242e0..5f8e4b9 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 2cceb57..d0a0f05 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index e26bb59..73f6a07 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index b2067b9..2e74804 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 53ff55b..72a3e56 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 2b6f4ac..87fa5a3 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 190a8e9..749e489 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 9b5faa0..c3f5931 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index f5281b3..7536c46 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -15,6 +15,7 @@ CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CONSOLE_RECORD=y
 CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
 # CONFIG_CMD_ELF is not set
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 78df0ac..703db9c 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SANSA_FUZE_PLUS=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 3e23852..1189558 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 255d598..fe2300e 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index f97d5ca..71ce297 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index b6f3968..41503f3 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 63f4943..de0e1f3 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index 367711b..1aebb1a 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index a682da2..205f90b 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index dede802..5a1e593 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index b61913e..8e5237a 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_SBC8641D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 06f2322..1bcd479 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SC_SPS_1=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 00cd081..3613286 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_SEABOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 0980e68..d19876a 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -5,6 +5,7 @@ CONFIG_SECOMX6_UQ7=y
 CONFIG_SECOMX6Q=y
 CONFIG_SECOMX6_2GB=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index 6f6007c..1becb75 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index f805238..6b9425c 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index ce514c2..d6ac40b 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SMARTWEB=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
index bb80d55..66c2034 100644
--- a/configs/smdk2410_defconfig
+++ b/configs/smdk2410_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SMDK2410=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK2410 # "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index b3d16ab..7a757ee 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK5250 # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index a84d159..de79ca9 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK5420 # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index cbd8cc3..01a3eb0 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_TARGET_SMDKC100=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDKC100 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 851fc5c..5334f89 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_EXYNOS=y
 CONFIG_TARGET_SMDKV310=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDKV310 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 9315b03..33386b4 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Snapper> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 9c24d79..ec88dfb 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 6a31771..86bae46 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_SNIPER=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="sniper # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 5dbd18a..0b740e9 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="snow # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 9c8671c..d451fea 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -16,10 +17,10 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b68b298..db443c9 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -16,10 +17,10 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index d813dc9..e5ef64b 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -19,7 +20,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 5fe6238..c7f4ff4 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -19,7 +20,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 8894e09..d932993 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -16,10 +17,10 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 562052c..7764879 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -16,6 +17,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
@@ -23,7 +25,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 83eada3..5f19eee 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -9,15 +9,16 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 3b73dbd..4d86ad1 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SOCRATES=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 352bd1a..935257e 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="spring # "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 00d105b..a407d52 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F4=y
 CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 07aa874..abbb1e9 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 704ad89..8934992 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 81b706f..05a2e13 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 6d39dec..28b1633 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,6 +11,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index 79a0ca6..c3e5390 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_SUVD3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index fa495ba..788d5c1 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index e9fe84d..21d2e76 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_T3CORP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index c1eb34c..05021d2 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_TAO3530=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="TAO-3530 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 9f6aa8d..be37090 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TBS2910=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 389603c..d4019f4 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_TEC_NG=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
 CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 56970c4..95d1838 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_TEC=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
 CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 054038a..800abca 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index 9a6abf2..11624d6 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 047dc69..c051460 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_THUBAN=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 52d3a65..5d2a79a 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TI814X_EVM=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 13a2c6e..03365fc 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TI816X_EVM=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot/ti816x# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index 6c93616..de3c26d 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TITANIUM=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Titanium > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 6c52fff..24e64b6 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_TQMA6=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 85b239b..be870ba 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -5,6 +5,7 @@ CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 977f98a..157d762 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -5,6 +5,7 @@ CONFIG_TQMA6S=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index c6dac61..928c480 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -6,6 +6,7 @@ CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index a7068e5..a051a9f 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -6,6 +6,7 @@ CONFIG_WRU4=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
 CONFIG_AUTOBOOT_ENCRYPTION=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 14bdc6a..73fc63c 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Trats2 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index c3b82bb..8fbb5f2 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_TRATS=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Trats # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index bdd9c89..ff2c785 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_TRICORDER=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 3bac8e3..4ed1ada 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TRICORDER=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 2d8579b..98678d5 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_TRIMSLICE=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 1b30033..ac81a46 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TS4800=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index b144575..904bc89 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_TUXX1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 7563336..7bbe36d 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_TUXX1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 064cf91..f6b30c2 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -3,13 +3,14 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TWISTER=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="twister => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
 CONFIG_USB=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
+CONFIG_USB_ULPI=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 3f53749..5e2cb85 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_UDOO=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index e90dd66..fe14f9a 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_USB_A9263=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 68f78b3..b4a3c00 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_TARGET_USBARMORY=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 8624695..b2ae829 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_VE8313=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 75e7579..4ebce04 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA124=y
 CONFIG_TARGET_VENICE2=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 0cce4d4..5dc16b3 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_VENTANA=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 440dccf..1497605 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index c702800..b9bfc26 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS64_JUNO=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index d7f7294..8818527 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM_SERIAL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 0016030..0508796 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS_CA15_TC2=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index b260401..9e53655 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS_CA5X2=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 4a64339..524ef4b 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS_CA9X4=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index d959293..80ec20f 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index b6a96f2..afe8a47 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 565577d..29da314 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_VINCO=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="vinco => "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index e21d4ff..5f0971a 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index fa495ba..788d5c1 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index f6bd308..773b493 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_WANDBOARD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index f37c9f5..77ccecf 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_WARP7=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index b9e4648..c7c1d25 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_WARP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index a818a0f..d443ae3 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -5,6 +5,7 @@ CONFIG_TEGRA20=y
 CONFIG_TARGET_WHISTLER=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index 6c60f5e..f335294 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 2d2ee9e..f73206e 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN_SD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 1a9097a..2999772 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_DM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 3d046cd..25ce098 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -3,5 +3,6 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 881c080..e2a2c81 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_X600=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="X600> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 652e443..515ae41 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_XFI3=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index 2008a8d..edfcc20 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="xlx-ppc405:/# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index 8df33d3..2e65a2c 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="board:/# "
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index 45cd821..e189859 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_XPEDITE1000=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 38f6290..9baac08 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index d9957e0..6b8f4bc 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index a4f648c..538c6cd 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index 10cf7e8..9b3c5c9 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index fb2e7b2..418fb7c 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_XPRESS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 4ac7ef0..b464d15 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_XPRESS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 773e93b..4f76e37 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index bad6df2..9a64852 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -3,5 +3,6 @@ CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index 5dbbaba..b2f9784 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -2,5 +2,6 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_YUCCA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index d2fa63d..299cf65 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ZIPITZ2=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index f853308..955bf37 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ZMX25=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="zmx25> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index e325317..99ce69e 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index ffbc73d..9198418 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_TARGET_ZYNQ_PICOZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 5d9136c..214d754 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index d7c1b96..26cfc0e 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index cec722f..fc58fa1 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 2bc88b8..ea0df44 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index b0fa661..7f8a17a 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 9672940..6a68f7e 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index bc3af09..9cb1485 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 1895f95..89739a6 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 5cc2af8..ae44512 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -64,7 +64,6 @@
 #define CONFIG_EFI_PARTITION
 #define CONFIG_ISO_PARTITION
 #define CONFIG_SUPPORT_RAW_INITRD
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 
 #endif	/* _CONFIG_CMD_DISTRO_DEFAULTS_H */
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 6b6ec00..5262641 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -102,7 +102,6 @@
 #undef CONFIG_SYS_LONGHELP
 #undef CONFIG_CMD_BOOTD
 #undef CONFIG_CMD_RUN
-#undef CONFIG_SYS_HUSH_PARSER
 #undef CONFIG_CMD_ASKENV
 #undef CONFIG_MENU
 #endif
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2d9be20..ef87bda 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -498,11 +498,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 #endif
 
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index e870ffe..e7a90bd 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -241,12 +241,6 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 108e924..17ae12e 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -425,12 +425,6 @@ combinations. this should be removed later
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x4700)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x4800)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER    /* hush parser */
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400800 /* I2C speed and slave address*/
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index a7a5e8e..9c69f91 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -393,9 +393,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index c3a7714..40fff81 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -68,7 +68,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 1b5b907..b0281be 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -92,7 +92,6 @@
  */
 #undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 826de5b..9b87de6 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -210,10 +210,6 @@
 
 #define CONFIG_PRAM			2048	/* 2048 KB */
 
-/* HUSH */
-#define CONFIG_SYS_HUSH_PARSER		1
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 1a793d7..5726605 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -71,7 +71,6 @@
 #endif
 
 
-#define	 CONFIG_SYS_HUSH_PARSER
 /**************************************************************
  * I2C Stuff:
  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 9e9765c..fc625d4 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -321,11 +321,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index d440d88..a3cfe6a 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -374,9 +374,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 3b49f1c..a05ce63 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -302,9 +302,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 97f48e2..8b95920 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -224,8 +224,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index d218f59..4e5e986 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -304,8 +304,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5b0900a..9bf4226 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -330,8 +330,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 4346eda..8cdfcea 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -532,7 +532,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser */
 
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 2475ae4..68a8e71 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -318,9 +318,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index aa66927..366febc 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -344,9 +344,6 @@
 #define CONFIG_FSL_SERDES1	0xe3000
 #define CONFIG_FSL_SERDES2	0xe3100
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 980cb99..27db9ef 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -381,9 +381,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 0a6d5bc..06d54a9 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -231,11 +231,6 @@
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 79f81ec..dd638eb 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -254,11 +254,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 2372d5f..4d56284 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -206,9 +206,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 8d29762..a4868f9 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -331,9 +331,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index b64bbe5..3bce162 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -252,11 +252,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 2284646..a5a3dc4 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -226,11 +226,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a130001..24c32ca 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -237,11 +237,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser*/
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 0e003e5..1224a20 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -248,11 +248,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser*/
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 95f59e0..10ee862 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -377,9 +377,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index ac219d1..7528456 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -233,9 +233,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE	8192
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 1f4ed2a..1f2505f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -269,9 +269,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /*
  * I2C
  */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 249e11b..6e69258 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -619,9 +619,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index bc4c733..d009913 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -406,9 +406,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* Video */
 
 #ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index a53b1ac..833affd 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -172,9 +172,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 2d27fcf..6f9680f 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -336,9 +336,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index b5959c8..5d639b1 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -59,7 +59,6 @@
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_BSP
 
-#define	 CONFIG_SYS_HUSH_PARSER
 /**************************************************************
  * I2C Stuff:
  * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 345affa..0e6ad7a 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -90,7 +90,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index f07b2d1..800c246 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -510,10 +510,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* Video */
 #ifdef CONFIG_PPC_T1024		/* no DIU on T1023 */
 #define CONFIG_FSL_DIU_FB
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 1a22bee..d288a9f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -511,10 +511,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* Video */
 #undef CONFIG_FSL_DIU_FB	/* RDB doesn't support DIU */
 #ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index f52889d..5a4382e 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -411,10 +411,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* Video */
 #define CONFIG_FSL_DIU_FB
 #ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 84e195d..0ba3913 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -465,10 +465,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 #endif
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
 /* Video */
 #define CONFIG_FSL_DIU_FB
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 5957fa8..69d161b 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -455,10 +455,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /*
  * I2C
  */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e0769d0..df4c5dc 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -415,10 +415,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /*
  * I2C
  */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index faf06a0..e075442 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -209,10 +209,6 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index e646c00..8fd3a8b 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -604,7 +604,6 @@
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index d03f2e6..7e3fdda 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -126,7 +126,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 7d39766..fc305f4 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -121,7 +121,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 9ed469a..b9baad6 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -311,7 +311,6 @@
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser */
 
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index c70c4d7..472dbb3 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -110,7 +110,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 52cba86..3aec34c 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -111,7 +111,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index fb2652b..a46f689 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -114,7 +114,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 301a0a8..b44a31b 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -144,7 +144,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index a390e3f..cdbae5c 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -113,7 +113,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 0d2e119..c1866a5 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -114,7 +114,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 6fd08c7..881d654 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -117,7 +117,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index fcdc3e5..e06de45 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -117,7 +117,6 @@
 #define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 2a0fdf5..6b585f9 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -157,7 +157,6 @@
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index c9925ab..83b094c 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -152,7 +152,6 @@
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 139e629..a37fbe2 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -342,9 +342,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index de7d5c2..ef47e98 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -63,7 +63,6 @@
 
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 
 /*
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index a734c28..0ed44a8 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -77,7 +77,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 31348da..df3e06e 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -240,8 +240,6 @@
 #define CONFIG_SYS_LONGHELP
 
 #define CONFIG_CMDLINE_EDITING
-#define	CONFIG_SYS_HUSH_PARSER
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index a883afb..2b58830 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -260,7 +260,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING	1
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 3cc2874..6c1556a 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -208,7 +208,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 75fe558..f33c7b7 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -285,7 +285,6 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_PARTITION_UUIDS
 
 /* We set the max number of command args high to avoid HUSH bugs. */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 0388ffc..8b1920d 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -92,7 +92,6 @@
 #define CONFIG_VERSION_VARIABLE 	/* include version env variable */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
 
-#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser		*/
 
 #define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 018d586..fe3b714 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -148,8 +148,6 @@
 						/* Boot argument buffer size */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER			/* enable the "hush" shell */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "	/* secondary prompt string */
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_PREBOOT			"run check_flash check_env;"
 
diff --git a/include/configs/aria.h b/include/configs/aria.h
index c56a2e3..b3050df 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -326,10 +326,6 @@
 #define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
 
 #define CONFIG_CMDLINE_EDITING		1	/* command line history */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
 
 /*
  * PCI
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 828bc60..05d41ce 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -69,7 +69,6 @@
 #define CONFIG_CMD_FPGA_LOADMK
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_MCFRTC
 #undef RTC_DEBUG
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 6525b5c..c55446d 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -115,7 +115,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 5903f7c..2a5acf5 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -191,7 +191,6 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 /* Print Buffer Size */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index c826427..3d39387 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -332,7 +332,6 @@
 #define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING		1
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index d4baf48..e292632 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -183,7 +183,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 14a8436..9dda777 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -222,7 +222,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index cd91a7b..fcd1008 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -224,7 +224,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index be8cb80..9456a31 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -114,7 +114,6 @@
 /* version string, parser, etc */
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 344f89d..efc5de5 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -72,7 +72,6 @@
 /* version string, parser, etc */
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_SYS_LONGHELP
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index 658b16d..4563c54 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -133,7 +133,6 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index e6b2d4d..d5d4ded 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -200,7 +200,6 @@
 #define CONFIG_LOADADDR        0xc0700000
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 3910b46..016e752 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -217,7 +217,6 @@
 #define CONFIG_TIMESTAMP
 #define CONFIG_SYS_AUTOLOAD		"no"
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index d8a29f0..ca0b47e 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -226,7 +226,6 @@
 #define CONFIG_TIMESTAMP
 #define CONFIG_SYS_AUTOLOAD		"no"
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index e8851e7..edd0329 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -95,14 +95,9 @@
 #define	CONFIG_BOOTP_HOSTNAME
 #endif
 
-/*
- * HUSH Shell Configuration
- */
-#define	CONFIG_SYS_HUSH_PARSER		1
-
 #undef	CONFIG_SYS_LONGHELP		/* Saves 10 KB */
 #undef CONFIG_SYS_PROMPT
-#ifdef	CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_HUSH_PARSER
 #define	CONFIG_SYS_PROMPT		"$ "
 #else
 #endif
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index f79c58a..70e970f 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -166,8 +166,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #undef CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index fa64a1e..3f03978 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -365,7 +365,6 @@
  * Command line configuration.
  */
 #ifndef CONFIG_TRAILBLAZER
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index d30d7ff..c937957 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -341,9 +341,6 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index a525555..6ef6a7d 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -152,7 +152,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index b4bf350..1691cea 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -227,10 +227,6 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 24e55e8..3e84cbc 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -265,7 +265,6 @@
 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 0041ab9..db3759f 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -387,7 +387,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE	1
 #define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_LOOPW		1
 #define CONFIG_MX_CYCLIC	1
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
index 80f7a1e..85a2594 100644
--- a/include/configs/dns325.h
+++ b/include/configs/dns325.h
@@ -80,11 +80,6 @@
 #define CONFIG_KIRKWOOD_GPIO
 
 /*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
  * Console configuration
  */
 #define CONFIG_CONSOLE_MUX
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 10b30c1..85db470 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -128,7 +128,6 @@
 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 7bc58dc..0645d34 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -34,8 +34,6 @@
 #define CONFIG_BOOTARGS		"root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
 #define CONFIG_BOOTFILE		"edb93xx.img"
 
-#define CONFIG_SYS_HUSH_PARSER		1
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 
 #define CONFIG_SYS_LDSCRIPT	"board/cirrus/edb93xx/u-boot.lds"
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 1dfa721..d622ef8 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -235,9 +235,6 @@
 #define CONFIG_SYS_RESET_ADDRESS	0xffff0000
 #define CONFIG_SYS_MAXARGS		16
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* Enable command line editing */
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 23a2935..0606194 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -235,7 +235,6 @@
 #endif
 
 /* Misc. u-boot settings */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + 16 \
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 15905b9..df75152 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -110,7 +110,6 @@
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index fbdfdf0..c45a92b 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -260,8 +260,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_AUTO_COMPLETE
 
 /* Print Buffer Size */
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 274175b..8cde96a 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -99,7 +99,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 47c3573..3e81f0d 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -66,7 +66,6 @@
 	"echo"
 
 #undef	CONFIG_BOOTARGS
-/*#define CONFIG_SYS_HUSH_PARSER 0*/
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 0a5292e..e06e261 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -61,7 +61,6 @@
 	"echo"
 
 #undef	CONFIG_BOOTARGS
-/*#define CONFIG_SYS_HUSH_PARSER 0*/
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index fe0211a..0bdb570 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -121,8 +121,6 @@
 #define CONFIG_INITRD_TAG
 
 /* Monitor Command Prompt */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"$ "
 
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		256
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 0851626..ce4a006 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -140,7 +140,6 @@
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index c984613..75496d7 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -310,9 +310,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* Pass open firmware flat tree */
 
 /* I2C */
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index de51d10..17e1f05 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -472,8 +472,6 @@
 					 + sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #define CONFIG_SYS_MEMTEST_START	0x00001000
 #define CONFIG_SYS_MEMTEST_END		0x00C00000
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 43d2c3d..4cd889b 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -13,7 +13,6 @@
 #define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
 #define CONFIG_SYS_LOAD_ADDR		0x7fc0	/* default load address */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 3c4a70c..4f0aa69 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -212,7 +212,6 @@
 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index b494683..09f308f 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -239,7 +239,6 @@
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 6cbafdd..1087902 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -156,7 +156,6 @@
 #define CONFIG_AUTO_COMPLETE
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_CBSIZE	512
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 5edc8f6..ab727aa 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -33,7 +33,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	  */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index d981951..44829e8 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -255,9 +255,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 
 #define CONFIG_SYS_I2C
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 842169d..12fef29 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -165,11 +165,6 @@
 #define CONFIG_CMD_FAT
 
 /*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
  * Console configuration
  */
 #define CONFIG_CONSOLE_MUX
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index b6d4a79..ee458d3 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -155,7 +155,6 @@
 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 62cf6e5..134cb08 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -605,8 +605,6 @@ unsigned long get_board_ddr_clk(void);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index b2e431a..4654f67 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -450,8 +450,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e900c50..8aa557f 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -273,8 +273,6 @@
 #define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING		1
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 7c19122..7b79295 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -407,8 +407,6 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_PBSIZE		\
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 57e2a29..aee8e5e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -267,8 +267,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING		1
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 8fb0135..f9ada1a 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -39,7 +39,6 @@
 #define CONFIG_KIRKWOOD_GPIO
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 
@@ -83,7 +82,6 @@
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
 
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  *  Environment variables configurations
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 648e189..ebc0f8b 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -429,7 +429,6 @@
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index dc85768..5763ae3 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -86,7 +86,6 @@
 #define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
 #define CONFIG_AUTO_COMPLETE			/* Command auto complete */
 #define CONFIG_CMDLINE_EDITING			/* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Serial Driver
diff --git a/include/configs/malta.h b/include/configs/malta.h
index aecc8ce..7f93b94 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -68,7 +68,6 @@
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS		16
 
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 9a4f638..6bd6933 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -263,7 +263,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index e561026..61a4a8e 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -244,10 +244,6 @@
 
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
 
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 88fb3e8..76b2e1d 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -185,7 +185,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index f4d5dbc..53907f9 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -73,8 +73,6 @@
 #undef CONFIG_BOOTARGS
 
 #define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
-#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h
index 0d70e83..f06ca9c 100644
--- a/include/configs/mpc5121-common.h
+++ b/include/configs/mpc5121-common.h
@@ -29,7 +29,5 @@
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 #define CONFIG_CMDLINE_EDITING		1	/* command line history */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
 
 #endif /* __MPC5121_COMMON_H */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 4ac291c..1b2e029 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -291,10 +291,6 @@
 #define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
 
 /*
  * Clocks in use
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 1bab9ab..bf7f745 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -302,9 +302,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 6dbeeca..a85855d 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -224,7 +224,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 
 #define CONFIG_SYS_MAXARGS	       16
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 1177b0a..f7a050e 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -133,7 +133,6 @@
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 31cd5bb..125d25d 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -213,7 +213,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 22e1b68..033a542 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -184,7 +184,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index fca567d..a41c778 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -131,7 +131,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index cfb3ae3..7f9e3b4 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -178,7 +178,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 33d2163..e851da2 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -118,7 +118,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 3abc773..c6996e2 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -81,7 +81,6 @@
 /* Miscellaneous configurable options */
 #undef CONFIG_CMD_IMLS
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	512
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 9bd6114..05c5281 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -54,7 +54,6 @@
 /* Miscellaneous configurable options */
 #undef CONFIG_CMD_IMLS
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		512
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index a4ffe75..0882d5d 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -97,8 +97,6 @@
 #define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
 #define CONFIG_AUTO_COMPLETE			/* Command auto complete */
 #define CONFIG_CMDLINE_EDITING			/* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /* Booting Linux */
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index 36a00d3..d4bea63 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -54,8 +54,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 5c41405..7a1ce3c 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -393,8 +393,6 @@ int rx51_kp_getc(struct stdio_dev *sdev);
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 4ffab8a..724c33d 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -293,7 +293,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 996f772..c831f36 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -41,7 +41,6 @@
  * ----------------------------------------------------------------------------
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 
 /* Display CPU and Board information */
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index fc7bfce..a4b26d2 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -190,8 +190,6 @@
 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 799521e..15b8164 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -662,9 +662,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 1e49ee6..732b36f 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -225,12 +225,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 4e29cf3..edc555f 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -213,8 +213,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index b2ba6fc..54ebcba 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -160,7 +160,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index ede0ee1..53fdaa7 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -155,7 +155,6 @@
 #define CONFIG_SYS_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING		1
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 5a043d5..a9ecf6a 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -85,7 +85,6 @@
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
 
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		256
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 070b5de..8258bfe 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -87,7 +87,6 @@
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
 
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		256
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 293684e..5542352 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -113,10 +113,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 8520423..916895a 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -195,7 +195,6 @@
 	"dfu_alt_info=" CONFIG_DFU_ALT "\0"
 
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 2dd7fc0..d489b1d 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -65,7 +65,6 @@
 #define CONFIG_MALLOC_F_ADDR		0x0010000
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
 
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* #undef to save memory */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CONFIG_SILENT_CONSOLE
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index b74a268..05ddb3a 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -279,8 +279,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 56c197c..2c074a1 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -416,9 +416,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /*
  * I2C
  */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index b7238fb..e3c1250 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -257,11 +257,6 @@
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
 /*
  * I2C
  */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 16f697d..481b89d 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -26,8 +26,6 @@
 #define CONFIG_ENV_SIZE			(0x2000)
 #define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_NO_FLASH
 #ifdef CONFIG_SIEMENS_MACH_TYPE
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 42ed098..b1760cc 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -56,8 +56,6 @@
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMARTWEB
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_ENV_OVERWRITE    1 /* Overwrite ethaddr / serial# */
-#define CONFIG_SYS_HUSH_PARSER    /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_AUTOLOAD "yes"
 #define CONFIG_RESET_TO_RETRY
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 9947dc0..34858cd 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -83,7 +83,6 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_USB
 
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_CMDLINE_EDITING
 
 /* autoboot */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index d52f500..e1c7c67 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -152,7 +152,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index a708c68..3674e91 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -140,7 +140,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /* U-Boot memory settings */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 2d82a66..2785925 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -169,7 +169,6 @@
 #define CONFIG_AUTO_COMPLETE
 
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_CBSIZE	512
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0c94bac..2b65241 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -68,7 +68,6 @@
 #define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
 #define CONFIG_AUTO_COMPLETE			/* Command auto complete */
 #define CONFIG_CMDLINE_EDITING			/* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
 
 #ifndef CONFIG_SYS_HOSTNAME
 #define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 62be008..60f8291 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -207,7 +207,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
 
 
 /*
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 05e2363..00f293a 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -89,7 +89,6 @@
  * Command line configuration.
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index e94812b..1511959 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -75,7 +75,6 @@
  * Command line configuration.
  */
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/strider.h b/include/configs/strider.h
index d5f1981..ec5fbe9 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -313,9 +313,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 /* Pass open firmware flat tree */
 
 /* I2C */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index ca6d285..0eed861 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -153,10 +153,6 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 59b6c5f..1426fbf 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -133,7 +133,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 73cd0a0..ee9fc7d 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -192,7 +192,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 
 /* turn on command-line edit/hist/auto */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 5864f27..4f1a5f3 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -79,8 +79,6 @@
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PREBOOT
 
-#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser	*/
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /* Keep device tree and initrd in lower memory so the kernel can access them */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 46d91e2..fc16678 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -99,7 +99,6 @@
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING		1
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index f00072e..9897a0b 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -29,7 +29,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* Use HUSH for command parsing */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_MACH_TYPE		MACH_TYPE_TI8148EVM
 
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index e09efc7..b5216a8 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -25,7 +25,6 @@
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (32 * 1024))
 #define CONFIG_SYS_LONGHELP		/* undef save memory */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 787d04a..d866690 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -138,7 +138,6 @@
 #else
 #define CONFIG_SYS_MALLOC_LEN	(16 << 20)
 #endif
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_ENV_VARS_UBOOT_CONFIG	/* Strongly encouraged */
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 915cbd8..73f0d84 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -279,7 +279,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_CMDLINE_EDITING		/* enable cmdline history */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index fcc9d80..8f3963a 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -135,7 +135,6 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 7b2f1ca..296ddcd 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -144,7 +144,6 @@
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP
 
 /*
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index de5c3ce..359239c 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -256,9 +256,6 @@
 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
 #if defined(CONFIG_PCI)
 /*
  * General PCI
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 31b1a24..d066a5a 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -276,7 +276,6 @@
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index d78ca0b..501b143 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -284,7 +284,6 @@
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 0809fbb..65830b7 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -224,8 +224,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #undef CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 7433d7e..7a7c92b 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -212,8 +212,6 @@
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index caa0434..4407557 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -132,7 +132,6 @@
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index e9127c3..a35876f 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -110,7 +110,6 @@
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/x600.h b/include/configs/x600.h
index ac477eb..9a8a7c7 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -133,8 +133,6 @@
 
 #define CONFIG_BOOTDELAY			3
 
-#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser	*/
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * U-Boot Environment placing definitions.
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index ea815c2..a596edd 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -69,7 +69,6 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SUPPORT_VFAT
 
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index 831b940..5980acb 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -69,7 +69,6 @@
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE		/* include version env variable */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
-#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser          */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download  */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change        */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 6f162dc..4f6084a 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -108,11 +108,6 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
  * NOR flash configuration
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	3
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 70af1e1..18e342a 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -226,11 +226,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 1972373..7284aa2 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -189,11 +189,6 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 1be043f..bdeee47 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -225,11 +225,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
  * I2C
  */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 0697714..0948035 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -215,11 +215,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-/*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
 #define CONFIG_FDT_FIXUP_PCI_IRQ	1
 
 /*
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 46836d5..8bb48a8 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -98,11 +98,6 @@ unsigned char zipitz2_spi_read(void);
 #endif
 #endif
 
-/*
- * HUSH Shell Configuration
- */
-#define	CONFIG_SYS_HUSH_PARSER		1
-
 #define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
 #define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
 #define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index bd8fdfb..3a401f7 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -86,7 +86,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB
 
-#define CONFIG_SYS_HUSH_PARSER
 
 /*
  * USB
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 23b1b2d..d535316 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -252,7 +252,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-- 
cgit v0.10.2


From 4d7100a61d6fe0652dd0e8b7b3cc31ad37483d64 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 22 Apr 2016 14:01:08 -0400
Subject: configs: Re-sync CONFIG_USB_MUSB_HOST

Now that CONFIG_USB_MUSB_HOST is part of Kconfig, migrate that over to
the defconfig files.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 51cabb4..0ddf061 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 7e0dcf5..79e469d 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index e5daa94..89aba13 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -26,6 +26,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index d40a9e6..e21d98e 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index aebfb58..67a048e 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index bc4f667..332f37f 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 346def4..4b30503 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index c457f6f..7ed400b 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 554af51..9859189 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index b9edf0d..1e0b35a 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -13,4 +13,6 @@ CONFIG_SYS_PROMPT="AM3517_EVM # "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 1e22f5c..5d1c0dc 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -13,6 +13,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index c024d03..a4aa6d9 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -13,6 +13,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index ea3e492..80a7c34 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -9,4 +9,6 @@ CONFIG_SYS_PROMPT="CM-T3517 # "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index abbc636..1b3aea5 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index ee729b1..c97faf0 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 632e764..63ef0bb 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index d04471b..4aead9e 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -8,6 +8,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 95ab0a3..cd8996a 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -15,6 +15,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index c6a1130..a3d2b86 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index d7b47e2..7526426 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -15,6 +15,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index c051460..c81e411 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 1b1684d..55f8dc5 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -287,7 +287,6 @@
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
@@ -337,7 +336,6 @@
 #define CONFIG_ENV_IS_NOWHERE
 #undef CONFIG_ENV_IS_IN_NAND
 /* disable host part of MUSB in SPL */
-#undef CONFIG_USB_MUSB_HOST
 /* disable EFI partitions and partition UUID support */
 #undef CONFIG_PARTITION_UUIDS
 #undef CONFIG_EFI_PARTITION
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index f33c7b7..45f016a 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -94,7 +94,6 @@
  * Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
  */
 #define CONFIG_USB_MUSB_AM35X
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_USB_MUSB_PIO_ONLY
 
 #ifdef CONFIG_USB_MUSB_AM35X
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 48d0613..23d0bb7 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -273,7 +273,6 @@
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_HOST
 #define CONFIG_AM335X_USB1
@@ -292,7 +291,6 @@
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
 /* disable host part of MUSB in SPL */
-#undef CONFIG_USB_MUSB_HOST
 /* disable EFI partitions and partition UUID support */
 #undef CONFIG_PARTITION_UUIDS
 #undef CONFIG_EFI_PARTITION
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 2c0ec9d..44ac2da 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -438,7 +438,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
@@ -469,7 +468,6 @@ DEFAULT_LINUX_BOOT_ENV \
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
 /* disable host part of MUSB in SPL */
-#undef CONFIG_USB_MUSB_HOST
 /* disable EFI partitions and partition UUID support */
 #undef CONFIG_PARTITION_UUIDS
 #undef CONFIG_EFI_PARTITION
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index ca0b47e..553b648 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -113,7 +113,6 @@
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
 #else /* !CONFIG_USB_MUSB_AM35X */
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_USB_MUSB_PIO_ONLY
 #endif /* CONFIG_USB_MUSB_AM35X */
 
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 3e66c19..4638c25 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -142,7 +142,6 @@
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 8977115..b75dbee 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -198,7 +198,6 @@
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_MUSB_HOST
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
 #define CONFIG_AM335X_USB1
@@ -211,7 +210,6 @@
 
 #if defined(CONFIG_SPL_BUILD)
 /* disable host part of MUSB in SPL */
-#undef CONFIG_USB_MUSB_HOST
 /* Disable CPSW SPL support so we fit within the 101KiB limit. */
 #undef CONFIG_SPL_ETH_SUPPORT
 #endif
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 481b89d..6af373e 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -222,7 +222,6 @@
 #define CONFIG_USB_MUSB_PIO_ONLY
 #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
 #undef CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_MUSB_HOST
 
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
-- 
cgit v0.10.2


From 78d1e1d0a157c8b48ea19be6170b992745d30f38 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 22 Apr 2016 16:41:25 -0400
Subject: configs: Re-sync almost all of cmd/Kconfig

This syncs up the current cmd/Kconfig and include/configs/ files with the
only exception being CMD_NAND.  Due to how we have used this historically
we need to take further care here when converting.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
index 3c07160..fd51531 100644
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -30,7 +30,6 @@
 #define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 
 #endif /* __ARCH_CONFIGS_H */
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index d2cf71b..3d98a00 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -138,9 +138,6 @@
 #ifndef CONFIG_SYS_BOOTM_LEN
 # define CONFIG_SYS_BOOTM_LEN 0x4000000
 #endif
-#ifndef CONFIG_SYS_PROMPT
-# define CONFIG_SYS_PROMPT "bfin> "
-#endif
 #ifndef CONFIG_SYS_CBSIZE
 # define CONFIG_SYS_CBSIZE 1024
 #elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 8703cdb..f4ec023 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -343,7 +343,7 @@ config CMD_FLASH
 	    protect - enable or disable FLASH write protection
 
 config CMD_ARMFLASH
-	depends on FLASH_CFI_DRIVER
+	#depends on FLASH_CFI_DRIVER
 	bool "armflash"
 	help
 	  ARM Ltd reference designs flash partition access
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index f034f1f..b4d7d84 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -12,7 +12,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 6679b04..7baff24 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -13,6 +13,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index be6ff9f..e03d9a8 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -17,6 +17,9 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 1934cf8..1ac88a4 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -19,7 +19,10 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 5d6da22..7a1f2a8 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -12,7 +12,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 58748a7..3093395 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -10,7 +10,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index e01d722..da76a97 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -13,6 +13,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index e19f872..7c9150e 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -15,7 +15,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 486baed..3ff15f8 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -17,5 +17,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index ce34985..e68e747 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -19,5 +19,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index bea5100..1b3d01d 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -11,6 +11,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 6f0362f..8edb572 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -9,6 +9,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index d9804d7..bcffc47 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 66da74e..6208567 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index 1b97a6a..300461b 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index ff76dae..f7ff204 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index d26fe6e..75cf823 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index b0faa7f..e9c045e 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index a63686c..b7ebc98 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index a29ab17..3420443 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index f8ccf4a..fdf4954 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -10,6 +10,11 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index b30132e..7c3683a 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -10,6 +10,11 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 7b5cea5..831e024 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index 9258040..c365a45 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index db01bbb..f766e05 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index c59d2e5..100f1bf 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index e5364bf..433b62d 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 3688646..2eb85d1 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index 3b75bb4..f0bb1cd 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index 822c14b..f521407 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 53e5626..2708794 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index bd8cf10..df67271 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 23d7138..072c2e5 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index 27dda3a..f3d96b3 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index f3febf6..231dab0 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index ecd0ddb..c775caa 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index 91cadef..2fb85e9 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index 9b612f8..89f7aa5 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 0eb8f15..43ccad1 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index a40bd6c..09421e0 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 054d7ce..f7db498 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -11,7 +11,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index b3b36ac..74c7446 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -13,7 +13,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO4_VOLT=2500
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index 6b455b1..d342640 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -9,6 +9,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 93eea63..5bedcb4 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -8,6 +8,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index 5bf96b8..f74c103 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -8,6 +8,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index 3597dbb..541ae65 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 7c6f233..7c50ea9 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 0e72d2c..4ef1840 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -10,6 +10,9 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig
index 1c821ba..ea0775d 100644
--- a/configs/CPCI2DP_defconfig
+++ b/configs/CPCI2DP_defconfig
@@ -1,6 +1,8 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CPCI2DP=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig
index 49810ff..c00ca1f 100644
--- a/configs/CPCI4052_defconfig
+++ b/configs/CPCI4052_defconfig
@@ -5,6 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index d0a2bd2..a0ed7a0 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -12,6 +12,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 393f337..ec30918 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -17,7 +17,10 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 85322d4..078243e 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -21,7 +21,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 26c770c..0a1f6cd 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 22372ef..3f3f812 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -10,5 +10,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index ea7cc0c..9eff740 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -15,7 +15,10 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 608ee14..5a15a58 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -18,7 +18,10 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index a7c8897..b60c569 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -9,6 +9,10 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 2618a72..0d86a8f 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -9,6 +9,10 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 12f74df..7daafb8 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -20,5 +20,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index cbe8341..5b221c3 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -14,6 +14,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 883edd9..b9f7f0e 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -18,5 +18,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 2209cbf..3959bae 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 96a876c..f6cae6b 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -11,6 +11,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUN
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 718aba5..69a082c 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -12,6 +12,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 0e95c76..8eeff7b 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 9af4db9..4a09f29 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -10,5 +10,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 7a12522..55841e6 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -3,3 +3,4 @@ CONFIG_TARGET_M5208EVBE=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index 711a411..d3519dd 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -3,6 +3,9 @@ CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index 05d20d6..b978c02 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -2,6 +2,9 @@ CONFIG_M68K=y
 CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_TEXT_BASE=0x43E00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index b8fb413..6bbacf3 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -4,4 +4,7 @@ CONFIG_SYS_TEXT_BASE=0xFFC00000
 CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index fdf2dd0..979d78c 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -4,4 +4,7 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index 2358d24..9bc8da9 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -1,5 +1,6 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5249EVB=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index c4da196..8c4678b 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -2,3 +2,4 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5253DEMO=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 6153a5c..efcadd6 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index d70fea1..dec9e63 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -4,4 +4,7 @@ CONFIG_SYS_TEXT_BASE=0xffe00000
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 10a3043..7aa36d9 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index e86fe5b..c63acd9 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -3,3 +3,4 @@ CONFIG_TARGET_M53017EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 2379a1e..51d0ba2 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_M5329EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 38a996b..cb79dbd 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_M5329EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 6595feb..52175cf 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_M5373EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index 19f8983..fac2fda 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index bc6f63a..a013ac8 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index a42f603..c29618c 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index a6c595d..522a150 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index bdfa3b4..2301738 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index 19f8983..fac2fda 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index a9fe02f..36fa4ea 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -5,6 +5,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index f10e86c..e526b46 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x47e00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
index 3053514..c8ba38c 100644
--- a/configs/M54455EVB_a66_defconfig
+++ b/configs/M54455EVB_a66_defconfig
@@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x04000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index 9f70f7e..e362886 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -5,6 +5,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
index 8421393..714c080 100644
--- a/configs/M54455EVB_i66_defconfig
+++ b/configs/M54455EVB_i66_defconfig
@@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
index c630108..e17382e 100644
--- a/configs/M54455EVB_intel_defconfig
+++ b/configs/M54455EVB_intel_defconfig
@@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index 4e8aee4..ce2dd81 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -4,6 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x4FE00000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index edfb9fc..2131e0e 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index 5177eb9..ead78c8 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index 431a264..04a31fd 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index 46d9964..242acc8 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index 4a2284d..3641a55 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index f8d53be..c0d1c5e 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index 61a3c56..57c5770 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index a8afe71..917d4bd 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index b9bdd4b..1dc119a 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index c5ec396..73c4d8a 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index 6872865..46ea740 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index c0d1e06..f2ae822 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index 904a639..f2b3f62 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index cb6f2c7..83f39b02 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index a3ef210..2e5bda4 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
 CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig
index 641fa06..c2bc17c 100644
--- a/configs/MIP405T_defconfig
+++ b/configs/MIP405T_defconfig
@@ -3,5 +3,8 @@ CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
 CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig
index 2250011..c243de8 100644
--- a/configs/MIP405_defconfig
+++ b/configs/MIP405_defconfig
@@ -2,5 +2,9 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index a363004..f8bf52a 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -8,5 +8,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 546e7c7..0ae4c7f 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -6,6 +6,9 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index ca1cfcd..96c9d54 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -5,7 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 9d4db2a..1d004fe 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -5,7 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 0df5e8b..893657e 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -6,7 +6,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index 8913a18..cb3c686 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -6,7 +6,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index f6d7c0f..97e7672 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_MPC8315ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index 3d13b8f..7f6156c 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_MPC8323ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index e573e0d..759165d 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index c32e0e9..08f1a41 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 2247e38..43d121c 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index a4b4257..079d017 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index efc6555..cf38f89 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index ab992fc..988e33a 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_MPC8349EMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 64a8241..2506e77 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -6,6 +6,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 61f9e79..80eb01b 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -6,6 +6,10 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 90a0df5..4c8cfce 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -6,6 +6,10 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index eb1a597..b459a40 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -5,6 +5,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index 99ff225..687fcfa 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index f0bd789..a1982e5 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_MPC837XERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index 957c102..c70ec54 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -5,6 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index 2eb8873..4343d40 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -5,6 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index b551c80..003099d 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -5,6 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index 60b944b..a746dbe 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -4,6 +4,10 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
index 6efbbc5..401a86d 100644
--- a/configs/MPC8540ADS_defconfig
+++ b/configs/MPC8540ADS_defconfig
@@ -4,5 +4,7 @@ CONFIG_TARGET_MPC8540ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index dde5a24..4e8b93d 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -4,5 +4,7 @@ CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index 1ab88f6..1c2316f 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -5,5 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index fd64677..83c0191 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_MPC8544DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_RTL8139=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 5bdf2cc..06edf18 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 00595c4..3b89bda 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index a95ea81..21819a3 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index e4ab923..e2de2a2 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -4,5 +4,7 @@ CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index 12364d1..d09370e 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -5,5 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig
index 11100c3..19407b3 100644
--- a/configs/MPC8560ADS_defconfig
+++ b/configs/MPC8560ADS_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_MPC8560ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 7d4b01c..142d8bf 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -4,5 +4,7 @@ CONFIG_TARGET_MPC8568MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index 597dad7..8968ee8 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="ATM"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index adcbf49..efbb008 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index 9dc690f..b2c5a70 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 76b9d25..c55289a 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -6,6 +6,9 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index 2b4cc3a..38e2034 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_MPC8610HPCD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index e1fb77f..b8dede6 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -5,6 +5,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index 9b2a697..98bf168 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 2f4e024..d335173 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -13,4 +13,7 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 7cf7b9d..3169c92 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -17,6 +17,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 041baab..626fb4c 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -8,6 +8,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index e49be8a..2665a64 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -12,6 +12,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 3dab55c..b8c8f78 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -10,5 +10,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 0d1c90e..82d91da 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -12,6 +12,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index fb88d94..ba59216 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -13,6 +13,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 1db614f..725554d 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -12,6 +12,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 7291022..8d298f8 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -12,6 +12,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 3003c3e..47a12a4 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -12,3 +12,5 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig
index 3255ed2..57b7db4 100644
--- a/configs/MigoR_defconfig
+++ b/configs/MigoR_defconfig
@@ -14,5 +14,6 @@ CONFIG_TARGET_MIGOR=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index bf88df6..ab2835c 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -9,6 +9,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index f393019..d9e609c 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index bc211aa..929e381 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D300=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index 210da9a..181a69e 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -7,5 +7,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="++++++++++"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index 8cbf6eb..9e45ecd 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -6,5 +6,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="++++++++++"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index f33191b..f79b3e5 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index 14b940f..b40b709 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2I=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index 6c9eeb4..9327068 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -4,5 +4,8 @@ CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index 84e4243..de360dc 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -4,5 +4,8 @@ CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index 00c516f..4425621 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -4,5 +4,8 @@ CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index 55ff0fa..b3a656a 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index 9556964..0fb75c5 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O3DNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 6f502db..3631181 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -14,6 +14,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index c07d25e..9734edf 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -16,6 +16,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index d91e4d3..c959a2e 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 6af298f..6c8bcfd 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 72dac9f..6338a08 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index b0410b0..d084188 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 14b9511..2de562f 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 1036eb4..148748d 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index ac8ca85..acf03c6 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index e668725..788fe9e 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index f99039d..d6138f9 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index 8af53af..b0df9d2 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 01ae04c..fd8508a 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index cb50efb..4e047f7 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index f536056..3a74a15 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 540dc07..8a124ef 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 0f3d4bc..94c5b29 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 8777721..1e7e5c3 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index ee28938..a6efbba 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 3518769..4971dcb 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 1aa52d0..f86a05b 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 76d1191..b02b1d3 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 0be70bf..1bfba42 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index cd7fd1a..75b064f 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 216f9c60..259c443 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index dbe5ac5..11bc5e3 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 47799fa..b26fbcb 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index d65c724..2c88ee8 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 3712bc2..80f1daf 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index ab7e97f..f79e913 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index b3b21c2..553e5da 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index 540c7ec..a93663f 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index b3fa9d4..9c3a6f7 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -8,6 +8,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index f079220..9133731 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 42021ce..d22bac7 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index be8cdd6..e046e40 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 2d94d7b..dc6d861 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 6d04758..a486593 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 3d6e980..cc2a569 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index d118293..a7c00df 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 526e65a..08286f7 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 450dbd5..6a8bc3c 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 5a3d66e..23e05d5 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 8fcbccf..872a247 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 77b4b6e..82a318e 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index a0e5bc3..f5e8a1b 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index 6d2c02f..442d43a 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 26b7697..0f4519c 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index b79b65a..93fe60c 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -8,6 +8,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 6f8615a..6118f0f 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index 059f9f2..108b467 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index e54d751..b17a3a0 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index e331a8d..83027ad 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index 6d83700..1d76a55 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 03795da..622ed59 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 01fb7ff..72d5835 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 80dcc12..2fff1ab 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index 3d339e0..341f905 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index 3f4f413..a57882f 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 3cdbb8d..edb6476 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index bf4b56e..c54094e 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index c94b53b..6b6811d 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index 98f2c03..c7e2cfd 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index b08b27a..7e321a4 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index 5ec0151..4f68c00 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index f444513..2b1925f 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -6,6 +6,10 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index 32871bb..cc31300 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -6,6 +6,9 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index bfd47ee..13546c3 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index 4ca3893..b80d2d9 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index d63a6dc..5250e16 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index dc3cdc9..2ba4ceb 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 312e2e2..4feecb5 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index a3adca6..6e5b913 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index c394d41..cef9432 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 7bd725e..0949ae1 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 56e4d87..35fbc67 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index 56f0b65..b1afcc0 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 4edf2e3..19dee97 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index c3d47fc..a48bdb9 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index a700fcd..abcb328 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 1fb4331..ec3d1e2 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index fc63360..9faa181 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -9,6 +9,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 1c6e99f..d463d9d 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index f14e444..f8f3f14 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -8,6 +8,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index eccf03a..84338ce 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -7,6 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index ec04df9..8e3df02 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 02b94e9..02401e6 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 890e100..568e44d 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 9553ab5..85c45f2 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index 1eb8835..db34b71 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 887ff28..91da52a 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -6,6 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index 4684fc9..16b8770 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index c238729..aed8b9c 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index a7995c3..e8910b9 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index f3037ea..6abde1b 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 9bbce6e..ed37b05 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index 7499ff8..6882a6d 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 291c3d1..e8fa833 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -6,6 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index febb822..e3f6724 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 66dea95..eb89714 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 4774147..c8eb351 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index 3aebc39..23353c7 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index aec0624..3a2e976 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -6,6 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 99b3932..c2112fa 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index f70a45c..61b4f21 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index 448b489..c823f05 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 298ee59..d220264 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 8ac8a9e..df41373 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index abbe15d..b831253 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index 5c272bb..8efb577 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -6,6 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 84df506..fd3ccfa 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 1a91eca..068cb68 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 72629a4..c3149d8 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 79b9f62..4828534 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index f71423d..1793865 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 2f2628e..ed72c24 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -6,6 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig
index 2bac731..c9fb9d4 100644
--- a/configs/PIP405_defconfig
+++ b/configs/PIP405_defconfig
@@ -2,5 +2,9 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PIP405=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig
index 52850dd..9fe4dc4 100644
--- a/configs/PLU405_defconfig
+++ b/configs/PLU405_defconfig
@@ -5,6 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig
index 1155bd1..ccbd7b3 100644
--- a/configs/PMC405DE_defconfig
+++ b/configs/PMC405DE_defconfig
@@ -5,6 +5,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig
index 156d813..f80410f 100644
--- a/configs/PMC440_defconfig
+++ b/configs/PMC440_defconfig
@@ -5,6 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 02fa5e4..2fdb844 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -16,6 +16,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index ce1a70e..011dfd6 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -10,3 +10,5 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index 174de08..b39164b 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -12,6 +12,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 4b69996..878d22f 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -19,6 +19,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 48511ec..0957dc3 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -9,7 +9,13 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index aabd1a3..f9dd7db 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -9,7 +9,13 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 16b3066..9577fe2 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 4b7ad52..e0b3ae1 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -9,7 +9,13 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index d79763a..ec0609f 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -7,6 +7,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index f15855b..ef01c2e 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index dac71a9..f3235bf 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 5adfe02..2be1046 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 7748356..1bca42a 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index 447283b..b22bba8 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 3c68c9f..a9bea77 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index 9a1d324..622e560 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 5f34727..ecd027f 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 474ae53..77e93b4 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 1eba789..68ac112 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index c4918a7..3443db8 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 9878b65..d11b954 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -7,6 +7,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index b27dd6c..3fb702d 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index 67cdc3a..acfa55f 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 3c7296d..777c448 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 94aea4f..c1e16b2 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index d5513f5..3d1040e 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 5d54cb5..8399ec8 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index fb37784..a7998bb 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 5d02f71..9c21b33 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 6512dad..6ed2f86 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index a878194..10dfd33 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 9570b7b..b9bb5be 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index 82e8f0f..f33805b 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index fa6bbfc..8dcf3e5 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 9c09bf0..4620e54 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 2b8f5de..54ffb94 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 906b243..0ca5bb0 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 1025ce4..ba4b274 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 0ad874a..488923e 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index a37117f..3a52ea9 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index 4d5ca01..c3d7cf6 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 0de0b4c..0b608a9 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index 99cdd37..aa66095 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 41ad0e2..dbb5bb6 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index cedd085..09b5bf5 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 9025458..51d452b 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 572da36..33da1b4 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index a2d3df4..ba7f61d 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index b4bd589..c1c7e42 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 75c7860..6753118 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index dd2343d..36dc163 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 8f7e7ee..147ce69 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 325dbfa..ebbb9e1 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index 261e027..d57cc6d 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index b7287b0..8bac4a0 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -8,6 +8,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index e72878d..ad5ce54 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -8,7 +8,13 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index abe0d2b..20ccc45 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -7,6 +7,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 16b38ec..1589d31 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index cd25ea9..fa04188 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 63cfc78..0100ad9 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index 5048d46..17e95d2 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index d73d8f2..ce8453f 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 27c4543..20fd55a 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index a283293..cc056d5 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 80c3318..4483184 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 015f85d..b4533ab 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index d0979b1..5a90b2b 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index c8e3a9b..423f4ed 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 30cbeb9..eceac1a 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 6e19e3a..dde4f56 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index 4c8932c..eea72e3 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -9,6 +9,11 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index e374328..1c38761 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index b8589b6..2c1847f 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -8,6 +8,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index c622fa6..9af072d 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -7,6 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index 71b4592..1269e39 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index 960cc3c..d8a724a 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index 14afa02..abecdb4 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index c49fc53..86e8572 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index fcd8b35..7592cc5 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index bb04df5..90821b3 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -3,5 +3,11 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index 285e773..b60d087 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -5,4 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 5148764..28ad9e1 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index 8f6b674..c569b24 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM823M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index af4a72d..f8d9df8 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -4,6 +4,10 @@ CONFIG_TARGET_TQM834X=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 646c552..9e71d16 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM850L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index 63941ac..77a9a6c 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM850M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index 869a7d3..4d443c5 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM855L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index 8022398..344da70 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM855M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index 7b24eeb..6c47c3e 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM860L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index 672ad4c..2a65fd9 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM860M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index af57396..e20def2 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM862L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index cd76e95..61a993f 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM862M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index 403ec90..e3ca7c7 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -4,4 +4,6 @@ CONFIG_TARGET_TQM866M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index f9d8610..5b8b869 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -3,5 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM885D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index a58e0aa..2c823db 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -5,4 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 31db63d..40d22fb 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -7,6 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
index f2b833d..d532e5f 100644
--- a/configs/UCP1020_SPIFLASH_defconfig
+++ b/configs/UCP1020_SPIFLASH_defconfig
@@ -10,7 +10,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b"
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index c94c3b7..3472c07 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -10,7 +10,13 @@ CONFIG_SYS_PROMPT="B$ "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b"
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index bf17a63..bad17c3 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -23,6 +23,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
index 0996af0..8bf5717 100644
--- a/configs/VCMA9_defconfig
+++ b/configs/VCMA9_defconfig
@@ -2,4 +2,8 @@ CONFIG_ARM=y
 CONFIG_TARGET_VCMA9=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VCMA9 # "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig
index 045fb78..3f80c58 100644
--- a/configs/VOM405_defconfig
+++ b/configs/VOM405_defconfig
@@ -2,6 +2,9 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_VOM405=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index cdcd4eb..f25a296 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -16,6 +16,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 5d0f327..6eaa9d6 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -15,6 +15,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index cb21222..84200e8 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -10,5 +10,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 2f2c26b..3163ca8 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -22,5 +22,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index a5b215f..440fd54 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -20,5 +20,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index abc6241..b47e308 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -5,6 +5,10 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_LINK_LOCAL=y
 CONFIG_LIB_RAND=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig
index f9ac1fc..c724993 100644
--- a/configs/a4m072_defconfig
+++ b/configs/a4m072_defconfig
@@ -6,5 +6,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="asdfg"
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index 356949e..7bbecf3 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -6,6 +6,10 @@ CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_LINK_LOCAL=y
 CONFIG_LIB_RAND=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig
index 3d74576..d839fc8 100644
--- a/configs/ac14xx_defconfig
+++ b/configs/ac14xx_defconfig
@@ -4,5 +4,8 @@ CONFIG_TARGET_AC14XX=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="ac14xx> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index 4a985cc..d98ff2d 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_ACADIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 87be263..8a2f7de 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -2,4 +2,5 @@ CONFIG_NDS32=y
 CONFIG_TARGET_ADP_AG101P=y
 CONFIG_SYS_PROMPT="NDS32 # "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 4ea33ef..a23d59f 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -10,11 +10,17 @@ CONFIG_TARGET_ALT=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 0ddf061..ea6e0f9 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -10,8 +10,13 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 79e469d..7cd15dd 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -12,8 +12,14 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DFU_TFTP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 89aba13..0231eed 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -15,8 +15,14 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index e21d98e..fade82f 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -12,8 +12,14 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 67a048e..6dc4e25 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -8,8 +8,14 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 332f37f..239b607 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -5,8 +5,14 @@ CONFIG_NOR_BOOT=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 4b30503..896f060 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -8,8 +8,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 7ed400b..f6b173f 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -8,8 +8,14 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 9859189..b069e3c 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -9,8 +9,14 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index 3d0d215..424018a 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -6,7 +6,11 @@ CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 2eca61c..dbc44b1 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -8,7 +8,11 @@ CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index b9115af..b860870 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -7,8 +7,11 @@ CONFIG_SYS_PROMPT="AM3517_CRANE # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 1e0b35a..fa169fa 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -9,9 +9,13 @@ CONFIG_SYS_PROMPT="AM3517_EVM # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 742e148..d634fbd 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -10,8 +10,14 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 276d14a..66b88a1 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -12,8 +12,14 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DMA=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index aee1584..fd97124 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -5,8 +5,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index b435ea7..3065710 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -5,8 +5,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 81afd7b..e92d918 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -4,8 +4,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 218b524..f6f6375 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -5,8 +5,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 3b1fed2..608f172 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -10,8 +10,13 @@ CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 375c10c..32a94b3 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -5,7 +5,12 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 9c83849..25826ca 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -4,7 +4,9 @@ CONFIG_SYS_TEXT_BASE=0xffc00000
 CONFIG_SYS_PROMPT="amcore $ "
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_LOOPW=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIMER=y
diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig
index 8c22020..5c15b71 100644
--- a/configs/ap325rxa_defconfig
+++ b/configs/ap325rxa_defconfig
@@ -14,5 +14,6 @@ CONFIG_TARGET_AP325RXA=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig
index 51d5f9e..df7c344 100644
--- a/configs/ap_sh4a_4a_defconfig
+++ b/configs/ap_sh4a_4a_defconfig
@@ -11,10 +11,12 @@ CONFIG_TARGET_AP_SH4A_4A=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 79031d2..dcf1a3e 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -10,9 +10,13 @@ CONFIG_SYS_PROMPT="Apalis T30 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_E1000=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 5143e26..2945e91 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -5,4 +5,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="BIOS> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index 8352247..92e3046 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -4,5 +4,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index 69b0c6b..64adfd7 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -5,5 +5,9 @@ CONFIG_ARCHES=y
 CONFIG_DEFAULT_DEVICE_TREE="arches"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index 19f1c41..1c8c8a7 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_ARIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 0e16206..8a75880 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index aa3f357..623f7b8 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 9eca59a..ae5ade4 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index dc326e1..06a7630 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -17,5 +17,7 @@ CONFIG_TARGET_ARMADILLO_800EVA=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 3fe7e97..259cb22 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -9,8 +9,13 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ARNDALE # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_SOUND=y
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
index d3ac8d8..4f5df35 100644
--- a/configs/aspenite_defconfig
+++ b/configs/aspenite_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_ASPENITE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index c616eb4..118f96b 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_ASTRO_MCF5373L=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="URMEL > "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index bba7e5d..3776bda 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -3,6 +3,9 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 3868ac1..0c69da8 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index a71a21f..014cb95 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index 5884ffa..a755103 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index 9d49a1a..bb65e89 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 2bdc4a6..e196e8a 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 0f6946a..4c26cc1 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 6a5a850..34e6ff1 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 332dc73..2978f2d 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -8,7 +8,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 332dc73..2978f2d 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -8,7 +8,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index ebcb08d..6e30d94 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -8,7 +8,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 0109a17..5b35645 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -8,7 +8,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 66a6ec3..cca6b13 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -8,7 +8,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 173990e..ef1af38 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 551bfea..d5c9a98 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 505c5ed..7de00c6 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index c5d0e68..db0af22 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index b8ec67c..7bb5fd5 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 0317cae..c7b5faf 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index c87188f..4f89b50 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index 7b13e96..063284d 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 0eea74b..663433d 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 276479a..e1a1bfc 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 9c8aa32..4f429cc 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -6,8 +6,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 600a370..4b27ab3 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -7,8 +7,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 71446cf..25f5a35 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -7,8 +7,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index fce9c5e..c4a0808 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -7,8 +7,12 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index f1c6dfa..62756f6 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -7,8 +7,12 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 7e660d7..aad7e85 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -8,8 +8,12 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 8a2aadd..310de74 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -8,8 +8,12 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 57e4481..861c3ff 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index f6b585b..2b8fa1b 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index 0d1c2c3..2a1fde8 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -7,7 +7,10 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig
index 7ef4677..02f6f97 100644
--- a/configs/atngw100_defconfig
+++ b/configs/atngw100_defconfig
@@ -7,8 +7,11 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig
index b552421..b45c426 100644
--- a/configs/atngw100mkii_defconfig
+++ b/configs/atngw100mkii_defconfig
@@ -7,7 +7,10 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig
index 1b108e5..47c1a35 100644
--- a/configs/atstk1002_defconfig
+++ b/configs/atstk1002_defconfig
@@ -10,3 +10,4 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 65c13eb..fbdd4f2 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -7,9 +7,13 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 43733ac..863169a 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -13,6 +13,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index c8f39c9..de5a857 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -3,5 +3,11 @@ CONFIG_4xx=y
 CONFIG_TARGET_BAMBOO=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 30c65fa..4c03856 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -16,9 +16,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index f7de603..aaeb555 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 754499f..f693095 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index f3ec577..75fbe46 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_BCM28155_AP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index d32e533..299ffa0 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index fc78fc0..68109d8 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -5,5 +5,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index a9c1d31..6cf2186 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -5,5 +5,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index 584ce17..ec7370f 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -5,5 +5,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index 6aebcb0..b939927 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -5,5 +5,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index 584ce17..ec7370f 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -5,5 +5,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index 584ce17..ec7370f 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -5,5 +5,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index 60ad272..e149735 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -5,5 +5,6 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
index bd0acfa..c7e223a 100644
--- a/configs/bct-brettl2_defconfig
+++ b/configs/bct-brettl2_defconfig
@@ -1,6 +1,10 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BCT_BRETTL2=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index bf22c7a..f0921e8 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -10,10 +10,16 @@ CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
index a8eab8c..41f1490 100644
--- a/configs/bf518f-ezbrd_defconfig
+++ b/configs/bf518f-ezbrd_defconfig
@@ -1,7 +1,14 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF518F_EZBRD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig
index 15a8f1f..84f229f 100644
--- a/configs/bf525-ucr2_defconfig
+++ b/configs/bf525-ucr2_defconfig
@@ -2,6 +2,7 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF525_UCR2=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index a5f4b73..614a137 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -1,7 +1,15 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF526_EZBRD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
index 4751df4..793ccfe 100644
--- a/configs/bf527-ad7160-eval_defconfig
+++ b/configs/bf527-ad7160-eval_defconfig
@@ -1,6 +1,9 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_AD7160_EVAL=y
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index 356ab64..9035165 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -1,8 +1,16 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_EZKIT=y
 CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index c1b139c..0b63ece 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -1,6 +1,14 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_EZKIT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_NET_TFTP_VARS is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
index 383f62e..a15b92b 100644
--- a/configs/bf527-sdp_defconfig
+++ b/configs/bf527-sdp_defconfig
@@ -1,6 +1,9 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_SDP=y
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
index 6a39874..84def80 100644
--- a/configs/bf533-ezkit_defconfig
+++ b/configs/bf533-ezkit_defconfig
@@ -1,6 +1,11 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_EZKIT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
index e52587f..af9ebd2 100644
--- a/configs/bf533-stamp_defconfig
+++ b/configs/bf533-stamp_defconfig
@@ -1,7 +1,13 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_STAMP=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 # CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
index bf3d79f..b7e11af 100644
--- a/configs/bf537-minotaur_defconfig
+++ b/configs/bf537-minotaur_defconfig
@@ -3,7 +3,11 @@ CONFIG_TARGET_BF537_MINOTAUR=y
 CONFIG_SYS_PROMPT="minotaur> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig
index e737561..9190de8 100644
--- a/configs/bf537-pnav_defconfig
+++ b/configs/bf537-pnav_defconfig
@@ -1,7 +1,14 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_PNAV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
index ba80e63..49a6fed 100644
--- a/configs/bf537-srv1_defconfig
+++ b/configs/bf537-srv1_defconfig
@@ -3,7 +3,11 @@ CONFIG_TARGET_BF537_SRV1=y
 CONFIG_SYS_PROMPT="srv1> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
index 34c774c..dc61dfd 100644
--- a/configs/bf537-stamp_defconfig
+++ b/configs/bf537-stamp_defconfig
@@ -1,7 +1,14 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_STAMP=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
index 48ad582..5ca81e8 100644
--- a/configs/bf538f-ezkit_defconfig
+++ b/configs/bf538f-ezkit_defconfig
@@ -1,6 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF538F_EZKIT=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 # CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index eca4c85..c7277f2 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -1,7 +1,15 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF548_EZKIT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index 4a25d2e..7e5d007 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -3,8 +3,13 @@ CONFIG_TARGET_BF561_ACVILON=y
 CONFIG_SYS_PROMPT="Acvilon> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
index 8a24403..987b58a 100644
--- a/configs/bf561-ezkit_defconfig
+++ b/configs/bf561-ezkit_defconfig
@@ -1,6 +1,10 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_EZKIT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig
index 642ca87..71e8406 100644
--- a/configs/bf609-ezkit_defconfig
+++ b/configs/bf609-ezkit_defconfig
@@ -1,7 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF609_EZKIT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 92c3ee7..1388370 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -4,7 +4,11 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 5d1c0dc..14c0ce3 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -7,8 +7,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index a4aa6d9..aebf7f1 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -7,8 +7,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig
index 944145a..2415b43 100644
--- a/configs/blackstamp_defconfig
+++ b/configs/blackstamp_defconfig
@@ -2,6 +2,9 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BLACKSTAMP=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig
index 41b5a23..c6b87b2 100644
--- a/configs/blackvme_defconfig
+++ b/configs/blackvme_defconfig
@@ -2,6 +2,9 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_BLACKVME=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
index effba78..0ca6567 100644
--- a/configs/br4_defconfig
+++ b/configs/br4_defconfig
@@ -3,8 +3,15 @@ CONFIG_TARGET_BR4=y
 CONFIG_SYS_PROMPT="br4>"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index 6dcb95a..facf9fd 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_BUBINGA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 13b57ca..b375453 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -5,7 +5,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 5da27d2..96f8ea0 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -7,8 +7,12 @@ CONFIG_SYS_PROMPT="Cairo # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index a2ba4b0..1f88b66 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -7,4 +7,6 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR="\x0b"
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index 3d643f5..da6f1d5 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index 99af7ce..ef63089 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig
index b1ec147..5caea0d 100644
--- a/configs/canmb_defconfig
+++ b/configs/canmb_defconfig
@@ -2,3 +2,5 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CANMB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index a2e27be..d95fe73 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -5,6 +5,12 @@ CONFIG_CANYONLANDS=y
 CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index c4a0580..42e0b2c 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -10,10 +10,16 @@ CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index ffc4d7c..d164d1a 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -7,8 +7,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index 7e50cfc..f391963 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -3,5 +3,11 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_CHARON=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 1fef01e..ef0e95b 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -11,7 +11,14 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 667d0ae..8088f0c 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -15,9 +15,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 11f25a4..20ea99a 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -14,9 +14,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index ba03f7d..e18c3c7 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -11,9 +11,15 @@ CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 57d6a64..9ecf08e 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -6,8 +6,15 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_DEBUG_UART=y
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
index 058e371..a9dafeb 100644
--- a/configs/cm-bf527_defconfig
+++ b/configs/cm-bf527_defconfig
@@ -1,6 +1,11 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF527=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
index a14c343..14b959c 100644
--- a/configs/cm-bf533_defconfig
+++ b/configs/cm-bf533_defconfig
@@ -2,5 +2,8 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF533=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
index 8cfb2b4..6366048 100644
--- a/configs/cm-bf537e_defconfig
+++ b/configs/cm-bf537e_defconfig
@@ -1,6 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537E=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
index 0dd30a8..67b04d1 100644
--- a/configs/cm-bf537u_defconfig
+++ b/configs/cm-bf537u_defconfig
@@ -1,6 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537U=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
index 30abb47..90187bd 100644
--- a/configs/cm-bf548_defconfig
+++ b/configs/cm-bf548_defconfig
@@ -1,7 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF548=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 # CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
index 1adbfc3..086a05a 100644
--- a/configs/cm-bf561_defconfig
+++ b/configs/cm-bf561_defconfig
@@ -2,5 +2,8 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF561=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
index 171ed47..7f854f9 100644
--- a/configs/cm5200_defconfig
+++ b/configs/cm5200_defconfig
@@ -2,5 +2,11 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 7fe6be3..bf8d21e 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -5,7 +5,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T335 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 80a7c34..774e259 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -5,9 +5,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3517 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 2f9f228..32d73ec 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -6,8 +6,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3x # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index f44ee68..e9494dd 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -5,12 +5,17 @@ CONFIG_DM_GPIO=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T43 # "
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index 496a3d3..a372aa3 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -7,8 +7,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T54 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 2e845e7..3cb69ac 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -5,3 +5,4 @@ CONFIG_SYS_PROMPT="COBRA > "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 2dead77..6926104 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -1,9 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_COLIBRI_PXA270=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 70da60c..c174b9c 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -10,9 +10,13 @@ CONFIG_SYS_PROMPT="Colibri T20 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 4f25973..24f0763 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -10,9 +10,13 @@ CONFIG_SYS_PROMPT="Colibri T30 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index bcafd59..9e37e21 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -8,9 +8,13 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_I
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri VFxx # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index ac83103..95d55be 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -20,6 +20,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO2_VOLT=1800
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 83d477e..a802bbd 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -16,9 +16,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index b5b6e7c..aa53c60 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -9,6 +9,10 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_TPM=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index 0590c8a..e4de7aa 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -9,6 +9,10 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_TPM=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index ff5c22e..e614122 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -7,8 +7,14 @@ CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 3318221..44fb275 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -9,8 +9,11 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 8bf4e14..60a6727 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -5,9 +5,15 @@ CONFIG_TARGET_COUGARCANYON2=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 8ea281e..5d0079e 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -14,9 +14,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 1b2fbfd..8f85ca0 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -3,9 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="d2v2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index b4820cf..8772ec8 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 605aba7..64bed91 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -7,7 +7,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index fdf6786..2105ebf 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -4,7 +4,10 @@ CONFIG_TARGET_DA850EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 59835a7..a2a6e23 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -10,10 +10,16 @@ CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index 75bc1f0..802e684 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -7,8 +7,15 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_MISC=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 111f3a1..c656c94 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -6,8 +6,15 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 6dda2ae..373773d 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -7,8 +7,15 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_NAND_PXA3XX=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig
index c69d404..c3fa26f 100644
--- a/configs/dbau1000_defconfig
+++ b/configs/dbau1000_defconfig
@@ -11,4 +11,5 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig
index 2e38812..5e2c9bd 100644
--- a/configs/dbau1100_defconfig
+++ b/configs/dbau1100_defconfig
@@ -11,4 +11,5 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig
index f61e7b6..10fe8aa 100644
--- a/configs/dbau1500_defconfig
+++ b/configs/dbau1500_defconfig
@@ -11,4 +11,5 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index 8d1b786..5d55c49 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -5,5 +5,11 @@ CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index dbb447d..b659da6 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -5,9 +5,14 @@ CONFIG_SPL_DM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index d7e9235..0e1cfc5 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -6,7 +6,10 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index b8e04f3..214a1ae 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -19,5 +19,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
index 4ac8bda..ad8292f 100644
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_RAMBOOT_defconfig
@@ -8,5 +8,11 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
index e43a910..e87618f 100644
--- a/configs/digsy_mtc_defconfig
+++ b/configs/digsy_mtc_defconfig
@@ -6,5 +6,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
index be8b855..cd24c16 100644
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
@@ -8,5 +8,11 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
index 67a8f2a..e617acc 100644
--- a/configs/digsy_mtc_rev5_defconfig
+++ b/configs/digsy_mtc_rev5_defconfig
@@ -8,5 +8,11 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index 1f4c633..5565bb8 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -8,6 +8,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index dd673b0..6554fb3 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -6,6 +6,8 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
+CONFIG_LOOPW=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dnp5370_defconfig b/configs/dnp5370_defconfig
index 3b323e9..1da61c1 100644
--- a/configs/dnp5370_defconfig
+++ b/configs/dnp5370_defconfig
@@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_DNP5370=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index 493da5b..ac236cd 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_DNS325=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 757043b..2fecf39 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_DOCKSTAR=y
 CONFIG_SYS_PROMPT="DockStar> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 287a6bd..9b5cd78 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -13,8 +13,14 @@ CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 99db387..47fd428 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -12,8 +12,14 @@ CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index b039719..41cdbbf 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -7,8 +7,14 @@ CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 3f9724b..15e94a0 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -8,8 +8,14 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index 6161057..ccc2124 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -9,8 +9,14 @@ CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 1b3aea5..bfee48a 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -8,8 +8,14 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index b64941f..68b5de4 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -5,7 +5,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="dragonboard410c => "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIMER=y
 CONFIG_CLK=y
 CONFIG_MSM_GPIO=y
 CONFIG_PM8916_GPIO=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 4c3c1df..fb5d916 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -6,7 +6,15 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 2648ccc..254440f 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -17,5 +17,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 3312dda..41f669b 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -6,8 +6,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="duovero # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index 6ce9de5..c23a298 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -8,10 +8,16 @@ CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index cdcfdf6..2c0f1e8 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -5,8 +5,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ea20 > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 1e204bf..5dcf4ec 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -4,4 +4,6 @@ CONFIG_SYS_TEXT_BASE=0xFF000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
 CONFIG_SYS_PROMPT="\nEB+CPU5282> "
 # CONFIG_CMD_LOADB is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 2db895c..a714458 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_EB_CPU5282=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
 # CONFIG_CMD_LOADB is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 63fd75b..33dcc7b 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -7,7 +7,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ECO5-PK # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig
index de4617c..93ad9ba 100644
--- a/configs/ecovec_defconfig
+++ b/configs/ecovec_defconfig
@@ -11,10 +11,13 @@ CONFIG_TARGET_ECOVEC=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
index 8a76405..c56f90a 100644
--- a/configs/edb9315a_defconfig
+++ b/configs/edb9315a_defconfig
@@ -2,6 +2,9 @@ CONFIG_ARM=y
 CONFIG_TARGET_EDB93XX=y
 CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="EDB9315A> "
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index e58a65d..d2a36e5 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -4,5 +4,7 @@ CONFIG_TARGET_EDMINIV2=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="EDMiniV2> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SYS_NS16550=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index 6f2967b..1954717 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -6,8 +6,14 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_DM_PCI=y
diff --git a/configs/espt_defconfig b/configs/espt_defconfig
index fbb712d..9d491cf 100644
--- a/configs/espt_defconfig
+++ b/configs/espt_defconfig
@@ -16,5 +16,6 @@ CONFIG_TARGET_ESPT=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index d25c225..7739473 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -6,6 +6,16 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index fc40b1d..d5ff72f 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -7,7 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 64cc90a..1c7155f 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -9,7 +9,14 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 94f283a..b51bff8 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -3,4 +3,8 @@ CONFIG_TARGET_FLEA3=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="flea3 U-Boot > "
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index ae90d45..f2ea59b 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -4,5 +4,11 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="FO300"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index da8e2fe..c5f943d 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index e613074..b1038d6 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -10,9 +10,15 @@ CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index 98a0dcc..336d602 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -5,5 +5,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 3f134cc..62aa0cd 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -4,7 +4,12 @@ CONFIG_TARGET_GE_B450V3=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index 067858d..bfe9de1 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -4,7 +4,12 @@ CONFIG_TARGET_GE_B650V3=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 5205152..bc34fdf 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -4,7 +4,12 @@ CONFIG_TARGET_GE_B850V3=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 3517348..4e85e13 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -5,6 +5,11 @@ CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index 7069c28..3b72ecb 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -6,6 +6,11 @@ CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index ece39de..2bdea8c 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_GOFLEXHOME=y
 CONFIG_SYS_PROMPT="GoFlexHome> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 475bdd1..6e3de27 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -10,11 +10,16 @@ CONFIG_TARGET_GOSE=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index b7ef262..3b99683 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -2,8 +2,13 @@ CONFIG_ARM=y
 CONFIG_TARGET_GPLUGD=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
index ddac3ab..d3f9c02 100644
--- a/configs/gr_cpci_ax2000_defconfig
+++ b/configs/gr_cpci_ax2000_defconfig
@@ -3,3 +3,4 @@ CONFIG_TARGET_GR_CPCI_AX2000=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
index 0064554..29c7f29 100644
--- a/configs/gr_ep2s60_defconfig
+++ b/configs/gr_ep2s60_defconfig
@@ -3,3 +3,4 @@ CONFIG_TARGET_GR_EP2S60=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
index 543cba5..e4877f2 100644
--- a/configs/gr_xc3s_1500_defconfig
+++ b/configs/gr_xc3s_1500_defconfig
@@ -3,3 +3,4 @@ CONFIG_TARGET_GR_XC3S_1500=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig
index 5e8bd8b..8dc1b63 100644
--- a/configs/grasshopper_defconfig
+++ b/configs/grasshopper_defconfig
@@ -9,3 +9,5 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 0e53cc5..723a4f2 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -21,5 +21,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 029fee0..e0d5acd 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -13,7 +13,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Ventana > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig
index 57f157a..22f0759 100644
--- a/configs/h2200_defconfig
+++ b/configs/h2200_defconfig
@@ -19,4 +19,5 @@ CONFIG_SYS_PROMPT="> "
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index a2e6a1c..066f353 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -15,6 +15,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index 9d6a3aa..6ee9a30 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 00dc37d..c706bfa 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -10,10 +10,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index a91f420..b853a4e 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -9,4 +9,6 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 3f1f928..32b5c65 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -2,5 +2,8 @@ CONFIG_ARM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 45241b4..af6d28f 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -8,6 +8,8 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 1d3d9b2..c060a07 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -7,5 +7,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 1d5bb33..e552f5d 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 71cfb75..871811e 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -17,5 +17,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index ccd01f5..b57d5bc 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -17,5 +17,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 3c4d960..e1a678a 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -16,5 +16,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig
index 9cf3652..7237cfe 100644
--- a/configs/ibf-dsp561_defconfig
+++ b/configs/ibf-dsp561_defconfig
@@ -1,5 +1,9 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_IBF_DSP561=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_LIB_RAND=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index 7fe6bf0..d9b65b8 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -17,6 +17,9 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index a55bbdb..ccf465d 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_ICON=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index cdb21b7..cd6fbb2 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_ICONNECT=y
 CONFIG_SYS_PROMPT="iconnect => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 3bf051e..08867e7 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -10,6 +10,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
 CONFIG_AUTOBOOT_DELAY_STR="ids"
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 6f6c539..6d1dd01 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -6,8 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig
index d8ffa00..05037f7 100644
--- a/configs/igep0020_nand_defconfig
+++ b/configs/igep0020_nand_defconfig
@@ -6,8 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
index 0ebf508..40150c2 100644
--- a/configs/igep0030_defconfig
+++ b/configs/igep0030_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig
index b0c4700..821e058 100644
--- a/configs/igep0030_nand_defconfig
+++ b/configs/igep0030_nand_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index 3a751c5..1374be2 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -6,8 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
index 6f3ae10..e824616 100644
--- a/configs/imx31_phycore_defconfig
+++ b/configs/imx31_phycore_defconfig
@@ -1,4 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_IMX31_PHYCORE=y
 CONFIG_SYS_PROMPT="uboot> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig
index 445c040..afe3c3c 100644
--- a/configs/imx31_phycore_eet_defconfig
+++ b/configs/imx31_phycore_eet_defconfig
@@ -1,4 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_IMX31_PHYCORE=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 8d24877..8e64ef6 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -17,6 +17,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index 446e841..ca7c260 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -16,5 +16,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index d701617..badf78b 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -19,5 +19,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index c5a6c65..c7fc889 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -16,5 +16,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 4f68833..79f2144 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -3,9 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig
index 4c1016a..e465e1b 100644
--- a/configs/inka4x0_defconfig
+++ b/configs/inka4x0_defconfig
@@ -1,4 +1,9 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_INKA4X0=y
+CONFIG_LOOPW=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
index e6b0bc4..7b70eed 100644
--- a/configs/integratorap_cm720t_defconfig
+++ b/configs/integratorap_cm720t_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM720T=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
index 4afd0e6..4acb12a 100644
--- a/configs/integratorap_cm920t_defconfig
+++ b/configs/integratorap_cm920t_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM920T=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
index 0cfbbf3..dc66f59 100644
--- a/configs/integratorap_cm926ejs_defconfig
+++ b/configs/integratorap_cm926ejs_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM926EJ_S=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
index f25c5ba..ce16756 100644
--- a/configs/integratorap_cm946es_defconfig
+++ b/configs/integratorap_cm946es_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_CM946ES=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-AP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig
index 36e8ad7..913ccab 100644
--- a/configs/integratorcp_cm1136_defconfig
+++ b/configs/integratorcp_cm1136_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM1136=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig
index 817544a..17c3f94 100644
--- a/configs/integratorcp_cm920t_defconfig
+++ b/configs/integratorcp_cm920t_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM920T=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig
index ae69cee..c757fad 100644
--- a/configs/integratorcp_cm926ejs_defconfig
+++ b/configs/integratorcp_cm926ejs_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM926EJ_S=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig
index 85086a5..196eab7 100644
--- a/configs/integratorcp_cm946es_defconfig
+++ b/configs/integratorcp_cm946es_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CM946ES=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Integrator-CP # "
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index fea4d10..b2d1b0b 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -7,5 +7,11 @@ CONFIG_SYS_EXTRA_OPTIONS="INTIB"
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index 01378b3..f387a71 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -7,5 +7,9 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/io_defconfig b/configs/io_defconfig
index 03a2898..f7351a0 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -8,6 +8,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_LOOPW=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index aa51065..5675808 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -7,6 +7,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_LOOPW=y
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
index e2aa906..b872dea 100644
--- a/configs/ip04_defconfig
+++ b/configs/ip04_defconfig
@@ -2,8 +2,13 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_IP04=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index 6b46da0..3f771ea 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -7,4 +7,6 @@ CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
index a8e5174..d8ff177 100644
--- a/configs/ipek01_defconfig
+++ b/configs/ipek01_defconfig
@@ -2,5 +2,9 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_IPEK01=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 666b7a8..99189b2 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -11,6 +11,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index a2be6f5..d123be0 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -10,10 +10,16 @@ CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig
index 072633c..21c448b 100644
--- a/configs/jupiter_defconfig
+++ b/configs/jupiter_defconfig
@@ -3,3 +3,4 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_JUPITER=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_SNTP=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index efddf9f..1d8cc82 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -10,7 +10,13 @@ CONFIG_SYS_PROMPT="K2E EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 2f9b5a0..ee6f335 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -8,8 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index a5bd073..4864d09 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -10,7 +10,13 @@ CONFIG_SYS_PROMPT="K2HK EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 3437dc4..7e60dff 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -10,7 +10,13 @@ CONFIG_SYS_PROMPT="K2L EVM # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index 08a8fd0..db79d95 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_KATMAI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index 7bf5858..13e8412 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -6,10 +6,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="kc1 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index 401fd4f..9048227 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index b58ab6a..4ac1501 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index 9b81c53..a617759 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index 0da9e21..6dda308 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 29eba85..82ea876 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -7,8 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index f8e7f15..85bee4e 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 05b5259..6edcab6 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index f3c0115..1f9b461 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index e263b85..b589ae8 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -7,8 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMLION1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index 5b391be..fb52ab0 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index e339b8a..eed0155 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index 11022f3..4d4cc50 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index bac694b..8728c35 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index d8f0d7c..262b004 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index 7ac4cc3..b311c48 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 61c943f..e049219 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index fcf52f9..e24ce97 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 24ea181..2b681fe 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -10,11 +10,17 @@ CONFIG_TARGET_KOELSCH=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 787c020..3f26874 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -7,7 +7,13 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index ac7690d..6a16d8c 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -2,5 +2,8 @@ CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_KZM9G=y
 CONFIG_SYS_PROMPT="KZM-A9-GT# "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index f042ff7..e3eeabf 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -10,11 +10,16 @@ CONFIG_TARGET_LAGER=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 97b81ef..89b3f9d 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -7,7 +7,11 @@ CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
 CONFIG_AUTOBOOT_STOP_STR="l"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 68172c9..5976cb2 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -6,7 +6,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 224fd8b..5ba935b 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -6,7 +6,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 7fa9daa..ac042b5 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -5,7 +5,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index cfc31a6..5610e06 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -5,7 +5,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 300ec9c..6947d3f 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -5,7 +5,13 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 3b9243a..ab4fc54 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -6,7 +6,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 208a1bc..924d323 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -7,7 +7,14 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 9d196e1..667bedc 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -4,7 +4,13 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 382cd11..a50fe68 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -5,7 +5,15 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index f81e12b..2ee3b91 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -5,7 +5,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index c4b1cba..a1bfbc1 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -5,7 +5,13 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index ebf2466..34a8569 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -6,7 +6,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 67917b2..571550b 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -7,7 +7,14 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 6f8666c..2f76715 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -5,6 +5,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 4253f8c..9c4e2da 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -7,6 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index a97654c..da0577b 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -7,6 +7,13 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index c85039b..e65e07f 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -8,6 +8,13 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 41e5104..441eb2c 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -8,6 +8,13 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 1ad2801..4b8c4f4 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -6,6 +6,13 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index f339096..8c72836 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -7,6 +7,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 2823524..86f6ac2 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -8,6 +8,13 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index fbb3611..84b75f5 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -8,6 +8,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 86f3f1a..3c6bcfe 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -7,6 +7,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 5423853..b74adfb 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -7,6 +7,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 7209d8d..8076ffa 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -8,6 +8,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 1e27b7f..4133fc3 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -8,6 +8,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index 679fb87..1e56c08 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -12,10 +12,13 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index a4055ab..c3429a0 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -12,10 +12,13 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 961262e..f3f2467 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -10,7 +10,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 9cc9784..05e33d1 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -10,7 +10,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 15e4850..ac30219 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -7,7 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index d95774e..13d09d0 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -10,7 +10,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 860e93c..b2e3464 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -10,7 +10,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 67481cb..f27bf6b 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -7,7 +7,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 9db98bb..da8f1a1 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index aa5f841..3068617 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index f9b7f06..ec443f9 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -3,5 +3,9 @@ CONFIG_4xx=y
 CONFIG_TARGET_LUAN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index 98ecb88..9999f45 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -4,6 +4,11 @@ CONFIG_TARGET_LWMON5=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index 55ad865..54829a9 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -5,7 +5,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 2f17ddc..1e9450d 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -6,4 +6,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index f7ad872..adda7fb 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -9,7 +9,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index d0ab4f1..a153e4d 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_MAKALU=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index ee3e9ea..a16f10b 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,10 +1,13 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="malta # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index ca28d92..5289797 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -2,10 +2,13 @@ CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="maltael # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index a873b61..02bad1e 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 200c7a0..3319d3f 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -6,7 +6,14 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index 5a9247a..67bc80c 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -8,9 +8,13 @@ CONFIG_SYS_PROMPT="mcx # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index 15f45df..c2e45de 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -3,5 +3,8 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MECP5123=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 4d9161e..e5fb0cc 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -11,10 +11,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 64108a7..2c2df2e 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -9,4 +9,6 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index 3024f52..a0bf894 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -9,4 +9,6 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig
index b7b2fdb..5dd0856 100644
--- a/configs/mgcoge3ne_defconfig
+++ b/configs/mgcoge3ne_defconfig
@@ -5,4 +5,10 @@ CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index 5143214..f1735c0 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig
index 9d6adea..86de799 100644
--- a/configs/mgcoge_defconfig
+++ b/configs/mgcoge_defconfig
@@ -5,4 +5,10 @@ CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MGCOGE"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 6689104..a46b37a 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -16,9 +16,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 89a52a2..74486a1 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -13,6 +13,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 7bc54d6..e1dc927 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -10,6 +10,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 98a73c2..35f0bfa 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -9,6 +9,9 @@ CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index 0786fcf..90addf4 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -7,5 +7,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig
index 100f898..6e568d4 100644
--- a/configs/motionpro_defconfig
+++ b/configs/motionpro_defconfig
@@ -6,5 +6,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index 62bd8e7..73bf67f 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -3,5 +3,9 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 5d99cb3..7df336c 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -4,5 +4,9 @@ CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 21a3b20..29d7d61 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_MPC8308_P1M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig
index 911f3dc..a9bc3d4 100644
--- a/configs/ms7722se_defconfig
+++ b/configs/ms7722se_defconfig
@@ -16,5 +16,6 @@ CONFIG_TARGET_MS7722SE=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index ea4eb55..a4933f4 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -7,8 +7,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mt_ventoux => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
index f490eab..6dd615b 100644
--- a/configs/munices_defconfig
+++ b/configs/munices_defconfig
@@ -3,4 +3,5 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_MUNICES=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 30de97a..59daea6 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -4,6 +4,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index dc14b21..cc7157e 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index 10d6385..66bff20 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -4,5 +4,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index 5cc051f..12a4011 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_M
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index f93c49a..d425a30 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index bd6a6e6..e591a37 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index d91822c..2aa8f1b 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig
index 20cadde..9ccf069 100644
--- a/configs/mx31ads_defconfig
+++ b/configs/mx31ads_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX31ADS=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index dd6a7b9..bcb85a1 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -2,4 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX31PDK=y
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 2b98931..486e7d9 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -1,5 +1,10 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX35PDK=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 4dd2f78..b9b8d24 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -3,5 +3,9 @@ CONFIG_TARGET_MX51EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index 1580003..b4d821e 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -3,4 +3,7 @@ CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index e9f8f9a..9dec972 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -3,5 +3,8 @@ CONFIG_TARGET_MX53EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index a572231..2e34ccb 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -3,5 +3,8 @@ CONFIG_TARGET_MX53LOCO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 1285d13..3d85014 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -3,5 +3,8 @@ CONFIG_TARGET_MX53SMD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 4dfd4e1..40ad38f 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -6,7 +6,10 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index 20873c7..a7554b7 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -5,6 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index 5fdc267..af2c985 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -5,6 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index eb30b16..12157ba 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 44db02f..01c8122 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 4684a3f..ff4af17 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -5,6 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index 1d0d109..5e02437 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -5,6 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 25f81fc..ee56d4e 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -3,7 +3,13 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 40f9012..0e24307 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 6ad6fd8..a19556d 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 595f8d8..1b69092 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 0ecc91f..7be6374 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 38cd927..47cf613 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -5,8 +5,13 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 73d9e46..b5de314 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -5,8 +5,13 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 995f8d1..b3f5c93 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -4,7 +4,13 @@ CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index f194432..17ad20e 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -5,8 +5,14 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index bf4d972..954201b 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -5,8 +5,13 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 4822d25..8d3cae3 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 660b815..a241e88 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -4,6 +4,11 @@ CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index b062757..88ef332 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -4,6 +4,11 @@ CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index c8894e9..9e43aa7 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -9,8 +9,12 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_USB=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 34c3b74..0d5a683 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -5,6 +5,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nas220> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index 0a6d2eb..cdfb432 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -6,6 +6,8 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
+CONFIG_LOOPW=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index 07bc0d4..d35458f 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -3,9 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="2big2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index b9ebf04..9090518 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -3,9 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index f642175..6cb311e 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -3,9 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index acb1aa2..90af1c7 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -3,9 +3,14 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 37c150a..1de1308 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -3,9 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 6471694..af8c8bb 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index ec15581..1896e44 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 69fc732..8de9ea0 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 2b9689b..e08020d 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 50aef70..a67e01c 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index d2f2e0b..f5f5519 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -4,8 +4,15 @@ CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index f2658cd..60106b3 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -8,6 +8,7 @@ CONFIG_AUTOBOOT_KEYED=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index cdf841c..90db4ff 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -7,7 +7,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index a14a531..40032df 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -12,10 +12,16 @@ CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 16d3ad1..942e8be 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -9,8 +9,13 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ODROID-XU3 # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_ADC=y
 CONFIG_ADC_EXYNOS=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 5f3503f..a32fb56 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -10,9 +10,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Odroid # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index ed790f7..e2ffc7b 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 9efa8d3..d02b47a 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -7,6 +7,10 @@ CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 9c294c3..e609988 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -7,7 +7,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 8efd71e..6062e5f 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -9,8 +9,12 @@ CONFIG_SYS_PROMPT="OMAP Logic # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index acb86ee..a1df368 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -7,9 +7,14 @@ CONFIG_SYS_PROMPT="Overo # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index ed80de0..67d4dd7 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -6,10 +6,14 @@ CONFIG_SYS_PROMPT="Pandora # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
index cdb91bc..afb2286 100644
--- a/configs/omap3_zoom1_defconfig
+++ b/configs/omap3_zoom1_defconfig
@@ -5,8 +5,12 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 12a4683..06450c3 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -5,8 +5,13 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 1d5dfa2..6ca4baf 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -5,9 +5,13 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index f9c7de3..f242d55 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -5,8 +5,13 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 40165da..57bef31 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -7,6 +7,8 @@ CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 26dc87e..79f6eda 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 2e0606d..12b9046 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 451c8ab..b640560 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig
index 47ed8df..d8a3b4c 100644
--- a/configs/openrisc-generic_defconfig
+++ b/configs/openrisc-generic_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_OPENRISC_GENERIC=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 97333c6..7e0be1e 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -13,6 +13,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 26ef10e..6a36955 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -13,4 +13,6 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index df9d0a2..98bbbc2 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -11,6 +11,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index fa12937..07ed4b5 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -15,6 +15,9 @@ CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 9b85b0e..666e206 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_PROMPT="ORIGEN # "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_CONTROL=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index 627eae5..b839c76 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 0283ff0..0b0330b 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -6,7 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 2683a79..ae3105a 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -9,10 +9,16 @@ CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 61742c1..6ee99d1 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -9,10 +9,16 @@ CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 73a9f4f..b2a76a5 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -9,10 +9,16 @@ CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 66eb1ee..f807990 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -10,10 +10,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index 131014d..d2f9258 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -11,4 +11,6 @@ CONFIG_SYS_PROMPT="Pb1x00 # "
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
index 6b66d4c..cc8f2a8 100644
--- a/configs/pcm030_LOWBOOT_defconfig
+++ b/configs/pcm030_LOWBOOT_defconfig
@@ -3,5 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index 7ee7658..25482e2 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -3,5 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="uboot> "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index c97faf0..909a157 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -5,8 +5,14 @@ CONFIG_SYS_EXTRA_OPTIONS="REV1"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 63ef0bb..d9f5c48 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -5,8 +5,14 @@ CONFIG_SYS_EXTRA_OPTIONS="REV3"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index c47dc01..7226f56 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -5,7 +5,12 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="pcm052"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index c94c499..ad9d9c7 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -5,5 +5,8 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 6132a92..b718650 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -9,8 +9,15 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Peach-Pi # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 0427142..68bacc0 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -9,8 +9,15 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Peach-Pit # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 4aead9e..4698b2e 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -4,8 +4,13 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 88a672f..bee3477 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -5,7 +5,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="pepper# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 34d21de..e4f8265 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -10,6 +10,9 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index a778736..a2e0b26 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,3 +10,5 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index e070b79..703f43a 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -7,6 +7,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="picon > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 2218131..1064baf 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -7,6 +7,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="titanium > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 7af9fd4..9c698f8 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -11,10 +11,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index 83e2573..a73d6ed 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -7,5 +7,8 @@ CONFIG_SYS_PROMPT="pm9261> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index 44c78e1..c97ac16 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -7,5 +7,8 @@ CONFIG_SYS_PROMPT="u-boot-pm9263> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index c43901b..9dcc20c 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -6,5 +6,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 53ee15c..11cf100 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -4,6 +4,9 @@ CONFIG_TARGET_POGO_E02=y
 CONFIG_SYS_PROMPT="PogoE02> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 2c3c7bb..7a7651e 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -21,5 +21,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 5899f73..2edfeaf 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -10,11 +10,17 @@ CONFIG_TARGET_PORTER=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
index 07a5507..c2ad41b 100644
--- a/configs/portl2_defconfig
+++ b/configs/portl2_defconfig
@@ -3,8 +3,15 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_KM_KIRKWOOD=y
 CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 59b6249..605d589 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -17,5 +17,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
index c813502..f087b3f 100644
--- a/configs/pr1_defconfig
+++ b/configs/pr1_defconfig
@@ -3,8 +3,15 @@ CONFIG_TARGET_PR1=y
 CONFIG_SYS_PROMPT="pr1>"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index cd8996a..df371f7 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -9,8 +9,14 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index c9c4adc..48a37cd 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -19,5 +19,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index a107c1b..ded6ffc 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -21,5 +21,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 27c2c58..a4eb5c5 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -21,5 +21,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 93d1086..dc820ea 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -21,5 +21,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 0d2d5f7..e474494 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -8,6 +8,8 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 12a7403..2e891e2 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -12,8 +12,14 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
index 17efc24..3d9ef12 100644
--- a/configs/qemu_mips64_defconfig
+++ b/configs/qemu_mips64_defconfig
@@ -2,8 +2,11 @@ CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_CPU_MIPS64_R1=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="qemu-mips64 # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
index a8f1912..9eb93ef 100644
--- a/configs/qemu_mips64el_defconfig
+++ b/configs/qemu_mips64el_defconfig
@@ -3,8 +3,11 @@ CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R1=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="qemu-mips64el # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
index 69ce12d..cc440f8 100644
--- a/configs/qemu_mips_defconfig
+++ b/configs/qemu_mips_defconfig
@@ -1,8 +1,10 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="qemu-mips # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
index c1edee7..3fa84ab 100644
--- a/configs/qemu_mipsel_defconfig
+++ b/configs/qemu_mipsel_defconfig
@@ -2,8 +2,10 @@ CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="qemu-mipsel # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig
index d8a15ac..91926d4 100644
--- a/configs/r0p7734_defconfig
+++ b/configs/r0p7734_defconfig
@@ -11,10 +11,12 @@ CONFIG_TARGET_R0P7734=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index cca0156..f4df61a 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SH=y
 CONFIG_TARGET_R2DPLUS=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 343e917..a067693 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -9,6 +9,9 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig
index 180b9e9..7d8cb38 100644
--- a/configs/r7780mp_defconfig
+++ b/configs/r7780mp_defconfig
@@ -16,5 +16,6 @@ CONFIG_TARGET_R7780MP=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index 095f7c1..6684bd9 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -4,5 +4,9 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 56eb3f3..0679959 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -4,5 +4,9 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index a3d2b86..73b3b36 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -8,8 +8,14 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index 0b3610f..afdb0ed 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -3,5 +3,9 @@ CONFIG_4xx=y
 CONFIG_TARGET_REDWOOD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 52fe27f..cbd97d7 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -5,7 +5,12 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 3abe68f..4bfd7c8 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -9,7 +9,14 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 7cd1e8a..b8f99aa 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -6,7 +6,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index 1f189d4..bf0ca97 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -6,7 +6,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index d52f0b1..c823d0e 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -6,7 +6,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 59e4e6b..9ddd6bc 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -6,7 +6,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rsk7203_defconfig b/configs/rsk7203_defconfig
index 6134172..40adf42 100644
--- a/configs/rsk7203_defconfig
+++ b/configs/rsk7203_defconfig
@@ -16,5 +16,6 @@ CONFIG_TARGET_RSK7203=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 7526426..e2993cb 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -9,8 +9,14 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index bd2675f..f28b928 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -6,9 +6,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Universal # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 9abc136..05efce5 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -9,7 +9,10 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index f1aff9e..1b6649c 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -9,7 +9,10 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index a3377a6..7de3247 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -8,5 +8,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index dd32e4b..8c61615 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -8,5 +8,8 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 1c936c0..9795c0c 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 5f8e4b9..f77145a 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index d0a0f05..08773f5 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 73f6a07..3d020b5 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -8,7 +8,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 2e74804..f93bbdb 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -8,7 +8,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 72a3e56..7b231d9 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -8,7 +8,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 87fa5a3..356aebc 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -8,7 +8,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 749e489..a599251 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -8,7 +8,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index c3f5931..a328c8c 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -8,7 +8,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 7536c46..cc04361 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -25,10 +25,21 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MX_CYCLIC=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_DEMO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_SOUND=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 703db9c..73c2762 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -3,9 +3,12 @@ CONFIG_TARGET_SANSA_FUZE_PLUS=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 1189558..b55d644 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index fe2300e..3de150d 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index 71ce297..f311a2d 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index 41503f3..649e36e 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index de0e1f3..f0e3982 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index 1aebb1a..ce6d600 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index 205f90b..5e37927 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -5,6 +5,8 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index 5a1e593..fa6e61e 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index 8e5237a..ad38457 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_SBC8641D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 1bcd479..097748a 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -4,5 +4,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 3613286..5c72a09 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -10,10 +10,14 @@ CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index d19876a..0da341f 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -10,4 +10,6 @@ CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index 1becb75..ecda85b 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index 6b9425c..1c3a0b9 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index 4c8883b..5a77fe0 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -11,11 +11,13 @@ CONFIG_TARGET_SH7752EVB=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index 9992cff..0dd488f 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -10,11 +10,13 @@ CONFIG_TARGET_SH7753EVB=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index 54d6436..b75fd84 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -11,11 +11,13 @@ CONFIG_TARGET_SH7757LCR=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig
index ff84516..983f2a2 100644
--- a/configs/sh7763rdp_defconfig
+++ b/configs/sh7763rdp_defconfig
@@ -16,5 +16,6 @@ CONFIG_TARGET_SH7763RDP=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig
index 611ee18..ab2cff7 100644
--- a/configs/sh7785lcr_32bit_defconfig
+++ b/configs/sh7785lcr_32bit_defconfig
@@ -11,10 +11,12 @@ CONFIG_TARGET_SH7785LCR=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig
index bc27765..059f5f7 100644
--- a/configs/sh7785lcr_defconfig
+++ b/configs/sh7785lcr_defconfig
@@ -10,10 +10,12 @@ CONFIG_TARGET_SH7785LCR=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/shmin_defconfig b/configs/shmin_defconfig
index 8240aad..1749f13 100644
--- a/configs/shmin_defconfig
+++ b/configs/shmin_defconfig
@@ -16,5 +16,6 @@ CONFIG_TARGET_SHMIN=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 67fca2a..acad1d6 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -10,11 +10,17 @@ CONFIG_TARGET_SILK=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index d6ac40b..e526653 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -9,6 +9,13 @@ CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
index 66c2034..39375de 100644
--- a/configs/smdk2410_defconfig
+++ b/configs/smdk2410_defconfig
@@ -2,4 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_SMDK2410=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK2410 # "
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 7a757ee..e46fcae 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -9,8 +9,15 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK5250 # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index de79ca9..39b329a 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -9,8 +9,15 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK5420 # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 5334f89..19662c8 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -8,7 +8,9 @@ CONFIG_SYS_PROMPT="SMDKV310 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 33386b4..f45243d 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -10,7 +10,11 @@ CONFIG_SYS_PROMPT="Snapper> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index ec88dfb..5458b48 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -9,7 +9,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 86bae46..444a78a 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -6,10 +6,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="sniper # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 0b740e9..3a53d26 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -9,8 +9,15 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="snow # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index d451fea..a64a1e2 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -12,7 +12,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index db443c9..caa3999 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -12,7 +12,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index e5ef64b..9a8dbaa 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -12,7 +12,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index c7f4ff4..5e3d09c 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -12,7 +12,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index d932993..823c512 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -12,7 +12,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 7764879..ae6c23e 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -12,7 +12,13 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 5f19eee..d29027c 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -11,7 +11,15 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 4d86ad1..fe491b5 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -5,7 +5,12 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index 49296bc..7e40037 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 560ff26..51e9358 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index 3e280d5..5ce8720 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index 97a0f2a..1fa6223 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index d4ce01d..5f8feee 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index 517e42f..a070f36 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 2fe149b..5802684 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index f8b027d..b39f1e0 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index a4d8fdc..8188314 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index fd1d8c0..581dfb1 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index e720f38..558bdb8 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index 24c01c6..d9fcd6a 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index 636bb48..3aff58c 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index ca98d58..75855bc 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index cdb1f31..f0f46c2 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index 85f2af6..a4aab03 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index 95a530b1..fac6a3c 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -4,6 +4,9 @@ CONFIG_SYS_EXTRA_OPTIONS="spear600"
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index 019e74a..8f421b7 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 2168013..8b8f28d 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index fc501d9..f0ce802 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand"
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 935257e..2af8184 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -9,8 +9,15 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="spring # "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index a407d52..86dfd0e 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -5,4 +5,5 @@ CONFIG_TARGET_STM32F429_DISCOVERY=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIMER=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index abbb1e9..0048226 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -7,6 +7,8 @@ CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIMER=y
 CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index c5af189..d4d1d89 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -10,11 +10,16 @@ CONFIG_TARGET_STOUT=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 8934992..316ceaf 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -9,6 +9,9 @@ CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 05a2e13..77f4fc1 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -9,6 +9,9 @@ CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index cce8818..6a3b5b8 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -8,8 +8,12 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 28b1633..3cae955 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -14,5 +14,8 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index c3e5390..3ab8901 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index 788d5c1..c462fa2 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index 21d2e76..0deda13 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -4,5 +4,9 @@ CONFIG_TARGET_T3CORP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index 05021d2..9b096cc 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -7,7 +7,11 @@ CONFIG_SYS_PROMPT="TAO-3530 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index b5ab8b4..00bd63f 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -8,9 +8,14 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig
index 053b74c..83b1b56 100644
--- a/configs/tb100_defconfig
+++ b/configs/tb100_defconfig
@@ -8,6 +8,8 @@ CONFIG_SYS_PROMPT="[tb100]:~# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_DM=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index be37090..1841e93 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -5,8 +5,14 @@ CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
index 7a8700f..91e0f75 100644
--- a/configs/tcm-bf518_defconfig
+++ b/configs/tcm-bf518_defconfig
@@ -1,6 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF518=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
index 056b69f..b39e260 100644
--- a/configs/tcm-bf537_defconfig
+++ b/configs/tcm-bf537_defconfig
@@ -1,6 +1,12 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF537=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index d4019f4..8ed7809 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -11,10 +11,16 @@ CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 95d1838..240f11e 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -11,10 +11,13 @@ CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 800abca..1eb4b10 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -11,9 +11,15 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index 11624d6..e9e6290 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -11,9 +11,11 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index c81e411..0437874 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -8,8 +8,14 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 5d2a79a..2208e9a 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -6,5 +6,7 @@ CONFIG_SYS_PROMPT="U-Boot# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index de3c26d..9e38f5d 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -6,6 +6,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Titanium > "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 24e64b6..b5492a9 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -7,7 +7,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index be870ba..69cf92e 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -8,7 +8,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 157d762..40a6f42 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -8,7 +8,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 928c480..b141f16 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -9,7 +9,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index a051a9f..92cc5c9 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -11,6 +11,11 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
 CONFIG_AUTOBOOT_ENCRYPTION=y
 CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_PCA9551_LED=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 73fc63c..693d845 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -9,9 +9,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Trats2 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 8fbb5f2..66a11c9 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -8,9 +8,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Trats # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index ff2c785..21d0bbf 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 4ed1ada..1dfff4d 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -7,6 +7,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 98678d5..8e8618e 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -10,10 +10,16 @@ CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index ac81a46..3a7fa63 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -2,5 +2,8 @@ CONFIG_ARM=y
 CONFIG_TARGET_TS4800=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 904bc89..97fb231 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 7bbe36d..3a03ecb 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -5,5 +5,11 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
 CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index f6b30c2..83cf623 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -7,8 +7,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="twister => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 5e2cb85..af48888 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -4,7 +4,10 @@ CONFIG_TARGET_UDOO=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index fe14f9a..fa5561a 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -12,4 +12,6 @@ CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index b4a3c00..215e87b 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -3,5 +3,10 @@ CONFIG_ARCH_MX5=y
 CONFIG_TARGET_USBARMORY=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
index cc3d802..3dadfcc 100644
--- a/configs/v38b_defconfig
+++ b/configs/v38b_defconfig
@@ -1,4 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_V38B=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index 4b0b5b4..b889976 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -2,6 +2,11 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_SYS_PROMPT="$ "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index 62d8878..597f764 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -5,6 +5,11 @@ CONFIG_VCT_ONENAND=y
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig
index 92a3027..c47f102 100644
--- a/configs/vct_platinumavc_defconfig
+++ b/configs/vct_platinumavc_defconfig
@@ -2,8 +2,10 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_SYS_PROMPT="VCT# "
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig
index 87767bd..e7aef31 100644
--- a/configs/vct_platinumavc_onenand_defconfig
+++ b/configs/vct_platinumavc_onenand_defconfig
@@ -5,8 +5,10 @@ CONFIG_VCT_ONENAND=y
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 7ca6e34..68c4af1 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -2,6 +2,11 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_SYS_PROMPT="$ "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index 88555d9..1d73069 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -5,6 +5,11 @@ CONFIG_VCT_ONENAND=y
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index b2ae829..4243848 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -5,5 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 4ebce04..5749d1c 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -10,10 +10,16 @@ CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 5dc16b3..cbb17c9 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -10,10 +10,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 1497605..644a207 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -9,11 +9,15 @@ CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index b9bfc26..7bae9c9 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -9,11 +9,15 @@ CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index 8818527..2006176 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -9,11 +9,15 @@ CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 0508796..389c384 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -10,9 +10,10 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index 9e53655..4118b58 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -10,9 +10,10 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 524ef4b..433dc34 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -10,9 +10,10 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index 80ec20f..4504af2 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -6,8 +6,12 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index afe8a47..26b045a 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -6,8 +6,12 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 29da314..57d0169 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -8,7 +8,11 @@ CONFIG_SYS_PROMPT="vinco => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 5f0971a..323b416 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index 788d5c1..c462fa2 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -3,5 +3,10 @@ CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 773b493..e03a1d9 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -6,7 +6,11 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 77ccecf..29c5e91 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -9,5 +9,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index c7c1d25..aa15c81 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -5,6 +5,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index d443ae3..a6d1438 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -10,10 +10,14 @@ CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index f335294..ddbd697 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -2,5 +2,9 @@ CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index f73206e..d801c3b 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -4,5 +4,9 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 2999772..12df37b 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -8,7 +8,11 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 25ce098..8c163fb 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -5,4 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index e2a2c81..05d2f35 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -6,8 +6,13 @@ CONFIG_SYS_PROMPT="X600> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 515ae41..5f25633 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -4,8 +4,10 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index edfcc20..9d4b137 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x041000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="xlx-ppc405:/# "
 # CONFIG_CMD_IMLS is not set
+CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index 2e65a2c..4f814a6 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="board:/# "
+CONFIG_LOOPW=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 834cc45..48d95c1 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 7249495..598da20 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index b4b1119..81170dc 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index eb89b12..05c5cdd 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -11,6 +11,8 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index bfbe053..f6767f3 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -11,6 +11,8 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index e189859..13e0069 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -4,5 +4,9 @@ CONFIG_TARGET_XPEDITE1000=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 9baac08..81eb5f8 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -6,6 +6,10 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index 6b8f4bc..77386f5 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -6,6 +6,10 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index 538c6cd..a4dcd78 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -6,6 +6,10 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index 9b3c5c9..113d16d 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -6,6 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 418fb7c..fc13e9d 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -3,6 +3,10 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_XPRESS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index b464d15..9c2bcc5 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -4,6 +4,10 @@ CONFIG_TARGET_XPRESS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 4f76e37..2f1cea2 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -4,5 +4,9 @@ CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index 9a64852..fdede36 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -4,5 +4,10 @@ CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index b2f9784..edf1b45 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -3,5 +3,9 @@ CONFIG_4xx=y
 CONFIG_TARGET_YUCCA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_LOOPW=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index 299cf65..22bdbd3 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -3,6 +3,8 @@ CONFIG_TARGET_ZIPITZ2=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index 955bf37..0578850 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -6,4 +6,7 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
 CONFIG_AUTOBOOT_DELAY_STR="delaygs"
 CONFIG_AUTOBOOT_STOP_STR="stopgs"
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 99ce69e..748c160 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -10,8 +10,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 9198418..cd41af0 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -7,8 +7,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 214d754..8471e10 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -9,8 +9,14 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 26cfc0e..99ddf3c 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -10,8 +10,14 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index fc58fa1..50724b5 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -11,8 +11,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index ea0df44..a80dd11 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -13,6 +13,9 @@ CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 7f8a17a..dbb0d13 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -11,6 +11,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 6a68f7e..be7c425 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -13,6 +13,9 @@ CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 9cb1485..f3c7e1c 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -10,8 +10,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 89739a6..9063010 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -10,8 +10,14 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index e858e55..4054900 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -19,10 +19,8 @@
 #define CONFIG_CMD_BOOTZ	/* boot zImage			*/
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
 #define CONFIG_CMD_CACHE	/* icache, dcache		*/
-#define CONFIG_CMD_CDP		/* Cisco Discovery Protocol	*/
 #define CONFIG_CMD_CLK		/* Clock support		*/
 #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
-#define CONFIG_CMD_DHCP		/* DHCP Support			*/
 #define CONFIG_CMD_DIAG		/* Diagnostics			*/
 #define CONFIG_CMD_DISPLAY	/* Display support		*/
 #define CONFIG_CMD_DOC		/* Disk-On-Chip Support		*/
@@ -34,16 +32,12 @@
 #define CONFIG_CMD_FUSE		/* Device fuse support		*/
 #define CONFIG_CMD_GETTIME	/* Get time since boot         */
 #define CONFIG_CMD_HASH		/* calculate hash / digest	*/
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_IDE		/* IDE harddisk support		*/
 #define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
 #define CONFIG_CMD_IO		/* Access to X86 IO space	*/
 #define CONFIG_CMD_IRQ		/* irqinfo			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 #define CONFIG_CMD_KGDB		/* kgdb				*/
-#define CONFIG_CMD_LICENSE	/* console license display	*/
-#define CONFIG_CMD_MEMINFO	/* meminfo			*/
-#define CONFIG_CMD_MEMTEST	/* mtest			*/
 #define CONFIG_CMD_MFSL		/* FSL support for Microblaze	*/
 #define CONFIG_CMD_MII		/* MII support			*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
@@ -52,24 +46,19 @@
 #define CONFIG_CMD_ONENAND	/* OneNAND support		*/
 #define CONFIG_CMD_PCI		/* pciinfo			*/
 #define CONFIG_CMD_PCMCIA	/* PCMCIA support		*/
-#define CONFIG_CMD_PING		/* ping support			*/
 #define CONFIG_CMD_PORTIO	/* Port I/O			*/
 #define CONFIG_CMD_REGINFO	/* Register dump		*/
 #define CONFIG_CMD_REISER	/* Reiserfs support		*/
-#define CONFIG_CMD_RARP		/* rarpboot support		*/
 #define CONFIG_CMD_READ		/* Read data from partition	*/
 #define CONFIG_CMD_SANDBOX	/* sb command to access sandbox features */
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
 #define CONFIG_CMD_SCSI		/* SCSI Support			*/
 #define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
-#define CONFIG_CMD_SNTP		/* SNTP support			*/
-#define CONFIG_CMD_SPI		/* SPI utility			*/
 #define CONFIG_CMD_TERMINAL	/* built-in Serial Terminal	*/
 #define CONFIG_CMD_UBI		/* UBI Support			*/
 #define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
 #define CONFIG_CMD_UNIVERSE	/* Tundra Universe Support	*/
 #define CONFIG_CMD_UNZIP	/* unzip from memory to memory	*/
-#define CONFIG_CMD_USB		/* USB Support			*/
 #define CONFIG_CMD_ZFS		/* ZFS Support			*/
 
 #endif	/* _CONFIG_CMD_ALL_H */
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index ae44512..a0e490b 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -46,13 +46,11 @@
 #else
 #define CONFIG_CMD_BOOTZ
 #endif
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_PXE
 
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 5262641..e3c222e 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -75,10 +75,6 @@
 #define CONFIG_CMD_BMP
 #endif
 
-#ifndef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT	"=> "
-#endif
-
 #ifndef CONFIG_SYS_PBSIZE
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + 128)
 #endif
@@ -100,8 +96,6 @@
 #ifndef CONFIG_CMDLINE
 #undef CONFIG_CMDLINE_EDITING
 #undef CONFIG_SYS_LONGHELP
-#undef CONFIG_CMD_BOOTD
-#undef CONFIG_CMD_RUN
 #undef CONFIG_CMD_ASKENV
 #undef CONFIG_MENU
 #endif
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h
index 3b198ae..3c1499c 100644
--- a/include/config_uncmd_spl.h
+++ b/include/config_uncmd_spl.h
@@ -10,16 +10,6 @@
 
 #ifdef CONFIG_SPL_BUILD
 /* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
-#undef CONFIG_CMD_CDP
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DNS
-#undef CONFIG_CMD_LINK_LOCAL
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_PING
-#undef CONFIG_CMD_RARP
-#undef CONFIG_CMD_SNTP
-#undef CONFIG_CMD_TFTPPUT
-#undef CONFIG_CMD_TFTPSRV
 
 #ifndef CONFIG_SPL_DM
 #undef CONFIG_DM_SERIAL
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index ef87bda..cda5a65 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -572,7 +572,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -736,14 +735,11 @@ unsigned long get_board_ddr_clk(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -765,7 +761,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index e7a90bd..42cc6db 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -253,12 +253,8 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-#define CONFIG_CMD_I2C
-
-
 /* eSPI - Enhanced SPI */
 #ifdef CONFIG_FSL_ESPI
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
@@ -318,14 +314,12 @@ extern unsigned long get_sdram_size(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 /*
@@ -367,7 +361,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 17ae12e..51bdc0f 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -462,7 +462,6 @@ combinations. this should be removed later
  */
 /* eSPI - Enhanced SPI */
 #ifdef CONFIG_FSL_ESPI
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
@@ -510,7 +509,6 @@ combinations. this should be removed later
 
 #define CONFIG_USB_EHCI  /* USB */
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
@@ -557,12 +555,9 @@ combinations. this should be removed later
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 9c69f91..ba5fbfd 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -409,10 +409,7 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
-#define CONFIG_CMD_I2C
-
 /* eSPI - Enhanced SPI */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 
@@ -476,7 +473,6 @@
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 /* Hash command with SHA acceleration supported in hardware */
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 40fff81..1c4b01f 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -54,7 +54,6 @@
  */
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
@@ -103,7 +102,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_LOOPW            1       /* enable loopw command         */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index b0281be..51054a1 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -66,15 +66,12 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
@@ -129,8 +126,6 @@
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index b38a349..cc7aeb8 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -23,9 +23,7 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
-#undef CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #define CONFIG_MCFFEC
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index f2ea9a8..133f15c 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -39,13 +39,9 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_USB
 #undef CONFIG_CMD_BMP
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 
 #define CONFIG_HOSTNAME			M52277EVB
 #define CONFIG_SYS_UBOOT_END		0x3FFFF
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 2a198e5..efc7827 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -36,11 +36,8 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index a93bafc..e29cb24 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -55,7 +55,6 @@
 #define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
 #define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
-#define CONFIG_LOOPW		1	/* enable loopw command	*/
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
 
 #define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index ddb5cda..ada212c 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -43,7 +43,6 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_PING
 
 #ifdef CONFIG_CMD_IDE
 /* ATA */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 718f31f..fcb0587 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -58,8 +58,6 @@
  */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_MCFFEC
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 195595f..5f055e7 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -56,10 +56,7 @@
 
 /* Available command configuration */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
 
 
 #define CONFIG_MCFFEC
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index eff0aa6..3442723 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -48,7 +48,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 
 #define CONFIG_MCFFEC
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 42cbb0f..c90ea27 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -29,9 +29,7 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#undef CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #define CONFIG_SYS_UNIFY_CACHE
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index b2d544c..0e0e109 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -29,9 +29,7 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_NANDFLASH_SIZE
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index a906204..39733f9 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -29,9 +29,7 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_NANDFLASH_SIZE
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 9b87de6..933b8cd 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -40,17 +40,11 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_UBI
 #define CONFIG_CMD_MII
 #undef CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-
 
 /*
  * NAND FLASH
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index c778823..3b01bd6 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -41,15 +41,9 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #undef CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-
 
 /* Network configuration */
 #define CONFIG_MCFFEC
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7941040..8a7cea5 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -41,19 +41,13 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #undef CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-
 
 /* Network configuration */
 #define CONFIG_MCFFEC
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 81ecbc8..ff8420f 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -31,12 +31,9 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_USB
 
 #define CONFIG_SLTTMR
 
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 8621d7a..9c83d17 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -31,12 +31,9 @@
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_USB
 
 #define CONFIG_SLTTMR
 
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 5726605..8e2bd85 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -52,22 +52,18 @@
  */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_BSP
 
 #if !defined(CONFIG_MIP405T)
-    #define CONFIG_CMD_USB
 #endif
 
 
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index fc625d4..422f223 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -339,9 +339,7 @@
  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
  */
 #ifdef CONFIG_MPC8XXX_SPI
-#define CONFIG_CMD_SPI
 #define CONFIG_USE_SPIFLASH
-#define CONFIG_CMD_SF
 #endif
 
 /*
@@ -432,11 +430,8 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index a3cfe6a..536fc06 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -478,9 +478,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index a05ce63..9cb8012 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -372,7 +372,6 @@
 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_SYS_SCCR_USBDRCM		3
 
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
@@ -459,8 +458,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 8b95920..f815b20 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -326,8 +326,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ASKENV
 
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 4e5e986..c1eb442 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -411,8 +411,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_ASKENV
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 9bf4226..7e0cb2a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -477,8 +477,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_MII
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 8cdfcea..447974c 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -151,7 +151,6 @@
 /*
  * Support USB
  */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
@@ -492,8 +491,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_SDRAM
 
 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
@@ -519,10 +516,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 	#define CONFIG_CMD_PCI
 #endif
 
-#ifdef CONFIG_SYS_I2C
-	#define CONFIG_CMD_I2C
-#endif
-
 /* Watchdog */
 #undef CONFIG_WATCHDOG		/* watchdog disabled */
 
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 68a8e71..09dd4c6 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -379,7 +379,6 @@ extern int board_pci_host_broken(void);
 #define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
 
 #define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
@@ -480,8 +479,6 @@ extern int board_pci_host_broken(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 366febc..ff6c962 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -490,8 +490,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 
@@ -670,7 +668,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 27db9ef..c19e991 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -411,7 +411,6 @@
 #define CONFIG_HARD_SPI
 
 #if defined(CONFIG_SPI_FLASH)
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED	10000000
 #define CONFIG_SF_DEFAULT_MODE	0
 #endif
@@ -619,8 +618,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
@@ -648,7 +645,6 @@
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 06d54a9..6e715f6 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -339,8 +339,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index dd638eb..1187310 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -357,8 +357,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 4d56284..535f648 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -372,8 +372,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
@@ -390,7 +388,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI_PCI
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a4868f9..8085969 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -483,8 +483,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 3bce162..d24309a 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -355,8 +355,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index a5a3dc4..c0841db 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -376,8 +376,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 24c32ca..47b0955 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -377,8 +377,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 1224a20..51abcab 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -467,8 +467,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 10ee862..fe9d4cd 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -576,8 +576,6 @@
  */
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
@@ -593,7 +591,6 @@
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI_PCI
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 7528456..b40d72f 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -455,15 +455,12 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SCSI
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_USB
 #endif
 
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 1f2505f..6f70bd1 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -613,15 +613,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
     #define CONFIG_CMD_SCSI
     #define CONFIG_CMD_EXT2
-    #define CONFIG_CMD_USB
 #endif
 
 
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index f1af928..f4c9312 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -13,7 +13,6 @@
 #define CONFIG_CPU_SH7722	1
 #define CONFIG_MIGO_R		1
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SDRAM
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 6e69258..fcb1644 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -653,15 +653,12 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_RTC_PT7C4338
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
-#define CONFIG_CMD_I2C
-
 /*
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
  * used for SLIC
  */
 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 /* eSPI - Enhanced SPI */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #endif
@@ -736,7 +733,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
@@ -796,7 +792,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index d009913..5272878 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -466,7 +466,6 @@
 
 #define CONFIG_HARD_SPI
 
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		0
 
@@ -662,9 +661,7 @@
  */
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -679,7 +676,6 @@
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 833affd..74cb57d 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -193,8 +193,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_EEPROM_BUS_NUM		0
 
-#define CONFIG_CMD_I2C
-
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
@@ -255,7 +253,6 @@ extern unsigned long get_clock_freq(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
@@ -271,7 +268,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 6f9680f..43709e8 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -397,7 +397,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -601,13 +600,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
@@ -620,7 +616,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_HAS_FSL_MPH_USB
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 5d639b1..5290208 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -41,21 +41,17 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_FDC
 #define CONFIG_CMD_SCSI
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_BSP
 
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 0e6ad7a..c775100 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -60,18 +60,14 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_USB
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index bb0c8bb..a4d7bee 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -56,13 +56,10 @@
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 
 #undef  CONFIG_WATCHDOG			/* watchdog disabled */
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
@@ -96,7 +93,6 @@
 #define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
-#define CONFIG_LOOPW		1	/* enable loopw command         */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index dab4fa7..f69eee6 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -270,16 +270,12 @@
 
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
 
 /* POST support */
@@ -319,7 +315,6 @@
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
-#define CONFIG_LOOPW		1	/* enable loopw command         */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 800c246..90572f4 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -569,7 +569,6 @@ unsigned long get_board_ddr_clk(void);
  */
 #ifndef CONFIG_SPL_BUILD
 #endif
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
@@ -679,7 +678,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -831,14 +829,11 @@ unsigned long get_board_ddr_clk(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index d288a9f..846ad39 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -239,7 +239,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
@@ -556,10 +555,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#if defined(CONFIG_T1024RDB)
-#elif defined(CONFIG_T1023RDB)
-#endif
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	10000000
 #define CONFIG_SF_DEFAULT_MODE	0
@@ -676,7 +671,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -834,14 +828,11 @@ unsigned long get_board_ddr_clk(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 5a4382e..04c564f 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -469,7 +469,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -562,7 +561,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -704,14 +702,11 @@ unsigned long get_board_ddr_clk(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 0ba3913..1e61ec9 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -525,7 +525,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SPI_FLASH_BAR
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 #define CONFIG_ENV_SPI_BUS              0
@@ -619,7 +618,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -771,13 +769,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #ifdef CONFIG_T1042RDB_PI
 #define CONFIG_CMD_DATE
 #endif
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 69d161b..b1bd4fd 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -540,7 +540,6 @@ unsigned long get_board_ddr_clk(void);
 #ifndef CONFIG_SPL_BUILD
 #endif
 
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
@@ -721,7 +720,6 @@ unsigned long get_board_ddr_clk(void);
  * USB
  */
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -772,13 +770,10 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index df4c5dc..dc6e211 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -138,7 +138,6 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
@@ -492,7 +491,6 @@ unsigned long get_board_ddr_clk(void);
  */
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED	 10000000
 #define CONFIG_SF_DEFAULT_MODE	  0
 #endif
@@ -684,7 +682,6 @@ unsigned long get_board_ddr_clk(void);
  * USB
  */
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -730,11 +727,8 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 91857d6..af5855c 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -401,7 +401,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -528,7 +527,6 @@ unsigned long get_board_ddr_clk(void);
 /*
 * USB
 */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index e075442..2b50594 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -302,13 +302,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
@@ -606,7 +603,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -729,7 +725,6 @@ unsigned long get_board_ddr_clk(void);
 /*
 * USB
 */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 8fd3a8b..516acd3 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -130,7 +130,6 @@
 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
 
 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
@@ -167,14 +166,10 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
 #define CONFIG_CMD_BSP
 
 #ifdef CONFIG_VIDEO
@@ -628,11 +623,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
 /*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
  * Various low-level settings
  */
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 7e3fdda..474ab5f 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -107,11 +107,9 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
 
 #ifdef	CONFIG_SPLASH_SCREEN
     #define CONFIG_CMD_BMP
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index fc305f4..98b900a 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -105,16 +105,12 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index b9baad6..2becc46 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -288,15 +288,11 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 472dbb3..8b57f08 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -95,12 +95,9 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 3aec34c..40c60fc 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -95,11 +95,9 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
 
 
 #define CONFIG_NETCONSOLE
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index a46f689..cae97c6 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -98,16 +98,12 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index b44a31b..e6868ef 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -127,17 +127,13 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index cdbae5c..25ce29b 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -98,12 +98,9 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index c1866a5..117d1e4 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -98,16 +98,12 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 881d654..bb61986b 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -101,16 +101,12 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index e06de45..ff473e9 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -101,16 +101,12 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 6b585f9..78cf804 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -140,17 +140,13 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_SNTP
-
 
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 83b094c..778fcf5 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -123,7 +123,6 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
@@ -131,20 +130,15 @@
 
 #define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
 
-
 /*
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
 
 /*
  * Miscellaneous configurable options
@@ -170,11 +164,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
 /*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index a37fbe2..ccdfafa 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -366,8 +366,6 @@
  */
 #define CONFIG_HARD_SPI
 
-#define CONFIG_CMD_SF			1
-#define CONFIG_CMD_SPI			1
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 
@@ -470,14 +468,10 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_CRAMFS
@@ -493,7 +487,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
@@ -564,7 +557,6 @@
 #error "UCP1020 module revision is not defined !!!"
 #endif
 
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_SERVERIP
 
 #define CONFIG_MII		/* MII PHY management */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index ef47e98..0b6e3f3 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -52,12 +52,8 @@
  */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_NAND
 
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 0ed44a8..e2aa578 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -58,12 +58,9 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index df3e06e..f44a20c 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -48,7 +48,6 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_MAY_FAIL
@@ -56,10 +55,8 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_NET_RETRY_COUNT 3
-#define CONFIG_CMD_LINK_LOCAL
 #define CONFIG_NETCONSOLE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_CMD_PING
 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define CONFIG_MTD_PARTITIONS	/* needed for UBI */
 #define CONFIG_FLASH_CFI_MTD
@@ -255,7 +252,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define CONFIG_LOOPW
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
 
 /*
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 2b58830..c6a8553 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -94,13 +94,8 @@
  */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DISPLAY
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index 57421c6..8c60f10 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -394,15 +394,12 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1
 
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_FUSE
-#define CONFIG_CMD_I2C
 #undef CONFIG_CMD_IDE
 #undef CONFIG_CMD_EXT2
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 2f53d73..ab9a4ca 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -167,7 +167,6 @@
  */
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
 
 /*-----------------------------------------------------------------------
  * NAND FLASH
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index f6c0147..95fc41e 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -117,7 +117,6 @@
  */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_PING
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 6bd2983..b8b9644 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -68,7 +68,6 @@
 #define CONFIG_SYS_TMU_CLK_DIV  4
 
 /* i2c */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE		0x7F
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 55f8dc5..bee6b83 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -306,7 +306,6 @@
 #endif
 
 #ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 
@@ -431,7 +430,6 @@
 #endif
 
 /* SPI flash. */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		24000000
 
 /* Network. */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 6c1556a..cd6e0fd 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -100,7 +100,6 @@
 #ifdef CONFIG_USB_AM35X
 
 #ifdef CONFIG_USB_MUSB_HCD
-#define CONFIG_CMD_USB
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
@@ -132,11 +131,8 @@
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_PING
 
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 45f016a..2cbf04e 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -99,7 +99,6 @@
 #ifdef CONFIG_USB_MUSB_AM35X
 
 #ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
@@ -129,10 +128,7 @@
 #define CONFIG_CMD_PART
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MTDPARTS
 
 /* I2C */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5d5ae5e..59a9749 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -109,7 +109,6 @@
 
 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_DWC3
@@ -221,8 +220,6 @@
 
 /* SPI */
 #undef CONFIG_OMAP3_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_TI_SPI_MMAP
 #define CONFIG_QSPI_SEL_GPIO                   48
 #define CONFIG_SF_DEFAULT_SPEED                48000000
@@ -323,8 +320,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* CPSW Ethernet */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_MII
 #define CONFIG_BOOTP_DEFAULT
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 1fffdb1..099ecdd 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -48,14 +48,12 @@
 #define CONFIG_EFI_PARTITION
 
 /* CPSW Ethernet */
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT		10
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
@@ -66,7 +64,6 @@
 #define CONFIG_SUPPORT_EMMC_BOOT
 
 /* USB xHCI HOST */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 8b1920d..f97988c 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -55,14 +55,11 @@
 #if defined(CONFIG_440)
 #define CONFIG_CMD_CACHE
 #endif
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 /*
@@ -86,7 +83,6 @@
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
-#define CONFIG_LOOPW			/* enable loopw command         */
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 	/* include version env variable */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index bbab8b2..3ef7257 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -23,7 +23,6 @@
 
 #undef CONFIG_CMD_AES
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_TIMER
 #define CONFIG_CMD_DIAG
 
 /* undef to save memory	*/
@@ -45,7 +44,6 @@
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1 /* no console @ startup	*/
 #define CONFIG_AUTO_COMPLETE		1 /* add autocompletion support	*/
-#define CONFIG_LOOPW			1 /* enable loopw command	*/
 #define CONFIG_MX_CYCLIC		1 /* enable mdc/mwc commands	*/
 
 #define CONFIG_SYS_LOAD_ADDR		0x20000	/* default load address */
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index 03810c3..fdcbf31 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -14,7 +14,6 @@
 #define CONFIG_CPU_SH7723	1
 #define CONFIG_AP325RXA	1
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index 4bcfb4c..d458705 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -18,7 +18,6 @@
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
@@ -42,7 +41,6 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SH_SH7734_I2C	1
 #define CONFIG_HARD_I2C			1
 #define CONFIG_I2C_MULTI_BUS	1
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 32e9ba3..9c09087 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -26,7 +26,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC support */
 #define CONFIG_MMC
@@ -44,7 +43,6 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* PCI host support */
 #define CONFIG_PCI
@@ -55,7 +53,6 @@
 #define CONFIG_E1000_NO_NVM
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		16384
 #define CONFIG_TFTP_TSIZE
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index fe3b714..f0e88ee 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -69,20 +69,16 @@
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
 #define CONFIG_CMD_CACHE	/* icache, dcache		*/
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP		/* DHCP Support			*/
-#define CONFIG_CMD_DNS
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_IMX_FUSE	/* imx iim fuse                 */
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII		/* MII support			*/
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_MTDPARTS	/* MTD partition support	*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_NAND_LOCK_UNLOCK
 #define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_PING		/* ping support			*/
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index 2bbef55..fc7a35e 100644
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -26,15 +26,11 @@
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/aria.h b/include/configs/aria.h
index b3050df..b69e08e 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -403,14 +403,11 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1
 
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_FUSE
-#define CONFIG_CMD_I2C
 #undef CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index efbf816..8154b2e 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -29,8 +29,6 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -41,7 +39,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
 
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_MTD
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_SPEED		20000000
@@ -185,7 +182,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -216,7 +212,6 @@
 #define CONFIG_CMD_DATE
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 1ce9b9a..e1fe7e6 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -19,8 +19,6 @@
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BOOTZ
 
 #define BOARD_LATE_INIT
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
index fcb5f81..c468484 100644
--- a/include/configs/aspenite.h
+++ b/include/configs/aspenite.h
@@ -35,7 +35,6 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_I2C
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 05d41ce..f7fa058 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -61,7 +61,6 @@
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #if ENABLE_JFFS
 #define CONFIG_CMD_JFFS2
 #endif
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index c55446d..e260867 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -48,8 +48,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 #ifdef CONFIG_SYS_USE_MMC
 
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 2a5acf5..0d98a44 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -120,11 +120,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 
 /*
  * Network Driver Setting
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 7820295..2a5301f 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -76,11 +76,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB		1
 
 /*
  * SDRAM: 1 bank, min 32, max 128 MB
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index c7ba9eb..82f90f2 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -82,10 +82,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 3d39387..c7fac7f 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -91,11 +91,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB		1
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index e292632..8bc5144 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -77,10 +77,7 @@
 
 /* No NOR flash */
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 9dda777..fdebcc2 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -68,13 +68,9 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
 
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x20000000
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 0d45354..126b8d4 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -73,7 +73,6 @@
 /*
  * Command line configuration.
  */
-#undef CONFIG_CMD_USB
 
 #define CONFIG_CMD_NAND			1
 
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index fcd1008..a4d9cb8 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -65,13 +65,9 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
 
 /*
  * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 11d7d0c..4118cac 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -81,13 +81,10 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 
 
 #define CONFIG_ATMEL_USART
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index 0dcc192..dd4e1a3 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -100,13 +100,10 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_MII
 
 
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 8cd7c35..2d34077 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -102,7 +102,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 23d0bb7..560dc88 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -279,7 +279,6 @@
 #define CONFIG_AM335X_USB1_MODE MUSB_OTG
 
 #ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index bb2abf1..d231f7a 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -189,8 +189,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_BAMBOO_NAND
 #define CONFIG_CMD_NAND
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 44ac2da..377fa94 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -457,7 +457,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #endif
 
 #ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 
@@ -563,7 +562,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #endif
 
 /* SPI flash. */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		24000000
 
 /* Network. */
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 9456a31..b9e9dcc 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -127,7 +127,6 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_FAT_WRITE
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index efc5de5..4ac4faf 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -92,7 +92,6 @@
 #define CONFIG_SHA256
 
 /* Enable Time Command */
-#define CONFIG_CMD_TIME
 
 #define CONFIG_CMD_BOOTZ
 
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index f68d8ee..44e3621 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -26,7 +26,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -44,15 +43,12 @@
 #define CONFIG_TEGRA_SLINK_CTRLS       6
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED        24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
@@ -64,7 +60,6 @@
 #define CONFIG_CMD_PCI
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
index 68a91a6..8be2ecb 100644
--- a/include/configs/bf506f-ezkit.h
+++ b/include/configs/bf506f-ezkit.h
@@ -72,10 +72,6 @@
 #define CONFIG_BFIN_SPI
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
-/*
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-*/
 
 /*
  * Env Storage Settings
diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h
index 5a6067e..66339ca 100644
--- a/include/configs/bf525-ucr2.h
+++ b/include/configs/bf525-ucr2.h
@@ -67,7 +67,6 @@
 
 /* support for serial flash */
 #define CONFIG_BFIN_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_HZ	30000000
 
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index be474ad..425f0a9 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -144,16 +144,9 @@
 # define CONFIG_BOOTDELAY	5
 #endif
 
-#ifdef CONFIG_BFIN_MAC
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_PING
-#endif
-
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SF
 
 #define CONFIG_BOOTCOMMAND	"run ramboot"
 #define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 6d4a93b..fc4f50b 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -144,15 +144,11 @@
 #endif
 
 #ifdef CONFIG_BFIN_MAC
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_PING
 #endif
 
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SF
 
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 9c537e0..1b35a86 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -10,15 +10,12 @@
  */
 #ifndef _CONFIG_CMD_DEFAULT_H
 # ifdef ADI_CMDS_NETWORK
-#  define CONFIG_CMD_DHCP
 #  define CONFIG_BOOTP_SUBNETMASK
 #  define CONFIG_BOOTP_GATEWAY
 #  define CONFIG_BOOTP_DNS
 #  define CONFIG_BOOTP_NTPSERVER
 #  define CONFIG_BOOTP_RANDOM_DELAY
 #  define CONFIG_KEEP_SERVERADDR
-#  define CONFIG_CMD_DNS
-#  define CONFIG_CMD_PING
 #  ifdef CONFIG_BFIN_MAC
 #   define CONFIG_CMD_MII
 #  endif
@@ -41,7 +38,6 @@
 # ifdef CONFIG_USB
 #  define CONFIG_CMD_EXT2
 #  define CONFIG_CMD_FAT
-#  define CONFIG_CMD_USB
 #  define CONFIG_CMD_USB_STORAGE
 #  define CONFIG_DOS_PARTITION
 # endif
@@ -55,20 +51,12 @@
 # ifdef CONFIG_RTC_BFIN
 #  define CONFIG_CMD_DATE
 #  ifdef ADI_CMDS_NETWORK
-#   define CONFIG_CMD_SNTP
 #  endif
 # endif
 # ifdef CONFIG_SPI
 #  define CONFIG_CMD_EEPROM
 # endif
-# if defined(CONFIG_BFIN_SPI) || defined(CONFIG_SOFT_SPI)
-#  define CONFIG_CMD_SPI
-# endif
-# ifdef CONFIG_SPI_FLASH
-#  define CONFIG_CMD_SF
-# endif
 # if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-#  define CONFIG_CMD_I2C
 #  define CONFIG_SOFT_I2C_READ_REPEATED_START
 # endif
 # ifndef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index 05c932f..e48be7a 100644
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -16,13 +16,9 @@
 
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index b9e859c..515ed77 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -102,21 +102,10 @@
 #define CONFIG_AUTO_COMPLETE	1
 #define CONFIG_ENV_OVERWRITE	1
 
-#ifdef CONFIG_SMC91111
-# define CONFIG_CMD_DHCP
-# define CONFIG_CMD_PING
-#else
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-# define CONFIG_CMD_I2C
-#endif
-
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_CPLBINFO
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_SF
 
 #define CONFIG_BOOTDELAY     5
 #define CONFIG_BOOTCOMMAND   "run ramboot"
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
index a262e79..ef90603 100644
--- a/include/configs/blackvme.h
+++ b/include/configs/blackvme.h
@@ -83,8 +83,6 @@
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_ROOTPATH		"/export/uClinux-dist/romfs"	/*NFS*/
 #define CFG_AUTOLOAD		"no"
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 /*
  * SDRAM settings & memory map
@@ -154,7 +152,6 @@
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_CPLBINFO
-#define CONFIG_CMD_SF
 
 /*
  * Default: boot from SPI flash.
@@ -218,7 +215,6 @@
  * PF12,13 on SPI connector 0.
  */
 #ifdef CONFIG_SYS_I2C_SOFT
-# define CONFIG_CMD_I2C
 # define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF12
 # define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF13
 # define CONFIG_SYS_I2C_SPEED		50000
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index ea7b104..51d4624 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -95,7 +95,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
 
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index d5d4ded..37adede 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -309,16 +309,12 @@
  */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
 #endif
 
 /* additions for new relocation code, must added to all boards */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 2a6c09f..0a39cdf 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -37,7 +37,6 @@
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-
 /*
  * BOOTP options
  */
@@ -46,18 +45,14 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-
 
 /*
  * MUST be low boot - HIGHBOOT is not supported anymore
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index e136824..ad9f418 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -388,15 +388,12 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SATA
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 #elif defined(CONFIG_GLACIER)
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
 #else
 #error "board type not defined"
 #endif
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index acfe968..85fd327 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -29,7 +29,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -47,15 +46,12 @@
 #define CONFIG_TEGRA_SLINK_CTRLS       6
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED        24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
@@ -67,7 +63,6 @@
 #define CONFIG_CMD_PCI
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-post.h"
 
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 1ac9dca..57dfdde 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
 /* SPI NOR */
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_SST
@@ -57,7 +56,6 @@
 #define CONFIG_IMX_THERMAL
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -72,7 +70,6 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -133,8 +130,6 @@
 #define CONFIG_LIBATA
 
 /* Ethernet */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h
index 67f45c0..d1f5b46 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -21,7 +21,6 @@
 #define CONFIG_SPI_FLASH_GIGADEVICE
 
 #define CONFIG_CMD_SF_TEST
-#define CONFIG_CMD_TIME
 
 #undef CONFIG_SPL_GPIO_SUPPORT
 
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index f0de827..991121d 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -27,20 +27,13 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
-#define CONFIG_CMD_TIME
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 3744af2..766faa6 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -28,16 +28,11 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 
 /*
  * Serial console configuration
@@ -292,8 +287,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */
 
-#define CONFIG_LOOPW		1
-
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
 /*
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index adf05b1..99b5d3e 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -19,7 +19,6 @@
 #undef CONFIG_BOARD_LATE_INIT
 #undef CONFIG_SPI
 #undef CONFIG_OMAP3_SPI
-#undef CONFIG_CMD_SPI
 #undef CONFIG_SPL_OS_BOOT
 #undef CONFIG_BOOTCOUNT_LIMIT
 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 016e752..debedec 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -99,7 +99,6 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_MUSB_UDC
 #define CONFIG_TWL4030_USB
-#define CONFIG_CMD_USB
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE
@@ -118,11 +117,8 @@
 				"1920k(u-boot),256k(u-boot-env),"\
 				"4m(kernel),-(fs)"
 
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 553b648..8ac41e2 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -117,7 +117,6 @@
 #endif /* CONFIG_USB_MUSB_AM35X */
 
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* commands to include */
 #define CONFIG_CMD_CACHE
@@ -131,11 +130,8 @@
 				"1920k(u-boot),256k(u-boot-env),"\
 				"4m(kernel),-(fs)"
 
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 1c1951c..0e05194 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -101,7 +101,6 @@
 #undef CONFIG_SYS_MONITOR_LEN
 #undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#undef CONFIG_CMD_IMLS
 
 #define CONFIG_ENV_SIZE			(16 * 1024)
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index c8c67c4..9b13aa6 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -69,7 +69,6 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 /* USB UHH support options */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
@@ -81,8 +80,6 @@
 #define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO	83 /* HSIC3 ETH #RESET */
 
 /* Enabled commands */
-#define CONFIG_CMD_DHCP		/* DHCP Support			*/
-#define CONFIG_CMD_PING
 
 /* USB Networking options */
 #define CONFIG_USB_HOST_ETHER
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 67a143f..9e44015 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -120,7 +120,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
 
 #undef CONFIG_CMD_MII
 
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index edd0329..c38d888 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -55,11 +55,9 @@
  */
 #define	CONFIG_CMD_ENV
 #define	CONFIG_CMD_MMC
-#define	CONFIG_CMD_USB
 
 /* I2C support */
 #ifdef CONFIG_SYS_I2C
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_PXA
 #define CONFIG_PXA_STD_I2C
 #define CONFIG_PXA_PWR_I2C
@@ -80,8 +78,6 @@
  * Networking Configuration
  */
 #ifdef	CONFIG_CMD_NET
-#define	CONFIG_CMD_PING
-#define	CONFIG_CMD_DHCP
 
 #define	CONFIG_DRIVER_DM9000		1
 #define CONFIG_DM9000_BASE		0x08000000
@@ -96,11 +92,6 @@
 #endif
 
 #undef	CONFIG_SYS_LONGHELP		/* Saves 10 KB */
-#undef CONFIG_SYS_PROMPT
-#ifdef	CONFIG_HUSH_PARSER
-#define	CONFIG_SYS_PROMPT		"$ "
-#else
-#endif
 #define	CONFIG_SYS_CBSIZE		256
 #define	CONFIG_SYS_PBSIZE		\
 	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index e97e5a1..01fc13d 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -25,7 +25,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC support */
 #define CONFIG_MMC
@@ -38,14 +37,12 @@
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	3
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		1536
 #define CONFIG_TFTP_TSIZE
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 47914c7..a34da80 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -26,7 +26,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC support */
 #define CONFIG_MMC
@@ -44,14 +43,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 #define CONFIG_IP_DEFRAG
 #define CONFIG_TFTP_BLOCKSIZE		16384
 #define CONFIG_TFTP_TSIZE
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 70e970f..ea33e7a 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -83,8 +83,6 @@
 #define CONFIG_MTD_UBI_FASTMAP
 #define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -173,7 +171,6 @@
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80010000
 #define CONFIG_SYS_MEMTEST_END		0x87C00000
 
@@ -223,7 +220,6 @@
 #define CONFIG_SYS_CACHELINE_SIZE 32
 
 /* USB Host Support */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_VF
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 3f03978..77b3e50 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -201,7 +201,6 @@
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 
 #ifndef CONFIG_TRAILBLAZER
-#define CONFIG_CMD_I2C
 #endif
 
 #define CONFIG_PCA9698			/* NXP PCA9698 */
@@ -217,7 +216,6 @@
 #define CONFIG_HARD_SPI
 
 
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		0
 #endif
@@ -326,7 +324,6 @@
  * USB
  */
 #define CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 
 #define CONFIG_HAS_FSL_DR_USB
@@ -388,7 +385,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c937957..1ab2efb 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -402,7 +402,6 @@
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -611,13 +610,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -631,7 +627,6 @@
 #define CONFIG_HAS_FSL_MPH_USB
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 6ef6a7d..fffcd95 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -69,10 +69,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 1691cea..701f59e 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -436,13 +436,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -456,7 +453,6 @@
 #define CONFIG_HAS_FSL_MPH_USB
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
@@ -489,7 +485,6 @@
 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 3e84cbc..2972057 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -141,7 +141,6 @@
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 
 #define CONFIG_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_DAVINCI_SPI
 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
@@ -288,10 +287,8 @@
  */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
@@ -299,9 +296,7 @@
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
 #endif
 
 #ifdef CONFIG_USE_NAND
@@ -317,7 +312,6 @@
 #endif
 
 #ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_CMD_SPI
 #endif
 
 #if !defined(CONFIG_USE_NAND) && \
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index f74ced1b..40dc35c 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -22,7 +22,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -41,22 +40,18 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED        24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 7f19334..f8454cf 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -25,18 +25,11 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
-#define CONFIG_CMD_TIME
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index ef14132..d31e74f 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -26,21 +26,14 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
-#define CONFIG_CMD_TIME
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index c8b0344..66b723d 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -27,21 +27,14 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
-#define CONFIG_CMD_TIME
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 817676f..faf2a87 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -80,14 +80,12 @@
 
 #ifdef CONFIG_DBAU1550
 
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_IDE
 #undef CONFIG_CMD_PCMCIA
 
 #else
 
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_DHCP
 
 #endif
 
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index a8ce7e1..4114f9e 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -61,7 +61,6 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_LPC32XX
 #define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_CMD_I2C
 
 /*
  * GPIO
@@ -73,7 +72,6 @@
  */
 #define CONFIG_LPC32XX_SSP
 #define CONFIG_LPC32XX_SSP_TIMEOUT	100000
-#define CONFIG_CMD_SPI
 
 /*
  * Ethernet
@@ -85,8 +83,6 @@
 #define CONFIG_PHY_ADDR			0x1F
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 /*
  * NOR Flash
@@ -131,7 +127,6 @@
 #define CONFIG_USB_ISP1301_I2C_ADDR		0x2d
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
 
 /*
  * U-Boot General Configurations
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index b8975fa..4afc91b 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -96,11 +96,9 @@
 							/* partition */
 
 /* commands to include */
-#define CONFIG_CMD_DHCP			/* DHCP support			*/
 #define CONFIG_CMD_JFFS2		/* JFFS2 Support		*/
 #define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
 
-#undef CONFIG_CMD_SPI
 #undef CONFIG_CMD_ASKENV
 #undef CONFIG_CMD_BOOTZ
 #undef CONFIG_SUPPORT_RAW_INITRD
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index db3759f..0bf5088 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -103,21 +103,16 @@
 #endif
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_USB
 
 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
 #define CONFIG_SYS_LOWBOOT	1
@@ -388,7 +383,6 @@
 #define CONFIG_AUTO_COMPLETE	1
 #define CONFIG_CMDLINE_EDITING	1
 
-#define CONFIG_LOOPW		1
 #define CONFIG_MX_CYCLIC	1
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index bbeed76..445a346 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -62,10 +62,8 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_DTT
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 
 /*
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index 1e461f5..4dda319 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -58,10 +58,8 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_DTT
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 
 /*
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
index c46e60d..c0c0de9 100644
--- a/include/configs/dnp5370.h
+++ b/include/configs/dnp5370.h
@@ -54,7 +54,6 @@
 #define CONFIG_RMII             1
 
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 #endif
 
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
index 85a2594..7ee274e 100644
--- a/include/configs/dns325.h
+++ b/include/configs/dns325.h
@@ -31,11 +31,8 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_DATE
 #define CONFIG_SYS_MVFS
@@ -49,7 +46,6 @@
 #include "mv-common.h"
 
 /* Remove or override few declarations from mv-common.h */
-#undef CONFIG_SYS_PROMPT
 
 /*
  * Ethernet Driver configuration
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index efe5807..ae3017c 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -30,12 +30,9 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index d2d16a6..8d6ed05 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -142,14 +142,12 @@
 #define CONFIG_HSMMC2_8BIT
 
 /* CPSW Ethernet */
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT		10
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
@@ -159,8 +157,6 @@
 
 /* SPI */
 #undef	CONFIG_OMAP3_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_TI_SPI_MMAP
 #define CONFIG_SF_DEFAULT_SPEED                64000000
 #define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_0
@@ -215,7 +211,6 @@
 #define CONFIG_SUPPORT_EMMC_BOOT
 
 /* USB xHCI HOST */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_DWC3
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index edf8cfb..ae4fbb4 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -61,10 +61,8 @@
 /* Extra Commands */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GPT
 #define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MMC
 /* Enable that for switching of boot partitions */
 /* Disabled by default as some sub-commands can brick eMMC */
@@ -72,7 +70,6 @@
 #define CONFIG_CMD_PART
 #define CONFIG_CMD_REGINFO	/* Register dump		*/
 #define CONFIG_CMD_TFTP
-#define CONFIG_CMD_TIMER
 #define CONFIG_CMD_UNZIP
 
 /* Partition table support */
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index e3c7087..64c546c 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -24,15 +24,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_USB
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/duovero.h b/include/configs/duovero.h
index bb3ba55..ac9a67f 100644
--- a/include/configs/duovero.h
+++ b/include/configs/duovero.h
@@ -28,7 +28,6 @@
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 
 /* USB UHH support options */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
@@ -40,8 +39,6 @@
 
 #define CONFIG_SYS_ENABLE_PADS_ALL
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_32_BIT
diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h
index 33ebb7c..3a7f490 100644
--- a/include/configs/e2220-1170.h
+++ b/include/configs/e2220-1170.h
@@ -20,7 +20,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -37,22 +36,18 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE		(4 << 20)
 
 /* USB2.0 Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 85db470..06e988a 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -146,21 +146,16 @@
  */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
-#define CONFIG_CMD_I2C
 
 #ifdef CONFIG_CMD_BDI
 #define CONFIG_CLOCKS
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
 #endif
 
 /* NAND Setup */
@@ -188,8 +183,6 @@
 
 /* SPI Flash */
 #ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #endif
 
 #if !defined(CONFIG_SYS_USE_NAND) && \
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index f9ec028..861f2ac 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -65,8 +65,6 @@
  */
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_LED
 #define CONFIG_CMD_MII
 
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
index f23d383..f463521 100644
--- a/include/configs/eco5pk.h
+++ b/include/configs/eco5pk.h
@@ -18,7 +18,6 @@
 #undef CONFIG_USB_EHCI
 #undef CONFIG_USB_EHCI_OMAP
 #undef CONFIG_USB_OMAP3
-#undef CONFIG_CMD_USB
 
 /* Our console port is port3 */
 #undef CONFIG_CONS_INDEX
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 8e62674..3ab1803 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -30,11 +30,9 @@
 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
 
@@ -49,7 +47,6 @@
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE	0x7F
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 0645d34..ce50973 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -38,46 +38,37 @@
 
 #define CONFIG_SYS_LDSCRIPT	"board/cirrus/edb93xx/u-boot.lds"
 
-#undef CONFIG_SYS_PROMPT
 #ifdef CONFIG_EDB9301
 #define CONFIG_EP9301
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9301
-#define CONFIG_SYS_PROMPT		"EDB9301> "
 #define CONFIG_ENV_SECT_SIZE		0x00020000
 #elif defined(CONFIG_EDB9302)
 #define CONFIG_EP9302
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9302
-#define CONFIG_SYS_PROMPT		"EDB9302> "
 #define CONFIG_ENV_SECT_SIZE		0x00020000
 #elif defined(CONFIG_EDB9302A)
 #define CONFIG_EP9302
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9302A
-#define CONFIG_SYS_PROMPT		"EDB9302A> "
 #define CONFIG_ENV_SECT_SIZE		0x00020000
 #elif defined(CONFIG_EDB9307)
 #define CONFIG_EP9307
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9307
-#define CONFIG_SYS_PROMPT		"EDB9307> "
 #define CONFIG_ENV_SECT_SIZE		0x00040000
 #elif defined(CONFIG_EDB9307A)
 #define CONFIG_EP9307
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9307A
-#define CONFIG_SYS_PROMPT		"EDB9307A> "
 #define CONFIG_ENV_SECT_SIZE		0x00020000
 #elif defined(CONFIG_EDB9312)
 #define CONFIG_EP9312
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9312
-#define CONFIG_SYS_PROMPT		"EDB9312> "
 #define CONFIG_ENV_SECT_SIZE		0x00040000
 #elif defined(CONFIG_EDB9315)
 #define CONFIG_EP9315
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9315
-#define CONFIG_SYS_PROMPT		"EDB9315> "
 #define CONFIG_ENV_SECT_SIZE		0x00040000
 #elif defined(CONFIG_EDB9315A)
 #define CONFIG_EP9315
 #define CONFIG_MACH_TYPE		MACH_TYPE_EDB9315A
-#define CONFIG_SYS_PROMPT		"EDB9315A> "
 #define CONFIG_ENV_SECT_SIZE		0x00020000
 #else
 #error "no board defined"
@@ -91,7 +82,6 @@
 
 /* Monitor configuration */
 #undef CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_JFFS2
 
 #define CONFIG_SYS_LONGHELP			/* Enable "long" help in mon */
@@ -269,7 +259,6 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_CMD_BOOTZ
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index d622ef8..4444bc9 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -133,8 +133,6 @@
  * Commands configuration
  */
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_USB
 
 /*
  * Network
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 90cd959..59a06ba 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -30,7 +30,6 @@
 #define CONFIG_MXC_UART
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -39,7 +38,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -63,7 +61,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
-#define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 4896498..ed92865 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -19,7 +19,6 @@
  */
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BOOTDELAY        -1
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 0606194..28bf6b5 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -92,30 +92,20 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_SPI
 
 #ifndef MINIMAL_LOADER
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DNS
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RARP
 #define CONFIG_CMD_REISER
 #define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SNTP
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_USB
 #endif
 
 /* NAND flash */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 7d600bf..97fcd4a 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -121,7 +121,6 @@
 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
@@ -129,8 +128,6 @@
 
 /* SPI */
 #ifdef CONFIG_SPI_FLASH
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		50000000
 #endif
@@ -157,11 +154,9 @@
 #define CONFIG_SHA256
 
 /* Enable Time Command */
-#define CONFIG_CMD_TIME
 
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index df75152..54b9315 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -73,8 +73,6 @@
 /*
  * Command definition
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_DNS
@@ -82,8 +80,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_CACHE
 
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_MII
 #define CONFIG_NET_RETRY_COUNT	100
 
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index c45a92b..0c594b8 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -81,7 +81,6 @@
 #define CONFIG_DOS_PARTITION
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -107,8 +106,6 @@
 #define CONFIG_G_DNL_MANUFACTURER "Advantech"
 
 /* Networking Configs */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -120,7 +117,6 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Serial Flash */
-#define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
@@ -137,7 +133,6 @@
 /* Command definition */
 #define CONFIG_CMD_BMODE
 #define CONFIG_CMD_BOOTZ
-#undef CONFIG_CMD_IMLS
 
 #define CONFIG_LOADADDR	0x12000000
 #define CONFIG_SYS_TEXT_BASE	0x17800000
@@ -337,7 +332,6 @@
 #endif
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED		  100000
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index 188d2e2..243e19f 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -52,12 +52,9 @@
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EXT4
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 52c67d5..638fad1 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -52,8 +52,6 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 
@@ -62,11 +60,9 @@
 
 /* Network configuration */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PING
 #define CONFIG_ARMADA100_FEC
 
 /* DHCP Support */
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
 #endif /* CONFIG_CMD_NET */
 
@@ -90,7 +86,6 @@
 #define CONFIG_SYS_SSP_PORT		2
 
 /* Flash Support */
-#define CONFIG_CMD_SF
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index c3b1729..f3361d0 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -60,7 +60,6 @@
  * Supported commands
  */
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_IRQ
 
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 45163ed..563b205 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -54,7 +54,6 @@
  * Supported commands
  */
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_IRQ
 
@@ -63,7 +62,6 @@
 #define CONFIG_USB_UHCI
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 /* Enable needed helper functions */
 #define CONFIG_SYS_STDIO_DEREGISTER	/* needs stdio_deregister */
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index f675b75..dcb72c9 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -41,7 +41,6 @@
  * Supported commands
  */
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_IRQ
 
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 8cde96a..8e0cff9 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -94,9 +94,7 @@
  */
 /* add useful commands */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #define CONFIG_AUTO_COMPLETE
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 747eafc..58598c3 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -65,7 +65,6 @@
 #ifdef CONFIG_SPI_FLASH
 
 /* SPI */
-#define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
   #define CONFIG_MXC_SPI
   #define CONFIG_SPI_FLASH_MTD
@@ -79,7 +78,6 @@
 
 #else
 /* Enable NAND support */
-#define CONFIG_CMD_TIME
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
 #ifdef CONFIG_CMD_NAND
@@ -98,7 +96,6 @@
 #endif /* CONFIG_SPI_FLASH */
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -152,8 +149,6 @@
 #define CONFIG_POWER_LTC3676_I2C_ADDR  0x3c
 
 /* Various command support */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_BMODE         /* set eFUSE shadow for a boot dev and reset */
 #define CONFIG_CMD_HDMIDETECT    /* detect HDMI output device */
@@ -172,7 +167,6 @@
 #define CONFIG_ARP_TIMEOUT       200UL
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 0bdb570..1bb5ebb 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -135,7 +135,6 @@
 #define CONFIG_USB_DEV_PULLUP_GPIO	33
 /* USB VBUS GPIO 3 */
 
-#define CONFIG_CMD_PING
 
 #define CONFIG_BOOTDELAY		2
 #define CONFIG_BOOTCOMMAND		\
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 0a3cb18..aa0f38c 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -45,7 +45,6 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
@@ -54,7 +53,6 @@
 #define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index ce4a006..4987373 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -61,7 +61,6 @@
 #define CONFIG_PL01X_SERIAL
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_DWC2
 #define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 75496d7..aecfda4 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -534,10 +534,8 @@ void fpga_control_clear(unsigned int bus, int pin);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
diff --git a/include/configs/icon.h b/include/configs/icon.h
index d9a3671..d42e6f0 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -171,7 +171,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
 #ifdef CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #endif
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
index adf3703..10f1e9b 100644
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -42,8 +42,6 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 17e1f05..ff93c7d 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -277,7 +277,6 @@
 /*
  * I2C setup
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
@@ -291,7 +290,6 @@
  */
 #ifdef CONFIG_HARD_SPI
 #define CONFIG_MPC8XXX_SPI
-#define CONFIG_CMD_SPI
 #define CONFIG_SYS_GPIO1_PRELIM
 #define CONFIG_SYS_GPIO1_DIR		0x00000001
 #define CONFIG_SYS_GPIO1_DAT		0x00000001
@@ -416,10 +414,7 @@
 /*
  * U-Boot environment setup
  */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_SNTP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 526659c..c03e566 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -173,14 +173,12 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
 
 #define CONFIG_BOOTDELAY	5
 
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 235fdd1..94dd796 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -53,9 +53,7 @@
 /***********************************************************
  * Command definition
  ***********************************************************/
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 
 #define CONFIG_BOOTDELAY	3
 
@@ -183,7 +181,6 @@
 
 #define CONFIG_HARD_SPI
 #define CONFIG_MXC_SPI
-#define CONFIG_CMD_SPI
 
 #define CONFIG_S6E63D6
 
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 24da83c..149c8c6 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -82,14 +82,10 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
 
@@ -342,11 +338,6 @@ static inline void tws_data_config_output(unsigned output)
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
 /*
- * Enable loopw command.
- */
-#define CONFIG_LOOPW
-
-/*
  * Various low-level settings
  */
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 4cd889b..f4982e1 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -96,7 +96,6 @@
  * - SIB block
  * - U-Boot environment
  */
-#define CONFIG_CMD_ARMFLASH
 #define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #define CONFIG_SYS_FLASH_BASE		0x24000000
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 913fdab..69f0f4d 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -285,8 +285,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
diff --git a/include/configs/io.h b/include/configs/io.h
index f05eb0a..0dd7f00 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -62,10 +62,8 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_DTT
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 
 /*
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index f75ca76..4d1f309 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -64,7 +64,6 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_FPGAD
 #undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 
 /*
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 4f0aa69..869d8c4 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -253,10 +253,8 @@
  */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
@@ -264,9 +262,7 @@
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
 #endif
 
 #define CONFIG_CMD_NAND
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index ea9d8b0..636f6bd 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -106,14 +106,11 @@
 #define CONFIG_CMD_BMP		/* BMP support */
 #endif
 #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
-#define CONFIG_CMD_DHCP		/* DHCP Support */
 #define CONFIG_CMD_FAT		/* FAT support */
-#define CONFIG_CMD_I2C		/* I2C serial bus support */
 #define CONFIG_CMD_IDE		/* IDE harddisk support */
 #define CONFIG_CMD_IRQ		/* irqinfo */
 #define CONFIG_CMD_MII		/* MII support */
 #define CONFIG_CMD_PCI		/* pciinfo */
-#define CONFIG_CMD_USB		/* USB Support */
 
 #define CONFIG_SYS_LOWBOOT	1
 
@@ -291,8 +288,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
 
-#define CONFIG_LOOPW
-
 /*
  * Various low-level settings
  */
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 59dbb20..30ef13f 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -24,7 +24,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -41,15 +40,12 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE		(4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
@@ -61,7 +57,6 @@
 #define CONFIG_CMD_PCI
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 09f308f..ce92e78 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -86,7 +86,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_SNTP
 
 #if defined(CONFIG_PCI)
 #define CODFIG_CMD_PCI
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 664896b..f5dddae 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -179,7 +179,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
 
 #define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 1087902..15029f9 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -80,7 +80,6 @@
 #define CONFIG_SYS_I2C_OMAP24XX
 #define CONFIG_I2C_MULTI_BUS
 
-#define CONFIG_CMD_I2C
 
 /*
  * Flash
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 1990b2d..227504f 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -369,7 +369,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
 
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
 
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index ab727aa..dd0cec4 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -14,14 +14,11 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DEFAULTENV_VARS
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MTDPARTS
 
@@ -55,9 +52,6 @@
 #define CONFIG_LOADS_ECHO
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "Hit <SPACE> key to stop autoboot in %2ds\n"
-#define CONFIG_AUTOBOOT_STOP_STR        " "
 
 /* Support the IVM EEprom */
 #define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index dfc1c7e..fdd293f 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -41,7 +41,6 @@
 #include "keymile-common.h"
 
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_SF
 
 /* SPI NOR Flash default params, used by sf commands */
 #define CONFIG_SF_DEFAULT_SPEED		8100000
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 44829e8..9232ee3 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -285,7 +285,6 @@ int get_scl(void);
  * eSPI - Enhanced SPI
  */
 #define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         20000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index caeb14d..685f0e5 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -65,7 +65,6 @@
 #define CONFIG_SYS_TMU_CLK_DIV	4
 
 /* i2c */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE	0x7F
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 6c9eed4..bf283fe 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -125,15 +125,12 @@
 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
 
 /* Ether */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_BASE	(0x10000000)
 #define CONFIG_SMC911X_32_BIT
 #define CONFIG_NFS_TIMEOUT 10000UL
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 12fef29..18cd4bb 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -54,13 +54,8 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
-#define CONFIG_CMD_USB
 #endif
 
 /*
@@ -94,15 +89,7 @@
 #undef CONFIG_ENV_SPI_MAX_HZ
 #undef CONFIG_SYS_IDE_MAXBUS
 #undef CONFIG_SYS_IDE_MAXDEVICE
-#undef CONFIG_SYS_PROMPT
 #define CONFIG_ENV_SPI_MAX_HZ           20000000 /* 20Mhz */
-#if defined(CONFIG_D2NET_V2)
-#define CONFIG_SYS_PROMPT		"d2v2> "
-#elif defined(CONFIG_NET2BIG_V2)
-#define CONFIG_SYS_PROMPT		"2big2> "
-#else
-#define CONFIG_SYS_PROMPT		"ns2> "
-#endif
 
 /*
  * Enable platform initialisation via misc_init_r() function
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index ee458d3..a2a337d 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -128,7 +128,6 @@
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 
 #define CONFIG_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_DAVINCI_SPI
 #define CONFIG_SYS_SPI_BASE		DAVINCI_SPI0_BASE
 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
@@ -211,17 +210,14 @@
  * U-Boot commands
  */
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
 #define CONFIG_CLOCKS
 #endif
 
-#define CONFIG_CMD_SPI
 
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 134cb08..3cbb522 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -395,7 +395,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * I2C
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -431,7 +430,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* DM SPI */
 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_CMD_SF
 #define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH_DATAFLASH
 #endif
@@ -461,7 +459,6 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 #endif
@@ -560,17 +557,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_PCI
 #endif
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#undef CONFIG_CMD_IMLS
-#endif
-
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
@@ -613,8 +604,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 4654f67..1fd9e03 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -64,7 +64,6 @@
 #endif
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 #endif
@@ -281,7 +280,6 @@
 /*
  * I2C
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -320,7 +318,6 @@
 
 /* DM SPI */
 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_CMD_SF
 #define CONFIG_DM_SPI_FLASH
 #endif
 
@@ -409,17 +406,11 @@
 #define CONFIG_CMD_PCI
 #endif
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#undef CONFIG_CMD_IMLS
-#endif
-
 #define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
@@ -458,8 +449,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 8aa557f..d84c734 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -135,7 +135,6 @@
 #endif
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1
@@ -176,9 +175,7 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_PING
 
 /*  MMC  */
 #define CONFIG_MMC
@@ -194,7 +191,6 @@
 /*  DSPI  */
 #define CONFIG_FSL_DSPI
 #ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
 #define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
 #define CONFIG_SPI_FLASH_SST		/* cs1 */
@@ -270,7 +266,6 @@
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 7b79295..5c3ece8 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -229,7 +229,6 @@ unsigned long get_board_ddr_clk(void);
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
 #endif
 
 /*
@@ -397,7 +396,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 #endif
@@ -407,15 +405,12 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_PBSIZE		\
 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index bc40b06..7c662a3 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -283,7 +283,6 @@
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 #endif
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index aee8e5e..648a6ff 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -89,7 +89,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -214,11 +213,9 @@ unsigned long long get_qixis_addr(void);
 
 /* Command line configuration */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 91fad0a..c40f0f2 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -283,7 +283,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #endif
 
@@ -395,7 +394,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 15a1172..4aed2de 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -272,7 +272,6 @@ unsigned long get_board_sys_clk(void);
 
 /* SPI */
 #ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
 #endif
@@ -327,7 +326,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index f9ada1a..0ce422e 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -51,16 +51,10 @@
  * Commands configuration
  */
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FS_GENERIC
 
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index ebc0f8b..0b1788f 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -403,14 +403,11 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
@@ -419,7 +416,6 @@
 #endif
 
 #ifdef CONFIG_440EPX
-#define CONFIG_CMD_USB
 #endif
 
 /*
@@ -446,7 +442,6 @@
 #define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 57599f9..0a537ce 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -24,22 +24,16 @@
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_USB
 #define	CONFIG_VIDEO
 
 
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 5763ae3..600eea0 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -31,20 +31,16 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
-#define CONFIG_CMD_USB
 #define CONFIG_VIDEO
 
 
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index df141c9..2429e3a 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -25,7 +25,6 @@
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -33,9 +32,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_USB
 
 /*
  * Memory configurations
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index fd4c26e..dcfe3d7 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -236,7 +236,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
 
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 7f93b94..04dca71 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -53,16 +53,6 @@
 #define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
 #define CONFIG_SYS_BOOTM_LEN		(64 * 1024 * 1024)
 
-/*
- * Console configuration
- */
-#undef CONFIG_SYS_PROMPT
-#if defined(CONFIG_SYS_LITTLE_ENDIAN)
-#define CONFIG_SYS_PROMPT		"maltael # "
-#else
-#define CONFIG_SYS_PROMPT		"malta # "
-#endif
-
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -116,10 +106,8 @@
  * Commands
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 
 #define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
 
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index 3c081a2..20457f6 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -23,15 +23,11 @@
  */
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DISPLAY
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_SNTP
 
 /*
  * 8-symbol LED display (can be accessed with 'display' command)
@@ -113,6 +109,5 @@
 /*
  * Enable loopw command.
  */
-#define CONFIG_LOOPW
 
 #endif /* __MANROLAND_COMMON_H */
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 43d7fd0..fed310f 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -24,14 +24,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
-#define CONFIG_CMD_TIME
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 6bd6933..01f1d83 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -114,13 +114,9 @@
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 61a4a8e..46453c4 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -292,10 +292,7 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
 
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index 4c05fc8..8a24cfb 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -38,14 +38,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 76b2e1d..e7d2694 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -85,13 +85,7 @@
 /*
  * Command line configuration.
  */
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_IMLS
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 #ifdef CONFIG_SYS_USE_NANDFLASH
 #define CONFIG_CMD_NAND
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 09bfabc..cdaf828 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -193,7 +193,6 @@
 
 #else
 #if defined(SPIFLASH)
-# define CONFIG_CMD_SF
 
 # if !defined(RAMENV)
 #  define CONFIG_CMD_SAVES
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 53907f9..f4b0e34 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -37,16 +37,13 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 1b2e029..9cc940c 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -379,7 +379,6 @@
 /*
  * USB  Support
  */
-#define CONFIG_CMD_USB
 
 #if defined(CONFIG_CMD_USB)
 #define CONFIG_USB_EHCI				/* Enable EHCI Support	*/
@@ -412,14 +411,11 @@
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #undef CONFIG_CMD_FUSE
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index bf7f745..149f365 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -388,11 +388,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 12bb3a0..f983f2d 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -13,7 +13,6 @@
 #define CONFIG_MS7722SE		1
 
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SDRAM
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 0601256..438497e 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -28,7 +28,6 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index e6a08d1..705bee8 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -16,12 +16,10 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_LED
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB
 
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 92f8f86..4936733 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -22,7 +22,6 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_VIDEO
 
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index a85855d..cc86c94 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -111,7 +111,6 @@
 #define CONFIG_DOS_PARTITION
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -123,8 +122,6 @@
 
 /* Ethernet Configs */
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 #define CONFIG_BOOTDELAY	1
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 4d86c13..36a5063 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -22,17 +22,12 @@
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 5f94e19..78aa22b 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -63,9 +63,6 @@
 /***********************************************************
  * Command definition
  ***********************************************************/
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
 
 #define CONFIG_BOOTDELAY	3
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 3813e25..75d24bf 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -81,9 +81,6 @@
  * Command definition
  ***********************************************************/
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_BOOTZ
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index f7a050e..9e736eb 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -80,8 +80,6 @@
  * Command definition
  */
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_DNS
@@ -89,13 +87,10 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_CACHE
 
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_MII
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 125d25d..2f75f2b 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -49,7 +49,6 @@
 /*
  * SPI Configs
  * */
-#define CONFIG_CMD_SPI
 
 #define CONFIG_MXC_SPI
 
@@ -87,12 +86,9 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX5
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 033a542..0eb5203 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -47,7 +47,6 @@
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -69,8 +68,6 @@
 #define CONFIG_HAS_ETH1
 #define CONFIG_MII
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index a41c778..46f93b9 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -36,7 +36,6 @@
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -69,8 +68,6 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 7f9e3b4..8d2581a 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -55,12 +55,9 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX5
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index e851da2..f5019c2 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -35,7 +35,6 @@
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -61,8 +60,6 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index c6996e2..ffd13ca 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -79,7 +79,6 @@
 #define CONFIG_CMD_FAT
 
 /* Miscellaneous configurable options */
-#undef CONFIG_CMD_IMLS
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 4feb121..70760a1 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -27,8 +27,6 @@
 
 /* Ethernet Configuration */
 #define CONFIG_FEC_MXC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -56,7 +54,6 @@
 #define CONFIG_CONSOLE_MUX
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 86a0316..60c07cf 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -23,8 +23,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define	CONFIG_FEC_MXC
 #define	CONFIG_MII
@@ -132,7 +130,6 @@
 #define CONFIG_SYS_MMC_ENV_DEV		1
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 1c99805..6039fc4 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -16,7 +16,6 @@
 #define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -48,7 +47,6 @@
 #endif
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 87bbf2e..072003c 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -24,8 +24,6 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -37,7 +35,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
-#define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index bfc4f61..25f51be 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -40,7 +40,6 @@
 #endif
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -55,7 +54,6 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 6423796..cc73684 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -32,7 +32,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -46,8 +45,6 @@
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -168,7 +165,6 @@
 #define CONFIG_ENV_IS_IN_MMC
 #endif
 
-#define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS		0
@@ -178,7 +174,6 @@
 #endif
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 2e739f9..14acea9 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -120,7 +120,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -151,8 +150,6 @@
 #define CONFIG_APBH_DMA_BURST8
 
 /* Network */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 #define CONFIG_FEC_MXC
@@ -168,7 +165,6 @@
 #define CONFIG_PHY_ATHEROS
 
 
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -183,11 +179,9 @@
 
 #define CONFIG_IMX_THERMAL
 
-#define CONFIG_CMD_TIME
 
 #define CONFIG_FSL_QSPI
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SYS_FSL_QSPI_AHB
 #define CONFIG_SF_DEFAULT_BUS		0
 #define CONFIG_SF_DEFAULT_CS		0
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index fdf2396..c28a747 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -29,7 +29,6 @@
 #ifdef CONFIG_IMX_BOOTAUX
 /* Set to QSPI2 B flash at default */
 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
-#define CONFIG_CMD_SETEXPR
 
 #define UPDATE_M4_ENV \
 	"m4image=m4_qspi.bin\0" \
@@ -149,7 +148,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -164,8 +162,6 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* Network */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -180,7 +176,6 @@
 #define CONFIG_PHY_ATHEROS
 
 
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -205,11 +200,9 @@
 
 #define CONFIG_IMX_THERMAL
 
-#define CONFIG_CMD_TIME
 
 
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SYS_FSL_QSPI_LE
 #define CONFIG_SYS_FSL_QSPI_AHB
 #ifdef CONFIG_MX6SX_SABRESD_REVA
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 2fff34a..eb92138 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -50,7 +50,6 @@
 #endif
 
 /* I2C configs */
-#define CONFIG_CMD_I2C
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
@@ -154,7 +153,6 @@
 	   "else run netboot; fi"
 
 /* Miscellaneous configurable options */
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
 
@@ -196,7 +194,6 @@
 
 #define CONFIG_FSL_QSPI
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_BUS		0
@@ -209,7 +206,6 @@
 #endif
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 05c5281..bf6bae6 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -52,7 +52,6 @@
 #define CONFIG_CMD_FAT
 
 /* Miscellaneous configurable options */
-#undef CONFIG_CMD_IMLS
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index ad87b24..5f63a1f 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -52,11 +52,7 @@
 #undef CONFIG_BOOTM_PLAN9
 #undef CONFIG_BOOTM_RTEMS
 
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-
 /* I2C configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -68,7 +64,6 @@
 #ifdef CONFIG_IMX_BOOTAUX
 /* Set to QSPI1 A flash at default */
 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
-#define CONFIG_CMD_SETEXPR
 
 #define UPDATE_M4_ENV \
 	"m4image=m4_qspi.bin\0" \
@@ -185,7 +180,6 @@
 		   "fi; " \
 	   "else run netboot; fi"
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
 
@@ -244,7 +238,6 @@
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX7
 #define CONFIG_USB_STORAGE
@@ -285,7 +278,6 @@
 #endif
 
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_MACRONIX
 #define CONFIG_SPI_FLASH_BAR
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index d4bea63..96ee7ec 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -44,11 +44,8 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IDE
 #define CONFIG_SYS_LONGHELP
diff --git a/include/configs/neo.h b/include/configs/neo.h
index bd2b190..3121c03 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -61,10 +61,8 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_DTT
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_DIAG
 #undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 
 /*
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index cb249c0..7696b53 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -27,7 +27,6 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	       UART2_BASE
 
-#define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  0
@@ -37,7 +36,6 @@
 #endif
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -66,8 +64,6 @@
 #define CONFIG_LIBATA
 #endif
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -80,7 +76,6 @@
 #define CONFIG_PHY_MICREL_KSZ9021
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -313,8 +308,6 @@
 
 #define CONFIG_CMD_BMP
 
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_ALT_MEMTEST
 
 /*
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 7a1ce3c..c6353e0 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -128,7 +128,6 @@
 #define CONFIG_CMD_EXT4			/* EXT4 Support */
 #define CONFIG_CMD_FAT			/* FAT support */
 
-#define CONFIG_CMD_I2C			/* I2C serial bus support */
 #define CONFIG_CMD_MMC			/* MMC support */
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index d58c95f..8b6e93e 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -21,16 +21,11 @@
 /* U-Boot Commands */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BMODE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_FAT_WRITE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_USB
 #define CONFIG_VIDEO
 
 /* U-Boot general configurations */
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index 0b6173b..49e5eae 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -23,7 +23,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -48,22 +47,18 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED        24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #define CONFIG_KEYBOARD
 
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 724c33d..1b06719 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -77,10 +77,7 @@
  */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #endif
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 9d764d5..0b691e4 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -180,7 +180,6 @@
 	"fdtaddr=40800000\0"
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
 #define CONFIG_SYS_I2C_S3C24X0_SLAVE	0
@@ -194,14 +193,11 @@
 
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
 #define CONFIG_USB_STORAGE
 
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 3fa8d7e..d7e6c37 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -71,7 +71,6 @@
 #define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
 
 /* USB EHCI */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 
 #define CONFIG_USB_EHCI_OMAP
@@ -100,7 +99,6 @@
 #define CONFIG_USB_STORAGE	/* USB storage support		*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_LED		/* LED support			*/
-#define CONFIG_CMD_DHCP
 
 #define CONFIG_VIDEO_OMAP3	/* DSS Support			*/
 
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index c831f36..8048ce8 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -30,11 +30,8 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 /* ----------------------------------------------------------------------------
  * Supported U-Boot features
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 0f16a6e..99dab5f 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -146,7 +146,6 @@
 #ifdef CONFIG_USB_OMAP3
 
 #ifdef CONFIG_USB_MUSB_HCD
-#define CONFIG_CMD_USB
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 5e33845..8e438e9 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -73,8 +73,6 @@
 #ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_CMD_ONENAND	/* ONENAND support		*/
 #endif
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 #ifndef CONFIG_SPL_BUILD
 
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 0cb62e9..9aaab01 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -69,8 +69,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 /* I2C */
 #define CONFIG_SYS_I2C_OMAP34XX
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 3b1e5d7..5db5dcf 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -57,7 +57,6 @@
 
 /* commands to include */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_NAND
 #define CONFIG_CMD_UBI		/* UBI-formated MTD partition support */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index a59fd42..e9e8da8 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -77,8 +77,6 @@
 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
 #endif
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 #undef CONFIG_SYS_I2C_OMAP24XX
 #define CONFIG_SYS_I2C_OMAP34XX
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 15f3eec..3e7096e 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -17,7 +17,6 @@
  */
 
 /* USB UHH support options */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
@@ -33,8 +32,6 @@
 
 #define CONFIG_UBOOT_ENABLE_PADS_ALL
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 #include <configs/ti_omap4_common.h>
 
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 10b97a0..a794662 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -88,7 +88,6 @@
 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
 
 /* USB UHH support options */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
@@ -107,7 +106,6 @@
 #define CONFIG_DFU_MMC
 
 /* Enabled commands */
-#define CONFIG_CMD_DHCP		/* DHCP Support			*/
 
 /* USB Networking options */
 #define CONFIG_USB_HOST_ETHER
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index a4b26d2..be93ca3 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -211,19 +211,15 @@
  */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 #ifdef CONFIG_CMD_BDI
 #define CONFIG_CLOCKS
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
 #endif
 
 #ifdef CONFIG_USE_NAND
@@ -239,8 +235,6 @@
 #endif
 
 #ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #endif
 
 #if !defined(CONFIG_USE_NAND) && \
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
index 62f15b7..6eb7e6e 100644
--- a/include/configs/openrd.h
+++ b/include/configs/openrd.h
@@ -45,13 +45,10 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_IDE
 
 /*
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index 28e4275..f7c3aaa 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -117,8 +117,6 @@
 #define CONFIG_CMD_BSP
 
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 #define CONFIG_LMB
 
diff --git a/include/configs/origen.h b/include/configs/origen.h
index fa71874..4f14357 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -50,8 +50,6 @@
 #define S5P_CHECK_DIDLE			0xBAD00000
 #define S5P_CHECK_LPA			0xABAD0000
 
-#undef CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_BOOTZ
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 879ad58..100d634 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -21,7 +21,6 @@
 #define CONFIG_MXC_UART_BASE           UART1_BASE
 
 /* SF Configs */
-#define CONFIG_CMD_SF
 #define CONFIG_SPI
 #define CONFIG_MXC_SPI
 #define CONFIG_SF_DEFAULT_BUS  2
@@ -37,7 +36,6 @@
 #define CONFIG_CMD_PCA953X_INFO
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -58,7 +56,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -92,8 +89,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 15b8164..5e63b0c 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -696,7 +696,6 @@
 #define CONFIG_HARD_SPI
 
 #if defined(CONFIG_SPI_FLASH)
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED	10000000
 #define CONFIG_SF_DEFAULT_MODE	0
 #endif
@@ -872,8 +871,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_REGINFO
@@ -887,7 +884,6 @@
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 732b36f..bba75ab 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -401,8 +401,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
@@ -415,7 +413,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_USB_EHCI
 
 #ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
index 9ca29f8..c4a5799 100644
--- a/include/configs/p2371-0000.h
+++ b/include/configs/p2371-0000.h
@@ -20,7 +20,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -37,22 +36,18 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE		(4 << 20)
 
 /* USB2.0 Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h
index c55f07e..3bf3b56 100644
--- a/include/configs/p2371-2180.h
+++ b/include/configs/p2371-2180.h
@@ -20,7 +20,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -37,15 +36,12 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE		(4 << 20)
 
 /* USB2.0 Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
@@ -57,7 +53,6 @@
 #define CONFIG_CMD_PCI
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/p2571.h b/include/configs/p2571.h
index d35e255..95d2d63 100644
--- a/include/configs/p2571.h
+++ b/include/configs/p2571.h
@@ -21,7 +21,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -38,22 +37,18 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE		(4 << 20)
 
 /* USB2.0 Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 6acecb1..e7b084a 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -38,14 +38,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index f490e79..f094850 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -172,9 +172,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 #undef CONFIG_CMD_FAT
 #undef CONFIG_CMD_IDE
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index b4a7225..3a9b8f3 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -51,9 +51,7 @@ Serial console configuration
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 4638c25..d555455 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -97,7 +97,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
 					+ (8 * 1024 * 1024))
 
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		24000000
 
 #define CONFIG_CONS_INDEX		1
@@ -148,7 +147,6 @@
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 
 #ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index edc555f..356cd79 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -33,8 +33,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE			115200
 
-#undef CONFIG_CMD_IMLS
-
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
@@ -83,8 +81,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -97,7 +93,6 @@
 /* QSPI Configs*/
 
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH
 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
 #define FSL_QSPI_FLASH_NUM		2
@@ -105,7 +100,6 @@
 #endif
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC_I2C3
 #define CONFIG_SYS_I2C_MXC
@@ -221,7 +215,6 @@
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80010000
 #define CONFIG_SYS_MEMTEST_END		0x87C00000
 
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index f2c05f8..ff3f53d 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -382,11 +382,8 @@
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
 #undef CONFIG_CMD_FUSE
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index b75dbee..733ff28 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -204,7 +204,6 @@
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 
 #if defined(CONFIG_USB_MUSB_HOST)
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 54ebcba..118316b 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -83,9 +83,6 @@
 
 /* No NOR flash */
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS	2
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
index bb7e845..4f78a3d 100644
--- a/include/configs/platinum.h
+++ b/include/configs/platinum.h
@@ -22,17 +22,12 @@
  */
 
 #define CONFIG_CMD_BMODE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_TIME
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_USB
 
 /*
  * Hardware configuration
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 4590063..0f79472 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -38,14 +38,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-post.h"
 
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 407b83d..f883ca3 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -183,10 +183,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_USB		1
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS			1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index f6886a6..0fb0a36 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -197,10 +197,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_USB		1
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS	1
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 53fdaa7..ba9e6d3 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -72,10 +72,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_USB		1
 
 #define CONFIG_CMD_JFFS2		1
 #define CONFIG_JFFS2_CMDLINE		1
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index b1a3dc7..6314365 100644
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -33,12 +33,9 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/porter.h b/include/configs/porter.h
index e34cd05..1e7f48d 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -69,7 +69,6 @@
 #define CONFIG_SYS_TMU_CLK_DIV	4
 
 /* i2c */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE		0x7F
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index a9ecf6a..4b0f98b 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -47,7 +47,6 @@
  */
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_DHCP
 
 #define CONFIG_DRIVER_NE2000
 #define CONFIG_DRIVER_NE2000_BASE	0xb4000300
@@ -75,14 +74,6 @@
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
-/* Monitor Command Prompt */
-#undef CONFIG_SYS_PROMPT
-#if defined(CONFIG_SYS_LITTLE_ENDIAN)
-#define CONFIG_SYS_PROMPT		"qemu-mipsel # "
-#else
-#define CONFIG_SYS_PROMPT		"qemu-mips # "
-#endif
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 8258bfe..9e5cbb1 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -47,7 +47,6 @@
  */
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_DHCP
 
 #define CONFIG_DRIVER_NE2000
 #define CONFIG_DRIVER_NE2000_BASE	0xffffffffb4000300
@@ -70,21 +69,12 @@
 
 #define CONFIG_SYS_IDE_MAXDEVICE	4
 
-#define CONFIG_CMD_RARP
 
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
-/* Monitor Command Prompt */
-#undef CONFIG_SYS_PROMPT
-#if defined(CONFIG_SYS_LITTLE_ENDIAN)
-#define CONFIG_SYS_PROMPT		"qemu-mips64el # "
-#else
-#define CONFIG_SYS_PROMPT		"qemu-mips64 # "
-#endif
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 5542352..15f906a 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -142,11 +142,9 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index b1d79fd..88fe641 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -18,7 +18,6 @@
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
@@ -48,7 +47,6 @@
 
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SH_SH7734_I2C	1
 #define CONFIG_HARD_I2C			1
 #define CONFIG_I2C_MULTI_BUS	1
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 82e7a89..daf7e22 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -13,7 +13,6 @@
  */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index e2da244..8add5f8 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -21,7 +21,6 @@
  */
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 6bc33e0..c814189 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -16,13 +16,8 @@
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 368d046..01c3005 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -60,7 +60,6 @@
 #define CONFIG_CMD_PART
 
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_TIME
 
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
@@ -68,12 +67,9 @@
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH_GIGADEVICE
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
-#define CONFIG_CMD_I2C
 
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 5322685..02cb94b 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -79,8 +79,6 @@
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_GPIO
 
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_NR_DRAM_BANKS		1
@@ -88,11 +86,8 @@
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
-#define CONFIG_CMD_I2C
 
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 19ca606..0fd040f 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -96,7 +96,6 @@
 #define CONFIG_MMC_SDHCI_IO_ACCESSORS
 #define CONFIG_BCM2835_SDHCI
 
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_DWC2
 #ifndef CONFIG_BCM2835
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index 039880b..c7ef864 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -14,7 +14,6 @@
 #define CONFIG_CPU_SH7203	1
 #define CONFIG_RSK7203	1
 
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_CACHE
 
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 25aedc2..c14a247 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -162,7 +162,6 @@
 #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7
 #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6
 
-#define CONFIG_CMD_I2C
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index 427fed9..bdb39a3 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -64,7 +64,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 73de62c..ee3e34d 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -91,7 +91,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 2567502..c4ad3c4 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -76,7 +76,6 @@
 #endif
 
 /* SerialFlash */
-#define CONFIG_CMD_SF
 
 #ifdef CONFIG_CMD_SF
 #define CONFIG_ATMEL_SPI
@@ -125,7 +124,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index e310ee3..a81766a 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
 
 /* SerialFlash */
-#define CONFIG_CMD_SF
 
 #ifdef CONFIG_CMD_SF
 #define CONFIG_ATMEL_SPI
@@ -73,7 +72,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 8af3033..339fcf1 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
 
 /* SerialFlash */
-#define CONFIG_CMD_SF
 
 #ifdef CONFIG_CMD_SF
 #define CONFIG_ATMEL_SPI
@@ -73,7 +72,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index d489b1d..4b8fe16 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -82,11 +82,8 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 /* SPI - enable all SPI flash types for testing purposes */
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_SF_TEST
-#define CONFIG_CMD_SPI
 
-#define CONFIG_CMD_I2C
 #define CONFIG_I2C_EDID
 #define CONFIG_I2C_EEPROM
 
@@ -124,12 +121,7 @@
 
 #define CONFIG_KEEP_SERVERADDR
 #define CONFIG_UDP_CHECKSUM
-#define CONFIG_CMD_LINK_LOCAL
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DNS
-#define CONFIG_CMD_SNTP
 #define CONFIG_TIMESTAMP
-#define CONFIG_CMD_RARP
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
@@ -205,7 +197,6 @@
 #define CONFIG_LZMA
 
 #define CONFIG_CMD_LZMADEC
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_DATE
 
 #endif
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index c8f4542..f6e07b4 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -18,10 +18,7 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_VIDEO
-#define CONFIG_CMD_MEMTEST
 
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 05ddb3a..37fdeaa 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -408,9 +408,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 2c074a1..7e5cdfb 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -526,8 +526,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index e3c1250..298e3ee 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -467,8 +467,6 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 6642b3f..9ec8417 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -20,13 +20,10 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 0611213..54aeb5b 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -30,7 +30,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -48,14 +47,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* Enable keyboard */
 #define CONFIG_TEGRA_KEYBOARD
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
index 703f4fc..d4bba6d 100644
--- a/include/configs/secomx6quq7.h
+++ b/include/configs/secomx6quq7.h
@@ -32,8 +32,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 /* Ethernet Configuration */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index f32459b..7ca7afa 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -236,7 +236,6 @@
 #define CONFIG_CMD_SDRAM
 
 #ifdef CONFIG_440EPX
-#define CONFIG_CMD_USB
 #endif
 
 #ifndef CONFIG_RAINIER
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index fc9d246..58f9540 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -17,10 +17,8 @@
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7752evb/u-boot.lds"
 
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
 #define CONFIG_CMD_MMC
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 31dd984..540d36c 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -17,10 +17,8 @@
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7753evb/u-boot.lds"
 
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
 #define CONFIG_CMD_MMC
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 26d70f4..298d3a2 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -18,9 +18,7 @@
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7757lcr/u-boot.lds"
 
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
 #define CONFIG_CMD_MMC
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 0fd2caf..9f6fe0e 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -19,7 +19,6 @@
  */
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_JFFS2
 
 #define CONFIG_BOOTDELAY        -1
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index e85256d..e5ba30a 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -14,11 +14,9 @@
 #define CONFIG_SH7785LCR	1
 
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SH_ZIMAGEBOOT
 
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
diff --git a/include/configs/shmin.h b/include/configs/shmin.h
index 11ae15c..897ba1d 100644
--- a/include/configs/shmin.h
+++ b/include/configs/shmin.h
@@ -16,7 +16,6 @@
 /* #define CONFIG_T_SH7706LSR	1 */
 
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 6af373e..b4aa283 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -41,7 +41,6 @@
 /* commands to include */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_TIME
 
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
@@ -95,7 +94,6 @@
 #define CONFIG_SPI
 #define CONFIG_OMAP3_SPI
 #define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		(75000000)
 
  /* Physical Memory Map */
@@ -124,7 +122,6 @@
 
 /* I2C Configuration */
 #define CONFIG_I2C
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
@@ -228,7 +225,6 @@
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 #ifdef CONFIG_USB_MUSB_HOST
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #endif
 
@@ -273,8 +269,6 @@
 /* Unsupported features */
 #undef CONFIG_USE_IRQ
 
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_DRIVER_TI_CPSW
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE
diff --git a/include/configs/silk.h b/include/configs/silk.h
index 93c3d0d..a3790f0 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -69,7 +69,6 @@
 #define CONFIG_SYS_TMU_CLK_DIV  4
 
 /* i2c */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SH
 #define CONFIG_SYS_I2C_SLAVE		0x7F
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index b1760cc..54701f3 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -149,7 +149,6 @@
 
 #if !defined(CONFIG_SPL_BUILD)
 /* USB configuration */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL
 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #define CONFIG_USB_OHCI_NEW
@@ -214,21 +213,12 @@
 	"mtdparts="MTDPARTS_DEFAULT"\0"
 
 /* Command line & features configuration */
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
 
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_FAT
 
 #ifdef CONFIG_MACB
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
 #else
-# undef CONFIG_CMD_BOOTD
-# undef CONFIG_CMD_NET
-# undef CONFIG_CMD_NFS
 #endif /* CONFIG_MACB */
 
 #ifdef CONFIG_SPL_BUILD
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 34858cd..6b460bf 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -77,11 +77,8 @@
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_USB
 
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 856bf7d..63f6204 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -41,8 +41,6 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 /* MMC SPL */
 #define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 3674e91..bff49b1 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -145,11 +145,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
 
 /* Command line configuration */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCA953X
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 2785925..3fbc2be 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -88,7 +88,6 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_I2C_MULTI_BUS
 
-#define CONFIG_CMD_I2C
 
 /*
  * Flash
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 153f9f8..6cdf38b 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -18,7 +18,6 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -26,8 +25,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
 /* Memory configurations */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2b65241..9b2313c 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -89,8 +89,6 @@
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED		30000000
 /*
  * The base address is configurable in QSys, each board must specify the
@@ -197,7 +195,6 @@
 unsigned int cm_get_l4_sp_clk_hz(void);
 #define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
 #endif
-#define CONFIG_CMD_I2C
 
 /*
  * QSPI support
@@ -216,12 +213,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
 #endif
 #define CONFIG_CQSPI_DECODER		0
-#define CONFIG_CMD_SF
 
 /*
  * Designware SPI support
  */
-#define CONFIG_CMD_SPI
 
 /*
  * Serial Driver
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index d7c339e..bf75e0f 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -18,7 +18,6 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -26,8 +25,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
 /* Memory configurations */
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 314b9bf..90592a8 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -18,7 +18,6 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -26,8 +25,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
 /* Memory configurations */
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index f260a64..f1cfe21 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -18,7 +18,6 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -26,8 +25,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
 /* Memory configurations */
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 07cfcbf..7ac5889 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -18,7 +18,6 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -26,8 +25,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
 /* Memory configurations */
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index 02ea0c5..e2ed253 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -18,7 +18,6 @@
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
@@ -26,8 +25,6 @@
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_USB_MASS_STORAGE
 
 /* Memory configurations */
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index e43b5cf..fb98546 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -20,20 +20,13 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TIME
 
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 60f8291..f45d91f 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -310,16 +310,11 @@
  */
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index a309448..63a5b70 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -99,13 +99,10 @@
 /*
  * Command support defines
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 
 /*
  * Default Environment Varible definitions
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 00f293a..d53f8c1 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -93,6 +93,5 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_CMD_MEM
-#define CONFIG_CMD_TIMER
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 1511959..9d1f02e 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -79,6 +79,4 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_CMD_MEM
-#define CONFIG_CMD_TIMER
-#undef CONFIG_CMD_IMLS
 #endif /* __CONFIG_H */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index ec5fbe9..2c1d4fb 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -40,7 +40,6 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_EXT2
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_ALT_MEMTEST
 
 #define CONFIG_CMD_FPGAD
@@ -507,10 +506,8 @@ int fpga_gpio_get(unsigned int bus, int pin);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 375159e..d3704a4 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -57,12 +57,10 @@
 #define CONFIG_PHY_MICREL
 
 /* Command support defines */
-#define CONFIG_CMD_PING
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 
 #define CONFIG_SYS_MEMTEST_START               0x0000
 #define CONFIG_SYS_MEMTEST_END                 1024*1024
-#define CONFIG_CMD_MEMTEST
 
 /* Misc configuration */
 #define CONFIG_SYS_LONGHELP
@@ -77,9 +75,7 @@
 #ifdef CONFIG_OF_CONTROL		/* QSPI is controlled via DT */
 #define CONFIG_CQSPI_DECODER		0
 #define CONFIG_CQSPI_REF_CLK		((30/4)/2)*1000*1000
-#define CONFIG_CMD_SPI
 
-#define CONFIG_CMD_SF
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 9c6c9b6..bd16ff9 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -236,7 +236,6 @@
 #define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_SYS_I2C_SPEED		400000
 #define CONFIG_SYS_I2C_SLAVE		0x7f
-#define CONFIG_CMD_I2C
 #endif
 
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 0eed861..be68fac 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -257,13 +257,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 1426fbf..b270d9d 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -97,15 +97,11 @@
 
 /* commands to include */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_EEPROM
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index ee9fc7d..38f3446 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -102,11 +102,8 @@
 					"1920k(u-boot),128k(u-boot-env),"\
 					"4m(kernel),-(fs)"
 
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_I2C
@@ -276,7 +273,6 @@
  */
 
 /* USB EHCI */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 405ed72..d389752 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -69,8 +69,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
 
 /*
@@ -135,7 +133,6 @@
 #define CONFIG_USB_GADGET_AT91
 
 /* DFU class support */
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
@@ -147,8 +144,6 @@
 
 /* SPI EEPROM */
 #define CONFIG_SPI
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_ATMEL_SPI
 #define TAURUS_SPI_MASK (1 << 4)
 #define TAURUS_SPI_CS_PIN	AT91_PIN_PA3
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 62b9de3..870406b 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -65,8 +65,6 @@
 /*
  * Command line configuration
  */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		16
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index d0734a7..bd4d98e 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -56,8 +56,6 @@
 
 /* *** Command definition *** */
 #define CONFIG_CMD_BMODE
-#define CONFIG_CMD_MEMTEST
-#define CONFIG_CMD_TIME
 
 /* Filesystems / image support */
 #define CONFIG_EFI_PARTITION
@@ -69,8 +67,6 @@
 
 /* Ethernet */
 #define CONFIG_FEC_MXC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -118,7 +114,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -148,13 +143,11 @@
 /* RTC */
 #define CONFIG_CMD_DATE
 #ifdef CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
 #define CONFIG_RTC_DS1307
 #define CONFIG_SYS_RTC_BUS_NUM		2
 #endif
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index 019e32c..d131c17 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -19,7 +19,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -37,22 +36,18 @@
 #define CONFIG_TEGRA_SLINK_CTRLS       6
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED        24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* Tag support */
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/tec.h b/include/configs/tec.h
index a947214..976f9c1 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -38,14 +38,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* LCD support */
 #define CONFIG_SYS_WHITE_ON_BLACK
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index b6b8ffc..a1daf8c 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -112,7 +112,6 @@
 #undef CONFIG_SYS_I2C_TEGRA
 #endif
 #ifdef CONFIG_CMD_I2C
-#undef CONFIG_CMD_I2C
 #endif
 
 /* remove MMC support */
@@ -166,7 +165,6 @@
 #undef CONFIG_USB_STORAGE
 #endif
 #ifdef CONFIG_CMD_USB
-#undef CONFIG_CMD_USB
 #endif
 
 /* remove part command support */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 4f1a5f3..4183867 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -30,9 +30,7 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_SATA
-#define CONFIG_CMD_TIME
 
 /*
  * The debugging version enables USB support via defconfig.
@@ -40,11 +38,7 @@
  * interfaces / features.
  */
 #ifdef CONFIG_USB
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_TFTPPUT
 #endif
 
 /* I2C */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 9897a0b..4dfbd82 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -210,8 +210,6 @@
 #undef CONFIG_USE_IRQ
 
 /* Ethernet */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_DRIVER_TI_CPSW
 #define CONFIG_MII
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 4535b8c..049b92a 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -30,7 +30,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* Network defines. */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
@@ -38,7 +37,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_CMD_PING
 #define CONFIG_MII			/* Required in net/eth.c */
 #endif
 
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index d866690..6d77e78 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -110,7 +110,6 @@
 
 /* I2C IP block */
 #define CONFIG_I2C
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 
 /* MMC/SD IP block */
@@ -120,7 +119,6 @@
 
 /* McSPI IP block */
 #define CONFIG_SPI
-#define CONFIG_CMD_SPI
 
 /* GPIO block */
 
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index be3c299..ceebffb 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -205,14 +205,10 @@
 #define CONFIG_USB_PHY_CFG_BASE			KS2_USB_PHY_CFG_BASE
 
 /* U-Boot command configuration */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_USB
 
 /* U-Boot general configuration */
 #define CONFIG_MISC_INIT_R
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index acfa84a..94b2f27 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -30,7 +30,6 @@
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -42,8 +41,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -55,7 +52,6 @@
 #define CONFIG_PHY_MICREL_KSZ9021
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -164,7 +160,6 @@
 /* Enable NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_TIME
 
 #ifdef CONFIG_CMD_NAND
 
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 1fd3f2a..2e729d2 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -44,21 +44,18 @@
 #define CONFIG_MXC_UART
 
 /* SPI */
-#define CONFIG_CMD_SPI
 #define CONFIG_MXC_SPI
 
 /* SPI Flash */
 
 #define TQMA6_SPI_FLASH_SECTOR_SIZE	SZ_64K
 
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_BUS	0
 #define CONFIG_SF_DEFAULT_CS	0
 #define CONFIG_SF_DEFAULT_SPEED	50000000
 #define CONFIG_SF_DEFAULT_MODE	(SPI_MODE_0)
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -91,7 +88,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -101,8 +97,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 #define CONFIG_FEC_MXC
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index 450073c..c67e0bd 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -71,8 +71,6 @@
  * Remove all unused interfaces / commands that are defined in
  * the common header tqms6.h
  */
-#undef CONFIG_CMD_SF
-#undef CONFIG_CMD_SPI
 #undef CONFIG_MXC_SPI
 
 #endif /* __CONFIG_TQMA6_WRU4_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 7caf0ac..2c0e5ed 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -184,7 +184,6 @@
 /* I2C */
 #include <asm/arch/gpio.h>
 
-#define CONFIG_CMD_I2C
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_S3C24X0
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index a5f6c11..bad360e 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -160,7 +160,6 @@
 /* I2C */
 #include <asm/arch/gpio.h>
 
-#define CONFIG_CMD_I2C
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_S3C24X0
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 73f0d84..41cc9fa 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -149,7 +149,6 @@
 /* commands to include */
 #define CONFIG_CMD_EXT2			/* EXT2 Support */
 #define CONFIG_CMD_FAT			/* FAT support */
-#define CONFIG_CMD_I2C			/* I2C serial bus support */
 #define CONFIG_CMD_MMC			/* MMC support */
 #define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands */
 #define CONFIG_CMD_NAND			/* NAND support */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index ca188be..b763eec 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -23,12 +23,9 @@
 
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -47,7 +44,6 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
@@ -59,7 +55,6 @@
 #define CONFIG_CMD_PCI
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-post.h"
 
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 8f3963a..7dc7443 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -55,7 +55,6 @@
  * */
 #define CONFIG_HARD_SPI /* puts SPI: ready */
 #define CONFIG_MXC_SPI /* driver for the SPI controllers*/
-#define CONFIG_CMD_SPI /* SPI serial bus support */
 
 /*
  * MMC Configs
@@ -82,8 +81,6 @@
 #define CONFIG_ETHPRIME		"FEC"
 #define CONFIG_FEC_MXC_PHYADDR	0
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 
 /* allow to overwrite serial and ethaddr */
@@ -96,7 +93,6 @@
  ***********************************************************/
 
 #define CONFIG_CMD_BOOTZ
-#undef CONFIG_CMD_IMLS
 
 /* Environment variables */
 
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 3d0cafa..4437700 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -41,8 +41,6 @@
 
 /* Network support */
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 296ddcd..2202d98 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -59,8 +59,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NAND
 
 /* SDRAM */
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 7e24fc6..d23674c 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -23,7 +23,6 @@
 #include <config_distro_defaults.h>
 
 /* U-Boot commands */
-#define CONFIG_CMD_MEMTEST
 
 /* U-Boot environment */
 #define CONFIG_ENV_OVERWRITE
@@ -54,7 +53,6 @@
 #define CONFIG_GENERIC_MMC
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX5
 #define CONFIG_USB_STORAGE
@@ -63,7 +61,6 @@
 #define CONFIG_MXC_USB_FLAGS	0
 
 /* I2C */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index f154208..870e5a8 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -87,17 +87,13 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 
 
diff --git a/include/configs/vct.h b/include/configs/vct.h
index ea6e3c0..679cd74 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -83,17 +83,13 @@
 /*
  * Commands
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 
 /*
  * Only Premium/Platinum have ethernet support right now
  */
 #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
 	!defined(CONFIG_VCT_SMALL_IMAGE)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
 #endif
 
 /*
@@ -101,7 +97,6 @@
  */
 #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
 	!defined(CONFIG_VCT_SMALL_IMAGE)
-#define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #endif
 
@@ -284,21 +279,15 @@ int vct_gpio_get(int pin);
 #undef CONFIG_CMD_ASKENV
 #undef CONFIG_CMD_BEDBUG
 #undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_I2C
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 #undef CONFIG_CMD_LOADY
 #undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
 #undef CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_SNTP
 #undef CONFIG_CMD_STRINGS
 #undef CONFIG_CMD_TERMINAL
-#undef CONFIG_CMD_USB
 
 #undef CONFIG_SMC911X
 #undef CONFIG_SYS_I2C_SOFT
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 359239c..face83f 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -321,9 +321,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_PCI
 
 #define CONFIG_CMDLINE_EDITING 1
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 75f7268..f413f40 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -21,7 +21,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -38,22 +37,18 @@
 /* SPI */
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED        24000000
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_SIZE          (4 << 20)
 
 /* USB Host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 7f970d0..5c2fe9b 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -36,14 +36,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 /* USB keyboard */
 #define CONFIG_USB_KEYBOARD
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index d066a5a..e924963 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -137,11 +137,9 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_BOOTI
 #define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PXE
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
@@ -172,7 +170,6 @@
 #endif
 
 /* Enable memtest */
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
 
@@ -298,7 +295,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x00040000
 #endif
 
-#define CONFIG_CMD_ARMFLASH
 #define CONFIG_SYS_FLASH_CFI		1
 #define CONFIG_FLASH_CFI_DRIVER		1
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 501b143..67379fd 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -186,7 +186,6 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_CMD_ECHO
 
 #include <config_distro_defaults.h>
 
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 65830b7..d8c45de 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -82,8 +82,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
@@ -96,14 +94,12 @@
 /* QSPI Configs*/
 
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_CMD_SF
 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
 #define FSL_QSPI_FLASH_NUM		2
 #define CONFIG_SYS_FSL_QSPI_LE
 #endif
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -231,7 +227,6 @@
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80010000
 #define CONFIG_SYS_MEMTEST_END		0x87C00000
 
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index 69cb63f..353b17b 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
 
 /* SerialFlash */
-#define CONFIG_CMD_SF
 
 #ifdef CONFIG_CMD_SF
 #define CONFIG_ATMEL_SPI
@@ -76,7 +75,6 @@
 #endif
 
 /* USB */
-#define CONFIG_CMD_USB
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 7a7c92b..f9e6a8d 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -347,9 +347,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DATE
 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 #define CONFIG_SYS_I2C_RTC_ADDR	0x32
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index dd6b519..d07b74f 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -56,7 +56,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
 
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 8fb0abc..7898a81 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -48,7 +47,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -57,8 +55,6 @@
 #define CONFIG_MXC_USB_FLAGS		0
 
 /* Ethernet Configuration */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 4c3df1d..42b728a 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -63,7 +63,6 @@
 #define CONFIG_SYS_SD_VOLTAGE		0x00000080
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -86,7 +85,6 @@
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
 /* I2C Configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index d1404b2..0afa75f 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -84,7 +84,6 @@
 		   "fi; " \
 	   "fi"
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
 
@@ -119,7 +118,6 @@
 #define CONFIG_MMCROOT			"/dev/mmcblk2p2"
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX7
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index ff85964..a5cd38b 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -23,7 +23,6 @@
 
 /* I2C */
 #define CONFIG_SYS_I2C_TEGRA
-#define CONFIG_CMD_I2C
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -46,14 +45,12 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 
 /* General networking support */
-#define CONFIG_CMD_DHCP
 
 #include "tegra-common-post.h"
 
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 4407557..631f273 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -84,9 +84,7 @@
 /*
  * Command definition
  */
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_DNS
@@ -94,8 +92,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_CACHE
 
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SPI
 #define CONFIG_CMD_MII
 
 #define CONFIG_CMD_MMC
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index a35876f..5d8ac41 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -64,8 +64,6 @@
 #define CONFIG_PHY_ADDR 0
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
 
 /*
@@ -74,7 +72,6 @@
 
 #define CONFIG_SYS_I2C_LPC32XX
 #define CONFIG_SYS_I2C
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C_SPEED 350000
 
 /*
@@ -158,7 +155,6 @@
  * SSP/SPI/DISPLAY
  */
 
-#define CONFIG_CMD_SPI
 #define CONFIG_LPC32XX_SSP
 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
 #define CONFIG_CMD_MAX6957
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 9a8a7c7..1cdb10d 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -111,20 +111,16 @@
  */
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_FPGA_LOADMK
 #define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_USB
 #define CONFIG_LZO
 
 /* Filesystem support (for USB key) */
@@ -153,7 +149,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_LOOPW			/* enable loopw command         */
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index a596edd..7cca864 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -102,8 +102,6 @@
 #define CONFIG_CMD_IO
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_TIME
 #define CONFIG_CMD_GETTIME
 #define CONFIG_CMD_SCSI
 
@@ -161,9 +159,7 @@
  * FLASH configuration
  */
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_SF
 #define CONFIG_CMD_SF_TEST
-#define CONFIG_CMD_SPI
 #define CONFIG_SPI
 
 /*-----------------------------------------------------------------------
@@ -193,13 +189,11 @@
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_TFTP_TSIZE
-#define CONFIG_CMD_DHCP
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-#define CONFIG_CMD_USB
 
 /* Default environment */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 83c18f0..8d5ea48 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -18,8 +18,6 @@
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
 #define CONFIG_VIDEO
 
 /* Memory configuration */
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index 5980acb..ec26dc1 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -32,11 +32,7 @@
 #define CONFIG_CMD_REGINFO
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_MTDPARTS
-#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_I2C
 #undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_PING
-#undef CONFIG_CMD_DHCP
 #undef CONFIG_CMD_EEPROM
 
 /*Misc*/
@@ -64,7 +60,6 @@
 					/* decrementer freq: 1 ms ticks */
 #define CONFIG_CMDLINE_EDITING		/* add command line history     */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
-#define CONFIG_LOOPW			/* enable loopw command         */
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE		/* include version env variable */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 980fcb2..be43aa6 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -83,7 +83,6 @@
 
 /* SPI */
 #ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_CMD_SF
 #endif
 
 #if defined(CONFIG_ZYNQ_SDHCI)
@@ -118,7 +117,6 @@
 #define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
-#define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_XHCI_ZYNQMP
 
@@ -193,7 +191,6 @@
 
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
-# define CONFIG_CMD_I2C
 # define CONFIG_SYS_I2C
 # define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
 # define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 4f6084a..f707f57 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -182,15 +182,11 @@ extern void out32(unsigned int, unsigned long);
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 18e342a..d7e696e 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -513,12 +513,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DS4510_INFO
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
@@ -527,9 +525,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PCI_ENUM
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 7284aa2..09f0c3f 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -299,9 +299,7 @@
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
@@ -309,8 +307,6 @@
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PCI_ENUM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index bdeee47..1946bb9 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -368,12 +368,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DS4510_INFO
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
@@ -381,8 +379,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PCI_ENUM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 0948035..a84099a 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -355,10 +355,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
@@ -366,10 +364,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PCI_ENUM
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index dc7a75b..9a0aac5 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -33,7 +33,6 @@
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
 
 /* I2C configs */
-#define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
@@ -42,7 +41,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* Miscellaneous configurable options */
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
 
@@ -82,7 +80,6 @@
 #define CONFIG_CMD_CACHE
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 0cffab8..37f7a07 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -193,7 +193,6 @@
 #define CONFIG_CMD_PCI
 
 #ifdef CONFIG_440EP
-    #define CONFIG_CMD_USB
     #define CONFIG_CMD_FAT
     #define CONFIG_CMD_EXT2
 #endif
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 8bb48a8..81de228 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -60,8 +60,6 @@
  */
 #define	CONFIG_CMD_ENV
 #define	CONFIG_CMD_MMC
-#define	CONFIG_CMD_SPI
-#define	CONFIG_CMD_USB
 #define	CONFIG_CMD_CACHE
 
 /*
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 3a401f7..e66a7f4 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -81,10 +81,7 @@
 /*
  * Additional command
  */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
 
 
 /*
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index d535316..39665ee 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -55,14 +55,12 @@
 
 /* SPI */
 #ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_CMD_SF
 #endif
 
 /* QSPI */
 #ifdef CONFIG_ZYNQ_QSPI
 # define CONFIG_SF_DEFAULT_SPEED	30000000
 # define CONFIG_SPI_FLASH_ISSI
-# define CONFIG_CMD_SF
 #endif
 
 /* NOR */
@@ -92,7 +90,6 @@
 
 #ifdef CONFIG_ZYNQ_USB
 # define CONFIG_USB_EHCI
-# define CONFIG_CMD_USB
 # define CONFIG_USB_STORAGE
 # define CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_EHCI_IS_TDI
@@ -157,7 +154,6 @@
 
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)
-# define CONFIG_CMD_I2C
 # define CONFIG_SYS_I2C
 # define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
 # define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
@@ -307,10 +303,7 @@
 #define CONFIG_SYS_LDSCRIPT  "arch/arm/mach-zynq/u-boot.lds"
 
 /* Commands */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_TFTPPUT
 
 /* SPL part */
 #define CONFIG_CMD_SPL
-- 
cgit v0.10.2


From cb04db155f4e7ccaec1b961d8a84e1a1b9524594 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Sun, 24 Apr 2016 10:24:59 -0400
Subject: include/configs: Whitespace fixup

A number of moveconfig.py runs have left a instances of multiple empty
lines in a row.  Correct this to a single empty line.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index cda5a65..a9c6272 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -712,7 +712,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
 
-
 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 42cc6db..07070cd 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -52,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 
-
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 51bdc0f..1eb2ff6 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -93,7 +93,6 @@
 
 #define CONFIG_CMD_PCI
 
-
 /*
  * PCI Windows
  * Memory space is mapped 1-1, but I/O space must start from 0.
@@ -223,7 +222,6 @@ combinations. this should be removed later
 #define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
 #endif
 
-
 /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
@@ -590,7 +588,6 @@ combinations. this should be removed later
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index ba5fbfd..1600417 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -100,7 +100,6 @@
 
 #define CONFIG_CMD_PCI
 
-
 /*
  * PCI Windows
  * Memory space is mapped 1-1, but I/O space must start from 0.
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 1c4b01f..b60da5e 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -48,7 +48,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -57,7 +56,6 @@
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -67,7 +65,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
@@ -102,7 +99,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 51054a1..de6ff7f 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -62,7 +62,6 @@
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -89,7 +88,6 @@
  */
 #undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index efc7827..b5d49b5 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -40,7 +40,6 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 
-
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_MII		1
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index 7f5ee8a..e5aa1c7 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -37,7 +37,6 @@
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o      (.text)
 
-
 /*
  * BOOTP options
  */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 5f055e7..5f3ec3f 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -58,7 +58,6 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MII
 
-
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #define CONFIG_MII		1
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 8e2bd85..7c4509f 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -21,7 +21,6 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
 
-
 /***********************************************************
  * Note that it may also be a MIP405T board which is a subset of the
  * MIP405
@@ -37,7 +36,6 @@
  ***********************************************************/
 #define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */
 
-
 /*
  * BOOTP options
  */
@@ -46,7 +44,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -66,7 +63,6 @@
 #if !defined(CONFIG_MIP405T)
 #endif
 
-
 /**************************************************************
  * I2C Stuff:
  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@@ -89,7 +85,6 @@
 					/* last	6 bits of the address	*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */
@@ -280,7 +275,6 @@
 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 #define CONFIG_PORT_ADDR	PER_PLD_ADDR + 5
 
-
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in On Chip SRAM)
  */
@@ -406,5 +400,4 @@
 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 #endif
 
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 536fc06..4b7a773 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -276,7 +276,6 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 
-
 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
 				| BR_PS_8		/* 8 bit port */ \
@@ -427,7 +426,6 @@
 #define TSEC2_PHYIDX		0
 #endif
 
-
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC1"
 
@@ -474,7 +472,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 9cb8012..d29519d 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -635,7 +635,6 @@
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
-
 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index c1eb442..38bb613 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -337,7 +337,6 @@
 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
 
-
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 
@@ -407,7 +406,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -602,7 +600,6 @@
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
-
 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 7e0cb2a..b3a3bc5 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -464,7 +464,6 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-
 /*
  * BOOTP options
  */
@@ -473,7 +472,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -617,7 +615,6 @@
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST) */
 
-
 #define CONFIG_SYS_HID2 HID2_HBE
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 447974c..9b3c6ea 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -484,7 +484,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -710,7 +709,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
 #endif
 
-
 /*
  * Environment Configuration
  */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 09dd4c6..7f26ecb 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -475,7 +475,6 @@ extern int board_pci_host_broken(void);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -695,7 +694,6 @@ extern int board_pci_host_broken(void);
 	"tftp $fdtaddr $fdtfile;"					\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
-
 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index ff6c962..ebf30e7 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -486,7 +486,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index c19e991..f22ba9b 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -156,7 +156,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Memory map -- xxx -this is wrong, needs updating
  *
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 6e715f6..38bd38c 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -65,7 +65,6 @@
 #define CONFIG_SYS_CLK_FREQ	33000000
 #endif
 
-
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -136,7 +135,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */
@@ -201,7 +199,6 @@
 #define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 #define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
-
 /*
  * 32KB, 8-bit wide for ADS config reg
  */
@@ -278,7 +275,6 @@
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -293,7 +289,6 @@
 #define TSEC1_FLAGS		TSEC_GIGABIT
 #define TSEC2_FLAGS		TSEC_GIGABIT
 
-
 #if CONFIG_HAS_FEC
 #define CONFIG_MPC85XX_FEC	1
 #define CONFIG_MPC85XX_FEC_NAME		"FEC"
@@ -307,7 +302,6 @@
 
 #endif	/* CONFIG_TSEC_ENET */
 
-
 /*
  * Environment
  */
@@ -326,7 +320,6 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-
 /*
  * BOOTP options
  */
@@ -335,7 +328,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -377,7 +369,6 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 
-
 /*
  * Environment Configuration
  */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 1187310..4f49633 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -133,7 +133,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
-
 /*
  * SDRAM on the Local Bus
  */
@@ -314,7 +313,6 @@ extern unsigned long get_clock_freq(void);
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -353,7 +351,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -365,7 +362,6 @@ extern unsigned long get_clock_freq(void);
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 /*
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 535f648..435bdc8 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -179,12 +179,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
 #define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 
-
 #define CONFIG_SYS_INIT_RAM_LOCK      1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
 
-
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
@@ -317,7 +315,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -368,7 +365,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 8085969..0fdf939 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -132,7 +132,6 @@ extern unsigned long get_clock_freq(void);
  *
  */
 
-
 /*
  * Local Bus Definitions
  */
@@ -421,7 +420,6 @@ extern unsigned long get_clock_freq(void);
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -479,7 +477,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -491,7 +488,6 @@ extern unsigned long get_clock_freq(void);
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 /*
@@ -580,7 +576,6 @@ extern unsigned long get_clock_freq(void);
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr - $fdtaddr"
 
-
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "					\
       "console=$consoledev,$baudrate $othbootargs;"			\
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index d24309a..56f6ef5 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -33,7 +33,6 @@
 
 #define CONFIG_FSL_VIA
 
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif
@@ -131,7 +130,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
-
 /*
  * SDRAM on the Local Bus
  */
@@ -312,7 +310,6 @@ extern unsigned long get_clock_freq(void);
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -351,7 +348,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -363,7 +359,6 @@ extern unsigned long get_clock_freq(void);
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 /*
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index c0841db..c049d8d 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -60,7 +60,6 @@
 #define CONFIG_SYS_CLK_FREQ	33000000
 #endif
 
-
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -133,7 +132,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */
@@ -198,7 +196,6 @@
 #define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 #define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
-
 /*
  * 32KB, 8-bit wide for ADS config reg
  */
@@ -273,7 +270,6 @@
 
 #endif	/* CONFIG_PCI */
 
-
 #ifdef CONFIG_TSEC_ENET
 
 #ifndef CONFIG_MII
@@ -345,7 +341,6 @@
 
 #endif
 
-
 /*
  * Environment
  */
@@ -372,7 +367,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -419,7 +413,6 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif
 
-
 /*
  * Environment Configuration
  */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 47b0955..d42191b 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -51,7 +51,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
-
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
 
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
@@ -144,14 +143,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
-
 /*
  * SDRAM on the LocalBus
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
 #define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
 
-
 /*Chip select 2 - SDRAM*/
 #define CONFIG_SYS_BR2_PRELIM      0xf0001861
 #define CONFIG_SYS_OR2_PRELIM		0xfc006901
@@ -364,7 +361,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-
 /*
  * BOOTP options
  */
@@ -373,7 +369,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -385,7 +380,6 @@ extern unsigned long get_clock_freq(void);
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 /*
@@ -459,14 +453,12 @@ extern unsigned long get_clock_freq(void);
    "ramargs=setenv bootargs root=/dev/ram rw "				\
       "console=$consoledev,$baudrate $othbootargs\0"			\
 
-
 #define CONFIG_NFSBOOTCOMMAND	                                        \
    "run nfsargs;"							\
    "tftp $loadaddr $bootfile;"                                          \
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr - $fdtaddr"
 
-
 #define CONFIG_RAMBOOTCOMMAND \
    "run ramargs;"							\
    "tftp $ramdiskaddr $ramdiskfile;"                                    \
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 51abcab..37156cb 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -463,7 +463,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -475,7 +474,6 @@ extern unsigned long get_clock_freq(void);
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 #define CONFIG_MMC     1
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index fe9d4cd..00db9b7 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -177,7 +177,6 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 
-
 #define CONFIG_FLASH_BR_PRELIM \
 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
@@ -318,7 +317,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 
-
 /* NAND flash config */
 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -358,7 +356,6 @@
 			       | BR_V)		       /* valid */
 #define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
-
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
@@ -509,7 +506,6 @@
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index b40d72f..b6539b8 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -20,7 +20,6 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xfff00000
 
-
 /* video */
 #define CONFIG_FSL_DIU_FB
 
@@ -136,14 +135,12 @@
 
 #endif
 
-
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 
-
 #define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
 
@@ -161,7 +158,6 @@
 #define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
 #define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
 
-
 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
 #define PIXIS_BASE	0xe8000000	/* PIXIS registers */
 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
@@ -277,7 +273,6 @@
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
 
-
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -386,7 +381,6 @@
 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
-
 /*
  * BAT5		128K	Cacheable, non-guarded
  * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
@@ -424,7 +418,6 @@
 #define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
 
-
 /*
  * Environment
  */
@@ -442,7 +435,6 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-
 /*
  * BOOTP options
  */
@@ -451,7 +443,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -463,7 +454,6 @@
 #define CONFIG_CMD_EXT2
 #endif
 
-
 #define CONFIG_WATCHDOG			/* watchdog enabled */
 #define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
 
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 6f70bd1..b2e2f36 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -134,7 +134,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
 #define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
 
-
 /*
  * These are used when DDR doesn't use SPD.
  */
@@ -359,7 +358,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
-
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
@@ -440,7 +438,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #endif	/* CONFIG_TSEC_ENET */
 
-
 #ifdef CONFIG_PHYS_64BIT
 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
@@ -600,7 +597,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-
 /*
  * BOOTP options
  */
@@ -609,7 +605,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -621,7 +616,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
     #define CONFIG_CMD_EXT2
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 /*
@@ -703,7 +697,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 	"maxcpus=2"
 
-
 #define CONFIG_NFSBOOTCOMMAND						\
 	"setenv bootargs root=/dev/nfs rw "				\
 	      "nfsroot=$serverip:$rootpath "				\
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index fcb1644..87726a4 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -185,7 +185,6 @@
 
 #define CONFIG_CMD_PCI
 
-
 /*
  * PCI Windows
  * Memory space is mapped 1-1, but I/O space must start from 0.
@@ -699,7 +698,6 @@ extern unsigned long get_sdram_size(void);
 
 #endif	/* CONFIG_TSEC_ENET */
 
-
 /* SATA */
 #define CONFIG_FSL_SATA
 #define CONFIG_FSL_SATA_V2
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 5272878..5a7bef9 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -172,7 +172,6 @@
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
-
 /* DDR Setup */
 #define CONFIG_DDR_SPD
 #define CONFIG_VERY_BIG_RAM
@@ -217,7 +216,6 @@
 #define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
 
-
 /*
  * Memory map
  *
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 81d535f..9f3c037 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -21,14 +21,12 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF00000
 
-
 /* Serial Console Configuration */
 #define	CONFIG_5xx_CONS_SCI1
 #undef	CONFIG_5xx_CONS_SCI2
 
 #define CONFIG_BAUDRATE		9600
 
-
 /*
  * BOOTP options
  */
@@ -37,7 +35,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -47,7 +44,6 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
 
-
 #if 0
 #define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
 #else
@@ -135,7 +131,6 @@
  */
 #define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
 
-
 /*-----------------------------------------------------------------------
  * FLASH organization
  *-----------------------------------------------------------------------
@@ -165,7 +160,6 @@
 #define CONFIG_ENV_OFFSET		((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)		/* Environment starts at this adress	*/
 #endif
 
-
 #define CONFIG_SPI		1
 #define CONFIG_SYS_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
 #define CONFIG_SYS_SPI_CS_BASE	0x08 /* CS3 is active low */
@@ -224,7 +218,6 @@
  */
 #define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
 
-
 #define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 5290208..7d7e2d0 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -21,13 +21,11 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFF80000
 
-
 /***********************************************************
  * Clock
  ***********************************************************/
 #define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
 
-
 /*
  * BOOTP options
  */
@@ -36,7 +34,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -81,7 +78,6 @@
 					/* last	6 bits of the address	*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-
 /***************************************************************
  * Definitions for Serial Presence Detect EEPROM address
  * (to get SDRAM settings)
@@ -96,13 +92,11 @@
  **************************************************************/
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
 
-
 #define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
 
-
 #define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
 #define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 
@@ -231,7 +225,6 @@
 #define CONFIG_PORT_ADDR	0xF4000000
 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 
-
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in On Chip SRAM)
  */
@@ -353,5 +346,4 @@
 #define CONFIG_ISO_STRING "MEV-10066-001"
 #define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index c775100..a868ec9 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -47,7 +47,6 @@
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
-
 /*
  * BOOTP options
  */
@@ -56,7 +55,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -86,7 +84,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index a4d7bee..03c8fb9 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -158,7 +158,6 @@
 #define CONFIG_SYS_FLASH_EMPTY_INFO	1 /* 'E' for empty sector (flinfo) */
 #define CONFIG_SYS_FLASH_QUIET_TEST	1 /* don't warn upon unknown flash */
 
-
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index f69eee6..e5555cc 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -158,7 +158,6 @@
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_1		400000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1		0x7F
 
-
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 90572f4..22f42f0 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -202,7 +202,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 
-
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
@@ -879,7 +878,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BAUDRATE		115200
 #define __USB_PHY_TYPE		utmi
 
-
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 846ad39..7b6625f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -217,7 +217,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
 
-
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
@@ -916,7 +915,6 @@ unsigned long get_board_ddr_clk(void);
 	"setenv loadaddr 0x1000000;"			\
 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
-
 #define CONFIG_NFSBOOTCOMMAND			\
 	"setenv bootargs root=/dev/nfs rw "	\
 	"nfsroot=$serverip:$rootpath "		\
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 04c564f..da06bfd 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -450,7 +450,6 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_PCA_ADDR		0x77
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
 
-
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
 #define I2C_MUX_CH_DIU		0xC
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 1e61ec9..e58691b 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -709,7 +709,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #endif
 #endif
 
-
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b1bd4fd..6f81368 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -744,7 +744,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif
 
-
 /*
  * Dynamic MTD Partition support with mtdparts
  */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index dc6e211..508c896 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -652,7 +652,6 @@ unsigned long get_board_ddr_clk(void);
 #define FM1_10GEC4_PHY_ADDR	0x01
 #endif
 
-
 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC3"
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index af5855c..1ff6309 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -343,7 +343,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_RAMBOOT
 #endif
 
-
 /* I2C */
 #define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
 #define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
@@ -404,7 +403,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
-
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
@@ -492,7 +490,6 @@ unsigned long get_board_ddr_clk(void);
 #define FM2_10GEC2_PHY_ADDR	0x3
 #endif
 
-
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 2b50594..495c09c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -154,14 +154,12 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR3
 
-
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 
-
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
 #else
@@ -349,7 +347,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-
 #define CONFIG_BAUDRATE	115200
 
 #define CONFIG_HVBOOT					\
@@ -572,7 +569,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_RAMBOOT
 #endif
 
-
 /* I2C */
 #define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
 #define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
@@ -606,7 +602,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SF_DEFAULT_SPEED         10000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
-
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
@@ -696,7 +691,6 @@ unsigned long get_board_ddr_clk(void);
 #define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
 #endif
 
-
 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 516acd3..d542d2a 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -117,7 +117,6 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #endif /* #ifndef CONFIG_TQM5200S */
 
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -151,7 +150,6 @@
 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 #endif
 
-
 /*
  * BOOTP options
  */
@@ -160,7 +158,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -198,7 +195,6 @@
     #define CONFIG_CMD_DIAG
 #endif
 
-
 #define	CONFIG_TIMESTAMP		/* display image timestamps */
 
 #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
@@ -485,7 +481,6 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
-
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 474ab5f..304dc09 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -95,13 +95,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
@@ -115,7 +113,6 @@
     #define CONFIG_CMD_BMP
 #endif
 
-
 #define CONFIG_NETCONSOLE
 
 /*
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 98b900a..72cd1e4 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -93,13 +93,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 2becc46..24ed057 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -282,7 +282,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -307,7 +306,6 @@
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
 
-
 #if defined(CONFIG_CMD_KGDB)
 	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 8b57f08..2ed1539 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -84,7 +84,6 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 40c60fc..469cd3f 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -84,7 +84,6 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
@@ -99,10 +98,8 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
-
 #define CONFIG_NETCONSOLE
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index cae97c6..eb0077b 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -86,13 +86,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index e6868ef..b504713 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -115,13 +115,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 25ce29b..dfddd03 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -86,13 +86,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 117d1e4..2733849 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -86,13 +86,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index bb61986b..9f09319 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -89,13 +89,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index ff473e9..e76cb64 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -89,13 +89,11 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 78cf804..0d84ac7 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -127,7 +127,6 @@
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_BOOTFILESIZE
 
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
@@ -135,7 +134,6 @@
 
 #define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 0b6e3f3..5d7874b 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 #define MACH_TYPE_MPL_VCMA9	227
 
 /*
@@ -29,7 +28,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x0
 
-
 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* input clock of PLL (VCMA9 has 12MHz input clock) */
@@ -113,7 +111,6 @@
 /* RTC */
 #define CONFIG_RTC_S3C24X0
 
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index e2aa578..405ac0d 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -74,7 +74,6 @@
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index f44a20c..47e35c5 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -230,7 +230,6 @@
  *                                                        +- 31    0 PSC1
  */
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index c6a8553..09216d1 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -88,7 +88,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -222,7 +221,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
@@ -276,7 +274,6 @@
 #  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-
 /*
  * Various low-level settings
  */
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index 8c60f10..efd63a0 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -342,7 +342,6 @@
 			 CLOCK_SCCR2_DIU_EN |		\
 			 CLOCK_SCCR2_I2C_EN)
 
-
 #define CONFIG_CMDLINE_EDITING		1	/* command line history */
 
 /* I2C */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index cd6e0fd..cbfe1bd 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -134,7 +134,6 @@
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
-
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index f97988c..89093bd 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -10,7 +10,6 @@
 #ifndef __AMCC_COMMON_H
 #define __AMCC_COMMON_H
 
-
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
 #define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
@@ -88,7 +87,6 @@
 #define CONFIG_VERSION_VARIABLE 	/* include version env variable */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
 
-
 #define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
 
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index f0e88ee..f8c91f8 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -147,7 +147,6 @@
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_PREBOOT			"run check_flash check_env;"
 
-
 /*
  * Boot Linux
  */
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index fc7a35e..1f7ef8f 100644
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -38,7 +38,6 @@
 #define PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 
-
 /* Environment */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_ENV_IS_IN_NAND
@@ -92,7 +91,6 @@
 #define CONFIG_USB_STORAGE
 #endif
 
-
 /* RTC */
 #ifdef CONFIG_CMD_DATE
 #define CONFIG_RTC_PCF8563
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index f7fa058..6660eb0 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -68,7 +68,6 @@
 #define CONFIG_CMD_FPGA_LOADMK
 #define CONFIG_CMDLINE_EDITING
 
-
 #define CONFIG_MCFRTC
 #undef RTC_DEBUG
 
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 0d98a44..ee3712c 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -60,7 +60,6 @@
 
 #define CONFIG_CMD_BOOTZ
 
-
 /*
  * Memory Configuration
  */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 126b8d4..6a03923 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -61,7 +61,6 @@
 #undef CONFIG_FB_ADDR
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
-
 /* LED */
 #define CONFIG_AT91_LED
 #define	CONFIG_RED_LED		AT91_PIN_PD14	/* this is the power led */
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index a4d9cb8..fd87bb7 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -74,7 +74,6 @@
  * NB: in this case, USB 1.1 devices won't be recognized.
  */
 
-
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x20000000
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 4118cac..a18a2c9 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -86,7 +86,6 @@
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
 
-
 #define CONFIG_ATMEL_USART
 #define CONFIG_MACB
 #define CONFIG_PORTMUX_PIO
@@ -97,7 +96,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_ATMEL_SPI
 
-
 #define CONFIG_SYS_DCACHE_LINESZ		32
 #define CONFIG_SYS_ICACHE_LINESZ		32
 
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index dd4e1a3..09e193e 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -106,7 +106,6 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_MII
 
-
 #define CONFIG_ATMEL_USART
 #define CONFIG_MACB
 #define CONFIG_PORTMUX_PIO
@@ -117,7 +116,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_ATMEL_SPI
 
-
 #define CONFIG_SYS_DCACHE_LINESZ	32
 #define CONFIG_SYS_ICACHE_LINESZ	32
 
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 2d34077..62f01a7 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -107,7 +107,6 @@
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
 
-
 #define CONFIG_ATMEL_USART
 #define CONFIG_MACB
 #define CONFIG_PORTMUX_PIO
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 560dc88..27ab8f7 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -198,7 +198,6 @@
 	"run mmcboot;" \
 	"run nandboot;"
 
-
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 #define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index 4563c54..e95deac 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf536-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -39,14 +37,12 @@
 #define CONFIG_SCLK_DIV			3
 #define CONFIG_VR_CTL_VAL	(VLEV_110 | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
 #define CONFIG_MEM_ADD_WDTH	9
 #define CONFIG_MEM_SIZE		32
 
-
 /*
  * SDRAM Settings
  */
@@ -60,7 +56,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -75,7 +70,6 @@
 #define CONFIG_ROOTPATH		"/romfs/brettl2"
 #endif
 
-
 /*
  * Flash Settings
  */
@@ -87,7 +81,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
 #define CONFIG_SYS_MAX_FLASH_SECT		135
 
-
 /*
  * Env Storage Settings
  */
@@ -115,14 +108,12 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
index 8be2ecb..dc7d83f 100644
--- a/include/configs/bf506f-ezkit.h
+++ b/include/configs/bf506f-ezkit.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf506-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -52,7 +49,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(4 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(4 * 1024)
 
-
 /*
  * Flash Settings
  */
@@ -79,7 +75,6 @@
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_SIZE 0x400
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 9f44ebd..510cd47 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf518-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -56,7 +53,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -98,7 +94,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	71
 
-
 /*
  * SPI Settings
  */
@@ -106,7 +101,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -124,14 +118,12 @@
 #endif
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SDH Settings
  */
@@ -141,7 +133,6 @@
 #define CONFIG_BFIN_SDH
 #endif
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index e9d900e..74c3464 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf526-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -56,7 +53,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
 
-
 /*
  * NAND Settings
  * (can't be used same time as ethernet)
@@ -73,7 +69,6 @@
 #define CONFIG_CMD_NAND
 #endif
 
-
 /*
  * Network Settings
  */
@@ -96,7 +91,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	71
 
-
 /*
  * SPI Settings
  */
@@ -104,7 +98,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -122,14 +115,12 @@
 #endif
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * USB Settings
  */
@@ -141,7 +132,6 @@
 #define CONFIG_USB_MUSB_TIMEOUT 100000
 #endif
 
-
 /*
  * Misc Settings
  */
@@ -167,7 +157,6 @@
 /* #define STATUS_LED_BIT2 GPIO_PG12 */
 #endif
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index dd62e7e..258115a 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf527-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -55,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
 
-
 /*
  * NAND Settings
  * (can't be used same time as ethernet)
@@ -71,7 +67,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #endif
 
-
 /*
  * Flash Settings
  */
@@ -82,7 +77,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	259
 
-
 /*
  * SPI Settings
  */
@@ -90,7 +84,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -113,14 +106,12 @@
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SPI_MMC Settings
  */
@@ -128,7 +119,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SPI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 44de44f..e268473 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf527-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			4
 
-
 /*
  * Memory Settings
  */
@@ -55,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
 
-
 /*
  * NAND Settings
  * (can't be used same time as ethernet)
@@ -71,7 +67,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #endif
 
-
 /*
  * Network Settings
  */
@@ -94,7 +89,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	259
 
-
 /*
  * SPI Settings
  */
@@ -102,7 +96,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -125,14 +118,12 @@
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * USB Settings
  */
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
index 6b51201..6b7d19e 100644
--- a/include/configs/bf527-sdp.h
+++ b/include/configs/bf527-sdp.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf527-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -42,7 +40,6 @@
 #define CONFIG_PLL_CTL_VAL		0x2a00
 #define CONFIG_VR_CTL_VAL		0x7090
 
-
 /*
  * Memory Settings
  */
@@ -59,7 +56,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
 
-
 /*
  * Flash Settings
  */
@@ -70,7 +66,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	259
 
-
 /*
  * SPI Settings
  */
@@ -79,7 +74,6 @@
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH_ALL
 
-
 /*
  * Env Storage Settings
  */
@@ -98,14 +92,12 @@
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 9581101..e154812 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -60,7 +57,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -76,7 +72,6 @@
 	} while (0)
 #define CONFIG_HOSTNAME		bf533-ezkit
 
-
 /*
  * Flash Settings
  */
@@ -88,7 +83,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define FLASH_TOT_SECT		40
 
-
 /*
  * I2C Settings
  */
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index c8c48ae..c2466ca 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -7,7 +7,6 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
@@ -53,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -69,7 +67,6 @@
 	} while (0)
 #define CONFIG_HOSTNAME		bf533-stamp
 
-
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
@@ -134,7 +131,6 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
@@ -177,7 +173,6 @@
 #define CONFIG_EBIU_AMBCTL1_VAL	0x99B3ffc2
 #endif
 
-
 /*
  * Misc Settings
  */
@@ -211,7 +206,6 @@
 /* define to enable splash screen support */
 /* #define CONFIG_VIDEO */
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 425f0a9..a351d1b 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -20,14 +20,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -51,7 +49,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -68,7 +65,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(128 << 10)
 
-
 /*
  * Network Settings
  */
@@ -87,14 +83,12 @@
 #define CONFIG_SYS_AUTOLOAD	"no"
 #define CONFIG_ROOTPATH		"/romfs"
 
-
 /*
  * Flash Settings
  */
 /* We don't have a parallel flash chip there */
 #define CONFIG_SYS_NO_FLASH
 
-
 /*
  * SPI Settings
  */
@@ -102,7 +96,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -112,7 +105,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C settings
  */
@@ -121,7 +113,6 @@
 #define CONFIG_SYS_I2C_SPEED		50000
 #define CONFIG_SYS_I2C_SLAVE		0
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 5794f47..bced1df 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			4
 
-
 /*
  * Memory Settings
  */
@@ -55,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -75,7 +71,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	71
 
-
 /*
  * SPI Settings
  */
@@ -83,7 +78,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -112,7 +106,6 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * NAND Settings
  */
@@ -133,14 +126,12 @@
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 
-
 /*
  * I2C settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
@@ -157,7 +148,6 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTARGS_ROOT	"/dev/mtdblock1 rw rootfstype=yaffs"
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index fc4f50b..cbe752a 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -20,14 +20,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -51,7 +49,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -68,7 +65,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(384 << 10)
 
-
 /*
  * Network Settings
  */
@@ -93,7 +89,6 @@
 /* We don't have a parallel flash chip there */
 #define CONFIG_SYS_NO_FLASH
 
-
 /*
  * SPI Settings
  */
@@ -101,7 +96,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -111,7 +105,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C settings
  */
@@ -120,7 +113,6 @@
 #define CONFIG_SYS_I2C_SPEED		50000
 #define CONFIG_SYS_I2C_SLAVE		0
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index b178713..4f861aa 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			4
 
-
 /*
  * Memory Settings
  */
@@ -55,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -77,7 +73,6 @@
 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
 #define CONFIG_SYS_MAX_FLASH_SECT	71
 
-
 /*
  * SPI Settings
  */
@@ -86,7 +81,6 @@
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH_ALL
 
-
 /*
  * Env Storage Settings
  */
@@ -120,14 +114,12 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SPI_MMC Settings
  */
@@ -243,7 +235,6 @@
 
 #endif
 
-
 /*
  * Misc Settings
  */
@@ -270,7 +261,6 @@
 #define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
 #endif
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 55becdc..a6d039c 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf538-0.4
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			4
 
-
 /*
  * Memory Settings
  */
@@ -55,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -64,7 +60,6 @@
 #define CONFIG_SMC91111_BASE	0x20310300
 #define CONFIG_HOSTNAME		bf538f-ezkit
 
-
 /*
  * Flash Settings
  */
@@ -75,7 +70,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	71
 
-
 /*
  * SPI Settings
  */
@@ -119,14 +113,12 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 8198cb8..6830e4d 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf548-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			4
 
-
 /*
  * Memory Settings
  */
@@ -64,7 +61,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(1024 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(768 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -74,7 +70,6 @@
 #define CONFIG_SMC911X_16_BIT
 #define CONFIG_HOSTNAME		bf548-ezkit
 
-
 /*
  * Flash Settings
  */
@@ -85,7 +80,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	259
 
-
 /*
  * SPI Settings
  */
@@ -93,7 +87,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -133,7 +126,6 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SATA
  */
@@ -146,7 +138,6 @@
 #define CONFIG_BFIN_ATA_MODE	XFER_PIO_4
 #endif
 
-
 /*
  * SDH Settings
  */
@@ -156,7 +147,6 @@
 #define CONFIG_BFIN_SDH
 #endif
 
-
 /*
  * USB Settings
  */
@@ -168,7 +158,6 @@
 #define CONFIG_USB_MUSB_TIMEOUT 100000
 #endif
 
-
 /*
  * Misc Settings
  */
@@ -199,7 +188,6 @@
 #define CONFIG_SYS_POST_FLASH_END	127
 #endif
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 31862da..c36be03 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -8,14 +8,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf561-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -39,7 +37,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV				5
 
-
 /*
  * Memory Settings
  */
@@ -56,7 +53,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
-
 /*
  * RTC Settings
  */
@@ -71,7 +67,6 @@
 #define CONFIG_SYS_DTT_LOW_TEMP -30
 #define CONFIG_SYS_DTT_HYSTERESIS       3*/
 
-
 /*
  * Network Settings
  */
@@ -91,13 +86,11 @@
 
 #define CONFIG_HOSTNAME		bf561-acvilon
 
-
 /*
  * Flash Settings
  */
 #define CONFIG_SYS_NO_FLASH
 
-
 /*
  * I2C Settings
  */
@@ -107,7 +100,6 @@
 #define CONFIG_PCA9564_I2C
 #define CONFIG_PCA9564_BASE			0x2c000000
 
-
 /*
  * SPI Settings
  */
@@ -115,7 +107,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ		10000000
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 
-
 /*
  * Env Storage Settings
  */
@@ -124,7 +115,6 @@
 #define CONFIG_ENV_OFFSET			((16 + 256) * 1056)
 #define CONFIG_ENV_SIZE				(8 * 1056)
 
-
 /*
  * NAND Settings
  * We're using NAND_PLAT driver to make things simplier
@@ -146,7 +136,6 @@
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1a3b33f..2fefe98 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf561-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			6
 
-
 /*
  * Memory Settings
  */
@@ -55,7 +52,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -65,7 +61,6 @@
 #define CONFIG_SMC_USE_32_BIT	1
 #define CONFIG_HOSTNAME		bf561-ezkit
 
-
 /*
  * Flash Settings
  */
@@ -82,7 +77,6 @@
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	0x2000
 
-
 /*
  * I2C Settings
  */
@@ -106,7 +100,6 @@
  */
 /* #define CONFIG_CORE1_RUN	1 */
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 3e0bff5..a62038e 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -13,7 +13,6 @@
 #define CONFIG_BFIN_CPU             bf609-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /* For ez-board version 1.0, else undef this */
 #define CONFIG_BFIN_BOARD_VERSION_1_0
 
diff --git a/include/configs/br4.h b/include/configs/br4.h
index 85f31a4..402f352 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -10,14 +10,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -75,7 +71,6 @@
  */
 #define CONFIG_SYS_NO_FLASH	/* We have no parallel FLASH */
 
-
 /*
  * SPI Settings
  */
@@ -83,7 +78,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -93,14 +87,12 @@
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * NAND Settings
  */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 0a39cdf..028d0a2 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -135,7 +135,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/charon.h b/include/configs/charon.h
index 2f537e0..578c108 100644
--- a/include/configs/charon.h
+++ b/include/configs/charon.h
@@ -34,7 +34,6 @@
 	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
 
-
 /* additional features on charon board */
 #define CONFIG_RESET_PHY_R
 
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index 761e2c5..0b31dc9 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf527-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Decrease core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * NAND Settings
  * (can't be used sametime as ethernet)
@@ -71,7 +67,6 @@
 #define CONFIG_CMD_NAND
 #endif
 
-
 /*
  * Network Settings
  */
@@ -95,7 +90,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT 	67
 
-
 /*
  * Env Storage Settings
  */
@@ -106,14 +100,12 @@
 #define CONFIG_ENV_SECT_SIZE	0x8000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index d06333d..7039cba 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Decrease core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -67,7 +63,6 @@
 #define CONFIG_SMC91111_BASE	0x20200300
 #define CONFIG_HOSTNAME		cm-bf533
 
-
 /*
  * Flash Settings
  */
@@ -78,7 +73,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	16
 
-
 /*
  * Env Storage Settings
  */
@@ -87,7 +81,6 @@
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_SIZE		0x10000
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 746a5bd..78841cd 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Decrease core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -83,14 +79,12 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	35
 
-
 /*
  * SPI Settings
  */
 #define CONFIG_BFIN_SPI
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -115,14 +109,12 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SPI_MMC Settings
  */
@@ -130,7 +122,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SPI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 71008aa..5785ebd 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -40,7 +38,6 @@
 /* Core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -57,7 +54,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -81,14 +77,12 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	35
 
-
 /*
  * SPI Settings
  */
 #define CONFIG_BFIN_SPI
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -113,14 +107,12 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SPI_MMC Settings
  */
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 37205a9..d1aa262 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf548-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Decrease core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -67,7 +64,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -77,7 +73,6 @@
 #define CONFIG_SMC911X_16_BIT
 #define CONFIG_HOSTNAME		cm-bf548
 
-
 /*
  * Flash Settings
  */
@@ -88,7 +83,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	259
 
-
 /*
  * Env Storage Settings
  */
@@ -98,14 +92,12 @@
 #define CONFIG_ENV_SIZE		0x8000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
@@ -134,7 +126,6 @@
 #define FLASH_END_POST_BLOCK   71       /* Should < = 71 */
 #endif
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 284ec83..3860e0e 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf561-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Decrease core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -68,7 +64,6 @@
 #define CONFIG_SMC911X_16_BIT
 #define CONFIG_HOSTNAME		cm-bf561
 
-
 /*
  * Flash Settings
  */
@@ -79,7 +74,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	67
 
-
 /*
  * Env Storage Settings
  */
@@ -89,7 +83,6 @@
 #define CONFIG_ENV_SIZE		0x10000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 766faa6..cdb8931 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -8,10 +8,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 #define CONFIG_DISPLAY_BOARDINFO
 
-
 /*
  * High Level Configuration Options
  */
@@ -167,13 +165,11 @@
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
 #define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
 
-
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT		1
 #undef CONFIG_SYS_LOWBOOT
 #endif
 
-
 /*
  * Chip selects configuration
  */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 99b5d3e..c4f1d4f 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -63,7 +63,6 @@
 		"nboot ${loadaddr} nand0 900000; " \
 		"bootm ${loadaddr}\0"
 
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=82000000\0" \
 	"console=ttyO0,115200n8\0" \
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index debedec..aca9288 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -120,7 +120,6 @@
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
-
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 8ac41e2..1bedea7 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -133,7 +133,6 @@
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
-
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 0e05194..ee818ed 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -154,7 +154,6 @@
 		"run emmcboot; " \
 	"fi;"
 
-
 #define CONFIG_CONS_INDEX		1
 
 /* SPL defines. */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 9e44015..b291ba4 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -116,7 +116,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -157,7 +156,6 @@ seconds u-boot will wait before starting defined (auto-)boot command, setting
 to -1 disables delay, setting to 0 will too prevent access to u-boot command
 interface: u-boot then has to reflashed */
 
-
 /* The following settings will be contained in the environment block ; if you
 want to use a neutral environment all those settings can be manually set in
 u-boot: 'set' command */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 77b3e50..9d1c6ae 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -45,7 +45,6 @@
 #define CONFIG_CONTROLCENTERD
 #define CONFIG_MP			/* support multiple processors */
 
-
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
@@ -98,7 +97,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
-
 /*
  * Memory map
  *
@@ -215,7 +213,6 @@
  */
 #define CONFIG_HARD_SPI
 
-
 #define CONFIG_SF_DEFAULT_SPEED		10000000
 #define CONFIG_SF_DEFAULT_MODE		0
 #endif
@@ -232,7 +229,6 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 
-
 #ifndef CONFIG_TRAILBLAZER
 
 /*
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index fc1a8ba..432f2f6 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -28,7 +28,6 @@
 #define CONFIG_SCSI_DEV_LIST		\
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
 
-
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 701f59e..d1927b5 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -17,7 +17,6 @@
 #error Must call Cyrus CONFIG with a specific CPU enabled.
 #endif
 
-
 #define CONFIG_MMC
 #define CONFIG_SDCARD
 #define CONFIG_FSL_SATA_V2
@@ -43,7 +42,6 @@
 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
 #endif
 
-
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -51,7 +49,6 @@
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
 #define CONFIG_MP			/* support multiple processors */
 
-
 #define CONFIG_SYS_MMC_MAX_DEVICE     1
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -173,7 +170,6 @@
 #define CONFIG_SYS_OR0_PRELIM	0xfff00010
 #define CONFIG_SYS_OR1_PRELIM	0xfff00010
 
-
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
 
 #if defined(CONFIG_RAMBOOT_PBL)
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 2972057..9466332 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -20,7 +20,6 @@
 #define CONFIG_USE_SPIFLASH
 #endif
 
-
 /*
  * SoC Configuration
  */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index faf2a87..f9f30b1 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -61,7 +61,6 @@
 #define CONFIG_BOOTCOMMAND	"bootp;bootm"
 #endif /* CONFIG_DBAU1550 */
 
-
 /*
  * BOOTP options
  */
@@ -70,7 +69,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -89,7 +87,6 @@
 
 #endif
 
-
 /*
  * Miscellaneous configurable options
  */
@@ -172,7 +169,6 @@
 
 #define CONFIG_NR_DRAM_BANKS	2
 
-
 #ifdef CONFIG_DBAU1550
 #define MEM_SIZE 192
 #else
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 4afc91b..6acd2fe 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -185,7 +185,6 @@
 			"fi; " \
 		"else run nandboot; fi\0"
 
-
 #define CONFIG_BOOTCOMMAND "run autoboot"
 
 /* Boot Argument Buffer Size */
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index ae3017c..e54321b 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -12,7 +12,6 @@
 #ifndef _CONFIG_DOCKSTAR_H
 #define _CONFIG_DOCKSTAR_H
 
-
 /*
  * Version number information
  */
diff --git a/include/configs/draco.h b/include/configs/draco.h
index acefd3e..2d4a45d 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -67,7 +67,6 @@
 #define CONFIG_ENV_SIZE_REDUND      0x2000
 #define CONFIG_ENV_RANGE        (4 * CONFIG_SYS_ENV_SECT_SIZE)
 
-
 #define MTDPARTS_DEFAULT	MTDPARTS_DEFAULT_V2
 
 #ifndef CONFIG_SPL_BUILD
@@ -95,7 +94,6 @@
 "run nand_boot_backup;" \
 "reset;"
 
-
 #else
 #define CONFIG_BOOTDELAY		0
 
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index ae4fbb4..42fb0f3 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -99,7 +99,6 @@
 "tftp $loadaddr "#file" && " \
 "mmc write $loadaddr $start $size && "
 
-
 #define CONFIG_ENV_REFLASH \
 "mmc dev 0 && "\
 "usb start && "\
diff --git a/include/configs/duovero.h b/include/configs/duovero.h
index ac9a67f..d8f48ef 100644
--- a/include/configs/duovero.h
+++ b/include/configs/duovero.h
@@ -39,7 +39,6 @@
 
 #define CONFIG_SYS_ENABLE_PADS_ALL
 
-
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_32_BIT
 #define CONFIG_SMC911X_BASE		0x2C000000
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 06e988a..b52f34b 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -24,7 +24,6 @@
 #define CONFIG_VIDEO
 #define CONFIG_PREBOOT
 
-
 /*
  * SoC Configuration
  */
@@ -102,7 +101,6 @@
 #define CONFIG_SYS_NO_FLASH
 #endif
 
-
 #if defined(CONFIG_VIDEO)
 #define CONFIG_VIDEO_DA8XX
 #define CONFIG_CFB_CONSOLE
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
index f463521..bb5d7e5 100644
--- a/include/configs/eco5pk.h
+++ b/include/configs/eco5pk.h
@@ -58,5 +58,4 @@
 	"mtdparts="MTDPARTS_DEFAULT"\0" \
 	"serverip=192.168.142.60\0"
 
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index ce50973..c64d119 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -25,7 +25,6 @@
 #error "no board defined"
 #endif
 
-
 /* Initial environment and monitor configuration options. */
 #define CONFIG_BOOTDELAY		2
 #define CONFIG_CMDLINE_TAG		1
@@ -34,8 +33,6 @@
 #define CONFIG_BOOTARGS		"root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
 #define CONFIG_BOOTFILE		"edb93xx.img"
 
-
-
 #define CONFIG_SYS_LDSCRIPT	"board/cirrus/edb93xx/u-boot.lds"
 
 #ifdef CONFIG_EDB9301
@@ -160,7 +157,6 @@
 #error "no SDCS configuration for this board"
 #endif
 
-
 #if defined(CONFIG_EDB93XX_SDCS3)
 #define CONFIG_SYS_LOAD_ADDR	0x01000000	/* Default load address	*/
 #define PHYS_SDRAM_1		0x00000000
@@ -175,7 +171,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
     (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
 
-
 /* Must match kernel config */
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
 
@@ -214,7 +209,6 @@
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
-
 #define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 28bf6b5..cfb009c 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -12,7 +12,6 @@
 
 #include <asm/hardware.h>
 
-
 /* The first stage boot loader expects u-boot running at this address. */
 #define CONFIG_SYS_TEXT_BASE	0x27000000	/* 16MB available */
 
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 852829c..0a2d610 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -16,7 +16,6 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <linux/sizes.h>
 
-
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 97fcd4a..b2ff4dd 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -155,7 +155,6 @@
 
 /* Enable Time Command */
 
-
 /* USB */
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_XHCI_DWC3
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 54b9315..e74aa68 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -87,7 +87,6 @@
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
-
 /*
  * Ethernet on SOC (FEC)
  */
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index 243e19f..d0432ad 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -15,7 +15,6 @@
 #ifndef _CONFIG_GOFLEXHOME_H
 #define _CONFIG_GOFLEXHOME_H
 
-
 /*
  * Version number information
  */
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index e06e261..ab1e11d 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -189,7 +189,6 @@
 #undef CONFIG_SYS_SRAM_BASE
 #undef CONFIG_SYS_SRAM_SIZE
 
-
 /* Always Run U-Boot from SDRAM */
 #define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 712bfd7..5907e98 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -10,7 +10,6 @@
 #ifndef _CONFIG_GURUPLUG_H
 #define _CONFIG_GURUPLUG_H
 
-
 /*
  * Version number information
  */
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 1bb5ebb..3d510d6 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -135,7 +135,6 @@
 #define CONFIG_USB_DEV_PULLUP_GPIO	33
 /* USB VBUS GPIO 3 */
 
-
 #define CONFIG_BOOTDELAY		2
 #define CONFIG_BOOTCOMMAND		\
 	"setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 510741b..3bce12b 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -69,7 +69,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x800000
 #define CONFIG_SYS_64BIT_LBA
 
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  * The DRAM is already setup, so do not touch the DT node later.
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 4987373..d08ab1d 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -123,7 +123,6 @@
 				"initrd_high=0xffffffffffffffff\0" \
 				BOOTENV
 
-
 /* Preserve enviroment on sd card */
 #define CONFIG_COMMAND_HISTORY
 
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index aecfda4..d59d21f 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -26,7 +26,6 @@
 #define CONFIG_IDENT_STRING	" hrcon 0.01"
 #endif
 
-
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
@@ -665,5 +664,4 @@ void fpga_control_clear(unsigned int bus, int pin);
 
 #define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND
 
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 7cb2346..4cd0f77 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf561-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -56,7 +53,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -65,7 +61,6 @@
 #define AX88180_BASE		0x2c000000
 #define CONFIG_HOSTNAME		ibf-dsp561
 
-
 /*
  * Flash Settings
  */
@@ -99,7 +94,6 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
@@ -113,7 +107,6 @@
  */
 #define CONFIG_UART_CONSOLE	0
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
index 10f1e9b..c156bd3 100644
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -9,7 +9,6 @@
 #ifndef _CONFIG_ICONNECT_H
 #define _CONFIG_ICONNECT_H
 
-
 /*
  * Version number information
  */
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index ff93c7d..da4cba7 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -19,7 +19,6 @@
 #define CONFIG_MPC8313
 #define CONFIG_IDS8313
 
-
 #define CONFIG_FSL_ELBC
 
 #define CONFIG_MISC_INIT_R
@@ -442,7 +441,6 @@
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 
-
 #define CONFIG_NETDEV			eth1
 #define CONFIG_HOSTNAME		ids8313
 #define CONFIG_ROOTPATH		"/opt/eldk-4.2/ppc_6xx"
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 94dd796..94fc077 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -18,7 +18,6 @@
 #define CONFIG_MX31			/* This is a mx31 */
 #define CONFIG_MX31_CLK32	32000
 
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -92,7 +91,6 @@
 		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
 		"sync:1241513985,vmode:0\0"
 
-
 #define CONFIG_SMC911X
 #define CONFIG_SMC911X_BASE	0xa8000000
 #define CONFIG_SMC911X_32_BIT
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 149c8c6..282cc25 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -68,7 +68,6 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 
-
 /*
  * BOOTP options
  */
@@ -77,7 +76,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index f4982e1..b95851a 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -73,7 +73,6 @@
  */
 /* #define SKIP_CONFIG_RELOCATE_UBOOT */
 
-
 /*
  * Physical Memory Map
  */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index c80e915..a5a8819 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -28,7 +28,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -54,7 +53,6 @@
 #define CONFIG_EEPRO100
 #define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 
-
 /*-----------------------------------------------------------------------
  * There are various dependencies on the core module (CM) fitted
  * Users should refer to their CM user guide
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 69f0f4d..6f48b4b 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -309,7 +309,6 @@
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
-
 /*
  * External Bus Controller (EBC) Setup
  */
@@ -324,7 +323,6 @@
  * 0xfc00.0000 -> 4.cc00.0000
  */
 
-
 /* Memory Bank 0 (NOR-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB0AP		0x10055e00
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 3638648..4a9093c 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -16,14 +16,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf532-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -47,7 +45,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			3
 
-
 /*
  * Memory Settings
  */
@@ -64,7 +61,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -77,14 +73,12 @@
 #define DM9000_IO		CONFIG_DM9000_BASE
 #define DM9000_DATA		(CONFIG_DM9000_BASE + 2)
 
-
 /*
  * Flash Settings
  */
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_SYS_NO_FLASH		/* we have only NAND */
 
-
 /*
  * SPI Settings
  */
@@ -92,7 +86,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -102,7 +95,6 @@
 #define CONFIG_ENV_SIZE		0x10000
 #define CONFIG_ENV_SECT_SIZE	0x10000
 
-
 /*
  * NAND Settings
  */
@@ -122,7 +114,6 @@
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
-
 /*
  * Misc Settings
  */
@@ -134,7 +125,6 @@
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 
-
 /*
  * Pull in common ADI header for remaining command/environment setup
  */
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 869d8c4..3675099 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -90,7 +90,6 @@
 #define CONFIG_SYS_DA850_DDR2_SDBCR2	0x00000004
 #define CONFIG_SYS_DA850_DDR2_PBBPR	0x00000020
 
-
 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
 	(13 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
 	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
@@ -129,7 +128,6 @@
 				DAVINCI_ABCR_TA(0)	| \
 				DAVINCI_ABCR_ASIZE_8BIT)
 
-
 /*
  * Serial Driver info
  */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index ce92e78..0628203 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -73,7 +73,6 @@
 
 #define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
-
 /*
  * BOOTP options
  */
@@ -82,7 +81,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -91,7 +89,6 @@
 #define CODFIG_CMD_PCI
 #endif
 
-
 /*
  * Autobooting
  */
@@ -203,7 +200,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 15029f9..30be533 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -80,7 +80,6 @@
 #define CONFIG_SYS_I2C_OMAP24XX
 #define CONFIG_I2C_MULTI_BUS
 
-
 /*
  * Flash
  */
diff --git a/include/configs/km8360.h b/include/configs/km8360.h
index 49b9200..c8039e1 100644
--- a/include/configs/km8360.h
+++ b/include/configs/km8360.h
@@ -233,7 +233,6 @@
 
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
-
 #ifdef CONFIG_KMCOGE5NE
 /* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT6L (\
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index a445aaf..b377c41 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -180,5 +180,4 @@
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #endif
 
-
 #endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index a2a337d..54563e3 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -31,7 +31,6 @@
 
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
 
-
 /*
  * Memory Info
  */
@@ -218,7 +217,6 @@
 #define CONFIG_CLOCKS
 #endif
 
-
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_SIZE		(16 << 10)
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 5c3ece8..3bdece7 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -114,7 +114,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
-
 /* EEPROM */
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 648a6ff..8b75088 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -7,7 +7,6 @@
 #ifndef __LS2_COMMON_H
 #define __LS2_COMMON_H
 
-
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_FSL_LSCH3
@@ -15,7 +14,6 @@
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
 
-
 #include <asm/arch/ls2080a_stream_id.h>
 #include <asm/arch/config.h>
 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
@@ -297,5 +295,4 @@ unsigned long long get_qixis_addr(void);
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-
 #endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 0dbe95f..924011c 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -72,7 +72,6 @@
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 
-
 #define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index c40f0f2..3ec4bb6 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -119,7 +119,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 
-
 #define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 4aed2de..8ba0512 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -127,7 +127,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 
-
 #define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 0ce422e..094a7e2 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -8,7 +8,6 @@
 #ifndef _CONFIG_LSXL_H
 #define _CONFIG_LSXL_H
 
-
 /*
  * Version number information
  */
@@ -75,8 +74,6 @@
 #undef CONFIG_SF_DEFAULT_SPEED
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
-
-
 /*
  *  Environment variables configurations
  */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 0b1788f..3dc59e4 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -23,7 +23,6 @@
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
 #define CONFIG_440		1		/* ... PPC440 family	*/
 
-
 #define CONFIG_SYS_TEXT_BASE	0xFFF80000
 #define CONFIG_HOSTNAME		lwmon5
 
@@ -425,7 +424,6 @@
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 0a537ce..2070f33 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -36,7 +36,6 @@
 #define CONFIG_CMD_NAND_TRIMFFS
 #define	CONFIG_VIDEO
 
-
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 600eea0..9ababa3 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -43,7 +43,6 @@
 #define CONFIG_CMD_SATA
 #define CONFIG_VIDEO
 
-
 /*
  * Memory configurations
  */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 01f1d83..d12f291 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -25,7 +25,6 @@
 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
 #define CONFIG_BOARD_LATE_INIT
 
-
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 46453c4..cca7c33 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -242,7 +242,6 @@
 #define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
 			 CLOCK_SCCR2_I2C_EN)
 
-
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 
 /* I2C */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index e7d2694..d65a4cd 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -86,7 +86,6 @@
  * Command line configuration.
  */
 
-
 #ifdef CONFIG_SYS_USE_NANDFLASH
 #define CONFIG_CMD_NAND
 #endif
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index e0006d8..93d34e9 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -28,7 +28,6 @@
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
 
-
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 9cc940c..2179f60 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -332,7 +332,6 @@
 #define CONFIG_SYS_PCI_IO_PHYS		0x84000000
 #define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
 
-
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
@@ -450,7 +449,6 @@
 						"1m(u-boot);"		\
 					"mpc5121.nand:-(data)"
 
-
 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
 
 #define CONFIG_DOS_PARTITION
@@ -483,7 +481,6 @@
 	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
-
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 3e99966..5b6880b 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -57,7 +57,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
-
 /* FLASH */
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index bbd2d6b..025a4a6 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -64,7 +64,6 @@
 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
 
-
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h
index 496bc1f..116c821 100644
--- a/include/configs/mv-plug-common.h
+++ b/include/configs/mv-plug-common.h
@@ -8,7 +8,6 @@
 #ifndef _CONFIG_MARVELL_PLUG_H
 #define _CONFIG_MARVELL_PLUG_H
 
-
 /*
  * High Level Configuration Options (easy to change)
  */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 78aa22b..b9992de 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -14,7 +14,6 @@
  /* High Level Configuration Options */
 #define CONFIG_MX31		1		/* This is a mx31 */
 
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -154,7 +153,6 @@
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
 
-
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
  */
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 75d24bf..797eb09 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -19,7 +19,6 @@
 /* High Level Configuration Options */
 #define CONFIG_MX31			/* This is a mx31 */
 
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -175,7 +174,6 @@
 #define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
 
-
 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 #define CCM_CCMR_SETUP		0x074B0BF5
 #define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 9e736eb..5f4142a 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -48,7 +48,6 @@
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
 
-
 /*
  * PMIC Configs
  */
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 0eb5203..48b4dca 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -221,7 +221,6 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV	0
 
-
 #define MX53ARD_CS1GCR1		(CSEN | DSZ(2))
 #define MX53ARD_CS1RCR1		(RCSN(2) | OEN (1) | RWSC(22))
 #define MX53ARD_CS1RCR2		RBEN(2)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 072003c..d777666 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -164,7 +164,6 @@
 					"echo WARNING: Could not determine dtb to use; fi; " \
 			"fi;\0" \
 
-
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt;" \
 	"mmc dev ${mmcdev};" \
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 14acea9..9617e24 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -6,13 +6,11 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #include "mx6_common.h"
 
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
 
@@ -164,7 +162,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -179,7 +176,6 @@
 
 #define CONFIG_IMX_THERMAL
 
-
 #define CONFIG_FSL_QSPI
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SYS_FSL_QSPI_AHB
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index c28a747..71b9fe3 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -6,7 +6,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
@@ -175,7 +174,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
@@ -200,8 +198,6 @@
 
 #define CONFIG_IMX_THERMAL
 
-
-
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SYS_FSL_QSPI_LE
 #define CONFIG_SYS_FSL_QSPI_AHB
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index eb92138..fa79d48 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -8,7 +8,6 @@
 #ifndef __MX6UL_14X14_EVK_CONFIG_H
 #define __MX6UL_14X14_EVK_CONFIG_H
 
-
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 #include "mx6_common.h"
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 3121c03..4f244a9 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -8,7 +8,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
 #define CONFIG_NEO	        1	/*  on a Neo board */
 
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 7696b53..9f16da7 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -320,7 +320,6 @@
 #define CONFIG_PCIE_IMX
 #endif
 
-
 #define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 0b691e4..3e2bcec 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -191,7 +191,6 @@
 #define CONFIG_EXYNOS_ACE_SHA
 #define CONFIG_LIB_HW_RAND
 
-
 /* USB */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_EXYNOS
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 8e438e9..cfe7012 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -92,7 +92,6 @@
 
 #include <config_distro_bootcmd.h>
 
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	ENV_DEVICE_SETTINGS \
 	MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 9aaab01..ab83714 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -282,7 +282,6 @@
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
-
 /* SMSC922x Ethernet */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_SMC911X
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index e9e8da8..99d9fc3 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -77,7 +77,6 @@
 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
 #endif
 
-
 #undef CONFIG_SYS_I2C_OMAP24XX
 #define CONFIG_SYS_I2C_OMAP34XX
 
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 3e7096e..0d62ccd 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -32,7 +32,6 @@
 
 #define CONFIG_UBOOT_ENABLE_PADS_ALL
 
-
 #include <configs/ti_omap4_common.h>
 
 /* GPIO */
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index f7c3aaa..ffed6c5 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -128,5 +128,4 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 100d634..9b5c369 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -78,7 +78,6 @@
 #define CONFIG_LIBATA
 #endif
 
-
 /* SPL */
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 5e63b0c..fba61a4 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -434,7 +434,6 @@
  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
  */
 
-
 /*
  * Local Bus Definitions
  */
@@ -449,7 +448,6 @@
 #define CONFIG_SYS_FLASH_BASE		0xef000000
 #endif
 
-
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 #else
@@ -581,7 +579,6 @@
 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
 
-
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index f094850..b1fd2b8 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -108,10 +108,8 @@
 
 #define CONFIG_NR_DRAM_BANKS	2
 
-
 #define CONFIG_MEMSIZE_IN_BYTES
 
-
 /*---USB -------------------------------------------*/
 #if 0
 #define CONFIG_USB_OHCI
@@ -159,7 +157,6 @@
 #define CONFIG_SYS_ICACHE_SIZE		16384
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
-
 /*
  * BOOTP options
  */
@@ -168,7 +165,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 3a9b8f3..f503520 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -76,7 +76,6 @@ Autobooting
 					/* even with bootdelay=0 */
 #undef	CONFIG_BOOTARGS
 
-
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
 		"mount root filesystem over NFS;" \
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 733ff28..155f589 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -149,7 +149,6 @@
 					  174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
 					  194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
 
-
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	26
 #define CONFIG_SYS_NAND_ECCSTEPS	8
@@ -162,8 +161,6 @@
 /* #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000 */
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
 
-
-
 #define CONFIG_CMD_MTDPARTS
 
 #define CONFIG_CMD_ASKENV /* monitor functions : ask for env variable */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index f883ca3..dcfc774 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -20,7 +20,6 @@
 #include <asm/hardware.h>
 /* ARM asynchronous clock */
 
-
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define MASTER_PLL_DIV		15
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 0fb0a36..92d080e 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -18,7 +18,6 @@
  */
 #include <asm/hardware.h>
 
-
 /* ARM asynchronous clock */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index ba9e6d3..a6472fb 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -22,7 +22,6 @@
  */
 #include <asm/hardware.h>
 
-
 #define CONFIG_PM9G45		1	/* It's an Ronetix PM9G45 */
 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
 
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index 6314365..731b9de 100644
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -13,7 +13,6 @@
 #ifndef _CONFIG_POGO_E02_H
 #define _CONFIG_POGO_E02_H
 
-
 /*
  * Machine type definition and ID
  */
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 1af9ef7..9b394dd 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -10,14 +10,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -70,13 +66,11 @@
 #define CONFIG_HOSTNAME		pr1
 #define CONFIG_TFTP_BLOCKSIZE	4404
 
-
 /*
  * Flash Settings
  */
 #define CONFIG_SYS_NO_FLASH	/* We have no parallel FLASH */
 
-
 /*
  * SPI Settings
  */
@@ -84,7 +78,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -94,14 +87,12 @@
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * NAND Settings
  */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 145a933..7450a1a 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -40,7 +40,6 @@
 #define CONFIG_SYS_I2C_SPEED		400000
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 
-
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300
 
 #undef CONFIG_SPL_NET_SUPPORT
@@ -51,7 +50,6 @@
 
 #define CONFIG_FACTORYSET
 
-
 /* Watchdog */
 #define CONFIG_OMAP_WATCHDOG
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 9e5cbb1..b998052 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -69,7 +69,6 @@
 
 #define CONFIG_SYS_IDE_MAXDEVICE	4
 
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index 88fe641..f19898f 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -45,7 +45,6 @@
 # define CONFIG_SMC911X_BASE (0x84000000)
 #endif
 
-
 /* I2C */
 #define CONFIG_SH_SH7734_I2C	1
 #define CONFIG_HARD_I2C			1
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index d9dde9c..aa130a1 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -70,8 +70,6 @@
 #define CONFIG_ENV_SIZE_REDUND		0x2000
 #define CONFIG_ENV_RANGE		(4 * CONFIG_SYS_ENV_SECT_SIZE)
 
-
-
 #define MTDPARTS_DEFAULT	MTDPARTS_DEFAULT_V3
 
 #ifndef CONFIG_SPL_BUILD
@@ -99,7 +97,6 @@
 "run nand_boot_backup;" \
 "reset;"
 
-
 #else
 #define CONFIG_BOOTDELAY		0
 
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 01c3005..a5ab569 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -70,7 +70,6 @@
 #define CONFIG_SPI_FLASH_GIGADEVICE
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
-
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 02cb94b..c1ea280 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -88,7 +88,6 @@
 #define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
-
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
diff --git a/include/configs/rut.h b/include/configs/rut.h
index cf018e0..bf2cc2f 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -45,7 +45,6 @@
 
 #define CONFIG_FACTORYSET
 
-
 /* Watchdog */
 #define WATCHDOG_TRIGGER_GPIO	14
 
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index c14a247..bdb368e 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -162,7 +162,6 @@
 #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7
 #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6
 
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 4b8fe16..0bdb73a 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -50,7 +50,6 @@
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MD5SUM
 
-
 #define CONFIG_CMD_GPT
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_AMIGA_PARTITION
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 37fdeaa..fc22134 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -395,7 +395,6 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-
 /*
  * BOOTP options
  */
@@ -404,7 +403,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -522,7 +520,6 @@
 	HID0_ENABLE_M_BIT |\
 	HID0_ENABLE_ADDRESS_BROADCAST) */
 
-
 #define CONFIG_SYS_HID2 HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 7e5cdfb..19601e7 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 /*
  * Top level Makefile configuration choices
  */
@@ -472,7 +471,6 @@
 
 #endif	/* CONFIG_PCI */
 
-
 #if defined(CONFIG_TSEC_ENET)
 
 #define CONFIG_MII		1	/* MII PHY management */
@@ -522,7 +520,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -533,7 +530,6 @@
     #define CONFIG_CMD_PCI
 #endif
 
-
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 /*
@@ -613,7 +609,6 @@
    "tftp $fdtaddr $fdtfile;"						\
    "bootm $loadaddr - $fdtaddr"
 
-
 #define CONFIG_RAMBOOTCOMMAND \
    "setenv bootargs root=/dev/ram rw "					\
       "console=$consoledev,$baudrate $othbootargs;"			\
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 298e3ee..f34cef5 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -20,7 +20,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 /* High Level Configuration Options */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_SBC8641D		1	/* SBC8641D board specific */
@@ -67,7 +66,6 @@
 #define BANK_INTERLEAVING		0x22000000
 #define SUPER_BANK_INTERLEAVING		0x23000000
 
-
 #define CONFIG_ALTIVEC          1
 
 /*
@@ -173,7 +171,6 @@
     #define CONFIG_SYS_DDR2_CLK_CTRL	0x03800000
     #define CONFIG_SYS_DDR2_CFG_1B	0xC3008008
 
-
 #endif
 
 /* #define CONFIG_ID_EEPROM	1
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
index d4bba6d..e1c0e9a 100644
--- a/include/configs/secomx6quq7.h
+++ b/include/configs/secomx6quq7.h
@@ -71,7 +71,6 @@
 	"stdout=serial\0"						\
 	"stderr=serial\0"
 
-
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index e5ba30a..1d7fced 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -69,7 +69,6 @@
 #undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 
-
 #define CONFIG_SYS_MEMTEST_START	(SH7785LCR_SDRAM_BASE)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
 					(SH7785LCR_SDRAM_SIZE) - \
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index f9fb9bc..2019156 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -10,7 +10,6 @@
 #ifndef _CONFIG_SHEEVAPLUG_H
 #define _CONFIG_SHEEVAPLUG_H
 
-
 /*
  * Version number information
  */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index b4aa283..aecd06f 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -42,7 +42,6 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_CACHE
 
-
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_ROOTPATH		"/opt/eldk"
@@ -485,7 +484,6 @@
 					"512k(mtdoops)," \
 					"-(rootfs)"
 
-
 #define DFU_ALT_INFO_NAND_V2 \
 	"spl part 0 1;" \
 	"spl.backup1 part 0 2;" \
@@ -577,7 +575,6 @@
 					"512k(mtdoops),"	\
 					"-(configuration)"
 
-
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 54701f3..4daab98 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -235,7 +235,6 @@
 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
 #endif
 
-
 /* Defines for SPL */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		0x0
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index 6b460bf..f009343 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -23,7 +23,6 @@
 
 #define CONFIG_SYS_TEXT_BASE	0x0
 
-
 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* input clock of PLL (the SMDK2410 has 12MHz input clock) */
@@ -60,7 +59,6 @@
  ************************************************************/
 #define CONFIG_RTC_S3C24X0
 
-
 #define CONFIG_BAUDRATE		115200
 
 /*
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 63f6204..0c21deb 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -41,7 +41,6 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-
 /* MMC SPL */
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define COPY_BL2_FNPTR_ADDR	0x00002488
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 3fbc2be..eb53a21 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -88,7 +88,6 @@
 #define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_I2C_MULTI_BUS
 
-
 /*
  * Flash
  */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 9b2313c..4fdc09a 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -6,7 +6,6 @@
 #ifndef __CONFIG_SOCFPGA_COMMON_H__
 #define __CONFIG_SOCFPGA_COMMON_H__
 
-
 /* Virtual target or real hardware */
 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index f45d91f..cf1e904 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -208,7 +208,6 @@
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */
 
-
 /*
  * I2C
  */
@@ -257,7 +256,6 @@
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
 #endif	/* CONFIG_PCI */
 
-
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_TSEC1	1
 #define CONFIG_TSEC1_NAME	"TSEC0"
@@ -295,7 +293,6 @@
 
 #define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
 
-
 /*
  * BOOTP options
  */
@@ -304,7 +301,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -350,7 +346,6 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
 #endif
 
-
 #define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
 
 #define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 63a5b70..269ce7e 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -11,7 +11,6 @@
  * Common configurations used for both spear3xx as well as spear6xx
  */
 
-
 /* U-Boot Load Address */
 #define CONFIG_SYS_TEXT_BASE			0x00700000
 
@@ -176,7 +175,6 @@
 		"console=ttyAMA0,115200 $(othbootargs);"		\
 	CONFIG_BOOTCOMMAND
 
-
 #define CONFIG_ENV_SIZE				0x02000
 #define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
 
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 2c1d4fb..a5b2223 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -637,5 +637,4 @@ int fpga_gpio_get(unsigned int bus, int pin);
 
 #define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND
 
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index bf1b740..b9a8731 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -26,7 +26,6 @@
 	#define CONFIG_SUNXI_USB_PHYS	2
 #endif
 
-
 #ifndef CONFIG_MACH_SUN8I_A83T
 #define CONFIG_ARMV7_PSCI		1
 #if defined(CONFIG_MACH_SUN8I_A23)
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 1ac54e2..64e200e 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -372,7 +372,6 @@
 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
-
 /*
  * External Bus Controller (EBC) Setup
  */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index be68fac..f77e63c 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -98,14 +98,12 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR3
 
-
 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 
-
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
@@ -304,7 +302,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-
 #define CONFIG_BAUDRATE	115200
 
 #define CONFIG_HVBOOT				\
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index b270d9d..ef9e22e 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -316,7 +316,6 @@
 		"fi;"							\
 		"else echo U-Boot not downloaded..exiting;fi\0"		\
 
-
 /*
  * this is common code for all TAM3517 boards.
  * MAC address is stored from manufacturer in
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index d389752..946bfd4 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -22,7 +22,6 @@
 #include <asm/hardware.h>
 #include <linux/sizes.h>
 
-
 #if defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_SYS_ICACHE_OFF
@@ -35,7 +34,6 @@
  * hex number here!
  */
 
-
 #define CONFIG_SYS_TEXT_BASE		0x21000000
 
 /* ARM asynchronous clock */
@@ -299,7 +297,6 @@
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
-
 #define CONFIG_SPL_ATMEL_SIZE
 #define CONFIG_SYS_MASTER_CLOCK		132096000
 #define AT91_PLL_LOCK_TIMEOUT		1000000
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 0f4d959..e017ba9 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf518-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -38,7 +36,6 @@
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			4
 
-
 /*
  * Memory Settings
  */
@@ -56,7 +53,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -77,7 +73,6 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	19
 
-
 /*
  * SPI Settings
  */
@@ -85,7 +80,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -96,14 +90,12 @@
 #define CONFIG_ENV_SECT_SIZE	0x8000
 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * Misc Settings
  */
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index fc98d24..c294f70 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -7,14 +7,12 @@
 
 #include <asm/config-pre.h>
 
-
 /*
  * Processor Settings
  */
 #define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-
 /*
  * Clock Settings
  *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
@@ -41,7 +39,6 @@
 /* Decrease core voltage */
 #define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
 
-
 /*
  * Memory Settings
  */
@@ -58,7 +55,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
-
 /*
  * Network Settings
  */
@@ -83,14 +79,12 @@
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	67
 
-
 /*
  * SPI Settings
  */
 #define CONFIG_BFIN_SPI
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 
-
 /*
  * Env Storage Settings
  */
@@ -115,14 +109,12 @@
 	common/env_embedded.o (.text*);
 #endif
 
-
 /*
  * I2C Settings
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_ADI
 
-
 /*
  * SPI_MMC Settings
  */
@@ -148,5 +140,4 @@
  */
 #include <configs/bfin_adi_common.h>
 
-
 #endif
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 4183867..a5a7fae 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -73,7 +73,6 @@
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PREBOOT
 
-
 /* Keep device tree and initrd in lower memory so the kernel can access them */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"fdt_high=0x10000000\0"		\
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index 4024468..077422f 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -63,7 +63,6 @@
 #define CONFIG_ENV_SIZE_REDUND      0x2000
 #define CONFIG_ENV_RANGE        (4 * CONFIG_SYS_ENV_SECT_SIZE)
 
-
 #define MTDPARTS_DEFAULT	MTDPARTS_DEFAULT_V2
 
 #ifndef CONFIG_SPL_BUILD
@@ -91,7 +90,6 @@
 "run nand_boot_backup;" \
 "reset;"
 
-
 #else
 #define CONFIG_BOOTDELAY		0
 
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index fc16678..7c35d8c 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -15,7 +15,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-
 #define CONFIG_IDENT_STRING	\
 	" for Cavium Thunder CN88XX ARM v8 Multi-Core"
 #define CONFIG_BOOTP_VCI_STRING		"Diagnostics"
@@ -31,11 +30,9 @@
 /* SMP Spin Table Definitions */
 #define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
 
-
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
 
-
 #define CONFIG_SYS_MEMTEST_START	MEM_BASE
 #define CONFIG_SYS_MEMTEST_END		(MEM_BASE + PHYS_SDRAM_1_SIZE)
 
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index b5216a8..83b745a 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -84,7 +84,6 @@
 #define CONFIG_TI816X_USE_EMIF0	1
 #define CONFIG_TI816X_USE_EMIF1	1
 
-
 #define CONFIG_NR_DRAM_BANKS	2		/* we have 2 banks of DRAM */
 #define PHYS_DRAM_1		0x80000000	/* DRAM Bank #1 */
 #define PHYS_DRAM_1_SIZE        0x40000000	/* 1 GB */
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 6a4868c..32877d1 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -76,7 +76,6 @@
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
 					 (64 << 20))
 
-
 #ifdef CONFIG_NAND
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SYS_NAND_BASE		0x30000000
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 202b18c..b049be4 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -112,7 +112,6 @@
 	DFUARGS \
 	NETARGS \
 
-
 #define CONFIG_BOOTCOMMAND \
 	"if test ${dofastboot} -eq 1; then " \
 		"echo Boot fastboot requested, resetting dofastboot ...;" \
@@ -129,7 +128,6 @@
 	""
 #endif
 
-
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 2e729d2..439a4fd 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -281,7 +281,6 @@
 		"sf read ${${fdt_addr}} ${offset} ${size}; "                   \
 		"setenv size ; setenv offset\0"                                \
 
-
 #define CONFIG_BOOTCOMMAND                                                     \
 	"sf probe; run mmcboot; run netboot; run panicboot"                    \
 
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index c67e0bd..8896bc3 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -38,7 +38,6 @@
 #define CONFIG_SYS_RTC_DS1337_NOOSC
 #define CONFIG_CMD_DATE
 
-
 /* LED */
 #define CONFIG_CMD_LED
 #define CONFIG_STATUS_LED
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 2c0e5ed..0c875cb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -14,7 +14,6 @@
 
 #define CONFIG_TRATS
 
-
 #define CONFIG_TIZEN			/* TIZEN lib */
 
 #define CONFIG_SYS_L2CACHE_OFF
@@ -184,7 +183,6 @@
 /* I2C */
 #include <asm/arch/gpio.h>
 
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index bad360e..492a253 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -160,7 +160,6 @@
 /* I2C */
 #include <asm/arch/gpio.h>
 
-
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 41cc9fa..2514e88 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -41,7 +41,6 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap.h>
 
-
 /* Display CPU and Board information */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 870e5a8..c8cc842 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -73,7 +73,6 @@
 #define CONFIG_USB_CLOCK	0x0001BBBB
 #define CONFIG_USB_CONFIG	0x00001000
 
-
 /*
  * BOOTP options
  */
@@ -82,7 +81,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -96,7 +94,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_FAT
 
-
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
 /*
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index face83f..59bf2b3 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -280,7 +280,6 @@
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 
-
 #define CONFIG_TSEC1
 #ifdef CONFIG_TSEC1
 #define CONFIG_HAS_ETH0
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index e924963..a7e1195 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -307,5 +307,4 @@
 #define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
 #define CONFIG_ENV_IS_IN_FLASH		1
 
-
 #endif /* __VEXPRESS_AEMV8A_H */
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index 353b17b..b0737e7 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -34,7 +34,6 @@
 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
 #define CONFIG_SYS_SDRAM_SIZE		0x4000000
 
-
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
 
@@ -54,7 +53,6 @@
 #define CONFIG_ENV_SPI_MODE		(SPI_MODE_0)
 #endif
 
-
 /* MMC */
 #define CONFIG_CMD_MMC
 
@@ -101,12 +99,10 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_MACB_SEARCH_PHY
 
-
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_RNDIS
 
-
 #ifdef CONFIG_SYS_USE_SERIALFLASH
 /* bootstrap + u-boot + env + linux in serial flash */
 #define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 0afa75f..8c72178 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -16,7 +16,6 @@
 
 #define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
 
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index 631f273..af6cbe4 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -62,7 +62,6 @@
 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
 #define CONFIG_RTC_MC13XXX
 
-
 /* mmc driver */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -108,7 +107,6 @@
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
-
 /*
  * Ethernet on SOC (FEC)
  */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 5d8ac41..c59688c 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -107,7 +107,6 @@
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 1cdb10d..265d710 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -129,7 +129,6 @@
 
 #define CONFIG_BOOTDELAY			3
 
-
 /*
  * U-Boot Environment placing definitions.
  */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 7cca864..c72ae72 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -194,7 +194,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /* Default environment */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_HOSTNAME		x86
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index ec26dc1..3ab8eab 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_XLX_H
 #define __CONFIG_XLX_H
 
-
 /*
 #define DEBUG
 #define ET_DEBUG
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index a84099a..3aa21eb 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -299,7 +299,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
-
 /*
  * Networking options
  */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index e66a7f4..72c6c0a 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -15,7 +15,6 @@
 #define CONFIG_MX25
 #define CONFIG_SYS_TEXT_BASE		0xA0000000
 
-
 #define CONFIG_SYS_TIMER_RATE		32768
 #define CONFIG_SYS_TIMER_COUNTER	\
 	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
@@ -83,7 +82,6 @@
  */
 #define CONFIG_CMD_FAT
 
-
 /*
  * USB
  */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 39665ee..4f49ba8 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -389,5 +389,4 @@
 
 #define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
 
-
 #endif /* __CONFIG_ZYNQ_COMMON_H */
-- 
cgit v0.10.2


From ab8243e43145598a55182c3f8ba0784f70526358 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@kernel.org>
Date: Thu, 21 Apr 2016 09:05:23 -0500
Subject: cmd: Kconfig: Add a Kconfig options for a few CMD

Add the following CMD options to Kconfig:

CMD_BOOTZ
CMD_ASKENV
CMD_GREPENV
CMD_USB_MASS_STORAGE
CMD_FAT
CMD_MII
CMD_CACHE
CMD_DFU
CMD_EXT2
CMD_EXT4
CMD_EXT4_WRITE
CMD_FS_GENERIC
CMD_MMC

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[trini: Don't make CMD_USB_MASS_STORAGE nor CMD_DFU depend on CMD_USB]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/Kconfig b/cmd/Kconfig
index f4ec023..9336752 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -160,6 +160,11 @@ config CMD_BOOTM
 	help
 	  Boot an application image from the memory.
 
+config CMD_BOOTZ
+	bool "bootz"
+	help
+	  Boot the Linux zImage
+
 config CMD_BOOTEFI
 	bool "bootefi"
 	depends on EFI_LOADER
@@ -217,6 +222,11 @@ endmenu
 
 menu "Environment commands"
 
+config CMD_ASKENV
+	bool "ask for env variable"
+	help
+	  Ask for environment variable
+
 config CMD_EXPORTENV
 	bool "env export"
 	default y
@@ -235,6 +245,11 @@ config CMD_EDITENV
 	help
 	  Edit environment variable.
 
+config CMD_GREPENV
+	bool "search env"
+	help
+	  Allow for searching environment variables
+
 config CMD_SAVEENV
 	bool "saveenv"
 	default y
@@ -348,6 +363,11 @@ config CMD_ARMFLASH
 	help
 	  ARM Ltd reference designs flash partition access
 
+config CMD_MMC
+	bool "mmc"
+	help
+	  MMC memory mapped support.
+
 config CMD_NAND
 	bool "nand"
 	help
@@ -373,6 +393,17 @@ config CMD_USB
 	help
 	  USB support.
 
+config CMD_DFU
+	bool "dfu"
+	help
+	  Enables the command "dfu" which is used to have U-Boot create a DFU
+	  class device via USB.
+
+config CMD_USB_MASS_STORAGE
+	bool "UMS usb mass storage"
+	help
+	  USB mass storage support
+
 config CMD_FPGA
 	bool "fpga"
 	default y
@@ -461,6 +492,11 @@ config CMD_NFS
 	help
 	  Boot image via network using NFS protocol.
 
+config CMD_MII
+	bool "mii"
+	help
+	  Enable MII utility commands.
+
 config CMD_PING
 	bool "ping"
 	help
@@ -515,6 +551,11 @@ config CMD_BLOCK_CACHE
 	  during development, but also allows the cache to be disabled when
 	  it might hurt performance (e.g. when using the ums command).
 
+config CMD_CACHE
+	bool "icache or dcache"
+	help
+	  Enable the "icache" and "dcache" commands
+
 config CMD_TIME
 	bool "time"
 	help
@@ -619,4 +660,33 @@ config CMD_TPM_TEST
 
 endmenu
 
+menu "Filesystem commands"
+config CMD_EXT2
+	bool "ext2 command support"
+	help
+	  Enables EXT2 FS command
+
+config CMD_EXT4
+	bool "ext4 command support"
+	help
+	  Enables EXT4 FS command
+
+config CMD_EXT4_WRITE
+	depends on CMD_EXT4
+	bool "ext4 write command support"
+	help
+	  Enables EXT4 FS write command
+
+config CMD_FAT
+	bool "FAT command support"
+	help
+	  Support for the FAT fs
+
+config CMD_FS_GENERIC
+	bool "filesystem commands"
+	help
+	  Enables filesystem commands (e.g. load, ls) that work for multiple
+	  fs types.
+endmenu
+
 endmenu
-- 
cgit v0.10.2


From 89cb2b5f8be4f6d04bd87220aa8f72eb0850edc4 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Sun, 24 Apr 2016 17:29:26 -0400
Subject: configs: Re-sync with cmd/Kconfig

Update the config.h and defconfig files for the commands that 8e3c036
converted over to Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
index fd51531..af7f3bf 100644
--- a/arch/arm/include/asm/arch-bcmcygnus/configs.h
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -30,6 +30,4 @@
 #define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
 
-#define CONFIG_CMD_MII
-
 #endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ab4b697..267bd17 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -90,7 +90,6 @@
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_FSL_ERRATUM_A008407
 
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 0c4309f..60b60aa 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -80,7 +80,6 @@
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
 #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
@@ -102,7 +101,6 @@
  */
 #ifdef CONFIG_CMD_IDE
 #define __io
-#define CONFIG_CMD_EXT2
 #define CONFIG_MVSATA_IDE
 #define CONFIG_IDE_PREINIT
 #define CONFIG_MVSATA_IDE_USE_PORT1
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index b8a8c62..4df70d7 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -77,7 +77,6 @@
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
 #define CONFIG_MII		/* expose smi ove miiphy interface */
 #if !defined(CONFIG_ARMADA_375)
 #define CONFIG_MVNETA		/* Enable Marvell Gbe Controller Driver */
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index d4b768d..4f85c22 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ALTERA_PIO=y
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index 5fdaee0..c145caf 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ALTERA_PIO=y
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index b4d7d84..d7725e4 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -10,12 +10,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 7baff24..c39daf1 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -11,11 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index e03d9a8..955b6cf 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -15,11 +15,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 1ac88a4..d2d0cbd 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -17,12 +17,21 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 7a1f2a8..546c84c 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -10,12 +10,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 3093395..5dc4ba3 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -8,12 +8,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index da76a97..e952562 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -11,11 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 7c9150e..cecf4c2 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -13,12 +13,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 3ff15f8..7479f7f 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -15,10 +15,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index e68e747..fde84ac 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -17,10 +17,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 1b3d01d..45539c1 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 8edb572..52dfdf2 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -7,11 +7,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index bcffc47..369afbb 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -8,11 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 6208567..408e84e 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -7,11 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index 300461b..bab96ca 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -7,11 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index f7ff204..10fe1d0 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -8,11 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 75cf823..5e754eb 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -8,11 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index e9c045e..fca6f5a 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -7,11 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index b7ebc98..e833e0c 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,15 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index 3420443..cd27638 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -7,11 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index fdf4954..cdfccbe 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -14,7 +14,10 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 7c3683a..555e446 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -14,7 +14,10 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 831e024..014916c 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -13,7 +13,10 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index c365a45..941fe75 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -13,7 +13,10 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index f766e05..ae8271b 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index 100f1bf..502ba3c 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index 433b62d..d60c0c1 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 2eb85d1..43fa804 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index f0bb1cd..adc42c5 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index f521407..d591a37 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -7,11 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 2708794..034109e 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index df67271..c804b4f 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -7,11 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 072c2e5..49609b7 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index f3d96b3..a64db9bb 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -7,11 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 231dab0..0850d84 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index c775caa..7d7ecd2 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -7,11 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index 2fb85e9..a46d8d7 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index 89f7aa5..3ef15fc 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -7,11 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 43ccad1..307813c 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index 09421e0..aef5e7b 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -7,11 +7,15 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index f7db498..fd6b8de 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -9,12 +9,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 74c7446..ae38583 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -11,12 +11,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO4_VOLT=2500
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index d342640..726e08e 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 5bedcb4..032be47 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index f74c103..a450c60 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index 541ae65..c50234c 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index 7c50ea9..c16559d 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 4ef1840..0eca229 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -9,10 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_I2C=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig
index c00ca1f..25818bd 100644
--- a/configs/CPCI4052_defconfig
+++ b/configs/CPCI4052_defconfig
@@ -9,6 +9,8 @@ CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index a0ed7a0..ab6f329 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index ec30918..080bfbd 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -15,12 +15,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 078243e..6380a22 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -19,12 +19,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 0a1f6cd..683f7f9 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -8,11 +8,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 3f3f812..f8c7107 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -8,10 +8,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 9eff740..0d43c53 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -13,12 +13,21 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 5a15a58..b5959ee 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -16,12 +16,19 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index b60c569..78e94ab 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index 0d86a8f..f03d738 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 7daafb8..7cc162b 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -18,10 +18,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 5b221c3..f424557 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -11,11 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index b9f7f0e..4ff0a6b 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -16,10 +16,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 3959bae..f4832a7 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -8,11 +8,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index f6cae6b..1227994 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 69a082c..3b0d8cf 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -10,11 +10,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 8eeff7b..28768ec 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -8,11 +8,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 4a09f29..11bb709 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -8,10 +8,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 55841e6..8cee863 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_M5208EVBE=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index d3519dd..93e39b4 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -9,5 +9,6 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index b978c02..b63386d 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -8,5 +8,6 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index 6bbacf3..ffb709c 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -7,4 +7,6 @@ CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 979d78c..0885727 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -7,4 +7,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index 9bc8da9..f06379f 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -4,3 +4,4 @@ CONFIG_SYS_TEXT_BASE=0xffe00000
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index 8c4678b..fc29e30 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -3,3 +3,6 @@ CONFIG_TARGET_M5253DEMO=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig
index 2e82cce..15c22df 100644
--- a/configs/M5253EVBE_defconfig
+++ b/configs/M5253EVBE_defconfig
@@ -3,3 +3,6 @@ CONFIG_TARGET_M5253EVBE=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index efcadd6..585ea17 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -5,4 +5,6 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index dec9e63..cd75118 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -7,4 +7,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 7aa36d9..df12b3a 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -5,4 +5,6 @@ CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index c63acd9..b9a4fde 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -3,4 +3,6 @@ CONFIG_TARGET_M53017EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 51d0ba2..dc90334 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -5,4 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index cb79dbd..2850e3a 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -5,4 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 52175cf..9b63e54 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -5,4 +5,6 @@ CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
index fac2fda..be7a37f 100644
--- a/configs/M54418TWR_defconfig
+++ b/configs/M54418TWR_defconfig
@@ -12,6 +12,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
index a013ac8..c04e9ca 100644
--- a/configs/M54418TWR_nand_mii_defconfig
+++ b/configs/M54418TWR_nand_mii_defconfig
@@ -12,6 +12,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
index c29618c..3f454e9 100644
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ b/configs/M54418TWR_nand_rmii_defconfig
@@ -12,6 +12,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
index 522a150..2206554 100644
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
@@ -12,6 +12,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
index 2301738..244fc73 100644
--- a/configs/M54418TWR_serial_mii_defconfig
+++ b/configs/M54418TWR_serial_mii_defconfig
@@ -12,6 +12,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
index fac2fda..be7a37f 100644
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ b/configs/M54418TWR_serial_rmii_defconfig
@@ -12,6 +12,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index 36fa4ea..5f354a8 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -10,6 +10,8 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index e526b46..c43c49d 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -9,6 +9,8 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
index c8ba38c..8e1bcbf 100644
--- a/configs/M54455EVB_a66_defconfig
+++ b/configs/M54455EVB_a66_defconfig
@@ -9,6 +9,10 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index e362886..705b5ae 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -10,6 +10,10 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
index 714c080..a1dd018 100644
--- a/configs/M54455EVB_i66_defconfig
+++ b/configs/M54455EVB_i66_defconfig
@@ -9,6 +9,10 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
index e17382e..3a17303 100644
--- a/configs/M54455EVB_intel_defconfig
+++ b/configs/M54455EVB_intel_defconfig
@@ -9,6 +9,10 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index ce2dd81..52441d4 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -9,6 +9,10 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index 2131e0e..3bad5d0 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index ead78c8..d3ff58b 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index 04a31fd..670bda5 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index 242acc8..4a49e90 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index 3641a55..8e90823 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index c0d1c5e..e26b1fe 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index 57c5770..e79d991 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index 917d4bd..abdf504 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index 1dc119a..0708f18 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index 73c4d8a..de2c9f1 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index 46ea740..cc93f81 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index f2ae822..d084d58 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index f2b3f62..0e1b285 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index 83f39b02..66e5316 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index 2e5bda4..9ec6c45 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -6,4 +6,6 @@ CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig
index c2bc17c..0d0c029 100644
--- a/configs/MIP405T_defconfig
+++ b/configs/MIP405T_defconfig
@@ -6,5 +6,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig
index c243de8..aa23499 100644
--- a/configs/MIP405_defconfig
+++ b/configs/MIP405_defconfig
@@ -6,5 +6,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index f8bf52a..ca61e5c 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -6,10 +6,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 0ae4c7f..9e6f50b 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -6,9 +6,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 96c9d54..978e231 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -9,6 +9,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 1d004fe..35db541 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -9,6 +9,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 893657e..63c6d7b 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -10,6 +10,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index cb3c686..a3d5294 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -10,6 +10,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index 97e7672..dfb41f0 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -7,6 +7,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index 7f6156c..cf2f655 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8323ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index 759165d..0c85f40 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 08f1a41..e9cf0c8 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 43d121c..9272431 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 079d017..d807884 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index cf38f89..8900665 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 988e33a..60561cf 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 2506e77..fb7485c 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -10,5 +10,6 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 80eb01b..65edb63 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -11,5 +11,8 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 4c8cfce..358656e 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -11,5 +11,8 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index b459a40..0e09e77 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -5,9 +5,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index 687fcfa..f7ad159 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -4,8 +4,12 @@ CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index a1982e5..1b2c787 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_MPC837XERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index c70ec54..40d1a3a 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -5,10 +5,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index 4343d40..c6afe45 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -5,10 +5,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index 003099d..eafa11c 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -5,10 +5,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index a746dbe..0ae81ef 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -4,10 +4,14 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index 4e8b93d..ddc3b5b 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index 1c2316f..a340c8b 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index 83c0191..06569e2 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -6,7 +6,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_RTL8139=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 06edf18..d038267 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 3b89bda..a42d991 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 21819a3..3a730f9 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index e2de2a2..86db71c 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index d09370e..485e987 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 142d8bf..5ec3712 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index 8968ee8..daacef7 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -5,8 +5,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="ATM"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index efbb008..26ab184 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -4,8 +4,12 @@ CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index b2c5a70..1720d9e 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -9,7 +9,9 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index c55289a..63cf745 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -8,7 +8,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index 38e2034..6883249 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -7,6 +7,8 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index b8dede6..c85ddfe 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -9,5 +9,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index 98bf168..d71369e 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -8,5 +8,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index d335173..a9d5aae 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -11,9 +11,16 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 3169c92..14db5ae 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -14,11 +14,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 626fb4c..cb9ca3b 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -6,11 +6,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index 2665a64..bae638f 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index b8c8f78..9311799 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -8,10 +8,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 82d91da..831578e 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index ba59216..d628c7c 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -11,11 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 725554d..35df225 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -10,11 +10,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 8d298f8..8a4980e 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 47a12a4..842db29 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -9,8 +9,15 @@ CONFIG_MMC0_CD_PIN="PH18"
 CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index ab2835c..102b96c 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -7,11 +7,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index d9e609c..bad6a39 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index 929e381..f7d7f00 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -6,5 +6,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index 181a69e..31e309f 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -10,5 +10,7 @@ CONFIG_AUTOBOOT_STOP_STR="++++++++++"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index 9e45ecd..eb65c22 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -9,5 +9,7 @@ CONFIG_AUTOBOOT_STOP_STR="++++++++++"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index f79b3e5..67a7757 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -6,5 +6,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index b40b709..7a29872 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -6,5 +6,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index 9327068..4f35c2e 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -7,5 +7,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index de360dc..77d1879 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -7,5 +7,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index 4425621..6d91a11 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -7,5 +7,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index b3a656a..e135f93 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -6,5 +6,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index 0fb75c5..b6bc88e 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -6,5 +6,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 3631181..212f98c 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -12,11 +12,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 9734edf..148b4fa 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -14,11 +14,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index c959a2e..af6a4be 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 6c8bcfd..5ed93a1 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 6338a08..2c05f6e 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index d084188..4dbff83 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 2de562f..f421b22 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index 148748d..f0a74fd 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index acf03c6..6bd7dcb 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index 788fe9e..b8968a8 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index d6138f9..551b9db 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index b0df9d2..7d8ebfe 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index fd8508a..6fd23ac 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 4e047f7..1f29b11 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 3a74a15..6da92e4 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 8a124ef..fa7cab8 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 94c5b29..860bc6a 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 1e7e5c3..23d938b 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index a6efbba..5bc446b 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 4971dcb..7b83294 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index f86a05b..234645e 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index b02b1d3..7adcca8 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 1bfba42..c455059 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 75b064f..45f54f7 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 259c443..7d6de18 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index 11bc5e3..629fbbb 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index b26fbcb..8f44aee 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 2c88ee8..37ebca3 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 80f1daf..6d6edd1 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index f79e913..d21afae 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index 553e5da..a0e4471 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -8,9 +8,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index a93663f..d209581 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -7,9 +7,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index 9c3a6f7..d07ed43 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -8,9 +8,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 9133731..0fe87d1 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -7,9 +7,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index d22bac7..735c53f 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index e046e40..953552d 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index dc6d861..ec94e06 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index a486593..044e739 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index cc2a569..3bd72f0 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index a7c00df..a9a659c 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 08286f7..f01dbc3 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 6a8bc3c..37e14da 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 23e05d5..63faa06 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 872a247..255b8e2 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 82a318e..61a635a 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index f5e8a1b..f8e633a 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index 442d43a..d6775d9 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -8,9 +8,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 0f4519c..054e9fc 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -7,9 +7,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index 93fe60c..b0553ef 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -8,9 +8,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 6118f0f..36f7366 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -7,9 +7,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index 108b467..b24f8ec 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index b17a3a0..8f618ae 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 83027ad..70e4d44 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index 1d76a55..e119bef 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 622ed59..772a313 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 72d5835..9206cc7 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 2fff1ab..85c03aa 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index 341f905..ae78a8e 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index a57882f..af98b8e 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index edb6476..0ea0201 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index c54094e..4093449 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 6b6811d..24e8678 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index c7e2cfd..cbc3d76 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 7e321a4..8c36f58 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index 4f68c00..1c7b323 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index 2b1925f..b5dee33 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -6,10 +6,14 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index cc31300..bdf91d2 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -8,7 +8,10 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index 13546c3..bcc0aed 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index b80d2d9..dc74708 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index 5250e16..a59ddde 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 2ba4ceb..9993593 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 4feecb5..8f723c6 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index 6e5b913..5285f79 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index cef9432..ec6038c 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 0949ae1..6ba76fa 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 35fbc67..86b9cd7 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index b1afcc0..f7ce9b6 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 19dee97..21d98e3 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index a48bdb9..ce42c82 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index abcb328..c8f86e2 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index ec3d1e2..a6a01e8 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 9faa181..0f10e08 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -9,10 +9,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index d463d9d..8649e52 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index f8f3f14..1764f2c 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -8,10 +8,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 84338ce..b9610e4 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -7,10 +7,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 8e3df02..d4b1c55 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 02401e6..a36e731 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 568e44d..4d40511 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 85c45f2..c2dbd98 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index db34b71..3dbf5a3 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 91da52a..aea98c6 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -6,11 +6,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index 16b8770..d5b1c12 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index aed8b9c..dfe0e17 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index e8910b9..a8e2131 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index 6abde1b..13e2fed 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index ed37b05..901c373 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index 6882a6d..f9285a8 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index e8fa833..d648d97 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -6,11 +6,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index e3f6724..aaa97f7 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index eb89714..437e05a 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index c8eb351..a3f0d85 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index 23353c7..7059c81 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 3a2e976..752a6c6 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -6,11 +6,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index c2112fa..2ecb0b8 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index 61b4f21..c26e729 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index c823f05..acc617e 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index d220264..24d4f17 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index df41373..3e97ee0 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index b831253..f381326 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index 8efb577..d7145ae 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -6,11 +6,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index fd3ccfa..0495c4d 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 068cb68..9be5ff1 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index c3149d8..6675164 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 4828534..552d93a 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 1793865..2caec57 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index ed72c24..07e67c8 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -6,11 +6,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig
index c9fb9d4..fe88739 100644
--- a/configs/PIP405_defconfig
+++ b/configs/PIP405_defconfig
@@ -6,5 +6,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig
index 9fe4dc4..c1795a4 100644
--- a/configs/PLU405_defconfig
+++ b/configs/PLU405_defconfig
@@ -9,6 +9,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig
index ccbd7b3..8f60d87 100644
--- a/configs/PMC405DE_defconfig
+++ b/configs/PMC405DE_defconfig
@@ -9,6 +9,7 @@ CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig
index f80410f..4d060ab 100644
--- a/configs/PMC440_defconfig
+++ b/configs/PMC440_defconfig
@@ -10,6 +10,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 2fdb844..4136841 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -13,11 +13,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 011dfd6..03cef97 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -7,8 +7,15 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index b39164b..dc781db 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 878d22f..13dbb98 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -16,11 +16,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 0957dc3..9a916c9 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -9,13 +9,18 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index f9dd7db..2c41d03 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -9,13 +9,18 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index 9577fe2..e3cf48d 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index e0b3ae1..5ce9ed9 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -9,13 +9,18 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index ec0609f..44c9584 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -7,12 +7,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index ef01c2e..6c4505f 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index f3235bf..0af7eab 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index 2be1046..efdcbeb 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 1bca42a..12a0376 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index b22bba8..84da583 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index a9bea77..03d009f 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index 622e560..a70963f 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index ecd027f..a012f3d 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 77e93b4..d7cce8b 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 68ac112..ceae6cf 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 3443db8..1359aad 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index d11b954..7ffacd4 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -7,12 +7,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index 3fb702d..a07a59a 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index acfa55f..e4c095e 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index 777c448..a2c1495 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index c1e16b2..9a78aa9 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index 3d1040e..f2415d9 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index 8399ec8..df9e295 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index a7998bb..7f889c7 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index 9c21b33..f93f0b9 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 6ed2f86..023dc37 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index 10dfd33..bacb060 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index b9bb5be..9d6d9fb 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index f33805b..b5a050c 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index 8dcf3e5..a50f177 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 4620e54..f70d5ce 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 54ffb94..4f21813 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 0ca5bb0..07bdcf6 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index ba4b274..a49d32d 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 488923e..23f83e6 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 3a52ea9..1935dad 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index c3d7cf6..f093e92 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index 0b608a9..f7126e5 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index aa66095..f0aed08 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index dbb5bb6..0057e22 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 09b5bf5..8905b6c 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 51d452b..2459eba 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 33da1b4..b937af4 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index ba7f61d..049819e 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index c1c7e42..8634477 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 6753118..40c871e 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 36dc163..795a3f0 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 147ce69..c6e0710 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -9,11 +9,15 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index ebbb9e1..51caeeb 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -9,11 +9,15 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index d57cc6d..f4190af 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -9,11 +9,15 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 8bac4a0..9d4821d 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -9,11 +9,15 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index ad5ce54..0a15e05 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -10,11 +10,15 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 20ccc45..955b394 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -8,11 +8,15 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 1589d31..0b0e120 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index fa04188..bffca40 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index 0100ad9..fc8f1f5 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index 17e95d2..ed075eb 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index ce8453f..844fe10 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 20fd55a..92b0391 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index cc056d5..2a30e11 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 4483184..37aac2a 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index b4533ab..3b13a34 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 5a90b2b..3523fe1 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index 423f4ed..c2a16fd 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index eceac1a..3ec6c75 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index dde4f56..18c8e67 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index eea72e3..c590410 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,12 +8,17 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index 1c38761..afb665d 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 2c1847f..85fd13b 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -8,11 +8,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 9af072d..21e22be 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -7,11 +7,16 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_NETDEVICES=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index 1269e39..7adc71c 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index d8a724a..f098954 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index abecdb4..70eb383 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index 86e8572..6734495 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index 7592cc5..d0adb77 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index 90821b3..4456361 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -3,11 +3,15 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index b60d087..9bf21f5 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -4,7 +4,9 @@ CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 28ad9e1..9f3218b 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index c569b24..9a0ba9d 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index f8d9df8..00dd80d 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -4,9 +4,11 @@ CONFIG_TARGET_TQM834X=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 9e71d16..088ed6d 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM850L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index 77a9a6c..ab3c44b 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM850M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index 4d443c5..6ece068 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM855L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index 344da70..9940f96 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM855M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index 6c47c3e..4aec4ff 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM860L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index 2a65fd9..12b090a 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM860M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index e20def2..41737a3 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM862L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index 61a993f..642dd02 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM862M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index e3ca7c7..3d0bf8c 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -3,7 +3,9 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM866M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index 5b8b869..2238cdd 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -3,9 +3,12 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM885D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index 2c823db..df4efa4 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -4,7 +4,9 @@ CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 40d22fb..8d2f2e6 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -7,9 +7,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
index d532e5f..bd976fe 100644
--- a/configs/UCP1020_SPIFLASH_defconfig
+++ b/configs/UCP1020_SPIFLASH_defconfig
@@ -10,13 +10,17 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b"
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index 3472c07..0e21822 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -10,13 +10,17 @@ CONFIG_SYS_PROMPT="B$ "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b"
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index bad17c3..948107c 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -21,11 +21,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
index 8bf5717..4c2df57 100644
--- a/configs/VCMA9_defconfig
+++ b/configs/VCMA9_defconfig
@@ -7,3 +7,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig
index 3f80c58..8fb023a 100644
--- a/configs/VOM405_defconfig
+++ b/configs/VOM405_defconfig
@@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index f25a296..d754ccd 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -14,11 +14,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 6eaa9d6..4a7dbdb 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -13,11 +13,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 84200e8..0b40b83 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -8,10 +8,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 3163ca8..fab74f4 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -20,10 +20,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 440fd54..71f01db 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -17,10 +17,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index b47e308..97e4fc5 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -8,7 +8,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_CACHE=y
 CONFIG_LIB_RAND=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig
index c724993..5111bc0 100644
--- a/configs/a4m072_defconfig
+++ b/configs/a4m072_defconfig
@@ -10,6 +10,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index 7bbecf3..fc344c5 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -9,7 +9,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_CACHE=y
 CONFIG_LIB_RAND=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig
index d839fc8..36fb7af 100644
--- a/configs/ac14xx_defconfig
+++ b/configs/ac14xx_defconfig
@@ -4,8 +4,10 @@ CONFIG_TARGET_AC14XX=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_PROMPT="ac14xx> "
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index d98ff2d..31889fa 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -3,10 +3,13 @@ CONFIG_4xx=y
 CONFIG_TARGET_ACADIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 8a2f7de..6daefcc 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -1,6 +1,10 @@
 CONFIG_NDS32=y
 CONFIG_TARGET_ADP_AG101P=y
 CONFIG_SYS_PROMPT="NDS32 # "
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index a23d59f..bfa243f 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_ALT=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -20,8 +22,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index ea6e0f9..78f55cc 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -8,15 +8,24 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 7cd15dd..d310e0b 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -10,16 +10,26 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DFU_TFTP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 0231eed..903f518 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -13,16 +13,26 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index fade82f..62f26b5 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -10,16 +10,26 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 6dc4e25..f230671 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -7,15 +7,25 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 239b607..3fbc07b 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -4,15 +4,25 @@ CONFIG_NOR=y
 CONFIG_NOR_BOOT=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 896f060..65d88d8 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -6,16 +6,26 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index f6b173f..eee5e9b 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -6,16 +6,26 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index b069e3c..d7f126e 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -7,16 +7,26 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
index 424018a..d6022a3 100644
--- a/configs/am335x_igep0033_defconfig
+++ b/configs/am335x_igep0033_defconfig
@@ -4,13 +4,22 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index dbc44b1..c227ef4 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -6,13 +6,22 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index b860870..a8b8465 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_PROMPT="AM3517_CRANE # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -14,4 +15,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index fa169fa..d400c35 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -6,9 +6,12 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_EVM # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -16,6 +19,12 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index d634fbd..03b02ac 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -8,16 +8,26 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 66b88a1..48ec91f 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -10,16 +10,26 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DMA=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index fd97124..a6ae011 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -3,16 +3,26 @@ CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 3065710..662556a 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -3,16 +3,26 @@ CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index e92d918..00fa6be 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -2,16 +2,26 @@ CONFIG_ARM=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index f6f6375..e3d6b57 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -3,16 +3,26 @@ CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 608f172..8fc3ebb 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -8,15 +8,24 @@ CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 32a94b3..47d103b 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -3,14 +3,23 @@ CONFIG_OMAP54XX=y
 CONFIG_TARGET_BEAGLE_X15=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 25826ca..f169fd3 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -9,4 +9,5 @@ CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig
index 5c15b71..5192032 100644
--- a/configs/ap325rxa_defconfig
+++ b/configs/ap325rxa_defconfig
@@ -16,4 +16,5 @@ CONFIG_TARGET_AP325RXA=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig
index df7c344..77a0aa5 100644
--- a/configs/ap_sh4a_4a_defconfig
+++ b/configs/ap_sh4a_4a_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index dcf1a3e..40a65d2 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -7,16 +7,26 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Apalis T30 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_E1000=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 2945e91..88912e5 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -4,9 +4,15 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="BIOS> "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index 92e3046..0df8ac0 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -4,9 +4,14 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index 64adfd7..e05a64c 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -5,9 +5,13 @@ CONFIG_ARCHES=y
 CONFIG_DEFAULT_DEVICE_TREE="arches"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index 1c8c8a7..fb3257b 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -3,8 +3,10 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_ARIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 8a75880..0f68eba 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -4,14 +4,23 @@ CONFIG_TARGET_ARISTAINETOS2=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 623f7b8..2457513 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -4,14 +4,23 @@ CONFIG_TARGET_ARISTAINETOS2B=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index ae5ade4..ad2bf08 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -4,14 +4,23 @@ CONFIG_TARGET_ARISTAINETOS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 06a7630..1224da4 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_ARMADILLO_800EVA=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -18,6 +19,7 @@ CONFIG_TARGET_ARMADILLO_800EVA=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 259cb22..0cd529e 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -8,15 +8,24 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ARNDALE # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 118f96b..9888c7e 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -6,3 +6,4 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index 3776bda..bea73a5 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -3,9 +3,12 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 0c69da8..8012531 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -4,9 +4,12 @@ CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 014cb95..d8ec7f1 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index a755103..eb17f91 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index bb65e89..26ffd97 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index e196e8a..4e8dfa1 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -13,4 +13,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 4c26cc1..c5684f2 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -13,4 +13,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 34e6ff1..0fba314 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -13,4 +13,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 2978f2d..b09395f 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -5,13 +5,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 2978f2d..b09395f 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -5,13 +5,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index 6e30d94..dd46a68 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -5,13 +5,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 5b35645..25b9a17 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -5,13 +5,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index cca6b13..3cdce9b 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -5,13 +5,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index ef1af38..9ff65b5 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -13,4 +13,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index d5c9a98..76c3b15 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -13,4 +13,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 7de00c6..7438b86 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -13,4 +13,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index db0af22..0cded82 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -4,13 +4,16 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index 7bb5fd5..ddfce14 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -4,13 +4,16 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index c7b5faf..8ce99ee 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 4f89b50..9ed2b84 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index 063284d..f8f6afb 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 663433d..c931af2 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -6,13 +6,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index e1a1bfc..4aeca48 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -6,13 +6,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 4f429cc..2c4a81a 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -4,14 +4,17 @@ CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 4b27ab3..726d811 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -5,14 +5,17 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 25f5a35..d0cff22 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -5,14 +5,17 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 6dc8dbc..dda3edf 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -5,12 +5,15 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index dcf8ec6..c300438 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -5,12 +5,15 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 3e825aa..6b033fb 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -5,12 +5,15 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index c4a0808..56aa2a0 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 62756f6..db501c5 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index aad7e85..7f0b1a4 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -5,15 +5,18 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 310de74..f7a4d16 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -5,15 +5,18 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 861c3ff..0ded2ab 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 2b8fa1b..7995419 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index 2a1fde8..c859cb6 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
@@ -13,4 +14,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig
index 02f6f97..685d5ac 100644
--- a/configs/atngw100_defconfig
+++ b/configs/atngw100_defconfig
@@ -7,11 +7,15 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig
index b45c426..c392df7 100644
--- a/configs/atngw100mkii_defconfig
+++ b/configs/atngw100mkii_defconfig
@@ -7,10 +7,15 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig
index 47c1a35..bd37d2e 100644
--- a/configs/atstk1002_defconfig
+++ b/configs/atstk1002_defconfig
@@ -7,7 +7,11 @@ CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index fbdd4f2..ba43e35 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_TAURUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index b79dd3c..85af09e 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -7,10 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x"
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index a208a27..aa9bf33 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -7,10 +7,12 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x"
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 863169a..b61b15c 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -11,11 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index de5a857..b0f6bb3 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -3,11 +3,17 @@ CONFIG_4xx=y
 CONFIG_TARGET_BAMBOO=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 4c03856..ce1f519 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -26,6 +27,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index aaeb555..b8ec8ac 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -2,13 +2,18 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index f693095..6021fd2 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -2,13 +2,18 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 75fbe46..bfd519e 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -1,13 +1,18 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 299ffa0..1911122 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -2,13 +2,18 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index 68109d8..d8a30d1 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -2,10 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index 6cf2186..205db1e 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -2,10 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index ec7370f..bcb24b4 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -2,10 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index b939927..527f4a5 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -2,10 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index ec7370f..bcb24b4 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -2,10 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index ec7370f..bcb24b4 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -2,10 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index e149735..6d06b4e 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -2,9 +2,13 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMNSP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
index c7e223a..3e61a3f 100644
--- a/configs/bct-brettl2_defconfig
+++ b/configs/bct-brettl2_defconfig
@@ -5,6 +5,8 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index f0921e8..b9323c2 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -7,19 +7,29 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
index 41f1490..0b6f517 100644
--- a/configs/bf518f-ezbrd_defconfig
+++ b/configs/bf518f-ezbrd_defconfig
@@ -1,14 +1,19 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF518F_EZBRD=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index 614a137..85c2a6b 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -7,9 +7,13 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
index 793ccfe..b5f5f5d 100644
--- a/configs/bf527-ad7160-eval_defconfig
+++ b/configs/bf527-ad7160-eval_defconfig
@@ -1,6 +1,7 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_AD7160_EVAL=y
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -8,6 +9,9 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index 9035165..ff797f8 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -8,9 +8,13 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index 0b63ece..eff2a12 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -6,9 +6,13 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_NET_TFTP_VARS is not set
 CONFIG_SPI_FLASH=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
index a15b92b..5137293 100644
--- a/configs/bf527-sdp_defconfig
+++ b/configs/bf527-sdp_defconfig
@@ -8,6 +8,7 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
index 84def80..6b2395a 100644
--- a/configs/bf533-ezkit_defconfig
+++ b/configs/bf533-ezkit_defconfig
@@ -7,5 +7,6 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
index af9ebd2..ef23ea7 100644
--- a/configs/bf533-stamp_defconfig
+++ b/configs/bf533-stamp_defconfig
@@ -8,6 +8,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 # CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
index b7e11af..7c17cbb 100644
--- a/configs/bf537-minotaur_defconfig
+++ b/configs/bf537-minotaur_defconfig
@@ -8,6 +8,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig
index 9190de8..cb01bc1 100644
--- a/configs/bf537-pnav_defconfig
+++ b/configs/bf537-pnav_defconfig
@@ -6,9 +6,11 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
index 49a6fed..f8288d9 100644
--- a/configs/bf537-srv1_defconfig
+++ b/configs/bf537-srv1_defconfig
@@ -8,6 +8,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
index dc61dfd..15e5254 100644
--- a/configs/bf537-stamp_defconfig
+++ b/configs/bf537-stamp_defconfig
@@ -1,14 +1,19 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_STAMP=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
index 5ca81e8..2c71498 100644
--- a/configs/bf538f-ezkit_defconfig
+++ b/configs/bf538f-ezkit_defconfig
@@ -8,5 +8,6 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 # CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index c7277f2..6d398ac 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF548_EZKIT=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -10,6 +11,9 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index 7e5d007..3ecdd9f 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -8,8 +8,10 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
index 987b58a..1e99b4b 100644
--- a/configs/bf561-ezkit_defconfig
+++ b/configs/bf561-ezkit_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig
index 71e8406..68788a6 100644
--- a/configs/bf609-ezkit_defconfig
+++ b/configs/bf609-ezkit_defconfig
@@ -1,12 +1,17 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF609_EZKIT=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 1388370..709dfab 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -2,13 +2,16 @@ CONFIG_ARM=y
 CONFIG_TARGET_BG0900=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 14c0ce3..44ed671 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -5,16 +5,27 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index aebf7f1..861bdcf 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -5,16 +5,27 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig
index 2415b43..679aee1 100644
--- a/configs/blackstamp_defconfig
+++ b/configs/blackstamp_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig
index c6b87b2..808cc3d 100644
--- a/configs/blackvme_defconfig
+++ b/configs/blackvme_defconfig
@@ -5,6 +5,8 @@ CONFIG_TARGET_BLACKVME=y
 CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
index 0ca6567..db5d915 100644
--- a/configs/br4_defconfig
+++ b/configs/br4_defconfig
@@ -9,9 +9,11 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index facf9fd..d570d41 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -3,9 +3,12 @@ CONFIG_4xx=y
 CONFIG_TARGET_BUBINGA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index b375453..2eefd15 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 96f8ea0..a8775f3 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -4,15 +4,24 @@ CONFIG_TARGET_OMAP3_CAIRO=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Cairo # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index 1f88b66..5f6bc5c 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -5,8 +5,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Calimain > "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR="\x0b"
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index da6f1d5..7224588 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -4,10 +4,12 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index ef63089..00d8045 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -4,10 +4,12 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig
index 5caea0d..8d3b476 100644
--- a/configs/canmb_defconfig
+++ b/configs/canmb_defconfig
@@ -1,6 +1,8 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CANMB=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_SNTP=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index d95fe73..aac031b 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -5,12 +5,18 @@ CONFIG_CANYONLANDS=y
 CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 42e0b2c..979b693 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -7,9 +7,11 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -19,7 +21,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index d164d1a..68cf2ac 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -5,15 +5,26 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index f391963..ea50729 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -3,11 +3,15 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_CHARON=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index ef0e95b..25ead92 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -10,17 +10,25 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
 CONFIG_REGMAP=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 8088f0c..91e902f 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -27,6 +27,11 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 20ea99a..238eeac 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -26,6 +26,11 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index e18c3c7..245f164 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -23,6 +23,11 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 9ecf08e..0fde640 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -4,8 +4,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -13,8 +15,14 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_DEBUG_UART=y
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
index a9dafeb..072483a 100644
--- a/configs/cm-bf527_defconfig
+++ b/configs/cm-bf527_defconfig
@@ -4,8 +4,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
index 14b959c..1fb91b2 100644
--- a/configs/cm-bf533_defconfig
+++ b/configs/cm-bf533_defconfig
@@ -5,5 +5,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
index 6366048..c65a703 100644
--- a/configs/cm-bf537e_defconfig
+++ b/configs/cm-bf537e_defconfig
@@ -1,12 +1,17 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537E=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
index 67b04d1..b030a27 100644
--- a/configs/cm-bf537u_defconfig
+++ b/configs/cm-bf537u_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537U=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
@@ -8,5 +9,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
index 90187bd..1355dd4 100644
--- a/configs/cm-bf548_defconfig
+++ b/configs/cm-bf548_defconfig
@@ -7,6 +7,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 # CONFIG_REGEX is not set
 CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
index 086a05a..b6e711e 100644
--- a/configs/cm-bf561_defconfig
+++ b/configs/cm-bf561_defconfig
@@ -5,5 +5,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
index 7f854f9..c7df400 100644
--- a/configs/cm5200_defconfig
+++ b/configs/cm5200_defconfig
@@ -2,11 +2,14 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 13612f7..4193764 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -6,11 +6,14 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-FX6 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -19,6 +22,12 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index bf8d21e..1b29331 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -3,12 +3,21 @@ CONFIG_TARGET_CM_T335=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T335 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 774e259..72283a6 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -3,8 +3,10 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T3517=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3517 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -12,6 +14,9 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 32d73ec..9a7b205 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -4,8 +4,10 @@ CONFIG_TARGET_CM_T35=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3x # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -13,5 +15,8 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index e9494dd..c926a3a 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -5,8 +5,11 @@ CONFIG_DM_GPIO=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T43 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -15,7 +18,13 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index a372aa3..bcab16b 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -5,8 +5,11 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T54 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -14,6 +17,12 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 6926104..0bcb9a2 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -5,9 +5,12 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index c174b9c..a3b2a3c 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -7,16 +7,27 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri T20 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 24f0763..c920b39 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -7,16 +7,26 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri T30 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 9e37e21..df17f2e 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -7,14 +7,23 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri VFxx # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 95d55be..655a0e7 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -17,11 +17,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO2_VOLT=1800
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index a802bbd..5186345 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -26,6 +27,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index aa53c60..7cc9a6e 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -9,11 +9,15 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index e4de7aa..ee7739a 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -9,11 +9,15 @@ CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
index 59072cc..be8174b 100644
--- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TPM=y
 CONFIG_DM=y
diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig
index b1e3a80..74b5266 100644
--- a/configs/controlcenterd_TRAILBLAZER_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TPM=y
 CONFIG_DM=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index e614122..2fa11fd 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -18,6 +18,11 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 44fb275..37488dd 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -6,10 +6,12 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 60a6727..78bda52 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -14,6 +14,11 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 5d0079e..7c6b692 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -14,6 +14,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -24,6 +25,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 8f85ca0..0b77b1b 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -11,7 +11,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index 8772ec8..8fd51ad 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -5,12 +5,17 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 64bed91..866d187 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -6,12 +6,17 @@ CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 2105ebf..0bb2d37 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -4,9 +4,11 @@ CONFIG_TARGET_DA850EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index a2a6e23..75eaad8 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -7,19 +7,29 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index 802e684..e9ba1ef 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -14,8 +14,14 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_MISC=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index c656c94..7ad3bb6 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -13,8 +14,14 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 373773d..44f64fd 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -14,8 +14,14 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_NAND_PXA3XX=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index 5d55c49..5449cff 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -5,11 +5,17 @@ CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index b659da6..eca6e86 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -12,7 +12,10 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 0e1cfc5..c8021c6 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -6,10 +6,14 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 214a1ae..2b6dba8 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -17,10 +17,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
index ad8292f..67fda76 100644
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_RAMBOOT_defconfig
@@ -14,5 +14,9 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
index e87618f..e05583f 100644
--- a/configs/digsy_mtc_defconfig
+++ b/configs/digsy_mtc_defconfig
@@ -12,5 +12,9 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
index cd24c16..424c214 100644
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
@@ -14,5 +14,9 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
index e617acc..4579ab6 100644
--- a/configs/digsy_mtc_rev5_defconfig
+++ b/configs/digsy_mtc_rev5_defconfig
@@ -14,5 +14,9 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index 5565bb8..1ebfd23 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -8,9 +8,12 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index 6554fb3..7b28d1d 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -6,8 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dnp5370_defconfig b/configs/dnp5370_defconfig
index 1da61c1..b6d3b74 100644
--- a/configs/dnp5370_defconfig
+++ b/configs/dnp5370_defconfig
@@ -2,5 +2,6 @@ CONFIG_BLACKFIN=y
 CONFIG_TARGET_DNP5370=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index ac236cd..a3d053d 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -7,6 +7,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 2fecf39..6ae447c 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -7,6 +7,9 @@ CONFIG_SYS_PROMPT="DockStar> "
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 9b5cd78..00c6ac3 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -11,16 +11,26 @@ CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 47fd428..a11dcd5 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -10,16 +10,26 @@ CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_MMC=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 41cdbbf..b6458ae 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -5,16 +5,26 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
index 15e94a0..8ebfe49 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/dra7xx_evm_qspiboot_defconfig
@@ -6,16 +6,26 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
index ccc2124..54c7ba9 100644
--- a/configs/dra7xx_evm_uart3_defconfig
+++ b/configs/dra7xx_evm_uart3_defconfig
@@ -7,16 +7,26 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index bfee48a..0a437ed 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -7,15 +7,21 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 68b5de4..2566ded 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -6,11 +6,18 @@ CONFIG_SYS_PROMPT="dragonboard410c => "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_CLK=y
 CONFIG_MSM_GPIO=y
 CONFIG_PM8916_GPIO=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index c6b3b53..d293e30 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -8,7 +8,11 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index fb5d916..4d3cb34 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -13,8 +13,11 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 254440f..b0791b9 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -15,10 +15,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index 41f669b..ad564e4 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -4,8 +4,11 @@ CONFIG_TARGET_DUOVERO=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="duovero # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -13,6 +16,12 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
index c23a298..eb01dec 100644
--- a/configs/e2220-1170_defconfig
+++ b/configs/e2220-1170_defconfig
@@ -8,16 +8,25 @@ CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index 2c0f1e8..d6e51f8 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_EA20=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ea20 > "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
@@ -11,6 +12,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 5dcf4ec..55d5552 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -7,3 +7,4 @@ CONFIG_SYS_PROMPT="\nEB+CPU5282> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index a714458..e204ba2 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -6,3 +6,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 33dcc7b..467a0a1 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -7,10 +7,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ECO5-PK # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig
index 93ad9ba..0066c7d 100644
--- a/configs/ecovec_defconfig
+++ b/configs/ecovec_defconfig
@@ -18,6 +18,9 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig
index c56f90a..91ba24f 100644
--- a/configs/edb9315a_defconfig
+++ b/configs/edb9315a_defconfig
@@ -3,8 +3,12 @@ CONFIG_TARGET_EDB93XX=y
 CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="EDB9315A> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index d2a36e5..fa7c1b5 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -7,4 +7,5 @@ CONFIG_SYS_PROMPT="EDMiniV2> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index 1954717..412c2bc 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -14,6 +14,11 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_DM_PCI=y
diff --git a/configs/espt_defconfig b/configs/espt_defconfig
index 9d491cf..78e319c 100644
--- a/configs/espt_defconfig
+++ b/configs/espt_defconfig
@@ -16,6 +16,7 @@ CONFIG_TARGET_ESPT=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 7739473..579efd3 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -5,7 +5,9 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -13,9 +15,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_RARP=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index d5ff72f..4dd4586 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -6,14 +6,22 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 1c7155f..0995f9b 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -8,17 +8,25 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
 CONFIG_REGMAP=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index b51bff8..298888c 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -7,4 +7,6 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index f2ea59b..babfaf4 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -4,11 +4,15 @@ CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="FO300"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index c5f943d..03cdb17 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -19,11 +19,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index b1038d6..17b1458 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -10,6 +10,7 @@ CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -20,6 +21,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index 336d602..eacd4bb 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -5,9 +5,13 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 62aa0cd..ffa0440 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -2,14 +2,24 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B450V3=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index bfe9de1..b039c24 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -2,14 +2,24 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B650V3=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index bc34fdf..d9c8acd 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -2,14 +2,24 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B850V3=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 4e85e13..6d0dabe 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -5,11 +5,15 @@ CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index 3b72ecb..e7e1287 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -6,11 +6,15 @@ CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index 2bdea8c..ee02469 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -7,6 +7,10 @@ CONFIG_SYS_PROMPT="GoFlexHome> "
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 6e3de27..9f6589a 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_GOSE=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -19,8 +21,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index 3b99683..2bdd0e7 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_GPLUGD=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
@@ -8,7 +9,10 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig
index 8dc1b63..25b9c4e 100644
--- a/configs/grasshopper_defconfig
+++ b/configs/grasshopper_defconfig
@@ -7,6 +7,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_DELAY_STR="d"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 723a4f2..c11aed8 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -18,10 +18,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 453afb0..0baf3a3 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -2,12 +2,17 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_GURUPLUG=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index e0d5acd..9959ef4 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -11,14 +11,24 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Ventana > "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 066f353..7c731b3 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -12,11 +12,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index 6ee9a30..c90eff4 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -4,9 +4,12 @@ CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index c706bfa..129a72b 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -7,16 +7,24 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index b853a4e..56bf948 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -6,9 +6,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 32b5c65..f5660ea 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -2,8 +2,15 @@ CONFIG_ARM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index af6d28f..32d0486 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -8,8 +8,11 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index c060a07..657826a 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -7,7 +7,10 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index e552f5d..266015a 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -8,11 +8,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 871811e..e9ec810 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -15,10 +15,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index b57d5bc..64da00f 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -15,10 +15,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index e1a678a..8b64678 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -14,10 +14,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 22ef1a6..265114f 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -3,12 +3,16 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_IB62X0=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ib62x0 => "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig
index 7237cfe..5ce6abc 100644
--- a/configs/ibf-dsp561_defconfig
+++ b/configs/ibf-dsp561_defconfig
@@ -6,4 +6,5 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_LIB_RAND=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index d9b65b8..d432ff0 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -15,11 +15,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index ccf465d..d32bbc4 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -3,10 +3,16 @@ CONFIG_4xx=y
 CONFIG_TARGET_ICON=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index cd6fbb2..44a474e 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -6,6 +6,9 @@ CONFIG_SYS_PROMPT="iconnect => "
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 08867e7..794b85e 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 6d1dd01..66dd93f 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -4,14 +4,24 @@ CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig
index 05037f7..7535d10 100644
--- a/configs/igep0020_nand_defconfig
+++ b/configs/igep0020_nand_defconfig
@@ -4,14 +4,24 @@ CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
index 40150c2..3ab5c69 100644
--- a/configs/igep0030_defconfig
+++ b/configs/igep0030_defconfig
@@ -4,13 +4,23 @@ CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0030_nand_defconfig b/configs/igep0030_nand_defconfig
index 821e058..cdab71b 100644
--- a/configs/igep0030_nand_defconfig
+++ b/configs/igep0030_nand_defconfig
@@ -4,13 +4,23 @@ CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index 1374be2..d609d89 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -4,14 +4,24 @@ CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index 8e64ef6..b0f244d 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -15,11 +15,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index ca7c260..a953795 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -14,10 +14,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index badf78b..dace876 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -17,10 +17,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index c7fc889..35d9d7c 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -14,10 +14,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 79f2144..483703a 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -11,7 +11,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig
index e465e1b..506a8f8 100644
--- a/configs/inka4x0_defconfig
+++ b/configs/inka4x0_defconfig
@@ -7,3 +7,5 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index b2d1b0b..512d4a8 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -7,11 +7,17 @@ CONFIG_SYS_EXTRA_OPTIONS="INTIB"
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index f387a71..afc5a83 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -7,9 +7,12 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/io_defconfig b/configs/io_defconfig
index f7351a0..1bb9248 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index 5675808..2e66b94 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -7,9 +7,13 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
index b872dea..b944b07 100644
--- a/configs/ip04_defconfig
+++ b/configs/ip04_defconfig
@@ -9,6 +9,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index 3f771ea..cee6988 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -5,8 +5,10 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
index d8ff177..e0b4390 100644
--- a/configs/ipek01_defconfig
+++ b/configs/ipek01_defconfig
@@ -7,4 +7,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 99189b2..79f3cfb 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index d123be0..7b04a0c 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -7,19 +7,29 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 1d8cc82..044a9bf 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -7,7 +7,9 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="K2E EVM # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_SF=y
@@ -16,7 +18,13 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index ee6f335..d0b45ce 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -6,8 +6,11 @@ CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -15,7 +18,13 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 4864d09..3975e80 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -7,7 +7,9 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="K2HK EVM # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_SF=y
@@ -16,7 +18,13 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 7e60dff..844dd57 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -7,7 +7,9 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="K2L EVM # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_SF=y
@@ -16,7 +18,13 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index db79d95..b3e61f8 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -3,10 +3,16 @@ CONFIG_4xx=y
 CONFIG_TARGET_KATMAI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index 13e8412..add96a8 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -4,15 +4,22 @@ CONFIG_TARGET_KC1=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="kc1 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index 9048227..f85cfbb 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -4,9 +4,12 @@ CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig
index 4ac1501..24413a1 100644
--- a/configs/km_kirkwood_128m16_defconfig
+++ b/configs/km_kirkwood_128m16_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig
index a617759..991fe1d 100644
--- a/configs/km_kirkwood_defconfig
+++ b/configs/km_kirkwood_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig
index 6dda308..11c1b71 100644
--- a/configs/km_kirkwood_pci_defconfig
+++ b/configs/km_kirkwood_pci_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
index 82ea876..03e69f3 100644
--- a/configs/kmcoge4_defconfig
+++ b/configs/kmcoge4_defconfig
@@ -11,10 +11,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 85bee4e..bdf98a4 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig
index 6edcab6..3d1b986 100644
--- a/configs/kmcoge5un_defconfig
+++ b/configs/kmcoge5un_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 1f9b461..6256bb4 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig
index b589ae8..7911445 100644
--- a/configs/kmlion1_defconfig
+++ b/configs/kmlion1_defconfig
@@ -11,10 +11,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig
index fb52ab0..f5f36b7 100644
--- a/configs/kmnusa_defconfig
+++ b/configs/kmnusa_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index eed0155..14fb873 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig
index 4d4cc50..ef965ea 100644
--- a/configs/kmsugp1_defconfig
+++ b/configs/kmsugp1_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 8728c35..33dab62 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig
index 262b004..92d2787 100644
--- a/configs/kmsuv31_defconfig
+++ b/configs/kmsuv31_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index b311c48..b450499 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index e049219..a27a9ef 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index e24ce97..2d74209 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 2b681fe..5c45f7b 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_KOELSCH=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -20,8 +22,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
index c07e1e5..30558e7 100644
--- a/configs/kwb_defconfig
+++ b/configs/kwb_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_GO is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
@@ -14,6 +15,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -24,6 +26,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 3f26874..50fbe65 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -6,14 +6,22 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index 6a16d8c..e3902ce 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -2,8 +2,10 @@ CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_KZM9G=y
 CONFIG_SYS_PROMPT="KZM-A9-GT# "
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index e3eeabf..c262117 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_LAGER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -19,8 +21,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 89b3f9d..d080f05 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -6,12 +6,17 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
 CONFIG_AUTOBOOT_STOP_STR="l"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 5976cb2..6feb581 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -6,13 +6,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 5ba935b..563af48 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -6,13 +6,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index ac042b5..0786f20 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -5,13 +5,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 5610e06..243fcdd 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -5,13 +5,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 6947d3f..3cecdfe 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -5,13 +5,19 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index ab4fc54..75b763e 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -6,13 +6,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 924d323..c47fbce 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -6,15 +6,21 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 667bedc..61ab251 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -4,13 +4,19 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index a50fe68..bb88743 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -5,15 +5,21 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 2ee3b91..a5cbb22 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -5,13 +5,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index a1bfbc1..465054f 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -5,13 +5,19 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 34a8569..e96e31a 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -6,13 +6,19 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 571550b..987638c 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -6,15 +6,21 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 2f76715..df4d428 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -5,12 +5,18 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 9c4e2da..583325d 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -7,14 +7,20 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index da0577b..346faf4 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -7,13 +7,20 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index e65e07f..2c6ac35 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -8,13 +8,20 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 441eb2c..cc8d8fa 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -8,13 +8,20 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 4b8c4f4..7d0646c 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -6,13 +6,20 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 8c72836..8ea1416 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -7,14 +7,21 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 86f6ac2..7e5949d 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -8,13 +8,20 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 84b75f5..609fd63 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -8,14 +8,21 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 3c6bcfe..cacee2f 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -7,11 +7,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index b74adfb..49d0740 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -7,11 +7,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 8076ffa..d240cde 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -8,11 +8,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 4133fc3..f853685 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -8,11 +8,16 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index 1e56c08..f9b4eac 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -10,6 +10,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_I2C=y
@@ -18,7 +19,9 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index c3429a0..728fa25 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -10,16 +10,21 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index f3f2467..216559c 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -10,12 +10,18 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 05e33d1..854630a 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -10,12 +10,18 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index ac30219..4f385a1 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -7,11 +7,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 13d09d0..41d30a6 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -10,12 +10,18 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index b2e3464..2b775cd 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -10,12 +10,18 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index f27bf6b..0f184c0 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -7,11 +7,17 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index da8f1a1..4af7e5d 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
@@ -10,7 +11,11 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 3068617..5bcd367 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
@@ -10,7 +11,11 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index ec443f9..e0fa805 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -3,9 +3,13 @@ CONFIG_4xx=y
 CONFIG_TARGET_LUAN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index 9999f45..64794a1 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -4,11 +4,14 @@ CONFIG_TARGET_LWMON5=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index 54829a9..c598c72 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -4,14 +4,23 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 1e9450d..62496c3 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -5,9 +5,17 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index adda7fb..81a6700 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -5,15 +5,25 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index a153e4d..8f7baea 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -3,9 +3,12 @@ CONFIG_4xx=y
 CONFIG_TARGET_MAKALU=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 02bad1e..6e7b326 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -3,14 +3,23 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 3319d3f..7a5eeba 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -12,6 +12,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index 67bc80c..ab814cc 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -8,13 +8,18 @@ CONFIG_SYS_PROMPT="mcx # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index c2e45de..9597482 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -3,8 +3,11 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MECP5123=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index e5fb0cc..02eb704 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -8,16 +8,24 @@ CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 2c2df2e..3d295f5 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index a0bf894..aac7cc5 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig
index 5dd0856..d404c8b 100644
--- a/configs/mgcoge3ne_defconfig
+++ b/configs/mgcoge3ne_defconfig
@@ -8,7 +8,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig
index f1735c0..484abbe 100644
--- a/configs/mgcoge3un_defconfig
+++ b/configs/mgcoge3un_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig
index 86de799..2cc8f44 100644
--- a/configs/mgcoge_defconfig
+++ b/configs/mgcoge_defconfig
@@ -8,7 +8,10 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 39c2ad2..8c7e4b7 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -9,10 +9,12 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index a46b37a..9930d56 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -26,6 +27,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 74486a1..9a44466 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -10,11 +10,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index e1dc927..5e545d0 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -8,11 +8,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 35f0bfa..a76a699 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -7,11 +7,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index 90addf4..bdfb597 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -5,10 +5,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig
index 6e568d4..eaaa5ed 100644
--- a/configs/motionpro_defconfig
+++ b/configs/motionpro_defconfig
@@ -6,8 +6,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index 73bf67f..34935ad 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -3,9 +3,13 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 7df336c..664d949 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 29d7d61..1f28c08 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -7,6 +7,7 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mpr2_defconfig b/configs/mpr2_defconfig
index 6a832c7..a8dbfc5 100644
--- a/configs/mpr2_defconfig
+++ b/configs/mpr2_defconfig
@@ -18,5 +18,6 @@ CONFIG_TARGET_MPR2=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig
index 55d480a..2ef3105 100644
--- a/configs/ms7720se_defconfig
+++ b/configs/ms7720se_defconfig
@@ -18,5 +18,7 @@ CONFIG_TARGET_MS7720SE=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index a4933f4..dda0daa 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -7,12 +7,17 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mt_ventoux => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
index 6dd615b..eabfe1e 100644
--- a/configs/munices_defconfig
+++ b/configs/munices_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_MUNICES=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 59daea6..e201abb 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -4,8 +4,12 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index cc7157e..b1bd634 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -2,11 +2,16 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX23EVK=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index 66bff20..1c1afd8 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -2,10 +2,16 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX25PDK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index 12a4011..8738f59 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -3,14 +3,22 @@ CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index d425a30..de8a297 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -4,14 +4,22 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index e591a37..83ff3a3 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -3,14 +3,22 @@ CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index 2aa8f1b..906d3da 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -3,14 +3,22 @@ CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index bcb85a1..e1bb561 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -1,8 +1,10 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX31PDK=y
 CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 486e7d9..e6cc065 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -1,10 +1,16 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX35PDK=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index b9b8d24..0b3b232 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -2,10 +2,14 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX51EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index b4d821e..500b39c 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -2,8 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 9dec972..45f5e45 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -3,8 +3,11 @@ CONFIG_TARGET_MX53EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 2e34ccb..da9aa4f 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -2,9 +2,15 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX53LOCO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 3d85014..c24aec6 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -3,8 +3,11 @@ CONFIG_TARGET_MX53SMD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 40ad38f..9d06940 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -4,12 +4,21 @@ CONFIG_TARGET_MX6CUBOXI=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index a7554b7..eb30bf6 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -3,11 +3,20 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index af2c985..dc52b9b 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -3,11 +3,20 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index 12157ba..de925d9 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -3,14 +3,25 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 01c8122..2fcc088 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -3,14 +3,25 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index ff4af17..391da69 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -3,11 +3,20 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index 5e02437..af3b9b0 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -3,11 +3,20 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index ee56d4e..6212540 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -3,13 +3,24 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 0e24307..250411d 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -3,14 +3,25 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index a19556d..66575b8 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 1b69092..7456cf3 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -3,14 +3,25 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 7be6374..8d5e289 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -4,14 +4,23 @@ CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 47cf613..9f29b15 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -3,15 +3,24 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index b5de314..a43de4a 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -3,15 +3,24 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index b3f5c93..2efd833 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -4,13 +4,22 @@ CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 17ad20e..8a4c7d5 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -3,16 +3,25 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 954201b..55093c9 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -3,15 +3,24 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 8d3cae3..f01fd3b 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -4,14 +4,23 @@ CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index a241e88..dee1ef0 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -4,12 +4,20 @@ CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 88ef332..644fd20 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -4,12 +4,20 @@ CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 9e43aa7..3bde39f 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -6,17 +6,27 @@ CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index 0d5a683..f904e12 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -8,6 +8,10 @@ CONFIG_SYS_PROMPT="nas220> "
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index cdfb432..e306d68 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -6,8 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index d35458f..f930e47 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -11,7 +11,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 9090518..7917336 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -11,7 +11,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 6cb311e..55978f2 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -11,7 +11,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index 90af1c7..67b142d 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -10,7 +10,10 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 1de1308..8199bbd 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -11,7 +11,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index af8c8bb..cc86e3f 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 1896e44..05dcea2 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 8de9ea0..2de93a4 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index e08020d..a5f57f6 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index a67e01c..fdd444e 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index f5f5519..daace52 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -3,16 +3,26 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_USB=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 60106b3..6eb01ea 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -8,10 +8,14 @@ CONFIG_AUTOBOOT_KEYED=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SAVEENV is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 90db4ff..69e5ea9 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -5,14 +5,24 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index ddd9004..51da5ad 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -3,12 +3,16 @@ CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NSA310S=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nsa310s => "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 40032df..262042d 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -9,23 +9,33 @@ CONFIG_FIT_BEST_MATCH=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 942e8be..8995cc2 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -8,15 +8,26 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ODROID-XU3 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_ADC=y
 CONFIG_ADC_EXYNOS=y
 CONFIG_DM_I2C_COMPAT=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index a32fb56..ff3b339 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -8,18 +8,29 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Odroid # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_DM_PMIC=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index e2ffc7b..78f71d6 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -4,14 +4,24 @@ CONFIG_TARGET_OMAP3_BEAGLE=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index d02b47a..1a9f207 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -6,11 +6,15 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
index 1af2b45..3385d67 100644
--- a/configs/omap3_evm_quick_mmc_defconfig
+++ b/configs/omap3_evm_quick_mmc_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
@@ -24,4 +25,5 @@ CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index e609988..5f0dece 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -7,11 +7,15 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 6062e5f..3226247 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -6,15 +6,25 @@ CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP Logic # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index a1df368..6189296 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -4,9 +4,12 @@ CONFIG_TARGET_OMAP3_OVERO=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Overo # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -15,6 +18,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
index 67d4dd7..ec50417 100644
--- a/configs/omap3_pandora_defconfig
+++ b/configs/omap3_pandora_defconfig
@@ -3,9 +3,12 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_PANDORA=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Pandora # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
@@ -14,6 +17,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig
index afb2286..db2aafc 100644
--- a/configs/omap3_zoom1_defconfig
+++ b/configs/omap3_zoom1_defconfig
@@ -2,15 +2,24 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_ZOOM1=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 06450c3..406f0ac 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -3,8 +3,11 @@ CONFIG_OMAP44XX=y
 CONFIG_TARGET_OMAP4_PANDA=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -12,6 +15,12 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 6ca4baf..c5d6d61 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -3,8 +3,11 @@ CONFIG_OMAP44XX=y
 CONFIG_TARGET_OMAP4_SDP4430=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
@@ -12,6 +15,12 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index f242d55..f67676f 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -3,15 +3,25 @@ CONFIG_OMAP54XX=y
 CONFIG_TARGET_OMAP5_UEVM=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 57bef31..4d5e8a0 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -5,10 +5,15 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 79f6eda..7001921 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 12b9046..fd53c78 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index b640560..52b9a5b 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig
index d8a3b4c..a476ba7 100644
--- a/configs/openrisc-generic_defconfig
+++ b/configs/openrisc-generic_defconfig
@@ -4,5 +4,6 @@ CONFIG_TARGET_OPENRISC_GENERIC=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 7e0be1e..f33ac36 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -11,11 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 6a36955..de6e9c8 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -10,9 +10,16 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 98bbbc2..7bade8f 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -9,11 +9,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 07ed4b5..2df5859 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -13,11 +13,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 666e206..b1740dc 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -5,13 +5,24 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ORIGEN # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index b839c76..c604340 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -3,14 +3,23 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_OT1200=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 0b0330b..b5791ad 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -4,14 +4,23 @@ CONFIG_TARGET_OT1200=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index ae3105a..d27fd6d 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -9,16 +9,25 @@ CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index 6ee99d1..4e365b5 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -9,16 +9,25 @@ CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index b2a76a5..2b3c5c6 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -9,16 +9,25 @@ CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index f807990..0fe43b1 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -7,16 +7,24 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index d2f9258..6aa2c43 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -12,5 +12,6 @@ CONFIG_SYS_PROMPT="Pb1x00 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
index cc8f2a8..dbfaea1 100644
--- a/configs/pcm030_LOWBOOT_defconfig
+++ b/configs/pcm030_LOWBOOT_defconfig
@@ -6,4 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index 25482e2..6d25884 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -6,4 +6,5 @@ CONFIG_SYS_PROMPT="uboot> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 909a157..7f29119 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -3,8 +3,11 @@ CONFIG_TARGET_PCM051=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="REV1"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -12,7 +15,13 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index d9f5c48..eff099c 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -3,8 +3,11 @@ CONFIG_TARGET_PCM051=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="REV3"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -12,7 +15,13 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 7226f56..db8ebdd 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -5,12 +5,16 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="pcm052"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index ad9d9c7..c352195 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -5,8 +5,10 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index b718650..c8c74c0 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -8,7 +8,9 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Peach-Pi # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -16,12 +18,19 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_MUX=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 68bacc0..c5fbf8c 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -8,7 +8,9 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Peach-Pit # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -16,12 +18,19 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_MUX=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index 4698b2e..3eba3ce 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -2,15 +2,24 @@ CONFIG_ARM=y
 CONFIG_TARGET_PENGWYN=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index bee3477..4a46f24 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -3,13 +3,22 @@ CONFIG_TARGET_PEPPER=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="pepper# "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 750fefd..9547d48 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -14,13 +14,20 @@ CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MEMINFO=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_RARP=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index e4f8265..723466f 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -6,13 +6,16 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index a2e0b26..0494a9f 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -9,6 +9,12 @@ CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 703f43a..9676a99 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -5,13 +5,22 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="picon > "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 1064baf..f3de3fc 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -5,13 +5,22 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="titanium > "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 9c698f8..ed519a0 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -8,16 +8,24 @@ CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index a73d6ed..cb10fa3 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -12,3 +12,4 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index c97ac16..37629ba 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -12,3 +12,4 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 9dcc20c..0949e1f 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -11,3 +11,4 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 11cf100..2b3b4c8 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -7,6 +7,9 @@ CONFIG_SYS_PROMPT="PogoE02> "
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 7a7651e..cedbf53 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -18,10 +18,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 2edfeaf..2f819f5 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_PORTER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -20,8 +22,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig
index c2ad41b..87fd221 100644
--- a/configs/portl2_defconfig
+++ b/configs/portl2_defconfig
@@ -7,10 +7,13 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 605d589..aad9619 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -15,10 +15,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
index f087b3f..e7cf5e8 100644
--- a/configs/pr1_defconfig
+++ b/configs/pr1_defconfig
@@ -9,9 +9,11 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index df371f7..8655665 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -8,15 +8,22 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 48a37cd..97232ce 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -17,10 +17,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index ded6ffc..79dcc33 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -18,10 +18,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index a4eb5c5..ff29e81 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -18,10 +18,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index dc820ea..d87700c 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -18,10 +18,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index e474494..f7f3fb0 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -6,10 +6,13 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 2e891e2..53b1ff6 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -21,6 +21,11 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
index 3d9ef12..0826a0c 100644
--- a/configs/qemu_mips64_defconfig
+++ b/configs/qemu_mips64_defconfig
@@ -8,5 +8,7 @@ CONFIG_SYS_PROMPT="qemu-mips64 # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_RARP=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
index 9eb93ef..f70ebc3 100644
--- a/configs/qemu_mips64el_defconfig
+++ b/configs/qemu_mips64el_defconfig
@@ -9,5 +9,7 @@ CONFIG_SYS_PROMPT="qemu-mips64el # "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_RARP=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
index cc440f8..bb09796 100644
--- a/configs/qemu_mips_defconfig
+++ b/configs/qemu_mips_defconfig
@@ -6,5 +6,7 @@ CONFIG_SYS_PROMPT="qemu-mips # "
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
index 3fa84ab..19e6c7d 100644
--- a/configs/qemu_mipsel_defconfig
+++ b/configs/qemu_mipsel_defconfig
@@ -7,5 +7,7 @@ CONFIG_SYS_PROMPT="qemu-mipsel # "
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig
index 91926d4..5214923 100644
--- a/configs/r0p7734_defconfig
+++ b/configs/r0p7734_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index f4df61a..bd553be 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -2,4 +2,6 @@ CONFIG_SH=y
 CONFIG_TARGET_R2DPLUS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index a067693..4e1c393 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -7,11 +7,18 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig
index 7d8cb38..ad6f2f0 100644
--- a/configs/r7780mp_defconfig
+++ b/configs/r7780mp_defconfig
@@ -18,4 +18,5 @@ CONFIG_TARGET_R7780MP=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index 6684bd9..27998f3 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -4,9 +4,14 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 0679959..6ebdb38 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -4,9 +4,14 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 73b3b36..ec89f05 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -7,15 +7,21 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index afdb0ed..89c129f 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -3,9 +3,13 @@ CONFIG_4xx=y
 CONFIG_TARGET_REDWOOD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index cbd97d7..60a06ab 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -3,14 +3,23 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 4bfd7c8..fd32fb5 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -8,17 +8,25 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
 CONFIG_REGMAP=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index b8f99aa..a26f767 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -4,12 +4,19 @@ CONFIG_TARGET_RPI_2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index bf0ca97..922e01b 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -4,12 +4,19 @@ CONFIG_TARGET_RPI_3_32B=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index c823d0e..bff92df 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -6,10 +6,16 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 9ddd6bc..fc512b9 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -4,12 +4,19 @@ CONFIG_TARGET_RPI=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_PHYS_TO_BUS=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/rsk7203_defconfig b/configs/rsk7203_defconfig
index 40adf42..b63ad4e 100644
--- a/configs/rsk7203_defconfig
+++ b/configs/rsk7203_defconfig
@@ -17,5 +17,6 @@ CONFIG_TARGET_RSK7203=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index e2993cb..406eaf3 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -8,15 +8,22 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 2e2cc2a..c35287d 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -7,11 +7,18 @@ CONFIG_SYS_PROMPT="Goni # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index f28b928..638b728 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -4,15 +4,26 @@ CONFIG_TARGET_S5PC210_UNIVERSAL=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Universal # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 05efce5..7fd37d6 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 1b6649c..de4e6bc 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 7de3247..189a3e9 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -4,12 +4,18 @@ CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 8c61615..16e3f22 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -4,12 +4,18 @@ CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 9795c0c..8d3c3cf 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -4,13 +4,17 @@ CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index f77145a..8e15286 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -4,13 +4,17 @@ CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 08773f5..ffbafae 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -4,13 +4,17 @@ CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 3d020b5..1ea5cda 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index f93bbdb..5384917 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 7b231d9..b709cf6 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 356aebc..45128e9 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index a599251..9c1c232 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index a328c8c..59eb4dd 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -4,15 +4,18 @@ CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_USB=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cc04361..afdf4a3 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -18,8 +18,11 @@ CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MX_CYCLIC=y
@@ -35,6 +38,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
 CONFIG_CMD_RARP=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CDP=y
 CONFIG_CMD_SNTP=y
@@ -48,6 +52,11 @@ CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y
 CONFIG_NETCONSOLE=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 73c2762..9dd60b7 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -5,10 +5,14 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index b55d644..60bb817 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 3de150d..6c0fd99 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index f311a2d..e22c70a 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index 649e36e..6d5b3f6 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index f0e3982..8ecb126 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index ce6d600..bbea0cb 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index 5e37927..f146b2d 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index fa6e61e..3dea198 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 097748a..4b73506 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -4,8 +4,13 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 5c72a09..3f8648d 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -7,9 +7,11 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -17,7 +19,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 0da341f..2c57714 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -7,9 +7,18 @@ CONFIG_SECOMX6_2GB=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index ecda85b..66d6a1a 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -4,10 +4,15 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index 1c3a0b9..5c548ff 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -4,10 +4,15 @@ CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index 5a77fe0..07594d1 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -11,14 +11,17 @@ CONFIG_TARGET_SH7752EVB=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index 0dd488f..5e7a9c9 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -10,14 +10,17 @@ CONFIG_TARGET_SH7753EVB=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index b75fd84..fafba4c 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -11,14 +11,17 @@ CONFIG_TARGET_SH7757LCR=y
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ECHO is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig
index 983f2a2..cc20fbd 100644
--- a/configs/sh7763rdp_defconfig
+++ b/configs/sh7763rdp_defconfig
@@ -16,6 +16,7 @@ CONFIG_TARGET_SH7763RDP=y
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig
index ab2cff7..cc31e1c 100644
--- a/configs/sh7785lcr_32bit_defconfig
+++ b/configs/sh7785lcr_32bit_defconfig
@@ -19,4 +19,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig
index 059f5f7..d7724b3 100644
--- a/configs/sh7785lcr_defconfig
+++ b/configs/sh7785lcr_defconfig
@@ -18,4 +18,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index a51abc7..71ce49c 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -2,12 +2,18 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_SHEEVAPLUG=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index acad1d6..0beef09 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_SILK=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -20,8 +22,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index e526653..2ec6e48 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -13,9 +13,11 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
index 39375de..702b36c 100644
--- a/configs/smdk2410_defconfig
+++ b/configs/smdk2410_defconfig
@@ -6,3 +6,6 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index e46fcae..5d88391 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -8,7 +8,9 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK5250 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -16,11 +18,18 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 39b329a..40de7c1 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -8,7 +8,9 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK5420 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -16,8 +18,15 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 01a3eb0..a989e24 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -7,3 +7,5 @@ CONFIG_SYS_PROMPT="SMDKC100 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 19662c8..b8638e2 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -5,12 +5,21 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDKV310 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index f45243d..2f8dd50 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -17,4 +17,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 5458b48..f725693 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -16,4 +16,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 444a78a..1b313c4 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -4,15 +4,22 @@ CONFIG_TARGET_SNIPER=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="sniper # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 3a53d26..97133df 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -8,7 +8,9 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="snow # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -16,13 +18,20 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_I2C_MUX=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index a64a1e2..9a7c091 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -10,15 +10,27 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index caa3999..ac81854 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -10,15 +10,27 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 9a8dbaa..405d9d4 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -10,15 +10,27 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 5e3d09c..3615490 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -10,15 +10,27 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 823c512..bdc8e6b 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -10,15 +10,27 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index ae6c23e..b64ea15 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -10,15 +10,27 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index d29027c..c4b215a 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -10,16 +10,26 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index fe491b5..aa4bbb6 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -10,7 +10,9 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index 7e40037..af2f544 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear300"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 51e9358..6c53e1f 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear300,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index 5ce8720..6827701 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index 1fa6223..477a226 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index 5f8feee..0991f8e 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear310"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index a070f36..ef30a67 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear310,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 5802684..6cfe220 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index b39f1e0..c0d8edf 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index 8188314..e9d14ce 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index 581dfb1..2e46e64 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 558bdb8..8dba79a 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear320"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index d9fcd6a..7f33c78 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear320,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index 3aff58c..f7d3725 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index 75855bc..9e41253 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index f0f46c2..e61c74e 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index a4aab03..7410093 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index fac6a3c..f0e041f 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -7,6 +7,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index 8f421b7..cc4067d 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear600,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 8b8f28d..df21355 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index f0ce802..48140aa 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand"
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 2af8184..b720e04 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -8,7 +8,9 @@ CONFIG_FIT=y
 CONFIG_FIT_BEST_MATCH=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="spring # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -16,13 +18,20 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_SOUND=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_I2C_COMPAT=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_I2C_MUX=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index d4d1d89..a8f59ca 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -4,12 +4,14 @@ CONFIG_TARGET_STOUT=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
@@ -19,8 +21,13 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
 CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 316ceaf..985aab8 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -10,8 +10,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 77f4fc1..2766104 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -10,8 +10,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 3cae955..3677da7 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -12,10 +12,17 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index 3ab8901..ac6a9e2 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index c462fa2..9fdb2b3 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -3,9 +3,12 @@ CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index 0deda13..c5562c9 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_T3CORP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index 9b096cc..6d0877d 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -7,11 +7,15 @@ CONFIG_SYS_PROMPT="TAO-3530 # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 00bd63f..20f33a8 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -5,12 +5,14 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 1841e93..dc69b39 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -4,15 +4,25 @@ CONFIG_TARGET_TBS2910=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
index 91e0f75..cc46a52 100644
--- a/configs/tcm-bf518_defconfig
+++ b/configs/tcm-bf518_defconfig
@@ -5,8 +5,10 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
index b39e260..576dc6a 100644
--- a/configs/tcm-bf537_defconfig
+++ b/configs/tcm-bf537_defconfig
@@ -1,12 +1,17 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF537=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 8ed7809..b710229 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -8,9 +8,11 @@ CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -20,7 +22,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 240f11e..2055101 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -8,16 +8,24 @@ CONFIG_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 1eb4b10..8358757 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
@@ -18,8 +19,14 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index e9e6290..157985f 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
@@ -15,7 +16,12 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 0437874..f9391f2 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -7,15 +7,21 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index 2208e9a..e41e2a4 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -4,9 +4,14 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 03365fc..4eb7923 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -5,6 +5,9 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot/ti816x# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index 9e38f5d..4d16ef6 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -4,13 +4,22 @@ CONFIG_TARGET_TITANIUM=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Titanium > "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index b5492a9..22b16a1 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -5,15 +5,24 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 69cf92e..715db21 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -6,15 +6,24 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 40a6f42..824cd2b 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -6,15 +6,24 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index b141f16..058bb89 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -7,15 +7,24 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 92cc5c9..e348960 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -11,11 +11,20 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
 CONFIG_AUTOBOOT_ENCRYPTION=y
 CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_PCA9551_LED=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 693d845..c2ed8c8 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -7,15 +7,26 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Trats2 # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 66a11c9..46bfc4e 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -6,15 +6,26 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Trats # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 21d0bbf..25c499a 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -7,10 +7,13 @@ CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 1dfff4d..200fbe1 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -7,10 +7,13 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 8e8618e..67857a5 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -7,9 +7,11 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -19,7 +21,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_RTL8169=y
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 3a7fa63..7d8953d 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -1,9 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TS4800=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
index 5abd7f0..4b4cfd2 100644
--- a/configs/tseries_mmc_defconfig
+++ b/configs/tseries_mmc_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -12,6 +13,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -22,6 +24,10 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
index 19d9004..1485aaa 100644
--- a/configs/tseries_nand_defconfig
+++ b/configs/tseries_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -23,6 +24,10 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
index ae93795..a68cfac 100644
--- a/configs/tseries_spi_defconfig
+++ b/configs/tseries_spi_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
@@ -12,6 +13,7 @@ CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -24,6 +26,10 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 97fb231..475cf47 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 3a03ecb..e2d86d9 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -8,8 +8,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 83cf623..ffbc025 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -7,12 +7,17 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="twister => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index af48888..81c32cd 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -4,10 +4,19 @@ CONFIG_TARGET_UDOO=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index a6862db..22615a6 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -6,8 +6,10 @@ CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -17,6 +19,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index 7d50f1c..18f4caf 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -5,8 +5,10 @@ CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -16,6 +18,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index 747aeb8..cf6d3e4 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -6,8 +6,10 @@ CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -17,6 +19,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index f779ded..0965019 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -5,8 +5,10 @@ CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -16,6 +18,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
 CONFIG_MMC_UNIPHIER=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 215e87b..17e208b 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -2,11 +2,18 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX5=y
 CONFIG_TARGET_USBARMORY=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
index 3dadfcc..4dd2612 100644
--- a/configs/v38b_defconfig
+++ b/configs/v38b_defconfig
@@ -5,4 +5,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index b889976..ed27d85 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -8,5 +8,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index 597f764..82708f0 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -11,5 +11,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 68c4af1..29d16e3 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -8,5 +8,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index 1d73069..31b89e3 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -11,5 +11,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 4243848..4ae3550 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 5749d1c..17a6000 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -7,19 +7,29 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index cbb17c9..97b13a1 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -7,16 +7,24 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_PWM_TEGRA=y
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 644a207..989f068 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -17,7 +17,10 @@ CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 7bae9c9..c70851f 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -17,7 +17,10 @@ CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index 2006176..b0a2f67 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -17,7 +17,10 @@ CONFIG_CMD_ARMFLASH=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 389c384..2f141dd 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -3,17 +3,24 @@ CONFIG_TARGET_VEXPRESS_CA15_TC2=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index 4118b58..c495ee5 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -3,17 +3,24 @@ CONFIG_TARGET_VEXPRESS_CA5X2=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 433dc34..fcd6e26 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -3,17 +3,24 @@ CONFIG_TARGET_VEXPRESS_CA9X4=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EDITENV is not set
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_ITEST is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index 4504af2..c014294 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -5,13 +5,17 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index 26b045a..d50ad90 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -5,13 +5,17 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_VYBRID_GPIO=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 57d0169..e79cc4d 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -4,15 +4,19 @@ CONFIG_TARGET_VINCO=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="vinco => "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 323b416..887afdf 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index c462fa2..9fdb2b3 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -3,9 +3,12 @@ CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index e03a1d9..195c99b 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -4,13 +4,22 @@ CONFIG_TARGET_WANDBOARD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 29c5e91..e1b0c07 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -6,10 +6,19 @@ CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index aa15c81..3f9bb25 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -3,14 +3,24 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_WARP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index a6d1438..ca753a4 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -7,9 +7,11 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -17,7 +19,13 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index ddbd697..b4660cd 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -2,9 +2,14 @@ CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index d801c3b..bb1ef0a 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -4,9 +4,14 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 12df37b..5663b2f 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -13,6 +13,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_DM=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 8c163fb..9341087 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -4,7 +4,9 @@ CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXT2=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 05d2f35..1a07b9d 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -12,7 +12,11 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 5f25633..59e1014 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -4,10 +4,14 @@ CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index 9d4b137..6c021d7 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -8,10 +8,12 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x041000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="xlx-ppc405:/# "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
 CONFIG_XILINX_UARTLITE=y
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index 4f814a6..ab0ea5a 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -7,10 +7,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="board:/# "
+CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_OF_EMBED=y
 CONFIG_NETCONSOLE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 48d95c1..b185593 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -18,8 +18,10 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_ENV_EXISTS is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
@@ -27,9 +29,15 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_I2C_CADENCE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 598da20..cc08b03 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -12,14 +12,22 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_I2C_CADENCE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 81170dc..14d24a0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -14,12 +14,19 @@ CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_I2C_CADENCE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index a9b68de..e1e11b7 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -11,12 +11,19 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 05c5cdd..6f1cff8 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -11,14 +11,22 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index f6767f3..a8982a0 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -11,14 +11,22 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index 13e0069..4c0e58e 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -4,9 +4,11 @@ CONFIG_TARGET_XPEDITE1000=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index 81eb5f8..b0e92e0 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -6,9 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index 77386f5..4a328cd 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -6,9 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index a4dcd78..e0fe947 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -6,9 +6,11 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index 113d16d..e16c8c8 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -6,10 +6,12 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index fc13e9d..59a3138 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -3,10 +3,19 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_XPRESS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 9c2bcc5..ad0cddb 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -4,10 +4,19 @@ CONFIG_TARGET_XPRESS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 2f1cea2..00992e0 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -4,9 +4,13 @@ CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index fdede36..3a803f6 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -4,10 +4,16 @@ CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index edf1b45..e219fd2 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -3,9 +3,13 @@ CONFIG_4xx=y
 CONFIG_TARGET_YUCCA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig
index 22bdbd3..f350387 100644
--- a/configs/zipitz2_defconfig
+++ b/configs/zipitz2_defconfig
@@ -3,10 +3,14 @@ CONFIG_TARGET_ZIPITZ2=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index 0578850..9368610 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -10,3 +10,5 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 748c160..7c66247 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -10,13 +10,22 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index cd41af0..b46ab44 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -7,12 +7,21 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 8471e10..052679a 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -9,14 +9,23 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 99ddf3c..3539f05 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -10,14 +10,23 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 50724b5..6a4726c 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -11,12 +11,20 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index a80dd11..46dd6be 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -15,7 +15,9 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index dbb0d13..12f0e2c 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -13,7 +13,9 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index be7c425..8c7efe5 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -15,7 +15,9 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index f3c7e1c..7976e07 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -10,13 +10,22 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 9063010..cd222c5 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -10,14 +10,23 @@ CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index 4054900..ed502a1 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -13,12 +13,9 @@
  * Alphabetical list of all possible commands.
  */
 
-#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
 #define CONFIG_CMD_BEDBUG	/* Include BedBug Debugger	*/
 #define CONFIG_CMD_BMP		/* BMP support			*/
-#define CONFIG_CMD_BOOTZ	/* boot zImage			*/
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
-#define CONFIG_CMD_CACHE	/* icache, dcache		*/
 #define CONFIG_CMD_CLK		/* Clock support		*/
 #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
 #define CONFIG_CMD_DIAG		/* Diagnostics			*/
@@ -26,8 +23,6 @@
 #define CONFIG_CMD_DOC		/* Disk-On-Chip Support		*/
 #define CONFIG_CMD_DTT		/* Digital Therm and Thermostat */
 #define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_FDC		/* Floppy Disk Support		*/
 #define CONFIG_CMD_FUSE		/* Device fuse support		*/
 #define CONFIG_CMD_GETTIME	/* Get time since boot         */
@@ -39,8 +34,6 @@
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 #define CONFIG_CMD_KGDB		/* kgdb				*/
 #define CONFIG_CMD_MFSL		/* FSL support for Microblaze	*/
-#define CONFIG_CMD_MII		/* MII support			*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_MTDPARTS	/* mtd parts support		*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_ONENAND	/* OneNAND support		*/
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index a0e490b..766a212 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -43,14 +43,7 @@
 
 #ifdef CONFIG_ARM64
 #define CONFIG_CMD_BOOTI
-#else
-#define CONFIG_CMD_BOOTZ
 #endif
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PXE
 
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index e3c222e..2666191 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -96,7 +96,6 @@
 #ifndef CONFIG_CMDLINE
 #undef CONFIG_CMDLINE_EDITING
 #undef CONFIG_SYS_LONGHELP
-#undef CONFIG_CMD_ASKENV
 #undef CONFIG_MENU
 #endif
 
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 2076ef0..7eb9e98 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -33,7 +33,6 @@
  * NET options
  */
 #define CONFIG_SYS_RX_ETH_BUFFER	0
-#define CONFIG_CMD_MII
 #define CONFIG_PHY_GIGE
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #define CONFIG_PHY_MARVELL
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 802ac75..6489de3 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -36,7 +36,6 @@
  * NET options
  */
 #define CONFIG_SYS_RX_ETH_BUFFER	0
-#define CONFIG_CMD_MII
 #define CONFIG_PHY_GIGE
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #define CONFIG_PHY_MARVELL
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index a9c6272..94c8253 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -736,9 +736,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -763,7 +761,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #endif
 #endif
 
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 07070cd..b092933 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -314,10 +314,7 @@ extern unsigned long get_sdram_size(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 1eb2ff6..3a73379 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -498,7 +498,6 @@ combinations. this should be removed later
 
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
@@ -555,12 +554,9 @@ combinations. this should be removed later
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1600417..4d14c8b 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -471,7 +471,6 @@
  */
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /* Hash command with SHA acceleration supported in hardware */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index de6ff7f..b66b3ff 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -68,9 +68,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index cc7aeb8..2b2e4e7 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -22,8 +22,6 @@
 #define CONFIG_WATCHDOG_TIMEOUT		5000
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #define CONFIG_MCFFEC
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 133f15c..85b1c15 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -37,7 +37,6 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index b5d49b5..bacd8e0 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -35,8 +35,6 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index e29cb24..735c4da 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -39,7 +39,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 
 #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
 
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index ada212c..7c06fce 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -39,9 +39,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 
 #ifdef CONFIG_CMD_IDE
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index e5aa1c7..d14f979 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -48,9 +48,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 
 /* ATA */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index fcb0587..0753dc3 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -56,8 +56,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_MCFFEC
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 5f3ec3f..1709ccc 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -55,8 +55,6 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Available command configuration */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 3442723..8131ea0 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -47,8 +47,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index c90ea27..81e28f0 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -27,9 +27,7 @@
 #define CONFIG_WATCHDOG_TIMEOUT		5000
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #define CONFIG_SYS_UNIFY_CACHE
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 0e0e109..661063c 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -27,9 +27,7 @@
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_NANDFLASH_SIZE
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 39733f9..f0cf715 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -27,9 +27,7 @@
 #define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_NANDFLASH_SIZE
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index 933b8cd..e10c3e1 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -38,11 +38,9 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_DATE
 #undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_UBI
-#define CONFIG_CMD_MII
 #undef CONFIG_CMD_NAND
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 3b01bd6..00bdbd1 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -39,10 +39,8 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #undef CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /* Network configuration */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 8a7cea5..f32dd36 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -39,13 +39,9 @@
 #define CONFIG_BOOTP_HOSTNAME
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #undef CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index ff8420f..5fa9683 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -29,9 +29,7 @@
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 9c83d17..9a23e22 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -29,9 +29,7 @@
 #define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 7c4509f..75a26ed 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -47,14 +47,11 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SAVES
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 422f223..e3e3b44 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -31,9 +31,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -430,7 +428,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 4b7a773..fda894e 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -475,7 +475,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index d29519d..41b40cb 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -425,7 +425,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -458,7 +457,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_PCI
 
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index f815b20..5c40e5b 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -327,7 +327,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ASKENV
 
 #if defined(CONFIG_PCI)
 	#define CONFIG_CMD_PCI
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 38bb613..4a1cebb 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -409,7 +409,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index b3a3bc5..3518b3f 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -476,7 +476,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 9b3c6ea..8161903 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -487,7 +487,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SDRAM
@@ -495,7 +494,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
 				|| defined(CONFIG_USB_STORAGE)
 	#define CONFIG_DOS_PARTITION
-	#define CONFIG_CMD_FAT
 	#define CONFIG_SUPPORT_VFAT
 #endif
 
@@ -508,7 +506,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #endif
 
 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
-	#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 7f26ecb..28ed9c0 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -445,7 +445,6 @@ extern int board_pci_host_broken(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -478,7 +477,6 @@ extern int board_pci_host_broken(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 
 #if defined(CONFIG_PCI)
@@ -496,10 +494,7 @@ extern int board_pci_host_broken(void);
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index ebf30e7..fa131e2 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -456,7 +456,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -489,7 +488,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 
 #if defined(CONFIG_PCI)
@@ -507,10 +505,7 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index f22ba9b..8cc7f02 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -549,7 +549,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #if defined(CONFIG_TSEC_ENET)
@@ -617,7 +616,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
@@ -632,7 +630,6 @@
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #endif
 
@@ -651,8 +648,6 @@
 #endif
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 4f49633..d827d2a 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -354,7 +354,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 435bdc8..6202dff 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -368,14 +368,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
     #define CONFIG_CMD_SCSI
-    #define CONFIG_CMD_EXT2
 #endif
 
 /*
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 0fdf939..dd07dc4 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -480,7 +480,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 56f6ef5..c68e1d8 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -351,7 +351,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index c049d8d..fb76dd1 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -378,7 +378,6 @@
 #endif
 
 #if defined(CONFIG_ETHER_ON_FCC)
-    #define CONFIG_CMD_MII
 #endif
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index d42191b..09e32eb 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -372,7 +372,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 37156cb..923159b 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -466,7 +466,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
@@ -482,10 +481,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 00db9b7..9144f32 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -572,13 +572,11 @@
  */
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index b6539b8..88ca4f3 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -446,12 +446,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_EXT2
 #endif
 
 #define CONFIG_WATCHDOG			/* watchdog enabled */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index b2e2f36..3569849 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -613,7 +613,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
     #define CONFIG_CMD_SCSI
-    #define CONFIG_CMD_EXT2
 #endif
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 87726a4..5719e86 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -718,7 +718,6 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
@@ -789,15 +788,12 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 		 || defined(CONFIG_FSL_SATA)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 5a7bef9..8b29951 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -552,20 +552,16 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -659,7 +655,6 @@
  */
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -677,7 +672,6 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
 #endif
 #endif
 
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 74cb57d..fcbe288 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -253,7 +253,6 @@ extern unsigned long get_clock_freq(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
@@ -271,9 +270,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 #endif
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 43709e8..b7a08e0 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -568,7 +568,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -601,9 +600,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
@@ -622,18 +619,13 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 
-#define CONFIG_CMD_EXT2
-
 #define CONFIG_MMC
 
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 7d7e2d0..4bd06a4 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -39,15 +39,12 @@
  */
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_FDC
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_BSP
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index a868ec9..71a0375 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -61,10 +61,8 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_EEPROM
 
 #define CONFIG_MAC_PARTITION
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 03c8fb9..a622578 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -58,7 +58,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #undef  CONFIG_WATCHDOG			/* watchdog disabled */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index e5555cc..005fa2a 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -271,8 +271,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 22f42f0..12260aa 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -667,7 +667,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -680,7 +679,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -690,10 +688,7 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -830,9 +825,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 7b6625f..74274ca 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -673,7 +673,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -683,10 +682,7 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -829,9 +825,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index da06bfd..4c1175d 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -548,7 +548,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -563,7 +562,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #endif
 #endif
 
@@ -573,10 +571,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif
@@ -703,9 +698,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index e58691b..9a3965f 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -606,7 +606,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -621,7 +620,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #endif
 #endif
 
@@ -630,10 +628,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -769,9 +764,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_CMD_DATE
 #endif
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 6f81368..85df388 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -713,7 +713,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -723,7 +722,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #define CONFIG_HAS_FSL_DR_USB
 #endif
 
@@ -731,15 +729,12 @@ unsigned long get_board_ddr_clk(void);
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif
@@ -770,9 +765,7 @@ unsigned long get_board_ddr_clk(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 508c896..5e2d659 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -674,7 +674,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -684,7 +683,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #define CONFIG_HAS_FSL_DR_USB
 #endif
 
@@ -692,14 +690,11 @@ unsigned long get_board_ddr_clk(void);
  * SDHC
  */
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -727,7 +722,6 @@ unsigned long get_board_ddr_clk(void);
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 1ff6309..276428f 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -506,7 +506,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -528,7 +527,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #define CONFIG_HAS_FSL_DR_USB
 
 #define CONFIG_MMC
@@ -537,10 +535,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_ESDHC_DETECT_QUIRK \
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 495c09c..a0cce85 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -282,7 +282,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -301,9 +300,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
@@ -707,7 +704,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -723,7 +719,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #define CONFIG_HAS_FSL_DR_USB
 
 #define CONFIG_MMC
@@ -732,10 +727,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index d542d2a..42ebcf0 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -128,7 +128,6 @@
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
 
 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 #define CONFIG_SYS_USB_OHCI_CPU_INIT
@@ -161,11 +160,9 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_BSP
 
@@ -181,8 +178,6 @@
 #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
 	defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
     #define CONFIG_CMD_IDE
-    #define CONFIG_CMD_FAT
-    #define CONFIG_CMD_EXT2
 #endif
 
 #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 304dc09..395805c 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -103,9 +103,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 72cd1e4..ec36637 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -101,9 +101,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 24ed057..2aac682 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -285,12 +285,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 2ed1539..00c0cc3 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -92,9 +92,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 469cd3f..ca26024 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -92,9 +92,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index eb0077b..39cf02e 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -94,9 +94,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index b504713..30bfb8a 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -123,9 +123,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index dfddd03..abe49b9 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -94,9 +94,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 2733849..48252c4 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -94,9 +94,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 9f09319..a73395a 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -97,9 +97,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index e76cb64..3db6fa1 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -97,9 +97,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 0d84ac7..76c8f7a 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -137,9 +137,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
 
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 778fcf5..88b97ab 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -133,12 +133,9 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index ccdfafa..4ae61ca 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -468,10 +468,8 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ERRATA
 #define CONFIG_CMD_CRAMFS
@@ -498,15 +496,12 @@
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_MMC_SPI
 #define CONFIG_CMD_MMC_SPI
 #define CONFIG_GENERIC_MMC
 #endif
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 5d7874b..4e349d5 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -48,7 +48,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_DATE
@@ -202,7 +201,6 @@
 #define MULTI_PURPOSE_SOCKET_ADDR	0x08000000
 
 /* File system */
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 405ac0d..d401d3e 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -60,7 +60,6 @@
  */
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_EEPROM
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 47e35c5..e0c92d0 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -45,8 +45,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_BSP
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_SERVERIP
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 09216d1..ee1bff8 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -92,9 +92,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DISPLAY
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index efd63a0..bcf6942 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -392,13 +392,10 @@
 #define CONFIG_LOADS_ECHO		1
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1
 
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_FUSE
 #undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_EXT2
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 95fc41e..7b9470c 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -103,19 +103,15 @@
  * SD (MMC) controller
  */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FTSDC010
 #define CONFIG_FTSDC010_NUMBER		1
 #define CONFIG_FTSDC010_SDIO
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 
 /*
diff --git a/include/configs/alt.h b/include/configs/alt.h
index b8b9644..3a81c49 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -90,7 +90,6 @@
 /* MMCIF */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 
 #define CONFIG_SH_MMCIF
 #define CONFIG_SH_MMCIF_ADDR		0xee200000
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index bee6b83..cd8923d 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -348,7 +348,6 @@
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
-#define CONFIG_CMD_DFU
 #define DFU_ALT_INFO_MMC \
 	"dfu_alt_info_mmc=" \
 	"boot part 0 1;" \
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index cbfe1bd..822e1c8 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -103,7 +103,6 @@
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
 
 #ifdef CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
@@ -127,11 +126,8 @@
 #endif /* CONFIG_USB_AM35X */
 
 /* commands to include */
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 2cbf04e..6f83870 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -119,16 +119,7 @@
 
 /* commands to include */
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_PART
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_MTDPARTS
 
 /* I2C */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 59a9749..5b49988 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -11,8 +11,6 @@
 
 #define CONFIG_AM43XX
 
-#define CONFIG_CMD_FAT
-
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_CACHELINE_SIZE       32
@@ -149,7 +147,6 @@
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
-#define CONFIG_CMD_DFU
 
 #define CONFIG_DFU_MMC
 #define DFU_ALT_INFO_MMC \
@@ -320,7 +317,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* CPSW Ethernet */
-#define CONFIG_CMD_MII
 #define CONFIG_MII
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_DNS
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 099ecdd..32d7d4d 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -54,7 +54,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT		10
-#define CONFIG_CMD_MII
 #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
 #define CONFIG_PHY_GIGE			/* per-board part of CPSW */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 89093bd..9fa4d16 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -50,15 +50,11 @@
 /*
  * Commands
  */
-#define CONFIG_CMD_ASKENV
 #if defined(CONFIG_440)
-#define CONFIG_CMD_CACHE
 #endif
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 3ef7257..e819185 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -22,7 +22,6 @@
 #define CONFIG_BOOTCOMMAND		"bootm ffc20000"
 
 #undef CONFIG_CMD_AES
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DIAG
 
 /* undef to save memory	*/
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index fdcbf31..ae58ec8 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -16,7 +16,6 @@
 
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_BAUDRATE		38400
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index d458705..be8feed 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -18,7 +18,6 @@
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
 
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 9c09087..514e9ee 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -31,7 +31,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index f8c91f8..2291647 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -65,16 +65,10 @@
 /*
  * U-Boot Commands
  */
-#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
-#define CONFIG_CMD_CACHE	/* icache, dcache		*/
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_IMX_FUSE	/* imx iim fuse                 */
-#define CONFIG_CMD_MII		/* MII support			*/
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_MTDPARTS	/* MTD partition support	*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_NAND_LOCK_UNLOCK
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index 1f7ef8f..bb29f3f 100644
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -24,12 +24,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 
 /* Memory configuration */
diff --git a/include/configs/aria.h b/include/configs/aria.h
index b69e08e..2d32da1 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -402,12 +402,10 @@
 #define CONFIG_LOADS_ECHO		1
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1
 
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_FUSE
 #undef CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index 8154b2e..d87d40c 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -29,7 +29,6 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index e1fe7e6..681b4e7 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -18,8 +18,6 @@
 
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_BOOTZ
 
 #define BOARD_LATE_INIT
 
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 6660eb0..b08276f 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -59,7 +59,6 @@
 
 /* Define which commands should be available at u-boot command prompt */
 
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #if ENABLE_JFFS
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index e260867..dc955b2 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -30,7 +30,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_CMD_BOOTZ
 
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index ee3712c..2979b25 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -58,8 +58,6 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#define CONFIG_CMD_BOOTZ
-
 /*
  * Memory Configuration
  */
@@ -119,8 +117,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
 
 /*
  * Network Driver Setting
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 2a5301f..9db8d12 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -45,8 +45,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
@@ -77,7 +75,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_FAT
 
 /*
  * SDRAM: 1 bank, min 32, max 128 MB
@@ -128,7 +125,6 @@
 #define AT91_SPI_CLK			15000000
 #else
 /* Enable MMC. The MCCK is conflicted with DataFlash */
-#define CONFIG_CMD_MMC
 #endif
 
 #ifdef CONFIG_AT91SAM9G20EK
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 82f90f2..b369624 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -143,7 +143,6 @@
 #endif
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index c7fac7f..f248049 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -45,8 +45,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /*
  * Hardware drivers
  */
@@ -92,7 +90,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_MMC
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
@@ -118,11 +115,6 @@
 #define CONFIG_GENERIC_ATMEL_MCI
 #endif
 
-/* FAT */
-#ifdef CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
 /* NOR flash, if populated */
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define CONFIG_SYS_FLASH_CFI			1
@@ -287,7 +279,6 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
-#define CONFIG_CMD_FAT			1
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
 
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 8bc5144..18eb01d 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -30,8 +30,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
@@ -103,7 +101,6 @@
 #endif
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -112,7 +109,6 @@
 #endif
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index fdebcc2..2f8c377 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -67,10 +67,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_SDRAM_BASE		0x20000000
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 6a03923..d178d9d 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -31,8 +31,6 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO		1
 #define CONFIG_AT91_GPIO_PULLUP		1
@@ -111,13 +109,11 @@
 #endif
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index fd87bb7..251094e 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -26,8 +26,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
@@ -66,8 +64,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 
 /*
  * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index a18a2c9..e6f6125 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -80,11 +80,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
 
 #define CONFIG_ATMEL_USART
 #define CONFIG_MACB
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index 09e193e..fb12632 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -99,12 +99,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_MII
 
 #define CONFIG_ATMEL_USART
 #define CONFIG_MACB
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 62f01a7..9a647d8 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -101,11 +101,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MMC
 
 #define CONFIG_ATMEL_USART
 #define CONFIG_MACB
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 006ddb3..1bd4729 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -105,8 +105,6 @@
 /*
  * Commands still not supported in Kconfig
  */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 
 #define CONFIG_AUTO_COMPLETE
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 27ab8f7..4f3909a 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -304,7 +304,6 @@
 #define CONFIG_PHY_ADDR			0
 #define CONFIG_PHY_SMSC
 #define CONFIG_MII
-#define CONFIG_CMD_MII
 #define CONFIG_PHY_ATHEROS
 
 /* NAND support */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index d231f7a..784bfef 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -185,8 +185,6 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 377fa94..e391c91 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -461,7 +461,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #endif
 
 #ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #endif /* CONFIG_USB_MUSB_GADGET */
 
@@ -480,7 +479,6 @@ DEFAULT_LINUX_BOOT_ENV \
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
-#define CONFIG_CMD_DFU
 #define DFU_ALT_INFO_MMC \
 	"dfu_alt_info_mmc=" \
 	"boot part 0 1;" \
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
index 92326e1..8f31436 100644
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@@ -30,7 +30,6 @@
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SDMA
-#define CONFIG_CMD_MMC
 
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index b9e9dcc..889e5db 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -124,11 +124,6 @@
 #define CONFIG_BOOTCOMMAND		""
 
 /* Commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_FAT_WRITE
 
 /* Fastboot and USB OTG */
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 4ac4faf..d5888e8 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -80,9 +80,6 @@
 #define CONFIG_MX_CYCLIC
 
 /* Commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 
 /* SHA hashing */
@@ -93,8 +90,6 @@
 
 /* Enable Time Command */
 
-#define CONFIG_CMD_BOOTZ
-
 /* Misc utility code */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CRC32_VERIFY
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 44e3621..a1c2002 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -31,7 +31,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index a351d1b..43a9032 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -136,7 +136,6 @@
 #endif
 
 #define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 
 #define CONFIG_BOOTCOMMAND	"run ramboot"
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index cbe752a..7055366 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -139,7 +139,6 @@
 #endif
 
 #define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 
 #define CONFIG_BOOTCOMMAND	"run flashboot"
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index c36be03..76b891b 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -71,7 +71,6 @@
  * Network Settings
  */
 #define ADI_CMDS_NETWORK			1
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index a62038e..4deb2d2 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -72,7 +72,6 @@
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_DW_PORTS		1
 #define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_CMD_MII
 #define CONFIG_MII
 
 /* i2c Settings */
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 1b35a86..88d2ae9 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -17,18 +17,13 @@
 #  define CONFIG_BOOTP_RANDOM_DELAY
 #  define CONFIG_KEEP_SERVERADDR
 #  ifdef CONFIG_BFIN_MAC
-#   define CONFIG_CMD_MII
 #  endif
 # endif
 # ifdef CONFIG_LIBATA
-#  define CONFIG_CMD_FAT
 #  define CONFIG_CMD_SATA
 #  define CONFIG_DOS_PARTITION
 # endif
 # ifdef CONFIG_MMC
-#  define CONFIG_CMD_EXT2
-#  define CONFIG_CMD_FAT
-#  define CONFIG_CMD_MMC
 #  define CONFIG_DOS_PARTITION
 #  define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
 # endif
@@ -36,8 +31,6 @@
 #  define CONFIG_CMD_MMC_SPI
 # endif
 # ifdef CONFIG_USB
-#  define CONFIG_CMD_EXT2
-#  define CONFIG_CMD_FAT
 #  define CONFIG_CMD_USB_STORAGE
 #  define CONFIG_DOS_PARTITION
 # endif
@@ -66,7 +59,6 @@
 #  define CONFIG_JFFS2_SUMMARY
 # endif
 # define CONFIG_CMD_BOOTLDR
-# define CONFIG_CMD_CACHE
 # define CONFIG_CMD_CPLBINFO
 # define CONFIG_CMD_KGDB
 # define CONFIG_CMD_LDRINFO
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index e48be7a..6a5bc12 100644
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -14,9 +14,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
 
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 515ed77..6eb83a0 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -103,7 +103,6 @@
 #define CONFIG_ENV_OVERWRITE	1
 
 #define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_CPLBINFO
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
index ef90603..ba90830 100644
--- a/include/configs/blackvme.h
+++ b/include/configs/blackvme.h
@@ -74,7 +74,6 @@
  */
 #define CONFIG_DRIVER_AX88180	1
 #define AX88180_BASE		0x2c000000
-#define CONFIG_CMD_MII		/* enable probing PHY */
 
 #define CONFIG_HOSTNAME	blackvme	/* Bfin board  */
 #define CONFIG_IPADDR		169.254.144.145	/* Bfin board  */
@@ -150,7 +149,6 @@
 #define CONFIG_AUTO_COMPLETE	1
 
 #define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_CPLBINFO
 
 /*
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 37adede..506ad88 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -308,13 +308,10 @@
  * U-Boot commands
  */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_MII
 #endif
 
 /* additions for new relocation code, must added to all boards */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 028d0a2..31fe5f6 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -48,10 +48,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index ad9f418..e68e342 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -382,8 +382,6 @@
 #elif defined(CONFIG_CANYONLANDS)
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SATA
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 85fd327..7107b72 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -34,7 +34,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 57dfdde..dd03936 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -70,7 +70,6 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* USB Configs */
-#define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -85,11 +84,9 @@
 
 #define CONFIG_USBD_HS
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 /* USB Device Firmware Update support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_DFU_SF
@@ -130,7 +127,6 @@
 #define CONFIG_LIBATA
 
 /* Ethernet */
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index 991121d..ffaeedb 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -25,14 +25,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PCI
 
 /* I2C */
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index cdb8931..99182f4 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -23,13 +23,10 @@
 /*
  * Supported commands
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index b36ba14..9a12552 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -18,7 +18,6 @@
 #define CONFIG_MACH_TYPE		4273
 
 /* CMD */
-#define CONFIG_CMD_GREPENV
 
 /* MMC */
 #define CONFIG_SYS_FSL_USDHC_NUM	3
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index aca9288..5d58116 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -106,9 +106,6 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define CONFIG_MTD_PARTITIONS
@@ -117,7 +114,6 @@
 				"1920k(u-boot),256k(u-boot-env),"\
 				"4m(kernel),-(fs)"
 
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
 #define CONFIG_SYS_NO_FLASH
@@ -191,7 +187,6 @@
 		"nand read ${loadaddr} 2a0000 400000; " \
 		"bootm ${loadaddr}\0" \
 
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
 		"if run loadbootscript; then " \
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 1bedea7..7cedb67 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -119,9 +119,6 @@
 #define CONFIG_USB_STORAGE
 
 /* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define CONFIG_MTD_PARTITIONS
@@ -130,7 +127,6 @@
 				"1920k(u-boot),256k(u-boot-env),"\
 				"4m(kernel),-(fs)"
 
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
 #define CONFIG_SYS_NO_FLASH
@@ -199,7 +195,6 @@
 		"nand read ${loadaddr} 2a0000 400000; " \
 		"bootm ${loadaddr}\0" \
 
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
 		"if run loadbootscript; then " \
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index b291ba4..509c8b42 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -120,8 +120,6 @@
  * Command line configuration.
  */
 
-#undef CONFIG_CMD_MII
-
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_MII		1
 #	define CONFIG_MII_INIT		1
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index c38d888..5dffc9e 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -54,7 +54,6 @@
  * Bootloader Components Configuration
  */
 #define	CONFIG_CMD_ENV
-#define	CONFIG_CMD_MMC
 
 /* I2C support */
 #ifdef CONFIG_SYS_I2C
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 01fc13d..c15f0cb 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -30,7 +30,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* USB host support */
 #define CONFIG_USB_EHCI
@@ -76,7 +75,6 @@
 #define CONFIG_ENV_SIZE			(SZ_64K)
 
 /* UBI */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
 #define CONFIG_LZO
@@ -84,7 +82,6 @@
 #define CONFIG_RBTREE
 
 /* Debug commands */
-#define CONFIG_CMD_CACHE
 
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index a34da80..7e98166 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -31,7 +31,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index ea33e7a..50f7c21 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -43,7 +43,6 @@
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_CMD_ASKENV
 
 /* NAND support */
 #define CONFIG_CMD_NAND
@@ -69,21 +68,15 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT4
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_RBTREE
 #define CONFIG_LZO
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_UBI
 #define CONFIG_MTD_UBI_FASTMAP
 #define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET1_BASE_ADDR
@@ -213,8 +206,6 @@
 #define CONFIG_ENV_OFFSET		(12 * 64 * 2048)
 #endif
 
-#define CONFIG_CMD_BOOTZ
-
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_SYS_CACHELINE_SIZE 32
@@ -233,7 +224,6 @@
 #define CONFIG_TRDX_PID_COLIBRI_VF50IT   0x0019
 
 /* USB DFU */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_DFU_MMC
@@ -242,6 +232,5 @@
 /* USB Storage */
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_CMD_USB_MASS_STORAGE
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index 556d44e..4c37d5e 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -32,7 +32,6 @@
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SDMA
-#define CONFIG_CMD_MMC
 
 #undef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 9d1c6ae..1bb8d93 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -224,7 +224,6 @@
  */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
@@ -377,10 +376,7 @@
 #ifndef CONFIG_TRAILBLAZER
 
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 1ab2efb..96f17d3 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -579,7 +579,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -611,9 +610,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -631,17 +628,13 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index fffcd95..8b3c715 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -39,8 +39,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
@@ -115,7 +113,6 @@
 #define CONFIG_MTD_PARTITIONS
 
 /* DFU class support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 432f2f6..49ed3ef 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -32,7 +32,6 @@
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SDMA
-#define CONFIG_CMD_MMC
 
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index d1927b5..4280c9c 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -413,7 +413,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -433,9 +432,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
@@ -453,7 +450,6 @@
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_CMD_EXT2
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_STDIO_DEREGISTER
@@ -467,10 +463,7 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 9466332..af220fe 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -285,9 +285,7 @@
  * U-Boot commands
  */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
@@ -295,7 +293,6 @@
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_MII
 #endif
 
 #ifdef CONFIG_USE_NAND
@@ -336,9 +333,6 @@
  */
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #endif
 
 #ifndef CONFIG_DIRECT_NOR_BOOT
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 40dc35c..82b1f2c 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -27,7 +27,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index f8454cf..01c7895 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -24,12 +24,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index d31e74f..d84dde3 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -25,13 +25,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SCSI
 
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 66b723d..d6acbbc 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -26,12 +26,7 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SATA
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index f9f30b1..eb0a87c 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -73,8 +73,6 @@
  * Command line configuration.
  */
 #undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_MII
 
 #ifdef CONFIG_DBAU1550
 
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 4114f9e..913b948 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -82,7 +82,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR			0x1F
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_CMD_MII
 
 /*
  * NOR Flash
@@ -126,7 +125,6 @@
 #define CONFIG_USB_OHCI_LPC32XX
 #define CONFIG_USB_ISP1301_I2C_ADDR		0x2d
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
 
 /*
  * U-Boot General Configurations
@@ -174,7 +172,6 @@
 /*
  * U-Boot Commands
  */
-#define CONFIG_CMD_CACHE
 
 /*
  * Boot Linux
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 6acd2fe..5112ef3 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -99,12 +99,8 @@
 #define CONFIG_CMD_JFFS2		/* JFFS2 Support		*/
 #define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
 
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_BOOTZ
 #undef CONFIG_SUPPORT_RAW_INITRD
 #undef CONFIG_FAT_WRITE
-#undef CONFIG_CMD_EXT4
-#undef CONFIG_CMD_FS_GENERIC
 
 /* BOOTP/DHCP options */
 #define CONFIG_BOOTP_SUBNETMASK
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 0bf5088..18804d4 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -101,15 +101,11 @@
 #ifdef CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #endif
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SAVES
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
index c0c0de9..0a7bc8a 100644
--- a/include/configs/dnp5370.h
+++ b/include/configs/dnp5370.h
@@ -53,8 +53,6 @@
 #define CONFIG_PHY_ADDR         0
 #define CONFIG_RMII             1
 
-#define CONFIG_CMD_MII
-
 #endif
 
 /*
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index e54321b..cd05857 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -30,7 +30,6 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 /*
  * mv-common.h should be defined after CMD configs since it used them
@@ -87,8 +86,6 @@
 /*
  * File system
  */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d6ed05..79b6c09 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -148,7 +148,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT		10
-#define CONFIG_CMD_MII
 #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
 #define CONFIG_PHY_GIGE			/* per-board part of CPSW */
@@ -224,7 +223,6 @@
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
-#define CONFIG_CMD_DFU
 
 #define CONFIG_DFU_MMC
 #define CONFIG_DFU_RAM
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 2d4a45d..8aee25b 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -33,7 +33,6 @@
 	"led1=64,0,1\0"
 
 #undef CONFIG_DOS_PARTITION
-#undef CONFIG_CMD_FAT
 
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index 42fb0f3..d32889d 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -59,11 +59,9 @@
 #define CONFIG_MD5
 
 /* Extra Commands */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_GPT
 #define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_MMC
 /* Enable that for switching of boot partitions */
 /* Disabled by default as some sub-commands can brick eMMC */
 /*#define CONFIG_SUPPORT_EMMC_BOOT */
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index 0b7d89b..c78c949 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -39,8 +39,6 @@
 /*
  * Commands configuration
  */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 
 /*
  * mv-plug-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h
index 3a7f490..9de1179 100644
--- a/include/configs/e2220-1170.h
+++ b/include/configs/e2220-1170.h
@@ -25,7 +25,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index b52f34b..d4f3cfa 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -143,9 +143,7 @@
  * U-Boot commands
  */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
@@ -153,7 +151,6 @@
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_MII
 #endif
 
 /* NAND Setup */
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 861f2ac..521e3cf 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -66,7 +66,6 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_LED
-#define CONFIG_CMD_MII
 
 #define CONFIG_MCFTMR
 
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 3ab1803..2ac7757 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -30,11 +30,8 @@
 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index c64d119..174cdf3 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -238,7 +238,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SPI
-#define CONFIG_CMD_MMC
 #define CONFIG_MMC_SPI_NPOWER_EGPIO	9
 #endif
 
@@ -250,12 +249,7 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ep93xx-ohci"
 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80020000
 
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-
 #define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_CMD_BOOTZ
 
 /* Define to disable flash configuration*/
 /* #define CONFIG_EP93XX_NO_FLASH_CFG */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 4444bc9..99d16b0 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -157,7 +157,6 @@
 #define __io
 #define CONFIG_IDE_PREINIT
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 /* ED Mini V has an IDE-compatible SATA connector for port 1 */
 #define CONFIG_MVSATA_IDE
 #define CONFIG_MVSATA_IDE_USE_PORT1
diff --git a/include/configs/espt.h b/include/configs/espt.h
index ed92865..3d67376 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -18,7 +18,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BOOTDELAY        -1
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index cfb009c..94fee54 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -88,18 +88,12 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND
 
 #ifndef MINIMAL_LOADER
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BSP
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_REISER
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_UBI
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 0a2d610..f97f03c 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -26,7 +26,6 @@
 #define CONFIG_USE_ARCH_MEMSET
 
 /* Keep L2 Cache Disabled */
-#define CONFIG_CMD_CACHE
 
 /* input clock of PLL: 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
@@ -57,10 +56,7 @@
 #define CONFIG_PWM
 
 /* Command definition*/
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_FS_GENERIC
 
 #define CONFIG_CMD_PART
 #define CONFIG_PARTITION_UUIDS
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 8522a79..fbe0fa9 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -24,7 +24,6 @@
 
 #undef CONFIG_CMD_ONENAND
 #undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_DFU
 #define CONFIG_CMD_GPT
 
 /* TIZEN THOR downloader support */
@@ -46,7 +45,6 @@
 
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 /* Common environment variables */
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index e74aa68..7400870 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -78,9 +78,7 @@
 #define CONFIG_BOOTP_DNS
 
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
 
-#define CONFIG_CMD_MII
 #define CONFIG_NET_RETRY_COUNT	100
 
 #define CONFIG_BOOTDELAY	3
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 14a42b1..2f1f6d4 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -40,7 +40,6 @@
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SDMA
-#define CONFIG_CMD_MMC
 
 /* 10/100M Ethernet support */
 #define CONFIG_DESIGNWARE_ETH
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 0c594b8..1304879 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -73,15 +73,11 @@
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* USB Configs */
-#define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -97,7 +93,6 @@
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_GADGET_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_VBUS_DRAW 2
@@ -106,7 +101,6 @@
 #define CONFIG_G_DNL_MANUFACTURER "Advantech"
 
 /* Networking Configs */
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -132,7 +126,6 @@
 
 /* Command definition */
 #define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_LOADADDR	0x12000000
 #define CONFIG_SYS_TEXT_BASE	0x17800000
@@ -296,7 +289,6 @@
 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
 #endif
 
 #define CONFIG_SYS_FSL_USDHC_NUM	3
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index d0432ad..ffbe660 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -52,11 +52,9 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT4
 #define CONFIG_SYS_MVFS         /* Picks up Filesystem from mv-common.h */
 
 /*
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 4e29825..230be31 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -96,7 +96,6 @@
 
 /* SDHI */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_SH_SDHI_FREQ		97500000
 
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 638fad1..40ec030 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -52,8 +52,6 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 
 /* Disable DCACHE */
 #define CONFIG_SYS_DCACHE_OFF
@@ -71,7 +69,6 @@
 
 /* PHY configuration */
 #define CONFIG_MII
-#define CONFIG_CMD_MII
 #define CONFIG_RESET_PHY_R
 /* 88E3015 register definition */
 #define PHY_LED_PAR_SEL_REG		22
@@ -108,8 +105,6 @@
 #define CONFIG_ENV_SIZE			0x4000
 #define CONFIG_ENV_OFFSET		0x07C000
 
-#define CONFIG_CMD_ASKENV
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_ARMADA100
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 563b205..94eb7ac 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -60,8 +60,6 @@
 /* USB support */
 #if USE_GRUSB
 #define CONFIG_USB_UHCI
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_USB_STORAGE
 /* Enable needed helper functions */
 #define CONFIG_SYS_STDIO_DEREGISTER	/* needs stdio_deregister */
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 8e0cff9..83f1d73 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -93,7 +93,6 @@
  * Command line configuration.
  */
 /* add useful commands */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 58598c3..e11629c 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -149,7 +149,6 @@
 #define CONFIG_POWER_LTC3676_I2C_ADDR  0x3c
 
 /* Various command support */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_BMODE         /* set eFUSE shadow for a boot dev and reset */
 #define CONFIG_CMD_HDMIDETECT    /* detect HDMI output device */
 #define CONFIG_CMD_GSC
@@ -185,7 +184,6 @@
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 
 /* USB Mass Storage Gadget */
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 /* Framebuffer and LCD */
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index aa0f38c..d3ab10e 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -30,7 +30,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* NAND support */
 #define CONFIG_CMD_NAND
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index d08ab1d..114a6d1 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -82,13 +82,11 @@
 #define CONFIG_DWMMC
 #define CONFIG_HIKEY_DWMMC
 #define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_MMC
 
 #define CONFIG_FS_EXT4
 
 /* Command line configuration */
 #define CONFIG_MENU
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_UNZIP
 #define CONFIG_CMD_ENV
 
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index d59d21f..9f02a65 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -35,10 +35,8 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_CMD_FPGAD
 #define CONFIG_CMD_IOLOOP
@@ -533,7 +531,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index 57b1a43..ab23607 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -35,9 +35,7 @@
  */
 #define CONFIG_SYS_NO_FLASH		/* declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/icon.h b/include/configs/icon.h
index d42e6f0..7e9e7e6 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -167,8 +167,6 @@
  */
 #define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 #ifdef CONFIG_VIDEO
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
index c156bd3..f0d4250 100644
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -39,7 +39,6 @@
 #define CONFIG_SYS_NO_FLASH		/* declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 
 /*
@@ -95,8 +94,6 @@
 /*
  * File system
  */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index da4cba7..04515ba 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -414,7 +414,6 @@
  * U-Boot environment setup
  */
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CMD_JFFS2
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index c03e566..b8ee44d 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -171,13 +171,8 @@
 /*
  * U-Boot commands
  */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 
 #define CONFIG_BOOTDELAY	5
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 282cc25..0d4f292 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -80,8 +80,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_PCI
 
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 6f48b4b..f3db077 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -281,8 +281,6 @@
 #define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 4d1f309..43688c7 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -61,7 +61,6 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_FPGAD
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_IRQ
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 3675099..b2a6e7f 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -250,9 +250,7 @@
  * U-Boot commands
  */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
@@ -260,7 +258,6 @@
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_MII
 #endif
 
 #define CONFIG_CMD_NAND
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index 636f6bd..55ed656 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -106,10 +106,8 @@
 #define CONFIG_CMD_BMP		/* BMP support */
 #endif
 #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
-#define CONFIG_CMD_FAT		/* FAT support */
 #define CONFIG_CMD_IDE		/* IDE harddisk support */
 #define CONFIG_CMD_IRQ		/* irqinfo */
-#define CONFIG_CMD_MII		/* MII support */
 #define CONFIG_CMD_PCI		/* pciinfo */
 
 #define CONFIG_SYS_LOWBOOT	1
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 30ef13f..953c088 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -29,7 +29,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index a2d2646..3f98510 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -63,7 +63,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
 
 #undef CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_IS_IN_FAT
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index f5dddae..9513c6d 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -175,8 +175,6 @@
 #define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ECCTEST
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 30be533..b08cf21 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -94,8 +94,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
 
-#define CONFIG_CMD_MMC
-
 /*
  * Power
  */
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index dd0cec4..9f76034 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -13,11 +13,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DEFAULTENV_VARS
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MTDPARTS
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index fdd293f..25db704 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -158,7 +158,6 @@
  */
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_CMD_MII		/* to debug mdio phy config */
 #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 685f0e5..121fe3f 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -96,7 +96,6 @@
 
 /* SD */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_SH_SDHI_FREQ	97500000
 
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 4ec4e33..bcb9e7e 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -48,7 +48,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
 #define CONFIG_SUPPORT_EMMC_BOOT
 /* RAW SD card / eMMC locations. */
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
@@ -115,7 +114,6 @@ BUR_COMMON_ENV \
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-#define CONFIG_CMD_BOOTZ
 
 /* USB configuration */
 #define CONFIG_USB_MUSB_DSPS
@@ -140,9 +138,7 @@ BUR_COMMON_ENV \
  */
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_FS_GENERIC
 #endif /* CONFIG_MMC, ... */
 
 #endif	/* __CONFIG_KWB_H__ */
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index bf283fe..710629b 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -28,8 +28,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"root=/dev/null console=ttySC4,115200"
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 18cd4bb..9b2c575 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -148,8 +148,6 @@
 /*
  * File systems support
  */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 
 /*
  * Console configuration
diff --git a/include/configs/lager.h b/include/configs/lager.h
index ad8b12f..9971ad8 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -88,7 +88,6 @@
 
 /* MMC */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 
 #define CONFIG_SH_MMCIF
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 54563e3..1aad97d 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -208,9 +208,7 @@
 /*
  * U-Boot commands
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 
 #ifdef CONFIG_CMD_BDI
@@ -233,9 +231,6 @@
  */
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #endif
 
 /* additions for new relocation code, must added to all boards */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 3cbb522..3796395 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -412,11 +412,9 @@ unsigned long get_board_ddr_clk(void);
  * MMC
  */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* SPI */
@@ -460,7 +458,6 @@ unsigned long get_board_ddr_clk(void);
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -557,8 +554,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_PCI
 #endif
 
-#define CONFIG_CMD_MII
-
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
@@ -603,7 +598,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_GREPENV
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
@@ -654,8 +648,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
 #endif
 
-#define CONFIG_CMD_BOOTZ
-
 #define CONFIG_MISC_INIT_R
 
 /* Hash command with SHA acceleration supported in hardware */
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 1fd9e03..3e32128 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -65,7 +65,6 @@
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -299,11 +298,9 @@
  * MMC
  */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* SPI */
@@ -406,8 +403,6 @@
 #define CONFIG_CMD_PCI
 #endif
 
-#define CONFIG_CMD_MII
-
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
@@ -448,7 +443,6 @@
 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_GREPENV
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
@@ -497,8 +491,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
 #endif
 
-#define CONFIG_CMD_BOOTZ
-
 #define CONFIG_MISC_INIT_R
 
 /* Hash command with SHA acceleration supported in hardware */
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index d84c734..54968b5 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -174,14 +174,11 @@
 #endif
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
 
 /*  MMC  */
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 3bdece7..d71a229 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -109,8 +109,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
@@ -396,7 +394,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
 #endif
 
 /*
@@ -409,7 +406,6 @@ unsigned long get_board_ddr_clk(void);
 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_CMD_GREPENV
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
@@ -456,8 +452,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE			0x20000
 #endif
 
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_MII
 #define CONFIG_CMDLINE_TAG
 
 #include <asm/fsl_secure_boot.h>
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 7c662a3..6d35be2 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -246,7 +246,6 @@
 /* FMan */
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
-#define CONFIG_CMD_MII
 #define CONFIG_PHYLIB
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
@@ -284,7 +283,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
 #endif
 
 #include <asm/fsl_secure_boot.h>
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 8b75088..8e0b472 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -210,10 +210,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
 
 /* Command line configuration */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 924011c..bc0d678 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -131,11 +131,9 @@
 /*  MMC  */
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3ec4bb6..2d7567f 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -45,8 +45,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
@@ -324,11 +322,9 @@ unsigned long get_board_ddr_clk(void);
 /*  MMC  */
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -352,7 +348,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_MEMAC
 #define	CONFIG_PHYLIB
 #define CONFIG_PHYLIB_10G
-#define	CONFIG_CMD_MII
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_TERANETICS
@@ -394,7 +389,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
 
 #include <asm/fsl_secure_boot.h>
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 8ba0512..5bec509 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -63,8 +63,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
 #define CONFIG_CMD_SCSI
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
@@ -306,11 +304,9 @@ unsigned long get_board_sys_clk(void);
 /*  MMC  */
 #define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -326,7 +322,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 094a7e2..e878cbe 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -49,12 +49,8 @@
 /*
  * Commands configuration
  */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_FS_GENERIC
 
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 3dc59e4..d5082fa 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -400,13 +400,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 2070f33..428128d 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -20,18 +20,9 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BMP
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
 #define	CONFIG_VIDEO
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 9ababa3..4349357 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -28,16 +28,8 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
 #define CONFIG_CMD_SATA
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index 2429e3a..fb14463 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -23,16 +23,6 @@
 #define CONFIG_FAT_WRITE
 /*#define CONFIG_LCD*/
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-
 /*
  * Memory configurations
  */
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index 20457f6..8d4a8cd 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -26,8 +26,6 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
 
 /*
  * 8-symbol LED display (can be accessed with 'display' command)
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index d12f291..3dbd920 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -108,15 +108,10 @@
 #define CONFIG_USB_ETHER_MCS7830
 
 /* commands to include */
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_RBTREE
@@ -135,7 +130,6 @@
 #define CONFIG_RTC_DS1337
 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
 
-#define CONFIG_CMD_MII
 /*
  * Board NAND Info.
  */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index cca7c33..9262f72 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -290,15 +290,11 @@
 #define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
 #undef CONFIG_CMD_FUSE
 #undef CONFIG_CMD_IDE
-#undef CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_DOS_PARTITION
 
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index 8a24cfb..f3a6a86 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -23,7 +23,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* NAND support */
 #define CONFIG_CMD_NAND
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index d65a4cd..f71b662 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -56,8 +56,6 @@
 #define CONFIG_DISPLAY_CPUINFO			/* display cpu info and speed */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 
-#define CONFIG_CMD_BOOTZ
-
 /*
  * Hardware drivers
  */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index cdaf828..801d674 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -172,14 +172,11 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MFSL
 
 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
-# define CONFIG_CMD_CACHE
 #else
-# undef CONFIG_CMD_CACHE
 #endif
 
 #if defined(FLASH)
@@ -274,7 +271,6 @@
 
 #if defined(CONFIG_XILINX_AXIEMAC)
 # define CONFIG_MII		1
-# define CONFIG_CMD_MII		1
 # define CONFIG_PHY_GIGE	1
 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
 # define CONFIG_PHY_ATHEROS	1
@@ -289,7 +285,6 @@
 # define CONFIG_PHY_VITESSE	1
 #else
 # undef CONFIG_MII
-# undef CONFIG_CMD_MII
 #endif
 
 /* SPL part */
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 93d34e9..674d1f6 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -32,7 +32,6 @@
 #define CONFIG_SDHCI
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC_SDMA
-#define CONFIG_CMD_MMC
 
 #undef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index f4b0e34..62919e9 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -34,16 +34,13 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /*
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 2179f60..e0c9a98 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -408,13 +408,10 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #undef CONFIG_CMD_FUSE
@@ -455,7 +452,6 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_ISO_PARTITION
 
-#define CONFIG_CMD_FAT
 #define CONFIG_SUPPORT_VFAT
 
 #endif /* defined(CONFIG_CMD_IDE) */
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 149f365..66e1a45 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -388,7 +388,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 3ac4b0b..3f2bfa4 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -11,7 +11,6 @@
 #define __MPR2_H
 
 /* Supported commands */
-#define CONFIG_CMD_CACHE
 
 /* Default environment variables */
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 5b6880b..27ed1d5 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -13,10 +13,8 @@
 #define CONFIG_MS7720SE		1
 
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PCMCIA
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 438497e..efbd447 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -26,7 +26,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_IMMAP
 #define CONFIG_CMD_REGINFO
 
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 674aa0a..6d4bbd1 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -138,9 +138,7 @@
  * File system
  */
 #ifdef CONFIG_SYS_MVFS
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_RBTREE
diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h
index 116c821..bf583d0 100644
--- a/include/configs/mv-plug-common.h
+++ b/include/configs/mv-plug-common.h
@@ -23,7 +23,6 @@
 #ifdef CONFIG_SYS_MVFS
 #define CONFIG_BZIP2
 #define CONFIG_LZMA
-#define CONFIG_CMD_BOOTZ
 #endif /* CONFIG_SYS_MVFS */
 
 /*
@@ -33,12 +32,10 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
 
 /*
  * Extra file system
  */
-#define CONFIG_CMD_EXT4
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index 705bee8..1bdbe4b 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -15,11 +15,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_LED
-#define CONFIG_CMD_MMC
 
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 4936733..542f1f4 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -18,11 +18,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_VIDEO
 
 /* Memory configuration */
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index cc86c94..c63887b 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -82,11 +82,6 @@
 #define CONFIG_SYS_LONGHELP
 
 /* U-Boot commands */
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 
 /* Ethernet */
 #define CONFIG_FEC_MXC
@@ -122,8 +117,6 @@
 
 /* Ethernet Configs */
 
-#define CONFIG_CMD_MII
-
 #define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 36a5063..b3c03b3 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -20,15 +20,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
 #define CONFIG_VIDEO
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 797eb09..3f63007 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -79,10 +79,8 @@
 /***********************************************************
  * Command definition
  ***********************************************************/
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 5f4142a..aed0939 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -78,24 +78,18 @@
 /*
  * Command definition
  */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_DNS
 
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
 
-#define CONFIG_CMD_MII
 #define CONFIG_NET_RETRY_COUNT	100
 #define CONFIG_CMD_DATE
 
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 
 #define CONFIG_BOOTDELAY	1
 
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 2f75f2b..23b8b46 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -72,9 +72,7 @@
 
 #define CONFIG_MMC
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /*
@@ -86,10 +84,7 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_MII
-
 /* USB Configs */
-#define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX5
 #define CONFIG_USB_STORAGE
@@ -122,7 +117,6 @@
 /***********************************************************
  * Command definition
  ***********************************************************/
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 48b4dca..e697261 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -31,8 +31,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MXC_GPIO
 
-#define CONFIG_CMD_BOOTZ
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
 #define CONFIG_NAND_MXC
@@ -59,17 +57,13 @@
 #define CONFIG_SYS_FSL_ESDHC_NUM	2
 
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
 #define CONFIG_HAS_ETH1
 #define CONFIG_MII
 
-#define CONFIG_CMD_MII
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 46f93b9..feb5580 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -56,9 +56,7 @@
 #define CONFIG_SYS_FSL_ESDHC_NUM	2
 
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
@@ -68,7 +66,6 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 
 /* Miscellaneous commands */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 8d2581a..8743ddc 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -41,11 +41,7 @@
 #define CONFIG_SYS_FSL_ESDHC_NUM	2
 
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
@@ -55,10 +51,7 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_MII
-
 /* USB Configs */
-#define CONFIG_CMD_FAT
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX5
 #define CONFIG_USB_STORAGE
@@ -92,7 +85,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_SUPPORT_RAW_INITRD
 
 #define CONFIG_BOOTDELAY	1
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index f5019c2..9c76678 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -47,9 +47,7 @@
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
 
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
@@ -60,8 +58,6 @@
 #define IMX_FEC_BASE	FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR	0x1F
 
-#define CONFIG_CMD_MII
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index ffd13ca..17b6c48 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -69,14 +69,8 @@
 #define CONFIG_BAUDRATE         115200
 
 /* Filesystems and image support */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_SUPPORT_RAW_INITRD
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
@@ -87,7 +81,6 @@
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
 #endif
 
 /* GPIO */
@@ -95,7 +88,6 @@
 
 /* MMC */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_FSL_ESDHC
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 70760a1..d64323e 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -27,7 +27,6 @@
 
 /* Ethernet Configuration */
 #define CONFIG_FEC_MXC
-#define CONFIG_CMD_MII
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE		RGMII
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 60c07cf..eb89031 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -23,7 +23,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
-#define CONFIG_CMD_MII
 #define	CONFIG_FEC_MXC
 #define	CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index d777666..1ee880d 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -24,7 +24,6 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -232,7 +231,6 @@
 #ifndef CONFIG_SPL
 #define CONFIG_USBD_HS
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 #define CONFIG_USB_FUNCTION_FASTBOOT
@@ -242,7 +240,6 @@
 #define CONFIG_FASTBOOT_BUF_SIZE   0x07000000
 
 /* USB Device Firmware Update support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_DFU_SF
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index cc73684..d53e416 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -45,7 +45,6 @@
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 9617e24..d771f9d 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -148,7 +148,6 @@
 #define CONFIG_APBH_DMA_BURST8
 
 /* Network */
-#define CONFIG_CMD_MII
 
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 71b9fe3..183a759 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -161,7 +161,6 @@
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
 /* Network */
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index fa79d48..15976f7 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -184,11 +184,9 @@
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_BMODE
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
 #endif
 
 #define CONFIG_FSL_QSPI
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index bf6bae6..3c9a794 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -44,12 +44,7 @@
 #define CONFIG_BAUDRATE                 115200
 
 /* Filesystems and image support */
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP
@@ -60,7 +55,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
 #endif
 
 /* GPIO */
@@ -71,7 +65,6 @@
 
 /* MMC */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_FSL_ESDHC
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 5f63a1f..ece8a03 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -27,7 +27,6 @@
 #define CONFIG_CSF_SIZE			0x4000
 
 /* Network */
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define CONFIG_FEC_XCV_TYPE             RGMII
@@ -252,11 +251,9 @@
 
 #define CONFIG_USBD_HS
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 /* USB Device Firmware Update support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_DFU_RAM
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index 96ee7ec..dc8e265 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -44,7 +44,6 @@
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_IDE
@@ -110,9 +109,6 @@
 /*
  * File system
  */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_JFFS2_NAND
 #define CONFIG_JFFS2_LZO
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 9f16da7..b651eb3 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -64,7 +64,6 @@
 #define CONFIG_LIBATA
 #endif
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -320,7 +319,6 @@
 #define CONFIG_PCIE_IMX
 #endif
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 #define CONFIG_USB_FUNCTION_FASTBOOT
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index c6353e0..0fbbce6 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -124,11 +124,6 @@
 #define CONFIG_SYS_NO_FLASH
 
 /* commands to include */
-#define CONFIG_CMD_EXT2			/* EXT2 Support */
-#define CONFIG_CMD_EXT4			/* EXT4 Support */
-#define CONFIG_CMD_FAT			/* FAT support */
-
-#define CONFIG_CMD_MMC			/* MMC support */
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 8b6e93e..cfb92d6 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -19,11 +19,9 @@
 #include "mx6_common.h"
 
 /* U-Boot Commands */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BMODE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SATA
 #define CONFIG_VIDEO
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
index 4510b16..1987164 100644
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -26,9 +26,7 @@
 /* commands configuration */
 #define CONFIG_SYS_NO_FLASH		/* declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_MII
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index 49e5eae..056f518 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -28,7 +28,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 1b06719..16fa046 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -76,8 +76,6 @@
  * Supported commands
  */
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #endif
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 3e2bcec..12b7dc5 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -46,7 +46,6 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTARGS			"Please use defined boot"
 #define CONFIG_BOOTCOMMAND		"run autoboot"
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index e52d7ba..5196d58 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -24,8 +24,6 @@
 
 #define TZPC_BASE_OFFSET		0x10000
 
-#define CONFIG_CMD_MMC
-
 #define CONFIG_NR_DRAM_BANKS	8
 #define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
 /* Reserve the last 22 MiB for the secure firmware */
@@ -50,7 +48,6 @@
 /* DFU */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
-#define CONFIG_CMD_DFU
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_32M
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #define DFU_MANIFEST_POLL_TIMEOUT       25000
@@ -65,7 +62,6 @@
 #define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
 #define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_CMD_USB_MASS_STORAGE
 
 /* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
 #undef CONFIG_EXYNOS_TMU
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index d7e6c37..4dbe2b6 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -87,9 +87,6 @@
 #define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
 
 /* commands to include */
-#define CONFIG_CMD_ASKENV
-
-#define CONFIG_CMD_CACHE
 
 #define MTDIDS_DEFAULT			"nand0=nand"
 #define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 8048ce8..9dbca1c 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -24,13 +24,9 @@
  * Supported U-Boot commands
  * ----------------------------------------------------------------------------
  */
-#define CONFIG_CMD_ASKENV
 
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 
 /* ----------------------------------------------------------------------------
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 99dab5f..01336ff 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -149,7 +149,6 @@
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
 
 #ifdef CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index 23a8a07..a93a2fa 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -19,8 +19,6 @@
  * Supported U-Boot commands
  * ----------------------------------------------------------------------------
  */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 
 /*
  * Board revision is detected by probing the Ethernet chip.
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index cfe7012..5da50a5 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -69,7 +69,6 @@
 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
 #define CONFIG_USBD_PRODUCT_NAME	"IGEP"
 
-#define CONFIG_CMD_CACHE
 #ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_CMD_ONENAND	/* ONENAND support		*/
 #endif
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index ab83714..055dcb7 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -64,9 +64,6 @@
 
 /* commands to include */
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
 
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 5db5dcf..c066eae 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -56,7 +56,6 @@
 #define CONFIG_OMAP3_GPIO_6	/* GPIO160..191 is in GPIO Bank 6 */
 
 /* commands to include */
-#define CONFIG_CMD_CACHE
 
 #ifdef CONFIG_NAND
 #define CONFIG_CMD_UBI		/* UBI-formated MTD partition support */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 803f4b8..380ec12 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -57,7 +57,6 @@
 #define CONFIG_SERIAL3			3
 
 /* commands to include */
-#define CONFIG_CMD_CACHE	/* Cache control		*/
 
 /*
  * Board NAND Info.
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index a794662..86cefa3 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -101,7 +101,6 @@
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
-#define CONFIG_CMD_DFU
 
 #define CONFIG_DFU_MMC
 
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index be93ca3..f3287e3 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -210,16 +210,13 @@
  * U-Boot commands
  */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 #ifdef CONFIG_CMD_BDI
 #define CONFIG_CLOCKS
 #endif
 
 #ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_MII
 #endif
 
 #ifdef CONFIG_USE_NAND
@@ -253,9 +250,6 @@
 
 #ifdef CONFIG_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #undef CONFIG_ENV_IS_IN_MMC
 #endif
 
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
index 6eb7e6e..4defa7e 100644
--- a/include/configs/openrd.h
+++ b/include/configs/openrd.h
@@ -46,8 +46,6 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_IDE
 
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index ffed6c5..dfb8d3a 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -116,8 +116,6 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_BSP
 
-#define CONFIG_CMD_MII
-
 #define CONFIG_LMB
 
 /*
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 4f14357..1fa2f4d 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -50,9 +50,6 @@
 #define S5P_CHECK_DIDLE			0xBAD00000
 #define S5P_CHECK_LPA			0xABAD0000
 
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_SUPPORT_RAW_INITRD
 
 /* MMC SPL */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 9b5c369..891abce 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -88,7 +88,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #endif
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE                    ENET_BASE_ADDR
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index fba61a4..596193d 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -868,7 +868,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_REGINFO
 
@@ -896,14 +895,11 @@
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #endif
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 		 || defined(CONFIG_FSL_SATA)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index bba75ab..f2959c9 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -401,7 +401,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 /*
@@ -424,14 +423,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #endif
 
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 		 || defined(CONFIG_FSL_SATA)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
index c4a5799..e5dcb25 100644
--- a/include/configs/p2371-0000.h
+++ b/include/configs/p2371-0000.h
@@ -25,7 +25,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h
index 3bf3b56..6133d3f 100644
--- a/include/configs/p2371-2180.h
+++ b/include/configs/p2371-2180.h
@@ -25,7 +25,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/p2571.h b/include/configs/p2571.h
index 95d2d63..4c75a26 100644
--- a/include/configs/p2571.h
+++ b/include/configs/p2571.h
@@ -26,7 +26,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index e7b084a..0e65032 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -26,7 +26,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index b1fd2b8..caf75a6 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -168,9 +168,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 
-#undef CONFIG_CMD_FAT
 #undef CONFIG_CMD_IDE
 #undef CONFIG_CMD_BEDBUG
 
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index f503520..0007c50 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -53,7 +53,6 @@ Serial console configuration
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 356cd79..494524d 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -76,12 +76,9 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -258,6 +255,4 @@
 #define CONFIG_ENV_OFFSET_REDUND	0xC0000
 #endif
 
-#define CONFIG_CMD_BOOTZ
-
 #endif
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index ff3f53d..3b6c7dc 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -380,10 +380,8 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #undef CONFIG_CMD_FUSE
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 155f589..1f33bc6 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -163,7 +163,6 @@
 
 #define CONFIG_CMD_MTDPARTS
 
-#define CONFIG_CMD_ASKENV /* monitor functions : ask for env variable */
 #define CONFIG_VERSION_VARIABLE /* monitor functions :  u-boot version */
 #define CONFIG_CMD_DIAG /* monitor functions : Diagnostics */
 
@@ -214,7 +213,6 @@
 #define CONFIG_NET_MULTI
 
 /* Network */
-#define CONFIG_CMD_MII
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET	1
 #define CONFIG_PHY_NATSEMI
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index fccfb48..108c6a2 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -82,8 +82,6 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_ARP_TIMEOUT		500 /* millisec */
 
-#define CONFIG_CMD_MII
-
 /*
  * BOOTP options
  */
@@ -98,7 +96,6 @@
 #define CONFIG_SDHCI
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 
 /*--------------------------------------------------
  * USB Configuration
@@ -115,15 +112,10 @@
 #define CONFIG_SUPPORT_VFAT
 #define CONFIG_FS_FAT
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_PART
-#define CONFIG_CMD_FAT
 
 /* EXT4 FS */
 #define CONFIG_FS_EXT4
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 
 /* -------------------------------------------------
  * Environment
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 118316b..44ffd6d 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -33,8 +33,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
@@ -96,7 +94,6 @@
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -105,7 +102,6 @@
 #endif
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
index 4f78a3d..627e1a7 100644
--- a/include/configs/platinum.h
+++ b/include/configs/platinum.h
@@ -22,7 +22,6 @@
  */
 
 #define CONFIG_CMD_BMODE
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NAND_TRIMFFS
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 0f79472..617f927 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -23,7 +23,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* NAND support */
 #define CONFIG_CMD_NAND
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index dcfc774..39af5c0 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -181,7 +181,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NAND		1
 
 /* SDRAM */
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 92d080e..111e0f5 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -195,7 +195,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NAND		1
 
 /* SDRAM */
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index a6472fb..facba38 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -70,7 +70,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NAND		1
 
 #define CONFIG_CMD_JFFS2		1
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index 731b9de..6393ff3 100644
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -33,7 +33,6 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_SYS_MVFS
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 
 /*
@@ -82,8 +81,6 @@
 /*
  * File system
  */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 1e7f48d..929eede 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -90,7 +90,6 @@
 
 /* SD */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_SH_SDHI_FREQ	97500000
 
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index 7295687..375515e 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -26,8 +26,6 @@
 #define	CONFIG_MMC
 #define	CONFIG_GENERIC_MMC
 #define	CONFIG_PXA_MMC_GENERIC
-#define	CONFIG_CMD_FAT
-#define	CONFIG_CMD_EXT2
 #define	CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 4b0f98b..a7cd003 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -45,8 +45,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_DRIVER_NE2000
 #define CONFIG_DRIVER_NE2000_BASE	0xb4000300
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index b998052..394382c 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -45,8 +45,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_DRIVER_NE2000
 #define CONFIG_DRIVER_NE2000_BASE	0xffffffffb4000300
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 15f906a..73b3771 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -128,7 +128,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 
 #define CONFIG_LBA48
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 
 /*
  * Environment
@@ -142,8 +141,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
 
 #ifdef CONFIG_PCI
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index f19898f..437ea92 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -18,7 +18,6 @@
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
 
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index daf7e22..bf81d2b 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -11,10 +11,8 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_CMD_SH_ZIMAGEBOOT
 
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 8add5f8..6097dc2 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -22,7 +22,6 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_SCIF_CONSOLE	1
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index aa130a1..47d2379 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -36,7 +36,6 @@
 	"led5=63,0,1\0"
 
 #undef CONFIG_DOS_PARTITION
-#undef CONFIG_CMD_FAT
 
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index c814189..337ba02 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -15,12 +15,6 @@
 
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 
 #define CONFIG_SYS_THUMB_BUILD
 
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index a5ab569..1bdcf9d 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -45,22 +45,15 @@
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_SDHCI
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
-#define CONFIG_CMD_CACHE
-
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define SDRAM_BANK_SIZE			(512UL << 20UL)
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index c1ea280..8a81397 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -51,17 +51,12 @@
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_SDHCI
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
@@ -78,8 +73,6 @@
 #define CONFIG_SPL_RAM_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 
-#define CONFIG_CMD_CACHE
-
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_NR_DRAM_BANKS		1
 #define SDRAM_BANK_SIZE			(2UL << 30)
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 0fd040f..af58182 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -144,7 +144,6 @@
 #define CONFIG_COMMAND_HISTORY
 
 /* Commands */
-#define CONFIG_CMD_MMC
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index c7ef864..1e4166c 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -15,7 +15,6 @@
 #define CONFIG_RSK7203	1
 
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_CACHE
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 916895a..afea884 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -62,11 +62,8 @@
 
 #define CONFIG_SYS_NO_FLASH		1
 
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
 #define CONFIG_CMD_GPT
 
 /* USB Composite download gadget - g_dnl */
@@ -231,10 +228,6 @@
 
 #define CONFIG_DOS_PARTITION		1
 
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-
 /* write support for filesystems */
 #define CONFIG_FAT_WRITE
 #define CONFIG_EXT4_WRITE
@@ -267,7 +260,6 @@
 
 #define CONFIG_SYS_MAX_I2C_BUS	7
 #define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index bdb39a3..f9a8f6f 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -51,7 +51,6 @@
 #undef CONFIG_CMD_NAND
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -78,7 +77,6 @@
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2 XPlained"
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index ee3e34d..55615ea 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -77,11 +77,9 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_MACB_SEARCH_PHY
 #define CONFIG_RGMII
-#define CONFIG_CMD_MII
 #define CONFIG_PHYLIB
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -105,10 +103,7 @@
 #endif
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 #endif
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index c4ad3c4..1e721a9 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -108,13 +108,11 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_MACB_SEARCH_PHY
 #define CONFIG_RGMII
-#define CONFIG_CMD_MII
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -143,7 +141,6 @@
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 #endif
 
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index a81766a..8d141a9 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -62,7 +62,6 @@
 #endif
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -86,7 +85,6 @@
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D4EK"
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 339fcf1..4b19080 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -62,7 +62,6 @@
 #endif
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
@@ -86,7 +85,6 @@
 #define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D4EK"
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 0bdb73a..9790a14 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -39,15 +39,11 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_FS_EXT4
 #define CONFIG_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_CBFS
 #define CONFIG_CMD_CRAMFS
 #define CONFIG_CMD_PART
 #define CONFIG_DOS_PARTITION
 #define CONFIG_HOST_MAX_DEVICES 4
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MD5SUM
 
 #define CONFIG_CMD_GPT
@@ -138,8 +134,6 @@
 
 #define CONFIG_CMD_ENV_FLAGS
 #define CONFIG_CMD_ENV_CALLBACK
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_ASKENV
 
 #define CONFIG_BOOTARGS ""
 
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index f6e07b4..0c8ecc1 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -14,10 +14,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #define CONFIG_VIDEO
 
 /* Memory configuration */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index fc22134..6c0932a 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -406,7 +406,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 19601e7..bbd1a63 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -523,7 +523,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 9ec8417..42237d3 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -19,12 +19,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-
 /* Memory configuration */
 #define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 54aeb5b..4c01966 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -35,7 +35,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
index e1c0e9a..51b88a4 100644
--- a/include/configs/secomx6quq7.h
+++ b/include/configs/secomx6quq7.h
@@ -32,7 +32,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
 /* Ethernet Configuration */
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 7ca7afa..d34811f 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -230,7 +230,6 @@
  */
 #define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index 58f9540..80997a4 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -16,13 +16,10 @@
 #define CONFIG_SYS_TEXT_BASE	0x5ff80000
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7752evb/u-boot.lds"
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 540d36c..248435b 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -16,13 +16,10 @@
 #define CONFIG_SYS_TEXT_BASE	0x5ff80000
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7753evb/u-boot.lds"
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 298d3a2..547b500 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -17,12 +17,9 @@
 #define CONFIG_SYS_TEXT_BASE	0x8ef80000
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7757lcr/u-boot.lds"
 
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 9f6fe0e..9f1e6d7 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -18,7 +18,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_JFFS2
 
 #define CONFIG_BOOTDELAY        -1
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 1d7fced..bd4c6bd 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -18,8 +18,6 @@
 #define CONFIG_CMD_SH_ZIMAGEBOOT
 
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 2019156..fa76a25 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -24,7 +24,6 @@
 /*
  * Commands configuration
  */
-#define CONFIG_CMD_MMC
 
 /*
  * Standard filesystems
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index aecd06f..dfc928d 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -39,8 +39,6 @@
 #define CONFIG_SYS_CACHELINE_SIZE       64
 
 /* commands to include */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #ifndef CONFIG_SPL_BUILD
@@ -85,10 +83,7 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_SPI
 #define CONFIG_OMAP3_SPI
@@ -239,7 +234,6 @@
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
-#define CONFIG_CMD_DFU
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(1 << 20)
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
@@ -272,7 +266,6 @@
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
-#define CONFIG_CMD_MII
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_DNS2
diff --git a/include/configs/silk.h b/include/configs/silk.h
index a3790f0..dca0623 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -91,7 +91,6 @@
 /* MMCIF */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_SH_MMCIF
 #define CONFIG_SH_MMCIF_ADDR	0xee200000
 #define CONFIG_SH_MMCIF_CLK	48000000
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 4daab98..40b0cd2 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -169,7 +169,6 @@
 #define CONFIG_USB_GADGET_AT91
 
 /* DFU class support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
@@ -215,7 +214,6 @@
 /* Command line & features configuration */
 
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_FAT
 
 #ifdef CONFIG_MACB
 #else
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index f009343..c5c0c2c 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -73,7 +73,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_BSP
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_REGINFO
@@ -170,8 +169,6 @@
 /*
  * File system
  */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_MTDPARTS
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index e1c7c67..0f1a1ec 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -67,10 +67,8 @@
  ***********************************************************/
 #undef CONFIG_CMD_NAND
 
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_MTDPARTS
 
 #define CONFIG_BOOTDELAY	3
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 0c21deb..efb18ff 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -14,10 +14,8 @@
 #undef CONFIG_BOARD_COMMON
 #undef CONFIG_USB_GADGET_DWC2_OTG
 #undef CONFIG_USB_GADGET_DWC2_OTG_PHY
-#undef CONFIG_CMD_USB_MASS_STORAGE
 #undef CONFIG_REVISION_TAG
 #undef CONFIG_CMD_THOR_DOWNLOAD
-#undef CONFIG_CMD_DFU
 
 /* High Level Configuration Options */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index bff49b1..16aefc2 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -145,8 +145,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
 
 /* Command line configuration */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index eb53a21..fb348a5 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -102,8 +102,6 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
 
-#define CONFIG_CMD_MMC
-
 /*
  * Power
  */
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 6cdf38b..ca7f8a2 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -14,19 +14,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB_MASS_STORAGE
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index bf75e0f..a2da7d4 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -14,19 +14,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB_MASS_STORAGE
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 90592a8..fdddfa3 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -14,19 +14,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB_MASS_STORAGE
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
 
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index f1cfe21..f0fb43a 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -14,19 +14,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB_MASS_STORAGE
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on MCV */
 
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 7ac5889..675f5d1 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -14,19 +14,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB_MASS_STORAGE
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index e2ed253..79c16ce 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -14,19 +14,6 @@
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB_MASS_STORAGE
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCrates */
 
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index fb98546..efa9e42 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -16,18 +16,6 @@
 
 #define CONFIG_HW_WATCHDOG
 
-/* U-Boot Commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
 
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index cf1e904..4ed524b 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -308,9 +308,7 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 269ce7e..c4b6234 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -101,7 +101,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MII
 
 /*
  * Default Environment Varible definitions
diff --git a/include/configs/stout.h b/include/configs/stout.h
index 70fedf1..d21c3cb 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -94,7 +94,6 @@
 
 /* MMC */
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 
 /* Module stop status bits */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index a5b2223..5803b66 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -35,10 +35,8 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_SYS_ALT_MEMTEST
 
@@ -506,7 +504,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index bd16ff9..2406115 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -140,7 +140,6 @@
 /* mmc config */
 #ifdef CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_MMC_SUNXI
 #define CONFIG_MMC_SUNXI_SLOT		0
 #define CONFIG_ENV_IS_IN_MMC
@@ -347,7 +346,6 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_USB_FUNCTION_DFU
-#define CONFIG_CMD_DFU
 #define CONFIG_DFU_RAM
 #endif
 
@@ -366,7 +364,6 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_CMD_USB_MASS_STORAGE
 #endif
 
 #ifdef CONFIG_USB_KEYBOARD
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index f77e63c..af61f21 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -237,7 +237,6 @@
 #define CONFIG_LBA48
 #define CONFIG_CMD_SATA
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -256,9 +255,7 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index ef9e22e..efdc706 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -96,11 +96,6 @@
 #define CONFIG_USB_STORAGE
 
 /* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_EEPROM
 
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 38f3446..4d66dd2 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -92,9 +92,6 @@
 #define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
 
 /* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
 #define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define MTDIDS_DEFAULT			"nand0=nand"
@@ -102,7 +99,6 @@
 					"1920k(u-boot),128k(u-boot-env),"\
 					"4m(kernel),-(fs)"
 
-#define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 946bfd4..321fb47 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -49,8 +49,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_CMD_BOOTZ
-
 /* general purpose I/O */
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 #define CONFIG_AT91_GPIO
@@ -131,7 +129,6 @@
 #define CONFIG_USB_GADGET_AT91
 
 /* DFU class support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index bd4d98e..ec0bf05 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -67,7 +67,6 @@
 
 /* Ethernet */
 #define CONFIG_FEC_MXC
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -121,7 +120,6 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_USB_MASS_STORAGE
 #ifdef CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USBD_HS
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
index d131c17..d7f1a7c 100644
--- a/include/configs/tec-ng.h
+++ b/include/configs/tec-ng.h
@@ -24,7 +24,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 976f9c1..a90af06 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -23,7 +23,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* NAND support */
 #define CONFIG_CMD_NAND
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index a1daf8c..b206ce4 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -125,7 +125,6 @@
 #undef CONFIG_TEGRA_MMC
 #endif
 #ifdef CONFIG_CMD_MMC
-#undef CONFIG_CMD_MMC
 #endif
 
 /* remove partitions/filesystems */
@@ -135,18 +134,6 @@
 #ifdef CONFIG_EFI_PARTITION
 #undef CONFIG_EFI_PARTITION
 #endif
-#ifdef CONFIG_CMD_FS_GENERIC
-#undef CONFIG_CMD_FS_GENERIC
-#endif
-#ifdef CONFIG_CMD_EXT4
-#undef CONFIG_CMD_EXT4
-#endif
-#ifdef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_EXT2
-#endif
-#ifdef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FAT
-#endif
 #ifdef CONFIG_FS_EXT4
 #undef CONFIG_FS_EXT4
 #endif
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index 18851ca..3e3eeea 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -13,12 +13,10 @@
 #define CONFIG_CI_UDC_HAS_HOSTPC
 /* USB mass storage protocol */
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_CMD_USB_MASS_STORAGE
 /* DFU protocol */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
 #define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M
-#define CONFIG_CMD_DFU
 #ifdef CONFIG_MMC
 #define CONFIG_DFU_MMC
 #endif
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index b07ee56..92d4dd8 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -137,7 +137,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
-#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_FAT_WRITE
 #endif
 
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index a5a7fae..1caa858 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -23,13 +23,7 @@
 /*
  * Commands configuration
  */
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_SATA
 
 /*
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index 077422f..5fed55d 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -29,7 +29,6 @@
 	"led1=64,0,1\0"
 
 #undef CONFIG_DOS_PARTITION
-#undef CONFIG_CMD_FAT
 
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 4dfbd82..09f8e8f 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -37,7 +37,6 @@
 #define CONFIG_INITRD_TAG		/* for ramdisk support */
 
 /* commands to include */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_VERSION_VARIABLE
 
 #define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
@@ -122,10 +121,7 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 /**
  * Physical Memory Map
@@ -210,7 +206,6 @@
 #undef CONFIG_USE_IRQ
 
 /* Ethernet */
-#define CONFIG_CMD_MII
 #define CONFIG_DRIVER_TI_CPSW
 #define CONFIG_MII
 #define CONFIG_BOOTP_DNS
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 83b745a..2e84dd2 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -62,10 +62,7 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 
 #define CONFIG_FS_FAT
 
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 049b92a..bcd56fc 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -30,7 +30,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 /* Network defines. */
-#define CONFIG_CMD_MII
 #define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 6d77e78..7db0881 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -115,7 +115,6 @@
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_MMC
 
 /* McSPI IP block */
 #define CONFIG_SPI
@@ -168,8 +167,6 @@
 #define CONFIG_CMD_MTDPARTS
 #endif
 
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_SUPPORT_RAW_INITRD
 
 /*
@@ -178,11 +175,7 @@
  */
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 #endif
@@ -302,6 +295,5 @@
 #endif
 
 #include <config_distro_defaults.h>
-#define CONFIG_CMD_EXT4_WRITE
 
 #endif	/* __CONFIG_TI_ARMV7_COMMON_H__ */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index ceebffb..2c9028c 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -314,7 +314,6 @@
 #undef CONFIG_SPL_EXT_SUPPORT
 #undef CONFIG_MMC
 #undef CONFIG_GENERIC_MMC
-#undef CONFIG_CMD_MMC
 
 /* And no support for GPIO, yet.. */
 #undef CONFIG_SPL_GPIO_SUPPORT
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index 94b2f27..c6ba017 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 439a4fd..badb955 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -97,8 +97,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 
-#define CONFIG_CMD_MII
-
 #define CONFIG_FEC_MXC
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_PHYLIB
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 2514e88..855d789 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -146,9 +146,6 @@
 #define CONFIG_SYS_NAND_MAX_ECCPOS	56
 
 /* commands to include */
-#define CONFIG_CMD_EXT2			/* EXT2 Support */
-#define CONFIG_CMD_FAT			/* FAT support */
-#define CONFIG_CMD_MMC			/* MMC support */
 #define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands */
 #define CONFIG_CMD_NAND			/* NAND support */
 #define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index b763eec..b761640 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -31,7 +31,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in SPI */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 7dc7443..aa0605f 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -64,9 +64,7 @@
 
 #define CONFIG_MMC
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /*
@@ -81,8 +79,6 @@
 #define CONFIG_ETHPRIME		"FEC"
 #define CONFIG_FEC_MXC_PHYADDR	0
 
-#define CONFIG_CMD_MII
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE		/* disable vendor parameters protection (serial#, ethaddr) */
 #define CONFIG_CONS_INDEX		1 /* use UART0 : used by serial driver */
@@ -92,8 +88,6 @@
  * Command definition
  ***********************************************************/
 
-#define CONFIG_CMD_BOOTZ
-
 /* Environment variables */
 
 #define CONFIG_BOOTDELAY	1
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index e73bc83..b6a1ae0 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -46,7 +46,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-#define CONFIG_CMD_BOOTZ
 /*#define CONFIG_MACH_TYPE		3589*/
 #define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/
 
@@ -55,7 +54,6 @@
  #define CONFIG_MMC
  #define CONFIG_GENERIC_MMC
  #define CONFIG_OMAP_HSMMC
- #define CONFIG_CMD_MMC
  #define CONFIG_SUPPORT_EMMC_BOOT
 /* RAW SD card / eMMC locations. */
  #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
@@ -299,13 +297,9 @@ MMCARGS
  */
 #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
 #define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 #define CONFIG_FS_EXT4
 #define CONFIG_EXT4_WRITE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FS_GENERIC
 #endif /* CONFIG_MMC, ... */
 
 #endif	/* ! __CONFIG_TSERIES_H__ */
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 4437700..fba78d0 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -41,7 +41,6 @@
 
 /* Network support */
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE                    ENET_BASE_ADDR
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 8ecfc6f..18cb963 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -133,12 +133,10 @@
 /* USB */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
-#define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 #define CONFIG_DOS_PARTITION
 
 /* SD/MMC */
-#define CONFIG_CMD_MMC
 #define CONFIG_SUPPORT_EMMC_BOOT
 #define CONFIG_GENERIC_MMC
 
@@ -193,7 +191,6 @@
 #define KERNEL_SIZE			"kernel_size=0x00c00000\0"
 #define RAMDISK_ADDR			"ramdisk_addr=0x00e00000\0"
 #else
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_BOOTFILE			"zImage"
 #define LINUXBOOT_CMD			"bootz"
 #define KERNEL_ADDR_R			"kernel_addr_r=0x80208000\0"
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 2202d98..d118928 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -113,7 +113,6 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
 #endif
 
 #define CONFIG_SYS_LOAD_ADDR			0x22000000
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index d23674c..8568663 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -45,7 +45,6 @@
 #define CONFIG_BAUDRATE		115200
 
 /* SD/MMC */
-#define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_ESDHC_NUM	1
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index c8cc842..9a113f4 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -84,15 +84,12 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_FAT
 
 #define CONFIG_TIMESTAMP		/* Print image info with timestamp */
 
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 679cd74..6489e08 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -97,7 +97,6 @@
  */
 #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
 	!defined(CONFIG_VCT_SMALL_IMAGE)
-#define CONFIG_CMD_FAT
 #endif
 
 #if defined(CONFIG_CMD_USB)
@@ -276,15 +275,11 @@ int vct_gpio_get(int pin);
  * (NOR/OneNAND) usage and Linux kernel booting.
  */
 #if defined(CONFIG_VCT_SMALL_IMAGE)
-#undef CONFIG_CMD_ASKENV
 #undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_CACHE
 #undef CONFIG_CMD_EEPROM
 #undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_FAT
 #undef CONFIG_CMD_IRQ
 #undef CONFIG_CMD_LOADY
-#undef CONFIG_CMD_MII
 #undef CONFIG_CMD_REGINFO
 #undef CONFIG_CMD_STRINGS
 #undef CONFIG_CMD_TERMINAL
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 59bf2b3..2425ebf 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -320,7 +320,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 #define CONFIG_CMDLINE_EDITING 1
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index f413f40..1d24437 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -26,7 +26,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 5c2fe9b..cdf50e3 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -24,7 +24,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index a7e1195..1b5fc2e 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -134,13 +134,10 @@
 /* Command line configuration */
 #define CONFIG_MENU
 /*#define CONFIG_MENU_SHOW*/
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_BOOTI
 #define CONFIG_CMD_UNZIP
 #define CONFIG_CMD_PXE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 /* BOOTP options */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 67379fd..6dc8f25 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -153,7 +153,6 @@
 #define CONFIG_SYS_SERIAL1		V2M_UART1
 
 #define CONFIG_MMC			1
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_ARM_PL180_MMCI
 #define CONFIG_ARM_PL180_MMCI_BASE	V2M_MMCI
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index d8c45de..b240613 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -77,12 +77,9 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -267,6 +264,4 @@
 #define CONFIG_ENV_OFFSET		0x180000
 #endif
 
-#define CONFIG_CMD_BOOTZ
-
 #endif
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index b0737e7..35fe9de 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -54,7 +54,6 @@
 #endif
 
 /* MMC */
-#define CONFIG_CMD_MMC
 
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_SUPPORT_EMMC_BOOT
@@ -87,12 +86,10 @@
 #define CONFIG_USBNET_MANUFACTURER      "L+G VInCo"
 
 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
 /* Ethernet Hardware */
-#define CONFIG_CMD_MII
 #define CONFIG_PHY_SMSC
 #define CONFIG_MACB
 #define CONFIG_RMII
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index f9e6a8d..732d091 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -347,7 +347,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 #define CONFIG_SYS_I2C_RTC_ADDR	0x32
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 7898a81..99f5c0c 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -55,7 +55,6 @@
 #define CONFIG_MXC_USB_FLAGS		0
 
 /* Ethernet Configuration */
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 42b728a..4a8e270 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -75,10 +75,8 @@
 
 #define CONFIG_USBD_HS
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 8c72178..4dfcd28 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -133,7 +133,6 @@
 #define CONFIG_USB_GADGET_DUALSPEED
 
 #define CONFIG_USB_GADGET
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
@@ -143,7 +142,6 @@
 #define CONFIG_G_DNL_MANUFACTURER	"FSL"
 
 /* USB Device Firmware Update support */
-#define CONFIG_CMD_DFU
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index a5cd38b..9c194d5 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -28,7 +28,6 @@
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
 
 /*
  * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index af6cbe4..a4ae304 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -89,15 +89,9 @@
 #define CONFIG_BOOTP_DNS
 
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
 
-#define CONFIG_CMD_MII
-
-#define CONFIG_CMD_MMC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 
 #define CONFIG_MXC_GPIO
 
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index c59688c..b81b6ff 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -63,7 +63,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR 0
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_CMD_MII
 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
 
 /*
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 265d710..d7da0b2 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -109,13 +109,9 @@
 /*
  * Command support defines
  */
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_SAVES
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index c72ae72..a2822e0 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -84,8 +84,6 @@
 #ifdef CONFIG_SYS_COREBOOT
 #define CONFIG_CMD_CBFS
 #endif
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_PARTITION_UUIDS
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
@@ -97,7 +95,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_FPGA_LOADMK
 #define CONFIG_CMD_IO
 #define CONFIG_CMD_IRQ
@@ -105,9 +102,6 @@
 #define CONFIG_CMD_GETTIME
 #define CONFIG_CMD_SCSI
 
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
 #define CONFIG_CMD_ZBOOT
 
 #define CONFIG_BOOTARGS		\
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 8d5ea48..4d68c21 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -14,10 +14,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
 #define CONFIG_VIDEO
 
 /* Memory configuration */
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index 3ab8eab..067cfa6 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -24,8 +24,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
 
 /*Cmd*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index be43aa6..fe9c719 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -63,16 +63,10 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 #define CONFIG_MP
 
-#define CONFIG_CMD_MII
-
 /* BOOTP options */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
@@ -89,7 +83,6 @@
 # define CONFIG_MMC
 # define CONFIG_GENERIC_MMC
 # define CONFIG_SDHCI
-# define CONFIG_CMD_MMC
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ	200000000
 # endif
@@ -97,7 +90,6 @@
 
 #if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB)
 # define CONFIG_FAT_WRITE
-# define CONFIG_CMD_EXT4_WRITE
 #endif
 
 #ifdef CONFIG_NAND_ARASAN
@@ -125,7 +117,6 @@
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
 #define CONFIG_USB_CABLE_CHECK
-#define CONFIG_CMD_DFU
 #define CONFIG_CMD_THOR_DOWNLOAD
 #define CONFIG_USB_FUNCTION_THOR
 #define CONFIG_THOR_RESET_OFF
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index f707f57..9838fbf 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -180,12 +180,10 @@ extern void out32(unsigned int, unsigned long);
 /*
  * Command configuration
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_PCI
 
 /*
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index d7e696e..af02efb 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -511,7 +511,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Command configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DS4510_INFO
@@ -519,7 +518,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index 09f0c3f..d1847ac 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -297,11 +297,9 @@
 /*
  * Command configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 1946bb9..a1c5826 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -366,14 +366,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Command configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DS4510
 #define CONFIG_CMD_DS4510_INFO
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 3aa21eb..02685ca 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -352,12 +352,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Command configuration.
  */
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 9a0aac5..4625daf 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -75,9 +75,7 @@
 #define CONFIG_SYS_MMC_ENV_PART		1	/* boot parition */
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC2 */
 
-#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_BMODE
-#define CONFIG_CMD_CACHE
 
 /* USB Configs */
 #define CONFIG_USB_EHCI
@@ -90,7 +88,6 @@
 
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
-#define CONFIG_CMD_MII
 #define CONFIG_FEC_ENET_DEV		0
 #define IMX_FEC_BASE			ENET_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR          0x0
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 37f7a07..03cad10 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -193,8 +193,6 @@
 #define CONFIG_CMD_PCI
 
 #ifdef CONFIG_440EP
-    #define CONFIG_CMD_FAT
-    #define CONFIG_CMD_EXT2
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 81de228..fcd7772 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -59,8 +59,6 @@
  * Bootloader Components Configuration
  */
 #define	CONFIG_CMD_ENV
-#define	CONFIG_CMD_MMC
-#define	CONFIG_CMD_CACHE
 
 /*
  * MMC Card Configuration
@@ -70,8 +68,6 @@
 #define	CONFIG_GENERIC_MMC
 #define	CONFIG_PXA_MMC_GENERIC
 #define	CONFIG_SYS_MMC_BASE		0xF0000000
-#define	CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define	CONFIG_DOS_PARTITION
 #endif
 
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 72c6c0a..264bb63 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -75,12 +75,10 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_CACHE
 
 /*
  * Additional command
  */
-#define CONFIG_CMD_FAT
 
 /*
  * USB
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 4f49ba8..a3e4aec 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -16,7 +16,6 @@
 #endif
 
 /* Cache options */
-#define CONFIG_CMD_CACHE
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_SYS_L2CACHE_OFF
@@ -84,7 +83,6 @@
 # define CONFIG_MMC
 # define CONFIG_GENERIC_MMC
 # define CONFIG_SDHCI
-# define CONFIG_CMD_MMC
 # define CONFIG_ZYNQ_SDHCI_MAX_FREQ	52000000
 #endif
 
@@ -100,7 +98,6 @@
 # define CONFIG_USB_FUNCTION_DFU
 # define CONFIG_DFU_RAM
 # define CONFIG_USB_CABLE_CHECK
-# define CONFIG_CMD_DFU
 # define CONFIG_CMD_THOR_DOWNLOAD
 # define CONFIG_THOR_RESET_OFF
 # define CONFIG_USB_FUNCTION_THOR
@@ -139,13 +136,8 @@
 
 #if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
 # define CONFIG_SUPPORT_VFAT
-# define CONFIG_CMD_FAT
-# define CONFIG_CMD_EXT2
 # define CONFIG_FAT_WRITE
 # define CONFIG_DOS_PARTITION
-# define CONFIG_CMD_EXT4
-# define CONFIG_CMD_EXT4_WRITE
-# define CONFIG_CMD_FS_GENERIC
 #endif
 
 #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
@@ -303,7 +295,6 @@
 #define CONFIG_SYS_LDSCRIPT  "arch/arm/mach-zynq/u-boot.lds"
 
 /* Commands */
-#define CONFIG_CMD_MII
 
 /* SPL part */
 #define CONFIG_CMD_SPL
-- 
cgit v0.10.2


From ef5ebe951bec72631cdbc7cef9079e6c684e5d0b Mon Sep 17 00:00:00 2001
From: Semen Protsenko <semen.protsenko@linaro.org>
Date: Wed, 20 Apr 2016 12:05:59 +0300
Subject: ti_armv7_common.h: Fix U-Boot location on eMMC

According to common eMMC partition table for Android boot (see
PARTS_DEFAULT definition in include/configs/dra7xx_evm.h), "bootloader"
partition (where u-boot.img is stored) starts at 256 KiB. Which is equal
to 512 sectors (as 1 MMC sector size is 512 bytes).

This patch fixes CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR constant so that
it points to correct address of "bootloader" partition and SPL is able to
read, parse and run u-boot.img correctly.

This change was originally done as part of patch [1] in omapzoom u-boot.
Without this patch, SPL fails to parse U-Boot header with next error:

    mkimage signature not found - ih_magic = 4814325a

While at it, also fix U-Boot partition size, which is 384 KiB (as stated in
include/configs/dra7xx_evm.h).

[1] http://omapzoom.org/?p=repo/u-boot.git;a=commit;h=742b82d0c0aa0ed8096c2225a00e9f350212efa9

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 7db0881..2c7d542 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -219,8 +219,8 @@
 #endif
 
 /* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200	/* address 0x40000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300	/* 384 KB */
 
 /* FAT sd card locations. */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-- 
cgit v0.10.2


From 11b9a4d8d96674a57ff61ce622b0900ebee1392d Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 4 Apr 2016 11:03:52 -0600
Subject: sf: fix timebase data type in _wait_ready()

get_timer() returns an unsigned 64-bit value, but is currently assigned to
a signed 32-bit variable. Due to sign extension and data truncation, this
causes the timeout loop in spi_flash_cmd_wait_ready() to immediately (and
incorrectly) fire for about 50% of all time values, based on whether bit
31 is set. In sandbox at least, this causes the test to pass or fail based
on system uptime, as opposed to time since the U-Boot binary was started.

Fixes: 4efad20a1751 ("sf: Update status reg check in spi_flash_cmd_wait_ready")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 44d9e9b..5451725 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -265,7 +265,8 @@ static int spi_flash_ready(struct spi_flash *flash)
 static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
 					unsigned long timeout)
 {
-	int timebase, ret;
+	unsigned long timebase;
+	int ret;
 
 	timebase = get_timer(0);
 
-- 
cgit v0.10.2


From 9122109ad75ebf7ac2380ddd5d49b981899c9a67 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:13:57 +0100
Subject: ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.

Import the upstream kernel dts into U-Boot. Currently
only serial is supported, but a lot more DT changes are
queued for v4.7.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/hi6220-hikey.dts b/arch/arm/dts/hi6220-hikey.dts
new file mode 100644
index 0000000..8185251
--- /dev/null
+++ b/arch/arm/dts/hi6220-hikey.dts
@@ -0,0 +1,41 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e00000 0x00100000;
+
+#include "hi6220.dtsi"
+
+/ {
+	model = "HiKey Development Board";
+	compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+	aliases {
+		serial0 = &uart0; /* On board UART0 */
+		serial1 = &uart1; /* BT UART */
+		serial2 = &uart2; /* LS Expansion UART0 */
+		serial3 = &uart3; /* LS Expansion UART1 */
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&uart2 {
+	label = "LS-UART0";
+};
+&uart3 {
+	label = "LS-UART1";
+};
diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi
new file mode 100644
index 0000000..ad1f1eb
--- /dev/null
+++ b/arch/arm/dts/hi6220.dtsi
@@ -0,0 +1,213 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi6220-clock.h>
+
+/ {
+	compatible = "hisilicon,hi6220";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@100 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@101 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@102 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x102>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@103 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x103>;
+			enable-method = "psci";
+		};
+	};
+
+	gic: interrupt-controller@f6801000 {
+		compatible = "arm,gic-400";
+		reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
+		      <0x0 0xf6802000 0 0x2000>, /* GICC */
+		      <0x0 0xf6804000 0 0x2000>, /* GICH */
+		      <0x0 0xf6806000 0 0x2000>; /* GICV */
+		#address-cells = <0>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ao_ctrl: ao_ctrl@f7800000 {
+			compatible = "hisilicon,hi6220-aoctrl", "syscon";
+			reg = <0x0 0xf7800000 0x0 0x2000>;
+			#clock-cells = <1>;
+		};
+
+		sys_ctrl: sys_ctrl@f7030000 {
+			compatible = "hisilicon,hi6220-sysctrl", "syscon";
+			reg = <0x0 0xf7030000 0x0 0x2000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		media_ctrl: media_ctrl@f4410000 {
+			compatible = "hisilicon,hi6220-mediactrl", "syscon";
+			reg = <0x0 0xf4410000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		pm_ctrl: pm_ctrl@f7032000 {
+			compatible = "hisilicon,hi6220-pmctrl", "syscon";
+			reg = <0x0 0xf7032000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		uart0: uart@f8015000 {	/* console */
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf8015000 0x0 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
+				 <&ao_ctrl HI6220_UART0_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		uart1: uart@f7111000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7111000 0x0 0x1000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
+				 <&sys_ctrl HI6220_UART1_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: uart@f7112000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7112000 0x0 0x1000>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
+				 <&sys_ctrl HI6220_UART2_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: uart@f7113000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7113000 0x0 0x1000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
+				 <&sys_ctrl HI6220_UART3_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		uart4: uart@f7114000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7114000 0x0 0x1000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
+				 <&sys_ctrl HI6220_UART4_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
new file mode 100644
index 0000000..70ee383
--- /dev/null
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK	0
+
+/* fixed rate clocks */
+#define HI6220_REF32K		1
+#define HI6220_CLK_TCXO		2
+#define HI6220_MMC1_PAD		3
+#define HI6220_MMC2_PAD		4
+#define HI6220_MMC0_PAD		5
+#define HI6220_PLL_BBP		6
+#define HI6220_PLL_GPU		7
+#define HI6220_PLL1_DDR		8
+#define HI6220_PLL_SYS		9
+#define HI6220_PLL_SYS_MEDIA	10
+#define HI6220_DDR_SRC		11
+#define HI6220_PLL_MEDIA	12
+#define HI6220_PLL_DDR		13
+
+/* fixed factor clocks */
+#define HI6220_300M		14
+#define HI6220_150M		15
+#define HI6220_PICOPHY_SRC	16
+#define HI6220_MMC0_SRC_SEL	17
+#define HI6220_MMC1_SRC_SEL	18
+#define HI6220_MMC2_SRC_SEL	19
+#define HI6220_VPU_CODEC	20
+#define HI6220_MMC0_SMP		21
+#define HI6220_MMC1_SMP		22
+#define HI6220_MMC2_SMP		23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK	24
+#define HI6220_WDT1_PCLK	25
+#define HI6220_WDT2_PCLK	26
+#define HI6220_TIMER0_PCLK	27
+#define HI6220_TIMER1_PCLK	28
+#define HI6220_TIMER2_PCLK	29
+#define HI6220_TIMER3_PCLK	30
+#define HI6220_TIMER4_PCLK	31
+#define HI6220_TIMER5_PCLK	32
+#define HI6220_TIMER6_PCLK	33
+#define HI6220_TIMER7_PCLK	34
+#define HI6220_TIMER8_PCLK	35
+#define HI6220_UART0_PCLK	36
+
+#define HI6220_AO_NR_CLKS	37
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK		1
+#define HI6220_MMC0_CIUCLK	2
+#define HI6220_MMC1_CLK		3
+#define HI6220_MMC1_CIUCLK	4
+#define HI6220_MMC2_CLK		5
+#define HI6220_MMC2_CIUCLK	6
+#define HI6220_USBOTG_HCLK	7
+#define HI6220_CLK_PICOPHY	8
+#define HI6220_HIFI		9
+#define HI6220_DACODEC_PCLK	10
+#define HI6220_EDMAC_ACLK	11
+#define HI6220_CS_ATB		12
+#define HI6220_I2C0_CLK		13
+#define HI6220_I2C1_CLK		14
+#define HI6220_I2C2_CLK		15
+#define HI6220_I2C3_CLK		16
+#define HI6220_UART1_PCLK	17
+#define HI6220_UART2_PCLK	18
+#define HI6220_UART3_PCLK	19
+#define HI6220_UART4_PCLK	20
+#define HI6220_SPI_CLK		21
+#define HI6220_TSENSOR_CLK	22
+#define HI6220_MMU_CLK		23
+#define HI6220_HIFI_SEL		24
+#define HI6220_MMC0_SYSPLL	25
+#define HI6220_MMC1_SYSPLL	26
+#define HI6220_MMC2_SYSPLL	27
+#define HI6220_MMC0_SEL		28
+#define HI6220_MMC1_SEL		29
+#define HI6220_BBPPLL_SEL	30
+#define HI6220_MEDIA_PLL_SRC	31
+#define HI6220_MMC2_SEL		32
+#define HI6220_CS_ATB_SYSPLL	33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC		34
+#define HI6220_MMC0_SMP_IN	35
+#define HI6220_MMC1_SRC		36
+#define HI6220_MMC1_SMP_IN	37
+#define HI6220_MMC2_SRC		38
+#define HI6220_MMC2_SMP_IN	39
+#define HI6220_HIFI_SRC		40
+#define HI6220_UART1_SRC	41
+#define HI6220_UART2_SRC	42
+#define HI6220_UART3_SRC	43
+#define HI6220_UART4_SRC	44
+#define HI6220_MMC0_MUX0	45
+#define HI6220_MMC1_MUX0	46
+#define HI6220_MMC2_MUX0	47
+#define HI6220_MMC0_MUX1	48
+#define HI6220_MMC1_MUX1	49
+#define HI6220_MMC2_MUX1	50
+
+/* divider clocks */
+#define HI6220_CLK_BUS		51
+#define HI6220_MMC0_DIV		52
+#define HI6220_MMC1_DIV		53
+#define HI6220_MMC2_DIV		54
+#define HI6220_HIFI_DIV		55
+#define HI6220_BBPPLL0_DIV	56
+#define HI6220_CS_DAPB		57
+#define HI6220_CS_ATB_DIV	58
+
+#define HI6220_SYS_NR_CLKS	59
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK		1
+#define HI6220_G3D_PCLK		2
+#define HI6220_ACLK_CODEC_VPU	3
+#define HI6220_ISP_SCLK		4
+#define HI6220_ADE_CORE		5
+#define HI6220_MED_MMU		6
+#define HI6220_CFG_CSI4PHY	7
+#define HI6220_CFG_CSI2PHY	8
+#define HI6220_ISP_SCLK_GATE	9
+#define HI6220_ISP_SCLK_GATE1	10
+#define HI6220_ADE_CORE_GATE	11
+#define HI6220_CODEC_VPU_GATE	12
+#define HI6220_MED_SYSPLL	13
+
+/* mux clocks */
+#define HI6220_1440_1200	14
+#define HI6220_1000_1200	15
+#define HI6220_1000_1440	16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG	17
+#define HI6220_ISP_SCLK_SRC	18
+#define HI6220_ISP_SCLK1	19
+#define HI6220_ADE_CORE_SRC	20
+#define HI6220_ADE_PIX_SRC	21
+#define HI6220_G3D_CLK		22
+#define HI6220_CODEC_VPU_SRC	23
+
+#define HI6220_MEDIA_NR_CLKS	24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE	1
+#define HI6220_PLL1_DDR_GATE	2
+#define HI6220_PLL_DDR_GATE	3
+#define HI6220_PLL_MEDIA_GATE	4
+#define HI6220_PLL0_BBP_GATE	5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC		6
+#define HI6220_DDRC_AXI1	7
+
+#define HI6220_POWER_NR_CLKS	8
+#endif
-- 
cgit v0.10.2


From ae4dc15d98c0a591a41f449c6887707fa3891dd7 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:13:58 +0100
Subject: MAINTAINERS: Add myself as maintainer for hikey

This patch adds myself as maintainer for the hikey
U-Boot port.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 383a4ff..27eb8e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -103,6 +103,12 @@ F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/imx-common/
 
+ARM HISILICON
+M:	Peter Griffin <peter.griffin@linaro.org>
+S:	Maintained
+F:	arch/arm/cpu/armv8/hisilicon
+F:	arm/include/asm/arch-hi6220/
+
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
 M:	Prafulla Wadaskar <prafulla@marvell.com>
 M:	Luka Perkov <luka.perkov@sartura.hr>
diff --git a/board/hisilicon/hikey/MAINTAINERS b/board/hisilicon/hikey/MAINTAINERS
new file mode 100644
index 0000000..11088ee
--- /dev/null
+++ b/board/hisilicon/hikey/MAINTAINERS
@@ -0,0 +1,6 @@
+HIKEY BOARD
+M:     Peter Griffin <peter.griffin@linaro.org>
+S:     Maintained
+F:     board/hisilicon/hikey
+F:     include/configs/hikey.h
+F:     configs/hikey_defconfig
-- 
cgit v0.10.2


From cd593ed6999970cc705571332f0f3be7e40d1a96 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:13:59 +0100
Subject: ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.

Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d1c3157..6b65d8e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -668,6 +668,7 @@ config TARGET_HIKEY
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select OF_CONTROL
 	  help
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aa31fd9..d1f8e22 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -11,6 +11,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4412-trats2.dtb \
 	exynos4412-odroid.dtb
 
+dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
+
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-spring.dtb \
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 3b484a9..3f0a0cc 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -71,6 +71,8 @@ U_BOOT_DEVICES(hi6220_gpios) = {
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+
 static const struct pl01x_serial_platdata serial_platdata = {
 #if CONFIG_CONS_INDEX == 1
 	.base = HI6220_UART0_BASE,
@@ -87,6 +89,7 @@ U_BOOT_DEVICE(hikey_seriala) = {
 	.name = "serial_pl01x",
 	.platdata = &serial_platdata,
 };
+#endif
 
 static struct mm_region hikey_mem_map[] = {
 	{
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index f5660ea..d150dd3 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -14,3 +14,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
-- 
cgit v0.10.2


From 9261f8b1809d6bf2075cfc97bbd0cac23e086716 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:14:00 +0100
Subject: ARM: hisilicon: hikey: Implement reset_cpu() for hikey.

This allows the reset command to reset the board from
u-boot.

=> reset
resetting ...
INFO:    BL1: 0xf9810000 - 0xf9818000 [size = 32768]
NOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v1.1(debug):7fb9b0e
NOTICE:  BL1: Built : 17:06:41, Apr 19 2016

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 3f0a0cc..752ee6f 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -414,8 +414,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
-/* Use the Watchdog to cause reset */
 void reset_cpu(ulong addr)
 {
-	/* TODO program the watchdog */
+	writel(0x48698284, &ao_sc->stat0);
+	wfi();
 }
-- 
cgit v0.10.2


From 7e4902d47933eeeadb2eb5505683ffafa96691b7 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:14:01 +0100
Subject: ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.

This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi
index ad1f1eb..a610ccb 100644
--- a/arch/arm/dts/hi6220.dtsi
+++ b/arch/arm/dts/hi6220.dtsi
@@ -166,6 +166,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf8015000 0x0 0x1000>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 				 <&ao_ctrl HI6220_UART0_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -175,6 +176,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7111000 0x0 0x1000>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 				 <&sys_ctrl HI6220_UART1_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -185,6 +187,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7112000 0x0 0x1000>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 				 <&sys_ctrl HI6220_UART2_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -195,6 +198,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7113000 0x0 0x1000>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 				 <&sys_ctrl HI6220_UART3_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -204,6 +208,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7114000 0x0 0x1000>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 				 <&sys_ctrl HI6220_UART4_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
-- 
cgit v0.10.2


From 305b90919ea8c17edeb1e7d15ae5ca43f36bddc2 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:14:02 +0100
Subject: ARM: hisilicon: hikey: Align memory node with upstream kernel

The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.

However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 752ee6f..7abc678 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -410,8 +410,36 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
+	/*
+	 * Reserve regions below from DT memory node (which gets generated
+	 * by U-Boot from the dram banks in arch_fixup_fdt() before booting
+	 * the kernel. This will then match the kernel hikey dts memory node.
+	 *
+	 *  0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
+	 *  0x05f0,1000 - 0x05f0,1fff: Reboot reason
+	 *  0x06df,f000 - 0x06df,ffff: Mailbox message data
+	 *  0x0740,f000 - 0x0740,ffff: MCU firmware section
+	 *  0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
+	 *  0x3e00,0000 - 0x3fff,ffff: OP-TEE
+	*/
+
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[0].size = 0x05e00000;
+
+	gd->bd->bi_dram[1].start = 0x05f00000;
+	gd->bd->bi_dram[1].size = 0x00001000;
+
+	gd->bd->bi_dram[2].start = 0x05f02000;
+	gd->bd->bi_dram[2].size = 0x00efd000;
+
+	gd->bd->bi_dram[3].start = 0x06e00000;
+	gd->bd->bi_dram[3].size = 0x0060f000;
+
+	gd->bd->bi_dram[4].start = 0x07410000;
+	gd->bd->bi_dram[4].size = 0x1aaf0000;
+
+	gd->bd->bi_dram[5].start = 0x22000000;
+	gd->bd->bi_dram[5].size = 0x1c000000;
 }
 
 void reset_cpu(ulong addr)
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 114a6d1..83d9e10 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -33,7 +33,7 @@
 /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
 #define CONFIG_SYS_TEXT_BASE		0x35000000
 
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		6
 #define PHYS_SDRAM_1			0x00000000
 
 /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
-- 
cgit v0.10.2


From 532d5203e972092cb1029e49d906f28a0895ca39 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed, 20 Apr 2016 17:14:03 +0100
Subject: ARM: hikey: Simplify README instructions.

This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.

This patch also updates the link to the mcuimage.bin which was outdated.

Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README
index 36adbdb..0f6aab7 100644
--- a/board/hisilicon/hikey/README
+++ b/board/hisilicon/hikey/README
@@ -22,50 +22,55 @@ Currently the u-boot port supports: -
 * SD card
 * GPIO
 
-Compile u-boot
-==============
+The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
+U-Boot as the bl33.bin executable.
 
-  > mkdir -p ./aarch64/bin
-  > cd ./aarch64
-  > git clone http://git.denx.de/u-boot.git
-  > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
-  > make CROSS_COMPILE=aarch64-linux-gnu-
-  > cp u-boot.bin ./aarch64/bin/u-boot-hikey.bin
+Compile from source
+===================
 
-ARM Trusted Firmware (ATF) & l-loader
-=====================================
+First get all the sources
 
-This u-boot port has been tested with l-loader, booting ATF, which then boots
-u-boot as the bl33.bin executable.
+  > mkdir -p ~/hikey/src ~/hikey/bin
+  > cd ~/hikey/src
+  > git clone https://github.com/96boards/edk2.git
+  > git clone https://github.com/96boards/arm-trusted-firmware.git
+  > git clone https://github.com/96boards/l-loader.git
+  > git clone https://github.com/96boards/burn-boot.git
 
-Get the BL30 mcu binary.
-  > wget -P aarch64/bin https://builds.96boards.org/releases/hikey/linaro/binaries/15.05/mcuimage.bin
+Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the edk2 repo.
 
-1. Get ATF source code
-  > cd ./aarch64
-  > git clone https://github.com/96boards/arm-trusted-firmware.git
-  > cd ./arm-trusted-firmware
+  > cp edk2/HisiPkg/HiKeyPkg/NonFree/mcuimage.bin ~/hikey/bin/
 
-2. Compile ATF, I use the build-tf.mak in the directory with this README, and copy it to ATF directory
-  > cp ../u-boot/board/hisilicon/hikey/build-tf.mak .
-  > make -f  build-tf.mak build
+Get nvme.img binary (check this link is still the latest)
+  > wget -P ~/hikey/bin https://builds.96boards.org/releases/reference-platform/debian/hikey/16.03/bootloader/nvme.img
 
-3. Get l-loader
-  > cd ../
-  > git clone https://github.com/96boards/l-loader.git
-  > cd ./l-loader
+Compile U-Boot
+==============
 
-4. Make sym links to ATF bl1 / fip binaries
-  > ln -s ../bin/bl1-hikey.bin bl1.bin
-  > ln -s ../bin/fip-hikey.bin fip.bin
+  > cd ~/hikey/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/hikey/bin
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+  > cd ~/hikey/src/atf
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+    BL30=~/hikey/bin/mcuimage.bin \
+    BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
 
-  > arm-linux-gnueabihf-gcc -c -o start.o start.S
-  > arm-linux-gnueabihf-gcc -c -o debug.o debug.S
-  > arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader
-  > arm-linux-gnueabihf-objcopy -O binary loader temp
-  > python gen_loader.py -o ../bin/l-loader.bin --img_loader=temp --img_bl1=bl1.bin
-  > sudo bash -x generate_ptable.sh
-  > python gen_loader.py -o ../bin/ptable.img --img_prm_ptable=./prm_ptable.img --img_sec_ptable=./sec_ptable.img
+Copy resulting binaries
+  > cp build/hikey/debug/bl1.bin ~/hikey/bin
+  > cp build/hikey/debug/fip.bin ~/hikey/bin
+
+Compile l-loader
+===============
+  > cd ~/hikey/l-loader
+  > make BL1=~/hikey/bin/bl1.bin all
+  > cp *.img ~/hikey/bin
+  > cp l-loader.bin ~/hikey.bin
 
 These instructions are adapted from
 https://github.com/96boards/documentation/wiki/HiKeyUEFI
@@ -74,15 +79,12 @@ FLASHING
 ========
 
 1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
-fastboot using the hisi-idt.py utility.
-
-  > cd ../
-  > git clone https://github.com/96boards/burn-boot.git
+the hisi-idt.py utility.
 
 The command below assumes HiKey enumerated as the first USB serial port
-  > sudo ./burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=./bin/l-loader.bin
+  > sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin
 
-2. Once LED 0 comes on solid, it should be detected as a fastboot device by plugging a USB A to mini B
+2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B
    cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable).
 
   > sudo fastboot devices
@@ -90,10 +92,10 @@ The command below assumes HiKey enumerated as the first USB serial port
 0123456789ABCDEF	fastboot
 
 3. Flash the images
-  > wget -P aarch64/bin wget https://builds.96boards.org/releases/hikey/linaro/binaries/latest/nvme.img
-  > sudo fastboot flash ptable ./bin/ptable.img
-  > sudo fastboot flash fastboot ./bin/fip-hikey.bin
-  > sudo fastboot flash nvme ./bin/nvme.img
+
+  > sudo fastboot flash ptable ~/hikey/bin/ptable.img
+  > sudo fastboot flash fastboot ~/hikey/bin/fip.bin
+  > sudo fastboot flash nvme ~/hikey/bin/nvme.img
 
 4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
    have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the
@@ -102,7 +104,8 @@ The command below assumes HiKey enumerated as the first USB serial port
    Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
    will get 'dwc_otg_core_host_init: Timeout!' errors.
 
-See working boot trace below: -
+See working boot trace below (by default trace is now output to UART3 not UART0 on latest
+ATF, U-Boot and Kernel sources): -
 
 debug EMMC boot: send RST_N .
 debug EMMC boot: start eMMC boot......
-- 
cgit v0.10.2


From 5bbf4099098afb3e63574d05629e29b795d08c05 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Wed, 20 Apr 2016 23:12:04 -0300
Subject: spl: spl_mmc: Disambiguate error message

The error message "spl: mmc block read error" may come from two
different functions, so we should better annotate the function name
where the error comes from to help debugging.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 1a10c55..8d588d1 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -83,7 +83,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 end:
 	if (ret) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		puts("spl: mmc block read error\n");
+		puts("mmc_load_image_raw_sector: mmc block read error\n");
 #endif
 		return -1;
 	}
@@ -186,7 +186,7 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
 		(void *) CONFIG_SYS_SPL_ARGS_ADDR);
 	if (count == 0) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		puts("spl: mmc block read error\n");
+		puts("mmc_load_image_raw_os: mmc block read error\n");
 #endif
 		return -1;
 	}
-- 
cgit v0.10.2


From 4eece2602b6f90e56b900c5ccd0620327c92f4b3 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Thu, 21 Apr 2016 07:35:55 -0400
Subject: common/dlmalloc.c: Delete content that was moved to malloc.h

Remove several hundred lines of content surrounded by:

#if 0  /* Moved to malloc.h */
... moved stuff ...
#endif /* 0 */                 /* Moved to malloc.h */

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index d66e80c..b09f524 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -4,935 +4,6 @@
 #define DEBUG
 #endif
 
-#if 0	/* Moved to malloc.h */
-/* ---------- To make a malloc.h, start cutting here ------------ */
-
-/*
-  A version of malloc/free/realloc written by Doug Lea and released to the
-  public domain.  Send questions/comments/complaints/performance data
-  to dl@cs.oswego.edu
-
-* VERSION 2.6.6  Sun Mar  5 19:10:03 2000  Doug Lea  (dl at gee)
-
-   Note: There may be an updated version of this malloc obtainable at
-	   ftp://g.oswego.edu/pub/misc/malloc.c
-	 Check before installing!
-
-* Why use this malloc?
-
-  This is not the fastest, most space-conserving, most portable, or
-  most tunable malloc ever written. However it is among the fastest
-  while also being among the most space-conserving, portable and tunable.
-  Consistent balance across these factors results in a good general-purpose
-  allocator. For a high-level description, see
-     http://g.oswego.edu/dl/html/malloc.html
-
-* Synopsis of public routines
-
-  (Much fuller descriptions are contained in the program documentation below.)
-
-  malloc(size_t n);
-     Return a pointer to a newly allocated chunk of at least n bytes, or null
-     if no space is available.
-  free(Void_t* p);
-     Release the chunk of memory pointed to by p, or no effect if p is null.
-  realloc(Void_t* p, size_t n);
-     Return a pointer to a chunk of size n that contains the same data
-     as does chunk p up to the minimum of (n, p's size) bytes, or null
-     if no space is available. The returned pointer may or may not be
-     the same as p. If p is null, equivalent to malloc.  Unless the
-     #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
-     size argument of zero (re)allocates a minimum-sized chunk.
-  memalign(size_t alignment, size_t n);
-     Return a pointer to a newly allocated chunk of n bytes, aligned
-     in accord with the alignment argument, which must be a power of
-     two.
-  valloc(size_t n);
-     Equivalent to memalign(pagesize, n), where pagesize is the page
-     size of the system (or as near to this as can be figured out from
-     all the includes/defines below.)
-  pvalloc(size_t n);
-     Equivalent to valloc(minimum-page-that-holds(n)), that is,
-     round up n to nearest pagesize.
-  calloc(size_t unit, size_t quantity);
-     Returns a pointer to quantity * unit bytes, with all locations
-     set to zero.
-  cfree(Void_t* p);
-     Equivalent to free(p).
-  malloc_trim(size_t pad);
-     Release all but pad bytes of freed top-most memory back
-     to the system. Return 1 if successful, else 0.
-  malloc_usable_size(Void_t* p);
-     Report the number usable allocated bytes associated with allocated
-     chunk p. This may or may not report more bytes than were requested,
-     due to alignment and minimum size constraints.
-  malloc_stats();
-     Prints brief summary statistics.
-  mallinfo()
-     Returns (by copy) a struct containing various summary statistics.
-  mallopt(int parameter_number, int parameter_value)
-     Changes one of the tunable parameters described below. Returns
-     1 if successful in changing the parameter, else 0.
-
-* Vital statistics:
-
-  Alignment:                            8-byte
-       8 byte alignment is currently hardwired into the design.  This
-       seems to suffice for all current machines and C compilers.
-
-  Assumed pointer representation:       4 or 8 bytes
-       Code for 8-byte pointers is untested by me but has worked
-       reliably by Wolfram Gloger, who contributed most of the
-       changes supporting this.
-
-  Assumed size_t  representation:       4 or 8 bytes
-       Note that size_t is allowed to be 4 bytes even if pointers are 8.
-
-  Minimum overhead per allocated chunk: 4 or 8 bytes
-       Each malloced chunk has a hidden overhead of 4 bytes holding size
-       and status information.
-
-  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
-			  8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
-
-       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
-       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
-       needed; 4 (8) for a trailing size field
-       and 8 (16) bytes for free list pointers. Thus, the minimum
-       allocatable size is 16/24/32 bytes.
-
-       Even a request for zero bytes (i.e., malloc(0)) returns a
-       pointer to something of the minimum allocatable size.
-
-  Maximum allocated size: 4-byte size_t: 2^31 -  8 bytes
-			  8-byte size_t: 2^63 - 16 bytes
-
-       It is assumed that (possibly signed) size_t bit values suffice to
-       represent chunk sizes. `Possibly signed' is due to the fact
-       that `size_t' may be defined on a system as either a signed or
-       an unsigned type. To be conservative, values that would appear
-       as negative numbers are avoided.
-       Requests for sizes with a negative sign bit when the request
-       size is treaded as a long will return null.
-
-  Maximum overhead wastage per allocated chunk: normally 15 bytes
-
-       Alignnment demands, plus the minimum allocatable size restriction
-       make the normal worst-case wastage 15 bytes (i.e., up to 15
-       more bytes will be allocated than were requested in malloc), with
-       two exceptions:
-	 1. Because requests for zero bytes allocate non-zero space,
-	    the worst case wastage for a request of zero bytes is 24 bytes.
-	 2. For requests >= mmap_threshold that are serviced via
-	    mmap(), the worst case wastage is 8 bytes plus the remainder
-	    from a system page (the minimal mmap unit); typically 4096 bytes.
-
-* Limitations
-
-    Here are some features that are NOT currently supported
-
-    * No user-definable hooks for callbacks and the like.
-    * No automated mechanism for fully checking that all accesses
-      to malloced memory stay within their bounds.
-    * No support for compaction.
-
-* Synopsis of compile-time options:
-
-    People have reported using previous versions of this malloc on all
-    versions of Unix, sometimes by tweaking some of the defines
-    below. It has been tested most extensively on Solaris and
-    Linux. It is also reported to work on WIN32 platforms.
-    People have also reported adapting this malloc for use in
-    stand-alone embedded systems.
-
-    The implementation is in straight, hand-tuned ANSI C.  Among other
-    consequences, it uses a lot of macros.  Because of this, to be at
-    all usable, this code should be compiled using an optimizing compiler
-    (for example gcc -O2) that can simplify expressions and control
-    paths.
-
-  __STD_C                  (default: derived from C compiler defines)
-     Nonzero if using ANSI-standard C compiler, a C++ compiler, or
-     a C compiler sufficiently close to ANSI to get away with it.
-  DEBUG                    (default: NOT defined)
-     Define to enable debugging. Adds fairly extensive assertion-based
-     checking to help track down memory errors, but noticeably slows down
-     execution.
-  REALLOC_ZERO_BYTES_FREES (default: NOT defined)
-     Define this if you think that realloc(p, 0) should be equivalent
-     to free(p). Otherwise, since malloc returns a unique pointer for
-     malloc(0), so does realloc(p, 0).
-  HAVE_MEMCPY               (default: defined)
-     Define if you are not otherwise using ANSI STD C, but still
-     have memcpy and memset in your C library and want to use them.
-     Otherwise, simple internal versions are supplied.
-  USE_MEMCPY               (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
-     Define as 1 if you want the C library versions of memset and
-     memcpy called in realloc and calloc (otherwise macro versions are used).
-     At least on some platforms, the simple macro versions usually
-     outperform libc versions.
-  HAVE_MMAP                 (default: defined as 1)
-     Define to non-zero to optionally make malloc() use mmap() to
-     allocate very large blocks.
-  HAVE_MREMAP                 (default: defined as 0 unless Linux libc set)
-     Define to non-zero to optionally make realloc() use mremap() to
-     reallocate very large blocks.
-  malloc_getpagesize        (default: derived from system #includes)
-     Either a constant or routine call returning the system page size.
-  HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
-     Optionally define if you are on a system with a /usr/include/malloc.h
-     that declares struct mallinfo. It is not at all necessary to
-     define this even if you do, but will ensure consistency.
-  INTERNAL_SIZE_T           (default: size_t)
-     Define to a 32-bit type (probably `unsigned int') if you are on a
-     64-bit machine, yet do not want or need to allow malloc requests of
-     greater than 2^31 to be handled. This saves space, especially for
-     very small chunks.
-  INTERNAL_LINUX_C_LIB      (default: NOT defined)
-     Defined only when compiled as part of Linux libc.
-     Also note that there is some odd internal name-mangling via defines
-     (for example, internally, `malloc' is named `mALLOc') needed
-     when compiling in this case. These look funny but don't otherwise
-     affect anything.
-  WIN32                     (default: undefined)
-     Define this on MS win (95, nt) platforms to compile in sbrk emulation.
-  LACKS_UNISTD_H            (default: undefined if not WIN32)
-     Define this if your system does not have a <unistd.h>.
-  LACKS_SYS_PARAM_H         (default: undefined if not WIN32)
-     Define this if your system does not have a <sys/param.h>.
-  MORECORE                  (default: sbrk)
-     The name of the routine to call to obtain more memory from the system.
-  MORECORE_FAILURE          (default: -1)
-     The value returned upon failure of MORECORE.
-  MORECORE_CLEARS           (default 1)
-     true (1) if the routine mapped to MORECORE zeroes out memory (which
-     holds for sbrk).
-  DEFAULT_TRIM_THRESHOLD
-  DEFAULT_TOP_PAD
-  DEFAULT_MMAP_THRESHOLD
-  DEFAULT_MMAP_MAX
-     Default values of tunable parameters (described in detail below)
-     controlling interaction with host system routines (sbrk, mmap, etc).
-     These values may also be changed dynamically via mallopt(). The
-     preset defaults are those that give best performance for typical
-     programs/systems.
-  USE_DL_PREFIX             (default: undefined)
-     Prefix all public routines with the string 'dl'.  Useful to
-     quickly avoid procedure declaration conflicts and linker symbol
-     conflicts with existing memory allocation routines.
-
-
-*/
-
-
-
-/* Preliminaries */
-
-#ifndef __STD_C
-#ifdef __STDC__
-#define __STD_C     1
-#else
-#if __cplusplus
-#define __STD_C     1
-#else
-#define __STD_C     0
-#endif /*__cplusplus*/
-#endif /*__STDC__*/
-#endif /*__STD_C*/
-
-#ifndef Void_t
-#if (__STD_C || defined(WIN32))
-#define Void_t      void
-#else
-#define Void_t      char
-#endif
-#endif /*Void_t*/
-
-#if __STD_C
-#include <stddef.h>   /* for size_t */
-#else
-#include <sys/types.h>
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdio.h>    /* needed for malloc_stats */
-
-
-/*
-  Compile-time options
-*/
-
-
-/*
-    Debugging:
-
-    Because freed chunks may be overwritten with link fields, this
-    malloc will often die when freed memory is overwritten by user
-    programs.  This can be very effective (albeit in an annoying way)
-    in helping track down dangling pointers.
-
-    If you compile with -DDEBUG, a number of assertion checks are
-    enabled that will catch more memory errors. You probably won't be
-    able to make much sense of the actual assertion errors, but they
-    should help you locate incorrectly overwritten memory.  The
-    checking is fairly extensive, and will slow down execution
-    noticeably. Calling malloc_stats or mallinfo with DEBUG set will
-    attempt to check every non-mmapped allocated and free chunk in the
-    course of computing the summmaries. (By nature, mmapped regions
-    cannot be checked very much automatically.)
-
-    Setting DEBUG may also be helpful if you are trying to modify
-    this code. The assertions in the check routines spell out in more
-    detail the assumptions and invariants underlying the algorithms.
-
-*/
-
-/*
-  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
-  of chunk sizes. On a 64-bit machine, you can reduce malloc
-  overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
-  at the expense of not being able to handle requests greater than
-  2^31. This limitation is hardly ever a concern; you are encouraged
-  to set this. However, the default version is the same as size_t.
-*/
-
-#ifndef INTERNAL_SIZE_T
-#define INTERNAL_SIZE_T size_t
-#endif
-
-/*
-  REALLOC_ZERO_BYTES_FREES should be set if a call to
-  realloc with zero bytes should be the same as a call to free.
-  Some people think it should. Otherwise, since this malloc
-  returns a unique pointer for malloc(0), so does realloc(p, 0).
-*/
-
-
-/*   #define REALLOC_ZERO_BYTES_FREES */
-
-
-/*
-  WIN32 causes an emulation of sbrk to be compiled in
-  mmap-based options are not currently supported in WIN32.
-*/
-
-/* #define WIN32 */
-#ifdef WIN32
-#define MORECORE wsbrk
-#define HAVE_MMAP 0
-
-#define LACKS_UNISTD_H
-#define LACKS_SYS_PARAM_H
-
-/*
-  Include 'windows.h' to get the necessary declarations for the
-  Microsoft Visual C++ data structures and routines used in the 'sbrk'
-  emulation.
-
-  Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
-  Visual C++ header files are included.
-*/
-#define WIN32_LEAN_AND_MEAN
-#include <windows.h>
-#endif
-
-
-/*
-  HAVE_MEMCPY should be defined if you are not otherwise using
-  ANSI STD C, but still have memcpy and memset in your C library
-  and want to use them in calloc and realloc. Otherwise simple
-  macro versions are defined here.
-
-  USE_MEMCPY should be defined as 1 if you actually want to
-  have memset and memcpy called. People report that the macro
-  versions are often enough faster than libc versions on many
-  systems that it is better to use them.
-
-*/
-
-#define HAVE_MEMCPY
-
-#ifndef USE_MEMCPY
-#ifdef HAVE_MEMCPY
-#define USE_MEMCPY 1
-#else
-#define USE_MEMCPY 0
-#endif
-#endif
-
-#if (__STD_C || defined(HAVE_MEMCPY))
-
-#if __STD_C
-void* memset(void*, int, size_t);
-void* memcpy(void*, const void*, size_t);
-#else
-#ifdef WIN32
-/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
-/* 'windows.h' */
-#else
-Void_t* memset();
-Void_t* memcpy();
-#endif
-#endif
-#endif
-
-#if USE_MEMCPY
-
-/* The following macros are only invoked with (2n+1)-multiples of
-   INTERNAL_SIZE_T units, with a positive integer n. This is exploited
-   for fast inline execution when n is small. */
-
-#define MALLOC_ZERO(charp, nbytes)                                            \
-do {                                                                          \
-  INTERNAL_SIZE_T mzsz = (nbytes);                                            \
-  if(mzsz <= 9*sizeof(mzsz)) {                                                \
-    INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp);                         \
-    if(mzsz >= 5*sizeof(mzsz)) {     *mz++ = 0;                               \
-				     *mz++ = 0;                               \
-      if(mzsz >= 7*sizeof(mzsz)) {   *mz++ = 0;                               \
-				     *mz++ = 0;                               \
-	if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0;                               \
-				     *mz++ = 0; }}}                           \
-				     *mz++ = 0;                               \
-				     *mz++ = 0;                               \
-				     *mz   = 0;                               \
-  } else memset((charp), 0, mzsz);                                            \
-} while(0)
-
-#define MALLOC_COPY(dest,src,nbytes)                                          \
-do {                                                                          \
-  INTERNAL_SIZE_T mcsz = (nbytes);                                            \
-  if(mcsz <= 9*sizeof(mcsz)) {                                                \
-    INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src);                        \
-    INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest);                       \
-    if(mcsz >= 5*sizeof(mcsz)) {     *mcdst++ = *mcsrc++;                     \
-				     *mcdst++ = *mcsrc++;                     \
-      if(mcsz >= 7*sizeof(mcsz)) {   *mcdst++ = *mcsrc++;                     \
-				     *mcdst++ = *mcsrc++;                     \
-	if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++;                     \
-				     *mcdst++ = *mcsrc++; }}}                 \
-				     *mcdst++ = *mcsrc++;                     \
-				     *mcdst++ = *mcsrc++;                     \
-				     *mcdst   = *mcsrc  ;                     \
-  } else memcpy(dest, src, mcsz);                                             \
-} while(0)
-
-#else /* !USE_MEMCPY */
-
-/* Use Duff's device for good zeroing/copying performance. */
-
-#define MALLOC_ZERO(charp, nbytes)                                            \
-do {                                                                          \
-  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
-  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
-  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
-  switch (mctmp) {                                                            \
-    case 0: for(;;) { *mzp++ = 0;                                             \
-    case 7:           *mzp++ = 0;                                             \
-    case 6:           *mzp++ = 0;                                             \
-    case 5:           *mzp++ = 0;                                             \
-    case 4:           *mzp++ = 0;                                             \
-    case 3:           *mzp++ = 0;                                             \
-    case 2:           *mzp++ = 0;                                             \
-    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
-  }                                                                           \
-} while(0)
-
-#define MALLOC_COPY(dest,src,nbytes)                                          \
-do {                                                                          \
-  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
-  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
-  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
-  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
-  switch (mctmp) {                                                            \
-    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
-    case 7:           *mcdst++ = *mcsrc++;                                    \
-    case 6:           *mcdst++ = *mcsrc++;                                    \
-    case 5:           *mcdst++ = *mcsrc++;                                    \
-    case 4:           *mcdst++ = *mcsrc++;                                    \
-    case 3:           *mcdst++ = *mcsrc++;                                    \
-    case 2:           *mcdst++ = *mcsrc++;                                    \
-    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
-  }                                                                           \
-} while(0)
-
-#endif
-
-
-/*
-  Define HAVE_MMAP to optionally make malloc() use mmap() to
-  allocate very large blocks.  These will be returned to the
-  operating system immediately after a free().
-*/
-
-#ifndef HAVE_MMAP
-#define HAVE_MMAP 1
-#endif
-
-/*
-  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
-  large blocks.  This is currently only possible on Linux with
-  kernel versions newer than 1.3.77.
-*/
-
-#ifndef HAVE_MREMAP
-#ifdef INTERNAL_LINUX_C_LIB
-#define HAVE_MREMAP 1
-#else
-#define HAVE_MREMAP 0
-#endif
-#endif
-
-#if HAVE_MMAP
-
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-
-#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
-#define MAP_ANONYMOUS MAP_ANON
-#endif
-
-#endif /* HAVE_MMAP */
-
-/*
-  Access to system page size. To the extent possible, this malloc
-  manages memory from the system in page-size units.
-
-  The following mechanics for getpagesize were adapted from
-  bsd/gnu getpagesize.h
-*/
-
-#ifndef LACKS_UNISTD_H
-#  include <unistd.h>
-#endif
-
-#ifndef malloc_getpagesize
-#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
-#    ifndef _SC_PAGE_SIZE
-#      define _SC_PAGE_SIZE _SC_PAGESIZE
-#    endif
-#  endif
-#  ifdef _SC_PAGE_SIZE
-#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
-#  else
-#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
-       extern size_t getpagesize();
-#      define malloc_getpagesize getpagesize()
-#    else
-#      ifdef WIN32
-#        define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
-#      else
-#        ifndef LACKS_SYS_PARAM_H
-#          include <sys/param.h>
-#        endif
-#        ifdef EXEC_PAGESIZE
-#          define malloc_getpagesize EXEC_PAGESIZE
-#        else
-#          ifdef NBPG
-#            ifndef CLSIZE
-#              define malloc_getpagesize NBPG
-#            else
-#              define malloc_getpagesize (NBPG * CLSIZE)
-#            endif
-#          else
-#            ifdef NBPC
-#              define malloc_getpagesize NBPC
-#            else
-#              ifdef PAGESIZE
-#                define malloc_getpagesize PAGESIZE
-#              else
-#                define malloc_getpagesize (4096) /* just guess */
-#              endif
-#            endif
-#          endif
-#        endif
-#      endif
-#    endif
-#  endif
-#endif
-
-
-/*
-
-  This version of malloc supports the standard SVID/XPG mallinfo
-  routine that returns a struct containing the same kind of
-  information you can get from malloc_stats. It should work on
-  any SVID/XPG compliant system that has a /usr/include/malloc.h
-  defining struct mallinfo. (If you'd like to install such a thing
-  yourself, cut out the preliminary declarations as described above
-  and below and save them in a malloc.h file. But there's no
-  compelling reason to bother to do this.)
-
-  The main declaration needed is the mallinfo struct that is returned
-  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
-  bunch of fields, most of which are not even meaningful in this
-  version of malloc. Some of these fields are are instead filled by
-  mallinfo() with other numbers that might possibly be of interest.
-
-  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
-  /usr/include/malloc.h file that includes a declaration of struct
-  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
-  version is declared below.  These must be precisely the same for
-  mallinfo() to work.
-
-*/
-
-/* #define HAVE_USR_INCLUDE_MALLOC_H */
-
-#if HAVE_USR_INCLUDE_MALLOC_H
-#include "/usr/include/malloc.h"
-#else
-
-/* SVID2/XPG mallinfo structure */
-
-struct mallinfo {
-  int arena;    /* total space allocated from system */
-  int ordblks;  /* number of non-inuse chunks */
-  int smblks;   /* unused -- always zero */
-  int hblks;    /* number of mmapped regions */
-  int hblkhd;   /* total space in mmapped regions */
-  int usmblks;  /* unused -- always zero */
-  int fsmblks;  /* unused -- always zero */
-  int uordblks; /* total allocated space */
-  int fordblks; /* total non-inuse space */
-  int keepcost; /* top-most, releasable (via malloc_trim) space */
-};
-
-/* SVID2/XPG mallopt options */
-
-#define M_MXFAST  1    /* UNUSED in this malloc */
-#define M_NLBLKS  2    /* UNUSED in this malloc */
-#define M_GRAIN   3    /* UNUSED in this malloc */
-#define M_KEEP    4    /* UNUSED in this malloc */
-
-#endif
-
-/* mallopt options that actually do something */
-
-#define M_TRIM_THRESHOLD    -1
-#define M_TOP_PAD           -2
-#define M_MMAP_THRESHOLD    -3
-#define M_MMAP_MAX          -4
-
-
-#ifndef DEFAULT_TRIM_THRESHOLD
-#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
-#endif
-
-/*
-    M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
-      to keep before releasing via malloc_trim in free().
-
-      Automatic trimming is mainly useful in long-lived programs.
-      Because trimming via sbrk can be slow on some systems, and can
-      sometimes be wasteful (in cases where programs immediately
-      afterward allocate more large chunks) the value should be high
-      enough so that your overall system performance would improve by
-      releasing.
-
-      The trim threshold and the mmap control parameters (see below)
-      can be traded off with one another. Trimming and mmapping are
-      two different ways of releasing unused memory back to the
-      system. Between these two, it is often possible to keep
-      system-level demands of a long-lived program down to a bare
-      minimum. For example, in one test suite of sessions measuring
-      the XF86 X server on Linux, using a trim threshold of 128K and a
-      mmap threshold of 192K led to near-minimal long term resource
-      consumption.
-
-      If you are using this malloc in a long-lived program, it should
-      pay to experiment with these values.  As a rough guide, you
-      might set to a value close to the average size of a process
-      (program) running on your system.  Releasing this much memory
-      would allow such a process to run in memory.  Generally, it's
-      worth it to tune for trimming rather tham memory mapping when a
-      program undergoes phases where several large chunks are
-      allocated and released in ways that can reuse each other's
-      storage, perhaps mixed with phases where there are no such
-      chunks at all.  And in well-behaved long-lived programs,
-      controlling release of large blocks via trimming versus mapping
-      is usually faster.
-
-      However, in most programs, these parameters serve mainly as
-      protection against the system-level effects of carrying around
-      massive amounts of unneeded memory. Since frequent calls to
-      sbrk, mmap, and munmap otherwise degrade performance, the default
-      parameters are set to relatively high values that serve only as
-      safeguards.
-
-      The default trim value is high enough to cause trimming only in
-      fairly extreme (by current memory consumption standards) cases.
-      It must be greater than page size to have any useful effect.  To
-      disable trimming completely, you can set to (unsigned long)(-1);
-
-
-*/
-
-
-#ifndef DEFAULT_TOP_PAD
-#define DEFAULT_TOP_PAD        (0)
-#endif
-
-/*
-    M_TOP_PAD is the amount of extra `padding' space to allocate or
-      retain whenever sbrk is called. It is used in two ways internally:
-
-      * When sbrk is called to extend the top of the arena to satisfy
-	a new malloc request, this much padding is added to the sbrk
-	request.
-
-      * When malloc_trim is called automatically from free(),
-	it is used as the `pad' argument.
-
-      In both cases, the actual amount of padding is rounded
-      so that the end of the arena is always a system page boundary.
-
-      The main reason for using padding is to avoid calling sbrk so
-      often. Having even a small pad greatly reduces the likelihood
-      that nearly every malloc request during program start-up (or
-      after trimming) will invoke sbrk, which needlessly wastes
-      time.
-
-      Automatic rounding-up to page-size units is normally sufficient
-      to avoid measurable overhead, so the default is 0.  However, in
-      systems where sbrk is relatively slow, it can pay to increase
-      this value, at the expense of carrying around more memory than
-      the program needs.
-
-*/
-
-
-#ifndef DEFAULT_MMAP_THRESHOLD
-#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
-#endif
-
-/*
-
-    M_MMAP_THRESHOLD is the request size threshold for using mmap()
-      to service a request. Requests of at least this size that cannot
-      be allocated using already-existing space will be serviced via mmap.
-      (If enough normal freed space already exists it is used instead.)
-
-      Using mmap segregates relatively large chunks of memory so that
-      they can be individually obtained and released from the host
-      system. A request serviced through mmap is never reused by any
-      other request (at least not directly; the system may just so
-      happen to remap successive requests to the same locations).
-
-      Segregating space in this way has the benefit that mmapped space
-      can ALWAYS be individually released back to the system, which
-      helps keep the system level memory demands of a long-lived
-      program low. Mapped memory can never become `locked' between
-      other chunks, as can happen with normally allocated chunks, which
-      menas that even trimming via malloc_trim would not release them.
-
-      However, it has the disadvantages that:
-
-	 1. The space cannot be reclaimed, consolidated, and then
-	    used to service later requests, as happens with normal chunks.
-	 2. It can lead to more wastage because of mmap page alignment
-	    requirements
-	 3. It causes malloc performance to be more dependent on host
-	    system memory management support routines which may vary in
-	    implementation quality and may impose arbitrary
-	    limitations. Generally, servicing a request via normal
-	    malloc steps is faster than going through a system's mmap.
-
-      All together, these considerations should lead you to use mmap
-      only for relatively large requests.
-
-
-*/
-
-
-#ifndef DEFAULT_MMAP_MAX
-#if HAVE_MMAP
-#define DEFAULT_MMAP_MAX       (64)
-#else
-#define DEFAULT_MMAP_MAX       (0)
-#endif
-#endif
-
-/*
-    M_MMAP_MAX is the maximum number of requests to simultaneously
-      service using mmap. This parameter exists because:
-
-	 1. Some systems have a limited number of internal tables for
-	    use by mmap.
-	 2. In most systems, overreliance on mmap can degrade overall
-	    performance.
-	 3. If a program allocates many large regions, it is probably
-	    better off using normal sbrk-based allocation routines that
-	    can reclaim and reallocate normal heap memory. Using a
-	    small value allows transition into this mode after the
-	    first few allocations.
-
-      Setting to 0 disables all use of mmap.  If HAVE_MMAP is not set,
-      the default value is 0, and attempts to set it to non-zero values
-      in mallopt will fail.
-*/
-
-
-/*
-    USE_DL_PREFIX will prefix all public routines with the string 'dl'.
-      Useful to quickly avoid procedure declaration conflicts and linker
-      symbol conflicts with existing memory allocation routines.
-
-*/
-
-/* #define USE_DL_PREFIX */
-
-
-/*
-
-  Special defines for linux libc
-
-  Except when compiled using these special defines for Linux libc
-  using weak aliases, this malloc is NOT designed to work in
-  multithreaded applications.  No semaphores or other concurrency
-  control are provided to ensure that multiple malloc or free calls
-  don't run at the same time, which could be disasterous. A single
-  semaphore could be used across malloc, realloc, and free (which is
-  essentially the effect of the linux weak alias approach). It would
-  be hard to obtain finer granularity.
-
-*/
-
-
-#ifdef INTERNAL_LINUX_C_LIB
-
-#if __STD_C
-
-Void_t * __default_morecore_init (ptrdiff_t);
-Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
-
-#else
-
-Void_t * __default_morecore_init ();
-Void_t *(*__morecore)() = __default_morecore_init;
-
-#endif
-
-#define MORECORE (*__morecore)
-#define MORECORE_FAILURE 0
-#define MORECORE_CLEARS 1
-
-#else /* INTERNAL_LINUX_C_LIB */
-
-#if __STD_C
-extern Void_t*     sbrk(ptrdiff_t);
-#else
-extern Void_t*     sbrk();
-#endif
-
-#ifndef MORECORE
-#define MORECORE sbrk
-#endif
-
-#ifndef MORECORE_FAILURE
-#define MORECORE_FAILURE -1
-#endif
-
-#ifndef MORECORE_CLEARS
-#define MORECORE_CLEARS 1
-#endif
-
-#endif /* INTERNAL_LINUX_C_LIB */
-
-#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
-
-#define cALLOc		__libc_calloc
-#define fREe		__libc_free
-#define mALLOc		__libc_malloc
-#define mEMALIGn	__libc_memalign
-#define rEALLOc		__libc_realloc
-#define vALLOc		__libc_valloc
-#define pvALLOc		__libc_pvalloc
-#define mALLINFo	__libc_mallinfo
-#define mALLOPt		__libc_mallopt
-
-#pragma weak calloc = __libc_calloc
-#pragma weak free = __libc_free
-#pragma weak cfree = __libc_free
-#pragma weak malloc = __libc_malloc
-#pragma weak memalign = __libc_memalign
-#pragma weak realloc = __libc_realloc
-#pragma weak valloc = __libc_valloc
-#pragma weak pvalloc = __libc_pvalloc
-#pragma weak mallinfo = __libc_mallinfo
-#pragma weak mallopt = __libc_mallopt
-
-#else
-
-#ifdef USE_DL_PREFIX
-#define cALLOc		dlcalloc
-#define fREe		dlfree
-#define mALLOc		dlmalloc
-#define mEMALIGn	dlmemalign
-#define rEALLOc		dlrealloc
-#define vALLOc		dlvalloc
-#define pvALLOc		dlpvalloc
-#define mALLINFo	dlmallinfo
-#define mALLOPt		dlmallopt
-#else /* USE_DL_PREFIX */
-#define cALLOc		calloc
-#define fREe		free
-#define mALLOc		malloc
-#define mEMALIGn	memalign
-#define rEALLOc		realloc
-#define vALLOc		valloc
-#define pvALLOc		pvalloc
-#define mALLINFo	mallinfo
-#define mALLOPt		mallopt
-#endif /* USE_DL_PREFIX */
-
-#endif
-
-/* Public routines */
-
-#if __STD_C
-
-Void_t* mALLOc(size_t);
-void    fREe(Void_t*);
-Void_t* rEALLOc(Void_t*, size_t);
-Void_t* mEMALIGn(size_t, size_t);
-Void_t* vALLOc(size_t);
-Void_t* pvALLOc(size_t);
-Void_t* cALLOc(size_t, size_t);
-void    cfree(Void_t*);
-int     malloc_trim(size_t);
-size_t  malloc_usable_size(Void_t*);
-void    malloc_stats();
-int     mALLOPt(int, int);
-struct mallinfo mALLINFo(void);
-#else
-Void_t* mALLOc();
-void    fREe();
-Void_t* rEALLOc();
-Void_t* mEMALIGn();
-Void_t* vALLOc();
-Void_t* pvALLOc();
-Void_t* cALLOc();
-void    cfree();
-int     malloc_trim();
-size_t  malloc_usable_size();
-void    malloc_stats();
-int     mALLOPt();
-struct mallinfo mALLINFo();
-#endif
-
-
-#ifdef __cplusplus
-};  /* end of extern "C" */
-#endif
-
-/* ---------- To make a malloc.h, end cutting here ------------ */
-#endif	/* 0 */			/* Moved to malloc.h */
-
 #include <malloc.h>
 #include <asm/io.h>
 
-- 
cgit v0.10.2


From 2d9d057be6aaa410650b7ceecfcdb0aca4c24e31 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 21 Apr 2016 14:34:22 -0500
Subject: ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2

This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.

This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.

Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index cb41055..27e6871 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -584,7 +584,7 @@ void scale_vcores(struct vcores_data const *vcores)
 	debug("mpu: %d\n", vcores->mpu.value);
 	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
 	/* Configure MPU ABB LDO after scale */
-	abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+	abb_setup(vcores->mpu.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
@@ -621,7 +621,7 @@ void scale_vcores(struct vcores_data const *vcores)
 	do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
 
 	/* Configure MPU ABB LDO after scale */
-	abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+	abb_setup(vcores->mpu.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index cd289dd..c55c6af 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -297,7 +297,6 @@ struct prcm_regs const omap5_es1_prcm = {
 
 struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_status				= 0x4A002134,
-	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
 	.control_std_fuse_die_id_0		= 0x4A002200,
 	.control_std_fuse_die_id_1		= 0x4A002208,
 	.control_std_fuse_die_id_2		= 0x4A00220C,
@@ -440,7 +439,6 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_srcomp_code_latch		= 0x4A002E84,
 	.control_ddr_control_ext_0		= 0x4A002E88,
 	.control_padconf_core_base		= 0x4A003400,
-	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B20,
 	.control_port_emif1_sdram_config	= 0x4AE0C110,
 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
 	.control_port_emif2_sdram_config	= 0x4AE0C118,
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8c85f46..2daa440 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -363,7 +363,6 @@ struct omap_sys_ctrl_regs {
 	u32 control_core_mac_id_0_hi;
 	u32 control_core_mac_id_1_lo;
 	u32 control_core_mac_id_1_hi;
-	u32 control_std_fuse_opp_vdd_mpu_2;
 	u32 control_phy_power_usb;
 	u32 control_core_mmr_lock1;
 	u32 control_core_mmr_lock2;
-- 
cgit v0.10.2


From 3708e78c33b3853e300a6ded3113de90dacbc633 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 21 Apr 2016 14:34:23 -0500
Subject: ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure

ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.

Hence, move the txdone mask definition over to structure describing
voltage domain.

Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 27e6871..8fe695b 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -589,7 +589,7 @@ void scale_vcores(struct vcores_data const *vcores)
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
 		  (*prcm)->prm_irqstatus_mpu_2,
-		  OMAP_ABB_MPU_TXDONE_MASK,
+		  vcores->mpu.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
 
 	/* The .mm member is not used for the DRA7xx */
@@ -626,7 +626,7 @@ void scale_vcores(struct vcores_data const *vcores)
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
 		  (*prcm)->prm_irqstatus_mpu_2,
-		  OMAP_ABB_MPU_TXDONE_MASK,
+		  vcores->mpu.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
 
 	val = optimize_vcore_voltage(&vcores->mm);
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index b69c0d1..a4b31e4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -352,6 +352,7 @@ struct vcores_data omap5430_volts_es2 = {
 	.mpu.value = VDD_MPU_ES2,
 	.mpu.addr = SMPS_REG_ADDR_12_MPU,
 	.mpu.pmic = &palmas,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.core.value = VDD_CORE_ES2,
 	.core.addr = SMPS_REG_ADDR_8_CORE,
@@ -368,6 +369,7 @@ struct vcores_data dra752_volts = {
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.eve.value	= VDD_EVE_DRA752,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
@@ -400,6 +402,7 @@ struct vcores_data dra722_volts = {
 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
 	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.core.value	= VDD_CORE_DRA72x,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 2daa440..d3e8417 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -540,6 +540,8 @@ struct volts {
 	u32 addr;
 	struct volts_efuse_data efuse;
 	struct pmic_data *pmic;
+
+	u32 abb_tx_done_mask;
 };
 
 struct vcores_data {
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 1762089..2404eb5 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -221,6 +221,7 @@ struct vcores_data beagle_x15_volts = {
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.eve.value		= VDD_EVE_DRA752,
 	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
-- 
cgit v0.10.2


From a818097a330e73795dc0e783fbb67c5ec86b657f Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 21 Apr 2016 14:34:24 -0500
Subject: ARM: OMAP5: Enable ABB configuration for MM voltage domain

Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 8fe695b..da57b38 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -632,6 +632,15 @@ void scale_vcores(struct vcores_data const *vcores)
 	val = optimize_vcore_voltage(&vcores->mm);
 	do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
 
+	/* Configure MM ABB LDO after scale */
+	abb_setup(vcores->mm.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
+		  (*prcm)->prm_abbldo_mm_setup,
+		  (*prcm)->prm_abbldo_mm_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->mm.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
+
 	val = optimize_vcore_voltage(&vcores->gpu);
 	do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
 
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index a4b31e4..dfb1df6 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -361,6 +361,7 @@ struct vcores_data omap5430_volts_es2 = {
 	.mm.value = VDD_MM_ES2,
 	.mm.addr = SMPS_REG_ADDR_45_IVA,
 	.mm.pmic = &palmas,
+	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
 struct vcores_data dra752_volts = {
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index c55c6af..d126a32 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -352,6 +352,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
+	.control_wkup_ldovbb_mm_voltage_ctrl	= 0x4AE0C314,
 	.control_padconf_wkup_base		= 0x4AE0C800,
 	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
 	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
@@ -722,6 +723,7 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
 
 	/* prm irqstatus regs */
+	.prm_irqstatus_mpu = 0x4ae06010,
 	.prm_irqstatus_mpu_2 = 0x4ae06014,
 
 	/* l4 wkup regs */
@@ -751,6 +753,8 @@ struct prcm_regs const omap5_es2_prcm = {
 
 	.prm_abbldo_mpu_setup = 0x4ae07cdc,
 	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+	.prm_abbldo_mm_setup = 0x4ae07ce4,
+	.prm_abbldo_mm_ctrl = 0x4ae07ce8,
 
 	/* SCRM stuff, used by some boards */
 	.scrm_auxclk0 = 0x4ae0a310,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 1eeb8d5..cfec5b0 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -215,6 +215,7 @@ struct s32ktimer {
 
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
+#define OMAP_ABB_MM_TXDONE_MASK			(0x1 << 31)
 
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d3e8417..14c07fa 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -234,6 +234,7 @@ struct prcm_regs {
 	u32 cm_l3init_usb_otg_ss1_clkctrl;
 	u32 cm_l3init_usb_otg_ss2_clkctrl;
 
+	u32 prm_irqstatus_mpu;
 	u32 prm_irqstatus_mpu_2;
 
 	/* cm2.l4per */
@@ -321,6 +322,8 @@ struct prcm_regs {
 	u32 prm_vc_cfg_i2c_clk;
 	u32 prm_abbldo_mpu_setup;
 	u32 prm_abbldo_mpu_ctrl;
+	u32 prm_abbldo_mm_setup;
+	u32 prm_abbldo_mm_ctrl;
 
 	u32 cm_div_m4_dpll_core;
 	u32 cm_div_m5_dpll_core;
@@ -441,6 +444,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_emif1_sdram_config_ext;
 	u32 control_emif2_sdram_config_ext;
 	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+	u32 control_wkup_ldovbb_mm_voltage_ctrl;
 	u32 control_smart1nopmio_padconf_0;
 	u32 control_smart1nopmio_padconf_1;
 	u32 control_padconf_mode;
-- 
cgit v0.10.2


From e52e334e5cb493e19377d23a00aa4d021fc229ba Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Thu, 21 Apr 2016 14:34:25 -0500
Subject: ARM: DRA7: Add ABB setup for all domains

ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index da57b38..ef2ac98 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -596,10 +596,34 @@ void scale_vcores(struct vcores_data const *vcores)
 
 	debug("gpu: %d\n", vcores->gpu.value);
 	do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
+	/* Configure GPU ABB LDO after scale */
+	abb_setup(vcores->gpu.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
+		  (*prcm)->prm_abbldo_gpu_setup,
+		  (*prcm)->prm_abbldo_gpu_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->gpu.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
 	debug("eve: %d\n", vcores->eve.value);
 	do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
+	/* Configure EVE ABB LDO after scale */
+	abb_setup(vcores->eve.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
+		  (*prcm)->prm_abbldo_eve_setup,
+		  (*prcm)->prm_abbldo_eve_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->eve.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
 	debug("iva: %d\n", vcores->iva.value);
 	do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
+	/* Configure IVA ABB LDO after scale */
+	abb_setup(vcores->iva.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
+		  (*prcm)->prm_abbldo_iva_setup,
+		  (*prcm)->prm_abbldo_iva_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->iva.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
 	/* Might need udelay(1000) here if debug is enabled to see all prints */
 #else
 	u32 val;
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index dfb1df6..88e8920 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -377,12 +377,14 @@ struct vcores_data dra752_volts = {
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.gpu.value	= VDD_GPU_DRA752,
 	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
 	.core.value	= VDD_CORE_DRA752,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -395,6 +397,7 @@ struct vcores_data dra752_volts = {
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 };
 
 struct vcores_data dra722_volts = {
@@ -420,18 +423,21 @@ struct vcores_data dra722_volts = {
 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
 	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
 	.eve.value	= VDD_EVE_DRA72x,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
 	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.iva.value	= VDD_IVA_DRA72x,
 	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
 	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 };
 
 /*
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index d126a32..655e92b 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -446,6 +446,9 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
+	.control_wkup_ldovbb_iva_voltage_ctrl	= 0x4A002470,
+	.control_wkup_ldovbb_eve_voltage_ctrl	= 0x4A00246C,
+	.control_wkup_ldovbb_gpu_voltage_ctrl	= 0x4AE0C154,
 	.control_std_fuse_die_id_0		= 0x4AE0C200,
 	.control_std_fuse_die_id_1		= 0x4AE0C208,
 	.control_std_fuse_die_id_2		= 0x4AE0C20C,
@@ -831,6 +834,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
 
 	/* prm irqstatus regs */
+	.prm_irqstatus_mpu			= 0x4ae06010,
 	.prm_irqstatus_mpu_2			= 0x4ae06014,
 
 	/* cm2.ckgen */
@@ -999,6 +1003,12 @@ struct prcm_regs const dra7xx_prcm = {
 
 	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
 	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
+	.prm_abbldo_iva_setup			= 0x4AE07E34,
+	.prm_abbldo_iva_ctrl			= 0x4AE07E24,
+	.prm_abbldo_eve_setup			= 0x4AE07E30,
+	.prm_abbldo_eve_ctrl			= 0x4AE07E20,
+	.prm_abbldo_gpu_setup			= 0x4AE07DE4,
+	.prm_abbldo_gpu_ctrl			= 0x4AE07DE8,
 
 	/*l3main1 edma*/
 	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index cfec5b0..2fd5cda 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -216,6 +216,9 @@ struct s32ktimer {
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
 #define OMAP_ABB_MM_TXDONE_MASK			(0x1 << 31)
+#define OMAP_ABB_IVA_TXDONE_MASK		(0x1 << 30)
+#define OMAP_ABB_EVE_TXDONE_MASK		(0x1 << 29)
+#define OMAP_ABB_GPU_TXDONE_MASK		(0x1 << 28)
 
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 14c07fa..8fb05e1 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -324,6 +324,12 @@ struct prcm_regs {
 	u32 prm_abbldo_mpu_ctrl;
 	u32 prm_abbldo_mm_setup;
 	u32 prm_abbldo_mm_ctrl;
+	u32 prm_abbldo_iva_setup;
+	u32 prm_abbldo_iva_ctrl;
+	u32 prm_abbldo_eve_setup;
+	u32 prm_abbldo_eve_ctrl;
+	u32 prm_abbldo_gpu_setup;
+	u32 prm_abbldo_gpu_ctrl;
 
 	u32 cm_div_m4_dpll_core;
 	u32 cm_div_m5_dpll_core;
@@ -445,6 +451,9 @@ struct omap_sys_ctrl_regs {
 	u32 control_emif2_sdram_config_ext;
 	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
 	u32 control_wkup_ldovbb_mm_voltage_ctrl;
+	u32 control_wkup_ldovbb_iva_voltage_ctrl;
+	u32 control_wkup_ldovbb_eve_voltage_ctrl;
+	u32 control_wkup_ldovbb_gpu_voltage_ctrl;
 	u32 control_smart1nopmio_padconf_0;
 	u32 control_smart1nopmio_padconf_1;
 	u32 control_padconf_mode;
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 2404eb5..86b8f6e 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -228,12 +228,14 @@ struct vcores_data beagle_x15_volts = {
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
 
 	.gpu.value		= VDD_GPU_DRA752,
 	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU_NOM,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
 	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
 
 	.core.value		= VDD_CORE_DRA752,
 	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -246,6 +248,7 @@ struct vcores_data beagle_x15_volts = {
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
 	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
 };
 
 #ifdef CONFIG_SPL_BUILD
-- 
cgit v0.10.2


From cacd1d2f33da2d78e8568f2e48539a4a57de20ae Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 22 Apr 2016 20:59:31 +0900
Subject: mmc: sdhci: add const qualifier to the name of struct sdhci_host

This allows to drop annoying (char *) casts when setting the host
name of struct sdhci_host.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 5fb7151..340eef6 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -28,7 +28,7 @@ int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
 		if (!mmc_host)
 			return -ENOMEM;
 
-		mmc_host->name = (char *)name;
+		mmc_host->name = name;
 		dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
 		mmc_host->ioaddr = (void *)iobase;
 		mmc_host->quirks = 0;
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
index 28da55d..e03d6dd 100644
--- a/drivers/mmc/pic32_sdhci.c
+++ b/drivers/mmc/pic32_sdhci.c
@@ -29,7 +29,7 @@ static int pic32_sdhci_probe(struct udevice *dev)
 		return -EINVAL;
 
 	host->ioaddr	= ioremap(addr, size);
-	host->name	= (char *)dev->name;
+	host->name	= dev->name;
 	host->quirks	= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_NO_CD;
 	host->bus_width	= fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 					"bus-width", 4);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 039ec16..b59feca 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -43,7 +43,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 {
 	struct sdhci_host *host = dev_get_priv(dev);
 
-	host->name = (char *)dev->name;
+	host->name = dev->name;
 	host->ioaddr = (void *)dev_get_addr(dev);
 
 	return 0;
diff --git a/include/sdhci.h b/include/sdhci.h
index 23893b5..e0f6667 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -235,7 +235,7 @@ struct sdhci_ops {
 };
 
 struct sdhci_host {
-	char *name;
+	const char *name;
 	void *ioaddr;
 	unsigned int quirks;
 	unsigned int host_caps;
-- 
cgit v0.10.2


From 6d9f5b035d73129fe0ba4c0d28af55ee565e2490 Mon Sep 17 00:00:00 2001
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Date: Mon, 25 Apr 2016 15:41:01 +0900
Subject: pci: Device scanning range fix

The terminal condition in the area where a PCI device is scanned is wrong,
and 1f.7 isn't scanned.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index c7fbf7b..32590ce 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -682,7 +682,7 @@ int pci_bind_bus_devices(struct udevice *bus)
 	found_multi = false;
 	end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
 		      PCI_MAX_PCI_FUNCTIONS - 1);
-	for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
+	for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
 	     bdf += PCI_BDF(0, 0, 1)) {
 		struct pci_child_platdata *pplat;
 		struct udevice *dev;
-- 
cgit v0.10.2


From ac5c61bfa6ad24a5384b9b89902e024a994f715f Mon Sep 17 00:00:00 2001
From: Martin Pietryka <martin.pietryka@chello.at>
Date: Mon, 25 Apr 2016 21:25:07 +0200
Subject: drivers/video/am335x-fb: Fix bits for LCD_PALMODE_RAWDATA definition

According to the TRM you have to set bits [21:20] to 0b10 for RAW mode, so
(0x10 << 20) is obviously wrong here.

Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>

diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index e23d172..0ec843f 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -55,7 +55,7 @@
 /* LCD Raster Ctrl Register */
 #define LCD_TFT_24BPP_MODE			(1 << 25)
 #define LCD_TFT_24BPP_UNPACK			(1 << 26)
-#define LCD_PALMODE_RAWDATA			(0x10 << 20)
+#define LCD_PALMODE_RAWDATA			(0x02 << 20)
 #define LCD_TFT_MODE				(0x01 << 7)
 #define LCD_RASTER_ENABLE			(0x01 << 0)
 
-- 
cgit v0.10.2


From fc6e3c81deb14cab664afff45e31309b70bac19d Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 25 Apr 2016 18:03:48 -0400
Subject: pico-imx6ul: Update the defconfig

The defconfig/config.h file were merged but were already out of sync
with mainline.  This brings them further into line now.

Cc: Richard Hu <richard.hu@technexion.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 9157faa..cc49dc9 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -1,5 +1,22 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
 CONFIG_TARGET_PICO_IMX6UL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 3e37815..d848ead 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -31,14 +31,11 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
 
 #define CONFIG_MMC
-#define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SUPPORT_EMMC_BOOT
 
 /* USB Configs */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -52,7 +49,6 @@
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET
 
-#define CONFIG_CMD_USB_MASS_STORAGE
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
@@ -100,7 +96,6 @@
 		   "fi; " \
 	   "else run netboot; fi"
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + SZ_128M
 
@@ -134,7 +129,4 @@
 #define CONFIG_SYS_MMC_ENV_PART		0
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"
 
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-
 #endif /* __PICO_IMX6UL_CONFIG_H */
-- 
cgit v0.10.2


From a398e7aa216279652dd380d3ecd3683b3b5e588e Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 25 Apr 2016 19:27:37 -0400
Subject: Prepare v2016.05-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 66a0163..f03fec1 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From 266c63cbf2674e20077da9fce27757a7fbc40ec3 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 26 Apr 2016 11:23:39 +0900
Subject: ARM: uniphier: revive some commands lost by Kconfig re-sync

The recently added uniphier_ld20_defconfig missed the tree-wide
re-sync by commit 89cb2b5f8be4 ("configs: Re-sync with cmd/Kconfig").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index 3a5bf02..cbc65dd 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
@@ -16,6 +17,7 @@ CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_GPIO_UNIPHIER=y
-- 
cgit v0.10.2


From e25b369c048b51b1feb79587750e7e160fc0bd73 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 26 Apr 2016 16:12:06 +0200
Subject: ARM64: zynqmp: Cleanup config file after CMD move

The patch:
"configs: Re-sync almost all of cmd/Kconfig"
(sha1: 78d1e1d0a157c8b48ea19be6170b992745d30f38)
doesn't remove empty if-endif. This patch is fixing it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index fe9c719..060bca9 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -75,10 +75,6 @@
 #define CONFIG_BOOTP_MAY_FAIL
 #define CONFIG_BOOTP_SERVERIP
 
-/* SPI */
-#ifdef CONFIG_ZYNQ_SPI
-#endif
-
 #if defined(CONFIG_ZYNQ_SDHCI)
 # define CONFIG_MMC
 # define CONFIG_GENERIC_MMC
-- 
cgit v0.10.2


From bfb33f0bc45b9ee92ed2f85107cf20b9bfdf9f8a Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 14 Apr 2016 18:53:32 +0200
Subject: sunxi: mctl_mem_matches: Add missing memory barrier

We are running with the caches disabled when mctl_mem_matches gets called,
but the cpu's write buffer is still there and can still get in the way,
add a memory barrier to fix this.

This avoids mctl_mem_matches always returning false in some cases, which
was resulting in:

U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
DRAM: 1024 MiB

U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology

CPU:   Allwinner A23 (SUN8I)
DRAM:  512 MiB

Where 512 MiB is the right amount, but the DRAM controller would be
initialized for 1024 MiB.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 50318d2..e0c823a 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/io.h>
 #include <asm/arch/dram.h>
 
@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
 	/* Try to write different values to RAM at two addresses */
 	writel(0, CONFIG_SYS_SDRAM_BASE);
 	writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+	DSB;
 	/* Check if the same value is actually observed when reading back */
 	return readl(CONFIG_SYS_SDRAM_BASE) ==
 	       readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
-- 
cgit v0.10.2


From ad14166426ab8ca40424ede741d27fdcfb4fc2c6 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 14 Apr 2016 16:49:47 +0200
Subject: sunxi: Enable LDO3 at 3.3V on A13-OLinuXino board

LDO3 is used for the VGA output, this fixes a regression where the VGA
output on these boards would no longer work.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index d2d0cbd..30ea836 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -32,6 +32,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
-- 
cgit v0.10.2


From 2489a7e9f3055da15a8a8a0e54babf29ff5f6f14 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Wed, 27 Apr 2016 18:44:32 -0400
Subject: omap3: Reduce logic/overo SPL max image size

While the OMAP3 has 64KiB of SRAM, per the TRM the download area is only
from 0x40200000 to 0x4020F000 and exceeding that will cause failure to
boot.  Further, we need to make sure that we don't run into
SRAM_SCRATCH_SPACE_ADDR as once SPL is running we will write values
there and would corrupt our running image.

Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 055dcb7..6c79643 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -34,7 +34,7 @@
 #undef CONFIG_SPL_TEXT_BASE
 #undef CONFIG_SPL_MAX_SIZE
 #define CONFIG_SPL_TEXT_BASE   0x40200000
-#define CONFIG_SPL_MAX_SIZE    (64 * 1024)
+#define CONFIG_SPL_MAX_SIZE    (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
 
 /* Display CPU and Board information */
 
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index c066eae..fbd0c2a 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -12,9 +12,9 @@
 
 #include <configs/ti_omap3_common.h>
 #undef CONFIG_SPL_MAX_SIZE
-#define CONFIG_SPL_MAX_SIZE	(64*1024)
 #undef CONFIG_SPL_TEXT_BASE
 #define CONFIG_SPL_TEXT_BASE	0x40200000
+#define CONFIG_SPL_MAX_SIZE    (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
 
 #define CONFIG_BCH
 
-- 
cgit v0.10.2


From c510f2e436008e55a50b063f2180cb1e63984224 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Thu, 28 Apr 2016 10:07:53 +0800
Subject: video: ipu_common: fix build error

Some toolchains fail to build
"clk->rate = (u64)(clk->parent->rate * 16) / div;"
And the cast usage is wrong.

Use the following code to fix the issue,
"
  do_div(parent_rate, div);
  clk->rate = parent_rate;
"

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 36d4b23..5676a0f 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -352,7 +352,9 @@ static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 	 */
 	__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 
-	clk->rate = (u64)(clk->parent->rate * 16) / div;
+	do_div(parent_rate, div);
+
+	clk->rate = parent_rate;
 
 	return 0;
 }
-- 
cgit v0.10.2


From aaeadd3f7b248aeb1c72c36183ab9c6e77da6ce2 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Wed, 20 Apr 2016 22:48:13 -0300
Subject: mx6ul_evk: Remove CONFIG_SUPPORT_EMMC_BOOT

mx6ul_evk does not come with a eMMC populated, so we should not
define CONFIG_SUPPORT_EMMC_BOOT as it causes SPL to not be able
to boot some brands of SD cards, such as SanDisk microSD HC - 8GB:

U-Boot SPL 2016.05-rc1-28384-g108f841 (Apr 19 2016 - 11:19:11)
Trying to boot from MMC1
spl: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

When CONFIG_SUPPORT_EMMC_BOOT is defined spl_boot_mode() returns
MMCSD_MODE_EMMCBOOT, so remove this option to have a reliable boot
via SD card.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 15976f7..b2ba773 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -45,7 +45,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
 
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 #endif
 
 /* I2C configs */
-- 
cgit v0.10.2


From 7d045170ac1bf512ed148e97432b7a8d772943e9 Mon Sep 17 00:00:00 2001
From: Martin Pietryka <martin.pietryka@chello.at>
Date: Wed, 27 Apr 2016 21:39:15 +0200
Subject: drivers/video/am335x-fb: Add support for 16bpp format

To support 16bpp we just need to change the raster_ctrl register
accordingly. Also 32bpp mode should work as well, but was not tested.
According to the TRM the uppermost byte will be ignored when
LCD_TFT_24BPP_UNPACK is set.

The switch logic is based on the Linux kernel tilcdc driver:
drivers/gpu/drm/tilcdc/tilcdc_crtc.c: lines 407 through 419
(kernel was checked out at commit: bcc981e9ed8)

Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>

diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index 0ec843f..d984435 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -5,7 +5,7 @@
  * minimal framebuffer driver for TI's AM335x SoC to be compatible with
  * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
  *
- * - supporting only 24bit RGB/TFT raster Mode (not using palette)
+ * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
  * - sets up LCD controller as in 'am335x_lcdpanel' struct given
  * - starts output DMA from gd->fb_base buffer
  *
@@ -106,6 +106,8 @@ int lcd_get_size(int *line_length)
 
 int am335xfb_init(struct am335x_lcdpanel *panel)
 {
+	u32 raster_ctrl = 0;
+
 	if (0 == gd->fb_base) {
 		printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
 		return -1;
@@ -115,6 +117,21 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
 		return -1;
 	}
 
+	/* We can already set the bits for the raster_ctrl in this check */
+	switch (panel->bpp) {
+	case 16:
+		break;
+	case 32:
+		raster_ctrl |= LCD_TFT_24BPP_UNPACK;
+		/* fallthrough */
+	case 24:
+		raster_ctrl |= LCD_TFT_24BPP_MODE;
+		break;
+	default:
+		error("am335x-fb: invalid bpp value: %d\n", panel->bpp);
+		return -1;
+	}
+
 	debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
 	      panel->hactive, panel->vactive, panel->bpp,
 	      panel->hfp, panel->hbp, panel->hsw);
@@ -157,8 +174,7 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
 				LCD_HBPMSB(panel->hbp) |
 				LCD_HFPMSB(panel->hfp) |
 				0x0000FF00;	/* clk cycles for ac-bias */
-	lcdhw->raster_ctrl =	LCD_TFT_24BPP_MODE |
-				LCD_TFT_24BPP_UNPACK |
+	lcdhw->raster_ctrl =	raster_ctrl |
 				LCD_PALMODE_RAWDATA |
 				LCD_TFT_MODE |
 				LCD_RASTER_ENABLE;
-- 
cgit v0.10.2


From 3d47b2d741683023de05f08f9adb4bd25c189c46 Mon Sep 17 00:00:00 2001
From: Martin Pietryka <martin.pietryka@chello.at>
Date: Wed, 27 Apr 2016 21:39:16 +0200
Subject: drivers/video/am335x-fb: Properly point framebuffer behind palette

The DMA was outputting the palette on the screen because the base
for the DMA was not after the palette. In addition to that, the ceiling was
also too high, this led that the output on the screen was shifted.

NOTE: According to the TRM, even in 16/24bit mode a palette is required
in the first 32 bytes of the framebuffer.

See also:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/234967/834483#834483

"In this mode, the LCDC will assume all information is data and thus you
need to ensure that the DMA points to the first pixel of data and not the
first entry in the frame buffer which is the beginning of the 512 byte
palette."

Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>

diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index d984435..bb5cc97 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -143,6 +143,8 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
 	/* palette default entry */
 	memset((void *)gd->fb_base, 0, 0x20);
 	*(unsigned int *)gd->fb_base = 0x4000;
+	/* point fb behind palette */
+	gd->fb_base += 0x20;
 
 	/* turn ON display through powercontrol function if accessible */
 	if (0 != panel->panel_power_ctrl)
@@ -154,9 +156,9 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
 	lcdhw->raster_ctrl = 0;
 	lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
 	lcdhw->lcddma_fb0_base = gd->fb_base;
-	lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel) + 0x20;
+	lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
 	lcdhw->lcddma_fb1_base = gd->fb_base;
-	lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel) + 0x20;
+	lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
 	lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 
 	lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
@@ -179,8 +181,6 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
 				LCD_TFT_MODE |
 				LCD_RASTER_ENABLE;
 
-	gd->fb_base += 0x20;	/* point fb behind palette */
-
 	debug("am335x-fb: waiting picture to be stable.\n.");
 	mdelay(panel->pon_delay);
 
-- 
cgit v0.10.2


From 68340966e6766f1add5ab5137693abf02c9f9ab6 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 28 Apr 2016 15:37:13 +0900
Subject: ARM: uniphier: fix boot mode table of PH1-LD20

PH1-LD20 does not have the dedicated boot swap select latch.
Instead, it is controlled from the boot mode select.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
index 100275e..b092c1b 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -43,7 +43,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
 	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
 	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
+	{BOOT_DEVICE_NOR,  "NOR Boot (XECS1)"},
 };
 
 static int get_boot_mode_sel(void)
-- 
cgit v0.10.2


From 1dce5eb9de72eff89a42546186d511f24835816d Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 28 Apr 2016 15:37:14 +0900
Subject: ARM: uniphier: enable Peripherl clock to use UART in SPL

This is needed to use UART on SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
index 37adb37..5201a55 100644
--- a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c
@@ -21,6 +21,10 @@ int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
 	writel(tmp, SC_RSTCTRL7);
 
 	/* provide clocks */
+	tmp = readl(SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_PERI;
+	writel(tmp, SC_CLKCTRL4);
+
 	tmp = readl(SC_CLKCTRL7);
 	tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
 							SC_CLKCTRL7_UMC30;
-- 
cgit v0.10.2


From 5eb4150e84e55057a3504b2cb06d7f5c145c866f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 28 Apr 2016 15:37:15 +0900
Subject: ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20

The System Bus is not available by default on the ROM boot mode of
PH1-LD20.  To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
index dc4064c..a103902 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= early-pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
new file mode 100644
index 0000000..537deaf
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd)
+{
+	/* Comment format:    PAD Name -> Function Name */
+	sg_set_pinsel(0, 0, 8, 4);	/* XECS1  -> XECS1 */
+	sg_set_pinsel(1, 0, 8, 4);	/* ERXW   -> ERXW  */
+	sg_set_pinsel(2, 0, 8, 4);	/* XERWE1 -> XERWE1 */
+	sg_set_pinsel(6, 2, 8, 4);	/* XNFRE  -> XERWE0 */
+	sg_set_pinsel(7, 2, 8, 4);	/* XNFWE  -> ES0 */
+	sg_set_pinsel(8, 2, 8, 4);	/* NFALE  -> ES1 */
+	sg_set_pinsel(9, 2, 8, 4);	/* NFCLE  -> ES2 */
+	sg_set_pinsel(10, 2, 8, 4);	/* NFD0   -> ED0 */
+	sg_set_pinsel(11, 2, 8, 4);	/* NFD1   -> ED1 */
+	sg_set_pinsel(12, 2, 8, 4);	/* NFD2   -> ED2 */
+	sg_set_pinsel(13, 2, 8, 4);	/* NFD3   -> ED3 */
+	sg_set_pinsel(14, 2, 8, 4);	/* NFD4   -> ED4 */
+	sg_set_pinsel(15, 2, 8, 4);	/* NFD5   -> ED5 */
+	sg_set_pinsel(16, 2, 8, 4);	/* NFD6   -> ED6 */
+	sg_set_pinsel(17, 2, 8, 4);	/* NFD7   -> ED7 */
+	sg_set_iectrl_range(0, 2);
+	sg_set_iectrl_range(6, 17);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index f5b3fa8..5a0ebeb 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -90,6 +90,7 @@ int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
 
 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 0ad264c..660ad45 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -13,6 +13,8 @@
 int uniphier_ld20_init(const struct uniphier_board_data *bd)
 {
 	uniphier_sbc_init_savepin(bd);
+	uniphier_pxs2_sbc_init(bd);
+	uniphier_ld20_early_pin_init(bd);
 
 	support_card_reset();
 
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 3c1e92a..236f136 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -9,4 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-savepin.o sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o sbc-pxs2.o
-- 
cgit v0.10.2


From bef4b024e9839ea7afe689b050fc95118eeb0b01 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 28 Apr 2016 15:37:16 +0900
Subject: ARM: uniphier: move pin-mux code into pin_init function

The code in uniphier_sld3_sbc_init() is pin-muxing, so it would
be a better fit in uniphier_sld3_early_pin_init().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
index 22c07fb..6c5d58f 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
+++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
@@ -22,5 +22,7 @@ int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
 	sg_set_pinsel(102, 2, 4, 4);	/* TXD2 */
 #endif
 
+	sg_set_pinsel(99, 1, 4, 4);	/* GPIO26 -> EA24 */
+
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 5a0ebeb..ab0a68d 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -37,7 +37,6 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd);
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
 int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
-int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
 #else
@@ -53,11 +52,6 @@ static inline int uniphier_sbc_init_savepin(
 	return 0;
 }
 
-static inline int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
-	return 0;
-}
-
 static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
 {
 	return 0;
diff --git a/arch/arm/mach-uniphier/init/init-sld3.c b/arch/arm/mach-uniphier/init/init-sld3.c
index 473e0c8..50fcbb0 100644
--- a/arch/arm/mach-uniphier/init/init-sld3.c
+++ b/arch/arm/mach-uniphier/init/init-sld3.c
@@ -15,7 +15,8 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 	uniphier_sld3_bcu_init(bd);
 
 	uniphier_sbc_init_admulti(bd);
-	uniphier_sld3_sbc_init(bd);
+
+	uniphier_sld3_early_pin_init(bd);
 
 	support_card_reset();
 
@@ -34,8 +35,6 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 
 	led_puts("L2");
 
-	uniphier_sld3_early_pin_init(bd);
-
 	led_puts("L3");
 
 #ifdef CONFIG_SPL_SERIAL_SUPPORT
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 236f136..38da253 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= sbc-admulti.o sbc-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= sbc-admulti.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
diff --git a/arch/arm/mach-uniphier/sbc/sbc-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-sld3.c
deleted file mode 100644
index ac9d030..0000000
--- a/arch/arm/mach-uniphier/sbc/sbc-sld3.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
-	sg_set_pinsel(99, 1, 4, 4);	/* GPIO26 -> EA24 */
-
-	return 0;
-}
-- 
cgit v0.10.2


From f188357a155a5b7d6906f081c6e7265f6d6086ec Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 2 May 2016 08:49:53 -0400
Subject: Revert "ti_armv7_common.h: Fix U-Boot location on eMMC"

We cannot change the long standing hard-coded offset for raw boot mode
for everyone to accommodate how Android expects things to be done here.

This reverts commit ef5ebe951bec72631cdbc7cef9079e6c684e5d0b.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 2c7d542..7db0881 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -219,8 +219,8 @@
 #endif
 
 /* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200	/* address 0x40000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300	/* 384 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
 
 /* FAT sd card locations. */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-- 
cgit v0.10.2


From 821c89d38cb6832f162b5b20ec86f07610407c25 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 2 May 2016 10:52:51 -0400
Subject: Revert "omap3: Use raw SPL by default for mmc1"

Unfortunately with this change we now are unable to do FS mode boots
from MMC1 as with the way the code works today we will always load and
assume that the hard-coded raw location contains U-Boot.  Further, we
cannot fix this by just changing other logic to try FS-then-RAW as it
would also make us have to ignore what order the ROM is telling us to
try.

This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index ed9ba7b..0456263 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -111,6 +111,8 @@ void save_omap_boot_params(void)
 	    (boot_device <= MMC_BOOT_DEVICES_END)) {
 		switch (boot_device) {
 		case BOOT_DEVICE_MMC1:
+			boot_mode = MMCSD_MODE_FS;
+			break;
 		case BOOT_DEVICE_MMC2:
 			boot_mode = MMCSD_MODE_RAW;
 			break;
-- 
cgit v0.10.2


From b525556e6325aa71427c0519f36247981cd444df Mon Sep 17 00:00:00 2001
From: Vagrant Cascadian <vagrant@debian.org>
Date: Fri, 15 Apr 2016 13:43:25 -0700
Subject: Revert "rockchip: rk3288: correct sdram setting"

This reverts commit b5788dc0dd9570e98552833767f4373db965985d.

Ram size is incorrectly reported as 512MB on a firefly-rk3288 board
with 2GB of ram. Reverting this patch displays the full amount of ram.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 71330cb..2e21282 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -561,14 +561,14 @@ static void dram_all_config(const struct dram_info *dram,
 			&sdram_params->ch[chan];
 
 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+		sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+		sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
-		sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan);
+		sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
+		sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
 
 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 	}
@@ -720,13 +720,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 		rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 			SYS_REG_RANK_MASK);
 		col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-		bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ;
+		bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
 		cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 				SYS_REG_CS0_ROW_MASK);
 		cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 				SYS_REG_CS1_ROW_MASK);
-		bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-			SYS_REG_BW_MASK);
+		bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+			SYS_REG_BW_MASK;
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
 
-- 
cgit v0.10.2


From 37f23885e4905ff500a8524328aa3084ac11cdb4 Mon Sep 17 00:00:00 2001
From: Ronald Zachariah <rozachar@cisco.com>
Date: Thu, 28 Apr 2016 07:08:34 +0200
Subject: fs: ext4: fix symlink read function

The function ext4fs_read_symlink was unable to handle a symlink
which had target name of exactly 60 characters.

Signed-off-by: Ronald Zachariah <rozachar@cisco.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 84fba76..40b798a 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2040,7 +2040,7 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node)
 	if (!symlink)
 		return 0;
 
-	if (__le32_to_cpu(diro->inode.size) <= 60) {
+	if (__le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) {
 		strncpy(symlink, diro->inode.b.symlink,
 			 __le32_to_cpu(diro->inode.size));
 	} else {
-- 
cgit v0.10.2


From f1ab00fb537251b782147830dd6019087fc75fdc Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 2 May 2016 18:36:07 -0400
Subject: arch/arm/imx-common/Makefile: Update u-boot.uim MKIMAGEFLAGS

We need to be passing -T firmware here and aren't.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index c208628..d34a784 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -68,7 +68,7 @@ SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
 	$(call if_changed,mkimage)
 
 MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
-		-e $(CONFIG_SYS_TEXT_BASE) -C none
+		-e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware
 
 u-boot.uim: u-boot.bin FORCE
 	$(call if_changed,mkimage)
-- 
cgit v0.10.2


From 7a439cadcf3192eb012a2432ca34670b676c74d2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= <andreas.devel@googlemail.com>
Date: Sun, 1 May 2016 03:01:27 +0200
Subject: mkimage: fix argument parsing on BSD systems
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The getopt(3) optstring '-' is a GNU extension which is not available on BSD
systems like OS X.

Remove this dependency by implementing argument parsing in another way. This
will also change the lately introduced '-b' switch behaviour.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/Makefile b/Makefile
index f03fec1..293fad0 100644
--- a/Makefile
+++ b/Makefile
@@ -898,7 +898,7 @@ ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
-	-b $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
diff --git a/doc/mkimage.1 b/doc/mkimage.1
index e0f210a..4b3a255 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -97,8 +97,8 @@ Set XIP (execute in place) flag.
 .B Create FIT image:
 
 .TP
-.BI "\-b
-Specifies that the following arguments are device tree binary files (.dtb).
+.BI "\-b [" "device tree file" "]
+Appends the device tree binary file (.dtb) to the FIT.
 
 .TP
 .BI "\-c [" "comment" "]"
@@ -211,7 +211,7 @@ automatic mode. No .its file is required.
 .B mkimage -f auto -A arm -O linux -T kernel -C none -a 43e00000 -e 0 \\\\
 .br
 .B -c """Kernel 4.4 image for production devices""" -d vmlinuz \\\\
-.B -b /path/to/rk3288-firefly.dtb /path/to/rk3288-jerry.dtb kernel.itb
+.B -b /path/to/rk3288-firefly.dtb -b /path/to/rk3288-jerry.dtb kernel.itb
 .fi
 
 .SH HOMEPAGE
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 2931783..b407aed 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -85,8 +85,8 @@ static void usage(const char *msg)
 		"          -x ==> set XIP (execute in place)\n",
 		params.cmdname);
 	fprintf(stderr,
-		"       %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb_list>] fit-image\n"
-		"           <dtb_list> is used with -f auto, and is a space-separated list of .dtb files\n",
+		"       %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] fit-image\n"
+		"           <dtb> file is used with -f auto, it may occour multiple times.\n",
 		params.cmdname);
 	fprintf(stderr,
 		"          -D => set all options for device tree compiler\n"
@@ -138,7 +138,7 @@ static void process_args(int argc, char **argv)
 
 	expecting = IH_TYPE_COUNT;	/* Unknown */
 	while ((opt = getopt(argc, argv,
-			     "-a:A:bcC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
+			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
 		switch (opt) {
 		case 'a':
 			params.addr = strtoull(optarg, &ptr, 16);
@@ -155,6 +155,12 @@ static void process_args(int argc, char **argv)
 			break;
 		case 'b':
 			expecting = IH_TYPE_FLATDT;
+			if (add_content(expecting, optarg)) {
+				fprintf(stderr,
+					"%s: Out of memory adding content '%s'",
+					params.cmdname, optarg);
+				exit(EXIT_FAILURE);
+			}
 			break;
 		case 'c':
 			params.comment = optarg;
@@ -243,29 +249,14 @@ static void process_args(int argc, char **argv)
 		case 'x':
 			params.xflag++;
 			break;
-		case 1:
-			if (expecting == type || optind == argc) {
-				params.imagefile = optarg;
-				expecting = IH_TYPE_INVALID;
-			} else if (expecting == IH_TYPE_INVALID) {
-				fprintf(stderr,
-					"%s: Unknown content type: use -b before device tree files",
-					params.cmdname);
-				exit(EXIT_FAILURE);
-			} else {
-				if (add_content(expecting, optarg)) {
-					fprintf(stderr,
-						"%s: Out of memory adding content '%s'",
-						params.cmdname, optarg);
-					exit(EXIT_FAILURE);
-				}
-			}
-			break;
 		default:
 			usage("Invalid option");
 		}
 	}
 
+	if (optind < argc && expecting == type)
+		params.imagefile = argv[optind];
+
 	/*
 	 * For auto-generated FIT images we need to know the image type to put
 	 * in the FIT, which is separate from the file's image type (which
-- 
cgit v0.10.2


From 09c2b8f3e39925e5bdff12cb90add09bc9e117d4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= <andreas.devel@googlemail.com>
Date: Sun, 1 May 2016 03:46:16 +0200
Subject: Change my mailaddress
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

I'll switch my mails to my own server, so drop all gmail references.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

diff --git a/.mailmap b/.mailmap
index 5ea9f93..14b5ad7 100644
--- a/.mailmap
+++ b/.mailmap
@@ -10,6 +10,7 @@
 
 Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
+Andreas Bießmann <andreas@biessmann.org>
 Aneesh V <aneesh@ti.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Fabio Estevam <fabio.estevam@nxp.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 27eb8e5..1db8243 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -73,7 +73,7 @@ F:	arch/arm/cpu/armv7/socfpga/
 F:	board/altera/socfpga/
 
 ARM ATMEL AT91
-M:	Andreas Bießmann <andreas.devel@googlemail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
@@ -206,7 +206,7 @@ F:	arch/arm/cpu/armv8/zynqmp/
 F:	arch/arm/include/asm/arch-zynqmp/
 
 AVR32
-M:	Andreas Bießmann <andreas.devel@googlemail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-avr32.git
 F:	arch/avr32/
diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c
index cf10a53..4614d26 100644
--- a/arch/arm/lib/stack.c
+++ b/arch/arm/lib/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2002-2006
diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c
index 9b9800a..f139b91 100644
--- a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c
@@ -2,7 +2,7 @@
  * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
  *
  * (C) Copyright 2011
- * Andreas Bießmann <andreas.devel@googlemail.com>
+ * Andreas Bießmann <andreas@biessmann.org>
  *
  * (C) Copyright 2007-2008
  * Stelian Pop <stelian@popies.net>
diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c
index b0f411b..926d1c9 100644
--- a/arch/arm/mach-at91/arm920t/cpu.c
+++ b/arch/arm/mach-at91/arm920t/cpu.c
@@ -2,7 +2,7 @@
  * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
  *
  * (C) Copyright 2011
- * Andreas Bießmann, andreas.devel@googlemail.com
+ * Andreas Bießmann, andreas@biessmann.org
  * (C) Copyright 2010
  * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
  * (C) Copyright 2009
diff --git a/arch/avr32/cpu/mmc.c b/arch/avr32/cpu/mmc.c
index b7213e4..26ba3a2 100644
--- a/arch/avr32/cpu/mmc.c
+++ b/arch/avr32/cpu/mmc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2004-2006 Atmel Corporation
- * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com>
+ * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/arch/avr32/lib/bootm.c b/arch/avr32/lib/bootm.c
index 1c26f1b..342b9e2 100644
--- a/arch/avr32/lib/bootm.c
+++ b/arch/avr32/lib/bootm.c
@@ -174,7 +174,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	/*
 	 * allow the PREP bootm subcommand, it is required for bootm to work
 	 *
-	 * TODO: Andreas Bießmann <andreas.devel@googlemail.com> refactor the
+	 * TODO: Andreas Bießmann <andreas@biessmann.org> refactor the
 	 * do_bootm_linux() for avr32
 	 */
 	if (flag & BOOTM_STATE_OS_PREP)
diff --git a/arch/avr32/lib/dram_init.c b/arch/avr32/lib/dram_init.c
index 5078e77..79c2455 100644
--- a/arch/avr32/lib/dram_init.c
+++ b/arch/avr32/lib/dram_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
index 1985f03..7eccfe0 100644
--- a/arch/powerpc/lib/stack.c
+++ b/arch/powerpc/lib/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2002-2006
diff --git a/board/atmel/at91rm9200ek/MAINTAINERS b/board/atmel/at91rm9200ek/MAINTAINERS
index d2a479b..b25bc58 100644
--- a/board/atmel/at91rm9200ek/MAINTAINERS
+++ b/board/atmel/at91rm9200ek/MAINTAINERS
@@ -1,5 +1,5 @@
 AT91RM9200EK BOARD
-M:	Andreas Bießmann <andreas.devel@gmail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 F:	board/atmel/at91rm9200ek/
 F:	include/configs/at91rm9200ek.h
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
index 4ca8106..98d76a6 100644
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
+ * (C) Copyright 2010 Andreas Bießmann <andreas@biessmann.org>
  *
  * derived from previous work
  *
diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c
index fbe8e3d..5986ac0 100644
--- a/board/atmel/at91rm9200ek/led.c
+++ b/board/atmel/at91rm9200ek/led.c
@@ -4,7 +4,7 @@
  * Ulf Samuelsson <ulf@atmel.com>
  *
  * (C) Copyright 2010
- * Andreas Bießmann <andreas.devel@gmail.com>
+ * Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/board/atmel/atngw100mkii/MAINTAINERS b/board/atmel/atngw100mkii/MAINTAINERS
index 212363e..54eb1da 100644
--- a/board/atmel/atngw100mkii/MAINTAINERS
+++ b/board/atmel/atngw100mkii/MAINTAINERS
@@ -1,5 +1,5 @@
 ATNGW100MKII BOARD
-M:	Andreas Bießmann <andreas.devel@googlemail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 F:	board/atmel/atngw100mkii/
 F:	include/configs/atngw100mkii.h
diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c
index 8e215d5..68662c4 100644
--- a/board/atmel/atngw100mkii/atngw100mkii.c
+++ b/board/atmel/atngw100mkii/atngw100mkii.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2010 Atmel Corporation
  *
- * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/board/in-circuit/grasshopper/MAINTAINERS b/board/in-circuit/grasshopper/MAINTAINERS
index db8bd0a..4abdea8 100644
--- a/board/in-circuit/grasshopper/MAINTAINERS
+++ b/board/in-circuit/grasshopper/MAINTAINERS
@@ -1,5 +1,5 @@
 GRASSHOPPER BOARD
-M:	Andreas Bießmann <andreas.devel@googlemail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 F:	board/in-circuit/grasshopper/
 F:	include/configs/grasshopper.h
diff --git a/doc/README.at91-soc b/doc/README.at91-soc
index ab3f713..9a9f74e 100644
--- a/doc/README.at91-soc
+++ b/doc/README.at91-soc
@@ -40,7 +40,7 @@ The method for updating
 4. Convert arch, driver and boards file to new SoC
 5. remove legacy code, if all boards and drives are ready
 
-2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>:
+2013-10-30 Andreas Bießmann <andreas@biessmann.org>:
 
 The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
 remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
diff --git a/doc/README.atmel_pmecc b/doc/README.atmel_pmecc
index cc0f73d..274d860 100644
--- a/doc/README.atmel_pmecc
+++ b/doc/README.atmel_pmecc
@@ -30,7 +30,7 @@ Take AT91SAM9X5EK as an example, the board definition file likes:
 
 How to enable PMECC header for direct programmable boot.bin
 -----------------------------------------------------------
-2014-05-19 Andreas Bießmann <andreas.devel@googlemail.com>
+2014-05-19 Andreas Bießmann <andreas@biessmann.org>
 
 The usual way to program SPL into NAND flash is to use the SAM-BA Atmel tool.
 This however is often not usable when doing field updates. To be able to
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 1201d4a..1d6f4fc 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -11,7 +11,7 @@ alias u-boot uboot
 # Maintainer aliases.  Use the same alias here as patchwork to keep
 # things simple and easy to look up/coordinate.
 alias aaribaud       Albert Aribaud <albert.u.boot@aribaud.net>
-alias abiessmann     Andreas Bießmann <andreas.devel@googlemail.com>
+alias abiessmann     Andreas Bießmann <andreas@biessmann.org>
 alias abrodkin       Alexey Brodkin <alexey.brodkin@synopsys.com>
 alias afleming       Andy Fleming <afleming@gmail.com>
 alias ag             Anatolij Gustschin <agust@denx.de>
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index fb12632..dfa2d93 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2006 Atmel Corporation
  *
- * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
  *
  * Configuration settings for the AVR32 Network Gateway
  *
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
index 6cbae45..3a75674 100644
--- a/include/linux/mtd/omap_gpmc.h
+++ b/include/linux/mtd/omap_gpmc.h
@@ -2,7 +2,7 @@
  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
  * Rohit Choraria <rohitkc@ti.com>
  *
- * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
+ * (C) Copyright 2013 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/lib/hang.c b/lib/hang.c
index 8db268e..9246e12 100644
--- a/lib/hang.c
+++ b/lib/hang.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2013
- * Andreas Bießmann <andreas.devel@googlemail.com>
+ * Andreas Bießmann <andreas@biessmann.org>
  *
  * This file consolidates all the different hang() functions implemented in
  * u-boot.
diff --git a/tools/atmel_pmecc_params.c b/tools/atmel_pmecc_params.c
index 8eaf27f..eb97229 100644
--- a/tools/atmel_pmecc_params.c
+++ b/tools/atmel_pmecc_params.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2014 Andreas Bießmann <andreas.devel@googlemail.com>
+ * (C) Copyright 2014 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/tools/atmelimage.c b/tools/atmelimage.c
index 6b5603e..9b3600d 100644
--- a/tools/atmelimage.c
+++ b/tools/atmelimage.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2014
- * Andreas Bießmann <andreas.devel@googlemail.com>
+ * Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-- 
cgit v0.10.2


From eae4b2b67bc8c68e2440616a447ca6c6898ad188 Mon Sep 17 00:00:00 2001
From: Vagrant Cascadian <vagrant@debian.org>
Date: Sat, 30 Apr 2016 19:18:00 -0700
Subject: Fix spelling of "occurred".

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
index 3180a76..a7b3519 100644
--- a/board/bf533-ezkit/flash.c
+++ b/board/bf533-ezkit/flash.c
@@ -320,7 +320,7 @@ int poll_toggle_bit(long lOffset)
 		}
 		timeout--;
 	}
-	printf("Time out occured \n");
+	printf("Time out occurred \n");
 	if (timeout < 0)
 		return FLASH_FAIL;
 }
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 7c7690f..1bd2fbf 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -777,7 +777,7 @@ void print_pip405_info (void)
 			((sysman & 0x10) == 0x10) ? "" : "not ");
 	printf ("INIT asserts %sINT1# (NMI)\n",
 			((sysman & 0x20) == 0x20) ? "" : "not ");
-	printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
+	printf ("INIT occurred %d\n", (sysman >> 6) & 0x1);
 	printf ("SER1 is routed to %s\n",
 			((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
 	printf ("COM2 is routed to %s\n",
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
index 9d2d5a8..dc22ee4 100644
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -72,7 +72,7 @@ static int spi_transmit(unsigned char data)
 	spi->dr = data;
 	/* wait for SPI transmission completed */
 	while (!(spi->sr & 0x80)) {
-		if (spi->sr & 0x40) {	/* if write collision occured */
+		if (spi->sr & 0x40) {	/* if write collision occurred */
 			int dummy;
 
 			/* do dummy read to clear status register */
diff --git a/cmd/fdc.c b/cmd/fdc.c
index 058ae89..d2281ab 100644
--- a/cmd/fdc.c
+++ b/cmd/fdc.c
@@ -189,7 +189,7 @@ int wait_for_fdc_int(void)
 	while((read_fdc_reg(FDC_SRA)&0x80)==0) {
 		timeout--;
 		udelay(10);
-		if(timeout==0) /* timeout occured */
+		if(timeout==0) /* timeout occurred */
 			return false;
 	}
 	return true;
@@ -205,7 +205,7 @@ int read_fdc_byte(void)
 		/* direction out and ready */
 		udelay(10);
 		timeout--;
-		if(timeout==0) /* timeout occured */
+		if(timeout==0) /* timeout occurred */
 			return -1;
 	}
 	return read_fdc_reg(FDC_FIFO);
@@ -235,7 +235,7 @@ int write_fdc_byte(unsigned char val)
 		timeout--;
 		udelay(10);
 		fdc_need_more_output();
-		if(timeout==0) /* timeout occured */
+		if(timeout==0) /* timeout occurred */
 			return false;
 	}
 	write_fdc_reg(FDC_FIFO,val);
@@ -395,7 +395,7 @@ int fdc_terminate(FDC_COMMAND_STRUCT *pCMD)
 	int i;
 	for(i=0;i<100;i++)
 		udelay(500); /* wait 500usec for fifo overrun */
-	while((read_fdc_reg(FDC_SRA)&0x80)==0x00); /* wait as long as no int has occured */
+	while((read_fdc_reg(FDC_SRA)&0x80)==0x00); /* wait as long as no int has occurred */
 	for(i=0;i<7;i++) {
 		pCMD->result[i]=(unsigned char)read_fdc_byte();
 	}
diff --git a/common/kgdb.c b/common/kgdb.c
index d357463..daf53be 100644
--- a/common/kgdb.c
+++ b/common/kgdb.c
@@ -326,7 +326,7 @@ handle_exception (struct pt_regs *regs)
 		return (0);
 	}
 
-	/* probably should check which exception occured as well */
+	/* probably should check which exception occurred as well */
 	if (longjmp_on_fault) {
 		longjmp_on_fault = 0;
 		kgdb_longjmp(error_jmp_buf, KGDBERR_MEMFAULT);
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e6a2cdb..4f59802 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -475,7 +475,7 @@ static int usb_scan_port(struct usb_device_scan *usb_scan)
 			return 0;
 
 		/* Otherwise the device will get removed */
-		printf("Port %d over-current occured %d times\n", i + 1,
+		printf("Port %d over-current occurred %d times\n", i + 1,
 		       hub->overcurrent_count[i]);
 	}
 
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h
index cb3fb24..8cb0886 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -120,7 +120,7 @@
 #define MV_NO_RESOURCE	(0x13)	/* Resource not available (memory ...)   */
 #define MV_FULL		(0x14)	/* Item is full (Queue or table etc...)  */
 #define MV_EMPTY	(0x15)	/* Item is empty (Queue or table etc...) */
-#define MV_INIT_ERROR	(0x16)	/* Error occured while INIT process      */
+#define MV_INIT_ERROR	(0x16)	/* Error occurred while INIT process      */
 #define MV_HW_ERROR	(0x17)	/* Hardware error                        */
 #define MV_TX_ERROR	(0x18)	/* Transmit operation not succeeded      */
 #define MV_RX_ERROR	(0x19)	/* Recieve operation not succeeded       */
diff --git a/drivers/ddr/marvell/axp/ddr3_hw_training.h b/drivers/ddr/marvell/axp/ddr3_hw_training.h
index cffa7c4..343a6b6 100644
--- a/drivers/ddr/marvell/axp/ddr3_hw_training.h
+++ b/drivers/ddr/marvell/axp/ddr3_hw_training.h
@@ -41,7 +41,7 @@
 #define MV_NO_RESOURCE	(0x13)	/* Resource not available (memory ...)   */
 #define MV_FULL		(0x14)	/* Item is full (Queue or table etc...)  */
 #define MV_EMPTY	(0x15)	/* Item is empty (Queue or table etc...) */
-#define MV_INIT_ERROR	(0x16)	/* Error occured while INIT process      */
+#define MV_INIT_ERROR	(0x16)	/* Error occurred while INIT process      */
 #define MV_HW_ERROR	(0x17)	/* Hardware error                        */
 #define MV_TX_ERROR	(0x18)	/* Transmit operation not succeeded      */
 #define MV_RX_ERROR	(0x19)	/* Recieve operation not succeeded       */
diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
index 9af496b..11f29d9 100644
--- a/drivers/i2c/kona_i2c.c
+++ b/drivers/i2c/kona_i2c.c
@@ -381,7 +381,7 @@ static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
 		return -EREMOTEIO;
 	}
 
-	/* Check if a timeout occured */
+	/* Check if a timeout occurred */
 	if (!time_left) {
 		printf("completion timed out\n");
 		return -EREMOTEIO;
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 4814fa2..6a45d28 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -106,7 +106,7 @@ static uint32_t gen_true_ecc(uint8_t *ecc_buf)
 
 /*
  * omap_correct_data - Compares the ecc read from nand spare area with ECC
- * registers values and corrects one bit error if it has occured
+ * registers values and corrects one bit error if it has occurred
  * Further details can be had from OMAP TRM and the following selected links:
  * http://en.wikipedia.org/wiki/Hamming_code
  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
@@ -479,7 +479,7 @@ static void omap_reverse_list(u8 *list, unsigned int length)
 
 /*
  * omap_correct_data_bch - Compares the ecc read from nand spare area
- * with ECC registers values and corrects one bit error if it has occured
+ * with ECC registers values and corrects one bit error if it has occurred
  *
  * @mtd:	MTD device structure
  * @dat:	page data
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index 3c30f42..bc52ed3 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -1726,7 +1726,7 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
 	mtdcr (MAL0_RXDEIR, 0x80000000);
 
 #ifdef INFO_4XX_ENET
-	printf("\nMAL error occured.... ISR = %lx UIC = = %lx	MAL_DEF = %lx  MAL_ERR= %lx\n",
+	printf("\nMAL error occurred.... ISR = %lx UIC = = %lx	MAL_DEF = %lx  MAL_ERR= %lx\n",
 	       isr, uic, maldef, mal_errr);
 #endif
 
@@ -1740,7 +1740,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr)
 {
 	EMAC_4XX_HW_PST hw_p = dev->priv;
 
-	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
+	printf ("EMAC%d error occurred.... ISR = %lx\n", hw_p->devnum, isr);
 	out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
 }
 
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index 59ea11c..611eabb 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -381,7 +381,7 @@ static int enc_phy_link_wait(enc_dev_t *enc)
 		udelay(1000);
 	}
 
-	/* timeout occured */
+	/* timeout occurred */
 	printf("%s: link down\n", enc->dev->name);
 	return 1;
 }
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
index 71d133c..67bf140 100644
--- a/drivers/net/ne2000_base.c
+++ b/drivers/net/ne2000_base.c
@@ -582,7 +582,7 @@ dp83902a_Overflow(void)
 	/*
 	 * Read in as many packets as we can and acknowledge any and receive
 	 * interrupts. Since the buffer has overflowed, a receive event of
-	 * some kind will have occured.
+	 * some kind will have occurred.
 	 */
 	dp83902a_RxEvent();
 	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
@@ -592,7 +592,7 @@ dp83902a_Overflow(void)
 	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
 
 	/*
-	 * If a transmit command was issued, but no transmit event has occured,
+	 * If a transmit command was issued, but no transmit event has occurred,
 	 * restart it here.
 	 */
 	DP_IN(base, DP_ISR, isr);
diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c
index b3e178a..ad5ea7a 100644
--- a/drivers/usb/gadget/mpc8xx_udc.c
+++ b/drivers/usb/gadget/mpc8xx_udc.c
@@ -170,7 +170,7 @@ int udc_init (void)
 
 /* udc_irq
  *
- * Poll for whatever events may have occured
+ * Poll for whatever events may have occurred
  */
 void udc_irq (void)
 {
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 9a3b61a..4947936 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -73,9 +73,9 @@ static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
 }
 
 /*
- * This function checks if RxStall has occured on the endpoint. If a RxStall
- * has occured, the RxStall is cleared and 1 is returned. If RxStall has
- * not occured, 0 is returned.
+ * This function checks if RxStall has occurred on the endpoint. If a RxStall
+ * has occurred, the RxStall is cleared and 1 is returned. If RxStall has
+ * not occurred, 0 is returned.
  */
 static u8 check_stall(u8 ep, u8 dir_out)
 {
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 652cf3b..fcf331b 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -388,14 +388,14 @@ struct fb_cursor_user {
 #define FB_EVENT_GET_CONSOLE_MAP	0x07
 /*	CONSOLE-SPECIFIC: set console to framebuffer mapping */
 #define FB_EVENT_SET_CONSOLE_MAP	0x08
-/*	A hardware display blank change occured */
+/*	A hardware display blank change occurred */
 #define FB_EVENT_BLANK			0x09
 /*	Private modelist is to be replaced */
 #define FB_EVENT_NEW_MODELIST		0x0A
 /*	The resolution of the passed in fb_info about to change and
 	all vc's should be changed	   */
 #define FB_EVENT_MODE_CHANGE_ALL	0x0B
-/*	A software display blank change occured */
+/*	A software display blank change occurred */
 #define FB_EVENT_CONBLANK		0x0C
 /*	Get drawing requirements	*/
 #define FB_EVENT_GET_REQ		0x0D
diff --git a/include/test/ut.h b/include/test/ut.h
index da7c1a9..85434d7 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -17,9 +17,9 @@ struct unit_test_state;
  * ut_fail() - Record failure of a unit test
  *
  * @uts: Test state
- * @fname: Filename where the error occured
- * @line: Line number where the error occured
- * @func: Function name where the error occured
+ * @fname: Filename where the error occurred
+ * @line: Line number where the error occurred
+ * @func: Function name where the error occurred
  * @cond: The condition that failed
  */
 void ut_fail(struct unit_test_state *uts, const char *fname, int line,
@@ -29,9 +29,9 @@ void ut_fail(struct unit_test_state *uts, const char *fname, int line,
  * ut_failf() - Record failure of a unit test
  *
  * @uts: Test state
- * @fname: Filename where the error occured
- * @line: Line number where the error occured
- * @func: Function name where the error occured
+ * @fname: Filename where the error occurred
+ * @line: Line number where the error occurred
+ * @func: Function name where the error occurred
  * @cond: The condition that failed
  * @fmt: printf() format string for the error, followed by args
  */
diff --git a/include/usbdevice.h b/include/usbdevice.h
index da5af6e..f27e17f 100644
--- a/include/usbdevice.h
+++ b/include/usbdevice.h
@@ -438,7 +438,7 @@ typedef enum usb_device_event {
 	DEVICE_HUB_RESET,	/* bi  - bus has been unplugged */
 	DEVICE_DESTROY,		/* bi  - device instance should be destroyed */
 
-	DEVICE_HOTPLUG,		/* bi  - a hotplug event has occured */
+	DEVICE_HOTPLUG,		/* bi  - a hotplug event has occurred */
 
 	DEVICE_FUNCTION_PRIVATE,	/* function - private */
 
-- 
cgit v0.10.2


From f9f9d2d625056b674145b6773fe2d91852e4a7fa Mon Sep 17 00:00:00 2001
From: "matwey.kornilov@gmail.com" <matwey.kornilov@gmail.com>
Date: Sun, 1 May 2016 19:58:31 +0300
Subject: config: am335x_evm: detect BoneGreen using BBG1

Since 770e68c0a37fded897d4bdda661614fc81cb33d2
BoneGreen is detected in board_late_init as board_name 'BBG1'

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index cd8923d..16935a1 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -162,12 +162,9 @@
 		"if test $board_name = A335BONE; then " \
 			"setenv fdtfile am335x-bone.dtb; fi; " \
 		"if test $board_name = A335BNLT; then " \
-			"if test $board_rev = BBG1; then " \
-				"setenv fdtfile am335x-bonegreen.dtb; " \
-			"else " \
-				"setenv fdtfile am335x-boneblack.dtb; " \
-			"fi; " \
-		"fi; " \
+			"setenv fdtfile am335x-boneblack.dtb; fi; " \
+		"if test $board_name = BBG1; then " \
+			"setenv fdtfile am335x-bonegreen.dtb; fi; " \
 		"if test $board_name = A33515BB; then " \
 			"setenv fdtfile am335x-evm.dtb; fi; " \
 		"if test $board_name = A335X_SK; then " \
-- 
cgit v0.10.2


From 925c97c248527391de32c2926f7e1911850fd4b0 Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Fri, 29 Apr 2016 22:00:11 +0200
Subject: tools: env: fix config file loading in env library

env library is broken as the config file pointer is only initialized
in main(). When running in the env library parse_config() fails:

  Cannot parse config file '(null)': Bad address

Ensure that config file pointer is always initialized.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 1420ac5..06cf63d 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1325,6 +1325,9 @@ static int parse_config ()
 	struct stat st;
 
 #if defined(CONFIG_FILE)
+	if (!common_args.config_file)
+		common_args.config_file = CONFIG_FILE;
+
 	/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
 	if (get_config(common_args.config_file)) {
 		fprintf(stderr, "Cannot parse config file '%s': %m\n",
-- 
cgit v0.10.2


From 4c1dc1a90fb60c2e5f28351b6ff2ae187dc587ef Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 17:12:24 -0600
Subject: fit_image: Fix a double close() on the error path

There is an extra close() call which is not needed.

Reported-by: Coverity (CID: 143065)
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/fit_image.c b/tools/fit_image.c
index ddefa72..0551572 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -343,7 +343,6 @@ static int fit_build(struct image_tool_params *params, const char *fname)
 	if (ret != size) {
 		fprintf(stderr, "%s: Can't write %s: %s\n",
 			params->cmdname, fname, strerror(errno));
-		close(fd);
 		goto err;
 	}
 	close(fd);
-- 
cgit v0.10.2


From fd2d1e0d47d585eac936a7239eb2bdad7e07a8cc Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 28 Apr 2016 09:08:18 +0200
Subject: kbuild: Do not append dtb for OF_EMBED case

dtb is already included in binary that's why there is no need to replace
u-boot-spl.bin with u-boot-spl-dtb.bin. This is only needed for
OF_SEPARATE is enabled. Only copy -nodtb.bin version which is straight
output from objcopy -O binary.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 4424284..ec8d8f1 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -165,7 +165,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 quiet_cmd_copy = COPY    $@
       cmd_copy = cp $< $@
 
-ifeq ($(CONFIG_SPL_OF_CONTROL),y)
+ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE),yy)
 $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \
 		$(obj)/$(SPL_BIN).dtb FORCE
 	$(call if_changed,cat)
-- 
cgit v0.10.2


From 58abb988ce24525474f0d515d2a36c1b3acf893f Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Wed, 20 Apr 2016 22:48:13 -0300
Subject: mx6ul_evk: Remove CONFIG_SUPPORT_EMMC_BOOT

mx6ul_evk does not come with a eMMC populated, so we should not
define CONFIG_SUPPORT_EMMC_BOOT as it causes SPL to not be able
to boot some brands of SD cards, such as SanDisk microSD HC - 8GB:

U-Boot SPL 2016.05-rc1-28384-g108f841 (Apr 19 2016 - 11:19:11)
Trying to boot from MMC1
spl: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

When CONFIG_SUPPORT_EMMC_BOOT is defined spl_boot_mode() returns
MMCSD_MODE_EMMCBOOT, so remove this option to have a reliable boot
via SD card.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 15976f7..b2ba773 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -45,7 +45,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
 
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 #endif
 
 /* I2C configs */
-- 
cgit v0.10.2


From a6e7b7744e158c4c02f91fcbf991845cad4dc6e3 Mon Sep 17 00:00:00 2001
From: Mario Six <six@gdsys.de>
Date: Wed, 20 Apr 2016 10:44:52 +0200
Subject: i2c/eeprom: Always define I2C_RXTX_LEN

I2C_RXTX_LEN from include/i2c.h is not defined if CONFIG_DM_I2C is
enabled. This leads to a compilation error on boards that enable both
CONFIG_CMD_EEPROM and CONFIG_DM_I2C.

To avoid this, we define I2C_RXTX_LEN in cmd/eeprom.c if it is not
already defined.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 571240a..e5457ba 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -37,6 +37,10 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	8
 #endif
 
+#ifndef	I2C_RXTX_LEN
+#define I2C_RXTX_LEN	128
+#endif
+
 #define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
 #define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))
 
-- 
cgit v0.10.2


From 8edeac86db306482b9bcb860d572320a8c3ed95d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= <andreas@biessmann.org>
Date: Tue, 3 May 2016 15:17:03 +0200
Subject: mkimage: fix generation of FIT image
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 7a439cadcf3192eb012a2432ca34670b676c74d2 broke generation of SPL
loadable FIT images (CONFIG_SPL_LOAD_FIT).
Fix it by removing the unnecessary storage of expected image type. This was a
left over of the previous implementation. It is not longer necessary since the
mkimage -b switch always has one parameter.

Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index b407aed..93d1c16 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -133,10 +133,8 @@ static void process_args(int argc, char **argv)
 	char *ptr;
 	int type = IH_TYPE_INVALID;
 	char *datafile = NULL;
-	int expecting;
 	int opt;
 
-	expecting = IH_TYPE_COUNT;	/* Unknown */
 	while ((opt = getopt(argc, argv,
 			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
 		switch (opt) {
@@ -154,8 +152,7 @@ static void process_args(int argc, char **argv)
 				usage("Invalid architecture");
 			break;
 		case 'b':
-			expecting = IH_TYPE_FLATDT;
-			if (add_content(expecting, optarg)) {
+			if (add_content(IH_TYPE_FLATDT, optarg)) {
 				fprintf(stderr,
 					"%s: Out of memory adding content '%s'",
 					params.cmdname, optarg);
@@ -238,7 +235,6 @@ static void process_args(int argc, char **argv)
 				show_image_types();
 				usage("Invalid image type");
 			}
-			expecting = type;
 			break;
 		case 'v':
 			params.vflag++;
@@ -254,7 +250,8 @@ static void process_args(int argc, char **argv)
 		}
 	}
 
-	if (optind < argc && expecting == type)
+	/* The last parameter is expected to be the imagefile */
+	if (optind < argc)
 		params.imagefile = argv[optind];
 
 	/*
-- 
cgit v0.10.2


From e7fbcbc2566ab4bbcb07889a5791972ac49fa407 Mon Sep 17 00:00:00 2001
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Date: Tue, 3 May 2016 08:59:24 +0200
Subject: igep00x0: Use the SRAM available for SPL.

Move CONFIG_SPL_TEXT_BASE down to 0x40200000 and set CONFIG_SPL_MAX_SIZE
to (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE), so that it's clear
what the limit is.

This will also help some compilers to fit all the code into the allocated
space.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 5da50a5..9bd8915 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -19,6 +19,13 @@
 #include <configs/ti_omap3_common.h>
 #include <asm/mach-types.h>
 
+/* SRAM starts at 0x40200000 and ends at 0x4020FFFF (64KB) */
+#undef CONFIG_SPL_MAX_SIZE
+#undef CONFIG_SPL_TEXT_BASE
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_TEXT_BASE		0x40200000
+
 /*
  * Display CPU and Board information
  */
-- 
cgit v0.10.2


From 559019894b8db38a2cf3f74bed78be505d4f9a27 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 14:53:33 +0200
Subject: usb: dwc2: Pass private data into dwc_otg_core_init()

Pass the whole bulk of private data instead of just the regs,
since the private data will soon contain important configuration
flags.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index b2f4bc6..637b6c0 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -252,8 +252,9 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
  *
  * @param regs Programming view of the DWC_otg controller
  */
-static void dwc_otg_core_init(struct dwc2_core_regs *regs)
+static void dwc_otg_core_init(struct dwc2_priv *priv)
 {
+	struct dwc2_core_regs *regs = priv->regs;
 	uint32_t ahbcfg = 0;
 	uint32_t usbcfg = 0;
 	uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
@@ -1056,7 +1057,7 @@ static int dwc2_init_common(struct dwc2_priv *priv)
 		return -ENODEV;
 	}
 
-	dwc_otg_core_init(regs);
+	dwc_otg_core_init(priv);
 	dwc_otg_core_host_init(regs);
 
 	clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
-- 
cgit v0.10.2


From 618da5630b5629d1c506be17f642502b483dab1a Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 14:55:57 +0200
Subject: usb: dwc2: Pull Ext VBUS macro from dwc_otg_core_init()

Introduce a boolean flag in the dwc2 controller private data and set
it according to the macro (for now) instead of having this macro
directly in the dwc_otg_core_init(). This will let us configure the
flag from DT or such later on, if needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 637b6c0..5673220 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -39,6 +39,7 @@ struct dwc2_priv {
 	u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
 	struct dwc2_core_regs *regs;
 	int root_hub_devnum;
+	bool ext_vbus;
 };
 
 #ifndef CONFIG_DM_USB
@@ -263,13 +264,13 @@ static void dwc_otg_core_init(struct dwc2_priv *priv)
 	usbcfg = readl(&regs->gusbcfg);
 
 	/* Program the ULPI External VBUS bit if needed */
-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
-	usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
-		   DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
-		   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
-#else
-	usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
-#endif
+	if (priv->ext_vbus) {
+		usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
+			   DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
+			   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
+	} else {
+		usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+	}
 
 	/* Set external TS Dline pulsing */
 #ifdef CONFIG_DWC2_TS_DLINE
@@ -1057,6 +1058,12 @@ static int dwc2_init_common(struct dwc2_priv *priv)
 		return -ENODEV;
 	}
 
+#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+	priv->ext_vbus = 1;
+#else
+	priv->ext_vbus = 0;
+#endif
+
 	dwc_otg_core_init(priv);
 	dwc_otg_core_host_init(regs);
 
-- 
cgit v0.10.2


From b4fbd089e4b7ead53d4a27148f6df9c18572b1ce Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 14:58:49 +0200
Subject: usb: dwc2: Make OC protection configurable

Introduce a new flag in the controller private data, which allows selectively
disabling the OC protection. Use the standard 'disable-over-current' OF prop
to set this flag. This OC protection must be disabled on EBV SoCrates rev 1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 5673220..0c4adaf 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -18,6 +18,8 @@
 
 #include "dwc2.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Use only HC channel 0. */
 #define DWC2_HC_CHANNEL			0
 
@@ -40,6 +42,7 @@ struct dwc2_priv {
 	struct dwc2_core_regs *regs;
 	int root_hub_devnum;
 	bool ext_vbus;
+	bool oc_disable;
 };
 
 #ifndef CONFIG_DM_USB
@@ -265,9 +268,11 @@ static void dwc_otg_core_init(struct dwc2_priv *priv)
 
 	/* Program the ULPI External VBUS bit if needed */
 	if (priv->ext_vbus) {
-		usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
-			   DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
-			   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
+		usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+		if (!priv->oc_disable) {
+			usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
+				  DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
+		}
 	} else {
 		usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 	}
@@ -1177,6 +1182,7 @@ static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 {
 	struct dwc2_priv *priv = dev_get_priv(dev);
+	const void *prop;
 	fdt_addr_t addr;
 
 	addr = dev_get_addr(dev);
@@ -1184,6 +1190,11 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	priv->regs = (struct dwc2_core_regs *)addr;
 
+	prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "disable-over-current",
+			   NULL);
+	if (prop)
+		priv->oc_disable = true;
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From e96e064f51139c4af39f14499564ef76e40bbc29 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 26 Apr 2016 03:02:35 +0200
Subject: usb: dwc2: Init desc_before_addr

Initialize desc_before_addr, otherwise the USB core won't send the
first 64B Get Device Descriptor request in common/usb.c function
usb_setup_descriptor() . There are some USB devices which expect
this sequence and otherwise can misbehave.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 0c4adaf..30b51b3 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -1201,6 +1201,9 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 static int dwc2_usb_probe(struct udevice *dev)
 {
 	struct dwc2_priv *priv = dev_get_priv(dev);
+	struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
+
+	bus_priv->desc_before_addr = true;
 
 	return dwc2_init_common(priv);
 }
-- 
cgit v0.10.2


From a434fd1d282fd32d81296c6d4c2e0911f6e488b3 Mon Sep 17 00:00:00 2001
From: Lev Iserovich <Lev.Iserovich@deshawresearch.com>
Date: Thu, 7 Jan 2016 18:04:16 -0500
Subject: fdt: fix setting MAC addresses for multiple interfaces

For multiple ethernet interfaces the FDT offset of '/aliases' will change as we
are adding MAC addresses to the FDT.
Therefore only the first interface ('ethernet0') will get properly updated in
the FDT, with the rest getting FDT errors when we try to set their MAC address.

Signed-off-by: Lev Iserovich <iserovil@deshawresearch.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/common/fdt_support.c b/common/fdt_support.c
index ced119e..42e5d8a 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -467,23 +467,31 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size)
 
 void fdt_fixup_ethernet(void *fdt)
 {
-	int node, i, j;
+	int i, j, prop;
 	char *tmp, *end;
 	char mac[16];
 	const char *path;
 	unsigned char mac_addr[6];
 	int offset;
 
-	node = fdt_path_offset(fdt, "/aliases");
-	if (node < 0)
+	if (fdt_path_offset(fdt, "/aliases") < 0)
 		return;
 
-	for (offset = fdt_first_property_offset(fdt, node);
-	     offset > 0;
-	     offset = fdt_next_property_offset(fdt, offset)) {
+	/* Cycle through all aliases */
+	for (prop = 0; ; prop++) {
 		const char *name;
 		int len = strlen("ethernet");
 
+		/* FDT might have been edited, recompute the offset */
+		offset = fdt_first_property_offset(fdt,
+			fdt_path_offset(fdt, "/aliases"));
+		/* Select property number 'prop' */
+		for (i = 0; i < prop; i++)
+			offset = fdt_next_property_offset(fdt, offset);
+
+		if (offset < 0)
+			break;
+
 		path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
 		if (!strncmp(name, "ethernet", len)) {
 			i = trailing_strtol(name);
-- 
cgit v0.10.2


From 31a48cf4e158160e0482415457ef0f69f079368d Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Mon, 28 Mar 2016 14:11:05 +0530
Subject: drivers: net: ldpaa: Memset pools_params as "0" before use

Memset pools_params as "0" to avoid garbage value in dpni_set_pools.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index bc7f8bb..75b2b6b 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -920,6 +920,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
 	struct dpni_tx_conf_cfg tx_conf_cfg;
 	int err = 0;
 
+	memset(&pools_params, 0, sizeof(pools_params));
 	pools_params.num_dpbp = 1;
 	pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id;
 	pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE;
-- 
cgit v0.10.2


From 0299cee53014f12a60c5b7d317eb2e6ea97c530d Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Wed, 13 Apr 2016 16:38:01 -0700
Subject: net: fix vlan validation

VLAN identifiers are 12-bit decimal numbers, not IP addresses.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/include/env_flags.h b/include/env_flags.h
index 9e87e1b..0dcec06 100644
--- a/include/env_flags.h
+++ b/include/env_flags.h
@@ -57,8 +57,8 @@ enum env_flags_varaccess {
 	"gatewayip:i," \
 	"netmask:i," \
 	"serverip:i," \
-	"nvlan:i," \
-	"vlan:i," \
+	"nvlan:d," \
+	"vlan:d," \
 	"dnsip:i,"
 #else
 #define ETHADDR_FLAGS
-- 
cgit v0.10.2


From 700877a62bfa88ef6e0267749db49f4dc63e2ea2 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Wed, 13 Apr 2016 16:38:02 -0700
Subject: net: increase maximum frame size to accomediate VLAN packets

Ethernet packages with IEEE 802.1Q VLAN support may be up to 1522
bytes long. Increase the default size used to allocate packet
storage by 4 bytes. While at it, let git care about history and
rewrite the comment to represent the situation today only.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/include/net.h b/include/net.h
index 1fb4194..05800c4 100644
--- a/include/net.h
+++ b/include/net.h
@@ -465,20 +465,14 @@ struct icmp_hdr {
 #define IP_ICMP_HDR_SIZE	(IP_HDR_SIZE + ICMP_HDR_SIZE)
 
 /*
- * Maximum packet size; used to allocate packet storage.
- * TFTP packets can be 524 bytes + IP header + ethernet header.
- * Lets be conservative, and go for 38 * 16.  (Must also be
- * a multiple of 32 bytes).
- */
-/*
- * AS.HARNOIS : Better to set PKTSIZE to maximum size because
- * traffic type is not always controlled
- * maximum packet size =  1518
+ * Maximum packet size; used to allocate packet storage. Use
+ * the maxium Ethernet frame size as specified by the Ethernet
+ * standard including the 802.1Q tag (VLAN tagging).
+ * maximum packet size =  1522
  * maximum packet size and multiple of 32 bytes =  1536
  */
-#define PKTSIZE			1518
+#define PKTSIZE			1522
 #define PKTSIZE_ALIGN		1536
-/*#define PKTSIZE		608*/
 
 /*
  * Maximum receive ring size; that is, the number of packets
-- 
cgit v0.10.2


From b38eaec53570821043c94ad44eabcb23747d9969 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Tue, 3 May 2016 19:52:49 -0400
Subject: include/configs: Numerous typo fixes: "controler" -> "controller".

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 94c8253..5249751 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -83,7 +83,7 @@
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 3a73379..aaddfca 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -85,7 +85,7 @@
 
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #if defined(CONFIG_PCI)
-#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 4d14c8b..1e5b501 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -92,7 +92,7 @@
 
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #ifdef CONFIG_PCI
-#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 8cc7f02..03f17f9 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -51,9 +51,9 @@
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 6202dff..26d92da 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -25,9 +25,9 @@
 
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index dd07dc4..5de8b19 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -34,7 +34,7 @@
 
 #define CONFIG_PCI		/* enable any pci type devices */
 #define CONFIG_PCI1		/* PCI controller 1 */
-#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 9144f32..8c4e5e2 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -40,9 +40,9 @@
 
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 88ca4f3..e7f01d0 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -45,7 +45,7 @@
 #define CONFIG_SYS_SCRATCH_VA	0xc0000000
 
 #define CONFIG_PCI		1	/* Enable PCI/PCIE*/
-#define CONFIG_PCI1		1	/* PCI controler 1 */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 3569849..2f94c82 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,8 +46,8 @@
 #define CONFIG_SRIO1			/* SRIO port 1 */
 
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (ULI bridge) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 5719e86..f398b37 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -176,8 +176,8 @@
 
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #if defined(CONFIG_PCI)
-#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 8b29951..7457dfc 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -134,9 +134,9 @@
 
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3			/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3			/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index fcbe288..a10310e 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -33,9 +33,9 @@
 #define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
-#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2		/* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3		/* PCIE controler 3 (slot 3) */
+#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		/* PCIE controller 3 (slot 3) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b7a08e0..b3fb38c 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -52,9 +52,9 @@
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 12260aa..ef2ede4 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -577,9 +577,9 @@ unsigned long get_board_ddr_clk(void);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 #define CONFIG_PCI_INDIRECT_BRIDGE
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 74274ca..778c64b 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -563,11 +563,11 @@ unsigned long get_board_ddr_clk(void);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
 #ifdef CONFIG_PPC_T1040
-#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
 #endif
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 4c1175d..be4ae71 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -65,10 +65,10 @@
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
-#define CONFIG_PCIE4			/* PCIE controler 4 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_PCIE4			/* PCIE controller 4 */
 
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 9a3965f..ed3493b 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -130,10 +130,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
-#define CONFIG_PCIE4			/* PCIE controler 4 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_PCIE4			/* PCIE controller 4 */
 
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 85df388..d8c57a8 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -550,10 +550,10 @@ unsigned long get_board_ddr_clk(void);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
-#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
 #define CONFIG_FSL_PCIE_RESET
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 5e2d659..b6be46e 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -500,10 +500,10 @@ unsigned long get_board_ddr_clk(void);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
-#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index a0cce85..ab838a8 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -92,9 +92,9 @@
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 1bb8d93..c60c644 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -245,7 +245,7 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 96f17d3..a06bfe0 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -67,8 +67,8 @@
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 4280c9c..660646e 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -59,8 +59,8 @@
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 9232ee3..028623d 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -45,8 +45,8 @@
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 3796395..f605ca6 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -528,8 +528,8 @@ unsigned long get_board_ddr_clk(void);
 
 /* PCIe */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 3e32128..32d2acc 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -377,8 +377,8 @@
 
 /* PCIe */
 #define CONFIG_PCI		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 8e0b472..a3aad1b 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -185,10 +185,10 @@ unsigned long long get_qixis_addr(void);
 #endif
 
 /* PCIe */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
-#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #ifdef CONFIG_LS2080A
 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 596193d..71b2fa9 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -306,8 +306,8 @@
 
 #define CONFIG_FSL_ELBC
 #define CONFIG_PCI
-#define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index f2959c9..9b75afe 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -48,8 +48,8 @@
 
 #define CONFIG_FSL_ELBC
 #define CONFIG_PCI
-#define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index f34cef5..a7c7aef 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -44,8 +44,8 @@
 #define CONFIG_SRIO1			/* SRIO port 1 */
 
 #define CONFIG_PCI		1	/* Enable PCIE */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index af61f21..8ce337e 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -32,9 +32,9 @@
 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
 #define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE2			/* PCIE controler 2 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index af02efb..86c9b4c 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -30,8 +30,8 @@
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index a1c5826..6a06b0a 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -30,8 +30,8 @@
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 */
-#define CONFIG_PCIE2		1	/* PCIE controler 2 */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 02685ca..5b377e3 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -31,7 +31,7 @@
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
-#define CONFIG_PCIE1		1	/* PCIE controler 1 (PEX8112 or XMC) */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (PEX8112 or XMC) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-- 
cgit v0.10.2


From d9b6f58efd21adf892c2507a46a0d04dd1441650 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 12 Apr 2016 11:17:39 -0600
Subject: ARM: tegra: enable GPU node by compatible value

In current Linux kernel Tegra DT files, 64-bit addresses are represented
in unit addresses as a pair of comma-separated 32-bit values. Apparently
this is no longer the correct representation for simple busses, and the
unit address should be represented as a single 64-bit value. If this is
changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
longer be able to find and enable the GPU node, since it looks up the node
by name.

Fix that function to enable nodes based on their compatible value rather
than their node name. This will work no matter what the node name is, i.e
for DTs both before and after any rename operation.

Cc: Thierry Reding <treding@nvidia.com>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h
index 4423386..6be9f61 100644
--- a/arch/arm/include/asm/arch-tegra/gpu.h
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -26,7 +26,7 @@ int tegra_gpu_enable_node(void *blob, const char *gpupath);
 
 #else /* CONFIG_OF_LIBFDT */
 
-static inline int tegra_gpu_enable_node(void *blob, const char *gpupath)
+static inline int tegra_gpu_enable_node(void *blob, const char *compat)
 {
 	return 0;
 }
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index ac274e1..141d6e1 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -404,16 +404,22 @@ ulong board_get_usable_ram_top(ulong total_size)
  */
 int ft_system_setup(void *blob, bd_t *bd)
 {
-	const char *gpu_path =
-#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
-		"/gpu@0,57000000";
-#else
-		NULL;
+	const char *gpu_compats[] = {
+#if defined(CONFIG_TEGRA124)
+		"nvidia,gk20a",
+#endif
+#if defined(CONFIG_TEGRA210)
+		"nvidia,gm20b",
 #endif
+	};
+	int i, ret;
 
 	/* Enable GPU node if GPU setup has been performed */
-	if (gpu_path != NULL)
-		return tegra_gpu_enable_node(blob, gpu_path);
+	for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) {
+		ret = tegra_gpu_enable_node(blob, gpu_compats[i]);
+		if (ret)
+			return ret;
+	}
 
 	return 0;
 }
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index 0dbddd4..74b64a6 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -33,16 +33,17 @@ void tegra_gpu_config(void)
 
 #if defined(CONFIG_OF_LIBFDT)
 
-int tegra_gpu_enable_node(void *blob, const char *gpupath)
+int tegra_gpu_enable_node(void *blob, const char *compat)
 {
 	int offset;
 
-	if (_configured) {
-		offset = fdt_path_offset(blob, gpupath);
-		if (offset > 0) {
-			fdt_status_okay(blob, offset);
-			debug("enabled GPU node %s\n", gpupath);
-		}
+	if (!_configured)
+		return 0;
+
+	offset = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (offset != -FDT_ERR_NOTFOUND) {
+		fdt_status_okay(blob, offset);
+		offset = fdt_node_offset_by_compatible(blob, offset, compat);
 	}
 
 	return 0;
-- 
cgit v0.10.2


From f5c6db84e71c60bfc7ae746bfb2cd1090d0b8765 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 20 Apr 2016 15:46:50 -0600
Subject: pci: tegra: fix DM conversion issues on Tegra20

Tegra20's PCIe controller has a couple of quirks. There are workarounds in
the driver for these, but they don't work after the DM conversion:

1) The PCI_CLASS value is wrong in HW.

This is worked around in pci_tegra_read_config() by patching up the value
read from that register. Pre-DM, the PCIe core always read this via a
16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used,
so we need to check for offset 0x8 instead. Mask the offset value back to
32-bit alignment to make this work in all cases.

2) Accessing devices other than dev 1 causes a data abort.

Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code
called during enumeration while iterating over a bus. The DM PCIe core
doesn't use this function. Instead, enhance tegra_pcie_conf_address() to
validate the bdf being accessed, and refuse to access invalid devices.
Since pci_skip_dev() isn't used, delete it.

I've also validated that both these WARs are only needed for Tegra20, by
testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in
conditionally.

Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index 5dadf6f..c5b04da 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -275,12 +275,17 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
 				return 0;
 			}
 		}
+		return -EFAULT;
 	} else {
+#ifdef CONFIG_TEGRA20
+		unsigned int dev = PCI_DEV(bdf);
+		if (dev != 0)
+			return -EFAULT;
+#endif
+
 		*address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
 		return 0;
 	}
-
-	return -EFAULT;
 }
 
 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
@@ -299,13 +304,15 @@ static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
 
 	value = readl(address);
 
+#ifdef CONFIG_TEGRA20
 	/* fixup root port class */
 	if (PCI_BUS(bdf) == 0) {
-		if (offset == PCI_CLASS_REVISION) {
+		if ((offset & ~3) == PCI_CLASS_REVISION) {
 			value &= ~0x00ff0000;
 			value |= PCI_CLASS_BRIDGE_PCI << 16;
 		}
 	}
+#endif
 
 done:
 	*valuep = pci_conv_32_to_size(value, offset, size);
@@ -1041,11 +1048,3 @@ U_BOOT_DRIVER(pci_tegra) = {
 	.probe	= pci_tegra_probe,
 	.priv_auto_alloc_size = sizeof(struct tegra_pcie),
 };
-
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
-{
-	if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0)
-		return 1;
-
-	return 0;
-}
-- 
cgit v0.10.2


From bbca7108db79076d3a9a9c112792d7c4608a665c Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 21 Apr 2016 16:03:37 -0600
Subject: ARM: tegra: import latest Jetson TK1 spreadsheet

This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.

The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
index 14f0ce5..a66b710 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -31,6 +31,9 @@ void pinmux_init(void)
 
 	pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
 				   ARRAY_SIZE(jetson_tk1_drvgrps));
+
+	pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
+					ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
 }
 
 #ifdef CONFIG_PCI_TEGRA
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index b2b2057..00e0cdc 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -276,7 +276,6 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
 	PINCFG(CPU_PWR_REQ,            CPU,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
 	PINCFG(PWR_INT_N,              PMI,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
 	PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
-	PINCFG(OWR,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, NORMAL),
 	PINCFG(CLK_32K_IN,             CLK,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
 	PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
 };
@@ -296,4 +295,15 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
 static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
 };
 
+#define MIPIPADCTRLCFG(_grp, _mux) \
+	{							\
+		.grp		= PMUX_MIPIPADCTRLGRP_##_grp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+	}
+
+static const struct pmux_mipipadctrlgrp_config jetson_tk1_mipipadctrlgrps[] = {
+	/*             grp,   mux */
+	MIPIPADCTRLCFG(DSI_B, DSI_B),
+};
+
 #endif /* PINMUX_CONFIG_JETSON_TK1_H */
-- 
cgit v0.10.2


From ea948590a3e0bd08021f110db9784a6d201ea810 Mon Sep 17 00:00:00 2001
From: Ash Charles <ashcharles@gmail.com>
Date: Thu, 5 May 2016 11:58:06 -0700
Subject: omap4: load files for legacy boot

Be sure to load the zImage and fdtfile prior to actually booting in
case we are doing a legacy boot.

Signed-off-by: Ash Charles <ashcharles@gmail.com>

diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 586d848..5fad3c1 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -122,7 +122,10 @@
 	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
 		"run args_mmc; " \
-		"bootz ${loadaddr} - ${fdtaddr}\0" \
+		"if run loadimage; then " \
+			"run loadfdt; " \
+			"bootz ${loadaddr} - ${fdtaddr}; " \
+		"fi;\0" \
 	"uimageboot=echo Booting from mmc${mmcdev} ...; " \
 		"run args_mmc; " \
 		"bootm ${loadaddr}\0" \
-- 
cgit v0.10.2


From 4bf11dc88c246c354ab6060309018a8feb97ec10 Mon Sep 17 00:00:00 2001
From: Ash Charles <ashcharles@gmail.com>
Date: Thu, 5 May 2016 11:58:07 -0700
Subject: omap4: duovero: Disable EFI booting

The DuoVero board fails to compile with EFI enabled as the generated
binaries are too large.  As this platform doesn't currently need EFI,
disable this feature.

Signed-off-by: Ash Charles <ashcharles@gmail.com>

diff --git a/include/configs/duovero.h b/include/configs/duovero.h
index d8f48ef..98afe27 100644
--- a/include/configs/duovero.h
+++ b/include/configs/duovero.h
@@ -22,6 +22,7 @@
 #include <configs/ti_omap4_common.h>
 
 #undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_EFI_PARTITION
 
 #undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-- 
cgit v0.10.2


From b955e42bad81a2ddad2f82c1843771de9bdfe6d4 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 4 May 2016 16:35:25 +0200
Subject: mmc: Fix error in RPMB code

Since we do not build any board with CONFIG_SUPPORT_EMMC_RPMB , this
piece of code evaded conversion. Fix the following compiler error:

cmd/mmc.c: In function 'do_mmcrpmb':
cmd/mmc.c:316:32: error: 'struct blk_desc' has no member named 'part_num'
  original_part = mmc->block_dev.part_num;
                                ^

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/cmd/mmc.c b/cmd/mmc.c
index 39ef072..c5454bf 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -313,7 +313,7 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag,
 		return CMD_RET_FAILURE;
 	}
 	/* Switch to the RPMB partition */
-	original_part = mmc->block_dev.part_num;
+	original_part = mmc->block_dev.hwpart;
 	if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
 		return CMD_RET_FAILURE;
 	ret = cp->cmd(cmdtp, flag, argc, argv);
-- 
cgit v0.10.2


From 1cc0a9f49657734c54939f03fc1e3ca0ec9d7eef Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Wed, 4 May 2016 04:47:31 -0400
Subject: Fix various typos, scattered over the code.

Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d580a43..a9b12a4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num)
 
 	/*
 	 * DDR controller 0 & 1 are on memory complex 0
-	 * DDR controler 2 is on memory complext 1
+	 * DDR controller 2 is on memory complext 1
 	 */
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num >= 2)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 48e478c..b180f44 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -114,7 +114,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 U_BOOT_CMD(
 	   mmcsetn,	1,	1,	do_mmcsetn,
-	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment",
+	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
 	""
 );
 #endif
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f852a1f..fe37d1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -145,7 +145,7 @@ config MIPS_BOOT_ENV_LEGACY
 	  Enable this option if you want U-Boot to hand over the Yamon-style
 	  environment to the kernel. Information like memory size, initrd
 	  address and size will be prepared as zero-terminated key/value list.
-	  The address of the enviroment is stored in register $a2.
+	  The address of the environment is stored in register $a2.
 
 config MIPS_BOOT_FDT
 	bool "Hand over a flattened device tree to Linux kernel"
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index 916451a..455136c 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1151,7 +1151,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= ranks;
 	debug("dram_size = %lu\n", dram_size);
 
-	/* Start the SDRAM controler */
+	/* Start the SDRAM controller */
 	mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
 	denali_wait_for_dlllock();
 
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 64e4e30..8c171b1 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -812,9 +812,9 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
 }
 /* haddr - Address of the header of image to be validated.
  * arg_hash_str - Option hash string. If provided, this
- * overides the key hash in the SFP fuses.
+ * overrides the key hash in the SFP fuses.
  * img_addr_ptr - Optional pointer to address of image to be validated.
- * If non zero addr, this overides the addr of image in header,
+ * If non zero addr, this overrides the addr of image in header,
  * otherwise updated to image addr in header.
  * Acts as both input and output of function.
  * This pointer shouldn't be NULL.
diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README
index a248fb2..b8bee89 100644
--- a/board/freescale/mx28evk/README
+++ b/board/freescale/mx28evk/README
@@ -45,7 +45,7 @@ or
 
 or
 
-"make mx28evk_spi_config"       - store enviroment variables into SPI NOR flash
+"make mx28evk_spi_config"       - store environment variables into SPI NOR flash
 
 Choose the target accordingly.
 
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 4c18962..898217f 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -1055,7 +1055,7 @@ static char fdt_help_text[] =
 	"                                        <start> - addr of key blob\n"
 	"                                                  default gd->fdt_blob\n"
 #endif
-	"NOTE: Dereference aliases by omiting the leading '/', "
+	"NOTE: Dereference aliases by omitting the leading '/', "
 		"e.g. fdt print ethernet0.";
 #endif
 
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 86a4689..44b2c3a 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1742,7 +1742,7 @@ int mtdparts_init(void)
 	debug("last_partition : %s\n", last_partition);
 	debug("env_partition  : %s\n", current_partition);
 
-	/* if mtdids varible is empty try to use defaults */
+	/* if mtdids variable is empty try to use defaults */
 	if (!ids) {
 		if (mtdids_default) {
 			debug("mtdids variable not defined, using default\n");
diff --git a/doc/README.commands.spl b/doc/README.commands.spl
index ac33273..cb3e0c8 100644
--- a/doc/README.commands.spl
+++ b/doc/README.commands.spl
@@ -10,7 +10,7 @@ export has two subcommands:
 	fdt: exports the FDT
 
 Call is:
-spl export <ftd|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt]
+spl export <fdt|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt]
 
 
 TYPICAL CALL
diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia
index d3563a3..0a363b2 100644
--- a/doc/README.marubun-pcmcia
+++ b/doc/README.marubun-pcmcia
@@ -34,7 +34,7 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
 	ex.	#define CONFIG_PCMCIA_SLOT_A    1
 
     * CONFIG_SYS_MARUBUN_MRSHPC
-	This is MR-SHPC-01 PCMCIA controler base address.
+	This is MR-SHPC-01 PCMCIA controller base address.
 	You should do the setting matched to your environment.
 	ex.  #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0
 	     ( for MS7722SE01 environment )
diff --git a/doc/README.mxs b/doc/README.mxs
index 6ea73b9..4edf19f 100644
--- a/doc/README.mxs
+++ b/doc/README.mxs
@@ -219,7 +219,7 @@ There are two possibilities when preparing an image writable to NAND flash.
 
 	   This script expects a working TFTP server containing the file
 	   "u-boot.nand" in it's root directory. This can be changed by
-	   adjusting the "update_nand_full_filename" varible.
+	   adjusting the "update_nand_full_filename" variable.
 
 	   To update the system, run the following in U-Boot prompt:
 
@@ -242,7 +242,7 @@ There are two possibilities when preparing an image writable to NAND flash.
 
 	   This script expects a working TFTP server containing the file
 	   "u-boot.sb" in it's root directory. This can be changed by
-	   adjusting the "update_nand_firmware_filename" varible.
+	   adjusting the "update_nand_firmware_filename" variable.
 
 	   To update the system, run the following in U-Boot prompt:
 
diff --git a/doc/SPI/README.sandbox-spi b/doc/SPI/README.sandbox-spi
index bb73eaf..dfa845c 100644
--- a/doc/SPI/README.sandbox-spi
+++ b/doc/SPI/README.sandbox-spi
@@ -1,7 +1,7 @@
 Sandbox SPI/SPI Flash Implementation
 ====================================
 
-U-Boot supports SPI and SPI flash emuation in sandbox. This must be enabled
+U-Boot supports SPI and SPI flash emulation in sandbox. This must be enabled
 using the --spi_sf paramter when starting U-Boot.
 
 For example:
diff --git a/doc/SPI/README.ti_qspi_flash b/doc/SPI/README.ti_qspi_flash
index 9064739..5cc1fd0 100644
--- a/doc/SPI/README.ti_qspi_flash
+++ b/doc/SPI/README.ti_qspi_flash
@@ -31,7 +31,7 @@ Can be used in:
 Memory mapped read mode
 -----------------------
 In this, SPI controller is configured using configuration port and then
-controler is switched to memory mapped port for data read.
+controller is switched to memory mapped port for data read.
 
 Driver
 ------
diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c
index da44c3d..a9a01b5 100644
--- a/drivers/bios_emulator/x86emu/decode.c
+++ b/drivers/bios_emulator/x86emu/decode.c
@@ -241,7 +241,7 @@ no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to
 addresses relative to SS (ie: on the stack). So, at the minimum, all
 decodings of addressing modes would have to set/clear a bit describing
 whether the access is relative to DS or SS.  That is the function of the
-cpu-state-varible M.x86.mode. There are several potential states:
+cpu-state-variable M.x86.mode. There are several potential states:
 
     repe prefix seen  (handled elsewhere)
     repne prefix seen  (ditto)
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 4fe2219..6b92064 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -3,8 +3,8 @@ menu "DFU support"
 config DFU_TFTP
 	bool "DFU via TFTP"
 	help
-	  This option allows performing update of DFU managed medium with data
-	  send via TFTP boot.
-	  Detailed description of this feature can be found at ./doc/README.dfutftp
+	  This option allows performing update of DFU-managed medium with data
+	  sent via TFTP boot.
 
+	  Detailed description of this feature can be found at ./doc/README.dfutftp
 endmenu
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index be0659a..4bf8fa4 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -120,7 +120,7 @@ static int macb_is_gem(struct macb_device *macb)
 static int gem_is_gigabit_capable(struct macb_device *macb)
 {
 	/*
-	 * The GEM controllers embeded in SAMA5D2 and SAMA5D4 are
+	 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
 	 * configured to support only 10/100.
 	 */
 	return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 443a4da..2fa2016 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -1,5 +1,5 @@
 /*
- * sh_eth.c - Driver for Renesas ethernet controler.
+ * sh_eth.c - Driver for Renesas ethernet controller.
  *
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 5cb520c..3645f0e 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,5 +1,5 @@
 /*
- * sh_eth.h - Driver for Renesas SuperH ethernet controler.
+ * sh_eth.h - Driver for Renesas SuperH ethernet controller.
  *
  * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
  * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 3c6b36d..8e22ea7 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -1,7 +1,7 @@
 config DM_THERMAL
 	bool "Driver support for thermal devices"
 	help
-	  Enable support for temporary-sensing devices. Some SoCs have on-chip
+	  Enable support for temperature-sensing devices. Some SoCs have on-chip
 	  temperature sensors to permit warnings, speed throttling or even
 	  automatic power-off when the temperature gets too high or low. Other
 	  devices may be discrete but connected on a suitable bus.
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 83d9e10..ffcc4d2 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -121,7 +121,7 @@
 				"initrd_high=0xffffffffffffffff\0" \
 				BOOTENV
 
-/* Preserve enviroment on sd card */
+/* Preserve environment on sd card */
 #define CONFIG_COMMAND_HISTORY
 
 #define CONFIG_ENV_SIZE			0x1000
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 6c79643..3c11e2a 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -140,7 +140,7 @@
 #define CONFIG_PREBOOT \
 	"echo ======================NOTICE============================;"\
 	"echo \"The u-boot environment is not set.\";"			\
-	"echo \"If using a display a valid display varible for your panel\";" \
+	"echo \"If using a display a valid display variable for your panel\";" \
 	"echo \"needs to be set.\";"					\
 	"echo \"Valid display options are:\";"				\
 	"echo \"  2 == LQ121S1DG31     TFT SVGA    (12.1)  Sharp\";"	\
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index 1f33bc6..816c571 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -102,7 +102,7 @@
 	"run mmcboot;" \
 	"run nandboot;"
 
-/* NS16550 Configuration: primary UART via FDTI */
+/* NS16550 Configuration: primary UART via FTDI */
 #define CONFIG_SYS_NS16550_COM1		0x44e09000
 #define CONFIG_BAUDRATE			115200
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index fb88273..37d482a 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -570,7 +570,7 @@ int fdtdec_check_fdt(void);
  * @param id		Compatible ID to look for
  * @param node_list	Place to put list of found nodes
  * @param maxcount	Maximum number of nodes to find
- * @return number of nodes found on success, FTD_ERR_... on error
+ * @return number of nodes found on success, FDT_ERR_... on error
  */
 int fdtdec_find_aliases_for_id(const void *blob, const char *name,
 			enum fdt_compat_id id, int *node_list, int maxcount);
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 6f71b55..68631b7 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -273,12 +273,12 @@ def log_msg(color_enabled, color, defconfig, msg):
         color_text(color_enabled, color, msg) + '\n'
 
 def update_cross_compile():
-    """Update per-arch CROSS_COMPILE via enviroment variables
+    """Update per-arch CROSS_COMPILE via environment variables
 
     The default CROSS_COMPILE values are available
     in the CROSS_COMPILE list above.
 
-    You can override them via enviroment variables
+    You can override them via environment variables
     CROSS_COMPILE_{ARCH}.
 
     For example, if you want to override toolchain prefixes
-- 
cgit v0.10.2


From 116611937faab3a0b2adf4db612aeb4cf1391941 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 28 Apr 2016 12:45:44 -0600
Subject: ARM: fix ifdefs in ARMv8 lowlevel_init()

Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.

In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:

- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.

An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.

Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index deb44a8..c3cc819 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -214,7 +214,9 @@ WEAK(lowlevel_init)
 	ldr	x1, =GICC_BASE
 	bl	gic_init_secure_percpu
 #endif
+#endif
 
+#ifndef CONFIG_ARMV8_MULTIENTRY
 	branch_if_master x0, x1, 2f
 
 	/*
-- 
cgit v0.10.2


From b67d6b003cfdaf04335c3aaca3b27f15e7c6f204 Mon Sep 17 00:00:00 2001
From: Russ Dill <russ.dill@ti.com>
Date: Thu, 5 May 2016 08:52:10 -0500
Subject: ARM: am33xx: Fix DDR initialization delays

The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.

timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.

Note that this issue introduced in v2015.01 by:

b352dde "am33xx: Drop timer_init call from s_init".

Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.

Signed-off-by: Russ Dill <russ.dill@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 595c951..9b9b78e 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -237,4 +237,5 @@ void prcm_init()
 	enable_basic_clocks();
 	scale_vcores();
 	setup_dplls();
+	timer_init();
 }
-- 
cgit v0.10.2


From daa69f5f5dba48406836b1879434fc4af4bb7df7 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 5 May 2016 17:02:06 -0600
Subject: test/py: dfu: wait for USB device to go away at boot

It can take a while for a host machine to notice that a USB device has
disconnected, and process the change. At the end of the DFU test, we wait
up to 10 seconds for this to happen. This change makes the test wait the
same (up to) 10 seconds at the start of the test for any previously active
USB device-mode session to be cleaned up. Such as session might have been
used to download U-Boot into memory for example; this is certainly true
on my Tegra test systems. This changes should solve the DFU test
intermittency issues I've been seeing on some Tegra devices.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 8649d87..585e6b2 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -136,6 +136,8 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
             Nothing.
         """
 
+        u_boot_utils.wait_until_file_open_fails(
+            env__usb_dev_port['host_usb_dev_node'], True)
         fh = u_boot_utils.attempt_to_open_file(
             env__usb_dev_port['host_usb_dev_node'])
         if fh:
-- 
cgit v0.10.2


From ad7af5d7e4caf49581c7403d5a8edc0f11a5f652 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 4 May 2016 15:27:50 +0800
Subject: imx6: cache: disable L2 before touching Auxiliary Control Register

According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"

So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index 54b021c..b775488 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -43,6 +43,12 @@ void v7_outer_cache_enable(void)
 
 
 	/*
+	 * Must disable the L2 before changing the latency parameters
+	 * and auxiliary control register.
+	 */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+	/*
 	 * Set bit 22 in the auxiliary control register. If this bit
 	 * is cleared, PL310 treats Normal Shared Non-cacheable
 	 * accesses as Cacheable no-allocate.
@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
-	/* Must disable the L2 before changing the latency parameters */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);
 
-- 
cgit v0.10.2


From 79d867c2e683f7080a8724a54a4a12ac0ce1f837 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Thu, 5 May 2016 16:59:12 -0700
Subject: usb: ehci-mx6: allow board_ehci_hcd_init to fail

There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index a981b50..bb48d0d 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -254,7 +254,7 @@ static void usb_oc_config(int index)
 }
 
 /**
- * board_ehci_hcd_init - override usb phy mode
+ * board_usb_phy_mode - override usb phy mode
  * @port:	usb host/otg port
  *
  * Target board specific, override usb_phy_mode.
@@ -310,6 +310,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 #endif
 	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
 		(controller_spacing * index));
+	int ret;
 
 	if (index > 3)
 		return -EINVAL;
@@ -317,7 +318,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	mdelay(1);
 
 	/* Do board specific initialization */
-	board_ehci_hcd_init(index);
+	ret = board_ehci_hcd_init(index);
+	if (ret)
+		return ret;
 
 	usb_power_config(index);
 	usb_oc_config(index);
-- 
cgit v0.10.2


From 2f1b4302e352800b8b651a300281a7fae67cdf80 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 01:55:10 +0200
Subject: usb: Don't init pointer to zero, but NULL

The pointer should always be inited to NULL, not zero (0). These are
two different things and not necessarily equal.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/common/usb.c b/common/usb.c
index 4d0de4d..63429d4 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1064,7 +1064,7 @@ static int usb_prepare_device(struct usb_device *dev, int addr, bool do_read,
 
 int usb_select_config(struct usb_device *dev)
 {
-	unsigned char *tmpbuf = 0;
+	unsigned char *tmpbuf = NULL;
 	int err;
 
 	err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE);
-- 
cgit v0.10.2


From 268da813c7f963c8318778de99be382d6b51055d Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 15:07:03 +0200
Subject: ARM: socfpga: Disable USB OC protection on SoCrates

This is mandatory, otherwise the USB does not work.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index d2ab3b3..bdd9324 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -83,5 +83,6 @@
 };
 
 &usb1 {
+	disable-over-current;
 	status = "okay";
 };
-- 
cgit v0.10.2


From 8b1a07493f0ad56fafaccce640a0403500e57a78 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 28 Apr 2016 07:17:16 +0200
Subject: arm: socfpga: socrates: Add 'time' command

The time command is very helpful for performance and regressions tests.
So lets enable it on SoCrates.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>

diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index b64ea15..a17e9d0 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-- 
cgit v0.10.2


From 26da6353e17111d7f0882866950cf26a679b8d5f Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 23:18:55 +0200
Subject: mtd: cqspi: Simplify indirect write code

The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.

This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7786dd6..5e84144 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/errno.h>
+#include <wait_bit.h>
 #include "cadence_qspi.h"
 
 #define CQSPI_REG_POLL_US			(1) /* 1us */
@@ -214,32 +215,6 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 	return;
 }
 
-static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
-	const void *src, unsigned int bytes)
-{
-	unsigned int temp = 0;
-	int i;
-	int remaining = bytes;
-	unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
-	unsigned int *src_ptr = (unsigned int *)src;
-
-	while (remaining >= CQSPI_FIFO_WIDTH) {
-		for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
-			writel(*(src_ptr+i), dest_ptr+i);
-		src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
-		remaining -= CQSPI_FIFO_WIDTH;
-	}
-	if (remaining) {
-		/* dangling bytes */
-		i = remaining/sizeof(dest_ptr);
-		memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
-		writel(temp, dest_ptr+i);
-		for (--i; i >= 0; i--)
-			writel(*(src_ptr+i), dest_ptr+i);
-	}
-	return;
-}
-
 /* Read from SRAM FIFO with polling SRAM fill level. */
 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
 			const void *src_addr,  unsigned int num_bytes)
@@ -276,44 +251,6 @@ static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
 	return 0;
 }
 
-/* Write to SRAM FIFO with polling SRAM fill level. */
-static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
-				const void *src_addr, unsigned int num_bytes)
-{
-	const void *reg_base = plat->regbase;
-	void *dest_addr = plat->ahbbase;
-	unsigned int retry = CQSPI_REG_RETRY;
-	unsigned int sram_level;
-	unsigned int wr_bytes;
-	unsigned char *src = (unsigned char *)src_addr;
-	int remaining = num_bytes;
-	unsigned int page_size = plat->page_size;
-	unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
-
-	while (remaining > 0) {
-		retry = CQSPI_REG_RETRY;
-		while (retry--) {
-			sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
-			if (sram_level <= sram_threshold_words)
-				break;
-		}
-		if (!retry) {
-			printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
-			       sram_level, sram_threshold_words);
-			return -1;
-		}
-		/* Write a page or remaining bytes. */
-		wr_bytes = (remaining > page_size) ?
-					page_size : remaining;
-
-		cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
-		src += wr_bytes;
-		remaining -= wr_bytes;
-	}
-
-	return 0;
-}
-
 void cadence_qspi_apb_controller_enable(void *reg_base)
 {
 	unsigned int reg;
@@ -810,48 +747,45 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 }
 
 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
-	unsigned int txlen, const u8 *txbuf)
+	unsigned int n_tx, const u8 *txbuf)
 {
-	unsigned int reg = 0;
-	unsigned int retry;
+	unsigned int page_size = plat->page_size;
+	unsigned int remaining = n_tx;
+	unsigned int write_bytes;
+	int ret;
 
 	/* Configure the indirect read transfer bytes */
-	writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
+	writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 
 	/* Start the indirect write transfer */
 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
 	       plat->regbase + CQSPI_REG_INDIRECTWR);
 
-	if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
-		goto failwr;
-
-	/* Wait until last write is completed (FIFO empty) */
-	retry = CQSPI_REG_RETRY;
-	while (retry--) {
-		reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
-		if (reg == 0)
-			break;
-
-		udelay(1);
-	}
-
-	if (reg != 0) {
-		printf("QSPI: timeout for indirect write\n");
-		goto failwr;
-	}
+	while (remaining > 0) {
+		write_bytes = remaining > page_size ? page_size : remaining;
+		/* Handle non-4-byte aligned access to avoid data abort. */
+		if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
+			writesb(plat->ahbbase, txbuf, write_bytes);
+		else
+			writesl(plat->ahbbase, txbuf, write_bytes >> 2);
+
+		ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
+				   CQSPI_REG_SDRAMLEVEL_WR_MASK <<
+				   CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
+		if (ret) {
+			printf("Indirect write timed out (%i)\n", ret);
+			goto failwr;
+		}
 
-	/* Check flash indirect controller status */
-	retry = CQSPI_REG_RETRY;
-	while (retry--) {
-		reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
-		if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
-			break;
-		udelay(1);
+		txbuf += write_bytes;
+		remaining -= write_bytes;
 	}
 
-	if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
-		printf("QSPI: indirect completion status error with reg 0x%08x\n",
-		       reg);
+	/* Check indirect done status */
+	ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
+			   CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
+	if (ret) {
+		printf("Indirect write completion error (%i)\n", ret);
 		goto failwr;
 	}
 
@@ -864,7 +798,7 @@ failwr:
 	/* Cancel the indirect write */
 	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 	       plat->regbase + CQSPI_REG_INDIRECTWR);
-	return -1;
+	return ret;
 }
 
 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
-- 
cgit v0.10.2


From 5a824c493a31d06f04a6736fab8f67bf78145003 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 23:38:05 +0200
Subject: mtd: cqspi: Simplify indirect read code

The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 5e84144..a71531d 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -193,64 +193,6 @@ static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 	return addr;
 }
 
-static void cadence_qspi_apb_read_fifo_data(void *dest,
-	const void *src_ahb_addr, unsigned int bytes)
-{
-	unsigned int temp;
-	int remaining = bytes;
-	unsigned int *dest_ptr = (unsigned int *)dest;
-	unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
-
-	while (remaining >= sizeof(dest_ptr)) {
-		*dest_ptr = readl(src_ptr);
-		remaining -= sizeof(src_ptr);
-		dest_ptr++;
-	}
-	if (remaining) {
-		/* dangling bytes */
-		temp = readl(src_ptr);
-		memcpy(dest_ptr, &temp, remaining);
-	}
-
-	return;
-}
-
-/* Read from SRAM FIFO with polling SRAM fill level. */
-static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
-			const void *src_addr,  unsigned int num_bytes)
-{
-	unsigned int remaining = num_bytes;
-	unsigned int retry;
-	unsigned int sram_level = 0;
-	unsigned char *dest = (unsigned char *)dest_addr;
-
-	while (remaining > 0) {
-		retry = CQSPI_REG_RETRY;
-		while (retry--) {
-			sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
-			if (sram_level)
-				break;
-			udelay(1);
-		}
-
-		if (!retry) {
-			printf("QSPI: No receive data after polling for %d times\n",
-			       CQSPI_REG_RETRY);
-			return -1;
-		}
-
-		sram_level *= CQSPI_FIFO_WIDTH;
-		sram_level = sram_level > remaining ? remaining : sram_level;
-
-		/* Read data from FIFO. */
-		cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
-		dest += sram_level;
-		remaining -= sram_level;
-		udelay(1);
-	}
-	return 0;
-}
-
 void cadence_qspi_apb_controller_enable(void *reg_base)
 {
 	unsigned int reg;
@@ -679,40 +621,84 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 	return 0;
 }
 
+static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
+{
+	u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
+	reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
+	return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
+}
+
+static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
+{
+	unsigned int timeout = 10000;
+	u32 reg;
+
+	while (timeout--) {
+		reg = cadence_qspi_get_rd_sram_level(plat);
+		if (reg)
+			return reg;
+		udelay(1);
+	}
+
+	return -ETIMEDOUT;
+}
+
 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
-	unsigned int rxlen, u8 *rxbuf)
+	unsigned int n_rx, u8 *rxbuf)
 {
-	unsigned int reg;
+	unsigned int remaining = n_rx;
+	unsigned int bytes_to_read = 0;
+	int ret;
 
-	writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
+	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 
 	/* Start the indirect read transfer */
 	writel(CQSPI_REG_INDIRECTRD_START_MASK,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
 
-	if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
-				     (const void *)plat->ahbbase, rxlen))
-		goto failrd;
+	while (remaining > 0) {
+		ret = cadence_qspi_wait_for_data(plat);
+		if (ret < 0) {
+			printf("Indirect write timed out (%i)\n", ret);
+			goto failrd;
+		}
+
+		bytes_to_read = ret;
+
+		while (bytes_to_read != 0) {
+			bytes_to_read *= CQSPI_FIFO_WIDTH;
+			bytes_to_read = bytes_to_read > remaining ?
+					remaining : bytes_to_read;
+			/* Handle non-4-byte aligned access to avoid data abort. */
+			if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
+				readsb(plat->ahbbase, rxbuf, bytes_to_read);
+			else
+				readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
+			rxbuf += bytes_to_read;
+			remaining -= bytes_to_read;
+			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
+		}
+	}
 
-	/* Check flash indirect controller */
-	reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
-	if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
-		reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
-		printf("QSPI: indirect completion status error with reg 0x%08x\n",
-		       reg);
+	/* Check indirect done status */
+	ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
+			   CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
+	if (ret) {
+		printf("Indirect read completion error (%i)\n", ret);
 		goto failrd;
 	}
 
 	/* Clear indirect completion status */
 	writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
+
 	return 0;
 
 failrd:
 	/* Cancel the indirect read */
 	writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
-	return -1;
+	return ret;
 }
 
 /* Opcode + Address (3/4 bytes) */
-- 
cgit v0.10.2


From 5289c5fa5371dada10e9cbdcdbf3fb010905ea2d Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Fri, 6 May 2016 17:16:31 +0200
Subject: socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled

Building without ethernet driver doesn't work. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd05e14..5cbd8a4 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -172,7 +172,7 @@ static int socfpga_eth_reset(void)
 #else
 static int socfpga_eth_reset(void)
 {
-	return 0
+	return 0;
 };
 #endif
 
-- 
cgit v0.10.2


From f647bf0ba36a5236d4bc7f93d39bfacfb1cfe6c7 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 03:08:12 +0200
Subject: usb: Wait after sending Set Configuration request

Some devices, like the SanDisk Cruzer Pop need some time to process
the Set Configuration request, so wait a little until they are ready.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/common/usb.c b/common/usb.c
index 63429d4..205041b 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1107,6 +1107,14 @@ int usb_select_config(struct usb_device *dev)
 			"len %d, status %lX\n", dev->act_len, dev->status);
 		return err;
 	}
+
+	/*
+	 * Wait until the Set Configuration request gets processed by the
+	 * device. This is required by at least SanDisk Cruzer Pop USB 2.0
+	 * and Kingston DT Ultimate 32GB USB 3.0 on DWC2 OTG controller.
+	 */
+	mdelay(10);
+
 	debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
 	      dev->descriptor.iManufacturer, dev->descriptor.iProduct,
 	      dev->descriptor.iSerialNumber);
-- 
cgit v0.10.2


From ef71290be9b70d8cfa63b506c7d93c5069f63c42 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 27 Apr 2016 03:32:56 +0200
Subject: usb: Assure Get Descriptor request is in separate microframe

The Kingston DT Ultimate USB 3.0 stick is sensitive to this first
Get Descriptor request and if the request is not in a separate
microframe, the stick refuses to operate. Add slight delay, which
is enough for one microframe to pass on any USB spec revision.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/common/usb.c b/common/usb.c
index 205041b..8d9efe5 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1077,6 +1077,14 @@ int usb_select_config(struct usb_device *dev)
 	le16_to_cpus(&dev->descriptor.idProduct);
 	le16_to_cpus(&dev->descriptor.bcdDevice);
 
+	/*
+	 * Kingston DT Ultimate 32GB USB 3.0 seems to be extremely sensitive
+	 * about this first Get Descriptor request. If there are any other
+	 * requests in the first microframe, the stick crashes. Wait about
+	 * one microframe duration here (1mS for USB 1.x , 125uS for USB 2.0).
+	 */
+	mdelay(1);
+
 	/* only support for one config for now */
 	err = usb_get_configuration_len(dev, 0);
 	if (err >= 0) {
-- 
cgit v0.10.2


From d81db48d418edc30301961781d8a64d7cc109dd4 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 3 May 2016 22:22:59 +0200
Subject: usb: hub: Don't continue on get_port_status failure

The code shouldn't continue probing the port if get_port_status() failed.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/common/usb_hub.c b/common/usb_hub.c
index 4f59802..0f39c9f 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -402,6 +402,7 @@ static int usb_scan_port(struct usb_device_scan *usb_scan)
 			free(usb_scan);
 			return 0;
 		}
+		return 0;
 	}
 
 	portstatus = le16_to_cpu(portsts->wPortStatus);
-- 
cgit v0.10.2


From 2bf352f0c1b7f58d4610bc0777e8febbd2dfd5ff Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Fri, 6 May 2016 13:53:37 +0200
Subject: usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA

With patch c998da0d (usb: Change power-on / scanning timeout handling),
the USB scanning is started earlier and with a smaller timeout. This
resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not
getting detected any more. This patch now adds a 1 second delay (in
the host mode only) to the DWC2 driver before the scanning is started.
With this delay, now all problematic USB keys are detected successfully
again. And there is no need any more to change the delay / timeout
in the common USB code (usb_hub.c).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 30b51b3..d08879d 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -1088,6 +1088,15 @@ static int dwc2_init_common(struct dwc2_priv *priv)
 		}
 	}
 
+	/*
+	 * Add a 1 second delay here. This gives the host controller
+	 * a bit time before the comminucation with the USB devices
+	 * is started (the bus is scanned) and  fixes the USB detection
+	 * problems with some problematic USB keys.
+	 */
+	if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
+		mdelay(1000);
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From 5d8fae79163e94671956c99654abf48cf49757ba Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 10:24:52 +0800
Subject: dfu: avoid memory leak
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When dfu_fill_entity fail, need to free dfu to avoid memory leak.

Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 8f5915e..20dfcbb 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -468,8 +468,10 @@ int dfu_config_entities(char *env, char *interface, char *devstr)
 		s = strsep(&env, ";");
 		ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface,
 				      devstr);
-		if (ret)
+		if (ret) {
+			free(dfu);
 			return -1;
+		}
 
 		list_add_tail(&dfu[i].list, &dfu_list);
 		alt_num_cnt++;
-- 
cgit v0.10.2


From 12ff19dbfd93abdb62b7b326fee3f5bfa659a75e Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 10:25:22 +0800
Subject: usb: gadget: dfu: discard dead code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Reported by Coverity:
Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement:
(f_dfu->strings + --i).s = ....

If calloc failed, i is still 0 and no need to call free,
so discard the dead code.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 7d88008..8e7c981 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -636,7 +636,7 @@ dfu_prepare_strings(struct f_dfu *f_dfu, int n)
 
 	f_dfu->strings = calloc(sizeof(struct usb_string), n + 1);
 	if (!f_dfu->strings)
-		goto enomem;
+		return -ENOMEM;
 
 	for (i = 0; i < n; ++i) {
 		de = dfu_get_entity(i);
@@ -647,14 +647,6 @@ dfu_prepare_strings(struct f_dfu *f_dfu, int n)
 	f_dfu->strings[i].s = NULL;
 
 	return 0;
-
-enomem:
-	while (i)
-		f_dfu->strings[--i].s = NULL;
-
-	free(f_dfu->strings);
-
-	return -ENOMEM;
 }
 
 static int dfu_prepare_function(struct f_dfu *f_dfu, int n)
-- 
cgit v0.10.2


From e8bd2a0bf6e334adaf7703c517989433e730091b Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Tue, 10 May 2016 13:31:40 -0300
Subject: warp7: Fix boot by selecting CONFIG_OF_LIBFDT

CONFIG_OF_LIBFDT needs to be selected to avoid the following
boot problem:

reading zImage
6346216 bytes read in 118 ms (51.3 MiB/s)
Booting from mmc ...
reading imx7d-warp.dtb
32593 bytes read in 11 ms (2.8 MiB/s)
Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ]
FDT and ATAGS support not compiled in - hanging
### ERROR ### Please RESET the board ###

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index e1b0c07..ad4fbbf 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -22,3 +22,4 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_LIBFDT=y
-- 
cgit v0.10.2


From 4baca92001bff3c32a05001a7dc58996623e3ef8 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@kernel.org>
Date: Tue, 10 May 2016 15:13:59 -0500
Subject: arm: socfpga: Update iomux and pll for c5 socdk RevE

Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index f1e6d2b..2d123ba 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -8,7 +8,7 @@
 #define __SOCFPGA_PINMUX_CONFIG_H__
 
 const u8 sys_mgr_init_table[] = {
-	3, /* EMACIO0 */
+	0, /* EMACIO0 */
 	2, /* EMACIO1 */
 	2, /* EMACIO2 */
 	2, /* EMACIO3 */
@@ -17,7 +17,7 @@ const u8 sys_mgr_init_table[] = {
 	2, /* EMACIO6 */
 	2, /* EMACIO7 */
 	2, /* EMACIO8 */
-	3, /* EMACIO9 */
+	0, /* EMACIO9 */
 	2, /* EMACIO10 */
 	2, /* EMACIO11 */
 	2, /* EMACIO12 */
@@ -32,27 +32,27 @@ const u8 sys_mgr_init_table[] = {
 	0, /* FLASHIO1 */
 	3, /* FLASHIO2 */
 	3, /* FLASHIO3 */
-	3, /* FLASHIO4 */
-	3, /* FLASHIO5 */
-	3, /* FLASHIO6 */
-	3, /* FLASHIO7 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
 	0, /* FLASHIO8 */
 	3, /* FLASHIO9 */
 	3, /* FLASHIO10 */
 	3, /* FLASHIO11 */
-	0, /* GENERALIO0 */
-	1, /* GENERALIO1 */
-	1, /* GENERALIO2 */
-	0, /* GENERALIO3 */
-	0, /* GENERALIO4 */
-	1, /* GENERALIO5 */
-	1, /* GENERALIO6 */
-	1, /* GENERALIO7 */
-	1, /* GENERALIO8 */
-	0, /* GENERALIO9 */
-	0, /* GENERALIO10 */
-	0, /* GENERALIO11 */
-	0, /* GENERALIO12 */
+	3, /* GENERALIO0 */
+	3, /* GENERALIO1 */
+	3, /* GENERALIO2 */
+	3, /* GENERALIO3 */
+	3, /* GENERALIO4 */
+	3, /* GENERALIO5 */
+	3, /* GENERALIO6 */
+	3, /* GENERALIO7 */
+	3, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
 	2, /* GENERALIO13 */
 	2, /* GENERALIO14 */
 	3, /* GENERALIO15 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 4abd2e0..408235e 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -10,13 +10,13 @@
 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
@@ -27,26 +27,26 @@
 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
 #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
 #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
 #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
@@ -61,25 +61,25 @@
 #define CONFIG_HPS_CLK_OSC2_HZ 25000000
 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
 #define CONFIG_HPS_CLK_EMAC1_HZ 250000000
 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
 #define CONFIG_HPS_CLK_NAND_HZ 50000000
 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_QSPI_HZ 370000000
 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
 #define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
 #define CONFIG_HPS_CLK_GPIODB_HZ 32000
 #define CONFIG_HPS_CLK_L4_MP_HZ 100000000
 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
 
 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */
-- 
cgit v0.10.2


From 1ea4fac5a34604e67504ee6537bb01e809528cd4 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Thu, 12 May 2016 12:14:41 +0100
Subject: arm/arm64: Move barrier instructions into separate header

Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.

Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.

This fixes compilation for 64-bit sunxi boards (Pine64).

Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 30e7939..423fc70 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -59,26 +59,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
 #include <asm/io.h>
-
-/*
- * CP15 Barrier instructions
- * Please note that we have separate barrier instructions in ARMv7
- * However, we use the CP15 based instructtions because we use
- * -march=armv5 in U-Boot
- */
-#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
-#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
-#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
-
-#ifdef __ARM_ARCH_7A__
-#define ISB	asm volatile ("isb" : : : "memory")
-#define DSB	asm volatile ("dsb" : : : "memory")
-#define DMB	asm volatile ("dmb" : : : "memory")
-#else
-#define ISB	CP15ISB
-#define DSB	CP15DSB
-#define DMB	CP15DMB
-#endif
+#include <asm/barriers.h>
 
 /*
  * Workaround for ARM errata # 798870
diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h
new file mode 100644
index 0000000..37870f9
--- /dev/null
+++ b/arch/arm/include/asm/barriers.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * ARM and ARM64 barrier instructions
+ * split from armv7.h to allow sharing between ARM and ARM64
+ *
+ * Original copyright in armv7.h was:
+ * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
+ *
+ * Much of the original barrier code was contributed by:
+ *   Valentine Barshak <valentine.barshak@cogentembedded.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __BARRIERS_H__
+#define __BARRIERS_H__
+
+#ifndef __ASSEMBLY__
+
+#ifndef CONFIG_ARM64
+/*
+ * CP15 Barrier instructions
+ * Please note that we have separate barrier instructions in ARMv7
+ * However, we use the CP15 based instructtions because we use
+ * -march=armv5 in U-Boot
+ */
+#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
+#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
+#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
+
+#endif /* !CONFIG_ARM64 */
+
+#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
+#define ISB	asm volatile ("isb sy" : : : "memory")
+#define DSB	asm volatile ("dsb sy" : : : "memory")
+#define DMB	asm volatile ("dmb sy" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __BARRIERS_H__ */
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index e0c823a..20b430f 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/armv7.h>
+#include <asm/barriers.h>
 #include <asm/io.h>
 #include <asm/arch/dram.h>
 
-- 
cgit v0.10.2


From b8218a9146814ad1dba0c21facddce9adca680ef Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 9 May 2016 10:08:24 +0200
Subject: tests: py: fix NameError exception if bdi cmd is not supported

test/py raises an error, if a board has not enabled bdi command

>           pytest.skip('bdinfo command not supported')
E           NameError: global name 'pytest' is not defined

import pytest in test/py/u_boot_utils.py fixes this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 72d24e4..9d243e0 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -7,6 +7,7 @@
 import hashlib
 import os
 import os.path
+import pytest
 import sys
 import time
 
-- 
cgit v0.10.2


From 4cf4600f2569d7677a6f3cd933d7a189de6e7973 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Thu, 28 Apr 2016 08:17:28 +0200
Subject: test, tools: update tbot documentation

update tbot documentation in U-Boot, as I just
merged the event system into tbots master
branch.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/tools/tbot/README b/tools/tbot/README
index a637a63..49b9e95 100644
--- a/tools/tbot/README
+++ b/tools/tbot/README
@@ -92,6 +92,16 @@ https://github.com/hsdenx/tbot/blob/master/doc/tbot_structure.png )
 
   It is possible to switch in a single TC between board states.
 
+- Events
+  tbot creates while executing testcases so called events.
+  After tbot ended with the testcase it can call event_backends,
+  which convert the events to different formats. more info:
+
+  https://github.com/hsdenx/tbot/blob/master/doc/README.event
+
+  demo for a event backend:
+  http://xeidos.ddns.net/tests/test_db_auslesen.php
+
 - tbot cmdline parameters:
 
 $ python2.7 src/common/tbot.py --help
diff --git a/tools/tbot/README.install b/tools/tbot/README.install
index 24c67bc..a68e705 100644
--- a/tools/tbot/README.install
+++ b/tools/tbot/README.install
@@ -93,12 +93,6 @@ $
       cp src/tc/tc_lab_denx_connect_to_board.py src/tc/tc_lab_denx_connect_to_board_XXX.py
       and adapt the commands to your needs.
 
-      As this TC powers on the board for all your boards in your VL,
-      you can differ between the boards through the tbot class
-      variable "tb.boardlabname" (which is in the default case the
-      same as "tb.boardname"), but you may need to name the power target
-      with an other name than boardname, so you can configure this case.
-
       If connect fails end this TC with "tb.end_tc(False)"
       else call "tb.end_tc(True)"
 
@@ -150,12 +144,6 @@ $
       if (user == 'root'):
           password = ''
 
-  In the above example passwords for logging into the Lab PC tbot finds
-  through:
-  if (board == 'lab'):
-     user = 'name':
-         password = 'gnlmpf' # password 'gnlmpf' for login of user 'name'
-
 - prepare board config file
   Each board which is found in the VL needs a tbot configuration file
   pass the config file name with the option '-c' to tbot, tbot searches
@@ -187,13 +175,8 @@ $
              keepalive message.
   line 14: channel_timeout: passed to paramiko
   line 15: loglevel: tbots loglevel for adding entries into the logfile.
-  line 16: lap_api: used lap API (currently only 'ssh_std')
-             Should be declared as standard -> this line would be not needed
-             longer.
   line 17: wdt_timeout: timeout in seconds for tbots watchdog.
              Watchdog gets triggered if prompt get read.
-  line 20,21: include 'ssh_std' api
-             should be removed.
   line 24: tc_lab_denx_connect_to_board_tc: Which TC is used for
              connecting to the boards console the TC, here:
              https://github.com/hsdenx/tbot/blob/master/src/tc/tc_workfd_connect_with_kermit.py
@@ -215,156 +198,113 @@ TC (and hopefully share them), so continue with:
 u-boot:tools/tbot/README.create_a_new_testcase
 
 Heiko Schocher <hs@denx.de>
-v1 2016.01.22
+v2 2016.04.26
 
 --------------
 
 [1] tbot Dokumentation:
     [2] u-boot:/tools/tbot/README
     https://github.com/hsdenx/tbot/blob/master/README.md
+    tbot-devel@googlegroups.com
 
 [3] Example for a first U-Boot TC which should always work:
     (with commandline option "-v" for verbose output):
-
-hs@localhost:tbot  [master] $ python2.7 src/common/tbot.py -c tbot_dxr2.cfg -t tc_ub_setenv.py -v -l log/tbot.log
+hs@localhost:tbot  [event-devel] $ python2.7 src/common/tbot.py -c tbot_dxr2.cfg -t tc_ub_setenv.py -v -l log/tbot.log
 **** option cfg: tbot_dxr2.cfg log: log/tbot.log tc: tc_ub_setenv.py v 1
 ('CUR WORK PATH: ', '/home/hs/data/Entwicklung/tbot')
 ('CFGFILE ', 'tbot_dxr2.cfg')
 ('LOGFILE ', '/home/hs/data/Entwicklung/tbot/log/tbot.log')
-(<denx.tbot_lab_api object at 0x7f53ac1808d0>, <tbotlib.tbot object at 0x7f53a45fd410>, True)
-(<denx.tbot_lab_api object at 0x7f53ac1808d0>, <tbotlib.tbot object at 0x7f53a45fd410>, True)
-read 0: Last login: Fri Jan 22 12:20:12 2016 from 87.97.28.177
-read 0:
-read 0: *************************************************************
-read 0: BDI2000 Assignment:    (last updated:  2015-11-20 12:30 MET)
-read 0: bdi1  => techem     bdi2  => cetec_mx25   bdi3  => lpc3250
-read 0: bdi4  => -          bdi5  => --Rev.B!--   bdi6  => tqm5200s
-read 0: bdi7  => [stefano]  bdi8  => smartweb     bdi9  => sigmatek-nand
-read 0: bdi10 => pcm052     bdi11 => socrates     bdi12 => aristainetos
-read 0: bdi13 => imx53      bdi14 => ib8315       bdi15 => cairo
-read 0: bdi16 => g2c1       bdi17 => lwe090       bdi18 => symphony
-read 0: bdi19 => dxr2       bdi20 => ima3-mx6     bdi21 => sama5d3
-read 0: bdi98 => -          bdi99 => -            bdi0  => -
-read 0: Please power off unused systems when you leave!   Thanks, wd.
-read 0: *************************************************************
-read no ret 0:
-pollux:~ hs $
-write 0: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >"
-read 0: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >"
-read 0: hs@pollux [12:21:00] ttbott >
-read 1: Last login: Fri Jan 22 12:20:59 2016 from 87.97.28.177
-read 1:
-read 1: *************************************************************
-read 1: BDI2000 Assignment:    (last updated:  2015-11-20 12:30 MET)
-read 1: bdi1  => techem     bdi2  => cetec_mx25   bdi3  => lpc3250
-read 1: bdi4  => -          bdi5  => --Rev.B!--   bdi6  => tqm5200s
-read 1: bdi7  => [stefano]  bdi8  => smartweb     bdi9  => sigmatek-nand
-read 1: bdi10 => pcm052     bdi11 => socrates     bdi12 => aristainetos
-read 1: bdi13 => imx53      bdi14 => ib8315       bdi15 => cairo
-read 1: bdi16 => g2c1       bdi17 => lwe090       bdi18 => symphony
-read 1: bdi19 => dxr2       bdi20 => ima3-mx6     bdi21 => sama5d3
-read 1: bdi98 => -          bdi99 => -            bdi0  => -
-read 1: Please power off unused systems when you leave!   Thanks, wd.
-read 1: *************************************************************
-read no ret 1:
-pollux:~ hs $
-write 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >"
-read 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >"
-read 1: hs@pollux [12:21:02] ttbott >
-write 0: remote_power dxr2 -l
-read 0: hs@pollux [12:21:00] ttbott >remote_power dxr2 -l
-read 0: dxr2            ON
-read 0: hs@pollux [12:21:02] ttbott >
-read no ret 1:
-hs@pollux [12:21:02] ttbott >
-write 1: ssh hs@lena
-read 1: ssh hs@lena
-read no ret 1:
-hs@lena's password:
-read 1:
-read 1: Last login: Fri Jan 22 12:20:17 2016 from 192.168.1.1
-read 1:
-read no ret 1:
-[hs@lena ~]$
-write 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >"
-read 1: export PS1="\u@\h [\$(date +%k:%M:%S)] ttbott >"
-read 1: hs@lena [12:21:07] ttbott >
-read no ret 1:
-hs@lena [12:21:07] ttbott >
-write 1: stty cols 200
-read 1: stty cols 200
-read 1: hs@lena [12:21:08] ttbott >
-write 1: export TERM=vt200
-read 1: hs@lena [12:21:08] ttbott >export TERM=vt200
-read 1: hs@lena [12:21:08] ttbott >
-write 1: echo $COLUMNS
-read 1: hs@lena [12:21:08] ttbott >echo $COLUMNS
-read 1: 200
-read 1: hs@lena [12:21:08] ttbott >
-write 1: kermit
-read 1: hs@lena [12:21:08] ttbott >kermit
-read 1: C-Kermit 8.0.211, 10 Apr 2004, for Linux
-read 1:
-read 1:  Copyright (C) 1985, 2004,
-read 1:   Trustees of Columbia University in the City of New York.
-read 1: Type ? or HELP for help.
-read 1:
-read 1: (/home/hs/) C-Kermit>
-read 1:
-read no ret 1: (/home/hs/) C-Kermit>
-write 1: set line /dev/ttyUSB0
-read 1: set line /dev/ttyUSB0
-read 1:
-read 1: (/home/hs/) C-Kermit>
-write 1: set speed 115200
-read 1:
-read 1: (/home/hs/) C-Kermit>set speed 115200
-read 1: /dev/ttyUSB0, 115200 bps
-read 1:
-read 1: (/home/hs/) C-Kermit>
-write 1: set flow-control none
-read 1:
-read 1: (/home/hs/) C-Kermit>set flow-control none
-read 1:
-read 1: (/home/hs/) C-Kermit>
-write 1: set carrier-watch off
-read 1:
-read 1: (/home/hs/) C-Kermit>set carrier-watch off
-read 1:
-read 1: (/home/hs/) C-Kermit>
-write 1: connect
-read 1:
-read 1: (/home/hs/) C-Kermit>connect
-read 1: Connecting to /dev/ttyUSB0, speed 115200
-read 1:
-read 1:  Escape character: Ctrl-\ (ASCII 28, FS): enabled
-read 1:
-read 1: Type the escape character followed by C to get back,
-read 1:
-read 1: or followed by ? to see other options.
-read 1:
-read 1: ----------------------------------------------------
-read no ret 1:
-
-write no ret 1:
-
-read 1:
-read 1: Heiko=Schocher
-read no ret 1:
+tb_ctrl: Last login: Mon Apr 25 14:52:42 2016 from 87.97.29.27
+*************************************************************
+BDI2000 Assignment:    (last updated:  2015-11-20 12:30 MET)
+bdi1  => techem     bdi2  => cetec_mx25   bdi3  => lpc3250
+bdi4  => -          bdi5  => --Rev.B!--   bdi6  => tqm5200s
+bdi7  => [stefano]  bdi8  => smartweb     bdi9  => sigmatek-nand
+bdi10 => pcm052     bdi11 => socrates     bdi12 => aristainetos
+bdi13 => imx53      bdi14 => ib8315       bdi15 => cairo
+bdi16 => g2c1       bdi17 => lwe090       bdi18 => symphony
+bdi19 => dxr2       bdi20 => ima3-mx6     bdi21 => sama5d3
+bdi98 => -          bdi99 => -            bdi0  => -
+Please power off unused systems when you leave!   Thanks, wd.
+*************************************************************
+tb_ctrl: pollux:~ hs $
+tb_ctrl: export PS1=ttbott
+ttbott
+tb_ctrl: stty cols 200
+ttbott
+tb_ctrl: export TERM=vt200
+ttbott
+tb_ctrl: echo $COLUMNS
+200
+ttbott
+tb_con: Last login: Tue Apr 26 06:28:59 2016 from 87.97.29.27
+*************************************************************
+BDI2000 Assignment:    (last updated:  2015-11-20 12:30 MET)
+bdi1  => techem     bdi2  => cetec_mx25   bdi3  => lpc3250
+bdi4  => -          bdi5  => --Rev.B!--   bdi6  => tqm5200s
+bdi7  => [stefano]  bdi8  => smartweb     bdi9  => sigmatek-nand
+bdi10 => pcm052     bdi11 => socrates     bdi12 => aristainetos
+bdi13 => imx53      bdi14 => ib8315       bdi15 => cairo
+bdi16 => g2c1       bdi17 => lwe090       bdi18 => symphony
+bdi19 => dxr2       bdi20 => ima3-mx6     bdi21 => sama5d3
+bdi98 => -          bdi99 => -            bdi0  => -
+Please power off unused systems when you leave!   Thanks, wd.
+*************************************************************
+tb_con: pollux:~ hs $
+tb_con: export PS1=ttbot
+tb_con: t
+ttbott
+tb_con: stty cols 200
+ttbott
+tb_con: export TERM=vt200
+ttbott
+tb_con: echo $COLUMNS
+200
+ttbott
+tb_con: ssh hs@lena
+tb_con: hs@lena's password:
+tb_con:
+tb_con: Last login: Mon Apr 25 07:03:29 2016 from 192.168.1.1
+tb_con: [hs@lena ~]$
+tb_con: export PS1=ttbott
+ttbott
+tb_con: stty cols 200
+ttbott
+tb_con: export TERM=vt200
+ttbott
+tb_con: echo $COLUMNS
+200
+ttbott
+tb_con: kermit
+C-Kermit 8.0.211, 10 Apr 2004, for Linux
+ Copyright (C) 1985, 2004,
+  Trustees of Columbia University in the City of New York.
+Type ? or HELP for help.
+(/home/hs/) C-Kermit>
+tb_con: set line /dev/ttyUSB0
+(/home/hs/) C-Kermit>
+tb_con: set speed 115200
+/dev/ttyUSB0, 115200 bps
+(/home/hs/) C-Kermit>
+tb_con: set flow-control none
+(/home/hs/) C-Kermit>
+tb_con: set carrier-watch off
+(/home/hs/) C-Kermit>
+tb_con: connect
+Connecting to /dev/ttyUSB0, speed 115200
+ Escape character: Ctrl-\ (ASCII 28, FS): enabled
+Type the escape character followed by C to get back,
+or followed by ? to see other options.
+----------------------------------------------------
+tb_con: <INTERRUPT>
+U-Boot#
+tb_con: U-Boot#
 U-Boot#
-write no ret 1:
-write no ret 1:
-
-read 1: <INTERRUPT>
-read 1: U-Boot#
-write 1: setenv Heiko Schocher
-read 1: U-Boot# setenv Heiko Schocher
-read no ret 1:
+tb_con: setenv Heiko Schocher
 U-Boot#
-write 1: printenv Heiko
-read 1: printenv Heiko
-read 1: Heiko=Schocher
-read no ret 1:
+tb_con: printenv Heiko
+Heiko=Schocher
 U-Boot#
+[('tc_workfd_ssh.py', 1, 0), ('tc_workfd_connect_with_kermit.py', 1, 0), ('tc_ub_setenv.py', 1, 0)]
 End of TBOT: success
-hs@localhost:tbot  [master] $
+hs@localhost:tbot  [event-devel] $
-- 
cgit v0.10.2


From f0a711ec40a6af4ea438db0bd776886c32780ddd Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 12 May 2016 19:23:47 +0200
Subject: sunxi: Enable USB host in CHIP defconfig

Reported-and-tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 0eca229..cbbec47 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -29,3 +29,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
 CONFIG_G_DNL_VENDOR_NUM=0x1f3a
 CONFIG_G_DNL_PRODUCT_NUM=0x1010
+CONFIG_USB_EHCI_HCD=y
-- 
cgit v0.10.2


From aeaec0e682f45b9e0c62c522fafea353931f73ed Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 16 May 2016 10:40:32 -0400
Subject: Prepare v2016.05

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 293fad0..954a865 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From a13767bc0ee8ccaf4e7f64192e7f1d408dc7f900 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Apr 2016 14:15:47 +0200
Subject: i2c: cdns: Read address from DT in ofdata_to_platdata

Extract reading IP base address in function which is designed for it.
Also enable option to read more information from DT in this function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 909cea2..66bd580 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -125,10 +125,6 @@ static int cdns_i2c_probe(struct udevice *dev)
 {
 	struct i2c_cdns_bus *bus = dev_get_priv(dev);
 
-	bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
-	if (!bus->regs)
-		return -ENOMEM;
-
 	/* TODO: Calculate dividers based on CPU_CLK_1X */
 	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
 	writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
@@ -313,6 +309,17 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 	return 0;
 }
 
+static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+	struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
+
+	i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
+	if (!i2c_bus->regs)
+		return -ENOMEM;
+
+	return 0;
+}
+
 static const struct dm_i2c_ops cdns_i2c_ops = {
 	.xfer = cdns_i2c_xfer,
 	.probe_chip = cdns_i2c_probe_chip,
@@ -330,6 +337,7 @@ U_BOOT_DRIVER(cdns_i2c) = {
 	.of_match = cdns_i2c_of_match,
 	.probe = cdns_i2c_probe,
 	.remove = cdns_i2c_remove,
+	.ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 	.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 	.ops = &cdns_i2c_ops,
 };
-- 
cgit v0.10.2


From 6150be9094bb155022da3843b56e6314edf54305 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Apr 2016 14:15:48 +0200
Subject: i2c: cdns: Moving speed setup from probe to set_bus_speed function

set_bus_speed is the right function where bus speed should be setup.
This move enable option to remove probe and remove functions which are
empty.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 66bd580..0bc6aaa 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -115,41 +115,6 @@ struct i2c_cdns_bus {
 	struct cdns_i2c_regs __iomem *regs;	/* register base */
 };
 
-
-/** cdns_i2c_probe() - Probe method
- * @dev: udevice pointer
- *
- * DM callback called when device is probed
- */
-static int cdns_i2c_probe(struct udevice *dev)
-{
-	struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
-	/* TODO: Calculate dividers based on CPU_CLK_1X */
-	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
-	writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
-		(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
-
-	/* Enable master mode, ack, and 7-bit addressing */
-	setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
-		CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
-
-	debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
-	return 0;
-}
-
-static int cdns_i2c_remove(struct udevice *dev)
-{
-	struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
-	debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
-	unmap_sysmem(bus->regs);
-
-	return 0;
-}
-
 /* Wait for an interrupt */
 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 {
@@ -170,12 +135,23 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 
 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 {
+	struct i2c_cdns_bus *bus = dev_get_priv(dev);
+
 	if (speed != 100000) {
 		printf("%s, failed to set clock speed to %u\n", __func__,
 		       speed);
 		return -EINVAL;
 	}
 
+	/* TODO: Calculate dividers based on CPU_CLK_1X */
+	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
+	writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+		(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+
+	/* Enable master mode, ack, and 7-bit addressing */
+	setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
+		CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
+
 	return 0;
 }
 
@@ -335,8 +311,6 @@ U_BOOT_DRIVER(cdns_i2c) = {
 	.name = "i2c-cdns",
 	.id = UCLASS_I2C,
 	.of_match = cdns_i2c_of_match,
-	.probe = cdns_i2c_probe,
-	.remove = cdns_i2c_remove,
 	.ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 	.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 	.ops = &cdns_i2c_ops,
-- 
cgit v0.10.2


From ad72e7622bd587dc798fbac0351b558fb18caa97 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Apr 2016 14:15:49 +0200
Subject: i2c: cdns: Support different bus speeds

400kHz is maximum freq which can be used on Xilinx ZynqMP.
Support it with standard divider calculator.
Input freq is hardcoded to 100MHz input freq till we have clock driver
which can provide this information for exact configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 0bc6aaa..5642cd9 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -112,6 +112,7 @@ static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
 
 struct i2c_cdns_bus {
 	int id;
+	unsigned int input_freq;
 	struct cdns_i2c_regs __iomem *regs;	/* register base */
 };
 
@@ -133,20 +134,79 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 	return int_status & mask;
 }
 
+#define CDNS_I2C_DIVA_MAX	4
+#define CDNS_I2C_DIVB_MAX	64
+
+static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
+		unsigned int *a, unsigned int *b)
+{
+	unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
+	unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
+	unsigned int last_error, current_error;
+
+	/* calculate (divisor_a+1) x (divisor_b+1) */
+	temp = input_clk / (22 * fscl);
+
+	/*
+	 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
+	 * the fscl input is out of range. Return error.
+	 */
+	if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
+		return -EINVAL;
+
+	last_error = -1;
+	for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
+		div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
+
+		if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
+			continue;
+		div_b--;
+
+		actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
+
+		if (actual_fscl > fscl)
+			continue;
+
+		current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
+							(fscl - actual_fscl));
+
+		if (last_error > current_error) {
+			calc_div_a = div_a;
+			calc_div_b = div_b;
+			best_fscl = actual_fscl;
+			last_error = current_error;
+		}
+	}
+
+	*a = calc_div_a;
+	*b = calc_div_b;
+	*f = best_fscl;
+
+	return 0;
+}
+
 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 {
 	struct i2c_cdns_bus *bus = dev_get_priv(dev);
+	u32 div_a = 0, div_b = 0;
+	unsigned long speed_p = speed;
+	int ret = 0;
 
-	if (speed != 100000) {
-		printf("%s, failed to set clock speed to %u\n", __func__,
-		       speed);
+	if (speed > 400000) {
+		debug("%s, failed to set clock speed to %u\n", __func__,
+		      speed);
 		return -EINVAL;
 	}
 
-	/* TODO: Calculate dividers based on CPU_CLK_1X */
-	/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
-	writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
-		(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+	ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
+	if (ret)
+		return ret;
+
+	debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
+	      __func__, div_a, div_b, bus->input_freq, speed, speed_p);
+
+	writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+	       (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 
 	/* Enable master mode, ack, and 7-bit addressing */
 	setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
@@ -293,6 +353,8 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 	if (!i2c_bus->regs)
 		return -ENOMEM;
 
+	i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From d79ac324789839b4b10b37e2ff64dd9e4a92441e Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 25 Apr 2016 10:50:42 +0200
Subject: i2c: muxes: Add support for TI PCA954X mux

Add support for common TI i2c mux which is available on ZynqMP zcu102
board.
DM i2c mux core code is selecting/deselecting bus before/after
every command is performed that's why only one channel is active at a
time. That's also the reason why deselect is just disable all available
channels.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index f959d9d..48900ed 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -24,3 +24,13 @@ config I2C_ARB_GPIO_CHALLENGE
 	  I2C multimaster arbitration scheme using GPIOs and a challenge &
 	  response mechanism where masters have to claim the bus by asserting
 	  a GPIO.
+
+config I2C_MUX_PCA954x
+	tristate "TI PCA954x I2C Mux/switches"
+	depends on I2C_MUX
+	help
+	  If you say yes here you get support for the TI PCA954x
+	  I2C mux/switch devices. It is x width I2C multiplexer which enables to
+	  paritioning I2C bus and connect multiple devices with the same address
+	  to the same I2C controller where driver handles proper routing to
+	  target i2c device. PCA9544 and PCA9548 are supported.
diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile
index 47c1240..0811add 100644
--- a/drivers/i2c/muxes/Makefile
+++ b/drivers/i2c/muxes/Makefile
@@ -5,3 +5,4 @@
 #
 obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
 obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
+obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
new file mode 100644
index 0000000..7e0d2da
--- /dev/null
+++ b/drivers/i2c/muxes/pca954x.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Written by Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pca954x_priv {
+	u32 addr; /* I2C mux address */
+	u32 width; /* I2C mux width - number of busses */
+};
+
+static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
+			    uint channel)
+{
+	struct pca954x_priv *priv = dev_get_priv(mux);
+	uchar byte = 0;
+
+	return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static int pca954x_select(struct udevice *mux, struct udevice *bus,
+			  uint channel)
+{
+	struct pca954x_priv *priv = dev_get_priv(mux);
+	uchar byte = 1 << channel;
+
+	return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static const struct i2c_mux_ops pca954x_ops = {
+	.select = pca954x_select,
+	.deselect = pca954x_deselect,
+};
+
+static const struct udevice_id pca954x_ids[] = {
+	{ .compatible = "nxp,pca9548", .data = (ulong)8 },
+	{ .compatible = "nxp,pca9544", .data = (ulong)4 },
+	{ }
+};
+
+static int pca954x_ofdata_to_platdata(struct udevice *dev)
+{
+	struct pca954x_priv *priv = dev_get_priv(dev);
+
+	priv->addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+	if (!priv->addr) {
+		debug("MUX not found\n");
+		return -ENODEV;
+	}
+	priv->width = dev_get_driver_data(dev);
+
+	if (!priv->width) {
+		debug("No I2C MUX width specified\n");
+		return -EINVAL;
+	}
+
+	debug("Device %s at 0x%x with width %d\n",
+	      dev->name, priv->addr, priv->width);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(pca954x) = {
+	.name = "pca954x",
+	.id = UCLASS_I2C_MUX,
+	.of_match = pca954x_ids,
+	.ops = &pca954x_ops,
+	.ofdata_to_platdata = pca954x_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct pca954x_priv),
+};
-- 
cgit v0.10.2


From b6a77b0ce8ac21c154f02907c364b6d3e3c8af5e Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 27 Apr 2016 09:02:12 +0200
Subject: i2c: designware_i2c: Optionally check enable status register

Some platforms don't implement the enable status register at offset 0x9c.
The SPEAr600 platform is one of them. The recently added check to this
status register can't be performend on these platforms.

This patch introduces a new config option that can be enabled on such
platforms not supporting this register.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 0c7cd0b..e60fd0a 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -36,6 +36,14 @@ struct dw_i2c {
 	struct dw_scl_sda_cfg *scl_sda_cfg;
 };
 
+#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+{
+	u32 ena = enable ? IC_ENABLE_0B : 0;
+
+	writel(ena, &i2c_base->ic_enable);
+}
+#else
 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
 	u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -56,6 +64,7 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 
 	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
 }
+#endif
 
 /*
  * i2c_set_bus_speed - Set the i2c speed
-- 
cgit v0.10.2


From ec2c81c5d4681274f9f9d079b08ed259ff20dc69 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:01 +0200
Subject: dm: fsl_i2c: Rename I2C register structure

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h
index 1b1c25e..c7d2aa3 100644
--- a/arch/m68k/include/asm/fsl_i2c.h
+++ b/arch/m68k/include/asm/fsl_i2c.h
@@ -16,7 +16,7 @@
 
 #include <asm/types.h>
 
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
 
 	u8 adr;		/* I2C slave address */
 	u8 res0[3];
diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h
index cbbc834..e94bdc6 100644
--- a/arch/powerpc/include/asm/fsl_i2c.h
+++ b/arch/powerpc/include/asm/fsl_i2c.h
@@ -16,7 +16,7 @@
 
 #include <asm/types.h>
 
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
 
 	u8 adr;		/* I2C slave address */
 	u8 res0[3];
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 53ca6d9..07d2adf 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -120,8 +120,8 @@ typedef struct ccsr_local_ecm {
 
 /* I2C Registers */
 typedef struct ccsr_i2c {
-	struct fsl_i2c	i2c[1];
-	u8	res[4096 - 1 * sizeof(struct fsl_i2c)];
+	struct fsl_i2c_base	i2c[1];
+	u8	res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
 #if defined(CONFIG_MPC8540) \
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 177918b..b078569 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -92,8 +92,8 @@ typedef struct ccsr_local_mcm {
 
 /* Daul I2C Registers(0x3000-0x4000) */
 typedef struct ccsr_i2c {
-	struct fsl_i2c	i2c[2];
-	u8	res[4096 - 2 * sizeof(struct fsl_i2c)];
+	struct fsl_i2c_base	i2c[2];
+	u8	res[4096 - 2 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
 /* DUART Registers(0x4000-0x5000) */
diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c
index c961937..f0b528d 100644
--- a/board/keymile/km83xx/km83xx_i2c.c
+++ b/board/keymile/km83xx/km83xx_i2c.c
@@ -13,31 +13,33 @@
 
 static void i2c_write_start_seq(void)
 {
-	struct fsl_i2c *dev;
-	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+	struct fsl_i2c_base *base;
+	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+			CONFIG_SYS_I2C_OFFSET);
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN));
+	out_8(&base->cr, (I2C_CR_MEN));
 }
 
 int i2c_make_abort(void)
 {
-	struct fsl_i2c *dev;
-	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+	struct fsl_i2c_base *base;
+	base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+			CONFIG_SYS_I2C_OFFSET);
 	uchar   last;
 	int     nbr_read = 0;
 	int     i = 0;
 	int	    ret = 0;
 
 	/* wait after each operation to finsh with a delay */
-	out_8(&dev->cr, (I2C_CR_MSTA));
+	out_8(&base->cr, (I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+	out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
 	udelay(DELAY_ABORT_SEQ);
-	in_8(&dev->dr);
+	in_8(&base->dr);
 	udelay(DELAY_ABORT_SEQ);
-	last = in_8(&dev->dr);
+	last = in_8(&base->dr);
 	nbr_read++;
 
 	/*
@@ -47,7 +49,7 @@ int i2c_make_abort(void)
 	while (((last & 0x01) != 0x01) &&
 		(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
 		udelay(DELAY_ABORT_SEQ);
-		last = in_8(&dev->dr);
+		last = in_8(&base->dr);
 		nbr_read++;
 	}
 	if ((last & 0x01) != 0x01)
@@ -56,10 +58,10 @@ int i2c_make_abort(void)
 		printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
 			nbr_read, last);
 	udelay(DELAY_ABORT_SEQ);
-	out_8(&dev->cr, (I2C_CR_MEN));
+	out_8(&base->cr, (I2C_CR_MEN));
 	udelay(DELAY_ABORT_SEQ);
 	/* clear status reg */
-	out_8(&dev->sr, 0);
+	out_8(&base->sr, 0);
 
 	for (i = 0; i < 5; i++)
 		i2c_write_start_seq();
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index b56a1c2..70c7cba 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -34,16 +34,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct fsl_i2c *i2c_dev[4] = {
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
+static const struct fsl_i2c_base *i2c_base[4] = {
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
 #endif
 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
 #endif
 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
-	(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
+	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
 #endif
 };
 
@@ -104,7 +104,7 @@ static const struct {
 /**
  * Set the I2C bus speed for a given I2C device
  *
- * @param dev: the I2C device
+ * @param base: the I2C device registers
  * @i2c_clk: I2C bus clock frequency
  * @speed: the desired speed of the bus
  *
@@ -112,7 +112,7 @@ static const struct {
  *
  * The return value is the actual bus speed that is set.
  */
-static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
+static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
 	unsigned int i2c_clk, unsigned int speed)
 {
 	unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
@@ -173,8 +173,8 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
 	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
 	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
 #endif
-	writeb(dfsr, &dev->dfsrr);	/* set default filter */
-	writeb(fdr, &dev->fdr);		/* set bus speed */
+	writeb(dfsr, &base->dfsrr);	/* set default filter */
+	writeb(fdr, &base->fdr);	/* set bus speed */
 #else
 	unsigned int i;
 
@@ -184,7 +184,7 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
 
 			fdr = fsl_i2c_speed_map[i].fdr;
 			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
-			writeb(fdr, &dev->fdr);		/* set bus speed */
+			writeb(fdr, &base->fdr);	/* set bus speed */
 
 			break;
 		}
@@ -200,7 +200,7 @@ static unsigned int get_i2c_clock(int bus)
 		return gd->arch.i2c1_clk;	/* I2C1 clock */
 }
 
-static int fsl_i2c_fixup(const struct fsl_i2c *dev)
+static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
 {
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 	unsigned long long timeval = 0;
@@ -214,34 +214,34 @@ static int fsl_i2c_fixup(const struct fsl_i2c *dev)
 		flags = I2C_CR_BIT6;
 #endif
 
-	writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
+	writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
 
 	timeval = get_ticks();
-	while (!(readb(&dev->sr) & I2C_SR_MBB)) {
+	while (!(readb(&base->sr) & I2C_SR_MBB)) {
 		if ((get_ticks() - timeval) > timeout)
 			goto err;
 	}
 
-	if (readb(&dev->sr) & I2C_SR_MAL) {
+	if (readb(&base->sr) & I2C_SR_MAL) {
 		/* SDA is stuck low */
-		writeb(0, &dev->cr);
+		writeb(0, &base->cr);
 		udelay(100);
-		writeb(I2C_CR_MSTA | flags, &dev->cr);
-		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
+		writeb(I2C_CR_MSTA | flags, &base->cr);
+		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
 	}
 
-	readb(&dev->dr);
+	readb(&base->dr);
 
 	timeval = get_ticks();
-	while (!(readb(&dev->sr) & I2C_SR_MIF)) {
+	while (!(readb(&base->sr) & I2C_SR_MIF)) {
 		if ((get_ticks() - timeval) > timeout)
 			goto err;
 	}
 	ret = 0;
 
 err:
-	writeb(I2C_CR_MEN | flags, &dev->cr);
-	writeb(0, &dev->sr);
+	writeb(I2C_CR_MEN | flags, &base->cr);
+	writeb(0, &base->sr);
 	udelay(100);
 
 	return ret;
@@ -249,7 +249,7 @@ err:
 
 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
-	const struct fsl_i2c *dev;
+	const struct fsl_i2c_base *base;
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 	unsigned long long timeval;
 
@@ -260,21 +260,21 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 	*/
 	i2c_init_board();
 #endif
-	dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	base = (struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 
-	writeb(0, &dev->cr);		/* stop I2C controller */
+	writeb(0, &base->cr);		/* stop I2C controller */
 	udelay(5);			/* let it shutdown in peace */
-	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
-	writeb(slaveadd << 1, &dev->adr);/* write slave address */
-	writeb(0x0, &dev->sr);		/* clear status register */
-	writeb(I2C_CR_MEN, &dev->cr);	/* start I2C controller */
+	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
+	writeb(slaveadd << 1, &base->adr);/* write slave address */
+	writeb(0x0, &base->sr);		/* clear status register */
+	writeb(I2C_CR_MEN, &base->cr);	/* start I2C controller */
 
 	timeval = get_ticks();
-	while (readb(&dev->sr) & I2C_SR_MBB) {
+	while (readb(&base->sr) & I2C_SR_MBB) {
 		if ((get_ticks() - timeval) < timeout)
 			continue;
 
-		if (fsl_i2c_fixup(dev))
+		if (fsl_i2c_fixup(base))
 			debug("i2c_init: BUS#%d failed to init\n",
 			      adap->hwadapnr);
 
@@ -294,11 +294,12 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 static int
 i2c_wait4bus(struct i2c_adapter *adap)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	unsigned long long timeval = get_ticks();
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 
-	while (readb(&dev->sr) & I2C_SR_MBB) {
+	while (readb(&base->sr) & I2C_SR_MBB) {
 		if ((get_ticks() - timeval) > timeout)
 			return -1;
 	}
@@ -312,16 +313,17 @@ i2c_wait(struct i2c_adapter *adap, int write)
 	u32 csr;
 	unsigned long long timeval = get_ticks();
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 
 	do {
-		csr = readb(&dev->sr);
+		csr = readb(&base->sr);
 		if (!(csr & I2C_SR_MIF))
 			continue;
 		/* Read again to allow register to stabilise */
-		csr = readb(&dev->sr);
+		csr = readb(&base->sr);
 
-		writeb(0x0, &dev->sr);
+		writeb(0x0, &base->sr);
 
 		if (csr & I2C_SR_MAL) {
 			debug("i2c_wait: MAL\n");
@@ -348,13 +350,14 @@ i2c_wait(struct i2c_adapter *adap, int write)
 static __inline__ int
 i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
 {
-	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 	       | (rsta ? I2C_CR_RSTA : 0),
-	       &device->cr);
+	       &base->cr);
 
-	writeb((dev << 1) | dir, &device->dr);
+	writeb((dev << 1) | dir, &base->dr);
 
 	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
 		return 0;
@@ -365,11 +368,12 @@ i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
 static __inline__ int
 __i2c_write(struct i2c_adapter *adap, u8 *data, int length)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int i;
 
 	for (i = 0; i < length; i++) {
-		writeb(data[i], &dev->dr);
+		writeb(data[i], &base->dr);
 
 		if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
 			break;
@@ -381,14 +385,15 @@ __i2c_write(struct i2c_adapter *adap, u8 *data, int length)
 static __inline__ int
 __i2c_read(struct i2c_adapter *adap, u8 *data, int length)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int i;
 
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
-	       &dev->cr);
+	       &base->cr);
 
 	/* dummy read */
-	readb(&dev->dr);
+	readb(&base->dr);
 
 	for (i = 0; i < length; i++) {
 		if (i2c_wait(adap, I2C_READ_BIT) < 0)
@@ -397,14 +402,14 @@ __i2c_read(struct i2c_adapter *adap, u8 *data, int length)
 		/* Generate ack on last next to last byte */
 		if (i == length - 2)
 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
-			       &dev->cr);
+			       &base->cr);
 
 		/* Do not generate stop on last byte */
 		if (i == length - 1)
 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
-			       &dev->cr);
+			       &base->cr);
 
-		data[i] = readb(&dev->dr);
+		data[i] = readb(&base->dr);
 	}
 
 	return i;
@@ -414,7 +419,8 @@ static int
 fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
 	     int length)
 {
-	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int i = -1; /* signal error */
 	u8 *a = (u8*)&addr;
 	int len = alen * -1;
@@ -457,7 +463,7 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
 			i = __i2c_read(adap, data, length);
 	}
 
-	writeb(I2C_CR_MEN, &device->cr);
+	writeb(I2C_CR_MEN, &base->cr);
 
 	if (i2c_wait4bus(adap)) /* Wait until STOP */
 		debug("i2c_read: wait4bus timed out\n");
@@ -472,7 +478,8 @@ static int
 fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
 	      u8 *data, int length)
 {
-	struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int i = -1; /* signal error */
 	u8 *a = (u8*)&addr;
 
@@ -484,7 +491,7 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
 		i = __i2c_write(adap, data, length);
 	}
 
-	writeb(I2C_CR_MEN, &device->cr);
+	writeb(I2C_CR_MEN, &base->cr);
 	if (i2c_wait4bus(adap)) /* Wait until STOP */
 		debug("i2c_write: wait4bus timed out\n");
 
@@ -497,12 +504,13 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
 static int
 fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	/* For unknow reason the controller will ACK when
 	 * probing for a slave with the same address, so skip
 	 * it.
 	 */
-	if (chip == (readb(&dev->adr) >> 1))
+	if (chip == (readb(&base->adr) >> 1))
 		return -1;
 
 	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
@@ -511,11 +519,12 @@ fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
 			unsigned int speed)
 {
-	struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+	struct fsl_i2c_base *base =
+		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 
-	writeb(0, &dev->cr);		/* stop controller */
-	set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
-	writeb(I2C_CR_MEN, &dev->cr);	/* start controller */
+	writeb(0, &base->cr);		/* stop controller */
+	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
+	writeb(I2C_CR_MEN, &base->cr);	/* start controller */
 
 	return 0;
 }
-- 
cgit v0.10.2


From 2b21e960348998fbaefc802613c37bfb6321969b Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:02 +0200
Subject: dm: fsl_i2c: Use clearer parameter names

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 70c7cba..b0e65fc 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -416,24 +416,24 @@ __i2c_read(struct i2c_adapter *adap, u8 *data, int length)
 }
 
 static int
-fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
-	     int length)
+fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	     u8 *data, int dlen)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
-	int i = -1; /* signal error */
-	u8 *a = (u8*)&addr;
-	int len = alen * -1;
+	int ret = -1; /* signal error */
+	u8 *o = (u8 *)&offset;
+	int len = olen * -1;
 
 	if (i2c_wait4bus(adap) < 0)
 		return -1;
 
 	/* To handle the need of I2C devices that require to write few bytes
 	 * (more than 4 bytes of address as in the case of else part)
-	 * of data before reading, Negative equivalent of length(bytes to write)
+	 * of data before reading, Negative equivalent of dlen(bytes to write)
 	 * is passed, but used the +ve part of len for writing data
 	 */
-	if (alen < 0) {
+	if (olen < 0) {
 		/* Generate a START and send the Address and
 		 * the Tx Bytes to the slave.
 		 * "START: Address: Write bytes data[len]"
@@ -444,23 +444,24 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
 		 * "data", which will eventually keep the data READ,
 		 * after writing the len bytes out of it
 		 */
-		if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
-			i = __i2c_write(adap, data, len);
+		if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
+			ret = __i2c_write(adap, data, len);
 
-		if (i != len)
+		if (ret != len)
 			return -1;
 
-		if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
-			i = __i2c_read(adap, data, length);
+		if (dlen && i2c_write_addr(adap, chip_addr,
+					   I2C_READ_BIT, 1) != 0)
+			ret = __i2c_read(adap, data, dlen);
 	} else {
-		if ((!length || alen > 0) &&
-		    i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0  &&
-		    __i2c_write(adap, &a[4 - alen], alen) == alen)
-			i = 0; /* No error so far */
-
-		if (length &&
-		    i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
-			i = __i2c_read(adap, data, length);
+		if ((!dlen || olen > 0) &&
+		    i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
+		    __i2c_write(adap, &o[4 - olen], olen) == olen)
+			ret = 0; /* No error so far */
+
+		if (dlen && i2c_write_addr(adap, chip_addr, I2C_READ_BIT,
+					   olen ? 1 : 0) != 0)
+			ret = __i2c_read(adap, data, dlen);
 	}
 
 	writeb(I2C_CR_MEN, &base->cr);
@@ -468,35 +469,35 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
 	if (i2c_wait4bus(adap)) /* Wait until STOP */
 		debug("i2c_read: wait4bus timed out\n");
 
-	if (i == length)
-	    return 0;
+	if (ret == dlen)
+		return 0;
 
 	return -1;
 }
 
 static int
-fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
-	      u8 *data, int length)
+fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	      u8 *data, int dlen)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
-	int i = -1; /* signal error */
-	u8 *a = (u8*)&addr;
+	int ret = -1; /* signal error */
+	u8 *o = (u8 *)&offset;
 
 	if (i2c_wait4bus(adap) < 0)
 		return -1;
 
-	if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
-	    __i2c_write(adap, &a[4 - alen], alen) == alen) {
-		i = __i2c_write(adap, data, length);
+	if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+	    __i2c_write(adap, &o[4 - olen], olen) == olen) {
+		ret = __i2c_write(adap, data, dlen);
 	}
 
 	writeb(I2C_CR_MEN, &base->cr);
 	if (i2c_wait4bus(adap)) /* Wait until STOP */
 		debug("i2c_write: wait4bus timed out\n");
 
-	if (i == length)
-	    return 0;
+	if (ret == dlen)
+		return 0;
 
 	return -1;
 }
-- 
cgit v0.10.2


From 386b276918541f4108b56f0c7c422b64396f64f2 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:03 +0200
Subject: dm: fsl_i2c: Reword and clarify comment

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index b0e65fc..18b8848 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -428,22 +428,14 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 	if (i2c_wait4bus(adap) < 0)
 		return -1;
 
-	/* To handle the need of I2C devices that require to write few bytes
-	 * (more than 4 bytes of address as in the case of else part)
-	 * of data before reading, Negative equivalent of dlen(bytes to write)
-	 * is passed, but used the +ve part of len for writing data
+	/* Some drivers use offset lengths in excess of 4 bytes. These drivers
+	 * adhere to the following convention:
+	 * - the offset length is passed as negative (that is, the absolute
+	 *   value of olen is the actual offset length)
+	 * - the offset itself is passed in data, which is overwritten by the
+	 *   subsequent read operation
 	 */
 	if (olen < 0) {
-		/* Generate a START and send the Address and
-		 * the Tx Bytes to the slave.
-		 * "START: Address: Write bytes data[len]"
-		 * IF part supports writing any number of bytes in contrast
-		 * to the else part, which supports writing address offset
-		 * of upto 4 bytes only.
-		 * bytes that need to be written are passed in
-		 * "data", which will eventually keep the data READ,
-		 * after writing the len bytes out of it
-		 */
 		if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
 			ret = __i2c_write(adap, data, len);
 
-- 
cgit v0.10.2


From 03a112aad6893ab1059e716b7bfc36fe759eaec5 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:04 +0200
Subject: dm: fsl_i2c: Remove unnecessary variable

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 18b8848..4bc1dda 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -423,7 +423,6 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int ret = -1; /* signal error */
 	u8 *o = (u8 *)&offset;
-	int len = olen * -1;
 
 	if (i2c_wait4bus(adap) < 0)
 		return -1;
@@ -437,9 +436,9 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 	 */
 	if (olen < 0) {
 		if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
-			ret = __i2c_write(adap, data, len);
+			ret = __i2c_write(adap, data, -olen);
 
-		if (ret != len)
+		if (ret != -olen)
 			return -1;
 
 		if (dlen && i2c_write_addr(adap, chip_addr,
-- 
cgit v0.10.2


From 16579ecbccb96a677ab468eba3e5a8e260751126 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:05 +0200
Subject: dm: fsl_i2c: Rename probe method

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 4bc1dda..3a38713 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -494,7 +494,7 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 }
 
 static int
-fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
+fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
@@ -524,24 +524,24 @@ static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
 /*
  * Register fsl i2c adapters
  */
-U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
 			 0)
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
 			 1)
 #endif
 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
 			 2)
 #endif
 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 fsl_i2c_write, fsl_i2c_set_bus_speed,
 			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
 			 3)
-- 
cgit v0.10.2


From 00b61553f1248e7a57c3de6bf050a1489823db11 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:06 +0200
Subject: dm: fsl_i2c: Rename methods for reading/writing data

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 3a38713..b838afd 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -366,7 +366,7 @@ i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
 }
 
 static __inline__ int
-__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
+__i2c_write_data(struct i2c_adapter *adap, u8 *data, int length)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
@@ -383,7 +383,7 @@ __i2c_write(struct i2c_adapter *adap, u8 *data, int length)
 }
 
 static __inline__ int
-__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
+__i2c_read_data(struct i2c_adapter *adap, u8 *data, int length)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
@@ -436,23 +436,23 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 	 */
 	if (olen < 0) {
 		if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
-			ret = __i2c_write(adap, data, -olen);
+			ret = __i2c_write_data(adap, data, -olen);
 
 		if (ret != -olen)
 			return -1;
 
 		if (dlen && i2c_write_addr(adap, chip_addr,
 					   I2C_READ_BIT, 1) != 0)
-			ret = __i2c_read(adap, data, dlen);
+			ret = __i2c_read_data(adap, data, dlen);
 	} else {
 		if ((!dlen || olen > 0) &&
 		    i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
-		    __i2c_write(adap, &o[4 - olen], olen) == olen)
+		    __i2c_write_data(adap, &o[4 - olen], olen) == olen)
 			ret = 0; /* No error so far */
 
 		if (dlen && i2c_write_addr(adap, chip_addr, I2C_READ_BIT,
 					   olen ? 1 : 0) != 0)
-			ret = __i2c_read(adap, data, dlen);
+			ret = __i2c_read_data(adap, data, dlen);
 	}
 
 	writeb(I2C_CR_MEN, &base->cr);
@@ -479,8 +479,8 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 		return -1;
 
 	if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
-	    __i2c_write(adap, &o[4 - olen], olen) == olen) {
-		ret = __i2c_write(adap, data, dlen);
+	    __i2c_write_data(adap, &o[4 - olen], olen) == olen) {
+		ret = __i2c_write_data(adap, data, dlen);
 	}
 
 	writeb(I2C_CR_MEN, &base->cr);
-- 
cgit v0.10.2


From ad7e657cec8587b63dbf82d793cda54b74413a0a Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:07 +0200
Subject: dm: fsl_i2c: Prepare compatibility functions

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index b838afd..06f1db4 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -247,7 +247,7 @@ err:
 	return ret;
 }
 
-static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	const struct fsl_i2c_base *base;
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
@@ -416,8 +416,8 @@ __i2c_read_data(struct i2c_adapter *adap, u8 *data, int length)
 }
 
 static int
-fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
-	     u8 *data, int dlen)
+__i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	   u8 *data, int dlen)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
@@ -467,8 +467,8 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 }
 
 static int
-fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
-	      u8 *data, int dlen)
+__i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	    u8 *data, int dlen)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
@@ -494,7 +494,7 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 }
 
 static int
-fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+__i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 {
 	struct fsl_i2c_base *base =
 		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
@@ -505,10 +505,10 @@ fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 	if (chip == (readb(&base->adr) >> 1))
 		return -1;
 
-	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
+	return __i2c_read(adap, chip, 0, 0, NULL, 0);
 }
 
-static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
+static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
 			unsigned int speed)
 {
 	struct fsl_i2c_base *base =
@@ -521,6 +521,37 @@ static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
 	return 0;
 }
 
+static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+	__i2c_init(adap, speed, slaveadd);
+}
+
+static int
+fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+{
+	return __i2c_probe_chip(adap, chip);
+}
+
+static int
+fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	     u8 *data, int dlen)
+{
+	return __i2c_read(adap, chip_addr, offset, olen, data, dlen);
+}
+
+static int
+fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+	      u8 *data, int dlen)
+{
+	return __i2c_write(adap, chip_addr, offset, olen, data, dlen);
+}
+
+static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
+					  unsigned int speed)
+{
+	return __i2c_set_bus_speed(adap, speed);
+}
+
 /*
  * Register fsl i2c adapters
  */
-- 
cgit v0.10.2


From ecf591e303ed576817f0638ade56e2fab7d910c8 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:08 +0200
Subject: dm: fsl_i2c: Factor out adap parameter

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 06f1db4..7d99f48 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -247,9 +247,9 @@ err:
 	return ret;
 }
 
-static void __i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
+		       slaveadd, int i2c_clk, int busnum)
 {
-	const struct fsl_i2c_base *base;
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 	unsigned long long timeval;
 
@@ -260,11 +260,9 @@ static void __i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 	*/
 	i2c_init_board();
 #endif
-	base = (struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
-
 	writeb(0, &base->cr);		/* stop I2C controller */
 	udelay(5);			/* let it shutdown in peace */
-	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
+	set_i2c_bus_speed(base, i2c_clk, speed);
 	writeb(slaveadd << 1, &base->adr);/* write slave address */
 	writeb(0x0, &base->sr);		/* clear status register */
 	writeb(I2C_CR_MEN, &base->cr);	/* start I2C controller */
@@ -276,7 +274,7 @@ static void __i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 
 		if (fsl_i2c_fixup(base))
 			debug("i2c_init: BUS#%d failed to init\n",
-			      adap->hwadapnr);
+			      busnum);
 
 		break;
 	}
@@ -292,10 +290,8 @@ static void __i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 }
 
 static int
-i2c_wait4bus(struct i2c_adapter *adap)
+i2c_wait4bus(const struct fsl_i2c_base *base)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	unsigned long long timeval = get_ticks();
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 
@@ -307,14 +303,12 @@ i2c_wait4bus(struct i2c_adapter *adap)
 	return 0;
 }
 
-static __inline__ int
-i2c_wait(struct i2c_adapter *adap, int write)
+static inline int
+i2c_wait(const struct fsl_i2c_base *base, int write)
 {
 	u32 csr;
 	unsigned long long timeval = get_ticks();
 	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 
 	do {
 		csr = readb(&base->sr);
@@ -347,46 +341,39 @@ i2c_wait(struct i2c_adapter *adap, int write)
 	return -1;
 }
 
-static __inline__ int
-i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
+static inline int
+i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
-
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 	       | (rsta ? I2C_CR_RSTA : 0),
 	       &base->cr);
 
 	writeb((dev << 1) | dir, &base->dr);
 
-	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+	if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 		return 0;
 
 	return 1;
 }
 
-static __inline__ int
-__i2c_write_data(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int i;
 
 	for (i = 0; i < length; i++) {
 		writeb(data[i], &base->dr);
 
-		if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+		if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 			break;
 	}
 
 	return i;
 }
 
-static __inline__ int
-__i2c_read_data(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int i;
 
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
@@ -396,7 +383,7 @@ __i2c_read_data(struct i2c_adapter *adap, u8 *data, int length)
 	readb(&base->dr);
 
 	for (i = 0; i < length; i++) {
-		if (i2c_wait(adap, I2C_READ_BIT) < 0)
+		if (i2c_wait(base, I2C_READ_BIT) < 0)
 			break;
 
 		/* Generate ack on last next to last byte */
@@ -416,15 +403,12 @@ __i2c_read_data(struct i2c_adapter *adap, u8 *data, int length)
 }
 
 static int
-__i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
 	   u8 *data, int dlen)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int ret = -1; /* signal error */
-	u8 *o = (u8 *)&offset;
 
-	if (i2c_wait4bus(adap) < 0)
+	if (i2c_wait4bus(base) < 0)
 		return -1;
 
 	/* Some drivers use offset lengths in excess of 4 bytes. These drivers
@@ -435,29 +419,29 @@ __i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 	 *   subsequent read operation
 	 */
 	if (olen < 0) {
-		if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
-			ret = __i2c_write_data(adap, data, -olen);
+		if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
+			ret = __i2c_write_data(base, data, -olen);
 
 		if (ret != -olen)
 			return -1;
 
-		if (dlen && i2c_write_addr(adap, chip_addr,
+		if (dlen && i2c_write_addr(base, chip_addr,
 					   I2C_READ_BIT, 1) != 0)
-			ret = __i2c_read_data(adap, data, dlen);
+			ret = __i2c_read_data(base, data, dlen);
 	} else {
 		if ((!dlen || olen > 0) &&
-		    i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
-		    __i2c_write_data(adap, &o[4 - olen], olen) == olen)
+		    i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
+		    __i2c_write_data(base, offset, olen) == olen)
 			ret = 0; /* No error so far */
 
-		if (dlen && i2c_write_addr(adap, chip_addr, I2C_READ_BIT,
+		if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
 					   olen ? 1 : 0) != 0)
-			ret = __i2c_read_data(adap, data, dlen);
+			ret = __i2c_read_data(base, data, dlen);
 	}
 
 	writeb(I2C_CR_MEN, &base->cr);
 
-	if (i2c_wait4bus(adap)) /* Wait until STOP */
+	if (i2c_wait4bus(base)) /* Wait until STOP */
 		debug("i2c_read: wait4bus timed out\n");
 
 	if (ret == dlen)
@@ -467,24 +451,21 @@ __i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 }
 
 static int
-__i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
 	    u8 *data, int dlen)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	int ret = -1; /* signal error */
-	u8 *o = (u8 *)&offset;
 
-	if (i2c_wait4bus(adap) < 0)
+	if (i2c_wait4bus(base) < 0)
 		return -1;
 
-	if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
-	    __i2c_write_data(adap, &o[4 - olen], olen) == olen) {
-		ret = __i2c_write_data(adap, data, dlen);
+	if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+	    __i2c_write_data(base, offset, olen) == olen) {
+		ret = __i2c_write_data(base, data, dlen);
 	}
 
 	writeb(I2C_CR_MEN, &base->cr);
-	if (i2c_wait4bus(adap)) /* Wait until STOP */
+	if (i2c_wait4bus(base)) /* Wait until STOP */
 		debug("i2c_write: wait4bus timed out\n");
 
 	if (ret == dlen)
@@ -494,10 +475,8 @@ __i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 }
 
 static int
-__i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
 	/* For unknow reason the controller will ACK when
 	 * probing for a slave with the same address, so skip
 	 * it.
@@ -505,17 +484,14 @@ __i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 	if (chip == (readb(&base->adr) >> 1))
 		return -1;
 
-	return __i2c_read(adap, chip, 0, 0, NULL, 0);
+	return __i2c_read(base, chip, 0, 0, NULL, 0);
 }
 
-static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
-			unsigned int speed)
+static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base,
+			unsigned int speed, int i2c_clk)
 {
-	struct fsl_i2c_base *base =
-		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
-
 	writeb(0, &base->cr);		/* stop controller */
-	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
+	set_i2c_bus_speed(base, i2c_clk, speed);
 	writeb(I2C_CR_MEN, &base->cr);	/* start controller */
 
 	return 0;
@@ -523,33 +499,39 @@ static unsigned int __i2c_set_bus_speed(struct i2c_adapter *adap,
 
 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
-	__i2c_init(adap, speed, slaveadd);
+	__i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
+		   get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
 }
 
 static int
 fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 {
-	return __i2c_probe_chip(adap, chip);
+	return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
 }
 
 static int
 fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 	     u8 *data, int dlen)
 {
-	return __i2c_read(adap, chip_addr, offset, olen, data, dlen);
+	u8 *o = (u8 *)&offset;
+	return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+			  olen, data, dlen);
 }
 
 static int
 fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
 	      u8 *data, int dlen)
 {
-	return __i2c_write(adap, chip_addr, offset, olen, data, dlen);
+	u8 *o = (u8 *)&offset;
+	return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+			   olen, data, dlen);
 }
 
 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
 					  unsigned int speed)
 {
-	return __i2c_set_bus_speed(adap, speed);
+	return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
+				   get_i2c_clock(adap->hwadapnr));
 }
 
 /*
-- 
cgit v0.10.2


From dbc82ce31b4e90ed171c10e02d382d36bf201dc4 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 08:31:09 +0200
Subject: dm: fsl_i2c: Enable DM for FSL I2C

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h
index e94bdc6..d2586f9 100644
--- a/arch/powerpc/include/asm/fsl_i2c.h
+++ b/arch/powerpc/include/asm/fsl_i2c.h
@@ -68,4 +68,14 @@ typedef struct fsl_i2c_base {
 	u8 res6[0xE8];
 } fsl_i2c_t;
 
+#ifdef CONFIG_DM_I2C
+struct fsl_i2c_dev {
+	struct fsl_i2c_base __iomem *base;      /* register base */
+	u32 i2c_clk;
+	u32 index;
+	u8 slaveadd;
+	uint speed;
+};
+#endif
+
 #endif	/* _ASM_I2C_H_ */
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 9324c6c..ffe18f7 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,13 @@ config DM_I2C_GPIO
 	  bindings are supported.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_FSL
+       bool "Freescale I2C bus driver"
+       depends on DM_I2C
+       help
+	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
+	  MPC85xx processors.
+
 config SYS_I2C_CADENCE
 	tristate "Cadence I2C Controller"
 	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 7d99f48..b8cc647 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -12,6 +12,8 @@
 #include <i2c.h>		/* Functional interface */
 #include <asm/io.h>
 #include <asm/fsl_i2c.h>	/* HW definitions */
+#include <dm.h>
+#include <mapmem.h>
 
 /* The maximum number of microseconds we will wait until another master has
  * released the bus.  If not defined in the board header file, then use a
@@ -34,6 +36,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_DM_I2C
 static const struct fsl_i2c_base *i2c_base[4] = {
 	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
@@ -46,6 +49,7 @@ static const struct fsl_i2c_base *i2c_base[4] = {
 	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
 #endif
 };
+#endif
 
 /* I2C speed map for a DFSR value of 1 */
 
@@ -192,6 +196,7 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
 	return speed;
 }
 
+#ifndef CONFIG_DM_I2C
 static unsigned int get_i2c_clock(int bus)
 {
 	if (bus)
@@ -199,6 +204,7 @@ static unsigned int get_i2c_clock(int bus)
 	else
 		return gd->arch.i2c1_clk;	/* I2C1 clock */
 }
+#endif
 
 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
 {
@@ -497,6 +503,7 @@ static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base,
 	return 0;
 }
 
+#ifndef CONFIG_DM_I2C
 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	__i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
@@ -559,3 +566,99 @@ U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
 			 3)
 #endif
+#else /* CONFIG_DM_I2C */
+static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+			      u32 chip_flags)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
+}
+
+static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	u64 reg;
+	u32 addr, size;
+
+	reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg");
+	addr = reg >> 32;
+	size = reg & 0xFFFFFFFF;
+
+	dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+	if (!dev->base)
+		return -ENOMEM;
+
+	dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				    "cell-index", -1);
+	dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				       "u-boot,i2c-slave-addr", 0x7f);
+	dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				    "clock-frequency", 400000);
+
+	dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
+
+	return 0;
+}
+
+static int fsl_i2c_probe(struct udevice *bus)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	__i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
+		   dev->index);
+	return 0;
+}
+
+static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct fsl_i2c_dev *dev = dev_get_priv(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
+	/* We expect either two messages (one with an offset and one with the
+	 * actucal data) or one message (just data) */
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported.", __func__);
+		return -1;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	if (dmsg->flags & I2C_M_RD)
+		return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
+				  dmsg->buf, dmsg->len);
+	else
+		return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
+				   dmsg->buf, dmsg->len);
+}
+
+static const struct dm_i2c_ops fsl_i2c_ops = {
+	.xfer           = fsl_i2c_xfer,
+	.probe_chip     = fsl_i2c_probe_chip,
+	.set_bus_speed  = fsl_i2c_set_bus_speed,
+};
+
+static const struct udevice_id fsl_i2c_ids[] = {
+	{ .compatible = "fsl-i2c", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_fsl) = {
+	.name = "i2c_fsl",
+	.id = UCLASS_I2C,
+	.of_match = fsl_i2c_ids,
+	.probe = fsl_i2c_probe,
+	.ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
+	.ops = &fsl_i2c_ops,
+};
+
+#endif /* CONFIG_DM_I2C */
-- 
cgit v0.10.2


From e32d0db7985eece55ad099c6c86d00d441fdf48c Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 28 Apr 2016 09:47:17 +0200
Subject: i2c: Add entry for Designware I2C driver in Kconfig

This patch adds an entry for the Designware I2C driver in Kconfig.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index ffe18f7..193b9f5 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -72,6 +72,14 @@ config SYS_I2C_CADENCE
 	  Say yes here to select Cadence I2C Host Controller. This controller is
 	  e.g. used by Xilinx Zynq.
 
+config SYS_I2C_DW
+	bool "Designware I2C Controller"
+	default n
+	help
+	  Say yes here to select the Designware I2C Host Controller. This
+	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
+	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
+
 config SYS_I2C_INTEL
 	bool "Intel I2C/SMBUS driver"
 	depends on DM_I2C
-- 
cgit v0.10.2


From 4d5e9b39e21152734ffa4b533efbb83f278df18b Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 28 Apr 2016 09:47:18 +0200
Subject: i2c: config: Move SYS_I2C_DW to Kconfig

This patch moves all appearances of CONFIG_SYS_I2C_DW from the config
header to the defconfig files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 85af09e..07a6a18 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -18,6 +18,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index aa9bf33..01a5143 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -18,6 +18,7 @@ CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 9a7c091..a662e72 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -33,6 +33,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index ac81854..b2933f7 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -33,6 +33,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 405d9d4..f197b6d 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -32,6 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 3615490..6624f9e 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -32,6 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index bdc8e6b..c6414f8 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -33,6 +33,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index a17e9d0..b47a560 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index c4b215a..aab4498 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -32,6 +32,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index af2f544..db3b6ea 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index 6c53e1f..ea4e8d7 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index 6827701..a2b56f3 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index 477a226..1738489 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index 0991f8e..a6064a5 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index ef30a67..85944c6 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 6cfe220..48efe3d 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index c0d8edf..8edbe0c 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index e9d14ce..b622f74 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index 2e46e64..241a72a 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 8dba79a..49d7c04 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index 7f33c78..70b3025 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index f7d3725..5ced0e1 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index 9e41253..de75b17 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index e61c74e..2202d2e 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index 7410093..35bb036 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index f0e041f..f540839 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -9,5 +9,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index cc4067d..de416d9 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index df21355..8b6e0d0 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index 48140aa..e8b4b0a 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -6,5 +6,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 1a07b9d..ace620b 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 1bd4729..05d2d45 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -59,7 +59,6 @@
  * I2C configuration
  */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #define CONFIG_I2C_ENV_EEPROM_BUS	2
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SPEED1		100000
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 4fdc09a..f657766 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -173,7 +173,6 @@
  * I2C support
  */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #define CONFIG_SYS_I2C_BUS_MAX		4
 #define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
 #define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index c4b6234..7b2d262 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -35,7 +35,6 @@
 
 /* I2C driver configuration */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			0xD0200000
 #elif defined(CONFIG_SPEAR300)
diff --git a/include/configs/x600.h b/include/configs/x600.h
index d7da0b2..5fdd2be 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -85,7 +85,6 @@
 
 /* I2C config options */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
 #define CONFIG_SYS_I2C_BASE			0xD0200000
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
-- 
cgit v0.10.2


From 3a3705280d1d06e4d9a62fbe895dbe03939ad00e Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 28 Apr 2016 09:47:19 +0200
Subject: i2c: Select SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED for SPEAr

The DW I2C controller in the SPEAr SoCs doesn't support the enable
status register check. This patch selects
SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED for these boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 193b9f5..6e22bba 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -80,6 +80,16 @@ config SYS_I2C_DW
 	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
 	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
 
+config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+	bool "DW I2C Enable Status Register not supported"
+	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
+		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
+	default y
+	help
+	  Some versions of the Designware I2C controller do not support the
+	  enable status register. This config option can be enabled in such
+	  cases.
+
 config SYS_I2C_INTEL
 	bool "Intel I2C/SMBUS driver"
 	depends on DM_I2C
-- 
cgit v0.10.2


From d6b7757e41d22e08f21f58d3fe9183a150582f61 Mon Sep 17 00:00:00 2001
From: Chris Packham <judge.packham@gmail.com>
Date: Fri, 13 May 2016 15:19:31 +1200
Subject: i2c: mvtwsi: Eliminate twsi_control_flags

In a system where the initial u-boot location is genuinely NOR flash (as
opposed to RAM or a cache-line setup by a pre-bootloader) writes to the
data section are problematic. At best these writes have no effect, at
worst they put the flash memory into a status mode which changes the
executable code underneath us.

Pass around a stack variable from the top of the twsi i2c driver to
avoid writing to global data.

Signed-off-by: Chris Packham <judge.packham@gmail.com>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 221ff4f..bf44432 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -185,26 +185,17 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status)
 }
 
 /*
- * These flags are ORed to any write to the control register
- * They allow global setting of TWSIEN and ACK.
- * By default none are set.
- * twsi_start() sets TWSIEN (in case the controller was disabled)
- * twsi_recv() sets ACK or resets it depending on expected status.
- */
-static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
-
-/*
  * Assert the START condition, either in a single I2C transaction
  * or inside back-to-back ones (repeated starts).
  */
-static int twsi_start(struct i2c_adapter *adap, int expected_status)
+static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
 	/* globally set TWSIEN in case it was not */
-	twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
+	*flags |= MVTWSI_CONTROL_TWSIEN;
 	/* assert START */
-	writel(twsi_control_flags | MVTWSI_CONTROL_START |
+	writel(*flags | MVTWSI_CONTROL_START |
 				    MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* wait for controller to process START */
 	return twsi_wait(adap, expected_status);
@@ -213,14 +204,15 @@ static int twsi_start(struct i2c_adapter *adap, int expected_status)
 /*
  * Send a byte (i2c address or data).
  */
-static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
+static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
+		     u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
 	/* put byte in data register for sending */
 	writel(byte, &twsi->data);
 	/* clear any pending interrupt -- that'll cause sending */
-	writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* wait for controller to receive byte and check ACK */
 	return twsi_wait(adap, expected_status);
 }
@@ -229,18 +221,18 @@ static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
  * Receive a byte.
  * Global mvtwsi_control_flags variable says if we should ack or nak.
  */
-static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
+static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int expected_status, status;
 
 	/* compute expected status based on ACK bit in global control flags */
-	if (twsi_control_flags & MVTWSI_CONTROL_ACK)
+	if (*flags & MVTWSI_CONTROL_ACK)
 		expected_status = MVTWSI_STATUS_DATA_R_ACK;
 	else
 		expected_status = MVTWSI_STATUS_DATA_R_NAK;
 	/* acknowledge *previous state* and launch receive */
-	writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* wait for controller to receive byte and assert ACK or NAK */
 	status = twsi_wait(adap, expected_status);
 	/* if we did receive expected byte then store it */
@@ -296,8 +288,7 @@ static unsigned int twsi_calc_freq(const int n, const int m)
 static void twsi_reset(struct i2c_adapter *adap)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	/* ensure controller will be enabled by any twsi*() function */
-	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
+
 	/* reset controller */
 	writel(0, &twsi->soft_reset);
 	/* wait 2 ms -- this is what the Marvell LSP does */
@@ -353,7 +344,7 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
 static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
-		     u8 addr)
+		     u8 addr, u8 *flags)
 {
 	int status, expected_addr_status;
 
@@ -363,10 +354,11 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 	else /* writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 	/* assert START */
-	status = twsi_start(adap, expected_start_status);
+	status = twsi_start(adap, expected_start_status, flags);
 	/* send out the address if the start went well */
 	if (status == 0)
-		status = twsi_send(adap, addr, expected_addr_status);
+		status = twsi_send(adap, addr, expected_addr_status,
+				   flags);
 	/* return ok or status of first failure to caller */
 	return status;
 }
@@ -378,13 +370,14 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	u8 dummy_byte;
+	u8 flags = 0;
 	int status;
 
 	/* begin i2c read */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
 	/* dummy read was accepted: receive byte but NAK it. */
 	if (status == 0)
-		status = twsi_recv(adap, &dummy_byte);
+		status = twsi_recv(adap, &dummy_byte, &flags);
 	/* Stop transaction */
 	twsi_stop(adap, 0);
 	/* return 0 or status of first failure */
@@ -405,27 +398,28 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
 {
 	int status;
+	u8 flags = 0;
 
 	/* begin i2c write to send the address bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
 	/* send addr bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK);
+			MVTWSI_STATUS_DATA_W_ACK, &flags);
 	/* begin i2c read to receive eeprom data bytes */
 	if (status == 0)
 		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
-				   (chip << 1) | 1);
+				   (chip << 1) | 1, &flags);
 	/* prepare ACK if at least one byte must be received */
 	if (length > 0)
-		twsi_control_flags |= MVTWSI_CONTROL_ACK;
+		flags |= MVTWSI_CONTROL_ACK;
 	/* now receive actual bytes */
 	while ((status == 0) && length--) {
 		/* reset NAK if we if no more to read now */
 		if (length == 0)
-			twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
+			flags &= ~MVTWSI_CONTROL_ACK;
 		/* read current byte */
-		status = twsi_recv(adap, data++);
+		status = twsi_recv(adap, data++, &flags);
 	}
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
@@ -441,16 +435,18 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
 {
 	int status;
+	u8 flags = 0;
 
 	/* begin i2c write to send the eeprom adress bytes then data bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
 	/* send addr bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK);
+			MVTWSI_STATUS_DATA_W_ACK, &flags);
 	/* send data bytes */
 	while ((status == 0) && (length-- > 0))
-		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
+				   &flags);
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
 	/* return 0 or status of first failure */
-- 
cgit v0.10.2


From 0782a8803d555d80f1a68887a18cc32fc7185627 Mon Sep 17 00:00:00 2001
From: Adrian Alonso <adrian.alonso@nxp.com>
Date: Mon, 2 May 2016 10:29:14 -0500
Subject: imx: tools: imximage: fix CLR bit command

Fix incorrect parametr in CMD_CHECK_BITS_CLR command
Pass CLR parameter to DCD header for CMD_CHECK_BITS_CLR

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>

diff --git a/tools/imximage.c b/tools/imximage.c
index 7c21922..092d550 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -209,7 +209,7 @@ static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 		d = d2;
 		d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
 		d->write_dcd_command.length = cpu_to_be16(4);
-		d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+		d->write_dcd_command.param = DCD_CHECK_BITS_CLR_PARAM;
 		break;
 	default:
 		break;
-- 
cgit v0.10.2


From 9f623326eb67b3475797940a21bb405649c0729b Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Sun, 24 Apr 2016 10:54:19 -0700
Subject: imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5

This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 6ba1034..919d83d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -22,6 +22,7 @@ enum {
 	MX6_PAD_SD1_DAT3__USDHC1_DAT3				= IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT4__USDHC1_DAT4				= IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT5__USDHC1_DAT5				= IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT5__GPIO_5_9				= IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT6__USDHC1_DAT6				= IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
 	MX6_PAD_SD1_DAT7__USDHC1_DAT7				= IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
 	MX6_PAD_KEY_ROW7__GPIO_4_7					= IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
-- 
cgit v0.10.2


From fdb396aae8e024303bb17baa6409c686ffc376be Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 28 Apr 2016 00:50:28 +0200
Subject: ARM: mx6: Enable STDIO deregistering on Novena

Novena supports USB keyboard, which is a pluggable device and can be
unplugged. Thus, we need to be able to deregister it's stdio device.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/include/configs/novena.h b/include/configs/novena.h
index cfb92d6..e938fbc 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -150,6 +150,7 @@
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
-- 
cgit v0.10.2


From 1fb51333952ec59fb83312c777bb3665e68f818d Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Thu, 5 May 2016 13:32:09 -0700
Subject: imx: iomux-v3: fix UART input selects

Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.

diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
index d8b4097..0ab1246 100644
--- a/arch/arm/include/asm/arch-mx7/mx7d_pins.h
+++ b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
@@ -635,7 +635,7 @@ enum {
 	MX7D_PAD_LCD_DATA23__GPIO3_IO28                          = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
 	MX7D_PAD_LCD_DATA23__I2C4_SDA                            = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
 
-	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0),
 
 	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
 	MX7D_PAD_UART1_RX_DATA__I2C1_SCL                         = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
@@ -655,7 +655,7 @@ enum {
 	MX7D_PAD_UART1_TX_DATA__GPIO4_IO1                        = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
 	MX7D_PAD_UART1_TX_DATA__ENET1_MDC                        = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
 
-	MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0),
 
 	MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
 	MX7D_PAD_UART2_RX_DATA__I2C2_SCL                         = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
@@ -667,7 +667,7 @@ enum {
 
 	MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
 
-	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0),
 	MX7D_PAD_UART2_TX_DATA__I2C2_SDA                         = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
 	MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0                    = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
 	MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY                       = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
@@ -695,7 +695,7 @@ enum {
 	MX7D_PAD_UART3_TX_DATA__GPIO4_IO5                        = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
 	MX7D_PAD_UART3_TX_DATA__SD2_LCTL                         = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
 
-	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0),
 
 	MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
 	MX7D_PAD_UART3_RTS_B__USB_OTG2_OC                        = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
-- 
cgit v0.10.2


From f716bf11f3f96e487772d9e47d413c7b30f26b6c Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Thu, 5 May 2016 13:42:45 -0700
Subject: imx: imx7d: fix ahb clock mux 1

The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
index ad5d504..1665df9 100644
--- a/arch/arm/cpu/armv7/mx7/clock_slice.c
+++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
@@ -55,7 +55,7 @@ static struct clk_root_map root_array[] = {
 	  PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
 	},
 	{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
-	 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+	 {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
 	  PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
 	  PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
 	},
-- 
cgit v0.10.2


From 249092fa81f3dd3fee94fd05973833e30405f3c4 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Fri, 6 May 2016 11:21:50 -0700
Subject: imx: imx-common: print i.MX 7 SoC names consistently

According to the product website, the full names are i.MX 7Solo
and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be
consistent and print the short form for both supported i.MX 7 SoCs.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 5fb3ed8..4223187 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -138,7 +138,7 @@ const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
 	case MXC_CPU_MX7S:
-		return "7SOLO";	/* Single-core version of the mx7 */
+		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
 		return "7D";	/* Dual-core version of the mx7 */
 	case MXC_CPU_MX6QP:
-- 
cgit v0.10.2


From 7e0f22674ae871460706f9cc8653487bb51e0804 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 29 Apr 2016 00:44:54 +0200
Subject: SPL: Let spl_parse_image_header() return value

Allow the spl_parse_image_header() to return value. This is convenient
for controlling the SPL boot flow if the loaded image is corrupted.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 82e7f58..7259619 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -73,7 +73,7 @@ void spl_set_header_raw_uboot(void)
 	spl_image.name = "U-Boot";
 }
 
-void spl_parse_image_header(const struct image_header *header)
+int spl_parse_image_header(const struct image_header *header)
 {
 	u32 header_size = sizeof(struct image_header);
 
@@ -118,6 +118,7 @@ void spl_parse_image_header(const struct image_header *header)
 		spl_set_header_raw_uboot();
 #endif
 	}
+	return 0;
 }
 
 __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index b77dbf4..ade5496 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -48,7 +48,11 @@ int spl_load_image_ext(struct blk_desc *block_dev,
 		goto end;
 	}
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err < 0) {
+		puts("spl: ext4fs_read failed\n");
+		goto end;
+	}
 
 	err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index d761b26..338ea2f 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -57,7 +57,9 @@ int spl_load_image_fat(struct blk_desc *block_dev,
 	if (err <= 0)
 		goto end;
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err <= 0)
+		goto end;
 
 	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
 
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 8d588d1..360c754 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -23,8 +23,12 @@ static int mmc_load_legacy(struct mmc *mmc, ulong sector,
 {
 	u32 image_size_sectors;
 	unsigned long count;
+	int ret;
+
+	ret = spl_parse_image_header(header);
+	if (ret)
+		return ret;
 
-	spl_parse_image_header(header);
 	/* convert size to sectors - round up */
 	image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
 			     mmc->read_bl_len;
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 79388ff..bbd9546 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -32,7 +32,10 @@ static int spl_nand_load_element(int offset, struct image_header *header)
 	if (err)
 		return err;
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err)
+		return err;
+
 	return nand_spl_load_image(offset, spl_image.size,
 				   (void *)(unsigned long)spl_image.load_addr);
 }
@@ -77,7 +80,9 @@ int spl_nand_load_image(void)
 		/* load linux */
 		nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
 			sizeof(*header), (void *)header);
-		spl_parse_image_header(header);
+		err = spl_parse_image_header(header);
+		if (err)
+			return err;
 		if (header->ih_os == IH_OS_LINUX) {
 			/* happy - was a linux */
 			err = nand_spl_load_image(
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index 63b20d8..ae71d26 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -34,7 +34,5 @@ int spl_net_load_image(const char *device)
 		printf("Problem booting with BOOTP\n");
 		return rv;
 	}
-	spl_parse_image_header((struct image_header *)load_addr);
-
-	return 0;
+	return spl_parse_image_header((struct image_header *)load_addr);
 }
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index d0bd0b0..da2422f 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -9,6 +9,7 @@
 
 int spl_nor_load_image(void)
 {
+	int ret;
 	/*
 	 * Loading of the payload to SDRAM is done with skipping of
 	 * the mkimage header in this SPL NOR driver
@@ -28,7 +29,9 @@ int spl_nor_load_image(void)
 		if (image_get_os(header) == IH_OS_LINUX) {
 			/* happy - was a Linux */
 
-			spl_parse_image_header(header);
+			ret = spl_parse_image_header(header);
+			if (ret)
+				return ret;
 
 			memcpy((void *)spl_image.load_addr,
 			       (void *)(CONFIG_SYS_OS_BASE +
@@ -56,8 +59,10 @@ int spl_nor_load_image(void)
 	 * Load real U-Boot from its location in NOR flash to its
 	 * defined location in SDRAM
 	 */
-	spl_parse_image_header(
+	ret = spl_parse_image_header(
 			(const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+	if (ret)
+		return ret;
 
 	memcpy((void *)(unsigned long)spl_image.load_addr,
 	       (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c
index af7d82e..1a28a84 100644
--- a/common/spl/spl_onenand.c
+++ b/common/spl/spl_onenand.c
@@ -17,6 +17,7 @@
 int spl_onenand_load_image(void)
 {
 	struct image_header *header;
+	int ret;
 
 	debug("spl: onenand\n");
 
@@ -25,7 +26,9 @@ int spl_onenand_load_image(void)
 	/* Load u-boot */
 	onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
 		CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
-	spl_parse_image_header(header);
+	ret = spl_parse_image_header(header);
+	if (ret)
+		return ret;
 	onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
 		spl_image.size, (void *)spl_image.load_addr);
 
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 380d8dd..4f26ea5 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -40,8 +40,11 @@ int spl_ymodem_load_image(void)
 	if (!ret) {
 		while ((res =
 			xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
-			if (addr == 0)
-				spl_parse_image_header((struct image_header *)buf);
+			if (addr == 0) {
+				ret = spl_parse_image_header((struct image_header *)buf);
+				if (ret)
+					return ret;
+			}
 			store_addr = addr + spl_image.load_addr;
 			size += res;
 			addr += res;
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index ca56fe9..46c98a9 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -23,6 +23,8 @@
 static int spi_load_image_os(struct spi_flash *flash,
 			     struct image_header *header)
 {
+	int err;
+
 	/* Read for a header, parse or error out. */
 	spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
 		       (void *)header);
@@ -30,7 +32,9 @@ static int spi_load_image_os(struct spi_flash *flash,
 	if (image_get_magic(header) != IH_MAGIC)
 		return -1;
 
-	spl_parse_image_header(header);
+	err = spl_parse_image_header(header);
+	if (err)
+		return err;
 
 	spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
 		       spl_image.size, (void *)spl_image.load_addr);
@@ -81,7 +85,9 @@ int spl_spi_load_image(void)
 		if (err)
 			return err;
 
-		spl_parse_image_header(header);
+		err = spl_parse_image_header(header);
+		if (err)
+			return err;
 		err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
 			       spl_image.size, (void *)spl_image.load_addr);
 	}
diff --git a/include/spl.h b/include/spl.h
index de4f70a..7edfab4 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -56,7 +56,7 @@ void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(void);
 void spl_set_header_raw_uboot(void);
-void spl_parse_image_header(const struct image_header *header);
+int spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
 void __noreturn jump_to_image_linux(void *arg);
 int spl_start_uboot(void);
-- 
cgit v0.10.2


From e072751515d489b799c50b8c254367d4373403ee Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 29 Apr 2016 00:44:55 +0200
Subject: SPL: Add CONFIG_SPL_ABORT_ON_RAW_IMAGE

When defined, SPL will proceed to another boot method
if the image it has loaded does not have a signature.
This is useful if the subsequent boot methods are much
more complex.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/README b/README
index 88ff837..d881da2 100644
--- a/README
+++ b/README
@@ -3487,6 +3487,10 @@ FIT uImage format:
 		consider that a completely unreadable NAND block is bad,
 		and thus should be skipped silently.
 
+		CONFIG_SPL_ABORT_ON_RAW_IMAGE
+		When defined, SPL will proceed to another boot method
+		if the image it has loaded does not have a signature.
+
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7259619..93f9bd1 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -111,6 +111,9 @@ int spl_parse_image_header(const struct image_header *header)
 		 * is bad, and thus should be skipped silently.
 		 */
 		panic("** no mkimage signature but raw image not supported");
+#elif defined(CONFIG_SPL_ABORT_ON_RAW_IMAGE)
+		/* Signature not found, proceed to other boot methods. */
+		return -EINVAL;
 #else
 		/* Signature not found - assume u-boot.bin */
 		debug("mkimage signature not found - ih_magic = %x\n",
-- 
cgit v0.10.2


From 291000894ed4d6257830baba547764b86e335b5c Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 29 Apr 2016 00:44:56 +0200
Subject: ARM: mx6: Enable MMC and SATA extfs boot support

Enable support for booting U-Boot image from ext filesystem when either
SD/MMC or SATA support is compiled into the SPL. This will allow easy
transition from loading U-Boot image from ad-hoc offset on the card to
loading U-Boot image from the filesystem. VFAT support is intently not
enabled. The boot order is tweaked so that raw is tested first and if
the raw has no signature, FS boot is attempted.

To install just the SPL on i.MX6 board, perform the following operation
 $ dd if=SPL of=/dev/sdX seek=2 bs=512
To install the U-Boot image, copy u-boot.img to the first partition of
the SD/MMC/SATA drive. The partition must be formated to extfs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 68d3fd7..9bd9f6e 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -48,12 +48,16 @@
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_MONITOR_LEN  (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
 #endif
 
 /* SATA support */
 #if defined(CONFIG_SPL_SATA_SUPPORT)
 #define CONFIG_SPL_SATA_BOOT_DEVICE		0
 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
 #endif
 
 /* Define the payload for FAT/EXT support */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index e938fbc..2382951 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -75,7 +75,6 @@
 
 /* SPL */
 #define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #include "imx6_spl.h"			/* common IMX6 SPL configuration */
 
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index badb955..77ced71 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -16,7 +16,6 @@
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
 
 /* common IMX6 SPL configuration */
 #include "imx6_spl.h"
-- 
cgit v0.10.2


From 037734393ef6181e87d85be15468af4baee70b42 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Thu, 14 Apr 2016 21:45:06 +0800
Subject: dm: gpio: pca953x: introduce driver model support for pca953x

Introduce a new driver that supports driver model for pca953x.
The pca953x chips are used as I2C I/O expanders.
This driver is designed to support the following chips:
"
4 bits: pca9536, pca9537
8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
        pca9556, pca9557, pca9574, tca6408, xra1202
16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
         tca6416
24 bits: tca6424
40 bits: pca9505, pca9698
"
But for now this driver only supports max 24 bits and pca953x compatible
chips. pca957x compatible chips are not supported now.
These can be addressed when we need to add such support for the different
chips.
This driver has been tested on i.MX6 SoloX Sabreauto board with max7310
i2c expander using gpio command as following:

=>gpio status -a
Bank gpio@30_:
gpio@30_0: input: 1 [ ]

=> dm tree:
 i2c         [   ]    |   |   `-- i2c@021a8000
 gpio        [   ]    |   |       |-- gpio@30
 gpio        [   ]    |   |       `-- gpio@32

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Andrea Scian <andrea.scian@dave.eu>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <michal.simek@xilinx.com> #on ZynqMP zcu102

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2b4624d..e6337c2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -143,4 +143,26 @@ config ZYNQ_GPIO
 	help
 	  Supports GPIO access on Zynq SoC.
 
+config DM_PCA953X
+	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
+	depends on DM_GPIO
+	help
+	  Say yes here to provide access to several register-oriented
+	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
+	  models include:
+
+	  4 bits:	pca9536, pca9537
+
+	  8 bits:	max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+			pca9556, pca9557, pca9574, tca6408, xra1202
+
+	  16 bits:	max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+			tca6416
+
+	  24 bits:	tca6424
+
+	  40 bits:	pca9505, pca9698
+
+	  Now, max 24 bits chips and PCA953X compatible chips are
+	  supported
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4f071c4..4b1f6b9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_AXP_GPIO)		+= axp_gpio.o
 endif
 obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
 
+obj-$(CONFIG_DM_PCA953X)	+= pca953x_gpio.o
+
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
new file mode 100644
index 0000000..987d10e
--- /dev/null
+++ b/drivers/gpio/pca953x_gpio.c
@@ -0,0 +1,351 @@
+/*
+ * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
+ *
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+/*
+ * Note:
+ * The driver's compatible table is borrowed from Linux Kernel,
+ * but now max supported gpio pins is 24 and only PCA953X_TYPE
+ * is supported. PCA957X_TYPE is not supported now.
+ * Also the Polarity Inversion feature is not supported now.
+ *
+ * TODO:
+ * 1. Support PCA957X_TYPE
+ * 2. Support max 40 gpio pins
+ * 3. Support Plolarity Inversion
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define PCA953X_INPUT           0
+#define PCA953X_OUTPUT          1
+#define PCA953X_INVERT          2
+#define PCA953X_DIRECTION       3
+
+#define PCA_GPIO_MASK           0x00FF
+#define PCA_INT                 0x0100
+#define PCA953X_TYPE            0x1000
+#define PCA957X_TYPE            0x2000
+#define PCA_TYPE_MASK           0xF000
+#define PCA_CHIP_TYPE(x)        ((x) & PCA_TYPE_MASK)
+
+enum {
+	PCA953X_DIRECTION_IN,
+	PCA953X_DIRECTION_OUT,
+};
+
+#define MAX_BANK 3
+#define BANK_SZ 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * struct pca953x_info - Data for pca953x
+ *
+ * @dev: udevice structure for the device
+ * @addr: i2c slave address
+ * @invert: Polarity inversion or not
+ * @gpio_count: the number of gpio pins that the device supports
+ * @chip_type: indicate the chip type,PCA953X or PCA957X
+ * @bank_count: the number of banks that the device supports
+ * @reg_output: array to hold the value of output registers
+ * @reg_direction: array to hold the value of direction registers
+ */
+struct pca953x_info {
+	struct udevice *dev;
+	int addr;
+	int invert;
+	int gpio_count;
+	int chip_type;
+	int bank_count;
+	u8 reg_output[MAX_BANK];
+	u8 reg_direction[MAX_BANK];
+};
+
+static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
+				int offset)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
+	int off = offset / BANK_SZ;
+	int ret = 0;
+
+	ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
+	if (ret) {
+		dev_err(dev, "%s error\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
+			       int offset)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
+	int off = offset / BANK_SZ;
+	int ret;
+	u8 byte;
+
+	ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
+	if (ret) {
+		dev_err(dev, "%s error\n", __func__);
+		return ret;
+	}
+
+	*val = byte;
+
+	return 0;
+}
+
+static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int ret = 0;
+
+	if (info->gpio_count <= 8) {
+		ret = dm_i2c_read(dev, reg, val, 1);
+	} else if (info->gpio_count <= 16) {
+		ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+	} else {
+		dev_err(dev, "Unsupported now\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int pca953x_is_output(struct udevice *dev, int offset)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+
+	int bank = offset / BANK_SZ;
+	int off = offset % BANK_SZ;
+
+	/*0: output; 1: input */
+	return !(info->reg_direction[bank] & (1 << off));
+}
+
+static int pca953x_get_value(struct udevice *dev, unsigned offset)
+{
+	int ret;
+	u8 val = 0;
+
+	ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
+	if (ret)
+		return ret;
+
+	return (val >> offset) & 0x1;
+}
+
+static int pca953x_set_value(struct udevice *dev, unsigned offset,
+			     int value)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank = offset / BANK_SZ;
+	int off = offset % BANK_SZ;
+	u8 val;
+	int ret;
+
+	if (value)
+		val = info->reg_output[bank] | (1 << off);
+	else
+		val = info->reg_output[bank] & ~(1 << off);
+
+	ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
+	if (ret)
+		return ret;
+
+	info->reg_output[bank] = val;
+
+	return 0;
+}
+
+static int pca953x_set_direction(struct udevice *dev, unsigned offset, int dir)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	int bank = offset / BANK_SZ;
+	int off = offset % BANK_SZ;
+	u8 val;
+	int ret;
+
+	if (dir == PCA953X_DIRECTION_IN)
+		val = info->reg_direction[bank] | (1 << off);
+	else
+		val = info->reg_direction[bank] & ~(1 << off);
+
+	ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
+	if (ret)
+		return ret;
+
+	info->reg_direction[bank] = val;
+
+	return 0;
+}
+
+static int pca953x_direction_input(struct udevice *dev, unsigned offset)
+{
+	return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
+}
+
+static int pca953x_direction_output(struct udevice *dev, unsigned offset,
+				    int value)
+{
+	/* Configure output value. */
+	pca953x_set_value(dev, offset, value);
+
+	/* Configure direction as output. */
+	pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
+
+	return 0;
+}
+
+static int pca953x_get_function(struct udevice *dev, unsigned offset)
+{
+	if (pca953x_is_output(dev, offset))
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
+			 struct fdtdec_phandle_args *args)
+{
+	desc->offset = args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops pca953x_ops = {
+	.direction_input	= pca953x_direction_input,
+	.direction_output	= pca953x_direction_output,
+	.get_value		= pca953x_get_value,
+	.set_value		= pca953x_set_value,
+	.get_function		= pca953x_get_function,
+	.xlate			= pca953x_xlate,
+};
+
+static int pca953x_probe(struct udevice *dev)
+{
+	struct pca953x_info *info = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+	char name[32], *str;
+	int addr;
+	ulong driver_data;
+	int ret;
+
+	if (!info) {
+		dev_err(dev, "platdata not ready\n");
+		return -ENOMEM;
+	}
+
+	if (!chip) {
+		dev_err(dev, "i2c not ready\n");
+		return -ENODEV;
+	}
+
+	addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+	if (addr == 0)
+		return -ENODEV;
+
+	info->addr = addr;
+
+	driver_data = dev_get_driver_data(dev);
+
+	info->gpio_count = driver_data & PCA_GPIO_MASK;
+	if (info->gpio_count > MAX_BANK * BANK_SZ) {
+		dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
+		return -EINVAL;
+	}
+
+	info->chip_type = PCA_CHIP_TYPE(driver_data);
+	if (info->chip_type != PCA953X_TYPE) {
+		dev_err(dev, "Only support PCA953X chip type now.\n");
+		return -EINVAL;
+	}
+
+	info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
+
+	ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
+	if (ret) {
+		dev_err(dev, "Error reading output register\n");
+		return ret;
+	}
+
+	ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
+	if (ret) {
+		dev_err(dev, "Error reading direction register\n");
+		return ret;
+	}
+
+	snprintf(name, sizeof(name), "gpio@%x_", info->addr);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = info->gpio_count;
+
+	dev_dbg(dev, "%s is ready\n", str);
+
+	return 0;
+}
+
+#define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
+#define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
+
+static const struct udevice_id pca953x_ids[] = {
+	{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
+	{ .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
+	{ .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
+	{ .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
+	{ .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
+	{ .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
+	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
+	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+
+	{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
+	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
+
+	{ .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
+	{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
+	{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
+
+	{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
+
+	{ .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
+	{ }
+};
+
+U_BOOT_DRIVER(pca953x) = {
+	.name		= "pca953x",
+	.id		= UCLASS_GPIO,
+	.ops		= &pca953x_ops,
+	.probe		= pca953x_probe,
+	.platdata_auto_alloc_size = sizeof(struct pca953x_info),
+	.of_match	= pca953x_ids,
+};
-- 
cgit v0.10.2


From 5044c9cc6c4dffb2959769a785663f46cb418461 Mon Sep 17 00:00:00 2001
From: "angelo@sysam.it" <angelo@sysam.it>
Date: Wed, 27 Apr 2016 21:50:44 +0200
Subject: m68k: add malloc memory for early malloc

To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used.
So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and
call to board_init_f_mem() is added for all cpu's.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index 23024f9..13c036f 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -372,14 +372,29 @@ _start:
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for
-	   the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	bsr     board_init_f_init_reserve
 
 	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	clr.l   %sp@-
 	bsr board_init_f		/* run low-level board init code (from flash) */
 
 	/* board_init_f() does not return */
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 1702f98..3aa4dd6 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -134,17 +134,34 @@ _start:
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the
-	   first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 4af691f..a048884 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -192,16 +192,34 @@ _after_flashbar_copy:
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5		/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr (%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr (%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index 80dc239..b09eed8 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -142,7 +142,7 @@ int cpu_init_r(void)
 	return 0;
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 }
 
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index 097958a..ca8bb32 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -126,21 +126,32 @@ _start:
 	move.l	%d0, (%a1)
 	move.l	%d0, (%a2)
 
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
 	/*
-	 * set stackpointer to internal sram end - 80
-	 * (global data struct size + some bytes)
-	 * get some stackspace for the first c-code,
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
 	 */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l   %sp@-
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
 
-	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	bsr     board_init_f_init_reserve
 
 	/* run low-level CPU init code (from flash) */
 	bsr cpu_init_f
 
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	bsr board_init_f
 
 	/* board_init_f() does not return */
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 131ad6e..f25bc54 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -148,17 +148,34 @@ _start:
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the
-	   first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index f50f147..ba38678 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -657,17 +657,34 @@ _start:
 	movec	%d0, %RAMBAR1
 #endif
 
-	/* set stackpointer to end of internal ram to get some stackspace for
-	   the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
+
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	move.l	#board_init_f_alloc_reserve, %a1
+	jsr	(%a1)
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	move.l	#board_init_f_init_reserve, %a1
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
 	move.l #cpu_init_f, %a1
 	jsr (%a1)
 	/* run low-level board init code (from flash) */
+	clr.l   %sp@-
 	move.l #board_init_f, %a1
 	jsr (%a1)
 
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index 75de22d..9a87a0d 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -141,14 +141,29 @@ _start:
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
-	/* set stackpointer to end of internal ram to get some stackspace for the
-	   first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	/* put relocation table address to a5 */
+	move.l #__got_start, %a5
 
-	move.l #__got_start, %a5	/* put relocation table address to a5 */
+	/* setup stack initially on top of internal static ram  */
+	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+	/*
+	 * if configured, malloc_f arena will be reserved first,
+	 * then (and always) gd struct space will be reserved
+	 */
+	move.l	%sp, -(%sp)
+	bsr	board_init_f_alloc_reserve
+
+	/* update stack and frame-pointers */
+	move.l  %d0, %sp
+	move.l  %sp, %fp
+
+	/* initialize reserved area */
+	move.l  %d0, -(%sp)
+	bsr     board_init_f_init_reserve
 
 	jbsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	clr.l   %sp@-
 	jbsr board_init_f		/* run low-level board init code (from flash) */
 
 	/* board_init_f() does not return */
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index e1458ac..9c4d3fb 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -7,8 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
 #define CONFIG_NEEDS_MANUAL_RELOC
 
 #define CONFIG_LMB
-- 
cgit v0.10.2


From e27802af54c2ff2d4d58e4bc217644b75c04ac4c Mon Sep 17 00:00:00 2001
From: "angelo@sysam.it" <angelo@sysam.it>
Date: Wed, 27 Apr 2016 21:51:13 +0200
Subject: m68k: add DM model serial driver

Boards can now use DM serial driver, or still legacy mcf uart
driver version.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 407354f..059cb0f 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
  *
+ * Modified to add device model (DM) support
+ * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
@@ -11,9 +14,10 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
 #include <serial.h>
 #include <linux/compiler.h>
-
 #include <asm/immap.h>
 #include <asm/uart.h>
 
@@ -21,91 +25,110 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void uart_port_conf(int port);
 
-static int mcf_serial_init(void)
+static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
 {
-	volatile uart_t *uart;
 	u32 counter;
 
-	uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-
-	uart_port_conf(CONFIG_SYS_UART_PORT);
+	uart_port_conf(port_idx);
 
 	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
-	uart->ucr = UART_UCR_RESET_RX;
-	uart->ucr = UART_UCR_RESET_TX;
-	uart->ucr = UART_UCR_RESET_ERROR;
-	uart->ucr = UART_UCR_RESET_MR;
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+	writeb(UART_UCR_RESET_MR, &uart->ucr);
 	__asm__("nop");
 
-	uart->uimr = 0;
+	writeb(0, &uart->uimr);
 
 	/* write to CSR: RX/TX baud rate from timers */
-	uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
+	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
 
-	uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
-	uart->umr = UART_UMR_SB_STOP_BITS_1;
+	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
 
 	/* Setting up BaudRate */
-	counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
-	counter = counter / gd->baudrate;
+	counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+	counter = counter / baudrate;
 
 	/* write to CTUR: divide counter upper byte */
-	uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
+	writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
 	/* write to CTLR: divide counter lower byte */
-	uart->ubg2 = (u8) (counter & 0x00ff);
+	writeb((u8)(counter & 0x00ff), &uart->ubg2);
 
-	uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
 
 	return (0);
 }
 
+static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
+{
+	u32 counter;
+
+	/* Setting up BaudRate */
+	counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+	counter = counter / baudrate;
+
+	/* write to CTUR: divide counter upper byte */
+	writeb(((counter & 0xff00) >> 8), &uart->ubg1);
+	/* write to CTLR: divide counter lower byte */
+	writeb((counter & 0x00ff), &uart->ubg2);
+
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+}
+
+#ifndef CONFIG_DM_SERIAL
+
+static int mcf_serial_init(void)
+{
+	uart_t *uart_base;
+	int port_idx;
+
+	uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
+	port_idx = CONFIG_SYS_UART_PORT;
+
+	return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
+}
+
 static void mcf_serial_putc(const char c)
 {
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
 	if (c == '\n')
 		serial_putc('\r');
 
 	/* Wait for last character to go. */
-	while (!(uart->usr & UART_USR_TXRDY)) ;
+	while (!(readb(&uart->usr) & UART_USR_TXRDY))
+		;
 
-	uart->utb = c;
+	writeb(c, &uart->utb);
 }
 
 static int mcf_serial_getc(void)
 {
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
 	/* Wait for a character to arrive. */
-	while (!(uart->usr & UART_USR_RXRDY)) ;
-	return uart->urb;
-}
-
-static int mcf_serial_tstc(void)
-{
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+	while (!(readb(&uart->usr) & UART_USR_RXRDY))
+		;
 
-	return (uart->usr & UART_USR_RXRDY);
+	return readb(&uart->urb);
 }
 
 static void mcf_serial_setbrg(void)
 {
-	volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-	u32 counter;
-
-	/* Setting up BaudRate */
-	counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
-	counter = counter / gd->baudrate;
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
-	/* write to CTUR: divide counter upper byte */
-	uart->ubg1 = ((counter & 0xff00) >> 8);
-	/* write to CTLR: divide counter lower byte */
-	uart->ubg2 = (counter & 0x00ff);
+	mcf_serial_setbrg_common(uart, gd->baudrate);
+}
 
-	uart->ucr = UART_UCR_RESET_RX;
-	uart->ucr = UART_UCR_RESET_TX;
+static int mcf_serial_tstc(void)
+{
+	uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
 
-	uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
+	return readb(&uart->usr) & UART_USR_RXRDY;
 }
 
 static struct serial_device mcf_serial_drv = {
@@ -128,3 +151,80 @@ __weak struct serial_device *default_serial_console(void)
 {
 	return &mcf_serial_drv;
 }
+
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+static int coldfire_serial_probe(struct udevice *dev)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+
+	return mcf_serial_init_common((uart_t *)plat->base,
+						plat->port, plat->baudrate);
+}
+
+static int coldfire_serial_putc(struct udevice *dev, const char ch)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)plat->base;
+
+	/* Wait for last character to go. */
+	if (!(readb(&uart->usr) & UART_USR_TXRDY))
+		return -EAGAIN;
+
+	writeb(ch, &uart->utb);
+
+	return 0;
+}
+
+static int coldfire_serial_getc(struct udevice *dev)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)(plat->base);
+
+	/* Wait for a character to arrive. */
+	if (!(readb(&uart->usr) & UART_USR_RXRDY))
+		return -EAGAIN;
+
+	return readb(&uart->urb);
+}
+
+int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)(plat->base);
+
+	mcf_serial_setbrg_common(uart, baudrate);
+
+	return 0;
+}
+
+static int coldfire_serial_pending(struct udevice *dev, bool input)
+{
+	struct coldfire_serial_platdata *plat = dev->platdata;
+	uart_t *uart = (uart_t *)(plat->base);
+
+	if (input)
+		return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
+	else
+		return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
+
+	return 0;
+}
+
+static const struct dm_serial_ops coldfire_serial_ops = {
+	.putc = coldfire_serial_putc,
+	.pending = coldfire_serial_pending,
+	.getc = coldfire_serial_getc,
+	.setbrg = coldfire_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_coldfire) = {
+	.name = "serial_coldfire",
+	.id = UCLASS_SERIAL,
+	.probe = coldfire_serial_probe,
+	.ops = &coldfire_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+#endif
diff --git a/include/dm/platform_data/serial_coldfire.h b/include/dm/platform_data/serial_coldfire.h
new file mode 100644
index 0000000..5d86456
--- /dev/null
+++ b/include/dm/platform_data/serial_coldfire.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015  Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __serial_coldfire_h
+#define __serial_coldfire_h
+
+/*
+ * struct coldfire_serial_platdata - information about a coldfire port
+ *
+ * @base:               Uart port base register address
+ * @port:               Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre:          Uart port baudrate
+ */
+struct coldfire_serial_platdata {
+	unsigned long base;
+	int port;
+	int baudrate;
+};
+
+#endif /* __serial_coldfire_h */
-- 
cgit v0.10.2


From f79f1e0c0ea06de3af79094bc80be6e218b5f6ef Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 11 Apr 2016 10:48:44 -0600
Subject: buildman: allow more incremental building

One use-case for buildman is to continually run it interactively after
each small step in a large refactoring operation. This gives more
immediate feedback than making a number of commits and then going back and
testing them. For this to work well, buildman needs to be extremely fast.
At present, a couple issues prevent it being as fast as it could be:

1) Each time buildman runs "make %_defconfig", it runs "make mrproper"
first. This throws away all previous build results, requiring a
from-scratch build. Optionally avoiding this would speed up the build, at
the cost of potentially causing or missing some build issues.

2) A build tree is created per thread rather than per board. When a thread
switches between building different boards, this often causes many files
to be rebuilt due to changing config options. Using a separate build tree
for each board would avoid this. This does put more strain on the system's
disk cache, but it is worth it on my system at least.

This commit adds two command-line options to implement the changes
described above; -I ("--incremental") turns of "make mrproper" and -P
("--per-board-out-dir") creats a build directory per board rather than per
thread.

Tested:

    ./tools/buildman/buildman.py tegra
    ./tools/buildman/buildman.py -I -P tegra
    ./tools/buildman/buildman.py -b tegra_dev tegra
    ./tools/buildman/buildman.py -b tegra_dev -I -P tegra

... each once after deleting the buildman result/work directory, and once
"incrementally" after a previous identical invocation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org> # v1
Tested-by: Simon Glass <sjg@chromium.org> # v1
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/buildman/README b/tools/buildman/README
index 4705d26..26755c5 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -898,6 +898,48 @@ when using the -b flag. For example:
 will build commits in us-buildman that are not in upstream/master.
 
 
+Building Faster
+===============
+
+By default, buildman executes 'make mrproper' prior to building the first
+commit for each board. This causes everything to be built from scratch. If you
+trust the build system's incremental build capabilities, you can pass the -I
+flag to skip the 'make mproper' invocation, which will reduce the amount of
+work 'make' does, and hence speed up the build. This flag will speed up any
+buildman invocation, since it reduces the amount of work done on any build.
+
+One possible application of buildman is as part of a continual edit, build,
+edit, build, ... cycle; repeatedly applying buildman to the same change or
+series of changes while making small incremental modifications to the source
+each time. This provides quick feedback regarding the correctness of recent
+modifications. In this scenario, buildman's default choice of build directory
+causes more build work to be performed than strictly necessary.
+
+By default, each buildman thread uses a single directory for all builds. When a
+thread builds multiple boards, the configuration built in this directory will
+cycle through various different configurations, one per board built by the
+thread. Variations in the configuration will force a rebuild of affected source
+files when a thread switches between boards. Ideally, such buildman-induced
+rebuilds would not happen, thus allowing the build to operate as efficiently as
+the build system and source changes allow. buildman's -P flag may be used to
+enable this; -P causes each board to be built in a separate (board-specific)
+directory, thus avoiding any buildman-induced configuration changes in any
+build directory.
+
+U-Boot's build system embeds information such as a build timestamp into the
+final binary. This information varies each time U-Boot is built. This causes
+various files to be rebuilt even if no source changes are made, which in turn
+requires that the final U-Boot binary be re-linked. This unnecessary work can
+be avoided by turning off the timestamp feature. This can be achieved by
+setting the SOURCE_DATE_EPOCH environment variable to 0.
+
+Combining all of these options together yields the command-line shown below.
+This will provide the quickest possible feedback regarding the current content
+of the source tree, thus allowing rapid tested evolution of the code.
+
+    SOURCE_DATE_EPOCH=0 ./tools/buildman/buildman -I -P tegra
+
+
 Other options
 =============
 
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 141bf64..8ec3551 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -205,7 +205,8 @@ class Builder:
 
     def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
                  gnu_make='make', checkout=True, show_unknown=True, step=1,
-                 no_subdirs=False, full_path=False, verbose_build=False):
+                 no_subdirs=False, full_path=False, verbose_build=False,
+                 incremental=False, per_board_out_dir=False):
         """Create a new Builder object
 
         Args:
@@ -224,6 +225,10 @@ class Builder:
             full_path: Return the full path in CROSS_COMPILE and don't set
                 PATH
             verbose_build: Run build with V=1 and don't use 'make -s'
+            incremental: Always perform incremental builds; don't run make
+                mrproper when configuring
+            per_board_out_dir: Build in a separate persistent directory per
+                board rather than a thread-specific directory
         """
         self.toolchains = toolchains
         self.base_dir = base_dir
@@ -263,7 +268,8 @@ class Builder:
         self.queue = Queue.Queue()
         self.out_queue = Queue.Queue()
         for i in range(self.num_threads):
-            t = builderthread.BuilderThread(self, i)
+            t = builderthread.BuilderThread(self, i, incremental,
+                    per_board_out_dir)
             t.setDaemon(True)
             t.start()
             self.threads.append(t)
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index cf25bb8..c512d3b 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -80,11 +80,13 @@ class BuilderThread(threading.Thread):
         thread_num: Our thread number (0-n-1), used to decide on a
                 temporary directory
     """
-    def __init__(self, builder, thread_num):
+    def __init__(self, builder, thread_num, incremental, per_board_out_dir):
         """Set up a new builder thread"""
         threading.Thread.__init__(self)
         self.builder = builder
         self.thread_num = thread_num
+        self.incremental = incremental
+        self.per_board_out_dir = per_board_out_dir
 
     def Make(self, commit, brd, stage, cwd, *args, **kwargs):
         """Run 'make' on a particular commit and board.
@@ -136,7 +138,11 @@ class BuilderThread(threading.Thread):
         if self.builder.in_tree:
             out_dir = work_dir
         else:
-            out_dir = os.path.join(work_dir, 'build')
+            if self.per_board_out_dir:
+                out_rel_dir = os.path.join('..', brd.target)
+            else:
+                out_rel_dir = 'build'
+            out_dir = os.path.join(work_dir, out_rel_dir)
 
         # Check if the job was already completed last time
         done_file = self.builder.GetDoneFile(commit_upto, brd.target)
@@ -197,12 +203,12 @@ class BuilderThread(threading.Thread):
                         #
                         # Symlinks can confuse U-Boot's Makefile since
                         # we may use '..' in our path, so remove them.
-                        work_dir = os.path.realpath(work_dir)
-                        args.append('O=%s/build' % work_dir)
+                        out_dir = os.path.realpath(out_dir)
+                        args.append('O=%s' % out_dir)
                         cwd = None
                         src_dir = os.getcwd()
                     else:
-                        args.append('O=build')
+                        args.append('O=%s' % out_rel_dir)
                 if self.builder.verbose_build:
                     args.append('V=1')
                 else:
@@ -215,9 +221,11 @@ class BuilderThread(threading.Thread):
 
                 # If we need to reconfigure, do that now
                 if do_config:
-                    result = self.Make(commit, brd, 'mrproper', cwd,
-                            'mrproper', *args, env=env)
-                    config_out = result.combined
+                    config_out = ''
+                    if not self.incremental:
+                        result = self.Make(commit, brd, 'mrproper', cwd,
+                                'mrproper', *args, env=env)
+                        config_out += result.combined
                     result = self.Make(commit, brd, 'config', cwd,
                             *(args + config_args), env=env)
                     config_out += result.combined
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 8341ab1..3e3bd63 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -49,6 +49,8 @@ def ParseArgs():
     parser.add_option('-i', '--in-tree', dest='in_tree',
           action='store_true', default=False,
           help='Build in the source tree instead of a separate directory')
+    parser.add_option('-I', '--incremental', action='store_true',
+          default=False, help='Do not run make mrproper (when reconfiguring)')
     parser.add_option('-j', '--jobs', dest='jobs', type='int',
           default=None, help='Number of jobs to run at once (passed to make)')
     parser.add_option('-k', '--keep-outputs', action='store_true',
@@ -70,6 +72,8 @@ def ParseArgs():
           default=False, help='Do a rough build, with limited warning resolution')
     parser.add_option('-p', '--full-path', action='store_true',
           default=False, help="Use full toolchain path in CROSS_COMPILE")
+    parser.add_option('-P', '--per-board-out-dir', action='store_true',
+          default=False, help="Use an O= (output) directory per board rather than per thread")
     parser.add_option('-s', '--summary', action='store_true',
           default=False, help='Show a build summary')
     parser.add_option('-S', '--show-sizes', action='store_true',
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index c2c54bf..aeb128a 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -250,7 +250,9 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
             options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
             show_unknown=options.show_unknown, step=options.step,
             no_subdirs=options.no_subdirs, full_path=options.full_path,
-            verbose_build=options.verbose_build)
+            verbose_build=options.verbose_build,
+            incremental=options.incremental,
+            per_board_out_dir=options.per_board_out_dir,)
     builder.force_config_on_failure = not options.quick
     if make_func:
         builder.do_make = make_func
-- 
cgit v0.10.2


From 9fdfadf8fc83b173b3ba55aa82739ca92d8a273d Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 19 Apr 2016 16:19:29 -0600
Subject: dm: core: allow drivers to refuse to bind

In some cases, drivers may not want to bind to a device. Allow bind() to
return -ENODEV in this case, and don't treat this as an error. This can
be useful in situations where some information source other than the DT
node's main status property indicates whether the device should be
enabled, for example other DT properties might indicate this, or the
driver might query non-DT sources such as system fuses or a version number
register.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index c4fc216..a72db13 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -171,6 +171,10 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 
 		dm_dbg("   - found match at '%s'\n", entry->name);
 		ret = device_bind(parent, entry, name, NULL, offset, &dev);
+		if (ret == -ENODEV) {
+			dm_dbg("Driver '%s' refuses to bind\n", entry->name);
+			continue;
+		}
 		if (ret) {
 			dm_warn("Error binding driver '%s': %d\n", entry->name,
 				ret);
-- 
cgit v0.10.2


From 54693cbdca5724b8946d0522a736e8a49fa14c0c Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 19 Apr 2016 16:19:30 -0600
Subject: video: tegra: refuse to bind to disabled dcs

This prevents the following boot-time message on any board where only the
first DC is in use, yet the DC's DT node is enabled:

stdio_add_devices: Video device failed (ret=-22)

(This happens on at least Harmony, Ventana, and likely any other Tegra20
board with display enabled other than Seaboard).

The Tegra DC's DT node represents a display controller. It may itself
drive an integrated RGB display output, or be used by some other display
controller such as HDMI. For this reason the DC node itself is not
enabled/disabled in DT; the DC itself is considered a shared resource, not
the final (board-specific) display output. The node should instantiate a
display output driver only if the rgb subnode is enabled. Other output
drivers are free to use the DC if they are enabled and their DT node
references the DC's DT node. Adapt the Tegra display drivers' bind()
routine to only bind to the DC's DT node if the RGB subnode is enabled.

Now that the display driver does the right thing, remove the workaround
for this issue from Seaboard's DT file.

Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index eada590..5893d2a 100644
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -40,10 +40,6 @@
 				nvidia,panel = <&lcd_panel>;
 			};
 		};
-
-		dc@54240000 {
-			status = "disabled";
-		};
 	};
 
 	/* This is not used in U-Boot, but is expected to be in kernel .dts */
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 7fd10e6..c01809e 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -620,6 +620,13 @@ static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 static int tegra_lcd_bind(struct udevice *dev)
 {
 	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+	int rgb;
+
+	rgb = fdt_subnode_offset(blob, node, "rgb");
+	if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
+		return -ENODEV;
 
 	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 		(1 << LCD_MAX_LOG2_BPP) / 8;
-- 
cgit v0.10.2


From 35732098db382b48e3fb4f3595fc108f69ea4457 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 28 Apr 2016 16:04:15 -0600
Subject: fdt: fix dev_get_addr_name node offset

Use the device's own DT offset, not the device's parent's.

Fixes: 43c4d44e3330 ("fdt: implement dev_get_addr_name()")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 1322991..2b12ce7 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -657,8 +657,8 @@ fdt_addr_t dev_get_addr_name(struct udevice *dev, const char *name)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 	int index;
 
-	index = fdt_find_string(gd->fdt_blob, dev->parent->of_offset,
-				"reg-names", name);
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reg-names",
+				name);
 	if (index < 0)
 		return index;
 
-- 
cgit v0.10.2


From b6d54d527325f27c460777b882e23d21a935765a Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 10:02:20 +0800
Subject: dm: spi: soft_spi bug fix

When doing xfer, should use device->parent, but not device
When doing bit xfer, should use "!!(tmpdout & 0x80)", but not
"(tmpdout & 0x80)"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index aa4abcc..8cdb520 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -34,7 +34,8 @@ struct soft_spi_priv {
 
 static int soft_spi_scl(struct udevice *dev, int bit)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->sclk, bit);
 
@@ -43,7 +44,8 @@ static int soft_spi_scl(struct udevice *dev, int bit)
 
 static int soft_spi_sda(struct udevice *dev, int bit)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->mosi, bit);
 
@@ -52,7 +54,8 @@ static int soft_spi_sda(struct udevice *dev, int bit)
 
 static int soft_spi_cs_activate(struct udevice *dev)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->cs, 0);
 	dm_gpio_set_value(&plat->sclk, 0);
@@ -63,7 +66,8 @@ static int soft_spi_cs_activate(struct udevice *dev)
 
 static int soft_spi_cs_deactivate(struct udevice *dev)
 {
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 
 	dm_gpio_set_value(&plat->cs, 0);
 
@@ -100,8 +104,9 @@ static int soft_spi_release_bus(struct udevice *dev)
 static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 			 const void *dout, void *din, unsigned long flags)
 {
-	struct soft_spi_priv *priv = dev_get_priv(dev);
-	struct soft_spi_platdata *plat = dev->platdata;
+	struct udevice *bus = dev_get_parent(dev);
+	struct soft_spi_priv *priv = dev_get_priv(bus);
+	struct soft_spi_platdata *plat = dev_get_platdata(bus);
 	uchar		tmpdin  = 0;
 	uchar		tmpdout = 0;
 	const u8	*txd = dout;
@@ -134,7 +139,7 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 		if (!cpha)
 			soft_spi_scl(dev, 0);
-		soft_spi_sda(dev, tmpdout & 0x80);
+		soft_spi_sda(dev, !!(tmpdout & 0x80));
 		udelay(plat->spi_delay_us);
 		if (cpha)
 			soft_spi_scl(dev, 0);
-- 
cgit v0.10.2


From 102412c415b5e51b01ed5797c965d0feaa065439 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 10:02:21 +0800
Subject: dm: spi: soft_spi: switch to use linux compatible string

1. Support compatible string "spi-gpio" which is used by Linux
   Linux use different bindings, so use UBOOT_COMPAT and
   LINUX_COMPAT to differentiate them.
2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle
   no rx or no tx case.
3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 16948c9..ad3527e 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -42,11 +42,11 @@
 	};
 
 	soft-spi {
-		compatible = "u-boot,soft-spi";
-		cs-gpio = <&gpy4 3 0>;
-		sclk-gpio = <&gpy3 1 0>;
-		mosi-gpio = <&gpy3 3 0>;
-		miso-gpio = <&gpy3 0 0>;
+		compatible = "spi-gpio";
+		cs-gpios = <&gpy4 3 0>;
+		gpio-sck = <&gpy3 1 0>;
+		gpio-mosi = <&gpy3 3 0>;
+		gpio-miso = <&gpy3 0 0>;
 		spi-delay-us = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index 8cdb520..d23dc81 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -26,8 +26,12 @@ struct soft_spi_platdata {
 	struct gpio_desc mosi;
 	struct gpio_desc miso;
 	int spi_delay_us;
+	int flags;
 };
 
+#define SPI_MASTER_NO_RX        BIT(0)
+#define SPI_MASTER_NO_TX        BIT(1)
+
 struct soft_spi_priv {
 	unsigned int mode;
 };
@@ -139,14 +143,16 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 		if (!cpha)
 			soft_spi_scl(dev, 0);
-		soft_spi_sda(dev, !!(tmpdout & 0x80));
+		if ((plat->flags & SPI_MASTER_NO_TX) == 0)
+			soft_spi_sda(dev, !!(tmpdout & 0x80));
 		udelay(plat->spi_delay_us);
 		if (cpha)
 			soft_spi_scl(dev, 0);
 		else
 			soft_spi_scl(dev, 1);
 		tmpdin	<<= 1;
-		tmpdin	|= dm_gpio_get_value(&plat->miso);
+		if ((plat->flags & SPI_MASTER_NO_RX) == 0)
+			tmpdin	|= dm_gpio_get_value(&plat->miso);
 		tmpdout	<<= 1;
 		udelay(plat->spi_delay_us);
 		if (cpha)
@@ -208,24 +214,36 @@ static int soft_spi_probe(struct udevice *dev)
 	struct spi_slave *slave = dev_get_parent_priv(dev);
 	struct soft_spi_platdata *plat = dev->platdata;
 	int cs_flags, clk_flags;
+	int ret;
 
 	cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
 	clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
-	if (gpio_request_by_name(dev, "cs-gpio", 0, &plat->cs,
+
+	if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
 				 GPIOD_IS_OUT | cs_flags) ||
-	    gpio_request_by_name(dev, "sclk-gpio", 0, &plat->sclk,
-				 GPIOD_IS_OUT | clk_flags) ||
-	    gpio_request_by_name(dev, "mosi-gpio", 0, &plat->mosi,
-				 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE) ||
-	    gpio_request_by_name(dev, "miso-gpio", 0, &plat->miso,
-				 GPIOD_IS_IN))
+	    gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
+				 GPIOD_IS_OUT | clk_flags))
+		return -EINVAL;
+
+	ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret)
+		plat->flags |= SPI_MASTER_NO_TX;
+
+	ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
+				   GPIOD_IS_IN);
+	if (ret)
+		plat->flags |= SPI_MASTER_NO_RX;
+
+	if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
+	    (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX))
 		return -EINVAL;
 
 	return 0;
 }
 
 static const struct udevice_id soft_spi_ids[] = {
-	{ .compatible = "u-boot,soft-spi" },
+	{ .compatible = "spi-gpio" },
 	{ }
 };
 
-- 
cgit v0.10.2


From 7a3eff4ce962de50bd9a1d83a9fce178c04999d3 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 10:02:22 +0800
Subject: dm: spi: introduce dm api

Introduce dm_spi_claim_bus, dm_spi_release_bus and dm_spi_xfer
Convert spi_claim_bus, spi_release_bus and spi_xfer to use
the new API.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 5561f36..84b6786 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -45,12 +45,12 @@ static int spi_set_speed_mode(struct udevice *bus, int speed, int mode)
 	return 0;
 }
 
-int spi_claim_bus(struct spi_slave *slave)
+int dm_spi_claim_bus(struct udevice *dev)
 {
-	struct udevice *dev = slave->dev;
 	struct udevice *bus = dev->parent;
 	struct dm_spi_ops *ops = spi_get_ops(bus);
 	struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
 	int speed;
 	int ret;
 
@@ -73,9 +73,8 @@ int spi_claim_bus(struct spi_slave *slave)
 	return ops->claim_bus ? ops->claim_bus(dev) : 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
+void dm_spi_release_bus(struct udevice *dev)
 {
-	struct udevice *dev = slave->dev;
 	struct udevice *bus = dev->parent;
 	struct dm_spi_ops *ops = spi_get_ops(bus);
 
@@ -83,10 +82,9 @@ void spi_release_bus(struct spi_slave *slave)
 		ops->release_bus(dev);
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-	     const void *dout, void *din, unsigned long flags)
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
 {
-	struct udevice *dev = slave->dev;
 	struct udevice *bus = dev->parent;
 
 	if (bus->uclass->uc_drv->id != UCLASS_SPI)
@@ -95,6 +93,22 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
 }
 
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return dm_spi_claim_bus(slave->dev);
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	dm_spi_release_bus(slave->dev);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *dout, void *din, unsigned long flags)
+{
+	return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
+}
+
 static int spi_post_bind(struct udevice *dev)
 {
 	/* Scan the bus for devices */
diff --git a/include/spi.h b/include/spi.h
index 4b88d39..ca96fa4 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -612,6 +612,58 @@ int sandbox_spi_get_emul(struct sandbox_state *state,
 			 struct udevice *bus, struct udevice *slave,
 			 struct udevice **emulp);
 
+/**
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * @dev:	The SPI slave device
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int dm_spi_claim_bus(struct udevice *dev);
+
+/**
+ * Release the SPI bus
+ *
+ * This must be called once for every call to dm_spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * @slave:	The SPI slave device
+ */
+void dm_spi_release_bus(struct udevice *dev);
+
+/**
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * dm_spi_xfer() interface:
+ * @dev:	The SPI slave device which will be sending/receiving the data.
+ * @bitlen:	How many bits to write and read.
+ * @dout:	Pointer to a string of bits to send out.  The bits are
+ *		held in a byte array and are sent MSB first.
+ * @din:	Pointer to a string of bits that will be filled in.
+ * @flags:	A bitwise combination of SPI_XFER_* flags.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags);
+
 /* Access the operations for a SPI device */
 #define spi_get_ops(dev)	((struct dm_spi_ops *)(dev)->driver->ops)
 #define spi_emul_get_ops(dev)	((struct dm_spi_emul_ops *)(dev)->driver->ops)
-- 
cgit v0.10.2


From 9300f711baac8a181f70d7f64978e4bbadd4ac5c Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 10:02:23 +0800
Subject: dm: gpio: introduce 74x164 driver

Introduce driver to support "fairchild,74hc595" devices.
1. Take linux drivers/drivers/gpio/gpio-74x164.c as reference.
2. Following the naming used in Linux driver with gen_7x164 as the prefix.
3. Enable CONFIG_DM_74X164 to use this driver.
4. Follow Documentation/devicetree/bindings/gpio/gpio-74x164.txt to add device
   nodes
5. Tested on i.MX6 UltraLite with 74LV595 using gpio command and oscillograph.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c
new file mode 100644
index 0000000..9ac10a7
--- /dev/null
+++ b/drivers/gpio/74x164_gpio.c
@@ -0,0 +1,193 @@
+/*
+ * Take drivers/gpio/gpio-74x164.c as reference.
+ *
+ * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
+ *
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * struct gen_74x164_chip - Data for 74Hx164
+ *
+ * @oe: OE pin
+ * @nregs: number of registers
+ * @buffer: buffer for chained chips
+ */
+#define GEN_74X164_NUMBER_GPIOS 8
+
+struct gen_74x164_priv {
+	struct gpio_desc oe;
+	u32 nregs;
+	/*
+	 * Since the nregs are chained, every byte sent will make
+	 * the previous byte shift to the next register in the
+	 * chain. Thus, the first byte sent will end up in the last
+	 * register at the end of the transfer. So, to have a logical
+	 * numbering, store the bytes in reverse order.
+	 */
+	u8 *buffer;
+};
+
+static int gen_74x164_write_conf(struct udevice *dev)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = dm_spi_claim_bus(dev);
+	if (ret)
+		return ret;
+
+	ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
+			  SPI_XFER_BEGIN | SPI_XFER_END);
+
+	dm_spi_release_bus(dev);
+
+	return ret;
+}
+
+static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	uint bank = priv->nregs - 1 - offset / 8;
+	uint pin = offset % 8;
+
+	return (priv->buffer[bank] >> pin) & 0x1;
+}
+
+static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
+				int value)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	uint bank = priv->nregs - 1 - offset / 8;
+	uint pin = offset % 8;
+	int ret;
+
+	if (value)
+		priv->buffer[bank] |= 1 << pin;
+	else
+		priv->buffer[bank] &= ~(1 << pin);
+
+	ret = gen_74x164_write_conf(dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
+{
+	return -ENOSYS;
+}
+
+static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
+				      int value)
+{
+	return gen_74x164_set_value(dev, offset, value);
+}
+
+static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
+{
+	return GPIOF_OUTPUT;
+}
+
+static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
+			    struct fdtdec_phandle_args *args)
+{
+	desc->offset = args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gen_74x164_ops = {
+	.direction_input	= gen_74x164_direction_input,
+	.direction_output	= gen_74x164_direction_output,
+	.get_value		= gen_74x164_get_value,
+	.set_value		= gen_74x164_set_value,
+	.get_function		= gen_74x164_get_function,
+	.xlate			= gen_74x164_xlate,
+};
+
+static int gen_74x164_probe(struct udevice *dev)
+{
+	struct gen_74x164_priv *priv = dev_get_priv(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	char *str, name[32];
+	int ret;
+	const void *fdt = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	snprintf(name, sizeof(name), "%s_", dev->name);
+	str = strdup(name);
+	if (!str)
+		return -ENOMEM;
+
+	/*
+	 * See Linux kernel:
+	 * Documentation/devicetree/bindings/gpio/gpio-74x164.txt
+	 */
+	priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
+	priv->buffer = calloc(priv->nregs, sizeof(u8));
+	if (!priv->buffer) {
+		ret = -ENOMEM;
+		goto free_str;
+	}
+
+	ret = fdtdec_get_byte_array(fdt, node, "registers-default",
+				    priv->buffer, priv->nregs);
+	if (ret)
+		dev_dbg(dev, "No registers-default property\n");
+
+	ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret) {
+		dev_err(dev, "No oe-pins property\n");
+		goto free_buf;
+	}
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = priv->nregs * 8;
+
+	ret = gen_74x164_write_conf(dev);
+	if (ret)
+		goto free_buf;
+
+	dev_dbg(dev, "%s is ready\n", dev->name);
+
+	return 0;
+
+free_buf:
+	free(priv->buffer);
+free_str:
+	free(str);
+	return ret;
+}
+
+static const struct udevice_id gen_74x164_ids[] = {
+	{ .compatible = "fairchild,74hc595" },
+	{ }
+};
+
+U_BOOT_DRIVER(74x164) = {
+	.name		= "74x164",
+	.id		= UCLASS_GPIO,
+	.ops		= &gen_74x164_ops,
+	.probe		= gen_74x164_probe,
+	.priv_auto_alloc_size = sizeof(struct gen_74x164_priv),
+	.of_match	= gen_74x164_ids,
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e6337c2..93a7e8c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -143,6 +143,14 @@ config ZYNQ_GPIO
 	help
 	  Supports GPIO access on Zynq SoC.
 
+config DM_74X164
+	bool "74x164 serial-in/parallel-out 8-bits shift register"
+	depends on DM_GPIO
+	help
+	  Driver for 74x164 compatible serial-in/parallel-out 8-outputs
+	  shift registers, such as 74lv165, 74hc595.
+	  This driver can be used to provide access to more gpio outputs.
+
 config DM_PCA953X
 	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4b1f6b9..ddec1ef 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,6 +12,7 @@ endif
 obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
 
 obj-$(CONFIG_DM_PCA953X)	+= pca953x_gpio.o
+obj-$(CONFIG_DM_74X164)		+= 74x164_gpio.o
 
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
-- 
cgit v0.10.2


From c0c62d923344d5a68f43259282e68a827318db01 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Tue, 12 Apr 2016 16:01:19 +0530
Subject: drivers: usb: common: add common code for usb drivers to use

Add common usb code which usb drivers makes use of it.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index 2f3d43d..2f46d38 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -3,5 +3,6 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+obj-$(CONFIG_DM_USB) += common.o
 obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
 obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
new file mode 100644
index 0000000..35c2dc1
--- /dev/null
+++ b/drivers/usb/common/common.c
@@ -0,0 +1,40 @@
+/*
+ * Provides code common for host and device side USB.
+ *
+ * (C) Copyright 2016
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/usb/otg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *const usb_dr_modes[] = {
+	[USB_DR_MODE_UNKNOWN]		= "",
+	[USB_DR_MODE_HOST]		= "host",
+	[USB_DR_MODE_PERIPHERAL]	= "peripheral",
+	[USB_DR_MODE_OTG]		= "otg",
+};
+
+enum usb_dr_mode usb_get_dr_mode(int node)
+{
+	const void *fdt = gd->fdt_blob;
+	const char *dr_mode;
+	int i;
+
+	dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
+	if (!dr_mode) {
+		error("usb dr_mode not found\n");
+		return USB_DR_MODE_UNKNOWN;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
+		if (!strcmp(dr_mode, usb_dr_modes[i]))
+			return i;
+
+	return USB_DR_MODE_UNKNOWN;
+}
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 7ec5550..8f8ac6a 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -17,4 +17,13 @@ enum usb_dr_mode {
 	USB_DR_MODE_OTG,
 };
 
+/**
+ * usb_get_dr_mode() - Get dual role mode for given device
+ * @node: Node offset to the given device
+ *
+ * The function gets phy interface string from property 'dr_mode',
+ * and returns the correspondig enum usb_dr_mode
+ */
+enum usb_dr_mode usb_get_dr_mode(int node);
+
 #endif /* __LINUX_USB_OTG_H */
-- 
cgit v0.10.2


From 6c880b7719d73dc4bf4bf828b6341e086e6f5eb6 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Sun, 24 Apr 2016 16:32:40 -0700
Subject: dm: gpio: add a default gpio xlate routine

Many drivers use a common form of offset + flags for device
tree nodes. e.g.:
	<&gpio1 2 GPIO_ACTIVE_LOW>

This patch adds a common implementation of this type of parsing
and calls it when a gpio driver doesn't supply its' own xlate
routine.

This will allow removal of the driver-specific versions in a
handful of drivers and simplify the addition of new drivers.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index b58d4e6..732b6c2 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
@@ -113,19 +114,33 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
 	return 0;
 }
 
+int gpio_xlate_offs_flags(struct udevice *dev,
+					 struct gpio_desc *desc,
+					 struct fdtdec_phandle_args *args)
+{
+	if (args->args_count < 1)
+		return -EINVAL;
+
+	desc->offset = args->args[0];
+
+	if (args->args_count < 2)
+		return 0;
+
+	if (args->args[1] & GPIO_ACTIVE_LOW)
+		desc->flags = GPIOD_ACTIVE_LOW;
+
+	return 0;
+}
+
 static int gpio_find_and_xlate(struct gpio_desc *desc,
 			       struct fdtdec_phandle_args *args)
 {
 	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
 
-	/* Use the first argument as the offset by default */
-	if (args->args_count > 0)
-		desc->offset = args->args[0];
+	if (ops->xlate)
+		return ops->xlate(desc->dev, desc, args);
 	else
-		desc->offset = -1;
-	desc->flags = 0;
-
-	return ops->xlate ? ops->xlate(desc->dev, desc, args) : 0;
+		return gpio_xlate_offs_flags(desc->dev, desc, args);
 }
 
 int dm_gpio_request(struct gpio_desc *desc, const char *label)
@@ -605,6 +620,7 @@ static int _gpio_request_by_name_nodev(const void *blob, int node,
 
 	desc->dev = NULL;
 	desc->offset = 0;
+	desc->flags = 0;
 	ret = fdtdec_parse_phandle_with_args(blob, node, list_name,
 					     "#gpio-cells", 0, index, &args);
 	if (ret) {
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 68b5f0b..2500c10 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -207,6 +207,16 @@ int gpio_requestf(unsigned gpio, const char *fmt, ...)
 struct fdtdec_phandle_args;
 
 /**
+ * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate
+ *
+ * This routine sets the offset field to args[0] and the flags field to
+ * GPIOD_ACTIVE_LOW if the GPIO_ACTIVE_LOW flag is present in args[1].
+ *
+ */
+int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
+			  struct fdtdec_phandle_args *args);
+
+/**
  * struct struct dm_gpio_ops - Driver model GPIO operations
  *
  * Refer to functions above for description. These function largely copy
@@ -258,12 +268,11 @@ struct dm_gpio_ops {
 	 *
 	 *   @desc->dev to @dev
 	 *   @desc->flags to 0
-	 *   @desc->offset to the value of the first argument in args, if any,
-	 *		otherwise -1 (which is invalid)
+	 *   @desc->offset to 0
 	 *
-	 * This method is optional so if the above defaults suit it can be
-	 * omitted. Typical behaviour is to set up the GPIOD_ACTIVE_LOW flag
-	 * in desc->flags.
+	 * This method is optional and defaults to gpio_xlate_offs_flags,
+	 * which will parse offset and the GPIO_ACTIVE_LOW flag in the first
+	 * two arguments.
 	 *
 	 * Note that @dev is passed in as a parameter to follow driver model
 	 * uclass conventions, even though it is already available as
-- 
cgit v0.10.2


From 8376aaddaf29b5ec296759f2b374cf940b932962 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Wed, 20 Apr 2016 08:37:35 -0700
Subject: gpio: intel_broadwell: remove gpio_xlate routine

With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the intel_broadwell driver doesn't need a custom xlate routine.

Signed-off-by: Eric Nelson <eric@nelint.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 8cf76f9..81ce446 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -162,15 +162,6 @@ static int broadwell_gpio_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
-static int broadwell_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-				struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_broadwell_ops = {
 	.request		= broadwell_gpio_request,
 	.direction_input	= broadwell_gpio_direction_input,
@@ -178,7 +169,6 @@ static const struct dm_gpio_ops gpio_broadwell_ops = {
 	.get_value		= broadwell_gpio_get_value,
 	.set_value		= broadwell_gpio_set_value,
 	.get_function		= broadwell_gpio_get_function,
-	.xlate			= broadwell_gpio_xlate,
 };
 
 static const struct udevice_id intel_broadwell_gpio_ids[] = {
-- 
cgit v0.10.2


From 86222f6140895e451eafefc25437a33fa394dba5 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Wed, 20 Apr 2016 08:37:36 -0700
Subject: gpio: omap: remove gpio_xlate routine

With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the omap gpio driver doesn't need a custom xlate routine.

Signed-off-by: Eric Nelson <eric@nelint.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index 93d18e4..cd960dc 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -25,7 +25,6 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <malloc.h>
-#include <dt-bindings/gpio/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -277,22 +276,12 @@ static int omap_gpio_get_function(struct udevice *dev, unsigned offset)
 		return GPIOF_INPUT;
 }
 
-static int omap_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			   struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_omap_ops = {
 	.direction_input	= omap_gpio_direction_input,
 	.direction_output	= omap_gpio_direction_output,
 	.get_value		= omap_gpio_get_value,
 	.set_value		= omap_gpio_set_value,
 	.get_function		= omap_gpio_get_function,
-	.xlate			= omap_gpio_xlate,
 };
 
 static int omap_gpio_probe(struct udevice *dev)
-- 
cgit v0.10.2


From 5206e7bff575e3c0b96b8db89c80d4f020ed7539 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Wed, 20 Apr 2016 08:37:37 -0700
Subject: gpio: pic32: remove gpio_xlate routine

With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the pic32 gpio driver doesn't need a custom xlate routine.

Signed-off-by: Eric Nelson <eric@nelint.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Purna Chandra Mandal <purna.mandal@microchip.com>

diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
index 499b4fa..7a037f3 100644
--- a/drivers/gpio/pic32_gpio.c
+++ b/drivers/gpio/pic32_gpio.c
@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <linux/compat.h>
-#include <dt-bindings/gpio/gpio.h>
 #include <mach/pic32.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -99,14 +98,6 @@ static int pic32_gpio_direction_output(struct udevice *dev,
 	return 0;
 }
 
-static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			    struct fdtdec_phandle_args *args)
-{
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
 {
 	int ret = GPIOF_UNUSED;
@@ -131,7 +122,6 @@ static const struct dm_gpio_ops gpio_pic32_ops = {
 	.get_value		= pic32_gpio_get_value,
 	.set_value		= pic32_gpio_set_value,
 	.get_function		= pic32_gpio_get_function,
-	.xlate			= pic32_gpio_xlate,
 };
 
 static int pic32_gpio_probe(struct udevice *dev)
-- 
cgit v0.10.2


From 6c3dd3caf0e6469fa65819aec300210f97ad7536 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Wed, 20 Apr 2016 08:37:38 -0700
Subject: gpio: rk: remove gpio_xlate routine

With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Rockchip gpio driver doesn't need a custom xlate routine.

Signed-off-by: Eric Nelson <eric@nelint.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 40e87bd..fefe3ca 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -16,7 +16,6 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <dm/pinctrl.h>
-#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 
 enum {
@@ -98,15 +97,6 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
 #endif
 }
 
-static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			    struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static int rockchip_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -135,7 +125,6 @@ static const struct dm_gpio_ops gpio_rockchip_ops = {
 	.get_value		= rockchip_gpio_get_value,
 	.set_value		= rockchip_gpio_set_value,
 	.get_function		= rockchip_gpio_get_function,
-	.xlate			= rockchip_gpio_xlate,
 };
 
 static const struct udevice_id rockchip_gpio_ids[] = {
-- 
cgit v0.10.2


From f8353033884a25bedfef20e1fcc509db38a15218 Mon Sep 17 00:00:00 2001
From: Eric Nelson <eric@nelint.com>
Date: Wed, 20 Apr 2016 08:37:39 -0700
Subject: gpio: exynos(s5p): remove gpio_xlate routine

With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Exynos/S5P gpio driver doesn't need a custom xlate routine.

Signed-off-by: Eric Nelson <eric@nelint.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 0f22b23..377fed4 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dm/device-internal.h>
-#include <dt-bindings/gpio/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -276,22 +275,12 @@ static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
 		return GPIOF_FUNC;
 }
 
-static int exynos_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
-			     struct fdtdec_phandle_args *args)
-{
-	desc->offset = args->args[0];
-	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
-	return 0;
-}
-
 static const struct dm_gpio_ops gpio_exynos_ops = {
 	.direction_input	= exynos_gpio_direction_input,
 	.direction_output	= exynos_gpio_direction_output,
 	.get_value		= exynos_gpio_get_value,
 	.set_value		= exynos_gpio_set_value,
 	.get_function		= exynos_gpio_get_function,
-	.xlate			= exynos_gpio_xlate,
 };
 
 static int gpio_exynos_probe(struct udevice *dev)
-- 
cgit v0.10.2


From e161356bffd5b6757a43b9c55a81903227ddd20c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:49 -0600
Subject: Revert "dm: sandbox: Drop the pre-DM host implementation"

Bring this support back so that sandbox can be compiled with CONFIG_BLK. This
allows sandbox to have greater build coverage during the block-device
transition. This can be removed again later.

This reverts commit 33cf727b1634dbd9cd68a6ebc444a88f053822d7.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 2d340ef..6d41508 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -17,6 +17,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_BLK
+static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES];
+
+static struct host_block_dev *find_host_device(int dev)
+{
+	if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES)
+		return &host_devices[dev];
+
+	return NULL;
+}
+#endif
+
+#ifdef CONFIG_BLK
 static unsigned long host_block_read(struct udevice *dev,
 				     unsigned long start, lbaint_t blkcnt,
 				     void *buffer)
@@ -24,6 +37,18 @@ static unsigned long host_block_read(struct udevice *dev,
 	struct host_block_dev *host_dev = dev_get_priv(dev);
 	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 
+#else
+static unsigned long host_block_read(struct blk_desc *block_dev,
+				     unsigned long start, lbaint_t blkcnt,
+				     void *buffer)
+{
+	int dev = block_dev->devnum;
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -1;
+#endif
+
 	if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
 			-1) {
 		printf("ERROR: Invalid block %lx\n", start);
@@ -35,12 +60,21 @@ static unsigned long host_block_read(struct udevice *dev,
 	return -1;
 }
 
+#ifdef CONFIG_BLK
 static unsigned long host_block_write(struct udevice *dev,
 				      unsigned long start, lbaint_t blkcnt,
 				      const void *buffer)
 {
 	struct host_block_dev *host_dev = dev_get_priv(dev);
 	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#else
+static unsigned long host_block_write(struct blk_desc *block_dev,
+				      unsigned long start, lbaint_t blkcnt,
+				      const void *buffer)
+{
+	int dev = block_dev->devnum;
+	struct host_block_dev *host_dev = find_host_device(dev);
+#endif
 
 	if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
 			-1) {
@@ -53,6 +87,7 @@ static unsigned long host_block_write(struct udevice *dev,
 	return -1;
 }
 
+#ifdef CONFIG_BLK
 int host_dev_bind(int devnum, char *filename)
 {
 	struct host_block_dev *host_dev;
@@ -115,9 +150,51 @@ err:
 	free(str);
 	return ret;
 }
+#else
+int host_dev_bind(int dev, char *filename)
+{
+	struct host_block_dev *host_dev = find_host_device(dev);
+
+	if (!host_dev)
+		return -1;
+	if (host_dev->blk_dev.priv) {
+		os_close(host_dev->fd);
+		host_dev->blk_dev.priv = NULL;
+	}
+	if (host_dev->filename)
+		free(host_dev->filename);
+	if (filename && *filename) {
+		host_dev->filename = strdup(filename);
+	} else {
+		host_dev->filename = NULL;
+		return 0;
+	}
+
+	host_dev->fd = os_open(host_dev->filename, OS_O_RDWR);
+	if (host_dev->fd == -1) {
+		printf("Failed to access host backing file '%s'\n",
+		       host_dev->filename);
+		return 1;
+	}
+
+	struct blk_desc *blk_dev = &host_dev->blk_dev;
+	blk_dev->if_type = IF_TYPE_HOST;
+	blk_dev->priv = host_dev;
+	blk_dev->blksz = 512;
+	blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz;
+	blk_dev->block_read = host_block_read;
+	blk_dev->block_write = host_block_write;
+	blk_dev->devnum = dev;
+	blk_dev->part_type = PART_TYPE_UNKNOWN;
+	part_init(blk_dev);
+
+	return 0;
+}
+#endif
 
 int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
 {
+#ifdef CONFIG_BLK
 	struct udevice *dev;
 	int ret;
 
@@ -125,6 +202,17 @@ int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
 	if (ret)
 		return ret;
 	*blk_devp = dev_get_uclass_platdata(dev);
+#else
+	struct host_block_dev *host_dev = find_host_device(devnum);
+
+	if (!host_dev)
+		return -ENODEV;
+
+	if (!host_dev->blk_dev.priv)
+		return -ENOENT;
+
+	*blk_devp = &host_dev->blk_dev;
+#endif
 
 	return 0;
 }
@@ -139,6 +227,7 @@ struct blk_desc *host_get_dev(int dev)
 	return blk_dev;
 }
 
+#ifdef CONFIG_BLK
 static const struct blk_ops sandbox_host_blk_ops = {
 	.read	= host_block_read,
 	.write	= host_block_write,
@@ -150,3 +239,4 @@ U_BOOT_DRIVER(sandbox_host_blk) = {
 	.ops		= &sandbox_host_blk_ops,
 	.priv_auto_alloc_size	= sizeof(struct host_block_dev),
 };
+#endif
-- 
cgit v0.10.2


From f960ca0a5fde2d1ec673d335a06a0f408734b3b3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:50 -0600
Subject: dm: sandbox: Add a board for sandbox without CONFIG_BLK

While the driver-model block device support is in progress, it is useful to
build sandbox both with and without CONFIG_BLK. Add a separate board for
the latter.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS
index 10d88a2..f5db773 100644
--- a/board/sandbox/MAINTAINERS
+++ b/board/sandbox/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/sandbox/
 F:	include/configs/sandbox.h
 F:	configs/sandbox_defconfig
+
+SANDBOX_NOBLK BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox.h
+F:	configs/sandbox_noblk_defconfig
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
new file mode 100644
index 0000000..93167c2
--- /dev/null
+++ b/configs/sandbox_noblk_defconfig
@@ -0,0 +1,168 @@
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_PCI=y
+CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_I8042_KEYB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_FDT=y
+CONFIG_BOOTSTAGE_STASH=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_CONSOLE_RECORD=y
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_LOOPW=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DEMO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_HOSTFILE=y
+CONFIG_NETCONSOLE=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DEVRES=y
+CONFIG_DEBUG_DEVRES=y
+CONFIG_ADC=y
+CONFIG_ADC_SANDBOX=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_DEMO=y
+CONFIG_DM_DEMO_SIMPLE=y
+CONFIG_DM_DEMO_SHAPE=y
+CONFIG_PM8916_GPIO=y
+CONFIG_SANDBOX_GPIO=y
+CONFIG_DM_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_SANDBOX=y
+CONFIG_I2C_MUX=y
+CONFIG_SPL_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_CROS_EC_SANDBOX=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_SPL_PWRSEQ=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH_SANDBOX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_SANDBOX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_PINCTRL_SANDBOX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_PMIC_MAX77686=y
+CONFIG_PMIC_PM8916=y
+CONFIG_PMIC_RK808=y
+CONFIG_PMIC_S2MPS11=y
+CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_S5M8767=y
+CONFIG_PMIC_TPS65090=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_MAX77686=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_DM_REGULATOR_SANDBOX=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_SANDBOX=y
+CONFIG_DM_RTC=y
+CONFIG_SANDBOX_SERIAL=y
+CONFIG_SOUND=y
+CONFIG_SOUND_SANDBOX=y
+CONFIG_SANDBOX_SPI=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
+CONFIG_TIMER=y
+CONFIG_TIMER_EARLY=y
+CONFIG_SANDBOX_TIMER=y
+CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EMUL=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CONSOLE_ROTATION=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_TPM=y
+CONFIG_LZ4=y
+CONFIG_ERRNO_STR=y
+CONFIG_UNIT_TEST=y
+CONFIG_UT_TIME=y
+CONFIG_UT_DM=y
+CONFIG_UT_ENV=y
-- 
cgit v0.10.2


From cf63084492377108698619f6d33967af2119e584 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:51 -0600
Subject: pci: Drop CONFIG_SYS_SCSI_SCAN_BUS_REVERSE

This option is not used by any board. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4619089..4b73a0f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -175,11 +175,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 	int bus;
 
 	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
-#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-		for (bus = hose->last_busno; bus >= hose->first_busno; bus--) {
-#else
 		for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
-#endif
 			bdf = pci_hose_find_devices(hose, bus, ids, &index);
 			if (bdf != -1)
 				return bdf;
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 2f94c82..5e23007 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -354,8 +354,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 
-#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index a7c7aef..c9970f1 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -297,8 +297,6 @@
 
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
-#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
-- 
cgit v0.10.2


From a219639d4216e59a0c55f0b7d2c8a21f9cb0bb06 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:52 -0600
Subject: dm: Rename disk uclass to ahci

This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4ef27dc..396023e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -47,6 +47,9 @@ source "arch/x86/cpu/queensbay/Kconfig"
 
 # architecture-specific options below
 
+config AHCI
+	default y
+
 config SYS_MALLOC_F_LEN
 	default 0x800
 
diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c
index dfb8486..2e47082 100644
--- a/arch/x86/cpu/broadwell/sata.c
+++ b/arch/x86/cpu/broadwell/sata.c
@@ -261,7 +261,7 @@ static const struct udevice_id broadwell_ahci_ids[] = {
 
 U_BOOT_DRIVER(ahci_broadwell_drv) = {
 	.name		= "ahci_broadwell",
-	.id		= UCLASS_DISK,
+	.id		= UCLASS_AHCI,
 	.of_match	= broadwell_ahci_ids,
 	.ofdata_to_platdata	= broadwell_sata_ofdata_to_platdata,
 	.probe		= broadwell_sata_probe,
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 93e4505..0fdef6f 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -58,7 +58,7 @@ int cpu_common_init(void)
 		return -ENODEV;
 
 	/* Cause the SATA device to do its early init */
-	uclass_first_device(UCLASS_DISK, &dev);
+	uclass_first_device(UCLASS_AHCI, &dev);
 
 	return 0;
 }
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 4c039ac..5b58d6c 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -162,7 +162,7 @@ static int bd82x6x_probe(struct udevice *dev)
 		return 0;
 
 	/* Cause the SATA device to do its init */
-	uclass_first_device(UCLASS_DISK, &dev);
+	uclass_first_device(UCLASS_AHCI, &dev);
 
 	ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
 	if (ret)
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index c3d1057..1ce8195 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -233,7 +233,7 @@ static const struct udevice_id bd82x6x_ahci_ids[] = {
 
 U_BOOT_DRIVER(ahci_ivybridge_drv) = {
 	.name		= "ahci_ivybridge",
-	.id		= UCLASS_DISK,
+	.id		= UCLASS_AHCI,
 	.of_match	= bd82x6x_ahci_ids,
 	.probe		= bd82x6x_sata_probe,
 };
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index fcc9ccd..80eea84 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -9,10 +9,9 @@ config BLK
 	  be partitioned into several areas, called 'partitions' in U-Boot.
 	  A filesystem can be placed in each partition.
 
-config DISK
-	bool "Support disk controllers with driver model"
+config AHCI
+	bool "Support SATA controllers with driver model"
 	depends on DM
-	default y if DM
 	help
 	  This enables a uclass for disk controllers in U-Boot. Various driver
 	  types can use this, such as AHCI/SATA. It does not provide any standard
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index a43492f..b832ae1 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -7,7 +7,7 @@
 
 obj-$(CONFIG_BLK) += blk-uclass.o
 
-obj-$(CONFIG_DISK) += disk-uclass.o
+obj-$(CONFIG_AHCI) += ahci-uclass.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 obj-$(CONFIG_FSL_SATA) += fsl_sata.o
diff --git a/drivers/block/ahci-uclass.c b/drivers/block/ahci-uclass.c
new file mode 100644
index 0000000..7b8c326
--- /dev/null
+++ b/drivers/block/ahci-uclass.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+UCLASS_DRIVER(ahci) = {
+	.id		= UCLASS_AHCI,
+	.name		= "ahci",
+};
diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c
deleted file mode 100644
index d665b35..0000000
--- a/drivers/block/disk-uclass.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-
-UCLASS_DRIVER(disk) = {
-	.id		= UCLASS_DISK,
-	.name		= "disk",
-};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index cbf9b2c..a5cf6e2 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -26,11 +26,11 @@ enum uclass_id {
 
 	/* U-Boot uclasses start here - in alphabetical order */
 	UCLASS_ADC,		/* Analog-to-digital converter */
+	UCLASS_AHCI,		/* SATA disk controller */
 	UCLASS_BLK,		/* Block device */
 	UCLASS_CLK,		/* Clock source, e.g. used by peripherals */
 	UCLASS_CPU,		/* CPU, typically part of an SoC */
 	UCLASS_CROS_EC,		/* Chrome OS EC */
-	UCLASS_DISK,		/* Disk controller, e.g. SATA */
 	UCLASS_DISPLAY,		/* Display (e.g. DisplayPort, HDMI) */
 	UCLASS_DMA,		/* Direct Memory Access */
 	UCLASS_RAM,		/* RAM controller */
-- 
cgit v0.10.2


From 709e98b7b2461c2535d4ac2bb0311c3b3f53dbbb Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:53 -0600
Subject: Allow iotrace byte access to use an address of any size

If an address is used with readb() and writeb() which is smaller than the
expected size (e.g. 32-bit value on a machine with 64-bit addresses), a
warning results. Fix this by adding a cast.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/iotrace.h b/include/iotrace.h
index 9bd1f16..e4ceb61 100644
--- a/include/iotrace.h
+++ b/include/iotrace.h
@@ -31,10 +31,11 @@
 #define writew(val, addr)	iotrace_writew(val, (const void *)(addr))
 
 #undef readb
-#define readb(addr)	iotrace_readb((const void *)(addr))
+#define readb(addr)	iotrace_readb((const void *)(uintptr_t)addr)
 
 #undef writeb
-#define writeb(val, addr)	iotrace_writeb(val, (const void *)(addr))
+#define writeb(val, addr) \
+	iotrace_writeb(val, (const void *)(uintptr_t)addr)
 
 #endif
 
-- 
cgit v0.10.2


From e54094f2f9e812ae7b0d2ab2353ca11c0502849a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:54 -0600
Subject: sandbox: Add string and 16-bit I/O functions

Add outsw() and insw() functions for sandbox, as these are needed by the IDE
code. The functions will not do anything useful if called, but allow the
code to be compiled.

Also add out16() and in16(), required by systemace.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index b87ee19..6919632 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -56,6 +56,21 @@ void outl(unsigned int value, unsigned int addr);
 void outw(unsigned int value, unsigned int addr);
 void outb(unsigned int value, unsigned int addr);
 
+static inline void _insw(volatile u16 *port, void *buf, int ns)
+{
+}
+
+static inline void _outsw(volatile u16 *port, const void *buf, int ns)
+{
+}
+
+#define insw(port, buf, ns)		_insw((u16 *)port, buf, ns)
+#define outsw(port, buf, ns)		_outsw((u16 *)port, buf, ns)
+
+/* For systemace.c */
+#define out16(addr, val)
+#define in16(addr)		0
+
 #include <iotrace.h>
 #include <asm/types.h>
 
-- 
cgit v0.10.2


From 84d39cbd30a49390457232b44031e95abfa46e77 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:55 -0600
Subject: sandbox: Add dummy SCSI functions

Add some functions needed by the SCSI code. This allows it to be compiled
for sandbox, thus increasing build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index b832ae1..3b48eac 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_IDE_SIL680) += sil680.o
-obj-$(CONFIG_SANDBOX) += sandbox.o
+obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o
 obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
 obj-$(CONFIG_SYSTEMACE) += systemace.o
 obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
diff --git a/drivers/block/sandbox_scsi.c b/drivers/block/sandbox_scsi.c
new file mode 100644
index 0000000..ad961bd
--- /dev/null
+++ b/drivers/block/sandbox_scsi.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file contains dummy implementations of SCSI functions requried so
+ * that CONFIG_SCSI can be enabled for sandbox.
+ */
+
+#include <common.h>
+#include <scsi.h>
+
+void scsi_bus_reset(void)
+{
+}
+
+void scsi_init(void)
+{
+}
+
+int scsi_exec(ccb *pccb)
+{
+	return 0;
+}
+
+void scsi_print_error(ccb *pccb)
+{
+}
-- 
cgit v0.10.2


From a31e2c93cb9eb1d4fe732b5586316235dad537ea Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:56 -0600
Subject: sandbox: Add dummy SATA functions

Add some functions needed by the SATA code. This allows it to be compiled
for sandbox, thus increasing build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 3b48eac..3f75934 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_IDE_SIL680) += sil680.o
-obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o
+obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o sata_sandbox.o
 obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
 obj-$(CONFIG_SYSTEMACE) += systemace.o
 obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
diff --git a/drivers/block/sata_sandbox.c b/drivers/block/sata_sandbox.c
new file mode 100644
index 0000000..bd967d2
--- /dev/null
+++ b/drivers/block/sata_sandbox.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int init_sata(int dev)
+{
+	return 0;
+}
+
+int reset_sata(int dev)
+{
+	return 0;
+}
+
+int scan_sata(int dev)
+{
+	return 0;
+}
+
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+	return 0;
+}
+
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
+{
+	return 0;
+}
-- 
cgit v0.10.2


From 73a9cfde783421aa7355143bc5b535ae81126d2c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:57 -0600
Subject: dm: scsi: Remove the forward declarations

Reorder the code to avoid needing forward declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/scsi.c b/cmd/scsi.c
index 8991125..9ba070f 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -50,130 +50,230 @@ static int scsi_curr_dev; /* current device */
 
 static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
 
-/********************************************************************************
- *  forward declerations of some Setup Routines
+/****************************************************************************************
+ * scsi_read
  */
-void scsi_setup_test_unit_ready(ccb * pccb);
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks);
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks);
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks);
 
-static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
-				unsigned short blocks);
-void scsi_setup_inquiry(ccb * pccb);
-void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
+/* almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_READ_BLK 0xFFFF
+#define SCSI_LBA48_READ	0xFFFFFFF
 
+#ifdef CONFIG_SYS_64BIT_LBA
+void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
+{
+	pccb->cmd[0] = SCSI_READ16;
+	pccb->cmd[1] = pccb->lun<<5;
+	pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
+	pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
+	pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
+	pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
+	pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
+	pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
+	pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
+	pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
+	pccb->cmd[10] = 0;
+	pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
+	pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
+	pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
+	pccb->cmd[14] = (unsigned char) blocks & 0xff;
+	pccb->cmd[15] = 0;
+	pccb->cmdlen = 16;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug ("scsi_setup_read16: cmd: %02X %02X "
+	       "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
+	       "blccnt %02X%02X%02X%02X\n",
+		pccb->cmd[0], pccb->cmd[1],
+		pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+		pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+		pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+}
+#endif
 
-static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
-			      unsigned long *blksz);
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
-		       lbaint_t blkcnt, void *buffer);
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, const void *buffer);
+void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0]=SCSI_READ10;
+	pccb->cmd[1]=pccb->lun<<5;
+	pccb->cmd[2]=((unsigned char) (start>>24))&0xff;
+	pccb->cmd[3]=((unsigned char) (start>>16))&0xff;
+	pccb->cmd[4]=((unsigned char) (start>>8))&0xff;
+	pccb->cmd[5]=((unsigned char) (start))&0xff;
+	pccb->cmd[6]=0;
+	pccb->cmd[7]=((unsigned char) (blocks>>8))&0xff;
+	pccb->cmd[8]=(unsigned char) blocks & 0xff;
+	pccb->cmd[6]=0;
+	pccb->cmdlen=10;
+	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+	debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+		pccb->cmd[0],pccb->cmd[1],
+		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5],
+		pccb->cmd[7],pccb->cmd[8]);
+}
 
+void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_WRITE10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff;
+	pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff;
+	pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff;
+	pccb->cmd[5] = ((unsigned char) (start)) & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff;
+	pccb->cmd[8] = (unsigned char)blocks & 0xff;
+	pccb->cmd[9] = 0;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY;  /* NOT USED */
+	debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+	      __func__,
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[7], pccb->cmd[8]);
+}
 
-/*********************************************************************************
- * (re)-scan the scsi bus and reports scsi device info
- * to the user if mode = 1
- */
-void scsi_scan(int mode)
+void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
 {
-	unsigned char i,perq,modi,lun;
-	lbaint_t capacity;
-	unsigned long blksz;
-	ccb* pccb=(ccb *)&tempccb;
+	pccb->cmd[0]=SCSI_READ6;
+	pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
+	pccb->cmd[2]=((unsigned char) (start>>8))&0xff;
+	pccb->cmd[3]=((unsigned char) (start))&0xff;
+	pccb->cmd[4]=(unsigned char) blocks & 0xff;
+	pccb->cmd[5]=0;
+	pccb->cmdlen=6;
+	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+	debug ("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
+		pccb->cmd[0],pccb->cmd[1],
+		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4]);
+}
 
-	if(mode==1) {
-		printf("scanning bus for devices...\n");
-	}
-	for(i=0;i<CONFIG_SYS_SCSI_MAX_DEVICE;i++) {
-		scsi_dev_desc[i].target=0xff;
-		scsi_dev_desc[i].lun=0xff;
-		scsi_dev_desc[i].lba=0;
-		scsi_dev_desc[i].blksz=0;
-		scsi_dev_desc[i].log2blksz =
-			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
-		scsi_dev_desc[i].type=DEV_TYPE_UNKNOWN;
-		scsi_dev_desc[i].vendor[0]=0;
-		scsi_dev_desc[i].product[0]=0;
-		scsi_dev_desc[i].revision[0]=0;
-		scsi_dev_desc[i].removable = false;
-		scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
-		scsi_dev_desc[i].devnum = i;
-		scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
-		scsi_dev_desc[i].block_read=scsi_read;
-		scsi_dev_desc[i].block_write = scsi_write;
-	}
-	scsi_max_devs=0;
-	for(i=0;i<CONFIG_SYS_SCSI_MAX_SCSI_ID;i++) {
-		pccb->target=i;
-		for(lun=0;lun<CONFIG_SYS_SCSI_MAX_LUN;lun++) {
-			pccb->lun=lun;
-			pccb->pdata=(unsigned char *)&tempbuff;
-			pccb->datalen=512;
-			scsi_setup_inquiry(pccb);
-			if (scsi_exec(pccb) != true) {
-				if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
-					debug ("Selection timeout ID %d\n",pccb->target);
-					continue; /* selection timeout => assuming no device present */
-				}
-				scsi_print_error(pccb);
-				continue;
-			}
-			perq=tempbuff[0];
-			modi=tempbuff[1];
-			if((perq & 0x1f)==0x1f) {
-				continue; /* skip unknown devices */
-			}
-			if((modi&0x80)==0x80) /* drive is removable */
-				scsi_dev_desc[scsi_max_devs].removable=true;
-			/* get info for this device */
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
-				       &tempbuff[8], 8);
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
-				       &tempbuff[16], 16);
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
-				       &tempbuff[32], 4);
-			scsi_dev_desc[scsi_max_devs].target=pccb->target;
-			scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
 
-			pccb->datalen=0;
-			scsi_setup_test_unit_ready(pccb);
-			if (scsi_exec(pccb) != true) {
-				if (scsi_dev_desc[scsi_max_devs].removable == true) {
-					scsi_dev_desc[scsi_max_devs].type=perq;
-					goto removable;
-				}
-				scsi_print_error(pccb);
-				continue;
-			}
-			if (scsi_read_capacity(pccb, &capacity, &blksz)) {
-				scsi_print_error(pccb);
-				continue;
-			}
-			scsi_dev_desc[scsi_max_devs].lba=capacity;
-			scsi_dev_desc[scsi_max_devs].blksz=blksz;
-			scsi_dev_desc[scsi_max_devs].log2blksz =
-				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
-			scsi_dev_desc[scsi_max_devs].type=perq;
-			part_init(&scsi_dev_desc[scsi_max_devs]);
-removable:
-			if(mode==1) {
-				printf ("  Device %d: ", scsi_max_devs);
-				dev_print(&scsi_dev_desc[scsi_max_devs]);
-			} /* if mode */
-			scsi_max_devs++;
-		} /* next LUN */
-	}
-	if(scsi_max_devs>0)
-		scsi_curr_dev=0;
+void scsi_setup_inquiry(ccb * pccb)
+{
+	pccb->cmd[0]=SCSI_INQUIRY;
+	pccb->cmd[1]=pccb->lun<<5;
+	pccb->cmd[2]=0;
+	pccb->cmd[3]=0;
+	if(pccb->datalen>255)
+		pccb->cmd[4]=255;
 	else
-		scsi_curr_dev = -1;
+		pccb->cmd[4]=(unsigned char)pccb->datalen;
+	pccb->cmd[5]=0;
+	pccb->cmdlen=6;
+	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+}
 
-	printf("Found %d device(s).\n", scsi_max_devs);
-#ifndef CONFIG_SPL_BUILD
-	setenv_ulong("scsidevs", scsi_max_devs);
+static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
+		       lbaint_t blkcnt, void *buffer)
+{
+	int device = block_dev->devnum;
+	lbaint_t start, blks;
+	uintptr_t buf_addr;
+	unsigned short smallblks = 0;
+	ccb* pccb=(ccb *)&tempccb;
+	device&=0xff;
+	/* Setup  device
+	 */
+	pccb->target=scsi_dev_desc[device].target;
+	pccb->lun=scsi_dev_desc[device].lun;
+	buf_addr=(unsigned long)buffer;
+	start=blknr;
+	blks=blkcnt;
+	debug("\nscsi_read: dev %d startblk " LBAF
+	      ", blccnt " LBAF " buffer %lx\n",
+	      device, start, blks, (unsigned long)buffer);
+	do {
+		pccb->pdata=(unsigned char *)buf_addr;
+#ifdef CONFIG_SYS_64BIT_LBA
+		if (start > SCSI_LBA48_READ) {
+			unsigned long blocks;
+			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
+			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+			scsi_setup_read16(pccb, start, blocks);
+			start += blocks;
+			blks -= blocks;
+		} else
 #endif
+		if (blks > SCSI_MAX_READ_BLK) {
+			pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
+			smallblks=SCSI_MAX_READ_BLK;
+			scsi_setup_read_ext(pccb,start,smallblks);
+			start+=SCSI_MAX_READ_BLK;
+			blks-=SCSI_MAX_READ_BLK;
+		}
+		else {
+			pccb->datalen=scsi_dev_desc[device].blksz * blks;
+			smallblks=(unsigned short) blks;
+			scsi_setup_read_ext(pccb,start,smallblks);
+			start+=blks;
+			blks=0;
+		}
+		debug("scsi_read_ext: startblk " LBAF
+		      ", blccnt %x buffer %" PRIXPTR "\n",
+		      start, smallblks, buf_addr);
+		if (scsi_exec(pccb) != true) {
+			scsi_print_error(pccb);
+			blkcnt-=blks;
+			break;
+		}
+		buf_addr+=pccb->datalen;
+	} while(blks!=0);
+	debug("scsi_read_ext: end startblk " LBAF
+	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
+	return(blkcnt);
+}
+
+/*******************************************************************************
+ * scsi_write
+ */
+
+/* Almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_WRITE_BLK 0xFFFF
+
+static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
+			lbaint_t blkcnt, const void *buffer)
+{
+	int device = block_dev->devnum;
+	lbaint_t start, blks;
+	uintptr_t buf_addr;
+	unsigned short smallblks;
+	ccb* pccb = (ccb *)&tempccb;
+	device &= 0xff;
+	/* Setup  device
+	 */
+	pccb->target = scsi_dev_desc[device].target;
+	pccb->lun = scsi_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+	debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
+	      __func__, device, start, blks, (unsigned long)buffer);
+	do {
+		pccb->pdata = (unsigned char *)buf_addr;
+		if (blks > SCSI_MAX_WRITE_BLK) {
+			pccb->datalen = (scsi_dev_desc[device].blksz *
+					 SCSI_MAX_WRITE_BLK);
+			smallblks = SCSI_MAX_WRITE_BLK;
+			scsi_setup_write_ext(pccb, start, smallblks);
+			start += SCSI_MAX_WRITE_BLK;
+			blks -= SCSI_MAX_WRITE_BLK;
+		} else {
+			pccb->datalen = scsi_dev_desc[device].blksz * blks;
+			smallblks = (unsigned short)blks;
+			scsi_setup_write_ext(pccb, start, smallblks);
+			start += blks;
+			blks = 0;
+		}
+		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+		      __func__, start, smallblks, buf_addr);
+		if (scsi_exec(pccb) != true) {
+			scsi_print_error(pccb);
+			blkcnt -= blks;
+			break;
+		}
+		buf_addr += pccb->datalen;
+	} while (blks != 0);
+	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+	      __func__, start, smallblks, buf_addr);
+	return blkcnt;
 }
 
 int scsi_get_disk_count(void)
@@ -327,192 +427,69 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				printf("... is now current device\n");
 				return 0;
 			}
-			if (strncmp(argv[1],"part",4) == 0) {
-				int dev = (int)simple_strtoul(argv[2], NULL, 10);
-				if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) {
-					part_print(&scsi_dev_desc[dev]);
-				}
-				else {
-					printf ("\nSCSI device %d not available\n", dev);
-				}
-				return 1;
-			}
-			return CMD_RET_USAGE;
-    default:
-			/* at least 4 args */
-			if (strcmp(argv[1],"read") == 0) {
-				ulong addr = simple_strtoul(argv[2], NULL, 16);
-				ulong blk  = simple_strtoul(argv[3], NULL, 16);
-				ulong cnt  = simple_strtoul(argv[4], NULL, 16);
-				ulong n;
-				printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
-						scsi_curr_dev, blk, cnt);
-				n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
-					      blk, cnt, (ulong *)addr);
-				printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
-				return 0;
-			} else if (strcmp(argv[1], "write") == 0) {
-				ulong addr = simple_strtoul(argv[2], NULL, 16);
-				ulong blk = simple_strtoul(argv[3], NULL, 16);
-				ulong cnt = simple_strtoul(argv[4], NULL, 16);
-				ulong n;
-				printf("\nSCSI write: device %d block # %ld, "
-				       "count %ld ... ",
-				       scsi_curr_dev, blk, cnt);
-				n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
-					       blk, cnt, (ulong *)addr);
-				printf("%ld blocks written: %s\n", n,
-				       (n == cnt) ? "OK" : "ERROR");
-				return 0;
-			}
-	} /* switch */
-	return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
-	scsi, 5, 1, do_scsi,
-	"SCSI sub-system",
-	"reset - reset SCSI controller\n"
-	"scsi info  - show available SCSI devices\n"
-	"scsi scan  - (re-)scan SCSI bus\n"
-	"scsi device [dev] - show or set current device\n"
-	"scsi part [dev] - print partition table of one or all SCSI devices\n"
-	"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
-	"     to memory address `addr'\n"
-	"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
-	"     `blk#' from memory address `addr'"
-);
-
-U_BOOT_CMD(
-	scsiboot, 3, 1, do_scsiboot,
-	"boot from SCSI device",
-	"loadAddr dev:part"
-);
-#endif
-
-/****************************************************************************************
- * scsi_read
- */
-
-/* almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_READ_BLK 0xFFFF
-#define SCSI_LBA48_READ	0xFFFFFFF
-
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
-		       lbaint_t blkcnt, void *buffer)
-{
-	int device = block_dev->devnum;
-	lbaint_t start, blks;
-	uintptr_t buf_addr;
-	unsigned short smallblks = 0;
-	ccb* pccb=(ccb *)&tempccb;
-	device&=0xff;
-	/* Setup  device
-	 */
-	pccb->target=scsi_dev_desc[device].target;
-	pccb->lun=scsi_dev_desc[device].lun;
-	buf_addr=(unsigned long)buffer;
-	start=blknr;
-	blks=blkcnt;
-	debug("\nscsi_read: dev %d startblk " LBAF
-	      ", blccnt " LBAF " buffer %lx\n",
-	      device, start, blks, (unsigned long)buffer);
-	do {
-		pccb->pdata=(unsigned char *)buf_addr;
-#ifdef CONFIG_SYS_64BIT_LBA
-		if (start > SCSI_LBA48_READ) {
-			unsigned long blocks;
-			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
-			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
-			scsi_setup_read16(pccb, start, blocks);
-			start += blocks;
-			blks -= blocks;
-		} else
-#endif
-		if (blks > SCSI_MAX_READ_BLK) {
-			pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
-			smallblks=SCSI_MAX_READ_BLK;
-			scsi_setup_read_ext(pccb,start,smallblks);
-			start+=SCSI_MAX_READ_BLK;
-			blks-=SCSI_MAX_READ_BLK;
-		}
-		else {
-			pccb->datalen=scsi_dev_desc[device].blksz * blks;
-			smallblks=(unsigned short) blks;
-			scsi_setup_read_ext(pccb,start,smallblks);
-			start+=blks;
-			blks=0;
-		}
-		debug("scsi_read_ext: startblk " LBAF
-		      ", blccnt %x buffer %" PRIXPTR "\n",
-		      start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != true) {
-			scsi_print_error(pccb);
-			blkcnt-=blks;
-			break;
-		}
-		buf_addr+=pccb->datalen;
-	} while(blks!=0);
-	debug("scsi_read_ext: end startblk " LBAF
-	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
-	return(blkcnt);
-}
-
-/*******************************************************************************
- * scsi_write
- */
-
-/* Almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_WRITE_BLK 0xFFFF
-
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, const void *buffer)
-{
-	int device = block_dev->devnum;
-	lbaint_t start, blks;
-	uintptr_t buf_addr;
-	unsigned short smallblks;
-	ccb* pccb = (ccb *)&tempccb;
-	device &= 0xff;
-	/* Setup  device
-	 */
-	pccb->target = scsi_dev_desc[device].target;
-	pccb->lun = scsi_dev_desc[device].lun;
-	buf_addr = (unsigned long)buffer;
-	start = blknr;
-	blks = blkcnt;
-	debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
-	      __func__, device, start, blks, (unsigned long)buffer);
-	do {
-		pccb->pdata = (unsigned char *)buf_addr;
-		if (blks > SCSI_MAX_WRITE_BLK) {
-			pccb->datalen = (scsi_dev_desc[device].blksz *
-					 SCSI_MAX_WRITE_BLK);
-			smallblks = SCSI_MAX_WRITE_BLK;
-			scsi_setup_write_ext(pccb, start, smallblks);
-			start += SCSI_MAX_WRITE_BLK;
-			blks -= SCSI_MAX_WRITE_BLK;
-		} else {
-			pccb->datalen = scsi_dev_desc[device].blksz * blks;
-			smallblks = (unsigned short)blks;
-			scsi_setup_write_ext(pccb, start, smallblks);
-			start += blks;
-			blks = 0;
-		}
-		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
-		      __func__, start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != true) {
-			scsi_print_error(pccb);
-			blkcnt -= blks;
-			break;
-		}
-		buf_addr += pccb->datalen;
-	} while (blks != 0);
-	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
-	      __func__, start, smallblks, buf_addr);
-	return blkcnt;
+			if (strncmp(argv[1],"part",4) == 0) {
+				int dev = (int)simple_strtoul(argv[2], NULL, 10);
+				if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) {
+					part_print(&scsi_dev_desc[dev]);
+				}
+				else {
+					printf ("\nSCSI device %d not available\n", dev);
+				}
+				return 1;
+			}
+			return CMD_RET_USAGE;
+    default:
+			/* at least 4 args */
+			if (strcmp(argv[1],"read") == 0) {
+				ulong addr = simple_strtoul(argv[2], NULL, 16);
+				ulong blk  = simple_strtoul(argv[3], NULL, 16);
+				ulong cnt  = simple_strtoul(argv[4], NULL, 16);
+				ulong n;
+				printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
+						scsi_curr_dev, blk, cnt);
+				n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
+					      blk, cnt, (ulong *)addr);
+				printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
+				return 0;
+			} else if (strcmp(argv[1], "write") == 0) {
+				ulong addr = simple_strtoul(argv[2], NULL, 16);
+				ulong blk = simple_strtoul(argv[3], NULL, 16);
+				ulong cnt = simple_strtoul(argv[4], NULL, 16);
+				ulong n;
+				printf("\nSCSI write: device %d block # %ld, "
+				       "count %ld ... ",
+				       scsi_curr_dev, blk, cnt);
+				n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
+					       blk, cnt, (ulong *)addr);
+				printf("%ld blocks written: %s\n", n,
+				       (n == cnt) ? "OK" : "ERROR");
+				return 0;
+			}
+	} /* switch */
+	return CMD_RET_USAGE;
 }
 
+U_BOOT_CMD(
+	scsi, 5, 1, do_scsi,
+	"SCSI sub-system",
+	"reset - reset SCSI controller\n"
+	"scsi info  - show available SCSI devices\n"
+	"scsi scan  - (re-)scan SCSI bus\n"
+	"scsi device [dev] - show or set current device\n"
+	"scsi part [dev] - print partition table of one or all SCSI devices\n"
+	"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
+	"     to memory address `addr'\n"
+	"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
+	"     `blk#' from memory address `addr'"
+);
+
+U_BOOT_CMD(
+	scsiboot, 3, 1, do_scsiboot,
+	"boot from SCSI device",
+	"loadAddr dev:part"
+);
+#endif
+
 /* copy src to dest, skipping leading and trailing blanks
  * and null terminate the string
  */
@@ -630,105 +607,106 @@ void scsi_setup_test_unit_ready(ccb * pccb)
 	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
 }
 
-#ifdef CONFIG_SYS_64BIT_LBA
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
-{
-	pccb->cmd[0] = SCSI_READ16;
-	pccb->cmd[1] = pccb->lun<<5;
-	pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
-	pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
-	pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
-	pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
-	pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
-	pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
-	pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
-	pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
-	pccb->cmd[10] = 0;
-	pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
-	pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
-	pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
-	pccb->cmd[14] = (unsigned char) blocks & 0xff;
-	pccb->cmd[15] = 0;
-	pccb->cmdlen = 16;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read16: cmd: %02X %02X "
-	       "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
-	       "blccnt %02X%02X%02X%02X\n",
-		pccb->cmd[0], pccb->cmd[1],
-		pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-		pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
-		pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
-}
-#endif
-
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0]=SCSI_READ10;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=((unsigned char) (start>>24))&0xff;
-	pccb->cmd[3]=((unsigned char) (start>>16))&0xff;
-	pccb->cmd[4]=((unsigned char) (start>>8))&0xff;
-	pccb->cmd[5]=((unsigned char) (start))&0xff;
-	pccb->cmd[6]=0;
-	pccb->cmd[7]=((unsigned char) (blocks>>8))&0xff;
-	pccb->cmd[8]=(unsigned char) blocks & 0xff;
-	pccb->cmd[6]=0;
-	pccb->cmdlen=10;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
-		pccb->cmd[0],pccb->cmd[1],
-		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5],
-		pccb->cmd[7],pccb->cmd[8]);
-}
-
-void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0] = SCSI_WRITE10;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff;
-	pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff;
-	pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff;
-	pccb->cmd[5] = ((unsigned char) (start)) & 0xff;
-	pccb->cmd[6] = 0;
-	pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff;
-	pccb->cmd[8] = (unsigned char)blocks & 0xff;
-	pccb->cmd[9] = 0;
-	pccb->cmdlen = 10;
-	pccb->msgout[0] = SCSI_IDENTIFY;  /* NOT USED */
-	debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
-	      __func__,
-	      pccb->cmd[0], pccb->cmd[1],
-	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-	      pccb->cmd[7], pccb->cmd[8]);
-}
-
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
+/*********************************************************************************
+ * (re)-scan the scsi bus and reports scsi device info
+ * to the user if mode = 1
+ */
+void scsi_scan(int mode)
 {
-	pccb->cmd[0]=SCSI_READ6;
-	pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
-	pccb->cmd[2]=((unsigned char) (start>>8))&0xff;
-	pccb->cmd[3]=((unsigned char) (start))&0xff;
-	pccb->cmd[4]=(unsigned char) blocks & 0xff;
-	pccb->cmd[5]=0;
-	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
-		pccb->cmd[0],pccb->cmd[1],
-		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4]);
-}
+	unsigned char i,perq,modi,lun;
+	lbaint_t capacity;
+	unsigned long blksz;
+	ccb* pccb=(ccb *)&tempccb;
 
+	if(mode==1) {
+		printf("scanning bus for devices...\n");
+	}
+	for(i=0;i<CONFIG_SYS_SCSI_MAX_DEVICE;i++) {
+		scsi_dev_desc[i].target=0xff;
+		scsi_dev_desc[i].lun=0xff;
+		scsi_dev_desc[i].lba=0;
+		scsi_dev_desc[i].blksz=0;
+		scsi_dev_desc[i].log2blksz =
+			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
+		scsi_dev_desc[i].type=DEV_TYPE_UNKNOWN;
+		scsi_dev_desc[i].vendor[0]=0;
+		scsi_dev_desc[i].product[0]=0;
+		scsi_dev_desc[i].revision[0]=0;
+		scsi_dev_desc[i].removable = false;
+		scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
+		scsi_dev_desc[i].devnum = i;
+		scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
+		scsi_dev_desc[i].block_read=scsi_read;
+		scsi_dev_desc[i].block_write = scsi_write;
+	}
+	scsi_max_devs=0;
+	for(i=0;i<CONFIG_SYS_SCSI_MAX_SCSI_ID;i++) {
+		pccb->target=i;
+		for(lun=0;lun<CONFIG_SYS_SCSI_MAX_LUN;lun++) {
+			pccb->lun=lun;
+			pccb->pdata=(unsigned char *)&tempbuff;
+			pccb->datalen=512;
+			scsi_setup_inquiry(pccb);
+			if (scsi_exec(pccb) != true) {
+				if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
+					debug ("Selection timeout ID %d\n",pccb->target);
+					continue; /* selection timeout => assuming no device present */
+				}
+				scsi_print_error(pccb);
+				continue;
+			}
+			perq=tempbuff[0];
+			modi=tempbuff[1];
+			if((perq & 0x1f)==0x1f) {
+				continue; /* skip unknown devices */
+			}
+			if((modi&0x80)==0x80) /* drive is removable */
+				scsi_dev_desc[scsi_max_devs].removable=true;
+			/* get info for this device */
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
+				       &tempbuff[8], 8);
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
+				       &tempbuff[16], 16);
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
+				       &tempbuff[32], 4);
+			scsi_dev_desc[scsi_max_devs].target=pccb->target;
+			scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
 
-void scsi_setup_inquiry(ccb * pccb)
-{
-	pccb->cmd[0]=SCSI_INQUIRY;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=0;
-	pccb->cmd[3]=0;
-	if(pccb->datalen>255)
-		pccb->cmd[4]=255;
+			pccb->datalen=0;
+			scsi_setup_test_unit_ready(pccb);
+			if (scsi_exec(pccb) != true) {
+				if (scsi_dev_desc[scsi_max_devs].removable == true) {
+					scsi_dev_desc[scsi_max_devs].type=perq;
+					goto removable;
+				}
+				scsi_print_error(pccb);
+				continue;
+			}
+			if (scsi_read_capacity(pccb, &capacity, &blksz)) {
+				scsi_print_error(pccb);
+				continue;
+			}
+			scsi_dev_desc[scsi_max_devs].lba=capacity;
+			scsi_dev_desc[scsi_max_devs].blksz=blksz;
+			scsi_dev_desc[scsi_max_devs].log2blksz =
+				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
+			scsi_dev_desc[scsi_max_devs].type=perq;
+			part_init(&scsi_dev_desc[scsi_max_devs]);
+removable:
+			if(mode==1) {
+				printf ("  Device %d: ", scsi_max_devs);
+				dev_print(&scsi_dev_desc[scsi_max_devs]);
+			} /* if mode */
+			scsi_max_devs++;
+		} /* next LUN */
+	}
+	if(scsi_max_devs>0)
+		scsi_curr_dev=0;
 	else
-		pccb->cmd[4]=(unsigned char)pccb->datalen;
-	pccb->cmd[5]=0;
-	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+		scsi_curr_dev = -1;
+
+	printf("Found %d device(s).\n", scsi_max_devs);
+#ifndef CONFIG_SPL_BUILD
+	setenv_ulong("scsidevs", scsi_max_devs);
+#endif
 }
-- 
cgit v0.10.2


From f1d4d9379e1f83118307012a3edcc4ea20e12d92 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:58 -0600
Subject: dm: scsi: Fix up code style

Update the code style of this file so that it passes checkpatch.pl.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/scsi.c b/cmd/scsi.c
index 9ba070f..751fc58 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -50,59 +50,53 @@ static int scsi_curr_dev; /* current device */
 
 static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
 
-/****************************************************************************************
- * scsi_read
- */
-
 /* almost the maximum amount of the scsi_ext command.. */
 #define SCSI_MAX_READ_BLK 0xFFFF
 #define SCSI_LBA48_READ	0xFFFFFFF
 
 #ifdef CONFIG_SYS_64BIT_LBA
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
+void scsi_setup_read16(ccb *pccb, lbaint_t start, unsigned long blocks)
 {
 	pccb->cmd[0] = SCSI_READ16;
-	pccb->cmd[1] = pccb->lun<<5;
-	pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
-	pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
-	pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
-	pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
-	pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
-	pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
-	pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
-	pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff;
+	pccb->cmd[5] = (unsigned char)(start >> 32) & 0xff;
+	pccb->cmd[6] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[7] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[8] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[9] = (unsigned char)start & 0xff;
 	pccb->cmd[10] = 0;
-	pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
-	pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
-	pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
-	pccb->cmd[14] = (unsigned char) blocks & 0xff;
+	pccb->cmd[11] = (unsigned char)(blocks >> 24) & 0xff;
+	pccb->cmd[12] = (unsigned char)(blocks >> 16) & 0xff;
+	pccb->cmd[13] = (unsigned char)(blocks >> 8) & 0xff;
+	pccb->cmd[14] = (unsigned char)blocks & 0xff;
 	pccb->cmd[15] = 0;
 	pccb->cmdlen = 16;
 	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read16: cmd: %02X %02X "
-	       "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
-	       "blccnt %02X%02X%02X%02X\n",
-		pccb->cmd[0], pccb->cmd[1],
-		pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-		pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
-		pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+	debug("scsi_setup_read16: cmd: %02X %02X startblk %02X%02X%02X%02X%02X%02X%02X%02X blccnt %02X%02X%02X%02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+	      pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
 }
 #endif
 
 void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
 {
-	pccb->cmd[0]=SCSI_READ10;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=((unsigned char) (start>>24))&0xff;
-	pccb->cmd[3]=((unsigned char) (start>>16))&0xff;
-	pccb->cmd[4]=((unsigned char) (start>>8))&0xff;
-	pccb->cmd[5]=((unsigned char) (start))&0xff;
-	pccb->cmd[6]=0;
-	pccb->cmd[7]=((unsigned char) (blocks>>8))&0xff;
-	pccb->cmd[8]=(unsigned char) blocks & 0xff;
-	pccb->cmd[6]=0;
+	pccb->cmd[0] = SCSI_READ10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[5] = (unsigned char)start & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
+	pccb->cmd[8] = (unsigned char)blocks & 0xff;
+	pccb->cmd[6] = 0;
 	pccb->cmdlen=10;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
 	debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
 		pccb->cmd[0],pccb->cmd[1],
 		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5],
@@ -113,12 +107,12 @@ void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
 {
 	pccb->cmd[0] = SCSI_WRITE10;
 	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff;
-	pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff;
-	pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff;
-	pccb->cmd[5] = ((unsigned char) (start)) & 0xff;
+	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[5] = (unsigned char)start & 0xff;
 	pccb->cmd[6] = 0;
-	pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff;
+	pccb->cmd[7] = ((unsigned char)(blocks >> 8)) & 0xff;
 	pccb->cmd[8] = (unsigned char)blocks & 0xff;
 	pccb->cmd[9] = 0;
 	pccb->cmdlen = 10;
@@ -132,33 +126,33 @@ void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
 
 void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
 {
-	pccb->cmd[0]=SCSI_READ6;
-	pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
-	pccb->cmd[2]=((unsigned char) (start>>8))&0xff;
-	pccb->cmd[3]=((unsigned char) (start))&0xff;
-	pccb->cmd[4]=(unsigned char) blocks & 0xff;
-	pccb->cmd[5]=0;
+	pccb->cmd[0] = SCSI_READ6;
+	pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
+	pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[3] = (unsigned char)start & 0xff;
+	pccb->cmd[4] = (unsigned char)blocks & 0xff;
+	pccb->cmd[5] = 0;
 	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
-		pccb->cmd[0],pccb->cmd[1],
-		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4]);
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
 }
 
 
 void scsi_setup_inquiry(ccb * pccb)
 {
-	pccb->cmd[0]=SCSI_INQUIRY;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=0;
-	pccb->cmd[3]=0;
-	if(pccb->datalen>255)
-		pccb->cmd[4]=255;
+	pccb->cmd[0] = SCSI_INQUIRY;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = 0;
+	pccb->cmd[3] = 0;
+	if (pccb->datalen > 255)
+		pccb->cmd[4] = 255;
 	else
-		pccb->cmd[4]=(unsigned char)pccb->datalen;
-	pccb->cmd[5]=0;
+		pccb->cmd[4] = (unsigned char)pccb->datalen;
+	pccb->cmd[5] = 0;
 	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
 }
 
 static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
@@ -170,18 +164,18 @@ static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 	unsigned short smallblks = 0;
 	ccb* pccb=(ccb *)&tempccb;
 	device&=0xff;
-	/* Setup  device
-	 */
-	pccb->target=scsi_dev_desc[device].target;
-	pccb->lun=scsi_dev_desc[device].lun;
-	buf_addr=(unsigned long)buffer;
-	start=blknr;
-	blks=blkcnt;
+
+	/* Setup device */
+	pccb->target = scsi_dev_desc[device].target;
+	pccb->lun = scsi_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
 	debug("\nscsi_read: dev %d startblk " LBAF
 	      ", blccnt " LBAF " buffer %lx\n",
 	      device, start, blks, (unsigned long)buffer);
 	do {
-		pccb->pdata=(unsigned char *)buf_addr;
+		pccb->pdata = (unsigned char *)buf_addr;
 #ifdef CONFIG_SYS_64BIT_LBA
 		if (start > SCSI_LBA48_READ) {
 			unsigned long blocks;
@@ -193,17 +187,18 @@ static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 		} else
 #endif
 		if (blks > SCSI_MAX_READ_BLK) {
-			pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
-			smallblks=SCSI_MAX_READ_BLK;
-			scsi_setup_read_ext(pccb,start,smallblks);
-			start+=SCSI_MAX_READ_BLK;
-			blks-=SCSI_MAX_READ_BLK;
+			pccb->datalen = scsi_dev_desc[device].blksz *
+				SCSI_MAX_READ_BLK;
+			smallblks = SCSI_MAX_READ_BLK;
+			scsi_setup_read_ext(pccb, start, smallblks);
+			start += SCSI_MAX_READ_BLK;
+			blks -= SCSI_MAX_READ_BLK;
 		}
 		else {
-			pccb->datalen=scsi_dev_desc[device].blksz * blks;
-			smallblks=(unsigned short) blks;
-			scsi_setup_read_ext(pccb,start,smallblks);
-			start+=blks;
+			pccb->datalen = scsi_dev_desc[device].blksz * blks;
+			smallblks = (unsigned short)blks;
+			scsi_setup_read_ext(pccb, start, smallblks);
+			start += blks;
 			blks=0;
 		}
 		debug("scsi_read_ext: startblk " LBAF
@@ -211,14 +206,14 @@ static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 		      start, smallblks, buf_addr);
 		if (scsi_exec(pccb) != true) {
 			scsi_print_error(pccb);
-			blkcnt-=blks;
+			blkcnt -= blks;
 			break;
 		}
 		buf_addr+=pccb->datalen;
-	} while(blks!=0);
+	} while (blks != 0);
 	debug("scsi_read_ext: end startblk " LBAF
 	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
-	return(blkcnt);
+	return blkcnt;
 }
 
 /*******************************************************************************
@@ -365,106 +360,106 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return CMD_RET_USAGE;
 
 	case 2:
-			if (strncmp(argv[1],"res",3) == 0) {
-				printf("\nReset SCSI\n");
-				scsi_bus_reset();
-				scsi_scan(1);
-				return 0;
-			}
-			if (strncmp(argv[1],"inf",3) == 0) {
-				int i;
-				for (i=0; i<CONFIG_SYS_SCSI_MAX_DEVICE; ++i) {
-					if(scsi_dev_desc[i].type==DEV_TYPE_UNKNOWN)
-						continue; /* list only known devices */
-					printf ("SCSI dev. %d:  ", i);
-					dev_print(&scsi_dev_desc[i]);
-				}
-				return 0;
-			}
-			if (strncmp(argv[1],"dev",3) == 0) {
-				if ((scsi_curr_dev < 0) || (scsi_curr_dev >= CONFIG_SYS_SCSI_MAX_DEVICE)) {
-					printf("\nno SCSI devices available\n");
-					return 1;
-				}
-				printf ("\n    Device %d: ", scsi_curr_dev);
-				dev_print(&scsi_dev_desc[scsi_curr_dev]);
-				return 0;
-			}
-			if (strncmp(argv[1],"scan",4) == 0) {
-				scsi_scan(1);
-				return 0;
+		if (strncmp(argv[1], "res", 3) == 0) {
+			printf("\nReset SCSI\n");
+			scsi_bus_reset();
+			scsi_scan(1);
+			return 0;
+		}
+		if (strncmp(argv[1], "inf", 3) == 0) {
+			int i;
+			for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; ++i) {
+				if (scsi_dev_desc[i].type == DEV_TYPE_UNKNOWN)
+					continue; /* list only known devices */
+				printf("SCSI dev. %d:  ", i);
+				dev_print(&scsi_dev_desc[i]);
 			}
-			if (strncmp(argv[1],"part",4) == 0) {
-				int dev, ok;
-				for (ok=0, dev=0; dev<CONFIG_SYS_SCSI_MAX_DEVICE; ++dev) {
-					if (scsi_dev_desc[dev].type!=DEV_TYPE_UNKNOWN) {
-						ok++;
-						if (dev)
-							printf("\n");
-						debug ("print_part of %x\n",dev);
-						part_print(&scsi_dev_desc[dev]);
-					}
-				}
-				if (!ok)
-					printf("\nno SCSI devices available\n");
+			return 0;
+		}
+		if (strncmp(argv[1], "dev", 3) == 0) {
+			if (scsi_curr_dev < 0 ||
+			    scsi_curr_dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
+				printf("\nno SCSI devices available\n");
 				return 1;
 			}
-			return CMD_RET_USAGE;
-	case 3:
-			if (strncmp(argv[1],"dev",3) == 0) {
-				int dev = (int)simple_strtoul(argv[2], NULL, 10);
-				printf ("\nSCSI device %d: ", dev);
-				if (dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
-					printf("unknown device\n");
-					return 1;
-				}
-				printf ("\n    Device %d: ", dev);
-				dev_print(&scsi_dev_desc[dev]);
-				if(scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN) {
-					return 1;
-				}
-				scsi_curr_dev = dev;
-				printf("... is now current device\n");
-				return 0;
-			}
-			if (strncmp(argv[1],"part",4) == 0) {
-				int dev = (int)simple_strtoul(argv[2], NULL, 10);
-				if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) {
+			printf("\n    Device %d: ", scsi_curr_dev);
+			dev_print(&scsi_dev_desc[scsi_curr_dev]);
+			return 0;
+		}
+		if (strncmp(argv[1], "scan", 4) == 0) {
+			scsi_scan(1);
+			return 0;
+		}
+		if (strncmp(argv[1], "part", 4) == 0) {
+			int dev, ok;
+			for (ok = 0, dev = 0;
+			     dev < CONFIG_SYS_SCSI_MAX_DEVICE; ++dev) {
+				if (scsi_dev_desc[dev].type !=
+				    DEV_TYPE_UNKNOWN) {
+					ok++;
+					if (dev)
+						printf("\n");
+					debug("print_part of %x\n", dev);
 					part_print(&scsi_dev_desc[dev]);
 				}
-				else {
-					printf ("\nSCSI device %d not available\n", dev);
-				}
-				return 1;
 			}
-			return CMD_RET_USAGE;
-    default:
-			/* at least 4 args */
-			if (strcmp(argv[1],"read") == 0) {
-				ulong addr = simple_strtoul(argv[2], NULL, 16);
-				ulong blk  = simple_strtoul(argv[3], NULL, 16);
-				ulong cnt  = simple_strtoul(argv[4], NULL, 16);
-				ulong n;
-				printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
-						scsi_curr_dev, blk, cnt);
-				n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
-					      blk, cnt, (ulong *)addr);
-				printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
-				return 0;
-			} else if (strcmp(argv[1], "write") == 0) {
-				ulong addr = simple_strtoul(argv[2], NULL, 16);
-				ulong blk = simple_strtoul(argv[3], NULL, 16);
-				ulong cnt = simple_strtoul(argv[4], NULL, 16);
-				ulong n;
-				printf("\nSCSI write: device %d block # %ld, "
-				       "count %ld ... ",
-				       scsi_curr_dev, blk, cnt);
-				n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
-					       blk, cnt, (ulong *)addr);
-				printf("%ld blocks written: %s\n", n,
-				       (n == cnt) ? "OK" : "ERROR");
-				return 0;
+			if (!ok)
+				printf("\nno SCSI devices available\n");
+			return 1;
+		}
+		return CMD_RET_USAGE;
+	case 3:
+		if (strncmp(argv[1], "dev", 3) == 0) {
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
+			printf("\nSCSI device %d: ", dev);
+			if (dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
+				printf("unknown device\n");
+				return 1;
 			}
+			printf("\n    Device %d: ", dev);
+			dev_print(&scsi_dev_desc[dev]);
+			if (scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
+				return 1;
+			scsi_curr_dev = dev;
+			printf("... is now current device\n");
+			return 0;
+		}
+		if (strncmp(argv[1], "part", 4) == 0) {
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
+			if (scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN)
+				part_print(&scsi_dev_desc[dev]);
+			else
+				printf("\nSCSI device %d not available\n", dev);
+			return 1;
+		}
+		return CMD_RET_USAGE;
+	default:
+		/* at least 4 args */
+		if (strcmp(argv[1], "read") == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong blk  = simple_strtoul(argv[3], NULL, 16);
+			ulong cnt  = simple_strtoul(argv[4], NULL, 16);
+			ulong n;
+			printf("\nSCSI read: device %d block # %ld, count %ld ... ",
+			       scsi_curr_dev, blk, cnt);
+			n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
+				      blk, cnt, (ulong *)addr);
+			printf("%ld blocks read: %s\n", n,
+			       n == cnt ? "OK" : "ERROR");
+			return 0;
+		} else if (strcmp(argv[1], "write") == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong blk = simple_strtoul(argv[3], NULL, 16);
+			ulong cnt = simple_strtoul(argv[4], NULL, 16);
+			ulong n;
+			printf("\nSCSI write: device %d block # %ld, count %ld ... ",
+			       scsi_curr_dev, blk, cnt);
+			n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
+				       blk, cnt, (ulong *)addr);
+			printf("%ld blocks written: %s\n", n,
+			       n == cnt ? "OK" : "ERROR");
+			return 0;
+		}
 	} /* switch */
 	return CMD_RET_USAGE;
 }
@@ -493,25 +488,24 @@ U_BOOT_CMD(
 /* copy src to dest, skipping leading and trailing blanks
  * and null terminate the string
  */
-void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len)
+void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
 {
 	int start,end;
 
-	start=0;
-	while(start<len) {
-		if(src[start]!=' ')
+	start = 0;
+	while (start < len) {
+		if (src[start] != ' ')
 			break;
 		start++;
 	}
-	end=len-1;
-	while(end>start) {
-		if(src[end]!=' ')
+	end = len-1;
+	while (end > start) {
+		if (src[end] != ' ')
 			break;
 		end--;
 	}
-	for( ; start<=end; start++) {
-		*dest++=src[start];
-	}
+	for (; start <= end; start++)
+		*dest ++= src[start];
 	*dest='\0';
 }
 
@@ -534,7 +528,7 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
 {
 	*capacity = 0;
 
-	memset(pccb->cmd, 0, sizeof(pccb->cmd));
+	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
 	pccb->cmd[0] = SCSI_RD_CAPAC10;
 	pccb->cmd[1] = pccb->lun << 5;
 	pccb->cmdlen = 10;
@@ -559,8 +553,7 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
 	}
 
 	/* Read capacity (10) was insufficient. Use read capacity (16). */
-
-	memset(pccb->cmd, 0, sizeof(pccb->cmd));
+	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
 	pccb->cmd[0] = SCSI_RD_CAPAC16;
 	pccb->cmd[1] = 0x10;
 	pccb->cmdlen = 16;
@@ -597,14 +590,14 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
  */
 void scsi_setup_test_unit_ready(ccb * pccb)
 {
-	pccb->cmd[0]=SCSI_TST_U_RDY;
-	pccb->cmd[1]=pccb->lun<<5;
-	pccb->cmd[2]=0;
-	pccb->cmd[3]=0;
-	pccb->cmd[4]=0;
-	pccb->cmd[5]=0;
-	pccb->cmdlen=6;
-	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
+	pccb->cmd[0] = SCSI_TST_U_RDY;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = 0;
+	pccb->cmd[3] = 0;
+	pccb->cmd[4] = 0;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
 }
 
 /*********************************************************************************
@@ -618,50 +611,49 @@ void scsi_scan(int mode)
 	unsigned long blksz;
 	ccb* pccb=(ccb *)&tempccb;
 
-	if(mode==1) {
+	if (mode == 1)
 		printf("scanning bus for devices...\n");
-	}
-	for(i=0;i<CONFIG_SYS_SCSI_MAX_DEVICE;i++) {
-		scsi_dev_desc[i].target=0xff;
-		scsi_dev_desc[i].lun=0xff;
-		scsi_dev_desc[i].lba=0;
-		scsi_dev_desc[i].blksz=0;
-		scsi_dev_desc[i].log2blksz =
+	for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
+		scsi_dev_desc[i].target = 0xff;
+		scsi_dev_desc[i].lun = 0xff;
+		scsi_dev_desc[i].lba = 0;
+		scsi_dev_desc[i].blksz = 0;
+		scsi_dev_desc[i].log2blksz  =
 			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
-		scsi_dev_desc[i].type=DEV_TYPE_UNKNOWN;
-		scsi_dev_desc[i].vendor[0]=0;
-		scsi_dev_desc[i].product[0]=0;
-		scsi_dev_desc[i].revision[0]=0;
+		scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		scsi_dev_desc[i].vendor[0] = 0;
+		scsi_dev_desc[i].product[0] = 0;
+		scsi_dev_desc[i].revision[0] = 0;
 		scsi_dev_desc[i].removable = false;
-		scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
+		scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
 		scsi_dev_desc[i].devnum = i;
-		scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
-		scsi_dev_desc[i].block_read=scsi_read;
+		scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		scsi_dev_desc[i].block_read = scsi_read;
 		scsi_dev_desc[i].block_write = scsi_write;
 	}
-	scsi_max_devs=0;
-	for(i=0;i<CONFIG_SYS_SCSI_MAX_SCSI_ID;i++) {
-		pccb->target=i;
-		for(lun=0;lun<CONFIG_SYS_SCSI_MAX_LUN;lun++) {
-			pccb->lun=lun;
-			pccb->pdata=(unsigned char *)&tempbuff;
-			pccb->datalen=512;
+	scsi_max_devs = 0;
+	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+		pccb->target = i;
+		for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
+			pccb->lun = lun;
+			pccb->pdata = (unsigned char *)&tempbuff;
+			pccb->datalen = 512;
 			scsi_setup_inquiry(pccb);
 			if (scsi_exec(pccb) != true) {
 				if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
-					debug ("Selection timeout ID %d\n",pccb->target);
+					debug("Selection timeout ID %d\n",
+					      pccb->target);
 					continue; /* selection timeout => assuming no device present */
 				}
 				scsi_print_error(pccb);
 				continue;
 			}
-			perq=tempbuff[0];
-			modi=tempbuff[1];
-			if((perq & 0x1f)==0x1f) {
+			perq = tempbuff[0];
+			modi = tempbuff[1];
+			if ((perq & 0x1f) == 0x1f)
 				continue; /* skip unknown devices */
-			}
-			if((modi&0x80)==0x80) /* drive is removable */
-				scsi_dev_desc[scsi_max_devs].removable=true;
+			if ((modi & 0x80) == 0x80) /* drive is removable */
+				scsi_dev_desc[scsi_max_devs].removable = true;
 			/* get info for this device */
 			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
 				       &tempbuff[8], 8);
@@ -669,14 +661,15 @@ void scsi_scan(int mode)
 				       &tempbuff[16], 16);
 			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
 				       &tempbuff[32], 4);
-			scsi_dev_desc[scsi_max_devs].target=pccb->target;
-			scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
+			scsi_dev_desc[scsi_max_devs].target = pccb->target;
+			scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
 
-			pccb->datalen=0;
+			pccb->datalen = 0;
 			scsi_setup_test_unit_ready(pccb);
 			if (scsi_exec(pccb) != true) {
-				if (scsi_dev_desc[scsi_max_devs].removable == true) {
-					scsi_dev_desc[scsi_max_devs].type=perq;
+				if (scsi_dev_desc[scsi_max_devs].removable) {
+					scsi_dev_desc[scsi_max_devs].type =
+							perq;
 					goto removable;
 				}
 				scsi_print_error(pccb);
@@ -686,11 +679,11 @@ void scsi_scan(int mode)
 				scsi_print_error(pccb);
 				continue;
 			}
-			scsi_dev_desc[scsi_max_devs].lba=capacity;
-			scsi_dev_desc[scsi_max_devs].blksz=blksz;
+			scsi_dev_desc[scsi_max_devs].lba = capacity;
+			scsi_dev_desc[scsi_max_devs].blksz = blksz;
 			scsi_dev_desc[scsi_max_devs].log2blksz =
 				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
-			scsi_dev_desc[scsi_max_devs].type=perq;
+			scsi_dev_desc[scsi_max_devs].type = perq;
 			part_init(&scsi_dev_desc[scsi_max_devs]);
 removable:
 			if(mode==1) {
@@ -700,8 +693,8 @@ removable:
 			scsi_max_devs++;
 		} /* next LUN */
 	}
-	if(scsi_max_devs>0)
-		scsi_curr_dev=0;
+	if (scsi_max_devs > 0)
+		scsi_curr_dev = 0;
 	else
 		scsi_curr_dev = -1;
 
-- 
cgit v0.10.2


From 53dbcdd0cd4b90077b0b3893bcf25354ed825cec Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:35:59 -0600
Subject: dm: ide: Correct various code style problems

Adjust common/ide.c so that it passes most checkpatch.pl checks.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/ide.c b/cmd/ide.c
index c4c08c8..a46d0ac 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -58,13 +58,13 @@ struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_IDE_RESET
-static void  ide_reset (void);
+static void  ide_reset(void);
 #else
 #define ide_reset()	/* dummy */
 #endif
 
 static void ide_ident(struct blk_desc *dev_desc);
-static uchar ide_wait  (int dev, ulong t);
+static uchar ide_wait(int dev, ulong t);
 
 #define IDE_TIME_OUT	2000	/* 2 sec timeout */
 
@@ -72,14 +72,15 @@ static uchar ide_wait  (int dev, ulong t);
 
 #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
 
-static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
+static void ident_cpy(unsigned char *dest, unsigned char *src,
+		      unsigned int len);
 
 #ifndef CONFIG_SYS_ATA_PORT_ADDR
 #define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
 #endif
 
 #ifdef CONFIG_ATAPI
-static void	atapi_inquiry(struct blk_desc *dev_desc);
+static void atapi_inquiry(struct blk_desc *dev_desc);
 static ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr,
 			lbaint_t blkcnt, void *buffer);
 #endif
@@ -150,7 +151,7 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 		return CMD_RET_USAGE;
 	case 3:
 		if (strncmp(argv[1], "dev", 3) == 0) {
-			int dev = (int) simple_strtoul(argv[2], NULL, 10);
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
 			printf("\nIDE device %d: ", dev);
 			if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
@@ -169,7 +170,7 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev = (int) simple_strtoul(argv[2], NULL, 10);
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
 			if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
 				part_print(&ide_dev_desc[dev]);
@@ -194,13 +195,13 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 #ifdef CONFIG_SYS_64BIT_LBA
 			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
 
-			printf("\nIDE read: device %d block # %lld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE read: device %d block # %lld, count %ld...",
+			       curr_device, blk, cnt);
 #else
 			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
 
-			printf("\nIDE read: device %d block # %ld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE read: device %d block # %ld, count %ld...",
+			       curr_device, blk, cnt);
 #endif
 
 			dev_desc = &ide_dev_desc[curr_device];
@@ -223,13 +224,13 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 #ifdef CONFIG_SYS_64BIT_LBA
 			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
 
-			printf("\nIDE write: device %d block # %lld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE write: device %d block # %lld, count %ld...",
+			       curr_device, blk, cnt);
 #else
 			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
 
-			printf("\nIDE write: device %d block # %ld, count %ld ... ",
-				curr_device, blk, cnt);
+			printf("\nIDE write: device %d block # %ld, count %ld...",
+			       curr_device, blk, cnt);
 #endif
 			n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
 				      (ulong *)addr);
@@ -833,7 +834,7 @@ ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	}
 IDE_READ_E:
 	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return (n);
+	return n;
 }
 
 /* ------------------------------------------------------------------------- */
@@ -922,7 +923,7 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	}
 WR_OUT:
 	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return (n);
+	return n;
 }
 
 /* ------------------------------------------------------------------------- */
@@ -974,7 +975,7 @@ static uchar ide_wait(int dev, ulong t)
 		if (delay-- == 0)
 			break;
 	}
-	return (c);
+	return c;
 }
 
 /* ------------------------------------------------------------------------- */
@@ -1098,7 +1099,7 @@ static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
 		if (delay-- == 0)
 			break;
 	}
-	return (c);
+	return c;
 }
 
 /*
@@ -1142,7 +1143,7 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
 
 	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
 		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
-			device, c);
+		       device, c);
 		err = 0xFF;
 		goto AI_OUT;
 	}
@@ -1166,10 +1167,10 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
 		if (c & ATA_STAT_ERR) {
 			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
 			debug("atapi_issue 1 returned sense key %X status %02X\n",
-				err, c);
+			      err, c);
 		} else {
 			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
-				ccb[0], c);
+			       ccb[0], c);
 			err = 0xFF;
 		}
 		goto AI_OUT;
@@ -1190,7 +1191,7 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
 	}
 	if (n != buflen) {
 		debug("WARNING, transfer bytes %d not equal with requested %d\n",
-			n, buflen);
+		      n, buflen);
 	}
 	if (n != 0) {		/* data transfer */
 		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
@@ -1220,7 +1221,7 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
 	}
 AI_OUT:
 	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return (err);
+	return err;
 }
 
 /*
@@ -1297,7 +1298,7 @@ retry:
 	       ascq);
 error:
 	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
-	return (0xFF);
+	return 0xFF;
 }
 
 
@@ -1402,8 +1403,8 @@ ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	unsigned char ccb[12];	/* Command descriptor block */
 	ulong cnt;
 
-	debug("atapi_read dev %d start " LBAF " blocks " LBAF " buffer at %lX\n",
-	      device, blknr, blkcnt, (ulong) buffer);
+	debug("atapi_read dev %d start " LBAF " blocks " LBAF
+	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
 
 	do {
 		if (blkcnt > ATAPI_READ_MAX_BLOCK)
@@ -1428,14 +1429,14 @@ ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 					(unsigned char *) buffer,
 					cnt * ATAPI_READ_BLOCK_SIZE)
 		    == 0xFF) {
-			return (n);
+			return n;
 		}
 		n += cnt;
 		blkcnt -= cnt;
 		blknr += cnt;
 		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
 	} while (blkcnt > 0);
-	return (n);
+	return n;
 }
 
 /* ------------------------------------------------------------------------- */
-- 
cgit v0.10.2


From ed73508dec40afee7c90048fac510796bf91314d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:00 -0600
Subject: dm: ide: Remove the forward declarations

Reorder the code to avoid needing forward declarations. Fix up code style
as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/ide.c b/cmd/ide.c
index a46d0ac..db26f43 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -57,491 +57,518 @@ static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
 struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
 /* ------------------------------------------------------------------------- */
 
-#ifdef CONFIG_IDE_RESET
-static void  ide_reset(void);
-#else
-#define ide_reset()	/* dummy */
-#endif
-
-static void ide_ident(struct blk_desc *dev_desc);
-static uchar ide_wait(int dev, ulong t);
-
 #define IDE_TIME_OUT	2000	/* 2 sec timeout */
 
 #define ATAPI_TIME_OUT	7000	/* 7 sec timeout (5 sec seems to work...) */
 
 #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
 
-static void ident_cpy(unsigned char *dest, unsigned char *src,
-		      unsigned int len);
-
 #ifndef CONFIG_SYS_ATA_PORT_ADDR
 #define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
 #endif
 
-#ifdef CONFIG_ATAPI
-static void atapi_inquiry(struct blk_desc *dev_desc);
-static ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, void *buffer);
+#ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
 #endif
 
+#ifdef CONFIG_IDE_RESET
+extern void ide_set_reset(int idereset);
 
-/* ------------------------------------------------------------------------- */
-
-int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static void ide_reset(void)
 {
-	int rcode = 0;
-
-	switch (argc) {
-	case 0:
-	case 1:
-		return CMD_RET_USAGE;
-	case 2:
-		if (strncmp(argv[1], "res", 3) == 0) {
-			puts("\nReset IDE"
-#ifdef CONFIG_IDE_8xx_DIRECT
-			     " on PCMCIA " PCMCIA_SLOT_MSG
-#endif
-			     ": ");
-
-			ide_init();
-			return 0;
-		} else if (strncmp(argv[1], "inf", 3) == 0) {
-			int i;
+	int i;
 
-			putc('\n');
+	curr_device = -1;
+	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
+		ide_bus_ok[i] = 0;
+	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
+		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
 
-			for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-				if (ide_dev_desc[i].type == DEV_TYPE_UNKNOWN)
-					continue;  /* list only known devices */
-				printf("IDE device %d: ", i);
-				dev_print(&ide_dev_desc[i]);
-			}
-			return 0;
+	ide_set_reset(1);	/* assert reset */
 
-		} else if (strncmp(argv[1], "dev", 3) == 0) {
-			if ((curr_device < 0)
-			    || (curr_device >= CONFIG_SYS_IDE_MAXDEVICE)) {
-				puts("\nno IDE devices available\n");
-				return 1;
-			}
-			printf("\nIDE device %d: ", curr_device);
-			dev_print(&ide_dev_desc[curr_device]);
-			return 0;
-		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev, ok;
+	/* the reset signal shall be asserted for et least 25 us */
+	udelay(25);
 
-			for (ok = 0, dev = 0;
-			     dev < CONFIG_SYS_IDE_MAXDEVICE;
-			     ++dev) {
-				if (ide_dev_desc[dev].part_type !=
-				    PART_TYPE_UNKNOWN) {
-					++ok;
-					if (dev)
-						putc('\n');
-					part_print(&ide_dev_desc[dev]);
-				}
-			}
-			if (!ok) {
-				puts("\nno IDE devices available\n");
-				rcode++;
-			}
-			return rcode;
-		}
-		return CMD_RET_USAGE;
-	case 3:
-		if (strncmp(argv[1], "dev", 3) == 0) {
-			int dev = (int)simple_strtoul(argv[2], NULL, 10);
+	WATCHDOG_RESET();
 
-			printf("\nIDE device %d: ", dev);
-			if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
-				puts("unknown device\n");
-				return 1;
-			}
-			dev_print(&ide_dev_desc[dev]);
-			/*ide_print (dev); */
+	/* de-assert RESET signal */
+	ide_set_reset(0);
 
-			if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
-				return 1;
+	/* wait 250 ms */
+	for (i = 0; i < 250; ++i)
+		udelay(1000);
+}
+#else
+#define ide_reset()	/* dummy */
+#endif /* CONFIG_IDE_RESET */
 
-			curr_device = dev;
+/*
+ * Wait until Busy bit is off, or timeout (in ms)
+ * Return last status
+ */
+static uchar ide_wait(int dev, ulong t)
+{
+	ulong delay = 10 * t;	/* poll every 100 us */
+	uchar c;
 
-			puts("... is now current device\n");
+	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
+		udelay(100);
+		if (delay-- == 0)
+			break;
+	}
+	return c;
+}
 
-			return 0;
-		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev = (int)simple_strtoul(argv[2], NULL, 10);
+/*
+ * copy src to dest, skipping leading and trailing blanks and null
+ * terminate the string
+ * "len" is the size of available memory including the terminating '\0'
+ */
+static void ident_cpy(unsigned char *dst, unsigned char *src,
+		      unsigned int len)
+{
+	unsigned char *end, *last;
 
-			if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				part_print(&ide_dev_desc[dev]);
-			} else {
-				printf("\nIDE device %d not available\n",
-				       dev);
-				rcode = 1;
-			}
-			return rcode;
-		}
+	last = dst;
+	end = src + len - 1;
 
-		return CMD_RET_USAGE;
-	default:
-		/* at least 4 args */
+	/* reserve space for '\0' */
+	if (len < 2)
+		goto OUT;
 
-		if (strcmp(argv[1], "read") == 0) {
-			ulong addr = simple_strtoul(argv[2], NULL, 16);
-			ulong cnt = simple_strtoul(argv[4], NULL, 16);
-			struct blk_desc *dev_desc;
-			ulong n;
+	/* skip leading white space */
+	while ((*src) && (src < end) && (*src == ' '))
+		++src;
 
-#ifdef CONFIG_SYS_64BIT_LBA
-			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
+	/* copy string, omitting trailing white space */
+	while ((*src) && (src < end)) {
+		*dst++ = *src;
+		if (*src++ != ' ')
+			last = dst;
+	}
+OUT:
+	*last = '\0';
+}
 
-			printf("\nIDE read: device %d block # %lld, count %ld...",
-			       curr_device, blk, cnt);
-#else
-			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
+#ifdef CONFIG_ATAPI
+/****************************************************************************
+ * ATAPI Support
+ */
 
-			printf("\nIDE read: device %d block # %ld, count %ld...",
-			       curr_device, blk, cnt);
-#endif
+#if defined(CONFIG_IDE_SWAP_IO)
+/* since ATAPI may use commands with not 4 bytes alligned length
+ * we have our own transfer functions, 2 bytes alligned */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
 
-			dev_desc = &ide_dev_desc[curr_device];
-			n = blk_dread(dev_desc, blk, cnt, (ulong *)addr);
-			/* flush cache after read */
-			flush_cache(addr,
-				    cnt * ide_dev_desc[curr_device].blksz);
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
 
-			printf("%ld blocks read: %s\n",
-			       n, (n == cnt) ? "OK" : "ERROR");
-			if (n == cnt)
-				return 0;
-			else
-				return 1;
-		} else if (strcmp(argv[1], "write") == 0) {
-			ulong addr = simple_strtoul(argv[2], NULL, 16);
-			ulong cnt = simple_strtoul(argv[4], NULL, 16);
-			ulong n;
+	debug("in output data shorts base for read is %lx\n",
+	      (unsigned long) pbuf);
 
-#ifdef CONFIG_SYS_64BIT_LBA
-			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
+	while (shorts--) {
+		EIEIO;
+		*pbuf = *dbuf++;
+	}
+}
 
-			printf("\nIDE write: device %d block # %lld, count %ld...",
-			       curr_device, blk, cnt);
-#else
-			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
 
-			printf("\nIDE write: device %d block # %ld, count %ld...",
-			       curr_device, blk, cnt);
-#endif
-			n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
-				      (ulong *)addr);
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
 
-			printf("%ld blocks written: %s\n",
-				n, (n == cnt) ? "OK" : "ERROR");
-			if (n == cnt)
-				return 0;
-			else
-				return 1;
-		} else {
-			return CMD_RET_USAGE;
-		}
+	debug("in input data shorts base for read is %lx\n",
+	      (unsigned long) pbuf);
 
-		return rcode;
+	while (shorts--) {
+		EIEIO;
+		*dbuf++ = *pbuf;
 	}
 }
 
-int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-	return common_diskboot(cmdtp, "ide", argc, argv);
+	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
 }
 
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_led(uchar led, uchar status)
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
-	static uchar led_buffer;	/* Buffer for current LED status */
-
-	uchar *led_port = LED_PORT;
+	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
 
-	if (status)		/* switch LED on        */
-		led_buffer |= led;
-	else			/* switch LED off       */
-		led_buffer &= ~led;
+#endif /* CONFIG_IDE_SWAP_IO */
 
-	*led_port = led_buffer;
-#endif
-}
-
-#ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
-# define DEVICE_LED(x) 0
-# define LED_IDE1 1
-# define LED_IDE2 2
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_outb(int dev, int port, unsigned char val)
+/*
+ * Wait until (Status & mask) == res, or timeout (in ms)
+ * Return last status
+ * This is used since some ATAPI CD ROMs clears their Busy Bit first
+ * and then they set their DRQ Bit
+ */
+static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
 {
-	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
-	      dev, port, val,
-	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+	ulong delay = 10 * t;	/* poll every 100 us */
+	uchar c;
 
-#if defined(CONFIG_IDE_AHB)
-	if (port) {
-		/* write command */
-		ide_write_register(dev, port, val);
-	} else {
-		/* write data */
-		outb(val, (ATA_CURR_BASE(dev)));
+	/* prevents to read the status before valid */
+	c = ide_inb(dev, ATA_DEV_CTL);
+
+	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+		/* break if error occurs (doesn't make sense to wait more) */
+		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
+			break;
+		udelay(100);
+		if (delay-- == 0)
+			break;
 	}
-#else
-	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
+	return c;
 }
 
-__weak unsigned char ide_inb(int dev, int port)
+/*
+ * issue an atapi command
+ */
+unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
+			  unsigned char *buffer, int buflen)
 {
-	uchar val;
-
-#if defined(CONFIG_IDE_AHB)
-	val = ide_read_register(dev, port);
-#else
-	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
+	unsigned char c, err, mask, res;
+	int n;
 
-	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
-	      dev, port,
-	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
-	return val;
-}
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
 
-void ide_init(void)
-{
-	unsigned char c;
-	int i, bus;
+	/* Select device
+	 */
+	mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
+	res = 0;
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & mask) != res) {
+		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+		       c);
+		err = 0xFF;
+		goto AI_OUT;
+	}
+	/* write taskfile */
+	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
+	ide_outb(device, ATA_SECT_CNT, 0);
+	ide_outb(device, ATA_SECT_NUM, 0);
+	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
+	ide_outb(device, ATA_CYL_HIGH,
+		 (unsigned char) ((buflen >> 8) & 0xFF));
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
 
-#ifdef CONFIG_IDE_8xx_PCCARD
-	extern int ide_devices_found;	/* Initialized in check_ide_device() */
-#endif /* CONFIG_IDE_8xx_PCCARD */
+	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
+	udelay(50);
 
-#ifdef CONFIG_IDE_PREINIT
-	WATCHDOG_RESET();
+	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+	res = ATA_STAT_DRQ;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
 
-	if (ide_preinit()) {
-		puts("ide_preinit failed\n");
-		return;
+	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
+		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+		       device, c);
+		err = 0xFF;
+		goto AI_OUT;
 	}
-#endif /* CONFIG_IDE_PREINIT */
 
-	WATCHDOG_RESET();
+	/* write command block */
+	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
 
+	/* ATAPI Command written wait for completition */
+	udelay(5000);		/* device must set bsy */
+
+	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
 	/*
-	 * Reset the IDE just to be sure.
-	 * Light LED's to show
+	 * if no data wait for DRQ = 0 BSY = 0
+	 * if data wait for DRQ = 1 BSY = 0
 	 */
-	ide_led((LED_IDE1 | LED_IDE2), 1);	/* LED's on     */
-
-	/* ATAPI Drives seems to need a proper IDE Reset */
-	ide_reset();
-
-#ifdef CONFIG_IDE_INIT_POSTRESET
-	WATCHDOG_RESET();
-
-	if (ide_init_postreset()) {
-		puts("ide_preinit_postreset failed\n");
-		return;
+	res = 0;
+	if (buflen)
+		res = ATA_STAT_DRQ;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & mask) != res) {
+		if (c & ATA_STAT_ERR) {
+			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
+			debug("atapi_issue 1 returned sense key %X status %02X\n",
+			      err, c);
+		} else {
+			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
+			       ccb[0], c);
+			err = 0xFF;
+		}
+		goto AI_OUT;
 	}
-#endif /* CONFIG_IDE_INIT_POSTRESET */
+	n = ide_inb(device, ATA_CYL_HIGH);
+	n <<= 8;
+	n += ide_inb(device, ATA_CYL_LOW);
+	if (n > buflen) {
+		printf("ERROR, transfer bytes %d requested only %d\n", n,
+		       buflen);
+		err = 0xff;
+		goto AI_OUT;
+	}
+	if ((n == 0) && (buflen < 0)) {
+		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
+		err = 0xff;
+		goto AI_OUT;
+	}
+	if (n != buflen) {
+		debug("WARNING, transfer bytes %d not equal with requested %d\n",
+		      n, buflen);
+	}
+	if (n != 0) {		/* data transfer */
+		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+		/* we transfer shorts */
+		n >>= 1;
+		/* ok now decide if it is an in or output */
+		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
+			debug("Write to device\n");
+			ide_output_data_shorts(device, (unsigned short *)buffer,
+					       n);
+		} else {
+			debug("Read from device @ %p shorts %d\n", buffer, n);
+			ide_input_data_shorts(device, (unsigned short *)buffer,
+					      n);
+		}
+	}
+	udelay(5000);		/* seems that some CD ROMs need this... */
+	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
+	res = 0;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
+		debug("atapi_issue 2 returned sense key %X status %X\n", err,
+		      c);
+	} else {
+		err = 0;
+	}
+AI_OUT:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return err;
+}
 
-	/*
-	 * Wait for IDE to get ready.
-	 * According to spec, this can take up to 31 seconds!
-	 */
-	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
-		int dev =
-			bus * (CONFIG_SYS_IDE_MAXDEVICE /
-			       CONFIG_SYS_IDE_MAXBUS);
+/*
+ * sending the command to atapi_issue. If an status other than good
+ * returns, an request_sense will be issued
+ */
 
-#ifdef CONFIG_IDE_8xx_PCCARD
-		/* Skip non-ide devices from probing */
-		if ((ide_devices_found & (1 << bus)) == 0) {
-			ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off */
-			continue;
-		}
-#endif
-		printf("Bus %d: ", bus);
+#define ATAPI_DRIVE_NOT_READY	100
+#define ATAPI_UNIT_ATTN		10
 
-		ide_bus_ok[bus] = 0;
+unsigned char atapi_issue_autoreq(int device,
+				  unsigned char *ccb,
+				  int ccblen,
+				  unsigned char *buffer, int buflen)
+{
+	unsigned char sense_data[18], sense_ccb[12];
+	unsigned char res, key, asc, ascq;
+	int notready, unitattn;
 
-		/* Select device
-		 */
-		udelay(100000);	/* 100 ms */
-		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
-		udelay(100000);	/* 100 ms */
-		i = 0;
-		do {
-			udelay(10000);	/* 10 ms */
+	unitattn = ATAPI_UNIT_ATTN;
+	notready = ATAPI_DRIVE_NOT_READY;
 
-			c = ide_inb(dev, ATA_STATUS);
-			i++;
-			if (i > (ATA_RESET_TIME * 100)) {
-				puts("** Timeout **\n");
-				/* LED's off */
-				ide_led((LED_IDE1 | LED_IDE2), 0);
-				return;
-			}
-			if ((i >= 100) && ((i % 100) == 0))
-				putc('.');
+retry:
+	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
+	if (res == 0)
+		return 0;	/* Ok */
 
-		} while (c & ATA_STAT_BUSY);
+	if (res == 0xFF)
+		return 0xFF;	/* error */
 
-		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
-		} else if ((c & ATA_STAT_READY) == 0) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#endif
-		} else {
-			puts("OK ");
-			ide_bus_ok[bus] = 1;
-		}
-		WATCHDOG_RESET();
-	}
+	debug("(auto_req)atapi_issue returned sense key %X\n", res);
 
-	putc('\n');
+	memset(sense_ccb, 0, sizeof(sense_ccb));
+	memset(sense_data, 0, sizeof(sense_data));
+	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
+	sense_ccb[4] = 18;	/* allocation Length */
 
-	ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off    */
+	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
+	key = (sense_data[2] & 0xF);
+	asc = (sense_data[12]);
+	ascq = (sense_data[13]);
 
-	curr_device = -1;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-		ide_dev_desc[i].if_type = IF_TYPE_IDE;
-		ide_dev_desc[i].devnum = i;
-		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		ide_dev_desc[i].blksz = 0;
-		ide_dev_desc[i].log2blksz =
-			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
-		ide_dev_desc[i].lba = 0;
-		ide_dev_desc[i].block_read = ide_read;
-		ide_dev_desc[i].block_write = ide_write;
-		if (!ide_bus_ok[IDE_BUS(i)])
-			continue;
-		ide_led(led, 1);	/* LED on       */
-		ide_ident(&ide_dev_desc[i]);
-		ide_led(led, 0);	/* LED off      */
-		dev_print(&ide_dev_desc[i]);
+	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+	      sense_data[0], key, asc, ascq);
 
-		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
-			/* initialize partition type */
-			part_init(&ide_dev_desc[i]);
-			if (curr_device < 0)
-				curr_device = i;
+	if ((key == 0))
+		return 0;	/* ok device ready */
+
+	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+		if (unitattn-- > 0) {
+			udelay(200 * 1000);
+			goto retry;
 		}
+		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
+		goto error;
 	}
-	WATCHDOG_RESET();
+	if ((asc == 0x4) && (ascq == 0x1)) {
+		/* not ready, but will be ready soon */
+		if (notready-- > 0) {
+			udelay(200 * 1000);
+			goto retry;
+		}
+		printf("Drive not ready, tried %d times\n",
+		       ATAPI_DRIVE_NOT_READY);
+		goto error;
+	}
+	if (asc == 0x3a) {
+		debug("Media not present\n");
+		goto error;
+	}
+
+	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
+	       ascq);
+error:
+	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+	return 0xFF;
 }
 
-/* ------------------------------------------------------------------------- */
+/*
+ * atapi_read:
+ * we transfer only one block per command, since the multiple DRQ per
+ * command is not yet implemented
+ */
+#define ATAPI_READ_MAX_BYTES	2048	/* we read max 2kbytes */
+#define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
+#define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *ide_get_dev(int dev)
+ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		 void *buffer)
 {
-	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
-}
-#endif
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char ccb[12];	/* Command descriptor block */
+	ulong cnt;
 
-/* ------------------------------------------------------------------------- */
+	debug("atapi_read dev %d start " LBAF " blocks " LBAF
+	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
 
-/* We only need to swap data if we are running on a big endian cpu. */
-#if defined(__LITTLE_ENDIAN)
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	ide_input_data(dev, sect_buf, words);
+	do {
+		if (blkcnt > ATAPI_READ_MAX_BLOCK)
+			cnt = ATAPI_READ_MAX_BLOCK;
+		else
+			cnt = blkcnt;
+
+		ccb[0] = ATAPI_CMD_READ_12;
+		ccb[1] = 0;	/* reserved */
+		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
+		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
+		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
+		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
+		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
+		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
+		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
+		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
+		ccb[10] = 0;	/* reserved */
+		ccb[11] = 0;	/* reserved */
+
+		if (atapi_issue_autoreq(device, ccb, 12,
+					(unsigned char *)buffer,
+					cnt * ATAPI_READ_BLOCK_SIZE)
+		    == 0xFF) {
+			return n;
+		}
+		n += cnt;
+		blkcnt -= cnt;
+		blknr += cnt;
+		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+	} while (blkcnt > 0);
+	return n;
 }
-#else
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+
+static void atapi_inquiry(struct blk_desc *dev_desc)
 {
-	volatile ushort *pbuf =
-		(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	ushort *dbuf = (ushort *) sect_buf;
+	unsigned char ccb[12];	/* Command descriptor block */
+	unsigned char iobuf[64];	/* temp buf */
+	unsigned char c;
+	int device;
 
-	debug("in input swap data base for read is %lx\n",
-	      (unsigned long) pbuf);
+	device = dev_desc->devnum;
+	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
+	dev_desc->block_read = atapi_read;
 
-	while (words--) {
-#ifdef __MIPS__
-		*dbuf++ = swab16p((u16 *) pbuf);
-		*dbuf++ = swab16p((u16 *) pbuf);
-#else
-		*dbuf++ = ld_le16(pbuf);
-		*dbuf++ = ld_le16(pbuf);
-#endif /* !MIPS */
-	}
-}
-#endif /* __LITTLE_ENDIAN */
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
 
+	ccb[0] = ATAPI_CMD_INQUIRY;
+	ccb[4] = 40;		/* allocation Legnth */
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
 
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
+	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+	if (c != 0)
+		return;
 
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
-	while (words--) {
-		EIEIO;
-		*pbuf = *dbuf++;
-		EIEIO;
-		*pbuf = *dbuf++;
-	}
-}
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
-	ide_write_data(dev, sect_buf, words);
-#else
-	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-#endif /* CONFIG_IDE_SWAP_IO */
+	/* copy device ident strings */
+	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
+	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
+	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
 
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
+	dev_desc->lun = 0;
+	dev_desc->lba = 0;
+	dev_desc->blksz = 0;
+	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
+	dev_desc->type = iobuf[0] & 0x1f;
 
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
+	if ((iobuf[1] & 0x80) == 0x80)
+		dev_desc->removable = 1;
+	else
+		dev_desc->removable = 0;
 
-	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	ccb[0] = ATAPI_CMD_START_STOP;
+	ccb[4] = 0x03;		/* start */
 
-	while (words--) {
-		EIEIO;
-		*dbuf++ = *pbuf;
-		EIEIO;
-		*dbuf++ = *pbuf;
-	}
-}
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
-	ide_read_data(dev, sect_buf, words);
-#else
-	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+	debug("ATAPI_CMD_START_STOP returned %x\n", c);
+	if (c != 0)
+		return;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+	if (c != 0)
+		return;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	ccb[0] = ATAPI_CMD_READ_CAP;
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
+	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+	if (c != 0)
+		return;
+
+	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+
+	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
+		((unsigned long) iobuf[1] << 16) +
+		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
+	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
+		((unsigned long) iobuf[5] << 16) +
+		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
+	dev_desc->log2blksz = LOG2(dev_desc->blksz);
+#ifdef CONFIG_LBA48
+	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
+	dev_desc->lba48 = 0;
 #endif
+	return;
 }
 
-#endif /* CONFIG_IDE_SWAP_IO */
+#endif /* CONFIG_ATAPI */
 
-/* -------------------------------------------------------------------------
- */
 static void ide_ident(struct blk_desc *dev_desc)
 {
 	unsigned char c;
@@ -633,11 +660,11 @@ static void ide_ident(struct blk_desc *dev_desc)
 
 	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
 
-	ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev,
+	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
 		  sizeof(dev_desc->revision));
-	ident_cpy((unsigned char *) dev_desc->vendor, iop.model,
+	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
 		  sizeof(dev_desc->vendor));
-	ident_cpy((unsigned char *) dev_desc->product, iop.serial_no,
+	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
 		  sizeof(dev_desc->product));
 #ifdef __LITTLE_ENDIAN
 	/*
@@ -711,737 +738,678 @@ static void ide_ident(struct blk_desc *dev_desc)
 #endif
 }
 
+/* ------------------------------------------------------------------------- */
+
+int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int rcode = 0;
+
+	switch (argc) {
+	case 0:
+	case 1:
+		return CMD_RET_USAGE;
+	case 2:
+		if (strncmp(argv[1], "res", 3) == 0) {
+			puts("\nReset IDE"
+#ifdef CONFIG_IDE_8xx_DIRECT
+			     " on PCMCIA " PCMCIA_SLOT_MSG
+#endif
+			     ": ");
+
+			ide_init();
+			return 0;
+		} else if (strncmp(argv[1], "inf", 3) == 0) {
+			int i;
+
+			putc('\n');
+
+			for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
+				if (ide_dev_desc[i].type == DEV_TYPE_UNKNOWN)
+					continue;  /* list only known devices */
+				printf("IDE device %d: ", i);
+				dev_print(&ide_dev_desc[i]);
+			}
+			return 0;
+
+		} else if (strncmp(argv[1], "dev", 3) == 0) {
+			if (curr_device < 0 ||
+			    curr_device >= CONFIG_SYS_IDE_MAXDEVICE) {
+				puts("\nno IDE devices available\n");
+				return 1;
+			}
+			printf("\nIDE device %d: ", curr_device);
+			dev_print(&ide_dev_desc[curr_device]);
+			return 0;
+		} else if (strncmp(argv[1], "part", 4) == 0) {
+			int dev, ok;
+
+			for (ok = 0, dev = 0;
+			     dev < CONFIG_SYS_IDE_MAXDEVICE;
+			     ++dev) {
+				if (ide_dev_desc[dev].part_type !=
+				    PART_TYPE_UNKNOWN) {
+					++ok;
+					if (dev)
+						putc('\n');
+					part_print(&ide_dev_desc[dev]);
+				}
+			}
+			if (!ok) {
+				puts("\nno IDE devices available\n");
+				rcode++;
+			}
+			return rcode;
+		}
+		return CMD_RET_USAGE;
+	case 3:
+		if (strncmp(argv[1], "dev", 3) == 0) {
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-/* ------------------------------------------------------------------------- */
+			printf("\nIDE device %d: ", dev);
+			if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
+				puts("unknown device\n");
+				return 1;
+			}
+			dev_print(&ide_dev_desc[dev]);
+			/*ide_print (dev); */
 
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char c;
-	unsigned char pwrsave = 0;	/* power save */
+			if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
+				return 1;
 
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
+			curr_device = dev;
 
-	if (blknr & 0x0000fffff0000000ULL) {
-		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
-	}
-#endif
-	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
-	      device, blknr, blkcnt, (ulong) buffer);
+			puts("... is now current device\n");
 
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+			return 0;
+		} else if (strncmp(argv[1], "part", 4) == 0) {
+			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = ide_wait(device, IDE_TIME_OUT);
+			if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
+				part_print(&ide_dev_desc[dev]);
+			} else {
+				printf("\nIDE device %d not available\n",
+				       dev);
+				rcode = 1;
+			}
+			return rcode;
+		}
 
-	if (c & ATA_STAT_BUSY) {
-		printf("IDE read: device %d not ready\n", device);
-		goto IDE_READ_E;
-	}
+		return CMD_RET_USAGE;
+	default:
+		/* at least 4 args */
 
-	/* first check if the drive is in Powersaving mode, if yes,
-	 * increase the timeout value */
-	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
-	udelay(50);
+		if (strcmp(argv[1], "read") == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong cnt = simple_strtoul(argv[4], NULL, 16);
+			struct blk_desc *dev_desc;
+			ulong n;
 
-	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
+#ifdef CONFIG_SYS_64BIT_LBA
+			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
 
-	if (c & ATA_STAT_BUSY) {
-		printf("IDE read: device %d not ready\n", device);
-		goto IDE_READ_E;
-	}
-	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		printf("No Powersaving mode %X\n", c);
-	} else {
-		c = ide_inb(device, ATA_SECT_CNT);
-		debug("Powersaving %02X\n", c);
-		if (c == 0)
-			pwrsave = 1;
-	}
+			printf("\nIDE read: device %d block # %lld, count %ld...",
+			       curr_device, blk, cnt);
+#else
+			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
 
+			printf("\nIDE read: device %d block # %ld, count %ld...",
+			       curr_device, blk, cnt);
+#endif
 
-	while (blkcnt-- > 0) {
+			dev_desc = &ide_dev_desc[curr_device];
+			n = blk_dread(dev_desc, blk, cnt, (ulong *)addr);
+			/* flush cache after read */
+			flush_cache(addr,
+				    cnt * ide_dev_desc[curr_device].blksz);
 
-		c = ide_wait(device, IDE_TIME_OUT);
+			printf("%ld blocks read: %s\n",
+			       n, (n == cnt) ? "OK" : "ERROR");
+			if (n == cnt)
+				return 0;
+			else
+				return 1;
+		} else if (strcmp(argv[1], "write") == 0) {
+			ulong addr = simple_strtoul(argv[2], NULL, 16);
+			ulong cnt = simple_strtoul(argv[4], NULL, 16);
+			ulong n;
 
-		if (c & ATA_STAT_BUSY) {
-			printf("IDE read: device %d not ready\n", device);
-			break;
-		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			/* write high bits */
-			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
 #ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+			lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
+
+			printf("\nIDE write: device %d block # %lld, count %ld...",
+			       curr_device, blk, cnt);
 #else
-			ide_outb(device, ATA_LBA_MID, 0);
-			ide_outb(device, ATA_LBA_HIGH, 0);
+			lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
+
+			printf("\nIDE write: device %d block # %ld, count %ld...",
+			       curr_device, blk, cnt);
 #endif
+			n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
+				      (ulong *)addr);
+
+			printf("%ld blocks written: %s\n", n,
+			       n == cnt ? "OK" : "ERROR");
+			if (n == cnt)
+				return 0;
+			else
+				return 1;
+		} else {
+			return CMD_RET_USAGE;
 		}
-#endif
-		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
 
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
+		return rcode;
+	}
+}
 
-		} else
-#endif
-		{
-			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
-		}
+int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	return common_diskboot(cmdtp, "ide", argc, argv);
+}
 
-		udelay(50);
+/* ------------------------------------------------------------------------- */
 
-		if (pwrsave) {
-			/* may take up to 4 sec */
-			c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
-			pwrsave = 0;
-		} else {
-			/* can't take over 500 ms */
-			c = ide_wait(device, IDE_TIME_OUT);
-		}
+__weak void ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+	static uchar led_buffer;	/* Buffer for current LED status */
 
-		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
-		    ATA_STAT_DRQ) {
-			printf("Error (no IRQ) dev %d blk " LBAF ": status "
-			       "%#02x\n", device, blknr, c);
-			break;
-		}
+	uchar *led_port = LED_PORT;
 
-		ide_input_data(device, buffer, ATA_SECTORWORDS);
-		(void) ide_inb(device, ATA_STATUS);	/* clear IRQ */
+	if (status)		/* switch LED on        */
+		led_buffer |= led;
+	else			/* switch LED off       */
+		led_buffer &= ~led;
 
-		++n;
-		++blknr;
-		buffer += ATA_BLOCKSIZE;
-	}
-IDE_READ_E:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return n;
+	*led_port = led_buffer;
+#endif
 }
 
 /* ------------------------------------------------------------------------- */
 
+__weak void ide_outb(int dev, int port, unsigned char val)
+{
+	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+	      dev, port, val,
+	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
 
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer)
+#if defined(CONFIG_IDE_AHB)
+	if (port) {
+		/* write command */
+		ide_write_register(dev, port, val);
+	} else {
+		/* write data */
+		outb(val, (ATA_CURR_BASE(dev)));
+	}
+#else
+	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+}
+
+__weak unsigned char ide_inb(int dev, int port)
+{
+	uchar val;
+
+#if defined(CONFIG_IDE_AHB)
+	val = ide_read_register(dev, port);
+#else
+	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+
+	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+	      dev, port,
+	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+	return val;
+}
+
+void ide_init(void)
 {
-	int device = block_dev->devnum;
-	ulong n = 0;
 	unsigned char c;
+	int i, bus;
 
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
+#ifdef CONFIG_IDE_8xx_PCCARD
+	extern int ide_devices_found;	/* Initialized in check_ide_device() */
+#endif /* CONFIG_IDE_8xx_PCCARD */
 
-	if (blknr & 0x0000fffff0000000ULL) {
-		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
+#ifdef CONFIG_IDE_PREINIT
+	WATCHDOG_RESET();
+
+	if (ide_preinit()) {
+		puts("ide_preinit failed\n");
+		return;
 	}
-#endif
+#endif /* CONFIG_IDE_PREINIT */
 
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+	WATCHDOG_RESET();
 
-	/* Select device
+	/*
+	 * Reset the IDE just to be sure.
+	 * Light LED's to show
 	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	ide_led((LED_IDE1 | LED_IDE2), 1);	/* LED's on     */
 
-	while (blkcnt-- > 0) {
+	/* ATAPI Drives seems to need a proper IDE Reset */
+	ide_reset();
 
-		c = ide_wait(device, IDE_TIME_OUT);
+#ifdef CONFIG_IDE_INIT_POSTRESET
+	WATCHDOG_RESET();
 
-		if (c & ATA_STAT_BUSY) {
-			printf("IDE read: device %d not ready\n", device);
-			goto WR_OUT;
-		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			/* write high bits */
-			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
-			ide_outb(device, ATA_LBA_MID, 0);
-			ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
+	if (ide_init_postreset()) {
+		puts("ide_preinit_postreset failed\n");
+		return;
+	}
+#endif /* CONFIG_IDE_INIT_POSTRESET */
+
+	/*
+	 * Wait for IDE to get ready.
+	 * According to spec, this can take up to 31 seconds!
+	 */
+	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+		int dev =
+			bus * (CONFIG_SYS_IDE_MAXDEVICE /
+			       CONFIG_SYS_IDE_MAXBUS);
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+		/* Skip non-ide devices from probing */
+		if ((ide_devices_found & (1 << bus)) == 0) {
+			ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off */
+			continue;
 		}
 #endif
-		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+		printf("Bus %d: ", bus);
 
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
+		ide_bus_ok[bus] = 0;
 
-		} else
-#endif
-		{
-			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
-		}
+		/* Select device
+		 */
+		udelay(100000);	/* 100 ms */
+		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+		udelay(100000);	/* 100 ms */
+		i = 0;
+		do {
+			udelay(10000);	/* 10 ms */
 
-		udelay(50);
+			c = ide_inb(dev, ATA_STATUS);
+			i++;
+			if (i > (ATA_RESET_TIME * 100)) {
+				puts("** Timeout **\n");
+				/* LED's off */
+				ide_led((LED_IDE1 | LED_IDE2), 0);
+				return;
+			}
+			if ((i >= 100) && ((i % 100) == 0))
+				putc('.');
 
-		/* can't take over 500 ms */
-		c = ide_wait(device, IDE_TIME_OUT);
+		} while (c & ATA_STAT_BUSY);
 
-		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
-		    ATA_STAT_DRQ) {
-			printf("Error (no IRQ) dev %d blk " LBAF ": status "
-				"%#02x\n", device, blknr, c);
-			goto WR_OUT;
+		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+			puts("not available  ");
+			debug("Status = 0x%02X ", c);
+#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
+		} else if ((c & ATA_STAT_READY) == 0) {
+			puts("not available  ");
+			debug("Status = 0x%02X ", c);
+#endif
+		} else {
+			puts("OK ");
+			ide_bus_ok[bus] = 1;
 		}
-
-		ide_output_data(device, buffer, ATA_SECTORWORDS);
-		c = ide_inb(device, ATA_STATUS);	/* clear IRQ */
-		++n;
-		++blknr;
-		buffer += ATA_BLOCKSIZE;
+		WATCHDOG_RESET();
 	}
-WR_OUT:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return n;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * copy src to dest, skipping leading and trailing blanks and null
- * terminate the string
- * "len" is the size of available memory including the terminating '\0'
- */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
-		      unsigned int len)
-{
-	unsigned char *end, *last;
 
-	last = dst;
-	end = src + len - 1;
+	putc('\n');
 
-	/* reserve space for '\0' */
-	if (len < 2)
-		goto OUT;
+	ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off    */
 
-	/* skip leading white space */
-	while ((*src) && (src < end) && (*src == ' '))
-		++src;
+	curr_device = -1;
+	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
+		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
+		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		ide_dev_desc[i].if_type = IF_TYPE_IDE;
+		ide_dev_desc[i].devnum = i;
+		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		ide_dev_desc[i].blksz = 0;
+		ide_dev_desc[i].log2blksz =
+			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
+		ide_dev_desc[i].lba = 0;
+		ide_dev_desc[i].block_read = ide_read;
+		ide_dev_desc[i].block_write = ide_write;
+		if (!ide_bus_ok[IDE_BUS(i)])
+			continue;
+		ide_led(led, 1);	/* LED on       */
+		ide_ident(&ide_dev_desc[i]);
+		ide_led(led, 0);	/* LED off      */
+		dev_print(&ide_dev_desc[i]);
 
-	/* copy string, omitting trailing white space */
-	while ((*src) && (src < end)) {
-		*dst++ = *src;
-		if (*src++ != ' ')
-			last = dst;
+		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
+			/* initialize partition type */
+			part_init(&ide_dev_desc[i]);
+			if (curr_device < 0)
+				curr_device = i;
+		}
 	}
-OUT:
-	*last = '\0';
+	WATCHDOG_RESET();
 }
 
 /* ------------------------------------------------------------------------- */
 
-/*
- * Wait until Busy bit is off, or timeout (in ms)
- * Return last status
- */
-static uchar ide_wait(int dev, ulong t)
+#ifdef CONFIG_PARTITIONS
+struct blk_desc *ide_get_dev(int dev)
 {
-	ulong delay = 10 * t;	/* poll every 100 us */
-	uchar c;
-
-	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
-		udelay(100);
-		if (delay-- == 0)
-			break;
-	}
-	return c;
+	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
 }
+#endif
 
 /* ------------------------------------------------------------------------- */
 
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
-static void ide_reset(void)
+/* We only need to swap data if we are running on a big endian cpu. */
+#if defined(__LITTLE_ENDIAN)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
 {
-	int i;
-
-	curr_device = -1;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
-		ide_bus_ok[i] = 0;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-
-	ide_set_reset(1);	/* assert reset */
-
-	/* the reset signal shall be asserted for et least 25 us */
-	udelay(25);
-
-	WATCHDOG_RESET();
-
-	/* de-assert RESET signal */
-	ide_set_reset(0);
-
-	/* wait 250 ms */
-	for (i = 0; i < 250; ++i)
-		udelay(1000);
+	ide_input_data(dev, sect_buf, words);
 }
+#else
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	volatile ushort *pbuf =
+		(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	ushort *dbuf = (ushort *)sect_buf;
 
-#endif /* CONFIG_IDE_RESET */
-
-/* ------------------------------------------------------------------------- */
+	debug("in input swap data base for read is %lx\n",
+	      (unsigned long) pbuf);
 
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
-{
-	if (dev >= CONFIG_SYS_IDE_MAXBUS)
-		return 0;
-	return (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1);
+	while (words--) {
+#ifdef __MIPS__
+		*dbuf++ = swab16p((u16 *)pbuf);
+		*dbuf++ = swab16p((u16 *)pbuf);
+#else
+		*dbuf++ = ld_le16(pbuf);
+		*dbuf++ = ld_le16(pbuf);
+#endif /* !MIPS */
+	}
 }
-#endif
-/* ------------------------------------------------------------------------- */
+#endif /* __LITTLE_ENDIAN */
 
-#ifdef CONFIG_ATAPI
-/****************************************************************************
- * ATAPI Support
- */
 
 #if defined(CONFIG_IDE_SWAP_IO)
-/* since ATAPI may use commands with not 4 bytes alligned length
- * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
 {
 	ushort *dbuf;
 	volatile ushort *pbuf;
 
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
-
-	debug("in output data shorts base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (shorts--) {
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+	while (words--) {
+		EIEIO;
+		*pbuf = *dbuf++;
 		EIEIO;
 		*pbuf = *dbuf++;
 	}
 }
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+	ide_write_data(dev, sect_buf, words);
+#else
+	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+#endif /* CONFIG_IDE_SWAP_IO */
 
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
 {
 	ushort *dbuf;
 	volatile ushort *pbuf;
 
-	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *) sect_buf;
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
 
-	debug("in input data shorts base for read is %lx\n",
-	      (unsigned long) pbuf);
+	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
 
-	while (shorts--) {
+	while (words--) {
+		EIEIO;
+		*dbuf++ = *pbuf;
 		EIEIO;
 		*dbuf++ = *pbuf;
 	}
 }
-
 #else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
 {
-	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+#if defined(CONFIG_IDE_AHB)
+	ide_read_data(dev, sect_buf, words);
+#else
+	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
 }
 
 #endif /* CONFIG_IDE_SWAP_IO */
 
-/*
- * Wait until (Status & mask) == res, or timeout (in ms)
- * Return last status
- * This is used since some ATAPI CD ROMs clears their Busy Bit first
- * and then they set their DRQ Bit
- */
-static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
+/* ------------------------------------------------------------------------- */
+
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer)
 {
-	ulong delay = 10 * t;	/* poll every 100 us */
-	uchar c;
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char c;
+	unsigned char pwrsave = 0;	/* power save */
 
-	/* prevents to read the status before valid */
-	c = ide_inb(dev, ATA_DEV_CTL);
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
 
-	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
-		/* break if error occurs (doesn't make sense to wait more) */
-		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
-			break;
-		udelay(100);
-		if (delay-- == 0)
-			break;
+	if (blknr & 0x0000fffff0000000ULL) {
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
 	}
-	return c;
-}
-
-/*
- * issue an atapi command
- */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
-			  unsigned char *buffer, int buflen)
-{
-	unsigned char c, err, mask, res;
-	int n;
+#endif
+	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
+	      device, blknr, blkcnt, (ulong) buffer);
 
 	ide_led(DEVICE_LED(device), 1);	/* LED on       */
 
 	/* Select device
 	 */
-	mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
-	res = 0;
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & mask) != res) {
-		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
-		       c);
-		err = 0xFF;
-		goto AI_OUT;
-	}
-	/* write taskfile */
-	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
-	ide_outb(device, ATA_SECT_CNT, 0);
-	ide_outb(device, ATA_SECT_NUM, 0);
-	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
-	ide_outb(device, ATA_CYL_HIGH,
-		 (unsigned char) ((buflen >> 8) & 0xFF));
 	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = ide_wait(device, IDE_TIME_OUT);
 
-	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
-	udelay(50);
-
-	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
-	res = ATA_STAT_DRQ;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-
-	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
-		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
-		       device, c);
-		err = 0xFF;
-		goto AI_OUT;
-	}
-
-	/* write command block */
-	ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
-
-	/* ATAPI Command written wait for completition */
-	udelay(5000);		/* device must set bsy */
-
-	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
-	/*
-	 * if no data wait for DRQ = 0 BSY = 0
-	 * if data wait for DRQ = 1 BSY = 0
-	 */
-	res = 0;
-	if (buflen)
-		res = ATA_STAT_DRQ;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & mask) != res) {
-		if (c & ATA_STAT_ERR) {
-			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
-			debug("atapi_issue 1 returned sense key %X status %02X\n",
-			      err, c);
-		} else {
-			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
-			       ccb[0], c);
-			err = 0xFF;
-		}
-		goto AI_OUT;
-	}
-	n = ide_inb(device, ATA_CYL_HIGH);
-	n <<= 8;
-	n += ide_inb(device, ATA_CYL_LOW);
-	if (n > buflen) {
-		printf("ERROR, transfer bytes %d requested only %d\n", n,
-		       buflen);
-		err = 0xff;
-		goto AI_OUT;
-	}
-	if ((n == 0) && (buflen < 0)) {
-		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
-		err = 0xff;
-		goto AI_OUT;
-	}
-	if (n != buflen) {
-		debug("WARNING, transfer bytes %d not equal with requested %d\n",
-		      n, buflen);
-	}
-	if (n != 0) {		/* data transfer */
-		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
-		/* we transfer shorts */
-		n >>= 1;
-		/* ok now decide if it is an in or output */
-		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
-			debug("Write to device\n");
-			ide_output_data_shorts(device,
-				(unsigned short *) buffer, n);
-		} else {
-			debug("Read from device @ %p shorts %d\n", buffer, n);
-			ide_input_data_shorts(device,
-				(unsigned short *) buffer, n);
-		}
-	}
-	udelay(5000);		/* seems that some CD ROMs need this... */
-	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
-	res = 0;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
-		debug("atapi_issue 2 returned sense key %X status %X\n", err,
-		      c);
-	} else {
-		err = 0;
+	if (c & ATA_STAT_BUSY) {
+		printf("IDE read: device %d not ready\n", device);
+		goto IDE_READ_E;
 	}
-AI_OUT:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return err;
-}
-
-/*
- * sending the command to atapi_issue. If an status other than good
- * returns, an request_sense will be issued
- */
-
-#define ATAPI_DRIVE_NOT_READY	100
-#define ATAPI_UNIT_ATTN		10
-
-unsigned char atapi_issue_autoreq(int device,
-				  unsigned char *ccb,
-				  int ccblen,
-				  unsigned char *buffer, int buflen)
-{
-	unsigned char sense_data[18], sense_ccb[12];
-	unsigned char res, key, asc, ascq;
-	int notready, unitattn;
-
-	unitattn = ATAPI_UNIT_ATTN;
-	notready = ATAPI_DRIVE_NOT_READY;
-
-retry:
-	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
-	if (res == 0)
-		return 0;	/* Ok */
-
-	if (res == 0xFF)
-		return 0xFF;	/* error */
-
-	debug("(auto_req)atapi_issue returned sense key %X\n", res);
-
-	memset(sense_ccb, 0, sizeof(sense_ccb));
-	memset(sense_data, 0, sizeof(sense_data));
-	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
-	sense_ccb[4] = 18;	/* allocation Length */
-
-	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
-	key = (sense_data[2] & 0xF);
-	asc = (sense_data[12]);
-	ascq = (sense_data[13]);
 
-	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
-	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
-	      sense_data[0], key, asc, ascq);
+	/* first check if the drive is in Powersaving mode, if yes,
+	 * increase the timeout value */
+	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
+	udelay(50);
 
-	if ((key == 0))
-		return 0;	/* ok device ready */
+	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
 
-	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
-		if (unitattn-- > 0) {
-			udelay(200 * 1000);
-			goto retry;
-		}
-		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
-		goto error;
-	}
-	if ((asc == 0x4) && (ascq == 0x1)) {
-		/* not ready, but will be ready soon */
-		if (notready-- > 0) {
-			udelay(200 * 1000);
-			goto retry;
-		}
-		printf("Drive not ready, tried %d times\n",
-		       ATAPI_DRIVE_NOT_READY);
-		goto error;
+	if (c & ATA_STAT_BUSY) {
+		printf("IDE read: device %d not ready\n", device);
+		goto IDE_READ_E;
 	}
-	if (asc == 0x3a) {
-		debug("Media not present\n");
-		goto error;
+	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+		printf("No Powersaving mode %X\n", c);
+	} else {
+		c = ide_inb(device, ATA_SECT_CNT);
+		debug("Powersaving %02X\n", c);
+		if (c == 0)
+			pwrsave = 1;
 	}
 
-	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
-	       ascq);
-error:
-	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
-	return 0xFF;
-}
 
+	while (blkcnt-- > 0) {
 
-static void atapi_inquiry(struct blk_desc *dev_desc)
-{
-	unsigned char ccb[12];	/* Command descriptor block */
-	unsigned char iobuf[64];	/* temp buf */
-	unsigned char c;
-	int device;
+		c = ide_wait(device, IDE_TIME_OUT);
 
-	device = dev_desc->devnum;
-	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
-	dev_desc->block_read = atapi_read;
+		if (c & ATA_STAT_BUSY) {
+			printf("IDE read: device %d not ready\n", device);
+			break;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			ide_outb(device, ATA_SECT_CNT, 0);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb(device, ATA_LBA_MID, 0);
+			ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+		}
+#endif
+		ide_outb(device, ATA_SECT_CNT, 1);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
 
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
 
-	ccb[0] = ATAPI_CMD_INQUIRY;
-	ccb[4] = 40;		/* allocation Legnth */
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 40);
+		} else
+#endif
+		{
+			ide_outb(device, ATA_DEV_HD, ATA_LBA |
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
+		}
 
-	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
-	if (c != 0)
-		return;
+		udelay(50);
 
-	/* copy device ident strings */
-	ident_cpy((unsigned char *) dev_desc->vendor, &iobuf[8], 8);
-	ident_cpy((unsigned char *) dev_desc->product, &iobuf[16], 16);
-	ident_cpy((unsigned char *) dev_desc->revision, &iobuf[32], 5);
+		if (pwrsave) {
+			/* may take up to 4 sec */
+			c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
+			pwrsave = 0;
+		} else {
+			/* can't take over 500 ms */
+			c = ide_wait(device, IDE_TIME_OUT);
+		}
 
-	dev_desc->lun = 0;
-	dev_desc->lba = 0;
-	dev_desc->blksz = 0;
-	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
-	dev_desc->type = iobuf[0] & 0x1f;
+		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+		    ATA_STAT_DRQ) {
+			printf("Error (no IRQ) dev %d blk " LBAF
+			       ": status %#02x\n", device, blknr, c);
+			break;
+		}
 
-	if ((iobuf[1] & 0x80) == 0x80)
-		dev_desc->removable = 1;
-	else
-		dev_desc->removable = 0;
+		ide_input_data(device, buffer, ATA_SECTORWORDS);
+		(void) ide_inb(device, ATA_STATUS);	/* clear IRQ */
 
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	ccb[0] = ATAPI_CMD_START_STOP;
-	ccb[4] = 0x03;		/* start */
+		++n;
+		++blknr;
+		buffer += ATA_BLOCKSIZE;
+	}
+IDE_READ_E:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return n;
+}
 
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
+/* ------------------------------------------------------------------------- */
 
-	debug("ATAPI_CMD_START_STOP returned %x\n", c);
-	if (c != 0)
-		return;
 
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer)
+{
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char c;
 
-	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
-	if (c != 0)
-		return;
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
 
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	ccb[0] = ATAPI_CMD_READ_CAP;
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 8);
-	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
-	if (c != 0)
-		return;
+	if (blknr & 0x0000fffff0000000ULL) {
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
 
-	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
-	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
-	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
 
-	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
-		((unsigned long) iobuf[1] << 16) +
-		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
-	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
-		((unsigned long) iobuf[5] << 16) +
-		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
-	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
-	dev_desc->lba48 = 0;
-#endif
-	return;
-}
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
 
+	while (blkcnt-- > 0) {
+		c = ide_wait(device, IDE_TIME_OUT);
 
-/*
- * atapi_read:
- * we transfer only one block per command, since the multiple DRQ per
- * command is not yet implemented
- */
-#define ATAPI_READ_MAX_BYTES	2048	/* we read max 2kbytes */
-#define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
-#define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
+		if (c & ATA_STAT_BUSY) {
+			printf("IDE read: device %d not ready\n", device);
+			goto WR_OUT;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			ide_outb(device, ATA_SECT_CNT, 0);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb(device, ATA_LBA_MID, 0);
+			ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+		}
+#endif
+		ide_outb(device, ATA_SECT_CNT, 1);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
 
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		 void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char ccb[12];	/* Command descriptor block */
-	ulong cnt;
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
 
-	debug("atapi_read dev %d start " LBAF " blocks " LBAF
-	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+		} else
+#endif
+		{
+			ide_outb(device, ATA_DEV_HD, ATA_LBA |
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
+		}
 
-	do {
-		if (blkcnt > ATAPI_READ_MAX_BLOCK)
-			cnt = ATAPI_READ_MAX_BLOCK;
-		else
-			cnt = blkcnt;
+		udelay(50);
 
-		ccb[0] = ATAPI_CMD_READ_12;
-		ccb[1] = 0;	/* reserved */
-		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
-		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
-		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
-		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
-		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
-		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
-		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
-		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
-		ccb[10] = 0;	/* reserved */
-		ccb[11] = 0;	/* reserved */
+		/* can't take over 500 ms */
+		c = ide_wait(device, IDE_TIME_OUT);
 
-		if (atapi_issue_autoreq(device, ccb, 12,
-					(unsigned char *) buffer,
-					cnt * ATAPI_READ_BLOCK_SIZE)
-		    == 0xFF) {
-			return n;
+		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+		    ATA_STAT_DRQ) {
+			printf("Error (no IRQ) dev %d blk " LBAF
+			       ": status %#02x\n", device, blknr, c);
+			goto WR_OUT;
 		}
-		n += cnt;
-		blkcnt -= cnt;
-		blknr += cnt;
-		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
-	} while (blkcnt > 0);
+
+		ide_output_data(device, buffer, ATA_SECTORWORDS);
+		c = ide_inb(device, ATA_STATUS);	/* clear IRQ */
+		++n;
+		++blknr;
+		buffer += ATA_BLOCKSIZE;
+	}
+WR_OUT:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
 	return n;
 }
 
 /* ------------------------------------------------------------------------- */
 
-#endif /* CONFIG_ATAPI */
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev)
+{
+	if (dev >= CONFIG_SYS_IDE_MAXBUS)
+		return 0;
+	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
+}
+#endif
+/* ------------------------------------------------------------------------- */
 
 U_BOOT_CMD(ide, 5, 1, do_ide,
 	   "IDE sub-system",
-- 
cgit v0.10.2


From 2765c4d147011c9ac80cc014661321829056ee25 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:01 -0600
Subject: dm: sata: Fix code style problems in cmd/sata.c

This file has a few coding style problems. Fix these to make future updates
easier.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/sata.c b/cmd/sata.c
index 8748cce..b1a64d9 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -105,25 +105,27 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	case 1:
 		return CMD_RET_USAGE;
 	case 2:
-		if (strncmp(argv[1],"inf", 3) == 0) {
+		if (strncmp(argv[1], "inf", 3) == 0) {
 			int i;
+
 			putc('\n');
 			for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; ++i) {
 				if (sata_dev_desc[i].type == DEV_TYPE_UNKNOWN)
 					continue;
-				printf ("SATA device %d: ", i);
+				printf("SATA device %d: ", i);
 				dev_print(&sata_dev_desc[i]);
 			}
 			return 0;
-		} else if (strncmp(argv[1],"dev", 3) == 0) {
-			if ((sata_curr_device < 0) || (sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE)) {
+		} else if (strncmp(argv[1], "dev", 3) == 0) {
+			if (sata_curr_device < 0 ||
+			    sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE) {
 				puts("\nno SATA devices available\n");
 				return 1;
 			}
 			printf("\nSATA device %d: ", sata_curr_device);
 			dev_print(&sata_dev_desc[sata_curr_device]);
 			return 0;
-		} else if (strncmp(argv[1],"part",4) == 0) {
+		} else if (strncmp(argv[1], "part", 4) == 0) {
 			int dev, ok;
 
 			for (ok = 0, dev = 0; dev < CONFIG_SYS_SATA_MAX_DEVICE; ++dev) {
-- 
cgit v0.10.2


From c649e3c91cdc96a86ca2665fcfafaca5c4b384b1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:02 -0600
Subject: dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSI

This option currently enables both the command and the SCSI functionality.
Rename the existing option to CONFIG_SCSI since most of the code relates
to the feature.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/README b/README
index 88ff837..33dc788 100644
--- a/README
+++ b/README
@@ -1066,7 +1066,7 @@ The following options need to be configured:
 		CONFIG_CMD_RUN		  run command in env variable
 		CONFIG_CMD_SANDBOX	* sb command to access sandbox features
 		CONFIG_CMD_SAVES	* save S record dump
-		CONFIG_CMD_SCSI		* SCSI Support
+		CONFIG_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
@@ -1254,7 +1254,7 @@ The following options need to be configured:
 		CONFIG_MTD_PARTITIONS  Memory Technology Device partition table.
 
 		If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
-		CONFIG_CMD_SCSI) you must configure support for at
+		CONFIG_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 
 - IDE Reset method:
diff --git a/api/api_storage.c b/api/api_storage.c
index 8c30c56..d425a9a 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -67,7 +67,7 @@ void dev_stor_init(void)
 	specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
 	specs[ENUM_SATA].name = "sata";
 #endif
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
 	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 267bd17..d77c04a 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -82,7 +82,7 @@
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README
index e900c56..f039817 100644
--- a/board/mpl/pip405/README
+++ b/board/mpl/pip405/README
@@ -32,8 +32,8 @@ Changed files:
 - include/cmd_bsp.h		added PIP405 commands definitions
 - include/cmd_condefs.h		added Floppy and SCSI support
 - include/cmd_disk.h		changed to work with block device description
-- include/config_LANTEC.h	excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
-- include/config_hymod.h	excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
+- include/config_LANTEC.h	excluded CONFIG_CMD_FDC and CONFIG_SCSI
+- include/config_hymod.h	excluded CONFIG_CMD_FDC and CONFIG_SCSI
 - include/flash.h		added INTEL_ID_28F320C3T  0x88C488C4
 - include/i2c.h			added "defined(CONFIG_PIP405)"
 - include/image.h		added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
@@ -86,7 +86,7 @@ section "Changes".
 
 New Commands:
 -------------
-CONFIG_CMD_SCSI	SCSI Support
+CONFIG_SCSI	SCSI Support
 CONFIG_CMF_FDC	Floppy disk support
 
 IDE additions:
diff --git a/cmd/Makefile b/cmd/Makefile
index f95759e..6612a3b 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -112,7 +112,7 @@ obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
 obj-$(CONFIG_SANDBOX) += host.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_CMD_SCSI) += scsi.o
+obj-$(CONFIG_SCSI) += scsi.o
 obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
 obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
 obj-$(CONFIG_CMD_SOFTSWITCH) += softswitch.o
@@ -157,7 +157,7 @@ endif # !CONFIG_SPL_BUILD
 
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_SATA_SUPPORT
-obj-$(CONFIG_CMD_SCSI) += scsi.o
+obj-$(CONFIG_SCSI) += scsi.o
 endif
 endif # CONFIG_SPL_BUILD
 
diff --git a/cmd/disk.c b/cmd/disk.c
index 2fd1717..fcc4123 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -8,7 +8,7 @@
 #include <command.h>
 #include <part.h>
 
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_SCSI) || \
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_SCSI) || \
 	defined(CONFIG_USB_STORAGE)
 int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
 		    char *const argv[])
diff --git a/common/board_r.c b/common/board_r.c
index ad02549..d959ad3 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -620,7 +620,7 @@ static int initr_ambapp_print(void)
 }
 #endif
 
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
 static int initr_scsi(void)
 {
 	puts("SCSI:  ");
@@ -923,7 +923,7 @@ init_fnc_t init_sequence_r[] = {
 	initr_ambapp_print,
 #endif
 #endif
-#ifdef CONFIG_CMD_SCSI
+#ifdef CONFIG_SCSI
 	INIT_FUNC_WATCHDOG_RESET
 	initr_scsi,
 #endif
diff --git a/disk/part.c b/disk/part.c
index 543cab8..2613bff 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -28,7 +28,7 @@ const struct block_drvr block_drvr[] = {
 #if defined(CONFIG_CMD_SATA)
 	{.name = "sata", .get_dev = sata_get_dev, },
 #endif
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
 	{ .name = "scsi", .get_dev = scsi_get_dev, },
 #endif
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c
index c7c40af..5daede7 100644
--- a/drivers/block/sym53c8xx.c
+++ b/drivers/block/sym53c8xx.c
@@ -33,7 +33,7 @@
 #define PRINTF(fmt,args...)
 #endif
 
-#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
+#if defined(CONFIG_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
 
 #undef SCSI_SINGLE_STEP
 /*
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 600a90e..826bd85 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1254,7 +1254,7 @@ int file_fat_detectfs(void)
 
 #if defined(CONFIG_CMD_IDE) || \
     defined(CONFIG_CMD_SATA) || \
-    defined(CONFIG_CMD_SCSI) || \
+    defined(CONFIG_SCSI) || \
     defined(CONFIG_CMD_USB) || \
     defined(CONFIG_MMC)
 	printf("Interface:  ");
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index ed502a1..b5fd6c6 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -45,7 +45,7 @@
 #define CONFIG_CMD_READ		/* Read data from partition	*/
 #define CONFIG_CMD_SANDBOX	/* sb command to access sandbox features */
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
-#define CONFIG_CMD_SCSI		/* SCSI Support			*/
+#define CONFIG_SCSI		/* SCSI Support			*/
 #define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
 #define CONFIG_CMD_TERMINAL	/* built-in Serial Terminal	*/
 #define CONFIG_CMD_UBI		/* UBI Support			*/
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 7f67344..5a8d7f2 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -165,7 +165,7 @@
 	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
 #endif
 
-#ifdef CONFIG_CMD_SCSI
+#ifdef CONFIG_SCSI
 #define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
 #define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
 #define BOOTENV_SHARED_SCSI \
@@ -185,9 +185,9 @@
 #define BOOTENV_SET_SCSI_NEED_INIT
 #define BOOTENV_SHARED_SCSI
 #define BOOTENV_DEV_SCSI \
-	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
 #define BOOTENV_DEV_NAME_SCSI \
-	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
 #endif
 
 #ifdef CONFIG_CMD_IDE
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index 2666191..2ad54b7 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -45,7 +45,7 @@
 /* Rather than repeat this expression each time, add a define for it */
 #if defined(CONFIG_CMD_IDE) || \
 	defined(CONFIG_CMD_SATA) || \
-	defined(CONFIG_CMD_SCSI) || \
+	defined(CONFIG_SCSI) || \
 	defined(CONFIG_CMD_USB) || \
 	defined(CONFIG_CMD_PART) || \
 	defined(CONFIG_CMD_GPT) || \
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 26d92da..f3036c1 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -373,7 +373,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
-    #define CONFIG_CMD_SCSI
+    #define CONFIG_SCSI
 #endif
 
 /*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 8c4e5e2..bb7f38e 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -576,7 +576,7 @@
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 /*
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index e7f01d0..f6d45a9 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -449,7 +449,7 @@
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 #define CONFIG_WATCHDOG			/* watchdog enabled */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 5e23007..9b2623c 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -610,7 +610,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
-    #define CONFIG_CMD_SCSI
+    #define CONFIG_SCSI
 #endif
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 4bd06a4..4506d86 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -43,7 +43,7 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_FDC
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SAVES
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 32d7d4d..d53b0fd 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -75,7 +75,7 @@
 
 /* SATA */
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index 9b13aa6..ac6103c 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -60,7 +60,7 @@
 #define CONFIG_SPL_SATA_BOOT_DEVICE		0
 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
 
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index d84dde3..3539a62 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -27,7 +27,7 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 
 /* I2C */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 79b6c09..8a0cd66 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -230,7 +230,7 @@
 
 /* SATA */
 #define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h
index 6dd0b32..95e46c5 100644
--- a/include/configs/efi-x86.h
+++ b/include/configs/efi-x86.h
@@ -18,7 +18,7 @@
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
 #undef CONFIG_INTEL_ICH6_GPIO
 #undef CONFIG_USB_EHCI_PCI
 
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 2f1f6d4..40f7fba 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -29,7 +29,7 @@
 
 /* SATA is not supported in Quark SoC */
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
 
 /* Video is not supported in Quark SoC */
 #undef CONFIG_VIDEO
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 3bce12b..5cefddc 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -51,7 +51,7 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 
 #define CONFIG_BOOT_RETRY_TIME		-1
 #define CONFIG_RESET_TO_RETRY
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index d71a229..af1f73d 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -108,7 +108,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 2d7567f..f8c9e51 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -44,7 +44,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 5bec509..4577919 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -62,7 +62,7 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 86cefa3..4ddc492 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -115,7 +115,7 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index b0d2ffe..476d37d 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -43,7 +43,7 @@
 #define CONFIG_ATAPI
 
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
 #else
 #define CONFIG_SCSI_DEV_LIST		\
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 2406115..ac2d931 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -125,7 +125,7 @@
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 #define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index a2822e0..b79f47b 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -100,7 +100,7 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 
 #define CONFIG_CMD_ZBOOT
 
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 060bca9..6b8e3ea 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -201,7 +201,7 @@
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 					 CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
 #endif
 
 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
-- 
cgit v0.10.2


From 6eef6eac1fc137c97bf1993304ed83b8e483c80a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:03 -0600
Subject: dm: blk: Add a legacy block interface

There is quite a bit of duplicated common code related to block devices
in the IDE and SCSI implementations.

Create some helper functions that can be used to reduce the duplication.
These rely on a linker list of interface-type drivers

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 3f75934..436b79f 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -7,6 +7,10 @@
 
 obj-$(CONFIG_BLK) += blk-uclass.o
 
+ifndef CONFIG_BLK
+obj-y += blk_legacy.o
+endif
+
 obj-$(CONFIG_AHCI) += ahci-uclass.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
diff --git a/drivers/block/blk_legacy.c b/drivers/block/blk_legacy.c
new file mode 100644
index 0000000..7b90a8a
--- /dev/null
+++ b/drivers/block/blk_legacy.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+
+struct blk_driver *blk_driver_lookup_type(int if_type)
+{
+	struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+	const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+	struct blk_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (if_type == entry->if_type)
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
+static struct blk_driver *blk_driver_lookup_typename(const char *if_typename)
+{
+	struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+	const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+	struct blk_driver *entry;
+
+	for (entry = drv; entry != drv + n_ents; entry++) {
+		if (!strcmp(if_typename, entry->if_typename))
+			return entry;
+	}
+
+	/* Not found */
+	return NULL;
+}
+
+/**
+ * get_desc() - Get the block device descriptor for the given device number
+ *
+ * @drv:	Legacy block driver
+ * @devnum:	Device number (0 = first)
+ * @descp:	Returns block device descriptor on success
+ * @return 0 on success, -ENODEV if there is no such device, -ENOSYS if the
+ * driver does not provide a way to find a device, or other -ve on other
+ * error.
+ */
+static int get_desc(struct blk_driver *drv, int devnum, struct blk_desc **descp)
+{
+	if (drv->desc) {
+		if (devnum < 0 || devnum >= drv->max_devs)
+			return -ENODEV;
+		*descp = &drv->desc[devnum];
+		return 0;
+	}
+	if (!drv->get_dev)
+		return -ENOSYS;
+
+	return drv->get_dev(devnum, descp);
+}
+
+#ifdef HAVE_BLOCK_DEVICE
+int blk_list_part(enum if_type if_type)
+{
+	struct blk_driver *drv;
+	struct blk_desc *desc;
+	int devnum, ok;
+	bool first = true;
+
+	drv = blk_driver_lookup_type(if_type);
+	if (!drv)
+		return -ENOSYS;
+	for (ok = 0, devnum = 0; devnum < drv->max_devs; ++devnum) {
+		if (get_desc(drv, devnum, &desc))
+			continue;
+		if (desc->part_type != PART_TYPE_UNKNOWN) {
+			++ok;
+			if (!first)
+				putc('\n');
+			part_print(desc);
+			first = false;
+		}
+	}
+	if (!ok)
+		return -ENODEV;
+
+	return 0;
+}
+
+int blk_print_part_devnum(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+	part_print(desc);
+
+	return 0;
+}
+
+void blk_list_devices(enum if_type if_type)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int i;
+
+	if (!drv)
+		return;
+	for (i = 0; i < drv->max_devs; ++i) {
+		if (get_desc(drv, i, &desc))
+			continue;
+		if (desc->type == DEV_TYPE_UNKNOWN)
+			continue;  /* list only known devices */
+		printf("Device %d: ", i);
+		dev_print(desc);
+	}
+}
+
+int blk_print_device_num(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	printf("\n%s device %d: ", drv->if_typename, devnum);
+	dev_print(desc);
+
+	return 0;
+}
+
+int blk_show_device(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	printf("\nDevice %d: ", devnum);
+	if (devnum >= drv->max_devs) {
+		puts("unknown device\n");
+		return -ENODEV;
+	}
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	dev_print(desc);
+
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+
+	return 0;
+}
+#endif /* HAVE_BLOCK_DEVICE */
+
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+
+	if (!drv)
+		return NULL;
+
+	if (get_desc(drv, devnum, &desc))
+		return NULL;
+
+	return desc;
+}
+
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(desc->if_type);
+
+	if (!drv)
+		return -ENOSYS;
+	if (drv->select_hwpart)
+		return drv->select_hwpart(desc, hwpart);
+
+	return 0;
+}
+
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum)
+{
+	struct blk_driver *drv = blk_driver_lookup_typename(if_typename);
+	struct blk_desc *desc;
+
+	if (!drv)
+		return NULL;
+
+	if (get_desc(drv, devnum, &desc))
+		return NULL;
+
+	return desc;
+}
+
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	ulong n;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	n = desc->block_read(desc, start, blkcnt, buffer);
+	if (IS_ERR_VALUE(n))
+		return n;
+
+	/* flush cache after read */
+	flush_cache((ulong)buffer, blkcnt * desc->blksz);
+
+	return n;
+}
+
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	return desc->block_write(desc, start, blkcnt, buffer);
+}
+
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart)
+{
+	struct blk_driver *drv = blk_driver_lookup_type(if_type);
+	struct blk_desc *desc;
+	int ret;
+
+	if (!drv)
+		return -ENOSYS;
+	ret = get_desc(drv, devnum, &desc);
+	if (ret)
+		return ret;
+	return drv->select_hwpart(desc, hwpart);
+}
diff --git a/include/blk.h b/include/blk.h
index f624671..a562c10 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -340,6 +340,201 @@ static inline ulong blk_derase(struct blk_desc *block_dev, lbaint_t start,
 	blkcache_invalidate(block_dev->if_type, block_dev->devnum);
 	return block_dev->block_erase(block_dev, start, blkcnt);
 }
+
+/**
+ * struct blk_driver - Driver for block interface types
+ *
+ * This provides access to the block devices for each interface type. One
+ * driver should be provided using U_BOOT_LEGACY_BLK() for each interface
+ * type that is to be supported.
+ *
+ * @if_typename:	Interface type name
+ * @if_type:		Interface type
+ * @max_devs:		Maximum number of devices supported
+ * @desc:		Pointer to list of devices for this interface type,
+ *			or NULL to use @get_dev() instead
+ */
+struct blk_driver {
+	const char *if_typename;
+	enum if_type if_type;
+	int max_devs;
+	struct blk_desc *desc;
+	/**
+	 * get_dev() - get a pointer to a block device given its number
+	 *
+	 * Each interface allocates its own devices and typically
+	 * struct blk_desc is contained with the interface's data structure.
+	 * There is no global numbering for block devices. This method allows
+	 * the device for an interface type to be obtained when @desc is NULL.
+	 *
+	 * @devnum:	Device number (0 for first device on that interface,
+	 *		1 for second, etc.
+	 * @descp:	Returns pointer to the block device on success
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_dev)(int devnum, struct blk_desc **descp);
+
+	/**
+	 * select_hwpart() - Select a hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 * Partition 0 is the main user-data partition.
+	 *
+	 * @desc:	Block device descriptor
+	 * @hwpart:	Hardware partition number to select. 0 means the main
+	 *		user-data partition, 1 is the first partition, 2 is
+	 *		the second, etc.
+	 * @return 0 if OK, other value for an error
+	 */
+	int (*select_hwpart)(struct blk_desc *desc, int hwpart);
+};
+
+/*
+ * Declare a new U-Boot legacy block driver. New drivers should use driver
+ * model (UCLASS_BLK).
+ */
+#define U_BOOT_LEGACY_BLK(__name)					\
+	ll_entry_declare(struct blk_driver, __name, blk_driver)
+
+struct blk_driver *blk_driver_lookup_type(int if_type);
+
 #endif /* !CONFIG_BLK */
 
+/**
+ * blk_get_devnum_by_typename() - Get a block device by type and number
+ *
+ * This looks through the available block devices of the given type, returning
+ * the one with the given @devnum.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum);
+
+/**
+ * blk_get_devnum_by_type() - Get a block device by type name, and number
+ *
+ * This looks up the block device type based on @if_typename, then calls
+ * blk_get_devnum_by_type().
+ *
+ * @if_typename:	Block device type name
+ * @devnum:		Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename,
+					    int devnum);
+
+/**
+ * blk_dselect_hwpart() - select a hardware partition
+ *
+ * This selects a hardware partition (such as is supported by MMC). The block
+ * device size may change as this effectively points the block device to a
+ * partition at the hardware level. See the select_hwpart() method above.
+ *
+ * @desc:	Block device descriptor for the device to select
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart);
+
+/**
+ * blk_list_part() - list the partitions for block devices of a given type
+ *
+ * This looks up the partition type for each block device of type @if_type,
+ * then displays a list of partitions.
+ *
+ * @if_type:	Block device type
+ * @return 0 if OK, -ENODEV if there is none of that type
+ */
+int blk_list_part(enum if_type if_type);
+
+/**
+ * blk_list_devices() - list the block devices of a given type
+ *
+ * This lists each block device of the type @if_type, showing the capacity
+ * as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ */
+void blk_list_devices(enum if_type if_type);
+
+/**
+ * blk_show_device() - show information about a given block device
+ *
+ * This shows the block device capacity as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number
+ */
+int blk_show_device(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_device_num() - show information about a given block device
+ *
+ * This is similar to blk_show_device() but returns an error if the block
+ * device type is unknown.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number, -ENOENT if the block
+ * device is not connected
+ */
+int blk_print_device_num(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_part_devnum() - print the partition information for a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENOENT if the block device is not connected, -ENOSYS if
+ * the interface type is not supported, other -ve on other error
+ */
+int blk_print_part_devnum(enum if_type if_type, int devnum);
+
+/**
+ * blk_read_devnum() - read blocks from a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to read
+ * @buffer:	Address to write data to
+ * @return number of blocks read, or -ve error number on error
+ */
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer);
+
+/**
+ * blk_write_devnum() - write blocks to a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to write
+ * @buffer:	Address to read data from
+ * @return number of blocks written, or -ve error number on error
+ */
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer);
+
+/**
+ * blk_select_hwpart_devnum() - select a hardware partition
+ *
+ * This is similar to blk_dselect_hwpart() but it looks up the interface and
+ * device number.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
+
 #endif
-- 
cgit v0.10.2


From 3ef85e377201c1ebe84e74bfb785c95ccbc37b13 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:04 -0600
Subject: dm: systemace: Add a legacy block interface

Add a legacy block interface for systemace.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 09fe834..0d8e26f 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -132,6 +132,13 @@ struct blk_desc *systemace_get_dev(int dev)
 }
 #endif
 
+static int systemace_get_devp(int dev, struct blk_desc **descp)
+{
+	*descp = systemace_get_dev(dev);
+
+	return 0;
+}
+
 /*
  * This function is called (by dereferencing the block_read pointer in
  * the dev_desc) to read blocks of data. The return value is the
@@ -257,3 +264,10 @@ static unsigned long systemace_read(struct blk_desc *block_dev,
 
 	return blkcnt;
 }
+
+U_BOOT_LEGACY_BLK(systemace) = {
+	.if_typename	= "ace",
+	.if_type	= IF_TYPE_SYSTEMACE,
+	.max_devs	= 1,
+	.get_dev	= systemace_get_devp,
+};
diff --git a/include/blk.h b/include/blk.h
index a562c10..2caac9c 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -30,6 +30,7 @@ enum if_type {
 	IF_TYPE_SD,
 	IF_TYPE_SATA,
 	IF_TYPE_HOST,
+	IF_TYPE_SYSTEMACE,
 
 	IF_TYPE_COUNT,			/* Number of interface types */
 };
-- 
cgit v0.10.2


From 0cc65a7cc23bfbaab709d8934a6b8c73084852ea Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:05 -0600
Subject: dm: sandbox: Add a legacy host block interface

Add a legacy block interface for sandbox host.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 6d41508..2b6a893 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -239,4 +239,11 @@ U_BOOT_DRIVER(sandbox_host_blk) = {
 	.ops		= &sandbox_host_blk_ops,
 	.priv_auto_alloc_size	= sizeof(struct host_block_dev),
 };
+#else
+U_BOOT_LEGACY_BLK(sandbox_host) = {
+	.if_typename	= "host",
+	.if_type	= IF_TYPE_HOST,
+	.max_devs	= CONFIG_HOST_MAX_DEVICES,
+	.get_dev	= host_get_dev_err,
+};
 #endif
-- 
cgit v0.10.2


From c0543bf6be4bac277d65c601f9150c7faf3d125e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:06 -0600
Subject: dm: usb: Add a legacy block interface for USB storage

Add a legacy block interface for USB storage.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/usb_storage.c b/common/usb_storage.c
index 9285c95..80bf3db 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -1555,4 +1555,11 @@ U_BOOT_DRIVER(usb_storage_blk) = {
 	.id		= UCLASS_BLK,
 	.ops		= &usb_storage_ops,
 };
+#else
+U_BOOT_LEGACY_BLK(usb) = {
+	.if_typename	= "usb",
+	.if_type	= IF_TYPE_USB,
+	.max_devs	= USB_MAX_STOR_DEV,
+	.desc		= usb_dev_desc,
+};
 #endif
-- 
cgit v0.10.2


From 663acabdc548216d61a9d2b1f789d4e6606f7a52 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:07 -0600
Subject: dm: mmc: Add a legacy block interface for MMC

Add a legacy block interface for MMC.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d3c22ab..024368c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1582,14 +1582,31 @@ void mmc_destroy(struct mmc *mmc)
 	free(mmc);
 }
 
+static int mmc_get_devp(int dev, struct blk_desc **descp)
+{
+	struct mmc *mmc = find_mmc_device(dev);
+	int ret;
+
+	if (!mmc)
+		return -ENODEV;
+	ret = mmc_init(mmc);
+	if (ret)
+		return ret;
+
+	*descp = &mmc->block_dev;
+
+	return 0;
+}
+
 #ifdef CONFIG_PARTITIONS
 struct blk_desc *mmc_get_dev(int dev)
 {
-	struct mmc *mmc = find_mmc_device(dev);
-	if (!mmc || mmc_init(mmc))
+	struct blk_desc *desc;
+
+	if (mmc_get_devp(dev, &desc))
 		return NULL;
 
-	return &mmc->block_dev;
+	return desc;
 }
 #endif
 
@@ -1965,3 +1982,10 @@ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
 			  enable);
 }
 #endif
+
+U_BOOT_LEGACY_BLK(mmc) = {
+	.if_typename	= "mmc",
+	.if_type	= IF_TYPE_MMC,
+	.max_devs	= -1,
+	.get_dev	= mmc_get_devp,
+};
-- 
cgit v0.10.2


From d508c82ba90dd92fa3b70875d3419c9d1b5493c0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:08 -0600
Subject: dm: mmc: Add an implementation of the 'devnum' functions

Now that the MMC code accesses devices by number, we can implement this same
interface for driver model, allowing MMC to support using driver model for
block devices.

Add the required functions to the uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 617db22..3687b9a 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -11,6 +11,286 @@
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 
+static const char *if_typename_str[IF_TYPE_COUNT] = {
+	[IF_TYPE_IDE]		= "ide",
+	[IF_TYPE_SCSI]		= "scsi",
+	[IF_TYPE_ATAPI]		= "atapi",
+	[IF_TYPE_USB]		= "usb",
+	[IF_TYPE_DOC]		= "doc",
+	[IF_TYPE_MMC]		= "mmc",
+	[IF_TYPE_SD]		= "sd",
+	[IF_TYPE_SATA]		= "sata",
+	[IF_TYPE_HOST]		= "host",
+	[IF_TYPE_SYSTEMACE]	= "ace",
+};
+
+static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
+	[IF_TYPE_IDE]		= UCLASS_INVALID,
+	[IF_TYPE_SCSI]		= UCLASS_INVALID,
+	[IF_TYPE_ATAPI]		= UCLASS_INVALID,
+	[IF_TYPE_USB]		= UCLASS_MASS_STORAGE,
+	[IF_TYPE_DOC]		= UCLASS_INVALID,
+	[IF_TYPE_MMC]		= UCLASS_MMC,
+	[IF_TYPE_SD]		= UCLASS_INVALID,
+	[IF_TYPE_SATA]		= UCLASS_AHCI,
+	[IF_TYPE_HOST]		= UCLASS_ROOT,
+	[IF_TYPE_SYSTEMACE]	= UCLASS_INVALID,
+};
+
+static enum if_type if_typename_to_iftype(const char *if_typename)
+{
+	int i;
+
+	for (i = 0; i < IF_TYPE_COUNT; i++) {
+		if (if_typename_str[i] &&
+		    !strcmp(if_typename, if_typename_str[i]))
+			return i;
+	}
+
+	return IF_TYPE_UNKNOWN;
+}
+
+static enum uclass_id if_type_to_uclass_id(enum if_type if_type)
+{
+	return if_type_uclass_id[if_type];
+}
+
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	struct udevice *dev;
+	int ret;
+
+	ret = blk_get_device(if_type, devnum, &dev);
+	if (ret)
+		return NULL;
+	desc = dev_get_uclass_platdata(dev);
+
+	return desc;
+}
+
+/*
+ * This function is complicated with driver model. We look up the interface
+ * name in a local table. This gives us an interface type which we can match
+ * against the uclass of the block device's parent.
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum)
+{
+	enum uclass_id uclass_id;
+	enum if_type if_type;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	if_type = if_typename_to_iftype(if_typename);
+	if (if_type == IF_TYPE_UNKNOWN) {
+		debug("%s: Unknown interface type '%s'\n", __func__,
+		      if_typename);
+		return NULL;
+	}
+	uclass_id = if_type_to_uclass_id(if_type);
+	if (uclass_id == UCLASS_INVALID) {
+		debug("%s: Unknown uclass for interface type'\n",
+		      if_typename_str[if_type]);
+		return NULL;
+	}
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return NULL;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+		      if_type, devnum, dev->name, desc->if_type, desc->devnum);
+		if (desc->devnum != devnum)
+			continue;
+
+		/* Find out the parent device uclass */
+		if (device_get_uclass_id(dev->parent) != uclass_id) {
+			debug("%s: parent uclass %d, this dev %d\n", __func__,
+			      device_get_uclass_id(dev->parent), uclass_id);
+			continue;
+		}
+
+		if (device_probe(dev))
+			return NULL;
+
+		debug("%s: Device desc %p\n", __func__, desc);
+		return desc;
+	}
+	debug("%s: No device found\n", __func__);
+
+	return NULL;
+}
+
+/**
+ * get_desc() - Get the block device descriptor for the given device number
+ *
+ * @if_type:	Interface type
+ * @devnum:	Device number (0 = first)
+ * @descp:	Returns block device descriptor on success
+ * @return 0 on success, -ENODEV if there is no such device and no device
+ * with a higher device number, -ENOENT if there is no such device but there
+ * is one with a higher number, or other -ve on other error.
+ */
+static int get_desc(enum if_type if_type, int devnum, struct blk_desc **descp)
+{
+	bool found_more = false;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	*descp = NULL;
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+		      if_type, devnum, dev->name, desc->if_type, desc->devnum);
+		if (desc->if_type == if_type) {
+			if (desc->devnum == devnum) {
+				ret = device_probe(dev);
+				if (ret)
+					return ret;
+
+			} else if (desc->devnum > devnum) {
+				found_more = true;
+			}
+		}
+	}
+
+	return found_more ? -ENOENT : -ENODEV;
+}
+
+int blk_list_part(enum if_type if_type)
+{
+	struct blk_desc *desc;
+	int devnum, ok;
+	int ret;
+
+	for (ok = 0, devnum = 0;; ++devnum) {
+		ret = get_desc(if_type, devnum, &desc);
+		if (ret == -ENODEV)
+			break;
+		else if (ret)
+			continue;
+		if (desc->part_type != PART_TYPE_UNKNOWN) {
+			++ok;
+			if (devnum)
+				putc('\n');
+			part_print(desc);
+		}
+	}
+	if (!ok)
+		return -ENODEV;
+
+	return 0;
+}
+
+int blk_print_part_devnum(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+	part_print(desc);
+
+	return 0;
+}
+
+void blk_list_devices(enum if_type if_type)
+{
+	struct blk_desc *desc;
+	int ret;
+	int i;
+
+	for (i = 0;; ++i) {
+		ret = get_desc(if_type, i, &desc);
+		if (ret == -ENODEV)
+			break;
+		else if (ret)
+			continue;
+		if (desc->type == DEV_TYPE_UNKNOWN)
+			continue;  /* list only known devices */
+		printf("Device %d: ", i);
+		dev_print(desc);
+	}
+}
+
+int blk_print_device_num(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	printf("\nIDE device %d: ", devnum);
+	dev_print(desc);
+
+	return 0;
+}
+
+int blk_show_device(enum if_type if_type, int devnum)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	printf("\nDevice %d: ", devnum);
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret == -ENODEV || ret == -ENOENT) {
+		printf("unknown device\n");
+		return -ENODEV;
+	}
+	if (ret)
+		return ret;
+	dev_print(desc);
+
+	if (desc->type == DEV_TYPE_UNKNOWN)
+		return -ENOENT;
+
+	return 0;
+}
+
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer)
+{
+	struct blk_desc *desc;
+	ulong n;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	n = blk_dread(desc, start, blkcnt, buffer);
+	if (IS_ERR_VALUE(n))
+		return n;
+
+	/* flush cache after read */
+	flush_cache((ulong)buffer, blkcnt * desc->blksz);
+
+	return n;
+}
+
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer)
+{
+	struct blk_desc *desc;
+	int ret;
+
+	ret = get_desc(if_type, devnum, &desc);
+	if (ret)
+		return ret;
+	return blk_dwrite(desc, start, blkcnt, buffer);
+}
+
 int blk_first_device(int if_type, struct udevice **devp)
 {
 	struct blk_desc *desc;
-- 
cgit v0.10.2


From 11f610edf01abc96ca10e82e1752648ee911705b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:09 -0600
Subject: dm: scsi: Separate the non-command code into its own file

At present the SCSI command code includes both the command-processing code
and the core SCSI functions and data structures.

Separate the latter into its own file, adding functions as needed to avoid
the command code accessing data structures directly. This functions use the
new legacy block functions.

With this commit:
- There is no CONFIG option referenced from the command code
- The concept of a 'current SCSI device' is confined to the command code

This will make it easier to convert this code to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/Makefile b/cmd/Makefile
index 6612a3b..e3e0c74 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -155,12 +155,6 @@ obj-$(CONFIG_CMD_PMIC) += pmic.o
 obj-$(CONFIG_CMD_REGULATOR) += regulator.o
 endif # !CONFIG_SPL_BUILD
 
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_SATA_SUPPORT
-obj-$(CONFIG_SCSI) += scsi.o
-endif
-endif # CONFIG_SPL_BUILD
-
 obj-$(CONFIG_CMD_BLOB) += blob.o
 
 # core command
diff --git a/cmd/scsi.c b/cmd/scsi.c
index 751fc58..387ca1a 100644
--- a/cmd/scsi.c
+++ b/cmd/scsi.c
@@ -10,355 +10,27 @@
  */
 #include <common.h>
 #include <command.h>
-#include <inttypes.h>
-#include <asm/processor.h>
 #include <scsi.h>
-#include <image.h>
-#include <pci.h>
-
-#ifdef CONFIG_SCSI_DEV_LIST
-#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
-#else
-#ifdef CONFIG_SCSI_SYM53C8XX
-#define SCSI_VEND_ID	0x1000
-#ifndef CONFIG_SCSI_DEV_ID
-#define SCSI_DEV_ID		0x0001
-#else
-#define SCSI_DEV_ID		CONFIG_SCSI_DEV_ID
-#endif
-#elif defined CONFIG_SATA_ULI5288
-
-#define SCSI_VEND_ID 0x10b9
-#define SCSI_DEV_ID  0x5288
-
-#elif !defined(CONFIG_SCSI_AHCI_PLAT)
-#error no scsi device defined
-#endif
-#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
-const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
-#endif
-static ccb tempccb;	/* temporary scsi command buffer */
-
-static unsigned char tempbuff[512]; /* temporary data buffer */
-
-static int scsi_max_devs; /* number of highest available scsi device */
 
 static int scsi_curr_dev; /* current device */
 
-static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
-
-/* almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_READ_BLK 0xFFFF
-#define SCSI_LBA48_READ	0xFFFFFFF
-
-#ifdef CONFIG_SYS_64BIT_LBA
-void scsi_setup_read16(ccb *pccb, lbaint_t start, unsigned long blocks)
-{
-	pccb->cmd[0] = SCSI_READ16;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff;
-	pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff;
-	pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff;
-	pccb->cmd[5] = (unsigned char)(start >> 32) & 0xff;
-	pccb->cmd[6] = (unsigned char)(start >> 24) & 0xff;
-	pccb->cmd[7] = (unsigned char)(start >> 16) & 0xff;
-	pccb->cmd[8] = (unsigned char)(start >> 8) & 0xff;
-	pccb->cmd[9] = (unsigned char)start & 0xff;
-	pccb->cmd[10] = 0;
-	pccb->cmd[11] = (unsigned char)(blocks >> 24) & 0xff;
-	pccb->cmd[12] = (unsigned char)(blocks >> 16) & 0xff;
-	pccb->cmd[13] = (unsigned char)(blocks >> 8) & 0xff;
-	pccb->cmd[14] = (unsigned char)blocks & 0xff;
-	pccb->cmd[15] = 0;
-	pccb->cmdlen = 16;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-	debug("scsi_setup_read16: cmd: %02X %02X startblk %02X%02X%02X%02X%02X%02X%02X%02X blccnt %02X%02X%02X%02X\n",
-	      pccb->cmd[0], pccb->cmd[1],
-	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-	      pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
-	      pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
-}
-#endif
-
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0] = SCSI_READ10;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
-	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
-	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
-	pccb->cmd[5] = (unsigned char)start & 0xff;
-	pccb->cmd[6] = 0;
-	pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
-	pccb->cmd[8] = (unsigned char)blocks & 0xff;
-	pccb->cmd[6] = 0;
-	pccb->cmdlen=10;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-	debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
-		pccb->cmd[0],pccb->cmd[1],
-		pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5],
-		pccb->cmd[7],pccb->cmd[8]);
-}
-
-void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0] = SCSI_WRITE10;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
-	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
-	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
-	pccb->cmd[5] = (unsigned char)start & 0xff;
-	pccb->cmd[6] = 0;
-	pccb->cmd[7] = ((unsigned char)(blocks >> 8)) & 0xff;
-	pccb->cmd[8] = (unsigned char)blocks & 0xff;
-	pccb->cmd[9] = 0;
-	pccb->cmdlen = 10;
-	pccb->msgout[0] = SCSI_IDENTIFY;  /* NOT USED */
-	debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
-	      __func__,
-	      pccb->cmd[0], pccb->cmd[1],
-	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
-	      pccb->cmd[7], pccb->cmd[8]);
-}
-
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
-	pccb->cmd[0] = SCSI_READ6;
-	pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
-	pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
-	pccb->cmd[3] = (unsigned char)start & 0xff;
-	pccb->cmd[4] = (unsigned char)blocks & 0xff;
-	pccb->cmd[5] = 0;
-	pccb->cmdlen=6;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-	debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
-	      pccb->cmd[0], pccb->cmd[1],
-	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
-}
-
-
-void scsi_setup_inquiry(ccb * pccb)
-{
-	pccb->cmd[0] = SCSI_INQUIRY;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = 0;
-	pccb->cmd[3] = 0;
-	if (pccb->datalen > 255)
-		pccb->cmd[4] = 255;
-	else
-		pccb->cmd[4] = (unsigned char)pccb->datalen;
-	pccb->cmd[5] = 0;
-	pccb->cmdlen=6;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-}
-
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
-		       lbaint_t blkcnt, void *buffer)
-{
-	int device = block_dev->devnum;
-	lbaint_t start, blks;
-	uintptr_t buf_addr;
-	unsigned short smallblks = 0;
-	ccb* pccb=(ccb *)&tempccb;
-	device&=0xff;
-
-	/* Setup device */
-	pccb->target = scsi_dev_desc[device].target;
-	pccb->lun = scsi_dev_desc[device].lun;
-	buf_addr = (unsigned long)buffer;
-	start = blknr;
-	blks = blkcnt;
-	debug("\nscsi_read: dev %d startblk " LBAF
-	      ", blccnt " LBAF " buffer %lx\n",
-	      device, start, blks, (unsigned long)buffer);
-	do {
-		pccb->pdata = (unsigned char *)buf_addr;
-#ifdef CONFIG_SYS_64BIT_LBA
-		if (start > SCSI_LBA48_READ) {
-			unsigned long blocks;
-			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
-			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
-			scsi_setup_read16(pccb, start, blocks);
-			start += blocks;
-			blks -= blocks;
-		} else
-#endif
-		if (blks > SCSI_MAX_READ_BLK) {
-			pccb->datalen = scsi_dev_desc[device].blksz *
-				SCSI_MAX_READ_BLK;
-			smallblks = SCSI_MAX_READ_BLK;
-			scsi_setup_read_ext(pccb, start, smallblks);
-			start += SCSI_MAX_READ_BLK;
-			blks -= SCSI_MAX_READ_BLK;
-		}
-		else {
-			pccb->datalen = scsi_dev_desc[device].blksz * blks;
-			smallblks = (unsigned short)blks;
-			scsi_setup_read_ext(pccb, start, smallblks);
-			start += blks;
-			blks=0;
-		}
-		debug("scsi_read_ext: startblk " LBAF
-		      ", blccnt %x buffer %" PRIXPTR "\n",
-		      start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != true) {
-			scsi_print_error(pccb);
-			blkcnt -= blks;
-			break;
-		}
-		buf_addr+=pccb->datalen;
-	} while (blks != 0);
-	debug("scsi_read_ext: end startblk " LBAF
-	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
-	return blkcnt;
-}
-
-/*******************************************************************************
- * scsi_write
- */
-
-/* Almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_WRITE_BLK 0xFFFF
-
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
-			lbaint_t blkcnt, const void *buffer)
-{
-	int device = block_dev->devnum;
-	lbaint_t start, blks;
-	uintptr_t buf_addr;
-	unsigned short smallblks;
-	ccb* pccb = (ccb *)&tempccb;
-	device &= 0xff;
-	/* Setup  device
-	 */
-	pccb->target = scsi_dev_desc[device].target;
-	pccb->lun = scsi_dev_desc[device].lun;
-	buf_addr = (unsigned long)buffer;
-	start = blknr;
-	blks = blkcnt;
-	debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
-	      __func__, device, start, blks, (unsigned long)buffer);
-	do {
-		pccb->pdata = (unsigned char *)buf_addr;
-		if (blks > SCSI_MAX_WRITE_BLK) {
-			pccb->datalen = (scsi_dev_desc[device].blksz *
-					 SCSI_MAX_WRITE_BLK);
-			smallblks = SCSI_MAX_WRITE_BLK;
-			scsi_setup_write_ext(pccb, start, smallblks);
-			start += SCSI_MAX_WRITE_BLK;
-			blks -= SCSI_MAX_WRITE_BLK;
-		} else {
-			pccb->datalen = scsi_dev_desc[device].blksz * blks;
-			smallblks = (unsigned short)blks;
-			scsi_setup_write_ext(pccb, start, smallblks);
-			start += blks;
-			blks = 0;
-		}
-		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
-		      __func__, start, smallblks, buf_addr);
-		if (scsi_exec(pccb) != true) {
-			scsi_print_error(pccb);
-			blkcnt -= blks;
-			break;
-		}
-		buf_addr += pccb->datalen;
-	} while (blks != 0);
-	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
-	      __func__, start, smallblks, buf_addr);
-	return blkcnt;
-}
-
-int scsi_get_disk_count(void)
-{
-	return scsi_max_devs;
-}
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
-void scsi_init(void)
-{
-	int busdevfunc = -1;
-	int i;
-	/*
-	 * Find a device from the list, this driver will support a single
-	 * controller.
-	 */
-	for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
-		/* get PCI Device ID */
-#ifdef CONFIG_DM_PCI
-		struct udevice *dev;
-		int ret;
-
-		ret = dm_pci_find_device(scsi_device_list[i].vendor,
-					 scsi_device_list[i].device, 0, &dev);
-		if (!ret) {
-			busdevfunc = dm_pci_get_bdf(dev);
-			break;
-		}
-#else
-		busdevfunc = pci_find_device(scsi_device_list[i].vendor,
-					     scsi_device_list[i].device,
-					     0);
-#endif
-		if (busdevfunc != -1)
-			break;
-	}
-
-	if (busdevfunc == -1) {
-		printf("Error: SCSI Controller(s) ");
-		for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
-			printf("%04X:%04X ",
-			       scsi_device_list[i].vendor,
-			       scsi_device_list[i].device);
-		}
-		printf("not found\n");
-		return;
-	}
-#ifdef DEBUG
-	else {
-		printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
-		       scsi_device_list[i].vendor,
-		       scsi_device_list[i].device,
-		       (busdevfunc >> 16) & 0xFF,
-		       (busdevfunc >> 11) & 0x1F,
-		       (busdevfunc >> 8) & 0x7);
-	}
-#endif
-	bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
-	scsi_low_level_init(busdevfunc);
-	scsi_scan(1);
-	bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
-}
-#endif
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *scsi_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/******************************************************************************
+/*
  * scsi boot command intepreter. Derived from diskboot
  */
-int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	return common_diskboot(cmdtp, "scsi", argc, argv);
 }
 
-/*********************************************************************************
+/*
  * scsi command intepreter
  */
-int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	switch (argc) {
 	case 0:
 	case 1:
 		return CMD_RET_USAGE;
-
 	case 2:
 		if (strncmp(argv[1], "res", 3) == 0) {
 			printf("\nReset SCSI\n");
@@ -367,23 +39,15 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 0;
 		}
 		if (strncmp(argv[1], "inf", 3) == 0) {
-			int i;
-			for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; ++i) {
-				if (scsi_dev_desc[i].type == DEV_TYPE_UNKNOWN)
-					continue; /* list only known devices */
-				printf("SCSI dev. %d:  ", i);
-				dev_print(&scsi_dev_desc[i]);
-			}
+			blk_list_devices(IF_TYPE_SCSI);
 			return 0;
 		}
 		if (strncmp(argv[1], "dev", 3) == 0) {
-			if (scsi_curr_dev < 0 ||
-			    scsi_curr_dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
+			if (blk_print_device_num(IF_TYPE_SCSI, scsi_curr_dev)) {
 				printf("\nno SCSI devices available\n");
-				return 1;
+				return CMD_RET_FAILURE;
 			}
-			printf("\n    Device %d: ", scsi_curr_dev);
-			dev_print(&scsi_dev_desc[scsi_curr_dev]);
+
 			return 0;
 		}
 		if (strncmp(argv[1], "scan", 4) == 0) {
@@ -391,46 +55,32 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 0;
 		}
 		if (strncmp(argv[1], "part", 4) == 0) {
-			int dev, ok;
-			for (ok = 0, dev = 0;
-			     dev < CONFIG_SYS_SCSI_MAX_DEVICE; ++dev) {
-				if (scsi_dev_desc[dev].type !=
-				    DEV_TYPE_UNKNOWN) {
-					ok++;
-					if (dev)
-						printf("\n");
-					debug("print_part of %x\n", dev);
-					part_print(&scsi_dev_desc[dev]);
-				}
-			}
-			if (!ok)
+			if (blk_list_part(IF_TYPE_SCSI))
 				printf("\nno SCSI devices available\n");
-			return 1;
+			return 0;
 		}
 		return CMD_RET_USAGE;
 	case 3:
 		if (strncmp(argv[1], "dev", 3) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
-			printf("\nSCSI device %d: ", dev);
-			if (dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
-				printf("unknown device\n");
-				return 1;
+
+			if (!blk_show_device(IF_TYPE_SCSI, dev)) {
+				scsi_curr_dev = dev;
+				printf("... is now current device\n");
+			} else {
+				return CMD_RET_FAILURE;
 			}
-			printf("\n    Device %d: ", dev);
-			dev_print(&scsi_dev_desc[dev]);
-			if (scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
-				return 1;
-			scsi_curr_dev = dev;
-			printf("... is now current device\n");
 			return 0;
 		}
 		if (strncmp(argv[1], "part", 4) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
-			if (scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN)
-				part_print(&scsi_dev_desc[dev]);
-			else
-				printf("\nSCSI device %d not available\n", dev);
-			return 1;
+
+			if (blk_print_part_devnum(IF_TYPE_SCSI, dev)) {
+				printf("\nSCSI device %d not available\n",
+				       dev);
+				return CMD_RET_FAILURE;
+			}
+			return 0;
 		}
 		return CMD_RET_USAGE;
 	default:
@@ -440,10 +90,11 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			ulong blk  = simple_strtoul(argv[3], NULL, 16);
 			ulong cnt  = simple_strtoul(argv[4], NULL, 16);
 			ulong n;
+
 			printf("\nSCSI read: device %d block # %ld, count %ld ... ",
 			       scsi_curr_dev, blk, cnt);
-			n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
-				      blk, cnt, (ulong *)addr);
+			n = blk_read_devnum(IF_TYPE_SCSI, scsi_curr_dev, blk,
+					    cnt, (ulong *)addr);
 			printf("%ld blocks read: %s\n", n,
 			       n == cnt ? "OK" : "ERROR");
 			return 0;
@@ -452,10 +103,11 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			ulong blk = simple_strtoul(argv[3], NULL, 16);
 			ulong cnt = simple_strtoul(argv[4], NULL, 16);
 			ulong n;
+
 			printf("\nSCSI write: device %d block # %ld, count %ld ... ",
 			       scsi_curr_dev, blk, cnt);
-			n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
-				       blk, cnt, (ulong *)addr);
+			n = blk_write_devnum(IF_TYPE_SCSI, scsi_curr_dev, blk,
+					     cnt, (ulong *)addr);
 			printf("%ld blocks written: %s\n", n,
 			       n == cnt ? "OK" : "ERROR");
 			return 0;
@@ -483,223 +135,3 @@ U_BOOT_CMD(
 	"boot from SCSI device",
 	"loadAddr dev:part"
 );
-#endif
-
-/* copy src to dest, skipping leading and trailing blanks
- * and null terminate the string
- */
-void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
-{
-	int start,end;
-
-	start = 0;
-	while (start < len) {
-		if (src[start] != ' ')
-			break;
-		start++;
-	}
-	end = len-1;
-	while (end > start) {
-		if (src[end] != ' ')
-			break;
-		end--;
-	}
-	for (; start <= end; start++)
-		*dest ++= src[start];
-	*dest='\0';
-}
-
-
-/* Trim trailing blanks, and NUL-terminate string
- */
-void scsi_trim_trail (unsigned char *str, unsigned int len)
-{
-	unsigned char *p = str + len - 1;
-
-	while (len-- > 0) {
-		*p-- = '\0';
-		if (*p != ' ') {
-			return;
-		}
-	}
-}
-
-int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
-{
-	*capacity = 0;
-
-	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
-	pccb->cmd[0] = SCSI_RD_CAPAC10;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmdlen = 10;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-
-	pccb->datalen = 8;
-	if (scsi_exec(pccb) != true)
-		return 1;
-
-	*capacity = ((lbaint_t)pccb->pdata[0] << 24) |
-		    ((lbaint_t)pccb->pdata[1] << 16) |
-		    ((lbaint_t)pccb->pdata[2] << 8)  |
-		    ((lbaint_t)pccb->pdata[3]);
-
-	if (*capacity != 0xffffffff) {
-		/* Read capacity (10) was sufficient for this drive. */
-		*blksz = ((unsigned long)pccb->pdata[4] << 24) |
-			 ((unsigned long)pccb->pdata[5] << 16) |
-			 ((unsigned long)pccb->pdata[6] << 8)  |
-			 ((unsigned long)pccb->pdata[7]);
-		return 0;
-	}
-
-	/* Read capacity (10) was insufficient. Use read capacity (16). */
-	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
-	pccb->cmd[0] = SCSI_RD_CAPAC16;
-	pccb->cmd[1] = 0x10;
-	pccb->cmdlen = 16;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-
-	pccb->datalen = 16;
-	if (scsi_exec(pccb) != true)
-		return 1;
-
-	*capacity = ((uint64_t)pccb->pdata[0] << 56) |
-		    ((uint64_t)pccb->pdata[1] << 48) |
-		    ((uint64_t)pccb->pdata[2] << 40) |
-		    ((uint64_t)pccb->pdata[3] << 32) |
-		    ((uint64_t)pccb->pdata[4] << 24) |
-		    ((uint64_t)pccb->pdata[5] << 16) |
-		    ((uint64_t)pccb->pdata[6] << 8)  |
-		    ((uint64_t)pccb->pdata[7]);
-
-	*blksz = ((uint64_t)pccb->pdata[8]  << 56) |
-		 ((uint64_t)pccb->pdata[9]  << 48) |
-		 ((uint64_t)pccb->pdata[10] << 40) |
-		 ((uint64_t)pccb->pdata[11] << 32) |
-		 ((uint64_t)pccb->pdata[12] << 24) |
-		 ((uint64_t)pccb->pdata[13] << 16) |
-		 ((uint64_t)pccb->pdata[14] << 8)  |
-		 ((uint64_t)pccb->pdata[15]);
-
-	return 0;
-}
-
-
-/************************************************************************************
- * Some setup (fill-in) routines
- */
-void scsi_setup_test_unit_ready(ccb * pccb)
-{
-	pccb->cmd[0] = SCSI_TST_U_RDY;
-	pccb->cmd[1] = pccb->lun << 5;
-	pccb->cmd[2] = 0;
-	pccb->cmd[3] = 0;
-	pccb->cmd[4] = 0;
-	pccb->cmd[5] = 0;
-	pccb->cmdlen = 6;
-	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-}
-
-/*********************************************************************************
- * (re)-scan the scsi bus and reports scsi device info
- * to the user if mode = 1
- */
-void scsi_scan(int mode)
-{
-	unsigned char i,perq,modi,lun;
-	lbaint_t capacity;
-	unsigned long blksz;
-	ccb* pccb=(ccb *)&tempccb;
-
-	if (mode == 1)
-		printf("scanning bus for devices...\n");
-	for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
-		scsi_dev_desc[i].target = 0xff;
-		scsi_dev_desc[i].lun = 0xff;
-		scsi_dev_desc[i].lba = 0;
-		scsi_dev_desc[i].blksz = 0;
-		scsi_dev_desc[i].log2blksz  =
-			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
-		scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-		scsi_dev_desc[i].vendor[0] = 0;
-		scsi_dev_desc[i].product[0] = 0;
-		scsi_dev_desc[i].revision[0] = 0;
-		scsi_dev_desc[i].removable = false;
-		scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
-		scsi_dev_desc[i].devnum = i;
-		scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		scsi_dev_desc[i].block_read = scsi_read;
-		scsi_dev_desc[i].block_write = scsi_write;
-	}
-	scsi_max_devs = 0;
-	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
-		pccb->target = i;
-		for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
-			pccb->lun = lun;
-			pccb->pdata = (unsigned char *)&tempbuff;
-			pccb->datalen = 512;
-			scsi_setup_inquiry(pccb);
-			if (scsi_exec(pccb) != true) {
-				if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
-					debug("Selection timeout ID %d\n",
-					      pccb->target);
-					continue; /* selection timeout => assuming no device present */
-				}
-				scsi_print_error(pccb);
-				continue;
-			}
-			perq = tempbuff[0];
-			modi = tempbuff[1];
-			if ((perq & 0x1f) == 0x1f)
-				continue; /* skip unknown devices */
-			if ((modi & 0x80) == 0x80) /* drive is removable */
-				scsi_dev_desc[scsi_max_devs].removable = true;
-			/* get info for this device */
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
-				       &tempbuff[8], 8);
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
-				       &tempbuff[16], 16);
-			scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
-				       &tempbuff[32], 4);
-			scsi_dev_desc[scsi_max_devs].target = pccb->target;
-			scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
-
-			pccb->datalen = 0;
-			scsi_setup_test_unit_ready(pccb);
-			if (scsi_exec(pccb) != true) {
-				if (scsi_dev_desc[scsi_max_devs].removable) {
-					scsi_dev_desc[scsi_max_devs].type =
-							perq;
-					goto removable;
-				}
-				scsi_print_error(pccb);
-				continue;
-			}
-			if (scsi_read_capacity(pccb, &capacity, &blksz)) {
-				scsi_print_error(pccb);
-				continue;
-			}
-			scsi_dev_desc[scsi_max_devs].lba = capacity;
-			scsi_dev_desc[scsi_max_devs].blksz = blksz;
-			scsi_dev_desc[scsi_max_devs].log2blksz =
-				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
-			scsi_dev_desc[scsi_max_devs].type = perq;
-			part_init(&scsi_dev_desc[scsi_max_devs]);
-removable:
-			if(mode==1) {
-				printf ("  Device %d: ", scsi_max_devs);
-				dev_print(&scsi_dev_desc[scsi_max_devs]);
-			} /* if mode */
-			scsi_max_devs++;
-		} /* next LUN */
-	}
-	if (scsi_max_devs > 0)
-		scsi_curr_dev = 0;
-	else
-		scsi_curr_dev = -1;
-
-	printf("Found %d device(s).\n", scsi_max_devs);
-#ifndef CONFIG_SPL_BUILD
-	setenv_ulong("scsidevs", scsi_max_devs);
-#endif
-}
diff --git a/common/Makefile b/common/Makefile
index b23f312..397df61 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o
 obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
 obj-$(CONFIG_LYNXKDI) += lynxkdi.o
 obj-$(CONFIG_MENU) += menu.o
+obj-$(CONFIG_SCSI) += scsi.o
 obj-$(CONFIG_UPDATE_TFTP) += update.o
 obj-$(CONFIG_DFU_TFTP) += update.o
 obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
@@ -112,6 +113,9 @@ obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 endif
+ifdef CONFIG_SPL_SATA_SUPPORT
+obj-$(CONFIG_SCSI) += scsi.o
+endif
 endif
 #environment
 obj-y += env_common.o
diff --git a/common/scsi.c b/common/scsi.c
new file mode 100644
index 0000000..a336a10
--- /dev/null
+++ b/common/scsi.c
@@ -0,0 +1,567 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <inttypes.h>
+#include <pci.h>
+#include <scsi.h>
+
+#ifdef CONFIG_SCSI_DEV_LIST
+#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
+#else
+#ifdef CONFIG_SCSI_SYM53C8XX
+#define SCSI_VEND_ID	0x1000
+#ifndef CONFIG_SCSI_DEV_ID
+#define SCSI_DEV_ID		0x0001
+#else
+#define SCSI_DEV_ID		CONFIG_SCSI_DEV_ID
+#endif
+#elif defined CONFIG_SATA_ULI5288
+
+#define SCSI_VEND_ID 0x10b9
+#define SCSI_DEV_ID  0x5288
+
+#elif !defined(CONFIG_SCSI_AHCI_PLAT)
+#error no scsi device defined
+#endif
+#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
+const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
+#endif
+static ccb tempccb;	/* temporary scsi command buffer */
+
+static unsigned char tempbuff[512]; /* temporary data buffer */
+
+static int scsi_max_devs; /* number of highest available scsi device */
+
+static int scsi_curr_dev; /* current device */
+
+static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
+
+/* almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_READ_BLK 0xFFFF
+#define SCSI_LBA48_READ	0xFFFFFFF
+
+#ifdef CONFIG_SYS_64BIT_LBA
+void scsi_setup_read16(ccb *pccb, lbaint_t start, unsigned long blocks)
+{
+	pccb->cmd[0] = SCSI_READ16;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff;
+	pccb->cmd[5] = (unsigned char)(start >> 32) & 0xff;
+	pccb->cmd[6] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[7] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[8] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[9] = (unsigned char)start & 0xff;
+	pccb->cmd[10] = 0;
+	pccb->cmd[11] = (unsigned char)(blocks >> 24) & 0xff;
+	pccb->cmd[12] = (unsigned char)(blocks >> 16) & 0xff;
+	pccb->cmd[13] = (unsigned char)(blocks >> 8) & 0xff;
+	pccb->cmd[14] = (unsigned char)blocks & 0xff;
+	pccb->cmd[15] = 0;
+	pccb->cmdlen = 16;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read16: cmd: %02X %02X startblk %02X%02X%02X%02X%02X%02X%02X%02X blccnt %02X%02X%02X%02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+	      pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+}
+#endif
+
+void scsi_setup_read_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_READ10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[5] = (unsigned char)start & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
+	pccb->cmd[8] = (unsigned char)blocks & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[7], pccb->cmd[8]);
+}
+
+void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_WRITE10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+	pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+	pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[5] = (unsigned char)start & 0xff;
+	pccb->cmd[6] = 0;
+	pccb->cmd[7] = ((unsigned char)(blocks >> 8)) & 0xff;
+	pccb->cmd[8] = (unsigned char)blocks & 0xff;
+	pccb->cmd[9] = 0;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY;  /* NOT USED */
+	debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+	      __func__,
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+	      pccb->cmd[7], pccb->cmd[8]);
+}
+
+void scsi_setup_read6(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+	pccb->cmd[0] = SCSI_READ6;
+	pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
+	pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
+	pccb->cmd[3] = (unsigned char)start & 0xff;
+	pccb->cmd[4] = (unsigned char)blocks & 0xff;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+	debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
+	      pccb->cmd[0], pccb->cmd[1],
+	      pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
+}
+
+
+void scsi_setup_inquiry(ccb *pccb)
+{
+	pccb->cmd[0] = SCSI_INQUIRY;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = 0;
+	pccb->cmd[3] = 0;
+	if (pccb->datalen > 255)
+		pccb->cmd[4] = 255;
+	else
+		pccb->cmd[4] = (unsigned char)pccb->datalen;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
+static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
+		       lbaint_t blkcnt, void *buffer)
+{
+	int device = block_dev->devnum;
+	lbaint_t start, blks;
+	uintptr_t buf_addr;
+	unsigned short smallblks = 0;
+	ccb *pccb = (ccb *)&tempccb;
+	device &= 0xff;
+
+	/* Setup device */
+	pccb->target = scsi_dev_desc[device].target;
+	pccb->lun = scsi_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+	debug("\nscsi_read: dev %d startblk " LBAF
+	      ", blccnt " LBAF " buffer %lx\n",
+	      device, start, blks, (unsigned long)buffer);
+	do {
+		pccb->pdata = (unsigned char *)buf_addr;
+#ifdef CONFIG_SYS_64BIT_LBA
+		if (start > SCSI_LBA48_READ) {
+			unsigned long blocks;
+			blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
+			pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+			scsi_setup_read16(pccb, start, blocks);
+			start += blocks;
+			blks -= blocks;
+		} else
+#endif
+		if (blks > SCSI_MAX_READ_BLK) {
+			pccb->datalen = scsi_dev_desc[device].blksz *
+				SCSI_MAX_READ_BLK;
+			smallblks = SCSI_MAX_READ_BLK;
+			scsi_setup_read_ext(pccb, start, smallblks);
+			start += SCSI_MAX_READ_BLK;
+			blks -= SCSI_MAX_READ_BLK;
+		} else {
+			pccb->datalen = scsi_dev_desc[device].blksz * blks;
+			smallblks = (unsigned short)blks;
+			scsi_setup_read_ext(pccb, start, smallblks);
+			start += blks;
+			blks = 0;
+		}
+		debug("scsi_read_ext: startblk " LBAF
+		      ", blccnt %x buffer %" PRIXPTR "\n",
+		      start, smallblks, buf_addr);
+		if (scsi_exec(pccb) != true) {
+			scsi_print_error(pccb);
+			blkcnt -= blks;
+			break;
+		}
+		buf_addr += pccb->datalen;
+	} while (blks != 0);
+	debug("scsi_read_ext: end startblk " LBAF
+	      ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
+	return blkcnt;
+}
+
+/*******************************************************************************
+ * scsi_write
+ */
+
+/* Almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_WRITE_BLK 0xFFFF
+
+static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
+			lbaint_t blkcnt, const void *buffer)
+{
+	int device = block_dev->devnum;
+	lbaint_t start, blks;
+	uintptr_t buf_addr;
+	unsigned short smallblks;
+	ccb *pccb = (ccb *)&tempccb;
+
+	device &= 0xff;
+
+	/* Setup device */
+	pccb->target = scsi_dev_desc[device].target;
+	pccb->lun = scsi_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+	debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
+	      __func__, device, start, blks, (unsigned long)buffer);
+	do {
+		pccb->pdata = (unsigned char *)buf_addr;
+		if (blks > SCSI_MAX_WRITE_BLK) {
+			pccb->datalen = (scsi_dev_desc[device].blksz *
+					 SCSI_MAX_WRITE_BLK);
+			smallblks = SCSI_MAX_WRITE_BLK;
+			scsi_setup_write_ext(pccb, start, smallblks);
+			start += SCSI_MAX_WRITE_BLK;
+			blks -= SCSI_MAX_WRITE_BLK;
+		} else {
+			pccb->datalen = scsi_dev_desc[device].blksz * blks;
+			smallblks = (unsigned short)blks;
+			scsi_setup_write_ext(pccb, start, smallblks);
+			start += blks;
+			blks = 0;
+		}
+		debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+		      __func__, start, smallblks, buf_addr);
+		if (scsi_exec(pccb) != true) {
+			scsi_print_error(pccb);
+			blkcnt -= blks;
+			break;
+		}
+		buf_addr += pccb->datalen;
+	} while (blks != 0);
+	debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+	      __func__, start, smallblks, buf_addr);
+	return blkcnt;
+}
+
+int scsi_get_disk_count(void)
+{
+	return scsi_max_devs;
+}
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
+void scsi_init(void)
+{
+	int busdevfunc = -1;
+	int i;
+	/*
+	 * Find a device from the list, this driver will support a single
+	 * controller.
+	 */
+	for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+		/* get PCI Device ID */
+#ifdef CONFIG_DM_PCI
+		struct udevice *dev;
+		int ret;
+
+		ret = dm_pci_find_device(scsi_device_list[i].vendor,
+					 scsi_device_list[i].device, 0, &dev);
+		if (!ret) {
+			busdevfunc = dm_pci_get_bdf(dev);
+			break;
+		}
+#else
+		busdevfunc = pci_find_device(scsi_device_list[i].vendor,
+					     scsi_device_list[i].device,
+					     0);
+#endif
+		if (busdevfunc != -1)
+			break;
+	}
+
+	if (busdevfunc == -1) {
+		printf("Error: SCSI Controller(s) ");
+		for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+			printf("%04X:%04X ",
+			       scsi_device_list[i].vendor,
+			       scsi_device_list[i].device);
+		}
+		printf("not found\n");
+		return;
+	}
+#ifdef DEBUG
+	else {
+		printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
+		       scsi_device_list[i].vendor,
+		       scsi_device_list[i].device,
+		       (busdevfunc >> 16) & 0xFF,
+		       (busdevfunc >> 11) & 0x1F,
+		       (busdevfunc >> 8) & 0x7);
+	}
+#endif
+	bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
+	scsi_low_level_init(busdevfunc);
+	scsi_scan(1);
+	bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
+}
+#endif
+
+#ifdef CONFIG_PARTITIONS
+struct blk_desc *scsi_get_dev(int dev)
+{
+	return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
+}
+#endif
+
+/* copy src to dest, skipping leading and trailing blanks
+ * and null terminate the string
+ */
+void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
+{
+	int start, end;
+
+	start = 0;
+	while (start < len) {
+		if (src[start] != ' ')
+			break;
+		start++;
+	}
+	end = len-1;
+	while (end > start) {
+		if (src[end] != ' ')
+			break;
+		end--;
+	}
+	for (; start <= end; start++)
+		*dest ++= src[start];
+	*dest = '\0';
+}
+
+
+/* Trim trailing blanks, and NUL-terminate string
+ */
+void scsi_trim_trail(unsigned char *str, unsigned int len)
+{
+	unsigned char *p = str + len - 1;
+
+	while (len-- > 0) {
+		*p-- = '\0';
+		if (*p != ' ')
+			return;
+	}
+}
+
+int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
+{
+	*capacity = 0;
+
+	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
+	pccb->cmd[0] = SCSI_RD_CAPAC10;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmdlen = 10;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+	pccb->datalen = 8;
+	if (scsi_exec(pccb) != true)
+		return 1;
+
+	*capacity = ((lbaint_t)pccb->pdata[0] << 24) |
+		    ((lbaint_t)pccb->pdata[1] << 16) |
+		    ((lbaint_t)pccb->pdata[2] << 8)  |
+		    ((lbaint_t)pccb->pdata[3]);
+
+	if (*capacity != 0xffffffff) {
+		/* Read capacity (10) was sufficient for this drive. */
+		*blksz = ((unsigned long)pccb->pdata[4] << 24) |
+			 ((unsigned long)pccb->pdata[5] << 16) |
+			 ((unsigned long)pccb->pdata[6] << 8)  |
+			 ((unsigned long)pccb->pdata[7]);
+		return 0;
+	}
+
+	/* Read capacity (10) was insufficient. Use read capacity (16). */
+	memset(pccb->cmd, '\0', sizeof(pccb->cmd));
+	pccb->cmd[0] = SCSI_RD_CAPAC16;
+	pccb->cmd[1] = 0x10;
+	pccb->cmdlen = 16;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+	pccb->datalen = 16;
+	if (scsi_exec(pccb) != true)
+		return 1;
+
+	*capacity = ((uint64_t)pccb->pdata[0] << 56) |
+		    ((uint64_t)pccb->pdata[1] << 48) |
+		    ((uint64_t)pccb->pdata[2] << 40) |
+		    ((uint64_t)pccb->pdata[3] << 32) |
+		    ((uint64_t)pccb->pdata[4] << 24) |
+		    ((uint64_t)pccb->pdata[5] << 16) |
+		    ((uint64_t)pccb->pdata[6] << 8)  |
+		    ((uint64_t)pccb->pdata[7]);
+
+	*blksz = ((uint64_t)pccb->pdata[8]  << 56) |
+		 ((uint64_t)pccb->pdata[9]  << 48) |
+		 ((uint64_t)pccb->pdata[10] << 40) |
+		 ((uint64_t)pccb->pdata[11] << 32) |
+		 ((uint64_t)pccb->pdata[12] << 24) |
+		 ((uint64_t)pccb->pdata[13] << 16) |
+		 ((uint64_t)pccb->pdata[14] << 8)  |
+		 ((uint64_t)pccb->pdata[15]);
+
+	return 0;
+}
+
+
+/*
+ * Some setup (fill-in) routines
+ */
+void scsi_setup_test_unit_ready(ccb *pccb)
+{
+	pccb->cmd[0] = SCSI_TST_U_RDY;
+	pccb->cmd[1] = pccb->lun << 5;
+	pccb->cmd[2] = 0;
+	pccb->cmd[3] = 0;
+	pccb->cmd[4] = 0;
+	pccb->cmd[5] = 0;
+	pccb->cmdlen = 6;
+	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
+/*
+ * (re)-scan the scsi bus and reports scsi device info
+ * to the user if mode = 1
+ */
+void scsi_scan(int mode)
+{
+	unsigned char i, perq, modi, lun;
+	lbaint_t capacity;
+	unsigned long blksz;
+	ccb *pccb = (ccb *)&tempccb;
+
+	if (mode == 1)
+		printf("scanning bus for devices...\n");
+	for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
+		scsi_dev_desc[i].target = 0xff;
+		scsi_dev_desc[i].lun = 0xff;
+		scsi_dev_desc[i].lba = 0;
+		scsi_dev_desc[i].blksz = 0;
+		scsi_dev_desc[i].log2blksz =
+			LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
+		scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		scsi_dev_desc[i].vendor[0] = 0;
+		scsi_dev_desc[i].product[0] = 0;
+		scsi_dev_desc[i].revision[0] = 0;
+		scsi_dev_desc[i].removable = false;
+		scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
+		scsi_dev_desc[i].devnum = i;
+		scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		scsi_dev_desc[i].block_read = scsi_read;
+		scsi_dev_desc[i].block_write = scsi_write;
+	}
+	scsi_max_devs = 0;
+	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+		pccb->target = i;
+		for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
+			pccb->lun = lun;
+			pccb->pdata = (unsigned char *)&tempbuff;
+			pccb->datalen = 512;
+			scsi_setup_inquiry(pccb);
+			if (scsi_exec(pccb) != true) {
+				if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
+					/*
+					 * selection timeout => assuming no
+					 * device present
+					 */
+					debug("Selection timeout ID %d\n",
+					      pccb->target);
+					continue;
+				}
+				scsi_print_error(pccb);
+				continue;
+			}
+			perq = tempbuff[0];
+			modi = tempbuff[1];
+			if ((perq & 0x1f) == 0x1f)
+				continue; /* skip unknown devices */
+			if ((modi & 0x80) == 0x80) /* drive is removable */
+				scsi_dev_desc[scsi_max_devs].removable = true;
+			/* get info for this device */
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+						[scsi_max_devs].vendor[0],
+				       &tempbuff[8], 8);
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+						[scsi_max_devs].product[0],
+				       &tempbuff[16], 16);
+			scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+						[scsi_max_devs].revision[0],
+				       &tempbuff[32], 4);
+			scsi_dev_desc[scsi_max_devs].target = pccb->target;
+			scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
+
+			pccb->datalen = 0;
+			scsi_setup_test_unit_ready(pccb);
+			if (scsi_exec(pccb) != true) {
+				if (scsi_dev_desc[scsi_max_devs].removable) {
+					scsi_dev_desc[scsi_max_devs].type =
+							perq;
+					goto removable;
+				}
+				scsi_print_error(pccb);
+				continue;
+			}
+			if (scsi_read_capacity(pccb, &capacity, &blksz)) {
+				scsi_print_error(pccb);
+				continue;
+			}
+			scsi_dev_desc[scsi_max_devs].lba = capacity;
+			scsi_dev_desc[scsi_max_devs].blksz = blksz;
+			scsi_dev_desc[scsi_max_devs].log2blksz =
+				LOG2(scsi_dev_desc[scsi_max_devs].blksz);
+			scsi_dev_desc[scsi_max_devs].type = perq;
+			part_init(&scsi_dev_desc[scsi_max_devs]);
+removable:
+			if (mode == 1) {
+				printf("  Device %d: ", scsi_max_devs);
+				dev_print(&scsi_dev_desc[scsi_max_devs]);
+			} /* if mode */
+			scsi_max_devs++;
+		} /* next LUN */
+	}
+	if (scsi_max_devs > 0)
+		scsi_curr_dev = 0;
+	else
+		scsi_curr_dev = -1;
+
+	printf("Found %d device(s).\n", scsi_max_devs);
+#ifndef CONFIG_SPL_BUILD
+	setenv_ulong("scsidevs", scsi_max_devs);
+#endif
+}
+
+U_BOOT_LEGACY_BLK(scsi) = {
+	.if_typename	= "sata",
+	.if_type	= IF_TYPE_SCSI,
+	.max_devs	= CONFIG_SYS_SCSI_MAX_DEVICE,
+	.desc		= scsi_dev_desc,
+};
-- 
cgit v0.10.2


From e9be1ee75ed27c4281cad5168b6c51d26b2e8a15 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:10 -0600
Subject: dm: ide: Separate the non-command code into its own file

At present the IDE command code includes both the command-processing code
and the core IDE functions and data structures.

Separate the latter into its own file, adding functions as needed to avoid
the command code accessing data structures directly.

With this commit:
- Most CONFIG option are referenced from the non-command code
- The concept of a 'current IDE device' is confined to the command code

This will make it easier to convert this code to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/ide.c b/cmd/ide.c
index db26f43..c942744 100644
--- a/cmd/ide.c
+++ b/cmd/ide.c
@@ -29,717 +29,9 @@
 # include <status_led.h>
 #endif
 
-#ifdef __PPC__
-# define EIEIO		__asm__ volatile ("eieio")
-# define SYNC		__asm__ volatile ("sync")
-#else
-# define EIEIO		/* nothing */
-# define SYNC		/* nothing */
-#endif
-
-/* ------------------------------------------------------------------------- */
-
 /* Current I/O Device	*/
 static int curr_device = -1;
 
-/* Current offset for IDE0 / IDE1 bus access	*/
-ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
-#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
-	CONFIG_SYS_ATA_IDE0_OFFSET,
-#endif
-#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
-	CONFIG_SYS_ATA_IDE1_OFFSET,
-#endif
-};
-
-static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
-
-struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
-/* ------------------------------------------------------------------------- */
-
-#define IDE_TIME_OUT	2000	/* 2 sec timeout */
-
-#define ATAPI_TIME_OUT	7000	/* 7 sec timeout (5 sec seems to work...) */
-
-#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-
-#ifndef CONFIG_SYS_ATA_PORT_ADDR
-#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
-#endif
-
-#ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
-# define DEVICE_LED(x) 0
-# define LED_IDE1 1
-# define LED_IDE2 2
-#endif
-
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
-static void ide_reset(void)
-{
-	int i;
-
-	curr_device = -1;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
-		ide_bus_ok[i] = 0;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-
-	ide_set_reset(1);	/* assert reset */
-
-	/* the reset signal shall be asserted for et least 25 us */
-	udelay(25);
-
-	WATCHDOG_RESET();
-
-	/* de-assert RESET signal */
-	ide_set_reset(0);
-
-	/* wait 250 ms */
-	for (i = 0; i < 250; ++i)
-		udelay(1000);
-}
-#else
-#define ide_reset()	/* dummy */
-#endif /* CONFIG_IDE_RESET */
-
-/*
- * Wait until Busy bit is off, or timeout (in ms)
- * Return last status
- */
-static uchar ide_wait(int dev, ulong t)
-{
-	ulong delay = 10 * t;	/* poll every 100 us */
-	uchar c;
-
-	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
-		udelay(100);
-		if (delay-- == 0)
-			break;
-	}
-	return c;
-}
-
-/*
- * copy src to dest, skipping leading and trailing blanks and null
- * terminate the string
- * "len" is the size of available memory including the terminating '\0'
- */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
-		      unsigned int len)
-{
-	unsigned char *end, *last;
-
-	last = dst;
-	end = src + len - 1;
-
-	/* reserve space for '\0' */
-	if (len < 2)
-		goto OUT;
-
-	/* skip leading white space */
-	while ((*src) && (src < end) && (*src == ' '))
-		++src;
-
-	/* copy string, omitting trailing white space */
-	while ((*src) && (src < end)) {
-		*dst++ = *src;
-		if (*src++ != ' ')
-			last = dst;
-	}
-OUT:
-	*last = '\0';
-}
-
-#ifdef CONFIG_ATAPI
-/****************************************************************************
- * ATAPI Support
- */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-/* since ATAPI may use commands with not 4 bytes alligned length
- * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *)sect_buf;
-
-	debug("in output data shorts base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (shorts--) {
-		EIEIO;
-		*pbuf = *dbuf++;
-	}
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *)sect_buf;
-
-	debug("in input data shorts base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (shorts--) {
-		EIEIO;
-		*dbuf++ = *pbuf;
-	}
-}
-
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
-	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/*
- * Wait until (Status & mask) == res, or timeout (in ms)
- * Return last status
- * This is used since some ATAPI CD ROMs clears their Busy Bit first
- * and then they set their DRQ Bit
- */
-static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
-{
-	ulong delay = 10 * t;	/* poll every 100 us */
-	uchar c;
-
-	/* prevents to read the status before valid */
-	c = ide_inb(dev, ATA_DEV_CTL);
-
-	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
-		/* break if error occurs (doesn't make sense to wait more) */
-		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
-			break;
-		udelay(100);
-		if (delay-- == 0)
-			break;
-	}
-	return c;
-}
-
-/*
- * issue an atapi command
- */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
-			  unsigned char *buffer, int buflen)
-{
-	unsigned char c, err, mask, res;
-	int n;
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-
-	/* Select device
-	 */
-	mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
-	res = 0;
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & mask) != res) {
-		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
-		       c);
-		err = 0xFF;
-		goto AI_OUT;
-	}
-	/* write taskfile */
-	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
-	ide_outb(device, ATA_SECT_CNT, 0);
-	ide_outb(device, ATA_SECT_NUM, 0);
-	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
-	ide_outb(device, ATA_CYL_HIGH,
-		 (unsigned char) ((buflen >> 8) & 0xFF));
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
-	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
-	udelay(50);
-
-	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
-	res = ATA_STAT_DRQ;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-
-	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
-		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
-		       device, c);
-		err = 0xFF;
-		goto AI_OUT;
-	}
-
-	/* write command block */
-	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
-
-	/* ATAPI Command written wait for completition */
-	udelay(5000);		/* device must set bsy */
-
-	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
-	/*
-	 * if no data wait for DRQ = 0 BSY = 0
-	 * if data wait for DRQ = 1 BSY = 0
-	 */
-	res = 0;
-	if (buflen)
-		res = ATA_STAT_DRQ;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & mask) != res) {
-		if (c & ATA_STAT_ERR) {
-			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
-			debug("atapi_issue 1 returned sense key %X status %02X\n",
-			      err, c);
-		} else {
-			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
-			       ccb[0], c);
-			err = 0xFF;
-		}
-		goto AI_OUT;
-	}
-	n = ide_inb(device, ATA_CYL_HIGH);
-	n <<= 8;
-	n += ide_inb(device, ATA_CYL_LOW);
-	if (n > buflen) {
-		printf("ERROR, transfer bytes %d requested only %d\n", n,
-		       buflen);
-		err = 0xff;
-		goto AI_OUT;
-	}
-	if ((n == 0) && (buflen < 0)) {
-		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
-		err = 0xff;
-		goto AI_OUT;
-	}
-	if (n != buflen) {
-		debug("WARNING, transfer bytes %d not equal with requested %d\n",
-		      n, buflen);
-	}
-	if (n != 0) {		/* data transfer */
-		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
-		/* we transfer shorts */
-		n >>= 1;
-		/* ok now decide if it is an in or output */
-		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
-			debug("Write to device\n");
-			ide_output_data_shorts(device, (unsigned short *)buffer,
-					       n);
-		} else {
-			debug("Read from device @ %p shorts %d\n", buffer, n);
-			ide_input_data_shorts(device, (unsigned short *)buffer,
-					      n);
-		}
-	}
-	udelay(5000);		/* seems that some CD ROMs need this... */
-	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
-	res = 0;
-	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
-		debug("atapi_issue 2 returned sense key %X status %X\n", err,
-		      c);
-	} else {
-		err = 0;
-	}
-AI_OUT:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return err;
-}
-
-/*
- * sending the command to atapi_issue. If an status other than good
- * returns, an request_sense will be issued
- */
-
-#define ATAPI_DRIVE_NOT_READY	100
-#define ATAPI_UNIT_ATTN		10
-
-unsigned char atapi_issue_autoreq(int device,
-				  unsigned char *ccb,
-				  int ccblen,
-				  unsigned char *buffer, int buflen)
-{
-	unsigned char sense_data[18], sense_ccb[12];
-	unsigned char res, key, asc, ascq;
-	int notready, unitattn;
-
-	unitattn = ATAPI_UNIT_ATTN;
-	notready = ATAPI_DRIVE_NOT_READY;
-
-retry:
-	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
-	if (res == 0)
-		return 0;	/* Ok */
-
-	if (res == 0xFF)
-		return 0xFF;	/* error */
-
-	debug("(auto_req)atapi_issue returned sense key %X\n", res);
-
-	memset(sense_ccb, 0, sizeof(sense_ccb));
-	memset(sense_data, 0, sizeof(sense_data));
-	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
-	sense_ccb[4] = 18;	/* allocation Length */
-
-	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
-	key = (sense_data[2] & 0xF);
-	asc = (sense_data[12]);
-	ascq = (sense_data[13]);
-
-	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
-	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
-	      sense_data[0], key, asc, ascq);
-
-	if ((key == 0))
-		return 0;	/* ok device ready */
-
-	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
-		if (unitattn-- > 0) {
-			udelay(200 * 1000);
-			goto retry;
-		}
-		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
-		goto error;
-	}
-	if ((asc == 0x4) && (ascq == 0x1)) {
-		/* not ready, but will be ready soon */
-		if (notready-- > 0) {
-			udelay(200 * 1000);
-			goto retry;
-		}
-		printf("Drive not ready, tried %d times\n",
-		       ATAPI_DRIVE_NOT_READY);
-		goto error;
-	}
-	if (asc == 0x3a) {
-		debug("Media not present\n");
-		goto error;
-	}
-
-	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
-	       ascq);
-error:
-	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
-	return 0xFF;
-}
-
-/*
- * atapi_read:
- * we transfer only one block per command, since the multiple DRQ per
- * command is not yet implemented
- */
-#define ATAPI_READ_MAX_BYTES	2048	/* we read max 2kbytes */
-#define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
-#define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		 void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char ccb[12];	/* Command descriptor block */
-	ulong cnt;
-
-	debug("atapi_read dev %d start " LBAF " blocks " LBAF
-	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
-
-	do {
-		if (blkcnt > ATAPI_READ_MAX_BLOCK)
-			cnt = ATAPI_READ_MAX_BLOCK;
-		else
-			cnt = blkcnt;
-
-		ccb[0] = ATAPI_CMD_READ_12;
-		ccb[1] = 0;	/* reserved */
-		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
-		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
-		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
-		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
-		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
-		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
-		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
-		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
-		ccb[10] = 0;	/* reserved */
-		ccb[11] = 0;	/* reserved */
-
-		if (atapi_issue_autoreq(device, ccb, 12,
-					(unsigned char *)buffer,
-					cnt * ATAPI_READ_BLOCK_SIZE)
-		    == 0xFF) {
-			return n;
-		}
-		n += cnt;
-		blkcnt -= cnt;
-		blknr += cnt;
-		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
-	} while (blkcnt > 0);
-	return n;
-}
-
-static void atapi_inquiry(struct blk_desc *dev_desc)
-{
-	unsigned char ccb[12];	/* Command descriptor block */
-	unsigned char iobuf[64];	/* temp buf */
-	unsigned char c;
-	int device;
-
-	device = dev_desc->devnum;
-	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
-	dev_desc->block_read = atapi_read;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-
-	ccb[0] = ATAPI_CMD_INQUIRY;
-	ccb[4] = 40;		/* allocation Legnth */
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
-
-	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
-	if (c != 0)
-		return;
-
-	/* copy device ident strings */
-	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
-	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
-	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
-
-	dev_desc->lun = 0;
-	dev_desc->lba = 0;
-	dev_desc->blksz = 0;
-	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
-	dev_desc->type = iobuf[0] & 0x1f;
-
-	if ((iobuf[1] & 0x80) == 0x80)
-		dev_desc->removable = 1;
-	else
-		dev_desc->removable = 0;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	ccb[0] = ATAPI_CMD_START_STOP;
-	ccb[4] = 0x03;		/* start */
-
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
-
-	debug("ATAPI_CMD_START_STOP returned %x\n", c);
-	if (c != 0)
-		return;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
-
-	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
-	if (c != 0)
-		return;
-
-	memset(ccb, 0, sizeof(ccb));
-	memset(iobuf, 0, sizeof(iobuf));
-	ccb[0] = ATAPI_CMD_READ_CAP;
-	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
-	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
-	if (c != 0)
-		return;
-
-	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
-	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
-	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
-
-	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
-		((unsigned long) iobuf[1] << 16) +
-		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
-	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
-		((unsigned long) iobuf[5] << 16) +
-		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
-	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
-	dev_desc->lba48 = 0;
-#endif
-	return;
-}
-
-#endif /* CONFIG_ATAPI */
-
-static void ide_ident(struct blk_desc *dev_desc)
-{
-	unsigned char c;
-	hd_driveid_t iop;
-
-#ifdef CONFIG_ATAPI
-	int retries = 0;
-#endif
-	int device;
-
-	device = dev_desc->devnum;
-	printf("  Device %d: ", device);
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	dev_desc->if_type = IF_TYPE_IDE;
-#ifdef CONFIG_ATAPI
-
-	retries = 0;
-
-	/* Warning: This will be tricky to read */
-	while (retries <= 1) {
-		/* check signature */
-		if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
-		    (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
-		    (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
-		    (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
-			/* ATAPI Signature found */
-			dev_desc->if_type = IF_TYPE_ATAPI;
-			/*
-			 * Start Ident Command
-			 */
-			ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
-			/*
-			 * Wait for completion - ATAPI devices need more time
-			 * to become ready
-			 */
-			c = ide_wait(device, ATAPI_TIME_OUT);
-		} else
-#endif
-		{
-			/*
-			 * Start Ident Command
-			 */
-			ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
-
-			/*
-			 * Wait for completion
-			 */
-			c = ide_wait(device, IDE_TIME_OUT);
-		}
-		ide_led(DEVICE_LED(device), 0);	/* LED off      */
-
-		if (((c & ATA_STAT_DRQ) == 0) ||
-		    ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
-#ifdef CONFIG_ATAPI
-			{
-				/*
-				 * Need to soft reset the device
-				 * in case it's an ATAPI...
-				 */
-				debug("Retrying...\n");
-				ide_outb(device, ATA_DEV_HD,
-					 ATA_LBA | ATA_DEVICE(device));
-				udelay(100000);
-				ide_outb(device, ATA_COMMAND, 0x08);
-				udelay(500000);	/* 500 ms */
-			}
-			/*
-			 * Select device
-			 */
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			retries++;
-#else
-			return;
-#endif
-		}
-#ifdef CONFIG_ATAPI
-		else
-			break;
-	}			/* see above - ugly to read */
-
-	if (retries == 2)	/* Not found */
-		return;
-#endif
-
-	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
-
-	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
-		  sizeof(dev_desc->revision));
-	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
-		  sizeof(dev_desc->vendor));
-	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
-		  sizeof(dev_desc->product));
-#ifdef __LITTLE_ENDIAN
-	/*
-	 * firmware revision, model, and serial number have Big Endian Byte
-	 * order in Word. Convert all three to little endian.
-	 *
-	 * See CF+ and CompactFlash Specification Revision 2.0:
-	 * 6.2.1.6: Identify Drive, Table 39 for more details
-	 */
-
-	strswab(dev_desc->revision);
-	strswab(dev_desc->vendor);
-	strswab(dev_desc->product);
-#endif /* __LITTLE_ENDIAN */
-
-	if ((iop.config & 0x0080) == 0x0080)
-		dev_desc->removable = 1;
-	else
-		dev_desc->removable = 0;
-
-#ifdef CONFIG_ATAPI
-	if (dev_desc->if_type == IF_TYPE_ATAPI) {
-		atapi_inquiry(dev_desc);
-		return;
-	}
-#endif /* CONFIG_ATAPI */
-
-#ifdef __BIG_ENDIAN
-	/* swap shorts */
-	dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
-#else  /* ! __BIG_ENDIAN */
-	/*
-	 * do not swap shorts on little endian
-	 *
-	 * See CF+ and CompactFlash Specification Revision 2.0:
-	 * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
-	 */
-	dev_desc->lba = iop.lba_capacity;
-#endif /* __BIG_ENDIAN */
-
-#ifdef CONFIG_LBA48
-	if (iop.command_set_2 & 0x0400) {	/* LBA 48 support */
-		dev_desc->lba48 = 1;
-		dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
-			((unsigned long long) iop.lba48_capacity[1] << 16) |
-			((unsigned long long) iop.lba48_capacity[2] << 32) |
-			((unsigned long long) iop.lba48_capacity[3] << 48);
-	} else {
-		dev_desc->lba48 = 0;
-	}
-#endif /* CONFIG_LBA48 */
-	/* assuming HD */
-	dev_desc->type = DEV_TYPE_HARDDISK;
-	dev_desc->blksz = ATA_BLOCKSIZE;
-	dev_desc->log2blksz = LOG2(dev_desc->blksz);
-	dev_desc->lun = 0;	/* just to fill something in... */
-
-#if 0				/* only used to test the powersaving mode,
-				 * if enabled, the drive goes after 5 sec
-				 * in standby mode */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = ide_wait(device, IDE_TIME_OUT);
-	ide_outb(device, ATA_SECT_CNT, 1);
-	ide_outb(device, ATA_LBA_LOW, 0);
-	ide_outb(device, ATA_LBA_MID, 0);
-	ide_outb(device, ATA_LBA_HIGH, 0);
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	ide_outb(device, ATA_COMMAND, 0xe3);
-	udelay(50);
-	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
 int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	int rcode = 0;
@@ -759,79 +51,41 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 			ide_init();
 			return 0;
 		} else if (strncmp(argv[1], "inf", 3) == 0) {
-			int i;
-
-			putc('\n');
-
-			for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-				if (ide_dev_desc[i].type == DEV_TYPE_UNKNOWN)
-					continue;  /* list only known devices */
-				printf("IDE device %d: ", i);
-				dev_print(&ide_dev_desc[i]);
-			}
+			blk_list_devices(IF_TYPE_IDE);
 			return 0;
 
 		} else if (strncmp(argv[1], "dev", 3) == 0) {
-			if (curr_device < 0 ||
-			    curr_device >= CONFIG_SYS_IDE_MAXDEVICE) {
-				puts("\nno IDE devices available\n");
-				return 1;
+			if (blk_print_device_num(IF_TYPE_IDE, curr_device)) {
+				printf("\nno IDE devices available\n");
+				return CMD_RET_FAILURE;
 			}
-			printf("\nIDE device %d: ", curr_device);
-			dev_print(&ide_dev_desc[curr_device]);
+
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev, ok;
-
-			for (ok = 0, dev = 0;
-			     dev < CONFIG_SYS_IDE_MAXDEVICE;
-			     ++dev) {
-				if (ide_dev_desc[dev].part_type !=
-				    PART_TYPE_UNKNOWN) {
-					++ok;
-					if (dev)
-						putc('\n');
-					part_print(&ide_dev_desc[dev]);
-				}
-			}
-			if (!ok) {
-				puts("\nno IDE devices available\n");
-				rcode++;
-			}
-			return rcode;
+			if (blk_list_part(IF_TYPE_IDE))
+				printf("\nno IDE devices available\n");
+			return 1;
 		}
 		return CMD_RET_USAGE;
 	case 3:
 		if (strncmp(argv[1], "dev", 3) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			printf("\nIDE device %d: ", dev);
-			if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
-				puts("unknown device\n");
-				return 1;
+			if (!blk_show_device(IF_TYPE_IDE, dev)) {
+				curr_device = dev;
+				printf("... is now current device\n");
+			} else {
+				return CMD_RET_FAILURE;
 			}
-			dev_print(&ide_dev_desc[dev]);
-			/*ide_print (dev); */
-
-			if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
-				return 1;
-
-			curr_device = dev;
-
-			puts("... is now current device\n");
-
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				part_print(&ide_dev_desc[dev]);
-			} else {
-				printf("\nIDE device %d not available\n",
-				       dev);
-				rcode = 1;
+			if (blk_print_part_devnum(IF_TYPE_IDE, dev)) {
+				printf("\nIDE device %d not available\n", dev);
+				return CMD_RET_FAILURE;
 			}
-			return rcode;
+			return 1;
 		}
 
 		return CMD_RET_USAGE;
@@ -841,7 +95,6 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 		if (strcmp(argv[1], "read") == 0) {
 			ulong addr = simple_strtoul(argv[2], NULL, 16);
 			ulong cnt = simple_strtoul(argv[4], NULL, 16);
-			struct blk_desc *dev_desc;
 			ulong n;
 
 #ifdef CONFIG_SYS_64BIT_LBA
@@ -856,11 +109,8 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 			       curr_device, blk, cnt);
 #endif
 
-			dev_desc = &ide_dev_desc[curr_device];
-			n = blk_dread(dev_desc, blk, cnt, (ulong *)addr);
-			/* flush cache after read */
-			flush_cache(addr,
-				    cnt * ide_dev_desc[curr_device].blksz);
+			n = blk_read_devnum(IF_TYPE_IDE, curr_device, blk, cnt,
+					    (ulong *)addr);
 
 			printf("%ld blocks read: %s\n",
 			       n, (n == cnt) ? "OK" : "ERROR");
@@ -884,8 +134,8 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 			printf("\nIDE write: device %d block # %ld, count %ld...",
 			       curr_device, blk, cnt);
 #endif
-			n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
-				      (ulong *)addr);
+			n = blk_write_devnum(IF_TYPE_IDE, curr_device, blk, cnt,
+					     (ulong *)addr);
 
 			printf("%ld blocks written: %s\n", n,
 			       n == cnt ? "OK" : "ERROR");
@@ -906,511 +156,6 @@ int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 	return common_diskboot(cmdtp, "ide", argc, argv);
 }
 
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_led(uchar led, uchar status)
-{
-#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
-	static uchar led_buffer;	/* Buffer for current LED status */
-
-	uchar *led_port = LED_PORT;
-
-	if (status)		/* switch LED on        */
-		led_buffer |= led;
-	else			/* switch LED off       */
-		led_buffer &= ~led;
-
-	*led_port = led_buffer;
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_outb(int dev, int port, unsigned char val)
-{
-	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
-	      dev, port, val,
-	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-
-#if defined(CONFIG_IDE_AHB)
-	if (port) {
-		/* write command */
-		ide_write_register(dev, port, val);
-	} else {
-		/* write data */
-		outb(val, (ATA_CURR_BASE(dev)));
-	}
-#else
-	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-}
-
-__weak unsigned char ide_inb(int dev, int port)
-{
-	uchar val;
-
-#if defined(CONFIG_IDE_AHB)
-	val = ide_read_register(dev, port);
-#else
-	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-
-	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
-	      dev, port,
-	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
-	return val;
-}
-
-void ide_init(void)
-{
-	unsigned char c;
-	int i, bus;
-
-#ifdef CONFIG_IDE_8xx_PCCARD
-	extern int ide_devices_found;	/* Initialized in check_ide_device() */
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-#ifdef CONFIG_IDE_PREINIT
-	WATCHDOG_RESET();
-
-	if (ide_preinit()) {
-		puts("ide_preinit failed\n");
-		return;
-	}
-#endif /* CONFIG_IDE_PREINIT */
-
-	WATCHDOG_RESET();
-
-	/*
-	 * Reset the IDE just to be sure.
-	 * Light LED's to show
-	 */
-	ide_led((LED_IDE1 | LED_IDE2), 1);	/* LED's on     */
-
-	/* ATAPI Drives seems to need a proper IDE Reset */
-	ide_reset();
-
-#ifdef CONFIG_IDE_INIT_POSTRESET
-	WATCHDOG_RESET();
-
-	if (ide_init_postreset()) {
-		puts("ide_preinit_postreset failed\n");
-		return;
-	}
-#endif /* CONFIG_IDE_INIT_POSTRESET */
-
-	/*
-	 * Wait for IDE to get ready.
-	 * According to spec, this can take up to 31 seconds!
-	 */
-	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
-		int dev =
-			bus * (CONFIG_SYS_IDE_MAXDEVICE /
-			       CONFIG_SYS_IDE_MAXBUS);
-
-#ifdef CONFIG_IDE_8xx_PCCARD
-		/* Skip non-ide devices from probing */
-		if ((ide_devices_found & (1 << bus)) == 0) {
-			ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off */
-			continue;
-		}
-#endif
-		printf("Bus %d: ", bus);
-
-		ide_bus_ok[bus] = 0;
-
-		/* Select device
-		 */
-		udelay(100000);	/* 100 ms */
-		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
-		udelay(100000);	/* 100 ms */
-		i = 0;
-		do {
-			udelay(10000);	/* 10 ms */
-
-			c = ide_inb(dev, ATA_STATUS);
-			i++;
-			if (i > (ATA_RESET_TIME * 100)) {
-				puts("** Timeout **\n");
-				/* LED's off */
-				ide_led((LED_IDE1 | LED_IDE2), 0);
-				return;
-			}
-			if ((i >= 100) && ((i % 100) == 0))
-				putc('.');
-
-		} while (c & ATA_STAT_BUSY);
-
-		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
-		} else if ((c & ATA_STAT_READY) == 0) {
-			puts("not available  ");
-			debug("Status = 0x%02X ", c);
-#endif
-		} else {
-			puts("OK ");
-			ide_bus_ok[bus] = 1;
-		}
-		WATCHDOG_RESET();
-	}
-
-	putc('\n');
-
-	ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off    */
-
-	curr_device = -1;
-	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
-		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-		ide_dev_desc[i].if_type = IF_TYPE_IDE;
-		ide_dev_desc[i].devnum = i;
-		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		ide_dev_desc[i].blksz = 0;
-		ide_dev_desc[i].log2blksz =
-			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
-		ide_dev_desc[i].lba = 0;
-		ide_dev_desc[i].block_read = ide_read;
-		ide_dev_desc[i].block_write = ide_write;
-		if (!ide_bus_ok[IDE_BUS(i)])
-			continue;
-		ide_led(led, 1);	/* LED on       */
-		ide_ident(&ide_dev_desc[i]);
-		ide_led(led, 0);	/* LED off      */
-		dev_print(&ide_dev_desc[i]);
-
-		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
-			/* initialize partition type */
-			part_init(&ide_dev_desc[i]);
-			if (curr_device < 0)
-				curr_device = i;
-		}
-	}
-	WATCHDOG_RESET();
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *ide_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* We only need to swap data if we are running on a big endian cpu. */
-#if defined(__LITTLE_ENDIAN)
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	ide_input_data(dev, sect_buf, words);
-}
-#else
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	volatile ushort *pbuf =
-		(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	ushort *dbuf = (ushort *)sect_buf;
-
-	debug("in input swap data base for read is %lx\n",
-	      (unsigned long) pbuf);
-
-	while (words--) {
-#ifdef __MIPS__
-		*dbuf++ = swab16p((u16 *)pbuf);
-		*dbuf++ = swab16p((u16 *)pbuf);
-#else
-		*dbuf++ = ld_le16(pbuf);
-		*dbuf++ = ld_le16(pbuf);
-#endif /* !MIPS */
-	}
-}
-#endif /* __LITTLE_ENDIAN */
-
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *)sect_buf;
-	while (words--) {
-		EIEIO;
-		*pbuf = *dbuf++;
-		EIEIO;
-		*pbuf = *dbuf++;
-	}
-}
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
-	ide_write_data(dev, sect_buf, words);
-#else
-	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-#endif /* CONFIG_IDE_SWAP_IO */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-	ushort *dbuf;
-	volatile ushort *pbuf;
-
-	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
-	dbuf = (ushort *)sect_buf;
-
-	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
-
-	while (words--) {
-		EIEIO;
-		*dbuf++ = *pbuf;
-		EIEIO;
-		*dbuf++ = *pbuf;
-	}
-}
-#else  /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
-	ide_read_data(dev, sect_buf, words);
-#else
-	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/* ------------------------------------------------------------------------- */
-
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char c;
-	unsigned char pwrsave = 0;	/* power save */
-
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
-
-	if (blknr & 0x0000fffff0000000ULL) {
-		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
-	}
-#endif
-	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
-	      device, blknr, blkcnt, (ulong) buffer);
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-	c = ide_wait(device, IDE_TIME_OUT);
-
-	if (c & ATA_STAT_BUSY) {
-		printf("IDE read: device %d not ready\n", device);
-		goto IDE_READ_E;
-	}
-
-	/* first check if the drive is in Powersaving mode, if yes,
-	 * increase the timeout value */
-	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
-	udelay(50);
-
-	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
-
-	if (c & ATA_STAT_BUSY) {
-		printf("IDE read: device %d not ready\n", device);
-		goto IDE_READ_E;
-	}
-	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
-		printf("No Powersaving mode %X\n", c);
-	} else {
-		c = ide_inb(device, ATA_SECT_CNT);
-		debug("Powersaving %02X\n", c);
-		if (c == 0)
-			pwrsave = 1;
-	}
-
-
-	while (blkcnt-- > 0) {
-
-		c = ide_wait(device, IDE_TIME_OUT);
-
-		if (c & ATA_STAT_BUSY) {
-			printf("IDE read: device %d not ready\n", device);
-			break;
-		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			/* write high bits */
-			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
-			ide_outb(device, ATA_LBA_MID, 0);
-			ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
-		}
-#endif
-		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
-
-		} else
-#endif
-		{
-			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
-		}
-
-		udelay(50);
-
-		if (pwrsave) {
-			/* may take up to 4 sec */
-			c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
-			pwrsave = 0;
-		} else {
-			/* can't take over 500 ms */
-			c = ide_wait(device, IDE_TIME_OUT);
-		}
-
-		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
-		    ATA_STAT_DRQ) {
-			printf("Error (no IRQ) dev %d blk " LBAF
-			       ": status %#02x\n", device, blknr, c);
-			break;
-		}
-
-		ide_input_data(device, buffer, ATA_SECTORWORDS);
-		(void) ide_inb(device, ATA_STATUS);	/* clear IRQ */
-
-		++n;
-		++blknr;
-		buffer += ATA_BLOCKSIZE;
-	}
-IDE_READ_E:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return n;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer)
-{
-	int device = block_dev->devnum;
-	ulong n = 0;
-	unsigned char c;
-
-#ifdef CONFIG_LBA48
-	unsigned char lba48 = 0;
-
-	if (blknr & 0x0000fffff0000000ULL) {
-		/* more than 28 bits used, use 48bit mode */
-		lba48 = 1;
-	}
-#endif
-
-	ide_led(DEVICE_LED(device), 1);	/* LED on       */
-
-	/* Select device
-	 */
-	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
-	while (blkcnt-- > 0) {
-		c = ide_wait(device, IDE_TIME_OUT);
-
-		if (c & ATA_STAT_BUSY) {
-			printf("IDE read: device %d not ready\n", device);
-			goto WR_OUT;
-		}
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			/* write high bits */
-			ide_outb(device, ATA_SECT_CNT, 0);
-			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
-			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
-			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
-			ide_outb(device, ATA_LBA_MID, 0);
-			ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
-		}
-#endif
-		ide_outb(device, ATA_SECT_CNT, 1);
-		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
-		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
-		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
-		if (lba48) {
-			ide_outb(device, ATA_DEV_HD,
-				 ATA_LBA | ATA_DEVICE(device));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
-
-		} else
-#endif
-		{
-			ide_outb(device, ATA_DEV_HD, ATA_LBA |
-				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
-			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
-		}
-
-		udelay(50);
-
-		/* can't take over 500 ms */
-		c = ide_wait(device, IDE_TIME_OUT);
-
-		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
-		    ATA_STAT_DRQ) {
-			printf("Error (no IRQ) dev %d blk " LBAF
-			       ": status %#02x\n", device, blknr, c);
-			goto WR_OUT;
-		}
-
-		ide_output_data(device, buffer, ATA_SECTORWORDS);
-		c = ide_inb(device, ATA_STATUS);	/* clear IRQ */
-		++n;
-		++blknr;
-		buffer += ATA_BLOCKSIZE;
-	}
-WR_OUT:
-	ide_led(DEVICE_LED(device), 0);	/* LED off      */
-	return n;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
-{
-	if (dev >= CONFIG_SYS_IDE_MAXBUS)
-		return 0;
-	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
-}
-#endif
-/* ------------------------------------------------------------------------- */
-
 U_BOOT_CMD(ide, 5, 1, do_ide,
 	   "IDE sub-system",
 	   "reset - reset IDE controller\n"
diff --git a/common/Makefile b/common/Makefile
index 397df61..1df5add 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -134,6 +134,7 @@ obj-y += dlmalloc.o
 ifdef CONFIG_SYS_MALLOC_F_LEN
 obj-y += malloc_simple.o
 endif
+obj-$(CONFIG_CMD_IDE) += ide.o
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
diff --git a/common/ide.c b/common/ide.c
new file mode 100644
index 0000000..adc1966
--- /dev/null
+++ b/common/ide.c
@@ -0,0 +1,1206 @@
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ata.h>
+#include <ide.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#ifdef __PPC__
+# define EIEIO		__asm__ volatile ("eieio")
+# define SYNC		__asm__ volatile ("sync")
+#else
+# define EIEIO		/* nothing */
+# define SYNC		/* nothing */
+#endif
+
+/* Current offset for IDE0 / IDE1 bus access	*/
+ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
+#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
+	CONFIG_SYS_ATA_IDE0_OFFSET,
+#endif
+#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
+	CONFIG_SYS_ATA_IDE1_OFFSET,
+#endif
+};
+
+static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
+
+struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+#define IDE_TIME_OUT	2000	/* 2 sec timeout */
+
+#define ATAPI_TIME_OUT	7000	/* 7 sec timeout (5 sec seems to work...) */
+
+#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
+
+#ifndef CONFIG_SYS_ATA_PORT_ADDR
+#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
+#endif
+
+#ifndef CONFIG_IDE_LED	/* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
+#endif
+
+#ifdef CONFIG_IDE_RESET
+extern void ide_set_reset(int idereset);
+
+static void ide_reset(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
+		ide_bus_ok[i] = 0;
+	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
+		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+
+	ide_set_reset(1);	/* assert reset */
+
+	/* the reset signal shall be asserted for et least 25 us */
+	udelay(25);
+
+	WATCHDOG_RESET();
+
+	/* de-assert RESET signal */
+	ide_set_reset(0);
+
+	/* wait 250 ms */
+	for (i = 0; i < 250; ++i)
+		udelay(1000);
+}
+#else
+#define ide_reset()	/* dummy */
+#endif /* CONFIG_IDE_RESET */
+
+/*
+ * Wait until Busy bit is off, or timeout (in ms)
+ * Return last status
+ */
+static uchar ide_wait(int dev, ulong t)
+{
+	ulong delay = 10 * t;	/* poll every 100 us */
+	uchar c;
+
+	while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
+		udelay(100);
+		if (delay-- == 0)
+			break;
+	}
+	return c;
+}
+
+/*
+ * copy src to dest, skipping leading and trailing blanks and null
+ * terminate the string
+ * "len" is the size of available memory including the terminating '\0'
+ */
+static void ident_cpy(unsigned char *dst, unsigned char *src,
+		      unsigned int len)
+{
+	unsigned char *end, *last;
+
+	last = dst;
+	end = src + len - 1;
+
+	/* reserve space for '\0' */
+	if (len < 2)
+		goto OUT;
+
+	/* skip leading white space */
+	while ((*src) && (src < end) && (*src == ' '))
+		++src;
+
+	/* copy string, omitting trailing white space */
+	while ((*src) && (src < end)) {
+		*dst++ = *src;
+		if (*src++ != ' ')
+			last = dst;
+	}
+OUT:
+	*last = '\0';
+}
+
+#ifdef CONFIG_ATAPI
+/****************************************************************************
+ * ATAPI Support
+ */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+/* since ATAPI may use commands with not 4 bytes alligned length
+ * we have our own transfer functions, 2 bytes alligned */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+
+	debug("in output data shorts base for read is %lx\n",
+	      (unsigned long) pbuf);
+
+	while (shorts--) {
+		EIEIO;
+		*pbuf = *dbuf++;
+	}
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+
+	debug("in input data shorts base for read is %lx\n",
+	      (unsigned long) pbuf);
+
+	while (shorts--) {
+		EIEIO;
+		*dbuf++ = *pbuf;
+	}
+}
+
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+/*
+ * Wait until (Status & mask) == res, or timeout (in ms)
+ * Return last status
+ * This is used since some ATAPI CD ROMs clears their Busy Bit first
+ * and then they set their DRQ Bit
+ */
+static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
+{
+	ulong delay = 10 * t;	/* poll every 100 us */
+	uchar c;
+
+	/* prevents to read the status before valid */
+	c = ide_inb(dev, ATA_DEV_CTL);
+
+	while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+		/* break if error occurs (doesn't make sense to wait more) */
+		if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
+			break;
+		udelay(100);
+		if (delay-- == 0)
+			break;
+	}
+	return c;
+}
+
+/*
+ * issue an atapi command
+ */
+unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
+			  unsigned char *buffer, int buflen)
+{
+	unsigned char c, err, mask, res;
+	int n;
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+
+	/* Select device
+	 */
+	mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
+	res = 0;
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & mask) != res) {
+		printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+		       c);
+		err = 0xFF;
+		goto AI_OUT;
+	}
+	/* write taskfile */
+	ide_outb(device, ATA_ERROR_REG, 0);	/* no DMA, no overlaped */
+	ide_outb(device, ATA_SECT_CNT, 0);
+	ide_outb(device, ATA_SECT_NUM, 0);
+	ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
+	ide_outb(device, ATA_CYL_HIGH,
+		 (unsigned char) ((buflen >> 8) & 0xFF));
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+	ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
+	udelay(50);
+
+	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+	res = ATA_STAT_DRQ;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+
+	if ((c & mask) != res) {	/* DRQ must be 1, BSY 0 */
+		printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+		       device, c);
+		err = 0xFF;
+		goto AI_OUT;
+	}
+
+	/* write command block */
+	ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
+
+	/* ATAPI Command written wait for completition */
+	udelay(5000);		/* device must set bsy */
+
+	mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+	/*
+	 * if no data wait for DRQ = 0 BSY = 0
+	 * if data wait for DRQ = 1 BSY = 0
+	 */
+	res = 0;
+	if (buflen)
+		res = ATA_STAT_DRQ;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & mask) != res) {
+		if (c & ATA_STAT_ERR) {
+			err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
+			debug("atapi_issue 1 returned sense key %X status %02X\n",
+			      err, c);
+		} else {
+			printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x)  status 0x%02x\n",
+			       ccb[0], c);
+			err = 0xFF;
+		}
+		goto AI_OUT;
+	}
+	n = ide_inb(device, ATA_CYL_HIGH);
+	n <<= 8;
+	n += ide_inb(device, ATA_CYL_LOW);
+	if (n > buflen) {
+		printf("ERROR, transfer bytes %d requested only %d\n", n,
+		       buflen);
+		err = 0xff;
+		goto AI_OUT;
+	}
+	if ((n == 0) && (buflen < 0)) {
+		printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
+		err = 0xff;
+		goto AI_OUT;
+	}
+	if (n != buflen) {
+		debug("WARNING, transfer bytes %d not equal with requested %d\n",
+		      n, buflen);
+	}
+	if (n != 0) {		/* data transfer */
+		debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+		/* we transfer shorts */
+		n >>= 1;
+		/* ok now decide if it is an in or output */
+		if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
+			debug("Write to device\n");
+			ide_output_data_shorts(device, (unsigned short *)buffer,
+					       n);
+		} else {
+			debug("Read from device @ %p shorts %d\n", buffer, n);
+			ide_input_data_shorts(device, (unsigned short *)buffer,
+					      n);
+		}
+	}
+	udelay(5000);		/* seems that some CD ROMs need this... */
+	mask = ATA_STAT_BUSY | ATA_STAT_ERR;
+	res = 0;
+	c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+		err = (ide_inb(device, ATA_ERROR_REG) >> 4);
+		debug("atapi_issue 2 returned sense key %X status %X\n", err,
+		      c);
+	} else {
+		err = 0;
+	}
+AI_OUT:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return err;
+}
+
+/*
+ * sending the command to atapi_issue. If an status other than good
+ * returns, an request_sense will be issued
+ */
+
+#define ATAPI_DRIVE_NOT_READY	100
+#define ATAPI_UNIT_ATTN		10
+
+unsigned char atapi_issue_autoreq(int device,
+				  unsigned char *ccb,
+				  int ccblen,
+				  unsigned char *buffer, int buflen)
+{
+	unsigned char sense_data[18], sense_ccb[12];
+	unsigned char res, key, asc, ascq;
+	int notready, unitattn;
+
+	unitattn = ATAPI_UNIT_ATTN;
+	notready = ATAPI_DRIVE_NOT_READY;
+
+retry:
+	res = atapi_issue(device, ccb, ccblen, buffer, buflen);
+	if (res == 0)
+		return 0;	/* Ok */
+
+	if (res == 0xFF)
+		return 0xFF;	/* error */
+
+	debug("(auto_req)atapi_issue returned sense key %X\n", res);
+
+	memset(sense_ccb, 0, sizeof(sense_ccb));
+	memset(sense_data, 0, sizeof(sense_data));
+	sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
+	sense_ccb[4] = 18;	/* allocation Length */
+
+	res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
+	key = (sense_data[2] & 0xF);
+	asc = (sense_data[12]);
+	ascq = (sense_data[13]);
+
+	debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+	debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+	      sense_data[0], key, asc, ascq);
+
+	if ((key == 0))
+		return 0;	/* ok device ready */
+
+	if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+		if (unitattn-- > 0) {
+			udelay(200 * 1000);
+			goto retry;
+		}
+		printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
+		goto error;
+	}
+	if ((asc == 0x4) && (ascq == 0x1)) {
+		/* not ready, but will be ready soon */
+		if (notready-- > 0) {
+			udelay(200 * 1000);
+			goto retry;
+		}
+		printf("Drive not ready, tried %d times\n",
+		       ATAPI_DRIVE_NOT_READY);
+		goto error;
+	}
+	if (asc == 0x3a) {
+		debug("Media not present\n");
+		goto error;
+	}
+
+	printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
+	       ascq);
+error:
+	debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+	return 0xFF;
+}
+
+/*
+ * atapi_read:
+ * we transfer only one block per command, since the multiple DRQ per
+ * command is not yet implemented
+ */
+#define ATAPI_READ_MAX_BYTES	2048	/* we read max 2kbytes */
+#define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
+#define ATAPI_READ_MAX_BLOCK	(ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
+
+ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		 void *buffer)
+{
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char ccb[12];	/* Command descriptor block */
+	ulong cnt;
+
+	debug("atapi_read dev %d start " LBAF " blocks " LBAF
+	      " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+
+	do {
+		if (blkcnt > ATAPI_READ_MAX_BLOCK)
+			cnt = ATAPI_READ_MAX_BLOCK;
+		else
+			cnt = blkcnt;
+
+		ccb[0] = ATAPI_CMD_READ_12;
+		ccb[1] = 0;	/* reserved */
+		ccb[2] = (unsigned char) (blknr >> 24) & 0xFF;	/* MSB Block */
+		ccb[3] = (unsigned char) (blknr >> 16) & 0xFF;	/*  */
+		ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
+		ccb[5] = (unsigned char) blknr & 0xFF;	/* LSB Block */
+		ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
+		ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
+		ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
+		ccb[9] = (unsigned char) cnt & 0xFF;	/* LSB Block */
+		ccb[10] = 0;	/* reserved */
+		ccb[11] = 0;	/* reserved */
+
+		if (atapi_issue_autoreq(device, ccb, 12,
+					(unsigned char *)buffer,
+					cnt * ATAPI_READ_BLOCK_SIZE)
+		    == 0xFF) {
+			return n;
+		}
+		n += cnt;
+		blkcnt -= cnt;
+		blknr += cnt;
+		buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+	} while (blkcnt > 0);
+	return n;
+}
+
+static void atapi_inquiry(struct blk_desc *dev_desc)
+{
+	unsigned char ccb[12];	/* Command descriptor block */
+	unsigned char iobuf[64];	/* temp buf */
+	unsigned char c;
+	int device;
+
+	device = dev_desc->devnum;
+	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
+	dev_desc->block_read = atapi_read;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+
+	ccb[0] = ATAPI_CMD_INQUIRY;
+	ccb[4] = 40;		/* allocation Legnth */
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
+
+	debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+	if (c != 0)
+		return;
+
+	/* copy device ident strings */
+	ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
+	ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
+	ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
+
+	dev_desc->lun = 0;
+	dev_desc->lba = 0;
+	dev_desc->blksz = 0;
+	dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
+	dev_desc->type = iobuf[0] & 0x1f;
+
+	if ((iobuf[1] & 0x80) == 0x80)
+		dev_desc->removable = 1;
+	else
+		dev_desc->removable = 0;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	ccb[0] = ATAPI_CMD_START_STOP;
+	ccb[4] = 0x03;		/* start */
+
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+	debug("ATAPI_CMD_START_STOP returned %x\n", c);
+	if (c != 0)
+		return;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+	debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+	if (c != 0)
+		return;
+
+	memset(ccb, 0, sizeof(ccb));
+	memset(iobuf, 0, sizeof(iobuf));
+	ccb[0] = ATAPI_CMD_READ_CAP;
+	c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
+	debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+	if (c != 0)
+		return;
+
+	debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+	      iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+	      iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+
+	dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
+		((unsigned long) iobuf[1] << 16) +
+		((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
+	dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
+		((unsigned long) iobuf[5] << 16) +
+		((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
+	dev_desc->log2blksz = LOG2(dev_desc->blksz);
+#ifdef CONFIG_LBA48
+	/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
+	dev_desc->lba48 = 0;
+#endif
+	return;
+}
+
+#endif /* CONFIG_ATAPI */
+
+static void ide_ident(struct blk_desc *dev_desc)
+{
+	unsigned char c;
+	hd_driveid_t iop;
+
+#ifdef CONFIG_ATAPI
+	int retries = 0;
+#endif
+	int device;
+
+	device = dev_desc->devnum;
+	printf("  Device %d: ", device);
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	dev_desc->if_type = IF_TYPE_IDE;
+#ifdef CONFIG_ATAPI
+
+	retries = 0;
+
+	/* Warning: This will be tricky to read */
+	while (retries <= 1) {
+		/* check signature */
+		if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
+		    (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
+		    (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
+		    (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
+			/* ATAPI Signature found */
+			dev_desc->if_type = IF_TYPE_ATAPI;
+			/*
+			 * Start Ident Command
+			 */
+			ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
+			/*
+			 * Wait for completion - ATAPI devices need more time
+			 * to become ready
+			 */
+			c = ide_wait(device, ATAPI_TIME_OUT);
+		} else
+#endif
+		{
+			/*
+			 * Start Ident Command
+			 */
+			ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
+
+			/*
+			 * Wait for completion
+			 */
+			c = ide_wait(device, IDE_TIME_OUT);
+		}
+		ide_led(DEVICE_LED(device), 0);	/* LED off      */
+
+		if (((c & ATA_STAT_DRQ) == 0) ||
+		    ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
+#ifdef CONFIG_ATAPI
+			{
+				/*
+				 * Need to soft reset the device
+				 * in case it's an ATAPI...
+				 */
+				debug("Retrying...\n");
+				ide_outb(device, ATA_DEV_HD,
+					 ATA_LBA | ATA_DEVICE(device));
+				udelay(100000);
+				ide_outb(device, ATA_COMMAND, 0x08);
+				udelay(500000);	/* 500 ms */
+			}
+			/*
+			 * Select device
+			 */
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			retries++;
+#else
+			return;
+#endif
+		}
+#ifdef CONFIG_ATAPI
+		else
+			break;
+	}			/* see above - ugly to read */
+
+	if (retries == 2)	/* Not found */
+		return;
+#endif
+
+	ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
+
+	ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
+		  sizeof(dev_desc->revision));
+	ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
+		  sizeof(dev_desc->vendor));
+	ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
+		  sizeof(dev_desc->product));
+#ifdef __LITTLE_ENDIAN
+	/*
+	 * firmware revision, model, and serial number have Big Endian Byte
+	 * order in Word. Convert all three to little endian.
+	 *
+	 * See CF+ and CompactFlash Specification Revision 2.0:
+	 * 6.2.1.6: Identify Drive, Table 39 for more details
+	 */
+
+	strswab(dev_desc->revision);
+	strswab(dev_desc->vendor);
+	strswab(dev_desc->product);
+#endif /* __LITTLE_ENDIAN */
+
+	if ((iop.config & 0x0080) == 0x0080)
+		dev_desc->removable = 1;
+	else
+		dev_desc->removable = 0;
+
+#ifdef CONFIG_ATAPI
+	if (dev_desc->if_type == IF_TYPE_ATAPI) {
+		atapi_inquiry(dev_desc);
+		return;
+	}
+#endif /* CONFIG_ATAPI */
+
+#ifdef __BIG_ENDIAN
+	/* swap shorts */
+	dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
+#else  /* ! __BIG_ENDIAN */
+	/*
+	 * do not swap shorts on little endian
+	 *
+	 * See CF+ and CompactFlash Specification Revision 2.0:
+	 * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
+	 */
+	dev_desc->lba = iop.lba_capacity;
+#endif /* __BIG_ENDIAN */
+
+#ifdef CONFIG_LBA48
+	if (iop.command_set_2 & 0x0400) {	/* LBA 48 support */
+		dev_desc->lba48 = 1;
+		dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
+			((unsigned long long) iop.lba48_capacity[1] << 16) |
+			((unsigned long long) iop.lba48_capacity[2] << 32) |
+			((unsigned long long) iop.lba48_capacity[3] << 48);
+	} else {
+		dev_desc->lba48 = 0;
+	}
+#endif /* CONFIG_LBA48 */
+	/* assuming HD */
+	dev_desc->type = DEV_TYPE_HARDDISK;
+	dev_desc->blksz = ATA_BLOCKSIZE;
+	dev_desc->log2blksz = LOG2(dev_desc->blksz);
+	dev_desc->lun = 0;	/* just to fill something in... */
+
+#if 0				/* only used to test the powersaving mode,
+				 * if enabled, the drive goes after 5 sec
+				 * in standby mode */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = ide_wait(device, IDE_TIME_OUT);
+	ide_outb(device, ATA_SECT_CNT, 1);
+	ide_outb(device, ATA_LBA_LOW, 0);
+	ide_outb(device, ATA_LBA_MID, 0);
+	ide_outb(device, ATA_LBA_HIGH, 0);
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	ide_outb(device, ATA_COMMAND, 0xe3);
+	udelay(50);
+	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
+#endif
+}
+
+__weak void ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+	static uchar led_buffer;	/* Buffer for current LED status */
+
+	uchar *led_port = LED_PORT;
+
+	if (status)		/* switch LED on        */
+		led_buffer |= led;
+	else			/* switch LED off       */
+		led_buffer &= ~led;
+
+	*led_port = led_buffer;
+#endif
+}
+
+__weak void ide_outb(int dev, int port, unsigned char val)
+{
+	debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+	      dev, port, val,
+	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+
+#if defined(CONFIG_IDE_AHB)
+	if (port) {
+		/* write command */
+		ide_write_register(dev, port, val);
+	} else {
+		/* write data */
+		outb(val, (ATA_CURR_BASE(dev)));
+	}
+#else
+	outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+}
+
+__weak unsigned char ide_inb(int dev, int port)
+{
+	uchar val;
+
+#if defined(CONFIG_IDE_AHB)
+	val = ide_read_register(dev, port);
+#else
+	val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+
+	debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+	      dev, port,
+	      (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+	return val;
+}
+
+void ide_init(void)
+{
+	unsigned char c;
+	int i, bus;
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+	extern int ide_devices_found;	/* Initialized in check_ide_device() */
+#endif /* CONFIG_IDE_8xx_PCCARD */
+
+#ifdef CONFIG_IDE_PREINIT
+	WATCHDOG_RESET();
+
+	if (ide_preinit()) {
+		puts("ide_preinit failed\n");
+		return;
+	}
+#endif /* CONFIG_IDE_PREINIT */
+
+	WATCHDOG_RESET();
+
+	/*
+	 * Reset the IDE just to be sure.
+	 * Light LED's to show
+	 */
+	ide_led((LED_IDE1 | LED_IDE2), 1);	/* LED's on     */
+
+	/* ATAPI Drives seems to need a proper IDE Reset */
+	ide_reset();
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+	WATCHDOG_RESET();
+
+	if (ide_init_postreset()) {
+		puts("ide_preinit_postreset failed\n");
+		return;
+	}
+#endif /* CONFIG_IDE_INIT_POSTRESET */
+
+	/*
+	 * Wait for IDE to get ready.
+	 * According to spec, this can take up to 31 seconds!
+	 */
+	for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+		int dev =
+			bus * (CONFIG_SYS_IDE_MAXDEVICE /
+			       CONFIG_SYS_IDE_MAXBUS);
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+		/* Skip non-ide devices from probing */
+		if ((ide_devices_found & (1 << bus)) == 0) {
+			ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off */
+			continue;
+		}
+#endif
+		printf("Bus %d: ", bus);
+
+		ide_bus_ok[bus] = 0;
+
+		/* Select device
+		 */
+		udelay(100000);	/* 100 ms */
+		ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+		udelay(100000);	/* 100 ms */
+		i = 0;
+		do {
+			udelay(10000);	/* 10 ms */
+
+			c = ide_inb(dev, ATA_STATUS);
+			i++;
+			if (i > (ATA_RESET_TIME * 100)) {
+				puts("** Timeout **\n");
+				/* LED's off */
+				ide_led((LED_IDE1 | LED_IDE2), 0);
+				return;
+			}
+			if ((i >= 100) && ((i % 100) == 0))
+				putc('.');
+
+		} while (c & ATA_STAT_BUSY);
+
+		if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+			puts("not available  ");
+			debug("Status = 0x%02X ", c);
+#ifndef CONFIG_ATAPI		/* ATAPI Devices do not set DRDY */
+		} else if ((c & ATA_STAT_READY) == 0) {
+			puts("not available  ");
+			debug("Status = 0x%02X ", c);
+#endif
+		} else {
+			puts("OK ");
+			ide_bus_ok[bus] = 1;
+		}
+		WATCHDOG_RESET();
+	}
+
+	putc('\n');
+
+	ide_led((LED_IDE1 | LED_IDE2), 0);	/* LED's off    */
+
+	for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
+		int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
+		ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+		ide_dev_desc[i].if_type = IF_TYPE_IDE;
+		ide_dev_desc[i].devnum = i;
+		ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		ide_dev_desc[i].blksz = 0;
+		ide_dev_desc[i].log2blksz =
+			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
+		ide_dev_desc[i].lba = 0;
+		ide_dev_desc[i].block_read = ide_read;
+		ide_dev_desc[i].block_write = ide_write;
+		if (!ide_bus_ok[IDE_BUS(i)])
+			continue;
+		ide_led(led, 1);	/* LED on       */
+		ide_ident(&ide_dev_desc[i]);
+		ide_led(led, 0);	/* LED off      */
+		dev_print(&ide_dev_desc[i]);
+
+		if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
+			/* initialize partition type */
+			part_init(&ide_dev_desc[i]);
+		}
+	}
+	WATCHDOG_RESET();
+}
+
+#ifdef CONFIG_PARTITIONS
+struct blk_desc *ide_get_dev(int dev)
+{
+	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
+}
+#endif
+
+/* We only need to swap data if we are running on a big endian cpu. */
+#if defined(__LITTLE_ENDIAN)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	ide_input_data(dev, sect_buf, words);
+}
+#else
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	volatile ushort *pbuf =
+		(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	ushort *dbuf = (ushort *)sect_buf;
+
+	debug("in input swap data base for read is %lx\n",
+	      (unsigned long) pbuf);
+
+	while (words--) {
+#ifdef __MIPS__
+		*dbuf++ = swab16p((u16 *)pbuf);
+		*dbuf++ = swab16p((u16 *)pbuf);
+#else
+		*dbuf++ = ld_le16(pbuf);
+		*dbuf++ = ld_le16(pbuf);
+#endif /* !MIPS */
+	}
+}
+#endif /* __LITTLE_ENDIAN */
+
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+	while (words--) {
+		EIEIO;
+		*pbuf = *dbuf++;
+		EIEIO;
+		*pbuf = *dbuf++;
+	}
+}
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+	ide_write_data(dev, sect_buf, words);
+#else
+	outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *)sect_buf;
+
+	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+	while (words--) {
+		EIEIO;
+		*dbuf++ = *pbuf;
+		EIEIO;
+		*dbuf++ = *pbuf;
+	}
+}
+#else  /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+	ide_read_data(dev, sect_buf, words);
+#else
+	insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer)
+{
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char c;
+	unsigned char pwrsave = 0;	/* power save */
+
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
+
+	if (blknr & 0x0000fffff0000000ULL) {
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
+	debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
+	      device, blknr, blkcnt, (ulong) buffer);
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+	c = ide_wait(device, IDE_TIME_OUT);
+
+	if (c & ATA_STAT_BUSY) {
+		printf("IDE read: device %d not ready\n", device);
+		goto IDE_READ_E;
+	}
+
+	/* first check if the drive is in Powersaving mode, if yes,
+	 * increase the timeout value */
+	ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
+	udelay(50);
+
+	c = ide_wait(device, IDE_TIME_OUT);	/* can't take over 500 ms */
+
+	if (c & ATA_STAT_BUSY) {
+		printf("IDE read: device %d not ready\n", device);
+		goto IDE_READ_E;
+	}
+	if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+		printf("No Powersaving mode %X\n", c);
+	} else {
+		c = ide_inb(device, ATA_SECT_CNT);
+		debug("Powersaving %02X\n", c);
+		if (c == 0)
+			pwrsave = 1;
+	}
+
+
+	while (blkcnt-- > 0) {
+		c = ide_wait(device, IDE_TIME_OUT);
+
+		if (c & ATA_STAT_BUSY) {
+			printf("IDE read: device %d not ready\n", device);
+			break;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			ide_outb(device, ATA_SECT_CNT, 0);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb(device, ATA_LBA_MID, 0);
+			ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+		}
+#endif
+		ide_outb(device, ATA_SECT_CNT, 1);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
+
+		} else
+#endif
+		{
+			ide_outb(device, ATA_DEV_HD, ATA_LBA |
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
+		}
+
+		udelay(50);
+
+		if (pwrsave) {
+			/* may take up to 4 sec */
+			c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
+			pwrsave = 0;
+		} else {
+			/* can't take over 500 ms */
+			c = ide_wait(device, IDE_TIME_OUT);
+		}
+
+		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+		    ATA_STAT_DRQ) {
+			printf("Error (no IRQ) dev %d blk " LBAF
+			       ": status %#02x\n", device, blknr, c);
+			break;
+		}
+
+		ide_input_data(device, buffer, ATA_SECTORWORDS);
+		(void) ide_inb(device, ATA_STATUS);	/* clear IRQ */
+
+		++n;
+		++blknr;
+		buffer += ATA_BLOCKSIZE;
+	}
+IDE_READ_E:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return n;
+}
+
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer)
+{
+	int device = block_dev->devnum;
+	ulong n = 0;
+	unsigned char c;
+
+#ifdef CONFIG_LBA48
+	unsigned char lba48 = 0;
+
+	if (blknr & 0x0000fffff0000000ULL) {
+		/* more than 28 bits used, use 48bit mode */
+		lba48 = 1;
+	}
+#endif
+
+	ide_led(DEVICE_LED(device), 1);	/* LED on       */
+
+	/* Select device
+	 */
+	ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+	while (blkcnt-- > 0) {
+		c = ide_wait(device, IDE_TIME_OUT);
+
+		if (c & ATA_STAT_BUSY) {
+			printf("IDE read: device %d not ready\n", device);
+			goto WR_OUT;
+		}
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			/* write high bits */
+			ide_outb(device, ATA_SECT_CNT, 0);
+			ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+			ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+			ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb(device, ATA_LBA_MID, 0);
+			ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+		}
+#endif
+		ide_outb(device, ATA_SECT_CNT, 1);
+		ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+		ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+		ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+		if (lba48) {
+			ide_outb(device, ATA_DEV_HD,
+				 ATA_LBA | ATA_DEVICE(device));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
+
+		} else
+#endif
+		{
+			ide_outb(device, ATA_DEV_HD, ATA_LBA |
+				 ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+			ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
+		}
+
+		udelay(50);
+
+		/* can't take over 500 ms */
+		c = ide_wait(device, IDE_TIME_OUT);
+
+		if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+		    ATA_STAT_DRQ) {
+			printf("Error (no IRQ) dev %d blk " LBAF
+			       ": status %#02x\n", device, blknr, c);
+			goto WR_OUT;
+		}
+
+		ide_output_data(device, buffer, ATA_SECTORWORDS);
+		c = ide_inb(device, ATA_STATUS);	/* clear IRQ */
+		++n;
+		++blknr;
+		buffer += ATA_BLOCKSIZE;
+	}
+WR_OUT:
+	ide_led(DEVICE_LED(device), 0);	/* LED off      */
+	return n;
+}
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev)
+{
+	if (dev >= CONFIG_SYS_IDE_MAXBUS)
+		return 0;
+	return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
+}
+#endif
+
+U_BOOT_LEGACY_BLK(ide) = {
+	.if_typename	= "ide",
+	.if_type	= IF_TYPE_IDE,
+	.max_devs	= CONFIG_SYS_IDE_MAXDEVICE,
+	.desc		= ide_dev_desc,
+};
-- 
cgit v0.10.2


From d97dc8a0e6d38d11848ee78669639324edc0df01 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:11 -0600
Subject: dm: sata: Separate the non-command code into its own file

At present the SATA command code includes both the command-processing code
and the core SATA functions and data structures.

Separate the latter into its own file, adding functions as needed to avoid
the command code accessing data structures directly.

With this commit:
- All CONFIG option are referenced from the non-command code
- The concept of a 'current SATA device' is confined to the command code

This will make it easier to convert this code to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/sata.c b/cmd/sata.c
index b1a64d9..d18b523 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -16,70 +16,6 @@
 #include <sata.h>
 
 static int sata_curr_device = -1;
-struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
-				lbaint_t blkcnt, void *dst)
-{
-	return sata_read(block_dev->devnum, start, blkcnt, dst);
-}
-
-static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
-				 lbaint_t blkcnt, const void *buffer)
-{
-	return sata_write(block_dev->devnum, start, blkcnt, buffer);
-}
-
-int __sata_initialize(void)
-{
-	int rc;
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
-		memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
-		sata_dev_desc[i].if_type = IF_TYPE_SATA;
-		sata_dev_desc[i].devnum = i;
-		sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-		sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
-		sata_dev_desc[i].lba = 0;
-		sata_dev_desc[i].blksz = 512;
-		sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
-		sata_dev_desc[i].block_read = sata_bread;
-		sata_dev_desc[i].block_write = sata_bwrite;
-
-		rc = init_sata(i);
-		if (!rc) {
-			rc = scan_sata(i);
-			if (!rc && (sata_dev_desc[i].lba > 0) &&
-				(sata_dev_desc[i].blksz > 0))
-				part_init(&sata_dev_desc[i]);
-		}
-	}
-	sata_curr_device = 0;
-	return rc;
-}
-int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
-
-__weak int __sata_stop(void)
-{
-	int i, err = 0;
-
-	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
-		err |= reset_sata(i);
-
-	if (err)
-		printf("Could not reset some SATA devices\n");
-
-	return err;
-}
-int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *sata_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
-}
-#endif
 
 static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -106,70 +42,39 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return CMD_RET_USAGE;
 	case 2:
 		if (strncmp(argv[1], "inf", 3) == 0) {
-			int i;
-
-			putc('\n');
-			for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; ++i) {
-				if (sata_dev_desc[i].type == DEV_TYPE_UNKNOWN)
-					continue;
-				printf("SATA device %d: ", i);
-				dev_print(&sata_dev_desc[i]);
-			}
+			blk_list_devices(IF_TYPE_SATA);
 			return 0;
 		} else if (strncmp(argv[1], "dev", 3) == 0) {
-			if (sata_curr_device < 0 ||
-			    sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE) {
-				puts("\nno SATA devices available\n");
-				return 1;
+			if (blk_print_device_num(IF_TYPE_SATA,
+						 sata_curr_device)) {
+				printf("\nno SATA devices available\n");
+				return CMD_RET_FAILURE;
 			}
-			printf("\nSATA device %d: ", sata_curr_device);
-			dev_print(&sata_dev_desc[sata_curr_device]);
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
-			int dev, ok;
-
-			for (ok = 0, dev = 0; dev < CONFIG_SYS_SATA_MAX_DEVICE; ++dev) {
-				if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-					++ok;
-					if (dev)
-						putc ('\n');
-					part_print(&sata_dev_desc[dev]);
-				}
-			}
-			if (!ok) {
+			if (blk_list_part(IF_TYPE_SATA))
 				puts("\nno SATA devices available\n");
-				rc ++;
-			}
-			return rc;
+			return 0;
 		}
 		return CMD_RET_USAGE;
 	case 3:
 		if (strncmp(argv[1], "dev", 3) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			printf("\nSATA device %d: ", dev);
-			if (dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
-				puts ("unknown device\n");
-				return 1;
+			if (!blk_show_device(IF_TYPE_SATA, dev)) {
+				sata_curr_device = dev;
+				printf("... is now current device\n");
+			} else {
+				return CMD_RET_FAILURE;
 			}
-			dev_print(&sata_dev_desc[dev]);
-
-			if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
-				return 1;
-
-			sata_curr_device = dev;
-
-			puts("... is now current device\n");
-
 			return 0;
 		} else if (strncmp(argv[1], "part", 4) == 0) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 
-			if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
-				part_print(&sata_dev_desc[dev]);
-			} else {
-				printf("\nSATA device %d not available\n", dev);
-				rc = 1;
+			if (blk_print_part_devnum(IF_TYPE_SATA, dev)) {
+				printf("\nSATA device %d not available\n",
+				       dev);
+				return CMD_RET_FAILURE;
 			}
 			return rc;
 		}
@@ -185,11 +90,8 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			printf("\nSATA read: device %d block # %ld, count %ld ... ",
 				sata_curr_device, blk, cnt);
 
-			n = blk_dread(&sata_dev_desc[sata_curr_device],
-				      blk, cnt, (u32 *)addr);
-
-			/* flush cache after read */
-			flush_cache(addr, cnt * sata_dev_desc[sata_curr_device].blksz);
+			n = blk_read_devnum(IF_TYPE_SATA, sata_curr_device, blk,
+					    cnt, (ulong *)addr);
 
 			printf("%ld blocks read: %s\n",
 				n, (n==cnt) ? "OK" : "ERROR");
@@ -204,8 +106,8 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			printf("\nSATA write: device %d block # %ld, count %ld ... ",
 				sata_curr_device, blk, cnt);
 
-			n = blk_dwrite(&sata_dev_desc[sata_curr_device],
-				       blk, cnt, (u32 *)addr);
+			n = blk_write_devnum(IF_TYPE_SATA, sata_curr_device,
+					     blk, cnt, (ulong *)addr);
 
 			printf("%ld blocks written: %s\n",
 				n, (n == cnt) ? "OK" : "ERROR");
diff --git a/common/Makefile b/common/Makefile
index 1df5add..f9b26b7 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o
 obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
 obj-$(CONFIG_LYNXKDI) += lynxkdi.o
 obj-$(CONFIG_MENU) += menu.o
+obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_SCSI) += scsi.o
 obj-$(CONFIG_UPDATE_TFTP) += update.o
 obj-$(CONFIG_DFU_TFTP) += update.o
diff --git a/common/sata.c b/common/sata.c
new file mode 100644
index 0000000..1d52fcb
--- /dev/null
+++ b/common/sata.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2000-2005, DENX Software Engineering
+ *		Wolfgang Denk <wd@denx.de>
+ * Copyright (C) Procsys. All rights reserved.
+ *		Mushtaq Khan <mushtaq_k@procsys.com>
+ *			<mushtaqk_921@yahoo.co.in>
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+
+struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+
+#ifdef CONFIG_PARTITIONS
+struct blk_desc *sata_get_dev(int dev)
+{
+	return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
+}
+#endif
+
+static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
+				lbaint_t blkcnt, void *dst)
+{
+	return sata_read(block_dev->devnum, start, blkcnt, dst);
+}
+
+static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
+				 lbaint_t blkcnt, const void *buffer)
+{
+	return sata_write(block_dev->devnum, start, blkcnt, buffer);
+}
+
+int __sata_initialize(void)
+{
+	int rc;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
+		memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
+		sata_dev_desc[i].if_type = IF_TYPE_SATA;
+		sata_dev_desc[i].devnum = i;
+		sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
+		sata_dev_desc[i].lba = 0;
+		sata_dev_desc[i].blksz = 512;
+		sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
+		sata_dev_desc[i].block_read = sata_bread;
+		sata_dev_desc[i].block_write = sata_bwrite;
+
+		rc = init_sata(i);
+		if (!rc) {
+			rc = scan_sata(i);
+			if (!rc && sata_dev_desc[i].lba > 0 &&
+			    sata_dev_desc[i].blksz > 0)
+				part_init(&sata_dev_desc[i]);
+		}
+	}
+
+	return rc;
+}
+int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
+
+__weak int __sata_stop(void)
+{
+	int i, err = 0;
+
+	for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
+		err |= reset_sata(i);
+
+	if (err)
+		printf("Could not reset some SATA devices\n");
+
+	return err;
+}
+int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
+
+U_BOOT_LEGACY_BLK(sata) = {
+	.if_typename	= "sata",
+	.if_type	= IF_TYPE_SATA,
+	.max_devs	= CONFIG_SYS_SATA_MAX_DEVICE,
+	.desc		= sata_dev_desc,
+};
-- 
cgit v0.10.2


From a6331fa83cb4a1557df4acfa4214d556f4596904 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:12 -0600
Subject: dm: disk: Use legacy block driver info for block device access

Instead of calling xx_get_dev() functions for each interface type, use the
new legacy block driver which can provide the device through its interface.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index 2613bff..f055c74 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -72,7 +72,6 @@ static struct part_driver *part_driver_lookup_type(int part_type)
 static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
 	const struct block_drvr *drvr = block_drvr;
-	struct blk_desc* (*reloc_get_dev)(int dev);
 	int (*select_hwpart)(int dev_num, int hwpart);
 	char *name;
 	int ret;
@@ -86,16 +85,16 @@ static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 #endif
 	while (drvr->name) {
 		name = drvr->name;
-		reloc_get_dev = drvr->get_dev;
 		select_hwpart = drvr->select_hwpart;
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 		name += gd->reloc_off;
-		reloc_get_dev += gd->reloc_off;
 		if (select_hwpart)
 			select_hwpart += gd->reloc_off;
 #endif
 		if (strncmp(ifname, name, strlen(name)) == 0) {
-			struct blk_desc *dev_desc = reloc_get_dev(dev);
+			struct blk_desc *dev_desc;
+
+			dev_desc = blk_get_devnum_by_typename(name, dev);
 			if (!dev_desc)
 				return NULL;
 			if (hwpart == 0 && !select_hwpart)
-- 
cgit v0.10.2


From 57ebf67bad82da0b3ade1728fb39a64d1c29822f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:13 -0600
Subject: dm: usb: Drop the get_dev() function

This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
index 2ed90de..4740c83 100644
--- a/board/cm5200/fwupdate.c
+++ b/board/cm5200/fwupdate.c
@@ -105,7 +105,7 @@ static int load_rescue_image(ulong addr)
 
 	/* Detect storage device */
 	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
-		stor_dev = usb_stor_get_dev(devno);
+		stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
 		if (stor_dev->type != DEV_TYPE_UNKNOWN)
 			break;
 	}
diff --git a/cmd/usb.c b/cmd/usb.c
index f1a7deb..b83d323 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -723,7 +723,8 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		int devno, ok = 0;
 		if (argc == 2) {
 			for (devno = 0; ; ++devno) {
-				stor_dev = usb_stor_get_dev(devno);
+				stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+								  devno);
 				if (stor_dev == NULL)
 					break;
 				if (stor_dev->type != DEV_TYPE_UNKNOWN) {
@@ -736,7 +737,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			}
 		} else {
 			devno = simple_strtoul(argv[2], NULL, 16);
-			stor_dev = usb_stor_get_dev(devno);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
 			if (stor_dev != NULL &&
 			    stor_dev->type != DEV_TYPE_UNKNOWN) {
 				ok++;
@@ -762,7 +763,8 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			unsigned long n;
 			printf("\nUSB read: device %d block # %ld, count %ld"
 				" ... ", usb_stor_curr_dev, blk, cnt);
-			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+							  usb_stor_curr_dev);
 			n = blk_dread(stor_dev, blk, cnt, (ulong *)addr);
 			printf("%ld blocks read: %s\n", n,
 				(n == cnt) ? "OK" : "ERROR");
@@ -783,7 +785,8 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			unsigned long n;
 			printf("\nUSB write: device %d block # %ld, count %ld"
 				" ... ", usb_stor_curr_dev, blk, cnt);
-			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+							  usb_stor_curr_dev);
 			n = blk_dwrite(stor_dev, blk, cnt, (ulong *)addr);
 			printf("%ld blocks write: %s\n", n,
 				(n == cnt) ? "OK" : "ERROR");
@@ -796,7 +799,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if (argc == 3) {
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 			printf("\nUSB device %d: ", dev);
-			stor_dev = usb_stor_get_dev(dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, dev);
 			if (stor_dev == NULL) {
 				printf("unknown device\n");
 				return 1;
@@ -810,7 +813,8 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 0;
 		} else {
 			printf("\nUSB device %d: ", usb_stor_curr_dev);
-			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+							  usb_stor_curr_dev);
 			dev_print(stor_dev);
 			if (stor_dev->type == DEV_TYPE_UNKNOWN)
 				return 1;
diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c
index c42848e..04fa667 100644
--- a/common/spl/spl_usb.c
+++ b/common/spl/spl_usb.c
@@ -39,7 +39,7 @@ int spl_usb_load_image(void)
 #ifdef CONFIG_USB_STORAGE
 	/* try to recognize storage devices immediately */
 	usb_stor_curr_dev = usb_stor_scan(1);
-	stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+	stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, usb_stor_curr_dev);
 	if (!stor_dev)
 		return -ENODEV;
 #endif
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 80bf3db..f2da3a3 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -136,23 +136,6 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr,
 #endif
 void uhci_show_temp_int_td(void);
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *usb_stor_get_dev(int index)
-{
-#ifdef CONFIG_BLK
-	struct udevice *dev;
-	int ret;
-
-	ret = blk_get_device(IF_TYPE_USB, index, &dev);
-	if (ret)
-		return NULL;
-	return dev_get_uclass_platdata(dev);
-#else
-	return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL;
-#endif
-}
-#endif
-
 static void usb_show_progress(void)
 {
 	debug(".");
diff --git a/disk/part.c b/disk/part.c
index f055c74..1b33928 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -32,7 +32,7 @@ const struct block_drvr block_drvr[] = {
 	{ .name = "scsi", .get_dev = scsi_get_dev, },
 #endif
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
-	{ .name = "usb", .get_dev = usb_stor_get_dev, },
+	{ .name = "usb", },
 #endif
 #if defined(CONFIG_MMC)
 	{
diff --git a/drivers/Makefile b/drivers/Makefile
index 6900097..696b3ac 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
 obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
+obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 
 else
 
diff --git a/include/part.h b/include/part.h
index e3811c6..f206910 100644
--- a/include/part.h
+++ b/include/part.h
@@ -76,7 +76,6 @@ struct blk_desc *blk_get_dev(const char *ifname, int dev);
 struct blk_desc *ide_get_dev(int dev);
 struct blk_desc *sata_get_dev(int dev);
 struct blk_desc *scsi_get_dev(int dev);
-struct blk_desc *usb_stor_get_dev(int dev);
 struct blk_desc *mmc_get_dev(int dev);
 
 /**
@@ -178,7 +177,6 @@ static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 static inline struct blk_desc *ide_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *usb_stor_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mmc_get_dev(int dev) { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
 static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
diff --git a/include/usb.h b/include/usb.h
index 5adad36..02a0ccd 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -228,7 +228,6 @@ int board_usb_cleanup(int index, enum usb_init_type init);
 #ifdef CONFIG_USB_STORAGE
 
 #define USB_MAX_STOR_DEV 7
-struct blk_desc *usb_stor_get_dev(int index);
 int usb_stor_scan(int mode);
 int usb_stor_info(void);
 
-- 
cgit v0.10.2


From 74001a2570ccbc120366e66dd40e8c66e3a6820c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:14 -0600
Subject: dm: ide: Drop the get_dev() function

This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/ide.c b/common/ide.c
index adc1966..5dc90d4 100644
--- a/common/ide.c
+++ b/common/ide.c
@@ -890,13 +890,6 @@ void ide_init(void)
 	WATCHDOG_RESET();
 }
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *ide_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
-}
-#endif
-
 /* We only need to swap data if we are running on a big endian cpu. */
 #if defined(__LITTLE_ENDIAN)
 __weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
diff --git a/disk/part.c b/disk/part.c
index 1b33928..bf224b2 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -23,7 +23,7 @@
 
 const struct block_drvr block_drvr[] = {
 #if defined(CONFIG_CMD_IDE)
-	{ .name = "ide", .get_dev = ide_get_dev, },
+	{ .name = "ide", },
 #endif
 #if defined(CONFIG_CMD_SATA)
 	{.name = "sata", .get_dev = sata_get_dev, },
diff --git a/include/part.h b/include/part.h
index f206910..f09b794 100644
--- a/include/part.h
+++ b/include/part.h
@@ -73,7 +73,6 @@ typedef struct disk_partition {
  *	   error occurred.
  */
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
-struct blk_desc *ide_get_dev(int dev);
 struct blk_desc *sata_get_dev(int dev);
 struct blk_desc *scsi_get_dev(int dev);
 struct blk_desc *mmc_get_dev(int dev);
@@ -174,7 +173,6 @@ extern const struct block_drvr block_drvr[];
 #else
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
-static inline struct blk_desc *ide_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mmc_get_dev(int dev) { return NULL; }
-- 
cgit v0.10.2


From 3c457f4d2e47cc91385abe15d3c825d0ce1a2b6f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:15 -0600
Subject: dm: mmc: Drop the get_dev() function

This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/mmc.c b/cmd/mmc.c
index c5454bf..4f25187 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -432,7 +432,7 @@ static int do_mmc_part(cmd_tbl_t *cmdtp, int flag,
 	if (!mmc)
 		return CMD_RET_FAILURE;
 
-	mmc_dev = mmc_get_dev(curr_device);
+	mmc_dev = blk_get_devnum_by_type(IF_TYPE_MMC, curr_device);
 	if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) {
 		part_print(mmc_dev);
 		return CMD_RET_SUCCESS;
diff --git a/disk/part.c b/disk/part.c
index bf224b2..e70bef5 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -37,7 +37,6 @@ const struct block_drvr block_drvr[] = {
 #if defined(CONFIG_MMC)
 	{
 		.name = "mmc",
-		.get_dev = mmc_get_dev,
 		.select_hwpart = mmc_select_hwpart,
 	},
 #endif
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 024368c..185d7b2 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1582,7 +1582,7 @@ void mmc_destroy(struct mmc *mmc)
 	free(mmc);
 }
 
-static int mmc_get_devp(int dev, struct blk_desc **descp)
+static int mmc_get_dev(int dev, struct blk_desc **descp)
 {
 	struct mmc *mmc = find_mmc_device(dev);
 	int ret;
@@ -1598,18 +1598,6 @@ static int mmc_get_devp(int dev, struct blk_desc **descp)
 	return 0;
 }
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *mmc_get_dev(int dev)
-{
-	struct blk_desc *desc;
-
-	if (mmc_get_devp(dev, &desc))
-		return NULL;
-
-	return desc;
-}
-#endif
-
 /* board-specific MMC power initializations. */
 __weak void board_mmc_power_init(void)
 {
@@ -1987,5 +1975,5 @@ U_BOOT_LEGACY_BLK(mmc) = {
 	.if_typename	= "mmc",
 	.if_type	= IF_TYPE_MMC,
 	.max_devs	= -1,
-	.get_dev	= mmc_get_devp,
+	.get_dev	= mmc_get_dev,
 };
diff --git a/include/part.h b/include/part.h
index f09b794..1535930 100644
--- a/include/part.h
+++ b/include/part.h
@@ -75,7 +75,6 @@ typedef struct disk_partition {
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
 struct blk_desc *sata_get_dev(int dev);
 struct blk_desc *scsi_get_dev(int dev);
-struct blk_desc *mmc_get_dev(int dev);
 
 /**
  * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
@@ -175,7 +174,6 @@ static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
 static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *mmc_get_dev(int dev) { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
 static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-- 
cgit v0.10.2


From edd82ab3547e27b4c1ab1ee7e620f982db9126ad Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:16 -0600
Subject: dm: scsi: Drop the get_dev() function

This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/scsi.c b/common/scsi.c
index a336a10..5b6531f 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -327,13 +327,6 @@ void scsi_init(void)
 }
 #endif
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *scsi_get_dev(int dev)
-{
-	return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
-}
-#endif
-
 /* copy src to dest, skipping leading and trailing blanks
  * and null terminate the string
  */
diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c
index 1719946..9d8cc7c 100644
--- a/common/spl/spl_sata.c
+++ b/common/spl/spl_sata.c
@@ -34,7 +34,7 @@ int spl_sata_load_image(void)
 	} else {
 		/* try to recognize storage devices immediately */
 		scsi_scan(0);
-		stor_dev = scsi_get_dev(0);
+		stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
 		if (!stor_dev)
 			return -ENODEV;
 	}
diff --git a/disk/part.c b/disk/part.c
index e70bef5..67cb6c0 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -29,7 +29,7 @@ const struct block_drvr block_drvr[] = {
 	{.name = "sata", .get_dev = sata_get_dev, },
 #endif
 #if defined(CONFIG_SCSI)
-	{ .name = "scsi", .get_dev = scsi_get_dev, },
+	{ .name = "scsi", },
 #endif
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
 	{ .name = "usb", },
diff --git a/include/part.h b/include/part.h
index 1535930..ecb049f 100644
--- a/include/part.h
+++ b/include/part.h
@@ -74,7 +74,6 @@ typedef struct disk_partition {
  */
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
 struct blk_desc *sata_get_dev(int dev);
-struct blk_desc *scsi_get_dev(int dev);
 
 /**
  * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
@@ -173,7 +172,6 @@ extern const struct block_drvr block_drvr[];
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
 static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
 static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-- 
cgit v0.10.2


From 4e7189d4d8c2ab46c4c580ae300c14d1a9c20b11 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:17 -0600
Subject: dm: sata: Drop the get_dev() function

This function is implemented by the legacy block functions now. Drop it.

We cannot yet make sata_dev_desc[] private to common/sata.c as it is used by
the SATA drivers. This will require the SATA interface to be reworked.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index 67cb6c0..4fc774b 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -26,7 +26,7 @@ const struct block_drvr block_drvr[] = {
 	{ .name = "ide", },
 #endif
 #if defined(CONFIG_CMD_SATA)
-	{.name = "sata", .get_dev = sata_get_dev, },
+	{.name = "sata", },
 #endif
 #if defined(CONFIG_SCSI)
 	{ .name = "scsi", },
diff --git a/include/part.h b/include/part.h
index ecb049f..74bb5d6 100644
--- a/include/part.h
+++ b/include/part.h
@@ -73,7 +73,6 @@ typedef struct disk_partition {
  *	   error occurred.
  */
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
-struct blk_desc *sata_get_dev(int dev);
 
 /**
  * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
@@ -171,7 +170,6 @@ extern const struct block_drvr block_drvr[];
 #else
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
-static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
 static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-- 
cgit v0.10.2


From f6d000edbeaddfe8e5b5e3be9fd3f6c76fdff6d2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:18 -0600
Subject: dm: systemace: Drop the get_dev() function

This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index 4fc774b..28c8706 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -41,7 +41,7 @@ const struct block_drvr block_drvr[] = {
 	},
 #endif
 #if defined(CONFIG_SYSTEMACE)
-	{ .name = "ace", .get_dev = systemace_get_dev, },
+	{ .name = "ace", },
 #endif
 #if defined(CONFIG_SANDBOX)
 	{ .name = "host", .get_dev = host_get_dev, },
diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 0d8e26f..4f14d5f 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -104,8 +104,7 @@ static void release_cf_lock(void)
 	ace_writew((val & 0xffff), 0x18);
 }
 
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *systemace_get_dev(int dev)
+static int systemace_get_dev(int dev, struct blk_desc **descp)
 {
 	/* The first time through this, the systemace_dev object is
 	   not yet initialized. In that case, fill it in. */
@@ -127,14 +126,7 @@ struct blk_desc *systemace_get_dev(int dev)
 		part_init(&systemace_dev);
 
 	}
-
-	return &systemace_dev;
-}
-#endif
-
-static int systemace_get_devp(int dev, struct blk_desc **descp)
-{
-	*descp = systemace_get_dev(dev);
+	*descp = &systemace_dev;
 
 	return 0;
 }
@@ -269,5 +261,5 @@ U_BOOT_LEGACY_BLK(systemace) = {
 	.if_typename	= "ace",
 	.if_type	= IF_TYPE_SYSTEMACE,
 	.max_devs	= 1,
-	.get_dev	= systemace_get_devp,
+	.get_dev	= systemace_get_dev,
 };
diff --git a/include/part.h b/include/part.h
index 74bb5d6..3b59139 100644
--- a/include/part.h
+++ b/include/part.h
@@ -91,7 +91,6 @@ struct blk_desc *blk_get_dev(const char *ifname, int dev);
  * @return 0 if OK, other value for an error
  */
 int mmc_select_hwpart(int dev_num, int hwpart);
-struct blk_desc *systemace_get_dev(int dev);
 struct blk_desc *mg_disk_get_dev(int dev);
 struct blk_desc *host_get_dev(int dev);
 int host_get_dev_err(int dev, struct blk_desc **blk_devp);
@@ -171,7 +170,6 @@ extern const struct block_drvr block_drvr[];
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
-static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
 static inline struct blk_desc *host_get_dev(int dev) { return NULL; }
 
diff --git a/include/systemace.h b/include/systemace.h
index 3b6ec7d..bccb2a2 100644
--- a/include/systemace.h
+++ b/include/systemace.h
@@ -7,11 +7,4 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifdef CONFIG_SYSTEMACE
-
-# include  <part.h>
-
-struct blk_desc *systemace_get_dev(int dev);
-
-#endif	/* CONFIG_SYSTEMACE */
 #endif	/* __SYSTEMACE_H */
-- 
cgit v0.10.2


From ae9ffccdac12b21ad55401d8554b5d835c9c8f22 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:19 -0600
Subject: dm: blk: Drop the systemace.h header

This has nothing of consequence. Remove it and its only inclusion site.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 4f14d5f..79e1263 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -27,7 +27,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <systemace.h>
 #include <part.h>
 #include <asm/io.h>
 
diff --git a/include/systemace.h b/include/systemace.h
deleted file mode 100644
index bccb2a2..0000000
--- a/include/systemace.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __SYSTEMACE_H
-#define __SYSTEMACE_H
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- *    Stephen Williams (steve@picturel.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#endif	/* __SYSTEMACE_H */
-- 
cgit v0.10.2


From f1d86fd3b15c2af53964d948c72c9a0a63511927 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:20 -0600
Subject: dm: sandbox: Drop the host_get_dev() function

This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index 28c8706..e635d90 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -44,7 +44,7 @@ const struct block_drvr block_drvr[] = {
 	{ .name = "ace", },
 #endif
 #if defined(CONFIG_SANDBOX)
-	{ .name = "host", .get_dev = host_get_dev, },
+	{ .name = "host", },
 #endif
 	{ },
 };
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 2b6a893..ac28f83 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -217,16 +217,6 @@ int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
 	return 0;
 }
 
-struct blk_desc *host_get_dev(int dev)
-{
-	struct blk_desc *blk_dev;
-
-	if (host_get_dev_err(dev, &blk_dev))
-		return NULL;
-
-	return blk_dev;
-}
-
 #ifdef CONFIG_BLK
 static const struct blk_ops sandbox_host_blk_ops = {
 	.read	= host_block_read,
diff --git a/include/part.h b/include/part.h
index 3b59139..47f5baf 100644
--- a/include/part.h
+++ b/include/part.h
@@ -92,7 +92,6 @@ struct blk_desc *blk_get_dev(const char *ifname, int dev);
  */
 int mmc_select_hwpart(int dev_num, int hwpart);
 struct blk_desc *mg_disk_get_dev(int dev);
-struct blk_desc *host_get_dev(int dev);
 int host_get_dev_err(int dev, struct blk_desc **blk_devp);
 
 /* disk/part.c */
@@ -171,7 +170,6 @@ static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
 static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *host_get_dev(int dev) { return NULL; }
 
 static inline int part_get_info(struct blk_desc *dev_desc, int part,
 				disk_partition_t *info) { return -1; }
-- 
cgit v0.10.2


From 38bd29beaaf51f92d986ef63e5539f0bd0d371d8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:21 -0600
Subject: dm: part: Drop the get_dev() method

This is now handled by the legacy block driver. The get_dev() method is
no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/part.h b/include/part.h
index 47f5baf..bc9dc64 100644
--- a/include/part.h
+++ b/include/part.h
@@ -12,7 +12,6 @@
 
 struct block_drvr {
 	char *name;
-	struct blk_desc* (*get_dev)(int dev);
 	int (*select_hwpart)(int dev_num, int hwpart);
 };
 
-- 
cgit v0.10.2


From 145df842b443a2f2323a11f6e61223e3767dc55c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:22 -0600
Subject: dm: ide: Add support for driver-model block devices

Add driver-model block-device support to the IDE implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/ide.c b/common/ide.c
index 5dc90d4..ac5b91c 100644
--- a/common/ide.c
+++ b/common/ide.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <ata.h>
+#include <dm.h>
 #include <ide.h>
 #include <watchdog.h>
 #include <asm/io.h>
@@ -873,8 +874,10 @@ void ide_init(void)
 		ide_dev_desc[i].log2blksz =
 			LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
 		ide_dev_desc[i].lba = 0;
+#ifndef CONFIG_BLK
 		ide_dev_desc[i].block_read = ide_read;
 		ide_dev_desc[i].block_write = ide_write;
+#endif
 		if (!ide_bus_ok[IDE_BUS(i)])
 			continue;
 		ide_led(led, 1);	/* LED on       */
@@ -975,9 +978,17 @@ __weak void ide_input_data(int dev, ulong *sect_buf, int words)
 
 #endif /* CONFIG_IDE_SWAP_IO */
 
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer)
+#else
 ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	       void *buffer)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int device = block_dev->devnum;
 	ulong n = 0;
 	unsigned char c;
@@ -1097,9 +1108,17 @@ IDE_READ_E:
 	return n;
 }
 
+#ifdef CONFIG_BLK
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer)
+#else
 ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 		const void *buffer)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int device = block_dev->devnum;
 	ulong n = 0;
 	unsigned char c;
@@ -1191,9 +1210,22 @@ int ide_device_present(int dev)
 }
 #endif
 
+#ifdef CONFIG_BLK
+static const struct blk_ops ide_blk_ops = {
+	.read	= ide_read,
+	.write	= ide_write,
+};
+
+U_BOOT_DRIVER(ide_blk) = {
+	.name		= "ide_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &ide_blk_ops,
+};
+#else
 U_BOOT_LEGACY_BLK(ide) = {
 	.if_typename	= "ide",
 	.if_type	= IF_TYPE_IDE,
 	.max_devs	= CONFIG_SYS_IDE_MAXDEVICE,
 	.desc		= ide_dev_desc,
 };
+#endif
diff --git a/include/ide.h b/include/ide.h
index a4e65cf..9b0a4a9 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -34,10 +34,18 @@ void ide_led(uchar led, uchar status);
 
 void ide_init(void);
 struct blk_desc;
+struct udevice;
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer);
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer);
+#else
 ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 	       void *buffer);
 ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
 		const void *buffer);
+#endif
 
 #ifdef CONFIG_IDE_PREINIT
 int ide_preinit(void);
-- 
cgit v0.10.2


From 74c6dc14447e8386dd0799611d316eae5aad1e10 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:23 -0600
Subject: dm: sandbox: Enable IDE

Enable building the IDE code for sandbox. This is for build coverage only.
It does not currently work.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 9790a14..a2926fd 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -192,4 +192,14 @@
 #define CONFIG_CMD_LZMADEC
 #define CONFIG_CMD_DATE
 
+#define CONFIG_CMD_IDE
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+#define CONFIG_SYS_ATA_BASE_ADDR	0x100
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	1
+#define CONFIG_SYS_ATA_ALT_OFFSET	2
+#define CONFIG_SYS_ATA_STRIDE		4
+
 #endif
-- 
cgit v0.10.2


From 535556b2aa64966970ff75a8307549506a1a168a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:24 -0600
Subject: dm: scsi: Add support for driver-model block devices

Add driver-model block-device support to the SCSI implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/scsi.c b/common/scsi.c
index 5b6531f..8ac28dd 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <inttypes.h>
 #include <pci.h>
 #include <scsi.h>
@@ -149,9 +150,17 @@ void scsi_setup_inquiry(ccb *pccb)
 	pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
 }
 
+#ifdef CONFIG_BLK
+static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		       void *buffer)
+#else
 static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 		       lbaint_t blkcnt, void *buffer)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int device = block_dev->devnum;
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
@@ -216,9 +225,17 @@ static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
 /* Almost the maximum amount of the scsi_ext command.. */
 #define SCSI_MAX_WRITE_BLK 0xFFFF
 
+#ifdef CONFIG_BLK
+static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+			const void *buffer)
+#else
 static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
 			lbaint_t blkcnt, const void *buffer)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int device = block_dev->devnum;
 	lbaint_t start, blks;
 	uintptr_t buf_addr;
@@ -469,8 +486,10 @@ void scsi_scan(int mode)
 		scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
 		scsi_dev_desc[i].devnum = i;
 		scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+#ifndef CONFIG_BLK
 		scsi_dev_desc[i].block_read = scsi_read;
 		scsi_dev_desc[i].block_write = scsi_write;
+#endif
 	}
 	scsi_max_devs = 0;
 	for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
@@ -552,9 +571,22 @@ removable:
 #endif
 }
 
+#ifdef CONFIG_BLK
+static const struct blk_ops scsi_blk_ops = {
+	.read	= scsi_read,
+	.write	= scsi_write,
+};
+
+U_BOOT_DRIVER(scsi_blk) = {
+	.name		= "scsi_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &scsi_blk_ops,
+};
+#else
 U_BOOT_LEGACY_BLK(scsi) = {
 	.if_typename	= "sata",
 	.if_type	= IF_TYPE_SCSI,
 	.max_devs	= CONFIG_SYS_SCSI_MAX_DEVICE,
 	.desc		= scsi_dev_desc,
 };
+#endif
-- 
cgit v0.10.2


From e8c0a2509c6ec62a5c58a39c338cc1127bc83e1a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:25 -0600
Subject: dm: sandbox: Enable SCSI

Enable building the SCSI code for sandbox. This increases build coverage
for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index a2926fd..affc9cc 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -202,4 +202,10 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET	2
 #define CONFIG_SYS_ATA_STRIDE		4
 
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_DEVICE	2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	8
+#define CONFIG_SYS_SCSI_MAX_LUN		4
+
 #endif
-- 
cgit v0.10.2


From f5a14af9c42be077404dbbeaebbb629f7ddcbed6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:26 -0600
Subject: dm: sata: Add support for driver-model block devices

Add driver-model block-device support to the SATA implementation. This is
just a dummy implementation for now, since the SATA low-level API uses
numbered devices and that doesn't fit with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/sata.c b/common/sata.c
index 1d52fcb..88f08c9 100644
--- a/common/sata.c
+++ b/common/sata.c
@@ -11,6 +11,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <sata.h>
 
 struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
@@ -22,6 +23,19 @@ struct blk_desc *sata_get_dev(int dev)
 }
 #endif
 
+#ifdef CONFIG_BLK
+static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
+				lbaint_t blkcnt, void *dst)
+{
+	return -ENOSYS;
+}
+
+static unsigned long sata_bwrite(struct udevice *dev, lbaint_t start,
+				 lbaint_t blkcnt, const void *buffer)
+{
+	return -ENOSYS;
+}
+#else
 static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
 				lbaint_t blkcnt, void *dst)
 {
@@ -33,6 +47,7 @@ static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
 {
 	return sata_write(block_dev->devnum, start, blkcnt, buffer);
 }
+#endif
 
 int __sata_initialize(void)
 {
@@ -48,9 +63,10 @@ int __sata_initialize(void)
 		sata_dev_desc[i].lba = 0;
 		sata_dev_desc[i].blksz = 512;
 		sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
+#ifndef CONFIG_BLK
 		sata_dev_desc[i].block_read = sata_bread;
 		sata_dev_desc[i].block_write = sata_bwrite;
-
+#endif
 		rc = init_sata(i);
 		if (!rc) {
 			rc = scan_sata(i);
@@ -78,9 +94,22 @@ __weak int __sata_stop(void)
 }
 int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
 
+#ifdef CONFIG_BLK
+static const struct blk_ops sata_blk_ops = {
+	.read	= sata_bread,
+	.write	= sata_bwrite,
+};
+
+U_BOOT_DRIVER(sata_blk) = {
+	.name		= "sata_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &sata_blk_ops,
+};
+#else
 U_BOOT_LEGACY_BLK(sata) = {
 	.if_typename	= "sata",
 	.if_type	= IF_TYPE_SATA,
 	.max_devs	= CONFIG_SYS_SATA_MAX_DEVICE,
 	.desc		= sata_dev_desc,
 };
+#endif
-- 
cgit v0.10.2


From 199a1201ab901413a80c64a9eee72f82977ba8d3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:27 -0600
Subject: dm: sandbox: Enable SATA

Enable building the SATA code for sandbox. This increases build coverage
for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index affc9cc..7127611 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -208,4 +208,7 @@
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	8
 #define CONFIG_SYS_SCSI_MAX_LUN		4
 
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+
 #endif
-- 
cgit v0.10.2


From 52138fd4072b64448855eac4c2c9815b46f5b43c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:28 -0600
Subject: dm: blk: Allow blk_create_device() to allocate the device number

Allow a devnum parameter of -1 to indicate that the device number should be
alocated automatically. The next highest available device number for that
interface type is used.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 3687b9a..c947d95 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -411,6 +411,26 @@ int blk_prepare_device(struct udevice *dev)
 	return 0;
 }
 
+int blk_find_max_devnum(enum if_type if_type)
+{
+	struct udevice *dev;
+	int max_devnum = -ENODEV;
+	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(UCLASS_BLK, &uc);
+	if (ret)
+		return ret;
+	uclass_foreach_dev(dev, uc) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+		if (desc->if_type == if_type && desc->devnum > max_devnum)
+			max_devnum = desc->devnum;
+	}
+
+	return max_devnum;
+}
+
 int blk_create_device(struct udevice *parent, const char *drv_name,
 		      const char *name, int if_type, int devnum, int blksz,
 		      lbaint_t size, struct udevice **devp)
@@ -428,6 +448,15 @@ int blk_create_device(struct udevice *parent, const char *drv_name,
 	desc->lba = size / blksz;
 	desc->part_type = PART_TYPE_UNKNOWN;
 	desc->bdev = dev;
+	if (devnum == -1) {
+		ret = blk_find_max_devnum(if_type);
+		if (ret == -ENODEV)
+			devnum = 0;
+		else if (ret < 0)
+			return ret;
+		else
+			devnum = ret + 1;
+	}
 	desc->devnum = devnum;
 	*devp = dev;
 
diff --git a/include/blk.h b/include/blk.h
index 2caac9c..547c3b4 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -270,7 +270,8 @@ int blk_next_device(struct udevice **devp);
  * @drv_name:	Driver name to use for the block device
  * @name:	Name for the device
  * @if_type:	Interface type (enum if_type_t)
- * @devnum:	Device number, specific to the interface type
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
  * @blksz:	Block size of the device in bytes (typically 512)
  * @size:	Total size of the device in bytes
  * @devp:	the new device (which has not been probed)
@@ -299,6 +300,18 @@ int blk_prepare_device(struct udevice *dev);
  */
 int blk_unbind_all(int if_type);
 
+/**
+ * blk_find_max_devnum() - find the maximum device number for an interface type
+ *
+ * Finds the last allocated device number for an interface type @if_type. The
+ * next number is safe to use for a newly allocated device.
+ *
+ * @if_type:	Interface type to scan
+ * @return maximum device number found, or -ENODEV if none, or other -ve on
+ * error
+ */
+int blk_find_max_devnum(enum if_type if_type);
+
 #else
 #include <errno.h>
 /*
-- 
cgit v0.10.2


From 9107c973d32c72a6f7ac909fc4a6884a42e4e607 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:29 -0600
Subject: dm: blk: Add a easier way to create a named block device

Add a function that automatically builds the device name given the parent
and a supplied string. Most callers will want to do this, so putting this
functionality in one place makes more sense.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/usb_storage.c b/common/usb_storage.c
index f2da3a3..7e6e52d 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -200,7 +200,6 @@ static int usb_stor_probe_device(struct usb_device *udev)
 
 #ifdef CONFIG_BLK
 	struct us_data *data;
-	char dev_name[30], *str;
 	int ret;
 #else
 	int start;
@@ -223,14 +222,12 @@ static int usb_stor_probe_device(struct usb_device *udev)
 	for (lun = 0; lun <= max_lun; lun++) {
 		struct blk_desc *blkdev;
 		struct udevice *dev;
+		char str[10];
 
-		snprintf(dev_name, sizeof(dev_name), "%s.lun%d",
-			 udev->dev->name, lun);
-		str = strdup(dev_name);
-		if (!str)
-			return -ENOMEM;
-		ret = blk_create_device(udev->dev, "usb_storage_blk", str,
-				IF_TYPE_USB, usb_max_devs, 512, 0, &dev);
+		snprintf(str, sizeof(str), "lun%d", lun);
+		ret = blk_create_devicef(udev->dev, "usb_storage_blk", str,
+					 IF_TYPE_USB, usb_max_devs, 512, 0,
+					 &dev);
 		if (ret) {
 			debug("Cannot bind driver\n");
 			return ret;
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index c947d95..6ecbff0 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -463,6 +463,21 @@ int blk_create_device(struct udevice *parent, const char *drv_name,
 	return 0;
 }
 
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+		       const char *name, int if_type, int devnum, int blksz,
+		       lbaint_t size, struct udevice **devp)
+{
+	char dev_name[30], *str;
+
+	snprintf(dev_name, sizeof(dev_name), "%s.%s", parent->name, name);
+	str = strdup(dev_name);
+	if (!str)
+		return -ENOMEM;
+
+	return blk_create_device(parent, drv_name, str, if_type, devnum,
+				 blksz, size, devp);
+}
+
 int blk_unbind_all(int if_type)
 {
 	struct uclass *uc;
diff --git a/include/blk.h b/include/blk.h
index 547c3b4..82b2c1a 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -281,6 +281,23 @@ int blk_create_device(struct udevice *parent, const char *drv_name,
 		      lbaint_t size, struct udevice **devp);
 
 /**
+ * blk_create_devicef() - Create a new named block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device (parent name is prepended)
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @size:	Total size of the device in bytes
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+		       const char *name, int if_type, int devnum, int blksz,
+		       lbaint_t size, struct udevice **devp);
+
+/**
  * blk_prepare_device() - Prepare a block device for use
  *
  * This reads partition information from the device if supported.
-- 
cgit v0.10.2


From a0ff24c4672654fa6d13498e3a3367935bdc7334 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:30 -0600
Subject: dm: systemace: Reorder function to avoid forward declarataions

Move the systemace_get_dev() function below systemace_read() so that we can
avoid a forward declaration.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 79e1263..eeba7f0 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -68,10 +68,6 @@ static u16 ace_readw(unsigned off)
 	return in16(base + off);
 }
 
-static unsigned long systemace_read(struct blk_desc *block_dev,
-				    unsigned long start, lbaint_t blkcnt,
-				    void *buffer);
-
 static struct blk_desc systemace_dev = { 0 };
 
 static int get_cf_lock(void)
@@ -103,33 +99,6 @@ static void release_cf_lock(void)
 	ace_writew((val & 0xffff), 0x18);
 }
 
-static int systemace_get_dev(int dev, struct blk_desc **descp)
-{
-	/* The first time through this, the systemace_dev object is
-	   not yet initialized. In that case, fill it in. */
-	if (systemace_dev.blksz == 0) {
-		systemace_dev.if_type = IF_TYPE_UNKNOWN;
-		systemace_dev.devnum = 0;
-		systemace_dev.part_type = PART_TYPE_UNKNOWN;
-		systemace_dev.type = DEV_TYPE_HARDDISK;
-		systemace_dev.blksz = 512;
-		systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
-		systemace_dev.removable = 1;
-		systemace_dev.block_read = systemace_read;
-
-		/*
-		 * Ensure the correct bus mode (8/16 bits) gets enabled
-		 */
-		ace_writew(width == 8 ? 0 : 0x0001, 0);
-
-		part_init(&systemace_dev);
-
-	}
-	*descp = &systemace_dev;
-
-	return 0;
-}
-
 /*
  * This function is called (by dereferencing the block_read pointer in
  * the dev_desc) to read blocks of data. The return value is the
@@ -256,6 +225,32 @@ static unsigned long systemace_read(struct blk_desc *block_dev,
 	return blkcnt;
 }
 
+static int systemace_get_dev(int dev, struct blk_desc **descp)
+{
+	/* The first time through this, the systemace_dev object is
+	   not yet initialized. In that case, fill it in. */
+	if (systemace_dev.blksz == 0) {
+		systemace_dev.if_type = IF_TYPE_UNKNOWN;
+		systemace_dev.devnum = 0;
+		systemace_dev.part_type = PART_TYPE_UNKNOWN;
+		systemace_dev.type = DEV_TYPE_HARDDISK;
+		systemace_dev.blksz = 512;
+		systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
+		systemace_dev.removable = 1;
+		systemace_dev.block_read = systemace_read;
+
+		/*
+		 * Ensure the correct bus mode (8/16 bits) gets enabled
+		 */
+		ace_writew(width == 8 ? 0 : 0x0001, 0);
+
+		part_init(&systemace_dev);
+	}
+	*descp = &systemace_dev;
+
+	return 0;
+}
+
 U_BOOT_LEGACY_BLK(systemace) = {
 	.if_typename	= "ace",
 	.if_type	= IF_TYPE_SYSTEMACE,
-- 
cgit v0.10.2


From 4560ee470f021cfc3f6be37890c1391731c26f38 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:31 -0600
Subject: dm: systemace: Add driver-mode block-device support

Add support for CONFIG_BLK to the systemace driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index eeba7f0..9392bea 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -27,6 +27,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm.h>
 #include <part.h>
 #include <asm/io.h>
 
@@ -68,7 +69,9 @@ static u16 ace_readw(unsigned off)
 	return in16(base + off);
 }
 
+#ifndef CONFIG_BLK
 static struct blk_desc systemace_dev = { 0 };
+#endif
 
 static int get_cf_lock(void)
 {
@@ -104,9 +107,14 @@ static void release_cf_lock(void)
  * the dev_desc) to read blocks of data. The return value is the
  * number of blocks read. A zero return indicates an error.
  */
+#ifdef CONFIG_BLK
+static unsigned long systemace_read(struct udevice *dev, unsigned long start,
+				    lbaint_t blkcnt, void *buffer)
+#else
 static unsigned long systemace_read(struct blk_desc *block_dev,
 				    unsigned long start, lbaint_t blkcnt,
 				    void *buffer)
+#endif
 {
 	int retry;
 	unsigned blk_countdown;
@@ -225,6 +233,41 @@ static unsigned long systemace_read(struct blk_desc *block_dev,
 	return blkcnt;
 }
 
+#ifdef CONFIG_BLK
+static int systemace_bind(struct udevice *dev)
+{
+	struct blk_desc *bdesc;
+	struct udevice *bdev;
+	int ret;
+
+	ret = blk_create_devicef(dev, "systemace_blk", "blk", IF_TYPE_SYSTEMACE,
+				 -1, 512, 0, &bdev);
+	if (ret) {
+		debug("Cannot create block device\n");
+		return ret;
+	}
+	bdesc = dev_get_uclass_platdata(bdev);
+	bdesc->removable = 1;
+	bdesc->part_type = PART_TYPE_UNKNOWN;
+	bdesc->log2blksz = LOG2(bdesc->blksz);
+
+	/* Ensure the correct bus mode (8/16 bits) gets enabled */
+	ace_writew(width == 8 ? 0 : 0x0001, 0);
+
+	return 0;
+}
+
+static const struct blk_ops systemace_blk_ops = {
+	.read	= systemace_read,
+};
+
+U_BOOT_DRIVER(systemace_blk) = {
+	.name		= "systemace_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &systemace_blk_ops,
+	.bind		= systemace_bind,
+};
+#else
 static int systemace_get_dev(int dev, struct blk_desc **descp)
 {
 	/* The first time through this, the systemace_dev object is
@@ -257,3 +300,4 @@ U_BOOT_LEGACY_BLK(systemace) = {
 	.max_devs	= 1,
 	.get_dev	= systemace_get_dev,
 };
+#endif
-- 
cgit v0.10.2


From cd995a8aa0127128132bb50f485c53bfb9593312 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 11:36:32 -0600
Subject: dm: sandbox: Enable systemace

Enable building the systemace code for sandbox. This increases build
coverage for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 7127611..c51d4cd 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -211,4 +211,8 @@
 #define CONFIG_CMD_SATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 
+#define CONFIG_SYSTEMACE
+#define CONFIG_SYS_SYSTEMACE_WIDTH	16
+#define CONFIG_SYS_SYSTEMACE_BASE	0
+
 #endif
-- 
cgit v0.10.2


From 72a85c0d2dfe965c831670f06d3803aaad7bb5b1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:22 -0600
Subject: dm: blk: Fix allocation of block-device numbering

Due to code ordering the block devices are not numbered sequentially. Fix
this.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 6ecbff0..f67f9b9 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -439,15 +439,6 @@ int blk_create_device(struct udevice *parent, const char *drv_name,
 	struct udevice *dev;
 	int ret;
 
-	ret = device_bind_driver(parent, drv_name, name, &dev);
-	if (ret)
-		return ret;
-	desc = dev_get_uclass_platdata(dev);
-	desc->if_type = if_type;
-	desc->blksz = blksz;
-	desc->lba = size / blksz;
-	desc->part_type = PART_TYPE_UNKNOWN;
-	desc->bdev = dev;
 	if (devnum == -1) {
 		ret = blk_find_max_devnum(if_type);
 		if (ret == -ENODEV)
@@ -457,6 +448,15 @@ int blk_create_device(struct udevice *parent, const char *drv_name,
 		else
 			devnum = ret + 1;
 	}
+	ret = device_bind_driver(parent, drv_name, name, &dev);
+	if (ret)
+		return ret;
+	desc = dev_get_uclass_platdata(dev);
+	desc->if_type = if_type;
+	desc->blksz = blksz;
+	desc->lba = size / blksz;
+	desc->part_type = PART_TYPE_UNKNOWN;
+	desc->bdev = dev;
 	desc->devnum = devnum;
 	*devp = dev;
 
-- 
cgit v0.10.2


From a2040facd23b88082b9b40f0aa9bcfd495eab88e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:23 -0600
Subject: dm: core: Allow device names to be freed automatically

Some devices have a name that is stored in allocated memory. At present
there is no mechanism to free this memory when the device is unbound.

Add a device flag to track whether a name is allocated and a function to
add the flag. Free the memory when the device is unbound.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index e1714b2..0e56b23 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -112,6 +112,8 @@ int device_unbind(struct udevice *dev)
 
 	devres_release_all(dev);
 
+	if (dev->flags & DM_NAME_ALLOCED)
+		free((char *)dev->name);
 	free(dev);
 
 	return 0;
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 2b12ce7..5c2dc70 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -706,12 +706,18 @@ bool device_is_last_sibling(struct udevice *dev)
 	return list_is_last(&dev->sibling_node, &parent->child_head);
 }
 
+void device_set_name_alloced(struct udevice *dev)
+{
+	dev->flags |= DM_NAME_ALLOCED;
+}
+
 int device_set_name(struct udevice *dev, const char *name)
 {
 	name = strdup(name);
 	if (!name)
 		return -ENOMEM;
 	dev->name = name;
+	device_set_name_alloced(dev);
 
 	return 0;
 }
diff --git a/include/dm/device.h b/include/dm/device.h
index 8970fc0..e9a8ec7 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -41,6 +41,9 @@ struct driver_info;
 /* Device is bound */
 #define DM_FLAG_BOUND			(1 << 6)
 
+/* Device name is allocated and should be freed on unbind() */
+#define DM_NAME_ALLOCED			(1 << 7)
+
 /**
  * struct udevice - An instance of a driver
  *
@@ -523,6 +526,9 @@ bool device_is_last_sibling(struct udevice *dev);
  * this is unnecessary but for probed devices which don't get a useful name
  * this function can be helpful.
  *
+ * The name is allocated and will be freed automatically when the device is
+ * unbound.
+ *
  * @dev:	Device to update
  * @name:	New name (this string is allocated new memory and attached to
  *		the device)
@@ -532,6 +538,16 @@ bool device_is_last_sibling(struct udevice *dev);
 int device_set_name(struct udevice *dev, const char *name);
 
 /**
+ * device_set_name_alloced() - note that a device name is allocated
+ *
+ * This sets the DM_NAME_ALLOCED flag for the device, so that when it is
+ * unbound the name will be freed. This avoids memory leaks.
+ *
+ * @dev:	Device to update
+ */
+void device_set_name_alloced(struct udevice *dev);
+
+/**
  * device_is_on_pci_bus - Test if a device is on a PCI bus
  *
  * @dev:	device to test
-- 
cgit v0.10.2


From d0773524e18d2439390c88611b49f23ca46a82be Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:24 -0600
Subject: dm: blk: Free the block device name when unbound

Mark the device name as allocated so that it will be freed correctly when the
device is unbound.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index f67f9b9..a37239e 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -468,14 +468,22 @@ int blk_create_devicef(struct udevice *parent, const char *drv_name,
 		       lbaint_t size, struct udevice **devp)
 {
 	char dev_name[30], *str;
+	int ret;
 
 	snprintf(dev_name, sizeof(dev_name), "%s.%s", parent->name, name);
 	str = strdup(dev_name);
 	if (!str)
 		return -ENOMEM;
 
-	return blk_create_device(parent, drv_name, str, if_type, devnum,
-				 blksz, size, devp);
+	ret = blk_create_device(parent, drv_name, str, if_type, devnum,
+				blksz, size, devp);
+	if (ret) {
+		free(str);
+		return ret;
+	}
+	device_set_name_alloced(*devp);
+
+	return ret;
 }
 
 int blk_unbind_all(int if_type)
-- 
cgit v0.10.2


From ff3882ac23fcfda81284f372924063036bea507b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:25 -0600
Subject: dm: mmc: Move mmc_switch_part() above its callers

This function is defined after it is used. In preparation for making it
static, move it up a little. Also drop the printf() which should not appear
in a driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 185d7b2..2211ac6 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -582,30 +582,6 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
 	return 0;
 }
 
-int mmc_select_hwpart(int dev_num, int hwpart)
-{
-	struct mmc *mmc = find_mmc_device(dev_num);
-	int ret;
-
-	if (!mmc)
-		return -ENODEV;
-
-	if (mmc->block_dev.hwpart == hwpart)
-		return 0;
-
-	if (mmc->part_config == MMCPART_NOAVAILABLE) {
-		printf("Card doesn't support part_switch\n");
-		return -EMEDIUMTYPE;
-	}
-
-	ret = mmc_switch_part(dev_num, hwpart);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-
 int mmc_switch_part(int dev_num, unsigned int part_num)
 {
 	struct mmc *mmc = find_mmc_device(dev_num);
@@ -630,6 +606,27 @@ int mmc_switch_part(int dev_num, unsigned int part_num)
 	return ret;
 }
 
+int mmc_select_hwpart(int dev_num, int hwpart)
+{
+	struct mmc *mmc = find_mmc_device(dev_num);
+	int ret;
+
+	if (!mmc)
+		return -ENODEV;
+
+	if (mmc->block_dev.hwpart == hwpart)
+		return 0;
+
+	if (mmc->part_config == MMCPART_NOAVAILABLE)
+		return -EMEDIUMTYPE;
+
+	ret = mmc_switch_part(dev_num, hwpart);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 int mmc_hwpart_config(struct mmc *mmc,
 		      const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode)
-- 
cgit v0.10.2


From e17d1143c1a3f6f9bb1b21acb50e5e6a79855023 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:26 -0600
Subject: dm: mmc: Implement the select_hwpart() method

Implement this method so that hardware partitions will work correctly with
MMC.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2211ac6..e270f5f 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -606,6 +606,27 @@ int mmc_switch_part(int dev_num, unsigned int part_num)
 	return ret;
 }
 
+static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
+{
+	struct mmc *mmc = find_mmc_device(desc->devnum);
+	int ret;
+
+	if (!mmc)
+		return -ENODEV;
+
+	if (mmc->block_dev.hwpart == hwpart)
+		return 0;
+
+	if (mmc->part_config == MMCPART_NOAVAILABLE)
+		return -EMEDIUMTYPE;
+
+	ret = mmc_switch_part(desc->devnum, hwpart);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 int mmc_select_hwpart(int dev_num, int hwpart)
 {
 	struct mmc *mmc = find_mmc_device(dev_num);
@@ -1973,4 +1994,5 @@ U_BOOT_LEGACY_BLK(mmc) = {
 	.if_type	= IF_TYPE_MMC,
 	.max_devs	= -1,
 	.get_dev	= mmc_get_dev,
+	.select_hwpart	= mmc_select_hwpartp,
 };
-- 
cgit v0.10.2


From cb5ec33d9096f1f57c5ccc97d44ca0fb771729f5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:27 -0600
Subject: dm: mmc: Add a function to obtain the block device

The MMC block device is contained within struct mmc. But with driver model
this will not be the case. Add a function to obtain the block device. We
can later implement this for CONFIG_BLK.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index e270f5f..49996a8 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -24,6 +24,11 @@
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
 
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+	return &mmc->block_dev;
+}
+
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
diff --git a/include/mmc.h b/include/mmc.h
index cdb56e7..36449c3 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -498,4 +498,12 @@ int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 #endif
 
+/**
+ * mmc_get_blk_desc() - Get the block descriptor for an MMC device
+ *
+ * @mmc:	MMC device
+ * @return block device if found, else NULL
+ */
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
+
 #endif /* _MMC_H_ */
-- 
cgit v0.10.2


From 0776167ec5541a2b4fa099dfea5a1aad2d4b7c72 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:28 -0600
Subject: dm: mmc: spl: Use the legacy block interface in SPL

Bring this in for SPL so that we can use generic code for loading from
block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/Makefile b/drivers/Makefile
index 696b3ac..99dd07f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
 obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
+obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
 
 else
 
-- 
cgit v0.10.2


From 69f45cd53b8ad8bc3afef2cf2410baf58fe75a6f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:29 -0600
Subject: dm: mmc: Use the new select_hwpart() API

Avoid calling directly into the MMC code - use the new API call instead.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/mmc.c b/cmd/mmc.c
index 4f25187..8695c19 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -314,12 +314,14 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag,
 	}
 	/* Switch to the RPMB partition */
 	original_part = mmc->block_dev.hwpart;
-	if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
+	if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, MMC_PART_RPMB) !=
+	    0)
 		return CMD_RET_FAILURE;
 	ret = cp->cmd(cmdtp, flag, argc, argv);
 
 	/* Return to original partition */
-	if (mmc_select_hwpart(curr_device, original_part) != 0)
+	if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, original_part) !=
+	    0)
 		return CMD_RET_FAILURE;
 	return ret;
 }
@@ -467,7 +469,7 @@ static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag,
 	if (!mmc)
 		return CMD_RET_FAILURE;
 
-	ret = mmc_select_hwpart(dev, part);
+	ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
 	printf("switch to partitions #%d, %s\n",
 	       part, (!ret) ? "OK" : "ERROR");
 	if (ret)
diff --git a/common/env_mmc.c b/common/env_mmc.c
index bdb452e..c7fef18 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -86,8 +86,8 @@ static int mmc_set_env_part(struct mmc *mmc)
 	dev = 0;
 #endif
 
-	env_mmc_orig_hwpart = mmc->block_dev.hwpart;
-	ret = mmc_select_hwpart(dev, part);
+	env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
+	ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
 	if (ret)
 		puts("MMC partition switch failed\n");
 
@@ -119,7 +119,7 @@ static void fini_mmc_for_env(struct mmc *mmc)
 #ifdef CONFIG_SPL_BUILD
 	dev = 0;
 #endif
-	mmc_select_hwpart(dev, env_mmc_orig_hwpart);
+	blk_select_hwpart_devnum(IF_TYPE_MMC, dev, env_mmc_orig_hwpart);
 #endif
 }
 
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 8d588d1..cf527da 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -296,7 +296,7 @@ int spl_mmc_load_image(u32 boot_device)
 			if (part == 7)
 				part = 0;
 
-			err = mmc_switch_part(0, part);
+			err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
 			if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 				puts("spl: mmc partition switch failed\n");
diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index faece88..78724e4 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -50,8 +50,9 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
 
 	if (dfu->data.mmc.hw_partition >= 0) {
 		part_num_bkp = mmc->block_dev.hwpart;
-		ret = mmc_select_hwpart(dfu->data.mmc.dev_num,
-					dfu->data.mmc.hw_partition);
+		ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
+					       dfu->data.mmc.dev_num,
+					       dfu->data.mmc.hw_partition);
 		if (ret)
 			return ret;
 	}
@@ -75,12 +76,16 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
 	if (n != blk_count) {
 		error("MMC operation failed");
 		if (dfu->data.mmc.hw_partition >= 0)
-			mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
+			blk_select_hwpart_devnum(IF_TYPE_MMC,
+						 dfu->data.mmc.dev_num,
+						 part_num_bkp);
 		return -EIO;
 	}
 
 	if (dfu->data.mmc.hw_partition >= 0) {
-		ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
+		ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
+					       dfu->data.mmc.dev_num,
+					       part_num_bkp);
 		if (ret)
 			return ret;
 	}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 49996a8..7322f334 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -257,7 +257,7 @@ static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
 	if (!mmc)
 		return 0;
 
-	err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+	err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
 	if (err < 0)
 		return 0;
 
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 7b186f8..f4d42aa 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -78,7 +78,8 @@ unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
 	if (!mmc)
 		return -1;
 
-	err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,
+				       block_dev->hwpart);
 	if (err < 0)
 		return -1;
 
@@ -182,7 +183,7 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 	if (!mmc)
 		return 0;
 
-	err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, block_dev->hwpart);
 	if (err < 0)
 		return 0;
 
diff --git a/include/mmc.h b/include/mmc.h
index 36449c3..f01674d 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -415,7 +415,6 @@ struct mmc *find_mmc_device(int dev_num);
 int mmc_set_dev(int dev_num);
 void print_mmc_devices(char separator);
 int get_mmc_num(void);
-int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode);
 int mmc_getcd(struct mmc *mmc);
-- 
cgit v0.10.2


From cd0fb55b640b2991c1d29122d252a360037ed903 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:30 -0600
Subject: dm: blk: Add functions to select a hardware partition

The block device uclass does not currently support selecting a particular
hardware partition but this is needed for MMC. Add it so that the blk API
can support MMC properly.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index a37239e..6ba1026 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -165,6 +165,18 @@ static int get_desc(enum if_type if_type, int devnum, struct blk_desc **descp)
 	return found_more ? -ENOENT : -ENODEV;
 }
 
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = blk_get_device(if_type, devnum, &dev);
+	if (ret)
+		return ret;
+
+	return blk_select_hwpart(dev, hwpart);
+}
+
 int blk_list_part(enum if_type if_type)
 {
 	struct blk_desc *desc;
@@ -291,6 +303,23 @@ ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
 	return blk_dwrite(desc, start, blkcnt, buffer);
 }
 
+int blk_select_hwpart(struct udevice *dev, int hwpart)
+{
+	const struct blk_ops *ops = blk_get_ops(dev);
+
+	if (!ops)
+		return -ENOSYS;
+	if (!ops->select_hwpart)
+		return 0;
+
+	return ops->select_hwpart(dev, hwpart);
+}
+
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
+{
+	return blk_select_hwpart(desc->bdev, hwpart);
+}
+
 int blk_first_device(int if_type, struct udevice **devp)
 {
 	struct blk_desc *desc;
diff --git a/include/blk.h b/include/blk.h
index 82b2c1a..3fa373e 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -211,6 +211,25 @@ struct blk_ops {
 	 */
 	unsigned long (*erase)(struct udevice *dev, lbaint_t start,
 			       lbaint_t blkcnt);
+
+	/**
+	 * select_hwpart() - select a particular hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 *
+	 * @desc:	Block device to update
+	 * @hwpart:	Hardware partition number to select. 0 means the raw
+	 *		device, 1 is the first partition, 2 is the second, etc.
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*select_hwpart)(struct udevice *dev, int hwpart);
 };
 
 #define blk_get_ops(dev)	((struct blk_ops *)(dev)->driver->ops)
@@ -329,6 +348,17 @@ int blk_unbind_all(int if_type);
  */
 int blk_find_max_devnum(enum if_type if_type);
 
+/**
+ * blk_select_hwpart() - select a hardware partition
+ *
+ * Select a hardware partition if the device supports it (typically MMC does)
+ *
+ * @dev:	Device to update
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart(struct udevice *dev, int hwpart);
+
 #else
 #include <errno.h>
 /*
-- 
cgit v0.10.2


From 1fde473da7a5de1e6ad1c72d1b84763642bb1a9f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:31 -0600
Subject: dm: part: Use the legacy block driver for hardware partition support

Drop use of the table in part.c for this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index e635d90..db5dd5d 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -71,9 +71,7 @@ static struct part_driver *part_driver_lookup_type(int part_type)
 static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
 	const struct block_drvr *drvr = block_drvr;
-	int (*select_hwpart)(int dev_num, int hwpart);
 	char *name;
-	int ret;
 
 	if (!ifname)
 		return NULL;
@@ -84,11 +82,8 @@ static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 #endif
 	while (drvr->name) {
 		name = drvr->name;
-		select_hwpart = drvr->select_hwpart;
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 		name += gd->reloc_off;
-		if (select_hwpart)
-			select_hwpart += gd->reloc_off;
 #endif
 		if (strncmp(ifname, name, strlen(name)) == 0) {
 			struct blk_desc *dev_desc;
@@ -96,12 +91,7 @@ static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 			dev_desc = blk_get_devnum_by_typename(name, dev);
 			if (!dev_desc)
 				return NULL;
-			if (hwpart == 0 && !select_hwpart)
-				return dev_desc;
-			if (!select_hwpart)
-				return NULL;
-			ret = select_hwpart(dev_desc->devnum, hwpart);
-			if (ret < 0)
+			if (blk_dselect_hwpart(dev_desc, hwpart))
 				return NULL;
 			return dev_desc;
 		}
-- 
cgit v0.10.2


From 6dd9faf8f97e1aad9961a480775612f6cbde27de Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:32 -0600
Subject: dm: part: Drop the block_drvr table

This is not needed since we can use the functions provided by the legacy
block device support.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index db5dd5d..3039f5f 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -21,34 +21,6 @@
 #define PRINTF(fmt,args...)
 #endif
 
-const struct block_drvr block_drvr[] = {
-#if defined(CONFIG_CMD_IDE)
-	{ .name = "ide", },
-#endif
-#if defined(CONFIG_CMD_SATA)
-	{.name = "sata", },
-#endif
-#if defined(CONFIG_SCSI)
-	{ .name = "scsi", },
-#endif
-#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
-	{ .name = "usb", },
-#endif
-#if defined(CONFIG_MMC)
-	{
-		.name = "mmc",
-		.select_hwpart = mmc_select_hwpart,
-	},
-#endif
-#if defined(CONFIG_SYSTEMACE)
-	{ .name = "ace", },
-#endif
-#if defined(CONFIG_SANDBOX)
-	{ .name = "host", },
-#endif
-	{ },
-};
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef HAVE_BLOCK_DEVICE
@@ -70,34 +42,23 @@ static struct part_driver *part_driver_lookup_type(int part_type)
 
 static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
 {
-	const struct block_drvr *drvr = block_drvr;
-	char *name;
+	struct blk_desc *dev_desc;
+	int ret;
 
-	if (!ifname)
+	dev_desc = blk_get_devnum_by_typename(ifname, dev);
+	if (!dev_desc) {
+		debug("%s: No device for iface '%s', dev %d\n", __func__,
+		      ifname, dev);
 		return NULL;
-
-	name = drvr->name;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-	name += gd->reloc_off;
-#endif
-	while (drvr->name) {
-		name = drvr->name;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
-		name += gd->reloc_off;
-#endif
-		if (strncmp(ifname, name, strlen(name)) == 0) {
-			struct blk_desc *dev_desc;
-
-			dev_desc = blk_get_devnum_by_typename(name, dev);
-			if (!dev_desc)
-				return NULL;
-			if (blk_dselect_hwpart(dev_desc, hwpart))
-				return NULL;
-			return dev_desc;
-		}
-		drvr++;
 	}
-	return NULL;
+	ret = blk_dselect_hwpart(dev_desc, hwpart);
+	if (ret) {
+		debug("%s: Failed to select h/w partition: err-%d\n", __func__,
+		      ret);
+		return NULL;
+	}
+
+	return dev_desc;
 }
 
 struct blk_desc *blk_get_dev(const char *ifname, int dev)
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 28e5b7f..075fd34 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <blk.h>
 #include <efi_loader.h>
 #include <inttypes.h>
 #include <part.h>
@@ -142,7 +143,7 @@ static const struct efi_block_io block_io_disk_template = {
 };
 
 static void efi_disk_add_dev(char *name,
-			     const struct block_drvr *cur_drvr,
+			     const struct blk_driver *cur_drvr,
 			     const struct blk_desc *desc,
 			     int dev_index,
 			     lbaint_t offset)
@@ -160,7 +161,7 @@ static void efi_disk_add_dev(char *name,
 	diskobj->parent.protocols[1].open = efi_disk_open_dp;
 	diskobj->parent.handle = diskobj;
 	diskobj->ops = block_io_disk_template;
-	diskobj->ifname = cur_drvr->name;
+	diskobj->ifname = cur_drvr->if_typename;
 	diskobj->dev_index = dev_index;
 	diskobj->offset = offset;
 
@@ -189,7 +190,7 @@ static void efi_disk_add_dev(char *name,
 }
 
 static int efi_disk_create_eltorito(struct blk_desc *desc,
-				    const struct block_drvr *cur_drvr,
+				    const struct blk_driver *cur_drvr,
 				    int diskid)
 {
 	int disks = 0;
@@ -202,8 +203,8 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
 		return 0;
 
 	while (!part_get_info(desc, part, &info)) {
-		snprintf(devname, sizeof(devname), "%s%d:%d", cur_drvr->name,
-			 diskid, part);
+		snprintf(devname, sizeof(devname), "%s%d:%d",
+			 cur_drvr->if_typename, diskid, part);
 		efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
 		part++;
 		disks++;
@@ -222,25 +223,29 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
  */
 int efi_disk_register(void)
 {
-	const struct block_drvr *cur_drvr;
-	int i;
+	const struct blk_driver *cur_drvr;
+	int i, if_type;
 	int disks = 0;
 
 	/* Search for all available disk devices */
-	for (cur_drvr = block_drvr; cur_drvr->name; cur_drvr++) {
-		printf("Scanning disks on %s...\n", cur_drvr->name);
+	for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+		cur_drvr = blk_driver_lookup_type(if_type);
+		if (!cur_drvr)
+			continue;
+
+		printf("Scanning disks on %s...\n", cur_drvr->if_typename);
 		for (i = 0; i < 4; i++) {
 			struct blk_desc *desc;
 			char devname[32] = { 0 }; /* dp->str is u16[32] long */
 
-			desc = blk_get_dev(cur_drvr->name, i);
+			desc = blk_get_devnum_by_type(if_type, i);
 			if (!desc)
 				continue;
 			if (desc->type == DEV_TYPE_UNKNOWN)
 				continue;
 
 			snprintf(devname, sizeof(devname), "%s%d",
-				 cur_drvr->name, i);
+				 cur_drvr->if_typename, i);
 			efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
 			disks++;
 
-- 
cgit v0.10.2


From b6694a33c45530e4c260c7fd6c77cc8472c9412f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:33 -0600
Subject: dm: blk: Add a comment as to why the bdev member is needed

This member should be explained, since it is not obvious why it is needed.
Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/blk.h b/include/blk.h
index 3fa373e..66a1c55 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -63,6 +63,11 @@ struct blk_desc {
 	char		product[20+1];	/* IDE Serial no, SCSI product */
 	char		revision[8+1];	/* firmware revision */
 #ifdef CONFIG_BLK
+	/*
+	 * For now we have a few functions which take struct blk_desc as a
+	 * parameter. This field allows them to look up the associated
+	 * device. Once these functions are removed we can drop this field.
+	 */
 	struct udevice *bdev;
 #else
 	unsigned long	(*block_read)(struct blk_desc *block_dev,
-- 
cgit v0.10.2


From cffe5d86cfe853ae9271d37522f8bc5795cc4c69 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:34 -0600
Subject: dm: mmc: Set up the device pointer when using the MMC uclass

Update the existing drivers to set up this new pointer. This will be required
by the MMC uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 85a832b..be34057 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -825,6 +825,7 @@ static int omap_hsmmc_probe(struct udevice *dev)
 	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 #endif
 
+	mmc->dev = dev;
 	upriv->mmc = mmc;
 
 	return 0;
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
index e03d6dd..abe7429 100644
--- a/drivers/mmc/pic32_sdhci.c
+++ b/drivers/mmc/pic32_sdhci.c
@@ -41,7 +41,12 @@ static int pic32_sdhci_probe(struct udevice *dev)
 		return ret;
 	}
 
-	return add_sdhci(host, f_min_max[1], f_min_max[0]);
+	ret = add_sdhci(host, f_min_max[1], f_min_max[0]);
+	if (ret)
+		return ret;
+	host->mmc->dev = dev;
+
+	return 0;
 }
 
 static const struct udevice_id pic32_sdhci_ids[] = {
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index cb9e104..0a261c5 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -104,6 +104,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
+	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
 
 	return 0;
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 097db81..6a0e971 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -108,6 +108,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
 		return ret;
 
 	upriv->mmc = host->mmc;
+	host->mmc->dev = dev;
 
 	return 0;
 }
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 81a80cd..4978cca 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -725,6 +725,7 @@ int uniphier_sd_probe(struct udevice *dev)
 		return -EIO;
 
 	upriv->mmc = priv->mmc;
+	priv->mmc->dev = dev;
 
 	return 0;
 }
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index b59feca..d405929 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -35,6 +35,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
 		  CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 
 	upriv->mmc = host->mmc;
+	host->mmc->dev = dev;
 
 	return 0;
 }
diff --git a/include/mmc.h b/include/mmc.h
index f01674d..6d1f05c 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -381,6 +381,9 @@ struct mmc {
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
 	int ddr_mode;
+#ifdef CONFIG_DM_MMC
+	struct udevice *dev;	/* Device for this MMC controller */
+#endif
 };
 
 struct mmc_hwpart_conf {
-- 
cgit v0.10.2


From c40fdca6b7db469d3982cc44fd68a269adb41b25 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:35 -0600
Subject: dm: mmc: Move the device list into a separate file

At present the MMC subsystem maintains its own list of MMC devices. This
cannot work with driver model, which needs to maintain this itself. Move the
list code into a separate 'legacy' file. The core MMC code remains, and will
be shared with the driver-model implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/mmc.c b/cmd/mmc.c
index 8695c19..eb4a547 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -348,7 +348,7 @@ static int do_mmc_read(cmd_tbl_t *cmdtp, int flag,
 	printf("\nMMC read: dev # %d, block # %d, count %d ... ",
 	       curr_device, blk, cnt);
 
-	n = blk_dread(&mmc->block_dev, blk, cnt, addr);
+	n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
 	/* flush cache after read */
 	flush_cache((ulong)addr, cnt * 512); /* FIXME */
 	printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
@@ -380,7 +380,7 @@ static int do_mmc_write(cmd_tbl_t *cmdtp, int flag,
 		printf("Error: card is write protected!\n");
 		return CMD_RET_FAILURE;
 	}
-	n = blk_dwrite(&mmc->block_dev, blk, cnt, addr);
+	n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
 	printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
 
 	return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
@@ -408,7 +408,7 @@ static int do_mmc_erase(cmd_tbl_t *cmdtp, int flag,
 		printf("Error: card is write protected!\n");
 		return CMD_RET_FAILURE;
 	}
-	n = blk_derase(&mmc->block_dev, blk, cnt);
+	n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt);
 	printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
 
 	return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
@@ -480,7 +480,7 @@ static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag,
 		printf("mmc%d is current device\n", curr_device);
 	else
 		printf("mmc%d(part %d) is current device\n",
-		       curr_device, mmc->block_dev.hwpart);
+		       curr_device, mmc_get_blk_desc(mmc)->hwpart);
 
 	return CMD_RET_SUCCESS;
 }
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 585aaf3..6241649 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -7,6 +7,10 @@
 
 obj-$(CONFIG_DM_MMC) += mmc-uclass.o
 
+ifndef CONFIG_BLK
+obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
+endif
+
 obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
 obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 7322f334..48aedc2 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,14 +21,6 @@
 #include <div64.h>
 #include "mmc_private.h"
 
-static struct list_head mmc_devices;
-static int cur_dev_num = -1;
-
-struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
-{
-	return &mmc->block_dev;
-}
-
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
@@ -183,25 +175,6 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
 	return mmc_send_cmd(mmc, &cmd, NULL);
 }
 
-struct mmc *find_mmc_device(int dev_num)
-{
-	struct mmc *m;
-	struct list_head *entry;
-
-	list_for_each(entry, &mmc_devices) {
-		m = list_entry(entry, struct mmc, link);
-
-		if (m->block_dev.devnum == dev_num)
-			return m;
-	}
-
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-	printf("MMC Device %d not found\n", dev_num);
-#endif
-
-	return NULL;
-}
-
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 			   lbaint_t blkcnt)
 {
@@ -261,10 +234,10 @@ static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
 	if (err < 0)
 		return 0;
 
-	if ((start + blkcnt) > mmc->block_dev.lba) {
+	if ((start + blkcnt) > block_dev->lba) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
-			start + blkcnt, mmc->block_dev.lba);
+			start + blkcnt, block_dev->lba);
 #endif
 		return 0;
 	}
@@ -582,7 +555,7 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
 		return -1;
 	}
 
-	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+	mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 
 	return 0;
 }
@@ -1062,6 +1035,7 @@ static int mmc_startup(struct mmc *mmc)
 	int timeout = 1000;
 	bool has_parts = false;
 	bool part_completed;
+	struct blk_desc *bdesc;
 
 #ifdef CONFIG_MMC_SPI_CRC_ON
 	if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
@@ -1358,7 +1332,7 @@ static int mmc_startup(struct mmc *mmc)
 		mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
 	}
 
-	err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
+	err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
 	if (err)
 		return err;
 
@@ -1498,31 +1472,32 @@ static int mmc_startup(struct mmc *mmc)
 	}
 
 	/* fill in device description */
-	mmc->block_dev.lun = 0;
-	mmc->block_dev.hwpart = 0;
-	mmc->block_dev.type = 0;
-	mmc->block_dev.blksz = mmc->read_bl_len;
-	mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
-	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->lun = 0;
+	bdesc->hwpart = 0;
+	bdesc->type = 0;
+	bdesc->blksz = mmc->read_bl_len;
+	bdesc->log2blksz = LOG2(bdesc->blksz);
+	bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
 #if !defined(CONFIG_SPL_BUILD) || \
 		(defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
 		!defined(CONFIG_USE_TINY_PRINTF))
-	sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
+	sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
 		mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
 		(mmc->cid[3] >> 16) & 0xffff);
-	sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
+	sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
 		(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
 		(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
 		(mmc->cid[2] >> 24) & 0xff);
-	sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
+	sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
 		(mmc->cid[2] >> 16) & 0xf);
 #else
-	mmc->block_dev.vendor[0] = 0;
-	mmc->block_dev.product[0] = 0;
-	mmc->block_dev.revision[0] = 0;
+	bdesc->vendor[0] = 0;
+	bdesc->product[0] = 0;
+	bdesc->revision[0] = 0;
 #endif
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
-	part_init(&mmc->block_dev);
+	part_init(bdesc);
 #endif
 
 	return 0;
@@ -1562,6 +1537,7 @@ int __deprecated mmc_register(struct mmc *mmc)
 
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
+	struct blk_desc *bdesc;
 	struct mmc *mmc;
 
 	/* quick validation */
@@ -1582,19 +1558,17 @@ struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 	mmc->dsr_imp = 0;
 	mmc->dsr = 0xffffffff;
 	/* Setup the universal parts of the block interface just once */
-	mmc->block_dev.if_type = IF_TYPE_MMC;
-	mmc->block_dev.devnum = cur_dev_num++;
-	mmc->block_dev.removable = 1;
-	mmc->block_dev.block_read = mmc_bread;
-	mmc->block_dev.block_write = mmc_bwrite;
-	mmc->block_dev.block_erase = mmc_berase;
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->if_type = IF_TYPE_MMC;
+	bdesc->removable = 1;
+	bdesc->devnum = mmc_get_next_devnum();
+	bdesc->block_read = mmc_bread;
+	bdesc->block_write = mmc_bwrite;
+	bdesc->block_erase = mmc_berase;
 
 	/* setup initial part type */
-	mmc->block_dev.part_type = mmc->cfg->part_type;
-
-	INIT_LIST_HEAD(&mmc->link);
-
-	list_add_tail(&mmc->link, &mmc_devices);
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc_list_add(mmc);
 
 	return mmc;
 }
@@ -1664,7 +1638,7 @@ int mmc_start_init(struct mmc *mmc)
 		return err;
 
 	/* The internal partition reset to user partition(0) at every CMD0*/
-	mmc->block_dev.hwpart = 0;
+	mmc_get_blk_desc(mmc)->hwpart = 0;
 
 	/* Test for SD version 2 */
 	err = mmc_send_if_cond(mmc);
@@ -1744,66 +1718,11 @@ __weak int board_mmc_init(bd_t *bis)
 	return -1;
 }
 
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-
-void print_mmc_devices(char separator)
-{
-	struct mmc *m;
-	struct list_head *entry;
-	char *mmc_type;
-
-	list_for_each(entry, &mmc_devices) {
-		m = list_entry(entry, struct mmc, link);
-
-		if (m->has_init)
-			mmc_type = IS_SD(m) ? "SD" : "eMMC";
-		else
-			mmc_type = NULL;
-
-		printf("%s: %d", m->cfg->name, m->block_dev.devnum);
-		if (mmc_type)
-			printf(" (%s)", mmc_type);
-
-		if (entry->next != &mmc_devices) {
-			printf("%c", separator);
-			if (separator != '\n')
-				puts (" ");
-		}
-	}
-
-	printf("\n");
-}
-
-#else
-void print_mmc_devices(char separator) { }
-#endif
-
-int get_mmc_num(void)
-{
-	return cur_dev_num;
-}
-
 void mmc_set_preinit(struct mmc *mmc, int preinit)
 {
 	mmc->preinit = preinit;
 }
 
-static void do_preinit(void)
-{
-	struct mmc *m;
-	struct list_head *entry;
-
-	list_for_each(entry, &mmc_devices) {
-		m = list_entry(entry, struct mmc, link);
-
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
-		mmc_set_preinit(m, 1);
-#endif
-		if (m->preinit)
-			mmc_start_init(m);
-	}
-}
-
 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
 static int mmc_probe(bd_t *bis)
 {
@@ -1856,9 +1775,9 @@ int mmc_initialize(bd_t *bis)
 		return 0;
 	initialized = 1;
 
-	INIT_LIST_HEAD (&mmc_devices);
-	cur_dev_num = 0;
-
+#ifndef CONFIG_BLK
+	mmc_list_init();
+#endif
 	ret = mmc_probe(bis);
 	if (ret)
 		return ret;
@@ -1867,7 +1786,7 @@ int mmc_initialize(bd_t *bis)
 	print_mmc_devices(',');
 #endif
 
-	do_preinit();
+	mmc_do_preinit();
 	return 0;
 }
 
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
new file mode 100644
index 0000000..3ec649f
--- /dev/null
+++ b/drivers/mmc/mmc_legacy.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+static struct list_head mmc_devices;
+static int cur_dev_num = -1;
+
+struct mmc *find_mmc_device(int dev_num)
+{
+	struct mmc *m;
+	struct list_head *entry;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+		if (m->block_dev.devnum == dev_num)
+			return m;
+	}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+	printf("MMC Device %d not found\n", dev_num);
+#endif
+
+	return NULL;
+}
+
+int mmc_get_next_devnum(void)
+{
+	return cur_dev_num++;
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+	return &mmc->block_dev;
+}
+
+int get_mmc_num(void)
+{
+	return cur_dev_num;
+}
+
+void mmc_do_preinit(void)
+{
+	struct mmc *m;
+	struct list_head *entry;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+		mmc_set_preinit(m, 1);
+#endif
+		if (m->preinit)
+			mmc_start_init(m);
+	}
+}
+
+void mmc_list_init(void)
+{
+	INIT_LIST_HEAD(&mmc_devices);
+	cur_dev_num = 0;
+}
+
+void mmc_list_add(struct mmc *mmc)
+{
+	INIT_LIST_HEAD(&mmc->link);
+
+	list_add_tail(&mmc->link, &mmc_devices);
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+void print_mmc_devices(char separator)
+{
+	struct mmc *m;
+	struct list_head *entry;
+	char *mmc_type;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+		if (m->has_init)
+			mmc_type = IS_SD(m) ? "SD" : "eMMC";
+		else
+			mmc_type = NULL;
+
+		printf("%s: %d", m->cfg->name, m->block_dev.devnum);
+		if (mmc_type)
+			printf(" (%s)", mmc_type);
+
+		if (entry->next != &mmc_devices) {
+			printf("%c", separator);
+			if (separator != '\n')
+				puts(" ");
+		}
+	}
+
+	printf("\n");
+}
+
+#else
+void print_mmc_devices(char separator) { }
+#endif
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index d3f6bfe..6ec52fd 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -46,4 +46,28 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
 
 #endif /* CONFIG_SPL_BUILD */
 
+/**
+ * mmc_get_next_devnum() - Get the next available MMC device number
+ *
+ * @return next available device number (0 = first), or -ve on error
+ */
+int mmc_get_next_devnum(void);
+
+/**
+ * mmc_do_preinit() - Get an MMC device ready for use
+ */
+void mmc_do_preinit(void);
+
+/**
+ * mmc_list_init() - Set up the list of MMC devices
+ */
+void mmc_list_init(void);
+
+/**
+ * mmc_list_add() - Add a new MMC device to the list of devices
+ *
+ * @mmc:	Device to add
+ */
+void mmc_list_add(struct mmc *mmc);
+
 #endif /* _MMC_PRIVATE_H_ */
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index f4d42aa..bd07b20 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -122,9 +122,9 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
 	struct mmc_data data;
 	int timeout = 1000;
 
-	if ((start + blkcnt) > mmc->block_dev.lba) {
+	if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) {
 		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
-		       start + blkcnt, mmc->block_dev.lba);
+		       start + blkcnt, mmc_get_blk_desc(mmc)->lba);
 		return 0;
 	}
 
-- 
cgit v0.10.2


From 1598dfcb101c2c3aaac68a4ac8fc9bdef2293eaa Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:36 -0600
Subject: dm: blk: Use the correct error code for blk_get_device_by_str()

Return -EINVAL instead of -1 in this function, to provide a more meaningful
error.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/disk/part.c b/disk/part.c
index 3039f5f..6a1c02d 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -350,7 +350,7 @@ int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
 	if (*ep) {
 		printf("** Bad device specification %s %s **\n",
 		       ifname, dev_str);
-		dev = -1;
+		dev = -EINVAL;
 		goto cleanup;
 	}
 
@@ -359,7 +359,7 @@ int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
 		if (*ep) {
 			printf("** Bad HW partition specification %s %s **\n",
 			    ifname, hwpart_str);
-			dev = -1;
+			dev = -EINVAL;
 			goto cleanup;
 		}
 	}
@@ -367,7 +367,7 @@ int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
 	*dev_desc = get_dev_hwpart(ifname, dev, hwpart);
 	if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
 		printf("** Bad device %s %s **\n", ifname, dev_hwpart_str);
-		dev = -1;
+		dev = -ENOENT;
 		goto cleanup;
 	}
 
-- 
cgit v0.10.2


From fdbb139f0ce10325b44dd3ec76993f8c8e798395 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:37 -0600
Subject: dm: mmc: Adjust mmc_switch_part() to use a struct mmc

Instead of looking up the MMC device by number, just pass it in. This makes
it possible to use this function with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 48aedc2..4ba13a1 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -560,14 +560,10 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
 	return 0;
 }
 
-int mmc_switch_part(int dev_num, unsigned int part_num)
+static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 {
-	struct mmc *mmc = find_mmc_device(dev_num);
 	int ret;
 
-	if (!mmc)
-		return -1;
-
 	ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
 			 (mmc->part_config & ~PART_ACCESS_MASK)
 			 | (part_num & PART_ACCESS_MASK));
@@ -578,7 +574,7 @@ int mmc_switch_part(int dev_num, unsigned int part_num)
 	 */
 	if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
 		ret = mmc_set_capacity(mmc, part_num);
-		mmc->block_dev.hwpart = part_num;
+		mmc_get_blk_desc(mmc)->hwpart = part_num;
 	}
 
 	return ret;
@@ -598,7 +594,7 @@ static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
 	if (mmc->part_config == MMCPART_NOAVAILABLE)
 		return -EMEDIUMTYPE;
 
-	ret = mmc_switch_part(desc->devnum, hwpart);
+	ret = mmc_switch_part(mmc, hwpart);
 	if (ret)
 		return ret;
 
@@ -619,7 +615,7 @@ int mmc_select_hwpart(int dev_num, int hwpart)
 	if (mmc->part_config == MMCPART_NOAVAILABLE)
 		return -EMEDIUMTYPE;
 
-	ret = mmc_switch_part(dev_num, hwpart);
+	ret = mmc_switch_part(mmc, hwpart);
 	if (ret)
 		return ret;
 
-- 
cgit v0.10.2


From f8b7752e8f42c6f0bb8725f2488e398c849a7bf4 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:38 -0600
Subject: dm: sandbox: Only enable the sandbox MMC driver when valid

This driver will require generic MMC and block-device support in a future
commit. To avoid test errors, make this change now.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 6241649..38a172b 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -38,7 +38,11 @@ obj-$(CONFIG_ROCKCHIP_DWMMC) += rockchip_dw_mmc.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
 obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+ifdef CONFIG_BLK
+ifdef CONFIG_GENERIC_MMC
 obj-$(CONFIG_SANDBOX) += sandbox_mmc.o
+endif
+endif
 obj-$(CONFIG_SDHCI) += sdhci.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 9a11ae0..8ec391b 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,7 +21,9 @@ obj-$(CONFIG_DM_ETH) += eth.o
 obj-$(CONFIG_DM_GPIO) += gpio.o
 obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_LED) += led.o
-obj-$(CONFIG_DM_MMC) += mmc.o
+
+# Disable temporarily
+# obj-$(CONFIG_DM_MMC) += mmc.o
 obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
-- 
cgit v0.10.2


From 8ef761ed4cda2d078b3d8b098d105472cbad8fb5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:39 -0600
Subject: dm: mmc: Implement the MMC functions for block devices

Implement the functions in mmc_legacy.c for driver-model block devices, so
that MMC can use driver model for these. This allows CONFIG_BLK to be enabled
with DM_MMC.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 38a172b..3da4817 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -5,7 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_DM_MMC) += mmc-uclass.o
+ifdef CONFIG_DM_MMC
+obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o
+endif
 
 ifndef CONFIG_BLK
 obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 777489f..1b967d9 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -21,6 +21,112 @@ struct mmc *mmc_get_mmc_dev(struct udevice *dev)
 	return upriv->mmc;
 }
 
+#ifdef CONFIG_BLK
+struct mmc *find_mmc_device(int dev_num)
+{
+	struct udevice *dev, *mmc_dev;
+	int ret;
+
+	ret = blk_get_device(IF_TYPE_MMC, dev_num, &dev);
+
+	if (ret) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+		printf("MMC Device %d not found\n", dev_num);
+#endif
+		return NULL;
+	}
+
+	mmc_dev = dev_get_parent(dev);
+
+	return mmc_get_mmc_dev(mmc_dev);
+}
+
+int get_mmc_num(void)
+{
+	return max(blk_find_max_devnum(IF_TYPE_MMC), 0);
+}
+
+int mmc_get_next_devnum(void)
+{
+	int ret;
+
+	ret = get_mmc_num();
+	if (ret < 0)
+		return ret;
+
+	return ret + 1;
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+	struct blk_desc *desc;
+	struct udevice *dev;
+
+	device_find_first_child(mmc->dev, &dev);
+	if (!dev)
+		return NULL;
+	desc = dev_get_uclass_platdata(dev);
+
+	return desc;
+}
+
+void mmc_do_preinit(void)
+{
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(UCLASS_MMC, &uc);
+	if (ret)
+		return;
+	uclass_foreach_dev(dev, uc) {
+		struct mmc *m = mmc_get_mmc_dev(dev);
+
+		if (!m)
+			continue;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+		mmc_set_preinit(m, 1);
+#endif
+		if (m->preinit)
+			mmc_start_init(m);
+	}
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+void print_mmc_devices(char separator)
+{
+	struct udevice *dev;
+	char *mmc_type;
+	bool first = true;
+
+	for (uclass_first_device(UCLASS_MMC, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct mmc *m = mmc_get_mmc_dev(dev);
+
+		if (!first) {
+			printf("%c", separator);
+			if (separator != '\n')
+				puts(" ");
+		}
+		if (m->has_init)
+			mmc_type = IS_SD(m) ? "SD" : "eMMC";
+		else
+			mmc_type = NULL;
+
+		printf("%s: %d", m->cfg->name, mmc_get_blk_desc(m)->devnum);
+		if (mmc_type)
+			printf(" (%s)", mmc_type);
+	}
+
+	printf("\n");
+}
+
+#else
+void print_mmc_devices(char separator) { }
+#endif
+#endif /* CONFIG_BLK */
+
 U_BOOT_DRIVER(mmc) = {
 	.name	= "mmc",
 	.id	= UCLASS_MMC,
-- 
cgit v0.10.2


From ad27dd5e13436b554f0f3cb9cd3e79634494072d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:40 -0600
Subject: dm: mmc: Add a way to bind MMC devices with driver model

Binding an MMC device when CONFIG_BLK is enabled requires that a block
device be bound as a child of the MMC device. Add a function to do this.
The mmc_create() method will be used only when DM_BLK is disabled.

Add an unbind method also.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 4ba13a1..7183afc 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1531,6 +1531,53 @@ int __deprecated mmc_register(struct mmc *mmc)
 	return -1;
 }
 
+#ifdef CONFIG_BLK
+int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
+{
+	struct blk_desc *bdesc;
+	struct udevice *bdev;
+	int ret;
+
+	ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512,
+				 0, &bdev);
+	if (ret) {
+		debug("Cannot create block device\n");
+		return ret;
+	}
+	bdesc = dev_get_uclass_platdata(bdev);
+	mmc->cfg = cfg;
+	mmc->priv = dev;
+
+	/* the following chunk was from mmc_register() */
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = 0xffffffff;
+	/* Setup the universal parts of the block interface just once */
+	bdesc->if_type = IF_TYPE_MMC;
+	bdesc->removable = 1;
+
+	/* setup initial part type */
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc->dev = dev;
+
+	return 0;
+}
+
+int mmc_unbind(struct udevice *dev)
+{
+	struct udevice *bdev;
+
+	device_find_first_child(dev, &bdev);
+	if (bdev) {
+		device_remove(bdev);
+		device_unbind(bdev);
+	}
+
+	return 0;
+}
+
+#else
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
 	struct blk_desc *bdesc;
@@ -1574,6 +1621,7 @@ void mmc_destroy(struct mmc *mmc)
 	/* only freeing memory for now */
 	free(mmc);
 }
+#endif
 
 static int mmc_get_dev(int dev, struct blk_desc **descp)
 {
diff --git a/include/mmc.h b/include/mmc.h
index 6d1f05c..fb8d9b2 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -409,7 +409,29 @@ enum mmc_hwpart_conf_mode {
 
 int mmc_register(struct mmc *mmc);
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
+
+/**
+ * mmc_bind() - Set up a new MMC device ready for probing
+ *
+ * A child block device is bound with the IF_TYPE_MMC interface type. This
+ * allows the device to be used with CONFIG_BLK
+ *
+ * @dev:	MMC device to set up
+ * @mmc:	MMC struct
+ * @cfg:	MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_bind(struct udevice *dev, struct mmc *mmc,
+	     const struct mmc_config *cfg);
 void mmc_destroy(struct mmc *mmc);
+
+/**
+ * mmc_unbind() - Unbind a MMC device's child block device
+ *
+ * @dev:	MMC device
+ * @return 0 if OK, -ve on error
+ */
+int mmc_unbind(struct udevice *dev);
 int mmc_initialize(bd_t *bis);
 int mmc_init(struct mmc *mmc);
 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
-- 
cgit v0.10.2


From 33fb211dd2706e666db4008801dc0d5903fd82f6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:41 -0600
Subject: dm: mmc: Add support for driver-model block devices

Add support for enabling CONFIG_BLK with MMC. This involves changing a
few functions to use struct udevice and adding a MMC block device driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 7183afc..74b3d68 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -216,9 +216,17 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 	return blkcnt;
 }
 
+#ifdef CONFIG_BLK
+static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		       void *dst)
+#else
 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
 		       lbaint_t blkcnt, void *dst)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int dev_num = block_dev->devnum;
 	int err;
 	lbaint_t cur, blocks_todo = blkcnt;
@@ -580,15 +588,15 @@ static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 	return ret;
 }
 
-static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
+#ifdef CONFIG_BLK
+static int mmc_select_hwpart(struct udevice *bdev, int hwpart)
 {
-	struct mmc *mmc = find_mmc_device(desc->devnum);
+	struct udevice *mmc_dev = dev_get_parent(bdev);
+	struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
+	struct blk_desc *desc = dev_get_uclass_platdata(bdev);
 	int ret;
 
-	if (!mmc)
-		return -ENODEV;
-
-	if (mmc->block_dev.hwpart == hwpart)
+	if (desc->hwpart == hwpart)
 		return 0;
 
 	if (mmc->part_config == MMCPART_NOAVAILABLE)
@@ -600,10 +608,10 @@ static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
 
 	return 0;
 }
-
-int mmc_select_hwpart(int dev_num, int hwpart)
+#else
+static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
 {
-	struct mmc *mmc = find_mmc_device(dev_num);
+	struct mmc *mmc = find_mmc_device(desc->devnum);
 	int ret;
 
 	if (!mmc)
@@ -621,6 +629,7 @@ int mmc_select_hwpart(int dev_num, int hwpart)
 
 	return 0;
 }
+#endif
 
 int mmc_hwpart_config(struct mmc *mmc,
 		      const struct mmc_hwpart_conf *conf,
@@ -1554,7 +1563,6 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 	mmc->dsr_imp = 0;
 	mmc->dsr = 0xffffffff;
 	/* Setup the universal parts of the block interface just once */
-	bdesc->if_type = IF_TYPE_MMC;
 	bdesc->removable = 1;
 
 	/* setup initial part type */
@@ -1623,6 +1631,7 @@ void mmc_destroy(struct mmc *mmc)
 }
 #endif
 
+#ifndef CONFIG_BLK
 static int mmc_get_dev(int dev, struct blk_desc **descp)
 {
 	struct mmc *mmc = find_mmc_device(dev);
@@ -1638,6 +1647,7 @@ static int mmc_get_dev(int dev, struct blk_desc **descp)
 
 	return 0;
 }
+#endif
 
 /* board-specific MMC power initializations. */
 __weak void board_mmc_power_init(void)
@@ -1729,7 +1739,11 @@ int mmc_init(struct mmc *mmc)
 {
 	int err = 0;
 	unsigned start;
+#ifdef CONFIG_DM_MMC
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
 
+	upriv->mmc = mmc;
+#endif
 	if (mmc->has_init)
 		return 0;
 
@@ -1957,6 +1971,19 @@ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
 }
 #endif
 
+#ifdef CONFIG_BLK
+static const struct blk_ops mmc_blk_ops = {
+	.read	= mmc_bread,
+	.write	= mmc_bwrite,
+	.select_hwpart	= mmc_select_hwpart,
+};
+
+U_BOOT_DRIVER(mmc_blk) = {
+	.name		= "mmc_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &mmc_blk_ops,
+};
+#else
 U_BOOT_LEGACY_BLK(mmc) = {
 	.if_typename	= "mmc",
 	.if_type	= IF_TYPE_MMC,
@@ -1964,3 +1991,4 @@ U_BOOT_LEGACY_BLK(mmc) = {
 	.get_dev	= mmc_get_dev,
 	.select_hwpart	= mmc_select_hwpartp,
 };
+#endif
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 6ec52fd..27b9e5f 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -25,8 +25,13 @@ void mmc_adapter_card_type_ident(void);
 unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
 			 lbaint_t blkcnt);
 
-unsigned long mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
-			 lbaint_t blkcnt, const void *src);
+#ifdef CONFIG_BLK
+ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		 const void *src);
+#else
+ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
+		 const void *src);
+#endif
 
 #else /* CONFIG_SPL_BUILD */
 
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index bd07b20..0f8b5c7 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -9,6 +9,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <dm.h>
 #include <part.h>
 #include <div64.h>
 #include <linux/math64.h>
@@ -172,9 +173,17 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
 	return blkcnt;
 }
 
+#ifdef CONFIG_BLK
+ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		 const void *src)
+#else
 ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 		 const void *src)
+#endif
 {
+#ifdef CONFIG_BLK
+	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
 	int dev_num = block_dev->devnum;
 	lbaint_t cur, blocks_todo = blkcnt;
 	int err;
diff --git a/include/mmc.h b/include/mmc.h
index fb8d9b2..a5c6573 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -344,7 +344,9 @@ struct mmc_config {
 
 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 struct mmc {
+#ifndef CONFIG_BLK
 	struct list_head link;
+#endif
 	const struct mmc_config *cfg;	/* provided configuration */
 	uint version;
 	void *priv;
@@ -376,7 +378,9 @@ struct mmc {
 	u64 capacity_gp[4];
 	u64 enh_user_start;
 	u64 enh_user_size;
+#ifndef CONFIG_BLK
 	struct blk_desc block_dev;
+#endif
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
diff --git a/include/part.h b/include/part.h
index bc9dc64..226b5be 100644
--- a/include/part.h
+++ b/include/part.h
@@ -73,23 +73,6 @@ typedef struct disk_partition {
  */
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
 
-/**
- * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
- *
- * MMC devices can support partitioning at the hardware level. This is quite
- * separate from the normal idea of software-based partitions. MMC hardware
- * partitions must be explicitly selected. Once selected only the region of
- * the device covered by that partition is accessible.
- *
- * The MMC standard provides for two boot partitions (numbered 1 and 2),
- * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
- *
- * @dev_num:	Block device number (struct blk_desc->dev value)
- * @hwpart:	Hardware partition number to select. 0 means the raw device,
- *		1 is the first partition, 2 is the second, etc.
- * @return 0 if OK, other value for an error
- */
-int mmc_select_hwpart(int dev_num, int hwpart);
 struct blk_desc *mg_disk_get_dev(int dev);
 int host_get_dev_err(int dev, struct blk_desc **blk_devp);
 
@@ -167,7 +150,6 @@ extern const struct block_drvr block_drvr[];
 #else
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
-static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
 
 static inline int part_get_info(struct blk_desc *dev_desc, int part,
-- 
cgit v0.10.2


From f376a3cbbf34d3114d92789540ba2d2e9e904758 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:42 -0600
Subject: dm: mmc: sandbox: Add an SD-card emulation

Add an emulation of an SD card to sandbox, allowing MMC to be used in tests.
The emulation is very simple, supporting only card detection and reading
test data.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 4d3df11..c80efc3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -2,7 +2,7 @@ menu "MMC Host controller Support"
 
 config MMC
 	bool "Enable MMC support"
-	depends on ARCH_SUNXI
+	depends on ARCH_SUNXI || SANDBOX
 	help
 	  TODO: Move all architectures to use this option
 
@@ -58,4 +58,13 @@ config MMC_UNIPHIER
 	help
 	  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
+config SANDBOX_MMC
+	bool "Sandbox MMC support"
+	depends on MMC && SANDBOX
+	help
+	  This select a dummy sandbox MMC driver. At present this does nothing
+	  other than allow sandbox to be build with MMC support. This
+	  improves build coverage for sandbox and makes it easier to detect
+	  MMC build errors with sandbox.
+
 endmenu
diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c
index f4646a8..7da059c 100644
--- a/drivers/mmc/sandbox_mmc.c
+++ b/drivers/mmc/sandbox_mmc.c
@@ -8,18 +8,150 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <fdtdec.h>
 #include <mmc.h>
 #include <asm/test.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct sandbox_mmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+/**
+ * sandbox_mmc_send_cmd() - Emulate SD commands
+ *
+ * This emulate an SD card version 2. Single-block reads result in zero data.
+ * Multiple-block reads return a test string.
+ */
+static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+				struct mmc_data *data)
+{
+	switch (cmd->cmdidx) {
+	case MMC_CMD_ALL_SEND_CID:
+		break;
+	case SD_CMD_SEND_RELATIVE_ADDR:
+		cmd->response[0] = 0 << 16; /* mmc->rca */
+	case MMC_CMD_GO_IDLE_STATE:
+		break;
+	case SD_CMD_SEND_IF_COND:
+		cmd->response[0] = 0xaa;
+		break;
+	case MMC_CMD_SEND_STATUS:
+		cmd->response[0] = MMC_STATUS_RDY_FOR_DATA;
+		break;
+	case MMC_CMD_SELECT_CARD:
+		break;
+	case MMC_CMD_SEND_CSD:
+		cmd->response[0] = 0;
+		cmd->response[1] = 10 << 16;	/* 1 << block_len */
+		break;
+	case SD_CMD_SWITCH_FUNC: {
+		u32 *resp = (u32 *)data->dest;
+
+		resp[7] = cpu_to_be32(SD_HIGHSPEED_BUSY);
+		break;
+	}
+	case MMC_CMD_READ_SINGLE_BLOCK:
+		memset(data->dest, '\0', data->blocksize);
+		break;
+	case MMC_CMD_READ_MULTIPLE_BLOCK:
+		strcpy(data->dest, "this is a test");
+		break;
+	case MMC_CMD_STOP_TRANSMISSION:
+		break;
+	case SD_CMD_APP_SEND_OP_COND:
+		cmd->response[0] = OCR_BUSY | OCR_HCS;
+		cmd->response[1] = 0;
+		cmd->response[2] = 0;
+		break;
+	case MMC_CMD_APP_CMD:
+		break;
+	case MMC_CMD_SET_BLOCKLEN:
+		debug("block len %d\n", cmd->cmdarg);
+		break;
+	case SD_CMD_APP_SEND_SCR: {
+		u32 *scr = (u32 *)data->dest;
+
+		scr[0] = cpu_to_be32(2 << 24 | 1 << 15);  /* SD version 3 */
+		break;
+	}
+	default:
+		debug("%s: Unknown command %d\n", __func__, cmd->cmdidx);
+		break;
+	}
+
+	return 0;
+}
+
+static void sandbox_mmc_set_ios(struct mmc *mmc)
+{
+}
+
+static int sandbox_mmc_init(struct mmc *mmc)
+{
+	return 0;
+}
+
+static int sandbox_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+static const struct mmc_ops sandbox_mmc_ops = {
+	.send_cmd = sandbox_mmc_send_cmd,
+	.set_ios = sandbox_mmc_set_ios,
+	.init = sandbox_mmc_init,
+	.getcd = sandbox_mmc_getcd,
+};
+
+int sandbox_mmc_probe(struct udevice *dev)
+{
+	struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+
+	return mmc_init(&plat->mmc);
+}
+
+int sandbox_mmc_bind(struct udevice *dev)
+{
+	struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+	struct mmc_config *cfg = &plat->cfg;
+	int ret;
+
+	cfg->name = dev->name;
+	cfg->ops = &sandbox_mmc_ops;
+	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
+	cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+	cfg->f_min = 1000000;
+	cfg->f_max = 52000000;
+	cfg->b_max = U32_MAX;
+
+	ret = mmc_bind(dev, &plat->mmc, cfg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int sandbox_mmc_unbind(struct udevice *dev)
+{
+	mmc_unbind(dev);
+
+	return 0;
+}
+
 static const struct udevice_id sandbox_mmc_ids[] = {
 	{ .compatible = "sandbox,mmc" },
 	{ }
 };
 
-U_BOOT_DRIVER(warm_mmc_sandbox) = {
+U_BOOT_DRIVER(mmc_sandbox) = {
 	.name		= "mmc_sandbox",
 	.id		= UCLASS_MMC,
 	.of_match	= sandbox_mmc_ids,
+	.bind		= sandbox_mmc_bind,
+	.unbind		= sandbox_mmc_unbind,
+	.probe		= sandbox_mmc_probe,
+	.platdata_auto_alloc_size = sizeof(struct sandbox_mmc_plat),
 };
-- 
cgit v0.10.2


From afa2c3122db1ef5243e717b84d698353da412d92 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:43 -0600
Subject: dm: sandbox: mmc: Enable building MMC code for sandbox

Enable building the MMC code for sandbox. This increases build
coverage for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index afdf4a3..aec2e53 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
 CONFIG_I8042_KEYB=y
@@ -97,6 +98,7 @@ CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
+CONFIG_SANDBOX_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index c51d4cd..23a0c40 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -215,4 +215,6 @@
 #define CONFIG_SYS_SYSTEMACE_WIDTH	16
 #define CONFIG_SYS_SYSTEMACE_BASE	0
 
+#define CONFIG_GENERIC_MMC
+
 #endif
diff --git a/test/dm/blk.c b/test/dm/blk.c
index f4ea32e..012bf4c 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -83,12 +83,12 @@ static int dm_test_blk_usb(struct unit_test_state *uts)
 	ut_asserteq_ptr(usb_dev, dev_get_parent(dev));
 
 	/* Check we have one block device for each mass storage device */
-	ut_asserteq(3, count_blk_devices());
+	ut_asserteq(4, count_blk_devices());
 
 	/* Now go around again, making sure the old devices were unbound */
 	ut_assertok(usb_stop());
 	ut_assertok(usb_init());
-	ut_asserteq(3, count_blk_devices());
+	ut_asserteq(4, count_blk_devices());
 	ut_assertok(usb_stop());
 
 	return 0;
-- 
cgit v0.10.2


From 341392dd115f1385c31bb0b034ec15f542730e30 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:52:44 -0600
Subject: dm: mmc: test: Add tests for MMC

Add a simple test which checks that a sandbox-emulated SD card can be used
correctly. This tests plumbing through the MMC stack's block-device
implementaion.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/dm/Makefile b/test/dm/Makefile
index 8ec391b..9a11ae0 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,9 +21,7 @@ obj-$(CONFIG_DM_ETH) += eth.o
 obj-$(CONFIG_DM_GPIO) += gpio.o
 obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_LED) += led.o
-
-# Disable temporarily
-# obj-$(CONFIG_DM_MMC) += mmc.o
+obj-$(CONFIG_DM_MMC) += mmc.o
 obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
diff --git a/test/dm/mmc.c b/test/dm/mmc.c
index 0461423..5bca4b7 100644
--- a/test/dm/mmc.c
+++ b/test/dm/mmc.c
@@ -25,3 +25,22 @@ static int dm_test_mmc_base(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_mmc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_mmc_blk(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	struct blk_desc *dev_desc;
+	char cmp[1024];
+
+	ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
+	ut_assertok(blk_get_device_by_str("mmc", "0", &dev_desc));
+
+	/* Read a few blocks and look for the string we expect */
+	ut_asserteq(512, dev_desc->blksz);
+	memset(cmp, '\0', sizeof(cmp));
+	ut_asserteq(2, blk_dread(dev_desc, 0, 2, cmp));
+	ut_assertok(strcmp(cmp, "this is a test"));
+
+	return 0;
+}
+DM_TEST(dm_test_mmc_blk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-- 
cgit v0.10.2


From 074596c0b5f4e9a3642a3159a9fc7f8b8064c18a Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Thu, 7 Apr 2016 16:22:21 +0800
Subject: armv8/ls1043: Add workaround for DDR erratum A-008850

Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0cb0100..0fb5c7f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,8 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
@@ -271,6 +273,39 @@ static void erratum_a009660(void)
 #endif
 }
 
+static void erratum_a008850_early(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+	/* part 1 of 2 */
+	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	/* disables propagation of barrier transactions to DDRC from CCI400 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+	/* disable the re-ordering in DDRC */
+	ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+#endif
+}
+
+void erratum_a008850_post(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+	/* part 2 of 2 */
+	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 tmp;
+
+	/* enable propagation of barrier transactions to DDRC from CCI400 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+	/* enable the re-ordering in DDRC */
+	tmp = ddr_in32(&ddr->eor);
+	tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+	ddr_out32(&ddr->eor, tmp);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -295,6 +330,7 @@ void fsl_lsch2_early_init_f(void)
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
 	/* Erratum */
+	erratum_a008850_early(); /* part 1 of 2 */
 	erratum_a009929();
 	erratum_a009660();
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 10d17b2..a24dc28 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -191,6 +191,7 @@
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 
+#define CONFIG_SYS_FSL_ERRATUM_A008850
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 3d3c533..0fd835d 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -116,6 +116,7 @@ phys_size_t initdram(int board_type)
 
 	dram_size = fsl_ddr_sdram();
 #endif
+	erratum_a008850_post();
 
 #ifdef CONFIG_FSL_DEEP_SLEEP
 	fsl_dp_ddr_restore();
diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index 8adb660..d3f4082 100644
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -7,6 +7,8 @@
 #ifndef __DDR_H__
 #define __DDR_H__
 
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index fba6b88..fc097d9 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -307,14 +307,6 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-				   CONFIG_SYS_CCI400_ADDR;
-
-	/* Set CCI-400 control override register to enable barrier
-	 * transaction */
-	out_le32(&cci->ctrl_ord,
-		 CCI400_CTRLORD_EN_BARRIER);
-
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	board_retimer_init();
 
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 11bc0f2..1e2fd2e 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -177,6 +177,8 @@ phys_size_t initdram(int board_type)
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	erratum_a008850_post();
+
 #ifdef CONFIG_FSL_DEEP_SLEEP
 	fsl_dp_ddr_restore();
 #endif
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index b17eb80..8ca166b 100644
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -6,6 +6,9 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbf..8d80135 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -83,14 +83,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
-	/*
-	 * Set CCI-400 control override register to enable barrier
-	 * transaction
-	 */
-	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-
 #ifdef CONFIG_FSL_IFC
 	init_final_memctl_regs();
 #endif
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index cf316a4..44ae7fb 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define WR_DATA_DELAY_SHIFT	10
 #endif
 
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS	0x07000000
+#define DDR_EOR_WD_REOD_DIS	0x00100000
+
 /* DDR_MD_CNTL */
 #define MD_CNTL_MD_EN		0x80000000
 #define MD_CNTL_CS_SEL_CS0	0x00000000
-- 
cgit v0.10.2


From 4a68489e12313a7fa8740463dee0eea2985eb563 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Wed, 16 Mar 2016 13:50:22 +0800
Subject: drivers/ddr/fsl: update workaround for erratum A-008511

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 608810d..7cdb700 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -240,8 +240,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		/* Disable DRAM VRef training */
 		ddr_out32(&ddr->ddr_cdr2,
 			  regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
-		/* Disable deskew */
-		ddr_out32(&ddr->debug[28], 0x400);
+		/* disable transmit bit deskew */
+		temp32 = ddr_in32(&ddr->debug[28]);
+		temp32 |= DDR_TX_BD_DIS;
+		ddr_out32(&ddr->debug[28], temp32);
 		/* Disable D_INIT */
 		ddr_out32(&ddr->sdram_cfg_2,
 			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
@@ -358,7 +360,9 @@ step2:
 			debug("MR6 = 0x%08x\n", temp32);
 		}
 		ddr_out32(&ddr->sdram_md_cntl, 0);
-		ddr_out32(&ddr->debug[28], 0);		/* Enable deskew */
+		temp32 = ddr_in32(&ddr->debug[28]);
+		temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
+		ddr_out32(&ddr->debug[28], temp32);
 		ddr_out32(&ddr->debug[1], 0x400);	/* restart deskew */
 		/* wait for idle */
 		timeout = 40;
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 44ae7fb..acddf14 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -189,6 +189,9 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_MR5_CA_PARITY_LAT_4_CLK	0x1 /* for DDR4-1600/1866/2133 */
 #define DDR_MR5_CA_PARITY_LAT_5_CLK	0x2 /* for DDR4-2400 */
 
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS	(1 << 10) /* Transmit Bit Deskew Disable */
+
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
-- 
cgit v0.10.2


From 5fc62fe57097e195a8047859cd3c278a5d6790b6 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Wed, 16 Mar 2016 13:50:23 +0800
Subject: driver/ddr/fsl: Add workaround for erratum A-009801

The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index a24dc28..6529281 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -134,6 +134,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 #define CONFIG_SYS_FSL_ERRATUM_A009635
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009801
 #define CONFIG_SYS_FSL_ERRATUM_A009803
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 7cdb700..1dc0631 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	}
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
+	temp32 = ddr_in32(&ddr->debug[25]);
+	temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
+	temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
+	ddr_out32(&ddr->debug[25], temp32);
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 	tmp = ddr_in32(&ddr->debug[28]);
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index acddf14..486e47e 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_MR5_CA_PARITY_LAT_4_CLK	0x1 /* for DDR4-1600/1866/2133 */
 #define DDR_MR5_CA_PARITY_LAT_5_CLK	0x2 /* for DDR4-2400 */
 
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
 /* DEBUG_29 register */
 #define DDR_TX_BD_DIS	(1 << 10) /* Transmit Bit Deskew Disable */
 
-- 
cgit v0.10.2


From aa7a2226b5a7829915d189d727ee9320dc3a198b Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Thu, 7 Apr 2016 14:41:30 +0800
Subject: armv8/ls2080ardb: Update DDR timing to support more UDIMMs

Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.

Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
 - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
 - Apacer UDIMM: 78.C1GM4.AF10B
 - Transcend UDIMM: TS1GLH72V1H

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a..b3c6306 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -29,9 +29,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
 	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     8, 0x08090B0D, 0x0E10100C,},
-	{2,  1900, 0, 4,     8, 0x090A0C0E, 0x1012120D,},
-	{2,  2300, 0, 4,     9, 0x0A0B0C10, 0x1114140E,},
+	{2,  1666, 0, 5,     9, 0x090A0B0E, 0x0F11110C,},
+	{2,  1900, 0, 6,   0xA, 0x0B0C0E11, 0x1214140F,},
+	{2,  2300, 0, 6,   0xB, 0x0C0D0F12, 0x14161610,},
 	{}
 };
 
-- 
cgit v0.10.2


From 6f3819fe30763bd0d0515997eb4d4fece06abb56 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Sun, 10 Apr 2016 20:26:22 +0530
Subject: armv8: ls2080a: Update MAINTAINERS file

Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 7d3bfc8..0765326 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
 F:	board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 5562917..a20c003 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080ardb/
 F:	board/freescale/ls2080a/ls2080ardb.c
-- 
cgit v0.10.2


From f13c99c2a265d0586702523fab56a3562de31f86 Mon Sep 17 00:00:00 2001
From: Alex Porosanu <alexandru.porosanu@nxp.com>
Date: Mon, 11 Apr 2016 10:42:50 +0300
Subject: armv8/fdt: add fixup_crypto_node

For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in
order to update the SEC internal version (aka SEC ERA). This patch
adds the same functionality to the ARMv8 SoCs.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1e875c4..d17227a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -20,6 +20,8 @@
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
+#include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/soc.h>
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -75,6 +77,23 @@ void ft_fixup_cpu(void *blob)
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_LSCH2
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	unsigned int svr = in_be32(&gur->svr);
+
+	/* delete crypto node if not on an E-processor */
+	if (!IS_E_PROCESSOR(svr))
+		fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+	else {
+		ccsr_sec_t __iomem *sec;
+
+		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+	}
+#endif
+#endif
+
 #ifdef CONFIG_MP
 	ft_fixup_cpu(blob);
 #endif
-- 
cgit v0.10.2


From d15a244b059e361475302bccd471e65a48ee2b1f Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 3 May 2016 11:13:04 +0800
Subject: imx: correct speed grading info for i.MX6UL

Correct speed grading info for i.MX6UL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index d4b22ad..aaa1adb 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -108,6 +108,12 @@ u32 get_cpu_rev(void)
 #define OCOTP_CFG3_SPEED_1GHZ	2
 #define OCOTP_CFG3_SPEED_1P2GHZ	3
 
+/*
+ * For i.MX6UL
+ */
+#define OCOTP_CFG3_SPEED_528MHZ 1
+#define OCOTP_CFG3_SPEED_696MHZ 2
+
 u32 get_cpu_speed_grade_hz(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -120,6 +126,15 @@ u32 get_cpu_speed_grade_hz(void)
 	val >>= OCOTP_CFG3_SPEED_SHIFT;
 	val &= 0x3;
 
+	if (is_cpu_type(MXC_CPU_MX6UL)) {
+		if (val == OCOTP_CFG3_SPEED_528MHZ)
+			return 528000000;
+		else if (val == OCOTP_CFG3_SPEED_696MHZ)
+			return 69600000;
+		else
+			return 0;
+	}
+
 	switch (val) {
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_1P2GHZ:
-- 
cgit v0.10.2


From bf9bffa9784411ba743b127adc031bcb6e27735d Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Tue, 15 Mar 2016 14:36:40 +0800
Subject: spi: fsl_qspi: Fix issues on arm64

The address value and size value get from dts "reg" property have
type of u64 on arm64. If we assign those values to "u32" variables,
driver can't work correctly. Converting the type of those variables
to fdt_xxx_t.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index cb8d929..96fb909 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -92,9 +92,9 @@ DECLARE_GLOBAL_DATA_PTR;
 struct fsl_qspi_platdata {
 	u32 flags;
 	u32 speed_hz;
-	u32 reg_base;
-	u32 amba_base;
-	u32 amba_total_size;
+	fdt_addr_t reg_base;
+	fdt_addr_t amba_base;
+	fdt_size_t amba_total_size;
 	u32 flash_num;
 	u32 num_chipselect;
 };
@@ -940,8 +940,13 @@ static int fsl_qspi_probe(struct udevice *bus)
 	priv->flags = plat->flags;
 
 	priv->speed_hz = plat->speed_hz;
-	priv->amba_base[0] = plat->amba_base;
-	priv->amba_total_size = plat->amba_total_size;
+	/*
+	 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
+	 * AMBA memory zone should be located on the 0~4GB space
+	 * even on a 64bits cpu.
+	 */
+	priv->amba_base[0] = (u32)plat->amba_base;
+	priv->amba_total_size = (u32)plat->amba_total_size;
 	priv->flash_num = plat->flash_num;
 	priv->num_chipselect = plat->num_chipselect;
 
@@ -984,10 +989,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-	struct reg_data {
-		u32 addr;
-		u32 size;
-	} regs_data[2];
+	struct fdt_resource res_regs, res_mem;
 	struct fsl_qspi_platdata *plat = bus->platdata;
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;
@@ -996,10 +998,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 	if (fdtdec_get_bool(blob, node, "big-endian"))
 		plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 
-	ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
-				   sizeof(regs_data)/sizeof(u32));
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "QuadSPI", &res_regs);
+	if (ret) {
+		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+		return -ENOMEM;
+	}
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "QuadSPI-memory", &res_mem);
 	if (ret) {
-		debug("Error: can't get base addresses (ret = %d)!\n", ret);
+		debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
 
@@ -1017,16 +1025,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
 					      FSL_QSPI_MAX_CHIPSELECT_NUM);
 
-	plat->reg_base = regs_data[0].addr;
-	plat->amba_base = regs_data[1].addr;
-	plat->amba_total_size = regs_data[1].size;
+	plat->reg_base = res_regs.start;
+	plat->amba_base = res_mem.start;
+	plat->amba_total_size = res_mem.end - res_mem.start + 1;
 	plat->flash_num = flash_num;
 
-	debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
+	debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
 	      __func__,
-	      plat->reg_base,
-	      plat->amba_base,
-	      plat->amba_total_size,
+	      (u64)plat->reg_base,
+	      (u64)plat->amba_base,
+	      (u64)plat->amba_total_size,
 	      plat->speed_hz,
 	      plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
 	      );
-- 
cgit v0.10.2


From 4e14741833607f49eaccdfd4add9cb39e103c2db Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Tue, 15 Mar 2016 14:36:41 +0800
Subject: spi: fsl_qspi: Assign AMBA mem according CS num in dts

QSPI controller automatic enable the chipselect signal according the
dest AMBA memory address. Now we distribute the AMBA memory zone
averagely to every chipselect slave device according chipselect
numbers got from dts node.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 96fb909..db7ebee 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -927,10 +927,11 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev)
 
 static int fsl_qspi_probe(struct udevice *bus)
 {
-	u32 total_size;
+	u32 amba_size_per_chip;
 	struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 	struct fsl_qspi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_bus *dm_spi_bus;
+	int i;
 
 	dm_spi_bus = bus->uclass_priv;
 
@@ -956,7 +957,22 @@ static int fsl_qspi_probe(struct udevice *bus)
 	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 		QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 
-	total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
+	/*
+	 * Assign AMBA memory zone for every chipselect
+	 * QuadSPI has two channels, every channel has two chipselects.
+	 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
+	 * into two parts and assign to every channel. This indicate that every
+	 * channel only has one valid chipselect.
+	 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
+	 * into four parts and assign to every chipselect.
+	 * Every channel will has two valid chipselects.
+	 */
+	amba_size_per_chip = priv->amba_total_size >>
+			     (priv->num_chipselect >> 1);
+	for (i = 1 ; i < priv->num_chipselect ; i++)
+		priv->amba_base[i] =
+			amba_size_per_chip + priv->amba_base[i - 1];
+
 	/*
 	 * Any read access to non-implemented addresses will provide
 	 * undefined results.
@@ -967,14 +983,30 @@ static int fsl_qspi_probe(struct udevice *bus)
 	 * setting the size of these devices to 0.  This would ensure
 	 * that the complete memory map is assigned to only one flash device.
 	 */
-	qspi_write32(priv->flags, &priv->regs->sfa1ad,
-		     FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfa2ad,
-		     FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfb1ad,
-		     total_size | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfb2ad,
-		     total_size | priv->amba_base[0]);
+	qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
+	switch (priv->num_chipselect) {
+	case 2:
+		qspi_write32(priv->flags, &priv->regs->sfa2ad,
+			     priv->amba_base[1]);
+		qspi_write32(priv->flags, &priv->regs->sfb1ad,
+			     priv->amba_base[1] + amba_size_per_chip);
+		qspi_write32(priv->flags, &priv->regs->sfb2ad,
+			     priv->amba_base[1] + amba_size_per_chip);
+		break;
+	case 4:
+		qspi_write32(priv->flags, &priv->regs->sfa2ad,
+			     priv->amba_base[2]);
+		qspi_write32(priv->flags, &priv->regs->sfb1ad,
+			     priv->amba_base[3]);
+		qspi_write32(priv->flags, &priv->regs->sfb2ad,
+			     priv->amba_base[3] + amba_size_per_chip);
+		break;
+	default:
+		debug("Error: Unsupported chipselect number %u!\n",
+		      priv->num_chipselect);
+		qspi_module_disable(priv, 1);
+		return -EINVAL;
+	}
 
 	qspi_set_lut(priv);
 
@@ -1063,8 +1095,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
 	bus = dev->parent;
 	priv = dev_get_priv(bus);
 
-	priv->cur_amba_base =
-		priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
+	priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
 	qspi_module_disable(priv, 0);
 
-- 
cgit v0.10.2


From febffe8dd1c7ba841890eec578b050bb6faa3273 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Tue, 15 Mar 2016 14:36:42 +0800
Subject: spi: fsl_qspi: Enable Spansion S25FS-S family flashes

The flash type of LS2085AQDS QSPI is S25FS256S. It has special write
any device register command and read any device register command.
This patch enable support for those commands.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 007a5a0..da2bb7b 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -127,6 +127,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
 		const void *buf);
 #endif
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+/* Used for Spansion S25FS-S family flash only. */
+#define CMD_SPANSION_RDAR	0x65 /* Read any device register */
+#define CMD_SPANSION_WRAR	0x71 /* Write any device register */
+#endif
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index db7ebee..75cbab2 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -44,6 +44,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SEQID_RDEAR		11
 #define SEQID_WREAR		12
 #endif
+#define SEQID_WRAR		13
+#define SEQID_RDAR		14
 
 /* QSPI CMD */
 #define QSPI_CMD_PP		0x02	/* Page program (up to 256 bytes) */
@@ -63,6 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	QSPI_CMD_BRRD		0x16	/* Bank register read */
 #define	QSPI_CMD_BRWR		0x17	/* Bank register write */
 
+/* Used for Spansion S25FS-S family flash only. */
+#define QSPI_CMD_RDAR		0x65	/* Read any device register */
+#define QSPI_CMD_WRAR		0x71	/* Write any device register */
+
 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
 #define QSPI_CMD_FAST_READ_4B	0x0c    /* Read data bytes (high frequency) */
 #define QSPI_CMD_PP_4B		0x12    /* Page program (up to 256 bytes) */
@@ -317,6 +323,33 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 		     PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 #endif
+
+	/*
+	 * Read any device register.
+	 * Used for Spansion S25FS-S family flash only.
+	 */
+	lut_base = SEQID_RDAR * 4;
+	qspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
+		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
+		     OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+		     OPRND1(1) | PAD1(LUT_PAD1) |
+		     INSTR1(LUT_READ));
+
+	/*
+	 * Write any device register.
+	 * Used for Spansion S25FS-S family flash only.
+	 */
+	lut_base = SEQID_WRAR * 4;
+	qspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
+		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
+		     OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+
 	/* Lock the LUT */
 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
@@ -510,7 +543,6 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
 
-#ifndef CONFIG_SYS_FSL_QSPI_AHB
 /* If not use AHB read, read data from ip interface */
 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 {
@@ -518,6 +550,12 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 	u32 mcr_reg, data;
 	int i, size;
 	u32 to_or_from;
+	u32 seqid;
+
+	if (priv->cur_seqid == QSPI_CMD_RDAR)
+		seqid = SEQID_RDAR;
+	else
+		seqid = SEQID_FAST_READ;
 
 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 	qspi_write32(priv->flags, &regs->mcr,
@@ -536,7 +574,7 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 			RX_BUFFER_SIZE : len;
 
 		qspi_write32(priv->flags, &regs->ipcr,
-			     (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) |
+			     (seqid << QSPI_IPCR_SEQID_SHIFT) |
 			     size);
 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 			;
@@ -548,7 +586,10 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 		while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 			data = qspi_read32(priv->flags, &regs->rbdr[i]);
 			data = qspi_endian_xchg(data);
-			memcpy(rxbuf, &data, 4);
+			if (size < 4)
+				memcpy(rxbuf, &data, size);
+			else
+				memcpy(rxbuf, &data, 4);
 			rxbuf++;
 			size -= 4;
 			i++;
@@ -560,7 +601,6 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 
 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
-#endif
 
 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 {
@@ -601,6 +641,8 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 
 	/* Default is page programming */
 	seqid = SEQID_PP;
+	if (priv->cur_seqid == QSPI_CMD_WRAR)
+		seqid = SEQID_WRAR;
 #ifdef CONFIG_SPI_FLASH_BAR
 	if (priv->cur_seqid == QSPI_CMD_BRWR)
 		seqid = SEQID_BRWR;
@@ -725,13 +767,15 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 			return 0;
 		}
 
-		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
+		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
+		    priv->cur_seqid == QSPI_CMD_RDAR) {
 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 			qspi_op_erase(priv);
-		} else if (priv->cur_seqid == QSPI_CMD_PP) {
+		} else if (priv->cur_seqid == QSPI_CMD_PP ||
+			   priv->cur_seqid == QSPI_CMD_WRAR) {
 			wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 			 (priv->cur_seqid == QSPI_CMD_WREAR)) {
@@ -748,6 +792,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 #else
 			qspi_op_read(priv, din, bytes);
 #endif
+		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {
+			qspi_op_read(priv, din, bytes);
 		} else if (priv->cur_seqid == QSPI_CMD_RDID)
 			qspi_op_rdid(priv, din, bytes);
 		else if (priv->cur_seqid == QSPI_CMD_RDSR)
-- 
cgit v0.10.2


From 80c1bfd2332e71dfe669cac53ba06b7435a7ca39 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Tue, 15 Mar 2016 14:36:43 +0800
Subject: sf: Disable 4-KB erase command for SPANSION S25FS-S family

The S25FS-S family physical sectors may be configured as a hybrid
combination of eight 4-kB parameter sectors at the top or bottom
of the address space with all but one of the remaining sectors
being uniform size.
The default status of the flash is in this hybrid architecture.
The parameter sectors and the uniform sectors have different erase
commands.
This patch disable the hybrid sector architecture then the flash will
has uniform sector size and uniform erase command.
This configuration is temporary, the flash will revert to hybrid
architecture after power on reset.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5451725..fa0e799 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -971,6 +971,43 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 }
 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+{
+	u8 cmd[4];
+	u32 offset = 0x800004; /* CR3V register offset */
+	u8 cr3v;
+	int ret;
+
+	cmd[0] = CMD_SPANSION_RDAR;
+	cmd[1] = offset >> 16;
+	cmd[2] = offset >> 8;
+	cmd[3] = offset >> 0;
+
+	ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+	/* CR3V bit3: 4-KB Erase */
+	if (cr3v & 0x8)
+		return 0;
+
+	cmd[0] = CMD_SPANSION_WRAR;
+	cr3v |= 0x8;
+	ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+
+	cmd[0] = CMD_SPANSION_RDAR;
+	ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+	if (!(cr3v & 0x8))
+		return -EFAULT;
+
+	return 0;
+}
+#endif
+
 int spi_flash_scan(struct spi_flash *flash)
 {
 	struct spi_slave *spi = flash->spi;
@@ -1021,6 +1058,41 @@ int spi_flash_scan(struct spi_flash *flash)
 		return -EPROTONOSUPPORT;
 	}
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+	/*
+	 * The S25FS-S family physical sectors may be configured as a
+	 * hybrid combination of eight 4-kB parameter sectors
+	 * at the top or bottom of the address space with all
+	 * but one of the remaining sectors being uniform size.
+	 * The Parameter Sector Erase commands (20h or 21h) must
+	 * be used to erase the 4-kB parameter sectors individually.
+	 * The Sector (uniform sector) Erase commands (D8h or DCh)
+	 * must be used to erase any of the remaining
+	 * sectors, including the portion of highest or lowest address
+	 * sector that is not overlaid by the parameter sectors.
+	 * The uniform sector erase command has no effect on parameter sectors.
+	 */
+	if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+		int ret;
+		u8 id[6];
+
+		/* Read the ID codes again, 6 bytes */
+		ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+		if (ret)
+			return -EIO;
+
+		ret = memcmp(id, idcode, 5);
+		if (ret)
+			return -EIO;
+
+		/* 0x81: S25FS-S family 0x80: S25FL-S family */
+		if (id[5] == 0x81) {
+			ret = spansion_s25fss_disable_4KB_erase(spi);
+			if (ret)
+				return ret;
+		}
+	}
+#endif
 	/* Flash powers up read-only, so clear BP# bits */
 	if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
 	    idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
-- 
cgit v0.10.2


From 87e566d77347173cc901e5c9cd325c5d83f65f7e Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Tue, 15 Mar 2016 14:36:44 +0800
Subject: armv8/ls1043a: update the node for QSPI support

The address value and size value set for QSPI dts node "reg"
property have type of u64 on arm64.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 66b409a..bf1dfe6 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -240,8 +240,9 @@
 			compatible = "fsl,vf610-qspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0x1550000 0x10000>,
-				<0x40000000 0x4000000>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
 			num-cs = <2>;
 			big-endian;
 			status = "disabled";
-- 
cgit v0.10.2


From bcb55f67f22b297d6c10e039bfcef9847a20fbfb Mon Sep 17 00:00:00 2001
From: Aneesh Bansal <aneesh.bansal@nxp.com>
Date: Wed, 6 Apr 2016 22:25:51 +0530
Subject: armv8: ls2080: enable sec_init in U-Boot

Define CONFIG_FSL_CAAM for LS2080 which would enable
call to sec_init() during U-Boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index a3aad1b..c78aeb5 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -26,6 +26,8 @@
 /* We need architecture specific misc initializations */
 #define CONFIG_ARCH_MISC_INIT
 
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+
 /* Link Definitions */
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE		0x80400000
@@ -292,4 +294,10 @@ unsigned long long get_qixis_addr(void);
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 #endif /* __LS2_COMMON_H */
-- 
cgit v0.10.2


From 7ad9cc969b00cd5e238f4a194f0e974d74706b8e Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Tue, 19 Apr 2016 08:53:42 +0530
Subject: armv8: ls2080a: update eth prime

As per new PHY framework, DPNI naming convetion is no more used.
Use new naming convention.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 2d7567f..16a536a 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -374,7 +374,7 @@ unsigned long get_board_ddr_clk(void);
 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 
 #define CONFIG_MII		/* MII PHY management */
-#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 
 #endif
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 5bec509..45827f6 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -366,7 +366,7 @@ unsigned long get_board_sys_clk(void);
 #define AQR405_IRQ_MASK		0x36
 
 #define CONFIG_MII
-#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHY_AQUANTIA
 #endif
-- 
cgit v0.10.2


From acb8f5e914814ac6c697edb86701958da251a223 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Fri, 22 Apr 2016 10:37:25 +0800
Subject: armv8: fsl-layerscape: Remove unnecessary flushing dcache

As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit 70e21b064, the
workaround to flush dcache is unnecessary and should be removed.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d939900..9a5a6b5 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -396,9 +396,6 @@ static inline void final_mmu_setup(void)
 	flush_dcache_range((ulong)level0_table,
 			   (ulong)level0_table + gd->arch.tlb_size);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-	flush_dcache_all();
-#endif
 	/* point TTBR to the new table */
 	set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
 			  MEMORY_ATTRIBUTES);
-- 
cgit v0.10.2


From 15b96ad8318d8670d3a776e72dbf8edaca74e4a7 Mon Sep 17 00:00:00 2001
From: Vincent Siles <vincent.siles@provenrun.com>
Date: Fri, 22 Apr 2016 09:52:06 +0200
Subject: arm: Fix SCFG ICID reg addresses

On the LS102x boards, in order to initialize the ICID values of
masters, the dev_stream_id array holds absolute offsets from the
base of SCFG.

In ls102xa_config_ssmu_stream_id, the base pointer is cast to
uint32_t * before adding the offset, leading to an invalid address.
Casting it to void * solves the issue.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index f434269..39e7b30 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -10,11 +10,11 @@
 
 void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
 {
-	uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+	void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int i;
 
 	for (i = 0; i < num; i++)
-		out_be32(scfg + id[i].offset, id[i].stream_id);
+		out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
 }
 
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
-- 
cgit v0.10.2


From 12cbf20d78f93c86e287d86ff863926e5cde9355 Mon Sep 17 00:00:00 2001
From: Vincent Siles <vincent.siles@provenrun.com>
Date: Fri, 22 Apr 2016 09:52:07 +0200
Subject: arm: uniform usage of u32 in ls102x caam config

Mix usage of uint32_t and u32 fixed in favor of u32.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index 39e7b30..3d5404e 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -28,6 +28,6 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
 		else
 			liodn = tbl[i].id[0];
 
-		out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
+		out_le32((u32 *)(tbl[i].reg_offset), liodn);
 	}
 }
-- 
cgit v0.10.2


From 869bf86811a7c942dc48b294d5c0442b1f57ab53 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Mon, 25 Apr 2016 16:38:35 +0800
Subject: armv8/ls1043ardb: fix the limitation of using 'cpld reset'

The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 78c2824..c645283 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
 /* Set the boot bank to the alternate bank */
 void cpld_set_altbank(void)
 {
+	u16 reg = CPLD_CFG_RCW_SRC_NOR;
 	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
 	u8 reg7 = CPLD_READ(vbank);
 
-	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
 
 	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
 	CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
 /* Set the boot bank to the default bank */
 void cpld_set_defbank(void)
 {
-	CPLD_WRITE(global_rst, 1);
+	u16 reg = CPLD_CFG_RCW_SRC_NOR;
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(vbank, 0);
+
+	CPLD_WRITE(system_rst, 1);
 }
 
 void cpld_set_nand(void)
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index bd59c0e..cb175b5 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL	0x40
 #define CPLD_BANK_SEL_MASK	0x07
 #define CPLD_BANK_SEL_ALTBANK	0x04
+#define CPLD_CFG_RCW_SRC_NOR	0x025
 #define CPLD_CFG_RCW_SRC_NAND	0x106
 #define CPLD_CFG_RCW_SRC_SD	0x040
 #endif
-- 
cgit v0.10.2


From 1297cdb452fcdc6e7149c6761e43629f9c732010 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Mon, 25 Apr 2016 16:53:53 +0800
Subject: armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled

IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS.
So this patch could fix 'sync abort' caused by autoboot that tries to
access IFC address.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 54968b5..a7d49ed 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -257,8 +257,13 @@
 
 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
 					"earlycon=uart8250,mmio,0x21c0500"
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
+					"e0000 f00000 && bootm $kernel_load"
+#else
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
+#endif
 #define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
-- 
cgit v0.10.2


From ec93abe6f722e6e0103f96ee01bcd376e246f111 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Tue, 26 Apr 2016 12:51:42 +0800
Subject: armv8: ls1043a: remove redundant code in board files

gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index fc097d9..ca393e8 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -317,10 +317,6 @@ int board_init(void)
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
 #endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
-	gd->env_addr = (ulong)&default_environment[0];
-#endif
 	return 0;
 }
 
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 8d80135..2ed5ce1 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -19,7 +19,6 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <environment.h>
 #include <fsl_sec.h>
 #include "cpld.h"
 #ifdef CONFIG_U_QE
@@ -87,10 +86,6 @@ int board_init(void)
 	init_final_memctl_regs();
 #endif
 
-#ifdef CONFIG_ENV_IS_NOWHERE
-	gd->env_addr = (ulong)&default_environment[0];
-#endif
-
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
 #endif
-- 
cgit v0.10.2


From 9718650f8c37fe53727bde26ffc0ecba814008b5 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Tue, 26 Apr 2016 12:51:43 +0800
Subject: armv8: ls1043ardb: fix types of variables

Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 2ed5ce1..b169139 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -30,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
-	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
 #ifndef CONFIG_SD_BOOT
 	u8 cfg_rcw_src1, cfg_rcw_src2;
-	u32 cfg_rcw_src;
+	u16 cfg_rcw_src;
 #endif
-	u32 sd1refclk_sel;
+	u8 sd1refclk_sel;
 
 	printf("Board: LS1043ARDB, boot from ");
 
-- 
cgit v0.10.2


From 1f49dc3e91c4d3a35fcddaf468bc1b615ced8a6b Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Wed, 27 Apr 2016 09:43:11 +0800
Subject: armv8: fsl-layerscape: spl: remove duplicate init_early_memctl_regs()

init_early_memctl_regs() is also be called in board_early_init_f().
So remove the duplicated call in spl code.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index c1229c8..4c8a9a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -49,9 +49,6 @@ void board_init_f(ulong dummy)
 #ifdef CONFIG_LS2080A
 	arch_cpu_init();
 #endif
-#ifdef CONFIG_FSL_IFC
-	init_early_memctl_regs();
-#endif
 	board_early_init_f();
 	timer_init();
 #ifdef CONFIG_LS2080A
-- 
cgit v0.10.2


From f504227c9630edd7f05530b3f4dd99155ac58591 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Wed, 27 Apr 2016 09:45:23 +0800
Subject: armv8: fsl-layerscape: spl: fix the macro name of MMC mode

MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 4c8a9a0..5883c00 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -29,7 +29,7 @@ u32 spl_boot_mode(void)
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 #else
 		return MMCSD_MODE_RAW;
 #endif
-- 
cgit v0.10.2


From 56747bfdbd6f2c5bc391d0c9d5eb20a6a2d50505 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Wed, 27 Apr 2016 09:44:51 +0800
Subject: armv7: ls102xa: spl: fix the macro name of MMC mode

MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 1dfbf54..0289058 100644
--- a/arch/arm/cpu/armv7/ls102xa/spl.c
+++ b/arch/arm/cpu/armv7/ls102xa/spl.c
@@ -20,7 +20,7 @@ u32 spl_boot_mode(void)
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 #else
 		return MMCSD_MODE_RAW;
 #endif
-- 
cgit v0.10.2


From e99d7193593cf6331ea04cd394a9a4cf18886ef0 Mon Sep 17 00:00:00 2001
From: Alex Porosanu <alexandru.porosanu@freescale.com>
Date: Fri, 29 Apr 2016 15:17:58 +0300
Subject: arch/arm: add SEC JR0 offset

Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 0bad0c7..57b99d4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -37,8 +37,6 @@
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
@@ -157,6 +155,13 @@ struct sys_info {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
 /* Device Configuration and Pin Control */
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b336..65b3357 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -77,8 +77,12 @@
 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_ADDR		(CONFIG_SYS_IMMR + 0x07000000)
-#define CONFIG_SYS_FSL_JR0_ADDR		(CONFIG_SYS_IMMR + 0x07010000)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 267bd17..92f30e2 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -40,6 +40,7 @@
 	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
 #define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3ab04bf..ac37e4f 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -227,8 +227,13 @@
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 
-#define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET   0
+#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a3106e7..74917f0 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -218,10 +218,13 @@
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR  + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET       0
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
+					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/imx-common/regs-lcdif.h>
 #include <asm/types.h>
-- 
cgit v0.10.2


From 404bf4547ecb4c1409ae0936444fe02ba978e510 Mon Sep 17 00:00:00 2001
From: Alex Porosanu <alexandru.porosanu@freescale.com>
Date: Fri, 29 Apr 2016 15:17:59 +0300
Subject: arch/arm, arch/powerpc: add # of SEC engines on the SOC

Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 6529281..34b1500 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -144,6 +144,7 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
@@ -197,6 +198,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 92f30e2..139a623 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -132,6 +132,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index eccc146..505d355 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #elif defined(CONFIG_QEMU_E500)
 #define CONFIG_MAX_CPUS			1
@@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index e325b4d..45f463f 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
 
 	while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
 			CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
-			+ offset * 0x20000)) >= 0) {
+			+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
 		fdt_del_node(blob, nodeoff);
 		offset++;
 	}
-- 
cgit v0.10.2


From 76394c9c9139b82e21a6e52da0e7341a3374f4be Mon Sep 17 00:00:00 2001
From: Alex Porosanu <alexandru.porosanu@freescale.com>
Date: Fri, 29 Apr 2016 15:18:00 +0300
Subject: crypto/fsl: add support for multiple SEC engines initialization

For SoCs that contain multiple SEC engines, each of them needs
to be initialized (by means of initializing among others the
random number generator).

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index f168375..61f5639 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -958,6 +958,15 @@ int cpu_init_r(void)
 
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
+
+#if defined(CONFIG_PPC_C29X)
+	if ((SVR_SOC_VER(svr) == SVR_C292) ||
+	    (SVR_SOC_VER(svr) == SVR_C293))
+		sec_init_idx(1);
+
+	if (SVR_SOC_VER(svr) == SVR_C293)
+		sec_init_idx(2);
+#endif
 #endif
 
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8bc517d..510fa4e 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -19,11 +19,26 @@
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
 
-struct jobring jr;
+uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
+	0,
+#if defined(CONFIG_PPC_C29X)
+	CONFIG_SYS_FSL_SEC_IDX_OFFSET,
+	2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
+#endif
+};
+
+#define SEC_ADDR(idx)	\
+	((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+
+#define SEC_JR0_ADDR(idx)	\
+	(SEC_ADDR(idx) +	\
+	 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+
+struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
 
-static inline void start_jr0(void)
+static inline void start_jr0(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
 	u32 scfgr = sec_in32(&sec->scfgr);
 
@@ -42,15 +57,15 @@ static inline void start_jr0(void)
 	}
 }
 
-static inline void jr_reset_liodn(void)
+static inline void jr_reset_liodn(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	sec_out32(&sec->jrliodnr[0].ls, 0);
 }
 
-static inline void jr_disable_irq(void)
+static inline void jr_disable_irq(uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
 
 	jrcfg = jrcfg | JR_INTMASK;
@@ -58,11 +73,12 @@ static inline void jr_disable_irq(void)
 	sec_out32(&regs->jrcfg1, jrcfg);
 }
 
-static void jr_initregs(void)
+static void jr_initregs(uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
-	phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
-	phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	struct jobring *jr = &jr0[sec_idx];
+	phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
+	phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
 
 #ifdef CONFIG_PHYS_64BIT
 	sec_out32(&regs->irba_h, ip_base >> 32);
@@ -79,59 +95,63 @@ static void jr_initregs(void)
 	sec_out32(&regs->ors, JR_SIZE);
 	sec_out32(&regs->irs, JR_SIZE);
 
-	if (!jr.irq)
-		jr_disable_irq();
+	if (!jr->irq)
+		jr_disable_irq(sec_idx);
 }
 
-static int jr_init(void)
+static int jr_init(uint8_t sec_idx)
 {
-	memset(&jr, 0, sizeof(struct jobring));
+	struct jobring *jr = &jr0[sec_idx];
 
-	jr.jq_id = DEFAULT_JR_ID;
-	jr.irq = DEFAULT_IRQ;
+	memset(jr, 0, sizeof(struct jobring));
+
+	jr->jq_id = DEFAULT_JR_ID;
+	jr->irq = DEFAULT_IRQ;
 
 #ifdef CONFIG_FSL_CORENET
-	jr.liodn = DEFAULT_JR_LIODN;
+	jr->liodn = DEFAULT_JR_LIODN;
 #endif
-	jr.size = JR_SIZE;
-	jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+	jr->size = JR_SIZE;
+	jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
 				JR_SIZE * sizeof(dma_addr_t));
-	if (!jr.input_ring)
+	if (!jr->input_ring)
 		return -1;
 
-	jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
-			     ARCH_DMA_MINALIGN);
-	jr.output_ring =
-	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
-	if (!jr.output_ring)
+	jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
+			      ARCH_DMA_MINALIGN);
+	jr->output_ring =
+	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
+	if (!jr->output_ring)
 		return -1;
 
-	memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
-	memset(jr.output_ring, 0, jr.op_size);
+	memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+	memset(jr->output_ring, 0, jr->op_size);
 
-	start_jr0();
+	start_jr0(sec_idx);
 
-	jr_initregs();
+	jr_initregs(sec_idx);
 
 	return 0;
 }
 
-static int jr_sw_cleanup(void)
+static int jr_sw_cleanup(uint8_t sec_idx)
 {
-	jr.head = 0;
-	jr.tail = 0;
-	jr.read_idx = 0;
-	jr.write_idx = 0;
-	memset(jr.info, 0, sizeof(jr.info));
-	memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
-	memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
+	struct jobring *jr = &jr0[sec_idx];
+
+	jr->head = 0;
+	jr->tail = 0;
+	jr->read_idx = 0;
+	jr->write_idx = 0;
+	memset(jr->info, 0, sizeof(jr->info));
+	memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
+	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
 
 	return 0;
 }
 
-static int jr_hw_reset(void)
+static int jr_hw_reset(uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 	uint32_t timeout = 100000;
 	uint32_t jrint, jrcr;
 
@@ -161,10 +181,11 @@ static int jr_hw_reset(void)
 /* -1 --- error, can't enqueue -- no space available */
 static int jr_enqueue(uint32_t *desc_addr,
 	       void (*callback)(uint32_t status, void *arg),
-	       void *arg)
+	       void *arg, uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
-	int head = jr.head;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	struct jobring *jr = &jr0[sec_idx];
+	int head = jr->head;
 	uint32_t desc_word;
 	int length = desc_len(desc_addr);
 	int i;
@@ -184,18 +205,14 @@ static int jr_enqueue(uint32_t *desc_addr,
 
 	phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
 
-	if (sec_in32(&regs->irsa) == 0 ||
-	    CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
-		return -1;
-
-	jr.info[head].desc_phys_addr = desc_phys_addr;
-	jr.info[head].callback = (void *)callback;
-	jr.info[head].arg = arg;
-	jr.info[head].op_done = 0;
+	jr->info[head].desc_phys_addr = desc_phys_addr;
+	jr->info[head].callback = (void *)callback;
+	jr->info[head].arg = arg;
+	jr->info[head].op_done = 0;
 
-	unsigned long start = (unsigned long)&jr.info[head] &
+	unsigned long start = (unsigned long)&jr->info[head] &
 					~(ARCH_DMA_MINALIGN - 1);
-	unsigned long end = ALIGN((unsigned long)&jr.info[head] +
+	unsigned long end = ALIGN((unsigned long)&jr->info[head] +
 				  sizeof(struct jr_info), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
@@ -205,11 +222,11 @@ static int jr_enqueue(uint32_t *desc_addr,
 	 * depend on endianness of SEC block.
 	 */
 #ifdef CONFIG_SYS_FSL_SEC_LE
-	addr_lo = (uint32_t *)(&jr.input_ring[head]);
-	addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
+	addr_lo = (uint32_t *)(&jr->input_ring[head]);
+	addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
 #elif defined(CONFIG_SYS_FSL_SEC_BE)
-	addr_hi = (uint32_t *)(&jr.input_ring[head]);
-	addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
+	addr_hi = (uint32_t *)(&jr->input_ring[head]);
+	addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 
 	sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
@@ -217,21 +234,21 @@ static int jr_enqueue(uint32_t *desc_addr,
 
 #else
 	/* Write the 32 bit Descriptor address on Input Ring. */
-	sec_out32(&jr.input_ring[head], desc_phys_addr);
+	sec_out32(&jr->input_ring[head], desc_phys_addr);
 #endif /* ifdef CONFIG_PHYS_64BIT */
 
-	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
-	end = ALIGN((unsigned long)&jr.input_ring[head] +
+	start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+	end = ALIGN((unsigned long)&jr->input_ring[head] +
 		     sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
-	jr.head = (head + 1) & (jr.size - 1);
+	jr->head = (head + 1) & (jr->size - 1);
 
 	/* Invalidate output ring */
-	start = (unsigned long)jr.output_ring &
+	start = (unsigned long)jr->output_ring &
 					~(ARCH_DMA_MINALIGN - 1);
-	end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
-		     ARCH_DMA_MINALIGN);
+	end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
+		    ARCH_DMA_MINALIGN);
 	invalidate_dcache_range(start, end);
 
 	sec_out32(&regs->irja, 1);
@@ -239,11 +256,12 @@ static int jr_enqueue(uint32_t *desc_addr,
 	return 0;
 }
 
-static int jr_dequeue(void)
+static int jr_dequeue(int sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
-	int head = jr.head;
-	int tail = jr.tail;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	struct jobring *jr = &jr0[sec_idx];
+	int head = jr->head;
+	int tail = jr->tail;
 	int idx, i, found;
 	void (*callback)(uint32_t status, void *arg);
 	void *arg = NULL;
@@ -253,7 +271,8 @@ static int jr_dequeue(void)
 	uint32_t *addr;
 #endif
 
-	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+	while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
+						 jr->size)) {
 
 		found = 0;
 
@@ -264,11 +283,11 @@ static int jr_dequeue(void)
 		 * depend on endianness of SEC block.
 		 */
 	#ifdef CONFIG_SYS_FSL_SEC_LE
-		addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
-		addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+		addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+		addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 	#elif defined(CONFIG_SYS_FSL_SEC_BE)
-		addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
-		addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+		addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+		addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 	#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 
 		op_desc = ((u64)sec_in32(addr_hi) << 32) |
@@ -276,15 +295,15 @@ static int jr_dequeue(void)
 
 	#else
 		/* Read the 32 bit Descriptor address from Output Ring. */
-		addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
+		addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
 		op_desc = sec_in32(addr);
 	#endif /* ifdef CONFIG_PHYS_64BIT */
 
-		uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
+		uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
 
-		for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
-			idx = (tail + i) & (jr.size - 1);
-			if (op_desc == jr.info[idx].desc_phys_addr) {
+		for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
+			idx = (tail + i) & (jr->size - 1);
+			if (op_desc == jr->info[idx].desc_phys_addr) {
 				found = 1;
 				break;
 			}
@@ -294,9 +313,9 @@ static int jr_dequeue(void)
 		if (!found)
 			return -1;
 
-		jr.info[idx].op_done = 1;
-		callback = (void *)jr.info[idx].callback;
-		arg = jr.info[idx].arg;
+		jr->info[idx].op_done = 1;
+		callback = (void *)jr->info[idx].callback;
+		arg = jr->info[idx].arg;
 
 		/* When the job on tail idx gets done, increment
 		 * tail till the point where job completed out of oredr has
@@ -304,14 +323,14 @@ static int jr_dequeue(void)
 		 */
 		if (idx == tail)
 			do {
-				tail = (tail + 1) & (jr.size - 1);
-			} while (jr.info[tail].op_done);
+				tail = (tail + 1) & (jr->size - 1);
+			} while (jr->info[tail].op_done);
 
-		jr.tail = tail;
-		jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
+		jr->tail = tail;
+		jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
 
 		sec_out32(&regs->orjr, 1);
-		jr.info[idx].op_done = 0;
+		jr->info[idx].op_done = 0;
 
 		callback(status, arg);
 	}
@@ -327,7 +346,7 @@ static void desc_done(uint32_t status, void *arg)
 	x->done = 1;
 }
 
-int run_descriptor_jr(uint32_t *desc)
+static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 {
 	unsigned long long timeval = get_ticks();
 	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
@@ -336,7 +355,7 @@ int run_descriptor_jr(uint32_t *desc)
 
 	memset(&op, 0, sizeof(op));
 
-	ret = jr_enqueue(desc, desc_done, &op);
+	ret = jr_enqueue(desc, desc_done, &op, sec_idx);
 	if (ret) {
 		debug("Error in SEC enq\n");
 		ret = JQ_ENQ_ERR;
@@ -346,7 +365,7 @@ int run_descriptor_jr(uint32_t *desc)
 	timeval = get_ticks();
 	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
 	while (op.done != 1) {
-		ret = jr_dequeue();
+		ret = jr_dequeue(sec_idx);
 		if (ret) {
 			debug("Error in SEC deq\n");
 			ret = JQ_DEQ_ERR;
@@ -368,20 +387,30 @@ out:
 	return ret;
 }
 
-int jr_reset(void)
+int run_descriptor_jr(uint32_t *desc)
+{
+	return run_descriptor_jr_idx(desc, 0);
+}
+
+static inline int jr_reset_sec(uint8_t sec_idx)
 {
-	if (jr_hw_reset() < 0)
+	if (jr_hw_reset(sec_idx) < 0)
 		return -1;
 
 	/* Clean up the jobring structure maintained by software */
-	jr_sw_cleanup();
+	jr_sw_cleanup(sec_idx);
 
 	return 0;
 }
 
-int sec_reset(void)
+int jr_reset(void)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	return jr_reset_sec(0);
+}
+
+static inline int sec_reset_idx(uint8_t sec_idx)
+{
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	uint32_t mcfgr = sec_in32(&sec->mcfgr);
 	uint32_t timeout = 100000;
 
@@ -408,14 +437,13 @@ int sec_reset(void)
 	return 0;
 }
 
-static int instantiate_rng(void)
+static int instantiate_rng(uint8_t sec_idx)
 {
 	struct result op;
 	u32 *desc;
 	u32 rdsta_val;
 	int ret = 0;
-	ccsr_sec_t __iomem *sec =
-			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 
@@ -432,7 +460,7 @@ static int instantiate_rng(void)
 	flush_dcache_range((unsigned long)desc,
 			   (unsigned long)desc + size);
 
-	ret = run_descriptor_jr(desc);
+	ret = run_descriptor_jr_idx(desc, sec_idx);
 
 	if (ret)
 		printf("RNG: Instantiation failed with error %x\n", ret);
@@ -444,9 +472,14 @@ static int instantiate_rng(void)
 	return ret;
 }
 
-static u8 get_rng_vid(void)
+int sec_reset(void)
+{
+	return sec_reset_idx(0);
+}
+
+static u8 get_rng_vid(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	u32 cha_vid = sec_in32(&sec->chavid_ls);
 
 	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
@@ -456,10 +489,9 @@ static u8 get_rng_vid(void)
  * By default, the TRNG runs for 200 clocks per sample;
  * 1200 clocks per sample generates better entropy.
  */
-static void kick_trng(int ent_delay)
+static void kick_trng(int ent_delay, uint8_t sec_idx)
 {
-	ccsr_sec_t __iomem *sec =
-			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 val;
@@ -486,11 +518,10 @@ static void kick_trng(int ent_delay)
 	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 }
 
-static int rng_init(void)
+static int rng_init(uint8_t sec_idx)
 {
 	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
-	ccsr_sec_t __iomem *sec =
-			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 
@@ -509,7 +540,7 @@ static int rng_init(void)
 		 * Also, if a handle was instantiated, do not change
 		 * the TRNG parameters.
 		 */
-		kick_trng(ent_delay);
+		kick_trng(ent_delay, sec_idx);
 		ent_delay += 400;
 		/*
 		 * if instantiate_rng(...) fails, the loop will rerun
@@ -518,7 +549,7 @@ static int rng_init(void)
 		 * interval, leading to a sucessful initialization of
 		 * the RNG.
 		 */
-		ret = instantiate_rng();
+		ret = instantiate_rng(sec_idx);
 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 	if (ret) {
 		printf("RNG: Failed to instantiate RNG\n");
@@ -531,9 +562,9 @@ static int rng_init(void)
 	return ret;
 }
 
-int sec_init(void)
+int sec_init_idx(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	uint32_t mcr = sec_in32(&sec->mcfgr);
 	int ret = 0;
 
@@ -543,6 +574,11 @@ int sec_init(void)
 	uint32_t liodn_s;
 #endif
 
+	if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
+		printf("SEC initialization failed\n");
+		return -1;
+	}
+
 	/*
 	 * Modifying CAAM Read/Write Attributes
 	 * For LS2080A
@@ -568,7 +604,7 @@ int sec_init(void)
 	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 #endif
 
-	ret = jr_init();
+	ret = jr_init(sec_idx);
 	if (ret < 0) {
 		printf("SEC initialization failed\n");
 		return -1;
@@ -582,13 +618,18 @@ int sec_init(void)
 	pamu_enable();
 #endif
 
-	if (get_rng_vid() >= 4) {
-		if (rng_init() < 0) {
-			printf("RNG instantiation failed\n");
+	if (get_rng_vid(sec_idx) >= 4) {
+		if (rng_init(sec_idx) < 0) {
+			printf("SEC%u: RNG instantiation failed\n", sec_idx);
 			return -1;
 		}
-		printf("SEC: RNG instantiated\n");
+		printf("SEC%u: RNG instantiated\n", sec_idx);
 	}
 
 	return ret;
 }
+
+int sec_init(void)
+{
+	return sec_init_idx(0);
+}
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1642dbb..d897e57 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -90,6 +90,9 @@ struct jobring {
 	/* This ring can be on the stack */
 	struct jr_info info[JR_SIZE];
 	struct op_ring *output_ring;
+	/* Offset in CCSR to the SEC engine to which this JR belongs */
+	uint32_t sec_offset;
+
 };
 
 struct result {
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index a52110a..bffabc8 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -294,8 +294,6 @@ struct sg_entry {
 
 #endif
 
-int sec_init(void);
-
 /* blob_dek:
  * Encapsulates the src in a secure blob and stores it dst
  * @src: reference to the plaintext
@@ -305,6 +303,10 @@ int sec_init(void);
  */
 int blob_dek(const u8 *src, u8 *dst, u8 len);
 
+#if defined(CONFIG_PPC_C29X)
+int sec_init_idx(uint8_t);
+#endif
+int sec_init(void);
 #endif
 
 #endif /* __FSL_SEC_H */
-- 
cgit v0.10.2


From 7942550a146f3eaf00add0e13442946365cc9775 Mon Sep 17 00:00:00 2001
From: Shaohui Xie <Shaohui.Xie@nxp.com>
Date: Fri, 29 Apr 2016 22:07:21 +0800
Subject: armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY

To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity
by setting relative bit in SCFG_INTPCR register, because AQR105
interrupt is low active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index b169139..1436520 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -82,6 +82,8 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
 #ifdef CONFIG_FSL_IFC
 	init_final_memctl_regs();
 #endif
@@ -93,6 +95,8 @@ int board_init(void)
 #ifdef CONFIG_U_QE
 	u_qe_init();
 #endif
+	/* invert AQR105 IRQ pins polarity */
+	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 
 	return 0;
 }
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 6d35be2..39687cf 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -253,6 +253,7 @@
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK			0x40000000
 
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
-- 
cgit v0.10.2


From 397b0d9e2971e6956399b7efd7737c962dd63c81 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Wed, 4 May 2016 12:45:55 +0800
Subject: arm: ls1021a: Enable CONFIG_OF_LIBFDT and CONFIG_FIT in defconfig

In defconfig, enable CONFIG_OF_LIBFDT to support booting DT linux
kernel and enable COFNIG_FIT to support FIT image.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 6feb581..04ded54 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 563af48..7915200 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 0786f20..9002a01 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -22,3 +22,5 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 243fcdd..30c2ca5 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -24,3 +24,5 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 3cecdfe..a30153a 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 75b763e..217cf88 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index c47fbce..15b0b0d 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 61ab251..ef42d3d 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -1,6 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index bb88743..69f5b61 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -2,6 +2,9 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index a5cbb22..1c0ae06 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -24,3 +24,5 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 465054f..10cc576 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index e96e31a..f56f931 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 987638c..bc419fb 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -4,6 +4,9 @@ CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index df4d428..e27758b 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -21,3 +21,5 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 583325d..01856d4 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -5,6 +5,9 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-- 
cgit v0.10.2


From 019a147b658631921a5d9d429a9097b33e142d78 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Tue, 10 May 2016 16:03:47 +0800
Subject: driver/ddr/fsl: Add workaround for erratum A-010165

During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 34b1500..fbdaa52 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -137,6 +137,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009801
 #define CONFIG_SYS_FSL_ERRATUM_A009803
 #define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 
 /* ARM A57 CORE ERRATA */
 #define CONFIG_ARM_ERRATA_826974
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 1dc0631..5039f5d 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -56,7 +56,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};	/* for range 2 */
 	u32 *vref_seq = vref_seq1;
 #endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
+	defined(CONFIG_SYS_FSL_ERRATUM_A010165)
 	ulong ddr_freq;
 	u32 tmp;
 #endif
@@ -271,6 +272,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+		tmp = ddr_in32(&ddr->debug[28]);
+		ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+	}
+#endif
 	/*
 	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 	 * deasserted. Clocks start when any chip select is enabled and clock
-- 
cgit v0.10.2


From bc323b3fa7cbf1008f02d342c0505231961b5fa6 Mon Sep 17 00:00:00 2001
From: Po Liu <po.liu@nxp.com>
Date: Wed, 18 May 2016 10:09:38 +0800
Subject: armv8: ls1043ardb: enable scsi command and pcie to sata converter

Enable scsi command and pcie to sata chip 88SE9170.

Signed-off-by: Po Liu <po.liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 39687cf..aca8d95 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -286,6 +286,27 @@
 #define CONFIG_USB_STORAGE
 #endif
 
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_CMD_SCSI
+#ifndef CONFIG_CMD_FAT
+#define CONFIG_CMD_FAT
+#endif
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		2
+#define CONFIG_SYS_SCSI_MAX_LUN			2
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID  0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_PCI
+
 #include <asm/fsl_secure_boot.h>
 
 #endif /* __LS1043ARDB_H__ */
-- 
cgit v0.10.2


From cb1629f91a487e34284868a2d246bc3b122c6395 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 7 Apr 2016 09:56:48 -0700
Subject: powerpc: Disable flush or invalidate dcache by range for some SoCs

Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-op for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues when the dcache is flushed. While the root cause is under
investigation, disable these functions for affected SoCs so various
drivers can work.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index b96dbc6..66cf02d 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,6 +65,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range)
 	addi	r3,r3,L1_CACHE_BYTES
 	bdnz	1b
 	sync				/* wait for dcbst's to get to ram */
+#endif
 	blr
 
 /*
@@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range)
 	addi	r3,r3,L1_CACHE_BYTES
 	bdnz	1b
 	sync				/* wait for dcbi's to get to ram */
+#endif
 	blr
 
-- 
cgit v0.10.2


From a4d3074209f84038c488b3015d494ff1bb8bb7ee Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 7 Apr 2016 09:53:27 -0700
Subject: powerpc/t208xqds: Update MAINTAINERS file

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>

diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
index deda092..d747de3 100644
--- a/board/freescale/t208xqds/MAINTAINERS
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -1,5 +1,5 @@
 T208XQDS BOARD
-#M:	-
+M:	Shengzhou Liu <Shengzhou.Liu@nxp.com>
 S:	Maintained
 F:	board/freescale/t208xqds/
 F:	include/configs/T208xQDS.h
-- 
cgit v0.10.2


From 9272611e991d6be1c5f53f3ef8a580513ff65a39 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 7 Apr 2016 09:53:28 -0700
Subject: powerpc/t208xrdb: Update MAINTAINERS file

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>

diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 1642879..ccbfbab 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -1,5 +1,5 @@
 T208XRDB BOARD
-#M:	-
+M:	Shengzhou Liu <Shengzhou.Liu@nxp.com>
 S:	Maintained
 F:	board/freescale/t208xrdb/
 F:	include/configs/T208xRDB.h
-- 
cgit v0.10.2


From 46caebc1dff8f456b4f076bbebbb2ba32236d06d Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 7 Apr 2016 09:52:11 -0700
Subject: powerpc/t2080qds: Enable qixis commands to reboot from NAND and SD

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index d8c57a8..f48697c 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -291,6 +291,10 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_RCW_SRC_NAND		0x104
+#define QIXIS_RCW_SRC_SD		0x040
 #define QIXIS_RST_CTL_RESET		0x83
 #define QIXIS_RST_FORCE_MEM		0x1
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
-- 
cgit v0.10.2


From 29b59353fe7cd62c74960b76e7b56bbc368429d2 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 30 Apr 2016 14:45:42 +0200
Subject: arm: mvebu: a38x: Weed out floating point use

For reason unknown, recently, the DDR init code writers are really fond
of hiding some small floating point operating deep in their creations.
This patch removes one from the Marvell A38x code.

Instead of returning size of chip as float from ddr3_get_device_size()
in GiB units, return it as int in MiB units. Since this would interfere
with the huge switch code in ddr3_calc_mem_cs_size(), rework the code
to match the change.

Before this patch, the cs_mem_size variable could have these values:
 ( { 16, 32 } x { 8, 16 } x { 0.01, 0.5, 1, 2, 4, 8 } ) / 8 =
   { 0.000000, 0.001250, 0.002500, 0.005000, 0.062500, 0.125000,
     0.250000, 0.500000, 1.000000, 2.000000, 4.000000, }
The switch code checked for a subset of the resulting RAM sizes, which
is in range 128 MiB ... 2048 MiB.

With this patch, the cs_mem_size variable can have these values:
 ( { 16, 32 } x { 8, 16 } x { 0, 512, 1024, 2048, 4096, 8192 } ) / 8 =
   { 0, 64, 128, 256, 512, 1024, 2048, 4096 }
To retain previous behavior, filter out 0 MiB (invalid size), 64 MiB
and 4096 MiB options.

Removing the floating point stuff also saves 1.5k from text segment:
  clearfog       :  spl/u-boot-spl:all -1592  spl/u-boot-spl:text -1592

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index ee05f57..55baad4 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -678,7 +678,7 @@ u32 ddr3_get_device_width(u32 cs)
 	return (device_width == 0) ? 8 : 16;
 }
 
-float ddr3_get_device_size(u32 cs)
+static int ddr3_get_device_size(u32 cs)
 {
 	u32 device_size_low, device_size_high, device_size;
 	u32 data, cs_low_offset, cs_high_offset;
@@ -695,15 +695,15 @@ float ddr3_get_device_size(u32 cs)
 
 	switch (device_size) {
 	case 0:
-		return 2;
+		return 2048;
 	case 2:
-		return 0.5;
+		return 512;
 	case 3:
-		return 1;
+		return 1024;
 	case 4:
-		return 4;
+		return 4096;
 	case 5:
-		return 8;
+		return 8192;
 	case 1:
 	default:
 		DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
@@ -711,13 +711,13 @@ float ddr3_get_device_size(u32 cs)
 		 * Small value will give wrong emem size in
 		 * ddr3_calc_mem_cs_size
 		 */
-		return 0.01;
+		return 0;
 	}
 }
 
 int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
 {
-	float cs_mem_size;
+	int cs_mem_size;
 
 	/* Calculate in GiB */
 	cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
@@ -731,21 +731,12 @@ int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
 	 */
 	cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
 
-	if (cs_mem_size == 0.125) {
-		*cs_size = 128 << 20;
-	} else if (cs_mem_size == 0.25) {
-		*cs_size = 256 << 20;
-	} else if (cs_mem_size == 0.5) {
-		*cs_size = 512 << 20;
-	} else if (cs_mem_size == 1) {
-		*cs_size = 1 << 30;
-	} else if (cs_mem_size == 2) {
-		*cs_size = 2 << 30;
-	} else {
+	if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
 		DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
 		return MV_BAD_VALUE;
 	}
 
+	*cs_size = cs_mem_size << 20;
 	return MV_OK;
 }
 
-- 
cgit v0.10.2


From fbaf42724f372ee3fb0d7cd83107f5bae416028f Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 13 Apr 2016 11:02:20 +0200
Subject: arm: mvebu: theadorable: Enable CONFIG_ZERO_BOOTDELAY_CHECK

Enable bootdelay 0 check so that booting can be interrupted even with
bootdelay configured to 0.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 1caa858..dda70c5 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -64,6 +64,7 @@
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PREBOOT
 
-- 
cgit v0.10.2


From 2636ac65a84f2bbab4b6a773384cfc630b9b6d7b Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:02 +0300
Subject: cmd: eeprom: add bus switching support for all i2c drivers

The i2c_init function is always provided when CONFIG_SYS_I2C is
defined. No need to limit ourselves to just one supported I2C driver
(soft_i2c). Update the #ifdef conditions to support bus switching for
all I2C drivers.

Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index e5457ba..208b413 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -72,7 +72,7 @@ void eeprom_init(int bus)
 #endif
 
 	/* I2C EEPROM */
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
 #if defined(CONFIG_SYS_I2C)
 	if (bus >= 0)
 		i2c_set_bus_num(bus);
-- 
cgit v0.10.2


From aa9e60441095ee3f20a109742e3ba5cdfd28458b Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:03 +0300
Subject: cmd: eeprom: add support for layout aware commands

Introduce the (optional) eeprom print and eeprom update commands.

These commands are eeprom layout aware:
* The eeprom print command prints the contents of the eeprom in a human
  readable way (eeprom layout fields, and data formatted to be fit for human
  consumption).
* The eeprom update command allows user to update eeprom fields by specifying
  the field name, and providing the new data in a human readable format (same
  format as displayed by the eeprom print command).
* Both commands can either auto detect the layout, or be told which layout to
  use.

New CONFIG options:
CONFIG_CMD_EEPROM_LAYOUT - enables commands.
CONFIG_EEPROM_LAYOUT_HELP_STRING - tells user what layout names are supported

Feature API:
__weak int parse_layout_version(char *str)
	- override to provide your own layout name parsing
__weak void __eeprom_layout_assign(struct eeprom_layout *layout, int layout_version);
	- override to setup the layout metadata based on the version
__weak int eeprom_layout_detect(unsigned char *data)
	- override to provide your own algorithm for detecting layout version
eeprom_field.c
	- contains various printing and updating functions for common types of
	  eeprom fields. Can be used for defining custom layouts.

Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/README b/README
index 94e9943..6f4c09a 100644
--- a/README
+++ b/README
@@ -1003,6 +1003,7 @@ The following options need to be configured:
 		CONFIG_CMD_ECHO		  echo arguments
 		CONFIG_CMD_EDITENV	  edit env variable
 		CONFIG_CMD_EEPROM	* EEPROM read/write support
+		CONFIG_CMD_EEPROM_LAYOUT* EEPROM layout aware commands
 		CONFIG_CMD_ELF		* bootelf, bootvx
 		CONFIG_CMD_ENV_CALLBACK	* display details about env callbacks
 		CONFIG_CMD_ENV_FLAGS	* display details about env flags
diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 208b413..39ebee8 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -207,6 +207,131 @@ int eeprom_write(unsigned dev_addr, unsigned offset,
 	return ret;
 }
 
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+#include <eeprom_layout.h>
+
+__weak int eeprom_parse_layout_version(char *str)
+{
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE];
+
+#ifndef CONFIG_EEPROM_LAYOUT_HELP_STRING
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "<not defined>"
+#endif
+
+enum eeprom_action {
+	EEPROM_PRINT,
+	EEPROM_UPDATE,
+	EEPROM_ACTION_INVALID,
+};
+
+static enum eeprom_action parse_action(char *cmd)
+{
+	if (!strncmp(cmd, "print", 5))
+		return EEPROM_PRINT;
+	if (!strncmp(cmd, "update", 6))
+		return EEPROM_UPDATE;
+
+	return EEPROM_ACTION_INVALID;
+}
+
+static int parse_numeric_param(char *str)
+{
+	char *endptr;
+	int value = simple_strtol(str, &endptr, 16);
+
+	return (*endptr != '\0') ? -1 : value;
+}
+
+static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
+				  int i2c_addr, int layout_ver, char *key,
+				  char *value)
+{
+	int rcode;
+	struct eeprom_layout layout;
+
+	if (action == EEPROM_ACTION_INVALID)
+		return CMD_RET_USAGE;
+
+	eeprom_init(i2c_bus);
+	rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE);
+	if (rcode < 0)
+		return rcode;
+
+	eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE,
+			    layout_ver);
+
+	if (action == EEPROM_PRINT) {
+		layout.print(&layout);
+		return 0;
+	}
+
+	layout.update(&layout, key, value);
+
+	rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE);
+
+	return rcode;
+}
+
+#define NEXT_PARAM(argc, index)	{ (argc)--; (index)++; }
+static int do_eeprom_layout(cmd_tbl_t *cmdtp, int flag, int argc,
+			    char * const argv[])
+{
+	int layout_ver = LAYOUT_VERSION_AUTODETECT;
+	enum eeprom_action action = EEPROM_ACTION_INVALID;
+	int i2c_bus = -1, i2c_addr = -1, index = 0;
+	char *field_name = "";
+	char *field_value = "";
+
+	if (argc <= 1)
+		return CMD_RET_USAGE;
+
+	NEXT_PARAM(argc, index); /* Skip program name */
+
+	action = parse_action(argv[index]);
+	NEXT_PARAM(argc, index);
+
+	if (argc <= 1)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(argv[index], "-l")) {
+		NEXT_PARAM(argc, index);
+
+		layout_ver = eeprom_parse_layout_version(argv[index]);
+		NEXT_PARAM(argc, index);
+	}
+
+	if (argc <= 1)
+		return CMD_RET_USAGE;
+
+	i2c_bus = parse_numeric_param(argv[index]);
+	NEXT_PARAM(argc, index);
+
+	i2c_addr = parse_numeric_param(argv[index]);
+	NEXT_PARAM(argc, index);
+
+	if (action == EEPROM_PRINT)
+		goto done;
+
+	if (argc) {
+		field_name = argv[index];
+		NEXT_PARAM(argc, index);
+	}
+
+	if (argc) {
+		field_value = argv[index];
+		NEXT_PARAM(argc, index);
+	}
+
+done:
+	return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
+			       field_name, field_value);
+}
+
+#endif
+
 static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	const char *const fmt =
@@ -216,6 +341,13 @@ static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	ulong dev_addr, addr, off, cnt;
 	int bus_addr;
 
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	if (argc >= 2) {
+		if (!strcmp(argv[1], "update") || !strcmp(argv[1], "print"))
+			return do_eeprom_layout(cmdtp, flag, argc, argv);
+	}
+#endif
+
 	switch (argc) {
 #ifdef CONFIG_SYS_DEF_EEPROM_ADDR
 	case 5:
@@ -261,9 +393,23 @@ static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 }
 
 U_BOOT_CMD(
-	eeprom,	7,	1,	do_eeprom,
+	eeprom,	8,	1,	do_eeprom,
 	"EEPROM sub-system",
 	"read  <bus> <devaddr> addr off cnt\n"
 	"eeprom write <bus> <devaddr> addr off cnt\n"
 	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	"\n"
+	"eeprom print [-l <layout_version>] bus devaddr\n"
+	"       - Print layout fields and their data in human readable format\n"
+	"eeprom update [-l <layout_version>] bus devaddr <field_name> <field_value>\n"
+	"       - Update a specific eeprom field with new data.\n"
+	"         The new data must be written in the same human readable format as shown by the print command.\n"
+	"\n"
+	"LAYOUT VERSIONS\n"
+	"The -l option can be used to force the command to interpret the EEPROM data using the chosen layout.\n"
+	"If the -l option is omitted, the command will auto detect the layout based on the data in the EEPROM.\n"
+	"The values which can be provided with the -l option are:\n"
+	CONFIG_EEPROM_LAYOUT_HELP_STRING"\n"
+#endif
 )
diff --git a/common/Makefile b/common/Makefile
index f9b26b7..0562d5c 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -156,6 +156,9 @@ obj-y += fb_nand.o
 endif
 endif
 
+ifdef CONFIG_CMD_EEPROM_LAYOUT
+obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
+endif
 # We always have this since drivers/ddr/fs/interactive.c needs it
 obj-$(CONFIG_CMDLINE) += cli_simple.o
 
diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c
new file mode 100644
index 0000000..7f095a6
--- /dev/null
+++ b/common/eeprom/eeprom_field.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/string.h>
+#include <eeprom_field.h>
+
+static void __eeprom_field_print_bin(const struct eeprom_field *field,
+				     char *delimiter, bool reverse)
+{
+	int i;
+	int from = reverse ? field->size - 1 : 0;
+	int to = reverse ? 0 : field->size - 1;
+
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	for (i = from; i != to; reverse ? i-- : i++)
+		printf("%02x%s", field->buf[i], delimiter);
+
+	printf("%02x\n", field->buf[i]);
+}
+
+static int __eeprom_field_update_bin(struct eeprom_field *field,
+				     const char *value, bool reverse)
+{
+	int len = strlen(value);
+	int k, j, i = reverse ? len - 1 : 0;
+	unsigned char byte;
+	char *endptr;
+
+	/* each two characters in the string fit in one byte */
+	if (len > field->size * 2)
+		return -1;
+
+	memset(field->buf, 0, field->size);
+
+	/* i - string iterator, j - buf iterator */
+	for (j = 0; j < field->size; j++) {
+		byte = 0;
+		char tmp[3] = { 0, 0, 0 };
+
+		if ((reverse && i < 0) || (!reverse && i >= len))
+			break;
+
+		for (k = 0; k < 2; k++) {
+			if (reverse && i == 0) {
+				tmp[k] = value[i];
+				break;
+			}
+
+			tmp[k] = value[reverse ? i - 1 + k : i + k];
+		}
+
+		byte = simple_strtoul(tmp, &endptr, 0);
+		if (*endptr != '\0' || byte < 0)
+			return -1;
+
+		field->buf[j] = byte;
+		i = reverse ? i - 2 : i + 2;
+	}
+
+	return 0;
+}
+
+static int __eeprom_field_update_bin_delim(struct eeprom_field *field,
+					   char *value, char *delimiter)
+{
+	int count = 0;
+	int i, val;
+	const char *tmp = value;
+	char *tok;
+	char *endptr;
+
+	tmp = strstr(tmp, delimiter);
+	while (tmp != NULL) {
+		count++;
+		tmp++;
+		tmp = strstr(tmp, delimiter);
+	}
+
+	if (count > field->size)
+		return -1;
+
+	tok = strtok(value, delimiter);
+	for (i = 0; tok && i < field->size; i++) {
+		val = simple_strtoul(tok, &endptr, 0);
+		if (*endptr != '\0')
+			return -1;
+
+		/* here we assume that each tok is no more than byte long */
+		field->buf[i] = (unsigned char)val;
+		tok = strtok(NULL, delimiter);
+	}
+
+	return 0;
+}
+
+/**
+ * eeprom_field_print_bin() - print a field which contains binary data
+ *
+ * Treat the field data as simple binary data, and print it as two digit
+ * hexadecimal values.
+ * Sample output:
+ *      Field Name       0102030405060708090a
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin(const struct eeprom_field *field)
+{
+	__eeprom_field_print_bin(field, "", false);
+}
+
+/**
+ * eeprom_field_update_bin() - Update field with new data in binary form
+ *
+ * @field:	an initialized field
+ * @value:	a string of values (i.e. "10b234a")
+ */
+int eeprom_field_update_bin(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin(field, value, false);
+}
+
+/**
+ * eeprom_field_update_reserved() - Update reserved field with new data in
+ *				    binary form
+ *
+ * @field:	an initialized field
+ * @value:	a space delimited string of byte values (i.e. "1 02 3 0x4")
+ */
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin_delim(field, value, " ");
+}
+
+/**
+ * eeprom_field_print_bin_rev() - print a field which contains binary data in
+ *				  reverse order
+ *
+ * Treat the field data as simple binary data, and print it in reverse order
+ * as two digit hexadecimal values.
+ *
+ * Data in field:
+ *                      0102030405060708090a
+ * Sample output:
+ *      Field Name      0a090807060504030201
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin_rev(const struct eeprom_field *field)
+{
+	__eeprom_field_print_bin(field, "", true);
+}
+
+/**
+ * eeprom_field_update_bin_rev() - Update field with new data in binary form,
+ *				   storing it in reverse
+ *
+ * This function takes a string of byte values, and stores them
+ * in the field in the reverse order. i.e. if the input string was "1234",
+ * "3412" will be written to the field.
+ *
+ * @field:	an initialized field
+ * @value:	a string of byte values
+ */
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin(field, value, true);
+}
+
+/**
+ * eeprom_field_print_mac_addr() - print a field which contains a mac address
+ *
+ * Treat the field data as simple binary data, and print it formatted as a MAC
+ * address.
+ * Sample output:
+ *      Field Name     01:02:03:04:05:06
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_mac(const struct eeprom_field *field)
+{
+	__eeprom_field_print_bin(field, ":", false);
+}
+
+/**
+ * eeprom_field_update_mac() - Update a mac address field which contains binary
+ *			       data
+ *
+ * @field:	an initialized field
+ * @value:	a colon delimited string of byte values (i.e. "1:02:3:ff")
+ */
+int eeprom_field_update_mac(struct eeprom_field *field, char *value)
+{
+	return __eeprom_field_update_bin_delim(field, value, ":");
+}
+
+/**
+ * eeprom_field_print_ascii() - print a field which contains ASCII data
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_ascii(const struct eeprom_field *field)
+{
+	char format[8];
+
+	sprintf(format, "%%.%ds\n", field->size);
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	printf(format, field->buf);
+}
+
+/**
+ * eeprom_field_update_ascii() - Update field with new data in ASCII form
+ * @field:	an initialized field
+ * @value:	the new string data
+ *
+ * Returns 0 on success, -1 of failure (new string too long).
+ */
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value)
+{
+	if (strlen(value) >= field->size) {
+		printf("%s: new data too long\n", field->name);
+		return -1;
+	}
+
+	strncpy((char *)field->buf, value, field->size - 1);
+	field->buf[field->size - 1] = '\0';
+
+	return 0;
+}
+
+/**
+ * eeprom_field_print_reserved() - print the "Reserved fields" field
+ *
+ * Print a notice that the following field_size bytes are reserved.
+ *
+ * Sample output:
+ *      Reserved fields              (64 bytes)
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_reserved(const struct eeprom_field *field)
+{
+	printf(PRINT_FIELD_SEGMENT, "Reserved fields\t");
+	printf("(%d bytes)\n", field->size);
+}
diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c
new file mode 100644
index 0000000..c059233
--- /dev/null
+++ b/common/eeprom/eeprom_layout.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kernel.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+
+#define NO_LAYOUT_FIELDS	"Unknown layout. Dumping raw data\n"
+
+struct eeprom_field layout_unknown[1] = {
+	{ NO_LAYOUT_FIELDS, 256, NULL, eeprom_field_print_bin,
+				       eeprom_field_update_bin },
+};
+
+/*
+ * eeprom_layout_detect() - detect layout based on the contents of the data.
+ * @data: Pointer to the data to be analyzed.
+ *
+ * Returns: the detected layout version.
+ */
+__weak int eeprom_layout_detect(unsigned char *data)
+{
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+/*
+ * __eeprom_layout_assign() - set the layout fields
+ * @layout:		A pointer to an existing struct layout.
+ * @layout_version:	The version number of the desired layout
+ */
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+				   int layout_version)
+{
+	layout->fields = layout_unknown;
+	layout->num_of_fields = ARRAY_SIZE(layout_unknown);
+}
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) \
+		__attribute__((weak, alias("__eeprom_layout_assign")));
+
+/*
+ * eeprom_layout_print() - print the layout and the data which is assigned to it
+ * @layout: A pointer to an existing struct layout.
+ */
+static void eeprom_layout_print(const struct eeprom_layout *layout)
+{
+	int i;
+	struct eeprom_field *fields = layout->fields;
+
+	for (i = 0; i < layout->num_of_fields; i++)
+		fields[i].print(&fields[i]);
+}
+
+/*
+ * eeprom_layout_update_field() - update a single field in the layout data.
+ * @layout:	A pointer to an existing struct layout.
+ * @field_name:	The name of the field to update.
+ * @new_data:	The new field data (a string. Format depends on the field)
+ *
+ * Returns: 0 on success, negative error value on failure.
+ */
+static int eeprom_layout_update_field(struct eeprom_layout *layout,
+				      char *field_name, char *new_data)
+{
+	int i, err;
+	struct eeprom_field *fields = layout->fields;
+
+	if (new_data == NULL)
+		return 0;
+
+	if (field_name == NULL)
+		return -1;
+
+	for (i = 0; i < layout->num_of_fields; i++) {
+		if (fields[i].name == RESERVED_FIELDS ||
+		    strcmp(fields[i].name, field_name))
+			continue;
+
+		err = fields[i].update(&fields[i], new_data);
+		if (err)
+			printf("Invalid data for field %s\n", field_name);
+
+		return err;
+	}
+
+	printf("No such field '%s'\n", field_name);
+
+	return -1;
+}
+
+/*
+ * eeprom_layout_setup() - setup layout struct with the layout data and
+ *			   metadata as dictated by layout_version
+ * @layout:	A pointer to an existing struct layout.
+ * @buf:	A buffer initialized with the eeprom data.
+ * @buf_size:	Size of buf in bytes.
+ * @layout version: The version number of the layout.
+ */
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+			 unsigned int buf_size, int layout_version)
+{
+	int i;
+
+	if (layout_version == LAYOUT_VERSION_AUTODETECT)
+		layout->layout_version = eeprom_layout_detect(buf);
+	else
+		layout->layout_version = layout_version;
+
+	eeprom_layout_assign(layout, layout_version);
+	layout->data = buf;
+	for (i = 0; i < layout->num_of_fields; i++) {
+		layout->fields[i].buf = buf;
+		buf += layout->fields[i].size;
+	}
+
+	layout->data_size = buf_size;
+	layout->print = eeprom_layout_print;
+	layout->update = eeprom_layout_update_field;
+}
diff --git a/include/eeprom_field.h b/include/eeprom_field.h
new file mode 100644
index 0000000..94e259f
--- /dev/null
+++ b/include/eeprom_field.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FIELD_
+#define _FIELD_
+
+#define PRINT_FIELD_SEGMENT	"%-30s"
+
+struct eeprom_field {
+	char *name;
+	int size;
+	unsigned char *buf;
+
+	void (*print)(const struct eeprom_field *eeprom_field);
+	int (*update)(struct eeprom_field *eeprom_field, char *value);
+};
+
+void eeprom_field_print_bin(const struct eeprom_field *field);
+int eeprom_field_update_bin(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_bin_rev(const struct eeprom_field *field);
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_mac(const struct eeprom_field *field);
+int eeprom_field_update_mac(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_ascii(const struct eeprom_field *field);
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_reserved(const struct eeprom_field *field);
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value);
+
+#endif
diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h
new file mode 100644
index 0000000..459b99d
--- /dev/null
+++ b/include/eeprom_layout.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LAYOUT_
+#define _LAYOUT_
+
+#define RESERVED_FIELDS			NULL
+#define LAYOUT_VERSION_UNRECOGNIZED	-1
+#define LAYOUT_VERSION_AUTODETECT	-2
+
+struct eeprom_layout {
+	struct eeprom_field *fields;
+	int num_of_fields;
+	int layout_version;
+	unsigned char *data;
+	int data_size;
+	void (*print)(const struct eeprom_layout *eeprom_layout);
+	int (*update)(struct eeprom_layout *eeprom_layout, char *field_name,
+		      char *new_data);
+};
+
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+			 unsigned int buf_size, int layout_version);
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+				   int layout_version);
+
+#endif
-- 
cgit v0.10.2


From 8af5734b4e9322a9af8640ba1af48ebe14ebf6c3 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:04 +0300
Subject: compulab: add support for layout aware eeprom commands

Add layout definitions and implement functions for field printing/updating,
layout detection, layout assignment, and layout parsing.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index 6304468..b5f1aa6 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -9,6 +9,9 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+#include <linux/kernel.h>
 #include "eeprom.h"
 
 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
@@ -181,3 +184,344 @@ int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus)
 
 	return err;
 }
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+/**
+ * eeprom_field_print_bin_ver() - print a "version field" which contains binary
+ *				  data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a
+ * version number (2 digits after decimal point).
+ * The field size must be exactly 2 bytes.
+ *
+ * Sample output:
+ *      Field Name      123.45
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_bin_ver(const struct eeprom_field *field)
+{
+	if ((field->buf[0] == 0xff) && (field->buf[1] == 0xff)) {
+		field->buf[0] = 0;
+		field->buf[1] = 0;
+	}
+
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	int major = (field->buf[1] << 8 | field->buf[0]) / 100;
+	int minor = (field->buf[1] << 8 | field->buf[0]) - major * 100;
+	printf("%d.%02d\n", major, minor);
+}
+
+/**
+ * eeprom_field_update_bin_ver() - update a "version field" which contains
+ *				   binary data
+ *
+ * This function takes a version string in the form of x.y (x and y are both
+ * decimal values, y is limited to two digits), translates it to the binary
+ * form, then writes it to the field. The field size must be exactly 2 bytes.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow.
+ *
+ * @field:	an initialized field
+ * @value:	a version string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value)
+{
+	char *endptr;
+	char *tok = strtok(value, ".");
+	if (tok == NULL)
+		return -1;
+
+	int num = simple_strtol(tok, &endptr, 0);
+	if (*endptr != '\0')
+		return -1;
+
+	tok = strtok(NULL, "");
+	if (tok == NULL)
+		return -1;
+
+	int remainder = simple_strtol(tok, &endptr, 0);
+	if (*endptr != '\0')
+		return -1;
+
+	num = num * 100 + remainder;
+	if (num >> 16)
+		return -1;
+
+	field->buf[0] = (unsigned char)num;
+	field->buf[1] = num >> 8;
+
+	return 0;
+}
+
+char *months[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+		    "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
+
+/**
+ * eeprom_field_print_date() - print a field which contains date data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a date.
+ * Sample output:
+ *      Field Name      07/Feb/2014
+ *      Field Name      56/BAD/9999
+ *
+ * @field:	an initialized field to print
+ */
+void eeprom_field_print_date(const struct eeprom_field *field)
+{
+	printf(PRINT_FIELD_SEGMENT, field->name);
+	printf("%02d/", field->buf[0]);
+	if (field->buf[1] >= 1 && field->buf[1] <= 12)
+		printf("%s", months[field->buf[1] - 1]);
+	else
+		printf("BAD");
+
+	printf("/%d\n", field->buf[3] << 8 | field->buf[2]);
+}
+
+static int validate_date(unsigned char day, unsigned char month,
+			unsigned int year)
+{
+	int days_in_february;
+
+	switch (month) {
+	case 0:
+	case 2:
+	case 4:
+	case 6:
+	case 7:
+	case 9:
+	case 11:
+		if (day > 31)
+			return -1;
+		break;
+	case 3:
+	case 5:
+	case 8:
+	case 10:
+		if (day > 30)
+			return -1;
+		break;
+	case 1:
+		days_in_february = 28;
+		if (year % 4 == 0) {
+			if (year % 100 != 0)
+				days_in_february = 29;
+			else if (year % 400 == 0)
+				days_in_february = 29;
+		}
+
+		if (day > days_in_february)
+			return -1;
+
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * eeprom_field_update_date() - update a date field which contains binary data
+ *
+ * This function takes a date string in the form of x/Mon/y (x and y are both
+ * decimal values), translates it to the binary representation, then writes it
+ * to the field.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow in the
+ * year value, and checks the validity of the date.
+ *
+ * @field:	an initialized field
+ * @value:	a date string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_date(struct eeprom_field *field, char *value)
+{
+	char *endptr;
+	char *tok1 = strtok(value, "/");
+	char *tok2 = strtok(NULL, "/");
+	char *tok3 = strtok(NULL, "/");
+
+	if (tok1 == NULL || tok2 == NULL || tok3 == NULL) {
+		printf("%s: syntax error\n", field->name);
+		return -1;
+	}
+
+	unsigned char day = (unsigned char)simple_strtol(tok1, &endptr, 0);
+	if (*endptr != '\0' || day == 0) {
+		printf("%s: invalid day\n", field->name);
+		return -1;
+	}
+
+	unsigned char month;
+	for (month = 1; month <= 12; month++)
+		if (!strcmp(tok2, months[month - 1]))
+			break;
+
+	unsigned int year = simple_strtol(tok3, &endptr, 0);
+	if (*endptr != '\0') {
+		printf("%s: invalid year\n", field->name);
+		return -1;
+	}
+
+	if (validate_date(day, month - 1, year)) {
+		printf("%s: invalid date\n", field->name);
+		return -1;
+	}
+
+	if (year >> 16) {
+		printf("%s: year overflow\n", field->name);
+		return -1;
+	}
+
+	field->buf[0] = day;
+	field->buf[1] = month;
+	field->buf[2] = (unsigned char)year;
+	field->buf[3] = (unsigned char)(year >> 8);
+
+	return 0;
+}
+
+#define	LAYOUT_VERSION_LEGACY 1
+#define	LAYOUT_VERSION_VER1 2
+#define	LAYOUT_VERSION_VER2 3
+#define	LAYOUT_VERSION_VER3 4
+
+extern struct eeprom_field layout_unknown[1];
+
+#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x
+
+#ifdef CONFIG_CM_T3X
+struct eeprom_field layout_legacy[5] = {
+	{ "MAC address",          6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Board Revision",       2, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "Serial Number",        8, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,      176, NULL, eeprom_field_print_reserved,
+					   eeprom_field_update_ascii },
+};
+#else
+#define layout_legacy layout_unknown
+#endif
+
+#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517)
+struct eeprom_field layout_v1[12] = {
+	{ "Major Revision",      2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",      2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",     6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",     6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",     4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",      12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ RESERVED_FIELDS,      96, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,      64, NULL, eeprom_field_print_reserved,
+					  eeprom_field_update_ascii },
+};
+#else
+#define layout_v1 layout_unknown
+#endif
+
+struct eeprom_field layout_v2[15] = {
+	{ "Major Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",           4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",            12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ "3rd MAC Address (WIFI)",    6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Layout Version",            1, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ RESERVED_FIELDS,            83, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",             16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,            64, NULL, eeprom_field_print_reserved,
+						eeprom_field_update_ascii },
+};
+
+struct eeprom_field layout_v3[16] = {
+	{ "Major Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "Minor Revision",            2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+	{ "1st MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "2nd MAC Address",           6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Production Date",           4, NULL, DEFINE_PRINT_UPDATE(date) },
+	{ "Serial Number",            12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+	{ "3rd MAC Address (WIFI)",    6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+	{ "Layout Version",            1, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ "CompuLab EEPROM ID",        3, NULL, DEFINE_PRINT_UPDATE(bin) },
+	{ RESERVED_FIELDS,            80, NULL, DEFINE_PRINT_UPDATE(reserved) },
+	{ "Product Name",             16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #1",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #2",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ "Product Options #3",       16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+	{ RESERVED_FIELDS,            64, NULL, eeprom_field_print_reserved,
+						eeprom_field_update_ascii },
+};
+
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version)
+{
+	switch (layout->layout_version) {
+	case LAYOUT_VERSION_LEGACY:
+		layout->fields = layout_legacy;
+		layout->num_of_fields = ARRAY_SIZE(layout_legacy);
+		break;
+	case LAYOUT_VERSION_VER1:
+		layout->fields = layout_v1;
+		layout->num_of_fields = ARRAY_SIZE(layout_v1);
+		break;
+	case LAYOUT_VERSION_VER2:
+		layout->fields = layout_v2;
+		layout->num_of_fields = ARRAY_SIZE(layout_v2);
+		break;
+	case LAYOUT_VERSION_VER3:
+		layout->fields = layout_v3;
+		layout->num_of_fields = ARRAY_SIZE(layout_v3);
+		break;
+	default:
+		__eeprom_layout_assign(layout, layout_version);
+	}
+}
+
+int eeprom_parse_layout_version(char *str)
+{
+	if (!strcmp(str, "legacy"))
+		return LAYOUT_VERSION_LEGACY;
+	else if (!strcmp(str, "v1"))
+		return LAYOUT_VERSION_VER1;
+	else if (!strcmp(str, "v2"))
+		return LAYOUT_VERSION_VER2;
+	else if (!strcmp(str, "v3"))
+		return LAYOUT_VERSION_VER3;
+	else
+		return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+int eeprom_layout_detect(unsigned char *data)
+{
+	switch (data[EEPROM_LAYOUT_VER_OFFSET]) {
+	case 0xff:
+	case 0:
+		return LAYOUT_VERSION_VER1;
+	case 2:
+		return LAYOUT_VERSION_VER2;
+	case 3:
+		return LAYOUT_VERSION_VER3;
+	}
+
+	if (data[EEPROM_LAYOUT_VER_OFFSET] >= 0x20)
+		return LAYOUT_VERSION_LEGACY;
+
+	return LAYOUT_VERSION_UNRECOGNIZED;
+}
+#endif
-- 
cgit v0.10.2


From 126165312524305d1a5f2fc535e526fb92a3f8e0 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:05 +0300
Subject: arm: cm-fx6: add support for eeprom layout comands

Add support for EEPROM and EEPROM layout commands for CM-FX6.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 9a12552..1f20ec3 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -255,4 +255,15 @@
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 #endif	/* __CONFIG_CM_FX6_H */
-- 
cgit v0.10.2


From 0e656b825e76a9ac583c60c5110f9723d9a9f5d1 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:06 +0300
Subject: arm: cm-t335: add support for eeprom layout comands

Add support for EEPROM and EEPROM layout commands for CM-T335.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index c4f1d4f..6dbc9e9 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -165,6 +165,17 @@
 #define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
 #define STATUS_LED_BOOT			0
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 #ifndef CONFIG_SPL_BUILD
 /*
  * Enable PCA9555 at I2C0-0x26.
-- 
cgit v0.10.2


From 66b7e4201d90ed06ce10b7dff488c5e8932c38b2 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:07 +0300
Subject: arm: cm-t54: add support for eeprom layout comands

Add support for EEPROM and EEPROM layout commands for CM-T54.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index ac6103c..ff63d7a 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -81,6 +81,17 @@
 
 /* Enabled commands */
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 /* USB Networking options */
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
-- 
cgit v0.10.2


From 19a90ed67390f230373b736d328f5ca482f0f779 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:08 +0300
Subject: arm: cm-t3517: add support for eeprom layout comands

Add support for EEPROM and EEPROM layout commands for CM-T3517.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 7cedb67..7c087c6 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -305,4 +305,15 @@
 
 #define CONFIG_OMAP3_SPI
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
+
 #endif /* __CONFIG_H */
-- 
cgit v0.10.2


From bcb447e157edd50106a7995f7a4045a0b63914c7 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:09 +0300
Subject: arm: cm-t35: add support for eeprom layout comands

Add support for EEPROM and EEPROM layout commands for CM-T35.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 5d58116..0fb8530 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -361,4 +361,15 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
+
 #endif /* __CONFIG_H */
-- 
cgit v0.10.2


From 2d9a76b614c33e660b5556b5f96bd5ee4810953e Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:10 +0300
Subject: arm: cm-t43: add support for eeprom layout comands

Add support for EEPROM and EEPROM layout commands for CM-T43.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index ee818ed..c2dbd31 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -170,4 +170,15 @@
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
 #endif	/* __CONFIG_CM_T43_H */
-- 
cgit v0.10.2


From c40f03723fba2f77bccd92dd87fcd48c37d13cdc Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:11 +0300
Subject: eeprom: refactor i2c bus and devaddr parsing

Introduce parse_i2c_bus_addr() to generalize the parsing of i2c bus number and
i2c device address. This is done in preparation for merging layout aware and
layout unaware command parsing into one function.

No functional changes.

Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 39ebee8..54bf06c 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -207,6 +207,56 @@ int eeprom_write(unsigned dev_addr, unsigned offset,
 	return ret;
 }
 
+static int parse_numeric_param(char *str)
+{
+	char *endptr;
+	int value = simple_strtol(str, &endptr, 16);
+
+	return (*endptr != '\0') ? -1 : value;
+}
+
+/**
+ * parse_i2c_bus_addr - parse the i2c bus and i2c devaddr parameters
+ *
+ * @i2c_bus:	address to store the i2c bus
+ * @i2c_addr:	address to store the device i2c address
+ * @argc:	count of command line arguments left to parse
+ * @argv:	command line arguments left to parse
+ * @argc_no_bus_addr:	argc value we expect to see when bus & addr aren't given
+ *
+ * @returns:	number of arguments parsed or CMD_RET_USAGE if error
+ */
+static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc,
+			      char * const argv[], int argc_no_bus_addr)
+{
+	int argc_no_bus = argc_no_bus_addr + 1;
+	int argc_bus_addr = argc_no_bus_addr + 2;
+
+#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
+	if (argc == argc_no_bus_addr) {
+		*i2c_bus = -1;
+		*i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+
+		return 0;
+	}
+#endif
+	if (argc == argc_no_bus) {
+		*i2c_bus = -1;
+		*i2c_addr = parse_numeric_param(argv[0]);
+
+		return 1;
+	}
+
+	if (argc == argc_bus_addr) {
+		*i2c_bus = parse_numeric_param(argv[0]);
+		*i2c_addr = parse_numeric_param(argv[1]);
+
+		return 2;
+	}
+
+	return CMD_RET_USAGE;
+}
+
 #ifdef CONFIG_CMD_EEPROM_LAYOUT
 #include <eeprom_layout.h>
 
@@ -237,14 +287,6 @@ static enum eeprom_action parse_action(char *cmd)
 	return EEPROM_ACTION_INVALID;
 }
 
-static int parse_numeric_param(char *str)
-{
-	char *endptr;
-	int value = simple_strtol(str, &endptr, 16);
-
-	return (*endptr != '\0') ? -1 : value;
-}
-
 static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
 				  int i2c_addr, int layout_ver, char *key,
 				  char *value)
@@ -348,24 +390,9 @@ static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 #endif
 
-	switch (argc) {
-#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
-	case 5:
-		bus_addr = -1;
-		dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
-		break;
-#endif
-	case 6:
-		bus_addr = -1;
-		dev_addr = simple_strtoul(*args++, NULL, 16);
-		break;
-	case 7:
-		bus_addr = simple_strtoul(*args++, NULL, 16);
-		dev_addr = simple_strtoul(*args++, NULL, 16);
-		break;
-	default:
-		return CMD_RET_USAGE;
-	}
+	rcode = parse_i2c_bus_addr(&bus_addr, &dev_addr, argc - 2, argv + 2, 3);
+	if (rcode == CMD_RET_USAGE)
+		return rcode;
 
 	addr = simple_strtoul(*args++, NULL, 16);
 	off = simple_strtoul(*args++, NULL, 16);
-- 
cgit v0.10.2


From d92ea983b9dfc99063373c167dae6b7705bc552b Mon Sep 17 00:00:00 2001
From: Stanislav Galabov <sgalabov@gmail.com>
Date: Wed, 17 Feb 2016 15:23:29 +0200
Subject: Properly calculate ATA_SECTORWORDS, using a fixed-size integer, so it
 works for both 32-bit and 64-bit targets

Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>

diff --git a/include/ata.h b/include/ata.h
index 9d6f59c..dde377c 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -126,7 +126,7 @@
 
 #define ATA_BLOCKSIZE	512	/* bytes */
 #define ATA_BLOCKSHIFT	9	/* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
-#define ATA_SECTORWORDS	(512 / sizeof(unsigned long))
+#define ATA_SECTORWORDS	(512 / sizeof(uint32_t))
 
 #ifndef ATA_RESET_TIME
 #define ATA_RESET_TIME	60	/* spec allows up to 31 seconds */
-- 
cgit v0.10.2


From 713a9e15bba4a5b6582d5e85fef2f282782cbed7 Mon Sep 17 00:00:00 2001
From: Stanislav Galabov <sgalabov@gmail.com>
Date: Wed, 17 Feb 2016 15:23:30 +0200
Subject: Use CONFIG_IDE_SWAP_IO when running on big-endian MIPS (32 or 64-bit)
 in QEMU so that IDE transfers work properly

Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>

diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index a7cd003..702967c 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -58,6 +58,10 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_DOS_PARTITION
 
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
 #define CONFIG_SYS_IDE_MAXBUS		2
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
 #define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 394382c..2394549 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -58,6 +58,10 @@
 #define CONFIG_CMD_IDE
 #define CONFIG_DOS_PARTITION
 
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
 #define CONFIG_SYS_IDE_MAXBUS		2
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
 #define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
-- 
cgit v0.10.2


From 78757d52c8b27f7f33ab4035706796a414c81128 Mon Sep 17 00:00:00 2001
From: Stanislav Galabov <sgalabov@gmail.com>
Date: Wed, 17 Feb 2016 15:23:31 +0200
Subject: Fix FreeBSD loader API so that it works on both 32-bit and 64-bit
 targets.

Specifically tested on MIPS under QEMU (works with all  combination of bit-ness and endian-ness)

Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>

diff --git a/api/api.c b/api/api.c
index 457dc36..8a1433a 100644
--- a/api/api.c
+++ b/api/api.c
@@ -52,7 +52,7 @@ static int API_getc(va_list ap)
 {
 	int *c;
 
-	if ((c = (int *)va_arg(ap, u_int32_t)) == NULL)
+	if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	*c = getc();
@@ -68,7 +68,7 @@ static int API_tstc(va_list ap)
 {
 	int *t;
 
-	if ((t = (int *)va_arg(ap, u_int32_t)) == NULL)
+	if ((t = (int *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	*t = tstc();
@@ -84,7 +84,7 @@ static int API_putc(va_list ap)
 {
 	char *c;
 
-	if ((c = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((c = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	putc(*c);
@@ -100,7 +100,7 @@ static int API_puts(va_list ap)
 {
 	char *s;
 
-	if ((s = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((s = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	puts(s);
@@ -132,7 +132,7 @@ static int API_get_sys_info(va_list ap)
 {
 	struct sys_info *si;
 
-	si = (struct sys_info *)va_arg(ap, u_int32_t);
+	si = (struct sys_info *)va_arg(ap, uintptr_t);
 	if (si == NULL)
 		return API_ENOMEM;
 
@@ -148,7 +148,7 @@ static int API_udelay(va_list ap)
 {
 	unsigned long *d;
 
-	if ((d = (unsigned long *)va_arg(ap, u_int32_t)) == NULL)
+	if ((d = (unsigned long *)va_arg(ap, unsigned long)) == NULL)
 		return API_EINVAL;
 
 	udelay(*d);
@@ -164,11 +164,11 @@ static int API_get_timer(va_list ap)
 {
 	unsigned long *base, *cur;
 
-	cur = (unsigned long *)va_arg(ap, u_int32_t);
+	cur = (unsigned long *)va_arg(ap, unsigned long);
 	if (cur == NULL)
 		return API_EINVAL;
 
-	base = (unsigned long *)va_arg(ap, u_int32_t);
+	base = (unsigned long *)va_arg(ap, unsigned long);
 	if (base == NULL)
 		return API_EINVAL;
 
@@ -199,7 +199,7 @@ static int API_dev_enum(va_list ap)
 	struct device_info *di;
 
 	/* arg is ptr to the device_info struct we are going to fill out */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -233,7 +233,7 @@ static int API_dev_open(va_list ap)
 	int err = 0;
 
 	/* arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -265,7 +265,7 @@ static int API_dev_close(va_list ap)
 	int err = 0;
 
 	/* arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -319,7 +319,7 @@ static int API_dev_write(va_list ap)
 	int err = 0;
 
 	/* 1. arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -329,12 +329,12 @@ static int API_dev_write(va_list ap)
 		return API_ENODEV;
 
 	/* 2. arg is ptr to buffer from where to get data to write */
-	buf = (void *)va_arg(ap, u_int32_t);
+	buf = (void *)va_arg(ap, uintptr_t);
 	if (buf == NULL)
 		return API_EINVAL;
 
 	/* 3. arg is length of buffer */
-	len = (int *)va_arg(ap, u_int32_t);
+	len = (int *)va_arg(ap, uintptr_t);
 	if (len == NULL)
 		return API_EINVAL;
 	if (*len <= 0)
@@ -387,7 +387,7 @@ static int API_dev_read(va_list ap)
 	int *len_net, *act_len_net;
 
 	/* 1. arg is ptr to the device_info struct */
-	di = (struct device_info *)va_arg(ap, u_int32_t);
+	di = (struct device_info *)va_arg(ap, uintptr_t);
 	if (di == NULL)
 		return API_EINVAL;
 
@@ -397,23 +397,23 @@ static int API_dev_read(va_list ap)
 		return API_ENODEV;
 
 	/* 2. arg is ptr to buffer from where to put the read data */
-	buf = (void *)va_arg(ap, u_int32_t);
+	buf = (void *)va_arg(ap, uintptr_t);
 	if (buf == NULL)
 		return API_EINVAL;
 
 	if (di->type & DEV_TYP_STOR) {
 		/* 3. arg - ptr to var with # of blocks to read */
-		len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+		len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
 		if (!len_stor)
 			return API_EINVAL;
 		if (*len_stor <= 0)
 			return API_EINVAL;
 
 		/* 4. arg - ptr to var with start block */
-		start = (lbastart_t *)va_arg(ap, u_int32_t);
+		start = (lbastart_t *)va_arg(ap, uintptr_t);
 
 		/* 5. arg - ptr to var where to put the len actually read */
-		act_len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+		act_len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
 		if (!act_len_stor)
 			return API_EINVAL;
 
@@ -422,14 +422,14 @@ static int API_dev_read(va_list ap)
 	} else if (di->type & DEV_TYP_NET) {
 
 		/* 3. arg points to the var with length of packet to read */
-		len_net = (int *)va_arg(ap, u_int32_t);
+		len_net = (int *)va_arg(ap, uintptr_t);
 		if (!len_net)
 			return API_EINVAL;
 		if (*len_net <= 0)
 			return API_EINVAL;
 
 		/* 4. - ptr to var where to put the len actually read */
-		act_len_net = (int *)va_arg(ap, u_int32_t);
+		act_len_net = (int *)va_arg(ap, uintptr_t);
 		if (!act_len_net)
 			return API_EINVAL;
 
@@ -453,9 +453,9 @@ static int API_env_get(va_list ap)
 {
 	char *name, **value;
 
-	if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
-	if ((value = (char **)va_arg(ap, u_int32_t)) == NULL)
+	if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	*value = getenv(name);
@@ -476,9 +476,9 @@ static int API_env_set(va_list ap)
 {
 	char *name, *value;
 
-	if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
-	if ((value = (char *)va_arg(ap, u_int32_t)) == NULL)
+	if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	setenv(name, value);
@@ -498,9 +498,9 @@ static int API_env_enum(va_list ap)
 	int i, n;
 	char *last, **next;
 
-	last = (char *)va_arg(ap, u_int32_t);
+	last = (char *)va_arg(ap, unsigned long);
 
-	if ((next = (char **)va_arg(ap, u_int32_t)) == NULL)
+	if ((next = (char **)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
 	if (last == NULL)
@@ -662,14 +662,14 @@ void api_init(void)
 	}
 
 	setenv_hex("api_address", (unsigned long)sig);
-	debugf("API sig @ 0x%08x\n", sig);
+	debugf("API sig @ 0x%lX\n", (unsigned long)sig);
 	memcpy(sig->magic, API_SIG_MAGIC, 8);
 	sig->version = API_SIG_VERSION;
 	sig->syscall = &syscall;
 	sig->checksum = 0;
 	sig->checksum = crc32(0, (unsigned char *)sig,
 			      sizeof(struct api_signature));
-	debugf("syscall entry: 0x%08x\n", sig->syscall);
+	debugf("syscall entry: 0x%lX\n", (unsigned long)sig->syscall);
 }
 
 void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,
diff --git a/examples/api/Makefile b/examples/api/Makefile
index 4e9b8ea..6cffee7 100644
--- a/examples/api/Makefile
+++ b/examples/api/Makefile
@@ -11,8 +11,12 @@ ifeq ($(ARCH),arm)
 LOAD_ADDR = 0x1000000
 endif
 ifeq ($(ARCH),mips)
+ifdef CONFIG_64BIT
+LOAD_ADDR = 0xffffffff80200000
+else
 LOAD_ADDR = 0x80200000
 endif
+endif
 
 # Resulting ELF and binary exectuables will be named demo and demo.bin
 extra-y = demo
diff --git a/examples/api/crt0.S b/examples/api/crt0.S
index ced2c82..5a7049d 100644
--- a/examples/api/crt0.S
+++ b/examples/api/crt0.S
@@ -41,28 +41,29 @@ syscall:
 	ldr	pc, [ip]
 
 #elif defined(CONFIG_MIPS)
+#include <asm/asm.h>
 	.text
 	.globl __start
 	.ent __start
 __start:
-	sw	$sp, search_hint
+	PTR_S	$sp, search_hint
 	b	main
 	.end __start
 
 	.globl syscall
 	.ent syscall
 syscall:
-	sw	$ra, return_addr
-	lw	$t9, syscall_ptr
+	PTR_S	$ra, return_addr
+	PTR_L	$t9, syscall_ptr
 	jalr	$t9
 	nop
-	lw	$ra, return_addr
+	PTR_L	$ra, return_addr
 	jr	$ra
 	nop
 	.end syscall
 
 return_addr:
-	.align 4
+	.align 8
 	.long 0
 #else
 #error No support for this arch!
@@ -70,7 +71,7 @@ return_addr:
 
 	.globl syscall_ptr
 syscall_ptr:
-	.align	4
+	.align	8
 	.long	0
 
 	.globl search_hint
diff --git a/examples/api/glue.c b/examples/api/glue.c
index d619518..8aabf32 100644
--- a/examples/api/glue.c
+++ b/examples/api/glue.c
@@ -77,7 +77,7 @@ int ub_getc(void)
 {
 	int c;
 
-	if (!syscall(API_GETC, NULL, (uint32_t)&c))
+	if (!syscall(API_GETC, NULL, &c))
 		return -1;
 
 	return c;
@@ -87,7 +87,7 @@ int ub_tstc(void)
 {
 	int t;
 
-	if (!syscall(API_TSTC, NULL, (uint32_t)&t))
+	if (!syscall(API_TSTC, NULL, &t))
 		return -1;
 
 	return t;
@@ -95,12 +95,12 @@ int ub_tstc(void)
 
 void ub_putc(char c)
 {
-	syscall(API_PUTC, NULL, (uint32_t)&c);
+	syscall(API_PUTC, NULL, &c);
 }
 
 void ub_puts(const char *s)
 {
-	syscall(API_PUTS, NULL, (uint32_t)s);
+	syscall(API_PUTS, NULL, s);
 }
 
 /****************************************
@@ -126,7 +126,7 @@ struct sys_info * ub_get_sys_info(void)
 	si.mr_no = UB_MAX_MR;
 	memset(&mr, 0, sizeof(mr));
 
-	if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
+	if (!syscall(API_GET_SYS_INFO, &err, &si))
 		return NULL;
 
 	return ((err) ? NULL : &si);
@@ -344,7 +344,7 @@ char * ub_env_get(const char *name)
 {
 	char *value;
 
-	if (!syscall(API_ENV_GET, NULL, (uint32_t)name, (uint32_t)&value))
+	if (!syscall(API_ENV_GET, NULL, name, &value))
 		return NULL;
 
 	return value;
@@ -352,7 +352,7 @@ char * ub_env_get(const char *name)
 
 void ub_env_set(const char *name, char *value)
 {
-	syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
+	syscall(API_ENV_SET, NULL, name, value);
 }
 
 static char env_name[256];
@@ -369,7 +369,7 @@ const char * ub_env_enum(const char *last)
 	 * 'name=val' string), since the API_ENUM_ENV call uses envmatch()
 	 * internally, which handles such case
 	 */
-	if (!syscall(API_ENV_ENUM, NULL, (uint32_t)last, (uint32_t)&env))
+	if (!syscall(API_ENV_ENUM, NULL, last, &env))
 		return NULL;
 
 	if (!env)
@@ -396,7 +396,7 @@ int ub_display_get_info(int type, struct display_info *di)
 {
 	int err = 0;
 
-	if (!syscall(API_DISPLAY_GET_INFO, &err, (uint32_t)type, (uint32_t)di))
+	if (!syscall(API_DISPLAY_GET_INFO, &err, type, di))
 		return API_ESYSC;
 
 	return err;
-- 
cgit v0.10.2


From 4a48cfc4e57b4b247d94a614b2fbfcf03aa45ea1 Mon Sep 17 00:00:00 2001
From: Stanislav Galabov <sgalabov@gmail.com>
Date: Wed, 17 Feb 2016 15:23:33 +0200
Subject: Add support for 64-bit MIPS to examples/standalone

Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>

diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 920a0a9..0d62067 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -65,6 +65,23 @@ gd_t *global_data;
 	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "ip");
 #endif
 #elif defined(CONFIG_MIPS)
+#ifdef CONFIG_CPU_MIPS64
+/*
+ * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
+ * clobbered register that is also used to set gp ($26). Note that the
+ * jr instruction also executes the instruction immediately following
+ * it; however, GCC/mips generates an additional `nop' after each asm
+ * statement
+ */
+#define EXPORT_FUNC(f, a, x, ...) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	ld	$25, %0($26)\n"		\
+"	ld	$25, %1($25)\n"		\
+"	jr	$25\n"			\
+        : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
+#else
 /*
  * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
  * clobbered register that is also used to set gp ($26). Note that the
@@ -80,6 +97,7 @@ gd_t *global_data;
 "	lw	$25, %1($25)\n"		\
 "	jr	$25\n"			\
 	: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
+#endif
 #elif defined(CONFIG_NIOS2)
 /*
  * gp holds the pointer to the global_data, r8 is call-clobbered
-- 
cgit v0.10.2


From 1d3d0f1f1cd8bac8ea0135c92a2bcd5020abfb1d Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:52 +0800
Subject: mips: add base support for QCA/Atheros ath79 SOCs

This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fe37d1f..7162f3c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -55,6 +55,11 @@ config TARGET_PB1X00
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
 	select MIPS_TUNE_4KC
 
+config ARCH_ATH79
+	bool "Support QCA/Atheros ath79"
+	select OF_CONTROL
+	select DM
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select OF_CONTROL
@@ -67,6 +72,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index aec5a15..7a82316 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index a1ca257..3f230b0 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -23,6 +23,12 @@ struct arch_global_data {
 	unsigned long tbl;
 	unsigned long lastinc;
 #endif
+#ifdef CONFIG_ARCH_ATH79
+	unsigned long id;
+	unsigned long soc;
+	unsigned long rev;
+	unsigned long ver;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
new file mode 100644
index 0000000..7d8ce09
--- /dev/null
+++ b/arch/mips/mach-ath79/Kconfig
@@ -0,0 +1,7 @@
+menu "QCA/Atheros 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_SOC
+	default "ath79"
+
+endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
new file mode 100644
index 0000000..6203cf0
--- /dev/null
+++ b/arch/mips/mach-ath79/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
new file mode 100644
index 0000000..c6122f2
--- /dev/null
+++ b/arch/mips/mach-ath79/cpu.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+struct ath79_soc_desc {
+	enum ath79_soc_type soc;
+	const char *chip;
+	int major;
+	int minor;
+};
+
+static struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130",
+	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7130},
+	{ATH79_SOC_AR7141,      "7141",
+	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7141},
+	{ATH79_SOC_AR7161,      "7161",
+	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7161},
+	{ATH79_SOC_AR7240,      "7240", REV_ID_MAJOR_AR7240,    0},
+	{ATH79_SOC_AR7241,      "7241", REV_ID_MAJOR_AR7241,    0},
+	{ATH79_SOC_AR7242,      "7242", REV_ID_MAJOR_AR7242,    0},
+	{ATH79_SOC_AR9130,      "9130",
+	 REV_ID_MAJOR_AR913X,   AR913X_REV_ID_MINOR_AR9130},
+	{ATH79_SOC_AR9132,      "9132",
+	 REV_ID_MAJOR_AR913X,   AR913X_REV_ID_MINOR_AR9132},
+	{ATH79_SOC_AR9330,      "9330", REV_ID_MAJOR_AR9330,    0},
+	{ATH79_SOC_AR9331,      "9331", REV_ID_MAJOR_AR9331,    0},
+	{ATH79_SOC_AR9341,      "9341", REV_ID_MAJOR_AR9341,    0},
+	{ATH79_SOC_AR9342,      "9342", REV_ID_MAJOR_AR9342,    0},
+	{ATH79_SOC_AR9344,      "9344", REV_ID_MAJOR_AR9344,    0},
+	{ATH79_SOC_QCA9533,     "9533", REV_ID_MAJOR_QCA9533,   0},
+	{ATH79_SOC_QCA9533,     "9533",
+	 REV_ID_MAJOR_QCA9533_V2,       0},
+	{ATH79_SOC_QCA9556,     "9556", REV_ID_MAJOR_QCA9556,   0},
+	{ATH79_SOC_QCA9558,     "9558", REV_ID_MAJOR_QCA9558,   0},
+	{ATH79_SOC_TP9343,      "9343", REV_ID_MAJOR_TP9343,    0},
+	{ATH79_SOC_QCA9561,     "9561", REV_ID_MAJOR_QCA9561,   0},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor = 0;
+	u32 rev = 0, ver = 1;
+	int i;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+	case REV_ID_MAJOR_AR913X:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_QCA9533_V2:
+		ver = 2;
+		/* drop through */
+
+	case REV_ID_MAJOR_AR9341:
+	case REV_ID_MAJOR_AR9342:
+	case REV_ID_MAJOR_AR9344:
+	case REV_ID_MAJOR_QCA9533:
+	case REV_ID_MAJOR_QCA9556:
+	case REV_ID_MAJOR_QCA9558:
+	case REV_ID_MAJOR_TP9343:
+	case REV_ID_MAJOR_QCA9561:
+		rev = id & AR71XX_REV_ID_REVISION2_MASK;
+		break;
+	default:
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(desc); i++) {
+		if ((desc[i].major == major) &&
+		    (desc[i].minor == minor)) {
+			soc = desc[i].soc;
+			break;
+		}
+	}
+
+	gd->arch.id = id;
+	gd->arch.soc = soc;
+	gd->arch.rev = rev;
+	gd->arch.ver = ver;
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	const char *chip = "????";
+	u32 id, rev, ver;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(desc); i++) {
+		if (desc[i].soc == gd->arch.soc) {
+			chip = desc[i].chip;
+			soc = desc[i].soc;
+			break;
+		}
+	}
+
+	id = gd->arch.id;
+	rev = gd->arch.rev;
+	ver = gd->arch.ver;
+
+	switch (soc) {
+	case ATH79_SOC_QCA9533:
+	case ATH79_SOC_QCA9556:
+	case ATH79_SOC_QCA9558:
+	case ATH79_SOC_QCA9561:
+		printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
+		       ver, rev);
+		break;
+	case ATH79_SOC_TP9343:
+		printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
+		break;
+	case ATH79_SOC_UNKNOWN:
+		printf("ATH79: unknown SoC, id:0x%08x", id);
+		break;
+	default:
+		printf("Atheros AR%s rev %u\n", chip, rev);
+	}
+
+	return 0;
+}
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
new file mode 100644
index 0000000..c29e98c
--- /dev/null
+++ b/arch/mips/mach-ath79/dram.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/addrspace.h>
+#include <mach/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+	ddr_tap_tuning();
+	return get_ram_size((void *)KSEG1, SZ_256M);
+}
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
new file mode 100644
index 0000000..893dedc
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -0,0 +1,1184 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)                 (1 << (nr))
+#endif
+#endif
+
+#define AR71XX_APB_BASE                 0x18000000
+#define AR71XX_GE0_BASE                 0x19000000
+#define AR71XX_GE0_SIZE                 0x10000
+#define AR71XX_GE1_BASE                 0x1a000000
+#define AR71XX_GE1_SIZE                 0x10000
+#define AR71XX_EHCI_BASE                0x1b000000
+#define AR71XX_EHCI_SIZE                0x1000
+#define AR71XX_OHCI_BASE                0x1c000000
+#define AR71XX_OHCI_SIZE                0x1000
+#define AR71XX_SPI_BASE                 0x1f000000
+#define AR71XX_SPI_SIZE                 0x01000000
+
+#define AR71XX_DDR_CTRL_BASE            (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE            0x100
+#define AR71XX_UART_BASE                (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE                0x100
+#define AR71XX_USB_CTRL_BASE            (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE            0x100
+#define AR71XX_GPIO_BASE                (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE                0x100
+#define AR71XX_PLL_BASE                 (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE                 0x100
+#define AR71XX_RESET_BASE               (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE               0x100
+#define AR71XX_MII_BASE                 (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE                 0x100
+
+#define AR71XX_PCI_MEM_BASE             0x10000000
+#define AR71XX_PCI_MEM_SIZE             0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS            0x10000000
+#define AR71XX_PCI_WIN1_OFFS            0x11000000
+#define AR71XX_PCI_WIN2_OFFS            0x12000000
+#define AR71XX_PCI_WIN3_OFFS            0x13000000
+#define AR71XX_PCI_WIN4_OFFS            0x14000000
+#define AR71XX_PCI_WIN5_OFFS            0x15000000
+#define AR71XX_PCI_WIN6_OFFS            0x16000000
+#define AR71XX_PCI_WIN7_OFFS            0x07000000
+
+#define AR71XX_PCI_CFG_BASE \
+	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE             0x100
+
+#define AR7240_USB_CTRL_BASE            (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE            0x100
+#define AR7240_OHCI_BASE                0x1b000000
+#define AR7240_OHCI_SIZE                0x1000
+
+#define AR724X_PCI_MEM_BASE             0x10000000
+#define AR724X_PCI_MEM_SIZE             0x04000000
+
+#define AR724X_PCI_CFG_BASE             0x14000000
+#define AR724X_PCI_CFG_SIZE             0x1000
+#define AR724X_PCI_CRP_BASE             (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE             0x1000
+#define AR724X_PCI_CTRL_BASE            (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE            0x100
+
+#define AR724X_EHCI_BASE                0x1b000000
+#define AR724X_EHCI_SIZE                0x1000
+
+#define AR913X_EHCI_BASE                0x1b000000
+#define AR913X_EHCI_SIZE                0x1000
+#define AR913X_WMAC_BASE                (AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE                0x30000
+
+#define AR933X_UART_BASE                (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE                0x14
+#define AR933X_GMAC_BASE                (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE                0x04
+#define AR933X_WMAC_BASE                (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE                0x20000
+#define AR933X_RTC_BASE                 (AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_SIZE                 0x1000
+#define AR933X_EHCI_BASE                0x1b000000
+#define AR933X_EHCI_SIZE                0x1000
+#define AR933X_SRIF_BASE                (AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_SIZE                0x1000
+
+#define AR934X_GMAC_BASE                (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE                0x14
+#define AR934X_WMAC_BASE                (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE                0x20000
+#define AR934X_EHCI_BASE                0x1b000000
+#define AR934X_EHCI_SIZE                0x200
+#define AR934X_NFC_BASE                 0x1b000200
+#define AR934X_NFC_SIZE                 0xb8
+#define AR934X_SRIF_BASE                (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE                0x1000
+
+#define QCA953X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE               0x14
+#define QCA953X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE               0x20000
+#define QCA953X_RTC_BASE                (AR71XX_APB_BASE + 0x00107000)
+#define QCA953X_RTC_SIZE                0x1000
+#define QCA953X_EHCI_BASE               0x1b000000
+#define QCA953X_EHCI_SIZE               0x200
+#define QCA953X_SRIF_BASE               (AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE               0x1000
+
+#define QCA953X_PCI_CFG_BASE0           0x14000000
+#define QCA953X_PCI_CTRL_BASE0          (AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0           (AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0           0x10000000
+#define QCA953X_PCI_MEM_SIZE            0x02000000
+
+#define QCA955X_PCI_MEM_BASE0           0x10000000
+#define QCA955X_PCI_MEM_BASE1           0x12000000
+#define QCA955X_PCI_MEM_SIZE            0x02000000
+#define QCA955X_PCI_CFG_BASE0           0x14000000
+#define QCA955X_PCI_CFG_BASE1           0x16000000
+#define QCA955X_PCI_CFG_SIZE            0x1000
+#define QCA955X_PCI_CRP_BASE0           (AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1           (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE            0x1000
+#define QCA955X_PCI_CTRL_BASE0          (AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1          (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE           0x100
+
+#define QCA955X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE               0x40
+#define QCA955X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE               0x20000
+#define QCA955X_EHCI0_BASE              0x1b000000
+#define QCA955X_EHCI1_BASE              0x1b400000
+#define QCA955X_EHCI_SIZE               0x1000
+#define QCA955X_NFC_BASE                0x1b800200
+#define QCA955X_NFC_SIZE                0xb8
+
+#define QCA956X_PCI_MEM_BASE1           0x12000000
+#define QCA956X_PCI_MEM_SIZE            0x02000000
+#define QCA956X_PCI_CFG_BASE1           0x16000000
+#define QCA956X_PCI_CFG_SIZE            0x1000
+#define QCA956X_PCI_CRP_BASE1           (AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE            0x1000
+#define QCA956X_PCI_CTRL_BASE1          (AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE           0x100
+
+#define QCA956X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE               0x20000
+#define QCA956X_EHCI0_BASE              0x1b000000
+#define QCA956X_EHCI1_BASE              0x1b400000
+#define QCA956X_EHCI_SIZE               0x200
+#define QCA956X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE               0x64
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_CONFIG                           0x00
+#define AR71XX_DDR_REG_CONFIG2                          0x04
+#define AR71XX_DDR_REG_MODE                             0x08
+#define AR71XX_DDR_REG_EMR                              0x0c
+#define AR71XX_DDR_REG_CONTROL                          0x10
+#define AR71XX_DDR_REG_REFRESH                          0x14
+#define AR71XX_DDR_REG_RD_CYCLE                         0x18
+#define AR71XX_DDR_REG_TAP_CTRL0                        0x1c
+#define AR71XX_DDR_REG_TAP_CTRL1                        0x20
+
+#define AR71XX_DDR_REG_PCI_WIN0                         0x7c
+#define AR71XX_DDR_REG_PCI_WIN1                         0x80
+#define AR71XX_DDR_REG_PCI_WIN2                         0x84
+#define AR71XX_DDR_REG_PCI_WIN3                         0x88
+#define AR71XX_DDR_REG_PCI_WIN4                         0x8c
+#define AR71XX_DDR_REG_PCI_WIN5                         0x90
+#define AR71XX_DDR_REG_PCI_WIN6                         0x94
+#define AR71XX_DDR_REG_PCI_WIN7                         0x98
+#define AR71XX_DDR_REG_FLUSH_GE0                        0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1                        0xa0
+#define AR71XX_DDR_REG_FLUSH_USB                        0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI                        0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0                        0x7c
+#define AR724X_DDR_REG_FLUSH_GE1                        0x80
+#define AR724X_DDR_REG_FLUSH_USB                        0x84
+#define AR724X_DDR_REG_FLUSH_PCIE                       0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0                        0x7c
+#define AR913X_DDR_REG_FLUSH_GE1                        0x80
+#define AR913X_DDR_REG_FLUSH_USB                        0x84
+#define AR913X_DDR_REG_FLUSH_WMAC                       0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0                        0x7c
+#define AR933X_DDR_REG_FLUSH_GE1                        0x80
+#define AR933X_DDR_REG_FLUSH_USB                        0x84
+#define AR933X_DDR_REG_FLUSH_WMAC                       0x88
+#define AR933X_DDR_REG_DDR2_CONFIG                      0x8c
+#define AR933X_DDR_REG_EMR2                             0x90
+#define AR933X_DDR_REG_EMR3                             0x94
+#define AR933X_DDR_REG_BURST                            0x98
+#define AR933X_DDR_REG_TIMEOUT_MAX                      0x9c
+#define AR933X_DDR_REG_TIMEOUT_CNT                      0x9c
+#define AR933X_DDR_REG_TIMEOUT_ADDR                     0x9c
+
+#define AR934X_DDR_REG_FLUSH_GE0                        0x9c
+#define AR934X_DDR_REG_FLUSH_GE1                        0xa0
+#define AR934X_DDR_REG_FLUSH_USB                        0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE                       0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC                       0xac
+
+#define QCA953X_DDR_REG_FLUSH_GE0                       0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1                       0xa0
+#define QCA953X_DDR_REG_FLUSH_USB                       0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE                      0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC                      0xac
+#define QCA953X_DDR_REG_DDR2_CONFIG                     0xb8
+#define QCA953X_DDR_REG_BURST                           0xc4
+#define QCA953X_DDR_REG_BURST2                          0xc8
+#define QCA953X_DDR_REG_TIMEOUT_MAX                     0xcc
+#define QCA953X_DDR_REG_CTL_CONF                        0x108
+#define QCA953X_DDR_REG_CONFIG3                         0x15c
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG                       0x00
+#define AR71XX_PLL_REG_SEC_CONFIG                       0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK                   0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK                   0x14
+
+#define AR71XX_PLL_DIV_SHIFT                            3
+#define AR71XX_PLL_DIV_MASK                             0x1f
+#define AR71XX_CPU_DIV_SHIFT                            16
+#define AR71XX_CPU_DIV_MASK                             0x3
+#define AR71XX_DDR_DIV_SHIFT                            18
+#define AR71XX_DDR_DIV_MASK                             0x3
+#define AR71XX_AHB_DIV_SHIFT                            20
+#define AR71XX_AHB_DIV_MASK                             0x7
+
+#define AR71XX_ETH0_PLL_SHIFT                           17
+#define AR71XX_ETH1_PLL_SHIFT                           19
+
+#define AR724X_PLL_REG_CPU_CONFIG                       0x00
+#define AR724X_PLL_REG_PCIE_CONFIG                      0x18
+
+#define AR724X_PLL_DIV_SHIFT                            0
+#define AR724X_PLL_DIV_MASK                             0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT                        10
+#define AR724X_PLL_REF_DIV_MASK                         0xf
+#define AR724X_AHB_DIV_SHIFT                            19
+#define AR724X_AHB_DIV_MASK                             0x1
+#define AR724X_DDR_DIV_SHIFT                            22
+#define AR724X_DDR_DIV_MASK                             0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK                   0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG                       0x00
+#define AR913X_PLL_REG_ETH_CONFIG                       0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK                   0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK                   0x18
+
+#define AR913X_PLL_DIV_SHIFT                            0
+#define AR913X_PLL_DIV_MASK                             0x3ff
+#define AR913X_DDR_DIV_SHIFT                            22
+#define AR913X_DDR_DIV_MASK                             0x3
+#define AR913X_AHB_DIV_SHIFT                            19
+#define AR913X_AHB_DIV_MASK                             0x1
+
+#define AR913X_ETH0_PLL_SHIFT                           20
+#define AR913X_ETH1_PLL_SHIFT                           22
+
+#define AR933X_PLL_CPU_CONFIG_REG                       0x00
+#define AR933X_PLL_CLK_CTRL_REG                         0x08
+#define AR933X_PLL_DITHER_FRAC_REG                      0x10
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT                10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK                 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT              16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK               0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT              23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK               0x7
+
+#define AR933X_PLL_CLK_CTRL_BYPASS                      BIT(2)
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT          5
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK           0x3
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT          10
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK           0x3
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT          15
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK           0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG                       0x00
+#define AR934X_PLL_DDR_CONFIG_REG                       0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG                 0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG             0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG                 0x2c
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT               0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK                0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT                6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK                 0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT              12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK               0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT              19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK               0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT               0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK                0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT                10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK                 0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT              16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK               0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT              23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK               0x7
+
+#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS              BIT(2)
+#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS              BIT(3)
+#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS              BIT(4)
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT          5
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK           0x1f
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT          10
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK           0x1f
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT          15
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK           0x1f
+#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL          BIT(20)
+#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL          BIT(21)
+#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL          BIT(24)
+
+#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL         BIT(6)
+
+#define QCA953X_PLL_CPU_CONFIG_REG                      0x00
+#define QCA953X_PLL_DDR_CONFIG_REG                      0x04
+#define QCA953X_PLL_CLK_CTRL_REG                        0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG            0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG                0x2c
+#define QCA953X_PLL_DDR_DIT_FRAC_REG                    0x44
+#define QCA953X_PLL_CPU_DIT_FRAC_REG                    0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT              0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK               0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT               6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK                0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT              0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK               0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT               10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK                0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA953X_PLL_CONFIG_PWD                          BIT(30)
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT              0
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK               0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT              6
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK               0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT             12
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK              0x3f
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT               18
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK                0x3f
+
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT              0
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK               0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT              9
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK               0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT             20
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK              0x3f
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT               27
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK                0x3f
+
+#define QCA953X_PLL_DIT_FRAC_EN                         BIT(31)
+
+#define QCA955X_PLL_CPU_CONFIG_REG                      0x00
+#define QCA955X_PLL_DDR_CONFIG_REG                      0x04
+#define QCA955X_PLL_CLK_CTRL_REG                        0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG                0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG               0x48
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT              0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK               0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT               6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK                0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK              0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT              0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK               0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT               10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK                0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
+#define QCA956X_PLL_CPU_CONFIG_REG                      0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG                     0x04
+#define QCA956X_PLL_DDR_CONFIG_REG                      0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG                     0x0c
+#define QCA956X_PLL_CLK_CTRL_REG                        0x10
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT           0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK            0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT           5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK            0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT              18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK               0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT           0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK            0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT           5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK            0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT              18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK               0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL     BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL     BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ                       0x00
+#define AR71XX_USB_CTRL_REG_CONFIG                      0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER                          0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD                   0x04
+#define AR71XX_RESET_REG_WDOG_CTRL                      0x08
+#define AR71XX_RESET_REG_WDOG                           0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS                0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE                0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS                 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE                 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS              0x20
+#define AR71XX_RESET_REG_RESET_MODULE                   0x24
+#define AR71XX_RESET_REG_PERFC_CTRL                     0x2c
+#define AR71XX_RESET_REG_PERFC0                         0x30
+#define AR71XX_RESET_REG_PERFC1                         0x34
+#define AR71XX_RESET_REG_REV_ID                         0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS              0x18
+#define AR913X_RESET_REG_RESET_MODULE                   0x1c
+#define AR913X_RESET_REG_PERF_CTRL                      0x20
+#define AR913X_RESET_REG_PERFC0                         0x24
+#define AR913X_RESET_REG_PERFC1                         0x28
+
+#define AR724X_RESET_REG_RESET_MODULE                   0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE                   0x1c
+#define AR933X_RESET_REG_BOOTSTRAP                      0xac
+
+#define AR934X_RESET_REG_RESET_MODULE                   0x1c
+#define AR934X_RESET_REG_BOOTSTRAP                      0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS           0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE                  0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP                     0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS          0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE                  0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP                     0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS                0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE                  0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP                     0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS                0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK                  BIT(28)
+#define MISC_INT_ETHSW                                  BIT(12)
+#define MISC_INT_TIMER4                                 BIT(10)
+#define MISC_INT_TIMER3                                 BIT(9)
+#define MISC_INT_TIMER2                                 BIT(8)
+#define MISC_INT_DMA                                    BIT(7)
+#define MISC_INT_OHCI                                   BIT(6)
+#define MISC_INT_PERFC                                  BIT(5)
+#define MISC_INT_WDOG                                   BIT(4)
+#define MISC_INT_UART                                   BIT(3)
+#define MISC_INT_GPIO                                   BIT(2)
+#define MISC_INT_ERROR                                  BIT(1)
+#define MISC_INT_TIMER                                  BIT(0)
+
+#define AR71XX_RESET_EXTERNAL                           BIT(28)
+#define AR71XX_RESET_FULL_CHIP                          BIT(24)
+#define AR71XX_RESET_CPU_NMI                            BIT(21)
+#define AR71XX_RESET_CPU_COLD                           BIT(20)
+#define AR71XX_RESET_DMA                                BIT(19)
+#define AR71XX_RESET_SLIC                               BIT(18)
+#define AR71XX_RESET_STEREO                             BIT(17)
+#define AR71XX_RESET_DDR                                BIT(16)
+#define AR71XX_RESET_GE1_MAC                            BIT(13)
+#define AR71XX_RESET_GE1_PHY                            BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE                    BIT(10)
+#define AR71XX_RESET_GE0_MAC                            BIT(9)
+#define AR71XX_RESET_GE0_PHY                            BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL                       BIT(6)
+#define AR71XX_RESET_USB_HOST                           BIT(5)
+#define AR71XX_RESET_USB_PHY                            BIT(4)
+#define AR71XX_RESET_PCI_BUS                            BIT(1)
+#define AR71XX_RESET_PCI_CORE                           BIT(0)
+
+#define AR7240_RESET_USB_HOST                           BIT(5)
+#define AR7240_RESET_OHCI_DLL                           BIT(3)
+
+#define AR724X_RESET_GE1_MDIO                           BIT(23)
+#define AR724X_RESET_GE0_MDIO                           BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL                    BIT(10)
+#define AR724X_RESET_PCIE_PHY                           BIT(7)
+#define AR724X_RESET_PCIE                               BIT(6)
+#define AR724X_RESET_USB_HOST                           BIT(5)
+#define AR724X_RESET_USB_PHY                            BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE                    BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC                          BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE                    BIT(10)
+#define AR913X_RESET_USB_HOST                           BIT(5)
+#define AR913X_RESET_USB_PHY                            BIT(4)
+
+#define AR933X_RESET_GE1_MDIO                           BIT(23)
+#define AR933X_RESET_GE0_MDIO                           BIT(22)
+#define AR933X_RESET_GE1_MAC                            BIT(13)
+#define AR933X_RESET_WMAC                               BIT(11)
+#define AR933X_RESET_GE0_MAC                            BIT(9)
+#define AR933X_RESET_USB_HOST                           BIT(5)
+#define AR933X_RESET_USB_PHY                            BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE                    BIT(3)
+
+#define AR934X_RESET_HOST                               BIT(31)
+#define AR934X_RESET_SLIC                               BIT(30)
+#define AR934X_RESET_HDMA                               BIT(29)
+#define AR934X_RESET_EXTERNAL                           BIT(28)
+#define AR934X_RESET_RTC                                BIT(27)
+#define AR934X_RESET_PCIE_EP_INT                        BIT(26)
+#define AR934X_RESET_CHKSUM_ACC                         BIT(25)
+#define AR934X_RESET_FULL_CHIP                          BIT(24)
+#define AR934X_RESET_GE1_MDIO                           BIT(23)
+#define AR934X_RESET_GE0_MDIO                           BIT(22)
+#define AR934X_RESET_CPU_NMI                            BIT(21)
+#define AR934X_RESET_CPU_COLD                           BIT(20)
+#define AR934X_RESET_HOST_RESET_INT                     BIT(19)
+#define AR934X_RESET_PCIE_EP                            BIT(18)
+#define AR934X_RESET_UART1                              BIT(17)
+#define AR934X_RESET_DDR                                BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT                BIT(15)
+#define AR934X_RESET_NANDF                              BIT(14)
+#define AR934X_RESET_GE1_MAC                            BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG                  BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG                     BIT(11)
+#define AR934X_RESET_HOST_DMA_INT                       BIT(10)
+#define AR934X_RESET_GE0_MAC                            BIT(9)
+#define AR934X_RESET_ETH_SWITCH                         BIT(8)
+#define AR934X_RESET_PCIE_PHY                           BIT(7)
+#define AR934X_RESET_PCIE                               BIT(6)
+#define AR934X_RESET_USB_HOST                           BIT(5)
+#define AR934X_RESET_USB_PHY                            BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE                    BIT(3)
+#define AR934X_RESET_LUT                                BIT(2)
+#define AR934X_RESET_MBOX                               BIT(1)
+#define AR934X_RESET_I2S                                BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR                       BIT(29)
+#define QCA953X_RESET_EXTERNAL                          BIT(28)
+#define QCA953X_RESET_RTC                               BIT(27)
+#define QCA953X_RESET_FULL_CHIP                         BIT(24)
+#define QCA953X_RESET_GE1_MDIO                          BIT(23)
+#define QCA953X_RESET_GE0_MDIO                          BIT(22)
+#define QCA953X_RESET_CPU_NMI                           BIT(21)
+#define QCA953X_RESET_CPU_COLD                          BIT(20)
+#define QCA953X_RESET_DDR                               BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT               BIT(15)
+#define QCA953X_RESET_GE1_MAC                           BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG                 BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG                    BIT(11)
+#define QCA953X_RESET_GE0_MAC                           BIT(9)
+#define QCA953X_RESET_ETH_SWITCH                        BIT(8)
+#define QCA953X_RESET_PCIE_PHY                          BIT(7)
+#define QCA953X_RESET_PCIE                              BIT(6)
+#define QCA953X_RESET_USB_HOST                          BIT(5)
+#define QCA953X_RESET_USB_PHY                           BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE                   BIT(3)
+
+#define QCA955X_RESET_HOST                              BIT(31)
+#define QCA955X_RESET_SLIC                              BIT(30)
+#define QCA955X_RESET_HDMA                              BIT(29)
+#define QCA955X_RESET_EXTERNAL                          BIT(28)
+#define QCA955X_RESET_RTC                               BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT                       BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC                        BIT(25)
+#define QCA955X_RESET_FULL_CHIP                         BIT(24)
+#define QCA955X_RESET_GE1_MDIO                          BIT(23)
+#define QCA955X_RESET_GE0_MDIO                          BIT(22)
+#define QCA955X_RESET_CPU_NMI                           BIT(21)
+#define QCA955X_RESET_CPU_COLD                          BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT                    BIT(19)
+#define QCA955X_RESET_PCIE_EP                           BIT(18)
+#define QCA955X_RESET_UART1                             BIT(17)
+#define QCA955X_RESET_DDR                               BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT               BIT(15)
+#define QCA955X_RESET_NANDF                             BIT(14)
+#define QCA955X_RESET_GE1_MAC                           BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG                      BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG                    BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT                      BIT(10)
+#define QCA955X_RESET_GE0_MAC                           BIT(9)
+#define QCA955X_RESET_SGMII                             BIT(8)
+#define QCA955X_RESET_PCIE_PHY                          BIT(7)
+#define QCA955X_RESET_PCIE                              BIT(6)
+#define QCA955X_RESET_USB_HOST                          BIT(5)
+#define QCA955X_RESET_USB_PHY                           BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE                   BIT(3)
+#define QCA955X_RESET_LUT                               BIT(2)
+#define QCA955X_RESET_MBOX                              BIT(1)
+#define QCA955X_RESET_I2S                               BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN                   BIT(18)
+#define AR933X_BOOTSTRAP_DDR2                           BIT(13)
+#define AR933X_BOOTSTRAP_EEPBUSY                        BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40                     BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8                     BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7                     BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6                     BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5                     BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4                     BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3                     BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2                     BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1                     BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE                BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC                        BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE                     BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40                     BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI                  BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED                 BIT(1)
+#define AR934X_BOOTSTRAP_DDR1                           BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2                    BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1                    BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE                    BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40                    BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED                BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1                          BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40                    BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40                    BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC                  BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX                    BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP                  BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP                  BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC                    BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0                   BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1                   BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2                   BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3                   BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC                 BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX                   BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP                 BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP                 BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC                   BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0                  BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1                  BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2                  BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3                  BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC                       BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX                         BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP                       BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP                       BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1                        BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0                   BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1                   BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2                   BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3                   BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2                        BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0                   BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1                   BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2                   BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3                   BIT(16)
+#define QCA955X_EXT_INT_USB1                            BIT(24)
+#define QCA955X_EXT_INT_USB2                            BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define QCA956X_EXT_INT_WMAC_MISC                       BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX                         BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP                       BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP                       BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1                        BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0                   BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1                   BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2                   BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3                   BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2                        BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0                   BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1                   BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2                   BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3                   BIT(16)
+#define QCA956X_EXT_INT_USB1                            BIT(24)
+#define QCA956X_EXT_INT_USB2                            BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+	(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+	 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+	(QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+	 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+	 QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+	(QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+	 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+	 QCA956X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK                               0xfff0
+#define REV_ID_MAJOR_AR71XX                             0x00a0
+#define REV_ID_MAJOR_AR913X                             0x00b0
+#define REV_ID_MAJOR_AR7240                             0x00c0
+#define REV_ID_MAJOR_AR7241                             0x0100
+#define REV_ID_MAJOR_AR7242                             0x1100
+#define REV_ID_MAJOR_AR9330                             0x0110
+#define REV_ID_MAJOR_AR9331                             0x1110
+#define REV_ID_MAJOR_AR9341                             0x0120
+#define REV_ID_MAJOR_AR9342                             0x1120
+#define REV_ID_MAJOR_AR9344                             0x2120
+#define REV_ID_MAJOR_QCA9533                            0x0140
+#define REV_ID_MAJOR_QCA9533_V2                         0x0160
+#define REV_ID_MAJOR_QCA9556                            0x0130
+#define REV_ID_MAJOR_QCA9558                            0x1130
+#define REV_ID_MAJOR_TP9343                             0x0150
+#define REV_ID_MAJOR_QCA9561                            0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK                        0x3
+#define AR71XX_REV_ID_MINOR_AR7130                      0x0
+#define AR71XX_REV_ID_MINOR_AR7141                      0x1
+#define AR71XX_REV_ID_MINOR_AR7161                      0x2
+#define AR913X_REV_ID_MINOR_AR9130                      0x0
+#define AR913X_REV_ID_MINOR_AR9132                      0x1
+
+#define AR71XX_REV_ID_REVISION_MASK                     0x3
+#define AR71XX_REV_ID_REVISION_SHIFT                    2
+#define AR71XX_REV_ID_REVISION2_MASK                    0xf
+
+/*
+ * RTC block
+ */
+#define AR933X_RTC_REG_RESET                            0x40
+#define AR933X_RTC_REG_STATUS                           0x44
+#define AR933X_RTC_REG_DERIVED                          0x48
+#define AR933X_RTC_REG_FORCE_WAKE                       0x4c
+#define AR933X_RTC_REG_INT_CAUSE                        0x50
+#define AR933X_RTC_REG_CAUSE_CLR                        0x50
+#define AR933X_RTC_REG_INT_ENABLE                       0x54
+#define AR933X_RTC_REG_INT_MASKE                        0x58
+
+#define QCA953X_RTC_REG_SYNC_RESET                      0x40
+#define QCA953X_RTC_REG_SYNC_STATUS                     0x44
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS                               0x00
+#define AR71XX_SPI_REG_CTRL                             0x04
+#define AR71XX_SPI_REG_IOC                              0x08
+#define AR71XX_SPI_REG_RDS                              0x0c
+
+#define AR71XX_SPI_FS_GPIO                              BIT(0)
+
+#define AR71XX_SPI_CTRL_RD                              BIT(6)
+#define AR71XX_SPI_CTRL_DIV_MASK                        0x3f
+
+#define AR71XX_SPI_IOC_DO                               BIT(0)
+#define AR71XX_SPI_IOC_CLK                              BIT(8)
+#define AR71XX_SPI_IOC_CS(n)                            BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0                      AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1                      AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2                      AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL \
+	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE                              0x00
+#define AR71XX_GPIO_REG_IN                              0x04
+#define AR71XX_GPIO_REG_OUT                             0x08
+#define AR71XX_GPIO_REG_SET                             0x0c
+#define AR71XX_GPIO_REG_CLEAR                           0x10
+#define AR71XX_GPIO_REG_INT_MODE                        0x14
+#define AR71XX_GPIO_REG_INT_TYPE                        0x18
+#define AR71XX_GPIO_REG_INT_POLARITY                    0x1c
+#define AR71XX_GPIO_REG_INT_PENDING                     0x20
+#define AR71XX_GPIO_REG_INT_ENABLE                      0x24
+#define AR71XX_GPIO_REG_FUNC                            0x28
+#define AR933X_GPIO_REG_FUNC                            0x30
+
+#define AR934X_GPIO_REG_OUT_FUNC0                       0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1                       0x30
+#define AR934X_GPIO_REG_OUT_FUNC2                       0x34
+#define AR934X_GPIO_REG_OUT_FUNC3                       0x38
+#define AR934X_GPIO_REG_OUT_FUNC4                       0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5                       0x40
+#define AR934X_GPIO_REG_FUNC                            0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0                      0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1                      0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2                      0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3                      0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4                      0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0                     0x44
+#define QCA953X_GPIO_REG_FUNC                           0x6c
+
+#define QCA955X_GPIO_REG_OUT_FUNC0                      0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1                      0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2                      0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3                      0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4                      0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5                      0x40
+#define QCA955X_GPIO_REG_FUNC                           0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0                      0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1                      0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2                      0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3                      0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4                      0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5                      0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0                     0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3                     0x50
+#define QCA956X_GPIO_REG_FUNC                           0x6c
+
+#define AR71XX_GPIO_FUNC_STEREO_EN                      BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN                        BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN                     BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN                     BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN                        BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN                      BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN                     BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                 BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN                         BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2                     BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1                     BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN                    BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN                    BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN                    BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN                    BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN                    BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN             BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN             BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN             BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN             BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN             BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN                BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN                        BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE                   BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN                    BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN                 BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN                   BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN                      BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN                        BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN                        BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN                        BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN                 BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN                        BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN                     BIT(4)
+
+#define AR933X_GPIO(x)                                  BIT(x)
+#define AR933X_GPIO_FUNC_SPDIF2TCK                      BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN                       BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN                  BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN                     BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN                        BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL            BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL            BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT             BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN                         BIT(18)
+#define AR933X_GPIO_FUNC_RES_TRUE                       BIT(15)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2                     BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1                     BIT(13)
+#define AR933X_GPIO_FUNC_XLNA_EN                        BIT(12)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN             BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN             BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN             BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN             BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN             BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN                BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN                        BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE                   BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN                    BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN                    BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN                    BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN                    BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN                    BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN                    BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN                    BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN                    BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE                   BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO                            0
+#define AR934X_GPIO_OUT_SPI_CS1                         7
+#define AR934X_GPIO_OUT_LED_LINK0                       41
+#define AR934X_GPIO_OUT_LED_LINK1                       42
+#define AR934X_GPIO_OUT_LED_LINK2                       43
+#define AR934X_GPIO_OUT_LED_LINK3                       44
+#define AR934X_GPIO_OUT_LED_LINK4                       45
+#define AR934X_GPIO_OUT_EXT_LNA0                        46
+#define AR934X_GPIO_OUT_EXT_LNA1                        47
+
+#define QCA953X_GPIO(x)                                 BIT(x)
+#define QCA953X_GPIO_MUX_MASK(x)                        (0xff << (x))
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1                    10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2                    11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0                    9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK                    8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI                   12
+#define QCA953X_GPIO_OUT_MUX_UART0_SOUT                 22
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1                  41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2                  42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3                  43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4                  44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5                  45
+
+#define QCA953X_GPIO_IN_MUX_UART0_SIN                   9
+#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN                 8
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO                    32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC                    33
+
+#define AR71XX_GPIO_COUNT                               16
+#define AR7240_GPIO_COUNT                               18
+#define AR7241_GPIO_COUNT                               20
+#define AR913X_GPIO_COUNT                               22
+#define AR933X_GPIO_COUNT                               30
+#define AR934X_GPIO_COUNT                               23
+#define QCA953X_GPIO_COUNT                              18
+#define QCA955X_GPIO_COUNT                              24
+#define QCA956X_GPIO_COUNT                              23
+
+/*
+ * SRIF block
+ */
+#define AR933X_SRIF_DDR_DPLL1_REG                       0x240
+#define AR933X_SRIF_DDR_DPLL2_REG                       0x244
+#define AR933X_SRIF_DDR_DPLL3_REG                       0x248
+#define AR933X_SRIF_DDR_DPLL4_REG                       0x24c
+
+#define AR934X_SRIF_CPU_DPLL1_REG                       0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG                       0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG                       0x1c8
+
+#define AR934X_SRIF_DDR_DPLL1_REG                       0x240
+#define AR934X_SRIF_DDR_DPLL2_REG                       0x244
+#define AR934X_SRIF_DDR_DPLL3_REG                       0x248
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT                  27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK                   0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT                    18
+#define AR934X_SRIF_DPLL1_NINT_MASK                     0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK                    0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL                     BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT                  13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK                   0x7
+
+#define QCA953X_SRIF_BB_DPLL1_REG                       0x180
+#define QCA953X_SRIF_BB_DPLL2_REG                       0x184
+#define QCA953X_SRIF_BB_DPLL3_REG                       0x188
+
+#define QCA953X_SRIF_CPU_DPLL1_REG                      0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG                      0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG                      0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG                      0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG                      0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG                      0x248
+
+#define QCA953X_SRIF_PCIE_DPLL1_REG                     0xc00
+#define QCA953X_SRIF_PCIE_DPLL2_REG                     0xc04
+#define QCA953X_SRIF_PCIE_DPLL3_REG                     0xc08
+
+#define QCA953X_SRIF_PMU1_REG                           0xc40
+#define QCA953X_SRIF_PMU2_REG                           0xc44
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT                 27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK                  0x1f
+
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT                   18
+#define QCA953X_SRIF_DPLL1_NINT_MASK                    0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK                   0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL                    BIT(30)
+
+#define QCA953X_SRIF_DPLL2_KI_SHIFT                     29
+#define QCA953X_SRIF_DPLL2_KI_MASK                      0x3
+
+#define QCA953X_SRIF_DPLL2_KD_SHIFT                     25
+#define QCA953X_SRIF_DPLL2_KD_MASK                      0xf
+
+#define QCA953X_SRIF_DPLL2_PWD                          BIT(22)
+
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT                 13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK                  0x7
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL                        0x00
+#define AR71XX_MII_REG_MII1_CTRL                        0x04
+
+#define AR71XX_MII_CTRL_IF_MASK                         3
+#define AR71XX_MII_CTRL_SPEED_SHIFT                     4
+#define AR71XX_MII_CTRL_SPEED_MASK                      3
+#define AR71XX_MII_CTRL_SPEED_10                        0
+#define AR71XX_MII_CTRL_SPEED_100                       1
+#define AR71XX_MII_CTRL_SPEED_1000                      2
+
+#define AR71XX_MII0_CTRL_IF_GMII                        0
+#define AR71XX_MII0_CTRL_IF_MII                         1
+#define AR71XX_MII0_CTRL_IF_RGMII                       2
+#define AR71XX_MII0_CTRL_IF_RMII                        3
+
+#define AR71XX_MII1_CTRL_IF_RGMII                       0
+#define AR71XX_MII1_CTRL_IF_RMII                        1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG                         0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0                        BIT(0)
+#define AR933X_ETH_CFG_MII_GE0                          BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0                         BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER                   BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE                    BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN                   BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP                      BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP                 BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0                         BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10                  0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100                 BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG                         0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0                      BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0                        BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0                       BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER                 BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE                  BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN                 BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE                     BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP                      BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS                    BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0                       BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED                   BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER                BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST                 BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY                        BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK                   0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT                  14
+#define AR934X_ETH_CFG_RDV_DELAY                        BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK                   0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT                  16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG                        0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE                    BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP                     BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS                   BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST                BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG                        0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN                        BIT(0)
+#define QCA955X_ETH_CFG_GE0_SGMII                       BIT(6)
+
+#endif /* __ASM_AR71XX_H */
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
new file mode 100644
index 0000000..90d80b8
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -0,0 +1,143 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type {
+	ATH79_SOC_UNKNOWN,
+	ATH79_SOC_AR7130,
+	ATH79_SOC_AR7141,
+	ATH79_SOC_AR7161,
+	ATH79_SOC_AR7240,
+	ATH79_SOC_AR7241,
+	ATH79_SOC_AR7242,
+	ATH79_SOC_AR9130,
+	ATH79_SOC_AR9132,
+	ATH79_SOC_AR9330,
+	ATH79_SOC_AR9331,
+	ATH79_SOC_AR9341,
+	ATH79_SOC_AR9342,
+	ATH79_SOC_AR9344,
+	ATH79_SOC_QCA9533,
+	ATH79_SOC_QCA9556,
+	ATH79_SOC_QCA9558,
+	ATH79_SOC_TP9343,
+	ATH79_SOC_QCA9561,
+};
+
+static inline int soc_is_ar71xx(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7130 ||
+		gd->arch.soc == ATH79_SOC_AR7141 ||
+		gd->arch.soc == ATH79_SOC_AR7161;
+}
+
+static inline int soc_is_ar724x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7240 ||
+		gd->arch.soc == ATH79_SOC_AR7241 ||
+		gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar7240(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7240;
+}
+
+static inline int soc_is_ar7241(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7241;
+}
+
+static inline int soc_is_ar7242(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar913x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9130 ||
+		gd->arch.soc == ATH79_SOC_AR9132;
+}
+
+static inline int soc_is_ar933x(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9330 ||
+		gd->arch.soc == ATH79_SOC_AR9331;
+}
+
+static inline int soc_is_ar9341(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9341;
+}
+
+static inline int soc_is_ar9342(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9342;
+}
+
+static inline int soc_is_ar9344(void)
+{
+	return gd->arch.soc == ATH79_SOC_AR9344;
+}
+
+static inline int soc_is_ar934x(void)
+{
+	return soc_is_ar9341() ||
+		soc_is_ar9342() ||
+		soc_is_ar9344();
+}
+
+static inline int soc_is_qca9533(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+	return soc_is_qca9533();
+}
+
+static inline int soc_is_qca9556(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+	return soc_is_qca9556() || soc_is_qca9558();
+}
+
+static inline int soc_is_tp9343(void)
+{
+	return gd->arch.soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+	return gd->arch.soc == ATH79_SOC_QCA9561;
+}
+
+static inline int soc_is_qca956x(void)
+{
+	return soc_is_tp9343() || soc_is_qca9561();
+}
+
+#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h
new file mode 100644
index 0000000..181179a
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ddr.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_DDR_H
+#define __ASM_MACH_DDR_H
+
+void ddr_init(void);
+void ddr_tap_tuning(void);
+
+#endif /* __ASM_MACH_DDR_H */
diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h
new file mode 100644
index 0000000..c383bfe
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/reset.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_RESET_H
+#define __ASM_MACH_RESET_H
+
+#include <linux/types.h>
+
+u32 get_bootstrap(void);
+
+#endif /* __ASM_MACH_RESET_H */
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
new file mode 100644
index 0000000..2ea2f8d
--- /dev/null
+++ b/arch/mips/mach-ath79/reset.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+void _machine_restart(void)
+{
+	void __iomem *base;
+	u32 reg = 0;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+	if (soc_is_ar71xx())
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x())
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x())
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca955x())
+		reg = QCA955X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x())
+		reg = QCA956X_RESET_REG_RESET_MODULE;
+	else
+		puts("Reset register not defined for this SOC\n");
+
+	if (reg)
+		setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
+
+	while (1)
+		/* NOP */;
+}
+
+u32 get_bootstrap(void)
+{
+	const void __iomem *base;
+	u32 reg = 0;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+	if (soc_is_ar933x())
+		reg = AR933X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_ar934x())
+		reg = AR934X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_qca953x())
+		reg = QCA953X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_qca955x())
+		reg = QCA955X_RESET_REG_BOOTSTRAP;
+	else if (soc_is_qca956x())
+		reg = QCA956X_RESET_REG_BOOTSTRAP;
+	else
+		puts("Bootstrap register not defined for this SOC\n");
+
+	if (reg)
+		return readl(base + reg);
+
+	return 0;
+}
-- 
cgit v0.10.2


From ee7bb5be35af71df46733b0b3f3e8c96b7b4066d Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:53 +0800
Subject: mips: ath79: add support for AR933x SOCs

This patch enable work for ar933x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 7d8ce09..ab93d92 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -4,4 +4,13 @@ menu "QCA/Atheros 7xxx/9xxx platforms"
 config SYS_SOC
 	default "ath79"
 
+config SOC_AR933X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_TUNE_24KC
+	help
+	  This supports QCA/Atheros ar933x family SOCs.
+
 endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 6203cf0..9b9447e 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -5,3 +5,5 @@
 obj-y += reset.o
 obj-y += cpu.o
 obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X)	+= ar933x/
\ No newline at end of file
diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile
new file mode 100644
index 0000000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
new file mode 100644
index 0000000..9fcd496
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 ar933x_get_xtal(void)
+{
+	u32 val;
+
+	val = get_bootstrap();
+	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return ar933x_get_xtal();
+}
+
+int get_clocks(void)
+{
+	void __iomem *regs;
+	u32 val, xtal, pll, div;
+
+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+	xtal = ar933x_get_xtal();
+	val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
+
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_NINT_MASK;
+	pll *= div;
+	div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+			& AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
+
+	/* CPU_CLK = PLLOUT / CPU_POST_DIV */
+	div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+			& AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+	gd->cpu_clk = pll / div;
+
+	/* DDR_CLK = PLLOUT / DDR_POST_DIV */
+	div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+			& AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+	gd->mem_clk = pll / div;
+
+	/* AHB_CLK = PLLOUT / AHB_POST_DIV */
+	div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+			& AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+	gd->bus_clk = pll / div;
+
+	return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	if (!gd->bus_clk)
+		get_clocks();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	if (!gd->mem_clk)
+		get_clocks();
+	return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
new file mode 100644
index 0000000..74e8e80
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S      BIT(5)
+#define DDR_CTRL_UPD_EMR2S      BIT(4)
+#define DDR_CTRL_PRECHARGE      BIT(3)
+#define DDR_CTRL_AUTO_REFRESH   BIT(2)
+#define DDR_CTRL_UPD_EMRS       BIT(1)
+#define DDR_CTRL_UPD_MRS        BIT(0)
+
+#define DDR_REFRESH_EN          (1 << 14)
+#define DDR_REFRESH_M           0x3ff
+#define DDR_REFRESH(x)          ((x) & 0x3ff)
+#define DDR_REFRESH_VAL_25M     (DDR_REFRESH_EN | DDR_REFRESH(390))
+#define DDR_REFRESH_VAL_40M     (DDR_REFRESH_EN | DDR_REFRESH(624))
+
+#define DDR_TRAS_S              0
+#define DDR_TRAS_M              0x1f
+#define DDR_TRAS(x)             ((x) << DDR_TRAS_S)
+#define DDR_TRCD_M              0xf
+#define DDR_TRCD_S              5
+#define DDR_TRCD(x)             ((x) << DDR_TRCD_S)
+#define DDR_TRP_M               0xf
+#define DDR_TRP_S               9
+#define DDR_TRP(x)              ((x) << DDR_TRP_S)
+#define DDR_TRRD_M              0xf
+#define DDR_TRRD_S              13
+#define DDR_TRRD(x)             ((x) << DDR_TRRD_S)
+#define DDR_TRFC_M              0x7f
+#define DDR_TRFC_S              17
+#define DDR_TRFC(x)             ((x) << DDR_TRFC_S)
+#define DDR_TMRD_M              0xf
+#define DDR_TMRD_S              23
+#define DDR_TMRD(x)             ((x) << DDR_TMRD_S)
+#define DDR_CAS_L_M             0x17
+#define DDR_CAS_L_S             27
+#define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN                (1 << 30)
+#define DDR_CONF_REG_VAL        (DDR_TRAS(16) | DDR_TRCD(6) | \
+				 DDR_TRP(6) | DDR_TRRD(4) | \
+				 DDR_TRFC(30) | DDR_TMRD(15) | \
+				 DDR_CAS_L(7) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S         0
+#define DDR_BURST_LEN_M         0xf
+#define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE          (1 << 4)
+#define DDR_CNTL_OE_EN          (1 << 5)
+#define DDR_PHASE_SEL           (1 << 6)
+#define DDR_CKE                 (1 << 7)
+#define DDR_TWR_S               8
+#define DDR_TWR_M               0xf
+#define DDR_TWR(x)              ((x) << DDR_TWR_S)
+#define DDR_TRTW_S              12
+#define DDR_TRTW_M              0x1f
+#define DDR_TRTW(x)             ((x) << DDR_TRTW_S)
+#define DDR_TRTP_S              17
+#define DDR_TRTP_M              0xf
+#define DDR_TRTP(x)             ((x) << DDR_TRTP_S)
+#define DDR_TWTR_S              21
+#define DDR_TWTR_M              0x1f
+#define DDR_TWTR(x)             ((x) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S          26
+#define DDR_G_OPEN_L_M          0xf
+#define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW      (1 << 31)
+#define DDR_CONF2_REG_VAL       (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+				 DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
+				 DDR_TRTP(8) | DDR_TWTR(14) | \
+				 DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
+
+#define DDR2_CONF_TWL_S         10
+#define DDR2_CONF_TWL_M         0xf
+#define DDR2_CONF_TWL(x)        (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT           BIT(9)
+#define DDR2_CONF_TFAW_S        2
+#define DDR2_CONF_TFAW_M        0x3f
+#define DDR2_CONF_TFAW(x)       (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN            BIT(0)
+#define DDR2_CONF_VAL           (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
+				 DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL       0x02
+#define DDR2_EXT_MODE_VAL       0x402
+#define DDR2_EXT_MODE_OCD_VAL   0x382
+#define DDR1_MODE_DLL_VAL       0x133
+#define DDR2_MODE_DLL_VAL       0x100
+#define DDR1_MODE_VAL           0x33
+#define DDR2_MODE_VAL           0xa33
+#define DDR_TAP_VAL0            0x08
+#define DDR_TAP_VAL1            0x09
+
+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+
+	val = get_bootstrap();
+	if (val & AR933X_BOOTSTRAP_DDR2) {
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+		/* Enable DDR2 */
+		writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Disable High Temperature Self-Refresh, Full Array */
+		writel(0x00, regs + AR933X_DDR_REG_EMR2);
+
+		/* Extended Mode Register 2 Set (EMR2S) */
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+
+		writel(0x00, regs + AR933X_DDR_REG_EMR3);
+
+		/* Extended Mode Register 3 Set (EMR3S) */
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL,  Full strength, ODT Disabled */
+		writel(0x00, regs + AR71XX_DDR_REG_EMR);
+
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Reset DLL */
+		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
+		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Refresh time control */
+		if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+			writel(DDR_REFRESH_VAL_40M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+		else
+			writel(DDR_REFRESH_VAL_25M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+
+		/* DQS 0 Tap Control */
+		writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* For 16-bit DDR */
+		writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+	} else {
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Reset DLL, Burst Length 8, CAS Latency 3 */
+		writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+
+		/* Forces an MRS update cycle in DDR */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL, Full strength */
+		writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Normal DLL, Burst Length 8, CAS Latency 3 */
+		writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Refresh time control */
+		if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+			writel(DDR_REFRESH_VAL_40M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+		else
+			writel(DDR_REFRESH_VAL_25M, regs +
+			       AR71XX_DDR_REG_REFRESH);
+
+		/* DQS 0 Tap Control */
+		writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* For 16-bit DDR */
+		writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+	}
+}
+
+void ddr_tap_tuning(void)
+{
+	void __iomem *regs;
+	u32 *addr_k0, *addr_k1, *addr;
+	u32 val, tap, upper, lower;
+	int i, j, dir, err, done;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	/* Init memory pattern */
+	addr = (void *)CKSEG0ADDR(0x2000);
+	for (i = 0; i < 256; i++) {
+		val = 0;
+		for (j = 0; j < 8; j++) {
+			if (i & (1 << j)) {
+				if (j % 2)
+					val |= 0xffff0000;
+				else
+					val |= 0x0000ffff;
+			}
+
+			if (j % 2) {
+				*addr++ = val;
+				val = 0;
+			}
+		}
+	}
+
+	err = 0;
+	done = 0;
+	dir = 1;
+	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val = tap;
+	while (!done) {
+		err = 0;
+
+		/* Update new DDR tap value */
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		/* Compare DDR with cache */
+		for (i = 0; i < 2; i++) {
+			addr_k1 = (void *)CKSEG1ADDR(0x2000);
+			addr_k0 = (void *)CKSEG0ADDR(0x2000);
+			addr = (void *)CKSEG0ADDR(0x3000);
+
+			while (addr_k0 < addr) {
+				if (*addr_k1++ != *addr_k0++) {
+					err = 1;
+					break;
+				}
+			}
+
+			if (err)
+				break;
+		}
+
+		if (err) {
+			/* Save upper/lower threshold if error  */
+			if (dir) {
+				dir = 0;
+				val--;
+				upper = val;
+				val = tap;
+			} else {
+				val++;
+				lower = val;
+				done = 1;
+			}
+		} else {
+			/* Try the next value until limitation */
+			if (dir) {
+				if (val < 0x20) {
+					val++;
+				} else {
+					dir = 0;
+					upper = val;
+					val = tap;
+				}
+			} else {
+				if (!val) {
+					lower = val;
+					done = 1;
+				} else {
+					val--;
+				}
+			}
+		}
+	}
+
+	/* compute an intermediate value and write back */
+	val = (upper + lower) / 2;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val++;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
new file mode 100644
index 0000000..1b847f5
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK and u-boot_mod project
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
+#define SET_PLL_PD(val)     SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val)     SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
+ *                      =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
+ * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
+ *                      =>  1   (0x1)   [Must start at values 1]
+ * bits 21      (1bit)  RANGE   (VCO frequency range of the CPU PLL)
+ *                      =>  0   (0x0)   [Doesn't impact clock values]
+ * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
+ *                      =>  1   (0x1)   [0 is illegal!]
+ *                              PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2       (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
+ *                      Software must enable the CPU PLL for normal and
+ *                      then set this bit to 0)
+ * bits 5..6    (2bit)  CPU_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11  (2bit)  DDR_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16  (2bit)  AHB_POST_DIV    =>  1   (DEFAULT, Ratio = 2)
+ *                      AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+	/* These three WLAN_RESET will avoid original issue */
+	li      t3, 0x03
+1:
+	li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+	lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	ori     t1, t1, 0x0800
+	sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	nop
+	lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0xfffff7ff
+	and     t1, t1, t2
+	sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+	nop
+	addi    t3, t3, -1
+	bnez    t3, 1b
+	nop
+
+	li      t2, 0x20
+2:
+	beqz    t2, 1b
+	nop
+	addi    t2, t2, -1
+	lw      t5, AR933X_RESET_REG_BOOTSTRAP(t0)
+	andi    t1, t5, 0x10
+	bnez    t1, 2b
+	nop
+
+	li      t1, 0x02110E
+	sw      t1, AR933X_RESET_REG_BOOTSTRAP(t0)
+	nop
+
+	/* RTC Force Wake */
+	li      t0, CKSEG1ADDR(AR933X_RTC_BASE)
+	li      t1, 0x03
+	sw      t1, AR933X_RTC_REG_FORCE_WAKE(t0)
+	nop
+	nop
+
+	/* RTC Reset */
+	li      t1, 0x00
+	sw      t1, AR933X_RTC_REG_RESET(t0)
+	nop
+	nop
+
+	li      t1, 0x01
+	sw      t1, AR933X_RTC_REG_RESET(t0)
+	nop
+	nop
+
+	/* Wait for RTC in on state */
+1:
+	lw      t1, AR933X_RTC_REG_STATUS(t0)
+	andi    t1, t1, 0x02
+	beqz    t1, 1b
+	nop
+
+	/* Program ki/kd */
+	li      t0, CKSEG1ADDR(AR933X_SRIF_BASE)
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, 0x19e82f01
+	b       2f
+	nop
+1:
+	li      t1, 0x18e82f01
+2:
+	sw      t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
+
+	/* Program phase shift */
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0xc07fffff
+	and     t1, t1, t2
+	li      t2, 0x800000
+	or      t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	/* in some cases, the SoC doesn't start with higher clock on AHB */
+	li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+	li      t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
+	sw      t1, AR933X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	/* Set SETTLE_TIME in CPU PLL */
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, 0x0352
+	b       2f
+	nop
+1:
+	li      t1, 0x0550
+2:
+	sw      t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
+	nop
+
+	/* Set nint, frac, refdiv, outdiv, range according to xtal */
+0:
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
+	b       2f
+	nop
+1:
+	li      t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
+2:
+	sw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	nop
+1:
+	lw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, 0x80000000
+	and     t1, t1, t2
+	bnez    t1, 1b
+	nop
+
+	/* Put frac bit19:10 configuration */
+	li      t1, 0x1003E8
+	sw      t1, AR933X_PLL_DITHER_FRAC_REG(t0)
+	nop
+
+	/* Clear PLL power down bit in CPU PLL configuration */
+	andi    t1, t5, 0x01            # t5 BOOT_STRAP
+	bnez    t1, 1f
+	nop
+	li      t1, PLL_CPU_CONFIG_VAL_25M
+	b       2f
+	nop
+1:
+	li      t1, PLL_CPU_CONFIG_VAL_40M
+2:
+	sw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	/* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
+1:
+	lw      t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, 0x80000000
+	and     t1, t1, t2
+	bnez    t1, 1b
+	nop
+
+	/* Confirm DDR PLL lock */
+	li      t3, 100
+	li      t4, 0
+
+2:
+	addi    t4, t4, 1
+	bgt     t4, t3, 0b
+	nop
+
+	li      t3, 5
+3:
+	/* Clear do_meas */
+	li      t0, CKSEG1ADDR(AR933X_SRIF_BASE)
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0xBFFFFFFF
+	and     t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	li      t2, 10
+1:
+	subu    t2, t2, 1
+	bnez    t2, 1b
+	nop
+
+	/* Set do_meas */
+	li      t2, 0x40000000
+	or      t1, t1, t2
+	sw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	nop
+
+	/* Check meas_done */
+1:
+	lw      t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
+	andi    t1, t1, 0x8
+	beqz    t1, 1b
+	nop
+
+	lw      t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+	li      t2, 0x007FFFF8
+	and     t1, t1, t2
+	srl     t1, t1, 3
+	li      t2, 0x4000
+	bgt     t1, t2, 2b
+	nop
+	addi    t3, t3, -1
+	bnez    t3, 3b
+	nop
+
+	/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+	li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+	li      t1, PLL_CLK_CONTROL_VAL
+	sw      t1, AR933X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	nop
+	jr ra
+	nop
+    END(lowlevel_init)
-- 
cgit v0.10.2


From 9b03f802ae63cf9c053c0125a1edd2b4c7852b9a Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:54 +0800
Subject: mips: ath79: add support for QCA953x SOCs

This patch enable work for qca953x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index ab93d92..e35f1b5 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -13,4 +13,13 @@ config SOC_AR933X
 	help
 	  This supports QCA/Atheros ar933x family SOCs.
 
+config SOC_QCA953X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_TUNE_24KC
+	help
+	  This supports QCA/Atheros qca953x family SOCs.
+
 endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 9b9447e..160dfaa 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -6,4 +6,5 @@ obj-y += reset.o
 obj-y += cpu.o
 obj-y += dram.o
 
-obj-$(CONFIG_SOC_AR933X)	+= ar933x/
\ No newline at end of file
+obj-$(CONFIG_SOC_AR933X)	+= ar933x/
+obj-$(CONFIG_SOC_QCA953X)	+= qca953x/
\ No newline at end of file
diff --git a/arch/mips/mach-ath79/qca953x/Makefile b/arch/mips/mach-ath79/qca953x/Makefile
new file mode 100644
index 0000000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
new file mode 100644
index 0000000..ef0a28e
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 qca953x_get_xtal(void)
+{
+	u32 val;
+
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+	void __iomem *regs;
+	u32 val, ctrl, xtal, pll, div;
+
+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	xtal = qca953x_get_xtal();
+	ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+	val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
+
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+			& QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
+			& QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+	pll *= div;
+	div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+			& QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	/* CPU_CLK = PLLOUT / CPU_POST_DIV */
+	div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+			& QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+	gd->cpu_clk = pll / div;
+
+
+	val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
+	/* VCOOUT = XTAL * DIV_INT */
+	div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
+			& QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+	pll = xtal / div;
+
+	/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+	div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
+			& QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+	pll *= div;
+	div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
+			& QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+	if (!div)
+		div = 1;
+	pll >>= div;
+
+	/* DDR_CLK = PLLOUT / DDR_POST_DIV */
+	div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+			& QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+	gd->mem_clk = pll / div;
+
+	div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+			& QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+	if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
+		/* AHB_CLK = DDR_CLK / AHB_POST_DIV */
+		gd->bus_clk = gd->mem_clk / (div + 1);
+	} else {
+		/* AHB_CLK = CPU_CLK / AHB_POST_DIV */
+		gd->bus_clk = gd->cpu_clk / (div + 1);
+	}
+
+	return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	if (!gd->bus_clk)
+		get_clocks();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	if (!gd->mem_clk)
+		get_clocks();
+	return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
new file mode 100644
index 0000000..ac0130c
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -0,0 +1,472 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S      BIT(5)
+#define DDR_CTRL_UPD_EMR2S      BIT(4)
+#define DDR_CTRL_PRECHARGE      BIT(3)
+#define DDR_CTRL_AUTO_REFRESH   BIT(2)
+#define DDR_CTRL_UPD_EMRS       BIT(1)
+#define DDR_CTRL_UPD_MRS        BIT(0)
+
+#define DDR_REFRESH_EN          BIT(14)
+#define DDR_REFRESH_M           0x3ff
+#define DDR_REFRESH(x)          ((x) & DDR_REFRESH_M)
+#define DDR_REFRESH_VAL         (DDR_REFRESH_EN | DDR_REFRESH(312))
+
+#define DDR_TRAS_S              0
+#define DDR_TRAS_M              0x1f
+#define DDR_TRAS(x)             (((x) & DDR_TRAS_M) << DDR_TRAS_S)
+#define DDR_TRCD_M              0xf
+#define DDR_TRCD_S              5
+#define DDR_TRCD(x)             (((x) & DDR_TRCD_M) << DDR_TRCD_S)
+#define DDR_TRP_M               0xf
+#define DDR_TRP_S               9
+#define DDR_TRP(x)              (((x) & DDR_TRP_M) << DDR_TRP_S)
+#define DDR_TRRD_M              0xf
+#define DDR_TRRD_S              13
+#define DDR_TRRD(x)             (((x) & DDR_TRRD_M) << DDR_TRRD_S)
+#define DDR_TRFC_M              0x7f
+#define DDR_TRFC_S              17
+#define DDR_TRFC(x)             (((x) & DDR_TRFC_M) << DDR_TRFC_S)
+#define DDR_TMRD_M              0xf
+#define DDR_TMRD_S              23
+#define DDR_TMRD(x)             (((x) & DDR_TMRD_M) << DDR_TMRD_S)
+#define DDR_CAS_L_M             0x17
+#define DDR_CAS_L_S             27
+#define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN                BIT(30)
+#define DDR1_CONF_REG_VAL       (DDR_TRAS(16) | DDR_TRCD(6) | \
+				 DDR_TRP(6) | DDR_TRRD(4) | \
+				 DDR_TRFC(7) | DDR_TMRD(5) | \
+				 DDR_CAS_L(7) | DDR_OPEN)
+#define DDR2_CONF_REG_VAL       (DDR_TRAS(27) | DDR_TRCD(9) | \
+				 DDR_TRP(9) | DDR_TRRD(7) | \
+				 DDR_TRFC(21) | DDR_TMRD(15) | \
+				 DDR_CAS_L(17) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S         0
+#define DDR_BURST_LEN_M         0xf
+#define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE          BIT(4)
+#define DDR_CNTL_OE_EN          BIT(5)
+#define DDR_PHASE_SEL           BIT(6)
+#define DDR_CKE                 BIT(7)
+#define DDR_TWR_S               8
+#define DDR_TWR_M               0xf
+#define DDR_TWR(x)              (((x) & DDR_TWR_M) << DDR_TWR_S)
+#define DDR_TRTW_S              12
+#define DDR_TRTW_M              0x1f
+#define DDR_TRTW(x)             (((x) & DDR_TRTW_M) << DDR_TRTW_S)
+#define DDR_TRTP_S              17
+#define DDR_TRTP_M              0xf
+#define DDR_TRTP(x)             (((x) & DDR_TRTP_M) << DDR_TRTP_S)
+#define DDR_TWTR_S              21
+#define DDR_TWTR_M              0x1f
+#define DDR_TWTR(x)             (((x) & DDR_TWTR_M) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S          26
+#define DDR_G_OPEN_L_M          0xf
+#define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW      BIT(31)
+#define DDR1_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+				 DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
+				 DDR_TRTP(8) | DDR_TWTR(14) | \
+				 DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
+#define DDR2_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+				 DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
+				 DDR_TRTP(9) | DDR_TWTR(21) | \
+				 DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
+
+#define DDR_TWR_MSB             BIT(3)
+#define DDR_TRAS_MSB            BIT(2)
+#define DDR_TRFC_MSB_M          0x3
+#define DDR_TRFC_MSB(x)         (x)
+#define DDR1_CONF3_REG_VAL      0
+#define DDR2_CONF3_REG_VAL      (DDR_TWR_MSB | DDR_TRFC_MSB(2))
+
+#define DDR_CTL_SRAM_TSEL       BIT(30)
+#define DDR_CTL_SRAM_GE0_SYNC   BIT(20)
+#define DDR_CTL_SRAM_GE1_SYNC   BIT(19)
+#define DDR_CTL_SRAM_USB_SYNC   BIT(18)
+#define DDR_CTL_SRAM_PCIE_SYNC  BIT(17)
+#define DDR_CTL_SRAM_WMAC_SYNC  BIT(16)
+#define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
+#define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
+#define DDR_CTL_PAD_DDR2_SEL    BIT(6)
+#define DDR_CTL_HALF_WIDTH      BIT(1)
+#define DDR_CTL_CONFIG_VAL      (DDR_CTL_SRAM_TSEL | \
+				 DDR_CTL_SRAM_GE0_SYNC | \
+				 DDR_CTL_SRAM_GE1_SYNC | \
+				 DDR_CTL_SRAM_USB_SYNC | \
+				 DDR_CTL_SRAM_PCIE_SYNC | \
+				 DDR_CTL_SRAM_WMAC_SYNC | \
+				 DDR_CTL_HALF_WIDTH)
+
+#define DDR_BURST_GE0_MAX_BL_S  0
+#define DDR_BURST_GE0_MAX_BL_M  0xf
+#define DDR_BURST_GE0_MAX_BL(x) \
+	(((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
+#define DDR_BURST_GE1_MAX_BL_S  4
+#define DDR_BURST_GE1_MAX_BL_M  0xf
+#define DDR_BURST_GE1_MAX_BL(x) \
+	(((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
+#define DDR_BURST_PCIE_MAX_BL_S 8
+#define DDR_BURST_PCIE_MAX_BL_M 0xf
+#define DDR_BURST_PCIE_MAX_BL(x) \
+	(((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
+#define DDR_BURST_USB_MAX_BL_S  12
+#define DDR_BURST_USB_MAX_BL_M  0xf
+#define DDR_BURST_USB_MAX_BL(x) \
+	(((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
+#define DDR_BURST_CPU_MAX_BL_S  16
+#define DDR_BURST_CPU_MAX_BL_M  0xf
+#define DDR_BURST_CPU_MAX_BL(x) \
+	(((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
+#define DDR_BURST_RD_MAX_BL_S   20
+#define DDR_BURST_RD_MAX_BL_M   0xf
+#define DDR_BURST_RD_MAX_BL(x) \
+	(((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
+#define DDR_BURST_WR_MAX_BL_S   24
+#define DDR_BURST_WR_MAX_BL_M   0xf
+#define DDR_BURST_WR_MAX_BL(x) \
+	(((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
+#define DDR_BURST_RWP_MASK_EN_S 28
+#define DDR_BURST_RWP_MASK_EN_M 0x3
+#define DDR_BURST_RWP_MASK_EN(x) \
+	(((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
+#define DDR_BURST_CPU_PRI_BE    BIT(30)
+#define DDR_BURST_CPU_PRI       BIT(31)
+#define DDR_BURST_VAL           (DDR_BURST_CPU_PRI_BE | \
+				 DDR_BURST_RWP_MASK_EN(3) | \
+				 DDR_BURST_WR_MAX_BL(4) | \
+				 DDR_BURST_RD_MAX_BL(4) | \
+				 DDR_BURST_CPU_MAX_BL(4) | \
+				 DDR_BURST_USB_MAX_BL(4) | \
+				 DDR_BURST_PCIE_MAX_BL(4) | \
+				 DDR_BURST_GE1_MAX_BL(4) | \
+				 DDR_BURST_GE0_MAX_BL(4))
+
+#define DDR_BURST_WMAC_MAX_BL_S 0
+#define DDR_BURST_WMAC_MAX_BL_M 0xf
+#define DDR_BURST_WMAC_MAX_BL(x) \
+	(((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
+#define DDR_BURST2_VAL          DDR_BURST_WMAC_MAX_BL(4)
+
+#define DDR2_CONF_TWL_S         10
+#define DDR2_CONF_TWL_M         0xf
+#define DDR2_CONF_TWL(x) \
+	(((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT           BIT(9)
+#define DDR2_CONF_TFAW_S        2
+#define DDR2_CONF_TFAW_M        0x3f
+#define DDR2_CONF_TFAW(x) \
+	(((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN            BIT(0)
+#define DDR2_CONF_VAL           (DDR2_CONF_TWL(5) | \
+				 DDR2_CONF_TFAW(31) | \
+				 DDR2_CONF_ODT | \
+				 DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL       0
+#define DDR2_EXT_MODE_VAL       0x402
+#define DDR2_EXT_MODE_OCD_VAL   0x782
+#define DDR1_MODE_DLL_VAL       0x133
+#define DDR2_MODE_DLL_VAL       0x143
+#define DDR1_MODE_VAL           0x33
+#define DDR2_MODE_VAL           0x43
+#define DDR1_TAP_VAL            0x20
+#define DDR2_TAP_VAL            0x10
+
+#define DDR_REG_BIST_MASK_ADDR_0        0x2c
+#define DDR_REG_BIST_MASK_ADDR_1        0x30
+#define DDR_REG_BIST_MASK_AHB_GE0_0     0x34
+#define DDR_REG_BIST_COMP_AHB_GE0_0     0x38
+#define DDR_REG_BIST_MASK_AHB_GE1_0     0x3c
+#define DDR_REG_BIST_COMP_AHB_GE1_0     0x40
+#define DDR_REG_BIST_COMP_ADDR_0        0x64
+#define DDR_REG_BIST_COMP_ADDR_1        0x68
+#define DDR_REG_BIST_MASK_AHB_GE0_1     0x6c
+#define DDR_REG_BIST_COMP_AHB_GE0_1     0x70
+#define DDR_REG_BIST_MASK_AHB_GE1_1     0x74
+#define DDR_REG_BIST_COMP_AHB_GE1_1     0x78
+#define DDR_REG_BIST                    0x11c
+#define DDR_REG_BIST_STATUS             0x120
+
+#define DDR_BIST_COMP_CNT_S     1
+#define DDR_BIST_COMP_CNT_M     0xff
+#define DDR_BIST_COMP_CNT(x) \
+	(((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_COMP_CNT_MASK \
+	(DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_TEST_START     BIT(0)
+#define DDR_BIST_STATUS_DONE    BIT(0)
+
+/* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
+#define DDR_BIST_MASK_ADDR_VAL  0xfa5de83f
+
+#define DDR_TAP_MAGIC_VAL       0xaa55aa55
+#define DDR_TAP_MAX_VAL         0x40
+
+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_DDR1) {
+		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* ODT disable, Full strength, Enable DLL */
+		writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Reset DLL, CAS Latency 3, Burst Length 8 */
+		writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Update Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Normal DLL, CAS Latency 3, Burst Length 8 */
+		writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Update Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Refresh time control */
+		writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+		udelay(100);
+
+		/* DQS 0 Tap Control */
+		writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+	} else {
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(10);
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(10);
+		writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
+		       regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);
+
+		/* Enable DDR2 */
+		writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Update Extended Mode Register 2 Set (EMR2S) */
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Update Extended Mode Register 3 Set (EMR3S) */
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* 150 ohm, Reduced strength, Enable DLL */
+		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Reset DLL, CAS Latency 4, Burst Length 8 */
+		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Update Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Normal DLL, CAS Latency 4, Burst Length 8 */
+		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		udelay(100);
+
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Enable OCD, Enable DLL, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* OCD diable, Enable DLL, Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		/* Update Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+		udelay(100);
+
+		/* Refresh time control */
+		writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+		udelay(100);
+
+		/* DQS 0 Tap Control */
+		writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+		/* DQS 1 Tap Control */
+		writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+	}
+}
+
+void ddr_tap_tuning(void)
+{
+	void __iomem *regs;
+	u32 val, pass, tap, cnt, tap_val, last, first;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	first = DDR_TAP_MAGIC_VAL;
+	last = 0;
+	cnt = 0;
+	tap = 0;
+
+	do {
+		writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+		writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
+		writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
+		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
+		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
+
+		/* Start BIST test */
+		writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
+
+		do {
+			val = readl(regs + DDR_REG_BIST_STATUS);
+		} while (!(val & DDR_BIST_STATUS_DONE));
+
+		/* Stop BIST test */
+		writel(0, regs + DDR_REG_BIST);
+
+		pass = val & DDR_BIST_COMP_CNT_MASK;
+		pass ^= DDR_BIST_COMP_CNT(8);
+		if (!pass) {
+			if (first != DDR_TAP_MAGIC_VAL) {
+				last = tap;
+			} else  {
+				first = tap;
+				last = tap;
+			}
+			cnt++;
+		}
+		tap++;
+	} while (tap < DDR_TAP_MAX_VAL);
+
+	if (cnt) {
+		tap_val = (first + last) / 2;
+		tap_val %= DDR_TAP_MAX_VAL;
+	}
+
+	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
diff --git a/arch/mips/mach-ath79/qca953x/lowlevel_init.S b/arch/mips/mach-ath79/qca953x/lowlevel_init.S
new file mode 100644
index 0000000..d7038fa
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/lowlevel_init.S
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+#define SET_FIELD(name, v)      (((v) & QCA953X_##name##_MASK) << \
+				 QCA953X_##name##_SHIFT)
+
+#define DPLL2_KI(v)             SET_FIELD(SRIF_DPLL2_KI, v)
+#define DPLL2_KD(v)             SET_FIELD(SRIF_DPLL2_KD, v)
+#define DPLL2_PWD               QCA953X_SRIF_DPLL2_PWD
+#define MK_DPLL2(ki, kd)        (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
+
+#define PLL_CPU_NFRAC(v)        SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
+#define PLL_CPU_NINT(v)         SET_FIELD(PLL_CPU_CONFIG_NINT, v)
+#define PLL_CPU_REFDIV(v)       SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
+#define PLL_CPU_OUTDIV(v)       SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
+#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
+				(PLL_CPU_NFRAC(frac) | \
+				 PLL_CPU_NINT(nint) | \
+				 PLL_CPU_REFDIV(ref) | \
+				 PLL_CPU_OUTDIV(outdiv))
+
+#define PLL_DDR_NFRAC(v)        SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
+#define PLL_DDR_NINT(v)         SET_FIELD(PLL_DDR_CONFIG_NINT, v)
+#define PLL_DDR_REFDIV(v)       SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
+#define PLL_DDR_OUTDIV(v)       SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
+#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
+				(PLL_DDR_NFRAC(frac) | \
+				 PLL_DDR_REFDIV(ref) | \
+				 PLL_DDR_NINT(nint) | \
+				 PLL_DDR_OUTDIV(outdiv) | \
+				 QCA953X_PLL_CONFIG_PWD)
+
+#define PLL_CPU_CONF_VAL        MK_PLL_CPU_CONF(0, 26, 1, 0)
+#define PLL_DDR_CONF_VAL        MK_PLL_DDR_CONF(0, 15, 1, 0)
+
+#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
+				 QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
+				 QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+
+#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
+#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
+#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
+#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
+				(PLL_CLK_CTRL_CPU_DIV(cpu) | \
+				 PLL_CLK_CTRL_DDR_DIV(ddr) | \
+				 PLL_CLK_CTRL_AHB_DIV(ahb))
+#define PLL_CLK_CTRL_VAL    (MK_PLL_CLK_CTRL(0, 0, 2) | \
+			     PLL_CLK_CTRL_PLL_BYPASS | \
+			     QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
+			     QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+
+#define PLL_DDR_DIT_FRAC_MAX(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
+#define PLL_DDR_DIT_FRAC_MIN(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
+#define PLL_DDR_DIT_FRAC_STEP(v)    SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
+#define PLL_DDR_DIT_UPD_CNT(v)      SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
+#define PLL_CPU_DIT_FRAC_MAX(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
+#define PLL_CPU_DIT_FRAC_MIN(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
+#define PLL_CPU_DIT_FRAC_STEP(v)    SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
+#define PLL_CPU_DIT_UPD_CNT(v)      SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
+#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
+				(QCA953X_PLL_DIT_FRAC_EN | \
+				 PLL_DDR_DIT_FRAC_MAX(max) | \
+				 PLL_DDR_DIT_FRAC_MIN(min) | \
+				 PLL_DDR_DIT_FRAC_STEP(step) | \
+				 PLL_DDR_DIT_UPD_CNT(cnt))
+#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
+				(QCA953X_PLL_DIT_FRAC_EN | \
+				 PLL_CPU_DIT_FRAC_MAX(max) | \
+				 PLL_CPU_DIT_FRAC_MIN(min) | \
+				 PLL_CPU_DIT_FRAC_STEP(step) | \
+				 PLL_CPU_DIT_UPD_CNT(cnt))
+#define PLL_CPU_DIT_FRAC_VAL    MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
+#define PLL_DDR_DIT_FRAC_VAL    MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+	/* RTC Reset */
+	li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+	lw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0x08000000
+	or      t1, t1, t2
+	sw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	nop
+	lw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	li      t2, 0xf7ffffff
+	and     t1, t1, t2
+	sw      t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+	nop
+
+	/* RTC Force Wake */
+	li      t0, CKSEG1ADDR(QCA953X_RTC_BASE)
+	li      t1, 0x01
+	sw      t1, QCA953X_RTC_REG_SYNC_RESET(t0)
+	nop
+	nop
+
+	/* Wait for RTC in on state */
+1:
+	lw      t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
+	andi    t1, t1, 0x02
+	beqz    t1, 1b
+	nop
+
+	li      t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
+	li      t1, MK_DPLL2(2, 16)
+	sw      t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
+	sw      t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
+	sw      t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
+	sw      t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
+
+	li      t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+	lw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	ori     t1, PLL_CLK_CTRL_PLL_BYPASS
+	sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	li      t1, PLL_CPU_CONF_VAL
+	sw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	li      t1, PLL_DDR_CONF_VAL
+	sw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+	nop
+
+	li      t1, PLL_CLK_CTRL_VAL
+	sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	lw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+	li      t2, ~QCA953X_PLL_CONFIG_PWD
+	and     t1, t1, t2
+	sw      t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+	nop
+
+	lw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+	li      t2, ~QCA953X_PLL_CONFIG_PWD
+	and     t1, t1, t2
+	sw      t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+	nop
+
+	lw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	li      t2, ~PLL_CLK_CTRL_PLL_BYPASS
+	and     t1, t1, t2
+	sw      t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+	nop
+
+	li      t1, PLL_DDR_DIT_FRAC_VAL
+	sw      t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
+	nop
+
+	li      t1, PLL_CPU_DIT_FRAC_VAL
+	sw      t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
+	nop
+
+	li      t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+	lui     t1, 0x03fc
+	sw      t1, 0xb4(t0)
+
+	nop
+	jr ra
+	 nop
+    END(lowlevel_init)
-- 
cgit v0.10.2


From a79d0643f4cac19711cb8d1c2088fc907d47500f Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:55 +0800
Subject: drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros
 ar933x.

This is a simple pinctrl driver, it just support uart and spi pin-mux now.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2a69bab..854d5a5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -105,6 +105,15 @@ config SPL_PINCONF
 
 if PINCTRL || SPL_PINCTRL
 
+config AR933X_PINCTRL
+	bool "QCA/Athores ar933x pin control driver"
+	depends on DM && SOC_AR933X
+	help
+	  Support pin multiplexing control on QCA/Athores ar933x SoCs.
+	  The driver is controlled by a device tree node which contains
+	  both the GPIO definitions and pin control functions for each
+	  available multiplex function.
+
 config ROCKCHIP_PINCTRL
 	bool "Rockchip pin control driver"
 	depends on DM
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 37dc904..b99ed2f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -6,6 +6,7 @@ obj-y					+= pinctrl-uclass.o
 obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC)	+= pinctrl-generic.o
 
 obj-y					+= nxp/
+obj-$(CONFIG_ARCH_ATH79) += ath79/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 
diff --git a/drivers/pinctrl/ath79/Makefile b/drivers/pinctrl/ath79/Makefile
new file mode 100644
index 0000000..3fdcf6c
--- /dev/null
+++ b/drivers/pinctrl/ath79/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o
diff --git a/drivers/pinctrl/ath79/pinctrl_ar933x.c b/drivers/pinctrl/ath79/pinctrl_ar933x.c
new file mode 100644
index 0000000..e3f64b6
--- /dev/null
+++ b/drivers/pinctrl/ath79/pinctrl_ar933x.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+	PERIPH_ID_UART0,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_NONE = -1,
+};
+
+struct ar933x_pinctrl_priv {
+	void __iomem *regs;
+};
+
+static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
+{
+	switch (cs) {
+	case 0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				AR933X_GPIO(4), AR933X_GPIO(3) |
+				AR933X_GPIO(5) | AR933X_GPIO(2));
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+			     AR933X_GPIO_FUNC_SPI_EN |
+			     AR933X_GPIO_FUNC_RES_TRUE);
+		break;
+	}
+}
+
+static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
+{
+	switch (uart_id) {
+	case PERIPH_ID_UART0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				AR933X_GPIO(9), AR933X_GPIO(10));
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+			     AR933X_GPIO_FUNC_UART_EN |
+			     AR933X_GPIO_FUNC_RES_TRUE);
+		break;
+	}
+}
+
+static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_SPI0:
+		pinctrl_ar933x_spi_config(priv, flags);
+		break;
+	case PERIPH_ID_UART0:
+		pinctrl_ar933x_uart_config(priv, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[2];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[0]) {
+	case 128:
+		return PERIPH_ID_UART0;
+	case 129:
+		return PERIPH_ID_SPI0;
+	}
+	return -ENOENT;
+}
+
+static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = ar933x_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+	return ar933x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops ar933x_pinctrl_ops = {
+	.set_state_simple	= ar933x_pinctrl_set_state_simple,
+	.request	= ar933x_pinctrl_request,
+	.get_periph_id	= ar933x_pinctrl_get_periph_id,
+};
+
+static int ar933x_pinctrl_probe(struct udevice *dev)
+{
+	struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_GPIO_SIZE,
+				 MAP_NOCACHE);
+	return 0;
+}
+
+static const struct udevice_id ar933x_pinctrl_ids[] = {
+	{ .compatible = "qca,ar933x-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_ar933x) = {
+	.name		= "pinctrl_ar933x",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= ar933x_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
+	.ops		= &ar933x_pinctrl_ops,
+	.probe		= ar933x_pinctrl_probe,
+};
-- 
cgit v0.10.2


From c102453aebe92530962de41539ce4f198d27b9c7 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:56 +0800
Subject: drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros
 qca953x.

This is a simple pinctrl driver, it just support uart and spi pin-mux now.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 854d5a5..567b766 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -114,6 +114,15 @@ config AR933X_PINCTRL
 	  both the GPIO definitions and pin control functions for each
 	  available multiplex function.
 
+config QCA953X_PINCTRL
+	bool "QCA/Athores qca953x pin control driver"
+	depends on DM && SOC_QCA953X
+	help
+	  Support pin multiplexing control on QCA/Athores qca953x SoCs.
+	  The driver is controlled by a device tree node which contains
+	  both the GPIO definitions and pin control functions for each
+	  available multiplex function.
+
 config ROCKCHIP_PINCTRL
 	bool "Rockchip pin control driver"
 	depends on DM
diff --git a/drivers/pinctrl/ath79/Makefile b/drivers/pinctrl/ath79/Makefile
index 3fdcf6c..dcea10a 100644
--- a/drivers/pinctrl/ath79/Makefile
+++ b/drivers/pinctrl/ath79/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o
+obj-$(CONFIG_QCA953x_PINCTRL) += pinctrl_qca953x.o
diff --git a/drivers/pinctrl/ath79/pinctrl_qca953x.c b/drivers/pinctrl/ath79/pinctrl_qca953x.c
new file mode 100644
index 0000000..d02597e
--- /dev/null
+++ b/drivers/pinctrl/ath79/pinctrl_qca953x.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+	PERIPH_ID_UART0,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_NONE = -1,
+};
+
+struct qca953x_pinctrl_priv {
+	void __iomem *regs;
+};
+
+static void pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv *priv, int cs)
+{
+	switch (cs) {
+	case 0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				QCA953X_GPIO(5) | QCA953X_GPIO(6) |
+				QCA953X_GPIO(7), QCA953X_GPIO(8));
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC1,
+				QCA953X_GPIO_MUX_MASK(8) |
+				QCA953X_GPIO_MUX_MASK(16) |
+				QCA953X_GPIO_MUX_MASK(24),
+				(QCA953X_GPIO_OUT_MUX_SPI_CS0 << 8) |
+				(QCA953X_GPIO_OUT_MUX_SPI_CLK << 16) |
+				(QCA953X_GPIO_OUT_MUX_SPI_MOSI << 24));
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
+				QCA953X_GPIO_MUX_MASK(0),
+				QCA953X_GPIO_IN_MUX_SPI_DATA_IN);
+
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
+			     QCA953X_GPIO(8));
+		break;
+	}
+}
+
+static void pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv *priv, int uart_id)
+{
+	switch (uart_id) {
+	case PERIPH_ID_UART0:
+		clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+				QCA953X_GPIO(9), QCA953X_GPIO(10));
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC2,
+				QCA953X_GPIO_MUX_MASK(16),
+				QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16);
+
+		clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
+				QCA953X_GPIO_MUX_MASK(8),
+				QCA953X_GPIO_IN_MUX_UART0_SIN << 8);
+
+		setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
+			     QCA953X_GPIO(10));
+		break;
+	}
+}
+
+static int qca953x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_SPI0:
+		pinctrl_qca953x_spi_config(priv, flags);
+		break;
+	case PERIPH_ID_UART0:
+		pinctrl_qca953x_uart_config(priv, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int qca953x_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[2];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[0]) {
+	case 128:
+		return PERIPH_ID_UART0;
+	case 129:
+		return PERIPH_ID_SPI0;
+	}
+	return -ENOENT;
+}
+
+static int qca953x_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = qca953x_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+	return qca953x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops qca953x_pinctrl_ops = {
+	.set_state_simple	= qca953x_pinctrl_set_state_simple,
+	.request	= qca953x_pinctrl_request,
+	.get_periph_id	= qca953x_pinctrl_get_periph_id,
+};
+
+static int qca953x_pinctrl_probe(struct udevice *dev)
+{
+	struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_GPIO_SIZE,
+				 MAP_NOCACHE);
+	return 0;
+}
+
+static const struct udevice_id qca953x_pinctrl_ids[] = {
+	{ .compatible = "qca,qca953x-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_qca953x) = {
+	.name		= "pinctrl_qca953x",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= qca953x_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct qca953x_pinctrl_priv),
+	.ops		= &qca953x_pinctrl_ops,
+	.probe		= qca953x_pinctrl_probe,
+};
-- 
cgit v0.10.2


From 60b49761e9d2f0d16ac5cef934504bc895ac3913 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:57 +0800
Subject: drivers: serial: add serial driver for ar933x SOC

This patch add support for ar933x serial.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
new file mode 100644
index 0000000..ec576a1
--- /dev/null
+++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
@@ -0,0 +1,24 @@
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+  the length of the memory mapped region.
+
+Additional requirements:
+
+  Each UART port must have an alias correctly numbered in "aliases"
+  node.
+
+Example:
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	uart0: uart@18020000 {
+		compatible = "qca,ar9330-uart";
+		reg = <0x18020000 0x14>;
+	};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a9a5d47..2497ae9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -89,6 +89,15 @@ config DEBUG_UART_ALTERA_UART
 	  You will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 
+config DEBUG_UART_AR933X
+	bool "QCA/Atheros ar933x"
+	depends on AR933X_UART
+	help
+	  Select this to enable a debug UART using the ar933x uart driver.
+	  You will need to provide parameters to make this work. The
+	  driver will be available until the real driver model serial is
+	  running.
+
 config DEBUG_UART_NS16550
 	bool "ns16550"
 	help
@@ -263,6 +272,15 @@ config ALTERA_UART
 	  Select this to enable an UART for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config AR933X_UART
+	bool "QCA/Atheros ar933x UART support"
+	depends on DM_SERIAL && SOC_AR933X
+	help
+	  Select this to enable UART support for QCA/Atheros ar933x
+	  devices. This driver uses driver model and requires a device
+	  tree binding to operate, please refer to the document at
+	  doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+
 config FSL_LPUART
 	bool "Freescale LPUART support"
 	help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b0ac9d8..9def128 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
new file mode 100644
index 0000000..d43f9c9
--- /dev/null
+++ b/drivers/serial/serial_ar933x.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2
+#define AR933X_UART_CS_TX_RDY_ORIDE     BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE     BIT(8)
+#define AR933X_UART_CLK_STEP_M          0xffff
+#define AR933X_UART_CLK_SCALE_M         0xfff
+#define AR933X_UART_CLK_SCALE_S         16
+#define AR933X_UART_CLK_STEP_S          0
+
+struct ar933x_serial_priv {
+	void __iomem *regs;
+};
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+					 u32 *scale, u32 *step)
+{
+	u32 tscale, baudrate;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_CLK_STEP_M)
+			break;
+
+		baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+		diff = abs(baudrate - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 val, scale, step;
+
+	val = get_serial_clock();
+	ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	writel(val, priv->regs + AR933X_UART_CLK_REG);
+
+	return 0;
+}
+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 data;
+
+	data = readl(priv->regs + AR933X_UART_DATA_REG);
+	if (!(data & AR933X_UART_DATA_TX_CSR))
+		return -EAGAIN;
+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	writel(data, priv->regs + AR933X_UART_DATA_REG);
+
+	return 0;
+}
+
+static int ar933x_serial_getc(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 data;
+
+	data = readl(priv->regs + AR933X_UART_DATA_REG);
+	if (!(data & AR933X_UART_DATA_RX_CSR))
+		return -EAGAIN;
+
+	writel(AR933X_UART_DATA_RX_CSR, priv->regs + AR933X_UART_DATA_REG);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 data;
+
+	data = readl(priv->regs + AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	struct udevice *pinctrl;
+	fdt_addr_t addr;
+	u32 val;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret)
+		return ret;
+	ret = pinctrl_get_periph_id(pinctrl, dev);
+	if (ret < 0)
+		return ret;
+	ret = pinctrl_request(pinctrl, ret, 0);
+	if (ret < 0)
+		return ret;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR933X_UART_SIZE,
+				 MAP_NOCACHE);
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	writel(val, priv->regs + AR933X_UART_CS_REG);
+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+	{ .compatible = "qca,ar9330-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+	.name   = "serial_ar933x",
+	.id = UCLASS_SERIAL,
+	.of_match = ar933x_serial_ids,
+	.priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+	.probe = ar933x_serial_probe,
+	.ops    = &ar933x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_AR933X
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	u32 val, scale, step;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+	      AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+	writel(val, regs + AR933X_UART_CS_REG);
+
+	ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
+				     CONFIG_BAUDRATE, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	writel(val, regs + AR933X_UART_CLK_REG);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	u32 data;
+
+	do {
+		data = readl(regs + AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_TX_CSR));
+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	writel(data, regs + AR933X_UART_DATA_REG);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
-- 
cgit v0.10.2


From b85dc4607268ffc49af642ab702d44c8b5ef3719 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:58 +0800
Subject: drivers: spi: add spi support for QCA/Atheros ath79 SOCs

This patch add a compatible spi driver for ath79 series SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt
new file mode 100644
index 0000000..3fd9d67
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-ath79.txt
@@ -0,0 +1,19 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi@1f000000 {
+		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+		reg = <0x1f000000 0x10>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f0258f8..b7fd8e5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -23,6 +23,15 @@ config ALTERA_SPI
 	  IP core. Please find details on the "Embedded Peripherals IP
 	  User Guide" of Altera.
 
+config ATH79_SPI
+	bool "Atheros SPI driver"
+	depends on ARCH_ATH79
+	help
+	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+	  to access SPI NOR flash and other SPI peripherals. This driver
+	  uses driver model and requires a device tree binding to operate.
+	  please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+
 config CADENCE_QSPI
 	bool "Cadence QSPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3eca745..7fb2926 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
new file mode 100644
index 0000000..0c1022d
--- /dev/null
+++ b/drivers/spi/ath79_spi.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x)           (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR     12000
+#define ATH79_SPI_MHZ                  (1000 * 1000)
+
+struct ath79_spi_priv {
+	void __iomem *regs;
+	u32 rrw_delay;
+};
+
+static void spi_cs_activate(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+
+	writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+	writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+
+	writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
+	writel(0, priv->regs + AR71XX_SPI_REG_FS);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	u8 *rx = din;
+	const u8 *tx = dout;
+	u8 curbyte, curbitlen, restbits;
+	u32 bytes = bitlen / 8;
+	u32 out, in;
+	u64 tick;
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(dev);
+
+	restbits = (bitlen % 8);
+	if (restbits)
+		bytes++;
+
+	out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+	while (bytes > 0) {
+		bytes--;
+		curbyte = 0;
+		if (tx)
+			curbyte = *tx++;
+
+		if (restbits && !bytes) {
+			curbitlen = restbits;
+			curbyte <<= 8 - restbits;
+		} else {
+			curbitlen = 8;
+		}
+
+		for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+			if (curbyte & 0x80)
+				out |= AR71XX_SPI_IOC_DO;
+			else
+				out &= ~(AR71XX_SPI_IOC_DO);
+
+			writel(out, priv->regs + AR71XX_SPI_REG_IOC);
+
+			/* delay for low level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			writel(out | AR71XX_SPI_IOC_CLK,
+			       priv->regs + AR71XX_SPI_REG_IOC);
+
+			/* delay for high level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			curbyte <<= 1;
+		}
+
+		if (!bytes)
+			writel(out, priv->regs + AR71XX_SPI_REG_IOC);
+
+		in = readl(priv->regs + AR71XX_SPI_REG_RDS);
+		if (rx) {
+			if (restbits && !bytes)
+				*rx++ = (in << (8 - restbits));
+			else
+				*rx++ = in;
+		}
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(dev);
+
+	return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	u32 val, div = 0;
+	u64 time;
+
+	if (speed)
+		div = get_bus_freq(0) / speed;
+
+	if (div > 63)
+		div = 63;
+
+	if (div < 5)
+		div = 5;
+
+	/* calculate delay */
+	time = get_tbclk();
+	do_div(time, speed / 2);
+	val = get_bus_freq(0) / ATH79_SPI_MHZ;
+	val = ATH79_SPI_RRW_DELAY_FACTOR / val;
+	if (time > val)
+		priv->rrw_delay = time - val + 1;
+	else
+		priv->rrw_delay = 0;
+
+	writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+	clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL,
+			AR71XX_SPI_CTRL_DIV_MASK,
+			ATH79_SPI_CLK_DIV(div));
+	writel(0, priv->regs + AR71XX_SPI_REG_FS);
+	return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct udevice *pinctrl;
+	fdt_addr_t addr;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret)
+		return ret;
+	ret = pinctrl_get_periph_id(pinctrl, bus);
+	if (ret < 0)
+		return ret;
+	ret = pinctrl_request(pinctrl, ret, 0);
+	if (ret < 0)
+		return ret;
+
+	addr = dev_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_SPI_SIZE,
+				 MAP_NOCACHE);
+
+	/* Init SPI Hardware, disable remap, set clock */
+	writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+	writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
+	       priv->regs + AR71XX_SPI_REG_CTRL);
+	writel(0, priv->regs + AR71XX_SPI_REG_FS);
+
+	return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	/* Always allow activity on CS 0/1/2 */
+	if (cs >= 3)
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+	.claim_bus  = ath79_spi_claim_bus,
+	.release_bus    = ath79_spi_release_bus,
+	.xfer       = ath79_spi_xfer,
+	.set_speed  = ath79_spi_set_speed,
+	.set_mode   = ath79_spi_set_mode,
+	.cs_info    = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+	{ .compatible = "qca,ar7100-spi" },
+	{}
+};
+
+U_BOOT_DRIVER(ath79_spi) = {
+	.name   = "ath79_spi",
+	.id = UCLASS_SPI,
+	.of_match = ath79_spi_ids,
+	.ops    = &ath79_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+	.probe  = ath79_spi_probe,
+};
-- 
cgit v0.10.2


From 6a7b52bc8d30090633d098f9e988276beb7a53d5 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 16:59:59 +0800
Subject: mips: ath79: add AP121 reference board

This patch add board-level code and base DT for AP121.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b513918..30e5c68 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 
 targets += $(dtb-y)
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
new file mode 100644
index 0000000..e31f601
--- /dev/null
+++ b/arch/mips/dts/ap121.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+	model = "AP121 Reference Board";
+	compatible = "qca,ap121", "qca,ar933x";
+
+	aliases {
+		spi0 = &spi0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&xtal {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x9f000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
new file mode 100644
index 0000000..11f60a2
--- /dev/null
+++ b/arch/mips/dts/ar933x.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,ar933x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	pinctrl {
+		u-boot,dm-pre-reloc;
+		compatible = "qca,ar933x-pinctrl";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x18040000 0x100>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			uart0: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x20>;
+				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
+
+				status = "disabled";
+			};
+		};
+
+		spi0: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index e35f1b5..c3012f8 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -22,4 +22,15 @@ config SOC_QCA953X
 	help
 	  This supports QCA/Atheros qca953x family SOCs.
 
+choice
+	prompt "Board select"
+
+config TARGET_AP121
+	bool "AP121 Reference Board"
+	select SOC_AR933X
+
+endchoice
+
+source "board/qca/ap121/Kconfig"
+
 endmenu
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
new file mode 100644
index 0000000..f7e768a
--- /dev/null
+++ b/board/qca/ap121/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AP121
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap121"
+
+config SYS_CONFIG_NAME
+	default "ap121"
+
+endif
diff --git a/board/qca/ap121/MAINTAINERS b/board/qca/ap121/MAINTAINERS
new file mode 100644
index 0000000..8b02988
--- /dev/null
+++ b/board/qca/ap121/MAINTAINERS
@@ -0,0 +1,6 @@
+AP121 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap121/
+F:	include/configs/ap121.h
+F:	configs/ap121_defconfig
diff --git a/board/qca/ap121/Makefile b/board/qca/ap121/Makefile
new file mode 100644
index 0000000..ced5432
--- /dev/null
+++ b/board/qca/ap121/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ap121.o
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
new file mode 100644
index 0000000..d6c60fe
--- /dev/null
+++ b/board/qca/ap121/ap121.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val &= ~AR933X_GPIO(9);
+	val |= AR933X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_FUNC);
+	val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+	writel(val, regs + AR71XX_GPIO_REG_FUNC);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	ddr_init();
+	return 0;
+}
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
new file mode 100644
index 0000000..7604e2e
--- /dev/null
+++ b/configs/ap121_defconfig
@@ -0,0 +1,47 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_SYS_PROMPT="ap121 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_AR933X_PINCTRL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_AR933X=y
+CONFIG_DEBUG_UART_BASE=0xb8020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_AR933X_UART=y
+CONFIG_ATH79_SPI=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
new file mode 100644
index 0000000..2beffa4
--- /dev/null
+++ b/include/configs/ap121.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE            0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  200
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE          0x8000
+#define CONFIG_SYS_ICACHE_SIZE          0x10000
+#define CONFIG_SYS_CACHELINE_SIZE       32
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+#define CONFIG_BAUDRATE                 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY                3
+#define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
+					"root=/dev/mtdblock2 " \
+					"rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f300000"
+#define CONFIG_LZMA
+
+#define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
+					"256k(u-boot),64k(u-boot-env)," \
+					"2752k(rootfs),896k(uImage)," \
+					"64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ           25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif  /* __CONFIG_H */
-- 
cgit v0.10.2


From a2277cc30cdb40298aca80344f3764db6a0cfb8d Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Wed, 16 Mar 2016 17:00:00 +0800
Subject: mips: ath79: add AP143 reference board

This patch add board-level code and base DT for AP143.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 30e5c68..bd87ead 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -3,6 +3,7 @@
 #
 
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
+dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 
 targets += $(dtb-y)
diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts
new file mode 100644
index 0000000..f53207e
--- /dev/null
+++ b/arch/mips/dts/ap143.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "qca953x.dtsi"
+
+/ {
+	model = "AP143 Reference Board";
+	compatible = "qca,ap143", "qca,qca953x";
+
+	aliases {
+		spi0 = &spi0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&xtal {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x9f000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
new file mode 100644
index 0000000..870010f
--- /dev/null
+++ b/arch/mips/dts/qca953x.dtsi
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,qca953x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	pinctrl {
+		u-boot,dm-pre-reloc;
+		compatible = "qca,qca953x-pinctrl";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x18040000 0x100>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			uart0: uart@18020000 {
+				compatible = "ns16550";
+				reg = <0x18020000 0x20>;
+				reg-shift = <2>;
+				clock-frequency = <25000000>;
+				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
+
+				status = "disabled";
+			};
+		};
+
+		spi0: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index c3012f8..f45403b 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -29,8 +29,13 @@ config TARGET_AP121
 	bool "AP121 Reference Board"
 	select SOC_AR933X
 
+config TARGET_AP143
+	bool "AP143 Reference Board"
+	select SOC_QCA953X
+
 endchoice
 
 source "board/qca/ap121/Kconfig"
+source "board/qca/ap143/Kconfig"
 
 endmenu
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
new file mode 100644
index 0000000..4cdac0d
--- /dev/null
+++ b/board/qca/ap143/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AP143
+
+config SYS_VENDOR
+	default "qca"
+
+config SYS_BOARD
+	default "ap143"
+
+config SYS_CONFIG_NAME
+	default "ap143"
+
+endif
diff --git a/board/qca/ap143/MAINTAINERS b/board/qca/ap143/MAINTAINERS
new file mode 100644
index 0000000..11cb14f
--- /dev/null
+++ b/board/qca/ap143/MAINTAINERS
@@ -0,0 +1,6 @@
+AP143 BOARD
+M:	Wills Wang <wills.wang@live.com>
+S:	Maintained
+F:	board/qca/ap143/
+F:	include/configs/ap143.h
+F:	configs/ap143_defconfig
diff --git a/board/qca/ap143/Makefile b/board/qca/ap143/Makefile
new file mode 100644
index 0000000..00f7837
--- /dev/null
+++ b/board/qca/ap143/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ap143.o
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
new file mode 100644
index 0000000..1572472
--- /dev/null
+++ b/board/qca/ap143/ap143.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/*
+	 * GPIO9 as input, GPIO10 as output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OE);
+	val |= QCA953X_GPIO(9);
+	val &= ~QCA953X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OE);
+
+	/*
+	 * Enable GPIO10 as UART0_SOUT
+	 */
+	val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
+	val &= ~QCA953X_GPIO_MUX_MASK(16);
+	val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
+	writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
+
+	/*
+	 * Enable GPIO9 as UART0_SIN
+	 */
+	val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
+	val &= ~QCA953X_GPIO_MUX_MASK(8);
+	val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
+	writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
+
+	/*
+	 * Enable GPIO10 output
+	 */
+	val = readl(regs + AR71XX_GPIO_REG_OUT);
+	val |= QCA953X_GPIO(10);
+	writel(val, regs + AR71XX_GPIO_REG_OUT);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	ddr_init();
+	return 0;
+}
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
new file mode 100644
index 0000000..1aa6e5d
--- /dev/null
+++ b/configs/ap143_defconfig
@@ -0,0 +1,47 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_TARGET_AP143=y
+CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_SYS_PROMPT="ap143 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_QCA953X_PINCTRL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xb8020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ATH79_SPI=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
new file mode 100644
index 0000000..7b69e10
--- /dev/null
+++ b/include/configs/ap143.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE            0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  325
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE          0x8000
+#define CONFIG_SYS_ICACHE_SIZE          0x10000
+#define CONFIG_SYS_CACHELINE_SIZE       32
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x2000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK          25000000
+#define CONFIG_BAUDRATE                 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY                3
+#define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
+					"root=/dev/mtdblock2 " \
+					"rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f300000"
+#define CONFIG_LZMA
+
+#define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
+					"256k(u-boot),64k(u-boot-env)," \
+					"2752k(rootfs),896k(uImage)," \
+					"64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ           25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif  /* __CONFIG_H */
-- 
cgit v0.10.2


From 30fd42cba6e7d4147e2dd4e9dbe9728efbcd24fe Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Fri, 18 Mar 2016 18:36:07 +0530
Subject: flash: add device ID for Microchip PIC32 internal flash.

Microchip PIC32 has internal parallel flash (non-CFI compliant).
These flash devices do not support any identifier command so no
standard IDs. Added unique IDs to seperate these flash devices
from others supported by U-Boot.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>

diff --git a/include/flash.h b/include/flash.h
index c6321a0..2a5e13a 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
 #define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
 
+#define FLASH_MCHP100T	0x0060		/* MCHP internal (1M = 64K x 16) */
+#define FLASH_MCHP100B	0x0061		/* MCHP internal (1M = 64K x 16) */
+
 #define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
 #define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
 
@@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_MAN_SHARP 0x00500000
 #define FLASH_MAN_ATM	0x00600000
 #define FLASH_MAN_CFI	0x01000000
-
+#define FLASH_MAN_MCHP	0x02000000	/* Microchip Technology		*/
 
 #define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
 #define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
-- 
cgit v0.10.2


From 5c990456999c5672b8e626f945b0e8e17162e02f Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Fri, 18 Mar 2016 18:36:08 +0530
Subject: drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.

PIC32 internal flash devices are parallel NOR flash divided into
number of banks to allow erase-programming in one while fetch and
execution continues on other. As the flash banks are memory mapped
stored code can be executed directly from flash (XIP), also there
is additional hardware logic to prefetch and cache contents to
improve execution performance. These flash can also be used to
store user data (like environment).
Flash erase and programming are handled by on-chip NVM controller.

Driver implemented driver model but MTD is not really support.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index c58841e..390e9e4 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -28,6 +28,13 @@ config ALTERA_QSPI
 	  NOR flash to parallel flash interface. Please find details on the
 	  "Embedded Peripherals IP User Guide" of Altera.
 
+config FLASH_PIC32
+	bool "Microchip PIC32 Flash driver"
+	depends on MACH_PIC32 && MTD
+	help
+	  This enables access to Microchip PIC32 internal non-CFI flash
+	  chips through PIC32 Non-Volatile-Memory Controller.
+
 endmenu
 
 source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 703700a..bd680a7 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 obj-$(CONFIG_FTSMC020) += ftsmc020.o
 obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 obj-$(CONFIG_ST_SMI) += st_smi.o
 obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
new file mode 100644
index 0000000..9166fcd
--- /dev/null
+++ b/drivers/mtd/pic32_flash.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan <cristian.birsan@microchip.com>
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <flash.h>
+#include <mach/pic32.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+	struct pic32_reg_atomic ctrl;
+	struct pic32_reg_atomic key;
+	struct pic32_reg_atomic addr;
+	struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP		0
+#define NVMOP_WORD_WRITE	1
+#define NVMOP_PAGE_ERASE	4
+
+/* NVM control bits */
+#define NVM_WR			BIT(15)
+#define NVM_WREN		BIT(14)
+#define NVM_WRERR		BIT(13)
+#define NVM_LVDERR		BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY		0x0
+#define UNLOCK_KEY1		0xaa996655
+#define UNLOCK_KEY2		0x556699aa
+
+/*
+ * PIC32 flash banks consist of number of pages, each page
+ * into number of rows and rows into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+	/* set operation */
+	writel(nvmop, &nvm_regs_p->ctrl.raw);
+
+	/* enable flash write */
+	writel(NVM_WREN, &nvm_regs_p->ctrl.set);
+
+	/* unlock sequence */
+	writel(LOCK_KEY, &nvm_regs_p->key.raw);
+	writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
+	writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
+
+	/* initiate operation */
+	writel(NVM_WR, &nvm_regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+	int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
+			       NVM_WR, false, timeout, false);
+
+	return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+	u32 tmp;
+
+	tmp = readl(&nvm_regs_p->ctrl.raw);
+	if (tmp & NVM_WRERR) {
+		printf("Error in Block Erase - Lock Bit may be set!\n");
+		flash_initiate_operation(NVMOP_NOP);
+		return ERR_PROTECTED;
+	}
+
+	if (tmp & NVM_LVDERR) {
+		printf("Error in Block Erase - low-vol detected!\n");
+		flash_initiate_operation(NVMOP_NOP);
+		return ERR_NOT_ERASED;
+	}
+
+	/* disable flash write or erase operation */
+	writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
+
+	return ERR_OK;
+}
+
+/*
+ * Erase flash sectors, returns:
+ * ERR_OK - OK
+ * ERR_INVAL - invalid sector arguments
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ * ERR_UNKNOWN_FLASH_VENDOR - incorrect flash
+ */
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	ulong sect_start, sect_end, flags;
+	int prot, sect;
+	int rc;
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf("- no sectors to erase\n");
+		return ERR_INVAL;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	/* erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			continue;
+
+		/* disable interrupts */
+		flags = disable_interrupts();
+
+		/* write destination page address (physical) */
+		sect_start = CPHYSADDR(info->start[sect]);
+		writel(sect_start, &nvm_regs_p->addr.raw);
+
+		/* page erase */
+		flash_initiate_operation(NVMOP_PAGE_ERASE);
+
+		/* wait */
+		rc = flash_wait_till_busy(__func__,
+					  CONFIG_SYS_FLASH_ERASE_TOUT);
+
+		/* re-enable interrupts if necessary */
+		if (flags)
+			enable_interrupts();
+
+		if (rc != ERR_OK)
+			return rc;
+
+		rc = flash_complete_operation();
+		if (rc != ERR_OK)
+			return rc;
+
+		/*
+		 * flash content is updated but cache might contain stale
+		 * data, so invalidate dcache.
+		 */
+		sect_end = info->start[sect] + info->size / info->sector_count;
+		invalidate_dcache_range(info->start[sect], sect_end);
+	}
+
+	printf(" done\n");
+	return ERR_OK;
+}
+
+int page_erase(flash_info_t *info, int sect)
+{
+	return 0;
+}
+
+/* Write a word to flash */
+static int write_word(flash_info_t *info, ulong dest, ulong word)
+{
+	ulong flags;
+	int rc;
+
+	/* read flash to check if it is sufficiently erased */
+	if ((readl((void __iomem *)dest) & word) != word) {
+		printf("Error, Flash not erased!\n");
+		return ERR_NOT_ERASED;
+	}
+
+	/* disable interrupts */
+	flags = disable_interrupts();
+
+	/* update destination page address (physical) */
+	writel(CPHYSADDR(dest), &nvm_regs_p->addr.raw);
+	writel(word, &nvm_regs_p->data.raw);
+
+	/* word write */
+	flash_initiate_operation(NVMOP_WORD_WRITE);
+
+	/* wait for operation to complete */
+	rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);
+
+	/* re-enable interrupts if necessary */
+	if (flags)
+		enable_interrupts();
+
+	if (rc != ERR_OK)
+		return rc;
+
+	return flash_complete_operation();
+}
+
+/*
+ * Copy memory to flash, returns:
+ * ERR_OK - OK
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong dst, tmp_le, len = cnt;
+	int i, l, rc;
+	uchar *cp;
+
+	/* get lower word aligned address */
+	dst = (addr & ~3);
+
+	/* handle unaligned start bytes */
+	l = addr - dst;
+	if (l != 0) {
+		tmp_le = 0;
+		for (i = 0, cp = (uchar *)dst; i < l; ++i, ++cp)
+			tmp_le |= *cp << (i * 8);
+
+		for (; (i < 4) && (cnt > 0); ++i, ++src, --cnt, ++cp)
+			tmp_le |= *src << (i * 8);
+
+		for (; (cnt == 0) && (i < 4); ++i, ++cp)
+			tmp_le |= *cp << (i * 8);
+
+		rc = write_word(info, dst, tmp_le);
+		if (rc)
+			goto out;
+
+		dst += 4;
+	}
+
+	/* handle word aligned part */
+	while (cnt >= 4) {
+		tmp_le = src[0] | src[1] << 8 | src[2] << 16 | src[3] << 24;
+		rc = write_word(info, dst, tmp_le);
+		if (rc)
+			goto out;
+		src += 4;
+		dst += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		rc = ERR_OK;
+		goto out;
+	}
+
+	/* handle unaligned tail bytes */
+	tmp_le = 0;
+	for (i = 0, cp = (uchar *)dst; (i < 4) && (cnt > 0); ++i, ++cp) {
+		tmp_le |= *src++ << (i * 8);
+		--cnt;
+	}
+
+	for (; i < 4; ++i, ++cp)
+		tmp_le |= *cp << (i * 8);
+
+	rc = write_word(info, dst, tmp_le);
+out:
+	/*
+	 * flash content updated by nvm controller but CPU cache might
+	 * have stale data, so invalidate dcache.
+	 */
+	invalidate_dcache_range(addr, addr + len);
+
+	printf(" done\n");
+	return rc;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_MCHP:
+		printf("Microchip Technology ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_MCHP100T:
+		printf("Internal (8 Mbit, 64 x 16k)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s", info->start[i],
+		       info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	struct udevice *dev;
+	int bank;
+
+	/* probe every MTD device */
+	for (uclass_first_device(UCLASS_MTD, &dev); dev;
+	     uclass_next_device(&dev)) {
+		/* nop */
+	}
+
+	/* calc total flash size */
+	for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank)
+		size += flash_info[bank].size;
+
+	return size;
+}
+
+static void pic32_flash_bank_init(flash_info_t *info,
+				  ulong base, ulong size)
+{
+	ulong sect_size;
+	int sect;
+
+	/* device & manufacturer code */
+	info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	info->size = size;
+
+	/* update sector (i.e page) info */
+	sect_size = info->size / info->sector_count;
+	for (sect = 0; sect < info->sector_count; sect++) {
+		info->start[sect] = base;
+		/* protect each sector by default */
+		info->protect[sect] = 1;
+		base += sect_size;
+	}
+}
+
+static int pic32_flash_probe(struct udevice *dev)
+{
+	void *blob = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	const char *list, *end;
+	const fdt32_t *cell;
+	unsigned long addr, size;
+	int parent, addrc, sizec;
+	flash_info_t *info;
+	int len, idx;
+
+	/*
+	 * decode regs. there are multiple reg tuples, and they need to
+	 * match with reg-names.
+	 */
+	parent = fdt_parent_offset(blob, node);
+	of_bus_default_count_cells(blob, parent, &addrc, &sizec);
+	list = fdt_getprop(blob, node, "reg-names", &len);
+	if (!list)
+		return -ENOENT;
+
+	end = list + len;
+	cell = fdt_getprop(blob, node, "reg", &len);
+	if (!cell)
+		return -ENOENT;
+
+	for (idx = 0, info = &flash_info[0]; list < end;) {
+		addr = fdt_translate_address((void *)blob, node, cell + idx);
+		size = fdt_addr_to_cpu(cell[idx + addrc]);
+		len = strlen(list);
+		if (!strncmp(list, "nvm", len)) {
+			/* NVM controller */
+			nvm_regs_p = ioremap(addr, size);
+		} else if (!strncmp(list, "bank", 4)) {
+			/* Flash bank: use kseg0 cached address */
+			pic32_flash_bank_init(info, CKSEG0ADDR(addr), size);
+			info++;
+		}
+		idx += addrc + sizec;
+		list += len + 1;
+	}
+
+	/* disable flash write/erase operations */
+	writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
+
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+#endif
+	return 0;
+}
+
+static const struct udevice_id pic32_flash_ids[] = {
+	{ .compatible = "microchip,pic32mzda-flash" },
+	{}
+};
+
+U_BOOT_DRIVER(pic32_flash) = {
+	.name	= "pic32_flash",
+	.id	= UCLASS_MTD,
+	.of_match = pic32_flash_ids,
+	.probe	= pic32_flash_probe,
+};
-- 
cgit v0.10.2


From 8cf7a418bcff0492285d7dd2687bd42aaa377e5d Mon Sep 17 00:00:00 2001
From: Tim Chick <tim.chick@mediatek.com>
Date: Thu, 31 Mar 2016 12:51:20 +0100
Subject: mips: Report reloc information in bdinfo

Signed-off-by: Tim Chick <tim.chick@mediatek.com>

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8eda68b..1c4bed9 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -341,6 +341,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_eth(0);
 	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %u bps\n", gd->baudrate);
+	print_num("relocaddr", gd->relocaddr);
+	print_num("reloc off", gd->reloc_off);
 
 	return 0;
 }
-- 
cgit v0.10.2


From 5fabf2e7da1b738c6e0353b6a5a17b1a77ecc2e9 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Tue, 12 Apr 2016 11:09:18 +0800
Subject: ath79: spi: Remove the explicit pinctrl setting

The correct pinctrl is handled automatically so we don't need to do it in
the driver.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
index 0c1022d..b18c733 100644
--- a/drivers/spi/ath79_spi.c
+++ b/drivers/spi/ath79_spi.c
@@ -175,19 +175,7 @@ static int ath79_spi_set_mode(struct udevice *bus, uint mode)
 static int ath79_spi_probe(struct udevice *bus)
 {
 	struct ath79_spi_priv *priv = dev_get_priv(bus);
-	struct udevice *pinctrl;
 	fdt_addr_t addr;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret)
-		return ret;
-	ret = pinctrl_get_periph_id(pinctrl, bus);
-	if (ret < 0)
-		return ret;
-	ret = pinctrl_request(pinctrl, ret, 0);
-	if (ret < 0)
-		return ret;
 
 	addr = dev_get_addr(bus);
 	if (addr == FDT_ADDR_T_NONE)
-- 
cgit v0.10.2


From 773f3b25384363d53e457f1faae77c91db76e0c4 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Tue, 12 Apr 2016 11:09:19 +0800
Subject: ar933x: serial: Remove the explicit pinctrl setting

The correct pinctrl is handled automatically so we don't need to do it in
the driver.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
index d43f9c9..aae66dc 100644
--- a/drivers/serial/serial_ar933x.c
+++ b/drivers/serial/serial_ar933x.c
@@ -38,6 +38,7 @@ struct ar933x_serial_priv {
 };
 
 /*
+ * Baudrate algorithm come from Linux/drivers/tty/serial/ar933x_uart.c
  * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
  */
 static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
@@ -145,27 +146,14 @@ static int ar933x_serial_pending(struct udevice *dev, bool input)
 static int ar933x_serial_probe(struct udevice *dev)
 {
 	struct ar933x_serial_priv *priv = dev_get_priv(dev);
-	struct udevice *pinctrl;
 	fdt_addr_t addr;
 	u32 val;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret)
-		return ret;
-	ret = pinctrl_get_periph_id(pinctrl, dev);
-	if (ret < 0)
-		return ret;
-	ret = pinctrl_request(pinctrl, ret, 0);
-	if (ret < 0)
-		return ret;
 
 	addr = dev_get_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->regs = map_physmem(addr,
-				 AR933X_UART_SIZE,
+	priv->regs = map_physmem(addr, AR933X_UART_SIZE,
 				 MAP_NOCACHE);
 
 	/*
-- 
cgit v0.10.2


From 5691d10a0166d5a324f96d98757f206c6dedc989 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Tue, 12 Apr 2016 11:09:20 +0800
Subject: ath79: ar933x: use BIT macro for bit shift operation

used a uniform BIT macro for register bit-field shift

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 74e8e80..91452bc 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_CTRL_UPD_EMRS       BIT(1)
 #define DDR_CTRL_UPD_MRS        BIT(0)
 
-#define DDR_REFRESH_EN          (1 << 14)
+#define DDR_REFRESH_EN          BIT(14)
 #define DDR_REFRESH_M           0x3ff
 #define DDR_REFRESH(x)          ((x) & 0x3ff)
 #define DDR_REFRESH_VAL_25M     (DDR_REFRESH_EN | DDR_REFRESH(390))
@@ -48,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_CAS_L_M             0x17
 #define DDR_CAS_L_S             27
 #define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
-#define DDR_OPEN                (1 << 30)
+#define DDR_OPEN                BIT(30)
 #define DDR_CONF_REG_VAL        (DDR_TRAS(16) | DDR_TRCD(6) | \
 				 DDR_TRP(6) | DDR_TRRD(4) | \
 				 DDR_TRFC(30) | DDR_TMRD(15) | \
@@ -57,10 +57,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_BURST_LEN_S         0
 #define DDR_BURST_LEN_M         0xf
 #define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
-#define DDR_BURST_TYPE          (1 << 4)
-#define DDR_CNTL_OE_EN          (1 << 5)
-#define DDR_PHASE_SEL           (1 << 6)
-#define DDR_CKE                 (1 << 7)
+#define DDR_BURST_TYPE          BIT(4)
+#define DDR_CNTL_OE_EN          BIT(5)
+#define DDR_PHASE_SEL           BIT(6)
+#define DDR_CKE                 BIT(7)
 #define DDR_TWR_S               8
 #define DDR_TWR_M               0xf
 #define DDR_TWR(x)              ((x) << DDR_TWR_S)
@@ -76,7 +76,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DDR_G_OPEN_L_S          26
 #define DDR_G_OPEN_L_M          0xf
 #define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
-#define DDR_HALF_WIDTH_LOW      (1 << 31)
+#define DDR_HALF_WIDTH_LOW      BIT(31)
 #define DDR_CONF2_REG_VAL       (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
 				 DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
 				 DDR_TRTP(8) | DDR_TWTR(14) | \
-- 
cgit v0.10.2


From 59e4080c7e4d85bd29c343ea9167794feceadc3e Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Tue, 12 Apr 2016 18:24:10 +0800
Subject: ath79: add readonly attribute for ath79_soc_desc

use 'const' keywork to qualify readonly attribute for lookup-table member

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
index c6122f2..5756a06 100644
--- a/arch/mips/mach-ath79/cpu.c
+++ b/arch/mips/mach-ath79/cpu.c
@@ -12,13 +12,13 @@
 #include <mach/ar71xx_regs.h>
 
 struct ath79_soc_desc {
-	enum ath79_soc_type soc;
+	const enum ath79_soc_type soc;
 	const char *chip;
-	int major;
-	int minor;
+	const int major;
+	const int minor;
 };
 
-static struct ath79_soc_desc desc[] = {
+static const struct ath79_soc_desc desc[] = {
 	{ATH79_SOC_AR7130,      "7130",
 	 REV_ID_MAJOR_AR71XX,   AR71XX_REV_ID_MINOR_AR7130},
 	{ATH79_SOC_AR7141,      "7141",
-- 
cgit v0.10.2


From 5760fc7850a9ad98a8852200ea879bfccd66df26 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 5 May 2016 20:14:00 +0200
Subject: mips: Fix compiler warning in cpu.c

There really is zero reason for including netdev.h in generic mips CPU code.
Removing the netdev.h from cpu.c also fixes the following compiler warning:

In file included from arch/mips/cpu/cpu.c:10:0:
include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default]
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
                                         ^
include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 8d3b2f5..391feb3 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -7,7 +7,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <netdev.h>
 #include <linux/compiler.h>
 #include <asm/mipsregs.h>
 #include <asm/reboot.h>
-- 
cgit v0.10.2


From 0a0a958b68ee9d78a7cbccb5f72b95e1d488c9bd Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:33 +0200
Subject: mips: Add MIPS 74Kc tune

Add MIPS 74Kc tune Kconfig option.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
[added missing tune-y entry in arch/mips/Makefile]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7162f3c..188aaba 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -198,6 +198,9 @@ config MIPS_TUNE_14KC
 config MIPS_TUNE_24KC
 	bool
 
+config MIPS_TUNE_74KC
+	bool
+
 config 32BIT
 	bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 7a82316..94f7e16 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -26,6 +26,7 @@ arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
 tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
 tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
 
 # Include default header files
 cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
-- 
cgit v0.10.2


From 0a6767efabedbddc2351d14695aa3a7d63657e2c Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:34 +0200
Subject: mips: ath79: Fix ar71xx_regs.h indent

The indent in this file triggers my OCD, so fix it. Replace multiple
spaces with tabs and align the values in one column.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index 893dedc..bff9d05 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -16,709 +16,744 @@
 #include <linux/bitops.h>
 #else
 #ifndef BIT
-#define BIT(nr)                 (1 << (nr))
+#define BIT(nr)		(1 << (nr))
 #endif
 #endif
 
-#define AR71XX_APB_BASE                 0x18000000
-#define AR71XX_GE0_BASE                 0x19000000
-#define AR71XX_GE0_SIZE                 0x10000
-#define AR71XX_GE1_BASE                 0x1a000000
-#define AR71XX_GE1_SIZE                 0x10000
-#define AR71XX_EHCI_BASE                0x1b000000
-#define AR71XX_EHCI_SIZE                0x1000
-#define AR71XX_OHCI_BASE                0x1c000000
-#define AR71XX_OHCI_SIZE                0x1000
-#define AR71XX_SPI_BASE                 0x1f000000
-#define AR71XX_SPI_SIZE                 0x01000000
-
-#define AR71XX_DDR_CTRL_BASE            (AR71XX_APB_BASE + 0x00000000)
-#define AR71XX_DDR_CTRL_SIZE            0x100
-#define AR71XX_UART_BASE                (AR71XX_APB_BASE + 0x00020000)
-#define AR71XX_UART_SIZE                0x100
-#define AR71XX_USB_CTRL_BASE            (AR71XX_APB_BASE + 0x00030000)
-#define AR71XX_USB_CTRL_SIZE            0x100
-#define AR71XX_GPIO_BASE                (AR71XX_APB_BASE + 0x00040000)
-#define AR71XX_GPIO_SIZE                0x100
-#define AR71XX_PLL_BASE                 (AR71XX_APB_BASE + 0x00050000)
-#define AR71XX_PLL_SIZE                 0x100
-#define AR71XX_RESET_BASE               (AR71XX_APB_BASE + 0x00060000)
-#define AR71XX_RESET_SIZE               0x100
-#define AR71XX_MII_BASE                 (AR71XX_APB_BASE + 0x00070000)
-#define AR71XX_MII_SIZE                 0x100
-
-#define AR71XX_PCI_MEM_BASE             0x10000000
-#define AR71XX_PCI_MEM_SIZE             0x07000000
-
-#define AR71XX_PCI_WIN0_OFFS            0x10000000
-#define AR71XX_PCI_WIN1_OFFS            0x11000000
-#define AR71XX_PCI_WIN2_OFFS            0x12000000
-#define AR71XX_PCI_WIN3_OFFS            0x13000000
-#define AR71XX_PCI_WIN4_OFFS            0x14000000
-#define AR71XX_PCI_WIN5_OFFS            0x15000000
-#define AR71XX_PCI_WIN6_OFFS            0x16000000
-#define AR71XX_PCI_WIN7_OFFS            0x07000000
+#define AR71XX_APB_BASE					0x18000000
+#define AR71XX_GE0_BASE					0x19000000
+#define AR71XX_GE0_SIZE					0x10000
+#define AR71XX_GE1_BASE					0x1a000000
+#define AR71XX_GE1_SIZE					0x10000
+#define AR71XX_EHCI_BASE				0x1b000000
+#define AR71XX_EHCI_SIZE				0x1000
+#define AR71XX_OHCI_BASE				0x1c000000
+#define AR71XX_OHCI_SIZE				0x1000
+#define AR71XX_SPI_BASE					0x1f000000
+#define AR71XX_SPI_SIZE					0x01000000
+
+#define AR71XX_DDR_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE				0x100
+#define AR71XX_UART_BASE \
+	(AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE				0x100
+#define AR71XX_USB_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE				0x100
+#define AR71XX_GPIO_BASE \
+	(AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE				0x100
+#define AR71XX_PLL_BASE \
+	(AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE					0x100
+#define AR71XX_RESET_BASE \
+	(AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE				0x100
+#define AR71XX_MII_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE					0x100
+
+#define AR71XX_PCI_MEM_BASE				0x10000000
+#define AR71XX_PCI_MEM_SIZE				0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS				0x10000000
+#define AR71XX_PCI_WIN1_OFFS				0x11000000
+#define AR71XX_PCI_WIN2_OFFS				0x12000000
+#define AR71XX_PCI_WIN3_OFFS				0x13000000
+#define AR71XX_PCI_WIN4_OFFS				0x14000000
+#define AR71XX_PCI_WIN5_OFFS				0x15000000
+#define AR71XX_PCI_WIN6_OFFS				0x16000000
+#define AR71XX_PCI_WIN7_OFFS				0x07000000
 
 #define AR71XX_PCI_CFG_BASE \
 	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
-#define AR71XX_PCI_CFG_SIZE             0x100
-
-#define AR7240_USB_CTRL_BASE            (AR71XX_APB_BASE + 0x00030000)
-#define AR7240_USB_CTRL_SIZE            0x100
-#define AR7240_OHCI_BASE                0x1b000000
-#define AR7240_OHCI_SIZE                0x1000
-
-#define AR724X_PCI_MEM_BASE             0x10000000
-#define AR724X_PCI_MEM_SIZE             0x04000000
-
-#define AR724X_PCI_CFG_BASE             0x14000000
-#define AR724X_PCI_CFG_SIZE             0x1000
-#define AR724X_PCI_CRP_BASE             (AR71XX_APB_BASE + 0x000c0000)
-#define AR724X_PCI_CRP_SIZE             0x1000
-#define AR724X_PCI_CTRL_BASE            (AR71XX_APB_BASE + 0x000f0000)
-#define AR724X_PCI_CTRL_SIZE            0x100
-
-#define AR724X_EHCI_BASE                0x1b000000
-#define AR724X_EHCI_SIZE                0x1000
-
-#define AR913X_EHCI_BASE                0x1b000000
-#define AR913X_EHCI_SIZE                0x1000
-#define AR913X_WMAC_BASE                (AR71XX_APB_BASE + 0x000C0000)
-#define AR913X_WMAC_SIZE                0x30000
-
-#define AR933X_UART_BASE                (AR71XX_APB_BASE + 0x00020000)
-#define AR933X_UART_SIZE                0x14
-#define AR933X_GMAC_BASE                (AR71XX_APB_BASE + 0x00070000)
-#define AR933X_GMAC_SIZE                0x04
-#define AR933X_WMAC_BASE                (AR71XX_APB_BASE + 0x00100000)
-#define AR933X_WMAC_SIZE                0x20000
-#define AR933X_RTC_BASE                 (AR71XX_APB_BASE + 0x00107000)
-#define AR933X_RTC_SIZE                 0x1000
-#define AR933X_EHCI_BASE                0x1b000000
-#define AR933X_EHCI_SIZE                0x1000
-#define AR933X_SRIF_BASE                (AR71XX_APB_BASE + 0x00116000)
-#define AR933X_SRIF_SIZE                0x1000
-
-#define AR934X_GMAC_BASE                (AR71XX_APB_BASE + 0x00070000)
-#define AR934X_GMAC_SIZE                0x14
-#define AR934X_WMAC_BASE                (AR71XX_APB_BASE + 0x00100000)
-#define AR934X_WMAC_SIZE                0x20000
-#define AR934X_EHCI_BASE                0x1b000000
-#define AR934X_EHCI_SIZE                0x200
-#define AR934X_NFC_BASE                 0x1b000200
-#define AR934X_NFC_SIZE                 0xb8
-#define AR934X_SRIF_BASE                (AR71XX_APB_BASE + 0x00116000)
-#define AR934X_SRIF_SIZE                0x1000
-
-#define QCA953X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
-#define QCA953X_GMAC_SIZE               0x14
-#define QCA953X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
-#define QCA953X_WMAC_SIZE               0x20000
-#define QCA953X_RTC_BASE                (AR71XX_APB_BASE + 0x00107000)
-#define QCA953X_RTC_SIZE                0x1000
-#define QCA953X_EHCI_BASE               0x1b000000
-#define QCA953X_EHCI_SIZE               0x200
-#define QCA953X_SRIF_BASE               (AR71XX_APB_BASE + 0x00116000)
-#define QCA953X_SRIF_SIZE               0x1000
-
-#define QCA953X_PCI_CFG_BASE0           0x14000000
-#define QCA953X_PCI_CTRL_BASE0          (AR71XX_APB_BASE + 0x000f0000)
-#define QCA953X_PCI_CRP_BASE0           (AR71XX_APB_BASE + 0x000c0000)
-#define QCA953X_PCI_MEM_BASE0           0x10000000
-#define QCA953X_PCI_MEM_SIZE            0x02000000
-
-#define QCA955X_PCI_MEM_BASE0           0x10000000
-#define QCA955X_PCI_MEM_BASE1           0x12000000
-#define QCA955X_PCI_MEM_SIZE            0x02000000
-#define QCA955X_PCI_CFG_BASE0           0x14000000
-#define QCA955X_PCI_CFG_BASE1           0x16000000
-#define QCA955X_PCI_CFG_SIZE            0x1000
-#define QCA955X_PCI_CRP_BASE0           (AR71XX_APB_BASE + 0x000c0000)
-#define QCA955X_PCI_CRP_BASE1           (AR71XX_APB_BASE + 0x00250000)
-#define QCA955X_PCI_CRP_SIZE            0x1000
-#define QCA955X_PCI_CTRL_BASE0          (AR71XX_APB_BASE + 0x000f0000)
-#define QCA955X_PCI_CTRL_BASE1          (AR71XX_APB_BASE + 0x00280000)
-#define QCA955X_PCI_CTRL_SIZE           0x100
-
-#define QCA955X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
-#define QCA955X_GMAC_SIZE               0x40
-#define QCA955X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
-#define QCA955X_WMAC_SIZE               0x20000
-#define QCA955X_EHCI0_BASE              0x1b000000
-#define QCA955X_EHCI1_BASE              0x1b400000
-#define QCA955X_EHCI_SIZE               0x1000
-#define QCA955X_NFC_BASE                0x1b800200
-#define QCA955X_NFC_SIZE                0xb8
-
-#define QCA956X_PCI_MEM_BASE1           0x12000000
-#define QCA956X_PCI_MEM_SIZE            0x02000000
-#define QCA956X_PCI_CFG_BASE1           0x16000000
-#define QCA956X_PCI_CFG_SIZE            0x1000
-#define QCA956X_PCI_CRP_BASE1           (AR71XX_APB_BASE + 0x00250000)
-#define QCA956X_PCI_CRP_SIZE            0x1000
-#define QCA956X_PCI_CTRL_BASE1          (AR71XX_APB_BASE + 0x00280000)
-#define QCA956X_PCI_CTRL_SIZE           0x100
-
-#define QCA956X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
-#define QCA956X_WMAC_SIZE               0x20000
-#define QCA956X_EHCI0_BASE              0x1b000000
-#define QCA956X_EHCI1_BASE              0x1b400000
-#define QCA956X_EHCI_SIZE               0x200
-#define QCA956X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
-#define QCA956X_GMAC_SIZE               0x64
+#define AR71XX_PCI_CFG_SIZE				0x100
+
+#define AR7240_USB_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE				0x100
+#define AR7240_OHCI_BASE				0x1b000000
+#define AR7240_OHCI_SIZE				0x1000
+
+#define AR724X_PCI_MEM_BASE				0x10000000
+#define AR724X_PCI_MEM_SIZE				0x04000000
+
+#define AR724X_PCI_CFG_BASE				0x14000000
+#define AR724X_PCI_CFG_SIZE				0x1000
+#define AR724X_PCI_CRP_BASE \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE				0x1000
+#define AR724X_PCI_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE				0x100
+
+#define AR724X_EHCI_BASE				0x1b000000
+#define AR724X_EHCI_SIZE				0x1000
+
+#define AR913X_EHCI_BASE				0x1b000000
+#define AR913X_EHCI_SIZE				0x1000
+#define AR913X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE				0x30000
+
+#define AR933X_UART_BASE \
+	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE				0x14
+#define AR933X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE				0x04
+#define AR933X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE				0x20000
+#define AR933X_RTC_BASE \
+	(AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_SIZE					0x1000
+#define AR933X_EHCI_BASE				0x1b000000
+#define AR933X_EHCI_SIZE				0x1000
+#define AR933X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_SIZE				0x1000
+
+#define AR934X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE				0x14
+#define AR934X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE				0x20000
+#define AR934X_EHCI_BASE				0x1b000000
+#define AR934X_EHCI_SIZE				0x200
+#define AR934X_NFC_BASE					0x1b000200
+#define AR934X_NFC_SIZE					0xb8
+#define AR934X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE				0x1000
+
+#define QCA953X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE				0x14
+#define QCA953X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE				0x20000
+#define QCA953X_RTC_BASE \
+	(AR71XX_APB_BASE + 0x00107000)
+#define QCA953X_RTC_SIZE				0x1000
+#define QCA953X_EHCI_BASE				0x1b000000
+#define QCA953X_EHCI_SIZE				0x200
+#define QCA953X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE				0x1000
+
+#define QCA953X_PCI_CFG_BASE0				0x14000000
+#define QCA953X_PCI_CTRL_BASE0 \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0 \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0				0x10000000
+#define QCA953X_PCI_MEM_SIZE				0x02000000
+
+#define QCA955X_PCI_MEM_BASE0				0x10000000
+#define QCA955X_PCI_MEM_BASE1				0x12000000
+#define QCA955X_PCI_MEM_SIZE				0x02000000
+#define QCA955X_PCI_CFG_BASE0				0x14000000
+#define QCA955X_PCI_CFG_BASE1				0x16000000
+#define QCA955X_PCI_CFG_SIZE				0x1000
+#define QCA955X_PCI_CRP_BASE0 \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1 \
+	(AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE				0x1000
+#define QCA955X_PCI_CTRL_BASE0 \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1 \
+	(AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE				0x100
+
+#define QCA955X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE				0x40
+#define QCA955X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE				0x20000
+#define QCA955X_EHCI0_BASE				0x1b000000
+#define QCA955X_EHCI1_BASE				0x1b400000
+#define QCA955X_EHCI_SIZE				0x1000
+#define QCA955X_NFC_BASE				0x1b800200
+#define QCA955X_NFC_SIZE				0xb8
+
+#define QCA956X_PCI_MEM_BASE1				0x12000000
+#define QCA956X_PCI_MEM_SIZE				0x02000000
+#define QCA956X_PCI_CFG_BASE1				0x16000000
+#define QCA956X_PCI_CFG_SIZE				0x1000
+#define QCA956X_PCI_CRP_BASE1 \
+	(AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE				0x1000
+#define QCA956X_PCI_CTRL_BASE1 \
+	(AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE				0x100
+
+#define QCA956X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE				0x20000
+#define QCA956X_EHCI0_BASE				0x1b000000
+#define QCA956X_EHCI1_BASE				0x1b400000
+#define QCA956X_EHCI_SIZE				0x200
+#define QCA956X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE				0x64
 
 /*
  * DDR_CTRL block
  */
-#define AR71XX_DDR_REG_CONFIG                           0x00
-#define AR71XX_DDR_REG_CONFIG2                          0x04
-#define AR71XX_DDR_REG_MODE                             0x08
-#define AR71XX_DDR_REG_EMR                              0x0c
-#define AR71XX_DDR_REG_CONTROL                          0x10
-#define AR71XX_DDR_REG_REFRESH                          0x14
-#define AR71XX_DDR_REG_RD_CYCLE                         0x18
-#define AR71XX_DDR_REG_TAP_CTRL0                        0x1c
-#define AR71XX_DDR_REG_TAP_CTRL1                        0x20
-
-#define AR71XX_DDR_REG_PCI_WIN0                         0x7c
-#define AR71XX_DDR_REG_PCI_WIN1                         0x80
-#define AR71XX_DDR_REG_PCI_WIN2                         0x84
-#define AR71XX_DDR_REG_PCI_WIN3                         0x88
-#define AR71XX_DDR_REG_PCI_WIN4                         0x8c
-#define AR71XX_DDR_REG_PCI_WIN5                         0x90
-#define AR71XX_DDR_REG_PCI_WIN6                         0x94
-#define AR71XX_DDR_REG_PCI_WIN7                         0x98
-#define AR71XX_DDR_REG_FLUSH_GE0                        0x9c
-#define AR71XX_DDR_REG_FLUSH_GE1                        0xa0
-#define AR71XX_DDR_REG_FLUSH_USB                        0xa4
-#define AR71XX_DDR_REG_FLUSH_PCI                        0xa8
-
-#define AR724X_DDR_REG_FLUSH_GE0                        0x7c
-#define AR724X_DDR_REG_FLUSH_GE1                        0x80
-#define AR724X_DDR_REG_FLUSH_USB                        0x84
-#define AR724X_DDR_REG_FLUSH_PCIE                       0x88
-
-#define AR913X_DDR_REG_FLUSH_GE0                        0x7c
-#define AR913X_DDR_REG_FLUSH_GE1                        0x80
-#define AR913X_DDR_REG_FLUSH_USB                        0x84
-#define AR913X_DDR_REG_FLUSH_WMAC                       0x88
-
-#define AR933X_DDR_REG_FLUSH_GE0                        0x7c
-#define AR933X_DDR_REG_FLUSH_GE1                        0x80
-#define AR933X_DDR_REG_FLUSH_USB                        0x84
-#define AR933X_DDR_REG_FLUSH_WMAC                       0x88
-#define AR933X_DDR_REG_DDR2_CONFIG                      0x8c
-#define AR933X_DDR_REG_EMR2                             0x90
-#define AR933X_DDR_REG_EMR3                             0x94
-#define AR933X_DDR_REG_BURST                            0x98
-#define AR933X_DDR_REG_TIMEOUT_MAX                      0x9c
-#define AR933X_DDR_REG_TIMEOUT_CNT                      0x9c
-#define AR933X_DDR_REG_TIMEOUT_ADDR                     0x9c
-
-#define AR934X_DDR_REG_FLUSH_GE0                        0x9c
-#define AR934X_DDR_REG_FLUSH_GE1                        0xa0
-#define AR934X_DDR_REG_FLUSH_USB                        0xa4
-#define AR934X_DDR_REG_FLUSH_PCIE                       0xa8
-#define AR934X_DDR_REG_FLUSH_WMAC                       0xac
-
-#define QCA953X_DDR_REG_FLUSH_GE0                       0x9c
-#define QCA953X_DDR_REG_FLUSH_GE1                       0xa0
-#define QCA953X_DDR_REG_FLUSH_USB                       0xa4
-#define QCA953X_DDR_REG_FLUSH_PCIE                      0xa8
-#define QCA953X_DDR_REG_FLUSH_WMAC                      0xac
-#define QCA953X_DDR_REG_DDR2_CONFIG                     0xb8
-#define QCA953X_DDR_REG_BURST                           0xc4
-#define QCA953X_DDR_REG_BURST2                          0xc8
-#define QCA953X_DDR_REG_TIMEOUT_MAX                     0xcc
-#define QCA953X_DDR_REG_CTL_CONF                        0x108
-#define QCA953X_DDR_REG_CONFIG3                         0x15c
+#define AR71XX_DDR_REG_CONFIG				0x00
+#define AR71XX_DDR_REG_CONFIG2				0x04
+#define AR71XX_DDR_REG_MODE				0x08
+#define AR71XX_DDR_REG_EMR				0x0c
+#define AR71XX_DDR_REG_CONTROL				0x10
+#define AR71XX_DDR_REG_REFRESH				0x14
+#define AR71XX_DDR_REG_RD_CYCLE				0x18
+#define AR71XX_DDR_REG_TAP_CTRL0			0x1c
+#define AR71XX_DDR_REG_TAP_CTRL1			0x20
+
+#define AR71XX_DDR_REG_PCI_WIN0				0x7c
+#define AR71XX_DDR_REG_PCI_WIN1				0x80
+#define AR71XX_DDR_REG_PCI_WIN2				0x84
+#define AR71XX_DDR_REG_PCI_WIN3				0x88
+#define AR71XX_DDR_REG_PCI_WIN4				0x8c
+#define AR71XX_DDR_REG_PCI_WIN5				0x90
+#define AR71XX_DDR_REG_PCI_WIN6				0x94
+#define AR71XX_DDR_REG_PCI_WIN7				0x98
+#define AR71XX_DDR_REG_FLUSH_GE0			0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1			0xa0
+#define AR71XX_DDR_REG_FLUSH_USB			0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI			0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0			0x7c
+#define AR724X_DDR_REG_FLUSH_GE1			0x80
+#define AR724X_DDR_REG_FLUSH_USB			0x84
+#define AR724X_DDR_REG_FLUSH_PCIE			0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0			0x7c
+#define AR913X_DDR_REG_FLUSH_GE1			0x80
+#define AR913X_DDR_REG_FLUSH_USB			0x84
+#define AR913X_DDR_REG_FLUSH_WMAC			0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0			0x7c
+#define AR933X_DDR_REG_FLUSH_GE1			0x80
+#define AR933X_DDR_REG_FLUSH_USB			0x84
+#define AR933X_DDR_REG_FLUSH_WMAC			0x88
+#define AR933X_DDR_REG_DDR2_CONFIG			0x8c
+#define AR933X_DDR_REG_EMR2				0x90
+#define AR933X_DDR_REG_EMR3				0x94
+#define AR933X_DDR_REG_BURST				0x98
+#define AR933X_DDR_REG_TIMEOUT_MAX			0x9c
+#define AR933X_DDR_REG_TIMEOUT_CNT			0x9c
+#define AR933X_DDR_REG_TIMEOUT_ADDR			0x9c
+
+#define AR934X_DDR_REG_FLUSH_GE0			0x9c
+#define AR934X_DDR_REG_FLUSH_GE1			0xa0
+#define AR934X_DDR_REG_FLUSH_USB			0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE			0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC			0xac
+
+#define QCA953X_DDR_REG_FLUSH_GE0			0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1			0xa0
+#define QCA953X_DDR_REG_FLUSH_USB			0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE			0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC			0xac
+#define QCA953X_DDR_REG_DDR2_CONFIG			0xb8
+#define QCA953X_DDR_REG_BURST				0xc4
+#define QCA953X_DDR_REG_BURST2				0xc8
+#define QCA953X_DDR_REG_TIMEOUT_MAX			0xcc
+#define QCA953X_DDR_REG_CTL_CONF			0x108
+#define QCA953X_DDR_REG_CONFIG3				0x15c
 
 /*
  * PLL block
  */
-#define AR71XX_PLL_REG_CPU_CONFIG                       0x00
-#define AR71XX_PLL_REG_SEC_CONFIG                       0x04
-#define AR71XX_PLL_REG_ETH0_INT_CLOCK                   0x10
-#define AR71XX_PLL_REG_ETH1_INT_CLOCK                   0x14
-
-#define AR71XX_PLL_DIV_SHIFT                            3
-#define AR71XX_PLL_DIV_MASK                             0x1f
-#define AR71XX_CPU_DIV_SHIFT                            16
-#define AR71XX_CPU_DIV_MASK                             0x3
-#define AR71XX_DDR_DIV_SHIFT                            18
-#define AR71XX_DDR_DIV_MASK                             0x3
-#define AR71XX_AHB_DIV_SHIFT                            20
-#define AR71XX_AHB_DIV_MASK                             0x7
-
-#define AR71XX_ETH0_PLL_SHIFT                           17
-#define AR71XX_ETH1_PLL_SHIFT                           19
-
-#define AR724X_PLL_REG_CPU_CONFIG                       0x00
-#define AR724X_PLL_REG_PCIE_CONFIG                      0x18
-
-#define AR724X_PLL_DIV_SHIFT                            0
-#define AR724X_PLL_DIV_MASK                             0x3ff
-#define AR724X_PLL_REF_DIV_SHIFT                        10
-#define AR724X_PLL_REF_DIV_MASK                         0xf
-#define AR724X_AHB_DIV_SHIFT                            19
-#define AR724X_AHB_DIV_MASK                             0x1
-#define AR724X_DDR_DIV_SHIFT                            22
-#define AR724X_DDR_DIV_MASK                             0x3
-
-#define AR7242_PLL_REG_ETH0_INT_CLOCK                   0x2c
-
-#define AR913X_PLL_REG_CPU_CONFIG                       0x00
-#define AR913X_PLL_REG_ETH_CONFIG                       0x04
-#define AR913X_PLL_REG_ETH0_INT_CLOCK                   0x14
-#define AR913X_PLL_REG_ETH1_INT_CLOCK                   0x18
-
-#define AR913X_PLL_DIV_SHIFT                            0
-#define AR913X_PLL_DIV_MASK                             0x3ff
-#define AR913X_DDR_DIV_SHIFT                            22
-#define AR913X_DDR_DIV_MASK                             0x3
-#define AR913X_AHB_DIV_SHIFT                            19
-#define AR913X_AHB_DIV_MASK                             0x1
-
-#define AR913X_ETH0_PLL_SHIFT                           20
-#define AR913X_ETH1_PLL_SHIFT                           22
-
-#define AR933X_PLL_CPU_CONFIG_REG                       0x00
-#define AR933X_PLL_CLK_CTRL_REG                         0x08
-#define AR933X_PLL_DITHER_FRAC_REG                      0x10
-
-#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT                10
-#define AR933X_PLL_CPU_CONFIG_NINT_MASK                 0x3f
-#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT              16
-#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK               0x1f
-#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT              23
-#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK               0x7
-
-#define AR933X_PLL_CLK_CTRL_BYPASS                      BIT(2)
-#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT          5
-#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK           0x3
-#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT          10
-#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK           0x3
-#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT          15
-#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK           0x7
-
-#define AR934X_PLL_CPU_CONFIG_REG                       0x00
-#define AR934X_PLL_DDR_CONFIG_REG                       0x04
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG                 0x08
-#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG             0x24
-#define AR934X_PLL_ETH_XMII_CONTROL_REG                 0x2c
-
-#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT               0
-#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK                0x3f
-#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT                6
-#define AR934X_PLL_CPU_CONFIG_NINT_MASK                 0x3f
-#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT              12
-#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK               0x1f
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT              19
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK               0x3
-
-#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT               0
-#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK                0x3ff
-#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT                10
-#define AR934X_PLL_DDR_CONFIG_NINT_MASK                 0x3f
-#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT              16
-#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK               0x1f
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT              23
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK               0x7
-
-#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS              BIT(2)
-#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS              BIT(3)
-#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS              BIT(4)
-#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT          5
-#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK           0x1f
-#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT          10
-#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK           0x1f
-#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT          15
-#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK           0x1f
-#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL          BIT(20)
-#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL          BIT(21)
-#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL          BIT(24)
-
-#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL         BIT(6)
-
-#define QCA953X_PLL_CPU_CONFIG_REG                      0x00
-#define QCA953X_PLL_DDR_CONFIG_REG                      0x04
-#define QCA953X_PLL_CLK_CTRL_REG                        0x08
-#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG            0x24
-#define QCA953X_PLL_ETH_XMII_CONTROL_REG                0x2c
-#define QCA953X_PLL_DDR_DIT_FRAC_REG                    0x44
-#define QCA953X_PLL_CPU_DIT_FRAC_REG                    0x48
-
-#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT              0
-#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK               0x3f
-#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT               6
-#define QCA953X_PLL_CPU_CONFIG_NINT_MASK                0x3f
-#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
-#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
-#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
-#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK              0x7
-
-#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT              0
-#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK               0x3ff
-#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT               10
-#define QCA953X_PLL_DDR_CONFIG_NINT_MASK                0x3f
-#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
-#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
-#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
-#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
-
-#define QCA953X_PLL_CONFIG_PWD                          BIT(30)
-
-#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
-#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
-#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
-#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
-#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
-#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
-#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
-#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
-#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
-#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
-#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
-#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
-
-#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT              0
-#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK               0x3f
-#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT              6
-#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK               0x3f
-#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT             12
-#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK              0x3f
-#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT               18
-#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK                0x3f
-
-#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT              0
-#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK               0x3ff
-#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT              9
-#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK               0x3ff
-#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT             20
-#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK              0x3f
-#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT               27
-#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK                0x3f
-
-#define QCA953X_PLL_DIT_FRAC_EN                         BIT(31)
-
-#define QCA955X_PLL_CPU_CONFIG_REG                      0x00
-#define QCA955X_PLL_DDR_CONFIG_REG                      0x04
-#define QCA955X_PLL_CLK_CTRL_REG                        0x08
-#define QCA955X_PLL_ETH_XMII_CONTROL_REG                0x28
-#define QCA955X_PLL_ETH_SGMII_CONTROL_REG               0x48
-
-#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT              0
-#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK               0x3f
-#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT               6
-#define QCA955X_PLL_CPU_CONFIG_NINT_MASK                0x3f
-#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
-#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
-#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
-#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK              0x3
-
-#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT              0
-#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK               0x3ff
-#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT               10
-#define QCA955X_PLL_DDR_CONFIG_NINT_MASK                0x3f
-#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
-#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
-#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
-#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
-
-#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
-#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
-#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
-#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
-#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
-#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
-#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
-#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
-#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
-#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
-#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
-#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
-
-#define QCA956X_PLL_CPU_CONFIG_REG                      0x00
-#define QCA956X_PLL_CPU_CONFIG1_REG                     0x04
-#define QCA956X_PLL_DDR_CONFIG_REG                      0x08
-#define QCA956X_PLL_DDR_CONFIG1_REG                     0x0c
-#define QCA956X_PLL_CLK_CTRL_REG                        0x10
-
-#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT             12
-#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK              0x1f
-#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT             19
-#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK              0x7
-
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT           0
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK            0x1f
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT           5
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK            0x3fff
-#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT              18
-#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK               0x1ff
-
-#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT             16
-#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK              0x1f
-#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT             23
-#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK              0x7
-
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT           0
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK            0x1f
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT           5
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK            0x3fff
-#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT              18
-#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK               0x1ff
-
-#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
-#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
-#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
-#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
-#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
-#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
-#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
-#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
-#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
-#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL     BIT(20)
-#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL     BIT(21)
-#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+#define AR71XX_PLL_REG_CPU_CONFIG			0x00
+#define AR71XX_PLL_REG_SEC_CONFIG			0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK			0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK			0x14
+
+#define AR71XX_PLL_DIV_SHIFT				3
+#define AR71XX_PLL_DIV_MASK				0x1f
+#define AR71XX_CPU_DIV_SHIFT				16
+#define AR71XX_CPU_DIV_MASK				0x3
+#define AR71XX_DDR_DIV_SHIFT				18
+#define AR71XX_DDR_DIV_MASK				0x3
+#define AR71XX_AHB_DIV_SHIFT				20
+#define AR71XX_AHB_DIV_MASK				0x7
+
+#define AR71XX_ETH0_PLL_SHIFT				17
+#define AR71XX_ETH1_PLL_SHIFT				19
+
+#define AR724X_PLL_REG_CPU_CONFIG			0x00
+#define AR724X_PLL_REG_PCIE_CONFIG			0x18
+
+#define AR724X_PLL_DIV_SHIFT				0
+#define AR724X_PLL_DIV_MASK				0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT			10
+#define AR724X_PLL_REF_DIV_MASK				0xf
+#define AR724X_AHB_DIV_SHIFT				19
+#define AR724X_AHB_DIV_MASK				0x1
+#define AR724X_DDR_DIV_SHIFT				22
+#define AR724X_DDR_DIV_MASK				0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK			0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG			0x00
+#define AR913X_PLL_REG_ETH_CONFIG			0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK			0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK			0x18
+
+#define AR913X_PLL_DIV_SHIFT				0
+#define AR913X_PLL_DIV_MASK				0x3ff
+#define AR913X_DDR_DIV_SHIFT				22
+#define AR913X_DDR_DIV_MASK				0x3
+#define AR913X_AHB_DIV_SHIFT				19
+#define AR913X_AHB_DIV_MASK				0x1
+
+#define AR913X_ETH0_PLL_SHIFT				20
+#define AR913X_ETH1_PLL_SHIFT				22
+
+#define AR933X_PLL_CPU_CONFIG_REG			0x00
+#define AR933X_PLL_CLK_CTRL_REG				0x08
+#define AR933X_PLL_DITHER_FRAC_REG			0x10
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT		10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK			0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT		16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT		23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define AR933X_PLL_CLK_CTRL_BYPASS			BIT(2)
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x3
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x3
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG			0x00
+#define AR934X_PLL_DDR_CONFIG_REG			0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG			0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG			0x2c
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT		6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK			0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK		0x3
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT		10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK			0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL		BIT(6)
+
+#define QCA953X_PLL_CPU_CONFIG_REG			0x00
+#define QCA953X_PLL_DDR_CONFIG_REG			0x04
+#define QCA953X_PLL_CLK_CTRL_REG			0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG		0x2c
+#define QCA953X_PLL_DDR_DIT_FRAC_REG			0x44
+#define QCA953X_PLL_CPU_DIT_FRAC_REG			0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT		6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT		10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK		0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA953X_PLL_CONFIG_PWD		BIT(30)
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT		0
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK		0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT		6
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK		0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT		12
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK		0x3f
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT		18
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK		0x3f
+
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT		0
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK		0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT		9
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK		0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT		20
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK		0x3f
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT		27
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK		0x3f
+
+#define QCA953X_PLL_DIT_FRAC_EN				BIT(31)
+
+#define QCA955X_PLL_CPU_CONFIG_REG			0x00
+#define QCA955X_PLL_DDR_CONFIG_REG			0x04
+#define QCA955X_PLL_CLK_CTRL_REG			0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG		0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG		0x48
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT		6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK		0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT		10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK		0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+
+#define QCA956X_PLL_CPU_CONFIG_REG			0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG			0x04
+#define QCA956X_PLL_DDR_CONFIG_REG			0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG			0x0c
+#define QCA956X_PLL_CLK_CTRL_REG			0x10
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL	BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
 
 /*
  * USB_CONFIG block
  */
-#define AR71XX_USB_CTRL_REG_FLADJ                       0x00
-#define AR71XX_USB_CTRL_REG_CONFIG                      0x04
+#define AR71XX_USB_CTRL_REG_FLADJ			0x00
+#define AR71XX_USB_CTRL_REG_CONFIG			0x04
 
 /*
  * RESET block
  */
-#define AR71XX_RESET_REG_TIMER                          0x00
-#define AR71XX_RESET_REG_TIMER_RELOAD                   0x04
-#define AR71XX_RESET_REG_WDOG_CTRL                      0x08
-#define AR71XX_RESET_REG_WDOG                           0x0c
-#define AR71XX_RESET_REG_MISC_INT_STATUS                0x10
-#define AR71XX_RESET_REG_MISC_INT_ENABLE                0x14
-#define AR71XX_RESET_REG_PCI_INT_STATUS                 0x18
-#define AR71XX_RESET_REG_PCI_INT_ENABLE                 0x1c
-#define AR71XX_RESET_REG_GLOBAL_INT_STATUS              0x20
-#define AR71XX_RESET_REG_RESET_MODULE                   0x24
-#define AR71XX_RESET_REG_PERFC_CTRL                     0x2c
-#define AR71XX_RESET_REG_PERFC0                         0x30
-#define AR71XX_RESET_REG_PERFC1                         0x34
-#define AR71XX_RESET_REG_REV_ID                         0x90
-
-#define AR913X_RESET_REG_GLOBAL_INT_STATUS              0x18
-#define AR913X_RESET_REG_RESET_MODULE                   0x1c
-#define AR913X_RESET_REG_PERF_CTRL                      0x20
-#define AR913X_RESET_REG_PERFC0                         0x24
-#define AR913X_RESET_REG_PERFC1                         0x28
-
-#define AR724X_RESET_REG_RESET_MODULE                   0x1c
-
-#define AR933X_RESET_REG_RESET_MODULE                   0x1c
-#define AR933X_RESET_REG_BOOTSTRAP                      0xac
-
-#define AR934X_RESET_REG_RESET_MODULE                   0x1c
-#define AR934X_RESET_REG_BOOTSTRAP                      0xb0
-#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS           0xac
-
-#define QCA953X_RESET_REG_RESET_MODULE                  0x1c
-#define QCA953X_RESET_REG_BOOTSTRAP                     0xb0
-#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS          0xac
-
-#define QCA955X_RESET_REG_RESET_MODULE                  0x1c
-#define QCA955X_RESET_REG_BOOTSTRAP                     0xb0
-#define QCA955X_RESET_REG_EXT_INT_STATUS                0xac
-
-#define QCA956X_RESET_REG_RESET_MODULE                  0x1c
-#define QCA956X_RESET_REG_BOOTSTRAP                     0xb0
-#define QCA956X_RESET_REG_EXT_INT_STATUS                0xac
-
-#define MISC_INT_MIPS_SI_TIMERINT_MASK                  BIT(28)
-#define MISC_INT_ETHSW                                  BIT(12)
-#define MISC_INT_TIMER4                                 BIT(10)
-#define MISC_INT_TIMER3                                 BIT(9)
-#define MISC_INT_TIMER2                                 BIT(8)
-#define MISC_INT_DMA                                    BIT(7)
-#define MISC_INT_OHCI                                   BIT(6)
-#define MISC_INT_PERFC                                  BIT(5)
-#define MISC_INT_WDOG                                   BIT(4)
-#define MISC_INT_UART                                   BIT(3)
-#define MISC_INT_GPIO                                   BIT(2)
-#define MISC_INT_ERROR                                  BIT(1)
-#define MISC_INT_TIMER                                  BIT(0)
-
-#define AR71XX_RESET_EXTERNAL                           BIT(28)
-#define AR71XX_RESET_FULL_CHIP                          BIT(24)
-#define AR71XX_RESET_CPU_NMI                            BIT(21)
-#define AR71XX_RESET_CPU_COLD                           BIT(20)
-#define AR71XX_RESET_DMA                                BIT(19)
-#define AR71XX_RESET_SLIC                               BIT(18)
-#define AR71XX_RESET_STEREO                             BIT(17)
-#define AR71XX_RESET_DDR                                BIT(16)
-#define AR71XX_RESET_GE1_MAC                            BIT(13)
-#define AR71XX_RESET_GE1_PHY                            BIT(12)
-#define AR71XX_RESET_USBSUS_OVERRIDE                    BIT(10)
-#define AR71XX_RESET_GE0_MAC                            BIT(9)
-#define AR71XX_RESET_GE0_PHY                            BIT(8)
-#define AR71XX_RESET_USB_OHCI_DLL                       BIT(6)
-#define AR71XX_RESET_USB_HOST                           BIT(5)
-#define AR71XX_RESET_USB_PHY                            BIT(4)
-#define AR71XX_RESET_PCI_BUS                            BIT(1)
-#define AR71XX_RESET_PCI_CORE                           BIT(0)
-
-#define AR7240_RESET_USB_HOST                           BIT(5)
-#define AR7240_RESET_OHCI_DLL                           BIT(3)
-
-#define AR724X_RESET_GE1_MDIO                           BIT(23)
-#define AR724X_RESET_GE0_MDIO                           BIT(22)
-#define AR724X_RESET_PCIE_PHY_SERIAL                    BIT(10)
-#define AR724X_RESET_PCIE_PHY                           BIT(7)
-#define AR724X_RESET_PCIE                               BIT(6)
-#define AR724X_RESET_USB_HOST                           BIT(5)
-#define AR724X_RESET_USB_PHY                            BIT(4)
-#define AR724X_RESET_USBSUS_OVERRIDE                    BIT(3)
-
-#define AR913X_RESET_AMBA2WMAC                          BIT(22)
-#define AR913X_RESET_USBSUS_OVERRIDE                    BIT(10)
-#define AR913X_RESET_USB_HOST                           BIT(5)
-#define AR913X_RESET_USB_PHY                            BIT(4)
-
-#define AR933X_RESET_GE1_MDIO                           BIT(23)
-#define AR933X_RESET_GE0_MDIO                           BIT(22)
-#define AR933X_RESET_GE1_MAC                            BIT(13)
-#define AR933X_RESET_WMAC                               BIT(11)
-#define AR933X_RESET_GE0_MAC                            BIT(9)
-#define AR933X_RESET_USB_HOST                           BIT(5)
-#define AR933X_RESET_USB_PHY                            BIT(4)
-#define AR933X_RESET_USBSUS_OVERRIDE                    BIT(3)
-
-#define AR934X_RESET_HOST                               BIT(31)
-#define AR934X_RESET_SLIC                               BIT(30)
-#define AR934X_RESET_HDMA                               BIT(29)
-#define AR934X_RESET_EXTERNAL                           BIT(28)
-#define AR934X_RESET_RTC                                BIT(27)
-#define AR934X_RESET_PCIE_EP_INT                        BIT(26)
-#define AR934X_RESET_CHKSUM_ACC                         BIT(25)
-#define AR934X_RESET_FULL_CHIP                          BIT(24)
-#define AR934X_RESET_GE1_MDIO                           BIT(23)
-#define AR934X_RESET_GE0_MDIO                           BIT(22)
-#define AR934X_RESET_CPU_NMI                            BIT(21)
-#define AR934X_RESET_CPU_COLD                           BIT(20)
-#define AR934X_RESET_HOST_RESET_INT                     BIT(19)
-#define AR934X_RESET_PCIE_EP                            BIT(18)
-#define AR934X_RESET_UART1                              BIT(17)
-#define AR934X_RESET_DDR                                BIT(16)
-#define AR934X_RESET_USB_PHY_PLL_PWD_EXT                BIT(15)
-#define AR934X_RESET_NANDF                              BIT(14)
-#define AR934X_RESET_GE1_MAC                            BIT(13)
-#define AR934X_RESET_ETH_SWITCH_ANALOG                  BIT(12)
-#define AR934X_RESET_USB_PHY_ANALOG                     BIT(11)
-#define AR934X_RESET_HOST_DMA_INT                       BIT(10)
-#define AR934X_RESET_GE0_MAC                            BIT(9)
-#define AR934X_RESET_ETH_SWITCH                         BIT(8)
-#define AR934X_RESET_PCIE_PHY                           BIT(7)
-#define AR934X_RESET_PCIE                               BIT(6)
-#define AR934X_RESET_USB_HOST                           BIT(5)
-#define AR934X_RESET_USB_PHY                            BIT(4)
-#define AR934X_RESET_USBSUS_OVERRIDE                    BIT(3)
-#define AR934X_RESET_LUT                                BIT(2)
-#define AR934X_RESET_MBOX                               BIT(1)
-#define AR934X_RESET_I2S                                BIT(0)
-
-#define QCA953X_RESET_USB_EXT_PWR                       BIT(29)
-#define QCA953X_RESET_EXTERNAL                          BIT(28)
-#define QCA953X_RESET_RTC                               BIT(27)
-#define QCA953X_RESET_FULL_CHIP                         BIT(24)
-#define QCA953X_RESET_GE1_MDIO                          BIT(23)
-#define QCA953X_RESET_GE0_MDIO                          BIT(22)
-#define QCA953X_RESET_CPU_NMI                           BIT(21)
-#define QCA953X_RESET_CPU_COLD                          BIT(20)
-#define QCA953X_RESET_DDR                               BIT(16)
-#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT               BIT(15)
-#define QCA953X_RESET_GE1_MAC                           BIT(13)
-#define QCA953X_RESET_ETH_SWITCH_ANALOG                 BIT(12)
-#define QCA953X_RESET_USB_PHY_ANALOG                    BIT(11)
-#define QCA953X_RESET_GE0_MAC                           BIT(9)
-#define QCA953X_RESET_ETH_SWITCH                        BIT(8)
-#define QCA953X_RESET_PCIE_PHY                          BIT(7)
-#define QCA953X_RESET_PCIE                              BIT(6)
-#define QCA953X_RESET_USB_HOST                          BIT(5)
-#define QCA953X_RESET_USB_PHY                           BIT(4)
-#define QCA953X_RESET_USBSUS_OVERRIDE                   BIT(3)
-
-#define QCA955X_RESET_HOST                              BIT(31)
-#define QCA955X_RESET_SLIC                              BIT(30)
-#define QCA955X_RESET_HDMA                              BIT(29)
-#define QCA955X_RESET_EXTERNAL                          BIT(28)
-#define QCA955X_RESET_RTC                               BIT(27)
-#define QCA955X_RESET_PCIE_EP_INT                       BIT(26)
-#define QCA955X_RESET_CHKSUM_ACC                        BIT(25)
-#define QCA955X_RESET_FULL_CHIP                         BIT(24)
-#define QCA955X_RESET_GE1_MDIO                          BIT(23)
-#define QCA955X_RESET_GE0_MDIO                          BIT(22)
-#define QCA955X_RESET_CPU_NMI                           BIT(21)
-#define QCA955X_RESET_CPU_COLD                          BIT(20)
-#define QCA955X_RESET_HOST_RESET_INT                    BIT(19)
-#define QCA955X_RESET_PCIE_EP                           BIT(18)
-#define QCA955X_RESET_UART1                             BIT(17)
-#define QCA955X_RESET_DDR                               BIT(16)
-#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT               BIT(15)
-#define QCA955X_RESET_NANDF                             BIT(14)
-#define QCA955X_RESET_GE1_MAC                           BIT(13)
-#define QCA955X_RESET_SGMII_ANALOG                      BIT(12)
-#define QCA955X_RESET_USB_PHY_ANALOG                    BIT(11)
-#define QCA955X_RESET_HOST_DMA_INT                      BIT(10)
-#define QCA955X_RESET_GE0_MAC                           BIT(9)
-#define QCA955X_RESET_SGMII                             BIT(8)
-#define QCA955X_RESET_PCIE_PHY                          BIT(7)
-#define QCA955X_RESET_PCIE                              BIT(6)
-#define QCA955X_RESET_USB_HOST                          BIT(5)
-#define QCA955X_RESET_USB_PHY                           BIT(4)
-#define QCA955X_RESET_USBSUS_OVERRIDE                   BIT(3)
-#define QCA955X_RESET_LUT                               BIT(2)
-#define QCA955X_RESET_MBOX                              BIT(1)
-#define QCA955X_RESET_I2S                               BIT(0)
-
-#define AR933X_BOOTSTRAP_MDIO_GPIO_EN                   BIT(18)
-#define AR933X_BOOTSTRAP_DDR2                           BIT(13)
-#define AR933X_BOOTSTRAP_EEPBUSY                        BIT(4)
-#define AR933X_BOOTSTRAP_REF_CLK_40                     BIT(0)
-
-#define AR934X_BOOTSTRAP_SW_OPTION8                     BIT(23)
-#define AR934X_BOOTSTRAP_SW_OPTION7                     BIT(22)
-#define AR934X_BOOTSTRAP_SW_OPTION6                     BIT(21)
-#define AR934X_BOOTSTRAP_SW_OPTION5                     BIT(20)
-#define AR934X_BOOTSTRAP_SW_OPTION4                     BIT(19)
-#define AR934X_BOOTSTRAP_SW_OPTION3                     BIT(18)
-#define AR934X_BOOTSTRAP_SW_OPTION2                     BIT(17)
-#define AR934X_BOOTSTRAP_SW_OPTION1                     BIT(16)
-#define AR934X_BOOTSTRAP_USB_MODE_DEVICE                BIT(7)
-#define AR934X_BOOTSTRAP_PCIE_RC                        BIT(6)
-#define AR934X_BOOTSTRAP_EJTAG_MODE                     BIT(5)
-#define AR934X_BOOTSTRAP_REF_CLK_40                     BIT(4)
-#define AR934X_BOOTSTRAP_BOOT_FROM_SPI                  BIT(2)
-#define AR934X_BOOTSTRAP_SDRAM_DISABLED                 BIT(1)
-#define AR934X_BOOTSTRAP_DDR1                           BIT(0)
-
-#define QCA953X_BOOTSTRAP_SW_OPTION2                    BIT(12)
-#define QCA953X_BOOTSTRAP_SW_OPTION1                    BIT(11)
-#define QCA953X_BOOTSTRAP_EJTAG_MODE                    BIT(5)
-#define QCA953X_BOOTSTRAP_REF_CLK_40                    BIT(4)
-#define QCA953X_BOOTSTRAP_SDRAM_DISABLED                BIT(1)
-#define QCA953X_BOOTSTRAP_DDR1                          BIT(0)
-
-#define QCA955X_BOOTSTRAP_REF_CLK_40                    BIT(4)
-
-#define QCA956X_BOOTSTRAP_REF_CLK_40                    BIT(2)
-
-#define AR934X_PCIE_WMAC_INT_WMAC_MISC                  BIT(0)
-#define AR934X_PCIE_WMAC_INT_WMAC_TX                    BIT(1)
-#define AR934X_PCIE_WMAC_INT_WMAC_RXLP                  BIT(2)
-#define AR934X_PCIE_WMAC_INT_WMAC_RXHP                  BIT(3)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC                    BIT(4)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC0                   BIT(5)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC1                   BIT(6)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC2                   BIT(7)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC3                   BIT(8)
+#define AR71XX_RESET_REG_TIMER				0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD			0x04
+#define AR71XX_RESET_REG_WDOG_CTRL			0x08
+#define AR71XX_RESET_REG_WDOG				0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS		0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE		0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS			0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE			0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS		0x20
+#define AR71XX_RESET_REG_RESET_MODULE			0x24
+#define AR71XX_RESET_REG_PERFC_CTRL			0x2c
+#define AR71XX_RESET_REG_PERFC0				0x30
+#define AR71XX_RESET_REG_PERFC1				0x34
+#define AR71XX_RESET_REG_REV_ID				0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS		0x18
+#define AR913X_RESET_REG_RESET_MODULE			0x1c
+#define AR913X_RESET_REG_PERF_CTRL			0x20
+#define AR913X_RESET_REG_PERFC0				0x24
+#define AR913X_RESET_REG_PERFC1				0x28
+
+#define AR724X_RESET_REG_RESET_MODULE			0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE			0x1c
+#define AR933X_RESET_REG_BOOTSTRAP			0xac
+
+#define AR934X_RESET_REG_RESET_MODULE			0x1c
+#define AR934X_RESET_REG_BOOTSTRAP			0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS		0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE			0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP			0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS		0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE			0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP			0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS		0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE			0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP			0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS		0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK			BIT(28)
+#define MISC_INT_ETHSW					BIT(12)
+#define MISC_INT_TIMER4					BIT(10)
+#define MISC_INT_TIMER3					BIT(9)
+#define MISC_INT_TIMER2					BIT(8)
+#define MISC_INT_DMA					BIT(7)
+#define MISC_INT_OHCI					BIT(6)
+#define MISC_INT_PERFC					BIT(5)
+#define MISC_INT_WDOG					BIT(4)
+#define MISC_INT_UART					BIT(3)
+#define MISC_INT_GPIO					BIT(2)
+#define MISC_INT_ERROR					BIT(1)
+#define MISC_INT_TIMER					BIT(0)
+
+#define AR71XX_RESET_EXTERNAL				BIT(28)
+#define AR71XX_RESET_FULL_CHIP				BIT(24)
+#define AR71XX_RESET_CPU_NMI				BIT(21)
+#define AR71XX_RESET_CPU_COLD				BIT(20)
+#define AR71XX_RESET_DMA				BIT(19)
+#define AR71XX_RESET_SLIC				BIT(18)
+#define AR71XX_RESET_STEREO				BIT(17)
+#define AR71XX_RESET_DDR				BIT(16)
+#define AR71XX_RESET_GE1_MAC				BIT(13)
+#define AR71XX_RESET_GE1_PHY				BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE			BIT(10)
+#define AR71XX_RESET_GE0_MAC				BIT(9)
+#define AR71XX_RESET_GE0_PHY				BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL			BIT(6)
+#define AR71XX_RESET_USB_HOST				BIT(5)
+#define AR71XX_RESET_USB_PHY				BIT(4)
+#define AR71XX_RESET_PCI_BUS				BIT(1)
+#define AR71XX_RESET_PCI_CORE				BIT(0)
+
+#define AR7240_RESET_USB_HOST				BIT(5)
+#define AR7240_RESET_OHCI_DLL				BIT(3)
+
+#define AR724X_RESET_GE1_MDIO				BIT(23)
+#define AR724X_RESET_GE0_MDIO				BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL			BIT(10)
+#define AR724X_RESET_PCIE_PHY				BIT(7)
+#define AR724X_RESET_PCIE				BIT(6)
+#define AR724X_RESET_USB_HOST				BIT(5)
+#define AR724X_RESET_USB_PHY				BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE			BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC				BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE			BIT(10)
+#define AR913X_RESET_USB_HOST				BIT(5)
+#define AR913X_RESET_USB_PHY				BIT(4)
+
+#define AR933X_RESET_GE1_MDIO				BIT(23)
+#define AR933X_RESET_GE0_MDIO				BIT(22)
+#define AR933X_RESET_GE1_MAC				BIT(13)
+#define AR933X_RESET_WMAC				BIT(11)
+#define AR933X_RESET_GE0_MAC				BIT(9)
+#define AR933X_RESET_USB_HOST				BIT(5)
+#define AR933X_RESET_USB_PHY				BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE			BIT(3)
+
+#define AR934X_RESET_HOST				BIT(31)
+#define AR934X_RESET_SLIC				BIT(30)
+#define AR934X_RESET_HDMA				BIT(29)
+#define AR934X_RESET_EXTERNAL				BIT(28)
+#define AR934X_RESET_RTC				BIT(27)
+#define AR934X_RESET_PCIE_EP_INT			BIT(26)
+#define AR934X_RESET_CHKSUM_ACC				BIT(25)
+#define AR934X_RESET_FULL_CHIP				BIT(24)
+#define AR934X_RESET_GE1_MDIO				BIT(23)
+#define AR934X_RESET_GE0_MDIO				BIT(22)
+#define AR934X_RESET_CPU_NMI				BIT(21)
+#define AR934X_RESET_CPU_COLD				BIT(20)
+#define AR934X_RESET_HOST_RESET_INT			BIT(19)
+#define AR934X_RESET_PCIE_EP				BIT(18)
+#define AR934X_RESET_UART1				BIT(17)
+#define AR934X_RESET_DDR				BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT		BIT(15)
+#define AR934X_RESET_NANDF				BIT(14)
+#define AR934X_RESET_GE1_MAC				BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG			BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG			BIT(11)
+#define AR934X_RESET_HOST_DMA_INT			BIT(10)
+#define AR934X_RESET_GE0_MAC				BIT(9)
+#define AR934X_RESET_ETH_SWITCH				BIT(8)
+#define AR934X_RESET_PCIE_PHY				BIT(7)
+#define AR934X_RESET_PCIE				BIT(6)
+#define AR934X_RESET_USB_HOST				BIT(5)
+#define AR934X_RESET_USB_PHY				BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE			BIT(3)
+#define AR934X_RESET_LUT				BIT(2)
+#define AR934X_RESET_MBOX				BIT(1)
+#define AR934X_RESET_I2S				BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR			BIT(29)
+#define QCA953X_RESET_EXTERNAL				BIT(28)
+#define QCA953X_RESET_RTC				BIT(27)
+#define QCA953X_RESET_FULL_CHIP				BIT(24)
+#define QCA953X_RESET_GE1_MDIO				BIT(23)
+#define QCA953X_RESET_GE0_MDIO				BIT(22)
+#define QCA953X_RESET_CPU_NMI				BIT(21)
+#define QCA953X_RESET_CPU_COLD				BIT(20)
+#define QCA953X_RESET_DDR				BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT		BIT(15)
+#define QCA953X_RESET_GE1_MAC				BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG			BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG			BIT(11)
+#define QCA953X_RESET_GE0_MAC				BIT(9)
+#define QCA953X_RESET_ETH_SWITCH			BIT(8)
+#define QCA953X_RESET_PCIE_PHY				BIT(7)
+#define QCA953X_RESET_PCIE				BIT(6)
+#define QCA953X_RESET_USB_HOST				BIT(5)
+#define QCA953X_RESET_USB_PHY				BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE			BIT(3)
+
+#define QCA955X_RESET_HOST				BIT(31)
+#define QCA955X_RESET_SLIC				BIT(30)
+#define QCA955X_RESET_HDMA				BIT(29)
+#define QCA955X_RESET_EXTERNAL				BIT(28)
+#define QCA955X_RESET_RTC				BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT			BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC			BIT(25)
+#define QCA955X_RESET_FULL_CHIP				BIT(24)
+#define QCA955X_RESET_GE1_MDIO				BIT(23)
+#define QCA955X_RESET_GE0_MDIO				BIT(22)
+#define QCA955X_RESET_CPU_NMI				BIT(21)
+#define QCA955X_RESET_CPU_COLD				BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT			BIT(19)
+#define QCA955X_RESET_PCIE_EP				BIT(18)
+#define QCA955X_RESET_UART1				BIT(17)
+#define QCA955X_RESET_DDR				BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT		BIT(15)
+#define QCA955X_RESET_NANDF				BIT(14)
+#define QCA955X_RESET_GE1_MAC				BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG			BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG			BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT			BIT(10)
+#define QCA955X_RESET_GE0_MAC				BIT(9)
+#define QCA955X_RESET_SGMII				BIT(8)
+#define QCA955X_RESET_PCIE_PHY				BIT(7)
+#define QCA955X_RESET_PCIE				BIT(6)
+#define QCA955X_RESET_USB_HOST				BIT(5)
+#define QCA955X_RESET_USB_PHY				BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE			BIT(3)
+#define QCA955X_RESET_LUT				BIT(2)
+#define QCA955X_RESET_MBOX				BIT(1)
+#define QCA955X_RESET_I2S				BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN			BIT(18)
+#define AR933X_BOOTSTRAP_DDR2				BIT(13)
+#define AR933X_BOOTSTRAP_EEPBUSY			BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40			BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8			BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7			BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6			BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5			BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4			BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3			BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2			BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1			BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE		BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC			BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE			BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40			BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI			BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED			BIT(1)
+#define AR934X_BOOTSTRAP_DDR1				BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2			BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1			BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE			BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40			BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED		BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1				BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40			BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40			BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC			BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX			BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP			BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP			BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC			BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0			BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1			BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2			BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3			BIT(8)
 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \
 	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
 	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
@@ -728,15 +763,15 @@
 	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
 	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
 
-#define QCA953X_PCIE_WMAC_INT_WMAC_MISC                 BIT(0)
-#define QCA953X_PCIE_WMAC_INT_WMAC_TX                   BIT(1)
-#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP                 BIT(2)
-#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP                 BIT(3)
-#define QCA953X_PCIE_WMAC_INT_PCIE_RC                   BIT(4)
-#define QCA953X_PCIE_WMAC_INT_PCIE_RC0                  BIT(5)
-#define QCA953X_PCIE_WMAC_INT_PCIE_RC1                  BIT(6)
-#define QCA953X_PCIE_WMAC_INT_PCIE_RC2                  BIT(7)
-#define QCA953X_PCIE_WMAC_INT_PCIE_RC3                  BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC			BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX			BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP			BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP			BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC			BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0			BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1			BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2			BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3			BIT(8)
 #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
 	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
 	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
@@ -746,22 +781,22 @@
 	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
 	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
 
-#define QCA955X_EXT_INT_WMAC_MISC                       BIT(0)
-#define QCA955X_EXT_INT_WMAC_TX                         BIT(1)
-#define QCA955X_EXT_INT_WMAC_RXLP                       BIT(2)
-#define QCA955X_EXT_INT_WMAC_RXHP                       BIT(3)
-#define QCA955X_EXT_INT_PCIE_RC1                        BIT(4)
-#define QCA955X_EXT_INT_PCIE_RC1_INT0                   BIT(5)
-#define QCA955X_EXT_INT_PCIE_RC1_INT1                   BIT(6)
-#define QCA955X_EXT_INT_PCIE_RC1_INT2                   BIT(7)
-#define QCA955X_EXT_INT_PCIE_RC1_INT3                   BIT(8)
-#define QCA955X_EXT_INT_PCIE_RC2                        BIT(12)
-#define QCA955X_EXT_INT_PCIE_RC2_INT0                   BIT(13)
-#define QCA955X_EXT_INT_PCIE_RC2_INT1                   BIT(14)
-#define QCA955X_EXT_INT_PCIE_RC2_INT2                   BIT(15)
-#define QCA955X_EXT_INT_PCIE_RC2_INT3                   BIT(16)
-#define QCA955X_EXT_INT_USB1                            BIT(24)
-#define QCA955X_EXT_INT_USB2                            BIT(28)
+#define QCA955X_EXT_INT_WMAC_MISC			BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX				BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP			BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP			BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1			BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0			BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1			BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2			BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3			BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2			BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0			BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1			BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2			BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3			BIT(16)
+#define QCA955X_EXT_INT_USB1				BIT(24)
+#define QCA955X_EXT_INT_USB2				BIT(28)
 
 #define QCA955X_EXT_INT_WMAC_ALL \
 	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
@@ -777,22 +812,22 @@
 	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
 	 QCA955X_EXT_INT_PCIE_RC2_INT3)
 
-#define QCA956X_EXT_INT_WMAC_MISC                       BIT(0)
-#define QCA956X_EXT_INT_WMAC_TX                         BIT(1)
-#define QCA956X_EXT_INT_WMAC_RXLP                       BIT(2)
-#define QCA956X_EXT_INT_WMAC_RXHP                       BIT(3)
-#define QCA956X_EXT_INT_PCIE_RC1                        BIT(4)
-#define QCA956X_EXT_INT_PCIE_RC1_INT0                   BIT(5)
-#define QCA956X_EXT_INT_PCIE_RC1_INT1                   BIT(6)
-#define QCA956X_EXT_INT_PCIE_RC1_INT2                   BIT(7)
-#define QCA956X_EXT_INT_PCIE_RC1_INT3                   BIT(8)
-#define QCA956X_EXT_INT_PCIE_RC2                        BIT(12)
-#define QCA956X_EXT_INT_PCIE_RC2_INT0                   BIT(13)
-#define QCA956X_EXT_INT_PCIE_RC2_INT1                   BIT(14)
-#define QCA956X_EXT_INT_PCIE_RC2_INT2                   BIT(15)
-#define QCA956X_EXT_INT_PCIE_RC2_INT3                   BIT(16)
-#define QCA956X_EXT_INT_USB1                            BIT(24)
-#define QCA956X_EXT_INT_USB2                            BIT(28)
+#define QCA956X_EXT_INT_WMAC_MISC			BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX				BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP			BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP			BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1			BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0			BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1			BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2			BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3			BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2			BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0			BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1			BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2			BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3			BIT(16)
+#define QCA956X_EXT_INT_USB1				BIT(24)
+#define QCA956X_EXT_INT_USB2				BIT(28)
 
 #define QCA956X_EXT_INT_WMAC_ALL \
 	(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
@@ -808,377 +843,377 @@
 	 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
 	 QCA956X_EXT_INT_PCIE_RC2_INT3)
 
-#define REV_ID_MAJOR_MASK                               0xfff0
-#define REV_ID_MAJOR_AR71XX                             0x00a0
-#define REV_ID_MAJOR_AR913X                             0x00b0
-#define REV_ID_MAJOR_AR7240                             0x00c0
-#define REV_ID_MAJOR_AR7241                             0x0100
-#define REV_ID_MAJOR_AR7242                             0x1100
-#define REV_ID_MAJOR_AR9330                             0x0110
-#define REV_ID_MAJOR_AR9331                             0x1110
-#define REV_ID_MAJOR_AR9341                             0x0120
-#define REV_ID_MAJOR_AR9342                             0x1120
-#define REV_ID_MAJOR_AR9344                             0x2120
-#define REV_ID_MAJOR_QCA9533                            0x0140
-#define REV_ID_MAJOR_QCA9533_V2                         0x0160
-#define REV_ID_MAJOR_QCA9556                            0x0130
-#define REV_ID_MAJOR_QCA9558                            0x1130
-#define REV_ID_MAJOR_TP9343                             0x0150
-#define REV_ID_MAJOR_QCA9561                            0x1150
-
-#define AR71XX_REV_ID_MINOR_MASK                        0x3
-#define AR71XX_REV_ID_MINOR_AR7130                      0x0
-#define AR71XX_REV_ID_MINOR_AR7141                      0x1
-#define AR71XX_REV_ID_MINOR_AR7161                      0x2
-#define AR913X_REV_ID_MINOR_AR9130                      0x0
-#define AR913X_REV_ID_MINOR_AR9132                      0x1
-
-#define AR71XX_REV_ID_REVISION_MASK                     0x3
-#define AR71XX_REV_ID_REVISION_SHIFT                    2
-#define AR71XX_REV_ID_REVISION2_MASK                    0xf
+#define REV_ID_MAJOR_MASK				0xfff0
+#define REV_ID_MAJOR_AR71XX				0x00a0
+#define REV_ID_MAJOR_AR913X				0x00b0
+#define REV_ID_MAJOR_AR7240				0x00c0
+#define REV_ID_MAJOR_AR7241				0x0100
+#define REV_ID_MAJOR_AR7242				0x1100
+#define REV_ID_MAJOR_AR9330				0x0110
+#define REV_ID_MAJOR_AR9331				0x1110
+#define REV_ID_MAJOR_AR9341				0x0120
+#define REV_ID_MAJOR_AR9342				0x1120
+#define REV_ID_MAJOR_AR9344				0x2120
+#define REV_ID_MAJOR_QCA9533				0x0140
+#define REV_ID_MAJOR_QCA9533_V2				0x0160
+#define REV_ID_MAJOR_QCA9556				0x0130
+#define REV_ID_MAJOR_QCA9558				0x1130
+#define REV_ID_MAJOR_TP9343				0x0150
+#define REV_ID_MAJOR_QCA9561				0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK			0x3
+#define AR71XX_REV_ID_MINOR_AR7130			0x0
+#define AR71XX_REV_ID_MINOR_AR7141			0x1
+#define AR71XX_REV_ID_MINOR_AR7161			0x2
+#define AR913X_REV_ID_MINOR_AR9130			0x0
+#define AR913X_REV_ID_MINOR_AR9132			0x1
+
+#define AR71XX_REV_ID_REVISION_MASK			0x3
+#define AR71XX_REV_ID_REVISION_SHIFT			2
+#define AR71XX_REV_ID_REVISION2_MASK			0xf
 
 /*
  * RTC block
  */
-#define AR933X_RTC_REG_RESET                            0x40
-#define AR933X_RTC_REG_STATUS                           0x44
-#define AR933X_RTC_REG_DERIVED                          0x48
-#define AR933X_RTC_REG_FORCE_WAKE                       0x4c
-#define AR933X_RTC_REG_INT_CAUSE                        0x50
-#define AR933X_RTC_REG_CAUSE_CLR                        0x50
-#define AR933X_RTC_REG_INT_ENABLE                       0x54
-#define AR933X_RTC_REG_INT_MASKE                        0x58
-
-#define QCA953X_RTC_REG_SYNC_RESET                      0x40
-#define QCA953X_RTC_REG_SYNC_STATUS                     0x44
+#define AR933X_RTC_REG_RESET				0x40
+#define AR933X_RTC_REG_STATUS				0x44
+#define AR933X_RTC_REG_DERIVED				0x48
+#define AR933X_RTC_REG_FORCE_WAKE			0x4c
+#define AR933X_RTC_REG_INT_CAUSE			0x50
+#define AR933X_RTC_REG_CAUSE_CLR			0x50
+#define AR933X_RTC_REG_INT_ENABLE			0x54
+#define AR933X_RTC_REG_INT_MASKE			0x58
+
+#define QCA953X_RTC_REG_SYNC_RESET			0x40
+#define QCA953X_RTC_REG_SYNC_STATUS			0x44
 
 /*
  * SPI block
  */
-#define AR71XX_SPI_REG_FS                               0x00
-#define AR71XX_SPI_REG_CTRL                             0x04
-#define AR71XX_SPI_REG_IOC                              0x08
-#define AR71XX_SPI_REG_RDS                              0x0c
-
-#define AR71XX_SPI_FS_GPIO                              BIT(0)
-
-#define AR71XX_SPI_CTRL_RD                              BIT(6)
-#define AR71XX_SPI_CTRL_DIV_MASK                        0x3f
-
-#define AR71XX_SPI_IOC_DO                               BIT(0)
-#define AR71XX_SPI_IOC_CLK                              BIT(8)
-#define AR71XX_SPI_IOC_CS(n)                            BIT(16 + (n))
-#define AR71XX_SPI_IOC_CS0                      AR71XX_SPI_IOC_CS(0)
-#define AR71XX_SPI_IOC_CS1                      AR71XX_SPI_IOC_CS(1)
-#define AR71XX_SPI_IOC_CS2                      AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_REG_FS				0x00
+#define AR71XX_SPI_REG_CTRL				0x04
+#define AR71XX_SPI_REG_IOC				0x08
+#define AR71XX_SPI_REG_RDS				0x0c
+
+#define AR71XX_SPI_FS_GPIO				BIT(0)
+
+#define AR71XX_SPI_CTRL_RD				BIT(6)
+#define AR71XX_SPI_CTRL_DIV_MASK			0x3f
+
+#define AR71XX_SPI_IOC_DO				BIT(0)
+#define AR71XX_SPI_IOC_CLK				BIT(8)
+#define AR71XX_SPI_IOC_CS(n)				BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0				AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1				AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2				AR71XX_SPI_IOC_CS(2)
 #define AR71XX_SPI_IOC_CS_ALL \
 	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
 
 /*
  * GPIO block
  */
-#define AR71XX_GPIO_REG_OE                              0x00
-#define AR71XX_GPIO_REG_IN                              0x04
-#define AR71XX_GPIO_REG_OUT                             0x08
-#define AR71XX_GPIO_REG_SET                             0x0c
-#define AR71XX_GPIO_REG_CLEAR                           0x10
-#define AR71XX_GPIO_REG_INT_MODE                        0x14
-#define AR71XX_GPIO_REG_INT_TYPE                        0x18
-#define AR71XX_GPIO_REG_INT_POLARITY                    0x1c
-#define AR71XX_GPIO_REG_INT_PENDING                     0x20
-#define AR71XX_GPIO_REG_INT_ENABLE                      0x24
-#define AR71XX_GPIO_REG_FUNC                            0x28
-#define AR933X_GPIO_REG_FUNC                            0x30
-
-#define AR934X_GPIO_REG_OUT_FUNC0                       0x2c
-#define AR934X_GPIO_REG_OUT_FUNC1                       0x30
-#define AR934X_GPIO_REG_OUT_FUNC2                       0x34
-#define AR934X_GPIO_REG_OUT_FUNC3                       0x38
-#define AR934X_GPIO_REG_OUT_FUNC4                       0x3c
-#define AR934X_GPIO_REG_OUT_FUNC5                       0x40
-#define AR934X_GPIO_REG_FUNC                            0x6c
-
-#define QCA953X_GPIO_REG_OUT_FUNC0                      0x2c
-#define QCA953X_GPIO_REG_OUT_FUNC1                      0x30
-#define QCA953X_GPIO_REG_OUT_FUNC2                      0x34
-#define QCA953X_GPIO_REG_OUT_FUNC3                      0x38
-#define QCA953X_GPIO_REG_OUT_FUNC4                      0x3c
-#define QCA953X_GPIO_REG_IN_ENABLE0                     0x44
-#define QCA953X_GPIO_REG_FUNC                           0x6c
-
-#define QCA955X_GPIO_REG_OUT_FUNC0                      0x2c
-#define QCA955X_GPIO_REG_OUT_FUNC1                      0x30
-#define QCA955X_GPIO_REG_OUT_FUNC2                      0x34
-#define QCA955X_GPIO_REG_OUT_FUNC3                      0x38
-#define QCA955X_GPIO_REG_OUT_FUNC4                      0x3c
-#define QCA955X_GPIO_REG_OUT_FUNC5                      0x40
-#define QCA955X_GPIO_REG_FUNC                           0x6c
-
-#define QCA956X_GPIO_REG_OUT_FUNC0                      0x2c
-#define QCA956X_GPIO_REG_OUT_FUNC1                      0x30
-#define QCA956X_GPIO_REG_OUT_FUNC2                      0x34
-#define QCA956X_GPIO_REG_OUT_FUNC3                      0x38
-#define QCA956X_GPIO_REG_OUT_FUNC4                      0x3c
-#define QCA956X_GPIO_REG_OUT_FUNC5                      0x40
-#define QCA956X_GPIO_REG_IN_ENABLE0                     0x44
-#define QCA956X_GPIO_REG_IN_ENABLE3                     0x50
-#define QCA956X_GPIO_REG_FUNC                           0x6c
-
-#define AR71XX_GPIO_FUNC_STEREO_EN                      BIT(17)
-#define AR71XX_GPIO_FUNC_SLIC_EN                        BIT(16)
-#define AR71XX_GPIO_FUNC_SPI_CS2_EN                     BIT(13)
-#define AR71XX_GPIO_FUNC_SPI_CS1_EN                     BIT(12)
-#define AR71XX_GPIO_FUNC_UART_EN                        BIT(8)
-#define AR71XX_GPIO_FUNC_USB_OC_EN                      BIT(4)
-#define AR71XX_GPIO_FUNC_USB_CLK_EN                     BIT(0)
-
-#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                 BIT(19)
-#define AR724X_GPIO_FUNC_SPI_EN                         BIT(18)
-#define AR724X_GPIO_FUNC_SPI_CS_EN2                     BIT(14)
-#define AR724X_GPIO_FUNC_SPI_CS_EN1                     BIT(13)
-#define AR724X_GPIO_FUNC_CLK_OBS5_EN                    BIT(12)
-#define AR724X_GPIO_FUNC_CLK_OBS4_EN                    BIT(11)
-#define AR724X_GPIO_FUNC_CLK_OBS3_EN                    BIT(10)
-#define AR724X_GPIO_FUNC_CLK_OBS2_EN                    BIT(9)
-#define AR724X_GPIO_FUNC_CLK_OBS1_EN                    BIT(8)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN             BIT(7)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN             BIT(6)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN             BIT(5)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN             BIT(4)
-#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN             BIT(3)
-#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN                BIT(2)
-#define AR724X_GPIO_FUNC_UART_EN                        BIT(1)
-#define AR724X_GPIO_FUNC_JTAG_DISABLE                   BIT(0)
-
-#define AR913X_GPIO_FUNC_WMAC_LED_EN                    BIT(22)
-#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN                 BIT(21)
-#define AR913X_GPIO_FUNC_I2S_REFCLKEN                   BIT(20)
-#define AR913X_GPIO_FUNC_I2S_MCKEN                      BIT(19)
-#define AR913X_GPIO_FUNC_I2S1_EN                        BIT(18)
-#define AR913X_GPIO_FUNC_I2S0_EN                        BIT(17)
-#define AR913X_GPIO_FUNC_SLIC_EN                        BIT(16)
-#define AR913X_GPIO_FUNC_UART_RTSCTS_EN                 BIT(9)
-#define AR913X_GPIO_FUNC_UART_EN                        BIT(8)
-#define AR913X_GPIO_FUNC_USB_CLK_EN                     BIT(4)
-
-#define AR933X_GPIO(x)                                  BIT(x)
-#define AR933X_GPIO_FUNC_SPDIF2TCK                      BIT(31)
-#define AR933X_GPIO_FUNC_SPDIF_EN                       BIT(30)
-#define AR933X_GPIO_FUNC_I2SO_22_18_EN                  BIT(29)
-#define AR933X_GPIO_FUNC_I2S_MCK_EN                     BIT(27)
-#define AR933X_GPIO_FUNC_I2SO_EN                        BIT(26)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL            BIT(25)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL            BIT(24)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT             BIT(23)
-#define AR933X_GPIO_FUNC_SPI_EN                         BIT(18)
-#define AR933X_GPIO_FUNC_RES_TRUE                       BIT(15)
-#define AR933X_GPIO_FUNC_SPI_CS_EN2                     BIT(14)
-#define AR933X_GPIO_FUNC_SPI_CS_EN1                     BIT(13)
-#define AR933X_GPIO_FUNC_XLNA_EN                        BIT(12)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN             BIT(7)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN             BIT(6)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN             BIT(5)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN             BIT(4)
-#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN             BIT(3)
-#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN                BIT(2)
-#define AR933X_GPIO_FUNC_UART_EN                        BIT(1)
-#define AR933X_GPIO_FUNC_JTAG_DISABLE                   BIT(0)
-
-#define AR934X_GPIO_FUNC_CLK_OBS7_EN                    BIT(9)
-#define AR934X_GPIO_FUNC_CLK_OBS6_EN                    BIT(8)
-#define AR934X_GPIO_FUNC_CLK_OBS5_EN                    BIT(7)
-#define AR934X_GPIO_FUNC_CLK_OBS4_EN                    BIT(6)
-#define AR934X_GPIO_FUNC_CLK_OBS3_EN                    BIT(5)
-#define AR934X_GPIO_FUNC_CLK_OBS2_EN                    BIT(4)
-#define AR934X_GPIO_FUNC_CLK_OBS1_EN                    BIT(3)
-#define AR934X_GPIO_FUNC_CLK_OBS0_EN                    BIT(2)
-#define AR934X_GPIO_FUNC_JTAG_DISABLE                   BIT(1)
-
-#define AR934X_GPIO_OUT_GPIO                            0
-#define AR934X_GPIO_OUT_SPI_CS1                         7
-#define AR934X_GPIO_OUT_LED_LINK0                       41
-#define AR934X_GPIO_OUT_LED_LINK1                       42
-#define AR934X_GPIO_OUT_LED_LINK2                       43
-#define AR934X_GPIO_OUT_LED_LINK3                       44
-#define AR934X_GPIO_OUT_LED_LINK4                       45
-#define AR934X_GPIO_OUT_EXT_LNA0                        46
-#define AR934X_GPIO_OUT_EXT_LNA1                        47
-
-#define QCA953X_GPIO(x)                                 BIT(x)
-#define QCA953X_GPIO_MUX_MASK(x)                        (0xff << (x))
-#define QCA953X_GPIO_OUT_MUX_SPI_CS1                    10
-#define QCA953X_GPIO_OUT_MUX_SPI_CS2                    11
-#define QCA953X_GPIO_OUT_MUX_SPI_CS0                    9
-#define QCA953X_GPIO_OUT_MUX_SPI_CLK                    8
-#define QCA953X_GPIO_OUT_MUX_SPI_MOSI                   12
-#define QCA953X_GPIO_OUT_MUX_UART0_SOUT                 22
-#define QCA953X_GPIO_OUT_MUX_LED_LINK1                  41
-#define QCA953X_GPIO_OUT_MUX_LED_LINK2                  42
-#define QCA953X_GPIO_OUT_MUX_LED_LINK3                  43
-#define QCA953X_GPIO_OUT_MUX_LED_LINK4                  44
-#define QCA953X_GPIO_OUT_MUX_LED_LINK5                  45
-
-#define QCA953X_GPIO_IN_MUX_UART0_SIN                   9
-#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN                 8
-
-#define QCA956X_GPIO_OUT_MUX_GE0_MDO                    32
-#define QCA956X_GPIO_OUT_MUX_GE0_MDC                    33
-
-#define AR71XX_GPIO_COUNT                               16
-#define AR7240_GPIO_COUNT                               18
-#define AR7241_GPIO_COUNT                               20
-#define AR913X_GPIO_COUNT                               22
-#define AR933X_GPIO_COUNT                               30
-#define AR934X_GPIO_COUNT                               23
-#define QCA953X_GPIO_COUNT                              18
-#define QCA955X_GPIO_COUNT                              24
-#define QCA956X_GPIO_COUNT                              23
+#define AR71XX_GPIO_REG_OE				0x00
+#define AR71XX_GPIO_REG_IN				0x04
+#define AR71XX_GPIO_REG_OUT				0x08
+#define AR71XX_GPIO_REG_SET				0x0c
+#define AR71XX_GPIO_REG_CLEAR				0x10
+#define AR71XX_GPIO_REG_INT_MODE			0x14
+#define AR71XX_GPIO_REG_INT_TYPE			0x18
+#define AR71XX_GPIO_REG_INT_POLARITY			0x1c
+#define AR71XX_GPIO_REG_INT_PENDING			0x20
+#define AR71XX_GPIO_REG_INT_ENABLE			0x24
+#define AR71XX_GPIO_REG_FUNC				0x28
+#define AR933X_GPIO_REG_FUNC				0x30
+
+#define AR934X_GPIO_REG_OUT_FUNC0			0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1			0x30
+#define AR934X_GPIO_REG_OUT_FUNC2			0x34
+#define AR934X_GPIO_REG_OUT_FUNC3			0x38
+#define AR934X_GPIO_REG_OUT_FUNC4			0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5			0x40
+#define AR934X_GPIO_REG_FUNC				0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0			0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1			0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2			0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3			0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4			0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0			0x44
+#define QCA953X_GPIO_REG_FUNC				0x6c
+
+#define QCA955X_GPIO_REG_OUT_FUNC0			0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1			0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2			0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3			0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4			0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5			0x40
+#define QCA955X_GPIO_REG_FUNC				0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0			0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1			0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2			0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3			0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4			0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5			0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0			0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3			0x50
+#define QCA956X_GPIO_REG_FUNC				0x6c
+
+#define AR71XX_GPIO_FUNC_STEREO_EN			BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN			BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN			BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN			BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN			BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN			BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN			BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN			BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN				BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2			BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1			BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN			BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN			BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN			BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN			BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN			BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN		BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN		BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN		BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN		BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN		BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN		BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN			BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE			BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN			BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN			BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN			BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN			BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN			BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN			BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN			BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN			BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN			BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN			BIT(4)
+
+#define AR933X_GPIO(x)					BIT(x)
+#define AR933X_GPIO_FUNC_SPDIF2TCK			BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN			BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN			BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN			BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN			BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL		BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL		BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT		BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN				BIT(18)
+#define AR933X_GPIO_FUNC_RES_TRUE			BIT(15)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2			BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1			BIT(13)
+#define AR933X_GPIO_FUNC_XLNA_EN			BIT(12)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN		BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN		BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN		BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN		BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN		BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN		BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN			BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE			BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN			BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN			BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN			BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN			BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN			BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN			BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN			BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN			BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE			BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO				0
+#define AR934X_GPIO_OUT_SPI_CS1				7
+#define AR934X_GPIO_OUT_LED_LINK0			41
+#define AR934X_GPIO_OUT_LED_LINK1			42
+#define AR934X_GPIO_OUT_LED_LINK2			43
+#define AR934X_GPIO_OUT_LED_LINK3			44
+#define AR934X_GPIO_OUT_LED_LINK4			45
+#define AR934X_GPIO_OUT_EXT_LNA0			46
+#define AR934X_GPIO_OUT_EXT_LNA1			47
+
+#define QCA953X_GPIO(x)					BIT(x)
+#define QCA953X_GPIO_MUX_MASK(x)			(0xff << (x))
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1			10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2			11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0			9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK			8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI			12
+#define QCA953X_GPIO_OUT_MUX_UART0_SOUT			22
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1			41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2			42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3			43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4			44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5			45
+
+#define QCA953X_GPIO_IN_MUX_UART0_SIN			9
+#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN			8
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO			32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC			33
+
+#define AR71XX_GPIO_COUNT				16
+#define AR7240_GPIO_COUNT				18
+#define AR7241_GPIO_COUNT				20
+#define AR913X_GPIO_COUNT				22
+#define AR933X_GPIO_COUNT				30
+#define AR934X_GPIO_COUNT				23
+#define QCA953X_GPIO_COUNT				18
+#define QCA955X_GPIO_COUNT				24
+#define QCA956X_GPIO_COUNT				23
 
 /*
  * SRIF block
  */
-#define AR933X_SRIF_DDR_DPLL1_REG                       0x240
-#define AR933X_SRIF_DDR_DPLL2_REG                       0x244
-#define AR933X_SRIF_DDR_DPLL3_REG                       0x248
-#define AR933X_SRIF_DDR_DPLL4_REG                       0x24c
+#define AR933X_SRIF_DDR_DPLL1_REG			0x240
+#define AR933X_SRIF_DDR_DPLL2_REG			0x244
+#define AR933X_SRIF_DDR_DPLL3_REG			0x248
+#define AR933X_SRIF_DDR_DPLL4_REG			0x24c
 
-#define AR934X_SRIF_CPU_DPLL1_REG                       0x1c0
-#define AR934X_SRIF_CPU_DPLL2_REG                       0x1c4
-#define AR934X_SRIF_CPU_DPLL3_REG                       0x1c8
+#define AR934X_SRIF_CPU_DPLL1_REG			0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG			0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG			0x1c8
 
-#define AR934X_SRIF_DDR_DPLL1_REG                       0x240
-#define AR934X_SRIF_DDR_DPLL2_REG                       0x244
-#define AR934X_SRIF_DDR_DPLL3_REG                       0x248
+#define AR934X_SRIF_DDR_DPLL1_REG			0x240
+#define AR934X_SRIF_DDR_DPLL2_REG			0x244
+#define AR934X_SRIF_DDR_DPLL3_REG			0x248
 
-#define AR934X_SRIF_DPLL1_REFDIV_SHIFT                  27
-#define AR934X_SRIF_DPLL1_REFDIV_MASK                   0x1f
-#define AR934X_SRIF_DPLL1_NINT_SHIFT                    18
-#define AR934X_SRIF_DPLL1_NINT_MASK                     0x1ff
-#define AR934X_SRIF_DPLL1_NFRAC_MASK                    0x0003ffff
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT			27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK			0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT			18
+#define AR934X_SRIF_DPLL1_NINT_MASK			0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK			0x0003ffff
 
-#define AR934X_SRIF_DPLL2_LOCAL_PLL                     BIT(30)
-#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT                  13
-#define AR934X_SRIF_DPLL2_OUTDIV_MASK                   0x7
+#define AR934X_SRIF_DPLL2_LOCAL_PLL			BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT			13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK			0x7
 
-#define QCA953X_SRIF_BB_DPLL1_REG                       0x180
-#define QCA953X_SRIF_BB_DPLL2_REG                       0x184
-#define QCA953X_SRIF_BB_DPLL3_REG                       0x188
+#define QCA953X_SRIF_BB_DPLL1_REG			0x180
+#define QCA953X_SRIF_BB_DPLL2_REG			0x184
+#define QCA953X_SRIF_BB_DPLL3_REG			0x188
 
-#define QCA953X_SRIF_CPU_DPLL1_REG                      0x1c0
-#define QCA953X_SRIF_CPU_DPLL2_REG                      0x1c4
-#define QCA953X_SRIF_CPU_DPLL3_REG                      0x1c8
+#define QCA953X_SRIF_CPU_DPLL1_REG			0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG			0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG			0x1c8
 
-#define QCA953X_SRIF_DDR_DPLL1_REG                      0x240
-#define QCA953X_SRIF_DDR_DPLL2_REG                      0x244
-#define QCA953X_SRIF_DDR_DPLL3_REG                      0x248
+#define QCA953X_SRIF_DDR_DPLL1_REG			0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG			0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG			0x248
 
-#define QCA953X_SRIF_PCIE_DPLL1_REG                     0xc00
-#define QCA953X_SRIF_PCIE_DPLL2_REG                     0xc04
-#define QCA953X_SRIF_PCIE_DPLL3_REG                     0xc08
+#define QCA953X_SRIF_PCIE_DPLL1_REG			0xc00
+#define QCA953X_SRIF_PCIE_DPLL2_REG			0xc04
+#define QCA953X_SRIF_PCIE_DPLL3_REG			0xc08
 
-#define QCA953X_SRIF_PMU1_REG                           0xc40
-#define QCA953X_SRIF_PMU2_REG                           0xc44
+#define QCA953X_SRIF_PMU1_REG				0xc40
+#define QCA953X_SRIF_PMU2_REG				0xc44
 
-#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT                 27
-#define QCA953X_SRIF_DPLL1_REFDIV_MASK                  0x1f
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT			27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK			0x1f
 
-#define QCA953X_SRIF_DPLL1_NINT_SHIFT                   18
-#define QCA953X_SRIF_DPLL1_NINT_MASK                    0x1ff
-#define QCA953X_SRIF_DPLL1_NFRAC_MASK                   0x0003ffff
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT			18
+#define QCA953X_SRIF_DPLL1_NINT_MASK			0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK			0x0003ffff
 
-#define QCA953X_SRIF_DPLL2_LOCAL_PLL                    BIT(30)
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL			BIT(30)
 
-#define QCA953X_SRIF_DPLL2_KI_SHIFT                     29
-#define QCA953X_SRIF_DPLL2_KI_MASK                      0x3
+#define QCA953X_SRIF_DPLL2_KI_SHIFT			29
+#define QCA953X_SRIF_DPLL2_KI_MASK			0x3
 
-#define QCA953X_SRIF_DPLL2_KD_SHIFT                     25
-#define QCA953X_SRIF_DPLL2_KD_MASK                      0xf
+#define QCA953X_SRIF_DPLL2_KD_SHIFT			25
+#define QCA953X_SRIF_DPLL2_KD_MASK			0xf
 
-#define QCA953X_SRIF_DPLL2_PWD                          BIT(22)
+#define QCA953X_SRIF_DPLL2_PWD				BIT(22)
 
-#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT                 13
-#define QCA953X_SRIF_DPLL2_OUTDIV_MASK                  0x7
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT			13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK			0x7
 
 /*
  * MII_CTRL block
  */
-#define AR71XX_MII_REG_MII0_CTRL                        0x00
-#define AR71XX_MII_REG_MII1_CTRL                        0x04
+#define AR71XX_MII_REG_MII0_CTRL			0x00
+#define AR71XX_MII_REG_MII1_CTRL			0x04
 
-#define AR71XX_MII_CTRL_IF_MASK                         3
-#define AR71XX_MII_CTRL_SPEED_SHIFT                     4
-#define AR71XX_MII_CTRL_SPEED_MASK                      3
-#define AR71XX_MII_CTRL_SPEED_10                        0
-#define AR71XX_MII_CTRL_SPEED_100                       1
-#define AR71XX_MII_CTRL_SPEED_1000                      2
+#define AR71XX_MII_CTRL_IF_MASK				3
+#define AR71XX_MII_CTRL_SPEED_SHIFT			4
+#define AR71XX_MII_CTRL_SPEED_MASK			3
+#define AR71XX_MII_CTRL_SPEED_10			0
+#define AR71XX_MII_CTRL_SPEED_100			1
+#define AR71XX_MII_CTRL_SPEED_1000			2
 
-#define AR71XX_MII0_CTRL_IF_GMII                        0
-#define AR71XX_MII0_CTRL_IF_MII                         1
-#define AR71XX_MII0_CTRL_IF_RGMII                       2
-#define AR71XX_MII0_CTRL_IF_RMII                        3
+#define AR71XX_MII0_CTRL_IF_GMII			0
+#define AR71XX_MII0_CTRL_IF_MII				1
+#define AR71XX_MII0_CTRL_IF_RGMII			2
+#define AR71XX_MII0_CTRL_IF_RMII			3
 
-#define AR71XX_MII1_CTRL_IF_RGMII                       0
-#define AR71XX_MII1_CTRL_IF_RMII                        1
+#define AR71XX_MII1_CTRL_IF_RGMII			0
+#define AR71XX_MII1_CTRL_IF_RMII			1
 
 /*
  * AR933X GMAC interface
  */
-#define AR933X_GMAC_REG_ETH_CFG                         0x00
-
-#define AR933X_ETH_CFG_RGMII_GE0                        BIT(0)
-#define AR933X_ETH_CFG_MII_GE0                          BIT(1)
-#define AR933X_ETH_CFG_GMII_GE0                         BIT(2)
-#define AR933X_ETH_CFG_MII_GE0_MASTER                   BIT(3)
-#define AR933X_ETH_CFG_MII_GE0_SLAVE                    BIT(4)
-#define AR933X_ETH_CFG_MII_GE0_ERR_EN                   BIT(5)
-#define AR933X_ETH_CFG_SW_PHY_SWAP                      BIT(7)
-#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP                 BIT(8)
-#define AR933X_ETH_CFG_RMII_GE0                         BIT(9)
-#define AR933X_ETH_CFG_RMII_GE0_SPD_10                  0
-#define AR933X_ETH_CFG_RMII_GE0_SPD_100                 BIT(10)
+#define AR933X_GMAC_REG_ETH_CFG				0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0			BIT(0)
+#define AR933X_ETH_CFG_MII_GE0				BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0				BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER			BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE			BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN			BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP			BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP			BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0				BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10			0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100			BIT(10)
 
 /*
  * AR934X GMAC Interface
  */
-#define AR934X_GMAC_REG_ETH_CFG                         0x00
-
-#define AR934X_ETH_CFG_RGMII_GMAC0                      BIT(0)
-#define AR934X_ETH_CFG_MII_GMAC0                        BIT(1)
-#define AR934X_ETH_CFG_GMII_GMAC0                       BIT(2)
-#define AR934X_ETH_CFG_MII_GMAC0_MASTER                 BIT(3)
-#define AR934X_ETH_CFG_MII_GMAC0_SLAVE                  BIT(4)
-#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN                 BIT(5)
-#define AR934X_ETH_CFG_SW_ONLY_MODE                     BIT(6)
-#define AR934X_ETH_CFG_SW_PHY_SWAP                      BIT(7)
-#define AR934X_ETH_CFG_SW_APB_ACCESS                    BIT(9)
-#define AR934X_ETH_CFG_RMII_GMAC0                       BIT(10)
-#define AR933X_ETH_CFG_MII_CNTL_SPEED                   BIT(11)
-#define AR934X_ETH_CFG_RMII_GMAC0_MASTER                BIT(12)
-#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST                 BIT(13)
-#define AR934X_ETH_CFG_RXD_DELAY                        BIT(14)
-#define AR934X_ETH_CFG_RXD_DELAY_MASK                   0x3
-#define AR934X_ETH_CFG_RXD_DELAY_SHIFT                  14
-#define AR934X_ETH_CFG_RDV_DELAY                        BIT(16)
-#define AR934X_ETH_CFG_RDV_DELAY_MASK                   0x3
-#define AR934X_ETH_CFG_RDV_DELAY_SHIFT                  16
+#define AR934X_GMAC_REG_ETH_CFG				0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0			BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0			BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0			BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER			BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE			BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN			BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE			BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP			BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS			BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0			BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED			BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER			BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST			BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY			BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK			0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT			14
+#define AR934X_ETH_CFG_RDV_DELAY			BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK			0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT			16
 
 /*
  * QCA953X GMAC Interface
  */
-#define QCA953X_GMAC_REG_ETH_CFG                        0x00
+#define QCA953X_GMAC_REG_ETH_CFG			0x00
 
-#define QCA953X_ETH_CFG_SW_ONLY_MODE                    BIT(6)
-#define QCA953X_ETH_CFG_SW_PHY_SWAP                     BIT(7)
-#define QCA953X_ETH_CFG_SW_APB_ACCESS                   BIT(9)
-#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST                BIT(13)
+#define QCA953X_ETH_CFG_SW_ONLY_MODE			BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP			BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS			BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST		BIT(13)
 
 /*
  * QCA955X GMAC Interface
  */
 
-#define QCA955X_GMAC_REG_ETH_CFG                        0x00
+#define QCA955X_GMAC_REG_ETH_CFG			0x00
 
-#define QCA955X_ETH_CFG_RGMII_EN                        BIT(0)
-#define QCA955X_ETH_CFG_GE0_SGMII                       BIT(6)
+#define QCA955X_ETH_CFG_RGMII_EN			BIT(0)
+#define QCA955X_ETH_CFG_GE0_SGMII			BIT(6)
 
 #endif /* __ASM_AR71XX_H */
-- 
cgit v0.10.2


From 43a092ffdd5edd6a66e8e9ec34372f3abd396486 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:35 +0200
Subject: mips: ath79: Fix compiler warning on const assignment

The assignment const T var; var = value; is illegal, since var is
constant. Drop the const to fix the compiler warning.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 2ea2f8d..ba38609 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -46,7 +46,7 @@ void _machine_restart(void)
 
 u32 get_bootstrap(void)
 {
-	const void __iomem *base;
+	void __iomem *base;
 	u32 reg = 0;
 
 	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
-- 
cgit v0.10.2


From c31558780b50883bbbbb657592dc3391b2551353 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:36 +0200
Subject: mips: ath79: dts: Add generic-ehci node

Add generic EHCI node for the ChipIdea EHCI controller in the ath79.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 11f60a2..2e124a4 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -59,6 +59,13 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			ehci0: ehci@1b000100 {
+				compatible = "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				status = "disabled";
+			};
+
 			uart0: uart@18020000 {
 				compatible = "qca,ar9330-uart";
 				reg = <0x18020000 0x20>;
-- 
cgit v0.10.2


From 6b699742d4795804d553deaf5163a0923bd27274 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:37 +0200
Subject: mips: ath79: Add support for ungating USB on ar933x and ar934x

Add code to ungate the USB controller on ar933x and ar934x .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
index 90d80b8..682b6a2 100644
--- a/arch/mips/mach-ath79/include/mach/ath79.h
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -140,4 +140,6 @@ static inline int soc_is_qca956x(void)
 	return soc_is_tp9343() || soc_is_qca9561();
 }
 
+int ath79_usb_reset(void);
+
 #endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index ba38609..1538e32 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/types.h>
@@ -69,3 +70,61 @@ u32 get_bootstrap(void)
 
 	return 0;
 }
+
+static int usb_reset_ar933x(void __iomem *reset_regs)
+{
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+		     AR933X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+		     AR933X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+		     AR933X_RESET_USB_PHY);
+	mdelay(1);
+
+	return 0;
+}
+
+static int usb_reset_ar934x(void __iomem *reset_regs)
+{
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+		     AR934X_RESET_USB_HOST);
+	mdelay(1);
+
+	return 0;
+}
+
+int ath79_usb_reset(void)
+{
+	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
+					      AR71XX_USB_CTRL_SIZE,
+					      MAP_NOCACHE);
+	void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
+					       AR71XX_RESET_SIZE,
+					       MAP_NOCACHE);
+	/*
+	 * Turn on the Buff and Desc swap bits.
+	 * NOTE: This write into an undocumented register in mandatory to
+	 *       get the USB controller operational in BigEndian mode.
+	 */
+	writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
+
+	if (soc_is_ar933x())
+		return usb_reset_ar933x(reset_regs);
+	if (soc_is_ar934x())
+		return usb_reset_ar934x(reset_regs);
+
+	return -EINVAL;
+}
-- 
cgit v0.10.2


From 2986a9d4bd2197ff3db16c8a4f61574b5a5cca49 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:38 +0200
Subject: mips: ath79: dts: Add ethernet MAC nodes for ar933x

Add node for both ethernet controllers in the ar933x.
The PHY is attached only to the first ethernet controller.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 2e124a4..00896b2 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -73,6 +73,32 @@
 
 				status = "disabled";
 			};
+
+			gmac0: eth@0x19000000 {
+				compatible = "qca,ag7240-mac";
+				reg = <0x19000000 0x200>;
+				phy = <&phy0>;
+				phy-mode = "rmii";
+
+				status = "disabled";
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+
+			gmac1: eth@0x1a000000 {
+				compatible = "qca,ag7240-mac";
+				reg = <0x1a000000 0x200>;
+				phy = <&phy0>;
+				phy-mode = "rgmii";
+
+				status = "disabled";
+			};
 		};
 
 		spi0: spi@1f000000 {
-- 
cgit v0.10.2


From 4771bbee5d7f7857de47794e9636783d55c438f6 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:39 +0200
Subject: mips: ath79: Add support for ungating ethernet on ar933x and ar934x

Add code to ungate the ethernet controller on ar933x and ar934x .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index bff9d05..a9630c0 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -622,6 +622,7 @@
 #define AR933X_RESET_GE1_MAC				BIT(13)
 #define AR933X_RESET_WMAC				BIT(11)
 #define AR933X_RESET_GE0_MAC				BIT(9)
+#define AR933X_RESET_ETH_SWITCH				BIT(8)
 #define AR933X_RESET_USB_HOST				BIT(5)
 #define AR933X_RESET_USB_PHY				BIT(4)
 #define AR933X_RESET_USBSUS_OVERRIDE			BIT(3)
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
index 682b6a2..2c6c118 100644
--- a/arch/mips/mach-ath79/include/mach/ath79.h
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void)
 	return soc_is_tp9343() || soc_is_qca9561();
 }
 
+int ath79_eth_reset(void);
 int ath79_usb_reset(void);
 
 #endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 1538e32..188eccb 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -71,6 +71,84 @@ u32 get_bootstrap(void)
 	return 0;
 }
 
+static int eth_init_ar933x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
+			 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
+			 AR933X_RESET_ETH_SWITCH;
+
+	/* Clear MDIO slave EN bit. */
+	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
+	mdelay(10);
+
+	/* Get Atheros S26 PHY out of reset. */
+	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0x1f, 0x10);
+	mdelay(10);
+
+	setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
+	mdelay(10);
+	clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
+	mdelay(10);
+
+	/* Configure AR93xx GMAC register. */
+	clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
+			AR933X_ETH_CFG_MII_GE0_MASTER |
+			AR933X_ETH_CFG_MII_GE0_SLAVE,
+			AR933X_ETH_CFG_MII_GE0_SLAVE);
+	return 0;
+}
+
+static int eth_init_ar934x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+	void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
+			 AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
+			 AR934X_RESET_ETH_SWITCH_ANALOG;
+	u32 reg;
+
+	reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
+	if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
+		writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+	else
+		writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+	writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	/* Configure AR934x GMAC register. */
+	writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
+	return 0;
+}
+
+int ath79_eth_reset(void)
+{
+	/*
+	 * Un-reset ethernet. DM still doesn't have any notion of reset
+	 * framework, so we do it by hand here.
+	 */
+	if (soc_is_ar933x())
+		return eth_init_ar933x();
+	if (soc_is_ar934x())
+		return eth_init_ar934x();
+
+	return -EINVAL;
+}
+
 static int usb_reset_ar933x(void __iomem *reset_regs)
 {
 	/* Ungate the USB block */
-- 
cgit v0.10.2


From e08539b791336c45ca05ebdf55137a26baaba95e Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:40 +0200
Subject: mips: ath79: Add AR934x support

Add support for the Atheros AR934x WiSoCs. This patchs adds complete
system init, including PLL and DRAM init, both of which happen from
full C environment, since the AR934x has proper SRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/dts/ar934x.dtsi b/arch/mips/dts/ar934x.dtsi
new file mode 100644
index 0000000..7a036a8
--- /dev/null
+++ b/arch/mips/dts/ar934x.dtsi
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "qca,ar934x";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips74Kc";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		xtal: xtal {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-output-names = "xtal";
+		};
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ehci0: ehci@1b000100 {
+				compatible = "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				status = "disabled";
+			};
+
+			uart0: uart@18020000 {
+				compatible = "ns16550";
+				reg = <0x18020000 0x20>;
+				reg-shift = <2>;
+
+				status = "disabled";
+			};
+
+			gmac0: eth@0x19000000 {
+				compatible = "qca,ag934x-mac";
+				reg = <0x19000000 0x200>;
+				phy = <&phy0>;
+				phy-mode = "rgmii";
+
+				status = "disabled";
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+
+			gmac1: eth@0x1a000000 {
+				compatible = "qca,ag934x-mac";
+				reg = <0x1a000000 0x200>;
+				phy = <&phy1>;
+				phy-mode = "rgmii";
+
+				status = "disabled";
+
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy1: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+		};
+
+		spi0: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index f45403b..527960f 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -13,6 +13,15 @@ config SOC_AR933X
 	help
 	  This supports QCA/Atheros ar933x family SOCs.
 
+config SOC_AR934X
+	bool
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select MIPS_TUNE_74KC
+	help
+	  This supports QCA/Atheros ar934x family SOCs.
+
 config SOC_QCA953X
 	bool
 	select SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 160dfaa..d7e2666 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -7,4 +7,5 @@ obj-y += cpu.o
 obj-y += dram.o
 
 obj-$(CONFIG_SOC_AR933X)	+= ar933x/
-obj-$(CONFIG_SOC_QCA953X)	+= qca953x/
\ No newline at end of file
+obj-$(CONFIG_SOC_AR934X)	+= ar934x/
+obj-$(CONFIG_SOC_QCA953X)	+= qca953x/
diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile
new file mode 100644
index 0000000..348c65b
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clk.o
+obj-y += ddr.o
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
new file mode 100644
index 0000000..9c65184
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The math for calculating PLL:
+ *                                       NFRAC * 2^8
+ *                               NINT + -------------
+ *                XTAL [MHz]              2^(18 - 1)
+ *   PLL [MHz] = ------------ * ----------------------
+ *                  REFDIV              2^OUTDIV
+ *
+ * Unfortunatelly, there is no way to reliably compute the variables.
+ * The vendor U-Boot port contains macros for various combinations of
+ * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
+ * in those numbers.
+ */
+struct ar934x_pll_config {
+	u8	range;
+	u8	refdiv;
+	u8	outdiv;
+	/* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
+	u8	nint[2];
+};
+
+struct ar934x_clock_config {
+	u16				cpu_freq;
+	u16				ddr_freq;
+	u16				ahb_freq;
+
+	struct ar934x_pll_config	cpu_pll;
+	struct ar934x_pll_config	ddr_pll;
+};
+
+static const struct ar934x_clock_config ar934x_clock_config[] = {
+	{ 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
+	{ 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
+	{ 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
+	{ 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
+	{ 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
+	{ 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
+	{ 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
+	{ 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
+	{ 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
+	{ 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
+	{ 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
+	{ 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
+	{ 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
+	{ 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
+	{ 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
+	{ 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
+	{ 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
+	{ 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
+	{ 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
+	{ 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
+	{ 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
+	{ 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
+	{ 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
+	{ 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
+	{ 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
+};
+
+static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
+{
+	u32 reg;
+	do {
+		writel(0x10810f00, pll_reg_base + 0x4);
+		writel(srif_val, pll_reg_base + 0x0);
+		writel(0xd0810f00, pll_reg_base + 0x4);
+		writel(0x03000000, pll_reg_base + 0x8);
+		writel(0xd0800f00, pll_reg_base + 0x4);
+
+		clrbits_be32(pll_reg_base + 0x8, BIT(30));
+		udelay(5);
+		setbits_be32(pll_reg_base + 0x8, BIT(30));
+		udelay(5);
+
+		wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+
+		clrbits_be32(pll_reg_base + 0x8, BIT(30));
+		udelay(5);
+
+		/* Check if CPU SRIF PLL locked. */
+		reg = readl(pll_reg_base + 0x8);
+		reg = (reg & 0x7ffff8) >> 3;
+	} while (reg >= 0x40000);
+}
+
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
+{
+	void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
+					      AR934X_SRIF_SIZE, MAP_NOCACHE);
+	void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
+					     AR71XX_PLL_SIZE, MAP_NOCACHE);
+	const struct ar934x_pll_config *pll_cfg;
+	int i, pll_nint, pll_refdiv, xtal_40 = 0;
+	u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
+
+	/* Configure SRIF PLL with initial values. */
+	writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
+	writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
+	writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
+	writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
+	writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
+
+	/* Test for 40MHz XTAL */
+	reg = get_bootstrap();
+	if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
+		xtal_40 = 1;
+		cpu_srif = 0x41c00000;
+		ddr_srif = 0x41680000;
+	} else {
+		xtal_40 = 0;
+		cpu_srif = 0x29c00000;
+		ddr_srif = 0x29680000;
+	}
+
+	/* Locate CPU/DDR PLL configuration */
+	for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
+		if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
+			continue;
+		if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
+			continue;
+		if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
+			continue;
+
+		/* Entry found */
+		pll_cfg = &ar934x_clock_config[i].cpu_pll;
+		pll_nint = pll_cfg->nint[xtal_40];
+		pll_refdiv = pll_cfg->refdiv;
+		cpu_pll =
+			(pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
+			(pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
+			(pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
+			(pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
+
+		pll_cfg = &ar934x_clock_config[i].ddr_pll;
+		pll_nint = pll_cfg->nint[xtal_40];
+		pll_refdiv = pll_cfg->refdiv;
+		ddr_pll =
+			(pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
+			(pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
+			(pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
+			(pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
+		break;
+	}
+
+	/* PLL configuration not found, hang. */
+	if (i == ARRAY_SIZE(ar934x_clock_config))
+		hang();
+
+	/* Set PLL Bypass */
+	setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
+	setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
+	setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
+
+	/* Configure CPU PLL */
+	writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
+	       pll_regs + AR934X_PLL_CPU_CONFIG_REG);
+	/* Configure DDR PLL */
+	writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
+	       pll_regs + AR934X_PLL_DDR_CONFIG_REG);
+	/* Configure PLL routing */
+	writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
+	       AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
+	       AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
+	       (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
+	       (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
+	       (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
+	       AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
+	       AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
+	       AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
+	       pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+	/* Configure SRIF PLLs, which is completely undocumented :-) */
+	ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
+	ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
+
+	/* Unset PLL Bypass */
+	clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
+	clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
+	clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+		     AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
+
+	/* Enable PLL dithering */
+	writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
+	       (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
+	       pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
+	writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
+	       pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
+}
+
+static u32 ar934x_get_xtal(void)
+{
+	u32 val;
+
+	val = get_bootstrap();
+	if (val & AR934X_BOOTSTRAP_REF_CLK_40)
+		return 40000000;
+	else
+		return 25000000;
+}
+
+int get_serial_clock(void)
+{
+	return ar934x_get_xtal();
+}
+
+static u32 ar934x_cpupll_to_hz(const u32 regval)
+{
+	const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
+	const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_NINT_MASK;
+	const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+			   AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
+	const u32 xtal = ar934x_get_xtal();
+
+	return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+
+static u32 ar934x_ddrpll_to_hz(const u32 regval)
+{
+	const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+	const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
+	const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_NINT_MASK;
+	const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+			   AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
+	const u32 xtal = ar934x_get_xtal();
+
+	return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+
+static void ar934x_update_clock(void)
+{
+	void __iomem *regs;
+	u32 ctrl, cpu, cpupll, ddr, ddrpll;
+	u32 cpudiv, ddrdiv, busdiv;
+	u32 cpuclk, ddrclk, busclk;
+
+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
+	ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
+	ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+	cpupll = ar934x_cpupll_to_hz(cpu);
+	ddrpll = ar934x_ddrpll_to_hz(ddr);
+
+	if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+		cpuclk = ar934x_get_xtal();
+	else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+		cpuclk = cpupll;
+	else
+		cpuclk = ddrpll;
+
+	if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+		ddrclk = ar934x_get_xtal();
+	else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+		ddrclk = ddrpll;
+	else
+		ddrclk = cpupll;
+
+	if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+		busclk = ar934x_get_xtal();
+	else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+		busclk = ddrpll;
+	else
+		busclk = cpupll;
+
+	cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+		 AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+	ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+		 AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+	busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+		 AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+
+	gd->cpu_clk = cpuclk / (cpudiv + 1);
+	gd->mem_clk = ddrclk / (ddrdiv + 1);
+	gd->bus_clk = busclk / (busdiv + 1);
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	ar934x_update_clock();
+	return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+	ar934x_update_clock();
+	return gd->mem_clk;
+}
+
+int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ar934x_update_clock();
+	printf("CPU:       %8ld MHz\n", gd->cpu_clk / 1000000);
+	printf("Memory:    %8ld MHz\n", gd->mem_clk / 1000000);
+	printf("AHB:       %8ld MHz\n", gd->bus_clk / 1000000);
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,
+	"display clocks",
+	""
+);
diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c
new file mode 100644
index 0000000..8fcdf65
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/cpu.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+/* The lowlevel_init() is not needed on AR934x */
+void lowlevel_init(void) {}
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
new file mode 100644
index 0000000..4621d58
--- /dev/null
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	AR934X_SDRAM = 0,
+	AR934X_DDR1,
+	AR934X_DDR2,
+};
+
+struct ar934x_mem_config {
+	u32	config1;
+	u32	config2;
+	u32	mode;
+	u32	extmode;
+	u32	tap;
+};
+
+static const struct ar934x_mem_config ar934x_mem_config[] = {
+	[AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
+	[AR934X_DDR1]  = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
+	[AR934X_DDR2]  = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
+};
+
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
+{
+	void __iomem *ddr_regs;
+	const struct ar934x_mem_config *memcfg;
+	int memtype;
+	u32 reg, cycle, ctl;
+
+	ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			       MAP_NOCACHE);
+
+	reg = get_bootstrap();
+	if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) {	/* DDR */
+		if (reg & AR934X_BOOTSTRAP_DDR1) {	/* DDR 1 */
+			memtype = AR934X_DDR1;
+			cycle = 0xffff;
+		} else {				/* DDR 2 */
+			memtype = AR934X_DDR2;
+			if (gd->arch.rev) {
+				ctl = BIT(6);	/* Undocumented bit :-( */
+				if (reg & BIT(3))
+					cycle = 0xff;
+				else
+					cycle = 0xffff;
+			} else {
+				/* Force DDR2/x16 configuratio on old chips. */
+				ctl = 0;
+				cycle = 0xffff;		/* DDR2 16bit */
+			}
+
+			writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
+			udelay(100);
+
+			writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
+			udelay(10);
+
+			writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
+			udelay(10);
+
+			writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
+			udelay(10);
+		}
+	} else {					/* SDRAM */
+		memtype = AR934X_SDRAM;
+		cycle = 0xffffffff;
+
+		writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
+		udelay(100);
+
+		/* Undocumented register */
+		writel(0x13b, ddr_regs + 0x118);
+		udelay(100);
+	}
+
+	memcfg = &ar934x_mem_config[memtype];
+
+	writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
+	udelay(100);
+
+	writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
+	udelay(100);
+
+	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
+	mdelay(1);
+
+	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	if (memtype == AR934X_DDR2) {
+		writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
+		udelay(100);
+
+		writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
+		udelay(10);
+	}
+
+	if (memtype != AR934X_SDRAM)
+		writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
+
+	udelay(100);
+
+	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
+	udelay(100);
+
+	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
+	udelay(10);
+
+	writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
+	udelay(100);
+
+	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
+	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+	if (memtype != AR934X_SDRAM) {
+		if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
+			writel(memcfg->tap,
+			       ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
+			writel(memcfg->tap,
+			       ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
+		}
+	}
+
+	writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
+	udelay(100);
+
+	writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
+	udelay(100);
+
+	writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
+	udelay(100);
+
+	writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
+	udelay(100);
+}
+
+void ddr_tap_tuning(void)
+{
+}
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a9630c0..a8e51cb 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -250,11 +250,22 @@
 #define AR933X_DDR_REG_TIMEOUT_CNT			0x9c
 #define AR933X_DDR_REG_TIMEOUT_ADDR			0x9c
 
+#define AR934X_DDR_REG_TAP_CTRL2			0x24
+#define AR934X_DDR_REG_TAP_CTRL3			0x28
 #define AR934X_DDR_REG_FLUSH_GE0			0x9c
 #define AR934X_DDR_REG_FLUSH_GE1			0xa0
 #define AR934X_DDR_REG_FLUSH_USB			0xa4
 #define AR934X_DDR_REG_FLUSH_PCIE			0xa8
 #define AR934X_DDR_REG_FLUSH_WMAC			0xac
+#define AR934X_DDR_REG_FLUSH_SRC1			0xb0
+#define AR934X_DDR_REG_FLUSH_SRC2			0xb4
+#define AR934X_DDR_REG_DDR2_CONFIG			0xb8
+#define AR934X_DDR_REG_EMR2				0xbc
+#define AR934X_DDR_REG_EMR3				0xc0
+#define AR934X_DDR_REG_BURST				0xc4
+#define AR934X_DDR_REG_BURST2				0xc8
+#define AR934X_DDR_REG_TIMEOUT_MAX			0xcc
+#define AR934X_DDR_REG_CTL_CONF				0x108
 
 #define QCA953X_DDR_REG_FLUSH_GE0			0x9c
 #define QCA953X_DDR_REG_FLUSH_GE1			0xa0
@@ -341,6 +352,8 @@
 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG			0x08
 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
 #define AR934X_PLL_ETH_XMII_CONTROL_REG			0x2c
+#define AR934X_PLL_DDR_DIT_FRAC_REG			0x44
+#define AR934X_PLL_CPU_DIT_FRAC_REG			0x48
 
 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT		0
 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK		0x3f
@@ -348,8 +361,12 @@
 #define AR934X_PLL_CPU_CONFIG_NINT_MASK			0x3f
 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
+#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT		17
+#define AR934X_PLL_CPU_CONFIG_RANGE_MASK		0x3
 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK		0x3
+#define AR934X_PLL_CPU_CONFIG_PLLPWD			BIT(30)
+#define AR934X_PLL_CPU_CONFIG_UPDATING			BIT(31)
 
 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT		0
 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK		0x3ff
@@ -357,8 +374,12 @@
 #define AR934X_PLL_DDR_CONFIG_NINT_MASK			0x3f
 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
+#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT		21
+#define AR934X_PLL_DDR_CONFIG_RANGE_MASK		0x3
 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7
+#define AR934X_PLL_DDR_CONFIG_PLLPWD			BIT(30)
+#define AR934X_PLL_DDR_CONFIG_UPDATING			BIT(31)
 
 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
@@ -375,6 +396,26 @@
 
 #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL		BIT(6)
 
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT		0
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK		0x3ff
+#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT		10
+#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK		0x3ff
+#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT		20
+#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK		0x3f
+#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT		27
+#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK			0x3f
+#define AR934X_PLL_DDR_DIT_DITHER_EN			BIT(31)
+
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT		0
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK		0x3f
+#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT		6
+#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK		0x3f
+#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT		12
+#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK		0x3f
+#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT		18
+#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK			0x3f
+#define AR934X_PLL_CPU_DIT_DITHER_EN			BIT(31)
+
 #define QCA953X_PLL_CPU_CONFIG_REG			0x00
 #define QCA953X_PLL_DDR_CONFIG_REG			0x04
 #define QCA953X_PLL_CLK_CTRL_REG			0x08
@@ -1081,10 +1122,12 @@
 #define AR934X_SRIF_CPU_DPLL1_REG			0x1c0
 #define AR934X_SRIF_CPU_DPLL2_REG			0x1c4
 #define AR934X_SRIF_CPU_DPLL3_REG			0x1c8
+#define AR934X_SRIF_CPU_DPLL4_REG			0x1cc
 
 #define AR934X_SRIF_DDR_DPLL1_REG			0x240
 #define AR934X_SRIF_DDR_DPLL2_REG			0x244
 #define AR934X_SRIF_DDR_DPLL3_REG			0x248
+#define AR934X_SRIF_DDR_DPLL4_REG			0x24c
 
 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT			27
 #define AR934X_SRIF_DPLL1_REFDIV_MASK			0x1f
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
index 2c6c118..17af082 100644
--- a/arch/mips/mach-ath79/include/mach/ath79.h
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -143,4 +143,7 @@ static inline int soc_is_qca956x(void)
 int ath79_eth_reset(void);
 int ath79_usb_reset(void);
 
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
+
 #endif /* __ASM_MACH_ATH79_H */
-- 
cgit v0.10.2


From 400df3099896bdd43dd72dbb5d3930cf573d14f0 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 6 May 2016 20:10:41 +0200
Subject: mips: ath79: Add support for TPLink WDR4300

Add support for the TPLink WDR4300 router, which is based on the
AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported
on this system as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index bd87ead..a94b745 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -5,6 +5,7 @@
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
+dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/tplink_wdr4300.dts b/arch/mips/dts/tplink_wdr4300.dts
new file mode 100644
index 0000000..cfda4df
--- /dev/null
+++ b/arch/mips/dts/tplink_wdr4300.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar934x.dtsi"
+
+/ {
+	model = "TP-Link WDR4300 Board";
+	compatible = "tplink,wdr4300", "qca,ar934x";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&spi0 {
+	spi-max-frequency = <25000000>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		memory-map = <0x1e000000 0x00800000>;
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+	};
+};
+
+&uart0 {
+	clock-frequency = <40000000>;
+	status = "okay";
+};
+
+&xtal {
+	clock-frequency = <40000000>;
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 527960f..7d483aa 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -42,9 +42,14 @@ config TARGET_AP143
 	bool "AP143 Reference Board"
 	select SOC_QCA953X
 
+config BOARD_TPLINK_WDR4300
+	bool "TP-Link WDR4300 Board"
+	select SOC_AR934X
+
 endchoice
 
 source "board/qca/ap121/Kconfig"
 source "board/qca/ap143/Kconfig"
+source "board/tplink/wdr4300/Kconfig"
 
 endmenu
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
new file mode 100644
index 0000000..902abf5
--- /dev/null
+++ b/board/tplink/wdr4300/Kconfig
@@ -0,0 +1,15 @@
+if BOARD_TPLINK_WDR4300
+
+config SYS_VENDOR
+	default "tplink"
+
+config SYS_SOC
+	default "ath79"
+
+config SYS_BOARD
+	default "wdr4300"
+
+config SYS_CONFIG_NAME
+	default "tplink_wdr4300"
+
+endif
diff --git a/board/tplink/wdr4300/MAINTAINERS b/board/tplink/wdr4300/MAINTAINERS
new file mode 100644
index 0000000..db239c2
--- /dev/null
+++ b/board/tplink/wdr4300/MAINTAINERS
@@ -0,0 +1,6 @@
+TPLINK_WDR4300 BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	board/tplink/wdr4300/
+F:	include/configs/tplink_wdr4300.h
+F:	configs/tplink_wdr4300_defconfig
diff --git a/board/tplink/wdr4300/Makefile b/board/tplink/wdr4300/Makefile
new file mode 100644
index 0000000..4f0c296
--- /dev/null
+++ b/board/tplink/wdr4300/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= wdr4300.o
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
new file mode 100644
index 0000000..6e070fd
--- /dev/null
+++ b/board/tplink/wdr4300/wdr4300.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB
+static void wdr4300_usb_start(void)
+{
+	void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
+					      AR71XX_GPIO_SIZE, MAP_NOCACHE);
+	if (!gpio_regs)
+		return;
+
+	/* Power up the USB HUB. */
+	clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
+	writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
+	mdelay(1);
+
+	ath79_usb_reset();
+}
+#else
+static inline void wdr4300_usb_start(void) {}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	void __iomem *regs;
+
+	regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+			   MAP_NOCACHE);
+
+	/* Assure JTAG is not disconnected. */
+	writel(0x40, regs + AR934X_GPIO_REG_FUNC);
+
+	/* Configure default GPIO input/output regs. */
+	writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
+	writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
+
+	/* Configure pin multiplexing. */
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
+	writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
+	writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
+	writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
+	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
+
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	ar934x_pll_init(560, 480, 240);
+	ar934x_ddr_init(560, 480, 240);
+#endif
+
+	wdr4300_usb_start();
+	ath79_eth_reset();
+
+	return 0;
+}
+#endif
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
new file mode 100644
index 0000000..b1af2f6
--- /dev/null
+++ b/configs/tplink_wdr4300_defconfig
@@ -0,0 +1,43 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
+CONFIG_CLK=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
new file mode 100644
index 0000000..2b9e92e
--- /dev/null
+++ b/include/configs/tplink_wdr4300.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE		0xa1000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_MHZ			280
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		0x8000
+#define CONFIG_SYS_ICACHE_SIZE		0x10000
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN		0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN	0x20000
+
+#define CONFIG_SYS_SDRAM_BASE		0xa0000000
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTARGS			\
+	"console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND		\
+	"dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
+#define CONFIG_LZMA
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x10000
+
+/*
+ * Command
+ */
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* USB, USB storage, USB ethernet */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_USE_PRIVATE_LIBGCC
+
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_GIGE
+
+#endif  /* __CONFIG_H */
-- 
cgit v0.10.2


From 9f8ac82452d8bb5eccc38a0c3c0a8f82e1774452 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Mon, 16 May 2016 10:52:10 +0100
Subject: MIPS: Use unchecked immediate addition/subtraction

In MIPS assembly there have historically been 2 variants of immediate
addition - the standard "addi" which traps if an overflow occurs, and
the unchecked "addiu" which does not trap on overflow. In release 6 of
the MIPS architecture the trapping variants of immediate addition &
subtraction have been removed. In preparation for supporting MIPSr6,
stop using the trapping instructions from assembly & switch to their
unchecked variants.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 1b56ca3..fc6dd66 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -164,12 +164,14 @@ reset:
 	li	t0, -16
 	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
 	and	sp, t1, t0		# force 16 byte alignment
-	PTR_SUB	sp, sp, GD_SIZE		# reserve space for gd
+	PTR_SUBU \
+		sp, sp, GD_SIZE		# reserve space for gd
 	and	sp, sp, t0		# force 16 byte alignment
 	move	k0, sp			# save gd pointer
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 	li	t2, CONFIG_SYS_MALLOC_F_LEN
-	PTR_SUB	sp, sp, t2		# reserve space for early malloc
+	PTR_SUBU \
+		sp, sp, t2		# reserve space for early malloc
 	and	sp, sp, t0		# force 16 byte alignment
 #endif
 	move	fp, sp
@@ -179,7 +181,7 @@ reset:
 1:
 	PTR_S	zero, 0(t0)
 	blt	t0, t1, 1b
-	 PTR_ADDI t0, PTRSIZE
+	 PTR_ADDIU t0, PTRSIZE
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
 	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
@@ -237,7 +239,7 @@ ENTRY(relocate_code)
 	 move	a0, s2			# a0 <-- destination address
 
 	/* Jump to where we've relocated ourselves */
-	PTR_ADDI t0, s2, in_ram - _start
+	PTR_ADDIU t0, s2, in_ram - _start
 	jr	t0
 	 nop
 
@@ -257,7 +259,7 @@ in_ram:
 	PTR_L	t3, -(1 * PTRSIZE)(t0)	# t3 <-- num_got_entries
 	PTR_L	t8, -(2 * PTRSIZE)(t0)	# t8 <-- _GLOBAL_OFFSET_TABLE_
 	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
-	PTR_ADDI t8, t8, 2 * PTRSIZE	# skipping first two entries
+	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
 	PTR_LI	t2, 2
 1:
 	PTR_L	t1, 0(t8)
@@ -265,16 +267,16 @@ in_ram:
 	 PTR_ADD t1, s1
 	PTR_S	t1, 0(t8)
 2:
-	PTR_ADDI t2, 1
+	PTR_ADDIU t2, 1
 	blt	t2, t3, 1b
-	 PTR_ADDI t8, PTRSIZE
+	 PTR_ADDIU t8, PTRSIZE
 
 	/* Update dynamic relocations */
 	PTR_L	t1, -(4 * PTRSIZE)(t0)	# t1 <-- __rel_dyn_start
 	PTR_L	t2, -(5 * PTRSIZE)(t0)	# t2 <-- __rel_dyn_end
 
 	b	2f			# skip first reserved entry
-	 PTR_ADDI t1, 2 * PTRSIZE
+	 PTR_ADDIU t1, 2 * PTRSIZE
 
 1:
 	lw	t8, -4(t1)		# t8 <-- relocation info
@@ -293,7 +295,7 @@ in_ram:
 
 2:
 	blt	t1, t2, 1b
-	 PTR_ADDI t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
+	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
 
 	/*
 	 * Clear BSS
@@ -307,7 +309,7 @@ in_ram:
 1:
 	PTR_S	zero, 0(t1)
 	blt	t1, t2, 1b
-	 PTR_ADDI t1, PTRSIZE
+	 PTR_ADDIU t1, PTRSIZE
 
 	move	a0, s0			# a0 <-- gd
 	move	a1, s2
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 14cc2c4..08b7c3a 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -64,7 +64,7 @@
 	/* detect associativity */
 	srl	\sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
 	andi	\sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
-	addi	\sz, \sz, 1
+	addiu	\sz, \sz, 1
 
 	/* sz *= line_sz */
 	mul	\sz, \sz, \line_sz
-- 
cgit v0.10.2


From 20286cdff766d64dc718a9d855b049580dfeb3cc Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Mon, 16 May 2016 10:52:11 +0100
Subject: MIPS: Simplify CONFIG_SYS_CPU values

Rather than having the values for CONFIG_SYS_CPU depend upon each
architecture revision, have them depend upon the more general
CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the
architecture revisions.

This is done in preparation for adding MIPSr6 support, which would
otherwise need to introduce new cases here.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 188aaba..6acd1f4 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -5,8 +5,8 @@ config SYS_ARCH
 	default "mips"
 
 config SYS_CPU
-	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
-	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+	default "mips32" if CPU_MIPS32
+	default "mips64" if CPU_MIPS64
 
 choice
 	prompt "Target select"
-- 
cgit v0.10.2


From c52ebea1ccb6f8cdd0b1d883056d215c715a5920 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Mon, 16 May 2016 10:52:12 +0100
Subject: MIPS: Support for targetting MIPSr6

Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6acd1f4..994168c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -104,7 +104,7 @@ config CPU_MIPS32_R1
 	depends on SUPPORTS_CPU_MIPS32_R1
 	select 32BIT
 	help
-	  Choose this option to build an U-Boot for release 1 or later of the
+	  Choose this option to build an U-Boot for release 1 through 5 of the
 	  MIPS32 architecture.
 
 config CPU_MIPS32_R2
@@ -112,7 +112,15 @@ config CPU_MIPS32_R2
 	depends on SUPPORTS_CPU_MIPS32_R2
 	select 32BIT
 	help
-	  Choose this option to build an U-Boot for release 2 or later of the
+	  Choose this option to build an U-Boot for release 2 through 5 of the
+	  MIPS32 architecture.
+
+config CPU_MIPS32_R6
+	bool "MIPS32 Release 6"
+	depends on SUPPORTS_CPU_MIPS32_R6
+	select 32BIT
+	help
+	  Choose this option to build an U-Boot for release 6 or later of the
 	  MIPS32 architecture.
 
 config CPU_MIPS64_R1
@@ -120,7 +128,7 @@ config CPU_MIPS64_R1
 	depends on SUPPORTS_CPU_MIPS64_R1
 	select 64BIT
 	help
-	  Choose this option to build a kernel for release 1 or later of the
+	  Choose this option to build a kernel for release 1 through 5 of the
 	  MIPS64 architecture.
 
 config CPU_MIPS64_R2
@@ -128,7 +136,15 @@ config CPU_MIPS64_R2
 	depends on SUPPORTS_CPU_MIPS64_R2
 	select 64BIT
 	help
-	  Choose this option to build a kernel for release 2 or later of the
+	  Choose this option to build a kernel for release 2 through 5 of the
+	  MIPS64 architecture.
+
+config CPU_MIPS64_R6
+	bool "MIPS64 Release 6"
+	depends on SUPPORTS_CPU_MIPS64_R6
+	select 64BIT
+	help
+	  Choose this option to build a kernel for release 6 or later of the
 	  MIPS64 architecture.
 
 endchoice
@@ -175,19 +191,25 @@ config SUPPORTS_CPU_MIPS32_R1
 config SUPPORTS_CPU_MIPS32_R2
 	bool
 
+config SUPPORTS_CPU_MIPS32_R6
+	bool
+
 config SUPPORTS_CPU_MIPS64_R1
 	bool
 
 config SUPPORTS_CPU_MIPS64_R2
 	bool
 
+config SUPPORTS_CPU_MIPS64_R6
+	bool
+
 config CPU_MIPS32
 	bool
-	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
 
 config CPU_MIPS64
 	bool
-	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
 
 config MIPS_TUNE_4KC
 	bool
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 94f7e16..655a493 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -19,8 +19,10 @@ PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
 # Optimize for MIPS architectures
 arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
 arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
 
 # Allow extra optimization for specific CPUs/SoCs
 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
-- 
cgit v0.10.2


From 4685d4e90d615adbca417826a7b777ec431e48a5 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Mon, 16 May 2016 10:52:13 +0100
Subject: malta: Remove ".set mips32" directive

We always build for a mips32 or higher ISA, so this ".set mips32"
directive is redundant. Once MIPSr6 support is added it will become
harmful since some instruction encodings change & this directive will
cause the older encodings to be incorrectly emitted instead of the
appropriate ones for the build.

In preparation for supporting MIPSr6, remove this redundant directive.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index ae09c27..534db1d 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -24,7 +24,6 @@
 
 	.text
 	.set noreorder
-	.set mips32
 
 	.globl	lowlevel_init
 lowlevel_init:
-- 
cgit v0.10.2


From 40ba13c98627055465709acd67872e381b42f928 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Mon, 16 May 2016 10:52:14 +0100
Subject: malta: Support MIPS32r6 configurations

Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6
CPUs. Allow building U-Boot for such systems by selecting
CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 994168c..dc34c18 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -28,6 +28,7 @@ config TARGET_MALTA
 	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
+	select SUPPORTS_CPU_MIPS32_R6
 	select SWAP_IO_SPACE
 	select MIPS_L1_CACHE_SHIFT_6
 
-- 
cgit v0.10.2


From e7c2729bb358064ef7baf6081e6a47cf3f878e5c Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:12 +0300
Subject: eeprom: use eeprom_execute_command for all eeprom functions

Update eeprom_execute_command() and related code to accommodate both layout
aware and layout unaware functions.

No functional changes.

Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
[trini: Make eeprom_execute_command have ulong for i2c_addr]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 54bf06c..0f2a9f7 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -24,6 +24,7 @@
 #include <config.h>
 #include <command.h>
 #include <i2c.h>
+#include <eeprom_layout.h>
 
 #ifndef	CONFIG_SYS_I2C_SPEED
 #define	CONFIG_SYS_I2C_SPEED	50000
@@ -258,7 +259,6 @@ static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc,
 }
 
 #ifdef CONFIG_CMD_EEPROM_LAYOUT
-#include <eeprom_layout.h>
 
 __weak int eeprom_parse_layout_version(char *str)
 {
@@ -271,12 +271,17 @@ static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE];
 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "<not defined>"
 #endif
 
+#endif
+
 enum eeprom_action {
+	EEPROM_READ,
+	EEPROM_WRITE,
 	EEPROM_PRINT,
 	EEPROM_UPDATE,
 	EEPROM_ACTION_INVALID,
 };
 
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
 static enum eeprom_action parse_action(char *cmd)
 {
 	if (!strncmp(cmd, "print", 5))
@@ -286,18 +291,40 @@ static enum eeprom_action parse_action(char *cmd)
 
 	return EEPROM_ACTION_INVALID;
 }
+#endif
 
 static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
-				  int i2c_addr, int layout_ver, char *key,
-				  char *value)
+				  ulong i2c_addr, int layout_ver, char *key,
+				  char *value, ulong addr, ulong off, ulong cnt)
 {
-	int rcode;
+	int rcode = 0;
+	const char *const fmt =
+		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
 	struct eeprom_layout layout;
+#endif
 
 	if (action == EEPROM_ACTION_INVALID)
 		return CMD_RET_USAGE;
 
 	eeprom_init(i2c_bus);
+	if (action == EEPROM_READ) {
+		printf(fmt, i2c_addr, "read", addr, off, cnt);
+
+		rcode = eeprom_read(i2c_addr, off, (uchar *)addr, cnt);
+
+		puts("done\n");
+		return rcode;
+	} else if (action == EEPROM_WRITE) {
+		printf(fmt, i2c_addr, "write", addr, off, cnt);
+
+		rcode = eeprom_write(i2c_addr, off, (uchar *)addr, cnt);
+
+		puts("done\n");
+		return rcode;
+	}
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
 	rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE);
 	if (rcode < 0)
 		return rcode;
@@ -313,10 +340,12 @@ static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
 	layout.update(&layout, key, value);
 
 	rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE);
+#endif
 
 	return rcode;
 }
 
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
 #define NEXT_PARAM(argc, index)	{ (argc)--; (index)++; }
 static int do_eeprom_layout(cmd_tbl_t *cmdtp, int flag, int argc,
 			    char * const argv[])
@@ -369,15 +398,13 @@ static int do_eeprom_layout(cmd_tbl_t *cmdtp, int flag, int argc,
 
 done:
 	return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
-			       field_name, field_value);
+				      field_name, field_value, 0, 0, 0);
 }
 
 #endif
 
 static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	const char *const fmt =
-		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";
 	char * const *args = &argv[2];
 	int rcode;
 	ulong dev_addr, addr, off, cnt;
@@ -398,22 +425,14 @@ static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	off = simple_strtoul(*args++, NULL, 16);
 	cnt = simple_strtoul(*args++, NULL, 16);
 
-	eeprom_init(bus_addr);
-
 	if (strcmp(argv[1], "read") == 0) {
-		printf(fmt, dev_addr, argv[1], addr, off, cnt);
-
-		rcode = eeprom_read(dev_addr, off, (uchar *)addr, cnt);
-
-		puts("done\n");
-		return rcode;
+		return eeprom_execute_command(EEPROM_READ, bus_addr, dev_addr,
+					      LAYOUT_VERSION_UNRECOGNIZED,
+					      NULL, NULL, addr, off, cnt);
 	} else if (strcmp(argv[1], "write") == 0) {
-		printf(fmt, dev_addr, argv[1], addr, off, cnt);
-
-		rcode = eeprom_write(dev_addr, off, (uchar *)addr, cnt);
-
-		puts("done\n");
-		return rcode;
+		return eeprom_execute_command(EEPROM_WRITE, bus_addr, dev_addr,
+					      LAYOUT_VERSION_UNRECOGNIZED,
+					      NULL, NULL, addr, off, cnt);
 	}
 
 	return CMD_RET_USAGE;
-- 
cgit v0.10.2


From 3dc9be82088f826dd7927bd1f947a838c9ef72b0 Mon Sep 17 00:00:00 2001
From: Nikita Kiryanov <nikita@compulab.co.il>
Date: Sat, 16 Apr 2016 17:55:13 +0300
Subject: eeprom: merge cmdline parsing of eeprom commands

Merge the parsing of layout aware and layout unaware eeprom commands into
one parsing function. With this change, layout aware commands now follow
the eeprom read and eeprom write conventions of making i2c bus and i2c address
parameters optional.

Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 0f2a9f7..0a0e4a2 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -281,17 +281,21 @@ enum eeprom_action {
 	EEPROM_ACTION_INVALID,
 };
 
-#ifdef CONFIG_CMD_EEPROM_LAYOUT
 static enum eeprom_action parse_action(char *cmd)
 {
+	if (!strncmp(cmd, "read", 4))
+		return EEPROM_READ;
+	if (!strncmp(cmd, "write", 5))
+		return EEPROM_WRITE;
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
 	if (!strncmp(cmd, "print", 5))
 		return EEPROM_PRINT;
 	if (!strncmp(cmd, "update", 6))
 		return EEPROM_UPDATE;
+#endif
 
 	return EEPROM_ACTION_INVALID;
 }
-#endif
 
 static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
 				  ulong i2c_addr, int layout_ver, char *key,
@@ -345,14 +349,14 @@ static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
 	return rcode;
 }
 
-#ifdef CONFIG_CMD_EEPROM_LAYOUT
 #define NEXT_PARAM(argc, index)	{ (argc)--; (index)++; }
-static int do_eeprom_layout(cmd_tbl_t *cmdtp, int flag, int argc,
-			    char * const argv[])
+int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int layout_ver = LAYOUT_VERSION_AUTODETECT;
 	enum eeprom_action action = EEPROM_ACTION_INVALID;
-	int i2c_bus = -1, i2c_addr = -1, index = 0;
+	int i2c_bus = -1, index = 0;
+	ulong i2c_addr = -1, addr = 0, cnt = 0, off = 0;
+	int ret;
 	char *field_name = "";
 	char *field_value = "";
 
@@ -364,78 +368,63 @@ static int do_eeprom_layout(cmd_tbl_t *cmdtp, int flag, int argc,
 	action = parse_action(argv[index]);
 	NEXT_PARAM(argc, index);
 
-	if (argc <= 1)
+	if (action == EEPROM_ACTION_INVALID)
 		return CMD_RET_USAGE;
 
-	if (!strcmp(argv[index], "-l")) {
-		NEXT_PARAM(argc, index);
-
-		layout_ver = eeprom_parse_layout_version(argv[index]);
-		NEXT_PARAM(argc, index);
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+	if (action == EEPROM_PRINT || action == EEPROM_UPDATE) {
+		if (!strcmp(argv[index], "-l")) {
+			NEXT_PARAM(argc, index);
+			layout_ver = eeprom_parse_layout_version(argv[index]);
+			NEXT_PARAM(argc, index);
+		}
 	}
+#endif
 
-	if (argc <= 1)
+	switch (action) {
+	case EEPROM_READ:
+	case EEPROM_WRITE:
+		ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+					 argv + index, 3);
+		break;
+	case EEPROM_PRINT:
+		ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+					 argv + index, 0);
+		break;
+	case EEPROM_UPDATE:
+		ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+					 argv + index, 2);
+		break;
+	default:
+		/* Get compiler to stop whining */
 		return CMD_RET_USAGE;
+	}
 
-	i2c_bus = parse_numeric_param(argv[index]);
-	NEXT_PARAM(argc, index);
-
-	i2c_addr = parse_numeric_param(argv[index]);
-	NEXT_PARAM(argc, index);
-
-	if (action == EEPROM_PRINT)
-		goto done;
+	if (ret == CMD_RET_USAGE)
+		return ret;
 
-	if (argc) {
-		field_name = argv[index];
+	while (ret--)
 		NEXT_PARAM(argc, index);
-	}
 
-	if (argc) {
-		field_value = argv[index];
+	if (action == EEPROM_READ || action == EEPROM_WRITE) {
+		addr = parse_numeric_param(argv[index]);
+		NEXT_PARAM(argc, index);
+		off = parse_numeric_param(argv[index]);
 		NEXT_PARAM(argc, index);
+		cnt = parse_numeric_param(argv[index]);
 	}
 
-done:
-	return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
-				      field_name, field_value, 0, 0, 0);
-}
-
-#endif
-
-static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char * const *args = &argv[2];
-	int rcode;
-	ulong dev_addr, addr, off, cnt;
-	int bus_addr;
-
 #ifdef CONFIG_CMD_EEPROM_LAYOUT
-	if (argc >= 2) {
-		if (!strcmp(argv[1], "update") || !strcmp(argv[1], "print"))
-			return do_eeprom_layout(cmdtp, flag, argc, argv);
+	if (action == EEPROM_UPDATE) {
+		field_name = argv[index];
+		NEXT_PARAM(argc, index);
+		field_value = argv[index];
+		NEXT_PARAM(argc, index);
 	}
 #endif
 
-	rcode = parse_i2c_bus_addr(&bus_addr, &dev_addr, argc - 2, argv + 2, 3);
-	if (rcode == CMD_RET_USAGE)
-		return rcode;
-
-	addr = simple_strtoul(*args++, NULL, 16);
-	off = simple_strtoul(*args++, NULL, 16);
-	cnt = simple_strtoul(*args++, NULL, 16);
-
-	if (strcmp(argv[1], "read") == 0) {
-		return eeprom_execute_command(EEPROM_READ, bus_addr, dev_addr,
-					      LAYOUT_VERSION_UNRECOGNIZED,
-					      NULL, NULL, addr, off, cnt);
-	} else if (strcmp(argv[1], "write") == 0) {
-		return eeprom_execute_command(EEPROM_WRITE, bus_addr, dev_addr,
-					      LAYOUT_VERSION_UNRECOGNIZED,
-					      NULL, NULL, addr, off, cnt);
-	}
-
-	return CMD_RET_USAGE;
+	return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
+				      field_name, field_value, addr, off, cnt);
 }
 
 U_BOOT_CMD(
@@ -446,9 +435,9 @@ U_BOOT_CMD(
 	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
 #ifdef CONFIG_CMD_EEPROM_LAYOUT
 	"\n"
-	"eeprom print [-l <layout_version>] bus devaddr\n"
+	"eeprom print [-l <layout_version>] <bus> <devaddr>\n"
 	"       - Print layout fields and their data in human readable format\n"
-	"eeprom update [-l <layout_version>] bus devaddr <field_name> <field_value>\n"
+	"eeprom update [-l <layout_version>] <bus> <devaddr> field_name field_value\n"
 	"       - Update a specific eeprom field with new data.\n"
 	"         The new data must be written in the same human readable format as shown by the print command.\n"
 	"\n"
-- 
cgit v0.10.2


From 83b6a43e6efdce32c7f824263ad40c86d03901f9 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Tue, 17 May 2016 10:51:44 -0300
Subject: pico-imx6ul: Select CONFIG_HUSH_PARSER option

Select CONFIG_HUSH_PARSER option in order to fix the following
problem:

Unknown command 'if' - try 'help'
Unknown command 'then' - try 'help'
Unknown command 'else' - try 'help'
Unknown command 'fi' - try 'help'

Reported-by: Daiane Angolini <daiane.angolini@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Daiane Angolini <daiane.angolini@nxp.com>

diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index cc49dc9..d46cd3b 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
-- 
cgit v0.10.2


From b6524477df87eeec436d01dd361017468c7f915f Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:10 -0700
Subject: x86: Drop asm/acpi.h

Remove asm/acpi.h which is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 88ab797..ff1faa5 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -12,7 +12,6 @@
 #include <fdtdec.h>
 #include <rtc.h>
 #include <pci.h>
-#include <asm/acpi.h>
 #include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index cef4256..e710ac4 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,7 +12,6 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
 #include <asm/lapic.h>
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index f7e0bc3..491f289 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/msr.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
deleted file mode 100644
index 4872b92..0000000
--- a/arch/x86/include/asm/acpi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * From coreboot
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __ASM_ACPI_H
-#define __ASM_ACPI_H
-
-#define RSDP_SIG		"RSD PTR "  /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"U-BootAC"  /* Must be exactly 8 bytes long! */
-#define OEM_ID			"U-Boot"    /* Must be exactly 6 bytes long! */
-#define ASLC			"U-Bo"      /* Must be exactly 4 bytes long! */
-
-/* 0 = S0, 1 = S1 ...*/
-int acpi_get_slp_type(void);
-void apci_set_slp_type(int type);
-
-#endif
-- 
cgit v0.10.2


From 5cb0f0dc88f816a08003a06cef8bd5310425e573 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:11 -0700
Subject: x86: Fix build warning in tables.c when CONFIG_SEABIOS

The following build warning is seen in tables.c:

  warning: implicit declaration of function 'memalign'

Add the missing header file to fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index a156f2c..1213a9c 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <malloc.h>
 #include <asm/sfi.h>
 #include <asm/mpspec.h>
 #include <asm/smbios.h>
-- 
cgit v0.10.2


From dca4d1a2ce920544b8158d7a5d359d41a6d35330 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:12 -0700
Subject: x86: acpi: Fix compiler warnings in write_acpi_tables()

Fix the following two build warnings in function 'write_acpi_tables':

  warning: format '%lx' expects argument of type 'long unsigned int',
  but argument 2 has type 'u32' [-Wformat=]

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 790f6fb..9873cb3 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -50,7 +50,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	}
 
 	if (i >= entries_num) {
-		debug("ACPI: Error: too many tables.\n");
+		debug("ACPI: Error: too many tables\n");
 		return;
 	}
 
@@ -353,7 +353,7 @@ u32 write_acpi_tables(u32 start)
 	/* Align ACPI tables to 16byte */
 	current = ALIGN(current, 16);
 
-	debug("ACPI: Writing ACPI tables at %lx.\n", start);
+	debug("ACPI: Writing ACPI tables at %x\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (struct acpi_rsdp *)current;
@@ -432,9 +432,9 @@ u32 write_acpi_tables(u32 start)
 		current = ALIGN(current, 16);
 	}
 
-	debug("current = %lx\n", current);
+	debug("current = %x\n", current);
 
-	debug("ACPI: done.\n");
+	debug("ACPI: done\n");
 
 	return current;
 }
-- 
cgit v0.10.2


From 07ac84eaaa5daeae4a56ff70649a3e50fc470db5 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:13 -0700
Subject: x86: irq: Reserve IRQ9 for ACPI in PIC mode

Reserve IRQ9 which is to be used as SCI interrupt number
for ACPI in PIC mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 295078305..7586fc2 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -121,6 +121,11 @@ static int create_pirq_routing_table(struct udevice *dev)
 	priv->irq_mask = fdtdec_get_int(blob, node,
 					"intel,pirq-mask", PIRQ_BITMAP);
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+		/* Reserve IRQ9 for SCI */
+		priv->irq_mask &= ~(1 << 9);
+	}
+
 	if (priv->config == PIRQ_VIA_IBASE) {
 		int ibase_off;
 
-- 
cgit v0.10.2


From d4e61f505b8fd8662142b6e27ef443f88f73176e Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:14 -0700
Subject: x86: irq: Enable SCI on IRQ9

By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 7586fc2..86183b0 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -147,6 +147,9 @@ static int create_pirq_routing_table(struct udevice *dev)
 		priv->ibase &= ~0xf;
 	}
 
+	priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+	priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
 	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 	if (!cell || len % sizeof(struct pirq_routing))
 		return -EINVAL;
@@ -216,6 +219,22 @@ static int create_pirq_routing_table(struct udevice *dev)
 	return 0;
 }
 
+static void irq_enable_sci(struct udevice *dev)
+{
+	struct irq_router *priv = dev_get_priv(dev);
+
+	if (priv->actl_8bit) {
+		/* Bit7 must be turned on to enable ACPI */
+		dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+	} else {
+		/* Write 0 to enable SCI on IRQ9 */
+		if (priv->config == PIRQ_VIA_PCI)
+			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+		else
+			writel(0, priv->ibase + priv->actl_addr);
+	}
+}
+
 int irq_router_common_init(struct udevice *dev)
 {
 	int ret;
@@ -229,6 +248,9 @@ int irq_router_common_init(struct udevice *dev)
 	pirq_route_irqs(dev, pirq_routing_table->slots,
 			get_irq_slot_count(pirq_routing_table));
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+		irq_enable_sci(dev);
+
 	return 0;
 }
 
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 5b9e673..ddb529e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -34,6 +34,8 @@ enum pirq_config {
  *		IRQ N is available to be routed
  * @lb_bdf:	irq router's PCI bus/device/function number encoding
  * @ibase:	IBASE register block base address
+ * @actl_8bit:	ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr:	ACTL register offset
  */
 struct irq_router {
 	int config;
@@ -41,6 +43,8 @@ struct irq_router {
 	u16 irq_mask;
 	u32 bdf;
 	u32 ibase;
+	bool actl_8bit;
+	int actl_addr;
 };
 
 struct pirq_routing {
diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
index e4d8ead..04ad346 100644
--- a/doc/device-tree-bindings/misc/intel,irq-router.txt
+++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
@@ -14,6 +14,11 @@ Required properties :
       "ibase": IRQ routing is in the memory-mapped IBASE register block
 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
     configuration space, required only if intel,pirq-config = "ibase".
+- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
+    be specified. The 8-bit ACTL register is seen on ICH series chipset, like
+    ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
+- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
+    in the interrupt router's PCI configuration space, or IBASE.
 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
     first cell is the register offset that controls the first PIRQ link routing.
     The second cell is the total number of PIRQ links the router supports.
-- 
cgit v0.10.2


From ce8dd77d996f8920b290d7070d4bfe744249a871 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:15 -0700
Subject: x86: dts: Update to include ACTL register details

This updates all x86 boards that currently have IRQ router in the
dts files to include ACTL register details.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4ea9262..444de1b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -84,6 +84,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 478dece..624d66d 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -88,6 +88,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 337513b..78a1ef4 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -154,6 +154,7 @@
 			irq-router {
 				compatible = "intel,queensbay-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xcee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 21c3641..f784c50 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -88,6 +88,7 @@
 			irq-router {
 				compatible = "intel,quark-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xdef8>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 60bd05a..a6c86c9 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -117,6 +117,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 5d601b3..0d462a9 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -69,6 +69,8 @@
 			irq-router {
 				compatible = "intel,irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-8bit;
+				intel,actl-addr = <0x44>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0x0e40>;
 				intel,pirq-routing = <
-- 
cgit v0.10.2


From 68af8d887c463c688f3f1dc02edf04cb58f8bf5d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:16 -0700
Subject: acpi: Change build log for ASL files

Currently when compiling U-Boot with ASL file, the build log says:

  ASL     board/intel/bayleybay/dsdt.c

This looks odd as ASL compiler's input is ASL file, not C file.
Change the make rule to use $< instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index ad1d9b5..4f882f1 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -323,7 +323,7 @@ $(obj)/%.S: $(src)/%.ttf
 
 # ACPI
 # ---------------------------------------------------------------------------
-quiet_cmd_acpi_c_asl= ASL     $@
+quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
 	$(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \
 	iasl -p $< -tc -va $<.tmp; \
-- 
cgit v0.10.2


From 3a2a3d0b485e8c810e9133eb0c86af33f5d46a14 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:17 -0700
Subject: acpi: Explicitly spell out dsdt.c in the make rule

Currently the make rule for dsdt.c uses a wildcard, as below:

  $(obj)/%.c:    $(src)/%.asl

To avoid any side effect, explicitly mention dsdt.c as this is
the file we intend to use for ACPI DSDT AML generation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 4f882f1..85b5819 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -329,7 +329,7 @@ cmd_acpi_c_asl=         \
 	iasl -p $< -tc -va $<.tmp; \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-$(obj)/%.c:    $(src)/%.asl
+$(obj)/dsdt.c:    $(src)/dsdt.asl
 	$(call cmd,acpi_c_asl)
 
 # Bzip2
-- 
cgit v0.10.2


From 8c4cc21c1fabaa2824456d722943e2083c96c712 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:18 -0700
Subject: acpi: Specify U-Boot include path for ASL files

It will be much easier if we split the whole dsdt.asl file into
multiple smaller ASL parts and have access to U-Boot include files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 85b5819..5f0b050 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -325,7 +325,7 @@ $(obj)/%.S: $(src)/%.ttf
 # ---------------------------------------------------------------------------
 quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
-	$(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \
+	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
 	iasl -p $< -tc -va $<.tmp; \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-- 
cgit v0.10.2


From 5dafcb8f7d73a844f9f0b14054b1dfe4586238eb Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:19 -0700
Subject: acpi: Output all errors/warnings/remarks when compiling ASL

Remove -va option when invoking IASL compiler so that we can see
errors/warnings/remarks in the build log.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 5f0b050..44534e1 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -326,7 +326,7 @@ $(obj)/%.S: $(src)/%.ttf
 quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
 	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
-	iasl -p $< -tc -va $<.tmp; \
+	iasl -p $< -tc $<.tmp; \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
 $(obj)/dsdt.c:    $(src)/dsdt.asl
-- 
cgit v0.10.2


From f4446629c9d60cd92d2c5d3221aed7b4ce07c552 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:20 -0700
Subject: x86: acpi: Remove unused codes

- Remove #include <> header files.
- Remove APM_CNT register defines, which should not be here as
  they are SMI related.
- Remove MP_IRQ_ defines as they are duplicates of the same ones
  in asm/mpspec.h.
- Remove ACTL register defines, which should not be here as they
  are chipset specific.
- Remove functional fixed hardware defines, which are not used.
- Remove dev_scope related defines, which are not used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 9856fa6..e82752a 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -6,11 +6,6 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
 #define RSDP_SIG		"RSD PTR "	/* RSDT pointer signature */
 #define ACPI_TABLE_CREATOR	"UBOOT   "	/* Must be 8 bytes long! */
 #define OEM_ID			"UBOOT "	/* Must be 6 bytes long! */
@@ -19,42 +14,6 @@
 #define OEM_REVISION	42
 #define ASL_COMPILER_REVISION	42
 
-/* IO ports to generate SMIs */
-#define APM_CNT			0xb2
-#define APM_CNT_CST_CONTROL	0x85
-#define APM_CNT_PST_CONTROL	0x80
-#define APM_CNT_ACPI_DISABLE	0x1e
-#define APM_CNT_ACPI_ENABLE	0xe1
-#define APM_CNT_MBI_UPDATE	0xeb
-#define APM_CNT_GNVS_UPDATE	0xea
-#define APM_CNT_FINALIZE	0xcb
-#define APM_CNT_LEGACY		0xcc
-#define APM_ST			0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT	0x0
-#define MP_IRQ_POLARITY_HIGH	0x1
-#define MP_IRQ_POLARITY_LOW	0x3
-#define MP_IRQ_POLARITY_MASK	0x3
-#define MP_IRQ_TRIGGER_DEFAULT	0x0
-#define MP_IRQ_TRIGGER_EDGE	0x4
-#define MP_IRQ_TRIGGER_LEVEL	0xc
-#define MP_IRQ_TRIGGER_MASK	0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL		0x00
-#define SCIS_MASK	0x07
-#define SCIS_IRQ9	0x00
-#define SCIS_IRQ10	0x01
-#define SCIS_IRQ11	0x02
-#define SCIS_IRQ20	0x04
-#define SCIS_IRQ21	0x05
-#define SCIS_IRQ22	0x06
-#define SCIS_IRQ23	0x07
-
 #define ACPI_REV_ACPI_1_0	1
 #define ACPI_REV_ACPI_2_0	1
 #define ACPI_REV_ACPI_3_0	2
@@ -105,14 +64,6 @@ enum acpi_address_space_type {
 	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
 };
 
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL	1	/* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT	1	/* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT	2	/* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD	1	/* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS	2	/* BM_STS avoidance bit */
-
 /* Access size definitions for Generic address structure */
 enum acpi_address_space_size {
 	ACPI_ACCESS_SIZE_UNDEFINED = 0,	/* Undefined (legacy reasons) */
@@ -172,25 +123,6 @@ struct acpi_madt {
 	u32 flags;			/* Multiple APIC flags */
 } acpi_madt_t;
 
-enum dev_scope_type {
-	SCOPE_PCI_ENDPOINT = 1,
-	SCOPE_PCI_SUB = 2,
-	SCOPE_IOAPIC = 3,
-	SCOPE_MSI_HPET = 4
-};
-
-typedef struct dev_scope {
-	u8 type;
-	u8 length;
-	u8 reserved[2];
-	u8 enumeration;
-	u8 start_bus;
-	struct {
-		u8 dev;
-		u8 fn;
-	} path[0];
-} __packed dev_scope_t;
-
 /* MADT: APIC Structure Type*/
 enum acpi_apic_types {
 	LOCALAPIC	= 0,	/* Processor local APIC */
-- 
cgit v0.10.2


From 8a8c0352556cb63c941d9bf1ff58d45c4d27d61d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:21 -0700
Subject: x86: acpi: Various changes to acpi_table.h

- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID.
- Do not typedef acpi_header_t, instead use struct acpi_table_hader.
- Use a shorter name aslc_id and aslc-revision.
- Change MCFG base address to use 32-bit value pairs (_l and _h).
- Apply ACPI_APIC_ prefix to MADT APIC type macros and make
  their names to be more readable.
- Apply __packed to struct acpi_madt_irqoverride and struct
  acpi_madt_lapic_nmi tables, as they are not naturally aligned
  by the compiler which leads to wrong sizeof(struct).
- Rename model to res1 as it is reserved after ACPI spec 1.0.
- Apply ACPI_ prefix to the PM profile macros and change them
  to enum.
- Add ospm_flags to FACS structure which is defined since ACPI 4.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index e82752a..418870e 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -6,10 +6,10 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#define RSDP_SIG		"RSD PTR "	/* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"UBOOT   "	/* Must be 8 bytes long! */
-#define OEM_ID			"UBOOT "	/* Must be 6 bytes long! */
-#define ASLC			"INTL"		/* Must be 4 bytes long! */
+#define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
+#define OEM_ID			"U-BOOT"	/* U-Boot */
+#define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
+#define ASLC_ID			"INTL"		/* Intel ASL Compiler */
 
 #define OEM_REVISION	42
 #define ASL_COMPILER_REVISION	42
@@ -74,7 +74,7 @@ enum acpi_address_space_size {
 };
 
 /* Generic ACPI header, provided by (almost) all tables */
-typedef struct acpi_table_header {
+struct acpi_table_header {
 	char signature[4];	/* ACPI signature (4 ASCII characters) */
 	u32 length;		/* Table length in bytes (incl. header) */
 	u8 revision;		/* Table version (not ACPI version!) */
@@ -82,9 +82,9 @@ typedef struct acpi_table_header {
 	char oem_id[6];		/* OEM identification */
 	char oem_table_id[8];	/* OEM table identification */
 	u32 oem_revision;	/* OEM revision number */
-	char asl_compiler_id[4]; /* ASL compiler vendor ID */
-	u32 asl_compiler_revision; /* ASL compiler revision number */
-} acpi_header_t;
+	char aslc_id[4];	/* ASL compiler vendor ID */
+	u32 aslc_revision;	/* ASL compiler revision number */
+};
 
 /* A maximum number of 32 ACPI tables ought to be enough for now */
 #define MAX_ACPI_TABLES	32
@@ -108,8 +108,8 @@ struct acpi_mcfg {
 };
 
 struct acpi_mcfg_mmconfig {
-	u32 base_address;
-	u32 base_reserved;
+	u32 base_address_l;
+	u32 base_address_h;
 	u16 pci_segment_group_number;
 	u8 start_bus_number;
 	u8 end_bus_number;
@@ -125,17 +125,17 @@ struct acpi_madt {
 
 /* MADT: APIC Structure Type*/
 enum acpi_apic_types {
-	LOCALAPIC	= 0,	/* Processor local APIC */
-	IOAPIC,			/* I/O APIC */
-	IRQSOURCEOVERRIDE,	/* Interrupt source override */
-	NMITYPE,		/* NMI source */
-	LOCALNMITYPE, 		/* Local APIC NMI */
-	LAPICADDRESSOVERRIDE,	/* Local APIC address override */
-	IOSAPIC,		/* I/O SAPIC */
-	LOCALSAPIC,		/* Local SAPIC */
-	PLATFORMIRQSOURCES,	/* Platform interrupt sources */
-	LOCALX2SAPIC,		/* Processor local x2APIC */
-	LOCALX2APICNMI,		/* Local x2APIC NMI */
+	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
+	ACPI_APIC_IOAPIC,		/* I/O APIC */
+	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
+	ACPI_APIC_NMI_SRC,		/* NMI source */
+	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
+	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
+	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
+	ACPI_APIC_LSAPIC,		/* Local SAPIC */
+	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
+	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
+	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
 };
 
 /* MADT: Processor Local APIC Structure */
@@ -153,7 +153,7 @@ struct acpi_madt_lapic {
 /* bits 1-31: reserved */
 
 /* MADT: Local APIC NMI Structure */
-struct acpi_madt_lapic_nmi {
+struct __packed acpi_madt_lapic_nmi {
 	u8 type;		/* Type (4) */
 	u8 length;		/* Length in bytes (6) */
 	u8 processor_id;	/* ACPI processor ID */
@@ -172,7 +172,7 @@ struct acpi_madt_ioapic {
 };
 
 /* MADT: Interrupt Source Override Structure */
-struct acpi_madt_irqoverride {
+struct __packed acpi_madt_irqoverride {
 	u8 type;		/* Type (2) */
 	u8 length;		/* Length in bytes (10) */
 	u8 bus;			/* ISA (0) */
@@ -186,7 +186,7 @@ struct __packed acpi_fadt {
 	struct acpi_table_header header;
 	u32 firmware_ctrl;
 	u32 dsdt;
-	u8 model;
+	u8 res1;
 	u8 preferred_pm_profile;
 	u16 sci_int;
 	u32 smi_cmd;
@@ -281,15 +281,17 @@ struct __packed acpi_fadt {
 #define ACPI_FADT_LEGACY_FREE		0x00
 
 /* FADT Preferred Power Management Profile */
-#define PM_UNSPECIFIED		0
-#define PM_DESKTOP		1
-#define PM_MOBILE		2
-#define PM_WORKSTATION		3
-#define PM_ENTERPRISE_SERVER	4
-#define PM_SOHO_SERVER		5
-#define PM_APPLIANCE_PC		6
-#define PM_PERFORMANCE_SERVER	7
-#define PM_TABLET		8	/* ACPI 5.0 */
+enum acpi_pm_profile {
+	ACPI_PM_UNSPECIFIED = 0,
+	ACPI_PM_DESKTOP,
+	ACPI_PM_MOBILE,
+	ACPI_PM_WORKSTATION,
+	ACPI_PM_ENTERPRISE_SERVER,
+	ACPI_PM_SOHO_SERVER,
+	ACPI_PM_APPLIANCE_PC,
+	ACPI_PM_PERFORMANCE_SERVER,
+	ACPI_PM_TABLET
+};
 
 /* FACS (Firmware ACPI Control Structure) */
 struct acpi_facs {
@@ -302,7 +304,9 @@ struct acpi_facs {
 	u32 x_firmware_waking_vector_l;		/* X FW waking vector, low */
 	u32 x_firmware_waking_vector_h;		/* X FW waking vector, high */
 	u8 version;				/* ACPI 4.0: 2 */
-	u8 resv[31];				/* FIXME: 4.0: ospm_flags */
+	u8 res1[3];
+	u32 ospm_flags;				/* OSPM enabled flags */
+	u8 res2[24];
 };
 
 /* FACS flags */
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 9873cb3..7ade5c9 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -58,7 +58,8 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	rsdt->entry[i] = (u32)table;
 
 	/* Fix RSDT length or the kernel will assume invalid entries */
-	rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1));
+	rsdt->header.length = sizeof(struct acpi_table_header) +
+			      (sizeof(u32) * (i + 1));
 
 	/* Re-calculate checksum */
 	rsdt->header.checksum = 0;
@@ -74,7 +75,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 		xsdt->entry[i] = (u64)(u32)table;
 
 		/* Fix XSDT length */
-		xsdt->header.length = sizeof(acpi_header_t) +
+		xsdt->header.length = sizeof(struct acpi_table_header) +
 			 (sizeof(u64) * (i + 1));
 
 		/* Re-calculate checksum */
@@ -87,7 +88,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
 			 u8 cpu, u8 apic)
 {
-	lapic->type = LOCALAPIC; /* Local APIC structure */
+	lapic->type = ACPI_APIC_LAPIC; /* Local APIC structure */
 	lapic->length = sizeof(struct acpi_madt_lapic);
 	lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
 	lapic->processor_id = cpu;
@@ -115,7 +116,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
 			 u32 gsi_base)
 {
-	ioapic->type = IOAPIC;
+	ioapic->type = ACPI_APIC_IOAPIC;
 	ioapic->length = sizeof(struct acpi_madt_ioapic);
 	ioapic->reserved = 0x00;
 	ioapic->gsi_base = gsi_base;
@@ -128,7 +129,7 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 			 u8 bus, u8 source, u32 gsirq, u16 flags)
 {
-	irqoverride->type = IRQSOURCEOVERRIDE;
+	irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
 	irqoverride->length = sizeof(struct acpi_madt_irqoverride);
 	irqoverride->bus = bus;
 	irqoverride->source = source;
@@ -141,7 +142,7 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 			 u8 cpu, u16 flags, u8 lint)
 {
-	lapic_nmi->type = LOCALNMITYPE;
+	lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
 	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
 	lapic_nmi->flags = flags;
 	lapic_nmi->processor_id = cpu;
@@ -150,17 +151,18 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 	return lapic_nmi->length;
 }
 
-static void fill_header(acpi_header_t *header, char *signature, int length)
+static void fill_header(struct acpi_table_header *header, char *signature,
+			int length)
 {
 	memcpy(header->signature, signature, length);
 	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
 }
 
 static void acpi_create_madt(struct acpi_madt *madt)
 {
-	acpi_header_t *header = &(madt->header);
+	struct acpi_table_header *header = &(madt->header);
 	unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);
 
 	memset((void *)madt, 0, sizeof(struct acpi_madt));
@@ -173,7 +175,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
 	header->revision = ACPI_REV_ACPI_2_0;
 
 	madt->lapic_addr = LAPIC_DEFAULT_BASE;
-	madt->flags = PCAT_COMPAT;
+	madt->flags = ACPI_MADT_PCAT_COMPAT;
 
 	current = acpi_fill_madt(current);
 
@@ -187,8 +189,8 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
 			 u32 base, u16 seg_nr, u8 start, u8 end)
 {
 	memset(mmconfig, 0, sizeof(*mmconfig));
-	mmconfig->base_address = base;
-	mmconfig->base_reserved = 0;
+	mmconfig->base_address_l = base;
+	mmconfig->base_address_h = 0;
 	mmconfig->pci_segment_group_number = seg_nr;
 	mmconfig->start_bus_number = start;
 	mmconfig->end_bus_number = end;
@@ -208,7 +210,7 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
 /* MCFG is defined in the PCI Firmware Specification 3.0 */
 static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 {
-	acpi_header_t *header = &(mcfg->header);
+	struct acpi_table_header *header = &(mcfg->header);
 	unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);
 
 	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
@@ -244,7 +246,7 @@ static void acpi_create_facs(struct acpi_facs *facs)
 
 static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
 {
-	acpi_header_t *header = &(rsdt->header);
+	struct acpi_table_header *header = &(rsdt->header);
 
 	/* Fill out header fields */
 	fill_header(header, "RSDT", 4);
@@ -262,7 +264,7 @@ static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
 
 static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
 {
-	acpi_header_t *header = &(xsdt->header);
+	struct acpi_table_header *header = &(xsdt->header);
 
 	/* Fill out header fields */
 	fill_header(header, "XSDT", 4);
@@ -309,12 +311,13 @@ static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
 			sizeof(struct acpi_rsdp));
 }
 
-static void acpi_create_ssdt_generator(acpi_header_t *ssdt,
+static void acpi_create_ssdt_generator(struct acpi_table_header *ssdt,
 			 const char *oem_table_id)
 {
-	unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
+	unsigned long current = (unsigned long)ssdt +
+				sizeof(struct acpi_table_header);
 
-	memset((void *)ssdt, 0, sizeof(acpi_header_t));
+	memset((void *)ssdt, 0, sizeof(struct acpi_table_header));
 
 	memcpy(&ssdt->signature, "SSDT", 4);
 	/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
@@ -322,9 +325,9 @@ static void acpi_create_ssdt_generator(acpi_header_t *ssdt,
 	memcpy(&ssdt->oem_id, OEM_ID, 6);
 	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
 	ssdt->oem_revision = OEM_REVISION;
-	memcpy(&ssdt->asl_compiler_id, ASLC, 4);
-	ssdt->asl_compiler_revision = ASL_COMPILER_REVISION;
-	ssdt->length = sizeof(acpi_header_t);
+	memcpy(&ssdt->aslc_id, ASLC_ID, 4);
+	ssdt->aslc_revision = ASL_COMPILER_REVISION;
+	ssdt->length = sizeof(struct acpi_table_header);
 
 	/* (Re)calculate length and checksum */
 	ssdt->length = current - (unsigned long)ssdt;
@@ -342,11 +345,11 @@ u32 write_acpi_tables(u32 start)
 	struct acpi_rsdt *rsdt;
 	struct acpi_xsdt *xsdt;
 	struct acpi_facs *facs;
-	acpi_header_t *dsdt;
+	struct acpi_table_header *dsdt;
 	struct acpi_fadt *fadt;
 	struct acpi_mcfg *mcfg;
 	struct acpi_madt *madt;
-	acpi_header_t *ssdt;
+	struct acpi_table_header *ssdt;
 
 	current = start;
 
@@ -381,14 +384,14 @@ u32 write_acpi_tables(u32 start)
 	acpi_create_facs(facs);
 
 	debug("ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *)current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	if (dsdt->length >= sizeof(acpi_header_t)) {
-		current += sizeof(acpi_header_t);
+	dsdt = (struct acpi_table_header *)current;
+	memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
+	if (dsdt->length >= sizeof(struct acpi_table_header)) {
+		current += sizeof(struct acpi_table_header);
 		memcpy((char *)current,
-				(char *)&AmlCode + sizeof(acpi_header_t),
-				dsdt->length - sizeof(acpi_header_t));
-		current += dsdt->length - sizeof(acpi_header_t);
+			(char *)&AmlCode + sizeof(struct acpi_table_header),
+			dsdt->length - sizeof(struct acpi_table_header));
+		current += dsdt->length - sizeof(struct acpi_table_header);
 
 		/* (Re)calculate length and checksum */
 		dsdt->length = current - (unsigned long)dsdt;
@@ -424,9 +427,9 @@ u32 write_acpi_tables(u32 start)
 	current = ALIGN(current, 16);
 
 	debug("ACPI:    * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	if (ssdt->length > sizeof(acpi_header_t)) {
+	ssdt = (struct acpi_table_header *)current;
+	acpi_create_ssdt_generator(ssdt, OEM_TABLE_ID);
+	if (ssdt->length > sizeof(struct acpi_table_header)) {
 		current += ssdt->length;
 		acpi_add_table(rsdp, ssdt);
 		current = ALIGN(current, 16);
-- 
cgit v0.10.2


From 728c4afc39a865e20a3dda2a3b4f0139f5ef4c56 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:22 -0700
Subject: x86: acpi: Reorder code in acpi_table.h

Reorder the ACPI tables appearance by following the order:
RSDP, RSDT, XSDT, FADT, FACS, MADT, MCFG. And adjust the
table flag defines accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 418870e..9175e7a 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -2,6 +2,7 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -11,33 +12,9 @@
 #define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
 #define ASLC_ID			"INTL"		/* Intel ASL Compiler */
 
-#define OEM_REVISION	42
-#define ASL_COMPILER_REVISION	42
-
-#define ACPI_REV_ACPI_1_0	1
-#define ACPI_REV_ACPI_2_0	1
-#define ACPI_REV_ACPI_3_0	2
-#define ACPI_REV_ACPI_4_0	3
-#define ACPI_REV_ACPI_5_0	5
-
 #define ACPI_RSDP_REV_ACPI_1_0	0
 #define ACPI_RSDP_REV_ACPI_2_0	2
 
-typedef struct acpi_gen_regaddr {
-	u8  space_id;	/* Address space ID */
-	u8  bit_width;	/* Register size in bits */
-	u8  bit_offset;	/* Register bit offset */
-	union {
-		/* Reserved in ACPI 2.0 - 2.0b */
-		u8  resv;
-		/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-		u8  access_size;
-	};
-	u32 addrl;	/* Register address, low 32 bits */
-	u32 addrh;	/* Register address, high 32 bits */
-} acpi_addr_t;
-
-
 /*
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
@@ -46,7 +23,7 @@ struct acpi_rsdp {
 	char signature[8];	/* RSDP signature */
 	u8 checksum;		/* Checksum of the first 20 bytes */
 	char oem_id[6];		/* OEM ID */
-	u8 revision;		/* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
+	u8 revision;		/* 0 for ACPI 1.0, others 2 */
 	u32 rsdt_address;	/* Physical address of RSDT (32 bits) */
 	u32 length;		/* Total RSDP length (incl. extended part) */
 	u64 xsdt_address;	/* Physical address of XSDT (64 bits) */
@@ -54,24 +31,11 @@ struct acpi_rsdp {
 	u8 reserved[3];
 };
 
-enum acpi_address_space_type {
-	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
-	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
-	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
-	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
-	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
-	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
-	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
-};
-
-/* Access size definitions for Generic address structure */
-enum acpi_address_space_size {
-	ACPI_ACCESS_SIZE_UNDEFINED = 0,	/* Undefined (legacy reasons) */
-	ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
-	ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
-	ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
-	ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
-};
+#define ACPI_REV_ACPI_1_0	1
+#define ACPI_REV_ACPI_2_0	1
+#define ACPI_REV_ACPI_3_0	2
+#define ACPI_REV_ACPI_4_0	3
+#define ACPI_REV_ACPI_5_0	5
 
 /* Generic ACPI header, provided by (almost) all tables */
 struct acpi_table_header {
@@ -87,7 +51,7 @@ struct acpi_table_header {
 };
 
 /* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES	32
+#define MAX_ACPI_TABLES		32
 
 /* RSDT (Root System Description Table) */
 struct acpi_rsdt {
@@ -101,84 +65,80 @@ struct acpi_xsdt {
 	u64 entry[MAX_ACPI_TABLES];
 };
 
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
-	struct acpi_table_header header;
-	u8 reserved[8];
-};
-
-struct acpi_mcfg_mmconfig {
-	u32 base_address_l;
-	u32 base_address_h;
-	u16 pci_segment_group_number;
-	u8 start_bus_number;
-	u8 end_bus_number;
-	u8 reserved[4];
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+	ACPI_PM_UNSPECIFIED = 0,
+	ACPI_PM_DESKTOP,
+	ACPI_PM_MOBILE,
+	ACPI_PM_WORKSTATION,
+	ACPI_PM_ENTERPRISE_SERVER,
+	ACPI_PM_SOHO_SERVER,
+	ACPI_PM_APPLIANCE_PC,
+	ACPI_PM_PERFORMANCE_SERVER,
+	ACPI_PM_TABLET
 };
 
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
-	struct acpi_table_header header;
-	u32 lapic_addr;			/* Local APIC address */
-	u32 flags;			/* Multiple APIC flags */
-} acpi_madt_t;
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
-	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
-	ACPI_APIC_IOAPIC,		/* I/O APIC */
-	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
-	ACPI_APIC_NMI_SRC,		/* NMI source */
-	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
-	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
-	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
-	ACPI_APIC_LSAPIC,		/* Local SAPIC */
-	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
-	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
-	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
-};
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED	101
+#define ACPI_FADT_C3_NOT_SUPPORTED	1001
 
-/* MADT: Processor Local APIC Structure */
-struct acpi_madt_lapic {
-	u8 type;		/* Type (0) */
-	u8 length;		/* Length in bytes (8) */
-	u8 processor_id;	/* ACPI processor ID */
-	u8 apic_id;		/* Local APIC ID */
-	u32 flags;		/* Local APIC flags */
-};
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE		0x00
+#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
+#define ACPI_FADT_8042			(1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
 
-#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
-/* bits 1-31: reserved */
-#define PCAT_COMPAT		(1 << 0)
-/* bits 1-31: reserved */
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD		(1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
+#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
+#define ACPI_FADT_POWER_BUTTON		(1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
+#define ACPI_FADT_FIXED_RTC		(1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
+#define ACPI_FADT_32BIT_TIMER		(1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
+#define ACPI_FADT_RESET_REGISTER	(1 << 10)
+#define ACPI_FADT_SEALED_CASE		(1 << 11)
+#define ACPI_FADT_HEADLESS		(1 << 12)
+#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
+#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
+#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
 
-/* MADT: Local APIC NMI Structure */
-struct __packed acpi_madt_lapic_nmi {
-	u8 type;		/* Type (4) */
-	u8 length;		/* Length in bytes (6) */
-	u8 processor_id;	/* ACPI processor ID */
-	u16 flags;		/* MPS INTI flags */
-	u8 lint;		/* Local APIC LINT# */
+enum acpi_address_space_type {
+	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
+	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
+	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
+	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
+	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
+	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
+	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
 };
 
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
-	u8 type;		/* Type (1) */
-	u8 length;		/* Length in bytes (12) */
-	u8 ioapic_id;		/* I/O APIC ID */
-	u8 reserved;
-	u32 ioapic_addr;	/* I/O APIC address */
-	u32 gsi_base;		/* Global system interrupt base */
+enum acpi_address_space_size {
+	ACPI_ACCESS_SIZE_UNDEFINED = 0,
+	ACPI_ACCESS_SIZE_BYTE_ACCESS,
+	ACPI_ACCESS_SIZE_WORD_ACCESS,
+	ACPI_ACCESS_SIZE_DWORD_ACCESS,
+	ACPI_ACCESS_SIZE_QWORD_ACCESS
 };
 
-/* MADT: Interrupt Source Override Structure */
-struct __packed acpi_madt_irqoverride {
-	u8 type;		/* Type (2) */
-	u8 length;		/* Length in bytes (10) */
-	u8 bus;			/* ISA (0) */
-	u8 source;		/* Bus-relative int. source (IRQ) */
-	u32 gsirq;		/* Global system interrupt */
-	u16 flags;		/* MPS INTI flags */
+struct acpi_gen_regaddr {
+	u8 space_id;	/* Address space ID */
+	u8 bit_width;	/* Register size in bits */
+	u8 bit_offset;	/* Register bit offset */
+	u8 access_size;	/* Access size */
+	u32 addrl;	/* Register address, low 32 bits */
+	u32 addrh;	/* Register address, high 32 bits */
 };
 
 /* FADT (Fixed ACPI Description Table) */
@@ -241,78 +201,109 @@ struct __packed acpi_fadt {
 	struct acpi_gen_regaddr x_gpe1_blk;
 };
 
-/* Flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED	101
-#define ACPI_FADT_C3_NOT_SUPPORTED	1001
-
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD		(1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
-#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
-#define ACPI_FADT_POWER_BUTTON		(1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
-#define ACPI_FADT_FIXED_RTC		(1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
-#define ACPI_FADT_32BIT_TIMER		(1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
-#define ACPI_FADT_RESET_REGISTER	(1 << 10)
-#define ACPI_FADT_SEALED_CASE		(1 << 11)
-#define ACPI_FADT_HEADLESS		(1 << 12)
-#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
-#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
-#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
-/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
-#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
-/* bits 22-31: reserved ACPI 5.0 */
-
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
-#define ACPI_FADT_8042			(1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
-/* No legacy devices (including 8042) */
-#define ACPI_FADT_LEGACY_FREE		0x00
-
-/* FADT Preferred Power Management Profile */
-enum acpi_pm_profile {
-	ACPI_PM_UNSPECIFIED = 0,
-	ACPI_PM_DESKTOP,
-	ACPI_PM_MOBILE,
-	ACPI_PM_WORKSTATION,
-	ACPI_PM_ENTERPRISE_SERVER,
-	ACPI_PM_SOHO_SERVER,
-	ACPI_PM_APPLIANCE_PC,
-	ACPI_PM_PERFORMANCE_SERVER,
-	ACPI_PM_TABLET
-};
+/* FACS flags */
+#define ACPI_FACS_S4BIOS_F	(1 << 0)
+#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
 
 /* FACS (Firmware ACPI Control Structure) */
 struct acpi_facs {
-	char signature[4];			/* "FACS" */
-	u32 length;				/* Length in bytes (>= 64) */
-	u32 hardware_signature;			/* Hardware signature */
-	u32 firmware_waking_vector;		/* Firmware waking vector */
-	u32 global_lock;			/* Global lock */
-	u32 flags;				/* FACS flags */
-	u32 x_firmware_waking_vector_l;		/* X FW waking vector, low */
-	u32 x_firmware_waking_vector_h;		/* X FW waking vector, high */
-	u8 version;				/* ACPI 4.0: 2 */
+	char signature[4];		/* "FACS" */
+	u32 length;			/* Length in bytes (>= 64) */
+	u32 hardware_signature;		/* Hardware signature */
+	u32 firmware_waking_vector;	/* Firmware waking vector */
+	u32 global_lock;		/* Global lock */
+	u32 flags;			/* FACS flags */
+	u32 x_firmware_waking_vector_l;	/* X FW waking vector, low */
+	u32 x_firmware_waking_vector_h;	/* X FW waking vector, high */
+	u8 version;			/* Version 2 */
 	u8 res1[3];
-	u32 ospm_flags;				/* OSPM enabled flags */
+	u32 ospm_flags;			/* OSPM enabled flags */
 	u8 res2[24];
 };
 
-/* FACS flags */
-#define ACPI_FACS_S4BIOS_F	(1 << 0)
-#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
-/* Bits 31..2: reserved */
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT	(1 << 0)
+
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+	struct acpi_table_header header;
+	u32 lapic_addr;			/* Local APIC address */
+	u32 flags;			/* Multiple APIC flags */
+};
+
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
+	ACPI_APIC_IOAPIC,		/* I/O APIC */
+	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
+	ACPI_APIC_NMI_SRC,		/* NMI source */
+	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
+	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
+	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
+	ACPI_APIC_LSAPIC,		/* Local SAPIC */
+	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
+	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
+	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
+};
+
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
+
+struct acpi_madt_lapic {
+	u8 type;		/* Type (0) */
+	u8 length;		/* Length in bytes (8) */
+	u8 processor_id;	/* ACPI processor ID */
+	u8 apic_id;		/* Local APIC ID */
+	u32 flags;		/* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+	u8 type;		/* Type (1) */
+	u8 length;		/* Length in bytes (12) */
+	u8 ioapic_id;		/* I/O APIC ID */
+	u8 reserved;
+	u32 ioapic_addr;	/* I/O APIC address */
+	u32 gsi_base;		/* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+	u8 type;		/* Type (2) */
+	u8 length;		/* Length in bytes (10) */
+	u8 bus;			/* ISA (0) */
+	u8 source;		/* Bus-relative int. source (IRQ) */
+	u32 gsirq;		/* Global system interrupt */
+	u16 flags;		/* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+	u8 type;		/* Type (4) */
+	u8 length;		/* Length in bytes (6) */
+	u8 processor_id;	/* ACPI processor ID */
+	u16 flags;		/* MPS INTI flags */
+	u8 lint;		/* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+	struct acpi_table_header header;
+	u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+	u32 base_address_l;
+	u32 base_address_h;
+	u16 pci_segment_group_number;
+	u8 start_bus_number;
+	u8 end_bus_number;
+	u8 reserved[4];
+};
+
+#define OEM_REVISION		42
+#define ASL_COMPILER_REVISION	42
 
 /* These can be used by the target port */
 
-- 
cgit v0.10.2


From cea91319c25a044c50be8da980d9abd00727d121 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:23 -0700
Subject: x86: acpi: Remove acpi_create_ssdt_generator()

This acpi_create_ssdt_generator() currently does nothing.
Remove this for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 9175e7a..c6688ea 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -302,9 +302,6 @@ struct acpi_mcfg_mmconfig {
 	u8 reserved[4];
 };
 
-#define OEM_REVISION		42
-#define ASL_COMPILER_REVISION	42
-
 /* These can be used by the target port */
 
 unsigned long acpi_create_madt_lapics(unsigned long current);
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 7ade5c9..ffe32ca 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -311,29 +311,6 @@ static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
 			sizeof(struct acpi_rsdp));
 }
 
-static void acpi_create_ssdt_generator(struct acpi_table_header *ssdt,
-			 const char *oem_table_id)
-{
-	unsigned long current = (unsigned long)ssdt +
-				sizeof(struct acpi_table_header);
-
-	memset((void *)ssdt, 0, sizeof(struct acpi_table_header));
-
-	memcpy(&ssdt->signature, "SSDT", 4);
-	/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-	ssdt->revision = ACPI_REV_ACPI_3_0;
-	memcpy(&ssdt->oem_id, OEM_ID, 6);
-	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
-	ssdt->oem_revision = OEM_REVISION;
-	memcpy(&ssdt->aslc_id, ASLC_ID, 4);
-	ssdt->aslc_revision = ASL_COMPILER_REVISION;
-	ssdt->length = sizeof(struct acpi_table_header);
-
-	/* (Re)calculate length and checksum */
-	ssdt->length = current - (unsigned long)ssdt;
-	ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
-}
-
 /*
  * QEMU's version of write_acpi_tables is defined in
  * arch/x86/cpu/qemu/fw_cfg.c
@@ -349,7 +326,6 @@ u32 write_acpi_tables(u32 start)
 	struct acpi_fadt *fadt;
 	struct acpi_mcfg *mcfg;
 	struct acpi_madt *madt;
-	struct acpi_table_header *ssdt;
 
 	current = start;
 
@@ -426,15 +402,6 @@ u32 write_acpi_tables(u32 start)
 	}
 	current = ALIGN(current, 16);
 
-	debug("ACPI:    * SSDT\n");
-	ssdt = (struct acpi_table_header *)current;
-	acpi_create_ssdt_generator(ssdt, OEM_TABLE_ID);
-	if (ssdt->length > sizeof(struct acpi_table_header)) {
-		current += ssdt->length;
-		acpi_add_table(rsdp, ssdt);
-		current = ALIGN(current, 16);
-	}
-
 	debug("current = %x\n", current);
 
 	debug("ACPI: done\n");
-- 
cgit v0.10.2


From dfbb18bcf6bf36c96b4e51d05b285a2d50ab61a9 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:24 -0700
Subject: x86: acpi: Change fill_header()

Rename fill_header() to acpi_fill_header() for consistency.
Change its signature to remove the 'length' parameter and
make it a public API.

Also remove the unnecessary include files, and improve the
AmlCode[] comment a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index c6688ea..5a829de 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -304,6 +304,7 @@ struct acpi_mcfg_mmconfig {
 
 /* These can be used by the target port */
 
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
 unsigned long acpi_create_madt_lapics(unsigned long current);
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
 			 u32 gsi_base);
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index ffe32ca..1f44b43 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -10,18 +10,13 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
-#include <dm/lists.h>
 #include <asm/acpi_table.h>
-#include <asm/cpu.h>
-#include <asm/ioapic.h>
 #include <asm/lapic.h>
 #include <asm/tables.h>
-#include <asm/pci.h>
 
 /*
- * IASL compiles the dsdt entries and
- * writes the hex values to AmlCode array.
- * CamelCase cannot be handled here.
+ * IASL compiles the dsdt entries and writes the hex values
+ * to a C array AmlCode[] (see dsdt.c).
  */
 extern const unsigned char AmlCode[];
 
@@ -151,10 +146,9 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 	return lapic_nmi->length;
 }
 
-static void fill_header(struct acpi_table_header *header, char *signature,
-			int length)
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
 {
-	memcpy(header->signature, signature, length);
+	memcpy(header->signature, signature, 4);
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
 	memcpy(header->aslc_id, ASLC_ID, 4);
@@ -168,7 +162,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
 	memset((void *)madt, 0, sizeof(struct acpi_madt));
 
 	/* Fill out header fields */
-	fill_header(header, "APIC", 4);
+	acpi_fill_header(header, "APIC");
 	header->length = sizeof(struct acpi_madt);
 
 	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
@@ -216,7 +210,7 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
 
 	/* Fill out header fields */
-	fill_header(header, "MCFG", 4);
+	acpi_fill_header(header, "MCFG");
 	header->length = sizeof(struct acpi_mcfg);
 
 	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
@@ -249,7 +243,7 @@ static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
 	struct acpi_table_header *header = &(rsdt->header);
 
 	/* Fill out header fields */
-	fill_header(header, "RSDT", 4);
+	acpi_fill_header(header, "RSDT");
 	header->length = sizeof(struct acpi_rsdt);
 
 	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
@@ -267,7 +261,7 @@ static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
 	struct acpi_table_header *header = &(xsdt->header);
 
 	/* Fill out header fields */
-	fill_header(header, "XSDT", 4);
+	acpi_fill_header(header, "XSDT");
 	header->length = sizeof(struct acpi_xsdt);
 
 	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-- 
cgit v0.10.2


From ab5efd576c4e65f056f71eb1ecb7024affaa9a92 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:25 -0700
Subject: x86: acpi: Adjust order in acpi_table.c

Rearrange the routine order a little bit, to follow the order
in which ACPI table is defined in acpi_table.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 5a829de..ad39902 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -305,14 +305,14 @@ struct acpi_mcfg_mmconfig {
 /* These can be used by the target port */
 
 void acpi_fill_header(struct acpi_table_header *header, char *signature);
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt);
 unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base);
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags);
+				 u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint);
 unsigned long acpi_fill_madt(unsigned long current);
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-			 void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
-			 u16 flags, u8 lint);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 1f44b43..76ee39d 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -2,6 +2,7 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -20,10 +21,85 @@
  */
 extern const unsigned char AmlCode[];
 
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+			    struct acpi_xsdt *xsdt)
+{
+	memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+	memcpy(rsdp->signature, RSDP_SIG, 8);
+	memcpy(rsdp->oem_id, OEM_ID, 6);
+
+	rsdp->length = sizeof(struct acpi_rsdp);
+	rsdp->rsdt_address = (u32)rsdt;
+
+	/*
+	 * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
+	 *
+	 * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+	 * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+	 * revision 0)
+	 */
+	if (xsdt == NULL) {
+		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
+	} else {
+		rsdp->xsdt_address = (u64)(u32)xsdt;
+		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+	}
+
+	/* Calculate checksums */
+	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
+	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
+			sizeof(struct acpi_rsdp));
+}
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+	memcpy(header->signature, signature, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+	struct acpi_table_header *header = &(rsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "RSDT");
+	header->length = sizeof(struct acpi_rsdt);
+
+	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+	header->revision = ACPI_REV_ACPI_2_0;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)rsdt,
+			sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+	struct acpi_table_header *header = &(xsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "XSDT");
+	header->length = sizeof(struct acpi_xsdt);
+
+	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+	header->revision = ACPI_REV_ACPI_2_0;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)xsdt,
+			sizeof(struct acpi_xsdt));
+}
+
 /**
-* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
-* and checksum.
-*/
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
 static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 {
 	int i, entries_num;
@@ -54,12 +130,12 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 
 	/* Fix RSDT length or the kernel will assume invalid entries */
 	rsdt->header.length = sizeof(struct acpi_table_header) +
-			      (sizeof(u32) * (i + 1));
+				(sizeof(u32) * (i + 1));
 
 	/* Re-calculate checksum */
 	rsdt->header.checksum = 0;
 	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
-						       rsdt->header.length);
+			rsdt->header.length);
 
 	/*
 	 * And now the same thing for the XSDT. We use the same index as for
@@ -71,7 +147,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 
 		/* Fix XSDT length */
 		xsdt->header.length = sizeof(struct acpi_table_header) +
-			 (sizeof(u64) * (i + 1));
+			(sizeof(u64) * (i + 1));
 
 		/* Re-calculate checksum */
 		xsdt->header.checksum = 0;
@@ -80,12 +156,27 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	}
 }
 
+static void acpi_create_facs(struct acpi_facs *facs)
+{
+	memset((void *)facs, 0, sizeof(struct acpi_facs));
+
+	memcpy(facs->signature, "FACS", 4);
+	facs->length = sizeof(struct acpi_facs);
+	facs->hardware_signature = 0;
+	facs->firmware_waking_vector = 0;
+	facs->global_lock = 0;
+	facs->flags = 0;
+	facs->x_firmware_waking_vector_l = 0;
+	facs->x_firmware_waking_vector_h = 0;
+	facs->version = 1;
+}
+
 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
-			 u8 cpu, u8 apic)
+				  u8 cpu, u8 apic)
 {
-	lapic->type = ACPI_APIC_LAPIC; /* Local APIC structure */
+	lapic->type = ACPI_APIC_LAPIC;
 	lapic->length = sizeof(struct acpi_madt_lapic);
-	lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
+	lapic->flags = LOCAL_APIC_FLAG_ENABLED;
 	lapic->processor_id = cpu;
 	lapic->apic_id = apic;
 
@@ -104,12 +195,13 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 		current += acpi_create_madt_lapic(
 			(struct acpi_madt_lapic *)current,
 			plat->cpu_id, plat->cpu_id);
-		}
-		return current;
+	}
+
+	return current;
 }
 
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base)
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base)
 {
 	ioapic->type = ACPI_APIC_IOAPIC;
 	ioapic->length = sizeof(struct acpi_madt_ioapic);
@@ -122,7 +214,7 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
 }
 
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags)
+				 u8 bus, u8 source, u32 gsirq, u16 flags)
 {
 	irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
 	irqoverride->length = sizeof(struct acpi_madt_irqoverride);
@@ -135,7 +227,7 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 }
 
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
-			 u8 cpu, u16 flags, u8 lint)
+			       u8 cpu, u16 flags, u8 lint)
 {
 	lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
 	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
@@ -146,14 +238,6 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 	return lapic_nmi->length;
 }
 
-void acpi_fill_header(struct acpi_table_header *header, char *signature)
-{
-	memcpy(header->signature, signature, 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
-	memcpy(header->aslc_id, ASLC_ID, 4);
-}
-
 static void acpi_create_madt(struct acpi_madt *madt)
 {
 	struct acpi_table_header *header = &(madt->header);
@@ -180,7 +264,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
 }
 
 static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
-			 u32 base, u16 seg_nr, u8 start, u8 end)
+				     u32 base, u16 seg_nr, u8 start, u8 end)
 {
 	memset(mmconfig, 0, sizeof(*mmconfig));
 	mmconfig->base_address_l = base;
@@ -196,7 +280,7 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	current += acpi_create_mcfg_mmconfig
 		((struct acpi_mcfg_mmconfig *)current,
-		 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
+		CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
 
 	return current;
 }
@@ -223,88 +307,6 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 	header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
-static void acpi_create_facs(struct acpi_facs *facs)
-{
-	memset((void *)facs, 0, sizeof(struct acpi_facs));
-
-	memcpy(facs->signature, "FACS", 4);
-	facs->length = sizeof(struct acpi_facs);
-	facs->hardware_signature = 0;
-	facs->firmware_waking_vector = 0;
-	facs->global_lock = 0;
-	facs->flags = 0;
-	facs->x_firmware_waking_vector_l = 0;
-	facs->x_firmware_waking_vector_h = 0;
-	facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
-}
-
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
-{
-	struct acpi_table_header *header = &(rsdt->header);
-
-	/* Fill out header fields */
-	acpi_fill_header(header, "RSDT");
-	header->length = sizeof(struct acpi_rsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)rsdt,
-			sizeof(struct acpi_rsdt));
-}
-
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
-{
-	struct acpi_table_header *header = &(xsdt->header);
-
-	/* Fill out header fields */
-	acpi_fill_header(header, "XSDT");
-	header->length = sizeof(struct acpi_xsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)xsdt,
-			sizeof(struct acpi_xsdt));
-}
-
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
-			 struct acpi_xsdt *xsdt)
-{
-	memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
-	memcpy(rsdp->signature, RSDP_SIG, 8);
-	memcpy(rsdp->oem_id, OEM_ID, 6);
-
-	rsdp->length = sizeof(struct acpi_rsdp);
-	rsdp->rsdt_address = (u32)rsdt;
-
-	/*
-	* Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
-	*
-	* Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
-	* If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
-	* revision 0)
-	*/
-	if (xsdt == NULL) {
-		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
-	} else {
-		rsdp->xsdt_address = (u64)(u32)xsdt;
-		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
-	}
-
-	/* Calculate checksums */
-	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
-	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
-			sizeof(struct acpi_rsdp));
-}
-
 /*
  * QEMU's version of write_acpi_tables is defined in
  * arch/x86/cpu/qemu/fw_cfg.c
@@ -323,7 +325,7 @@ u32 write_acpi_tables(u32 start)
 
 	current = start;
 
-	/* Align ACPI tables to 16byte */
+	/* Align ACPI tables to 16 byte */
 	current = ALIGN(current, 16);
 
 	debug("ACPI: Writing ACPI tables at %x\n", start);
@@ -378,15 +380,6 @@ u32 write_acpi_tables(u32 start)
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	debug("ACPI:    * MCFG\n");
-	mcfg = (struct acpi_mcfg *)current;
-	acpi_create_mcfg(mcfg);
-	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
-		current += mcfg->header.length;
-		current = ALIGN(current, 16);
-		acpi_add_table(rsdp, mcfg);
-	}
-
 	debug("ACPI:    * MADT\n");
 	madt = (struct acpi_madt *)current;
 	acpi_create_madt(madt);
@@ -396,6 +389,15 @@ u32 write_acpi_tables(u32 start)
 	}
 	current = ALIGN(current, 16);
 
+	debug("ACPI:    * MCFG\n");
+	mcfg = (struct acpi_mcfg *)current;
+	acpi_create_mcfg(mcfg);
+	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
+		current += mcfg->header.length;
+		current = ALIGN(current, 16);
+		acpi_add_table(rsdp, mcfg);
+	}
+
 	debug("current = %x\n", current);
 
 	debug("ACPI: done\n");
-- 
cgit v0.10.2


From 7e79a6bc2edb7a7dd82cdabaceaa34dbb4ab5a55 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:26 -0700
Subject: x86: acpi: Use u32 in table write routines

Use u32 instead of unsigned long in the table write routines, as
other routines do.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index ad39902..44f528e 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -307,12 +307,12 @@ struct acpi_mcfg_mmconfig {
 void acpi_fill_header(struct acpi_table_header *header, char *signature);
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 		      void *dsdt);
-unsigned long acpi_create_madt_lapics(unsigned long current);
+u32 acpi_create_madt_lapics(u32 current);
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
 			    u32 addr, u32 gsi_base);
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 				 u8 bus, u8 source, u32 gsirq, u16 flags);
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 			       u8 cpu, u16 flags, u8 lint);
-unsigned long acpi_fill_madt(unsigned long current);
+u32 acpi_fill_madt(u32 current);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 76ee39d..7ff6e8c 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -183,7 +183,7 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
 	return lapic->length;
 }
 
-unsigned long acpi_create_madt_lapics(unsigned long current)
+u32 acpi_create_madt_lapics(u32 current)
 {
 	struct udevice *dev;
 
@@ -241,7 +241,7 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 static void acpi_create_madt(struct acpi_madt *madt)
 {
 	struct acpi_table_header *header = &(madt->header);
-	unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);
+	u32 current = (u32)madt + sizeof(struct acpi_madt);
 
 	memset((void *)madt, 0, sizeof(struct acpi_madt));
 
@@ -258,7 +258,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
 	current = acpi_fill_madt(current);
 
 	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)madt;
+	header->length = current - (u32)madt;
 
 	header->checksum = table_compute_checksum((void *)madt, header->length);
 }
@@ -276,7 +276,7 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
 	return sizeof(struct acpi_mcfg_mmconfig);
 }
 
-static unsigned long acpi_fill_mcfg(unsigned long current)
+static u32 acpi_fill_mcfg(u32 current)
 {
 	current += acpi_create_mcfg_mmconfig
 		((struct acpi_mcfg_mmconfig *)current,
@@ -289,7 +289,7 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
 static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 {
 	struct acpi_table_header *header = &(mcfg->header);
-	unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);
+	u32 current = (u32)mcfg + sizeof(struct acpi_mcfg);
 
 	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
 
@@ -303,7 +303,7 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 	current = acpi_fill_mcfg(current);
 
 	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)mcfg;
+	header->length = current - (u32)mcfg;
 	header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
@@ -366,7 +366,7 @@ u32 write_acpi_tables(u32 start)
 		current += dsdt->length - sizeof(struct acpi_table_header);
 
 		/* (Re)calculate length and checksum */
-		dsdt->length = current - (unsigned long)dsdt;
+		dsdt->length = current - (u32)dsdt;
 		dsdt->checksum = 0;
 		dsdt->checksum = table_compute_checksum((void *)dsdt,
 				dsdt->length);
-- 
cgit v0.10.2


From 25e133ecb760a46f6b4a88b4b17aecfb0d6af8dd Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:27 -0700
Subject: x86: acpi: Align FACS table to a 64 byte boundary

Per ACPI spec, the FACS table address must be aligned to a 64 byte
boundary (Windows checks this, but Linux does not).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 7ff6e8c..9cdea93 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -339,7 +339,11 @@ u32 write_acpi_tables(u32 start)
 	current = ALIGN(current, 16);
 	xsdt = (struct acpi_xsdt *)current;
 	current += sizeof(struct acpi_xsdt);
-	current = ALIGN(current, 16);
+	/*
+	 * Per ACPI spec, the FACS table address must be aligned to a 64 byte
+	 * boundary (Windows checks this, but Linux does not).
+	 */
+	current = ALIGN(current, 64);
 
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
-- 
cgit v0.10.2


From 7e6343ef94e7f495f91ee20e2f5e76cfab409134 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:28 -0700
Subject: x86: acpi: Clean up table header revisions

The comment of initializing table header revision says:

    /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */

which might mislead it may increase per ACPI spec revision.
However this is not the case. It's actually a fixed number
as defined in ACPI spec, and in the laest ACPI spec 6.1,
some table header revisions are still 1. Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 44f528e..b450c43 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -31,12 +31,6 @@ struct acpi_rsdp {
 	u8 reserved[3];
 };
 
-#define ACPI_REV_ACPI_1_0	1
-#define ACPI_REV_ACPI_2_0	1
-#define ACPI_REV_ACPI_3_0	2
-#define ACPI_REV_ACPI_4_0	3
-#define ACPI_REV_ACPI_5_0	5
-
 /* Generic ACPI header, provided by (almost) all tables */
 struct acpi_table_header {
 	char signature[4];	/* ACPI signature (4 ASCII characters) */
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 9cdea93..8fef9b8 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -67,9 +67,7 @@ static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
 	/* Fill out header fields */
 	acpi_fill_header(header, "RSDT");
 	header->length = sizeof(struct acpi_rsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 1;
 
 	/* Entries are filled in later, we come with an empty set */
 
@@ -85,9 +83,7 @@ static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
 	/* Fill out header fields */
 	acpi_fill_header(header, "XSDT");
 	header->length = sizeof(struct acpi_xsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 1;
 
 	/* Entries are filled in later, we come with an empty set */
 
@@ -248,9 +244,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
 	/* Fill out header fields */
 	acpi_fill_header(header, "APIC");
 	header->length = sizeof(struct acpi_madt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 4;
 
 	madt->lapic_addr = LAPIC_DEFAULT_BASE;
 	madt->flags = ACPI_MADT_PCAT_COMPAT;
@@ -296,9 +290,7 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 	/* Fill out header fields */
 	acpi_fill_header(header, "MCFG");
 	header->length = sizeof(struct acpi_mcfg);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 1;
 
 	current = acpi_fill_mcfg(current);
 
-- 
cgit v0.10.2


From 9e70a11622eb01c90c5152c08c3166adc60aed1e Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:29 -0700
Subject: x86: acpi: Add some generic ASL libraries

This adds several generic ASL libraries that can be included by
other ASL files, which are:

- debug.asl: for debug output using POST I/O port and legacy serial port
- globutil.asl: for string compare routines
- statdef.asl: for _STA status values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl
new file mode 100644
index 0000000..8e7b603
--- /dev/null
+++ b/arch/x86/include/asm/acpi/debug.asl
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,
+	    , 8,
+	CLCR, 8,
+	CMCR, 8,
+	CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+	Store(0x83, CLCR)
+	Store(0x01, CDAT)	/* 115200 baud (low) */
+	Store(0x00, CDLM)	/* 115200 baud (high) */
+	Store(0x03, CLCR)	/* word=8 stop=1 parity=none */
+	Store(0x03, CMCR)	/* DTR=1 RTS=1 out1/2=Off loop=Off */
+	Store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+	And(CLSR, 0x20, Local0)
+	While (LEqual(Local0, Zero)) {
+		And(CLSR, 0x20, Local0)
+	}
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+	THRE()
+	Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+	If (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+	And(Arg0, 0x0f, Local0)
+	If (LLess(Local0, 10)) {
+		Add(Local0, 0x30, Local0)
+	} Else {
+		Add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+	If (LEqual(ObjectType(Arg0), 1)) {
+		If (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} Else {
+			If (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} Else {
+				DBGB(Arg0)
+			}
+		}
+	} Else {
+		Name(BDBG, Buffer(80) {})
+		Store(Arg0, BDBG)
+		Store(0, Local1)
+		While (One) {
+			Store(GETC(BDBG, Local1), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (Zero)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+
+	Return (Zero)
+}
diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl
new file mode 100644
index 0000000..46381b6
--- /dev/null
+++ b/arch/x86/include/asm/acpi/globutil.asl
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Method(MIN, 2)
+{
+	If (LLess(Arg0, Arg1)) {
+		Return (Arg0)
+	} Else {
+		Return (Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While (LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		If (LGreater(Local2, Local3)) {
+			Return (One)
+		} Else {
+			If (LLess(Local2, Local3)) {
+				Return (Ones)
+			}
+		}
+		Increment(Local4)
+	}
+
+	If (LLess(Local4, Local5)) {
+		Return (One)
+	} Else {
+		If (LLess(Local4, Local6)) {
+			Return (Ones)
+		} Else {
+			Return (Zero)
+		}
+	}
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return (Zero)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While (LLess(Local2, Local3)) {
+		If (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return (Zero)
+		}
+		Increment(Local2)
+	}
+
+	Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	If (LNotEqual(Arg0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, Arg0, Local0)
+	}
+
+	Return (Local0)
+}
diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl
new file mode 100644
index 0000000..e8cff10
--- /dev/null
+++ b/arch/x86/include/asm/acpi/statdef.asl
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING		0x00
+#define STA_PRESENT		0x01
+#define STA_ENABLED		0x03
+#define STA_DISABLED		0x09
+#define STA_INVISIBLE		0x0b
+#define STA_UNAVAILABLE		0x0d
+#define STA_VISIBLE		0x0f
+
+/* SMBus status codes */
+#define SMB_OK			0x00
+#define SMB_UNKNOWN_FAIL	0x07
+#define SMB_DEV_ADDR_NAK	0x10
+#define SMB_DEVICE_ERROR	0x11
+#define SMB_DEV_CMD_DENIED	0x12
+#define SMB_UNKNOWN_ERR		0x13
+#define SMB_DEV_ACC_DENIED	0x17
+#define SMB_TIMEOUT		0x18
+#define SMB_HST_UNSUPP_PROTOCOL	0x19
+#define SMB_BUSY		0x1a
+#define SMB_PKT_CHK_ERROR	0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK	0x00
+#define NOTIFY_DEVICE_CHECK	0x01
+#define NOTIFY_DEVICE_WAKE	0x02
+#define NOTIFY_EJECT_REQUEST	0x03
+#define NOTIFY_DEVICE_CHECK_JR	0x04
+#define NOTIFY_FREQUENCY_ERROR	0x05
+#define NOTIFY_BUS_MODE		0x06
+#define NOTIFY_POWER_FAULT	0x07
+#define NOTIFY_CAPABILITIES	0x08
+#define NOTIFY_PLD_CHECK	0x09
+#define NOTIFY_SLIT_UPDATE	0x0b
+#define NOTIFY_SRA_UPDATE	0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG	0x80
+#define NOTIFY_BAT_INFOCHG	0x81
+#define NOTIFY_BAT_MAINTDATA	0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG	0x80
+#define NOTIFY_PWR_INFOCHG	0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG	0x80
+#define NOTIFY_TZ_TRIPPTCHG	0x81
+#define NOTIFY_TZ_DEVLISTCHG	0x82
+#define NOTIFY_TZ_RELTBLCHG	0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON	0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON	0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG	0x80
+#define NOTIFY_CPU_CSTATECHG	0x81
+#define NOTIFY_CPU_THROTLCHG	0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG	0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG	0x80
+#define NOTIFY_ALS_COLORTMPCHG	0x81
+#define NOTIFY_ALS_RESPCHG	0x82
-- 
cgit v0.10.2


From fc4f5cccd87abf4c72b13f64b49719fde9107cad Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:30 -0700
Subject: x86: acpi: Return table length in acpi_create_madt_lapics()

Like other MADT table write routines, make acpi_create_madt_lapics()
return how many bytes it has written instead of the table end addr.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index b450c43..ff4802a 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -301,7 +301,7 @@ struct acpi_mcfg_mmconfig {
 void acpi_fill_header(struct acpi_table_header *header, char *signature);
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 		      void *dsdt);
-u32 acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_lapics(u32 current);
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
 			    u32 addr, u32 gsi_base);
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 8fef9b8..989cf7d 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -179,21 +179,23 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
 	return lapic->length;
 }
 
-u32 acpi_create_madt_lapics(u32 current)
+int acpi_create_madt_lapics(u32 current)
 {
 	struct udevice *dev;
+	int length = 0;
 
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
 		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 
-		current += acpi_create_madt_lapic(
+		length += acpi_create_madt_lapic(
 			(struct acpi_madt_lapic *)current,
 			plat->cpu_id, plat->cpu_id);
+		current += length;
 	}
 
-	return current;
+	return length;
 }
 
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
-- 
cgit v0.10.2


From 42f8ebfd23a525c24011830b0d221c8d8cbcc5c9 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:31 -0700
Subject: x86: baytrail: Add platform ASL files

This adds basic BayTrail platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for
now. They will be added in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
new file mode 100644
index 0000000..2c3585a
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+	RP_METHOD(prefix_, dev_, 0) \
+	RP_METHOD(prefix_, dev_, 1) \
+	RP_METHOD(prefix_, dev_, 2) \
+	RP_METHOD(prefix_, dev_, 3) \
+	RP_METHOD(prefix_, dev_, 4) \
+	RP_METHOD(prefix_, dev_, 5) \
+	RP_METHOD(prefix_, dev_, 6) \
+	RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_IRQ(dev_, 0, a_), \
+	ACPI_DEV_IRQ(dev_, 1, b_), \
+	ACPI_DEV_IRQ(dev_, 2, c_), \
+	ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+	Name(_ADR, dev_ ## 000 ## func_) \
+	Name(_PRW, Package() { 0, 0 }) \
+	Method(_PRT) { \
+		If (PICM) { \
+			Return (prefix_ ## func_ ## A) \
+		} Else { \
+			Return (prefix_ ## func_ ## P) \
+		} \
+	} \
+}
+
+/* SoC specific PIRQ route configuration */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
new file mode 100644
index 0000000..aa72085
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+}
+
+Device (LNKA)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 1)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTA)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTA */
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTA, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 2)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTB)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTB */
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTB, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 3)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTC)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTC */
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTC, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 4)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTD)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTD */
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTD, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 5)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTE)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTE */
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTE, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 6)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTF)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTF */
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTF, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 7)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTG)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTG */
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTG, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 8)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTH)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTH */
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTH, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
new file mode 100644
index 0000000..64d3820
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice */
+	Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000..d746314
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,	A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, PCIE_DEV,	A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000..1dca977
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	#include "irqlinks.asl"
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			/*
+			 * Disable as Windows doesn't like it, and systems
+			 * don't seem to use it
+			 */
+			/* IRQNoFlags() { 8 } */
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000..bd72842
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
new file mode 100644
index 0000000..eb5ae76
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000..34d3951
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+
+		/* High PCI Memory Region */
+		QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , UMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		/* Update High PCI resource area */
+		CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+		CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+		CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+		/* Set base address to 48GB and allocate 16GB for PCI space */
+		Store(0xc00000000, UMIN)
+		Store(0x400000000, ULEN)
+		Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* USB EHCI 0:1d.0 */
+	#include "usb.asl"
+
+	/* USB XHCI 0:14.0 */
+	#include "xhci.asl"
+
+	/* IRQ routing for each PCI device */
+	#include "irqroute.asl"
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000..311f471
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 4 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 2)
+
+	/* Highest D state in S4 state */
+	Name(_S4D, 2)
+
+	Device (HUB7)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device(PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device(PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device(PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device(PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000..a5a4404
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name(_ADR, 0x00140000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 3 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 3)
+
+	Device (RHUB)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device (PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device (PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device (PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device (PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000..798d35b
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV		0x00
+
+/* Graphics and Display */
+#define GFX_DEV		0x02
+
+/* MIPI */
+#define MIPI_DEV	0x03
+
+/* EMMC Port */
+#define EMMC_DEV	0x10
+
+/* SDIO Port */
+#define SDIO_DEV	0x11
+
+/* SD Port */
+#define SD_DEV		0x12
+
+/* SATA */
+#define SATA_DEV	0x13
+
+/* xHCI */
+#define XHCI_DEV	0x14
+
+/* LPE Audio */
+#define LPE_DEV		0x15
+
+/* OTG */
+#define OTG_DEV		0x16
+
+/* MMC45 Port */
+#define MMC45_DEV	0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV	0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV		0x1a
+
+/* HD Audio */
+#define HDA_DEV		0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV	0x1c
+
+/* EHCI */
+#define EHCI_DEV	0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV	0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV		0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000..62a9105
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS		0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS		0xfeb00000
+#define ABORT_BASE_SIZE			0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS		0xfed01000
+#define SPI_BASE_SIZE			0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS		0xfed03000
+#define PMC_BASE_SIZE			0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS		0xfed05000
+#define PUNIT_BASE_SIZE			0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS		0xfed08000
+#define ILB_BASE_SIZE			0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		0xfed1c000
+#define RCBA_BASE_SIZE			0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS		0xfef00000
+#define MPHY_BASE_SIZE			0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS		0x0400
+#define ACPI_BASE_SIZE			0x80
+
+#define GPIO_BASE_ADDRESS		0x0500
+#define GPIO_BASE_SIZE			0x100
+
+#define SMBUS_BASE_ADDRESS		0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000..cd66f83
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ			16
+#define PIRQB_APIC_IRQ			17
+#define PIRQC_APIC_IRQ			18
+#define PIRQD_APIC_IRQ			19
+#define PIRQE_APIC_IRQ			20
+#define PIRQF_APIC_IRQ			21
+#define PIRQG_APIC_IRQ			22
+#define PIRQH_APIC_IRQ			23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ			24
+#define LPE_DMA1_IRQ			25
+#define LPE_SSP0_IRQ			26
+#define LPE_SSP1_IRQ			27
+#define LPE_SSP2_IRQ			28
+#define LPE_IPC2HOST_IRQ		29
+#define LPSS_I2C1_IRQ			32
+#define LPSS_I2C2_IRQ			33
+#define LPSS_I2C3_IRQ			34
+#define LPSS_I2C4_IRQ			35
+#define LPSS_I2C5_IRQ			36
+#define LPSS_I2C6_IRQ			37
+#define LPSS_I2C7_IRQ			38
+#define LPSS_HSUART1_IRQ		39
+#define LPSS_HSUART2_IRQ		40
+#define LPSS_SPI_IRQ			41
+#define LPSS_DMA1_IRQ			42
+#define LPSS_DMA2_IRQ			43
+#define SCC_EMMC_IRQ			44
+#define SCC_SDIO_IRQ			46
+#define SCC_SD_IRQ			47
+#define GPIO_NC_IRQ			48
+#define GPIO_SC_IRQ			49
+#define GPIO_SUS_IRQ			50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0		51
+#define GPIO_S0_DED_IRQ_1		52
+#define GPIO_S0_DED_IRQ_2		53
+#define GPIO_S0_DED_IRQ_3		54
+#define GPIO_S0_DED_IRQ_4		55
+#define GPIO_S0_DED_IRQ_5		56
+#define GPIO_S0_DED_IRQ_6		57
+#define GPIO_S0_DED_IRQ_7		58
+#define GPIO_S0_DED_IRQ_8		59
+#define GPIO_S0_DED_IRQ_9		60
+#define GPIO_S0_DED_IRQ_10		61
+#define GPIO_S0_DED_IRQ_11		62
+#define GPIO_S0_DED_IRQ_12		63
+#define GPIO_S0_DED_IRQ_13		64
+#define GPIO_S0_DED_IRQ_14		65
+#define GPIO_S0_DED_IRQ_15		66
+#define GPIO_S5_DED_IRQ_0		67
+#define GPIO_S5_DED_IRQ_1		68
+#define GPIO_S5_DED_IRQ_2		69
+#define GPIO_S5_DED_IRQ_3		70
+#define GPIO_S5_DED_IRQ_4		71
+#define GPIO_S5_DED_IRQ_5		72
+#define GPIO_S5_DED_IRQ_6		73
+#define GPIO_S5_DED_IRQ_7		74
+#define GPIO_S5_DED_IRQ_8		75
+#define GPIO_S5_DED_IRQ_9		76
+#define GPIO_S5_DED_IRQ_10		77
+#define GPIO_S5_DED_IRQ_11		78
+#define GPIO_S5_DED_IRQ_12		79
+#define GPIO_S5_DED_IRQ_13		80
+#define GPIO_S5_DED_IRQ_14		81
+#define GPIO_S5_DED_IRQ_15		82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot)		GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot)		GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot)		_GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot)		_GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
-- 
cgit v0.10.2


From 4470f2d51c26b80953e76c8eb54ed4e6947f4223 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:32 -0700
Subject: x86: baytrail: Generate ACPI FADT/MADT tables

FADT/MADT tables are platform specific. Generate them for BayTrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 5be5491..a0216f3 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += cpu.o
 obj-y += early_uart.o
 obj-y += fsp_configs.o
 obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
new file mode 100644
index 0000000..1d54f7d
--- /dev/null
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			2, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
-- 
cgit v0.10.2


From ad3098f7b8167915f59c2a2cb59fdac26730f601 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:33 -0700
Subject: x86: baytrail: Enable ACPI table generation for all boards

Enable ACPI table generation by creating a DSDT table for all baytrail
boards: conga-qeval20-qa3-e3845, bayleybay and minnowmax.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile
index 23b8748..b784510 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Makefile
+++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= conga-qeval20-qa3.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
new file mode 100644
index 0000000..eace459
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile
index 88b5aad..52dda7d 100644
--- a/board/intel/bayleybay/Makefile
+++ b/board/intel/bayleybay/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= bayleybay.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/bayleybay/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/bayleybay/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
index 1a61432..73e5a8f 100644
--- a/board/intel/minnowmax/Makefile
+++ b/board/intel/minnowmax/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= minnowmax.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/minnowmax/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index ce1f519..7758c11 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 5186345..26f416c4 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -8,6 +8,7 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 9930d56..5daa648 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,6 +8,7 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
-- 
cgit v0.10.2


From 7a47a0827ddc047ec6c722ac4567b4c19e699412 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:34 -0700
Subject: x86: baytrail: Add .gitignore for ACPI enabled boards

Let git ignore dsdt.aml, dsdt.asl.tmp and dsdt.c files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/bayleybay/.gitignore b/board/intel/bayleybay/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/bayleybay/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/minnowmax/.gitignore b/board/intel/minnowmax/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/minnowmax/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
-- 
cgit v0.10.2


From 030b9e34c97e94c0a1a30ed391058b130ba6d314 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:35 -0700
Subject: x86: Remove acpi=off boot parameter when ACPI is on

Remove the kernel boot parameter acpi=off so that kernel can turn on
ACPI support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index b79f47b..b4aad6c 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -193,14 +193,19 @@
 #define CONFIG_HOSTNAME		x86
 #define CONFIG_BOOTFILE		"bzImage"
 #define CONFIG_LOADADDR		0x1000000
-#define CONFIG_RAMDISK_ADDR		0x4000000
+#define CONFIG_RAMDISK_ADDR	0x4000000
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#define CONFIG_OTHBOOTARGS	"othbootargs=\0"
+#else
+#define CONFIG_OTHBOOTARGS	"othbootargs=acpi=off\0"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS			\
 	CONFIG_STD_DEVICES_SETTINGS			\
 	"pciconfighost=1\0"				\
 	"netdev=eth0\0"					\
 	"consoledev=ttyS0\0"				\
-	"othbootargs=acpi=off\0"			\
+	CONFIG_OTHBOOTARGS				\
 	"ramdiskaddr=0x4000000\0"			\
 	"ramdiskfile=initramfs.gz\0"
 
-- 
cgit v0.10.2


From eda995a8b021fdc9f8d862bdb86babb06d8ef5d1 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:36 -0700
Subject: x86: doc: Minor update for accuracy

This updates the doc for the following places:
- Mention CRB for Bayley Bay
- Mention Congatec QEVAL 2.0 & conga-QA3/E3845
- Limit part of the QEMU paragraphs to 80 cols
- Correct some typos (drive, it's, Ubuntu)
- Add description for "console=ttyS0,115200"
- Remove CONFIG_BOOTDELAY description which is already
  in x86-common.h

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.x86 b/doc/README.x86
index c5c3010..732d375 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -23,7 +23,8 @@ In this case, known as bare mode, from the fact that it runs on the
 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
 are supported:
 
-   - Bayley Bay
+   - Bayley Bay CRB
+   - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
    - Galileo
@@ -412,18 +413,19 @@ If you want to check both consoles, use '-serial stdio'.
 Multicore is also supported by QEMU via '-smp n' where n is the number of cores
 to instantiate. Note, the maximum supported CPU number in QEMU is 255.
 
-The fw_cfg interface in QEMU also provides information about kernel data, initrd,
-command-line arguments and more. U-Boot supports directly accessing these informtion
-from fw_cfg interface, this saves the time of loading them from hard disk or
-network again, through emulated devices. To use it , simply providing them in
-QEMU command line:
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line:
 
 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
     -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
 
 Note: -initrd and -smp are both optional
 
-Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel:
 
  => qfw
 qfw - QEMU firmware interface
@@ -437,8 +439,8 @@ qfw <command>
 => qfw load
 loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
 
-Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
-can be used to boot the kernel:
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel:
 
 => zboot 02000000 - 04000000 1b1ab50
 
@@ -490,8 +492,8 @@ Booting Ubuntu
 --------------
 As an example of how to set up your boot flow with U-Boot, here are
 instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA driver but are equally applicable on
-other platforms and other media. There are really only four steps and its a
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
 very simple script, but a more detailed explanation is provided here for
 completeness.
 
@@ -499,7 +501,7 @@ Note: It is possible to set up U-Boot to boot automatically using syslinux.
 It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
 GUID. If you figure these out, please post patches to this README.
 
-Firstly, you will need Ubunutu installed on an available disk. It should be
+Firstly, you will need Ubuntu installed on an available disk. It should be
 possible to make U-Boot start a USB start-up disk but for now let's assume
 that you used another boot loader to install Ubuntu.
 
@@ -659,7 +661,7 @@ U-Boot:
    Loading bzImage at address 100000 (5805728 bytes)
    Magic signature found
    Initial RAM disk at linear address 0x04000000, size 19215259 bytes
-   Kernel command line: "console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+   Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
 
    Starting kernel ...
 
@@ -679,13 +681,14 @@ above commands into a script since then it will be faster.
                   240,329  ahci
                 1,422,704  vesa display
 
-Now the kernel actually starts:
+Now the kernel actually starts: (if you want to examine kernel boot up message
+on the serial console, append "console=ttyS0,115200" to the kernel command line)
 
    [    0.000000] Initializing cgroup subsys cpuset
    [    0.000000] Initializing cgroup subsys cpu
    [    0.000000] Initializing cgroup subsys cpuacct
    [    0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
-   [    0.000000] Command line: console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+   [    0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
 
 It continues for a long time. Along the way you will see it pick up your
 ramdisk:
@@ -736,14 +739,6 @@ If you want to put this in a script you can use something like this:
 The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
 command.
 
-You will also need to add this to your board configuration file, e.g.
-include/configs/minnowmax.h:
-
-   #define CONFIG_BOOTDELAY	2
-
-Now when you reset your board it wait a few seconds (in case you want to
-interrupt) and then should boot straight into Ubuntu.
-
 You can also bake this behaviour into your build by hard-coding the
 environment variables if you add this to minnowmax.h:
 
-- 
cgit v0.10.2


From 49d929bbc49ebab3ffbc9ad2d0f13ba296d61d02 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 7 May 2016 07:46:37 -0700
Subject: x86: doc: Document ACPI support

Remove ACPI from the TODO list and add a new section to document
current ACPI support in U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.x86 b/doc/README.x86
index 732d375..ce806ee 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -958,12 +958,52 @@ transformations. Remember to add attribution to coreboot for new files added
 to U-Boot. This should go at the top of each file and list the coreboot
 filename where the code originated.
 
+ACPI Support Status
+-------------------
+Advanced Configuration and Power Interface (ACPI) [16] aims to establish
+industry-standard interfaces enabling OS-directed configuration, power
+management, and thermal management of mobile, desktop, and server platforms.
+
+Linux can boot without ACPI with "acpi=off" command line parameter, but
+with ACPI the kernel gains the capabilities to handle power management.
+For Windows, ACPI is a must-have firmware feature since Windows Vista.
+CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
+U-Boot. This requires Intel ACPI compiler to be installed on your host to
+compile ACPI DSDT table written in ASL format to AML format. You can get
+the compiler via "apt-get install iasl" if you are on Ubuntu or download
+the source from [17] to compile one by yourself.
+
+Current ACPI support in U-Boot is not complete. More features will be added
+in the future. The status as of today is:
+
+ * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
+ * Support one static DSDT table only, compiled by Intel ACPI compiler.
+ * Support S0/S5, reboot and shutdown from OS.
+ * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support ACPI interrupts with SCI only.
+
+Features not supported so far (to make it a complete ACPI solution):
+ * S3 (Suspend to RAM), S4 (Suspend to Disk).
+ * Install and boot Ubuntu 14.04 (or above) from U-Boot with legacy interface.
+ * Install and boot Windows 8.1/10 from U-Boot with legacy interface.
+
+Features that are optional:
+ * ACPI global NVS support. We may need it to simplify ASL code logic if
+   utilizing NVS variables. Most likely we will need this sooner or later.
+ * Dynamic AML bytecodes insertion at run-time. We may need this to support
+   SSDT table generation and DSDT fix up.
+ * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
+   those legacy stuff into U-Boot. ACPI spec allows a system that does not
+   support SMI (a legacy-free system).
+
+So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+a pre-installed Ubuntu 14.04 from a SATA drive. Most devices seem to work
+correctly and the board can respond a reboot/shutdown command from Ubuntu.
 
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
-- SMI and ACPI support, to provide platform info and facilities to Linux
 
 References
 ----------
@@ -982,3 +1022,5 @@ References
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
 [14] http://www.seabios.org/SeaBIOS
 [15] doc/device-tree-bindings/misc/intel,irq-router.txt
+[16] http://www.acpi.info
+[17] https://www.acpica.org/downloads
-- 
cgit v0.10.2


From dd6f3abbb81d4d0f8883a523e26fd45833a6b0d3 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 6 May 2016 10:40:22 -0400
Subject: x86: qemu: Move qfw command over to cmd and add Kconfig entry

- Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into
  cmd/qemu_fw_cfg.c
- Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h
- Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 2604a68..13bec7a 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qemu_fw_cfg.h>
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
@@ -21,7 +22,6 @@
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/sipi.h>
-#include <asm/fw_cfg.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 #include <dm/lists.h>
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 6eeddf1..97b965c 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,4 +7,5 @@
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
-obj-y += cpu.o fw_cfg.o qemu.o
+obj-y += cpu.o qemu.o
+obj-$(CONFIG_QEMU_ACPI_TABLE) += acpi_table.o
diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c
new file mode 100644
index 0000000..49381ac
--- /dev/null
+++ b/arch/x86/cpu/qemu/acpi_table.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <qemu_fw_cfg.h>
+#include <asm/io.h>
+#include <asm/tables.h>
+#include <asm/e820.h>
+#include <linux/list.h>
+#include <memalign.h>
+
+/*
+ * This function allocates memory for ACPI tables
+ *
+ * @entry : BIOS linker command entry which tells where to allocate memory
+ *          (either high memory or low memory)
+ * @addr  : The address that should be used for low memory allcation. If the
+ *          memory allocation request is 'ZONE_HIGH' then this parameter will
+ *          be ignored.
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
+{
+	uint32_t size, align;
+	struct fw_file *file;
+	unsigned long aligned_addr;
+
+	align = le32_to_cpu(entry->alloc.align);
+	/* align must be power of 2 */
+	if (align & (align - 1)) {
+		printf("error: wrong alignment %u\n", align);
+		return -EINVAL;
+	}
+
+	file = qemu_fwcfg_find_file(entry->alloc.file);
+	if (!file) {
+		printf("error: can't find file %s\n", entry->alloc.file);
+		return -ENOENT;
+	}
+
+	size = be32_to_cpu(file->cfg.size);
+
+	/*
+	 * ZONE_HIGH means we need to allocate from high memory, since
+	 * malloc space is already at the end of RAM, so we directly use it.
+	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
+	 * in which is low memory
+	 */
+	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+		aligned_addr = (unsigned long)memalign(align, size);
+		if (!aligned_addr) {
+			printf("error: allocating resource\n");
+			return -ENOMEM;
+		}
+	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
+		aligned_addr = ALIGN(*addr, align);
+	} else {
+		printf("error: invalid allocation zone\n");
+		return -EINVAL;
+	}
+
+	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
+	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
+
+	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+			      size, (void *)aligned_addr);
+	file->addr = aligned_addr;
+
+	/* adjust address for low memory allocation */
+	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+		*addr = (aligned_addr + size);
+
+	return 0;
+}
+
+/*
+ * This function patches ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells how to patch
+ *          ACPI tables
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_pointer(struct bios_linker_entry *entry)
+{
+	struct fw_file *dest, *src;
+	uint32_t offset = le32_to_cpu(entry->pointer.offset);
+	uint64_t pointer = 0;
+
+	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
+	if (!dest || !dest->addr)
+		return -ENOENT;
+	src = qemu_fwcfg_find_file(entry->pointer.src_file);
+	if (!src || !src->addr)
+		return -ENOENT;
+
+	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
+	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
+
+	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
+	pointer	= le64_to_cpu(pointer);
+	pointer += (unsigned long)src->addr;
+	pointer	= cpu_to_le64(pointer);
+	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
+
+	return 0;
+}
+
+/*
+ * This function updates checksum fields of ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells where to update ACPI table
+ *          checksums
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_checksum(struct bios_linker_entry *entry)
+{
+	struct fw_file *file;
+	uint8_t *data, cksum = 0;
+	uint8_t *cksum_start;
+
+	file = qemu_fwcfg_find_file(entry->cksum.file);
+	if (!file || !file->addr)
+		return -ENOENT;
+
+	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
+	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
+	cksum = table_compute_checksum(cksum_start,
+				       le32_to_cpu(entry->cksum.length));
+	*data = cksum;
+
+	return 0;
+}
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	entries[0].addr = 0;
+	entries[0].size = ISA_START_ADDRESS;
+	entries[0].type = E820_RAM;
+
+	entries[1].addr = ISA_START_ADDRESS;
+	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+	entries[1].type = E820_RESERVED;
+
+	/*
+	 * since we use memalign(malloc) to allocate high memory for
+	 * storing ACPI tables, we need to reserve them in e820 tables,
+	 * otherwise kernel will reclaim them and data will be corrupted
+	 */
+	entries[2].addr = ISA_END_ADDRESS;
+	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+	entries[2].type = E820_RAM;
+
+	/* for simplicity, reserve entire malloc space */
+	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+	entries[3].size = TOTAL_MALLOC_LEN;
+	entries[3].type = E820_RESERVED;
+
+	entries[4].addr = gd->relocaddr;
+	entries[4].size = gd->ram_size - gd->relocaddr;
+	entries[4].type = E820_RESERVED;
+
+	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[5].type = E820_RESERVED;
+
+	return 6;
+}
+
+/* This function loads and patches ACPI tables provided by QEMU */
+u32 write_acpi_tables(u32 addr)
+{
+	int i, ret = 0;
+	struct fw_file *file;
+	struct bios_linker_entry *table_loader;
+	struct bios_linker_entry *entry;
+	uint32_t size;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret) {
+		printf("error: can't read firmware file list\n");
+		return addr;
+	}
+
+	file = qemu_fwcfg_find_file("etc/table-loader");
+	if (!file) {
+		printf("error: can't find etc/table-loader\n");
+		return addr;
+	}
+
+	size = be32_to_cpu(file->cfg.size);
+	if ((size % sizeof(*entry)) != 0) {
+		printf("error: table-loader maybe corrupted\n");
+		return addr;
+	}
+
+	table_loader = malloc(size);
+	if (!table_loader) {
+		printf("error: no memory for table-loader\n");
+		return addr;
+	}
+
+	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+			      size, table_loader);
+
+	for (i = 0; i < (size / sizeof(*entry)); i++) {
+		entry = table_loader + i;
+		switch (le32_to_cpu(entry->command)) {
+		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
+			ret = bios_linker_allocate(entry, &addr);
+			if (ret)
+				goto out;
+			break;
+		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+			ret = bios_linker_add_pointer(entry);
+			if (ret)
+				goto out;
+			break;
+		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+			ret = bios_linker_add_checksum(entry);
+			if (ret)
+				goto out;
+			break;
+		default:
+			break;
+		}
+	}
+
+out:
+	if (ret)
+		qemu_fwcfg_free_files();
+
+	free(table_loader);
+	return addr;
+}
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index a1b70c6..4d2989a 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -8,8 +8,8 @@
 #include <cpu.h>
 #include <dm.h>
 #include <errno.h>
+#include <qemu_fw_cfg.h>
 #include <asm/cpu.h>
-#include <asm/fw_cfg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
deleted file mode 100644
index 2e2794e..0000000
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/fw_cfg.h>
-#include <asm/tables.h>
-#include <asm/e820.h>
-#include <linux/list.h>
-#include <memalign.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-
-static LIST_HEAD(fw_list);
-
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	uint32_t i = 0;
-	uint8_t *data = address;
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
-}
-
-static bool qemu_fwcfg_present(void)
-{
-	uint32_t qemu;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
-}
-
-static bool qemu_fwcfg_dma_present(void)
-{
-	uint8_t dma_enabled;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-	if (dma_enabled & FW_CFG_DMA_ENABLED)
-		return true;
-
-	return false;
-}
-
-static void qemu_fwcfg_read_entry(uint16_t entry,
-		uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
-	char *data_addr;
-	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
-	if (setup_size == 0 || kernel_size == 0) {
-		printf("warning: no kernel available\n");
-		return -1;
-	}
-
-	data_addr = load_addr;
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
-			      le32_to_cpu(setup_size), data_addr);
-	data_addr += le32_to_cpu(setup_size);
-
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
-			      le32_to_cpu(kernel_size), data_addr);
-	data_addr += le32_to_cpu(kernel_size);
-
-	data_addr = initrd_addr;
-	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
-	if (initrd_size == 0) {
-		printf("warning: no initrd available\n");
-	} else {
-		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
-				      le32_to_cpu(initrd_size), data_addr);
-		data_addr += le32_to_cpu(initrd_size);
-	}
-
-	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
-	if (cmdline_size) {
-		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
-				      le32_to_cpu(cmdline_size), data_addr);
-		/*
-		 * if kernel cmdline only contains '\0', (e.g. no -append
-		 * when invoking qemu), do not update bootargs
-		 */
-		if (*data_addr != '\0') {
-			if (setenv("bootargs", data_addr) < 0)
-				printf("warning: unable to change bootargs\n");
-		}
-	}
-
-	printf("loading kernel to address %p size %x", load_addr,
-	       le32_to_cpu(kernel_size));
-	if (initrd_size)
-		printf(" initrd %p size %x\n",
-		       initrd_addr,
-		       le32_to_cpu(initrd_size));
-	else
-		printf("\n");
-
-	return 0;
-}
-
-static int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-#ifdef CONFIG_QEMU_ACPI_TABLE
-static struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- *          (either high memory or low memory)
- * @addr  : The address that should be used for low memory allcation. If the
- *          memory allocation request is 'ZONE_HIGH' then this parameter will
- *          be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
-{
-	uint32_t size, align;
-	struct fw_file *file;
-	unsigned long aligned_addr;
-
-	align = le32_to_cpu(entry->alloc.align);
-	/* align must be power of 2 */
-	if (align & (align - 1)) {
-		printf("error: wrong alignment %u\n", align);
-		return -EINVAL;
-	}
-
-	file = qemu_fwcfg_find_file(entry->alloc.file);
-	if (!file) {
-		printf("error: can't find file %s\n", entry->alloc.file);
-		return -ENOENT;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-
-	/*
-	 * ZONE_HIGH means we need to allocate from high memory, since
-	 * malloc space is already at the end of RAM, so we directly use it.
-	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
-	 * in which is low memory
-	 */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
-		aligned_addr = (unsigned long)memalign(align, size);
-		if (!aligned_addr) {
-			printf("error: allocating resource\n");
-			return -ENOMEM;
-		}
-	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
-		aligned_addr = ALIGN(*addr, align);
-	} else {
-		printf("error: invalid allocation zone\n");
-		return -EINVAL;
-	}
-
-	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
-	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, (void *)aligned_addr);
-	file->addr = aligned_addr;
-
-	/* adjust address for low memory allocation */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
-		*addr = (aligned_addr + size);
-
-	return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- *          ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct bios_linker_entry *entry)
-{
-	struct fw_file *dest, *src;
-	uint32_t offset = le32_to_cpu(entry->pointer.offset);
-	uint64_t pointer = 0;
-
-	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
-	if (!dest || !dest->addr)
-		return -ENOENT;
-	src = qemu_fwcfg_find_file(entry->pointer.src_file);
-	if (!src || !src->addr)
-		return -ENOENT;
-
-	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
-	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
-	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
-	pointer	= le64_to_cpu(pointer);
-	pointer += (unsigned long)src->addr;
-	pointer	= cpu_to_le64(pointer);
-	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
-
-	return 0;
-}
-
-/*
- * This function updates checksum fields of ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells where to update ACPI table
- *          checksums
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_checksum(struct bios_linker_entry *entry)
-{
-	struct fw_file *file;
-	uint8_t *data, cksum = 0;
-	uint8_t *cksum_start;
-
-	file = qemu_fwcfg_find_file(entry->cksum.file);
-	if (!file || !file->addr)
-		return -ENOENT;
-
-	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
-	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
-	cksum = table_compute_checksum(cksum_start,
-				       le32_to_cpu(entry->cksum.length));
-	*data = cksum;
-
-	return 0;
-}
-
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-
-	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
-	 */
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[3].size = TOTAL_MALLOC_LEN;
-	entries[3].type = E820_RESERVED;
-
-	entries[4].addr = gd->relocaddr;
-	entries[4].size = gd->ram_size - gd->relocaddr;
-	entries[4].type = E820_RESERVED;
-
-	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[5].type = E820_RESERVED;
-
-	return 6;
-}
-
-/* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
-{
-	int i, ret = 0;
-	struct fw_file *file;
-	struct bios_linker_entry *table_loader;
-	struct bios_linker_entry *entry;
-	uint32_t size;
-	struct list_head *list;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret) {
-		printf("error: can't read firmware file list\n");
-		return addr;
-	}
-
-	file = qemu_fwcfg_find_file("etc/table-loader");
-	if (!file) {
-		printf("error: can't find etc/table-loader\n");
-		return addr;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-	if ((size % sizeof(*entry)) != 0) {
-		printf("error: table-loader maybe corrupted\n");
-		return addr;
-	}
-
-	table_loader = malloc(size);
-	if (!table_loader) {
-		printf("error: no memory for table-loader\n");
-		return addr;
-	}
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, table_loader);
-
-	for (i = 0; i < (size / sizeof(*entry)); i++) {
-		entry = table_loader + i;
-		switch (le32_to_cpu(entry->command)) {
-		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
-			ret = bios_linker_allocate(entry, &addr);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
-			ret = bios_linker_add_pointer(entry);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
-			ret = bios_linker_add_checksum(entry);
-			if (ret)
-				goto out;
-			break;
-		default:
-			break;
-		}
-	}
-
-out:
-	if (ret) {
-		list_for_each(list, &fw_list) {
-			file = list_entry(list, struct fw_file, list);
-			if (file->addr)
-				free((void *)file->addr);
-		}
-	}
-
-	free(table_loader);
-	return addr;
-}
-#endif
-
-static int qemu_fwcfg_list_firmware(void)
-{
-	int ret;
-	struct list_head *entry;
-	struct fw_file *file;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret)
-		return ret;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		printf("%-56s\n", file->cfg.name);
-	}
-
-	return 0;
-}
-
-void qemu_fwcfg_init(void)
-{
-	fwcfg_present = qemu_fwcfg_present();
-	if (fwcfg_present)
-		fwcfg_dma_present = qemu_fwcfg_dma_present();
-}
-
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	if (qemu_fwcfg_list_firmware() < 0)
-		return CMD_RET_FAILURE;
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	int ret = qemu_fwcfg_online_cpus();
-	if (ret < 0) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_FAILURE;
-	}
-
-	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	char *env;
-	void *load_addr;
-	void *initrd_addr;
-
-	env = getenv("loadaddr");
-	load_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_LOADADDR;
-
-	env = getenv("ramdiskaddr");
-	initrd_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_RAMDISK_ADDR;
-
-	if (argc == 2) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
-	} else if (argc == 1) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-	}
-
-	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
-
-static cmd_tbl_t fwcfg_commands[] = {
-	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
-	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
-	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
-
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int ret;
-	cmd_tbl_t *fwcfg_cmd;
-
-	if (!fwcfg_present) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_USAGE;
-	}
-
-	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
-				 ARRAY_SIZE(fwcfg_commands));
-	argc -= 2;
-	argv += 2;
-	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
-		return CMD_RET_USAGE;
-
-	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
-
-	return cmd_process_error(fwcfg_cmd, ret);
-}
-
-U_BOOT_CMD(
-	qfw,	4,	1,	do_qemu_fw,
-	"QEMU firmware interface",
-	"<command>\n"
-	"    - list                             : print firmware(s) currently loaded\n"
-	"    - cpus                             : print online cpu number\n"
-	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7ad0ee4..b41e4ec 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -6,12 +6,12 @@
 
 #include <common.h>
 #include <pci.h>
+#include <qemu_fw_cfg.h>
 #include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
 #include <asm/arch/qemu.h>
-#include <asm/fw_cfg.h>
 
 static bool i440fx;
 
diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h
deleted file mode 100644
index e9450c6..0000000
--- a/arch/x86/include/asm/fw_cfg.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FW_CFG__
-#define __FW_CFG__
-
-#define FW_CONTROL_PORT	0x510
-#define FW_DATA_PORT		0x511
-#define FW_DMA_PORT_LOW	0x514
-#define FW_DMA_PORT_HIGH	0x518
-
-#include <linux/list.h>
-
-enum qemu_fwcfg_items {
-	FW_CFG_SIGNATURE	= 0x00,
-	FW_CFG_ID		= 0x01,
-	FW_CFG_UUID		= 0x02,
-	FW_CFG_RAM_SIZE		= 0x03,
-	FW_CFG_NOGRAPHIC	= 0x04,
-	FW_CFG_NB_CPUS		= 0x05,
-	FW_CFG_MACHINE_ID	= 0x06,
-	FW_CFG_KERNEL_ADDR	= 0x07,
-	FW_CFG_KERNEL_SIZE	= 0x08,
-	FW_CFG_KERNEL_CMDLINE   = 0x09,
-	FW_CFG_INITRD_ADDR	= 0x0a,
-	FW_CFG_INITRD_SIZE	= 0x0b,
-	FW_CFG_BOOT_DEVICE	= 0x0c,
-	FW_CFG_NUMA		= 0x0d,
-	FW_CFG_BOOT_MENU	= 0x0e,
-	FW_CFG_MAX_CPUS		= 0x0f,
-	FW_CFG_KERNEL_ENTRY	= 0x10,
-	FW_CFG_KERNEL_DATA	= 0x11,
-	FW_CFG_INITRD_DATA	= 0x12,
-	FW_CFG_CMDLINE_ADDR	= 0x13,
-	FW_CFG_CMDLINE_SIZE	= 0x14,
-	FW_CFG_CMDLINE_DATA	= 0x15,
-	FW_CFG_SETUP_ADDR	= 0x16,
-	FW_CFG_SETUP_SIZE	= 0x17,
-	FW_CFG_SETUP_DATA	= 0x18,
-	FW_CFG_FILE_DIR		= 0x19,
-	FW_CFG_FILE_FIRST	= 0x20,
-	FW_CFG_WRITE_CHANNEL	= 0x4000,
-	FW_CFG_ARCH_LOCAL	= 0x8000,
-	FW_CFG_INVALID		= 0xffff,
-};
-
-enum {
-	BIOS_LINKER_LOADER_COMMAND_ALLOCATE	= 0x1,
-	BIOS_LINKER_LOADER_COMMAND_ADD_POINTER  = 0x2,
-	BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
-};
-
-enum {
-	BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
-	BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
-};
-
-#define FW_CFG_FILE_SLOTS	0x10
-#define FW_CFG_MAX_ENTRY	(FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
-#define FW_CFG_ENTRY_MASK	 ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
-
-#define FW_CFG_MAX_FILE_PATH	56
-#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
-
-#define QEMU_FW_CFG_SIGNATURE	(('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
-
-#define FW_CFG_DMA_ERROR	(1 << 0)
-#define FW_CFG_DMA_READ	(1 << 1)
-#define FW_CFG_DMA_SKIP	(1 << 2)
-#define FW_CFG_DMA_SELECT	(1 << 3)
-
-#define FW_CFG_DMA_ENABLED	(1 << 1)
-
-struct fw_cfg_file {
-	__be32 size;
-	__be16 select;
-	__be16 reserved;
-	char name[FW_CFG_MAX_FILE_PATH];
-};
-
-struct fw_file {
-	struct fw_cfg_file cfg; /* firmware file information */
-	unsigned long addr;     /* firmware file in-memory address */
-	struct list_head list;  /* list node to link to fw_list */
-};
-
-struct fw_cfg_dma_access {
-	__be32 control;
-	__be32 length;
-	__be64 address;
-};
-
-struct bios_linker_entry {
-	__le32 command;
-	union {
-		/*
-		 * COMMAND_ALLOCATE - allocate a table from @alloc.file
-		 * subject to @alloc.align alignment (must be power of 2)
-		 * and @alloc.zone (can be HIGH or FSEG) requirements.
-		 *
-		 * Must appear exactly once for each file, and before
-		 * this file is referenced by any other command.
-		 */
-		struct {
-			char file[BIOS_LINKER_LOADER_FILESZ];
-			__le32 align;
-			uint8_t zone;
-		} alloc;
-
-		/*
-		 * COMMAND_ADD_POINTER - patch the table (originating from
-		 * @dest_file) at @pointer.offset, by adding a pointer to the
-		 * table originating from @src_file. 1,2,4 or 8 byte unsigned
-		 * addition is used depending on @pointer.size.
-		 */
-		struct {
-			char dest_file[BIOS_LINKER_LOADER_FILESZ];
-			char src_file[BIOS_LINKER_LOADER_FILESZ];
-			__le32 offset;
-			uint8_t size;
-		} pointer;
-
-		/*
-		 * COMMAND_ADD_CHECKSUM - calculate checksum of the range
-		 * specified by @cksum_start and @cksum_length fields,
-		 * and then add the value at @cksum.offset.
-		 * Checksum simply sums -X for each byte X in the range
-		 * using 8-bit math.
-		 */
-		struct {
-			char file[BIOS_LINKER_LOADER_FILESZ];
-			__le32 offset;
-			__le32 start;
-			__le32 length;
-		} cksum;
-
-		/* padding */
-		char pad[124];
-	};
-} __packed;
-
-/**
- * Initialize QEMU fw_cfg interface
- */
-void qemu_fwcfg_init(void);
-
-/**
- * Get system cpu number
- *
- * @return:   cpu number in system
- */
-int qemu_fwcfg_online_cpus(void);
-
-#endif
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 989cf7d..be7b824 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -303,7 +303,7 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 
 /*
  * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/fw_cfg.c
+ * arch/x86/cpu/qemu/acpi_table.c
  */
 u32 write_acpi_tables(u32 start)
 {
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9336752..c0fffe3 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -593,6 +593,13 @@ config CMD_SOUND
 	     sound init   - set up sound system
 	     sound play   - play a sound
 
+config CMD_QEMU_FW_CFG
+	bool "qfw"
+	depends on X86
+	help
+	  This provides access to the QEMU firmware interface.  The main
+	  feature is to allow easy loading of files passed to qemu-system
+	  via -kernel / -initrd
 endmenu
 
 config CMD_BOOTSTAGE
diff --git a/cmd/Makefile b/cmd/Makefile
index e3e0c74..d4432c8 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,6 +105,7 @@ endif
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PORTIO) += portio.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_QEMU_FW_CFG) += qemu_fw_cfg.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c
new file mode 100644
index 0000000..48ae476
--- /dev/null
+++ b/cmd/qemu_fw_cfg.c
@@ -0,0 +1,343 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <qemu_fw_cfg.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+
+static LIST_HEAD(fw_list);
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(entry, FW_CONTROL_PORT);
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+		uint32_t size, void *address)
+{
+	struct fw_cfg_dma_access dma;
+
+	dma.length = cpu_to_be32(size);
+	dma.address = cpu_to_be64((uintptr_t)address);
+	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+	barrier();
+
+	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
+	      address, size, be32_to_cpu(dma.control));
+
+	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+static bool qemu_fwcfg_present(void)
+{
+	uint32_t qemu;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
+}
+
+static bool qemu_fwcfg_dma_present(void)
+{
+	uint8_t dma_enabled;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+	if (dma_enabled & FW_CFG_DMA_ENABLED)
+		return true;
+
+	return false;
+}
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+	if (fwcfg_dma_present)
+		qemu_fwcfg_read_entry_dma(entry, length, address);
+	else
+		qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+	uint16_t nb_cpus;
+
+	if (!fwcfg_present)
+		return -ENODEV;
+
+	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+	return le16_to_cpu(nb_cpus);
+}
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+	char *data_addr;
+	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+	if (setup_size == 0 || kernel_size == 0) {
+		printf("warning: no kernel available\n");
+		return -1;
+	}
+
+	data_addr = load_addr;
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+			      le32_to_cpu(setup_size), data_addr);
+	data_addr += le32_to_cpu(setup_size);
+
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+			      le32_to_cpu(kernel_size), data_addr);
+	data_addr += le32_to_cpu(kernel_size);
+
+	data_addr = initrd_addr;
+	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+	if (initrd_size == 0) {
+		printf("warning: no initrd available\n");
+	} else {
+		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+				      le32_to_cpu(initrd_size), data_addr);
+		data_addr += le32_to_cpu(initrd_size);
+	}
+
+	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+	if (cmdline_size) {
+		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+				      le32_to_cpu(cmdline_size), data_addr);
+		/*
+		 * if kernel cmdline only contains '\0', (e.g. no -append
+		 * when invoking qemu), do not update bootargs
+		 */
+		if (*data_addr != '\0') {
+			if (setenv("bootargs", data_addr) < 0)
+				printf("warning: unable to change bootargs\n");
+		}
+	}
+
+	printf("loading kernel to address %p size %x", load_addr,
+	       le32_to_cpu(kernel_size));
+	if (initrd_size)
+		printf(" initrd %p size %x\n",
+		       initrd_addr,
+		       le32_to_cpu(initrd_size));
+	else
+		printf("\n");
+
+	return 0;
+}
+
+int qemu_fwcfg_read_firmware_list(void)
+{
+	int i;
+	uint32_t count;
+	struct fw_file *file;
+	struct list_head *entry;
+
+	/* don't read it twice */
+	if (!list_empty(&fw_list))
+		return 0;
+
+	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+	if (!count)
+		return 0;
+
+	count = be32_to_cpu(count);
+	for (i = 0; i < count; i++) {
+		file = malloc(sizeof(*file));
+		if (!file) {
+			printf("error: allocating resource\n");
+			goto err;
+		}
+		qemu_fwcfg_read_entry(FW_CFG_INVALID,
+				      sizeof(struct fw_cfg_file), &file->cfg);
+		file->addr = 0;
+		list_add_tail(&file->list, &fw_list);
+	}
+
+	return 0;
+
+err:
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		free(file);
+	}
+
+	return -ENOMEM;
+}
+
+struct fw_file *qemu_fwcfg_find_file(const char *name)
+{
+	struct list_head *entry;
+	struct fw_file *file;
+
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		if (!strcmp(file->cfg.name, name))
+			return file;
+	}
+
+	return NULL;
+}
+
+void qemu_fwcfg_free_files(void)
+{
+	struct fw_file *file;
+	struct list_head *list;
+
+	list_for_each(list, &fw_list) {
+		file = list_entry(list, struct fw_file, list);
+		if (file->addr)
+			free((void *)file->addr);
+	}
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+	int ret;
+	struct list_head *entry;
+	struct fw_file *file;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret)
+		return ret;
+
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		printf("%-56s\n", file->cfg.name);
+	}
+
+	return 0;
+}
+
+void qemu_fwcfg_init(void)
+{
+	fwcfg_present = qemu_fwcfg_present();
+	if (fwcfg_present)
+		fwcfg_dma_present = qemu_fwcfg_dma_present();
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (qemu_fwcfg_list_firmware() < 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	int ret = qemu_fwcfg_online_cpus();
+	if (ret < 0) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	char *env;
+	void *load_addr;
+	void *initrd_addr;
+
+	env = getenv("loadaddr");
+	load_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+		(void *)CONFIG_LOADADDR;
+
+	env = getenv("ramdiskaddr");
+	initrd_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+		(void *)CONFIG_RAMDISK_ADDR;
+
+	if (argc == 2) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	} else if (argc == 1) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	}
+
+	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret;
+	cmd_tbl_t *fwcfg_cmd;
+
+	if (!fwcfg_present) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_USAGE;
+	}
+
+	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+				 ARRAY_SIZE(fwcfg_commands));
+	argc -= 2;
+	argv += 2;
+	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+	return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+	qfw,	4,	1,	do_qemu_fw,
+	"QEMU firmware interface",
+	"<command>\n"
+	"    - list                             : print firmware(s) currently loaded\n"
+	"    - cpus                             : print online cpu number\n"
+	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 53b1ff6..a813e5b 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_QEMU_FW_CFG=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h
new file mode 100644
index 0000000..e21f150
--- /dev/null
+++ b/include/qemu_fw_cfg.h
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#define FW_CONTROL_PORT	0x510
+#define FW_DATA_PORT		0x511
+#define FW_DMA_PORT_LOW	0x514
+#define FW_DMA_PORT_HIGH	0x518
+
+#include <linux/list.h>
+
+enum qemu_fwcfg_items {
+	FW_CFG_SIGNATURE	= 0x00,
+	FW_CFG_ID		= 0x01,
+	FW_CFG_UUID		= 0x02,
+	FW_CFG_RAM_SIZE		= 0x03,
+	FW_CFG_NOGRAPHIC	= 0x04,
+	FW_CFG_NB_CPUS		= 0x05,
+	FW_CFG_MACHINE_ID	= 0x06,
+	FW_CFG_KERNEL_ADDR	= 0x07,
+	FW_CFG_KERNEL_SIZE	= 0x08,
+	FW_CFG_KERNEL_CMDLINE   = 0x09,
+	FW_CFG_INITRD_ADDR	= 0x0a,
+	FW_CFG_INITRD_SIZE	= 0x0b,
+	FW_CFG_BOOT_DEVICE	= 0x0c,
+	FW_CFG_NUMA		= 0x0d,
+	FW_CFG_BOOT_MENU	= 0x0e,
+	FW_CFG_MAX_CPUS		= 0x0f,
+	FW_CFG_KERNEL_ENTRY	= 0x10,
+	FW_CFG_KERNEL_DATA	= 0x11,
+	FW_CFG_INITRD_DATA	= 0x12,
+	FW_CFG_CMDLINE_ADDR	= 0x13,
+	FW_CFG_CMDLINE_SIZE	= 0x14,
+	FW_CFG_CMDLINE_DATA	= 0x15,
+	FW_CFG_SETUP_ADDR	= 0x16,
+	FW_CFG_SETUP_SIZE	= 0x17,
+	FW_CFG_SETUP_DATA	= 0x18,
+	FW_CFG_FILE_DIR		= 0x19,
+	FW_CFG_FILE_FIRST	= 0x20,
+	FW_CFG_WRITE_CHANNEL	= 0x4000,
+	FW_CFG_ARCH_LOCAL	= 0x8000,
+	FW_CFG_INVALID		= 0xffff,
+};
+
+enum {
+	BIOS_LINKER_LOADER_COMMAND_ALLOCATE	= 0x1,
+	BIOS_LINKER_LOADER_COMMAND_ADD_POINTER  = 0x2,
+	BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+	BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+	BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+#define FW_CFG_FILE_SLOTS	0x10
+#define FW_CFG_MAX_ENTRY	(FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK	 ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH	56
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+#define QEMU_FW_CFG_SIGNATURE	(('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR	(1 << 0)
+#define FW_CFG_DMA_READ	(1 << 1)
+#define FW_CFG_DMA_SKIP	(1 << 2)
+#define FW_CFG_DMA_SELECT	(1 << 3)
+
+#define FW_CFG_DMA_ENABLED	(1 << 1)
+
+struct fw_cfg_file {
+	__be32 size;
+	__be16 select;
+	__be16 reserved;
+	char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_file {
+	struct fw_cfg_file cfg; /* firmware file information */
+	unsigned long addr;     /* firmware file in-memory address */
+	struct list_head list;  /* list node to link to fw_list */
+};
+
+struct fw_cfg_dma_access {
+	__be32 control;
+	__be32 length;
+	__be64 address;
+};
+
+struct bios_linker_entry {
+	__le32 command;
+	union {
+		/*
+		 * COMMAND_ALLOCATE - allocate a table from @alloc.file
+		 * subject to @alloc.align alignment (must be power of 2)
+		 * and @alloc.zone (can be HIGH or FSEG) requirements.
+		 *
+		 * Must appear exactly once for each file, and before
+		 * this file is referenced by any other command.
+		 */
+		struct {
+			char file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 align;
+			uint8_t zone;
+		} alloc;
+
+		/*
+		 * COMMAND_ADD_POINTER - patch the table (originating from
+		 * @dest_file) at @pointer.offset, by adding a pointer to the
+		 * table originating from @src_file. 1,2,4 or 8 byte unsigned
+		 * addition is used depending on @pointer.size.
+		 */
+		struct {
+			char dest_file[BIOS_LINKER_LOADER_FILESZ];
+			char src_file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 offset;
+			uint8_t size;
+		} pointer;
+
+		/*
+		 * COMMAND_ADD_CHECKSUM - calculate checksum of the range
+		 * specified by @cksum_start and @cksum_length fields,
+		 * and then add the value at @cksum.offset.
+		 * Checksum simply sums -X for each byte X in the range
+		 * using 8-bit math.
+		 */
+		struct {
+			char file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 offset;
+			__le32 start;
+			__le32 length;
+		} cksum;
+
+		/* padding */
+		char pad[124];
+	};
+} __packed;
+
+/**
+ * Initialize QEMU fw_cfg interface
+ */
+void qemu_fwcfg_init(void);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
+void qemu_fwcfg_free_files(void);
+
+/**
+ * Get system cpu number
+ *
+ * @return:   cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+#endif
-- 
cgit v0.10.2


From 34865a65c44d9c0dffb9b5346e66ea9b7757b880 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:10 -0700
Subject: x86: qemu: fix ACPI Kconfig options

CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI table from QEMU's fw_cfg interface.

But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop
our own ACPI implementation", there is only one way to support ACPI table
for QEMU targets which is the fw_cfg interface. Having two Kconfig options
for this purpose is not necessary any more, so this patch consolidates
the two.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 396023e..5a1e7a5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -439,21 +439,13 @@ config GENERATE_MP_TABLE
 config GENERATE_ACPI_TABLE
 	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 	default n
+	select CMD_QEMU_FW_CFG if QEMU
 	help
 	  The Advanced Configuration and Power Interface (ACPI) specification
 	  provides an open standard for device configuration and management
 	  by the operating system. It defines platform-independent interfaces
 	  for configuration and power management monitoring.
 
-config QEMU_ACPI_TABLE
-	bool "Load ACPI table from QEMU fw_cfg interface"
-	depends on GENERATE_ACPI_TABLE && QEMU
-	default y
-	help
-	  By default, U-Boot generates its own ACPI tables. This option, if
-	  enabled, disables U-Boot's version and loads ACPI tables generated
-	  by QEMU.
-
 config GENERATE_SMBIOS_TABLE
 	bool "Generate an SMBIOS (System Management BIOS) table"
 	default y
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 97b965c..43ee4bd 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -8,4 +8,4 @@ ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
 obj-y += cpu.o qemu.o
-obj-$(CONFIG_QEMU_ACPI_TABLE) += acpi_table.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index dc90df2..ce5eb82 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o
 obj-y += sfi.o
 obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
 obj-y	+= string.o
-ifndef CONFIG_QEMU_ACPI_TABLE
+ifndef CONFIG_QEMU
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o
-- 
cgit v0.10.2


From 099b2196e4a693968fd6205ac6d61f6eaab79fb1 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:11 -0700
Subject: cmd: qfw: add API to iterate firmware list

This patch is part of the refactor work of qfw. It adds 3 APIs to qfw
core to iterate firmware list.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c
index 48ae476..192b7d1 100644
--- a/cmd/qemu_fw_cfg.c
+++ b/cmd/qemu_fw_cfg.c
@@ -229,10 +229,27 @@ void qemu_fwcfg_free_files(void)
 	}
 }
 
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = fw_list.next;
+	return list_entry(iter->entry, struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = iter->entry->next;
+	return list_entry(iter->entry, struct fw_file, list);
+}
+
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+	return iter->entry == &fw_list;
+}
+
 static int qemu_fwcfg_list_firmware(void)
 {
 	int ret;
-	struct list_head *entry;
+	struct fw_cfg_file_iter iter;
 	struct fw_file *file;
 
 	/* make sure fw_list is loaded */
@@ -240,8 +257,10 @@ static int qemu_fwcfg_list_firmware(void)
 	if (ret)
 		return ret;
 
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
+
+	for (file = qemu_fwcfg_file_iter_init(&iter);
+	     !qemu_fwcfg_file_iter_end(&iter);
+	     file = qemu_fwcfg_file_iter_next(&iter)) {
 		printf("%-56s\n", file->cfg.name);
 	}
 
diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h
index e21f150..19d0ba0 100644
--- a/include/qemu_fw_cfg.h
+++ b/include/qemu_fw_cfg.h
@@ -87,6 +87,10 @@ struct fw_file {
 	struct list_head list;  /* list node to link to fw_list */
 };
 
+struct fw_cfg_file_iter {
+	struct list_head *entry; /* structure to iterate file list */
+};
+
 struct fw_cfg_dma_access {
 	__be32 control;
 	__be32 length;
@@ -159,4 +163,9 @@ void qemu_fwcfg_free_files(void);
  */
 int qemu_fwcfg_online_cpus(void);
 
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
 #endif
-- 
cgit v0.10.2


From 05dd6f183c8c20f0176a67ac885f8143c0052203 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:12 -0700
Subject: cmd: qfw: remove qemu_fwcfg_free_files()

This patch is part of the qfw refactor work.

The qemu_fwcfg_free_files() function is only used in error handling in
ACPI table generation, let's not make this a core function and move it
to the right place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c
index 49381ac..b17fa03 100644
--- a/arch/x86/cpu/qemu/acpi_table.c
+++ b/arch/x86/cpu/qemu/acpi_table.c
@@ -235,8 +235,17 @@ u32 write_acpi_tables(u32 addr)
 	}
 
 out:
-	if (ret)
-		qemu_fwcfg_free_files();
+	if (ret) {
+		struct fw_cfg_file_iter iter;
+		for (file = qemu_fwcfg_file_iter_init(&iter);
+		     !qemu_fwcfg_file_iter_end(&iter);
+		     file = qemu_fwcfg_file_iter_next(&iter)) {
+			if (file->addr) {
+				free((void *)file->addr);
+				file->addr = 0;
+			}
+		}
+	}
 
 	free(table_loader);
 	return addr;
diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c
index 192b7d1..9f03ab6 100644
--- a/cmd/qemu_fw_cfg.c
+++ b/cmd/qemu_fw_cfg.c
@@ -217,18 +217,6 @@ struct fw_file *qemu_fwcfg_find_file(const char *name)
 	return NULL;
 }
 
-void qemu_fwcfg_free_files(void)
-{
-	struct fw_file *file;
-	struct list_head *list;
-
-	list_for_each(list, &fw_list) {
-		file = list_entry(list, struct fw_file, list);
-		if (file->addr)
-			free((void *)file->addr);
-	}
-}
-
 struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
 {
 	iter->entry = fw_list.next;
diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h
index 19d0ba0..986f4b2 100644
--- a/include/qemu_fw_cfg.h
+++ b/include/qemu_fw_cfg.h
@@ -154,7 +154,6 @@ void qemu_fwcfg_init(void);
 void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
 int qemu_fwcfg_read_firmware_list(void);
 struct fw_file *qemu_fwcfg_find_file(const char *name);
-void qemu_fwcfg_free_files(void);
 
 /**
  * Get system cpu number
-- 
cgit v0.10.2


From d3ad06239291d89c1c598248d577cde5470ac1ee Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:13 -0700
Subject: cmd: qfw: make fwcfg_present and fwcfg_dma_present public

This patch is part of the qfw refactor work. This patch makes
qemu_fwcfg_present() and qemu_fwcfg_dma_present() public functions.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c
index 9f03ab6..aab6b1a 100644
--- a/cmd/qemu_fw_cfg.c
+++ b/cmd/qemu_fw_cfg.c
@@ -62,23 +62,14 @@ static void qemu_fwcfg_read_entry_dma(uint16_t entry,
 		__asm__ __volatile__ ("pause");
 }
 
-static bool qemu_fwcfg_present(void)
+bool qemu_fwcfg_present(void)
 {
-	uint32_t qemu;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
+	return fwcfg_present;
 }
 
-static bool qemu_fwcfg_dma_present(void)
+bool qemu_fwcfg_dma_present(void)
 {
-	uint8_t dma_enabled;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-	if (dma_enabled & FW_CFG_DMA_ENABLED)
-		return true;
-
-	return false;
+	return fwcfg_dma_present;
 }
 
 void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
@@ -257,9 +248,21 @@ static int qemu_fwcfg_list_firmware(void)
 
 void qemu_fwcfg_init(void)
 {
-	fwcfg_present = qemu_fwcfg_present();
-	if (fwcfg_present)
-		fwcfg_dma_present = qemu_fwcfg_dma_present();
+	uint32_t qemu;
+	uint32_t dma_enabled;
+
+	fwcfg_present = false;
+	fwcfg_dma_present = false;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+		fwcfg_present = true;
+
+	if (fwcfg_present) {
+		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+		if (dma_enabled & FW_CFG_DMA_ENABLED)
+			fwcfg_dma_present = true;
+	}
 }
 
 static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
@@ -323,7 +326,7 @@ static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	int ret;
 	cmd_tbl_t *fwcfg_cmd;
 
-	if (!fwcfg_present) {
+	if (!qemu_fwcfg_present()) {
 		printf("QEMU fw_cfg interface not found\n");
 		return CMD_RET_USAGE;
 	}
diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h
index 986f4b2..f718e09 100644
--- a/include/qemu_fw_cfg.h
+++ b/include/qemu_fw_cfg.h
@@ -167,4 +167,7 @@ struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
 struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
 bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
 
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
 #endif
-- 
cgit v0.10.2


From fcf5c04193b48c3f5e2d337a85d28c4026f90ac3 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:14 -0700
Subject: x86: qemu: split qfw command interface and qfw core

This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.

Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5a1e7a5..9d0f502 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -439,7 +439,7 @@ config GENERATE_MP_TABLE
 config GENERATE_ACPI_TABLE
 	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 	default n
-	select CMD_QEMU_FW_CFG if QEMU
+	select QFW if QEMU
 	help
 	  The Advanced Configuration and Power Interface (ACPI) specification
 	  provides an open standard for device configuration and management
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 13bec7a..c44a286 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -420,7 +420,7 @@ static int init_bsp(struct udevice **devp)
 	return 0;
 }
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 static int qemu_cpu_fixup(void)
 {
 	int ret;
@@ -496,7 +496,7 @@ int mp_init(struct mp_params *p)
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 	ret = qemu_cpu_fixup();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 43ee4bd..7c08c3d 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,5 +7,6 @@
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
-obj-y += cpu.o qemu.o
+obj-y += qemu.o
+obj-$(CONFIG_QFW) += cpu.o
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index b41e4ec..32a4351 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -88,7 +88,9 @@ static void qemu_chipset_init(void)
 		enable_pm_ich9();
 	}
 
+#ifdef CONFIG_QFW
 	qemu_fwcfg_init();
+#endif
 }
 
 int arch_cpu_init(void)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index c0fffe3..08b761f 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -596,6 +596,7 @@ config CMD_SOUND
 config CMD_QEMU_FW_CFG
 	bool "qfw"
 	depends on X86
+	select QFW
 	help
 	  This provides access to the QEMU firmware interface.  The main
 	  feature is to allow easy loading of files passed to qemu-system
diff --git a/cmd/Makefile b/cmd/Makefile
index d4432c8..ff4fc5b 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,7 +105,7 @@ endif
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PORTIO) += portio.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
-obj-$(CONFIG_CMD_QEMU_FW_CFG) += qemu_fw_cfg.o
+obj-$(CONFIG_CMD_QEMU_FW_CFG) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
diff --git a/cmd/qemu_fw_cfg.c b/cmd/qemu_fw_cfg.c
deleted file mode 100644
index aab6b1a..0000000
--- a/cmd/qemu_fw_cfg.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <qemu_fw_cfg.h>
-#include <asm/io.h>
-#include <linux/list.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-
-static LIST_HEAD(fw_list);
-
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	uint32_t i = 0;
-	uint8_t *data = address;
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
-}
-
-bool qemu_fwcfg_present(void)
-{
-	return fwcfg_present;
-}
-
-bool qemu_fwcfg_dma_present(void)
-{
-	return fwcfg_dma_present;
-}
-
-void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
-	char *data_addr;
-	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
-	if (setup_size == 0 || kernel_size == 0) {
-		printf("warning: no kernel available\n");
-		return -1;
-	}
-
-	data_addr = load_addr;
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
-			      le32_to_cpu(setup_size), data_addr);
-	data_addr += le32_to_cpu(setup_size);
-
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
-			      le32_to_cpu(kernel_size), data_addr);
-	data_addr += le32_to_cpu(kernel_size);
-
-	data_addr = initrd_addr;
-	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
-	if (initrd_size == 0) {
-		printf("warning: no initrd available\n");
-	} else {
-		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
-				      le32_to_cpu(initrd_size), data_addr);
-		data_addr += le32_to_cpu(initrd_size);
-	}
-
-	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
-	if (cmdline_size) {
-		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
-				      le32_to_cpu(cmdline_size), data_addr);
-		/*
-		 * if kernel cmdline only contains '\0', (e.g. no -append
-		 * when invoking qemu), do not update bootargs
-		 */
-		if (*data_addr != '\0') {
-			if (setenv("bootargs", data_addr) < 0)
-				printf("warning: unable to change bootargs\n");
-		}
-	}
-
-	printf("loading kernel to address %p size %x", load_addr,
-	       le32_to_cpu(kernel_size));
-	if (initrd_size)
-		printf(" initrd %p size %x\n",
-		       initrd_addr,
-		       le32_to_cpu(initrd_size));
-	else
-		printf("\n");
-
-	return 0;
-}
-
-int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
-struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
-{
-	iter->entry = fw_list.next;
-	return list_entry(iter->entry, struct fw_file, list);
-}
-
-struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
-{
-	iter->entry = iter->entry->next;
-	return list_entry(iter->entry, struct fw_file, list);
-}
-
-bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
-{
-	return iter->entry == &fw_list;
-}
-
-static int qemu_fwcfg_list_firmware(void)
-{
-	int ret;
-	struct fw_cfg_file_iter iter;
-	struct fw_file *file;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret)
-		return ret;
-
-
-	for (file = qemu_fwcfg_file_iter_init(&iter);
-	     !qemu_fwcfg_file_iter_end(&iter);
-	     file = qemu_fwcfg_file_iter_next(&iter)) {
-		printf("%-56s\n", file->cfg.name);
-	}
-
-	return 0;
-}
-
-void qemu_fwcfg_init(void)
-{
-	uint32_t qemu;
-	uint32_t dma_enabled;
-
-	fwcfg_present = false;
-	fwcfg_dma_present = false;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
-		fwcfg_present = true;
-
-	if (fwcfg_present) {
-		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-		if (dma_enabled & FW_CFG_DMA_ENABLED)
-			fwcfg_dma_present = true;
-	}
-}
-
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	if (qemu_fwcfg_list_firmware() < 0)
-		return CMD_RET_FAILURE;
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	int ret = qemu_fwcfg_online_cpus();
-	if (ret < 0) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_FAILURE;
-	}
-
-	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
-
-	return 0;
-}
-
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
-{
-	char *env;
-	void *load_addr;
-	void *initrd_addr;
-
-	env = getenv("loadaddr");
-	load_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_LOADADDR;
-
-	env = getenv("ramdiskaddr");
-	initrd_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_RAMDISK_ADDR;
-
-	if (argc == 2) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
-	} else if (argc == 1) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-	}
-
-	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
-
-static cmd_tbl_t fwcfg_commands[] = {
-	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
-	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
-	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
-
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int ret;
-	cmd_tbl_t *fwcfg_cmd;
-
-	if (!qemu_fwcfg_present()) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_USAGE;
-	}
-
-	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
-				 ARRAY_SIZE(fwcfg_commands));
-	argc -= 2;
-	argv += 2;
-	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
-		return CMD_RET_USAGE;
-
-	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
-
-	return cmd_process_error(fwcfg_cmd, ret);
-}
-
-U_BOOT_CMD(
-	qfw,	4,	1,	do_qemu_fw,
-	"QEMU firmware interface",
-	"<command>\n"
-	"    - list                             : print firmware(s) currently loaded\n"
-	"    - cpus                             : print online cpu number\n"
-	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
diff --git a/cmd/qfw.c b/cmd/qfw.c
new file mode 100644
index 0000000..37f1aa6
--- /dev/null
+++ b/cmd/qfw.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <qemu_fw_cfg.h>
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+	char *data_addr;
+	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+	if (setup_size == 0 || kernel_size == 0) {
+		printf("warning: no kernel available\n");
+		return -1;
+	}
+
+	data_addr = load_addr;
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+			      le32_to_cpu(setup_size), data_addr);
+	data_addr += le32_to_cpu(setup_size);
+
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+			      le32_to_cpu(kernel_size), data_addr);
+	data_addr += le32_to_cpu(kernel_size);
+
+	data_addr = initrd_addr;
+	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+	if (initrd_size == 0) {
+		printf("warning: no initrd available\n");
+	} else {
+		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+				      le32_to_cpu(initrd_size), data_addr);
+		data_addr += le32_to_cpu(initrd_size);
+	}
+
+	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+	if (cmdline_size) {
+		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+				      le32_to_cpu(cmdline_size), data_addr);
+		/*
+		 * if kernel cmdline only contains '\0', (e.g. no -append
+		 * when invoking qemu), do not update bootargs
+		 */
+		if (*data_addr != '\0') {
+			if (setenv("bootargs", data_addr) < 0)
+				printf("warning: unable to change bootargs\n");
+		}
+	}
+
+	printf("loading kernel to address %p size %x", load_addr,
+	       le32_to_cpu(kernel_size));
+	if (initrd_size)
+		printf(" initrd %p size %x\n",
+		       initrd_addr,
+		       le32_to_cpu(initrd_size));
+	else
+		printf("\n");
+
+	return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+	int ret;
+	struct fw_cfg_file_iter iter;
+	struct fw_file *file;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret)
+		return ret;
+
+
+	for (file = qemu_fwcfg_file_iter_init(&iter);
+	     !qemu_fwcfg_file_iter_end(&iter);
+	     file = qemu_fwcfg_file_iter_next(&iter)) {
+		printf("%-56s\n", file->cfg.name);
+	}
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (qemu_fwcfg_list_firmware() < 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	int ret = qemu_fwcfg_online_cpus();
+	if (ret < 0) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	char *env;
+	void *load_addr;
+	void *initrd_addr;
+
+	env = getenv("loadaddr");
+	load_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+		(void *)CONFIG_LOADADDR;
+
+	env = getenv("ramdiskaddr");
+	initrd_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+		(void *)CONFIG_RAMDISK_ADDR;
+
+	if (argc == 2) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	} else if (argc == 1) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	}
+
+	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret;
+	cmd_tbl_t *fwcfg_cmd;
+
+	if (!qemu_fwcfg_present()) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_USAGE;
+	}
+
+	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+				 ARRAY_SIZE(fwcfg_commands));
+	argc -= 2;
+	argv += 2;
+	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+	return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+	qfw,	4,	1,	do_qemu_fw,
+	"QEMU firmware interface",
+	"<command>\n"
+	"    - list                             : print firmware(s) currently loaded\n"
+	"    - cpus                             : print online cpu number\n"
+	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index af8667f..fa53700 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -138,4 +138,10 @@ config WINBOND_W83627
 	  legacy UART or other devices in the Winbond Super IO chips
 	  on X86 platforms.
 
+config QFW
+	bool
+	help
+	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
+	  either CONFIG_CMD_QEMU_FW_CFG or CONFIG_GENERATE_ACPI_TABLE.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5969d34..4893086 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_RESET) += reset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_QFW) += qemu_fw_cfg.o
diff --git a/drivers/misc/qemu_fw_cfg.c b/drivers/misc/qemu_fw_cfg.c
new file mode 100644
index 0000000..a574bd1
--- /dev/null
+++ b/drivers/misc/qemu_fw_cfg.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <qemu_fw_cfg.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+
+static LIST_HEAD(fw_list);
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(entry, FW_CONTROL_PORT);
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+		uint32_t size, void *address)
+{
+	struct fw_cfg_dma_access dma;
+
+	dma.length = cpu_to_be32(size);
+	dma.address = cpu_to_be64((uintptr_t)address);
+	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+	barrier();
+
+	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
+	      address, size, be32_to_cpu(dma.control));
+
+	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+bool qemu_fwcfg_present(void)
+{
+	return fwcfg_present;
+}
+
+bool qemu_fwcfg_dma_present(void)
+{
+	return fwcfg_dma_present;
+}
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+	if (fwcfg_dma_present)
+		qemu_fwcfg_read_entry_dma(entry, length, address);
+	else
+		qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+	uint16_t nb_cpus;
+
+	if (!fwcfg_present)
+		return -ENODEV;
+
+	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+	return le16_to_cpu(nb_cpus);
+}
+
+int qemu_fwcfg_read_firmware_list(void)
+{
+	int i;
+	uint32_t count;
+	struct fw_file *file;
+	struct list_head *entry;
+
+	/* don't read it twice */
+	if (!list_empty(&fw_list))
+		return 0;
+
+	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+	if (!count)
+		return 0;
+
+	count = be32_to_cpu(count);
+	for (i = 0; i < count; i++) {
+		file = malloc(sizeof(*file));
+		if (!file) {
+			printf("error: allocating resource\n");
+			goto err;
+		}
+		qemu_fwcfg_read_entry(FW_CFG_INVALID,
+				      sizeof(struct fw_cfg_file), &file->cfg);
+		file->addr = 0;
+		list_add_tail(&file->list, &fw_list);
+	}
+
+	return 0;
+
+err:
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		free(file);
+	}
+
+	return -ENOMEM;
+}
+
+struct fw_file *qemu_fwcfg_find_file(const char *name)
+{
+	struct list_head *entry;
+	struct fw_file *file;
+
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		if (!strcmp(file->cfg.name, name))
+			return file;
+	}
+
+	return NULL;
+}
+
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = fw_list.next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = ((struct list_head *)iter->entry)->next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+	return iter->entry == &fw_list;
+}
+
+void qemu_fwcfg_init(void)
+{
+	uint32_t qemu;
+	uint32_t dma_enabled;
+
+	fwcfg_present = false;
+	fwcfg_dma_present = false;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+		fwcfg_present = true;
+
+	if (fwcfg_present) {
+		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+		if (dma_enabled & FW_CFG_DMA_ENABLED)
+			fwcfg_dma_present = true;
+	}
+}
-- 
cgit v0.10.2


From 2e82e745a4cf6bad10d9fe5a53db6592f40ff903 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:15 -0700
Subject: x86: qemu: move x86 specific operations out of qfw core

The original implementation of qfw includes several x86 specific
operations, like directly calling outb/inb and using some inline
assembly code which prevents it being ported to other architectures.

This patch adds callback functions and moves those to arch/x86/

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 32a4351..6ff9947 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,6 +15,43 @@
 
 static bool i440fx;
 
+#ifdef CONFIG_QFW
+
+#define FW_CONTROL_PORT	0x510
+#define FW_DATA_PORT		0x511
+#define FW_DMA_PORT_LOW	0x514
+#define FW_DMA_PORT_HIGH	0x518
+
+static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(entry, FW_CONTROL_PORT);
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
+{
+	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+static struct fw_cfg_arch_ops fwcfg_x86_ops = {
+	.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
+	.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+};
+#endif
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -89,7 +126,7 @@ static void qemu_chipset_init(void)
 	}
 
 #ifdef CONFIG_QFW
-	qemu_fwcfg_init();
+	qemu_fwcfg_init(&fwcfg_x86_ops);
 #endif
 }
 
diff --git a/drivers/misc/qemu_fw_cfg.c b/drivers/misc/qemu_fw_cfg.c
index a574bd1..0f72549 100644
--- a/drivers/misc/qemu_fw_cfg.c
+++ b/drivers/misc/qemu_fw_cfg.c
@@ -14,6 +14,7 @@
 
 static bool fwcfg_present;
 static bool fwcfg_dma_present;
+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
 
 static LIST_HEAD(fw_list);
 
@@ -21,17 +22,10 @@ static LIST_HEAD(fw_list);
 static void qemu_fwcfg_read_entry_pio(uint16_t entry,
 		uint32_t size, void *address)
 {
-	uint32_t i = 0;
-	uint8_t *data = address;
+	debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
+	      entry, size, address);
 
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
+	return fwcfg_arch_ops->arch_read_pio(entry, size, address);
 }
 
 /* Read configuration item using fw_cfg DMA interface */
@@ -53,13 +47,10 @@ static void qemu_fwcfg_read_entry_dma(uint16_t entry,
 
 	barrier();
 
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
+	debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+	      entry, size, address, be32_to_cpu(dma.control));
 
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
+	fwcfg_arch_ops->arch_read_dma(&dma);
 }
 
 bool qemu_fwcfg_present(void)
@@ -164,13 +155,18 @@ bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
 	return iter->entry == &fw_list;
 }
 
-void qemu_fwcfg_init(void)
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
 {
 	uint32_t qemu;
 	uint32_t dma_enabled;
 
 	fwcfg_present = false;
 	fwcfg_dma_present = false;
+	fwcfg_arch_ops = NULL;
+
+	if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
+		return;
+	fwcfg_arch_ops = ops;
 
 	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
 	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h
index f718e09..b0b3b59 100644
--- a/include/qemu_fw_cfg.h
+++ b/include/qemu_fw_cfg.h
@@ -7,11 +7,6 @@
 #ifndef __FW_CFG__
 #define __FW_CFG__
 
-#define FW_CONTROL_PORT	0x510
-#define FW_DATA_PORT		0x511
-#define FW_DMA_PORT_LOW	0x514
-#define FW_DMA_PORT_HIGH	0x518
-
 #include <linux/list.h>
 
 enum qemu_fwcfg_items {
@@ -97,6 +92,12 @@ struct fw_cfg_dma_access {
 	__be64 address;
 };
 
+struct fw_cfg_arch_ops {
+	void (*arch_read_pio)(uint16_t selector, uint32_t size,
+			void *address);
+	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
 struct bios_linker_entry {
 	__le32 command;
 	union {
@@ -148,8 +149,10 @@ struct bios_linker_entry {
 
 /**
  * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
  */
-void qemu_fwcfg_init(void);
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
 
 void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
 int qemu_fwcfg_read_firmware_list(void);
-- 
cgit v0.10.2


From 331ba7db6c19992b9800e9c53373d31794ce11ae Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:16 -0700
Subject: x86: qemu: add comment about qfw register endianness

This patch adds some comments about qfw register endianness for clarity.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 6ff9947..c29add3 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -17,6 +17,7 @@ static bool i440fx;
 
 #ifdef CONFIG_QFW
 
+/* on x86, the qfw registers are all IO ports */
 #define FW_CONTROL_PORT	0x510
 #define FW_DATA_PORT		0x511
 #define FW_DMA_PORT_LOW	0x514
@@ -31,15 +32,21 @@ static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
 	/*
 	 * writting FW_CFG_INVALID will cause read operation to resume at
 	 * last offset, otherwise read will start at offset 0
+	 *
+	 * Note: on platform where the control register is IO port, the
+	 * endianness is little endian.
 	 */
 	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
+		outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+	/* the endianness of data register is string-preserving */
 	while (size--)
 		data[i++] = inb(FW_DATA_PORT);
 }
 
 static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
 {
+	/* the DMA address register is big endian */
 	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
 
 	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
-- 
cgit v0.10.2


From 1868659002a6b7ab3b1da7be74f53d3e10e915be Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:17 -0700
Subject: cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]

Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index c44a286..8207274 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -11,7 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
-#include <qemu_fw_cfg.h>
+#include <qfw.h>
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c
index b17fa03..5bb1756 100644
--- a/arch/x86/cpu/qemu/acpi_table.c
+++ b/arch/x86/cpu/qemu/acpi_table.c
@@ -8,7 +8,7 @@
 #include <command.h>
 #include <errno.h>
 #include <malloc.h>
-#include <qemu_fw_cfg.h>
+#include <qfw.h>
 #include <asm/io.h>
 #include <asm/tables.h>
 #include <asm/e820.h>
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index 4d2989a..b1a965e 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -8,7 +8,7 @@
 #include <cpu.h>
 #include <dm.h>
 #include <errno.h>
-#include <qemu_fw_cfg.h>
+#include <qfw.h>
 #include <asm/cpu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index c29add3..680e558 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <pci.h>
-#include <qemu_fw_cfg.h>
+#include <qfw.h>
 #include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 08b761f..c5a7a59 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -593,7 +593,7 @@ config CMD_SOUND
 	     sound init   - set up sound system
 	     sound play   - play a sound
 
-config CMD_QEMU_FW_CFG
+config CMD_QFW
 	bool "qfw"
 	depends on X86
 	select QFW
diff --git a/cmd/Makefile b/cmd/Makefile
index ff4fc5b..9ce7861 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,7 +105,7 @@ endif
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PORTIO) += portio.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
-obj-$(CONFIG_CMD_QEMU_FW_CFG) += qfw.o
+obj-$(CONFIG_CMD_QFW) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
diff --git a/cmd/qfw.c b/cmd/qfw.c
index 37f1aa6..c6730bf 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <command.h>
 #include <errno.h>
-#include <qemu_fw_cfg.h>
+#include <qfw.h>
 
 /*
  * This function prepares kernel for zboot. It loads kernel data
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index a813e5b..45bb3ec 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -20,7 +20,7 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_QEMU_FW_CFG=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fa53700..c40f6b5 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -142,6 +142,6 @@ config QFW
 	bool
 	help
 	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
-	  either CONFIG_CMD_QEMU_FW_CFG or CONFIG_GENERATE_ACPI_TABLE.
+	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
 
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 4893086..98704f2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -43,4 +43,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_RESET) += reset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
-obj-$(CONFIG_QFW) += qemu_fw_cfg.o
+obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/qemu_fw_cfg.c b/drivers/misc/qemu_fw_cfg.c
deleted file mode 100644
index 0f72549..0000000
--- a/drivers/misc/qemu_fw_cfg.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <qemu_fw_cfg.h>
-#include <asm/io.h>
-#include <linux/list.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-static struct fw_cfg_arch_ops *fwcfg_arch_ops;
-
-static LIST_HEAD(fw_list);
-
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
-	      entry, size, address);
-
-	return fwcfg_arch_ops->arch_read_pio(entry, size, address);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
-	      entry, size, address, be32_to_cpu(dma.control));
-
-	fwcfg_arch_ops->arch_read_dma(&dma);
-}
-
-bool qemu_fwcfg_present(void)
-{
-	return fwcfg_present;
-}
-
-bool qemu_fwcfg_dma_present(void)
-{
-	return fwcfg_dma_present;
-}
-
-void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
-struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
-{
-	iter->entry = fw_list.next;
-	return list_entry((struct list_head *)iter->entry,
-			  struct fw_file, list);
-}
-
-struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
-{
-	iter->entry = ((struct list_head *)iter->entry)->next;
-	return list_entry((struct list_head *)iter->entry,
-			  struct fw_file, list);
-}
-
-bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
-{
-	return iter->entry == &fw_list;
-}
-
-void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
-{
-	uint32_t qemu;
-	uint32_t dma_enabled;
-
-	fwcfg_present = false;
-	fwcfg_dma_present = false;
-	fwcfg_arch_ops = NULL;
-
-	if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
-		return;
-	fwcfg_arch_ops = ops;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
-		fwcfg_present = true;
-
-	if (fwcfg_present) {
-		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-		if (dma_enabled & FW_CFG_DMA_ENABLED)
-			fwcfg_dma_present = true;
-	}
-}
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
new file mode 100644
index 0000000..59d9376
--- /dev/null
+++ b/drivers/misc/qfw.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <qfw.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
+
+static LIST_HEAD(fw_list);
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
+	      entry, size, address);
+
+	return fwcfg_arch_ops->arch_read_pio(entry, size, address);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+		uint32_t size, void *address)
+{
+	struct fw_cfg_dma_access dma;
+
+	dma.length = cpu_to_be32(size);
+	dma.address = cpu_to_be64((uintptr_t)address);
+	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+	barrier();
+
+	debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+	      entry, size, address, be32_to_cpu(dma.control));
+
+	fwcfg_arch_ops->arch_read_dma(&dma);
+}
+
+bool qemu_fwcfg_present(void)
+{
+	return fwcfg_present;
+}
+
+bool qemu_fwcfg_dma_present(void)
+{
+	return fwcfg_dma_present;
+}
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+	if (fwcfg_dma_present)
+		qemu_fwcfg_read_entry_dma(entry, length, address);
+	else
+		qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+	uint16_t nb_cpus;
+
+	if (!fwcfg_present)
+		return -ENODEV;
+
+	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+	return le16_to_cpu(nb_cpus);
+}
+
+int qemu_fwcfg_read_firmware_list(void)
+{
+	int i;
+	uint32_t count;
+	struct fw_file *file;
+	struct list_head *entry;
+
+	/* don't read it twice */
+	if (!list_empty(&fw_list))
+		return 0;
+
+	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+	if (!count)
+		return 0;
+
+	count = be32_to_cpu(count);
+	for (i = 0; i < count; i++) {
+		file = malloc(sizeof(*file));
+		if (!file) {
+			printf("error: allocating resource\n");
+			goto err;
+		}
+		qemu_fwcfg_read_entry(FW_CFG_INVALID,
+				      sizeof(struct fw_cfg_file), &file->cfg);
+		file->addr = 0;
+		list_add_tail(&file->list, &fw_list);
+	}
+
+	return 0;
+
+err:
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		free(file);
+	}
+
+	return -ENOMEM;
+}
+
+struct fw_file *qemu_fwcfg_find_file(const char *name)
+{
+	struct list_head *entry;
+	struct fw_file *file;
+
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		if (!strcmp(file->cfg.name, name))
+			return file;
+	}
+
+	return NULL;
+}
+
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = fw_list.next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = ((struct list_head *)iter->entry)->next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+	return iter->entry == &fw_list;
+}
+
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
+{
+	uint32_t qemu;
+	uint32_t dma_enabled;
+
+	fwcfg_present = false;
+	fwcfg_dma_present = false;
+	fwcfg_arch_ops = NULL;
+
+	if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
+		return;
+	fwcfg_arch_ops = ops;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+		fwcfg_present = true;
+
+	if (fwcfg_present) {
+		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+		if (dma_enabled & FW_CFG_DMA_ENABLED)
+			fwcfg_dma_present = true;
+	}
+}
diff --git a/include/qemu_fw_cfg.h b/include/qemu_fw_cfg.h
deleted file mode 100644
index b0b3b59..0000000
--- a/include/qemu_fw_cfg.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FW_CFG__
-#define __FW_CFG__
-
-#include <linux/list.h>
-
-enum qemu_fwcfg_items {
-	FW_CFG_SIGNATURE	= 0x00,
-	FW_CFG_ID		= 0x01,
-	FW_CFG_UUID		= 0x02,
-	FW_CFG_RAM_SIZE		= 0x03,
-	FW_CFG_NOGRAPHIC	= 0x04,
-	FW_CFG_NB_CPUS		= 0x05,
-	FW_CFG_MACHINE_ID	= 0x06,
-	FW_CFG_KERNEL_ADDR	= 0x07,
-	FW_CFG_KERNEL_SIZE	= 0x08,
-	FW_CFG_KERNEL_CMDLINE   = 0x09,
-	FW_CFG_INITRD_ADDR	= 0x0a,
-	FW_CFG_INITRD_SIZE	= 0x0b,
-	FW_CFG_BOOT_DEVICE	= 0x0c,
-	FW_CFG_NUMA		= 0x0d,
-	FW_CFG_BOOT_MENU	= 0x0e,
-	FW_CFG_MAX_CPUS		= 0x0f,
-	FW_CFG_KERNEL_ENTRY	= 0x10,
-	FW_CFG_KERNEL_DATA	= 0x11,
-	FW_CFG_INITRD_DATA	= 0x12,
-	FW_CFG_CMDLINE_ADDR	= 0x13,
-	FW_CFG_CMDLINE_SIZE	= 0x14,
-	FW_CFG_CMDLINE_DATA	= 0x15,
-	FW_CFG_SETUP_ADDR	= 0x16,
-	FW_CFG_SETUP_SIZE	= 0x17,
-	FW_CFG_SETUP_DATA	= 0x18,
-	FW_CFG_FILE_DIR		= 0x19,
-	FW_CFG_FILE_FIRST	= 0x20,
-	FW_CFG_WRITE_CHANNEL	= 0x4000,
-	FW_CFG_ARCH_LOCAL	= 0x8000,
-	FW_CFG_INVALID		= 0xffff,
-};
-
-enum {
-	BIOS_LINKER_LOADER_COMMAND_ALLOCATE	= 0x1,
-	BIOS_LINKER_LOADER_COMMAND_ADD_POINTER  = 0x2,
-	BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
-};
-
-enum {
-	BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
-	BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
-};
-
-#define FW_CFG_FILE_SLOTS	0x10
-#define FW_CFG_MAX_ENTRY	(FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
-#define FW_CFG_ENTRY_MASK	 ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
-
-#define FW_CFG_MAX_FILE_PATH	56
-#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
-
-#define QEMU_FW_CFG_SIGNATURE	(('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
-
-#define FW_CFG_DMA_ERROR	(1 << 0)
-#define FW_CFG_DMA_READ	(1 << 1)
-#define FW_CFG_DMA_SKIP	(1 << 2)
-#define FW_CFG_DMA_SELECT	(1 << 3)
-
-#define FW_CFG_DMA_ENABLED	(1 << 1)
-
-struct fw_cfg_file {
-	__be32 size;
-	__be16 select;
-	__be16 reserved;
-	char name[FW_CFG_MAX_FILE_PATH];
-};
-
-struct fw_file {
-	struct fw_cfg_file cfg; /* firmware file information */
-	unsigned long addr;     /* firmware file in-memory address */
-	struct list_head list;  /* list node to link to fw_list */
-};
-
-struct fw_cfg_file_iter {
-	struct list_head *entry; /* structure to iterate file list */
-};
-
-struct fw_cfg_dma_access {
-	__be32 control;
-	__be32 length;
-	__be64 address;
-};
-
-struct fw_cfg_arch_ops {
-	void (*arch_read_pio)(uint16_t selector, uint32_t size,
-			void *address);
-	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
-};
-
-struct bios_linker_entry {
-	__le32 command;
-	union {
-		/*
-		 * COMMAND_ALLOCATE - allocate a table from @alloc.file
-		 * subject to @alloc.align alignment (must be power of 2)
-		 * and @alloc.zone (can be HIGH or FSEG) requirements.
-		 *
-		 * Must appear exactly once for each file, and before
-		 * this file is referenced by any other command.
-		 */
-		struct {
-			char file[BIOS_LINKER_LOADER_FILESZ];
-			__le32 align;
-			uint8_t zone;
-		} alloc;
-
-		/*
-		 * COMMAND_ADD_POINTER - patch the table (originating from
-		 * @dest_file) at @pointer.offset, by adding a pointer to the
-		 * table originating from @src_file. 1,2,4 or 8 byte unsigned
-		 * addition is used depending on @pointer.size.
-		 */
-		struct {
-			char dest_file[BIOS_LINKER_LOADER_FILESZ];
-			char src_file[BIOS_LINKER_LOADER_FILESZ];
-			__le32 offset;
-			uint8_t size;
-		} pointer;
-
-		/*
-		 * COMMAND_ADD_CHECKSUM - calculate checksum of the range
-		 * specified by @cksum_start and @cksum_length fields,
-		 * and then add the value at @cksum.offset.
-		 * Checksum simply sums -X for each byte X in the range
-		 * using 8-bit math.
-		 */
-		struct {
-			char file[BIOS_LINKER_LOADER_FILESZ];
-			__le32 offset;
-			__le32 start;
-			__le32 length;
-		} cksum;
-
-		/* padding */
-		char pad[124];
-	};
-} __packed;
-
-/**
- * Initialize QEMU fw_cfg interface
- *
- * @ops: arch specific read operations
- */
-void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
-
-void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
-int qemu_fwcfg_read_firmware_list(void);
-struct fw_file *qemu_fwcfg_find_file(const char *name);
-
-/**
- * Get system cpu number
- *
- * @return:   cpu number in system
- */
-int qemu_fwcfg_online_cpus(void);
-
-/* helper functions to iterate firmware file list */
-struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
-struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
-bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
-
-bool qemu_fwcfg_present(void);
-bool qemu_fwcfg_dma_present(void);
-
-#endif
diff --git a/include/qfw.h b/include/qfw.h
new file mode 100644
index 0000000..b0b3b59
--- /dev/null
+++ b/include/qfw.h
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#include <linux/list.h>
+
+enum qemu_fwcfg_items {
+	FW_CFG_SIGNATURE	= 0x00,
+	FW_CFG_ID		= 0x01,
+	FW_CFG_UUID		= 0x02,
+	FW_CFG_RAM_SIZE		= 0x03,
+	FW_CFG_NOGRAPHIC	= 0x04,
+	FW_CFG_NB_CPUS		= 0x05,
+	FW_CFG_MACHINE_ID	= 0x06,
+	FW_CFG_KERNEL_ADDR	= 0x07,
+	FW_CFG_KERNEL_SIZE	= 0x08,
+	FW_CFG_KERNEL_CMDLINE   = 0x09,
+	FW_CFG_INITRD_ADDR	= 0x0a,
+	FW_CFG_INITRD_SIZE	= 0x0b,
+	FW_CFG_BOOT_DEVICE	= 0x0c,
+	FW_CFG_NUMA		= 0x0d,
+	FW_CFG_BOOT_MENU	= 0x0e,
+	FW_CFG_MAX_CPUS		= 0x0f,
+	FW_CFG_KERNEL_ENTRY	= 0x10,
+	FW_CFG_KERNEL_DATA	= 0x11,
+	FW_CFG_INITRD_DATA	= 0x12,
+	FW_CFG_CMDLINE_ADDR	= 0x13,
+	FW_CFG_CMDLINE_SIZE	= 0x14,
+	FW_CFG_CMDLINE_DATA	= 0x15,
+	FW_CFG_SETUP_ADDR	= 0x16,
+	FW_CFG_SETUP_SIZE	= 0x17,
+	FW_CFG_SETUP_DATA	= 0x18,
+	FW_CFG_FILE_DIR		= 0x19,
+	FW_CFG_FILE_FIRST	= 0x20,
+	FW_CFG_WRITE_CHANNEL	= 0x4000,
+	FW_CFG_ARCH_LOCAL	= 0x8000,
+	FW_CFG_INVALID		= 0xffff,
+};
+
+enum {
+	BIOS_LINKER_LOADER_COMMAND_ALLOCATE	= 0x1,
+	BIOS_LINKER_LOADER_COMMAND_ADD_POINTER  = 0x2,
+	BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+	BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+	BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+#define FW_CFG_FILE_SLOTS	0x10
+#define FW_CFG_MAX_ENTRY	(FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK	 ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH	56
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+#define QEMU_FW_CFG_SIGNATURE	(('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR	(1 << 0)
+#define FW_CFG_DMA_READ	(1 << 1)
+#define FW_CFG_DMA_SKIP	(1 << 2)
+#define FW_CFG_DMA_SELECT	(1 << 3)
+
+#define FW_CFG_DMA_ENABLED	(1 << 1)
+
+struct fw_cfg_file {
+	__be32 size;
+	__be16 select;
+	__be16 reserved;
+	char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_file {
+	struct fw_cfg_file cfg; /* firmware file information */
+	unsigned long addr;     /* firmware file in-memory address */
+	struct list_head list;  /* list node to link to fw_list */
+};
+
+struct fw_cfg_file_iter {
+	struct list_head *entry; /* structure to iterate file list */
+};
+
+struct fw_cfg_dma_access {
+	__be32 control;
+	__be32 length;
+	__be64 address;
+};
+
+struct fw_cfg_arch_ops {
+	void (*arch_read_pio)(uint16_t selector, uint32_t size,
+			void *address);
+	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
+struct bios_linker_entry {
+	__le32 command;
+	union {
+		/*
+		 * COMMAND_ALLOCATE - allocate a table from @alloc.file
+		 * subject to @alloc.align alignment (must be power of 2)
+		 * and @alloc.zone (can be HIGH or FSEG) requirements.
+		 *
+		 * Must appear exactly once for each file, and before
+		 * this file is referenced by any other command.
+		 */
+		struct {
+			char file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 align;
+			uint8_t zone;
+		} alloc;
+
+		/*
+		 * COMMAND_ADD_POINTER - patch the table (originating from
+		 * @dest_file) at @pointer.offset, by adding a pointer to the
+		 * table originating from @src_file. 1,2,4 or 8 byte unsigned
+		 * addition is used depending on @pointer.size.
+		 */
+		struct {
+			char dest_file[BIOS_LINKER_LOADER_FILESZ];
+			char src_file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 offset;
+			uint8_t size;
+		} pointer;
+
+		/*
+		 * COMMAND_ADD_CHECKSUM - calculate checksum of the range
+		 * specified by @cksum_start and @cksum_length fields,
+		 * and then add the value at @cksum.offset.
+		 * Checksum simply sums -X for each byte X in the range
+		 * using 8-bit math.
+		 */
+		struct {
+			char file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 offset;
+			__le32 start;
+			__le32 length;
+		} cksum;
+
+		/* padding */
+		char pad[124];
+	};
+} __packed;
+
+/**
+ * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
+ */
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
+
+/**
+ * Get system cpu number
+ *
+ * @return:   cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
+#endif
-- 
cgit v0.10.2


From 86e30e67ad068ebedd1e6cc8833ba413ea28ed75 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:18 -0700
Subject: cmd: qfw: do not require default macros when building qfw command

The qfw command interface makes use of CONFIG_LOADADDR and
CONFIG_RAMDISKADDR to setup kernel. But not all boards have these macros,
which causes build problem on those platforms.

This patch fixes this issue.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/cmd/qfw.c b/cmd/qfw.c
index c6730bf..12436ec 100644
--- a/cmd/qfw.c
+++ b/cmd/qfw.c
@@ -126,12 +126,20 @@ static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
 	env = getenv("loadaddr");
 	load_addr = env ?
 		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_LOADADDR
 		(void *)CONFIG_LOADADDR;
+#else
+		NULL;
+#endif
 
 	env = getenv("ramdiskaddr");
 	initrd_addr = env ?
 		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_RAMDISK_ADDR
 		(void *)CONFIG_RAMDISK_ADDR;
+#else
+		NULL;
+#endif
 
 	if (argc == 2) {
 		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
@@ -140,6 +148,11 @@ static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
 		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
 	}
 
+	if (!load_addr || !initrd_addr) {
+		printf("missing load or initrd address\n");
+		return CMD_RET_FAILURE;
+	}
+
 	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
 }
 
-- 
cgit v0.10.2


From d6ccb14e5a8f3b782f9f09b88d5ca6695039a5f6 Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:19 -0700
Subject: cmd: qfw: do not depend on x86

The qfw command interface used to depend on X86, this patch removes
this restriction so it can be built for sandbox for testing. For normal
usage, it can only be used with CONFIG_QEMU.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/cmd/Kconfig b/cmd/Kconfig
index c5a7a59..d51645c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -595,7 +595,6 @@ config CMD_SOUND
 
 config CMD_QFW
 	bool "qfw"
-	depends on X86
 	select QFW
 	help
 	  This provides access to the QEMU firmware interface.  The main
-- 
cgit v0.10.2


From eece493a7ac14f5049a8bd7031ba37e2c6e2460a Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:20 -0700
Subject: cmd: qfw: bring ACPI generation code into qfw core

Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c
index 5bb1756..63853e4 100644
--- a/arch/x86/cpu/qemu/acpi_table.c
+++ b/arch/x86/cpu/qemu/acpi_table.c
@@ -5,139 +5,7 @@
  */
 
 #include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <qfw.h>
-#include <asm/io.h>
-#include <asm/tables.h>
 #include <asm/e820.h>
-#include <linux/list.h>
-#include <memalign.h>
-
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- *          (either high memory or low memory)
- * @addr  : The address that should be used for low memory allcation. If the
- *          memory allocation request is 'ZONE_HIGH' then this parameter will
- *          be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
-{
-	uint32_t size, align;
-	struct fw_file *file;
-	unsigned long aligned_addr;
-
-	align = le32_to_cpu(entry->alloc.align);
-	/* align must be power of 2 */
-	if (align & (align - 1)) {
-		printf("error: wrong alignment %u\n", align);
-		return -EINVAL;
-	}
-
-	file = qemu_fwcfg_find_file(entry->alloc.file);
-	if (!file) {
-		printf("error: can't find file %s\n", entry->alloc.file);
-		return -ENOENT;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-
-	/*
-	 * ZONE_HIGH means we need to allocate from high memory, since
-	 * malloc space is already at the end of RAM, so we directly use it.
-	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
-	 * in which is low memory
-	 */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
-		aligned_addr = (unsigned long)memalign(align, size);
-		if (!aligned_addr) {
-			printf("error: allocating resource\n");
-			return -ENOMEM;
-		}
-	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
-		aligned_addr = ALIGN(*addr, align);
-	} else {
-		printf("error: invalid allocation zone\n");
-		return -EINVAL;
-	}
-
-	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
-	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, (void *)aligned_addr);
-	file->addr = aligned_addr;
-
-	/* adjust address for low memory allocation */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
-		*addr = (aligned_addr + size);
-
-	return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- *          ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct bios_linker_entry *entry)
-{
-	struct fw_file *dest, *src;
-	uint32_t offset = le32_to_cpu(entry->pointer.offset);
-	uint64_t pointer = 0;
-
-	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
-	if (!dest || !dest->addr)
-		return -ENOENT;
-	src = qemu_fwcfg_find_file(entry->pointer.src_file);
-	if (!src || !src->addr)
-		return -ENOENT;
-
-	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
-	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
-	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
-	pointer	= le64_to_cpu(pointer);
-	pointer += (unsigned long)src->addr;
-	pointer	= cpu_to_le64(pointer);
-	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
-
-	return 0;
-}
-
-/*
- * This function updates checksum fields of ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells where to update ACPI table
- *          checksums
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_checksum(struct bios_linker_entry *entry)
-{
-	struct fw_file *file;
-	uint8_t *data, cksum = 0;
-	uint8_t *cksum_start;
-
-	file = qemu_fwcfg_find_file(entry->cksum.file);
-	if (!file || !file->addr)
-		return -ENOENT;
-
-	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
-	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
-	cksum = table_compute_checksum(cksum_start,
-				       le32_to_cpu(entry->cksum.length));
-	*data = cksum;
-
-	return 0;
-}
 
 unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
 {
@@ -173,80 +41,3 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
 
 	return 6;
 }
-
-/* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
-{
-	int i, ret = 0;
-	struct fw_file *file;
-	struct bios_linker_entry *table_loader;
-	struct bios_linker_entry *entry;
-	uint32_t size;
-
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret) {
-		printf("error: can't read firmware file list\n");
-		return addr;
-	}
-
-	file = qemu_fwcfg_find_file("etc/table-loader");
-	if (!file) {
-		printf("error: can't find etc/table-loader\n");
-		return addr;
-	}
-
-	size = be32_to_cpu(file->cfg.size);
-	if ((size % sizeof(*entry)) != 0) {
-		printf("error: table-loader maybe corrupted\n");
-		return addr;
-	}
-
-	table_loader = malloc(size);
-	if (!table_loader) {
-		printf("error: no memory for table-loader\n");
-		return addr;
-	}
-
-	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
-			      size, table_loader);
-
-	for (i = 0; i < (size / sizeof(*entry)); i++) {
-		entry = table_loader + i;
-		switch (le32_to_cpu(entry->command)) {
-		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
-			ret = bios_linker_allocate(entry, &addr);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
-			ret = bios_linker_add_pointer(entry);
-			if (ret)
-				goto out;
-			break;
-		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
-			ret = bios_linker_add_checksum(entry);
-			if (ret)
-				goto out;
-			break;
-		default:
-			break;
-		}
-	}
-
-out:
-	if (ret) {
-		struct fw_cfg_file_iter iter;
-		for (file = qemu_fwcfg_file_iter_init(&iter);
-		     !qemu_fwcfg_file_iter_end(&iter);
-		     file = qemu_fwcfg_file_iter_next(&iter)) {
-			if (file->addr) {
-				free((void *)file->addr);
-				file->addr = 0;
-			}
-		}
-	}
-
-	free(table_loader);
-	return addr;
-}
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index 59d9376..d43d1d3 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -10,6 +10,9 @@
 #include <malloc.h>
 #include <qfw.h>
 #include <asm/io.h>
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#include <asm/tables.h>
+#endif
 #include <linux/list.h>
 
 static bool fwcfg_present;
@@ -18,6 +21,209 @@ static struct fw_cfg_arch_ops *fwcfg_arch_ops;
 
 static LIST_HEAD(fw_list);
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+/*
+ * This function allocates memory for ACPI tables
+ *
+ * @entry : BIOS linker command entry which tells where to allocate memory
+ *          (either high memory or low memory)
+ * @addr  : The address that should be used for low memory allcation. If the
+ *          memory allocation request is 'ZONE_HIGH' then this parameter will
+ *          be ignored.
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
+{
+	uint32_t size, align;
+	struct fw_file *file;
+	unsigned long aligned_addr;
+
+	align = le32_to_cpu(entry->alloc.align);
+	/* align must be power of 2 */
+	if (align & (align - 1)) {
+		printf("error: wrong alignment %u\n", align);
+		return -EINVAL;
+	}
+
+	file = qemu_fwcfg_find_file(entry->alloc.file);
+	if (!file) {
+		printf("error: can't find file %s\n", entry->alloc.file);
+		return -ENOENT;
+	}
+
+	size = be32_to_cpu(file->cfg.size);
+
+	/*
+	 * ZONE_HIGH means we need to allocate from high memory, since
+	 * malloc space is already at the end of RAM, so we directly use it.
+	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
+	 * in which is low memory
+	 */
+	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+		aligned_addr = (unsigned long)memalign(align, size);
+		if (!aligned_addr) {
+			printf("error: allocating resource\n");
+			return -ENOMEM;
+		}
+	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
+		aligned_addr = ALIGN(*addr, align);
+	} else {
+		printf("error: invalid allocation zone\n");
+		return -EINVAL;
+	}
+
+	debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
+	      file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
+
+	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+			      size, (void *)aligned_addr);
+	file->addr = aligned_addr;
+
+	/* adjust address for low memory allocation */
+	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+		*addr = (aligned_addr + size);
+
+	return 0;
+}
+
+/*
+ * This function patches ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells how to patch
+ *          ACPI tables
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_pointer(struct bios_linker_entry *entry)
+{
+	struct fw_file *dest, *src;
+	uint32_t offset = le32_to_cpu(entry->pointer.offset);
+	uint64_t pointer = 0;
+
+	dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
+	if (!dest || !dest->addr)
+		return -ENOENT;
+	src = qemu_fwcfg_find_file(entry->pointer.src_file);
+	if (!src || !src->addr)
+		return -ENOENT;
+
+	debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
+	      dest->addr, src->addr, offset, entry->pointer.size, pointer);
+
+	memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
+	pointer	= le64_to_cpu(pointer);
+	pointer += (unsigned long)src->addr;
+	pointer	= cpu_to_le64(pointer);
+	memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
+
+	return 0;
+}
+
+/*
+ * This function updates checksum fields of ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells where to update ACPI table
+ *          checksums
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_checksum(struct bios_linker_entry *entry)
+{
+	struct fw_file *file;
+	uint8_t *data, cksum = 0;
+	uint8_t *cksum_start;
+
+	file = qemu_fwcfg_find_file(entry->cksum.file);
+	if (!file || !file->addr)
+		return -ENOENT;
+
+	data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
+	cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
+	cksum = table_compute_checksum(cksum_start,
+				       le32_to_cpu(entry->cksum.length));
+	*data = cksum;
+
+	return 0;
+}
+
+/* This function loads and patches ACPI tables provided by QEMU */
+u32 write_acpi_tables(u32 addr)
+{
+	int i, ret = 0;
+	struct fw_file *file;
+	struct bios_linker_entry *table_loader;
+	struct bios_linker_entry *entry;
+	uint32_t size;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret) {
+		printf("error: can't read firmware file list\n");
+		return addr;
+	}
+
+	file = qemu_fwcfg_find_file("etc/table-loader");
+	if (!file) {
+		printf("error: can't find etc/table-loader\n");
+		return addr;
+	}
+
+	size = be32_to_cpu(file->cfg.size);
+	if ((size % sizeof(*entry)) != 0) {
+		printf("error: table-loader maybe corrupted\n");
+		return addr;
+	}
+
+	table_loader = malloc(size);
+	if (!table_loader) {
+		printf("error: no memory for table-loader\n");
+		return addr;
+	}
+
+	qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+			      size, table_loader);
+
+	for (i = 0; i < (size / sizeof(*entry)); i++) {
+		entry = table_loader + i;
+		switch (le32_to_cpu(entry->command)) {
+		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
+			ret = bios_linker_allocate(entry, &addr);
+			if (ret)
+				goto out;
+			break;
+		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+			ret = bios_linker_add_pointer(entry);
+			if (ret)
+				goto out;
+			break;
+		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+			ret = bios_linker_add_checksum(entry);
+			if (ret)
+				goto out;
+			break;
+		default:
+			break;
+		}
+	}
+
+out:
+	if (ret) {
+		struct fw_cfg_file_iter iter;
+		for (file = qemu_fwcfg_file_iter_init(&iter);
+		     !qemu_fwcfg_file_iter_end(&iter);
+		     file = qemu_fwcfg_file_iter_next(&iter)) {
+			if (file->addr) {
+				free((void *)file->addr);
+				file->addr = 0;
+			}
+		}
+	}
+
+	free(table_loader);
+	return addr;
+}
+#endif
+
 /* Read configuration item using fw_cfg PIO interface */
 static void qemu_fwcfg_read_entry_pio(uint16_t entry,
 		uint32_t size, void *address)
-- 
cgit v0.10.2


From 494ec0d0933784b4d14cfb40380fb77408a8b7ef Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:21 -0700
Subject: x86: qemu: rename qemu/acpi_table.c

Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved
to qfw core, this file only contains code for installing e820 table.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 7c08c3d..a080c5e 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -8,5 +8,4 @@ ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
 obj-y += qemu.o
-obj-$(CONFIG_QFW) += cpu.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
+obj-$(CONFIG_QFW) += cpu.o e820.o
diff --git a/arch/x86/cpu/qemu/acpi_table.c b/arch/x86/cpu/qemu/acpi_table.c
deleted file mode 100644
index 63853e4..0000000
--- a/arch/x86/cpu/qemu/acpi_table.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/e820.h>
-
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-
-	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
-	 */
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[3].size = TOTAL_MALLOC_LEN;
-	entries[3].type = E820_RESERVED;
-
-	entries[4].addr = gd->relocaddr;
-	entries[4].size = gd->ram_size - gd->relocaddr;
-	entries[4].type = E820_RESERVED;
-
-	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[5].type = E820_RESERVED;
-
-	return 6;
-}
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
new file mode 100644
index 0000000..63853e4
--- /dev/null
+++ b/arch/x86/cpu/qemu/e820.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	entries[0].addr = 0;
+	entries[0].size = ISA_START_ADDRESS;
+	entries[0].type = E820_RAM;
+
+	entries[1].addr = ISA_START_ADDRESS;
+	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+	entries[1].type = E820_RESERVED;
+
+	/*
+	 * since we use memalign(malloc) to allocate high memory for
+	 * storing ACPI tables, we need to reserve them in e820 tables,
+	 * otherwise kernel will reclaim them and data will be corrupted
+	 */
+	entries[2].addr = ISA_END_ADDRESS;
+	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+	entries[2].type = E820_RAM;
+
+	/* for simplicity, reserve entire malloc space */
+	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+	entries[3].size = TOTAL_MALLOC_LEN;
+	entries[3].type = E820_RESERVED;
+
+	entries[4].addr = gd->relocaddr;
+	entries[4].size = gd->ram_size - gd->relocaddr;
+	entries[4].type = E820_RESERVED;
+
+	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[5].type = E820_RESERVED;
+
+	return 6;
+}
-- 
cgit v0.10.2


From f7e20f6628c679bd2617c0a58b44e8d9407b475d Mon Sep 17 00:00:00 2001
From: Miao Yan <yanmiaobest@gmail.com>
Date: Sun, 22 May 2016 19:37:22 -0700
Subject: config: sandbox: enable qfw and cmd_qfw for testing

This patch enables qfw and cmd_qfw on sandbox for build coverage test

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index aec2e53..9e4a92d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -48,6 +48,7 @@ CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_SOUND=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
-- 
cgit v0.10.2


From 91fc5bf652c1e959373cd21df4809a74d31e75fe Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:44:55 -0700
Subject: x86: minnowmax: Adjust U-Boot environment address in SPI flash

Currently U-Boot environment address is at offset 0x7fe00 of a 8MB
SPI flash. When creating a partial u-boot.rom image without flash
descriptor and ME firmware, U-Boot actually occupies the last 1MB
of the flash, and reprograming U-Boot causes previous environment
settings get lost which is not convenient during testing.

Adjust the environment address to 0x6ef000 instead (before the MRC
cache data region in the flash).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.x86 b/doc/README.x86
index ce806ee..25cb218 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -304,12 +304,12 @@ Offset   Description         Controlling config
 000000   descriptor.bin      Hard-coded to 0 in ifdtool
 001000   me.bin              Set by the descriptor
 500000   <spare>
+6ef000   Environment         CONFIG_ENV_OFFSET
 6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
 790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
-7fe000   Environment         CONFIG_ENV_OFFSET
 7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
 
 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 674d1f6..95ad128 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -40,6 +40,6 @@
 #define CONFIG_X86EMU_RAW_IO
 
 #define CONFIG_ENV_SECT_SIZE		0x1000
-#define CONFIG_ENV_OFFSET		0x007fe000
+#define CONFIG_ENV_OFFSET		0x006ef000
 
 #endif	/* __CONFIG_H */
-- 
cgit v0.10.2


From 1e2f7b9e8e077cb6937204c305d554ef7a970be5 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:44:56 -0700
Subject: x86: Call board_final_cleanup() in last_stage_init()

At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, VxWorks or Windows.

Move the call to last_stage_init() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 845f86a..1b04203 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,15 +39,7 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-	if (gd->flags & GD_FLG_COLD_BOOT)
-		timestamp_add_to_bootstage();
-
-	return 0;
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
 {
 	/*
 	 * Un-cache the ROM so the kernel has one
@@ -79,6 +71,16 @@ void board_final_cleanup(void)
 	}
 }
 
+int last_stage_init(void)
+{
+	if (gd->flags & GD_FLG_COLD_BOOT)
+		timestamp_add_to_bootstage();
+
+	board_final_cleanup();
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	return 0;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 233a6c8..1482153 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -661,10 +661,20 @@ void show_boot_progress(int val)
 }
 
 #ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
 	write_tables();
 
+	board_final_cleanup();
+
 	return 0;
 }
 #endif
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 783be69..7cf9de4 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -26,14 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define COMMAND_LINE_OFFSET 0x9000
 
-/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
- */
-__weak void board_final_cleanup(void)
-{
-}
-
 void bootm_announce_and_cleanup(void)
 {
 	printf("\nStarting kernel ...\n\n");
@@ -45,7 +37,6 @@ void bootm_announce_and_cleanup(void)
 #ifdef CONFIG_BOOTSTAGE_REPORT
 	bootstage_report();
 #endif
-	board_final_cleanup();
 }
 
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
-- 
cgit v0.10.2


From 10d569ea1a6083eec6022dfd1e6b35e74c962ee3 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:44:57 -0700
Subject: x86: Fix up PIRQ routing table checksum earlier

PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksum field not being zero before fix up, since
the checksum has already been calculated in the first run.

To fix this, move the checksum fixup to create_pirq_routing_table(),
so that copy_pirq_routing_table() only does what its function name
suggests: copy the table to somewhere else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 86183b0..df3cd0a 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -13,6 +13,7 @@
 #include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
+#include <asm/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -214,6 +215,9 @@ static int create_pirq_routing_table(struct udevice *dev)
 
 	rt->size = irq_entries * sizeof(struct irq_info) + 32;
 
+	/* Fix up the table checksum */
+	rt->checksum = table_compute_checksum(rt, rt->size);
+
 	pirq_routing_table = rt;
 
 	return 0;
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index 3cc6adb..a93d355 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -10,7 +10,6 @@
 #include <pci.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
-#include <asm/tables.h>
 
 static bool irq_already_routed[16];
 
@@ -111,9 +110,6 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
 {
 	struct irq_routing_table *rom_rt;
 
-	/* Fix up the table checksum */
-	rt->checksum = table_compute_checksum(rt, rt->size);
-
 	/* Align the table to be 16 byte aligned */
 	addr = ALIGN(addr, 16);
 
-- 
cgit v0.10.2


From 548344912f791ff7f7f932afdaf669f45a20448b Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:44:58 -0700
Subject: x86: Compile coreboot_table.c only for SeaBIOS

coreboot_table.c only needs to be built when SeaBIOS is used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index ce5eb82..e17f0bb 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,7 +10,7 @@ obj-y += bios_asm.o
 obj-y += bios_interrupts.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cmd_boot.o
-obj-y	+= coreboot_table.o
+obj-$(CONFIG_SEABIOS) += coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
 obj-y	+= e820.o
 obj-y	+= gcc.o
-- 
cgit v0.10.2


From 789b6dceccbb852b0be235334b713467f88e2f8e Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:44:59 -0700
Subject: x86: Prepare configuration tables in dedicated high memory region

Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration
tables via normal malloc(). To simplify, use a dedicated memory
region which is reserved on the stack before relocation for this
purpose. Add functions for reserve and malloc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d0f502..2ba36b7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -531,6 +531,20 @@ config SEABIOS
 
 	  Check http://www.seabios.org/SeaBIOS for details.
 
+config HIGH_TABLE_SIZE
+	hex "Size of configuration tables which reside in high memory"
+	default 0x10000
+	depends on SEABIOS
+	help
+	  SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
+	  configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
+	  puts a copy of configuration tables in high memory region which
+	  is reserved on the stack before relocation. The region size is
+	  determined by this option.
+
+	  Increse it if the default size does not fit the board's needs.
+	  This is most likely due to a large ACPI DSDT table is used.
+
 source "arch/x86/lib/efi/Kconfig"
 
 endmenu
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 15ccf9b..e036f74 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -295,6 +295,25 @@ struct cbmem_entry {
 #define CBMEM_ID_NONE			0x00000000
 
 /**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return:	always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes:	size of configuration table to be allocated
+ * @return:	pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
+/**
  * write_coreboot_table() - write coreboot table
  *
  * This writes coreboot table at a given address.
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3bc2ac2..7434f77 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,10 @@ struct arch_global_data {
 	char *mrc_output;
 	unsigned int mrc_output_len;
 	ulong table;			/* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+	u32 high_table_ptr;
+	u32 high_table_limit;
+#endif
 };
 
 #endif
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
index cb45a79..ceab3cf 100644
--- a/arch/x86/lib/coreboot_table.c
+++ b/arch/x86/lib/coreboot_table.c
@@ -9,6 +9,37 @@
 #include <asm/coreboot_tables.h>
 #include <asm/e820.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int high_table_reserve(void)
+{
+	/* adjust stack pointer to reserve space for configuration tables */
+	gd->arch.high_table_limit = gd->start_addr_sp;
+	gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
+	gd->arch.high_table_ptr = gd->start_addr_sp;
+
+	/* clear the memory */
+	memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE);
+
+	gd->start_addr_sp &= ~0xf;
+
+	return 0;
+}
+
+void *high_table_malloc(size_t bytes)
+{
+	u32 new_ptr;
+	void *ptr;
+
+	new_ptr = gd->arch.high_table_ptr + bytes;
+	if (new_ptr >= gd->arch.high_table_limit)
+		return NULL;
+	ptr = (void *)gd->arch.high_table_ptr;
+	gd->arch.high_table_ptr = new_ptr;
+
+	return ptr;
+}
+
 /**
  * cb_table_init() - initialize a coreboot table header
  *
-- 
cgit v0.10.2


From 0c2b7eef97b00c3d1e5545518b2647b8fbf42537 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:00 -0700
Subject: x86: Unify reserve_arch() for all x86 boards

Instead of asking each platform to provide reserve_arch(),
supply it in arch/x86/cpu/cpu.c in a unified way.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 25382f9..b31f24e 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -53,14 +53,6 @@ int arch_misc_init(void)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
 #endif
 
 void reset_cpu(ulong addr)
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 4bf5d15..e7befde 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -190,11 +190,6 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 int dram_init(void)
 {
 	struct pei_data _pei_data __aligned(8);
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 1482153..2e27d78 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -29,6 +29,7 @@
 #include <asm/lapic.h>
 #include <asm/microcode.h>
 #include <asm/mp.h>
+#include <asm/mrccache.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
@@ -751,3 +752,14 @@ int cpu_init_r(void)
 
 	return 0;
 }
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	return mrccache_reserve();
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e35e543..9d9f63d 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -201,11 +201,6 @@ static int recovery_mode_enabled(void)
 	return false;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
 	const void *data;
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index afb3463..cf3fe7f 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -360,12 +360,3 @@ void board_final_cleanup(void)
 
 	return;
 }
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
-- 
cgit v0.10.2


From d19c90747d8975a523489f863984c521ae72ce39 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:01 -0700
Subject: x86: Reserve configuration tables in high memory

When SeaBIOS is on, reserve configuration tables in reserve_arch().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 2e27d78..e522ff3 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,6 +25,7 @@
 #include <errno.h>
 #include <malloc.h>
 #include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
@@ -757,9 +758,13 @@ int cpu_init_r(void)
 int reserve_arch(void)
 {
 #ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
+	mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+	high_table_reserve();
 #endif
+
+	return 0;
 }
 #endif
-- 
cgit v0.10.2


From 644a76742c85ae8bbdd9fcd00d06b7099015d593 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:02 -0700
Subject: x86: Use high_table_malloc() for tables passing to SeaBIOS

Now that we already reserved high memory for configuration tables,
call high_table_malloc() to allocate tables from the region.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 1213a9c..f92111e 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <asm/sfi.h>
 #include <asm/mpspec.h>
 #include <asm/smbios.h>
@@ -81,9 +80,8 @@ void write_tables(void)
 
 #ifdef CONFIG_SEABIOS
 		table_size = rom_table_end - rom_table_start;
-		high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
+		high_table = (u32)high_table_malloc(table_size);
 		if (high_table) {
-			memset((void *)high_table, 0, table_size);
 			table_write_funcs[i](high_table);
 
 			cfg_tables[i].start = high_table;
-- 
cgit v0.10.2


From 6aef68dc36bc93e1c32c1f7119b580f5eda92182 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:03 -0700
Subject: x86: acpi: Switch to ACPI mode by ourselves instead of requested by
 OSPM

Per ACPI spec, during ACPI OS initialization, OSPM can determine
that the ACPI hardware registers are owned by SMI (by way of the
SCI_EN bit in the PM1_CNT register), in which case the ACPI OS
issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit
effectively tracks the ownership of the ACPI hardware registers.

However since U-Boot does not support SMI, we report all 3 fields
in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following
the spec who says: these fields are reserved and must be zero on
system that does not support System Management mode.

U-Boot seems to behave in a correct way that the ACPI spec allows,
at least Linux does not complain, but apparently Windows does not
think so. During Windows bring up debugging, it is observed that
even these 3 fields are zero, Windows are still trying to issue SMI
with hardcoded SMI port address and commands, and expecting SCI_EN
to be changed by the firmware. Eventually Windows gives us a BSOD
(Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start.

To fix this, turn on the SCI_EN bit by ourselves. With this patch,
now U-Boot can install and boot Windows 8.1/10 successfully with
the help of SeaBIOS using legacy interface (non-UEFI mode).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index ff4802a..56aa282 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -296,6 +296,9 @@ struct acpi_mcfg_mmconfig {
 	u8 reserved[4];
 };
 
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN		(1 << 0)
+
 /* These can be used by the target port */
 
 void acpi_fill_header(struct acpi_table_header *header, char *signature);
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index be7b824..855d4a0 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <asm/acpi_table.h>
+#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/tables.h>
 
@@ -301,6 +302,25 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 	header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
+static void enter_acpi_mode(int pm1_cnt)
+{
+	/*
+	 * PM1_CNT register bit0 selects the power management event to be
+	 * either an SCI or SMI interrupt. When this bit is set, then power
+	 * management events will generate an SCI interrupt. When this bit
+	 * is reset power management events will generate an SMI interrupt.
+	 *
+	 * Per ACPI spec, it is the responsibility of the hardware to set
+	 * or reset this bit. OSPM always preserves this bit position.
+	 *
+	 * U-Boot does not support SMI. And we don't have plan to support
+	 * anything running in SMM within U-Boot. To create a legacy-free
+	 * system, and expose ourselves to OSPM as working under ACPI mode
+	 * already, turn this bit on.
+	 */
+	outw(PM1_CNT_SCI_EN, pm1_cnt);
+}
+
 /*
  * QEMU's version of write_acpi_tables is defined in
  * arch/x86/cpu/qemu/acpi_table.c
@@ -400,5 +420,11 @@ u32 write_acpi_tables(u32 start)
 
 	debug("ACPI: done\n");
 
+	/*
+	 * Other than waiting for OSPM to request us to switch to ACPI mode,
+	 * do it by ourselves, since SMI will not be triggered.
+	 */
+	enter_acpi_mode(fadt->pm1a_cnt_blk);
+
 	return current;
 }
-- 
cgit v0.10.2


From 17b63c80bffbaad344a4f6dd2363830e13ed8c03 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:04 -0700
Subject: x86: acpi: Remove the unnecessary checksum calculation of DSDT

The generated AmlCode[] from IASL already has the calculated DSDT
table checksum in place. No need for us to calculate it again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 855d4a0..1c57094 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -382,12 +382,6 @@ u32 write_acpi_tables(u32 start)
 			(char *)&AmlCode + sizeof(struct acpi_table_header),
 			dsdt->length - sizeof(struct acpi_table_header));
 		current += dsdt->length - sizeof(struct acpi_table_header);
-
-		/* (Re)calculate length and checksum */
-		dsdt->length = current - (u32)dsdt;
-		dsdt->checksum = 0;
-		dsdt->checksum = table_compute_checksum((void *)dsdt,
-				dsdt->length);
 	}
 	current = ALIGN(current, 16);
 
-- 
cgit v0.10.2


From 10fcabed8857d2c12a5806c68cf884802f975aae Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:05 -0700
Subject: x86: acpi: Remove header length check when writing tables

Before moving 'current' pointer during ACPI table writing, we always
check the table length to see if it is larger than the table header.
Since our purpose is to generate valid tables, the check logic is
always true, which can be avoided.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 1c57094..ffb4678 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -376,13 +376,11 @@ u32 write_acpi_tables(u32 start)
 	debug("ACPI:    * DSDT\n");
 	dsdt = (struct acpi_table_header *)current;
 	memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
-	if (dsdt->length >= sizeof(struct acpi_table_header)) {
-		current += sizeof(struct acpi_table_header);
-		memcpy((char *)current,
-			(char *)&AmlCode + sizeof(struct acpi_table_header),
-			dsdt->length - sizeof(struct acpi_table_header));
-		current += dsdt->length - sizeof(struct acpi_table_header);
-	}
+	current += sizeof(struct acpi_table_header);
+	memcpy((char *)current,
+	       (char *)&AmlCode + sizeof(struct acpi_table_header),
+	       dsdt->length - sizeof(struct acpi_table_header));
+	current += dsdt->length - sizeof(struct acpi_table_header);
 	current = ALIGN(current, 16);
 
 	debug("ACPI:    * FADT\n");
@@ -395,20 +393,16 @@ u32 write_acpi_tables(u32 start)
 	debug("ACPI:    * MADT\n");
 	madt = (struct acpi_madt *)current;
 	acpi_create_madt(madt);
-	if (madt->header.length > sizeof(struct acpi_madt)) {
-		current += madt->header.length;
-		acpi_add_table(rsdp, madt);
-	}
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
 	current = ALIGN(current, 16);
 
 	debug("ACPI:    * MCFG\n");
 	mcfg = (struct acpi_mcfg *)current;
 	acpi_create_mcfg(mcfg);
-	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
-		current += mcfg->header.length;
-		current = ALIGN(current, 16);
-		acpi_add_table(rsdp, mcfg);
-	}
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+	current = ALIGN(current, 16);
 
 	debug("current = %x\n", current);
 
-- 
cgit v0.10.2


From 5a6a2c714e74ba18ebd6f890f5f60dc7f0bb0a72 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:06 -0700
Subject: x86: doc: Update information about IGD with SeaBIOS

Document how to make SeaBIOS load and run the VGA ROM of Intel
IGD device when loaded by U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.x86 b/doc/README.x86
index 25cb218..250d5a3 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -807,6 +807,30 @@ to install/boot a Windows XP OS (below for example command to install Windows).
 This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
 SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
 
+If you are using Intel Integrated Graphics Device (IGD) as the primary display
+device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
+loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
+register, but IGD device does not have its VGA ROM mapped by this register.
+Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
+which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
+
+diff --git a/src/optionroms.c b/src/optionroms.c
+index 65f7fe0..c7b6f5e 100644
+--- a/src/optionroms.c
++++ b/src/optionroms.c
+@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
+         rom = deploy_romfile(file);
+     else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
+         rom = map_pcirom(pci);
++    if (pci->bdf == pci_to_bdf(0, 2, 0))
++        rom = (struct rom_header *)0xfff90000;
+     if (! rom)
+         // No ROM present.
+         return;
+
+Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
+is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
+Change these two accordingly if this is not the case on your board.
 
 Development Flow
 ----------------
-- 
cgit v0.10.2


From da944391e8eddbd1675e980f4aba14be792177b1 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:07 -0700
Subject: x86: baytrail: Enable SeaBIOS on all boards

SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu
and Windows to a SATA drive and boot from there. Enable it on all
BayTrail boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 7758c11..9f1d7fb 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -10,6 +10,7 @@ CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 26f416c4..64fd7c9 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 5daa648..28b837d 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
-- 
cgit v0.10.2


From 206a3a424678a05f709378feac7c51ae2f491fe4 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:08 -0700
Subject: x86: doc: Mention Ubuntu/Windows installation and boot support

As of now, U-Boot can support installing and booting Ubuntu/Windows
with the help of SeaBIOS. Update the documentation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.x86 b/doc/README.x86
index 250d5a3..75762de 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -1004,12 +1004,14 @@ in the future. The status as of today is:
  * Support one static DSDT table only, compiled by Intel ACPI compiler.
  * Support S0/S5, reboot and shutdown from OS.
  * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
+   the help of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support installing and booting Windows 8.1/10 from U-Boot with the help
+   of SeaBIOS using legacy interface (non-UEFI mode).
  * Support ACPI interrupts with SCI only.
 
 Features not supported so far (to make it a complete ACPI solution):
  * S3 (Suspend to RAM), S4 (Suspend to Disk).
- * Install and boot Ubuntu 14.04 (or above) from U-Boot with legacy interface.
- * Install and boot Windows 8.1/10 from U-Boot with legacy interface.
 
 Features that are optional:
  * ACPI global NVS support. We may need it to simplify ASL code logic if
@@ -1021,8 +1023,10 @@ Features that are optional:
    support SMI (a legacy-free system).
 
 So far ACPI is enabled on BayTrail based boards. Testing was done by booting
-a pre-installed Ubuntu 14.04 from a SATA drive. Most devices seem to work
-correctly and the board can respond a reboot/shutdown command from Ubuntu.
+a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
+Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
+devices seem to work correctly and the board can respond a reboot/shutdown
+command from the OS.
 
 TODO List
 ---------
-- 
cgit v0.10.2


From bb68dd528f841686a1778d36db38e7e06df38bc9 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:09 -0700
Subject: acpi: Quieten IASL output when 'make -s' is used

IASL compiler does not provide a command line option to turn off
its non-warning message. To quieten the output when 'make -s',
redirect its output to /dev/null.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 44534e1..97a09a2 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -326,7 +326,7 @@ $(obj)/%.S: $(src)/%.ttf
 quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
 	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
-	iasl -p $< -tc $<.tmp; \
+	iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
 $(obj)/dsdt.c:    $(src)/dsdt.asl
-- 
cgit v0.10.2


From fa427438bd3f0e2d8a6dfd0f721f52aa950b52ee Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:10 -0700
Subject: x86: baytrail: Add internal UART ASL description

BayTrail integrates an internal ns15550 compatible UART (PNP0501).
Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer
revision one IRQ4 is being used for ISA compatibility. Handle this
correctly in the ASL file.

Linux does not need this ASL, but Windows need this to correctly
discover a COM port existing in the system so that Windows can
show it in the 'Device Manager' window, and expose this COM port
to any terminal emulation application.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
index aa72085..0affa23 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -21,6 +21,10 @@ Scope (\)
 		PRTF, 8,
 		PRTG, 8,
 		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
 	}
 }
 
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 1dca977..385671c 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -14,6 +14,15 @@ Device (LPCB)
 {
 	Name(_ADR, 0x001f0000)
 
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field(LPC0, AnyAcc, NoLock, Preserve) {
+		Offset(0x08),
+		SRID, 8,
+		Offset(0x80),
+		C1EN, 1,
+		Offset(0x84)
+	}
+
 	#include "irqlinks.asl"
 
 	/* Firmware Hub */
@@ -81,6 +90,57 @@ Device (LPCB)
 		}
 	}
 
+	/* Internal UART */
+	Device (IURT)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		Method(_STA, 0, Serialized)
+		{
+			/*
+			 * TODO:
+			 *
+			 * Need to hide the internal UART depending on whether
+			 * internal UART is enabled or not so that external
+			 * SuperIO UART can be exposed to system.
+			 */
+			Store(1, UI3E)
+			Store(1, UI4E)
+			Store(1, C1EN)
+			Return (STA_VISIBLE)
+
+		}
+
+		Method(_DIS, 0, Serialized)
+		{
+			Store(0, UI3E)
+			Store(0, UI4E)
+			Store(0, C1EN)
+		}
+
+		Method(_CRS, 0, Serialized)
+		{
+			Name(BUF0, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 3 }
+			})
+
+			Name(BUF1, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 4 }
+			})
+
+			If (LLessEqual(SRID, 0x04)) {
+				Return (BUF0)
+			} Else {
+				Return (BUF1)
+			}
+		}
+	}
+
 	/* Real Time Clock */
 	Device (RTC)
 	{
-- 
cgit v0.10.2


From 7bfe0da4d21a1f62d65210779b073d8ff2e1ab33 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:11 -0700
Subject: x86: baytrail: Add GPIO ASL description

Since BayTrail, Intel starts to use new GPIO IPs in their chipset.
This adds the GPIO ASL, so that OS can load corresponding drivers
for it. On Linux, this is BayTrail pinctrl driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644
index 0000000..ef340f3
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 1)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 2)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 3)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
index bd72842..6bc82ec 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -27,6 +27,9 @@ Method(_WAK, 1)
 Scope (\_SB)
 {
 	#include "southcluster.asl"
+
+	/* ACPI devices */
+	#include "gpio.asl"
 }
 
 /* Chipset specific sleep states */
-- 
cgit v0.10.2


From efd4be4c82daeab0df91e034e505b1bf8cbcba84 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 11 May 2016 07:45:12 -0700
Subject: x86: doc: Add porting hints for ACPI with Windows

Windows might cache system information and only detect ACPI changes
if you modify the ACPI table versions.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.x86 b/doc/README.x86
index 75762de..4d50feb 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -982,6 +982,12 @@ transformations. Remember to add attribution to coreboot for new files added
 to U-Boot. This should go at the top of each file and list the coreboot
 filename where the code originated.
 
+Debugging ACPI issues with Windows:
+
+Windows might cache system information and only detect ACPI changes if you
+modify the ACPI table versions. So tweak them liberally when debugging ACPI
+issues with Windows.
+
 ACPI Support Status
 -------------------
 Advanced Configuration and Power Interface (ACPI) [16] aims to establish
-- 
cgit v0.10.2


From 0fbdaa0e079b0bd83caa5a34ac6c52689e369bb3 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:25 -0700
Subject: acpi: Clean IASL generated intermediate files

For boards that support ACPI, there are dsdt.aml, dsdt.asl.tmp and
dsdt.c in the board directory after a successful build. These are
intermediate files generated by IASL, and should be removed during
a 'make clean'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/Makefile b/Makefile
index 954a865..4dc179b 100644
--- a/Makefile
+++ b/Makefile
@@ -1452,6 +1452,7 @@ clean: $(clean-dirs)
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
+		-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
 		-o -name '*.gcno' \) -type f -print | xargs rm -f
 
 # mrproper - Delete all generated files, including .config
-- 
cgit v0.10.2


From 2baf3a5584b5bea0f433d3cc6e217066b88e69ed Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:26 -0700
Subject: x86: crownbay: Disable boot stage support

It is observed that when enabling boot stage support, occasionally
the board reboots during boot over and over again, and eventually
boots to shell. This was seen on my board, but not on Jian's board.
Debugging shows that the TSC timer calibration against PIT fails
as boot stage APIs utilize timer in a very early stage and at that
time TSC/PIT may not be stable enough for the calibration to pass.

Disable it for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Jian Luo <Jian.Luo4@boschrexroth.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 7c6b692..8e086c5 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -8,8 +8,6 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -24,7 +22,6 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-- 
cgit v0.10.2


From 5c60a3abde29844f27c227adda1be088ea80e7dd Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:27 -0700
Subject: x86: Add some notes for MRC cache with Intel FSP

MRC cache relies on Intel FSP to produce a special GUID that
contains the MRC cache data. Add such information in the
CONFIG_ENABLE_MRC_CACHE help entry.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 2ba36b7..65cbb9c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -274,6 +274,13 @@ config ENABLE_MRC_CACHE
 	  to be used for speeding up boot time on future reboots and/or
 	  power cycles.
 
+	  For platforms that use Intel FSP for the memory initialization,
+	  please check FSP output HOB via U-Boot command 'fsp hob' to see
+	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+	  If such GUID does not exist, MRC cache is not avaiable on such
+	  platform (eg: Intel Queensbay), which means selecting this option
+	  here does not make any difference.
+
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	depends on !HAVE_FSP
-- 
cgit v0.10.2


From c88f508f692671bfed4cc9982671998c001fbc1d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:28 -0700
Subject: x86: baytrail: Update to latest microcode

Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907
(for CPUID 30679).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/microcode/m0130673325.dtsi b/arch/x86/dts/microcode/m0130673325.dtsi
new file mode 100644
index 0000000..8063a75
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673325.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x325>;
+intel,date-code = <0x11192014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x5edcd570>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x25030000	0x14201911	0x73060300
+	0x70d5dc5e	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x25030000
+	0x00000000	0x00000000	0x19111420	0x11320000
+	0x01000000	0x73060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0xfff634fa	0x937ca2ab	0xb28d19b6	0xdefc54a7
+	0xd8df0b32	0x13e9a2a8	0x7b7cb24d	0xd588d3a7
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x1f504653	0xe21b5652	0xe97686b4
+	0x5f67c59f	0xa9b26fd4	0x9dc84f1a	0x0f02451e
+	0x0a821675	0x12547714	0xefe1084e	0x91260f23
+	0x17e46cf5	0x3dad6dd8	0x4e16210b	0x0472bd56
+	0xd3fca8a6	0xfa3f5184	0x87d91976	0xa7b008eb
+	0x17bad553	0x89835b41	0x32e7d87c	0xdfcf298a
+	0x6a740196	0x0405a296	0x4f830df5	0xfcf047f1
+	0xca0e7a10	0x8d0afa7b	0x08facdae	0xcf7bbe22
+	0x8e08e283	0x6b51333b	0x452cf734	0x03da5390
+	0x7075365b	0x402e71ba	0x4a8d4547	0x0da62d39
+	0x3fcae342	0xe8cb1437	0x6ddc21bd	0xe22b5edb
+	0x319decc1	0x6c558ad3	0x3b44648a	0x8cdf8642
+	0x5a3a8cdf	0x6aae06b2	0x7360d1a5	0x774351c9
+	0x88681d42	0x466d3573	0x6d8538cb	0xa3350f1e
+	0x7b431d3c	0x21074f32	0x6955a68f	0xa3988611
+	0xad1c79d3	0xe00884c6	0x12e5baa8	0x7dad4109
+	0x61d16a48	0xd2074a23	0x58611da6	0xad7b774e
+	0x90a80987	0x05aca95d	0x482b51ca	0xbb8fe27d
+	0x2abe5e48	0x590c8b98	0xef745dbf	0xce17a591
+	0x6607216b	0xbefec476	0x7a8b08a9	0xb281bfc4
+	0x76f7dc81	0xaacd78a8	0x38cd6888	0x9636aa2e
+	0x7035053d	0x069305f5	0x0da92823	0x46d344df
+	0xce46f308	0x1fcca5d0	0xf4b0daa0	0xed8ecd8e
+	0xdae9e33d	0x69be5bef	0xc545c95b	0xadeaeeb8
+	0xdd903783	0x5a2f3287	0x73865fd0	0x865d709d
+	0x1ed58537	0xe44c821a	0xc9ad0d97	0xe81b9851
+	0x552cf1e7	0x03a3b2dc	0x219194a0	0xd8875c82
+	0xe39b25b7	0x61149b84	0x79a99812	0x287eada3
+	0x057cc940	0x0ed85405	0xf4cbb20d	0x8d87a099
+	0x2018b6ae	0xd14f3646	0x35bf5bd8	0x82931be1
+	0x52234bd1	0x9143a967	0xd9d1a3d4	0x869c266c
+	0xcaff55f0	0x64ad39c2	0x02435da4	0x32e2907c
+	0xbc2682a9	0x60863cea	0x163028c0	0x007fc9fd
+	0x6553eb56	0xab00c11c	0x3aa77e22	0x87f722d4
+	0x004850a6	0x5460e040	0x9e91042c	0x46dd43c7
+	0x3b05c92f	0x060ce074	0x62730a12	0xc6d47872
+	0x03d26f06	0xf7b3d04f	0x92adc672	0xc31d8130
+	0xd40eab22	0x616b7f8f	0x56b2c742	0xde6015c3
+	0xc10c0d02	0x3ab28f97	0xa091494f	0x1fa0c28b
+	0xc76c5661	0x27effd8f	0x3de80c1e	0x5713a42c
+	0xd9114db2	0x17ab3314	0x0e3aea42	0x60712f1f
+	0x4a7d4389	0x9db1857c	0x1103baa8	0x579462a6
+	0x82ac5a7e	0xda8d9f67	0x835bed5a	0x08705479
+	0xbf4bd494	0x082d8b22	0x408878b0	0xa698e9d8
+	0x27fba6da	0x2308fb71	0xcc1b9c9c	0x5200bd18
+	0xf1baf601	0xe67b1d1b	0xf3c95153	0xf8fb4f22
+	0x2859e330	0x3e7bc864	0x02c88201	0xf835c5f7
+	0xcefd31e1	0x4c430b43	0xce13d99c	0xf9aa01ab
+	0x9f5c0d3a	0xbf06696f	0xc834c22c	0x145cf026
+	0xb45e1f1b	0x97302dd5	0x5b5d108a	0xffde5401
+	0xffbd2caf	0x8eb5c823	0x3f113711	0x144ec354
+	0xab3864a7	0xeee70354	0x208ea79c	0x1b2c7364
+	0xc3cb82d0	0x21d9b3bc	0x27846121	0x50bd8910
+	0x43a2616a	0xface9686	0xe12195b9	0xde4639d9
+	0x0b88b493	0x32b1685e	0xbd782bea	0xc674188e
+	0x23425d26	0x9d2d3c81	0x33b3a260	0x4ebebf2f
+	0x6a634d1f	0xb977b1c1	0x476223c5	0x654c5461
+	0xbeaa9c98	0x75242b30	0x26061148	0x69889154
+	0x910a2132	0x07df3136	0x372a7cf0	0x58541d8f
+	0x65ce78aa	0x0c6e4ff7	0xab8c31b6	0xbe39960d
+	0x63bc072d	0x53872b7c	0x959f3049	0xc13ba7a0
+	0xd7111cd7	0x5e68763f	0x923dc674	0xdb2e8a4d
+	0x5c2cd5e0	0xd93be0e2	0x1bccff32	0xbbdffc8a
+	0x1641ff1b	0xeab24fc7	0x70aff37e	0xc87fe4f8
+	0x32afd630	0x060dbdf9	0x6e119a8c	0x987e51c5
+	0x57abb8f6	0x15b3755b	0x938f709a	0x7c4b5522
+	0xfd376691	0xd909457d	0x58656778	0x3bdee518
+	0xaf65afd2	0xe1cd74ec	0xd2bc8a3a	0x9aa30f8b
+	0x6e1f183f	0xc2fa7bf8	0xa60385fd	0xe0320d46
+	0x2e5bc0df	0xf95b8c37	0xfa760bc7	0xc8960509
+	0xdebed2f2	0x560ac9de	0xb3ac0e62	0xefe328dc
+	0x358d5330	0x72c31526	0x5932780a	0xb3b824b4
+	0xda37daae	0x69dd74c1	0x41c91b5c	0x8180b956
+	0xc69574b5	0x1830993b	0x0d5ef14b	0xa8dec45f
+	0x5c4019ed	0x559e7b51	0xd07a3c14	0x49208a2b
+	0x5265dad8	0x1b9826c0	0xb8cc3edf	0x63ccaf33
+	0xdfdfb78b	0x3292f976	0x9f1ddbc1	0x2e3bfa8f
+	0xc4b5a941	0xd8b1fcea	0x68764a2c	0xbec828e1
+	0x07db4118	0x2022cfd1	0x6be82389	0x7ecb046a
+	0xd31a639f	0xa0f50a18	0xbb4dc035	0x765a6e5f
+	0x59fe51c8	0xd2138643	0xccfeebae	0x234c0440
+	0x49bcdabd	0x88e86cb6	0x48760e88	0xcc34f20c
+	0x0977dead	0xf3f0d324	0x736f4df6	0x0a94f658
+	0x0bbb01cb	0xe962549c	0x6a1c39c6	0xbec25a26
+	0x4cb71dd7	0xf1043105	0xba0f3726	0xc97645e3
+	0x23d4b508	0x7c0827ae	0x097f96f0	0x0a054e0a
+	0x79e7a543	0xbedbd7d1	0x52d2b51f	0xebabfee4
+	0x1f0e76e2	0xa07922a8	0x3a630243	0x41b8b460
+	0x11f8e1be	0x97ab45cf	0xd952588f	0x70461a90
+	0xdf62afd8	0x169cd499	0xc9a38028	0xe2d36ebf
+	0xa86477c5	0x1890d4fb	0xb78c189e	0x6002b07d
+	0x346599a1	0x998b8687	0xa073f3ff	0x561c2a62
+	0xc4904bcd	0x59a5194c	0x6b2d285d	0x3c7208dd
+	0x1a2e9b5e	0x7a7732a8	0x2c803c45	0xb307e8fe
+	0x9a402093	0x521740de	0xb25a372e	0x1abeec65
+	0xd9f84a17	0xed465fd4	0xfcc2e034	0xdc9bc727
+	0x9607ab7b	0xe0bd62d8	0x8630873a	0x361b3b75
+	0x603255fa	0xd815876b	0x32d0e705	0x5f99a520
+	0xf15a63b3	0x83f3009f	0x7ad4b916	0x1ba9093c
+	0x824dc86d	0xcd792af9	0x8d1e623d	0xad4877c1
+	0x2c09f508	0xab062540	0x242c5f5e	0xb46796bd
+	0x0bbc1a5d	0x02be8545	0x4ad68f23	0x370b4b1b
+	0xc16c7ebf	0x8b65ef74	0x11b64ded	0xc00f5586
+	0x41d6033a	0x0f79c8e9	0x356094c0	0xff3ec289
+	0x11a0d26f	0x347ebbef	0x23f2b11a	0xb6b15aca
+	0xe6856320	0xacecde47	0x513fbdea	0x7d7ac026
+	0xb72b0011	0x7d8cac25	0x222704f3	0xabc6b166
+	0x60995d26	0x95ccf438	0xce21d44f	0x27e15e98
+	0x9e229da5	0x929009b0	0xe79afdb0	0xf91bcab4
+	0xe5894312	0xe98d7607	0xb2bd2408	0x5abc5003
+	0x532b2c0a	0xb41dbdf7	0x248d6b00	0x7b811187
+	0xff7afcb3	0x818c2c38	0xacc7a704	0xaa14713a
+	0xeed076d3	0xcca8d4aa	0xd90177c0	0x9fcc01ae
+	0x8edd4189	0x1c896cfe	0xc4856a25	0xbeeb2217
+	0x52249b24	0xad45ff42	0xb43ae3a7	0x4bf0df57
+	0x91e369cf	0xcfafc488	0x6c218f44	0x0aab7b09
+	0x5f9c2410	0x87cdac03	0x986e83cd	0x56a7bba7
+	0xc7d2270b	0x467b995a	0x4b398fc4	0x64f04f87
+	0x30334708	0x8d0c7e49	0x69c792c2	0x725eba77
+	0x6870df0c	0x84d8a30c	0x0c5c6ac2	0xd9bc43cb
+	0xc52ab350	0x64878641	0xef306551	0xcfe54739
+	0x1aa176e8	0x6f1a7e1a	0x965be809	0x21e345f9
+	0x9ad41590	0x5e5de630	0x82cc1207	0x6120734f
+	0x846449fb	0x9d822218	0x2c8e025f	0x747f180c
+	0x90a64365	0xec79c646	0xaf2a29b0	0xb5a4cfa3
+	0x4f5b82de	0x0b7ad494	0x3b02b3e0	0xe5d96463
+	0x241aa4f3	0xefeeed3d	0x6e6d49ff	0x2d45821c
+	0x4598f881	0x7de00efb	0x25509321	0xc64ceb14
+	0x218dde9d	0x59c3cf6b	0xf8f702e6	0x3e0cf0c0
+	0x178f8a4a	0xc8aa3338	0xdcb7989d	0x297f30a0
+	0x270b7ea6	0xceff00a3	0x22ec287d	0x50673360
+	0x1fccbc8f	0x66c3805a	0x8a327234	0x52e1978f
+	0x538b121c	0x1f2fa957	0xeada2b4e	0x29423125
+	0x81d3a179	0x968b4097	0x3522324d	0x5cccf20c
+	0xa6adfc16	0x3d1cb3b9	0xbaefea60	0x57978720
+	0xf5eb4b9c	0x5a8b3acf	0x4f3ac467	0x94a7e4ca
+	0xb4100044	0x54fc2e4c	0x16ec9a22	0x3aecc34a
+	0x6df7f52a	0xe1279f5c	0xaa25ad1a	0x907baa13
+	0x51c19956	0x35987a2e	0x1adbb651	0xaf0a5285
+	0x83ce12f0	0xcbabf9e6	0xfaa1cbff	0x73139922
+	0xc6f5b18a	0x9f91c4fd	0x6583a1bf	0xa144eed0
+	0xc9f2b43b	0x249407d3	0xe3520b2c	0x60dc9aba
+	0x53ff14c4	0x24133ac0	0x4b6a4452	0xe0aea55c
+	0x884302dc	0x24d8ced4	0x3db6976b	0x48aad95a
+	0x7e4defba	0x80215bbf	0x62241272	0x0747edc0
+	0x32206c16	0xffebdcc1	0xdd1662c9	0x1bd3eb01
+	0x785d4a0f	0x4b37087b	0xce5142e8	0x1262ef36
+	0xb04665e5	0x84491927	0x9df53726	0x8d175409
+	0x79fcc87b	0x647f1da3	0x68c89316	0x14926e0b
+	0xf7ca65bb	0x20634f45	0xbd13da4c	0x683991d5
+	0x81cab56c	0xeb840c6a	0x8954031e	0x06deeb42
+	0x92f26c77	0x6b2de0c6	0x80a23d71	0xd11b9d58
+	0x703498a0	0xacade451	0x797bf69b	0x0f6b0db2
+	0x92430faa	0x1756940d	0x99aa9ef0	0xcee8c383
+	0x8bc70735	0x19b263e3	0x36a5345d	0x271c893d
+	0xa32a1999	0x0345759b	0x3f89c616	0x52132086
+	0x10d16c86	0xd7425739	0x961a376a	0x3c4f62a9
+	0x64c0bbe2	0xbf9fcf69	0x3b9055a6	0x88ce084f
+	0x12d088cc	0x2ca9dba5	0x01e2d480	0x7510c47a
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+	0x70b4ef71	0xe68fd886	0xbf9813e5	0xfbea41ec
+	0x0e9c7205	0x4f4324b3	0xe9f241c0	0x59848c26
+	0xa6c883b0	0x6fed019d	0x3bea1228	0xd636e300
+	0x6950359e	0xcf52052c	0x1b528057	0x06fe6742
+	0x04965c8d	0x9a7b26c5	0xc99230d8	0xb579c7aa
+	0xe24a7255	0xe814e07a	0x76f58992	0xbad495de
+	0x55700746	0xfaf4da35	0xb5536992	0x1008288a
+	0xd867fd0b	0xb1c9720c	0x047d6414	0x561bdcc4
+	0x74e334f1	0xb66a42e7	0xc08e03a2	0x859a375c
+	0x2d6c3b8b	0x0aa6b45f	0xc97b7c6b	0x5765735c
+	0x5367cf95	0xd957151b	0xb6354238	0x7c9dbd21
+	0x97fbcb95	0x110361bb	0x2394edad	0xbf8e18b3
+	0x2d4d9bd2	0x24b42b08	0xace76b11	0x2b8fb939
+	0x04105821	0x79af703d	0x434c240e	0x2a019bf0
+	0x02a38fc2	0x9c640e05	0xdde8995a	0x3b8c0b1d
+	0xb44190f0	0x3c84367d	0xdbb9bb01	0x27c42ea7
+	0x87f24ef1	0xc9abb097	0xe4df5c7b	0x45e04755
+	0xe29ab2aa	0x29be8522	0x4efa4f5f	0x2b4522d2
+	0x67f465fd	0x4171364a	0xd2bed8f0	0x477e8b5c
+	0x982c0339	0x48fcc0aa	0x06206cf1	0x4c132f24
+	0xc2a78b32	0x18a3806e	0x84551ba3	0xbc8dab25
+	0x3cea4ede	0xbe3cb62f	0x7be253ed	0x828e2dca
+	0xae76b847	0xc018fe6f	0x09e3d2ab	0xfd775e4c
+	0x80f2595b	0x1a1d440b	0xc48f9889	0x52d1cadb
+	0x99fd2c1a	0x3d700d86	0x079d1761	0x6811c4eb
+	0xcc2f677b	0xe5422423	0x11a606e9	0x3fd6ea3d
+	0xf9ae700e	0x09aca633	0xa7097790	0x5db8d41b
+	0x34941e1b	0x3fc50d4c	0x2fd2cf3d	0xa60aa40a
+	0xed6381c1	0xb192e754	0x3248af41	0xe0cc843e
+	0xef3c9504	0x3712da7c	0x9fffb613	0xdef40782
+	0x86f9bd62	0xbd8a3260	0xf6dcbb87	0xf9a264e7
+	0x3bb46aee	0x6f92d88e	0x6b0861e4	0x5ab7d4cb
+	0x2f1cf740	0x8213ac78	0xa34f0812	0x4d7db7bb
+	0x20d1abcc	0x9c519247	0xbc708c1a	0x66871981
+	0xc436271e	0x88247723	0x2996c404	0xca9c48f6
+	0xdcea7c3d	0xf6cdd451	0xbab6a23f	0xf064060b
+	0x3c0d3775	0x3a7ccc2d	0x5d056c98	0xa6521199
+	0x7f3b8753	0x3ca8407a	0x3097264f	0x60c75837
+	0x96e43535	0x5d17c5bd	0x89bb2825	0xd35fac11
+	0x1c323feb	0xe8fd05e7	0xcad8184e	0x23456746
+	0x6e4f1d7d	0xfbfada38	0x20faac8d	0xdcedab37
+	0xf094bd0c	0x7d4e750c	0xbd7ef698	0x0125c05a
+	0x17d840cc	0xf44bd1bc	0x236e7f10	0xdd53c6ac
+	0xb0bc6a1e	0x019b1a51	0xfd99d0b1	0xb723b517
+	0x728e0e9f	0x4280e2d0	0x8da35086	0x2e3cb572
+	0x2a53e018	0x6f7a3e41	0x7afe2ee6	0xe4efc53a
+	0xe2ed04c6	0x67112c67	0xe7e43b4a	0x03f680d7
+	0xe3434120	0xe2c12215	0x63ff546e	0x4d87e2b7
+	0x6f95093f	0x7c7a5e18	0xef98c38b	0x8ccf2684
+	0xf4619327	0x148676c5	0x4be2254a	0xcda85631
+	0x00ae4a2c	0x2df961dc	0x85b6fd89	0x1512b1fb
+	0xc17a7547	0xbd062ec9	0x91229a47	0xf6d4b08c
+	0xf7d3c4f1	0x4d951e94	0x62c8a9e9	0xd7df6f2a
+	0xce34f11d	0xc04b655f	0xfcf369b9	0x40eb0ec3
+	0xf7b55c23	0x8edce54f	0xba8ce0db	0x2a5e5a92
+	0x3b243dcc	0xbcc8c5d0	0x906db8bd	0x6a0aee9f
+	0x9e6c3df4	0x16f2252d	0xd389126d	0x5118a5bc
+	0xa75cc327	0x559dde05	0x5bb43b00	0x7fbe942e
+	0xa24e752a	0xabbfe05c	0x916daec7	0x8817b357
+	0x5be9fbfb	0x6e8bc90d	0xcdf7cb49	0x0b28069a
+	0x1922e927	0x24713a66	0xb9c800e5	0x63968dee
+	0x34464be9	0x712fa6d8	0x9f9c814f	0xf6121f78
+	0x12863a08	0x349158d3	0x66556d8b	0x4938c818
+	0x69374151	0x55046a98	0x94c8e4f4	0x48430cff
+	0xb885cdc4	0x762fb5b6	0xee98caee	0x8e582d5c
+	0x808ba575	0x7878cbac	0x1d257ec1	0x85bb9f16
+	0x50adfb99	0x98e3f712	0x532b6bb5	0xd3aa0b14
+	0x07369ec9	0xc6f71890	0x1bb76ff9	0x0e91023e
+	0x7d6e119a	0xe8c5f447	0x49edf0c4	0x8d380eed
+	0x99984929	0xd37dd90b	0xfffb0a41	0x69eb9ab1
+	0x67b2585d	0xe3a5a664	0x7f9d9156	0x0454b9c2
+	0x4b5d28f2	0xfa6d0a33	0x3c9206a7	0x5aa2fb75
+	0x767201c8	0x7db04d90	0xc27e89a0	0x4df1cfb8
+	0x81efb5ad	0x2eeee02b	0x42d5ef5c	0x394fdbd2
+	0x0bcc3166	0x2f43982b	0x832520df	0xdb6fb558
+	0x63fccc0d	0xc42816d3	0x5cf66464	0x2b4b89e7
+	0x2d62dcb5	0x6c4f52fb	0x6c3ac264	0xc92c6977
+	0x1f6cc458	0xd639250c	0x4044e6b0	0xc39df4c4
+	0x65595b2b	0x1c9be044	0x5242d7f4	0xec710e0e
+	0xa991869f	0xacb3cd55	0x4e82d850	0xa7ddd47c
+	0x12c0cc9d	0x8ff166b2	0x89d6bb4a	0x136ef38b
+	0x3875e7df	0x8d59d30b	0x3d22b091	0xc64b065e
+	0x73077e1e	0xcdbbe7db	0x000e842c	0xd5147941
+	0x8fbcd501	0x6d731511	0x1a45fa09	0x1579e7bb
+	0x4dfa5ed6	0x192d360a	0xc36e445d	0x6df0bb79
+	0x9c60d757	0x99067a40	0x286e1450	0x21d95d9d
+	0xbffde5f4	0x5b6e43a1	0x61b62406	0x87e27b1d
+	0x12fbc7cb	0x52332046	0xe2ac85fa	0xe6dc1b49
+	0xb04e0d61	0xf9cd9aa9	0xe56424ff	0xc5b0b353
+	0x7b99dc04	0xf8bf97d2	0x3fc86848	0x396441ff
+	0x92c981c7	0x97a58a03	0x18862056	0xc9849658
+	0x683cec3b	0x3298b913	0x1d381d39	0xbe687457
+	0x1598e8c8	0xb4944287	0x59e42ebd	0xaf631121
+	0x81c6ed2b	0x811cd718	0x9d9ece91	0x6d26ed1c
+	0xca577a45	0xe87b71a4	0xf9d884ed	0x8c88c874
+	0x452020b4	0x9e6ac4b8	0xa99fb35c	0x3d0acc96
+	0x6d0220f5	0xcd4a9041	0x0f7b3489	0x4de2fca5
+	0xd91865bf	0x7ae85bea	0xd0ac675f	0x3643cfd2
+	0x9c9e938a	0xcc24771c	0x04a8d771	0x69ea870c
+	0x536c78b1	0x9c986d53	0x188133ed	0xc2449d1a
+	0x949dcfee	0x657b7cbb	0xbac748a6	0x5469c94f
+	0x58b00d1b	0x4a95f324	0x9e3d996a	0x7d61363b
+	0x95c3b5e5	0xe0c628e5	0x89ba2777	0x92530a59
+	0xa52ed8d8	0x96f64b04	0xd7a09900	0x2b7bdcec
+	0x31ddf392	0x796d19fd	0xdbaac550	0xc1b483dc
+	0x7003a526	0x260f55db	0x2065f6ad	0x97c38ccc
+	0x2a6b7ce5	0xec4e0018	0x990007bd	0x93e4d47f
+	0x04d2536e	0x4bfd17fd	0x173af016	0x26515f4e
+	0x9051893d	0x63333e26	0xe47971be	0xd909f5f9
+	0x2f5be247	0xfade7a04	0x121542b3	0xcd5f8f3b
+	0x416d8352	0xa66d58b6	0x5656d408	0x10ee1bf2
+	0x3c65b26a	0x31dbef80	0xb3badd4d	0x388342da
+	0xc430266f	0x53fa9fe3	0xfecd7bd3	0xac043f73
+	0xc94b4ee6	0x1dd26332	0x993b8b27	0x1d78261e
+	0xbd4a0564	0x170a57fb	0xaaa7be6c	0x9bbde43e
+	0x70d16f35	0x11525ae1	0x00b8c636	0x7088bf37
+	0xed6ea850	0xaa37bc1f	0xe08e79ea	0x7d4ed426
+	0x95f8916a	0xc2fdd49f	0x1fa1bc9a	0xb759624c
+	0xd7159d5d	0x65762aba	0x50c99a62	0x8879a995
+	0x496ad905	0xcf5447b3	0x230a9e21	0xb6d586ac
+	0xccfd911b	0xa4a58d33	0xbef8ff75	0x6381b0c3
+	0x62d0e4ad	0x2f0992a0	0x27d2e923	0xc9d67860
+	0x46f394b2	0x877ea324	0x6ed5c693	0x386dbfd3
+	0x5f5c1f7b	0x1a339481	0x1cd12853	0x4da6425d
+	0xe50aa540	0x2dd400e8	0xd7b37c5f	0x52046ed3
+	0xdb24073b	0xb28cbf56	0x67e62bdb	0x32f6e9bc
+	0x8f2f443b	0xacedd944	0xfa99423f	0x3ae8d636
+	0x613a42fb	0x1a410513	0x4469e127	0x2fdb4b5e
+	0xf86ed877	0x07637d77	0xbb197929	0xa8fa021b
+	0x9a9f4341	0x35e36444	0xc6728094	0x54c438fb
+	0x17b46ef7	0x152d988b	0x42c512fd	0xcc4f36dc
+	0x1ab4ed10	0xd367833b	0x1c08b3d9	0xb5d182e1
+	0x198f9d7a	0xd68ac623	0x964db9a6	0xd6c121f9
+	0xdb56e5d9	0x69e61f26	0x6b9fe5f6	0xc414f7ed
+	0x812a505a	0x7b73b945	0x08000c8a	0x8ed6ff2e
+	0x19b9394d	0xcce2bc3a	0x46d66935	0xf3e5468b
+	0xf345f275	0x5f9bf5c1	0x46ceb342	0x45149107
+	0xc02af675	0xbf3ca371	0x55237036	0x8ae2d3bd
+	0x19b01471	0xa77a83f0	0x6b003b46	0x29a22e11
+	0x89a94839	0xd0c249a3	0xdb36a03a	0xe38f4040
+	0x88f9c8b9	0xef50fad5	0xd69b106c	0x5f314dd3
+	0xde5e9f87	0x91c24944	0x49eee859	0x2aaeaa65
+	0xab45e53c	0xf3a0e4c0	0x200a36e5	0x77e484f5
+	0xcbf8952d	0x64d6ebfc	0x1f832895	0xd835590f
+	0x13f5a770	0x190849af	0x3068c161	0x61a78e84
+	0xd7567c5c	0x4a1ab2db	0x524ae318	0xd488b5be
+	0x1703785a	0x0a1889eb	0xd39c572a	0x4f99ba34
+	0x3015e101	0x99e6ff5d	0x13cee969	0x0d66997b
+	0x8e3dafe4	0x9c0507b7	0x28cebbab	0x2e6cf3d1
+	0xb24b11bc	0xe411de4c	0x64d5f845	0xb0b20f46
+	0xa49b7b52	0x9b65793d	0x8756f69d	0x0e0bfcd9
+	0x6631f0ee	0xfea0c152	0xc54d903a	0xe05159f1
+	0xb2cd54ac	0x039a6d29	0x81cd7e6b	0x58cd335c
+	0xf6e95cc4	0xa6a02bf1	0x62e10eb8	0x0b11d249
+	0x5b52a70a	0xff2eb36e	0x9ce7f597	0xfc4421c4
+	0xba74bbfa	0x4ba989b4	0xce7c369a	0x8c149a5f
+	0x063745c9	0x4a1dc1ba	0x3c798afe	0xa47ef113
+	0x54c6c987	0xa6623430	0xed26b37f	0x0ebac834
+	0x54cb0233	0x92995cf3	0x5412dbfb	0xaf94b295
+	0x80ea9fea	0x6c776fea	0xc638768e	0x3e2cd596
+	0x8c6f6218	0xe5b70298	0xad6cb433	0x0271dd2a
+	0x25c9a276	0x24ee6a85	0xe72e9d3f	0x3bdf3f97
+	0xabf11c1e	0x99937754	0x2bb62c14	0xf3da4c81
+	0xc962c562	0x727c4e26	0x97b1c000	0x0de49161
+	0xdb8d6318	0xc9b83dd7	0x40901e67	0x68ac3dd3
+	0x217fecae	0xfa36644a	0xb9399c9f	0x620ccdbf
+	0x81fa634f	0xdb38edb1	0xf7e11418	0x1f580868
+	0x48b35cae	0x7230c6e3	0xf7cc6a25	0x440c45d7
+	0xb390e675	0x9b78318a	0x0d359239	0x97e078cc
+	0x80e65a34	0xd71dbf0b	0xd112cd54	0x53a3f81e
+	0x098f7be4	0xa11d522e	0xebbb20dd	0x2c4a78c0
+	0xd4e79e2e	0x01c919dd	0x2fa34e3f	0x6a16a7df
+	0xb81c9cf9	0x472fd48e	0xd197dae0	0x94cc62c4
+	0xe052d018	0x1ca9bf15	0xb44ddb70	0x814d856c
+	0x68927beb	0x5622d712	0xfb289586	0xd40ab10c
+	0x4c7f3469	0x357a822a	0x717a3720	0x3f3a99ed
+	0xf13943e4	0x043dbfae	0x6fb72671	0x06bcaf58
+	0x790c1e70	0x3e8e537f	0x5a4fb50e	0xa2fe476d
+	0x9db652cf	0xace6b43f	0xd1273d75	0x88727f3f
+	0xe66f9c36	0x24339816	0x28f8dd6c	0x5a4f8879
+	0x51ebf963	0xd64769b3	0xd9006ec3	0x20bd215b
+	0xce24e7cc	0x61c00c46	0xf9b16868	0x429a54f8
+	0x328834df	0xfcdbb181	0xd782c3e9	0x6b71dbe0
+	0x70dcfe9d	0x95c1a80b	0x5ae919c7	0x7e71afab
+	0x4103d80a	0x955c62d8	0xca197e33	0x4b579a1e
+	0x94521734	0xa9bd1f4d	0x112ef524	0xbfafeec9
+	0x6358d4de	0xe68efe2d	0x93c564db	0xa3e4ac68
+	0xc61833f9	0xef2e5dbb	0x4d3a5a3d	0x30e7a355
+	0x6b1ed181	0x1e6cbb81	0xb6fa389c	0x0c7e7ee9
+	0xc20c8770	0xcb04a3ac	0xa4ba69e0	0x7e87b290
+	0x8c67e8db	0x2c3a40f7	0x366bc618	0xdeaab8e0
+	0x95d11262	0x665c9d87	0x68435cf0	0x924c1e1b
+	0xc8f8c882	0xdff0c036	0xfe411797	0x2bd049c1
+	0xf4def28d	0xd8d01637	0xc7ef2c00	0x6367f83f
+	0xd34fdf44	0xd392e10a	0x6d522ea0	0x16f8e3c6
+	0x4d9b0149	0x6ce5ac26	0x57431d08	0x77f105e2
+	0xe9f6f804	0x92dae4d9	0x63baf9f0	0x17056564
+	0x010e1d9f	0x50231c43	0x5ba79db6	0x8517839f
+	0x18afe138	0x88d3a85e	0x786ed442	0x9cf4a72b
+	0x629ebf65	0x613d8e8e	0x712a0fd8	0xbc88b08b
+	0x81ea88b3	0x3ac5f023	0xb93c236e	0x93a3468c
+	0xd86745c6	0x6df47eb2	0x10e2e256	0x2da86820
+	0x1513101f	0x38128155	0x7fbc9673	0x5e8aca10
+	0xc79677d1	0x8006a420	0x56909452	0xde047cd6
+	0x33256da8	0x63637d54	0xdbb682c2	0x9b00c56d
+	0x9f62d072	0xb7be713a	0xb0e603d8	0x047e37e3
+	0xd51ffb7a	0xeec69890	0x1e72d673	0x6d7f5c0d
+	0xa80c0473	0x12b89507	0xd605abac	0xd4c6899d
+	0x9bb98856	0xa6269a33	0xe08135cc	0x8a69b777
+	0x077837e8	0xd13014ea	0x9ca638ad	0x908e6612
+	0x5bf969fd	0xfd9da209	0x3e72a1a3	0xc7cbec2b
+	0x66cf84a1	0xd67e67eb	0x1684ed54	0x22feca3c
+	0x9c0d00c2	0x6337c641	0x89f65117	0x7fa4c657
+	0xebbd3208	0x89322dfb	0x925f82c7	0xebeef669
+	0x8cf74ade	0x55847368	0x28fd1623	0x5c2e0709
+	0xceb12802	0xbc4de4d3	0xec44bd13	0x33574d46
+	0xe89ce0f8	0xc09d2036	0xf83ce68e	0x0da18b34
+	0x30bd2849	0x252235cd	0xae7b84e6	0xb894640f
+	0x5b84fc6c	0x23f8cca0	0xd5a506ad	0x5605e837
+	>;
diff --git a/arch/x86/dts/microcode/m0130679907.dtsi b/arch/x86/dts/microcode/m0130679907.dtsi
new file mode 100644
index 0000000..30e2f9e
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130679907.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x907>;
+intel,date-code = <0x11142015>;
+intel,processor-signature = <0x30679>;
+intel,checksum = <0x1bb67b21>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x07090000	0x15201411	0x79060300
+	0x217bb61b	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x07090000
+	0x00000000	0x00000000	0x13111520	0x01320000
+	0x01000000	0x79060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x9703f29f	0x1c68d65c	0x1f15f858	0x114237f4
+	0xfef8d172	0x363b5a9d	0x4c3d9e71	0x13ff68a0
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
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+	0xd4d07268	0x1bb3faf1	0xde8dbf0f	0x2e7ba152
+	0xabc0ff05	0x6ca54fc8	0x51acd5dc	0x65a18671
+	0xa619f93a	0xa84535c1	0xa0ede59b	0x6bd55a4e
+	0x5aba8fb8	0x01cc90e7	0xc3eea3cd	0x0f503e9b
+	0xad697d5d	0x6021cacf	0x70dd0dec	0x11d7617f
+	0x19e6864a	0x6b252ab4	0x6820dba3	0x9db53d55
+	0x1108f4b2	0x71aeae7e	0xdff9a4fa	0xa724e0b9
+	0xefe50832	0x91ea4d28	0x4f02d339	0x15e0212b
+	0x2c725507	0x3de817ac	0x4fcbd836	0xf9484b90
+	0xeb9ebf31	0xcfd90e4d	0xd3d6a071	0x3dff27c3
+	0xb891858e	0x99daaeeb	0x3dc5528e	0xb2fea196
+	0x2724ae08	0x6c5845a7	0x184faafc	0x44446f10
+	0xe9d1537d	0xb0933101	0x9229e352	0x4f426c82
+	0x98147850	0xca22c0fb	0x4d414090	0x981ac8f9
+	0xb8d034af	0x6b8aa278	0x6508c7b7	0x6293fe73
+	0x66f15617	0x0679cf83	0x6a58257d	0x4deae251
+	0x6e19dc6e	0x899db947	0xcb261cce	0x9c8d3929
+	0x64a097e4	0x38acf6ab	0x07beeeb0	0x9ba17f04
+	0x6897fa21	0x1445cb4d	0x6d79f51a	0x83661214
+	0x812f8cb4	0x73a15a75	0x5d9edf24	0x490b66b2
+	0xf503c382	0x9a7b92bc	0x8367b4d9	0x8df42ea5
+	0x790dc812	0xe8a51197	0x1f9ec3e8	0x0fe9d551
+	0x29facbeb	0xaaa131a7	0xc0ce9784	0x3f0b2412
+	0x63d56d18	0xe2ca7aef	0x35f66550	0xe49095c1
+	0x8d8531f1	0x815ca696	0x18f31b28	0x39a102bf
+	0x96bd3241	0x1b79f65f	0xb5750fc0	0x7e41b1aa
+	0xe7c7e0f6	0x294a848b	0x0d90877b	0x87c42915
+	0xd5839e6e	0x00635ed9	0xc51b8d91	0x34e60826
+	0x08082536	0x3550eed6	0xc78b127e	0x2f428ec3
+	0xaf95830e	0xb0c8fb6c	0xc0b5e989	0xb45d0020
+	0xce6466e0	0x8e244ba2	0x17ef4563	0x2c74b037
+	0x8d15449e	0xa96ad89d	0x0672ebbc	0xf5a037f4
+	0x633b2cd2	0x82d1cb6a	0xeae7ab21	0xfe156394
+	0xb223326d	0x6bf37192	0x349934ac	0x747e4995
+	0xfff3f992	0xe916d599	0x95917b72	0xd3e810ad
+	0x704231a5	0x041ed2f0	0x32cca85f	0x2ceb1663
+	0x80d3e7c7	0x901d33a6	0x18a99b15	0x21b50c44
+	0x295e5a16	0xceab5147	0x503b6e34	0x732a4fdf
+	0xb6b38684	0xa1317fff	0xb76492ef	0x88e7eda4
+	0x5ccde55d	0x7448f240	0x12d3436b	0x6a152377
+	0xff0b0448	0x8b124b95	0x55321a93	0xed4229ef
+	0x7ea05a46	0x992eb553	0x5f2d7278	0x90dd258f
+	0x6ecd1946	0xab971c70	0x3d341faf	0x49855465
+	0x1973c8cf	0xb5976088	0x6640e00e	0x155dd9f3
+	0x674285a8	0x720515e1	0x5fdffc94	0x0d3a3347
+	0x1dbfe5ff	0x7079f37e	0x8c470652	0x46d6c1e3
+	0x1402e1b4	0x05217695	0x67e45039	0x683ba960
+	0x97cadd4e	0x59664501	0x4726c2a6	0x7601358b
+	0xec77b4b9	0x66a912a0	0x8f157d86	0xa0e221ba
+	0x3aa4bd23	0x547e9323	0xaa94772a	0x1ba6ac0c
+	0xbed2aa6f	0x8a945e94	0xeea5c775	0xf2c66a89
+	0x89ebde2f	0xd7b4e71c	0x6a1c8bb3	0xb9392201
+	0xc7a2191f	0xf180c19a	0xc3446d78	0x7f5f61c8
+	0xc6a251da	0xa27c507f	0x329133a1	0x0c951593
+	0x344ca56a	0x329dea98	0x73112997	0x32bc47a4
+	0xbeb18227	0xd3347aaf	0x1c481ab4	0x62606e69
+	0xe18da26b	0x8243c025	0xfe05b066	0xc1b0c590
+	0xd8c107ba	0x235b8c6a	0xac4fe894	0xa012810b
+	0x5470e6de	0x6f1217ae	0xcb099ad1	0x2b03655e
+	0x91f0b417	0xc21a1af4	0xb4a8c50e	0xa5988ed2
+	0x7f03fa1e	0xa0658a65	0x5532c4b3	0x1fdcfcec
+	0x17f41c26	0xd6b29efb	0x3411f331	0x1b774029
+	0x2ee2d094	0x9f5edaab	0xc644a9f3	0xdc4cf7b1
+	0xb6304748	0xb064cfca	0x89e4dbee	0xb1563a5e
+	0xd370bca8	0xe6cb17d8	0xbfcacc87	0x76940250
+	0xf2456a18	0x3c1873e4	0x0a3d7d0e	0xeb145eb9
+	0xe88a48fb	0x9413f290	0x626e4e00	0xb234a13b
+	0xcbf49379	0xcf600cee	0xc78891b8	0x799f8e80
+	0xdbf4e604	0x89860862	0x04fb77db	0x0fb1bf13
+	0x3b1aa906	0xadaf9a45	0x48526bf7	0x09d8ffb3
+	0xce751581	0x00e35b8d	0x0549e629	0x6d3cc316
+	0x3d8f300a	0xdcd790b5	0xde1ca316	0x737d5f31
+	0x171b2646	0x4798a85d	0xea36f650	0xcf889098
+	0xe4ec65b8	0x944637d3	0x019c8103	0x5fbdc21c
+	0xa61ebe77	0x74ea95a5	0x258eb8d1	0xf8c8c4d6
+	0x9a1edc66	0x9118b309	0x639ae9b5	0xd0c40735
+	0xc6ddec32	0x36d26a75	0x86018c99	0xe8bf66df
+	0xf345dba0	0x780670a3	0xe34e60fd	0x733ad4ba
+	0x2ef04d54	0xb1b9c41f	0x84cca1c2	0xaa09279b
+	0x34797d41	0xb93d4c70	0x919ce970	0xd0d6ec5e
+	0xdc70cc95	0xd89f4680	0x458cfd33	0xc257784b
+	0x29ec9364	0x8e717417	0x6d9732df	0xa3658440
+	0x8574b5c6	0xa58ebb8c	0x81bc4dea	0x1f396663
+	0x361dfd98	0x20b35a46	0x886a7e4c	0x69f0a1c5
+	0xd0b7de5f	0xbbc08761	0xa1cef991	0x084a8ea2
+	0x4df68c5b	0xb84b4b2e	0xd4bf1770	0x94b4f7c7
+	0x9906a752	0x878c7f1f	0x385b5a5e	0x99147c87
+	0x97c54a35	0xbacb57d4	0xf85f9733	0xb5d2c83f
+	0x4405f9f5	0x020260b5	0x5c0a8556	0xb623ad79
+	0x8d42a6a3	0x35ae5806	0x2c28a60d	0xa0200ee8
+	0xed9e0ece	0xb7e0442a	0x1ddf0e2b	0x26ceec5d
+	0xda397b2c	0xb073d9a2	0x9d856bbd	0x06e35ca8
+	0x6296193e	0x292dee18	0xf5a9bd7a	0xb62fe73f
+	0x95a8775f	0x1efc0fd0	0xf3338af4	0x06ccbe78
+	0xafb3f669	0xd9f7fe16	0x09beed63	0xa2f0bb3e
+	0x02f5c52f	0x24aee650	0xf715039b	0x3f566d89
+	0xd575429b	0x9d40207d	0xa89c7de9	0xde5157f0
+	0xd79025ae	0x4259c4b6	0x61e86217	0x6d2e3273
+	0x57b5c99d	0xa18edb02	0xf5f314be	0xfa58bf5f
+	0x581e95bb	0x04967c03	0x9187d903	0xdaf34bc3
+	0xa18e49f0	0xb7973963	0x2984967f	0x7332f94f
+	0x57e5a8b5	0xe6e0a6f8	0xbc08c39f	0xc9e73ad8
+	0x0ea113d8	0xa9cfdb06	0xfda1ebbb	0x1a30e9f9
+	0x69a9029a	0x44b43320	0x04182d93	0x00220972
+	0xa7f984c5	0xb4eeae8a	0x11718517	0x06e70840
+	0xb3091fe5	0x099ccb1a	0xac3df88c	0xa8bd0ca3
+	0xa202bbc0	0x19979cf1	0x8656c385	0x139abf7b
+	0xae298ea4	0xab9481ae	0xe08e2c38	0x27967dab
+	0x1108054c	0x1ba0d3c5	0x8a0fb923	0x9c54f682
+	0x5f363a46	0xec564b34	0x8d53c918	0x47f39642
+	0x3fd68743	0x197f16cc	0x2b03d11c	0xcc574d53
+	0x8b2d1aa3	0xd403c5b0	0xce21d3a6	0x57c88abe
+	0x56d6b12b	0x204f9ac8	0xfd44c338	0x18417de6
+	0x5582f0bf	0x7ea9d04f	0x7bdee65d	0x9fe3f5b5
+	0xa14edd82	0x8301f6ba	0x24bc737a	0x5c6e71a8
+	0xdb0d7fc2	0x243b6e99	0x3941f113	0xcaaa3674
+	0x1b25b686	0xfb219a33	0x1b122757	0x27298223
+	0x44cbb8ad	0xed4e6ef9	0xae338c2d	0xa8d231ee
+	0x9bc2d8f3	0xcecd4d27	0xe8ba9908	0x9a106344
+	0xbdf27147	0x0c547009	0x46b16833	0xd89b0690
+	0x4b742f40	0x733d4cd5	0x1abb6f77	0x803f40df
+	0xf8d909bb	0x8fa6a921	0x08966531	0xdf093174
+	0xc7ee92c8	0x4272612d	0x149f8242	0xf8c07ec3
+	0x99259781	0x8bf3f9c0	0x09d6b679	0x19a1968f
+	0x735b197e	0xa98c913f	0x3e208a56	0x59b2b40b
+	0x0ed212ed	0xfc92d02a	0xe9b1b441	0x1429fc3c
+	0x8a6fb38c	0x6235d73e	0x82f5aca8	0x9ebb490a
+	0x718fed05	0xee355cdc	0xf34bbc8e	0xcfde74ac
+	0x5c267a70	0x30b66c7f	0x9a655781	0x1d354268
+	0xd0debf01	0x71798948	0x4542b707	0x66c02ecf
+	0x49763e11	0xa02f170b	0xbcf30ee9	0xba9bbfec
+	0x6d915d18	0xcadd484f	0x8eadbd10	0x91463818
+	0xe8add34f	0x55620c30	0x14d47fa5	0x63c2a25f
+	0x7213f2f4	0x6d96a516	0xf10f4ed1	0x9825aeac
+	0xe9ca9b8a	0x4bb0e2aa	0x957f8851	0x1a41de29
+	0xa0039e6c	0x3ec63393	0x66b6ac8a	0x2992d983
+	0x2d73caa4	0xb0ae06c2	0xa4008915	0x2ba7050d
+	0x6d9e01e6	0x908f316f	0x3f17dabb	0x8c86b0e3
+	0x89fcebf8	0xbada4307	0x0f6e9f6f	0x07f36992
+	0x1a82520e	0x728f11a9	0x418aa9b7	0xc57f51d7
+	0xcffa1cd0	0xf9f6d902	0xdf22329a	0x4ac48293
+	0x37326e23	0xbb39c187	0xc9086dfe	0x1347e4f8
+	0x7ae88ecb	0xc280a07f	0x7f0a6b0a	0x57cff37d
+	0x2dfd629d	0x5a8a444d	0x934bcafb	0x593b6a3a
+	0x9c62c1ca	0x0ecdb2dc	0xb4c2fd82	0x2c19c0ab
+	0x26acf079	0x71aa1041	0x8aeb2595	0xed90f704
+	0x7d68f5c5	0x624429d5	0xefd0d147	0xc8682f79
+	0xfe7e9cc0	0xaee6c970	0x33e9231e	0x4720df4d
+	0x6a3f6428	0x463b676f	0x71960ee6	0xc684d974
+	0x9f01a6d2	0x728cbec7	0x2e20d715	0x172a4a11
+	0x4153ad1e	0xb1f36e53	0xc277f818	0x94ac6d39
+	0x502f91d8	0x3028b1ee	0x48390347	0x45a8b5af
+	0x2cb8095f	0x063cbe4a	0x07a53b3b	0xcfd08c80
+	0x81679803	0x9fa4726a	0xa682f4c8	0x4d90e8bf
+	>;
-- 
cgit v0.10.2


From bab4b96166037016010238a19c8ab7175386cbc4 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Mon, 23 May 2016 15:25:20 +0800
Subject: x86: Use latest microcode for all BayTrail boards

Update board device tree to include latest microcode, and remove
the old no longer needed microcode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 444de1b..4a50d86 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -250,10 +250,10 @@
 #include "microcode/m0230671117.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@2 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 624d66d..1a4ecaa 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -270,10 +270,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 };
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
deleted file mode 100644
index 90bf2fb..0000000
--- a/arch/x86/dts/microcode/m0130673322.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x322>;
-intel,date-code = <0x4012014>;
-intel,processor-signature = <0x30673>;
-intel,checksum = <0x17b0d914>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x22030000	0x14200104	0x73060300
-	0x14d9b017	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x22030000
-	0x00000000	0x00000000	0x31031420	0x11320000
-	0x01000000	0x73060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x0ae10178	0x7c98f9d1	0x41962d85	0x19391270
-	0xcf3c0336	0xc1f13d6f	0xe46abaf6	0x3b65ca6b
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0x8514b971	0x40df7b4a	0x6a6b7285
-	0x7978ef59	0x319bddf5	0x04c68e5a	0xe1c28b10
-	0x172f63dc	0x306fb95d	0x31d881e8	0x69f8e08d
-	0x617a99e1	0x1ab6b574	0x2951fa5b	0xcc7e3e94
-	0xff379d19	0x5c035dec	0xe28ed726	0x22b8a5ac
-	0xd08b3ac5	0x45c03b9e	0xcea4083c	0xc26758aa
-	0xbe7cf81e	0x43d898f3	0x5c45a635	0xc9cac095
-	0xb89aea20	0x2c02b40e	0xe3a8b48d	0xeabfb60e
-	0x776ed2a9	0x080ae6d5	0x7f64b1df	0x00e40ee6
-	0x0f1c10f4	0x792e5423	0x787f5459	0x63a8b02c
-	0x3fd6a255	0x049cae26	0x0949f5ff	0x9aebb236
-	0xecc01775	0x91b57b84	0xe0e45ea3	0x5a8bf79e
-	0x356a843a	0x2406795f	0x8aaae5d8	0x6a8c877c
-	0xa8b2b8f4	0x04cf8f49	0x422d9e2c	0xf09f9896
-	0xe9b92215	0x9c98fb44	0x88556b7f	0x519d6f4c
-	0x9e8a016b	0xcb18d16c	0x419b4ee7	0x080b49c8
-	0xc51b875e	0x46aabc9c	0x262d27eb	0x93ea189d
-	0xdd0da69d	0x3e5b17e8	0xcc78509a	0x00b07e6e
-	0x363d5a70	0x64572070	0x8a84abc4	0x1cb03838
-	0x965fd76a	0x540aafc9	0x83a91654	0x1a722e67
-	0x4bf98ce1	0x2b3c2ff9	0x972cebd4	0xf3a68395
-	0x2613e422	0xf8d031d7	0xb1c79a0f	0xfd44f65b
-	0xa7012a9b	0xd9a15a60	0xc311fc0c	0x6f52f878
-	0x3d68381d	0xd2a035d7	0xb790c50e	0x9f1e5010
-	0x41877064	0xa9d1e4ae	0xfe9abbd5	0x60c2c748
-	0x8167e5ad	0x022dbfb3	0x75abe483	0x51c37170
-	0x09b8590d	0xc1bb323d	0x2c7336b1	0xd4d0d49b
-	0xc7f6152b	0x7919d596	0x1e1ff62e	0xc49604a0
-	0x33857369	0xeaa3f382	0x98b8cd86	0x176e1bf3
-	0x1a68867b	0x6af0a11c	0x69a82b25	0x48c72525
-	0xa00aae2d	0xb09f67f4	0x1a99f83d	0x7266cca3
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-	0x14d2804c	0x2d635ad3	0xe1314781	0x3921ec18
-	0x3dbebec3	0x94e0df22	0xb0b4724e	0x0e7f986b
-	0x83dd7694	0x7041a22e	0x3c942757	0xd6ff5cbb
-	0x048b0426	0xa5d6c4cb	0x1f4e3bbd	0x78d5924e
-	0x6a857d77	0x1d115ecc	0x73c6a888	0xefb934ee
-	0xa7d1702b	0x6794a668	0x03715b90	0xfbab19f9
-	0xd5a433df	0x12f4d421	0x40519650	0x636a093e
-	0x1601be15	0xe0fbef6f	0x79d775bc	0x789c3a30
-	0x4d9fa618	0xedf8fa70	0xb0fa402d	0x692ee91b
-	0x5a593e5c	0x0fa3667f	0x3f51a636	0x935e28c7
-	0x230b725a	0x4929bc83	0x76de40ad	0x2d9a5f7f
-	0x8799e033	0xbf2700b0	0x5220159d	0x1ed71ca5
-	0xcc66f114	0x15fd868d	0x4236645a	0xded2558e
-	0xa561cc0d	0x02822e5b	0xd0177f80	0xf09badd9
-	0xd5380ae3	0xcfc11a46	0x36713416	0x7f3d60cc
-	0x4018797e	0xc6b23941	0xcb5a4861	0x614ce6df
-	0xabfc0629	0xa519bcfc	0x911f04f0	0xe509b546
-	0xbb411eb9	0x9e6b921c	0xbf0b1c70	0x80c2901c
-	0x85786713	0xad2aafec	0x62711ba7	0x6edb4971
-	0x214eb137	0x45b1b313	0x6742d5e9	0x7daf37a6
-	0x21d6a27a	0x059424f7	0x2c8c3dfb	0xe7a06c77
-	0x10815625	0xb4dc69e8	0x52767f66	0x44d48738
-	0x84d26c93	0x09008893	0xfc21394a	0x82155a72
-	0xc4fd7512	0x6d43cd2f	0xcae99e08	0x453175ae
-	0xc6ee93a3	0x2fed0eac	0xe48fb73d	0x0afe2d2a
-	0x5966735e	0xdc7e5fb6	0xed1ef13d	0x7e08a106
-	0xd3ca0e6b	0x4ce5ca02	0xa0beebed	0xe982c609
-	0x1ee9e5a2	0x24ae26cb	0xfd4c08d4	0x5e85e850
-	0x11b54b3b	0x87209692	0x4a5b0c35	0xcd25dd6f
-	0xd9570253	0xaad0b9fe	0xaf984fee	0x6cf7ae2d
-	0x45d9926c	0x07a66ac6	0x8e7aacdc	0xaf587d66
-	0x53972a4e	0x8da4a6c9	0x2bc311e5	0x36938ae8
-	0x179b965d	0x515743f7	0xb5bbbdcd	0xd8602715
-	0x9e43049f	0x4e78a080	0xba3f1750	0x68635cf0
-	0x85823047	0xbb03b5fd	0xb0d747c8	0x58d214af
-	0x94b1ba85	0x6d2cf8ac	0x2bc1faeb	0x6bd7c1e3
-	0x127658e9	0x8b499020	0xab8f0f62	0xee665a6a
-	0x89240e4d	0x8a95342b	0x00b38ccc	0xe6b14d9d
-	0x32a2af71	0x4c9ecb69	0xc8de2685	0xd7385184
-	0x8e943872	0x809b2c79	0x108511da	0x08b4f54d
-	0x95f52442	0x26fe296f	0xf7e037c0	0xa1aecdd3
-	0x89774a91	0xde67c55f	0x1f9816dc	0x1469a4c2
-	0x28240be2	0x5fd0ad14	0x0949db3a	0x451b94d3
-	0x637e6d49	0x8a4771c8	0xf65104b7	0xc3058c40
-	0x592fe4d0	0xe26129f0	0xe66e6ce9	0x26ab39b8
-	0x308da532	0x205afe77	0x6dc78664	0x84d4890f
-	0x9d49fcb0	0xcac8f2ed	0xe713d798	0xfed7c75b
-	0xe441a0d4	0xdf60df37	0xc2eed2f5	0x2d68b20e
-	0x7827c89a	0x9d4cb9f2	0xb8912cce	0x07516335
-	0x976ffbb6	0x5cd0de48	0xed716f54	0x6f3c9f7f
-	0x34cf42d1	0xc1027cbb	0xde67c065	0xe0a229af
-	0xfc8bd2e8	0xd62ca176	0x8bfb76b2	0x54a1388f
-	0xe0650bb6	0x6d60682b	0xe16cf130	0xbd7c3ca2
-	0xea642814	0xa25f4d44	0x27013786	0x7316aa38
-	0x571511c8	0xf1b6b789	0xb7bfe72b	0x8fd2652c
-	0xbfc7771a	0x51a2e551	0x3bd738c2	0x2698b495
-	0xec69a196	0xd5ecb5c4	0x9bd3224c	0x6d9ab4cf
-	0x326c9942	0x4d711191	0xde9be50a	0xa980ca0b
-	0xe8e59dd0	0x4439e4ae	0x35de914d	0xee499a84
-	0xd1ca0c9d	0xfe6ee96d	0x5b1f4fd0	0xabf0621a
-	0x0c8220c7	0xcb6dbb1e	0xa5116036	0xe858d3c3
-	0x728e3a56	0x3b33e818	0xbe2643c1	0x497bbcc7
-	0xeb369828	0x9a4a01be	0x8c7e72a6	0xaf052f25
-	0x8d3ca85b	0x4703e55e	0x45647d4c	0x86d1e3e8
-	0x40ab59f9	0x3259b195	0xf979a147	0xb8961870
-	0x88b024f9	0x366e26bc	0xd6811525	0x252910c2
-	0x4223a20e	0x7fc971a3	0x4a639bf3	0xb6550c3b
-	0xfe05e552	0xbdc98897	0x509923ff	0xf51a5abc
-	0xc6cc0891	0x61cdac05	0x03a68664	0x1b80cc76
-	0xe18d8ee1	0x798bb4d2	0xd7769bf9	0x9ab4c02d
-	0x7484774b	0xa9ee2c8b	0x87d34c85	0x15697682
-	0x9f6a4a55	0x9d7a731c	0x10014d6a	0xb9798070
-	0xd42f79cb	0x89db59b3	0xd5b0a0b6	0xf60864a5
-	0x2d6fb084	0x1cb607b2	0x48232701	0x9310cbc6
-	0x5bc81c98	0x6b25016c	0x2014b99d	0x0836e60b
-	0x0addbc4c	0x3b8bac7c	0x8d95ac77	0x1d56c3c7
-	0x58333104	0x3d6eb719	0x676eb951	0xd5c2d1a3
-	0x239dae86	0x92181ab8	0xbdde9741	0x7995d452
-	0xe0020661	0x2f80c8b7	0xeedcd4fc	0xe4bde175
-	0xb98fdf78	0x84b9228f	0x78ecb4f3	0xe99e5d46
-	0xa33b9b96	0xe2cbc71c	0xc19e2146	0xdc0ee758
-	0x2d8f8767	0x2036685b	0x149df155	0x2e7ab376
-	0xb13b4266	0xf5c8a3b0	0x02ca1e19	0x1badd81b
-	0xb9c1832a	0x73b31f75	0x69979b55	0x567070a2
-	0x2edeb3dc	0x26b55921	0x461df49f	0xc1aba883
-	0x25d6faec	0x5260e9bf	0xa8ccdd4c	0x04291961
-	0xfaf7a1b8	0xbc2d36e3	0xd6c86385	0x2757fbb9
-	0x62c7107c	0x87dac461	0x0c006454	0x0e971e49
-	0x4749afca	0x7f1fb389	0xdc0b69d3	0xc69fab09
-	0x12c372c9	0x78480a51	0x8ab03a94	0xb37022ca
-	0x1d00e893	0x0989de45	0x8c819503	0x8e0e1c06
-	0x11cfef86	0x3c2386a6	0x66c0e6c8	0x1befa478
-	0xd2e7a4a7	0x9a8b5917	0x2cfa1816	0xaf7e6c7a
-	0xd6c9f0ff	0x1aada3e0	0xbe36a471	0x5a91f3c7
-	0x6c61ea95	0x5246ef7c	0x20bc86c4	0xcfd87abd
-	0xdc61f595	0x8310a684	0x0477e35c	0xe59e776f
-	0xfa403863	0xdaf7bcb1	0xd6084825	0xb90bb047
-	0xeb9ff684	0x7223fbca	0x6b4af987	0x6b2553f8
-	0xdaabc6d2	0x82e2ebc3	0xa7c1c054	0x667eb0a7
-	0x53a0c7d4	0x3fcba743	0x38170187	0x2a2e5830
-	0xee134608	0xcd6e0112	0xac0831f9	0x9537d532
-	0x1e176b9c	0xe3fcb69f	0x17a2eee9	0xa9e6467f
-	0xbf6b0246	0x6a08c0fb	0x7fb943b6	0xb8f67c0e
-	0x2b3b4ffc	0xb155d20c	0x4eb5de53	0xf078715b
-	>;
diff --git a/arch/x86/dts/microcode/m0130679901.dtsi b/arch/x86/dts/microcode/m0130679901.dtsi
deleted file mode 100644
index 11aaaa0..0000000
--- a/arch/x86/dts/microcode/m0130679901.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x901>;
-intel,date-code = <0x4212014>;
-intel,processor-signature = <0x30679>;
-intel,checksum = <0x69c4e6f1>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x01090000	0x14202104	0x79060300
-	0xf1e6c469	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x01090000
-	0x00000000	0x00000000	0x18041420	0x01320000
-	0x01000000	0x79060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x3b6ec6fe	0xc0fda75e	0xb4ea6a9f	0x8fd6ed15
-	0xd537f374	0x669bf3bb	0xebedec72	0xb4cbc889
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0xf03f27bc	0x3ed2262b	0xe1f8f63d
-	0xc164c68f	0x92e5df39	0x46108645	0x99a9968f
-	0x1dfa58a4	0xd1ebfd99	0xca4dae70	0xe466a06a
-	0x49575333	0xe30f49f0	0x814e5961	0xfa4bb7bd
-	0x2e212282	0x31912456	0x7d722c47	0x9cda0657
-	0x111985e9	0xd28d3b0b	0xec52f0c2	0x956b5b95
-	0x0806f491	0xa8096786	0x1e4c1248	0x42ea1ecf
-	0xea09d662	0xa821f68e	0x4b84d60a	0xa6f61348
-	0xfc95c139	0xebcebc32	0xd68ffe3e	0xa9aefabe
-	0xf653aafc	0x2a9f10e4	0xdaf3d51d	0x5f25aaa5
-	0xdedacabe	0xf2e08b12	0x6fb9f444	0x31b13d4e
-	0x13074cd3	0x68905491	0x08ce3a00	0xb3e5a3dc
-	0x9554ca97	0x5955c3a4	0x2e9951fd	0x5d708c9f
-	0xf3abe824	0xcb9105a1	0x3f51122e	0xd2152f23
-	0x2873cd28	0x463c0ff3	0x7bb81500	0xaa360665
-	0xbe69bdf9	0xa32415d6	0x111af68c	0xd129eaf6
-	0xdd102779	0x098a2b08	0x90363b85	0xdb5d3420
-	0xd1d116e3	0x9e5dd54e	0xb4a93d32	0xb5ee99fe
-	0x409f0bca	0x40302319	0xe175ddaa	0xfd7c8d00
-	0x2c28edb9	0x698d27f4	0x2e7945f1	0xc0150485
-	0xf9c599fc	0x139824cb	0x1571f70e	0x222565e8
-	0x3377eb7a	0x70fdee6f	0xd409f0a6	0xc875d05f
-	0x70d6a86b	0x66201d61	0xf8fcb733	0x14279707
-	0xc204e0e4	0x124c89be	0x8b298d1d	0x79bfe168
-	0xdbf7fe94	0x0358af09	0x8291ef8a	0x3e74a2ea
-	0xb7780782	0x0194d445	0x0bab231d	0xd76f85b2
-	0xc7510861	0x4b9a5c80	0x6c9c8583	0x4e18d7db
-	0x7dfeaea8	0x59be4d17	0x8e96f5b7	0x51bcb2da
-	0x5f3afeed	0xd3f46ecd	0x10da04eb	0x29dd87db
-	0xb7df24c5	0xd58dc2dc	0xede0603f	0xadf00cf7
-	0x50090b9f	0xc9130c82	0x854fc603	0x13b8b4be
-	0x10e2e41f	0x5c1d2246	0x0ee11843	0x6d38356d
-	0xd3bd47ae	0xb419f115	0xb118cac7	0x9c61aa7d
-	0xca22cf8a	0xd41af2f1	0x0b5ebfab	0xc0889746
-	0x078c705f	0x9e5b2b7a	0xb886ff49	0x1ab413e4
-	0x085cebc5	0xe3a44ab5	0x8844df92	0x075a79cf
-	0xb8fdc33b	0x1766265c	0x9340a734	0x4af860c9
-	0xa933586e	0x3e8a9a5c	0xf6419a1b	0xa70a1556
-	0xf930240e	0xe294fb1f	0x9bba35c5	0x4051819b
-	0x6799015f	0x7eb725ad	0x3953fe03	0xb8760679
-	0x54c7978c	0x3dfd36c2	0x631212bb	0xdeaca312
-	0x56d994dc	0x3a1696d1	0x214451fd	0x6dc505f7
-	0x7bbf210f	0xa266b569	0x8fb5eb6f	0xa6b76bf8
-	0xc9e782a1	0x8456765d	0x0a9eb223	0xa67e533f
-	0x211016f4	0xd8783c3e	0xc35574b8	0xd97e9b52
-	0x28ad2911	0xbffc5dad	0xd807d783	0x3050f3d1
-	0xcc33efa8	0xb9cf97c2	0xee5dfc8c	0x2adad5bb
-	0x4011c50b	0xa16f5d93	0x5e2ac188	0x521c977f
-	0x6af1b858	0xcd7e4b4c	0xfc988f66	0xc0e4cee9
-	0x82ac99ea	0x54353832	0x2308e02f	0xd084d198
-	0x03574ad5	0xbe4b698f	0xe1d7d294	0xd772d08d
-	0xb7a4fb2a	0xf7c93bb8	0x42fb2f4b	0x98cb1a11
-	0xf564f28e	0xd6ace35f	0xc43f6639	0x85be741d
-	0x079b8c1f	0xb5b45522	0xfedab918	0xf7fa7494
-	0x32204c16	0x1c8d5434	0xc39e58e4	0x99c7a2c4
-	0x3ccfbc3a	0x3f5ba9ef	0xf919921b	0xcffbeb79
-	0xd2927d86	0x5a50486d	0x62bdb218	0x22731dcd
-	0xbad1db2c	0x2f4af4a5	0x8f7eded6	0xeca3dcca
-	0x0bb5ecf7	0x05e6f3c6	0xa38cddff	0xc7cae177
-	0x1d115485	0x711ea542	0x33729cf9	0x59000680
-	0xcaf26070	0xd2647235	0x4ce354fc	0x76d9bdbe
-	0x53e39ec2	0x2d8acfb3	0x193c03b9	0xb3cef3ba
-	0x1da26bd5	0x8dfeeaa5	0xc199d90d	0xcfc8ee2d
-	0x4cb1bd52	0x521d197c	0x008bf34b	0xb6ff25ca
-	0xf4922b7c	0xa91893a8	0xbd3d7874	0x32865e72
-	0xca72c49d	0x02733201	0x6156051d	0x47464b81
-	0x353a3c14	0xa87475c8	0x9681a015	0x4b58832d
-	0xea65c6a2	0xfefef1fb	0xd5fa7dbf	0x13aeee80
-	0x2915b47b	0xe4a54fca	0x31615326	0xbad80f83
-	0x21eedfcc	0x2a2787da	0x6eaa2c9c	0x9de76356
-	0x8a34d823	0x2e7641b8	0xef16714d	0x8267bad4
-	0xacdfff45	0x09a93862	0xf63863de	0x7eec7d8b
-	0x70b4cf72	0xc7a8118c	0x4ed89774	0xc12a5e0d
-	0xe77cc023	0xcdee8fd8	0x20ffe6d9	0x88bcfaa0
-	0xd945e4fb	0xf496fccc	0xe7587e99	0x42252ec4
-	0xcc47d738	0xcc549ca3	0xd5059657	0xfbf502a5
-	0x2788945d	0x4f8ca4d6	0x41b7c069	0x618ebdf6
-	0x0354452c	0xf7249d75	0xe048dd38	0x4ca484b3
-	0x0347342c	0x23608b20	0x8a76cb28	0xd445886d
-	0xfe0e1e6a	0x46678478	0x230c0ef0	0x3add3053
-	0xa6a158c1	0x22c589d3	0x3b728538	0x5f78bfe8
-	0xab0bb3ab	0xb39e20b7	0xbb913a69	0xdf8bb73c
-	0xc2d5bb32	0xbd3e928c	0x30374965	0x9accaf18
-	0x60bb410e	0xa7786a6d	0xd368444d	0xc5eda57d
-	0x7a835abd	0x9f5f74e9	0x33b14a30	0xc0129833
-	0xc5d2e117	0x5f884f0f	0xae6fd2f7	0x3ef71ba2
-	0x0f0b944c	0x1a8dd932	0x2448f0ed	0xfb8ca949
-	0x9d08756f	0x7914384d	0xdd70f795	0x8cf8daff
-	0x6755785b	0xf4e6a191	0x8c5a9a2e	0xfdc19939
-	0x66f39dc0	0x3da9fcc2	0x2c22797b	0x63f892d3
-	0xdcb75a66	0xa043c021	0xcb0f9292	0x887eb1a2
-	0x9d588452	0x9fdc185f	0xf481d465	0xbfef53b9
-	0x38da9baa	0x9d35c4f4	0xa652c843	0xf80f0007
-	0xb482a32c	0x7ae4df5b	0x74ad41c2	0x15d849b3
-	0xc4235054	0x36d44d98	0xc06ad604	0xdc83d81f
-	0xd4b87511	0xab79b430	0x832a7ce1	0xafe26f16
-	0x9f7d26db	0xd00816cd	0xec6e7b8b	0x0392bd20
-	0xfe4b6e2f	0x87795026	0xf9e4eef8	0x06cd2ec8
-	0x91670e6a	0x17aad6af	0x399050d1	0x043d05f8
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-	0xbc454c61	0x83647148	0xec9e834a	0x11527826
-	0x2c7eb009	0xc6d7e3f4	0xbe8befd2	0xd3cc42a8
-	0x0442b41e	0x89643506	0xfd1dc572	0x74b340bc
-	0x686f6f6c	0x48b92189	0xe8f88be6	0xfc591dbf
-	0x8b453678	0xea1fd8cc	0x659d57d9	0xb501f90c
-	0xa6d6b031	0x182d8378	0xd6a8d690	0x6419c2b6
-	0x523d3089	0xc23c971c	0x43994015	0xa4b23066
-	0x831e6ca5	0x03c18610	0xd6d1f4b5	0x28978a3d
-	0xdc620eba	0xc1f86faa	0xf6c4d906	0xf06f85f3
-	0x232fa1bf	0xcf80cc2a	0x6599a5b2	0xc2d4cdad
-	0x0287eb92	0x5cdc4dd6	0x34a9b6d4	0x6d4b1324
-	0x6d21a837	0x00026037	0x80a225a8	0xad75b226
-	0x414a3741	0xb74d0962	0x363b24b5	0xb5044295
-	0x0a01c1a1	0x90a110c8	0x53bdeee5	0xad31aa53
-	0xfb85cc5f	0xdf80b0f3	0x7ad3cb0f	0xb5c68bd6
-	0x89185ff8	0x41544629	0xad5adfe7	0x39061752
-	0x2e9c106c	0xbf52a0df	0x9d2cef79	0x99eba49d
-	0x4459b32c	0xdc98fd7b	0xd81f2f74	0x8aa59f53
-	0x1817857f	0x5f79e3bf	0xc4b7c810	0x9e3a9ddc
-	0x724af115	0x121239e3	0x3c33c849	0xd8abb44d
-	0x600d67b7	0xeaa06b4c	0x20fe7ba6	0x502c684b
-	0xf212d37d	0x413d883a	0x5abc83ec	0x3112bb6e
-	0x27e1b3e0	0xf6dc8508	0xfe602c4f	0xa5b34bce
-	0x4d03d689	0xdacb23c2	0xa00fb513	0x78606ea8
-	0x8fd43ecf	0x90072d2a	0xfcc7b1b9	0x7ffec951
-	0x684bbc25	0xc21a0374	0x8f06a016	0x0e28dfea
-	0x40da3a00	0x8c73a059	0xc0d565ef	0x13bb6c81
-	0x6e27c2ec	0x2f4c9a43	0xae1b4513	0x9738b38a
-	0x5557c3e1	0xa292c6ab	0xd0f78cea	0xb96402f7
-	0x6c281a04	0x948787f9	0xe59f0714	0x6f130446
-	0x4b12e263	0xcae5e073	0x00f0e279	0x9b03c647
-	0x2a141b72	0x19d1e112	0x97b3b6df	0x3c2b6c82
-	0x5b119136	0x57e2084c	0xe954bc0d	0xcdfbfa78
-	0xadc6b571	0x010b9122	0x236676d6	0x2458c822
-	0xcbb8384a	0x662cfd01	0x096c50d2	0x4959676b
-	0xf8b59f31	0xad912a4d	0x2e87fa6e	0x30182092
-	0xc0bf2c01	0x02b4bfa7	0xdd208dac	0x4c174da2
-	>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index a6c86c9..936455b 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -298,10 +298,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
-- 
cgit v0.10.2


From 0ac8d5e552c5642d97ce71658ecebb273d259221 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:30 -0700
Subject: x86: galileo: Enable CPU driver

Add a cpu node in the device tree and enable CPU driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index f784c50..da3cbff 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -29,6 +29,18 @@
 		stdout-path = &pciuart0;
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+	};
+
 	tsc-timer {
 		clock-frequency = <400000000>;
 	};
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 17b1458..21432e6 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
@@ -30,6 +31,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
-- 
cgit v0.10.2


From 3299be2479f9878dd3bb484f2b8f1ef7c0a20fb4 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:31 -0700
Subject: x86: Don't touch IA32_APIC_BASE MSR on Intel Quark

Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 30d2313..dbb32c4 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v)
 
 void enable_lapic(void)
 {
-	msr_t msr;
-
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.hi &= 0xffffff00;
-	msr.lo |= MSR_IA32_APICBASE_ENABLE;
-	msr.lo &= ~MSR_IA32_APICBASE_BASE;
-	msr.lo |= LAPIC_DEFAULT_BASE;
-	msr_write(MSR_IA32_APICBASE, msr);
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
+
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.hi &= 0xffffff00;
+		msr.lo |= MSR_IA32_APICBASE_ENABLE;
+		msr.lo &= ~MSR_IA32_APICBASE_BASE;
+		msr.lo |= LAPIC_DEFAULT_BASE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 void disable_lapic(void)
 {
-	msr_t msr;
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
 
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
-	msr_write(MSR_IA32_APICBASE, msr);
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 unsigned long lapicid(void)
-- 
cgit v0.10.2


From aaaa55751ab1e5a5cfa0962d604593a7e6f33ff6 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:32 -0700
Subject: x86: Remove SMP limitation in lapic_setup()

At present LAPIC is enabled and configured as virtual wire mode
in lapic_setup() only when CONFIG_SMP is on. This limitation is
however not necessary as for uniprocessor this is still needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index dbb32c4..fbea2d1 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -124,7 +124,6 @@ int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 
 void lapic_setup(void)
 {
-#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
@@ -154,11 +153,7 @@ void lapic_setup(void)
 		    LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !CONFIG_SMP */
-	/* Only Pentium Pro and later have those MSR stuff */
-	debug("Disabling local apic: ");
-	disable_lapic();
-#endif /* CONFIG_SMP */
+
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
-- 
cgit v0.10.2


From e2126711af40ae669610d3500fe23c81b7ad6307 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:33 -0700
Subject: x86: Call lapic_setup() in interrupt_init()

Let's configure LAPIC in a common place - interrupt_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 10dc4d4..dd2819a 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -15,14 +15,14 @@
 #include <dm.h>
 #include <asm/cache.h>
 #include <asm/control_regs.h>
+#include <asm/i8259.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <linux/compiler.h>
+#include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/processor-flags.h>
 #include <asm/processor.h>
 #include <asm/u-boot-x86.h>
-#include <asm/i8259.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -266,6 +266,8 @@ int interrupt_init(void)
 	i8259_init();
 #endif
 
+	lapic_setup();
+
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
 
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index e710ac4..38e244b 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -14,7 +14,6 @@
 #include <malloc.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
-#include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
@@ -418,7 +417,6 @@ static int model_206ax_init(struct udevice *dev)
 
 	/* Enable the local cpu apics */
 	enable_lapic_tpr();
-	lapic_setup();
 
 	/* Enable virtualization if enabled in CMOS */
 	enable_vmx();
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 8207274..2b6b3bd 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -408,8 +408,6 @@ static int init_bsp(struct udevice **devp)
 	cpu_get_name(processor_name);
 	debug("CPU: %s\n", processor_name);
 
-	lapic_setup();
-
 	apic_id = lapicid();
 	ret = find_cpu_by_apic_id(apic_id, devp);
 	if (ret) {
-- 
cgit v0.10.2


From 911d6f693292dbf9b54de43f18ac95427e9accd8 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:34 -0700
Subject: x86: quark: Assign a unique I/O APIC ID

After power-on, both LAPIC and I/O APIC appear with the same APIC ID
zero, which creates an ID conflict. When generating MP table, U-Boot
reports zero as the LAPIC ID in the processor entry, and zero as the
I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment
entries. Such MP table confuses Linux kernel and finally a kernel
panic is seen during boot:

  BUG: unable to handle kernel paging request at ffff9000
  IP: [<c101d462>] native_io_apic_write+0x22/0x30
  *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000
  Oops: 0002 [#1]
  Modules linked in:
  Pid: 1, comm: swapper Tainted: G        W    3.8.7 #3 intel galileo/galileo
  EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0
  EIP is at native_io_apic_write+0x22/0x30
  ...
  Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index cf3fe7f..bdd360a 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/ioapic.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -338,6 +339,9 @@ int arch_misc_init(void)
 	mrccache_save();
 #endif
 
+	/* Assign a unique I/O APIC ID */
+	io_apic_set_id(1);
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From b813ea9a14eaa9a6c071a9ab48a18d9a17dcef08 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:35 -0700
Subject: x86: broadwell: Correct I/O APIC ID

Currently ID 2 is assgined to broadwell I/O APIC, however per
chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change
I/O APIC ID to 4 to avoid conflict.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index f0798a7..317f57d 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -109,7 +109,8 @@ static void pch_enable_ioapic(void)
 {
 	u32 reg32;
 
-	io_apic_set_id(0x02);
+	/* Make sure this is a unique ID within system */
+	io_apic_set_id(0x04);
 
 	/* affirm full set of redirection table entries ("write once") */
 	reg32 = io_apic_read(0x01);
-- 
cgit v0.10.2


From 84c299940d63bb3dfff4469a9b509c78b7016bc0 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:36 -0700
Subject: x86: galileo: Enable MP table generation

Now that we have added CPU uclass driver and fixed the IOAPIC ID
conflict, enable MP table generation so that IOAPIC can be used
by the Linux kernel.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 21432e6..f8d3c3b 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -4,6 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo"
 CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-- 
cgit v0.10.2


From 5ce378cfcfc88284bd90cf8c02e473945aec9d35 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:37 -0700
Subject: x86: kconfig: Add two options for SMBIOS manufacturer and product
 name

This introduces two Kconfig options to be used by SMBIOS tables:
board manufacturer and product name.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 65cbb9c..29d2307 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -464,6 +464,22 @@ config GENERATE_SMBIOS_TABLE
 
 	  Check http://www.dmtf.org/standards/smbios for details.
 
+config SMBIOS_MANUFACTURER
+	string "SMBIOS Manufacturer"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_VENDOR
+	help
+	  The board manufacturer to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_VENDOR).
+
+config SMBIOS_PRODUCT_NAME
+	string "SMBIOS Product Name"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_BOARD
+	help
+	  The product name to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_BOARD).
+
 endmenu
 
 config MAX_PIRQ_LINKS
-- 
cgit v0.10.2


From 4cdce9f5b455195357fd7b5e89205888fe3115b8 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:38 -0700
Subject: x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables

Make use of the newly added Kconfig options of board manufacturer
and product name to write SMBIOS tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c
index 441fca9..9f30550 100644
--- a/arch/x86/lib/smbios.c
+++ b/arch/x86/lib/smbios.c
@@ -105,8 +105,8 @@ static int smbios_write_type1(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type1));
 	fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 
 	len = t->length + smbios_string_table_len(t->eos);
 	*current += len;
@@ -121,8 +121,8 @@ static int smbios_write_type2(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type2));
 	fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 	t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
 	t->board_type = SMBIOS_BOARD_MOTHERBOARD;
 
@@ -139,7 +139,7 @@ static int smbios_write_type3(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type3));
 	fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
 	t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
 	t->bootup_state = SMBIOS_STATE_SAFE;
 	t->power_supply_state = SMBIOS_STATE_SAFE;
-- 
cgit v0.10.2


From 8216b11cdd50515fbc423a4b2709a00865b8621d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 22 May 2016 01:45:39 -0700
Subject: x86: galileo: Override SMBIOS product name

Override the default product name U-Boot reports in the SMBIOS
table, to be compatible with the Intel provided UEFI BIOS, as
Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
it to do different board level configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 6515bac..87a0ec4 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -21,4 +21,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
 
+config SMBIOS_PRODUCT_NAME
+	default "GalileoGen2"
+	help
+	  Override the default product name U-Boot reports in the SMBIOS
+	  table, to be compatible with the Intel provided UEFI BIOS, as
+	  Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
+	  drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
+	  it to do different board level configuration.
+
+	  This can be "Galileo" for GEN1 Galileo board.
+
 endif
-- 
cgit v0.10.2


From 034eda867f47986e04be13087d193d2c12e3b9aa Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 25 Apr 2016 15:55:42 -0600
Subject: malloc: improve memalign fragmentation fix

Commit 4f144a416469 "malloc: work around some memalign fragmentation
issues" enhanced memalign() so that it can succeed in more cases where
heap fragmentation is present. However, it did not solve as many cases
as it could. This patch enhances the code to cover more cases.

The alignment code works by allocating more space than the user requests,
then adjusting the returned pointer to achieve alignment. In general, one
must allocate "alignment" bytes more than the user requested in order to
guarantee that alignment is possible. This is what the original code does.
The previous enhancement attempted a second allocation if the padded
allocation failed, and succeeded if that allocation just happened to be
aligned; a fluke that happened often in practice. There are still cases
where this could fail, yet where it is still possible to honor the user's
allocation request. In particular, if the heap contains a free region that
is large enough for the user's request, and for leading padding to ensure
alignment, but has no or little space for any trailing padding. In this
case, we can make a third(!) allocation attempt after calculating exactly
the size of the leading padding required to achieve alignment, which is
the minimal over-allocation needed for the overall memalign() operation to
succeed if the third and second allocations end up at the same location.

This patch isn't checkpatch-clean, since it conforms to the existing
coding style in dlmalloc.c, which is different to the rest of U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index b09f524..adc680e 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1909,6 +1909,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes;
   * fulfill the user's request.
   */
   if (m == NULL) {
+    size_t extra, extra2;
     /*
      * Use bytes not nb, since mALLOc internally calls request2size too, and
      * each call increases the size to allocate, to account for the header.
@@ -1917,9 +1918,27 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes;
     /* Aligned -> return it */
     if ((((unsigned long)(m)) % alignment) == 0)
       return m;
-    /* Otherwise, fail */
+    /*
+     * Otherwise, try again, requesting enough extra space to be able to
+     * acquire alignment.
+     */
     fREe(m);
-    m = NULL;
+    /* Add in extra bytes to match misalignment of unexpanded allocation */
+    extra = alignment - (((unsigned long)(m)) % alignment);
+    m  = (char*)(mALLOc(bytes + extra));
+    /*
+     * m might not be the same as before. Validate that the previous value of
+     * extra still works for the current value of m.
+     * If (!m), extra2=alignment so 
+     */
+    if (m) {
+      extra2 = alignment - (((unsigned long)(m)) % alignment);
+      if (extra2 > extra) {
+        fREe(m);
+        m = NULL;
+      }
+    }
+    /* Fall through to original NULL check and chunk splitting logic */
   }
 
   if (m == NULL) return NULL; /* propagate failure */
-- 
cgit v0.10.2


From 8df81e17f81ba0542f6dbb7636db64fa56c12d8a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:55:37 -0600
Subject: image-fit: Don't display an error in fit_set_timestamp()

This function returns an error code and its caller may be able to fix the
error. For example fit_handle_file() expands the device tree to fit if there
is a lack of space.

In this case the caller does not want an error displayed. It is confusing,
since it suggests that something is wrong, when it fact everything is fine.
Drop the error.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/image-fit.c b/common/image-fit.c
index 25f8a11..c86b7c6 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -886,9 +886,9 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp)
 	ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
 				sizeof(uint32_t));
 	if (ret) {
-		printf("Can't set '%s' property for '%s' node (%s)\n",
-		       FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
-		       fdt_strerror(ret));
+		debug("Can't set '%s' property for '%s' node (%s)\n",
+		      FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
+		      fdt_strerror(ret));
 		return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -1;
 	}
 
-- 
cgit v0.10.2


From bd6e14209445853f9024574b756bba3184bc215c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 May 2016 13:55:38 -0600
Subject: mkimage: Add a quiet mode

Some build systems want to be quiet unless there is a problem. At present
mkimage displays quite a bit of information when generating a FIT file. Add
a '-q' flag to silence this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/imagetool.c b/tools/imagetool.c
index 916ab96..08d191d 100644
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -51,7 +51,8 @@ int imagetool_verify_print_header(
 				 * successful
 				 */
 				if ((*curr)->print_header) {
-					(*curr)->print_header(ptr);
+					if (!params->quiet)
+						(*curr)->print_header(ptr);
 				} else {
 					fprintf(stderr,
 						"%s: print_header undefined for %s\n",
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 24f8f4b..a3ed0f4 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -73,6 +73,7 @@ struct image_tool_params {
 	struct content_info *content_head;	/* List of files to include */
 	struct content_info *content_tail;
 	bool external_data;	/* Store data outside the FIT */
+	bool quiet;		/* Don't output text in normal operation */
 };
 
 /*
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 93d1c16..aefe22f 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -136,7 +136,7 @@ static void process_args(int argc, char **argv)
 	int opt;
 
 	while ((opt = getopt(argc, argv,
-			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
+			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:qsT:vVx")) != -1) {
 		switch (opt) {
 		case 'a':
 			params.addr = strtoull(optarg, &ptr, 16);
@@ -216,6 +216,9 @@ static void process_args(int argc, char **argv)
 			if (params.os < 0)
 				usage("Invalid operating system");
 			break;
+		case 'q':
+			params.quiet = 1;
+			break;
 		case 'r':
 			params.require_keys = 1;
 			break;
-- 
cgit v0.10.2


From 5adfa265793d2e41fd1619cafcd9cf4e18f80341 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 4 May 2016 15:08:00 +0200
Subject: spl: fit: Print error message when FDT is not present

When FDT is not present in the image user doesn't get any error what's
wrong. Print error message if LIBCOMMON_SUPPORT is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Seris-cc: uboot
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 1a5c027..26842ba 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -39,8 +39,13 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 	     node >= 0;
 	     node = fdt_next_subnode(fdt, node)) {
 		name = fdt_getprop(fdt, node, "description", &len);
-		if (!name)
+		if (!name) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+			printf("%s: Missing FDT description in DTB\n",
+			       __func__);
+#endif
 			return -EINVAL;
+		}
 		if (board_fit_config_name_match(name))
 			continue;
 
-- 
cgit v0.10.2


From c409bd015c295ba088af75b117d1dd6ebd8080ba Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 4 May 2016 15:14:11 +0200
Subject: spl: Setup default value for OF_LIST

OF_LIST can't remain empty that's why setup it up to default DTB.

If it is empty u-boot.img is created without FDT partition:
For example:
  ./tools/mkimage -f auto -A arm -T firmware -C none -O u-boot -a
0x8000000 -e 0 -n "U-Boot 2016.05-rc3 ..." -E -b  -d u-boot-nodtb.bin u-boot.img
Can't set 'timestamp' property for '' node (FDT_ERR_NOSPACE)
FIT description: Firmware image with one or more FDT blobs
Created:         Wed May  4 15:02:52 2016
 Image 0 (firmware@1)
  Description:  U-Boot 2016.05-rc3-00080-gff2e12ae22a8-dirty for zynqmp
board
  Created:      Wed May  4 15:02:52 2016
  Type:         Firmware
  Compression:  uncompressed
  Data Size:    unavailable
  Architecture: ARM
  Load Address: 0x08000000
 Default Configuration: 'conf@1'
 Configuration 0 (conf@1)
  Description:  unavailable
  Kernel:       unavailable

And then image like this doesn't contain description and link to FDT and
can't boot.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/dts/Kconfig b/dts/Kconfig
index d585009..c56c129 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -62,6 +62,7 @@ config DEFAULT_DEVICE_TREE
 config OF_LIST
 	string "List of device tree files to include for DT control"
 	depends on SPL_LOAD_FIT
+	default DEFAULT_DEVICE_TREE
 	help
 	  This option specifies a list of device tree files to use for DT
 	  control. These will be packaged into a FIT. At run-time, SPL will
-- 
cgit v0.10.2


From c1420f8b2b0f3c833c024979495ab22db34a5dbe Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 13 May 2016 10:54:04 -0400
Subject: kbuild: fixdep: Check fstat(2) return value

Coverity has recently added a check that will find when we don't check
the return code from fstat(2).  Copy/paste the checking logic that
print_deps() has with an appropriate re-wording of the perror() message.

[ Linux commit : 46fe94ad18aa7ce6b3dad8c035fb538942020f2b ]

Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Marek <mmarek@suse.com>

diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index e8e8c77..9bd0de2 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -296,7 +296,11 @@ static void do_config_file(const char *filename)
 		perror(filename);
 		exit(2);
 	}
-	fstat(fd, &st);
+	if (fstat(fd, &st) < 0) {
+		fprintf(stderr, "fixdep: error fstat'ing config file: ");
+		perror(filename);
+		exit(2);
+	}
 	if (st.st_size == 0) {
 		close(fd);
 		return;
-- 
cgit v0.10.2


From 5f89a15e1630e9050c8b1b5307ccd800e4596ce5 Mon Sep 17 00:00:00 2001
From: Martin Hejnfelt <mh@newtec.dk>
Date: Thu, 19 May 2016 09:11:58 +0200
Subject: omap3: Fix SPI registers on am33xx and am43xx

When the base registers are read from device tree the base is not
0x48030100 as the driver expects, but 0x48030000, resulting in
non functioning SPI. To deal with this, use same idea as how this
is done in the linux kernel (drivers/spi/spi-omap2-mcspi.c) and
add a structure with a field that is used to shift the registers
on these systems.

v2: Fixed commit subject line to correct cpu

Signed-off-by: Martin Hejnfelt <mh@newtec.dk>

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 2fe34c9..60e9d6e 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -35,6 +35,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define OMAP3_MCSPI4_BASE	0x480BA000
 #endif
 
+#define OMAP4_MCSPI_REG_OFFSET	0x100
+
+struct omap2_mcspi_platform_config {
+	unsigned int regs_offset;
+};
+
 /* per-register bitmasks */
 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
@@ -623,7 +629,10 @@ static int omap3_spi_probe(struct udevice *dev)
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
 
-	priv->regs = (struct mcspi *)dev_get_addr(dev);
+	struct omap2_mcspi_platform_config* data =
+		(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
+
+	priv->regs = (struct mcspi *)(dev_get_addr(dev) + data->regs_offset);
 	priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
 					    MCSPI_PINDIR_D0_IN_D1_OUT);
 	priv->wordlen = SPI_DEFAULT_WORDLEN;
@@ -662,9 +671,17 @@ static const struct dm_spi_ops omap3_spi_ops = {
 	 */
 };
 
+static struct omap2_mcspi_platform_config omap2_pdata = {
+	.regs_offset = 0,
+};
+
+static struct omap2_mcspi_platform_config omap4_pdata = {
+	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
+};
+
 static const struct udevice_id omap3_spi_ids[] = {
-	{ .compatible = "ti,omap2-mcspi" },
-	{ .compatible = "ti,omap4-mcspi" },
+	{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
+	{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
 	{ }
 };
 
-- 
cgit v0.10.2


From d550e82e4efebf5995809e38e8fb029b8fe6e861 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 23 May 2016 11:51:13 -0400
Subject: SPL: fat: Fix spl_parse_image_header() return value handling

The spl_parse_image_header() can return 0 and it is not an error.
Only treat non-zero return value as an error.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 338ea2f..5b0d969 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -58,7 +58,7 @@ int spl_load_image_fat(struct blk_desc *block_dev,
 		goto end;
 
 	err = spl_parse_image_header(header);
-	if (err <= 0)
+	if (err)
 		goto end;
 
 	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-- 
cgit v0.10.2


From d38fca40c84e6d5f73dfe43cef4c46d42f90aa66 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 20 May 2016 12:13:10 +0900
Subject: ARM: fix ifdef in ARMv8 lowlevel_init() again

Commit 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY.

Fixes: 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index c3cc819..e933021 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -216,7 +216,7 @@ WEAK(lowlevel_init)
 #endif
 #endif
 
-#ifndef CONFIG_ARMV8_MULTIENTRY
+#ifdef CONFIG_ARMV8_MULTIENTRY
 	branch_if_master x0, x1, 2f
 
 	/*
-- 
cgit v0.10.2


From cc434ad5c1c97baa9d7020db35f74a4998f2146a Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Fri, 26 Feb 2016 17:20:25 +0800
Subject: ARM: at91: sama5d2: add macro & field definitions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

They will be used on SAMA5D2 PTC board.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
index b040256..b805a2c 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
@@ -32,6 +32,30 @@ struct atmel_sfr {
 #define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
 #define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
 
+/* Bit field in EBICFG */
+#define AT91_SFR_EBICFG_DRIVE0		(0x3 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_LOW		(0x0 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_MEDIUM		(0x2 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_HIGH		(0x3 << 0)
+#define AT91_SFR_EBICFG_PULL0		(0x3 << 2)
+#define AT91_SFR_EBICFG_PULL0_UP		(0x0 << 2)
+#define AT91_SFR_EBICFG_PULL0_NONE		(0x1 << 2)
+#define AT91_SFR_EBICFG_PULL0_DOWN		(0x3 << 2)
+#define AT91_SFR_EBICFG_SCH0		(0x1 << 4)
+#define AT91_SFR_EBICFG_SCH0_OFF		(0x0 << 4)
+#define AT91_SFR_EBICFG_SCH0_ON			(0x1 << 4)
+#define AT91_SFR_EBICFG_DRIVE1		(0x3 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_LOW		(0x0 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_MEDIUM		(0x2 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_HIGH		(0x3 << 8)
+#define AT91_SFR_EBICFG_PULL1		(0x3 << 10)
+#define AT91_SFR_EBICFG_PULL1_UP		(0x0 << 10)
+#define AT91_SFR_EBICFG_PULL1_NONE		(0x1 << 10)
+#define AT91_SFR_EBICFG_PULL1_DOWN		(0x3 << 10)
+#define AT91_SFR_EBICFG_SCH1		(0x1 << 12)
+#define AT91_SFR_EBICFG_SCH1_OFF		(0x0 << 12)
+#define AT91_SFR_EBICFG_SCH1_ON			(0x1 << 12)
+
 /* Bit field in AICREDIR */
 #define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
 
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index dd5a2a7..25c8541 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -135,7 +135,11 @@
 /*
  * Address Memory Space
  */
+#define ATMEL_BASE_CS0			0x10000000
 #define ATMEL_BASE_DDRCS		0x20000000
+#define ATMEL_BASE_CS1			0x60000000
+#define ATMEL_BASE_CS2			0x70000000
+#define ATMEL_BASE_CS3			0x80000000
 #define ATMEL_BASE_QSPI0_AES_MEM	0x90000000
 #define ATMEL_BASE_QSPI1_AES_MEM	0x98000000
 #define ATMEL_BASE_SDMMC0		0xa0000000
@@ -165,6 +169,7 @@
  */
 #define ATMEL_BASE_PMECC	(ATMEL_BASE_HSMC + 0x70)
 #define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_HSMC + 0x500)
+#define ATMEL_BASE_SMC		(ATMEL_BASE_HSMC + 0x700)
 
 #define ATMEL_BASE_PIOB		(ATMEL_BASE_PIOA + 0x40)
 #define ATMEL_BASE_PIOC		(ATMEL_BASE_PIOB + 0x40)
-- 
cgit v0.10.2


From 9989c1567d53a2558b872fabc39d1f8a9383c3ca Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Fri, 26 Feb 2016 17:20:26 +0800
Subject: board: atmel: add SAMA5D2 PTC Engineering board
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The board supports following features:
 - Boot media support: NAND Flash/SPI Flash
 - Support ethernet
 - Support USB mass storage

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9ce775e..73a9c74 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
 
+config TARGET_SAMA5D2_PTC
+	bool "SAMA5D2 PTC board"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_SAMA5D2_XPLAINED
 	bool "SAMA5D2 Xplained board"
 	select CPU_V7
@@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
 source "board/atmel/at91sam9n12ek/Kconfig"
 source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_ptc/Kconfig"
 source "board/atmel/sama5d2_xplained/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig
new file mode 100644
index 0000000..d2661c6
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_PTC
+
+config SYS_BOARD
+	default "sama5d2_ptc"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_ptc"
+
+endif
diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS
new file mode 100644
index 0000000..7ab03d6
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D2 PTC Engineering BOARD
+M:	Wenyou Yang <wenyou.yang@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d2_ptc/
+F:	include/configs/sama5d2_ptc.h
+F:	configs/sama5d2_ptc_spiflash_defconfig
+F:	configs/sama5d2_ptc_nandflash_defconfig
diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile
new file mode 100644
index 0000000..1fe0392
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Atmel
+#		     Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d2_ptc.o
diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
new file mode 100644
index 0000000..9e6544b
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d3_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+	at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+	writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
+	       AT91_SFR_EBICFG_PULL0_NONE |
+	       AT91_SFR_EBICFG_DRIVE1_HIGH |
+	       AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0);	/* D0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0);	/* D1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0);	/* D2 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0);	/* D3 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0);	/* D4 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0);	/* D5 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0);	/* D6 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0);	/* D7 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0);	/* RE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0);	/* WE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1);	/* NCS */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1);	/* RDY */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1);	/* ALE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1);	/* CLE */
+}
+
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
+}
+
+static void board_gmac_hw_init(void)
+{
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */
+
+	at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1);	/* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
+
+	at91_periph_clk_enable(CONFIG_USART_ID);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	board_uart0_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	board_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+	board_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	board_gmac_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	if (rc)
+		printf("GMAC register failed\n");
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+	board_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+	board_nand_hw_init();
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DIS_DLL |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	at91_plla_init(AT91_PMC_PLLAR_29 |
+		       AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+		       AT91_PMC_PLLXR_MUL(82) |
+		       AT91_PMC_PLLXR_DIV(1));
+
+	at91_pllicpr_init(0);
+
+	at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
+		      AT91_PMC_MCKR_PLLADIV_2 |
+		      AT91_PMC_MCKR_MDIV_3 |
+		      AT91_PMC_MCKR_CSS_PLLA);
+}
+#endif
diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig
new file mode 100644
index 0000000..7425184
--- /dev/null
+++ b/configs/sama5d2_ptc_nandflash_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig
new file mode 100644
index 0000000..27fc394
--- /dev/null
+++ b/configs/sama5d2_ptc_spiflash_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h
new file mode 100644
index 0000000..d91d75e
--- /dev/null
+++ b/include/configs/sama5d2_ptc.h
@@ -0,0 +1,155 @@
+/*
+ * Configuration settings for the SAMA5D2 PTC Engineering board.
+ *
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_UART0
+#define CONFIG_USART_ID			ATMEL_ID_UART0
+
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x210000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2_PTC"
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_OFFSET_REDUND
+#undef CONFIG_BOOTCOMMAND
+/* u-boot env in nand flash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x200000
+#define CONFIG_ENV_OFFSET_REDUND	0x400000
+#define CONFIG_BOOTCOMMAND		"nand read 0x21000000 0xb80000 0x80000;"	\
+					"nand read 0x22000000 0x600000 0x600000;"	\
+					"bootz 0x22000000 - 0x21000000"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,57600 earlyprintk "				\
+	"mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) "	\
+	"rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x200000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_PMECC_CAP		8
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+#endif
+
+#endif
-- 
cgit v0.10.2


From a9c89bf1669cbeb7bce6ae7a626eb9f2120af73f Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Mon, 11 Apr 2016 14:07:17 +0800
Subject: board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix the missing pin config of the SDMMC0 interface.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 10edf28..04422ce 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -171,6 +171,7 @@ static void board_sdhci0_hw_init(void)
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* SDMMC0_DAT7 */
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* SDMMC0_RSTN */
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SDMMC0_VDDSEL */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SDMMC0_CD */
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
-- 
cgit v0.10.2


From 4adf6a715796de4f0e858e0246c3abf5e3c118f3 Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Mon, 11 Apr 2016 16:41:31 +0800
Subject: ARM: at91: clock: fix the GCK's clock source
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Before enabling a generated clock whose source is from the UPLL
clock, check and enable the UPLL clock.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 81e9f69..27372b3 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -162,6 +162,11 @@ int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
 	if (div > 0xff)
 		return -EINVAL;
 
+	if (clk_source == GCK_CSS_UPLL_CLK) {
+		if (at91_upll_clk_enable())
+			return -ENODEV;
+	}
+
 	writel(id, &pmc->pcr);
 	regval = readl(&pmc->pcr);
 	regval &= ~AT91_PMC_PCR_GCKCSS;
-- 
cgit v0.10.2


From 7a91e1a3835413aac3e7c894ca1ba205e6ade887 Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Mon, 11 Apr 2016 16:41:32 +0800
Subject: ARM: at91: clock: complete the GCK's clock sources
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add the UPLL clock and master clock as a clock source for getting
the generated clock frequency to complete its clock sources support.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 27372b3..76fcada 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -236,6 +236,12 @@ u32 at91_get_periph_generated_clk(u32 id)
 	case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
 		freq = gd->arch.plla_rate_hz;
 		break;
+	case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
+		freq = AT91_UTMI_PLL_CLK_FREQ;
+		break;
+	case AT91_PMC_PCR_GCKCSS_MCK_CLK:
+		freq = gd->arch.mck_rate_hz;
+		break;
 	default:
 		printf("Improper GCK clock source selection!\n");
 		freq = 0;
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index 8577c74..ca7d7d0 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -20,6 +20,8 @@
 #define GCK_CSS_MCK_CLK		4
 #define GCK_CSS_AUDIO_CLK	5
 
+#define AT91_UTMI_PLL_CLK_FREQ	480000000
+
 static inline unsigned long get_cpu_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-- 
cgit v0.10.2


From c043d8d8ce8bf1c1946c87a89b6639db3ebb4243 Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Mon, 11 Apr 2016 16:41:33 +0800
Subject: board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change the clock source of the SDHCI's generated clock from PLLA to
UPLL clock to align to Linux driver.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 04422ce..93df7ba 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -175,7 +175,7 @@ static void board_sdhci0_hw_init(void)
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
-					 GCK_CSS_PLLA_CLK, 1);
+					 GCK_CSS_UPLL_CLK, 1);
 }
 
 static void board_sdhci1_hw_init(void)
@@ -191,7 +191,7 @@ static void board_sdhci1_hw_init(void)
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
-					 GCK_CSS_PLLA_CLK, 1);
+					 GCK_CSS_UPLL_CLK, 1);
 }
 
 int board_mmc_init(bd_t *bis)
-- 
cgit v0.10.2


From 12328f25f257c347c79562ebc7f66c1a0f48bc2b Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 18 Apr 2016 18:30:41 +0200
Subject: ARM: atmel: Enable FIT image support for SAMA5Dx
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Enable the fitImage support for the entire SAMA5Dx lineup of CPUs.
The fitImage is superior image format to uImage and it is useful
to have it available.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebase on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 7fd37d6..1880256 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -21,3 +21,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index de4e6bc..de8f4d9 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -21,3 +21,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 189a3e9..1dabc5f 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -19,3 +19,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 16e3f22..458a486 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -19,3 +19,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 8d3c3cf..488d950 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -21,3 +21,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 8e15286..12f28f2 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -21,3 +21,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index ffbafae..42fcc1e 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -21,3 +21,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 1ea5cda..3110269 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 5384917..3ea4bd7 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index b709cf6..dbec4ad 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 45128e9..f2a5844 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 9c1c232..58186ce 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 59eb4dd..ab23e95 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
-- 
cgit v0.10.2


From bb0c63a5f3b05770e8cb6171be57ca69995bd447 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 22 Apr 2016 21:56:21 +0200
Subject: ARM: sama5d2: Implement boot device autodetection
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Implement support for saving ARM register R4 early during boot using
save_boot_params . Implement support for decoding the stored register
R4 value in spl_boot_device() to obtain boot device from which the
SoC booted. This way, the SPL will always load U-Boot from the same
device from which the SPL itself booted instead of using hard-coded
boot device.

This functionality is useful for example when booting sama5d2-xplained
from SD card, where by default the SPL would try loading the U-Boot
from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1),
while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired
to always boot from BOOT_DEVICE_MMC1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 4424523..d2abf31 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
-obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
+obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
diff --git a/arch/arm/mach-at91/bootparams_atmel.S b/arch/arm/mach-at91/bootparams_atmel.S
new file mode 100644
index 0000000..568094b
--- /dev/null
+++ b/arch/arm/mach-at91/bootparams_atmel.S
@@ -0,0 +1,18 @@
+/*
+ * Atmel SAMA5Dx boot parameter handling
+ *
+ * Copyright (c) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	ldr	r0, =bootrom_stash
+	str	r4, [r0, #0]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index 25c8541..ee841da 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -230,6 +230,18 @@
 /* No PMECC Galois table in ROM */
 #define NO_GALOIS_TABLE_IN_ROM
 
+/* Boot modes stored by BootROM in r4 */
+#define ATMEL_SAMA5D2_BOOT_FROM_OFF	0
+#define ATMEL_SAMA5D2_BOOT_FROM_MASK	0xf
+#define ATMEL_SAMA5D2_BOOT_FROM_SPI	(0 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_MCI	(1 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_SMC	(2 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_TWI	(3 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_QSPI	(4 << 0)
+
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF	4
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK	0xf
+
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
 unsigned int get_extension_chip_id(void);
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index 27a405a..c4ed224 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -23,6 +23,40 @@ void at91_disable_wdt(void)
 }
 #endif
 
+#if defined(CONFIG_SAMA5D2)
+struct {
+	u32	r4;
+} bootrom_stash __attribute__((section(".data")));
+
+u32 spl_boot_device(void)
+{
+	u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) &
+		  ATMEL_SAMA5D2_BOOT_FROM_MASK;
+	u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) &
+		  ATMEL_SAMA5D2_BOOT_DEV_ID_MASK;
+
+#if defined(CONFIG_SYS_USE_MMC)
+	if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) {
+		if (off == 0)
+			return BOOT_DEVICE_MMC1;
+		if (off == 1)
+			return BOOT_DEVICE_MMC2;
+		printf("ERROR: MMC controller %i not present!\n", dev);
+		hang();
+	}
+#endif
+
+#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
+	if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI)
+		return BOOT_DEVICE_SPI;
+#endif
+
+	printf("ERROR: SMC/TWI/QSPI boot device not supported!\n"
+	       "       Boot device %i, controller number %i\n", dev, off);
+
+	return BOOT_DEVICE_NONE;
+}
+#else
 u32 spl_boot_device(void)
 {
 #ifdef CONFIG_SYS_USE_MMC
@@ -34,12 +68,14 @@ u32 spl_boot_device(void)
 #endif
 	return BOOT_DEVICE_NONE;
 }
+#endif
 
 u32 spl_boot_mode(void)
 {
 	switch (spl_boot_device()) {
 #ifdef CONFIG_SYS_USE_MMC
 	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_FS;
 		break;
 #endif
-- 
cgit v0.10.2


From 7f307d93ed147fc831425189463d92e50d5c7566 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 14 Apr 2016 06:52:26 +0900
Subject: ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or
 not

Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device
tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always
load u-boot.img whether CONFIG_OF_SEPARATE is defined or not.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index a3e4aec..82ece0d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -315,11 +315,7 @@
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#ifdef CONFIG_OF_SEPARATE
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
-#endif
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
 #endif
 
 /* Disable dcache for SPL just for sure */
-- 
cgit v0.10.2


From a6b9587bad47749118229da32c7cc3c25a16d962 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 4 Mar 2016 15:56:50 +0100
Subject: gpio: zynq: Add support for reading gpio pin state

Add zynq_gpio_get_function() which return status on gpio pin.
This function enables gpio status command.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 3a995f6..4ab2356 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -299,11 +299,33 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
 	return 0;
 }
 
+static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(offset, dev) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
+
+	/* set the GPIO pin as output */
+	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg &= BIT(bank_pin_num);
+	if (reg)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
 static const struct dm_gpio_ops gpio_zynq_ops = {
 	.direction_input	= zynq_gpio_direction_input,
 	.direction_output	= zynq_gpio_direction_output,
 	.get_value		= zynq_gpio_get_value,
 	.set_value		= zynq_gpio_set_value,
+	.get_function		= zynq_gpio_get_function,
+
 };
 
 static const struct udevice_id zynq_gpio_ids[] = {
-- 
cgit v0.10.2


From 621a93e14068787fe07dd31079da9fdf0b312dea Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 25 Apr 2016 12:14:43 +0900
Subject: ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus

Commit 9f56917ab88a ("dm: core: make simple-bus compatible to
simple-mfd") made possible to import the following commit:

Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1

The SLCR (System-Level Control Registers) block is an MFD (Multi
Function Device) rather than a bus.

"simple-mfd" seems a more suitable compatible string than "simple-bus".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a327557..b618a3f 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -251,7 +251,7 @@
 		slcr: slcr@f8000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 			reg = <0xF8000000 0x1000>;
 			ranges;
 			clkc: clkc@100 {
-- 
cgit v0.10.2


From af3b4cd6b5ca548105ace3b593a745775347951c Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 22 Apr 2016 13:04:42 +0200
Subject: ARM64: zynqmp: Enable HUSH parser for all zynqmp targets

Enable HUSH for all zynqmp boards which don't have it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index cc08b03..9b40b1f 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 14d24a0..af122f7 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index e1e11b7..dcc5dd2 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 6f1cff8..98aaee6 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index a8982a0..482013f 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
-- 
cgit v0.10.2


From a1207de0e6d6526e470361fac42f2c077b43a0ad Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 22 Apr 2016 14:28:17 +0200
Subject: ARM64: zynqmp: Enable missing distro default options

Enable all options which distros requires.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 6b8e3ea..f41a2cb 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -65,6 +65,7 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
+#define CONFIG_ISO_PARTITION
 #define CONFIG_MP
 
 /* BOOTP options */
@@ -74,6 +75,19 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
 #define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
+
+/* Diff from config_distro_defaults.h */
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_AUTO_COMPLETE
+
+/* PXE */
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
 
 #if defined(CONFIG_ZYNQ_SDHCI)
 # define CONFIG_MMC
-- 
cgit v0.10.2


From 6919b4bf36357463b419c4b848b5778d7ba0874e Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 22 Apr 2016 11:48:49 +0200
Subject: ARM64: zynqmp: Add support for reading MAC from eeprom

Add support for on board eeprom with programmed MAC for using in u-boot
to have uniq address for every board.
Most of the time uniq MAC address is on a label on the board.
If address is not programmed use these command to program it.

On zcu102:
ZynqMP> mm.b 0
00000000: 00 ? 00
00000001: a0 ? 0a
00000002: 35 ? 35
00000003: 02 ? 02
00000004: 00 ? ef
00000005: 00 ? 67
00000006: 00 ? q
i2c dev 5
i2c write 0 54 20 6
i2c md 54 20

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 132d724..4623cd4 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <usb.h>
 #include <dwc3-uboot.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +51,22 @@ int board_early_init_r(void)
 	return 0;
 }
 
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
+    defined(CONFIG_ZYNQ_EEPROM_BUS)
+	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
+
+	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+			ethaddr, 6))
+		printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+	return 0;
+}
+
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 /*
  * fdt_get_reg - Fill buffer by information from DT
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 30db2e4..81079fe 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -48,6 +48,12 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZCU102"
 
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_EEPROM_BUS		5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR	0x54
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET	0x20
+
 #define CONFIG_KERNEL_FDT_OFST_SIZE \
 	"kernel_offset=0x180000\0" \
 	"fdt_offset=0x100000\0" \
-- 
cgit v0.10.2


From 926782cdf8be8769ae2f9a40ec7a62af1b91ac77 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 26 Apr 2016 16:03:42 +0200
Subject: ARM64: zynqmp: Enable eMMC boot partitions commands

Enable some additional features of the eMMC boot partitions.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index f41a2cb..e36dde6 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -92,6 +92,7 @@
 #if defined(CONFIG_ZYNQ_SDHCI)
 # define CONFIG_MMC
 # define CONFIG_GENERIC_MMC
+# define CONFIG_SUPPORT_EMMC_BOOT
 # define CONFIG_SDHCI
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ	200000000
-- 
cgit v0.10.2


From 73dc3fa6fe37baed8fc5ddeedea7295efd9bbd17 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 22 Apr 2016 08:50:45 +0200
Subject: ARM64: zynqmp: Wire up debug_uart setup

It has to be enabled by debug_uart_init().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index b185593..dbf4906 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -46,6 +46,11 @@ CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 98aaee6..1ebadd2 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -39,6 +39,11 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 482013f..59e1cf1 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -39,6 +39,11 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-- 
cgit v0.10.2


From 9a23f458cbddfbfb67033a2aa60397821698a8a7 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 3 May 2016 14:20:17 +0200
Subject: ARM: zynq: Add support for SPL_LOAD_FIT

Enable minimal function to be able to compile SPL_LOAD_FIT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 723019d..9988965 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -90,3 +90,13 @@ __weak void ps7_init(void)
 	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
 	 */
 }
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
-- 
cgit v0.10.2


From 013642c2d4a652878a4e7583fe125ea76582ce55 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 29 Apr 2016 13:04:02 +0200
Subject: ARM64: zynqmp: Remove CONFIG_PREBOOT

CONFIG_PREBOOT variable is breaking ./test/py framework.
Remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index e36dde6..e6c38a5 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -159,7 +159,6 @@
 		"booti $kernel_addr - $fdt_addr\0" \
 	DFU_ALT_INFO
 
-#define CONFIG_PREBOOT		"run bootargs"
 #define CONFIG_BOOTCOMMAND	"run $modeboot"
 #define CONFIG_BOOTDELAY	3
 
-- 
cgit v0.10.2


From 71eb243be3edffdc32f3c7b577e86d9f76f6f289 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 17 Mar 2016 23:02:37 +0100
Subject: ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108

Add missing SPI flash options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index dbf4906..903dc48 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -44,6 +44,8 @@ CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_DEBUG_UART=y
-- 
cgit v0.10.2


From bd483780d3925d62dc896cc9bf1351b8a8c01ed8 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 4 May 2016 12:33:22 +0200
Subject: ARM64: zynqmp: Add debug uart for zc1751-dc1

It is helpful for debugging.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 9b40b1f..77a508e 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -41,6 +41,11 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-- 
cgit v0.10.2


From 3a3b9147892cb47f96dff1075f1494dca17b6eaf Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 10 May 2016 07:54:20 +0200
Subject: spl: Introduce new function spl_board_prepare_for_boot

Call this function before passing control from SPL.
For fpga case it is necessary to enable for example level shifters
when bitstream is programmed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 93f9bd1..caaf135 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -64,6 +64,11 @@ __weak void spl_board_prepare_for_linux(void)
 	/* Nothing to do! */
 }
 
+__weak void spl_board_prepare_for_boot(void)
+{
+	/* Nothing to do! */
+}
+
 void spl_set_header_raw_uboot(void)
 {
 	spl_image.size = CONFIG_SYS_MONITOR_LEN;
@@ -404,6 +409,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 #endif
 
 	debug("loaded - jumping to U-Boot...");
+	spl_board_prepare_for_boot();
 	jump_to_image_no_args(&spl_image);
 }
 
diff --git a/include/spl.h b/include/spl.h
index 7edfab4..335b76a 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -58,6 +58,7 @@ u32 spl_boot_mode(void);
 void spl_set_header_raw_uboot(void);
 int spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
+void spl_board_prepare_for_boot(void);
 void __noreturn jump_to_image_linux(void *arg);
 int spl_start_uboot(void);
 void spl_display_print(void);
-- 
cgit v0.10.2


From 27640fda55bf998d1eb5109b3410bf62e445e191 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 10 May 2016 09:50:35 +0200
Subject: ARM64: zynqmp: Enable option to overwrite default variables

Enable overwriting variables out of main config file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index e6c38a5..1a1892d 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -148,6 +148,7 @@
 #endif
 
 /* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"kernel_addr=0x80000\0" \
 	"fdt_addr=0x7000000\0" \
@@ -158,6 +159,7 @@
 		"load mmc $sdbootdev:$partid $kernel_addr Image && " \
 		"booti $kernel_addr - $fdt_addr\0" \
 	DFU_ALT_INFO
+#endif
 
 #define CONFIG_BOOTCOMMAND	"run $modeboot"
 #define CONFIG_BOOTDELAY	3
-- 
cgit v0.10.2


From f44e603f73ea43268f0858b9aa4daf962f1eb347 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 10 May 2016 07:55:52 +0200
Subject: ARM: zynq: Call ps7_post_config() for SPL

If ps7_post_config() is defined call it. It is enabling for example
level shifters for PL bitstreams.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 9988965..6c5415a 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -91,6 +91,21 @@ __weak void ps7_init(void)
 	 */
 }
 
+__weak int ps7_post_config(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+	 */
+	return 0;
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	ps7_post_config();
+	debug("SPL bye\n");
+}
+
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-- 
cgit v0.10.2


From 8d16e1d5931bb1323ef5307204563b7afcb3b6c3 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 28 Apr 2016 09:54:16 +0200
Subject: SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode

Support loading FIT in SPL for RAM bootmode.
CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored
in memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index caaf135..bdde716 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -140,20 +140,47 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	image_entry();
 }
 
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
+# define CONFIG_SPL_LOAD_FIT_ADDRESS	0
+#endif
+
 #ifdef CONFIG_SPL_RAM_DEVICE
+static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
+			       ulong count, void *buf)
+{
+	debug("%s: sector %lx, count %lx, buf %lx\n",
+	      __func__, sector, count, (ulong)buf);
+	memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
+	return count;
+}
+
 static int spl_ram_load_image(void)
 {
-	const struct image_header *header;
+	struct image_header *header;
 
-	/*
-	 * Get the header.  It will point to an address defined by handoff
-	 * which will tell where the image located inside the flash. For
-	 * now, it will temporary fixed to address pointed by U-Boot.
-	 */
-	header = (struct image_header *)
-		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+	header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
 
-	spl_parse_image_header(header);
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.bl_len = 1;
+		load.read = spl_ram_load_read;
+		spl_load_simple_fit(&load, 0, header);
+	} else {
+		debug("Legacy image\n");
+		/*
+		 * Get the header.  It will point to an address defined by
+		 * handoff which will tell where the image located inside
+		 * the flash. For now, it will temporary fixed to address
+		 * pointed by U-Boot.
+		 */
+		header = (struct image_header *)
+			(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+		spl_parse_image_header(header);
+	}
 
 	return 0;
 }
-- 
cgit v0.10.2


From d9b58b303120fb8fe0b7c9799e2b7682da4bec16 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 27 Apr 2016 14:03:29 +0200
Subject: tools: zynqmpimage: Add Xilinx ZynqMP boot header generation

Add support for the zynqmpimage to mkimage.
Only basic functionality is supported without encryption and register
initialization with one partition which is filled by U-Boot SPL.
For more detail information look at Xilinx ZynqMP TRM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/image.c b/common/image.c
index 26d6c9a..9824685 100644
--- a/common/image.c
+++ b/common/image.c
@@ -159,6 +159,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_RKSD,       "rksd",       "Rockchip SD Boot Image" },
 	{	IH_TYPE_RKSPI,      "rkspi",      "Rockchip SPI Boot Image" },
 	{	IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
+	{	IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index f9ee564..a8488f2 100644
--- a/include/image.h
+++ b/include/image.h
@@ -246,8 +246,9 @@ struct lmb;
 #define IH_TYPE_RKSD		24	/* Rockchip SD card		*/
 #define IH_TYPE_RKSPI		25	/* Rockchip SPI image		*/
 #define IH_TYPE_ZYNQIMAGE	26	/* Xilinx Zynq Boot Image */
+#define IH_TYPE_ZYNQMPIMAGE	27	/* Xilinx ZynqMP Boot Image */
 
-#define IH_TYPE_COUNT		27	/* Number of image types */
+#define IH_TYPE_COUNT		28	/* Number of image types */
 
 /*
  * Compression Types
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ec8d8f1..6d2017d 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -129,7 +129,12 @@ endif
 boot.bin: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 else
+ifdef CONFIG_ARCH_ZYNQ
 MKIMAGEFLAGS_boot.bin = -T zynqimage
+endif
+ifdef CONFIG_ARCH_ZYNQMP
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage
+endif
 
 spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
@@ -157,6 +162,8 @@ ifdef CONFIG_ARCH_ZYNQ
 ALL-y	+= $(obj)/boot.bin
 endif
 
+ALL-(CONFIG_ARCH_ZYNQMP)	+= $(obj)/boot.bin
+
 all:	$(ALL-y)
 
 quiet_cmd_cat = CAT     $@
diff --git a/tools/Makefile b/tools/Makefile
index da50e1b..63355aa 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \
 			common/hash.o \
 			ublimage.o \
 			zynqimage.o \
+			zynqmpimage.o \
 			$(LIBFDT_OBJS) \
 			$(RSA_OBJS-y)
 
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
new file mode 100644
index 0000000..3f28eb4
--- /dev/null
+++ b/tools/zynqmpimage.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The following Boot Header format/structures and values are defined in the
+ * following documents:
+ *   * ug1085 ZynqMP TRM (Chapter 9, Table 9-3)
+ *
+ * Expected Header Size = 0x9C0
+ * Forced as 'little' endian, 32-bit words
+ *
+ *  0x  0 - Interrupt table (8 words)
+ *  ...     (Default value = 0xeafffffe)
+ *  0x 1f
+ *  0x 20 - Width detection
+ *         * DEFAULT_WIDTHDETECTION    0xaa995566
+ *  0x 24 - Image identifier
+ *         * DEFAULT_IMAGEIDENTIFIER   0x584c4e58
+ *  0x 28 - Encryption
+ *         * 0x00000000 - None
+ *         * 0xa5c3c5a3 - eFuse
+ *         * 0xa5c3c5a7 - obfuscated key in eFUSE
+ *         * 0x3a5c3c5a - bbRam
+ *         * 0xa35c7ca5 - obfuscated key in boot header
+ *  0x 2C - Image load
+ *  0x 30 - Image offset
+ *  0x 34 - PFW image length
+ *  0x 38 - Total PFW image length
+ *  0x 3C - Image length
+ *  0x 40 - Total image length
+ *  0x 44 - Image attributes
+ *  0x 48 - Header checksum
+ *  0x 4c - Obfuscated key
+ *  ...
+ *  0x 68
+ *  0x 6c - Reserved
+ *  0x 70 - User defined
+ *  ...
+ *  0x 9c
+ *  0x a0 - Secure header initialization vector
+ *  ...
+ *  0x a8
+ *  0x ac - Obfuscated key initialization vector
+ *  ...
+ *  0x b4
+ *  0x b8 - Register Initialization, 511 Address and Data word pairs
+ *         * List is terminated with an address of 0xffffffff or
+ *  ...    * at the max number of entries
+ *  0x8b4
+ *  0x8b8 - Reserved
+ *  ...
+ *  0x9bf
+ *  0x9c0 - Data/Image starts here or above
+ */
+
+#include "imagetool.h"
+#include "mkimage.h"
+#include <image.h>
+
+#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
+#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
+#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
+#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
+
+enum {
+	ENCRYPTION_EFUSE = 0xa5c3c5a3,
+	ENCRYPTION_OEFUSE = 0xa5c3c5a7,
+	ENCRYPTION_BBRAM = 0x3a5c3c5a,
+	ENCRYPTION_OBBRAM = 0xa35c7ca5,
+	ENCRYPTION_NONE = 0x0,
+};
+
+struct zynqmp_reginit {
+	uint32_t address;
+	uint32_t data;
+};
+
+#define HEADER_INTERRUPT_VECTORS	8
+#define HEADER_REGINITS			256
+
+struct zynqmp_header {
+	uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
+	uint32_t width_detection; /* 0x20 */
+	uint32_t image_identifier; /* 0x24 */
+	uint32_t encryption; /* 0x28 */
+	uint32_t image_load; /* 0x2c */
+	uint32_t image_offset; /* 0x30 */
+	uint32_t pfw_image_length; /* 0x34 */
+	uint32_t total_pfw_image_length; /* 0x38 */
+	uint32_t image_size; /* 0x3c */
+	uint32_t image_stored_size; /* 0x40 */
+	uint32_t image_attributes; /* 0x44 */
+	uint32_t checksum; /* 0x48 */
+	uint32_t __reserved1[27]; /* 0x4c */
+	struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
+	uint32_t __reserved4[66]; /* 0x9c0 */
+};
+
+static struct zynqmp_header zynqmpimage_header;
+
+static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
+{
+	uint32_t checksum = 0;
+
+	if (ptr == NULL)
+		return 0;
+
+	checksum += le32_to_cpu(ptr->width_detection);
+	checksum += le32_to_cpu(ptr->image_identifier);
+	checksum += le32_to_cpu(ptr->encryption);
+	checksum += le32_to_cpu(ptr->image_load);
+	checksum += le32_to_cpu(ptr->image_offset);
+	checksum += le32_to_cpu(ptr->pfw_image_length);
+	checksum += le32_to_cpu(ptr->total_pfw_image_length);
+	checksum += le32_to_cpu(ptr->image_size);
+	checksum += le32_to_cpu(ptr->image_stored_size);
+	checksum += le32_to_cpu(ptr->image_attributes);
+	checksum = ~checksum;
+
+	return cpu_to_le32(checksum);
+}
+
+static void zynqmpimage_default_header(struct zynqmp_header *ptr)
+{
+	int i;
+
+	if (ptr == NULL)
+		return;
+
+	ptr->width_detection = HEADER_WIDTHDETECTION;
+	ptr->image_attributes = 0x800;
+	ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
+	ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
+
+	/* Setup not-supported/constant/reserved fields */
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
+		ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		ptr->register_init[i].address = HEADER_REGINIT_NULL;
+		ptr->register_init[i].data = 0;
+	}
+
+	/*
+	 * Certain reserved fields are required to be set to 0, ensure they are
+	 * set as such.
+	 */
+	ptr->pfw_image_length = 0x0;
+	ptr->total_pfw_image_length = 0x0;
+}
+
+/* mkimage glue functions */
+static int zynqmpimage_verify_header(unsigned char *ptr, int image_size,
+		struct image_tool_params *params)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+
+	if (image_size < sizeof(struct zynqmp_header))
+		return -1;
+
+	if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
+		return -1;
+	if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
+		return -1;
+
+	if (zynqmpimage_checksum(zynqhdr) != zynqhdr->checksum)
+		return -1;
+
+	return 0;
+}
+
+static void zynqmpimage_print_header(const void *ptr)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+	int i;
+
+	printf("Image Type   : Xilinx Zynq Boot Image support\n");
+	printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
+	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
+	       (unsigned long)le32_to_cpu(zynqhdr->image_size),
+	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
+	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
+
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
+		if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
+			continue;
+
+		printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
+		       le32_to_cpu(zynqhdr->interrupt_vectors[i]));
+	}
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
+			break;
+
+		if (i == 0)
+			printf("Custom Register Initialization:\n");
+
+		printf("    @ 0x%08x -> 0x%08x\n",
+		       le32_to_cpu(zynqhdr->register_init[i].address),
+		       le32_to_cpu(zynqhdr->register_init[i].data));
+	}
+}
+
+static int zynqmpimage_check_params(struct image_tool_params *params)
+{
+	if (!params)
+		return 0;
+
+	if (params->addr != 0x0) {
+		fprintf(stderr, "Error: Load Address cannot be specified.\n");
+		return -1;
+	}
+
+	/*
+	 * If the entry point is specified ensure it is 64 byte aligned.
+	 */
+	if (params->eflag && (params->ep % 64 != 0)) {
+		fprintf(stderr,
+			"Error: Entry Point must be aligned to a 64-byte boundary.\n");
+		return -1;
+	}
+
+	return !(params->lflag || params->dflag);
+}
+
+static int zynqmpimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_ZYNQMPIMAGE)
+		return EXIT_SUCCESS;
+	return EXIT_FAILURE;
+}
+
+static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+		struct image_tool_params *params)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+	zynqmpimage_default_header(zynqhdr);
+
+	/* place image directly after header */
+	zynqhdr->image_offset =
+		cpu_to_le32((uint32_t)sizeof(struct zynqmp_header));
+	zynqhdr->image_size = cpu_to_le32(params->file_size -
+					  sizeof(struct zynqmp_header));
+	zynqhdr->image_stored_size = zynqhdr->image_size;
+	zynqhdr->image_load = 0xfffc0000;
+	if (params->eflag)
+		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+
+	zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
+}
+
+U_BOOT_IMAGE_TYPE(
+	zynqmpimage,
+	"Xilinx ZynqMP Boot Image support",
+	sizeof(struct zynqmp_header),
+	(void *)&zynqmpimage_header,
+	zynqmpimage_check_params,
+	zynqmpimage_verify_header,
+	zynqmpimage_print_header,
+	zynqmpimage_set_header,
+	NULL,
+	zynqmpimage_check_image_types,
+	NULL,
+	NULL
+);
-- 
cgit v0.10.2


From 0a8c4f67f3783eaf5330953b957e232dde747331 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 12 May 2016 13:44:01 +0200
Subject: ARM64: zynqmp: Align gic ranges for 64k in device tree

The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.

This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index fb95b48..c6ba872 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -253,9 +253,9 @@
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			reg = <0x0 0xf9010000 0x10000>,
-			      <0x0 0xf902f000 0x2000>,
+			      <0x0 0xf9020000 0x20000>,
 			      <0x0 0xf9040000 0x20000>,
-			      <0x0 0xf906f000 0x2000>;
+			      <0x0 0xf9060000 0x20000>;
 			interrupt-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <1 9 0xf04>;
-- 
cgit v0.10.2


From c9811e14cfee68e3df054fd1597064f58c4e7e27 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 22 Feb 2016 09:57:27 +0100
Subject: ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI

Add missing u-boot,dm-pre-reloc to get IPs initialized.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index c6ba872..619450e 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -264,6 +264,7 @@
 
 	amba: amba {
 		compatible = "simple-bus";
+		u-boot,dm-pre-reloc;
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0 0xffffffff>;
@@ -674,6 +675,7 @@
 		};
 
 		sdhci0: sdhci@ff160000 {
+			u-boot,dm-pre-reloc;
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -685,6 +687,7 @@
 		};
 
 		sdhci1: sdhci@ff170000 {
+			u-boot,dm-pre-reloc;
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -776,6 +779,7 @@
 		};
 
 		uart0: serial@ff000000 {
+			u-boot,dm-pre-reloc;
 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -786,6 +790,7 @@
 		};
 
 		uart1: serial@ff010000 {
+			u-boot,dm-pre-reloc;
 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
-- 
cgit v0.10.2


From e6a9ed04e78cf87ec97e306fa4e7a1669ef98df6 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 20 Nov 2015 13:17:22 +0100
Subject: ARM64: zynqmp: Add SPL support support

Support RAM and MMC boot mode in SPL also with SPL_FIT images.

In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
 aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
 mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
 -d bl31.bin atf.ub
 cp spl/boot.bin <sdcard fat partition>
 cp atf.ub <sdcard fat partition>
 cp u-boot.bin <sdcard fat partition>

2) Boot flow with full U-Boot(EL3):
 cp spl/boot.bin <sdcard>
 cp u-boot*.img <sdcard>

3) emmc boot mode
 dd if=/dev/zero of=sd.img bs=1024 count=1024
 parted sd.img mktable msdos
 parted sd.img mkpart p fat32 0% 100%
 kpartx -a sd.img
 mkfs.vfat /dev/mapper/loop0p1
 mount /dev/mapper/loop0p1 /mnt/
 cp spl/boot.bin /mnt
 cp u-boot.img /mnt
 cp u-boot.bin /mnt
 cp atf.ub /mnt
 umount /dev/mapper/loop0p1
 kpartx -d sd.img
 cp sd.img /tftpboot/

 and program it via u-boot
 tftpb 10000 sd.img
 mmcinfo
 mmc write 10000 0 $filesize
 mmc rescan
 mmc part
 ls mmc 0

psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.

The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b65d8e..729b181 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -594,6 +594,7 @@ config ARCH_ZYNQMP
 	select DM
 	select OF_CONTROL
 	select DM_SERIAL
+	select SUPPORT_SPL
 
 config TEGRA
 	bool "NVIDIA Tegra"
diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index d0ed222..be8673a 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -9,3 +9,4 @@ obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-y	+= slcr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
new file mode 100644
index 0000000..e3e2a4f
--- /dev/null
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2015 - 2016 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+void board_init_f(ulong dummy)
+{
+	psu_init();
+	board_early_init_r();
+
+#ifdef CONFIG_DEBUG_UART
+	/* Uart debug for sure */
+	debug_uart_init();
+	puts("Debug uart enabled\n"); /* or printch() */
+#endif
+	/* Delay is required for clocks to be propagated */
+	udelay(1000000);
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* No need to call timer init - it is empty for ZynqMP */
+	board_init_r(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	preloader_console_init();
+	board_init();
+}
+#endif
+
+u32 spl_boot_device(void)
+{
+	u32 reg = 0;
+	u8 bootmode;
+
+	reg = readl(&crlapb_base->boot_mode);
+	bootmode = reg & BOOT_MODES_MASK;
+
+	switch (bootmode) {
+	case JTAG_MODE:
+		return BOOT_DEVICE_RAM;
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD_MODE1:
+		return BOOT_DEVICE_MMC1;
+#endif
+	default:
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_RAM:
+		return 0;
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FS;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+__weak void psu_init(void)
+{
+	 /*
+	  * This function is overridden by the one in
+	  * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+	  */
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 021626d..1db2bd6 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -17,4 +17,6 @@ int zynq_slcr_get_mio_pin_status(const char *periph);
 
 unsigned int zynqmp_get_silicon_version(void);
 
+void psu_init(void);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 2ab3f19..90f00c6 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -1,8 +1,29 @@
 #
-# (C) Copyright 2014 - 2015 Xilinx, Inc.
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
 # Michal Simek <michal.simek@xilinx.com>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
 obj-y	:= zynqmp.o
+
+hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+	$(hw-platform-y)/psu_init_gpl.o)
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
new file mode 100644
index 0000000..57ca4ad
--- /dev/null
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+
+#define xil_printf(...)
+
+void Xil_ICacheEnable(void)
+{}
+
+void Xil_DCacheEnable(void)
+{}
+
+void Xil_ICacheDisable(void)
+{}
+
+void Xil_DCacheDisable(void)
+{}
+
+void Xil_Out32(unsigned long addr, unsigned long val)
+{
+	writel(val, addr);
+}
+
+int Xil_In32(unsigned long addr)
+{
+	return readl(addr);
+}
+
+#endif /* XIL_IO_H */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 1a1892d..b2fa164 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -41,7 +41,7 @@
 # define CONFIG_IDENT_STRING		" Xilinx ZynqMP"
 #endif
 
-#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		0xfffffffc
 
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
@@ -65,7 +65,9 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
-#define CONFIG_ISO_PARTITION
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_ISO_PARTITION
+#endif
 #define CONFIG_MP
 
 /* BOOTP options */
@@ -228,4 +230,41 @@
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 
+#define CONFIG_SPL_TEXT_BASE		0xfffc0000
+#define CONFIG_SPL_MAX_SIZE		0x20000
+
+/* Just random location in OCM */
+#define CONFIG_SPL_BSS_START_ADDR	0x1000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x2000000
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+
+#define CONFIG_SPL_OS_BOOT
+/* u-boot is like dtb */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"u-boot.bin"
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x8000000
+
+/* ATF is my kernel image */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"atf.ub"
+
+/* FIT load address for RAM boot */
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	0x10000000
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI
+# define CONFIG_SPL_MMC_SUPPORT
+# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
+# define CONFIG_SPL_LIBDISK_SUPPORT
+# define CONFIG_SPL_FAT_SUPPORT
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#endif
+
 #endif /* __XILINX_ZYNQMP_H */
-- 
cgit v0.10.2


From 293271cbc3080a3d23afe48adafbfba271cd6761 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 17 May 2016 13:33:11 +0200
Subject: ARM64: zynqmp: Enable CLK framework

ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 903dc48..37b8052 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -40,6 +40,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 77a508e..fa761e5 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -31,6 +31,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index af122f7..2811d4b 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index dcc5dd2..3711084 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -26,6 +26,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 1ebadd2..46a5dd0 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 59e1cf1..96a2be1 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
-- 
cgit v0.10.2


From 905bca6c2d65fc639cffdca42004602e041eb97a Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 17 May 2016 14:32:00 +0200
Subject: fpga: Fix typo in function comment

Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index d94eb5c..7e2f3e1 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -120,7 +120,7 @@ static int fpga_dev_info(int devnum)
 }
 
 /*
- * fgpa_init is usually called from misc_init_r() and MUST be called
+ * fpga_init is usually called from misc_init_r() and MUST be called
  * before any of the other fpga functions are used.
  */
 void fpga_init(void)
-- 
cgit v0.10.2


From ed0cea7c5271cbfd37089f3a6392ba383eda06f7 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 17 May 2016 13:58:44 +0200
Subject: mkimage: Report information about fpga

Add FIT_FPGA_PROP that user can identify an optional
entry for fpga.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/image-fit.c b/common/image-fit.c
index c86b7c6..8a0ca2a 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1483,6 +1483,10 @@ void fit_conf_print(const void *fit, int noffset, const char *p)
 	if (uname)
 		printf("%s  FDT:          %s\n", p, uname);
 
+	uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
+	if (uname)
+		printf("%s  FPGA:         %s\n", p, uname);
+
 	/* Print out all of the specified loadables */
 	for (loadables_index = 0;
 	     fdt_get_string_index(fit, noffset,
diff --git a/common/image.c b/common/image.c
index 9824685..ec78b7e 100644
--- a/common/image.c
+++ b/common/image.c
@@ -160,6 +160,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_RKSPI,      "rkspi",      "Rockchip SPI Boot Image" },
 	{	IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
 	{	IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
+	{	IH_TYPE_FPGA,       "fpga",       "FPGA Image" },
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/doc/uImage.FIT/multi-with-fpga.its b/doc/uImage.FIT/multi-with-fpga.its
new file mode 100644
index 0000000..0cdb31f
--- /dev/null
+++ b/doc/uImage.FIT/multi-with-fpga.its
@@ -0,0 +1,67 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ * This example makes use of the 'loadables' field
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Configuration to load fpga before Kernel";
+	#address-cells = <1>;
+
+	images {
+		fdt@1 {
+			description = "zc706";
+			data = /incbin/("/tftpboot/devicetree.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			load = <0x10000000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+
+		fpga@1 {
+			description = "FPGA";
+			data = /incbin/("/tftpboot/download.bit");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+			load = <0x30000000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+
+		linux_kernel@1 {
+			description = "Linux";
+			data = /incbin/("/tftpboot/zImage");
+			type = "kernel";
+			arch = "arm";
+			os = "linux";
+			compression = "none";
+			load = <0x8000>;
+			entry = <0x8000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+	};
+
+	configurations {
+		default = "config@2";
+		config@1 {
+			description = "Linux";
+			kernel = "linux_kernel@1";
+			fdt = "fdt@1";
+		};
+
+		config@2 {
+			description = "Linux with fpga";
+			kernel = "linux_kernel@1";
+			fdt = "fdt@1";
+			fpga = "fpga@1";
+		};
+	};
+};
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 9c527c3..3f54180 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -236,6 +236,7 @@ o config@1
   |- kernel = "kernel sub-node unit name"
   |- ramdisk = "ramdisk sub-node unit name"
   |- fdt = "fdt sub-node unit-name"
+  |- fpga = "fpga sub-node unit-name"
   |- loadables = "loadables sub-node unit-name"
 
 
@@ -251,6 +252,8 @@ o config@1
     "fdt type").
   - setup : Unit name of the corresponding setup binary (used for booting
     an x86 kernel). This contains the setup.bin file built by the kernel.
+  - fpga : Unit name of the corresponding fpga bitstream blob
+    (component image node of a "fpga type").
   - loadables : Unit name containing a list of additional binaries to be
     loaded at their given locations.  "loadables" is a comma-separated list
     of strings. U-Boot will load each binary at its given start-address.
diff --git a/include/image.h b/include/image.h
index a8488f2..e2a90ca 100644
--- a/include/image.h
+++ b/include/image.h
@@ -247,8 +247,9 @@ struct lmb;
 #define IH_TYPE_RKSPI		25	/* Rockchip SPI image		*/
 #define IH_TYPE_ZYNQIMAGE	26	/* Xilinx Zynq Boot Image */
 #define IH_TYPE_ZYNQMPIMAGE	27	/* Xilinx ZynqMP Boot Image */
+#define IH_TYPE_FPGA		28	/* FPGA Image */
 
-#define IH_TYPE_COUNT		28	/* Number of image types */
+#define IH_TYPE_COUNT		29	/* Number of image types */
 
 /*
  * Compression Types
@@ -810,6 +811,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end);
 #define FIT_LOADABLE_PROP	"loadables"
 #define FIT_DEFAULT_PROP	"default"
 #define FIT_SETUP_PROP		"setup"
+#define FIT_FPGA_PROP		"fpga"
 
 #define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
 
-- 
cgit v0.10.2


From 55259e7cda875bff3e0fcfd5fc61478f40872841 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 18 May 2016 12:37:22 +0200
Subject: net: xilinx: Handle error value from phy_startup()

Handle error returned by phy_startup() properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 5862bf0..7b85aa0 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -250,7 +250,7 @@ static void emaclite_stop(struct udevice *dev)
 
 static int setup_phy(struct udevice *dev)
 {
-	int i;
+	int i, ret;
 	u16 phyreg;
 	struct xemaclite *emaclite = dev_get_priv(dev);
 	struct phy_device *phydev;
@@ -302,7 +302,9 @@ static int setup_phy(struct udevice *dev)
 	phydev->advertising = supported;
 	emaclite->phydev = phydev;
 	phy_config(phydev);
-	phy_startup(phydev);
+	ret = phy_startup(phydev);
+	if (ret)
+		return ret;
 
 	if (!phydev->link) {
 		printf("%s: No link.\n", phydev->dev->name);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index aec8077..3704ce0 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -360,6 +360,7 @@ static int zynq_phy_init(struct udevice *dev)
 static int zynq_gem_init(struct udevice *dev)
 {
 	u32 i, nwconfig;
+	int ret;
 	unsigned long clk_rate = 0;
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
 	struct zynq_gem_regs *regs = priv->iobase;
@@ -427,7 +428,9 @@ static int zynq_gem_init(struct udevice *dev)
 		priv->init++;
 	}
 
-	phy_startup(priv->phydev);
+	ret = phy_startup(priv->phydev);
+	if (ret)
+		return ret;
 
 	if (!priv->phydev->link) {
 		printf("%s: No link.\n", priv->phydev->dev->name);
-- 
cgit v0.10.2


From ef5e821bd89aa059a20841e041221dadbf60aa7d Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 18 May 2016 12:48:57 +0200
Subject: phy: Return correct error code when timeout happens

Return -ETIMEDOUT if timeout happens.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index b8b1157..d24451b 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -103,7 +103,7 @@ static int m88e1011s_config(struct phy_device *phydev)
 /* Parse the 88E1011's status register for speed and duplex
  * information
  */
-static uint m88e1xxx_parse_status(struct phy_device *phydev)
+static int m88e1xxx_parse_status(struct phy_device *phydev)
 {
 	unsigned int speed;
 	unsigned int mii_reg;
@@ -120,7 +120,7 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev)
 			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 				puts(" TIMEOUT !\n");
 				phydev->link = 0;
-				break;
+				return -ETIMEDOUT;
 			}
 
 			if ((i++ % 1000) == 0)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 23c82bb..68e752e 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -248,7 +248,7 @@ int genphy_update_link(struct phy_device *phydev)
 			if (i > PHY_ANEG_TIMEOUT) {
 				printf(" TIMEOUT !\n");
 				phydev->link = 0;
-				return 0;
+				return -ETIMEDOUT;
 			}
 
 			if (ctrlc()) {
-- 
cgit v0.10.2


From b733c278d7adc48c71bd06faf359db3d9e385185 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 18 May 2016 12:46:12 +0200
Subject: net: phy: Handle phy_startup() error codes properly

Propagate error code from genphy_update_link() to phy startup().

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 4b2808e..9871cc3 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -84,11 +84,14 @@ static int bcm54xx_parse_status(struct phy_device *phydev)
 
 static int bcm54xx_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	bcm54xx_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return bcm54xx_parse_status(phydev);
 }
 
 /* Broadcom BCM5482S */
@@ -139,11 +142,14 @@ static int bcm5482_config(struct phy_device *phydev)
 
 static int bcm_cygnus_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return genphy_parse_link(phydev);
 }
 
 static int bcm_cygnus_config(struct phy_device *phydev)
@@ -239,17 +245,21 @@ static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
  */
 static int bcm5482_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	if (bcm5482_is_serdes(phydev)) {
 		bcm5482_parse_serdes_sr(phydev);
 		phydev->port = PORT_FIBRE;
-	} else {
-		/* Wait for auto-negotiation to complete or fail */
-		genphy_update_link(phydev);
-		/* Parse BCM54xx copper aux status register */
-		bcm54xx_parse_status(phydev);
+		return 0;
 	}
 
-	return 0;
+	/* Wait for auto-negotiation to complete or fail */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	/* Parse BCM54xx copper aux status register */
+	return bcm54xx_parse_status(phydev);
 }
 
 static struct phy_driver BCM5461S_driver = {
diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c
index 0c039fe..0a6e410 100644
--- a/drivers/net/phy/davicom.c
+++ b/drivers/net/phy/davicom.c
@@ -60,10 +60,13 @@ static int dm9161_parse_status(struct phy_device *phydev)
 
 static int dm9161_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dm9161_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dm9161_parse_status(phydev);
 }
 
 static struct phy_driver DM9161_driver = {
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index 70c15e2..2fe0132 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -79,9 +79,13 @@ static int et1011c_parse_status(struct phy_device *phydev)
 
 static int et1011c_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	et1011c_parse_status(phydev);
-	return 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return et1011c_parse_status(phydev);
 }
 
 static struct phy_driver et1011c_driver = {
diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c
index 91838ce..9abc2a8 100644
--- a/drivers/net/phy/lxt.c
+++ b/drivers/net/phy/lxt.c
@@ -49,10 +49,13 @@ static int lxt971_parse_status(struct phy_device *phydev)
 
 static int lxt971_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	lxt971_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return lxt971_parse_status(phydev);
 }
 
 static struct phy_driver LXT971_driver = {
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index d24451b..64713fb 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -162,10 +162,13 @@ static int m88e1xxx_parse_status(struct phy_device *phydev)
 
 static int m88e1011s_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	m88e1xxx_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1111S */
@@ -358,13 +361,16 @@ static int m88e1118_config(struct phy_device *phydev)
 
 static int m88e1118_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Change Page Number */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 
-	genphy_update_link(phydev);
-	m88e1xxx_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1121R */
@@ -421,12 +427,15 @@ static int m88e1145_config(struct phy_device *phydev)
 
 static int m88e1145_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
 			MIIM_88E1145_PHY_LED_DIRECT);
-	m88e1xxx_parse_status(phydev);
-
-	return 0;
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1149S */
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 8fcf737..b08788a 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -181,7 +181,12 @@ static struct phy_driver KS8721_driver = {
 static int ksz90xx_startup(struct phy_device *phydev)
 {
 	unsigned phy_ctl;
-	genphy_update_link(phydev);
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
 	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
 
 	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c
index d2e4c3c..1592e9b 100644
--- a/drivers/net/phy/natsemi.c
+++ b/drivers/net/phy/natsemi.c
@@ -93,10 +93,13 @@ static int dp83865_parse_status(struct phy_device *phydev)
 
 static int dp83865_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dp83865_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dp83865_parse_status(phydev);
 }
 
 
@@ -134,10 +137,13 @@ static int dp83848_parse_status(struct phy_device *phydev)
 
 static int dp83848_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dp83848_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dp83848_parse_status(phydev);
 }
 
 static struct phy_driver DP83848_driver = {
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 68e752e..98986bb 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -431,10 +431,13 @@ int genphy_config(struct phy_device *phydev)
 
 int genphy_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 int genphy_shutdown(struct phy_device *phydev)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 9d7f55b..7a99cb0 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -208,28 +208,38 @@ static int rtl8211f_parse_status(struct phy_device *phydev)
 
 static int rtl8211x_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	rtl8211x_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return rtl8211x_parse_status(phydev);
 }
 
 static int rtl8211e_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 static int rtl8211f_startup(struct phy_device *phydev)
 {
+	int ret;
+
+	/* Read the Status (2x to make sure link is right) */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	rtl8211f_parse_status(phydev);
 
-	return 0;
+	return rtl8211f_parse_status(phydev);
 }
 
 /* Support for RTL8211B PHY */
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 34986a2..313fcdf 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -34,9 +34,13 @@ static int smsc_parse_status(struct phy_device *phydev)
 
 static int smsc_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	smsc_parse_status(phydev);
-	return 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return smsc_parse_status(phydev);
 }
 
 static struct phy_driver lan8700_driver = {
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 941d076..2635b82 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -112,10 +112,12 @@ static int vitesse_parse_status(struct phy_device *phydev)
 
 static int vitesse_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	vitesse_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+	return vitesse_parse_status(phydev);
 }
 
 static int cis8204_config(struct phy_device *phydev)
-- 
cgit v0.10.2


From 62afc601883e788f3f22291202d5b2a23c1a8b06 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 17 May 2016 14:03:50 +0200
Subject: image: Add boot_get_fpga() to load fpga with bootm

Add function boot_get_fpga() which find and load bitstream to
programmable logic if fpga entry is present.
Function is supported on Xilinx devices for full and partial bitstreams
in BIN and BIT format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove additional blankline in image.h

diff --git a/common/bootm.c b/common/bootm.c
index c965326..4941414 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -246,6 +246,16 @@ int bootm_find_images(int flag, int argc, char * const argv[])
 #endif
 
 #if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+	/* find bitstreams */
+	ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+			    NULL, NULL);
+	if (ret) {
+		printf("FPGA image is corrupted or invalid\n");
+		return 1;
+	}
+#endif
+
 	/* find all of the loadables */
 	ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
 			       NULL, NULL);
diff --git a/common/image-fit.c b/common/image-fit.c
index 8a0ca2a..9873957 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -422,7 +422,8 @@ void fit_image_print(const void *fit, int image_noffset, const char *p)
 	}
 
 	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
-	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
+	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK) ||
+	    (type == IH_TYPE_FPGA)) {
 		ret = fit_image_get_load(fit, image_noffset, &load);
 		printf("%s  Load Address: ", p);
 		if (ret)
@@ -1571,6 +1572,8 @@ static const char *fit_get_image_type_property(int type)
 		return FIT_SETUP_PROP;
 	case IH_TYPE_LOADABLE:
 		return FIT_LOADABLE_PROP;
+	case IH_TYPE_FPGA:
+		return FIT_FPGA_PROP;
 	}
 
 	return "unknown";
@@ -1685,7 +1688,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 			fit_image_check_type(fit, noffset,
 					     IH_TYPE_KERNEL_NOLOAD));
 
-	os_ok = image_type == IH_TYPE_FLATDT ||
+	os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA ||
 		fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
 		fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
 
diff --git a/common/image.c b/common/image.c
index ec78b7e..0be09e5 100644
--- a/common/image.c
+++ b/common/image.c
@@ -32,6 +32,8 @@
 #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <fpga.h>
+#include <xilinx.h>
 #endif
 
 #include <u-boot/md5.h>
@@ -1212,6 +1214,96 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch,
 }
 
 #if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		  uint8_t arch, const ulong *ld_start, ulong * const ld_len)
+{
+	ulong tmp_img_addr, img_data, img_len;
+	void *buf;
+	int conf_noffset;
+	int fit_img_result;
+	char *uname, *name;
+	int err;
+	int devnum = 0; /* TODO support multi fpga platforms */
+	const fpga_desc * const desc = fpga_get_desc(devnum);
+	xilinx_desc *desc_xilinx = desc->devdesc;
+
+	/* Check to see if the images struct has a FIT configuration */
+	if (!genimg_has_config(images)) {
+		debug("## FIT configuration was not specified\n");
+		return 0;
+	}
+
+	/*
+	 * Obtain the os FIT header from the images struct
+	 * copy from dataflash if needed
+	 */
+	tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+	tmp_img_addr = genimg_get_image(tmp_img_addr);
+	buf = map_sysmem(tmp_img_addr, 0);
+	/*
+	 * Check image type. For FIT images get FIT node
+	 * and attempt to locate a generic binary.
+	 */
+	switch (genimg_get_format(buf)) {
+	case IMAGE_FORMAT_FIT:
+		conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+		err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0,
+					   (const char **)&uname);
+		if (err < 0) {
+			debug("## FPGA image is not specified\n");
+			return 0;
+		}
+		fit_img_result = fit_image_load(images,
+						tmp_img_addr,
+						(const char **)&uname,
+						&(images->fit_uname_cfg),
+						arch,
+						IH_TYPE_FPGA,
+						BOOTSTAGE_ID_FPGA_INIT,
+						FIT_LOAD_OPTIONAL_NON_ZERO,
+						&img_data, &img_len);
+
+		debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+		      uname, img_data, img_len);
+
+		if (fit_img_result < 0) {
+			/* Something went wrong! */
+			return fit_img_result;
+		}
+
+		if (img_len >= desc_xilinx->size) {
+			name = "full";
+			err = fpga_loadbitstream(devnum, (char *)img_data,
+						 img_len, BIT_FULL);
+			if (err)
+				err = fpga_load(devnum, (const void *)img_data,
+						img_len, BIT_FULL);
+		} else {
+			name = "partial";
+			err = fpga_loadbitstream(devnum, (char *)img_data,
+						 img_len, BIT_PARTIAL);
+			if (err)
+				err = fpga_load(devnum, (const void *)img_data,
+						img_len, BIT_PARTIAL);
+		}
+
+		printf("   Programming %s bitstream... ", name);
+		if (err)
+			printf("failed\n");
+		else
+			printf("OK\n");
+		break;
+	default:
+		printf("The given image format is not supported (corrupt?)\n");
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
 int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
diff --git a/include/bootstage.h b/include/bootstage.h
index 9765360..0880a68 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -198,6 +198,7 @@ enum bootstage_id {
 	BOOTSTAGE_ID_ACCUM_SCSI,
 	BOOTSTAGE_ID_ACCUM_SPI,
 	BOOTSTAGE_ID_ACCUM_DECOMP,
+	BOOTSTAGE_ID_FPGA_INIT,
 
 	/* a few spare for the user, from here */
 	BOOTSTAGE_ID_USER,
diff --git a/include/image.h b/include/image.h
index e2a90ca..a8f6bd1 100644
--- a/include/image.h
+++ b/include/image.h
@@ -496,6 +496,8 @@ int genimg_get_format(const void *img_addr);
 int genimg_has_config(bootm_headers_t *images);
 ulong genimg_get_image(ulong img_addr);
 
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, const ulong *ld_start, ulong * const ld_len);
 int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, ulong *rd_start, ulong *rd_end);
 
-- 
cgit v0.10.2


From 7a673f0b0642fc542b464a91957bdd44179296b2 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 18 May 2016 14:37:23 +0200
Subject: phy: Wire return value from phy_config()

Fix zynq_gem driver to handle error from phy_config correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 98986bb..4b6c09f 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -879,9 +879,7 @@ __weak int board_phy_config(struct phy_device *phydev)
 int phy_config(struct phy_device *phydev)
 {
 	/* Invoke an optional board-specific helper */
-	board_phy_config(phydev);
-
-	return 0;
+	return board_phy_config(phydev);
 }
 
 int phy_shutdown(struct phy_device *phydev)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3704ce0..4d9c296 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -352,9 +352,8 @@ static int zynq_phy_init(struct udevice *dev)
 	priv->phydev->supported = supported | ADVERTISED_Pause |
 				  ADVERTISED_Asym_Pause;
 	priv->phydev->advertising = priv->phydev->supported;
-	phy_config(priv->phydev);
 
-	return 0;
+	return phy_config(priv->phydev);
 }
 
 static int zynq_gem_init(struct udevice *dev)
-- 
cgit v0.10.2


From 1b008fdb06848c7c84e7c1a4a9b2b76239550555 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 18 May 2016 14:46:28 +0200
Subject: phy: marvell: Do not reset phy after negotiation

The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c358c3ecf5f394ff37def6a45eb26768c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 64713fb..d2e68d4 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -352,11 +352,7 @@ static int m88e1118_config(struct phy_device *phydev)
 	/* Change Page Number */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 
-	genphy_config_aneg(phydev);
-
-	phy_reset(phydev);
-
-	return 0;
+	return genphy_config_aneg(phydev);
 }
 
 static int m88e1118_startup(struct phy_device *phydev)
-- 
cgit v0.10.2


From ad5b5801264e573bfbf17a20b04c546985c5bfc1 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 20 May 2016 14:59:33 +0200
Subject: ARM: zynq: Simplify zynq configuration

Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index d396a13..db3c579 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,41 +1,5 @@
 if ARCH_ZYNQ
 
-config ZYNQ_CUSTOM_INIT
-	bool "Use custom ps7_init provided by Xilinx tool"
-	help
-	  U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants.
-	  If you want to override them with customized ones
-	  or ps7_init code for your board is missing, please say Y here
-	  and add ones into board/xilinx/zynq/custom_hw_platform/ directory.
-
-choice
-	prompt "Xilinx Zynq board select"
-	default TARGET_ZYNQ_ZC702
-
-config TARGET_ZYNQ_ZED
-	bool "Zynq ZedBoard"
-
-config TARGET_ZYNQ_MICROZED
-	bool "Zynq MicroZed"
-
-config TARGET_ZYNQ_PICOZED
-	bool "Zynq PicoZed"
-
-config TARGET_ZYNQ_ZC702
-	bool "Zynq ZC702 Board"
-
-config TARGET_ZYNQ_ZC706
-	bool "Zynq ZC706 Board"
-
-config TARGET_ZYNQ_ZC770
-	bool "Zynq ZC770 Board"
-	select ZYNQ_CUSTOM_INIT
-
-config TARGET_ZYNQ_ZYBO
-	bool "Zynq Zybo Board"
-
-endchoice
-
 config SYS_BOARD
 	default "zynq"
 
@@ -46,11 +10,11 @@ config SYS_SOC
 	default "zynq"
 
 config SYS_CONFIG_NAME
-	default "zynq_zed" if TARGET_ZYNQ_ZED
-	default "zynq_microzed" if TARGET_ZYNQ_MICROZED
-	default "zynq_picozed" if TARGET_ZYNQ_PICOZED
-	default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
-	default "zynq_zc770" if TARGET_ZYNQ_ZC770
-	default "zynq_zybo" if TARGET_ZYNQ_ZYBO
+	string "Board configuration name"
+	default "zynq-common"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 endif
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index eab9303..7de0212 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -7,17 +7,7 @@
 
 obj-y	:= board.o
 
-# Copied from Xilinx SDK 2014.4
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZED)		:= zed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED)	:= MicroZed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702)		:= ZC702_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706)		:= ZC706_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO)		:= zybo_hw_platform
-# If you want to use customized ps7_init_gpl.c/h,
-# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
-# This line must be placed at the bottom of the list because
-# it takes precedence over the default ones.
-hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT)		:= custom_hw_platform
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
 
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
 	$(hw-platform-y)/ps7_init_gpl.o)
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
deleted file mode 100644
index eb29002..0000000
--- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
+++ /dev/null
@@ -1,12963 +0,0 @@
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000180[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x1e
-    // .. ==> 0XF8000190[13:8] = 0x0000001EU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reserved_reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1a
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
-    // .. .. reg_ddrc_t_rfc_min = 0xa0
-    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x16
-    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x13
-    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
-    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
-    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
-    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
-    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
-    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
-    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
-    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
-    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. reserved_SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. reserved_VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. reserved_REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reserved_VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reserved_VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reserved_VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reserved_INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reserved_TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. reserved_TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reserved_INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000728[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800072C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000730[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000734[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000740[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000740[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000744[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000744[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000748[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000748[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800074C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800074C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000750[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000750[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000754[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000754[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000758[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800075C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000760[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000764[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000768[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800076C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007BC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 50
-    // .. ==> 0XF8000830[5:0] = 0x00000032U
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
-    // .. SDIO0_CD_SEL = 46
-    // .. ==> 0XF8000830[21:16] = 0x0000002EU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_LVL_INP_EN_0 = 1
-    // .. ==> 0XF8000900[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. USER_LVL_OUT_EN_0 = 1
-    // .. ==> 0XF8000900[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USER_LVL_INP_EN_1 = 1
-    // .. ==> 0XF8000900[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. USER_LVL_OUT_EN_1 = 1
-    // .. ==> 0XF8000900[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. reserved_FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reserved_FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000180[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x1e
-    // .. ==> 0XF8000190[13:8] = 0x0000001EU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1a
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
-    // .. .. reg_ddrc_t_rfc_min = 0xa0
-    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x16
-    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x13
-    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
-    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
-    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
-    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
-    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
-    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
-    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
-    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
-    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000728[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800072C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000730[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000734[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000740[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000740[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000744[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000744[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000748[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000748[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800074C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800074C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000750[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000750[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000754[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000754[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000758[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800075C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000760[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000764[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000768[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800076C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007BC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 50
-    // .. ==> 0XF8000830[5:0] = 0x00000032U
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
-    // .. SDIO0_CD_SEL = 46
-    // .. ==> 0XF8000830[21:16] = 0x0000002EU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000180[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x1e
-    // .. ==> 0XF8000190[13:8] = 0x0000001EU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1a
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
-    // .. .. reg_ddrc_t_rfc_min = 0xa0
-    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x16
-    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x13
-    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
-    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
-    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
-    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
-    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
-    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
-    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
-    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
-    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000728[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800072C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000730[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000734[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000740[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000740[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000744[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000744[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000748[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000748[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800074C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800074C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000750[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000750[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000754[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000754[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000758[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800075C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000760[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000764[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000768[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800076C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007BC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 50
-    // .. ==> 0XF8000830[5:0] = 0x00000032U
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
-    // .. SDIO0_CD_SEL = 46
-    // .. ==> 0XF8000830[21:16] = 0x0000002EU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_post_config_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_post_config_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_post_config_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret;
-  //int pcw_ver = 0;
-
-  if (si_ver == PCW_SILICON_VERSION_1) {
-    ps7_mio_init_data = ps7_mio_init_data_1_0;
-    ps7_pll_init_data = ps7_pll_init_data_1_0;
-    ps7_clock_init_data = ps7_clock_init_data_1_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
-    //pcw_ver = 1;
-
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-    ps7_mio_init_data = ps7_mio_init_data_2_0;
-    ps7_pll_init_data = ps7_pll_init_data_2_0;
-    ps7_clock_init_data = ps7_clock_init_data_2_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
-    //pcw_ver = 2;
-
-  } else {
-    ps7_mio_init_data = ps7_mio_init_data_3_0;
-    ps7_pll_init_data = ps7_pll_init_data_3_0;
-    ps7_clock_init_data = ps7_clock_init_data_3_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-    //pcw_ver = 3;
-  }
-
-  // MIO init
-  ret = ps7_config (ps7_mio_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // PLL init
-  ret = ps7_config (ps7_pll_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // Clock init
-  ret = ps7_config (ps7_clock_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // DDR init
-  ret = ps7_config (ps7_ddr_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
-  // Peripherals init
-  ret = ps7_config (ps7_peripherals_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
-  return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
deleted file mode 100644
index bdea5a0..0000000
--- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  100000000
-#define FPGA2_FREQ  33333336
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
deleted file mode 100644
index abfd911..0000000
--- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
+++ /dev/null
@@ -1,13296 +0,0 @@
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x5
-    // .. ==> 0XF8000140[25:20] = 0x00000005U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF800015C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF800015C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800015C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xe
-    // .. ==> 0XF800015C[13:8] = 0x0000000EU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF800015C[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
-    // .. CAN0_MUX = 0x0
-    // .. ==> 0XF8000160[5:0] = 0x00000000U
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
-    // .. CAN0_REF_SEL = 0x0
-    // .. ==> 0XF8000160[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. CAN1_MUX = 0x0
-    // .. ==> 0XF8000160[21:16] = 0x00000000U
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
-    // .. CAN1_REF_SEL = 0x0
-    // .. ==> 0XF8000160[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reserved_reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x10
-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x4
-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
-    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
-    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x12
-    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
-    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0xc
-    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xde
-    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x21
-    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xee
-    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
-    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
-    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
-    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
-    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
-    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
-    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
-    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
-    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
-    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
-    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
-    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
-    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x0
-    // .. ==> 0XF8000B00[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. reserved_SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. reserved_VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. reserved_REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reserved_VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reserved_VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reserved_VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reserved_INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reserved_TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. reserved_TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reserved_INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000700[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000700[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000700[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000704[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000704[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000708[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800070C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000710[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000714[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000718[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800071C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000720[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000724[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000724[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000728[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800072C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000730[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000734[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000738[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000738[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800073C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800073C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800073C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 1
-    // .. ==> 0XF80007B8[7:5] = 0x00000001U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007B8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 1
-    // .. ==> 0XF80007BC[7:5] = 0x00000001U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007BC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007C8[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007C8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007CC[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007CC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 15
-    // .. ==> 0XF8000830[5:0] = 0x0000000FU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
-    // .. SDIO0_CD_SEL = 0
-    // .. ==> 0XF8000830[21:16] = 0x00000000U
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x800
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x800
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. DIRECTION_0 = 0x2000
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. OP_ENABLE_0 = 0x2000
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_LVL_INP_EN_0 = 1
-    // .. ==> 0XF8000900[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. USER_LVL_OUT_EN_0 = 1
-    // .. ==> 0XF8000900[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USER_LVL_INP_EN_1 = 1
-    // .. ==> 0XF8000900[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. USER_LVL_OUT_EN_1 = 1
-    // .. ==> 0XF8000900[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. reserved_FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reserved_FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x5
-    // .. ==> 0XF8000140[25:20] = 0x00000005U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF800015C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF800015C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800015C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xe
-    // .. ==> 0XF800015C[13:8] = 0x0000000EU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF800015C[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
-    // .. CAN0_MUX = 0x0
-    // .. ==> 0XF8000160[5:0] = 0x00000000U
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
-    // .. CAN0_REF_SEL = 0x0
-    // .. ==> 0XF8000160[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. CAN1_MUX = 0x0
-    // .. ==> 0XF8000160[21:16] = 0x00000000U
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
-    // .. CAN1_REF_SEL = 0x0
-    // .. ==> 0XF8000160[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x10
-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x4
-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
-    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
-    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x12
-    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
-    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0xc
-    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xde
-    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x21
-    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xee
-    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
-    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
-    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
-    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
-    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
-    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
-    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
-    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
-    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
-    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
-    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
-    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
-    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. CLK_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. SRSTN_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000700[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000700[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000700[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000704[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000704[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000708[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800070C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000710[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000714[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000718[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800071C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000720[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000724[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000724[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000728[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800072C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000730[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000734[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000738[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000738[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800073C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800073C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800073C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 1
-    // .. ==> 0XF80007B8[7:5] = 0x00000001U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007B8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 1
-    // .. ==> 0XF80007BC[7:5] = 0x00000001U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007BC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007C8[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007C8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007CC[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007CC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 15
-    // .. ==> 0XF8000830[5:0] = 0x0000000FU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
-    // .. SDIO0_CD_SEL = 0
-    // .. ==> 0XF8000830[21:16] = 0x00000000U
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x800
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x800
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. DIRECTION_0 = 0x2000
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. OP_ENABLE_0 = 0x2000
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x5
-    // .. ==> 0XF8000140[25:20] = 0x00000005U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF800015C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF800015C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800015C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xe
-    // .. ==> 0XF800015C[13:8] = 0x0000000EU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF800015C[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
-    // .. CAN0_MUX = 0x0
-    // .. ==> 0XF8000160[5:0] = 0x00000000U
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
-    // .. CAN0_REF_SEL = 0x0
-    // .. ==> 0XF8000160[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. CAN1_MUX = 0x0
-    // .. ==> 0XF8000160[21:16] = 0x00000000U
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
-    // .. CAN1_REF_SEL = 0x0
-    // .. ==> 0XF8000160[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x10
-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x4
-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
-    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
-    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x12
-    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
-    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0xc
-    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xde
-    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x21
-    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xee
-    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
-    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
-    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
-    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
-    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
-    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
-    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
-    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
-    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
-    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
-    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
-    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
-    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. CLK_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. SRSTN_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000700[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000700[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000700[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000704[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000704[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000708[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800070C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000710[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000714[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000718[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800071C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000720[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000724[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000724[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000728[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800072C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000730[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000734[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000738[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000738[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800073C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800073C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800073C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 1
-    // .. ==> 0XF80007B8[7:5] = 0x00000001U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007B8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 1
-    // .. ==> 0XF80007BC[7:5] = 0x00000001U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007BC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007C8[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007C8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007CC[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007CC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 15
-    // .. ==> 0XF8000830[5:0] = 0x0000000FU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
-    // .. SDIO0_CD_SEL = 0
-    // .. ==> 0XF8000830[21:16] = 0x00000000U
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x800
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x800
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xf7ff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
-    // .. .. .. .. DATA_0_LSW = 0x800
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. DIRECTION_0 = 0x2000
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. OP_ENABLE_0 = 0x2000
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xdfff
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
-    // .. .. .. .. DATA_0_LSW = 0x2000
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_post_config_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_post_config_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_post_config_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret;
-  //int pcw_ver = 0;
-
-  if (si_ver == PCW_SILICON_VERSION_1) {
-    ps7_mio_init_data = ps7_mio_init_data_1_0;
-    ps7_pll_init_data = ps7_pll_init_data_1_0;
-    ps7_clock_init_data = ps7_clock_init_data_1_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
-    //pcw_ver = 1;
-
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-    ps7_mio_init_data = ps7_mio_init_data_2_0;
-    ps7_pll_init_data = ps7_pll_init_data_2_0;
-    ps7_clock_init_data = ps7_clock_init_data_2_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
-    //pcw_ver = 2;
-
-  } else {
-    ps7_mio_init_data = ps7_mio_init_data_3_0;
-    ps7_pll_init_data = ps7_pll_init_data_3_0;
-    ps7_clock_init_data = ps7_clock_init_data_3_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-    //pcw_ver = 3;
-  }
-
-  // MIO init
-  ret = ps7_config (ps7_mio_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // PLL init
-  ret = ps7_config (ps7_pll_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // Clock init
-  ret = ps7_config (ps7_clock_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // DDR init
-  ret = ps7_config (ps7_ddr_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
-  // Peripherals init
-  ret = ps7_config (ps7_peripherals_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
-  return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
deleted file mode 100644
index 16fa810..0000000
--- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  25000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  23809523
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  50000000
-#define FPGA1_FREQ  50000000
-#define FPGA2_FREQ  50000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
deleted file mode 100644
index 77fd949..0000000
--- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
+++ /dev/null
@@ -1,13203 +0,0 @@
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x5
-    // .. ==> 0XF8000140[25:20] = 0x00000005U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reserved_reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x10
-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x4
-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
-    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xee
-    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x25
-    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
-    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x19
-    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
-    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
-    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
-    // .. .. reg_phy_gatelvl_init_ratio = 0x109
-    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
-    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
-    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
-    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
-    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
-    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
-    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
-    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
-    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xde
-    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
-    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
-    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xea
-    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x0
-    // .. ==> 0XF8000B00[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. reserved_SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. reserved_VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. reserved_REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reserved_VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reserved_VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reserved_VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reserved_INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reserved_TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. reserved_TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reserved_INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000700[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000700[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000700[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000704[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000704[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000708[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800070C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000710[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000714[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000718[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800071C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000720[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000724[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000724[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000724[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000728[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000728[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800072C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800072C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000730[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000730[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000734[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000734[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000738[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000738[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000738[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800073C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800073C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800073C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007B8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007B8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007BC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007BC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007C8[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007C8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007CC[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007CC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 15
-    // .. ==> 0XF8000830[5:0] = 0x0000000FU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
-    // .. SDIO0_CD_SEL = 14
-    // .. ==> 0XF8000830[21:16] = 0x0000000EU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. DIRECTION_1 = 0x8000
-    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. OP_ENABLE_1 = 0x8000
-    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. DIRECTION_1 = 0x4000
-    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. OP_ENABLE_1 = 0x4000
-    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_LVL_INP_EN_0 = 1
-    // .. ==> 0XF8000900[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. USER_LVL_OUT_EN_0 = 1
-    // .. ==> 0XF8000900[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USER_LVL_INP_EN_1 = 1
-    // .. ==> 0XF8000900[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. USER_LVL_OUT_EN_1 = 1
-    // .. ==> 0XF8000900[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. reserved_FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reserved_FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x5
-    // .. ==> 0XF8000140[25:20] = 0x00000005U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x10
-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x4
-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
-    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xee
-    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x25
-    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
-    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x19
-    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
-    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
-    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
-    // .. .. reg_phy_gatelvl_init_ratio = 0x109
-    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
-    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
-    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
-    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
-    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
-    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
-    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
-    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
-    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xde
-    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
-    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
-    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xea
-    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. CLK_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. SRSTN_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000700[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000700[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000700[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000704[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000704[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000708[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800070C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000710[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000714[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000718[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800071C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000720[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000724[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000724[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000724[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000728[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000728[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800072C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800072C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000730[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000730[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000734[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000734[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000738[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000738[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000738[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800073C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800073C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800073C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007B8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007B8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007BC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007BC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007C8[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007C8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007CC[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007CC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 15
-    // .. ==> 0XF8000830[5:0] = 0x0000000FU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
-    // .. SDIO0_CD_SEL = 14
-    // .. ==> 0XF8000830[21:16] = 0x0000000EU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. DIRECTION_1 = 0x8000
-    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. OP_ENABLE_1 = 0x8000
-    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. DIRECTION_1 = 0x4000
-    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. OP_ENABLE_1 = 0x4000
-    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x5
-    // .. ==> 0XF8000140[25:20] = 0x00000005U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000170[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000180[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x10
-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x4
-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
-    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
-    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
-    // .. .. reg_phy_gatelvl_init_ratio = 0xee
-    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x25
-    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
-    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x19
-    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
-    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
-    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
-    // .. .. reg_phy_gatelvl_init_ratio = 0x109
-    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
-    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
-    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
-    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
-    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
-    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
-    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
-    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
-    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xde
-    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
-    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
-    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xea
-    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. CLK_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. SRSTN_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000700[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000700[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000700[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000704[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000704[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000704[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000708[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000708[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800070C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800070C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000710[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000710[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000714[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000714[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000718[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000718[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800071C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000720[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000720[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000724[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000724[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000724[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000728[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000728[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800072C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800072C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000730[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000730[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000734[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000734[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000738[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000738[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000738[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800073C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800073C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF800073C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000740[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000744[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000748[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800074C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000750[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000754[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000758[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800075C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000760[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000764[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000768[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800076C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000770[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000774[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000778[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800077C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000780[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000784[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000788[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800078C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000790[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000794[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000798[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800079C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007A8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007AC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007B4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007B8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007B8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007BC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007BC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007BC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007BC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007BC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007BC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007C8[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007C8[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007CC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF80007CC[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 1
-    // .. ==> 0XF80007CC[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 15
-    // .. ==> 0XF8000830[5:0] = 0x0000000FU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
-    // .. SDIO0_CD_SEL = 14
-    // .. ==> 0XF8000830[21:16] = 0x0000000EU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. DIRECTION_0 = 0x80
-    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. OP_ENABLE_0 = 0x80
-    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. MASK_0_LSW = 0xff7f
-    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
-    // .. .. .. .. DATA_0_LSW = 0x80
-    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. DIRECTION_1 = 0x8000
-    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. OP_ENABLE_1 = 0x8000
-    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0x7fff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x8000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. DIRECTION_1 = 0x4000
-    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. OP_ENABLE_1 = 0x4000
-    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. ..
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_post_config_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_post_config_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_post_config_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret;
-  //int pcw_ver = 0;
-
-  if (si_ver == PCW_SILICON_VERSION_1) {
-    ps7_mio_init_data = ps7_mio_init_data_1_0;
-    ps7_pll_init_data = ps7_pll_init_data_1_0;
-    ps7_clock_init_data = ps7_clock_init_data_1_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
-    //pcw_ver = 1;
-
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-    ps7_mio_init_data = ps7_mio_init_data_2_0;
-    ps7_pll_init_data = ps7_pll_init_data_2_0;
-    ps7_clock_init_data = ps7_clock_init_data_2_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
-    //pcw_ver = 2;
-
-  } else {
-    ps7_mio_init_data = ps7_mio_init_data_3_0;
-    ps7_pll_init_data = ps7_pll_init_data_3_0;
-    ps7_clock_init_data = ps7_clock_init_data_3_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-    //pcw_ver = 3;
-  }
-
-  // MIO init
-  ret = ps7_config (ps7_mio_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // PLL init
-  ret = ps7_config (ps7_pll_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // Clock init
-  ret = ps7_config (ps7_clock_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // DDR init
-  ret = ps7_config (ps7_ddr_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
-  // Peripherals init
-  ret = ps7_config (ps7_peripherals_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
-  return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
deleted file mode 100644
index 8527eef..0000000
--- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  25000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  50000000
-#define FPGA1_FREQ  50000000
-#define FPGA2_FREQ  50000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/custom_hw_platform/.gitignore b/board/xilinx/zynq/custom_hw_platform/.gitignore
deleted file mode 100644
index c455361..0000000
--- a/board/xilinx/zynq/custom_hw_platform/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-ps7_init_gpl.[ch]
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
deleted file mode 100644
index f4f45be..0000000
--- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
+++ /dev/null
@@ -1,12861 +0,0 @@
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reserved_reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x18
-    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
-    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
-    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
-    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
-    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
-    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
-    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
-    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
-    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
-    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
-    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
-    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
-    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
-    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. reserved_INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. reserved_SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. reserved_DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. reserved_DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. reserved_SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. reserved_SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. reserved_GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. reserved_RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. reserved_VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. reserved_REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reserved_VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reserved_VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reserved_VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reserved_VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reserved_INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reserved_TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reserved_TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. reserved_TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reserved_INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000704[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000708[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800070C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000710[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000714[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000718[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000720[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000720[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000728[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800072C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000730[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000734[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000740[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000740[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000740[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000744[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000744[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000744[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000748[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000748[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000748[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800074C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800074C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800074C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000750[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000750[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000750[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000754[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000754[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000754[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000758[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000758[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800075C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800075C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000760[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000760[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000764[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000764[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000768[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000768[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800076C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800076C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000770[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000774[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000778[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800077C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000780[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000784[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000788[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800078C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000790[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000794[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000798[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800079C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A8[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007AC[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007BC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007C8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 46
-    // .. ==> 0XF8000830[5:0] = 0x0000002EU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
-    // .. SDIO0_CD_SEL = 47
-    // .. ==> 0XF8000830[21:16] = 0x0000002FU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_LVL_INP_EN_0 = 1
-    // .. ==> 0XF8000900[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. USER_LVL_OUT_EN_0 = 1
-    // .. ==> 0XF8000900[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USER_LVL_INP_EN_1 = 1
-    // .. ==> 0XF8000900[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. USER_LVL_OUT_EN_1 = 1
-    // .. ==> 0XF8000900[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. reserved_FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reserved_FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_3_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x18
-    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
-    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
-    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
-    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
-    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
-    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
-    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
-    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
-    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
-    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
-    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
-    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
-    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
-    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000704[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000708[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800070C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000710[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000714[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000718[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000720[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000720[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000728[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800072C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000730[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000734[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000740[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000740[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000740[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000744[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000744[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000744[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000748[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000748[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000748[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800074C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800074C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800074C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000750[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000750[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000750[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000754[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000754[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000754[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000758[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000758[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800075C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800075C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000760[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000760[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000764[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000764[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000768[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000768[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800076C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800076C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000770[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000774[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000778[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800077C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000780[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000784[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000788[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800078C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000790[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000794[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000798[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800079C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A8[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007AC[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007BC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007C8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 46
-    // .. ==> 0XF8000830[5:0] = 0x0000002EU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
-    // .. SDIO0_CD_SEL = 47
-    // .. ==> 0XF8000830[21:16] = 0x0000002FU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_2_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x12c
-    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x20
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
-    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
-    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. ..
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. ..
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x23
-    // .. ==> 0XF8000128[13:8] = 0x00000023U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
-    // .. DIVISOR1 = 0x3
-    // .. ==> 0XF8000128[25:20] = 0x00000003U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
-    // ..
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x0
-    // .. ==> 0XF8000154[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // ..
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // ..
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000180[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x7
-    // .. ==> 0XF8000180[13:8] = 0x00000007U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000190[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF8000190[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000190[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0x14
-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // ..
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // ..
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1b
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
-    // .. .. reg_ddrc_t_rfc_min = 0x56
-    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x18
-    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_ras_max = 0x24
-    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
-    // .. .. reg_ddrc_t_ras_min = 0x14
-    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
-    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. ..
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xcb73
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
-    // .. .. dram_rstn_x1024 = 0x69
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. ..
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. ..
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_tx = 0x0
-    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_board_lpbk_rx = 0x0
-    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
-    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
-    // .. ..
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x3
-    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
-    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
-    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
-    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
-    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
-    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
-    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
-    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
-    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
-    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
-    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
-    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
-    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
-    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
-    // .. .. reg_phy_loopback = 0x0
-    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_rank0_delays = 0x1
-    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_phy_int_lpbk = 0x0
-    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_rmw_portn = 0x1
-    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_per_bank_refresh = 0x0
-    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. ..
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. ..
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. ..
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x3
-    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
-    // .. SLEW_N = 0x3
-    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B68[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. VREF_INT_EN = 0x1
-    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x4
-    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
-    // .. VREF_EXT_EN = 0x0
-    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. ..
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000704[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000708[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800070C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000710[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000714[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000718[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000720[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000720[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000728[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000728[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800072C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800072C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000730[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000730[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000734[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000734[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000740[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000740[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000740[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000744[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000744[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000744[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000748[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000748[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000748[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800074C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800074C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800074C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000750[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000750[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000750[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000754[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000754[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000754[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000758[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000758[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800075C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800075C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000760[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000760[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000764[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000764[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000768[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000768[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800076C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800076C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000770[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000774[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000778[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800077C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000780[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000784[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000788[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800078C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000790[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000794[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000798[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800079C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A8[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007AC[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007BC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007C8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_WP_SEL = 46
-    // .. ==> 0XF8000830[5:0] = 0x0000002EU
-    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
-    // .. SDIO0_CD_SEL = 47
-    // .. ==> 0XF8000830[21:16] = 0x0000002FU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
-    // ..
-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // ..
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // ..
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: USB0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB0 RESET
-    // .. .. .. START: USB1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: USB1 RESET
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: ENET0 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET0 RESET
-    // .. .. .. START: ENET1 RESET
-    // .. .. .. .. START: DIR MODE BANK 0
-    // .. .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. .. START: DIR MODE BANK 1
-    // .. .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: ENET1 RESET
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: I2C0 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C0 RESET
-    // .. .. .. START: I2C1 RESET
-    // .. .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: OUTPUT ENABLE
-    // .. .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. .. START: ADD 1 MS DELAY
-    // .. .. .. ..
-    EMIT_MASKDELAY(0XF8F00200, 1),
-    // .. .. .. .. FINISH: ADD 1 MS DELAY
-    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: I2C1 RESET
-    // .. .. FINISH: I2C RESET
-    // .. .. START: NOR CHIP SELECT
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. FINISH: NOR CHIP SELECT
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // ..
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // ..
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // ..
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_debug_1_0[] = {
-    // START: top
-    // .. START: CROSS TRIGGER CONFIGURATIONS
-    // .. .. START: UNLOCKING CTI REGISTERS
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. KEY = 0XC5ACCE55
-    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
-    // .. ..
-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
-    // .. .. FINISH: UNLOCKING CTI REGISTERS
-    // .. .. START: ENABLING CTI MODULES AND CHANNELS
-    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-
-  return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        volatile unsigned long *addr = (volatile unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ )
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-
-
-        switch ( opcode ) {
-
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        case OPCODE_MASKDELAY:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            int delay = get_number_of_cycles_for_delay(mask);
-            perf_reset_and_start_timer();
-            while ((*addr < delay)) {
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_post_config_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_post_config_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_post_config_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_debug_1_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_debug_2_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_debug_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret;
-  //int pcw_ver = 0;
-
-  if (si_ver == PCW_SILICON_VERSION_1) {
-    ps7_mio_init_data = ps7_mio_init_data_1_0;
-    ps7_pll_init_data = ps7_pll_init_data_1_0;
-    ps7_clock_init_data = ps7_clock_init_data_1_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
-    //pcw_ver = 1;
-
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-    ps7_mio_init_data = ps7_mio_init_data_2_0;
-    ps7_pll_init_data = ps7_pll_init_data_2_0;
-    ps7_clock_init_data = ps7_clock_init_data_2_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
-    //pcw_ver = 2;
-
-  } else {
-    ps7_mio_init_data = ps7_mio_init_data_3_0;
-    ps7_pll_init_data = ps7_pll_init_data_3_0;
-    ps7_clock_init_data = ps7_clock_init_data_3_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-    //pcw_ver = 3;
-  }
-
-  // MIO init
-  ret = ps7_config (ps7_mio_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // PLL init
-  ret = ps7_config (ps7_pll_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // Clock init
-  ret = ps7_config (ps7_clock_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // DDR init
-  ret = ps7_config (ps7_ddr_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
-  // Peripherals init
-  ret = ps7_config (ps7_peripherals_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
-  return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
-						      (1 << 3) | // Auto-increment
-						      (0 << 8) // Pre-scale
-	);
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
-	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
-	    perf_reset_clock();
-	    perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
deleted file mode 100644
index 9b41e28..0000000
--- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier:	GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  666666687
-#define DDR_FREQ  533333374
-#define DCI_FREQ  10158731
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  111111115
-#define WDT_FREQ  111111115
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  142857132
-#define FPGA2_FREQ  50000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
deleted file mode 100644
index 83daf7b..0000000
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
+++ /dev/null
@@ -1,13045 +0,0 @@
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: PLL SLCR REGISTERS */
-	/* .. .. START: ARM PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x177 */
-	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x1a */
-	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. ARM_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. .. SRCSEL = 0x0 */
-	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. .. DIVISOR = 0x2 */
-	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
-	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
-	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
-	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
-	/* .. .. .. CPU_2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
-	/* .. .. .. CPU_1XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
-	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
-	/* .. .. FINISH: ARM PLL INIT */
-	/* .. .. START: DDR PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x1db */
-	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x15 */
-	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. DDR_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. .. DDR_3XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. DDR_2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
-	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
-	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
-	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
-	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
-	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
-	/* .. .. FINISH: DDR PLL INIT */
-	/* .. .. START: IO PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x1f4 */
-	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x14 */
-	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. IO_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. FINISH: IO PLL INIT */
-	/* .. FINISH: PLL SLCR REGISTERS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: CLOCK CONTROL SLCR REGISTERS */
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. DIVISOR0 = 0x34 */
-	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
-	/* .. DIVISOR1 = 0x2 */
-	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
-	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x8 */
-	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
-	/* .. DIVISOR1 = 0x1 */
-	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
-	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x5 */
-	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
-	/* .. CLKACT0 = 0x1 */
-	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. CLKACT1 = 0x0 */
-	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x14 */
-	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
-	/* .. CLKACT0 = 0x0 */
-	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. CLKACT1 = 0x1 */
-	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0xa */
-	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
-	/* .. .. START: TRACE CLOCK */
-	/* .. .. FINISH: TRACE CLOCK */
-	/* .. .. CLKACT = 0x1 */
-	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR = 0x5 */
-	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0xa */
-	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x7 */
-	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x5 */
-	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x14 */
-	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
-	/* .. .. CLK_621_TRUE = 0x1 */
-	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
-	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
-	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
-	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
-	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
-	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
-	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
-	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
-	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
-	/* .. START: THIS SHOULD BE BLANK */
-	/* .. FINISH: THIS SHOULD BE BLANK */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
-	/* START: top */
-	/* .. START: DDR INITIALIZATION */
-	/* .. .. START: LOCK DDR */
-	/* .. .. reg_ddrc_soft_rstb = 0 */
-	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_powerdown_en = 0x0 */
-	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_data_bus_width = 0x0 */
-	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
-	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
-	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
-	/* .. .. FINISH: LOCK DDR */
-	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
-	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
-	/* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
-	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
-	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
-	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
-	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
-	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
-	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
-	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
-	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
-	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
-	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
-	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
-	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
-	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
-	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
-	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
-	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
-	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
-	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
-	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
-	/* .. .. reg_ddrc_t_rc = 0x1a */
-	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
-	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
-	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
-	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
-	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
-	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
-	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
-	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
-	/* .. .. reg_ddrc_wr2pre = 0x12 */
-	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
-	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
-	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
-	/* .. .. reg_ddrc_t_faw = 0x15 */
-	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
-	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
-	/* .. .. reg_ddrc_t_ras_max = 0x23 */
-	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
-	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
-	/* .. .. reg_ddrc_t_ras_min = 0x13 */
-	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
-	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
-	/* .. .. reg_ddrc_t_cke = 0x4 */
-	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
-	/* .. .. reg_ddrc_write_latency = 0x5 */
-	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
-	/* .. .. reg_ddrc_rd2wr = 0x7 */
-	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
-	/* .. .. reg_ddrc_wr2rd = 0xe */
-	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
-	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
-	/* .. .. reg_ddrc_t_xp = 0x4 */
-	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
-	/* .. .. reg_ddrc_pad_pd = 0x0 */
-	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rd2pre = 0x4 */
-	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
-	/* .. .. reg_ddrc_t_rcd = 0x7 */
-	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
-	/* .. .. reg_ddrc_t_ccd = 0x4 */
-	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
-	/* .. .. reg_ddrc_t_rrd = 0x6 */
-	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
-	/* .. .. reg_ddrc_refresh_margin = 0x2 */
-	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_t_rp = 0x7 */
-	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
-	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
-	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
-	/* .. .. reg_ddrc_mobile = 0x0 */
-	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
-	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_read_latency = 0x7 */
-	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
-	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
-	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
-	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
-	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
-	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
-	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_prefer_write = 0x0 */
-	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_wr = 0x0 */
-	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_addr = 0x0 */
-	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_data = 0x0 */
-	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
-	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
-	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_type = 0x0 */
-	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
-	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
-	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
-	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
-	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
-	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_t_mrd = 0x4 */
-	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
-	/* .. .. reg_ddrc_emr2 = 0x8 */
-	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
-	/* .. .. reg_ddrc_emr3 = 0x0 */
-	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
-	/* .. .. reg_ddrc_mr = 0x930 */
-	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
-	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
-	/* .. .. reg_ddrc_emr = 0x4 */
-	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
-	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
-	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
-	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
-	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
-	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
-	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
-	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
-	/* .. .. reg_ddrc_burstchop = 0x0 */
-	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
-	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
-	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_dq = 0x0 */
-	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
-	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
-	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
-	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
-	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
-	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
-	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
-	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
-	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
-	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
-	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
-	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
-	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
-	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
-	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
-	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
-	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
-	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
-	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
-	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
-	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
-	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
-	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
-	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
-	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
-	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
-	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
-	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
-	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
-	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
-	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
-	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
-	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
-	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
-	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
-	/* .. .. reg_phy_rd_local_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_local_odt = 0x3 */
-	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
-	/* .. .. reg_phy_idle_local_odt = 0x3 */
-	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
-	/* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
-	/* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
-	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
-	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
-	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
-	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
-	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
-	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_use_fixed_re = 0x1 */
-	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
-	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
-	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
-	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_clk_stall_level = 0x0 */
-	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
-	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
-	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
-	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
-	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
-	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
-	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
-	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
-	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
-	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
-	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
-	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
-	/* .. .. reg_ddrc_pageclose = 0x0 */
-	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
-	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
-	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
-	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
-	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
-	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_wc = 0x0 */
-	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
-	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_selfref_en = 0x0 */
-	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
-	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
-	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
-	/* .. .. reg_arb_go2critical_en = 0x1 */
-	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
-	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
-	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
-	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
-	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
-	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
-	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
-	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
-	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
-	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
-	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
-	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
-	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
-	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
-	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
-	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
-	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
-	/* .. .. reg_ddrc_t_cksre = 0x6 */
-	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
-	/* .. .. reg_ddrc_t_cksrx = 0x6 */
-	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
-	/* .. .. reg_ddrc_t_ckesr = 0x4 */
-	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
-	/* .. .. reg_ddrc_t_ckpde = 0x2 */
-	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
-	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
-	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
-	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
-	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
-	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
-	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
-	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
-	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
-	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_ddr3 = 0x1 */
-	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. reg_ddrc_t_mod = 0x200 */
-	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
-	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
-	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
-	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
-	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
-	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
-	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
-	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
-	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
-	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
-	/* .. .. dram_rstn_x1024 = 0x67 */
-	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
-	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
-	/* .. .. deeppowerdown_en = 0x0 */
-	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. deeppowerdown_to_x1024 = 0xff */
-	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
-	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
-	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
-	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
-	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
-	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
-	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
-	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
-	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
-	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
-	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
-	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
-	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
-	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
-	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
-	/* .. .. reg_ddrc_skip_ocd = 0x1 */
-	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
-	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
-	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
-	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
-	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
-	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
-	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
-	/* .. .. START: RESET ECC ERROR */
-	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
-	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
-	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
-	/* .. .. FINISH: RESET ECC ERROR */
-	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
-	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
-	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
-	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
-	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
-	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
-	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
-	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
-	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
-	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
-	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
-	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
-	/* .. .. reg_ddrc_ecc_mode = 0x0 */
-	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_scrub = 0x1 */
-	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
-	/* .. .. reg_phy_dif_on = 0x0 */
-	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_phy_dif_off = 0x0 */
-	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
-	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
-	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
-	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
-	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
-	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
-	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
-	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
-	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
-	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
-	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
-	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
-	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
-	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
-	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
-	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
-	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
-	/* .. .. reg_phy_bl2 = 0x0 */
-	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_at_spd_atpg = 0x0 */
-	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_enable = 0x0 */
-	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_force_err = 0x0 */
-	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_mode = 0x0 */
-	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. .. reg_phy_invert_clkout = 0x1 */
-	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. .. reg_phy_sel_logic = 0x0 */
-	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
-	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
-	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_lpddr = 0x0 */
-	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_cmd_latency = 0x0 */
-	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
-	/* .. .. reg_phy_wr_rl_delay = 0x2 */
-	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
-	/* .. .. reg_phy_rd_rl_delay = 0x4 */
-	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
-	/* .. .. reg_phy_dll_lock_diff = 0xf */
-	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
-	/* .. .. reg_phy_use_wr_level = 0x1 */
-	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
-	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
-	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
-	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
-	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
-	/* .. .. reg_phy_dis_calib_rst = 0x0 */
-	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
-	/* .. .. reg_arb_page_addr_mask = 0x0 */
-	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_ddrc_lpddr2 = 0x0 */
-	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_derate_enable = 0x0 */
-	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr4_margin = 0x0 */
-	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
-	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
-	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
-	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
-	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
-	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
-	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
-	/* .. .. reg_ddrc_t_mrw = 0x5 */
-	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
-	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
-	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
-	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
-	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
-	/* .. .. START: POLL ON DCI STATUS */
-	/* .. .. DONE = 1 */
-	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. .. */
-	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-	/* .. .. FINISH: POLL ON DCI STATUS */
-	/* .. .. START: UNLOCK DDR */
-	/* .. .. reg_ddrc_soft_rstb = 0x1 */
-	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_powerdown_en = 0x0 */
-	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_data_bus_width = 0x0 */
-	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
-	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
-	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
-	/* .. .. FINISH: UNLOCK DDR */
-	/* .. .. START: CHECK DDR STATUS */
-	/* .. .. ddrc_reg_operating_mode = 1 */
-	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-	/* .. .. FINISH: CHECK DDR STATUS */
-	/* .. FINISH: DDR INITIALIZATION */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: OCM REMAPPING */
-	/* .. VREF_EN = 0x1 */
-	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. VREF_SEL = 0x0 */
-	/* .. ==> 0XF8000B00[6:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
-	/* .. FINISH: OCM REMAPPING */
-	/* .. START: DDRIOB SETTINGS */
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCI_TYPE = 0x0 */
-	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCI_TYPE = 0x0 */
-	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x1 */
-	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCI_TYPE = 0x3 */
-	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x1 */
-	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCI_TYPE = 0x3 */
-	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x2 */
-	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCI_TYPE = 0x3 */
-	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x2 */
-	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCI_TYPE = 0x3 */
-	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
-	/* .. reserved_INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE_B = 0x0 */
-	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCI_TYPE = 0x0 */
-	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
-	/* .. reserved_DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. reserved_DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. reserved_SLEW_P = 0x3 */
-	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
-	/* .. reserved_SLEW_N = 0x3 */
-	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
-	/* .. reserved_GTL = 0x0 */
-	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. reserved_RTERM = 0x0 */
-	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
-	/* .. reserved_DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. reserved_DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. reserved_SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. reserved_SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. reserved_GTL = 0x0 */
-	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. reserved_RTERM = 0x0 */
-	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. reserved_DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. reserved_DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. reserved_SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. reserved_SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. reserved_GTL = 0x0 */
-	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. reserved_RTERM = 0x0 */
-	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. reserved_DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. reserved_DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. reserved_SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. reserved_SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. reserved_GTL = 0x0 */
-	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. reserved_RTERM = 0x0 */
-	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. VREF_INT_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. VREF_SEL = 0x0 */
-	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
-	/* .. VREF_EXT_EN = 0x3 */
-	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. reserved_VREF_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
-	/* .. REFIO_EN = 0x1 */
-	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
-	/* .. reserved_REFIO_TEST = 0x0 */
-	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
-	/* .. reserved_REFIO_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. reserved_DRST_B_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. reserved_CKE_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
-	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
-	/* .. .. START: ASSERT RESET */
-	/* .. .. RESET = 1 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
-	/* .. .. FINISH: ASSERT RESET */
-	/* .. .. START: DEASSERT RESET */
-	/* .. .. RESET = 0 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reserved_VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
-	/* .. .. FINISH: DEASSERT RESET */
-	/* .. .. RESET = 0x1 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. ENABLE = 0x1 */
-	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. reserved_VRP_TRI = 0x0 */
-	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reserved_VRN_TRI = 0x0 */
-	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reserved_VRP_OUT = 0x0 */
-	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reserved_VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. NREF_OPT1 = 0x0 */
-	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. .. NREF_OPT2 = 0x0 */
-	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
-	/* .. .. NREF_OPT4 = 0x1 */
-	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
-	/* .. .. PREF_OPT1 = 0x0 */
-	/* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
-	/* .. .. PREF_OPT2 = 0x0 */
-	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
-	/* .. .. UPDATE_CONTROL = 0x0 */
-	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. reserved_INIT_COMPLETE = 0x0 */
-	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. .. reserved_TST_CLK = 0x0 */
-	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. .. reserved_TST_HLN = 0x0 */
-	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. .. reserved_TST_HLP = 0x0 */
-	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. .. reserved_TST_RST = 0x0 */
-	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reserved_INT_DCI_EN = 0x0 */
-	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
-	/* .. FINISH: DDRIOB SETTINGS */
-	/* .. START: MIO PROGRAMMING */
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 7 */
-	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 7 */
-	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
-	/* .. SDIO0_WP_SEL = 55 */
-	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
-	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
-	/* .. SDIO0_CD_SEL = 47 */
-	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
-	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
-	/* .. FINISH: MIO PROGRAMMING */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
-	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* .. START: SRAM/NOR SET OPMODE */
-	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
-	/* .. START: QSPI REGISTERS */
-	/* .. Holdb_dr = 1 */
-	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
-	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
-	/* .. FINISH: QSPI REGISTERS */
-	/* .. START: PL POWER ON RESET REGISTERS */
-	/* .. PCFG_POR_CNT_4K = 0 */
-	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
-	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
-	/* .. FINISH: PL POWER ON RESET REGISTERS */
-	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
-	/* .. .. START: NAND SET CYCLE */
-	/* .. .. FINISH: NAND SET CYCLE */
-	/* .. .. START: OPMODE */
-	/* .. .. FINISH: OPMODE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
-	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: NOR CS0 BASE ADDRESS */
-	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
-	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
-	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: NOR CS1 BASE ADDRESS */
-	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
-	/* .. .. START: USB RESET */
-	/* .. .. .. START: USB0 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. DIRECTION_1 = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x0 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: USB0 RESET */
-	/* .. .. .. START: USB1 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: USB1 RESET */
-	/* .. .. FINISH: USB RESET */
-	/* .. .. START: ENET RESET */
-	/* .. .. .. START: ENET0 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: ENET0 RESET */
-	/* .. .. .. START: ENET1 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: ENET1 RESET */
-	/* .. .. FINISH: ENET RESET */
-	/* .. .. START: I2C RESET */
-	/* .. .. .. START: I2C0 RESET */
-	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: I2C0 RESET */
-	/* .. .. .. START: I2C1 RESET */
-	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: I2C1 RESET */
-	/* .. .. FINISH: I2C RESET */
-	/* .. .. START: NOR CHIP SELECT */
-	/* .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. FINISH: NOR CHIP SELECT */
-	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_post_config_3_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: ENABLING LEVEL SHIFTER */
-	/* .. USER_LVL_INP_EN_0 = 1 */
-	/* .. ==> 0XF8000900[3:3] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. USER_LVL_OUT_EN_0 = 1 */
-	/* .. ==> 0XF8000900[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. USER_LVL_INP_EN_1 = 1 */
-	/* .. ==> 0XF8000900[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. USER_LVL_OUT_EN_1 = 1 */
-	/* .. ==> 0XF8000900[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
-	/* .. FINISH: ENABLING LEVEL SHIFTER */
-	/* .. START: FPGA RESETS TO 0 */
-	/* .. reserved_3 = 0 */
-	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
-	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_ACP_RST = 0 */
-	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_AXDS3_RST = 0 */
-	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
-	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_AXDS2_RST = 0 */
-	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
-	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_AXDS1_RST = 0 */
-	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
-	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_AXDS0_RST = 0 */
-	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
-	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. reserved_2 = 0 */
-	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
-	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
-	/* .. reserved_FSSW1_FPGA_RST = 0 */
-	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
-	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. reserved_FSSW0_FPGA_RST = 0 */
-	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
-	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. reserved_1 = 0 */
-	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
-	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_FMSW1_RST = 0 */
-	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_FMSW0_RST = 0 */
-	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_DMA3_RST = 0 */
-	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_DMA2_RST = 0 */
-	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_DMA1_RST = 0 */
-	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. reserved_FPGA_DMA0_RST = 0 */
-	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. reserved = 0 */
-	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. FPGA3_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. FPGA2_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. FPGA1_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. FPGA0_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
-	/* .. FINISH: FPGA RESETS TO 0 */
-	/* .. START: AFI REGISTERS */
-	/* .. .. START: AFI0 REGISTERS */
-	/* .. .. FINISH: AFI0 REGISTERS */
-	/* .. .. START: AFI1 REGISTERS */
-	/* .. .. FINISH: AFI1 REGISTERS */
-	/* .. .. START: AFI2 REGISTERS */
-	/* .. .. FINISH: AFI2 REGISTERS */
-	/* .. .. START: AFI3 REGISTERS */
-	/* .. .. FINISH: AFI3 REGISTERS */
-	/* .. .. START: AFI2 SECURE REGISTER */
-	/* .. .. FINISH: AFI2 SECURE REGISTER */
-	/* .. FINISH: AFI REGISTERS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_debug_3_0[] = {
-	/* START: top */
-	/* .. START: CROSS TRIGGER CONFIGURATIONS */
-	/* .. .. START: UNLOCKING CTI REGISTERS */
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
-	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: PLL SLCR REGISTERS */
-	/* .. .. START: ARM PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x177 */
-	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x1a */
-	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. ARM_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. .. SRCSEL = 0x0 */
-	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. .. DIVISOR = 0x2 */
-	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
-	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
-	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
-	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
-	/* .. .. .. CPU_2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
-	/* .. .. .. CPU_1XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
-	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
-	/* .. .. FINISH: ARM PLL INIT */
-	/* .. .. START: DDR PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x1db */
-	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x15 */
-	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. DDR_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. .. DDR_3XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. DDR_2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
-	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
-	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
-	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
-	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
-	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
-	/* .. .. FINISH: DDR PLL INIT */
-	/* .. .. START: IO PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x1f4 */
-	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x14 */
-	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. IO_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. FINISH: IO PLL INIT */
-	/* .. FINISH: PLL SLCR REGISTERS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: CLOCK CONTROL SLCR REGISTERS */
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. DIVISOR0 = 0x34 */
-	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
-	/* .. DIVISOR1 = 0x2 */
-	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
-	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x8 */
-	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
-	/* .. DIVISOR1 = 0x1 */
-	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
-	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x5 */
-	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
-	/* .. CLKACT0 = 0x1 */
-	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. CLKACT1 = 0x0 */
-	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x14 */
-	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
-	/* .. CLKACT0 = 0x0 */
-	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. CLKACT1 = 0x1 */
-	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0xa */
-	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
-	/* .. .. START: TRACE CLOCK */
-	/* .. .. FINISH: TRACE CLOCK */
-	/* .. .. CLKACT = 0x1 */
-	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR = 0x5 */
-	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0xa */
-	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x7 */
-	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x5 */
-	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x14 */
-	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
-	/* .. .. CLK_621_TRUE = 0x1 */
-	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
-	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
-	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
-	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
-	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
-	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
-	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
-	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
-	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
-	/* .. START: THIS SHOULD BE BLANK */
-	/* .. FINISH: THIS SHOULD BE BLANK */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
-	/* START: top */
-	/* .. START: DDR INITIALIZATION */
-	/* .. .. START: LOCK DDR */
-	/* .. .. reg_ddrc_soft_rstb = 0 */
-	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_powerdown_en = 0x0 */
-	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_data_bus_width = 0x0 */
-	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
-	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
-	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
-	/* .. .. FINISH: LOCK DDR */
-	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
-	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
-	/* .. .. reg_ddrc_active_ranks = 0x1 */
-	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
-	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
-	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
-	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
-	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
-	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
-	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
-	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
-	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
-	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
-	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
-	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
-	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
-	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
-	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
-	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
-	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
-	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
-	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
-	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
-	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
-	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
-	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
-	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
-	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
-	/* .. .. reg_ddrc_t_rc = 0x1a */
-	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
-	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
-	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
-	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
-	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
-	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
-	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
-	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
-	/* .. .. reg_ddrc_wr2pre = 0x12 */
-	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
-	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
-	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
-	/* .. .. reg_ddrc_t_faw = 0x15 */
-	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
-	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
-	/* .. .. reg_ddrc_t_ras_max = 0x23 */
-	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
-	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
-	/* .. .. reg_ddrc_t_ras_min = 0x13 */
-	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
-	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
-	/* .. .. reg_ddrc_t_cke = 0x4 */
-	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
-	/* .. .. reg_ddrc_write_latency = 0x5 */
-	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
-	/* .. .. reg_ddrc_rd2wr = 0x7 */
-	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
-	/* .. .. reg_ddrc_wr2rd = 0xe */
-	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
-	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
-	/* .. .. reg_ddrc_t_xp = 0x4 */
-	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
-	/* .. .. reg_ddrc_pad_pd = 0x0 */
-	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rd2pre = 0x4 */
-	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
-	/* .. .. reg_ddrc_t_rcd = 0x7 */
-	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
-	/* .. .. reg_ddrc_t_ccd = 0x4 */
-	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
-	/* .. .. reg_ddrc_t_rrd = 0x6 */
-	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
-	/* .. .. reg_ddrc_refresh_margin = 0x2 */
-	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_t_rp = 0x7 */
-	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
-	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
-	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
-	/* .. .. reg_ddrc_sdram = 0x1 */
-	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
-	/* .. .. reg_ddrc_mobile = 0x0 */
-	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
-	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_read_latency = 0x7 */
-	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
-	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
-	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
-	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
-	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_loopback = 0x0 */
-	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
-	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
-	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_prefer_write = 0x0 */
-	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_max_rank_rd = 0xf */
-	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
-	/* .. .. reg_ddrc_mr_wr = 0x0 */
-	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_addr = 0x0 */
-	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_data = 0x0 */
-	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
-	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
-	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_type = 0x0 */
-	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
-	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
-	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
-	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
-	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
-	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_t_mrd = 0x4 */
-	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
-	/* .. .. reg_ddrc_emr2 = 0x8 */
-	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
-	/* .. .. reg_ddrc_emr3 = 0x0 */
-	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
-	/* .. .. reg_ddrc_mr = 0x930 */
-	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
-	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
-	/* .. .. reg_ddrc_emr = 0x4 */
-	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
-	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
-	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
-	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
-	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
-	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
-	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
-	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
-	/* .. .. reg_ddrc_burstchop = 0x0 */
-	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
-	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
-	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_dq = 0x0 */
-	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_debug_mode = 0x0 */
-	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_level_start = 0x0 */
-	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_level_start = 0x0 */
-	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq0_wait_t = 0x0 */
-	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
-	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
-	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
-	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
-	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
-	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
-	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
-	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
-	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
-	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
-	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
-	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
-	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
-	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
-	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
-	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
-	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
-	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
-	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
-	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
-	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
-	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
-	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
-	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
-	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
-	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
-	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
-	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
-	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
-	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
-	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
-	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
-	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
-	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
-	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
-	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
-	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
-	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. .. reg_phy_rd_local_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_local_odt = 0x3 */
-	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
-	/* .. .. reg_phy_idle_local_odt = 0x3 */
-	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
-	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
-	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
-	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
-	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
-	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
-	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
-	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_use_fixed_re = 0x1 */
-	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
-	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
-	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
-	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_clk_stall_level = 0x0 */
-	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
-	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
-	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
-	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
-	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
-	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
-	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
-	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
-	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
-	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
-	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
-	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
-	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
-	/* .. .. reg_ddrc_pageclose = 0x0 */
-	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
-	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
-	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
-	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
-	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
-	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_wc = 0x0 */
-	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
-	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_selfref_en = 0x0 */
-	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
-	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
-	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
-	/* .. .. reg_arb_go2critical_en = 0x1 */
-	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
-	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
-	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
-	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
-	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
-	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
-	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
-	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
-	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
-	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
-	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
-	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
-	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
-	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
-	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
-	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
-	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
-	/* .. .. reg_ddrc_t_cksre = 0x6 */
-	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
-	/* .. .. reg_ddrc_t_cksrx = 0x6 */
-	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
-	/* .. .. reg_ddrc_t_ckesr = 0x4 */
-	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
-	/* .. .. reg_ddrc_t_ckpde = 0x2 */
-	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
-	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
-	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
-	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
-	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
-	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
-	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
-	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
-	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
-	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
-	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
-	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
-	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
-	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_ddr3 = 0x1 */
-	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. reg_ddrc_t_mod = 0x200 */
-	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
-	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
-	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
-	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
-	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
-	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
-	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
-	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
-	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
-	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
-	/* .. .. dram_rstn_x1024 = 0x67 */
-	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
-	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
-	/* .. .. deeppowerdown_en = 0x0 */
-	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. deeppowerdown_to_x1024 = 0xff */
-	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
-	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
-	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
-	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
-	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
-	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
-	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
-	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
-	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
-	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
-	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
-	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
-	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
-	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
-	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
-	/* .. .. reg_ddrc_2t_delay = 0x0 */
-	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_skip_ocd = 0x1 */
-	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
-	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
-	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
-	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
-	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
-	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
-	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
-	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
-	/* .. .. START: RESET ECC ERROR */
-	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
-	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
-	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
-	/* .. .. FINISH: RESET ECC ERROR */
-	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
-	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
-	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
-	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
-	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
-	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
-	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
-	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
-	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
-	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
-	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
-	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
-	/* .. .. reg_ddrc_ecc_mode = 0x0 */
-	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_scrub = 0x1 */
-	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
-	/* .. .. reg_phy_dif_on = 0x0 */
-	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_phy_dif_off = 0x0 */
-	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
-	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
-	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
-	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
-	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
-	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
-	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
-	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
-	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
-	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
-	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
-	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
-	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
-	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
-	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
-	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
-	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
-	/* .. .. reg_phy_loopback = 0x0 */
-	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bl2 = 0x0 */
-	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_at_spd_atpg = 0x0 */
-	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_enable = 0x0 */
-	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_force_err = 0x0 */
-	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_mode = 0x0 */
-	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. .. reg_phy_invert_clkout = 0x1 */
-	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
-	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_phy_sel_logic = 0x0 */
-	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
-	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
-	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_use_rank0_delays = 0x1 */
-	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. reg_phy_lpddr = 0x0 */
-	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_cmd_latency = 0x0 */
-	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_int_lpbk = 0x0 */
-	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
-	/* .. .. reg_phy_wr_rl_delay = 0x2 */
-	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
-	/* .. .. reg_phy_rd_rl_delay = 0x4 */
-	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
-	/* .. .. reg_phy_dll_lock_diff = 0xf */
-	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
-	/* .. .. reg_phy_use_wr_level = 0x1 */
-	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
-	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
-	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
-	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
-	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
-	/* .. .. reg_phy_dis_calib_rst = 0x0 */
-	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
-	/* .. .. reg_arb_page_addr_mask = 0x0 */
-	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_ddrc_lpddr2 = 0x0 */
-	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
-	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_derate_enable = 0x0 */
-	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr4_margin = 0x0 */
-	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
-	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
-	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
-	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
-	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
-	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
-	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
-	/* .. .. reg_ddrc_t_mrw = 0x5 */
-	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
-	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
-	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
-	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
-	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
-	/* .. .. START: POLL ON DCI STATUS */
-	/* .. .. DONE = 1 */
-	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. .. */
-	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-	/* .. .. FINISH: POLL ON DCI STATUS */
-	/* .. .. START: UNLOCK DDR */
-	/* .. .. reg_ddrc_soft_rstb = 0x1 */
-	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_powerdown_en = 0x0 */
-	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_data_bus_width = 0x0 */
-	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
-	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
-	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
-	/* .. .. FINISH: UNLOCK DDR */
-	/* .. .. START: CHECK DDR STATUS */
-	/* .. .. ddrc_reg_operating_mode = 1 */
-	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-	/* .. .. FINISH: CHECK DDR STATUS */
-	/* .. FINISH: DDR INITIALIZATION */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: OCM REMAPPING */
-	/* .. VREF_EN = 0x1 */
-	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. VREF_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. CLK_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. SRSTN_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
-	/* .. FINISH: OCM REMAPPING */
-	/* .. START: DDRIOB SETTINGS */
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCR_TYPE = 0x0 */
-	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCR_TYPE = 0x0 */
-	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x1 */
-	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x1 */
-	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x2 */
-	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x2 */
-	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCR_TYPE = 0x0 */
-	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x3 */
-	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
-	/* .. SLEW_N = 0x3 */
-	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. VREF_INT_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. VREF_SEL = 0x0 */
-	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
-	/* .. VREF_EXT_EN = 0x3 */
-	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. VREF_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
-	/* .. REFIO_EN = 0x1 */
-	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
-	/* .. REFIO_TEST = 0x0 */
-	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
-	/* .. REFIO_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DRST_B_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. CKE_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
-	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
-	/* .. .. START: ASSERT RESET */
-	/* .. .. RESET = 1 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
-	/* .. .. FINISH: ASSERT RESET */
-	/* .. .. START: DEASSERT RESET */
-	/* .. .. RESET = 0 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
-	/* .. .. FINISH: DEASSERT RESET */
-	/* .. .. RESET = 0x1 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. ENABLE = 0x1 */
-	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. VRP_TRI = 0x0 */
-	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. VRN_TRI = 0x0 */
-	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. VRP_OUT = 0x0 */
-	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. NREF_OPT1 = 0x0 */
-	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. .. NREF_OPT2 = 0x0 */
-	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
-	/* .. .. NREF_OPT4 = 0x1 */
-	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
-	/* .. .. PREF_OPT1 = 0x0 */
-	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
-	/* .. .. PREF_OPT2 = 0x0 */
-	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
-	/* .. .. UPDATE_CONTROL = 0x0 */
-	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. INIT_COMPLETE = 0x0 */
-	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. .. TST_CLK = 0x0 */
-	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. .. TST_HLN = 0x0 */
-	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. .. TST_HLP = 0x0 */
-	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. .. TST_RST = 0x0 */
-	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. INT_DCI_EN = 0x0 */
-	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
-	/* .. FINISH: DDRIOB SETTINGS */
-	/* .. START: MIO PROGRAMMING */
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 7 */
-	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 7 */
-	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
-	/* .. SDIO0_WP_SEL = 55 */
-	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
-	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
-	/* .. SDIO0_CD_SEL = 47 */
-	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
-	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
-	/* .. FINISH: MIO PROGRAMMING */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
-	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* .. START: SRAM/NOR SET OPMODE */
-	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. IRMODE = 0x0 */
-	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. UCLKEN = 0x0 */
-	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
-	/* .. START: QSPI REGISTERS */
-	/* .. Holdb_dr = 1 */
-	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
-	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
-	/* .. FINISH: QSPI REGISTERS */
-	/* .. START: PL POWER ON RESET REGISTERS */
-	/* .. PCFG_POR_CNT_4K = 0 */
-	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
-	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
-	/* .. FINISH: PL POWER ON RESET REGISTERS */
-	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
-	/* .. .. START: NAND SET CYCLE */
-	/* .. .. FINISH: NAND SET CYCLE */
-	/* .. .. START: OPMODE */
-	/* .. .. FINISH: OPMODE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
-	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: NOR CS0 BASE ADDRESS */
-	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
-	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
-	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: NOR CS1 BASE ADDRESS */
-	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
-	/* .. .. START: USB RESET */
-	/* .. .. .. START: USB0 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. DIRECTION_1 = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x0 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: USB0 RESET */
-	/* .. .. .. START: USB1 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: USB1 RESET */
-	/* .. .. FINISH: USB RESET */
-	/* .. .. START: ENET RESET */
-	/* .. .. .. START: ENET0 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: ENET0 RESET */
-	/* .. .. .. START: ENET1 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: ENET1 RESET */
-	/* .. .. FINISH: ENET RESET */
-	/* .. .. START: I2C RESET */
-	/* .. .. .. START: I2C0 RESET */
-	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: I2C0 RESET */
-	/* .. .. .. START: I2C1 RESET */
-	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: I2C1 RESET */
-	/* .. .. FINISH: I2C RESET */
-	/* .. .. START: NOR CHIP SELECT */
-	/* .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. FINISH: NOR CHIP SELECT */
-	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_post_config_2_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: ENABLING LEVEL SHIFTER */
-	/* .. USER_INP_ICT_EN_0 = 3 */
-	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
-	/* .. USER_INP_ICT_EN_1 = 3 */
-	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
-	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
-	/* .. FINISH: ENABLING LEVEL SHIFTER */
-	/* .. START: FPGA RESETS TO 0 */
-	/* .. reserved_3 = 0 */
-	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
-	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
-	/* .. FPGA_ACP_RST = 0 */
-	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS3_RST = 0 */
-	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
-	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS2_RST = 0 */
-	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
-	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS1_RST = 0 */
-	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
-	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS0_RST = 0 */
-	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
-	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. reserved_2 = 0 */
-	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
-	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
-	/* .. FSSW1_FPGA_RST = 0 */
-	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
-	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. FSSW0_FPGA_RST = 0 */
-	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
-	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. reserved_1 = 0 */
-	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
-	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
-	/* .. FPGA_FMSW1_RST = 0 */
-	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. FPGA_FMSW0_RST = 0 */
-	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. FPGA_DMA3_RST = 0 */
-	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. FPGA_DMA2_RST = 0 */
-	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. FPGA_DMA1_RST = 0 */
-	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. FPGA_DMA0_RST = 0 */
-	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. reserved = 0 */
-	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. FPGA3_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. FPGA2_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. FPGA1_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. FPGA0_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
-	/* .. FINISH: FPGA RESETS TO 0 */
-	/* .. START: AFI REGISTERS */
-	/* .. .. START: AFI0 REGISTERS */
-	/* .. .. FINISH: AFI0 REGISTERS */
-	/* .. .. START: AFI1 REGISTERS */
-	/* .. .. FINISH: AFI1 REGISTERS */
-	/* .. .. START: AFI2 REGISTERS */
-	/* .. .. FINISH: AFI2 REGISTERS */
-	/* .. .. START: AFI3 REGISTERS */
-	/* .. .. FINISH: AFI3 REGISTERS */
-	/* .. FINISH: AFI REGISTERS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_debug_2_0[] = {
-	/* START: top */
-	/* .. START: CROSS TRIGGER CONFIGURATIONS */
-	/* .. .. START: UNLOCKING CTI REGISTERS */
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
-	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: PLL SLCR REGISTERS */
-	/* .. .. START: ARM PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x177 */
-	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x1a */
-	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. ARM_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. .. SRCSEL = 0x0 */
-	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. .. DIVISOR = 0x2 */
-	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
-	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
-	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
-	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
-	/* .. .. .. CPU_2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
-	/* .. .. .. CPU_1XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
-	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
-	/* .. .. FINISH: ARM PLL INIT */
-	/* .. .. START: DDR PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x1db */
-	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x15 */
-	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. DDR_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. .. DDR_3XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. DDR_2XCLKACT = 0x1 */
-	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
-	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
-	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
-	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
-	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
-	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
-	/* .. .. FINISH: DDR PLL INIT */
-	/* .. .. START: IO PLL INIT */
-	/* .. .. PLL_RES = 0xc */
-	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
-	/* .. .. PLL_CP = 0x2 */
-	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. LOCK_CNT = 0x1f4 */
-	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
-	/* .. .. .. START: UPDATE FB_DIV */
-	/* .. .. .. PLL_FDIV = 0x14 */
-	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
-	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
-	/* .. .. .. FINISH: UPDATE FB_DIV */
-	/* .. .. .. START: BY PASS PLL */
-	/* .. .. .. PLL_BYPASS_FORCE = 1 */
-	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
-	/* .. .. .. FINISH: BY PASS PLL */
-	/* .. .. .. START: ASSERT RESET */
-	/* .. .. .. PLL_RESET = 1 */
-	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
-	/* .. .. .. FINISH: ASSERT RESET */
-	/* .. .. .. START: DEASSERT RESET */
-	/* .. .. .. PLL_RESET = 0 */
-	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
-	/* .. .. .. FINISH: DEASSERT RESET */
-	/* .. .. .. START: CHECK PLL STATUS */
-	/* .. .. .. IO_PLL_LOCK = 1 */
-	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
-	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. .. .. */
-	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-	/* .. .. .. FINISH: CHECK PLL STATUS */
-	/* .. .. .. START: REMOVE PLL BY PASS */
-	/* .. .. .. PLL_BYPASS_FORCE = 0 */
-	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
-	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. .. */
-	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
-	/* .. .. .. FINISH: REMOVE PLL BY PASS */
-	/* .. .. FINISH: IO PLL INIT */
-	/* .. FINISH: PLL SLCR REGISTERS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: CLOCK CONTROL SLCR REGISTERS */
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. DIVISOR0 = 0x34 */
-	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
-	/* .. DIVISOR1 = 0x2 */
-	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
-	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x8 */
-	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
-	/* .. DIVISOR1 = 0x1 */
-	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
-	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
-	/* .. CLKACT = 0x1 */
-	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x5 */
-	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
-	/* .. CLKACT0 = 0x1 */
-	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. CLKACT1 = 0x0 */
-	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0x14 */
-	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
-	/* .. CLKACT0 = 0x0 */
-	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. CLKACT1 = 0x1 */
-	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. SRCSEL = 0x0 */
-	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. DIVISOR = 0xa */
-	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
-	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
-	/* .. .. START: TRACE CLOCK */
-	/* .. .. FINISH: TRACE CLOCK */
-	/* .. .. CLKACT = 0x1 */
-	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR = 0x5 */
-	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0xa */
-	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x7 */
-	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x5 */
-	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
-	/* .. .. SRCSEL = 0x0 */
-	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
-	/* .. .. DIVISOR0 = 0x14 */
-	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
-	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
-	/* .. .. DIVISOR1 = 0x1 */
-	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
-	/* .. .. CLK_621_TRUE = 0x1 */
-	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
-	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
-	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
-	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
-	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
-	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
-	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
-	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
-	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
-	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
-	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
-	/* .. START: THIS SHOULD BE BLANK */
-	/* .. FINISH: THIS SHOULD BE BLANK */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
-	/* START: top */
-	/* .. START: DDR INITIALIZATION */
-	/* .. .. START: LOCK DDR */
-	/* .. .. reg_ddrc_soft_rstb = 0 */
-	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_powerdown_en = 0x0 */
-	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_data_bus_width = 0x0 */
-	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
-	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
-	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
-	/* .. .. FINISH: LOCK DDR */
-	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
-	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
-	/* .. .. reg_ddrc_active_ranks = 0x1 */
-	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
-	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
-	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
-	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
-	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
-	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
-	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
-	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
-	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
-	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
-	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
-	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
-	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
-	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
-	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
-	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
-	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
-	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
-	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
-	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
-	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
-	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
-	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
-	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
-	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
-	/* .. .. reg_ddrc_t_rc = 0x1a */
-	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
-	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
-	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
-	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
-	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
-	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
-	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
-	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
-	/* .. .. reg_ddrc_wr2pre = 0x12 */
-	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
-	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
-	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
-	/* .. .. reg_ddrc_t_faw = 0x15 */
-	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
-	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
-	/* .. .. reg_ddrc_t_ras_max = 0x23 */
-	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
-	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
-	/* .. .. reg_ddrc_t_ras_min = 0x13 */
-	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
-	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
-	/* .. .. reg_ddrc_t_cke = 0x4 */
-	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
-	/* .. .. reg_ddrc_write_latency = 0x5 */
-	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
-	/* .. .. reg_ddrc_rd2wr = 0x7 */
-	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
-	/* .. .. reg_ddrc_wr2rd = 0xe */
-	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
-	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
-	/* .. .. reg_ddrc_t_xp = 0x4 */
-	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
-	/* .. .. reg_ddrc_pad_pd = 0x0 */
-	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rd2pre = 0x4 */
-	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
-	/* .. .. reg_ddrc_t_rcd = 0x7 */
-	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
-	/* .. .. reg_ddrc_t_ccd = 0x4 */
-	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
-	/* .. .. reg_ddrc_t_rrd = 0x6 */
-	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
-	/* .. .. reg_ddrc_refresh_margin = 0x2 */
-	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_t_rp = 0x7 */
-	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
-	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
-	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
-	/* .. .. reg_ddrc_sdram = 0x1 */
-	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
-	/* .. .. reg_ddrc_mobile = 0x0 */
-	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
-	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_read_latency = 0x7 */
-	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
-	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
-	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
-	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
-	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_loopback = 0x0 */
-	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
-	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
-	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_prefer_write = 0x0 */
-	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_max_rank_rd = 0xf */
-	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
-	/* .. .. reg_ddrc_mr_wr = 0x0 */
-	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_addr = 0x0 */
-	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_data = 0x0 */
-	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
-	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
-	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_type = 0x0 */
-	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
-	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
-	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
-	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
-	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
-	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_t_mrd = 0x4 */
-	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
-	/* .. .. reg_ddrc_emr2 = 0x8 */
-	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
-	/* .. .. reg_ddrc_emr3 = 0x0 */
-	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
-	/* .. .. reg_ddrc_mr = 0x930 */
-	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
-	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
-	/* .. .. reg_ddrc_emr = 0x4 */
-	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
-	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
-	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
-	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
-	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
-	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
-	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
-	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
-	/* .. .. reg_ddrc_burstchop = 0x0 */
-	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
-	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
-	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_dq = 0x0 */
-	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_debug_mode = 0x0 */
-	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_level_start = 0x0 */
-	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_level_start = 0x0 */
-	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq0_wait_t = 0x0 */
-	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
-	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
-	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
-	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
-	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
-	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
-	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
-	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
-	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
-	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
-	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
-	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
-	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
-	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
-	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
-	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
-	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
-	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
-	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
-	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
-	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
-	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
-	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
-	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
-	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
-	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
-	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
-	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
-	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
-	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
-	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
-	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
-	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
-	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
-	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
-	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
-	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
-	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
-	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. .. reg_phy_rd_local_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_local_odt = 0x3 */
-	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
-	/* .. .. reg_phy_idle_local_odt = 0x3 */
-	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
-	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
-	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
-	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
-	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
-	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
-	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
-	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
-	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_use_fixed_re = 0x1 */
-	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
-	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
-	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
-	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_clk_stall_level = 0x0 */
-	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
-	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
-	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
-	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
-	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
-	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
-	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
-	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
-	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
-	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
-	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
-	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
-	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
-	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
-	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
-	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
-	/* .. .. reg_ddrc_pageclose = 0x0 */
-	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
-	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
-	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
-	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
-	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
-	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_wc = 0x0 */
-	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
-	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_selfref_en = 0x0 */
-	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
-	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
-	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
-	/* .. .. reg_arb_go2critical_en = 0x1 */
-	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
-	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
-	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
-	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
-	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
-	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
-	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
-	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
-	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
-	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
-	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
-	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
-	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
-	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
-	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
-	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
-	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
-	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
-	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_ddr3 = 0x1 */
-	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. reg_ddrc_t_mod = 0x200 */
-	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
-	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
-	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
-	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
-	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
-	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
-	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
-	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
-	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
-	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
-	/* .. .. dram_rstn_x1024 = 0x67 */
-	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
-	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
-	/* .. .. deeppowerdown_en = 0x0 */
-	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. deeppowerdown_to_x1024 = 0xff */
-	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
-	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
-	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
-	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
-	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
-	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
-	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
-	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
-	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
-	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
-	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
-	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
-	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
-	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
-	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
-	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
-	/* .. .. reg_ddrc_2t_delay = 0x0 */
-	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_skip_ocd = 0x1 */
-	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
-	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
-	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
-	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
-	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
-	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
-	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
-	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
-	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
-	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
-	/* .. .. START: RESET ECC ERROR */
-	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
-	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
-	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
-	/* .. .. FINISH: RESET ECC ERROR */
-	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
-	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
-	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
-	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
-	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
-	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
-	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
-	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
-	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
-	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
-	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
-	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
-	/* .. .. reg_ddrc_ecc_mode = 0x0 */
-	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_scrub = 0x1 */
-	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
-	/* .. .. reg_phy_dif_on = 0x0 */
-	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
-	/* .. .. reg_phy_dif_off = 0x0 */
-	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_data_slice_in_use = 0x1 */
-	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
-	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
-	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
-	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_shift_dq = 0x0 */
-	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_err_clr = 0x0 */
-	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_dq_offset = 0x40 */
-	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
-	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
-	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
-	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
-	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
-	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
-	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
-	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
-	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
-	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
-	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
-	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
-	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
-	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
-	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
-	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
-	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
-	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
-	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
-	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
-	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
-	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
-	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
-	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
-	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
-	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
-	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
-	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
-	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
-	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
-	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
-	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
-	/* .. .. reg_phy_loopback = 0x0 */
-	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bl2 = 0x0 */
-	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_phy_at_spd_atpg = 0x0 */
-	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_enable = 0x0 */
-	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_force_err = 0x0 */
-	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. reg_phy_bist_mode = 0x0 */
-	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. .. reg_phy_invert_clkout = 0x1 */
-	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
-	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. .. reg_phy_sel_logic = 0x0 */
-	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
-	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
-	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
-	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
-	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_use_rank0_delays = 0x1 */
-	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
-	/* .. .. reg_phy_lpddr = 0x0 */
-	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_cmd_latency = 0x0 */
-	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_int_lpbk = 0x0 */
-	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
-	/* .. .. reg_phy_wr_rl_delay = 0x2 */
-	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
-	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
-	/* .. .. reg_phy_rd_rl_delay = 0x4 */
-	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
-	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
-	/* .. .. reg_phy_dll_lock_diff = 0xf */
-	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
-	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
-	/* .. .. reg_phy_use_wr_level = 0x1 */
-	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
-	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
-	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
-	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
-	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
-	/* .. .. reg_phy_dis_calib_rst = 0x0 */
-	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
-	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
-	/* .. .. reg_arb_page_addr_mask = 0x0 */
-	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
-	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
-	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
-	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
-	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
-	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
-	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
-	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
-	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
-	/* .. .. reg_ddrc_lpddr2 = 0x0 */
-	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
-	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_derate_enable = 0x0 */
-	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_mr4_margin = 0x0 */
-	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
-	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
-	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
-	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
-	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
-	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
-	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
-	/* .. .. reg_ddrc_t_mrw = 0x5 */
-	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
-	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
-	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
-	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
-	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
-	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
-	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
-	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
-	/* .. .. START: POLL ON DCI STATUS */
-	/* .. .. DONE = 1 */
-	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. .. */
-	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-	/* .. .. FINISH: POLL ON DCI STATUS */
-	/* .. .. START: UNLOCK DDR */
-	/* .. .. reg_ddrc_soft_rstb = 0x1 */
-	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. reg_ddrc_powerdown_en = 0x0 */
-	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_data_bus_width = 0x0 */
-	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
-	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
-	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
-	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
-	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
-	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
-	/* .. .. FINISH: UNLOCK DDR */
-	/* .. .. START: CHECK DDR STATUS */
-	/* .. .. ddrc_reg_operating_mode = 1 */
-	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
-	/* .. .. */
-	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-	/* .. .. FINISH: CHECK DDR STATUS */
-	/* .. FINISH: DDR INITIALIZATION */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: OCM REMAPPING */
-	/* .. VREF_EN = 0x1 */
-	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. VREF_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. CLK_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. SRSTN_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
-	/* .. FINISH: OCM REMAPPING */
-	/* .. START: DDRIOB SETTINGS */
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCR_TYPE = 0x0 */
-	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCR_TYPE = 0x0 */
-	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x1 */
-	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x1 */
-	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x2 */
-	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x2 */
-	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x1 */
-	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. DCR_TYPE = 0x3 */
-	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. IBUF_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0 */
-	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
-	/* .. INP_POWER = 0x0 */
-	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. INP_TYPE = 0x0 */
-	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. DCI_UPDATE = 0x0 */
-	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. TERM_EN = 0x0 */
-	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. DCR_TYPE = 0x0 */
-	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
-	/* .. IBUF_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. TERM_DISABLE_MODE = 0x0 */
-	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. OUTPUT_EN = 0x3 */
-	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
-	/* .. PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x3 */
-	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
-	/* .. SLEW_N = 0x3 */
-	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. DRIVE_P = 0x1c */
-	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
-	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
-	/* .. DRIVE_N = 0xc */
-	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
-	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
-	/* .. SLEW_P = 0x6 */
-	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
-	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
-	/* .. SLEW_N = 0x1f */
-	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
-	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
-	/* .. GTL = 0x0 */
-	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
-	/* .. RTERM = 0x0 */
-	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
-	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
-	/* .. VREF_INT_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. VREF_SEL = 0x0 */
-	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
-	/* .. VREF_EXT_EN = 0x3 */
-	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
-	/* .. VREF_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
-	/* .. REFIO_EN = 0x1 */
-	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
-	/* .. REFIO_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DRST_B_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. CKE_PULLUP_EN = 0x0 */
-	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
-	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
-	/* .. .. START: ASSERT RESET */
-	/* .. .. RESET = 1 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
-	/* .. .. FINISH: ASSERT RESET */
-	/* .. .. START: DEASSERT RESET */
-	/* .. .. RESET = 0 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. .. VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
-	/* .. .. FINISH: DEASSERT RESET */
-	/* .. .. RESET = 0x1 */
-	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. .. ENABLE = 0x1 */
-	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. .. VRP_TRI = 0x0 */
-	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. .. VRN_TRI = 0x0 */
-	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. .. VRP_OUT = 0x0 */
-	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
-	/* .. .. VRN_OUT = 0x1 */
-	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
-	/* .. .. NREF_OPT1 = 0x0 */
-	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. .. NREF_OPT2 = 0x0 */
-	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
-	/* .. .. NREF_OPT4 = 0x1 */
-	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
-	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
-	/* .. .. PREF_OPT1 = 0x0 */
-	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
-	/* .. .. PREF_OPT2 = 0x0 */
-	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
-	/* .. .. UPDATE_CONTROL = 0x0 */
-	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. .. INIT_COMPLETE = 0x0 */
-	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. .. TST_CLK = 0x0 */
-	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. .. TST_HLN = 0x0 */
-	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. .. TST_HLP = 0x0 */
-	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. .. TST_RST = 0x0 */
-	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
-	/* .. .. INT_DCI_EN = 0x0 */
-	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
-	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
-	/* .. FINISH: DDRIOB SETTINGS */
-	/* .. START: MIO PROGRAMMING */
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 3 */
-	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 1 */
-	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 1 */
-	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 4 */
-	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 1 */
-	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 1 */
-	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 1 */
-	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 7 */
-	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
-	/* .. TRI_ENABLE = 1 */
-	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 7 */
-	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 0 */
-	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
-	/* .. TRI_ENABLE = 0 */
-	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. L0_SEL = 0 */
-	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. L1_SEL = 0 */
-	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. L2_SEL = 0 */
-	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
-	/* .. L3_SEL = 4 */
-	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
-	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
-	/* .. Speed = 0 */
-	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. IO_Type = 1 */
-	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
-	/* .. PULLUP = 0 */
-	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. DisableRcvr = 0 */
-	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
-	/* .. SDIO0_WP_SEL = 55 */
-	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
-	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
-	/* .. SDIO0_CD_SEL = 47 */
-	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
-	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
-	/* .. FINISH: MIO PROGRAMMING */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
-	/* .. IBUF_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
-	/* .. TERM_DISABLE_MODE = 0x1 */
-	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
-	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* .. START: SRAM/NOR SET OPMODE */
-	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. IRMODE = 0x0 */
-	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. UCLKEN = 0x0 */
-	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
-	/* .. START: QSPI REGISTERS */
-	/* .. Holdb_dr = 1 */
-	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
-	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
-	/* .. FINISH: QSPI REGISTERS */
-	/* .. START: PL POWER ON RESET REGISTERS */
-	/* .. PCFG_POR_CNT_4K = 0 */
-	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
-	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
-	/* .. FINISH: PL POWER ON RESET REGISTERS */
-	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
-	/* .. .. START: NAND SET CYCLE */
-	/* .. .. FINISH: NAND SET CYCLE */
-	/* .. .. START: OPMODE */
-	/* .. .. FINISH: OPMODE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
-	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: NOR CS0 BASE ADDRESS */
-	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
-	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
-	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
-	/* .. .. START: DIRECT COMMAND */
-	/* .. .. FINISH: DIRECT COMMAND */
-	/* .. .. START: NOR CS1 BASE ADDRESS */
-	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
-	/* .. .. START: USB RESET */
-	/* .. .. .. START: USB0 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. DIRECTION_1 = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x0 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. MASK_1_LSW = 0xbfff */
-	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
-	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
-	/* .. .. .. .. DATA_1_LSW = 0x4000 */
-	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
-	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
-	/* .. .. .. .. */
-	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: USB0 RESET */
-	/* .. .. .. START: USB1 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: USB1 RESET */
-	/* .. .. FINISH: USB RESET */
-	/* .. .. START: ENET RESET */
-	/* .. .. .. START: ENET0 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: ENET0 RESET */
-	/* .. .. .. START: ENET1 RESET */
-	/* .. .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. .. START: DIR MODE BANK 1 */
-	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: ENET1 RESET */
-	/* .. .. FINISH: ENET RESET */
-	/* .. .. START: I2C RESET */
-	/* .. .. .. START: I2C0 RESET */
-	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: I2C0 RESET */
-	/* .. .. .. START: I2C1 RESET */
-	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
-	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: OUTPUT ENABLE */
-	/* .. .. .. .. FINISH: OUTPUT ENABLE */
-	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
-	/* .. .. .. .. START: ADD 1 MS DELAY */
-	/* .. .. .. .. */
-	EMIT_MASKDELAY(0XF8F00200, 1),
-	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
-	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
-	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
-	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
-	/* .. .. .. FINISH: I2C1 RESET */
-	/* .. .. FINISH: I2C RESET */
-	/* .. .. START: NOR CHIP SELECT */
-	/* .. .. .. START: DIR MODE BANK 0 */
-	/* .. .. .. FINISH: DIR MODE BANK 0 */
-	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
-	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
-	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
-	/* .. .. FINISH: NOR CHIP SELECT */
-	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_post_config_1_0[] = {
-	/* START: top */
-	/* .. START: SLCR SETTINGS */
-	/* .. UNLOCK_KEY = 0XDF0D */
-	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
-	/* .. FINISH: SLCR SETTINGS */
-	/* .. START: ENABLING LEVEL SHIFTER */
-	/* .. USER_INP_ICT_EN_0 = 3 */
-	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
-	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
-	/* .. USER_INP_ICT_EN_1 = 3 */
-	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
-	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
-	/* .. FINISH: ENABLING LEVEL SHIFTER */
-	/* .. START: FPGA RESETS TO 0 */
-	/* .. reserved_3 = 0 */
-	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
-	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
-	/* .. FPGA_ACP_RST = 0 */
-	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
-	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS3_RST = 0 */
-	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
-	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS2_RST = 0 */
-	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
-	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS1_RST = 0 */
-	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
-	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
-	/* .. FPGA_AXDS0_RST = 0 */
-	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
-	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
-	/* .. reserved_2 = 0 */
-	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
-	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
-	/* .. FSSW1_FPGA_RST = 0 */
-	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
-	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
-	/* .. FSSW0_FPGA_RST = 0 */
-	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
-	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
-	/* .. reserved_1 = 0 */
-	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
-	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
-	/* .. FPGA_FMSW1_RST = 0 */
-	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
-	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
-	/* .. FPGA_FMSW0_RST = 0 */
-	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
-	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
-	/* .. FPGA_DMA3_RST = 0 */
-	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. FPGA_DMA2_RST = 0 */
-	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. FPGA_DMA1_RST = 0 */
-	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
-	/* .. FPGA_DMA0_RST = 0 */
-	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. reserved = 0 */
-	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
-	/* .. FPGA3_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. FPGA2_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
-	/* .. FPGA1_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
-	/* .. FPGA0_OUT_RST = 0 */
-	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
-	/* .. FINISH: FPGA RESETS TO 0 */
-	/* .. START: AFI REGISTERS */
-	/* .. .. START: AFI0 REGISTERS */
-	/* .. .. FINISH: AFI0 REGISTERS */
-	/* .. .. START: AFI1 REGISTERS */
-	/* .. .. FINISH: AFI1 REGISTERS */
-	/* .. .. START: AFI2 REGISTERS */
-	/* .. .. FINISH: AFI2 REGISTERS */
-	/* .. .. START: AFI3 REGISTERS */
-	/* .. .. FINISH: AFI3 REGISTERS */
-	/* .. FINISH: AFI REGISTERS */
-	/* .. START: LOCK IT BACK */
-	/* .. LOCK_KEY = 0X767B */
-	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
-	/* .. */
-	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	/* .. FINISH: LOCK IT BACK */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-unsigned long ps7_debug_1_0[] = {
-	/* START: top */
-	/* .. START: CROSS TRIGGER CONFIGURATIONS */
-	/* .. .. START: UNLOCKING CTI REGISTERS */
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. KEY = 0XC5ACCE55 */
-	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
-	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
-	/* .. .. */
-	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
-	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
-	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
-	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
-	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
-	/* FINISH: top */
-	/* */
-	EMIT_EXIT(),
-
-	/* */
-};
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
-	char *err_msg = "";
-	switch (key) {
-	case PS7_INIT_SUCCESS:
-		err_msg = "PS7 initialization successful";
-		break;
-	case PS7_INIT_CORRUPT:
-		err_msg = "PS7 init Data Corrupted";
-		break;
-	case PS7_INIT_TIMEOUT:
-		err_msg = "PS7 init mask poll timeout";
-		break;
-	case PS7_POLL_FAILED_DDR_INIT:
-		err_msg = "Mask Poll failed for DDR Init";
-		break;
-	case PS7_POLL_FAILED_DMA:
-		err_msg = "Mask Poll failed for PLL Init";
-		break;
-	case PS7_POLL_FAILED_PLL:
-		err_msg = "Mask Poll failed for DMA done bit";
-		break;
-	default:
-		err_msg = "Undefined error status";
-		break;
-	}
-
-	return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
-	/* Read PS version from MCTRL register [31:28] */
-	unsigned long mask = 0xF0000000;
-	unsigned long *addr = (unsigned long *)0XF8007080;
-	unsigned long ps_version = (*addr & mask) >> 28;
-	return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
-	unsigned long *addr = (unsigned long *)add;
-	*addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
-	volatile unsigned long *addr = (volatile unsigned long *)add;
-	int i = 0;
-	while (!(*addr & mask)) {
-		if (i == PS7_MASK_POLL_TIME)
-			return -1;
-		i++;
-	}
-	return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
-	unsigned long *addr = (unsigned long *)add;
-	unsigned long val = (*addr & mask);
-	return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
-	unsigned long *ptr = ps7_config_init;
-
-	unsigned long opcode;	/* current instruction .. */
-	unsigned long args[16];	/* no opcode has so many args ... */
-	int numargs;		/* number of arguments of this instruction */
-	int j;			/* general purpose index */
-
-	volatile unsigned long *addr;	/* some variable to make code readable */
-	unsigned long val, mask;	/* some variable to make code readable */
-
-	int finish = -1;	/* loop while this is negative ! */
-	int i = 0;		/* Timeout variable */
-
-	while (finish < 0) {
-		numargs = ptr[0] & 0xF;
-		opcode = ptr[0] >> 4;
-
-		for (j = 0; j < numargs; j++)
-			args[j] = ptr[j + 1];
-		ptr += numargs + 1;
-
-		switch (opcode) {
-		case OPCODE_EXIT:
-			finish = PS7_INIT_SUCCESS;
-			break;
-
-		case OPCODE_CLEAR:
-			addr = (unsigned long *)args[0];
-			*addr = 0;
-			break;
-
-		case OPCODE_WRITE:
-			addr = (unsigned long *)args[0];
-			val = args[1];
-			*addr = val;
-			break;
-
-		case OPCODE_MASKWRITE:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			val = args[2];
-			*addr = (val & mask) | (*addr & ~mask);
-			break;
-
-		case OPCODE_MASKPOLL:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			i = 0;
-			while (!(*addr & mask)) {
-				if (i == PS7_MASK_POLL_TIME) {
-					finish = PS7_INIT_TIMEOUT;
-					break;
-				}
-				i++;
-			}
-			break;
-		case OPCODE_MASKDELAY:
-			addr = (unsigned long *)args[0];
-			mask = args[1];
-			int delay = get_number_of_cycles_for_delay(mask);
-			perf_reset_and_start_timer();
-			while ((*addr < delay))
-				;
-			break;
-		default:
-			finish = PS7_INIT_CORRUPT;
-			break;
-		}
-	}
-	return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int ps7_post_config(void)
-{
-	/* Get the PS_VERSION on run time */
-	unsigned long si_ver = ps7GetSiliconVersion();
-	int ret = -1;
-	if (si_ver == PCW_SILICON_VERSION_1) {
-		ret = ps7_config(ps7_post_config_1_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	} else if (si_ver == PCW_SILICON_VERSION_2) {
-		ret = ps7_config(ps7_post_config_2_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	} else {
-		ret = ps7_config(ps7_post_config_3_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	}
-	return PS7_INIT_SUCCESS;
-}
-
-int ps7_debug(void)
-{
-	/* Get the PS_VERSION on run time */
-	unsigned long si_ver = ps7GetSiliconVersion();
-	int ret = -1;
-	if (si_ver == PCW_SILICON_VERSION_1) {
-		ret = ps7_config(ps7_debug_1_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	} else if (si_ver == PCW_SILICON_VERSION_2) {
-		ret = ps7_config(ps7_debug_2_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	} else {
-		ret = ps7_config(ps7_debug_3_0);
-		if (ret != PS7_INIT_SUCCESS)
-			return ret;
-	}
-	return PS7_INIT_SUCCESS;
-}
-
-int ps7_init(void)
-{
-	/* Get the PS_VERSION on run time */
-	unsigned long si_ver = ps7GetSiliconVersion();
-	int ret;
-	/*int pcw_ver = 0; */
-
-	if (si_ver == PCW_SILICON_VERSION_1) {
-		ps7_mio_init_data = ps7_mio_init_data_1_0;
-		ps7_pll_init_data = ps7_pll_init_data_1_0;
-		ps7_clock_init_data = ps7_clock_init_data_1_0;
-		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
-		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
-		/*pcw_ver = 1; */
-
-	} else if (si_ver == PCW_SILICON_VERSION_2) {
-		ps7_mio_init_data = ps7_mio_init_data_2_0;
-		ps7_pll_init_data = ps7_pll_init_data_2_0;
-		ps7_clock_init_data = ps7_clock_init_data_2_0;
-		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
-		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
-		/*pcw_ver = 2; */
-
-	} else {
-		ps7_mio_init_data = ps7_mio_init_data_3_0;
-		ps7_pll_init_data = ps7_pll_init_data_3_0;
-		ps7_clock_init_data = ps7_clock_init_data_3_0;
-		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-		/*pcw_ver = 3; */
-	}
-
-	/* MIO init */
-	ret = ps7_config(ps7_mio_init_data);
-	if (ret != PS7_INIT_SUCCESS)
-		return ret;
-
-	/* PLL init */
-	ret = ps7_config(ps7_pll_init_data);
-	if (ret != PS7_INIT_SUCCESS)
-		return ret;
-
-	/* Clock init */
-	ret = ps7_config(ps7_clock_init_data);
-	if (ret != PS7_INIT_SUCCESS)
-		return ret;
-
-	/* DDR init */
-	ret = ps7_config(ps7_ddr_init_data);
-	if (ret != PS7_INIT_SUCCESS)
-		return ret;
-
-	/* Peripherals init */
-	ret = ps7_config(ps7_peripherals_init_data);
-	if (ret != PS7_INIT_SUCCESS)
-		return ret;
-	return PS7_INIT_SUCCESS;
-}
-
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) |	/* Timer Enable */
-							      (1 << 3) |	/* Auto-increment */
-							      (0 << 8)	/* Pre-scale */
-	    );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
-	perf_disable_clock();
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
-	/* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
-	return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
-	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
-	perf_reset_clock();
-	perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
deleted file mode 100644
index 22d9fd9..0000000
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int  u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define OPCODE_MASKDELAY  5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
-#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
-#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
-#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  650000000
-#define DDR_FREQ  525000000
-#define DCI_FREQ  10096154
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  10000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  10000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  100000000
-#define SPI_FREQ  10000000
-#define I2C_FREQ  108333336
-#define WDT_FREQ  108333336
-#define TTC_FREQ  50000000
-#define CAN_FREQ  10000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  200000000
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  142857132
-#define FPGA2_FREQ  200000000
-#define FPGA3_FREQ  50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-int ps7_debug(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
new file mode 100644
index 0000000..eb29002
--- /dev/null
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -0,0 +1,12963 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+
+  return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        unsigned long *addr = (unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        unsigned long *addr = (unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ )
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+
+        switch ( opcode ) {
+
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer();
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	);
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+	    perf_reset_clock();
+	    perf_start_clock();
+}
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
new file mode 100644
index 0000000..bdea5a0
--- /dev/null
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  100000000
+#define FPGA2_FREQ  33333336
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
new file mode 100644
index 0000000..abfd911
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -0,0 +1,13296 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+
+  return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        unsigned long *addr = (unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        unsigned long *addr = (unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ )
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+
+        switch ( opcode ) {
+
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer();
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	);
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+	    perf_reset_clock();
+	    perf_start_clock();
+}
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
new file mode 100644
index 0000000..16fa810
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  25000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  23809523
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  50000000
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
new file mode 100644
index 0000000..77fd949
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -0,0 +1,13203 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+
+  return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        unsigned long *addr = (unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        unsigned long *addr = (unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ )
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+
+        switch ( opcode ) {
+
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer();
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	);
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+	    perf_reset_clock();
+	    perf_start_clock();
+}
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
new file mode 100644
index 0000000..8527eef
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  25000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  50000000
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
new file mode 100644
index 0000000..f4f45be
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -0,0 +1,12861 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // ..
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // ..
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. ..
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+
+  return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        unsigned long *addr = (unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        unsigned long *addr = (unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ )
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+
+
+        switch ( opcode ) {
+
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer();
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	);
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+	    perf_reset_clock();
+	    perf_start_clock();
+}
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
new file mode 100644
index 0000000..9b41e28
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
@@ -0,0 +1,117 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier:	GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  142857132
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
new file mode 100644
index 0000000..83daf7b
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -0,0 +1,13045 @@
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_t_cksre = 0x6 */
+	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_t_cksrx = 0x6 */
+	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_t_ckesr = 0x4 */
+	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	/* .. .. reg_ddrc_t_ckpde = 0x2 */
+	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
+	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
+	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
+	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
+	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B00[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. reserved_SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. reserved_VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. reserved_REFIO_TEST = 0x0 */
+	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
+	/* .. reserved_REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. reserved_DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. reserved_CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reserved_VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reserved_VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reserved_INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reserved_INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: UART REGISTERS */
+	/* .. BDIV = 0x6 */
+	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
+	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	/* .. CD = 0x7c */
+	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	/* .. STPBRK = 0x0 */
+	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. STTBRK = 0x0 */
+	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. RSTTO = 0x0 */
+	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. TXDIS = 0x0 */
+	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. TXEN = 0x1 */
+	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. RXDIS = 0x0 */
+	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. RXEN = 0x1 */
+	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. TXRES = 0x1 */
+	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. RXRES = 0x1 */
+	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	/* .. CHMODE = 0x0 */
+	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
+	/* .. NBSTOP = 0x0 */
+	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. PAR = 0x4 */
+	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
+	/* .. CHRL = 0x0 */
+	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. CLKS = 0x0 */
+	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+	/* .. FINISH: UART REGISTERS */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_LVL_INP_EN_0 = 1 */
+	/* .. ==> 0XF8000900[3:3] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. USER_LVL_OUT_EN_0 = 1 */
+	/* .. ==> 0XF8000900[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. USER_LVL_INP_EN_1 = 1 */
+	/* .. ==> 0XF8000900[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. USER_LVL_OUT_EN_1 = 1 */
+	/* .. ==> 0XF8000900[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. reserved_FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. reserved_FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. .. START: AFI2 SECURE REGISTER */
+	/* .. .. FINISH: AFI2 SECURE REGISTER */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_debug_3_0[] = {
+	/* START: top */
+	/* .. START: CROSS TRIGGER CONFIGURATIONS */
+	/* .. .. START: UNLOCKING CTI REGISTERS */
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
+	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
+	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_sdram = 0x1 */
+	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_loopback = 0x0 */
+	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_max_rank_rd = 0xf */
+	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_debug_mode = 0x0 */
+	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq0_wait_t = 0x0 */
+	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
+	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_t_cksre = 0x6 */
+	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_t_cksrx = 0x6 */
+	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_t_ckesr = 0x4 */
+	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	/* .. .. reg_ddrc_t_ckpde = 0x2 */
+	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
+	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
+	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
+	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
+	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
+	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
+	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
+	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_2t_delay = 0x0 */
+	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_loopback = 0x0 */
+	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_rank0_delays = 0x1 */
+	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_int_lpbk = 0x0 */
+	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. CLK_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. SRSTN_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. REFIO_TEST = 0x0 */
+	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
+	/* .. REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: UART REGISTERS */
+	/* .. BDIV = 0x6 */
+	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
+	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	/* .. CD = 0x7c */
+	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	/* .. STPBRK = 0x0 */
+	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. STTBRK = 0x0 */
+	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. RSTTO = 0x0 */
+	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. TXDIS = 0x0 */
+	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. TXEN = 0x1 */
+	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. RXDIS = 0x0 */
+	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. RXEN = 0x1 */
+	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. TXRES = 0x1 */
+	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. RXRES = 0x1 */
+	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	/* .. IRMODE = 0x0 */
+	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. UCLKEN = 0x0 */
+	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. CHMODE = 0x0 */
+	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
+	/* .. NBSTOP = 0x0 */
+	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. PAR = 0x4 */
+	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
+	/* .. CHRL = 0x0 */
+	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. CLKS = 0x0 */
+	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
+	/* .. FINISH: UART REGISTERS */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_INP_ICT_EN_0 = 3 */
+	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
+	/* .. USER_INP_ICT_EN_1 = 3 */
+	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
+	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_debug_2_0[] = {
+	/* START: top */
+	/* .. START: CROSS TRIGGER CONFIGURATIONS */
+	/* .. .. START: UNLOCKING CTI REGISTERS */
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
+	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
+	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_sdram = 0x1 */
+	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_loopback = 0x0 */
+	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_max_rank_rd = 0xf */
+	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_debug_mode = 0x0 */
+	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq0_wait_t = 0x0 */
+	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
+	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
+	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
+	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
+	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_2t_delay = 0x0 */
+	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_loopback = 0x0 */
+	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_rank0_delays = 0x1 */
+	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_int_lpbk = 0x0 */
+	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. CLK_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. SRSTN_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: UART REGISTERS */
+	/* .. BDIV = 0x6 */
+	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
+	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	/* .. CD = 0x7c */
+	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	/* .. STPBRK = 0x0 */
+	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. STTBRK = 0x0 */
+	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. RSTTO = 0x0 */
+	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. TXDIS = 0x0 */
+	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. TXEN = 0x1 */
+	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. RXDIS = 0x0 */
+	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. RXEN = 0x1 */
+	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. TXRES = 0x1 */
+	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. RXRES = 0x1 */
+	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	/* .. IRMODE = 0x0 */
+	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. UCLKEN = 0x0 */
+	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. CHMODE = 0x0 */
+	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
+	/* .. NBSTOP = 0x0 */
+	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. PAR = 0x4 */
+	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
+	/* .. CHRL = 0x0 */
+	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. CLKS = 0x0 */
+	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
+	/* .. FINISH: UART REGISTERS */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_INP_ICT_EN_0 = 3 */
+	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
+	/* .. USER_INP_ICT_EN_1 = 3 */
+	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
+	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_debug_1_0[] = {
+	/* START: top */
+	/* .. START: CROSS TRIGGER CONFIGURATIONS */
+	/* .. .. START: UNLOCKING CTI REGISTERS */
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. KEY = 0XC5ACCE55 */
+	/* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+	/* .. .. FINISH: UNLOCKING CTI REGISTERS */
+	/* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+	/* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+	/* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+	/* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+	/* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char *getPS7MessageInfo(unsigned key)
+{
+	char *err_msg = "";
+	switch (key) {
+	case PS7_INIT_SUCCESS:
+		err_msg = "PS7 initialization successful";
+		break;
+	case PS7_INIT_CORRUPT:
+		err_msg = "PS7 init Data Corrupted";
+		break;
+	case PS7_INIT_TIMEOUT:
+		err_msg = "PS7 init mask poll timeout";
+		break;
+	case PS7_POLL_FAILED_DDR_INIT:
+		err_msg = "Mask Poll failed for DDR Init";
+		break;
+	case PS7_POLL_FAILED_DMA:
+		err_msg = "Mask Poll failed for PLL Init";
+		break;
+	case PS7_POLL_FAILED_PLL:
+		err_msg = "Mask Poll failed for DMA done bit";
+		break;
+	default:
+		err_msg = "Undefined error status";
+		break;
+	}
+
+	return err_msg;
+}
+
+unsigned long ps7GetSiliconVersion(void)
+{
+	/* Read PS version from MCTRL register [31:28] */
+	unsigned long mask = 0xF0000000;
+	unsigned long *addr = (unsigned long *)0XF8007080;
+	unsigned long ps_version = (*addr & mask) >> 28;
+	return ps_version;
+}
+
+void mask_write(unsigned long add, unsigned long mask, unsigned long val)
+{
+	unsigned long *addr = (unsigned long *)add;
+	*addr = (val & mask) | (*addr & ~mask);
+}
+
+int mask_poll(unsigned long add, unsigned long mask)
+{
+	volatile unsigned long *addr = (volatile unsigned long *)add;
+	int i = 0;
+	while (!(*addr & mask)) {
+		if (i == PS7_MASK_POLL_TIME)
+			return -1;
+		i++;
+	}
+	return 1;
+}
+
+unsigned long mask_read(unsigned long add, unsigned long mask)
+{
+	unsigned long *addr = (unsigned long *)add;
+	unsigned long val = (*addr & mask);
+	return val;
+}
+
+int ps7_config(unsigned long *ps7_config_init)
+{
+	unsigned long *ptr = ps7_config_init;
+
+	unsigned long opcode;	/* current instruction .. */
+	unsigned long args[16];	/* no opcode has so many args ... */
+	int numargs;		/* number of arguments of this instruction */
+	int j;			/* general purpose index */
+
+	volatile unsigned long *addr;	/* some variable to make code readable */
+	unsigned long val, mask;	/* some variable to make code readable */
+
+	int finish = -1;	/* loop while this is negative ! */
+	int i = 0;		/* Timeout variable */
+
+	while (finish < 0) {
+		numargs = ptr[0] & 0xF;
+		opcode = ptr[0] >> 4;
+
+		for (j = 0; j < numargs; j++)
+			args[j] = ptr[j + 1];
+		ptr += numargs + 1;
+
+		switch (opcode) {
+		case OPCODE_EXIT:
+			finish = PS7_INIT_SUCCESS;
+			break;
+
+		case OPCODE_CLEAR:
+			addr = (unsigned long *)args[0];
+			*addr = 0;
+			break;
+
+		case OPCODE_WRITE:
+			addr = (unsigned long *)args[0];
+			val = args[1];
+			*addr = val;
+			break;
+
+		case OPCODE_MASKWRITE:
+			addr = (unsigned long *)args[0];
+			mask = args[1];
+			val = args[2];
+			*addr = (val & mask) | (*addr & ~mask);
+			break;
+
+		case OPCODE_MASKPOLL:
+			addr = (unsigned long *)args[0];
+			mask = args[1];
+			i = 0;
+			while (!(*addr & mask)) {
+				if (i == PS7_MASK_POLL_TIME) {
+					finish = PS7_INIT_TIMEOUT;
+					break;
+				}
+				i++;
+			}
+			break;
+		case OPCODE_MASKDELAY:
+			addr = (unsigned long *)args[0];
+			mask = args[1];
+			int delay = get_number_of_cycles_for_delay(mask);
+			perf_reset_and_start_timer();
+			while ((*addr < delay))
+				;
+			break;
+		default:
+			finish = PS7_INIT_CORRUPT;
+			break;
+		}
+	}
+	return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_debug(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_debug_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_debug_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_debug_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+	/*int pcw_ver = 0; */
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+		/*pcw_ver = 1; */
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+		/*pcw_ver = 2; */
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+		/*pcw_ver = 3; */
+	}
+
+	/* MIO init */
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* PLL init */
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* Clock init */
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* DDR init */
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* Peripherals init */
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
+
+/* For delay calculation using global timer */
+
+/* start timer */
+void perf_start_clock(void)
+{
+	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) |	/* Timer Enable */
+							      (1 << 3) |	/* Auto-increment */
+							      (0 << 8)	/* Pre-scale */
+	    );
+}
+
+/* stop timer and reset timer count regs */
+void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+	/* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
+	return APU_FREQ * delay / (2 * 1000);
+}
+
+/* stop timer */
+void perf_disable_clock(void)
+{
+	*(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer(void)
+{
+	perf_reset_clock();
+	perf_start_clock();
+}
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
new file mode 100644
index 0000000..22d9fd9
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef unsigned int  u32; */
+
+/** do we need to make this name more unique ? **/
+/*extern u32 ps7_init_data[]; */
+extern unsigned long *ps7_ddr_init_data;
+extern unsigned long *ps7_mio_init_data;
+extern unsigned long *ps7_pll_init_data;
+extern unsigned long *ps7_clock_init_data;
+extern unsigned long *ps7_peripherals_init_data;
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ((OPCODE_EXIT      << 4) | 0)
+#define EMIT_CLEAR(addr)              ((OPCODE_CLEAR     << 4) | 1) , addr
+#define EMIT_WRITE(addr, val)          ((OPCODE_WRITE     << 4) | 2) , addr, val
+#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)      ((OPCODE_MASKPOLL  << 4) | 2) , addr, mask
+#define EMIT_MASKDELAY(addr, mask)      ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)	/* 0 is success in good old C */
+#define PS7_INIT_CORRUPT   (1)	/* 1 the data is corrupted, and slcr reg are in corrupted state now */
+#define PS7_INIT_TIMEOUT   (2)	/* 2 when a poll operation timed out */
+#define PS7_POLL_FAILED_DDR_INIT (3)	/* 3 when a poll operation timed out for ddr init */
+#define PS7_POLL_FAILED_DMA      (4)	/* 4 when a poll operation timed out for dma done bit */
+#define PS7_POLL_FAILED_PLL      (5)	/* 5 when a poll operation timed out for pll sequence init */
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  650000000
+#define DDR_FREQ  525000000
+#define DCI_FREQ  10096154
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  108333336
+#define WDT_FREQ  108333336
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  142857132
+#define FPGA2_FREQ  200000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config(unsigned long *);
+int ps7_init(void);
+int ps7_post_config(void);
+int ps7_debug(void);
+char *getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(void);
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 7c66247..d0b1ec9 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_microzed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_MICROZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index b46ab44..3624424 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_picozed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_PICOZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 052679a..e1b1fc9 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
 CONFIG_SPL=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 3539f05..63d32d9 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC706=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 6a4726c..6ccbb8c 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 46dd6be..e6c646b 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 12f0e2c..a8cfeb8 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 8c7efe5..f2d00ca 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7976e07..7783eeb 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index cd222c5..9236c5e 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zybo"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZYBO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
 CONFIG_SPL=y
 CONFIG_FIT=y
-- 
cgit v0.10.2


From 32ff58bb2e1f66aa0fc9d0e9913cdca54eb819a9 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:52 +0800
Subject: imx-common: introduce simpler macros for runtime dection

Introduce simpler macros for runtime cpu dection.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 386c2dc..32f95b3 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -24,7 +24,15 @@
 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
 #define is_soc_type(soc) (get_soc_type() == soc)
 
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
-- 
cgit v0.10.2


From dea572379e267780d7388f1ff28fca79537215c6 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:53 +0800
Subject: imx: mx6: support i.MX6SOLO when enable/disable_ldb_di_clock_sources

i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support
when enable/disable_ldb_di_clock_sources.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index e6f2275..a850d1a 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1228,7 +1228,7 @@ static void disable_ldb_di_clock_sources(void)
 	/* Make sure PFDs are disabled at boot. */
 	reg = readl(&mxc_ccm->analog_pfd_528);
 	/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
-	if (is_cpu_type(MXC_CPU_MX6DL))
+	if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
 		reg |= 0x80008080;
 	else
 		reg |= 0x80808080;
@@ -1251,7 +1251,7 @@ static void enable_ldb_di_clock_sources(void)
 	int reg;
 
 	reg = readl(&mxc_ccm->analog_pfd_528);
-	if (is_cpu_type(MXC_CPU_MX6DL))
+	if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
 		reg &= ~(0x80008080);
 	else
 		reg &= ~(0x80808080);
-- 
cgit v0.10.2


From b949fd2ccbd1d9877d85e1febdfe2e96b5c150c2 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:54 +0800
Subject: imx: mx6: use simpler runtime cpu dection macros

Use simpler runtime cpu dection macros.
i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index a850d1a..ff932aa 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -97,7 +97,7 @@ void enable_enet_clk(unsigned char enable)
 {
 	u32 mask, *addr;
 
-	if (is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6ul()) {
 		mask = MXC_CCM_CCGR3_ENET_MASK;
 		addr = &imx_ccm->CCGR3;
 	} else {
@@ -117,7 +117,7 @@ void enable_uart_clk(unsigned char enable)
 {
 	u32 mask;
 
-	if (is_cpu_type(MXC_CPU_MX6UL))
+	if (is_mx6ul())
 		mask = MXC_CCM_CCGR5_UART_MASK;
 	else
 		mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +168,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 			reg &= ~mask;
 		__raw_writel(reg, &imx_ccm->CCGR2);
 	} else {
-		if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+		if (is_mx6sx() || is_mx6ul()) {
 			mask = MXC_CCM_CCGR6_I2C4_MASK;
 			addr = &imx_ccm->CCGR6;
 		} else {
@@ -279,7 +279,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
 	switch (pll) {
 	case PLL_BUS:
-		if (!is_cpu_type(MXC_CPU_MX6UL)) {
+		if (!is_mx6ul()) {
 			if (pfd_num == 3) {
 				/* No PFD3 on PPL2 */
 				return 0;
@@ -379,8 +379,8 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6sl() || is_mx6sx() ||
+	    is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 			return MXC_HCLK; /* OSC 24Mhz */
 	}
@@ -396,8 +396,7 @@ static u32 get_uart_clk(void)
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
 
-	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 			freq = MXC_HCLK;
 	}
@@ -416,8 +415,7 @@ static u32 get_cspi_clk(void)
 	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-	if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
-	    is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 			return MXC_HCLK / (cspi_podf + 1);
 	}
@@ -479,14 +477,13 @@ static u32 get_mmdc_ch0_clk(void)
 
 	u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-	    is_cpu_type(MXC_CPU_MX6SL)) {
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
 		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 			MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 		if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 			per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 				MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
-			if (is_cpu_type(MXC_CPU_MX6SL)) {
+			if (is_mx6sl()) {
 				if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 					freq = MXC_HCLK;
 				else
@@ -618,7 +615,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
 	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-	if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+	if (!is_mx6sx() && !is_mx6ul()) {
 		debug("This chip not support lcd!\n");
 		return;
 	}
@@ -630,7 +627,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 			return;
 	}
 
-	if (is_cpu_type(MXC_CPU_MX6SX)) {
+	if (is_mx6sx()) {
 		reg = readl(&imx_ccm->cscdr2);
 		/* Can't change clocks when clock not from pre-mux */
 		if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
@@ -711,7 +708,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 				MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 				((postd - 1) <<
 				 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
-	} else if (is_cpu_type(MXC_CPU_MX6SX)) {
+	} else if (is_mx6sx()) {
 		/* Setting LCDIF2 for i.MX6SX */
 		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 			return;
@@ -737,7 +734,7 @@ int enable_lcdif_clock(u32 base_addr)
 	u32 reg = 0;
 	u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 
-	if (is_cpu_type(MXC_CPU_MX6SX)) {
+	if (is_mx6sx()) {
 		if ((base_addr != LCDIF1_BASE_ADDR) &&
 		    (base_addr != LCDIF2_BASE_ADDR)) {
 			puts("Wrong LCD interface!\n");
@@ -752,7 +749,7 @@ int enable_lcdif_clock(u32 base_addr)
 			 MXC_CCM_CCGR3_DISP_AXI_MASK) :
 			(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 			 MXC_CCM_CCGR3_DISP_AXI_MASK);
-	} else if (is_cpu_type(MXC_CPU_MX6UL)) {
+	} else if (is_mx6ul()) {
 		if (base_addr != LCDIF1_BASE_ADDR) {
 			puts("Wrong LCD interface!\n");
 			return -EINVAL;
@@ -850,8 +847,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 	} else if (fec_id == 1) {
 		/* Only i.MX6SX/UL support ENET2 */
-		if (!(is_cpu_type(MXC_CPU_MX6SX) ||
-		      is_cpu_type(MXC_CPU_MX6UL)))
+		if (!(is_mx6sx() || is_mx6ul()))
 			return -EINVAL;
 		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -1044,7 +1040,7 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF	0xa
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF	0xb
 
-	if (is_cpu_type(MXC_CPU_MX6SX))
+	if (is_mx6sx())
 		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 	else
 		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
@@ -1228,7 +1224,7 @@ static void disable_ldb_di_clock_sources(void)
 	/* Make sure PFDs are disabled at boot. */
 	reg = readl(&mxc_ccm->analog_pfd_528);
 	/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
-	if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+	if (is_mx6sdl())
 		reg |= 0x80008080;
 	else
 		reg |= 0x80808080;
@@ -1251,7 +1247,7 @@ static void enable_ldb_di_clock_sources(void)
 	int reg;
 
 	reg = readl(&mxc_ccm->analog_pfd_528);
-	if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+	if (is_mx6sdl())
 		reg &= ~(0x80008080);
 	else
 		reg &= ~(0x80808080);
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 1e7ae28..3cc8666 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -888,8 +888,7 @@ void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
-	    !is_cpu_type(MXC_CPU_MX6SL))				  \
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())			  \
 		mmdc1->entry = value;					  \
 	} while (0)
 
@@ -1197,12 +1196,11 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
-	    !is_cpu_type(MXC_CPU_MX6SL))
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+	if (is_mx6dq()) {
 		if (mem_speed > 1066)
 			mem_speed = 1066; /* 1066 MT/s */
 
@@ -1221,7 +1219,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
 	 * up to 528 MHz, so reduce the clock to fit chip specs
 	 */
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+	if (is_mx6dq()) {
 		if (clock > 528)
 			clock = 528; /* 528 MHz */
 	}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index aaa1adb..407f316 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void)
 	val >>= OCOTP_CFG3_SPEED_SHIFT;
 	val &= 0x3;
 
-	if (is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6ul()) {
 		if (val == OCOTP_CFG3_SPEED_528MHZ)
 			return 528000000;
 		else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -138,14 +138,14 @@ u32 get_cpu_speed_grade_hz(void)
 	switch (val) {
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_1P2GHZ:
-		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		if (is_mx6dq())
 			return 1200000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_1GHZ:
 		return 996000000;
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_850MHZ:
-		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		if (is_mx6dq())
 			return 852000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_800MHZ:
@@ -293,7 +293,7 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl())
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
 	else
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -459,8 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 
-	if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && 
-		dev_id == 1) {
+	if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
 		u32 value = readl(&fuse->mac_addr2);
 		mac[0] = value >> 24 ;
 		mac[1] = value >> 16 ;
@@ -524,7 +523,7 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+	if (is_mx6sx() || is_mx6ul())
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
-- 
cgit v0.10.2


From 003f0c7eb2f257eddc5173def53fcb5a137045c2 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:55 +0800
Subject: imx-common: hab: support i.MX6SOLO
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add i.MX6SOLO support for hab function.
The difference between i.MX6SOLO and i.MX6DL is
the number of CPU cores. Besides this, they work
the same.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 8bbcc22..1e4ed7e 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -21,7 +21,8 @@
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	((is_cpu_type(MXC_CPU_MX6DL) ||				\
+	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
 	 (soc_rev() >= CHIP_REV_1_2)) ?				\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)	\
@@ -33,7 +34,8 @@
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	((is_cpu_type(MXC_CPU_MX6DL) ||				\
+	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
 	 (soc_rev() >= CHIP_REV_1_2)) ?				\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)	\
@@ -45,7 +47,8 @@
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	((is_cpu_type(MXC_CPU_MX6DL) ||				\
+	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
 	 (soc_rev() >= CHIP_REV_1_2)) ?				\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)	\
@@ -57,7 +60,8 @@
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	((is_cpu_type(MXC_CPU_MX6DL) ||				\
+	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
 	 (soc_rev() >= CHIP_REV_1_2)) ?				\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY)			\
@@ -69,7 +73,8 @@
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	((is_cpu_type(MXC_CPU_MX6DL) ||				\
+	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
 	 (soc_rev() >= CHIP_REV_1_2)) ?				\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT)			\
-- 
cgit v0.10.2


From 27cd0da41e7c2f10d754efba0d178a5715d12bc2 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:56 +0800
Subject: imx-common: use simpler runtime cpu dection macros
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 1e4ed7e..a980688 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,65 +17,45 @@
 
 #define hab_rvt_report_event_p					\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
-	((is_cpu_type(MXC_CPU_MX6DL) ||				\
-	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)	\
 )
 
 #define hab_rvt_report_status_p					\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
-	((is_cpu_type(MXC_CPU_MX6DL) ||				\
-	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)	\
 )
 
 #define hab_rvt_authenticate_image_p				\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
-	((is_cpu_type(MXC_CPU_MX6DL) ||				\
-	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)	\
 )
 
 #define hab_rvt_entry_p						\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
-	((is_cpu_type(MXC_CPU_MX6DL) ||				\
-	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY)			\
 )
 
 #define hab_rvt_exit_p						\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
-	((is_cpu_type(MXC_CPU_MX6DL) ||				\
-	  is_cpu_type(MXC_CPU_MX6SOLO)) &&			\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT)			\
 )
@@ -429,8 +409,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 			 */
 			/* Check MMU enabled */
 			if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
-				if (is_cpu_type(MXC_CPU_MX6Q) ||
-				    is_cpu_type(MXC_CPU_MX6D)) {
+				if (is_mx6dq()) {
 					/*
 					 * This won't work on Rev 1.0.0 of
 					 * i.MX6Q/D, since their ROM doesn't
@@ -439,10 +418,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 */
 					if (!is_mx6dqp())
 						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
-				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
-					   is_cpu_type(MXC_CPU_MX6SOLO)) {
+				} else if (is_mx6sdl()) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
-				} else if (is_cpu_type(MXC_CPU_MX6SL)) {
+				} else if (is_mx6sl()) {
 					writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
 				}
 			}
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index 15dab1d..3d2ce3a 100644
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,7 +44,7 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr3);
 	writel(0x00000000, &aips2->opacr4);
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+	if (is_mx6sx() || is_mx7()) {
 		/*
 		 * Set all MPROTx to be non-bufferable, trusted for R/W,
 		 * not forced to user-mode.
@@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog1->wmcr);
 	writew(enable, &wdog2->wmcr);
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-			is_soc_type(MXC_SOC_MX7))
+	if (is_mx6sx() || is_mx6ul() || is_mx7())
 		writew(enable, &wdog3->wmcr);
 #ifdef CONFIG_MX7D
 	writew(enable, &wdog4->wmcr);
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 228d5f8..66137d1 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 
 #if defined(CONFIG_MX6QDL)
 	stride = 2;
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq())
 		p += 1;
 #else
 	stride = 1;
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index d174a46..dd9698d 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,7 @@ int setup_sata(void)
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq())
 		return 1;
 
 	ret = enable_sata_clock();
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 92c7218..bea17f2 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
-	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
-	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
-	     is_cpu_type(MXC_CPU_MX6UL))
+	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+	    is_mx6sdl() || is_mx6sx() || is_mx6ul())
 		return 1;
 
 	return 0;
@@ -86,10 +84,7 @@ int timer_init(void)
 		i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
 		/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
-		if (is_cpu_type(MXC_CPU_MX6DL) ||
-		    is_cpu_type(MXC_CPU_MX6SOLO) ||
-		    is_cpu_type(MXC_CPU_MX6SX) ||
-		    is_cpu_type(MXC_CPU_MX6UL)) {
+		if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
 			i |= GPTCR_24MEN;
 
 			/* Produce 3Mhz clock */
-- 
cgit v0.10.2


From e4d79dcaa41a20dfeba602ce9384af5851268825 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:57 +0800
Subject: imx: mx6: ddr: support i.MX6D/QPlus

Support i.MX6D/QPlus.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 3cc8666..f151eec 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1200,7 +1200,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */
-	if (is_mx6dq()) {
+	if (is_mx6dq() || is_mx6dqp()) {
 		if (mem_speed > 1066)
 			mem_speed = 1066; /* 1066 MT/s */
 
@@ -1219,7 +1219,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
 	 * up to 528 MHz, so reduce the clock to fit chip specs
 	 */
-	if (is_mx6dq()) {
+	if (is_mx6dq() || is_mx6dqp()) {
 		if (clock > 528)
 			clock = 528; /* 528 MHz */
 	}
-- 
cgit v0.10.2


From 04cb3c0b0e11cd50593af2330e5ba8f1f11068b3 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:58 +0800
Subject: imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQP

Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we
will get wrong speed grade info i.MX6DQP.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 407f316..88fcfdc 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -138,14 +138,14 @@ u32 get_cpu_speed_grade_hz(void)
 	switch (val) {
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_1P2GHZ:
-		if (is_mx6dq())
+		if (is_mx6dq() || is_mx6dqp())
 			return 1200000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_1GHZ:
 		return 996000000;
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_850MHZ:
-		if (is_mx6dq())
+		if (is_mx6dq() || is_mx6dqp())
 			return 852000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_800MHZ:
-- 
cgit v0.10.2


From b5437a8082b7385f0d2db90e37c2342b1c0fc59f Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:35:59 +0800
Subject: imx-common: hab: support i.MX6DQPlus

Support i.MX6DQPlus, otherwise wrong hab address will be used
for i.MX6QDPlus.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index a980688..6731825 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,6 +17,8 @@
 
 #define hab_rvt_report_event_p					\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -26,6 +28,8 @@
 
 #define hab_rvt_report_status_p					\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -35,6 +39,8 @@
 
 #define hab_rvt_authenticate_image_p				\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -44,6 +50,8 @@
 
 #define hab_rvt_entry_p						\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -53,6 +61,8 @@
 
 #define hab_rvt_exit_p						\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
-- 
cgit v0.10.2


From aff3756104544ed1bb45835db4a7824fece8709e Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:00 +0800
Subject: imx-common: sata: return failure if not i.MX6DQPlus

The i.MX6DQPlus support sata interface, we should not
return failure when CPU is i.MX6DQPlus.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index dd9698d..acf9831 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,7 @@ int setup_sata(void)
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (!is_mx6dq())
+	if (!is_mx6dq() && !is_mx6dqp())
 		return 1;
 
 	ret = enable_sata_clock();
-- 
cgit v0.10.2


From 492d60ac79aba67e8b9e98b251e3996746e58d60 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:01 +0800
Subject: imx-common: timer: support i.MX6DQPlus

To i.MX6DQPlus, osc can be choosed as the source of gpt, so
add i.MX6DQPlus support in gpt_has_clk_source_osc.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index bea17f2..a01590c 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -44,7 +44,7 @@ static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
 	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
-	    is_mx6sdl() || is_mx6sx() || is_mx6ul())
+	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
 		return 1;
 
 	return 0;
-- 
cgit v0.10.2


From 9aa550d2e8e9c6c2a149528d3d2b33870608a860 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:02 +0800
Subject: mtd: nand: mxs: use simpler runtime cpu dection macros

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Scott Wood <oss@buserror.net>

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index b5bbd88..5528d4b 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
 	int max_ecc_strength_supported;
 
 	/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
+	if (is_mx6sx() || is_mx7())
 		max_ecc_strength_supported = 62;
 	else
 		max_ecc_strength_supported = 40;
-- 
cgit v0.10.2


From bff755033133b49eaea38a68fe3284c1a25f2695 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:03 +0800
Subject: ocotp: mxc: use simpler runtime cpu dection macros

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 65ff815..38344e8 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -95,9 +95,9 @@ u32 fuse_bank_physical(int index)
 {
 	u32 phy_index;
 
-	if (is_cpu_type(MXC_CPU_MX6SL)) {
+	if (is_mx6sl()) {
 		phy_index = index;
-	} else if (is_cpu_type(MXC_CPU_MX6UL)) {
+	} else if (is_mx6ul()) {
 		if (index >= 6)
 			phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 		else
-- 
cgit v0.10.2


From 87f9989502763f36b1df94c909cbf05f65633fc4 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:04 +0800
Subject: net: fec_mxc: use simpler runtime cpu dection macros

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3340dd2..360f8e4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -566,7 +566,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 
 
 	/* Do not access reserved register for i.MX6UL */
-	if (!is_cpu_type(MXC_CPU_MX6UL)) {
+	if (!is_mx6ul()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);
-- 
cgit v0.10.2


From 3fd9eb66896768aaa73c26bc5686abac7e058652 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:05 +0800
Subject: block: dwc_ahsata: support i.MX6DQPlus

i.MX6DQPlus support sata interface, so not return failure
when CPU is i.MX6DQPlus.

In this patch, also use simpler runtime cpu dections macros to replace
is_cpu_type.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 6ec52a9..6056fe5 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -563,7 +563,7 @@ int init_sata(int dev)
 	struct ahci_probe_ent *probe_ent = NULL;
 
 #if defined(CONFIG_MX6)
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq() && !is_mx6dqp())
 		return 1;
 #endif
 	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
-- 
cgit v0.10.2


From 83e1394242180f683ce6ba4840f4a5f6a14d2fa0 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 23 May 2016 18:36:06 +0800
Subject: board: mx6sabresd/auto: use simpler runtime cpu dection macros

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c2e9c57..0712f08 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -625,9 +625,9 @@ int board_late_init(void)
 
 	if (is_mx6dqp())
 		setenv("board_rev", "MX6QP");
-	else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	else if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
-	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+	else if (is_mx6sdl())
 		setenv("board_rev", "MX6DL");
 #endif
 
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2319354..54ba36b 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -649,9 +649,9 @@ int board_late_init(void)
 
 	if (is_mx6dqp())
 		setenv("board_rev", "MX6QP");
-	else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	else if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
-	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+	else if (is_mx6sdl())
 		setenv("board_rev", "MX6DL");
 #endif
 
-- 
cgit v0.10.2


From 3061a5766ac34111929bec81b23e59ddf8a8b1e2 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 23 May 2016 08:25:26 -0700
Subject: imx: ventana: config: remove redundant config

remove redundant define that exists in mx6_common.h

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index e11629c..8d689f1 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -52,9 +52,6 @@
 #define CONFIG_DM_THERMAL
 #endif
 
-/* GPIO */
-#define CONFIG_MXC_GPIO
-
 /* Thermal */
 #define CONFIG_IMX_THERMAL
 
-- 
cgit v0.10.2


From a419352daf7a3dd29306d458fd3924e394d3cdc0 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 23 May 2016 08:25:27 -0700
Subject: imx: ventana: gsc: remove dependence on env

remove dependence on getenv() by using global board info struct for model.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 3febd12..4f26bfd 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -11,6 +11,7 @@
 #include <i2c.h>
 #include <linux/ctype.h>
 
+#include "ventana_eeprom.h"
 #include "gsc.h"
 
 /*
@@ -79,7 +80,6 @@ static void read_hwmon(const char *name, uint reg, uint size)
 
 int gsc_info(int verbose)
 {
-	const char *model = getenv("model");
 	unsigned char buf[16];
 
 	i2c_set_bus_num(0);
@@ -112,7 +112,7 @@ int gsc_info(int verbose)
 	read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
 	read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3);
 	read_hwmon("VDD_IO2",  GSC_HWMON_VDD_IO2, 3);
-	switch (model[3]) {
+	switch (ventana_info.model[3]) {
 	case '1': /* GW51xx */
 		read_hwmon("VDD_IO3",  GSC_HWMON_VDD_IO4, 3); /* -C rev */
 		break;
-- 
cgit v0.10.2


From 3c0fd17f61060f3077b0601e0d8353e2b1b6a3df Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 23 May 2016 08:25:28 -0700
Subject: imx: ventana: use EEPROM register for falcon boot mode

NAND+MMC env support costs 12KB in the SPL which is fairly expensive just
for the ability to specify whether or not to boot to uboot or directly
to linux. The Ventana boards have plenty of EEPROM storage so we will use
a byte there to signify if we should boot to the bootloader or to the OS.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
index 9418907..f3f8998 100644
--- a/board/gateworks/gw_ventana/README
+++ b/board/gateworks/gw_ventana/README
@@ -173,13 +173,8 @@ OS load time which defeats the purpose of Falcon mode in the first place.
 The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
 based on the return value of the spl_start_uboot() function. While often
 this can simply be the state of a GPIO based pushbutton or DIP switch, for
-Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if
-set to '1' will choose to boot the OS rather than U-Boot. While the choice
-of adding env support to the SPL adds a little bit of time to the boot
-process as well as (significant really) SPL code space this was deemed most
-flexible as within the large variety of Gateworks Ventana boards not all of
-them have a user pushbutton and that pushbutton may be configured as a hard
-reset per user configuration.
+Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
+set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
 
 To use Falcon mode it is required that you first 'prepare' the 'args' data
 that is stored on your boot medium along with the kernel (which can be any
@@ -235,8 +230,8 @@ using rootfs (ubi), kernel (uImage), and dtb from the network:
  # flash args (at 17MB)
  Ventana > nand erase.part args && nand write 18000000 args 100000
 
- # set boot_os env var to enable booting to Linux
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
 
 Be sure to adjust 'bootargs' above to your OS needs (this will be different
 for various distros such as OpenWrt, Yocto, Android, etc). You can use the
@@ -309,8 +304,8 @@ out in U-Boot and use the following to enable Falcon mode:
  # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
  Ventana > mmc write 18000000 0x800 0x800
 
- # set boot_os to enable falcon mode
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
 
 Be sure to adjust 'bootargs' above to your OS needs (this will be different
 for various distros such as OpenWrt, Yocto, Android, etc). You can use the
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 0a6ad47..ed42b86 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -15,6 +15,7 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <environment.h>
+#include <i2c.h>
 #include <spl.h>
 
 #include "gsc.h"
@@ -560,7 +561,7 @@ void spl_board_init(void)
 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 int spl_start_uboot(void)
 {
-	int ret = 1;
+	unsigned char ret = 1;
 
 	debug("%s\n", __func__);
 #ifdef CONFIG_SPL_ENV_SUPPORT
@@ -569,6 +570,10 @@ int spl_start_uboot(void)
 	debug("boot_os=%s\n", getenv("boot_os"));
 	if (getenv_yesno("boot_os") == 1)
 		ret = 0;
+#else
+	/* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+	i2c_set_bus_num(0);
+	gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 #endif
 	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
 	return ret;
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 8d689f1..c8d3cb8 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -18,7 +18,6 @@
 /* Falcon Mode */
 #define CONFIG_CMD_SPL
 #define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
 #define CONFIG_CMD_SPL_WRITE_SIZE	(128 * SZ_1K)
 
-- 
cgit v0.10.2


From a0eb8c9b91348966f7ae8748b4ab3febae792a76 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 23 May 2016 08:25:29 -0700
Subject: imx: ventana: remove SPL_EXT_SUPPORT

Remove SPL_EXT_SUPPORT to resolve build issue. It may be useful to bring
it back in the future after comparing its merits to storing the args/kernel
in fixed raw locations.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index c8d3cb8..874bb04 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -32,6 +32,7 @@
 
 #include "imx6_spl.h"                  /* common IMX6 SPL configuration */
 #include "mx6_common.h"
+#undef CONFIG_SPL_EXT_SUPPORT
 
 #define CONFIG_MACH_TYPE	4520   /* Gateworks Ventana Platform */
 
-- 
cgit v0.10.2


From e453794f87436c7788ba763f90e0e905ace8b7f7 Mon Sep 17 00:00:00 2001
From: Damien Riegel <damien.riegel@savoirfairelinux.com>
Date: Thu, 21 Apr 2016 17:34:02 -0400
Subject: ts4800: update environment to boot with device tree

This commit updates the environment variables to be able to boot with a
device tree. The expected partition layout on the SD card is:
 - partition 1: type 0xDA, contains u-boot.bin
 - partition 2: type 0xC (fat), contains zImage and device tree
 - partition 3: type 0x83, root filesystem.

Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>

diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index aa0605f..0392863 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -96,19 +96,28 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"image=uImage\0" \
+	"image=zImage\0" \
+	"fdt_file=imx51-ts4800.dtb\0" \
+	"fdt_addr=0x90fe0000\0" \
 	"mmcdev=0\0" \
-	"mmcpart=1\0" \
-	"mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcargs=setenv bootargs root=${mmcroot}\0" \
 	"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs addtty; " \
-                "bootm; "
+		"if run loadfdt; then " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"echo ERR: cannot load FDT; " \
+		"fi; "
+
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
-- 
cgit v0.10.2


From e96b6ee7bd6ad29d47d50ca69a731afa3c66f174 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Date: Thu, 21 Apr 2016 13:37:04 -0400
Subject: ts4800: add CONFIG_SYS_FSL_ERRATUM_ESDHC_A001

This commit fixes the MMC data transactions timeout problem on the
TS4800.

The changes introduced in the commit e978a31 on the timeout calculation
for the MMC data transactions has revealed there is something wrong with
the timeout setting of the eSDHC controller used in the IMX51.

The IMX51 seems to be concerned by this erratum and without this change
the MMC driver is unable to do any transactions.

Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 0392863..0db5ab5 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -62,6 +62,8 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	MMC_SDHC1_BASE_ADDR
 
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
 #define CONFIG_MMC
 
 #define CONFIG_GENERIC_MMC
-- 
cgit v0.10.2


From 83c05515d8b428b9dd1ce6e7031048d4c1971152 Mon Sep 17 00:00:00 2001
From: Kevin Smith <kevin.smith@elecsyscorp.com>
Date: Thu, 31 Mar 2016 19:33:12 +0000
Subject: net: Remove unused mv88e61xx switch driver

No boards are using this driver.  Remove in preparation for a new
driver with integrated PHY support.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>

diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
deleted file mode 100644
index 302abe8..0000000
--- a/drivers/net/phy/mv88e61xx.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include "mv88e61xx.h"
-
-/*
- * Uncomment either of the following line for local debug control;
- * otherwise global debug control will apply.
- */
-
-/* #undef DEBUG */
-/* #define DEBUG */
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-/* Chip Address mode
- * The Switch support two modes of operation
- * 1. single chip mode and
- * 2. Multi-chip mode
- * Refer section 9.2 &9.3 in chip datasheet-02 for more details
- *
- * By default single chip mode is configured
- * multichip mode operation can be configured in board header
- */
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
-{
-	u16 reg = 0;
-	u32 timeout = MV88E61XX_PHY_TIMEOUT;
-
-	/* Poll till SMIBusy bit is clear */
-	do {
-		miiphy_read(name, devaddr, 0x0, &reg);
-		if (timeout-- == 0) {
-			printf("SMI busy timeout\n");
-			return -1;
-		}
-	} while (reg & (1 << 15));
-	return 0;
-}
-
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data)
-{
-	u16 mii_dev_addr;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
-		printf("Error..could not read PHY dev address\n");
-		return;
-	}
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Write data to Switch indirect data register */
-	miiphy_write(name, mii_dev_addr, 0x1, data);
-	/* Write command to Switch indirect command register (write) */
-	miiphy_write(name, mii_dev_addr, 0x0,
-		     reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
-									 15));
-}
-
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data)
-{
-	u16 mii_dev_addr;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
-		printf("Error..could not read PHY dev address\n");
-		return;
-	}
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Write command to Switch indirect command register (read) */
-	miiphy_write(name, mii_dev_addr, 0x0,
-		     reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
-									 15));
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Read data from Switch indirect data register */
-	miiphy_read(name, mii_dev_addr, 0x1, data);
-}
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-/*
- * Convenience macros for switch device/port reads/writes
- * These macros output valid 'mv88e61xx' U_BOOT_CMDs
- */
-
-#ifndef DEBUG
-#define WR_SWITCH_REG wr_switch_reg
-#define RD_SWITCH_REG rd_switch_reg
-#define WR_SWITCH_PORT_REG(n, p, r, d) \
-	WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#define RD_SWITCH_PORT_REG(n, p, r, d) \
-	RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#else
-static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
-{
-	printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
-		name, dev_adr, reg_ofs, data);
-	wr_switch_reg(name, dev_adr, reg_ofs, data);
-}
-static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
-{
-	rd_switch_reg(name, dev_adr, reg_ofs, data);
-	printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
-		name, dev_adr, reg_ofs, *data);
-}
-static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-	u16 data)
-{
-	printf("mv88e61xx %s port %02x reg %02x write %04x\n",
-		name, prt_adr, reg_ofs, data);
-	wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
-}
-static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-	u16 *data)
-{
-	rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
-	printf("mv88e61xx %s port %02x reg %02x read %04x\n",
-		name, prt_adr, reg_ofs, *data);
-}
-#endif
-
-/*
- * Local functions to read/write registers on the switch PHYs.
- * NOTE! This goes through switch, not direct miiphy, writes and reads!
- */
-
-/*
- * Make sure SMIBusy bit cleared before another
- * SMI operation can take place
- */
-static int mv88e61xx_busychk(char *name)
-{
-	u16 reg = 0;
-	u32 timeout = MV88E61XX_PHY_TIMEOUT;
-	do {
-		rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
-		       MV88E61XX_PHY_CMD, &reg);
-		if (timeout-- == 0) {
-			printf("SMI busy timeout\n");
-			return -1;
-		}
-	} while (reg & 1 << 15);	/* busy mask */
-	return 0;
-}
-
-static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
-	u32 reg, u16 data)
-{
-	/* write switch data reg then cmd reg then check completion */
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
-		data);
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
-		(MV88E61XX_PHY_WRITE_CMD | (phy << 5)  | reg));
-	return mv88e61xx_busychk(name);
-}
-
-static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
-	u32 reg, u16 *data)
-{
-	/* write switch cmd reg, check for completion */
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
-		(MV88E61XX_PHY_READ_CMD | (phy << 5)  | reg));
-	if (mv88e61xx_busychk(name))
-		return -1;
-	/* read switch data reg and return success */
-	rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
-	return 0;
-}
-
-/*
- * Convenience macros for switch PHY reads/writes
- */
-
-#ifndef DEBUG
-#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
-#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
-#else
-static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data)
-{
-	int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
-	if (r)
-		printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
-			name, phy_adr, reg_ofs);
-	else
-		printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
-			name, phy_adr, reg_ofs, data);
-	return r;
-}
-static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data)
-{
-	int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
-	if (r)
-		printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
-			name, phy_adr, reg_ofs);
-	else
-		printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
-			name, phy_adr, reg_ofs, *data);
-	return r;
-}
-#endif
-
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
-{
-	u32 prt;
-	u16 reg;
-	char *name = swconfig->name;
-	u32 port_mask = swconfig->ports_enabled;
-
-	/* apply internal vlan config */
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		/* only for enabled ports */
-		if ((1 << prt) & port_mask) {
-			/* take vlan map from swconfig */
-			u8 vlanmap = swconfig->vlancfg[prt];
-			/* remove disabled ports from vlan map */
-			vlanmap &= swconfig->ports_enabled;
-			/* apply vlan map to port */
-			RD_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VMAP_REG, &reg);
-			reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
-			reg |= vlanmap;
-			WR_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VMAP_REG, reg);
-		}
-	}
-}
-
-/*
- * Power up the specified port and reset PHY
- */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
-{
-	char *name = swconfig->name;
-
-	/* Write Copper Specific control reg1 (0x10) for-
-	 * Enable Phy power up
-	 * Energy Detect on (sense&Xmit NLP Periodically
-	 * reset other settings default
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
-		return -1;
-
-	/* Write PHY ctrl reg (0x0) to apply
-	 * Phy reset (set bit 15 low)
-	 * reset other default values
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
-		return -1;
-
-	return 0;
-}
-
-/*
- * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
- * is set to "On-1000Mb/s Link, Off Else"
- * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
- *
- * This is optional settings may be needed on some boards
- * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
- * Link status
- */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
-{
-	char *name = swconfig->name;
-
-	if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
-		return 0;
-
-	/* set page address to 3 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
-		return -1;
-
-	/*
-	 * set LED Func Ctrl reg
-	 * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
-		return -1;
-
-	/* set page address to 0 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
-		return -1;
-
-	return 0;
-}
-
-/*
- * Reverse Transmit polarity for Media Dependent Interface
- * Pins (MDIP) bits in Copper Specific Control Register 3
- * (Page 0, Reg 20 for each phy (except cpu port)
- * Reference: Section 1.1 Switch datasheet-3
- *
- * This is optional settings may be needed on some boards
- * for PHY<->magnetics h/w tuning
- */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
-{
-	char *name = swconfig->name;
-
-	if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
-		return 0;
-
-	/*Reverse MDIP/N[3:0] bits */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
-		return -1;
-
-	return 0;
-}
-
-/*
- * Marvell 88E61XX Switch initialization
- */
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
-{
-	u32 prt;
-	u16 reg;
-	char *idstr;
-	char *name = swconfig->name;
-	int time;
-
-	if (miiphy_set_current_dev(name)) {
-		printf("%s failed\n", __FUNCTION__);
-		return -1;
-	}
-
-	if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
-		swconfig->cpuport = (1 << 5);
-		printf("Invalid cpu port config, using default port5\n");
-	}
-
-	RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg);
-	switch (reg &= 0xfff0) {
-	case 0x1610:
-		idstr = "88E6161";
-		break;
-	case 0x1650:
-		idstr = "88E6165";
-		break;
-	case 0x1210:
-		idstr = "88E6123";
-		/* ports 2,3,4 not available */
-		swconfig->ports_enabled &= 0x023;
-		break;
-	default:
-		/* Could not detect switch id */
-		idstr = "88E61??";
-		break;
-	}
-
-	/* be sure all ports are disabled */
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg);
-		reg &= ~0x3;
-		WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
-	}
-
-	/* wait 2 ms for queues to drain */
-	udelay(2000);
-
-	/* reset switch */
-	RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, &reg);
-	reg |= 0x8000;
-	WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
-
-	/* wait up to 1 second for switch reset complete */
-	for (time = 1000; time; time--) {
-		RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
-			&reg);
-		if ((reg & 0xc800) == 0xc800)
-			break;
-		udelay(1000);
-	}
-	if (!time)
-		return -1;
-
-	/* Port based VLANs configuration */
-	mv88e61xx_port_vlan_config(swconfig);
-
-	if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
-		/*
-		 * Enable RGMII delay on Tx and Rx for CPU port
-		 * Ref: sec 9.5 of chip datasheet-02
-		 */
-		/*Force port link down */
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
-		/* configure port RGMII delay */
-		WR_SWITCH_PORT_REG(name, 4,
-			MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
-		RD_SWITCH_PORT_REG(name, 5,
-			MV88E61XX_RGMII_TIMECTRL_REG, &reg);
-		WR_SWITCH_PORT_REG(name, 5,
-			MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
-		WR_SWITCH_PORT_REG(name, 4,
-			MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
-		/* Force port to RGMII FDX 1000Base then up */
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
-	}
-
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-
-		/* configure port's PHY */
-		if (!((1 << prt) & swconfig->cpuport)) {
-			/* port 4 has phy 6, not 4 */
-			int phy = (prt == 4) ? 6 : prt;
-			if (mv88361xx_powerup(swconfig, phy))
-				return -1;
-			if (mv88361xx_reverse_mdipn(swconfig, phy))
-				return -1;
-			if (mv88361xx_led_init(swconfig, phy))
-				return -1;
-		}
-
-		/* set port VID to port+1 except for cpu port */
-		if (!((1 << prt) & swconfig->cpuport)) {
-			RD_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VID_REG, &reg);
-			WR_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VID_REG,
-				(reg & ~1023) | (prt+1));
-		}
-
-		/*Program port state */
-		RD_SWITCH_PORT_REG(name, prt,
-			MV88E61XX_PRT_CTRL_REG, &reg);
-		WR_SWITCH_PORT_REG(name, prt,
-			MV88E61XX_PRT_CTRL_REG,
-			reg | (swconfig->portstate & 0x03));
-
-	}
-
-	printf("%s Initialized on %s\n", idstr, name);
-	return 0;
-}
-
-#ifdef CONFIG_MV88E61XX_CMD
-static int
-do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char *name, *endp;
-	int write = 0;
-	enum { dev, prt, phy } target = dev;
-	u32 addrlo, addrhi, addr;
-	u32 reglo, reghi, reg;
-	u16 data, rdata;
-
-	if (argc < 7)
-		return -1;
-
-	name = argv[1];
-
-	if (strcmp(argv[2], "phy") == 0)
-		target = phy;
-	else if (strcmp(argv[2], "port") == 0)
-		target = prt;
-	else if (strcmp(argv[2], "dev") != 0)
-		return 1;
-
-	addrlo = simple_strtoul(argv[3], &endp, 16);
-
-	if (!*endp) {
-		addrhi = addrlo;
-	} else {
-		while (*endp < '0' || *endp > '9')
-			endp++;
-		addrhi = simple_strtoul(endp, NULL, 16);
-	}
-
-	reglo = simple_strtoul(argv[5], &endp, 16);
-	if (!*endp) {
-		reghi = reglo;
-	} else {
-		while (*endp < '0' || *endp > '9')
-			endp++;
-		reghi = simple_strtoul(endp, NULL, 16);
-	}
-
-	if (strcmp(argv[6], "write") == 0)
-		write = 1;
-	else if (strcmp(argv[6], "read") != 0)
-		return 1;
-
-	data = simple_strtoul(argv[7], NULL, 16);
-
-	for (addr = addrlo; addr <= addrhi; addr++) {
-		for (reg = reglo; reg <= reghi; reg++) {
-			if (write) {
-				if (target == phy)
-					mv88e61xx_switch_miiphy_write(
-						name, addr, reg, data);
-				else if (target == prt)
-					wr_switch_reg(name,
-						addr+MV88E61XX_PRT_OFST,
-						reg, data);
-				else
-					wr_switch_reg(name, addr, reg, data);
-			} else {
-				if (target == phy)
-					mv88e61xx_switch_miiphy_read(
-						name, addr, reg, &rdata);
-				else if (target == prt)
-					rd_switch_reg(name,
-						addr+MV88E61XX_PRT_OFST,
-						reg, &rdata);
-				else
-					rd_switch_reg(name, addr, reg, &rdata);
-				printf("%s %s %s %02x %s %02x %s %04x\n",
-					argv[0], argv[1], argv[2], addr,
-					argv[4], reg, argv[6], rdata);
-				if (write && argc == 7 && rdata != data)
-					return 1;
-			}
-		}
-	}
-	return 0;
-}
-
-U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
-	"Read or write mv88e61xx switch registers",
-	"<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
-	"<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
-	"    - read/write switch device, port or phy at (addr,reg)\n"
-	"      addr=0..0x1C for dev, 0..5 for port or phy.\n"
-	"      reg=0..0x1F.\n"
-	"      data=0..0xFFFF (tested if present against actual read).\n"
-	"      All numeric parameters are assumed to be hex.\n"
-	"      <addr> and <<reg> arguments can be ranges (x..y)"
-);
-#endif /* CONFIG_MV88E61XX_CMD */
diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h
deleted file mode 100644
index 9c62e4a..0000000
--- a/drivers/net/phy/mv88e61xx.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _MV88E61XX_H
-#define _MV88E61XX_H
-
-#include <miiphy.h>
-
-#define MV88E61XX_CPU_PORT		0x5
-
-#define MV88E61XX_PHY_TIMEOUT		100000
-
-/* port dev-addr (= port + 0x10) */
-#define MV88E61XX_PRT_OFST		0x10
-/* port registers */
-#define MV88E61XX_PCS_CTRL_REG		0x1
-#define MV88E61XX_PRT_CTRL_REG		0x4
-#define MV88E61XX_PRT_VMAP_REG		0x6
-#define MV88E61XX_PRT_VID_REG		0x7
-#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
-
-/* global registers dev-addr */
-#define MV88E61XX_GLBREG_DEVADR	0x1B
-/* global registers */
-#define MV88E61XX_SGSR			0x00
-#define MV88E61XX_SGCR			0x04
-
-/* global 2 registers dev-addr */
-#define MV88E61XX_GLB2REG_DEVADR	0x1C
-/* global 2 registers */
-#define MV88E61XX_PHY_CMD		0x18
-#define MV88E61XX_PHY_DATA		0x19
-/* global 2 phy commands */
-#define MV88E61XX_PHY_WRITE_CMD		0x9400
-#define MV88E61XX_PHY_READ_CMD		0x9800
-
-#define MV88E61XX_BUSY_OFST		15
-#define MV88E61XX_MODE_OFST		12
-#define MV88E61XX_OP_OFST		10
-#define MV88E61XX_ADDR_OFST		5
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data);
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data);
-#define wr_switch_reg mv88e61xx_switch_write
-#define rd_switch_reg mv88e61xx_switch_read
-#else
-/* switch appears a s simple PHY and can thus use miiphy */
-#define wr_switch_reg miiphy_write
-#define rd_switch_reg miiphy_read
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-#endif /* _MV88E61XX_H */
diff --git a/include/netdev.h b/include/netdev.h
index 244f23f..7a211bc 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -134,64 +134,6 @@ static inline int pci_eth_init(bd_t *bis)
 	return num;
 }
 
-/*
- * Boards with mv88e61xx switch can use this by defining
- * CONFIG_MV88E61XX_SWITCH in respective board configheader file
- * the stuct and enums here are used to specify switch configuration params
- */
-#if defined(CONFIG_MV88E61XX_SWITCH)
-
-/* constants for any 88E61xx switch */
-#define MV88E61XX_MAX_PORTS_NUM	6
-
-enum mv88e61xx_cfg_mdip {
-	MV88E61XX_MDIP_NOCHANGE,
-	MV88E61XX_MDIP_REVERSE
-};
-
-enum mv88e61xx_cfg_ledinit {
-	MV88E61XX_LED_INIT_DIS,
-	MV88E61XX_LED_INIT_EN
-};
-
-enum mv88e61xx_cfg_rgmiid {
-	MV88E61XX_RGMII_DELAY_DIS,
-	MV88E61XX_RGMII_DELAY_EN
-};
-
-enum mv88e61xx_cfg_prtstt {
-	MV88E61XX_PORTSTT_DISABLED,
-	MV88E61XX_PORTSTT_BLOCKING,
-	MV88E61XX_PORTSTT_LEARNING,
-	MV88E61XX_PORTSTT_FORWARDING
-};
-
-struct mv88e61xx_config {
-	char *name;
-	u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
-	enum mv88e61xx_cfg_rgmiid rgmii_delay;
-	enum mv88e61xx_cfg_prtstt portstate;
-	enum mv88e61xx_cfg_ledinit led_init;
-	enum mv88e61xx_cfg_mdip mdip;
-	u32 ports_enabled;
-	u8 cpuport;
-};
-
-/*
- * Common mappings for Internal VLANs
- * These mappings consider that all ports are useable; the driver
- * will mask inexistent/unused ports.
- */
-
-/* Switch mode : routes any port to any port */
-#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
-
-/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
-#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
-
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
-#endif /* CONFIG_MV88E61XX_SWITCH */
-
 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
 #ifdef CONFIG_PHYLIB
 struct phy_device;
-- 
cgit v0.10.2


From 24ae3961f811ee79e6c98474e21e07f8ce222dfc Mon Sep 17 00:00:00 2001
From: Kevin Smith <kevin.smith@elecsyscorp.com>
Date: Thu, 31 Mar 2016 19:33:12 +0000
Subject: net: phy: Add PHY driver for mv88e61xx switches

The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot.  This is a complete
rework to support this device as a PHY.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
new file mode 100644
index 0000000..74d5609
--- /dev/null
+++ b/drivers/net/phy/mv88e61xx.c
@@ -0,0 +1,1017 @@
+/*
+ * (C) Copyright 2015
+ * Elecsys Corporation <www.elecsyscorp.com>
+ * Kevin Smith <kevin.smith@elecsyscorp.com>
+ *
+ * Original driver:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * PHY driver for mv88e61xx ethernet switches.
+ *
+ * This driver configures the mv88e61xx for basic use as a PHY.  The switch
+ * supports a VLAN configuration that determines how traffic will be routed
+ * between the ports.  This driver uses a simple configuration that routes
+ * traffic from each PHY port only to the CPU port, and from the CPU port to
+ * any PHY port.
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_MV88E61XX_PHY_PORTS bitmask.  Setting bit 0 will activate port 0, bit
+ * 1 activates port 1, etc.  Do not set the bit for the port the CPU is
+ * connected to unless it is connected over a PHY interface (not MII).
+ *
+ * This driver was written for and tested on the mv88e6176 with an SGMII
+ * connection.  Other configurations should be supported, but some additions or
+ * changes may be required.
+ */
+
+#include <common.h>
+
+#include <bitfield.h>
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#define PHY_AUTONEGOTIATE_TIMEOUT	5000
+
+#define PORT_COUNT			7
+#define PORT_MASK			((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p)			(p)
+#define DEVADDR_PORT(p)			(0x10 + (p))
+#define DEVADDR_SERDES			0x0F
+#define DEVADDR_GLOBAL_1		0x1B
+#define DEVADDR_GLOBAL_2		0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG			0x00
+#define SMI_DATA_REG			0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS			0x00
+#define GLOBAL1_CTRL			0x04
+#define GLOBAL1_MON_CTRL		0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD		0x18
+#define GLOBAL2_REG_PHY_DATA		0x19
+
+/* Port registers */
+#define PORT_REG_STATUS			0x00
+#define PORT_REG_PHYS_CTRL		0x01
+#define PORT_REG_SWITCH_ID		0x03
+#define PORT_REG_CTRL			0x04
+#define PORT_REG_VLAN_MAP		0x06
+#define PORT_REG_VLAN_ID		0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1			0x10
+#define PHY_REG_STATUS1			0x11
+#define PHY_REG_PAGE			0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1		0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER			0
+#define PHY_PAGE_SERDES			1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET		BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT	4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH	4
+
+#define PORT_REG_STATUS_LINK		BIT(11)
+#define PORT_REG_STATUS_DUPLEX		BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT	8
+#define PORT_REG_STATUS_SPEED_WIDTH	2
+#define PORT_REG_STATUS_SPEED_10	0
+#define PORT_REG_STATUS_SPEED_100	1
+#define PORT_REG_STATUS_SPEED_1000	2
+
+#define PORT_REG_STATUS_CMODE_MASK		0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X		0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X	0x9
+#define PORT_REG_STATUS_CMODE_SGMII		0xa
+
+#define PORT_REG_PHYS_CTRL_LINK_VALUE	BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE	BIT(4)
+
+#define PORT_REG_CTRL_PSTATE_SHIFT	0
+#define PORT_REG_CTRL_PSTATE_WIDTH	2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT	0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH	12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT	0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH	11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK	BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT	8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH	2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED	0
+#define PORT_REG_CTRL_PSTATE_FORWARD	3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF	0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY	2
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT	3
+
+/* PHY Status Register */
+#define PHY_REG_STATUS1_SPEED		0xc000
+#define PHY_REG_STATUS1_GBIT		0x8000
+#define PHY_REG_STATUS1_100		0x4000
+#define PHY_REG_STATUS1_DUPLEX		0x2000
+#define PHY_REG_STATUS1_SPDDONE		0x0800
+#define PHY_REG_STATUS1_LINK		0x0400
+#define PHY_REG_STATUS1_ENERGY		0x0010
+
+/*
+ * Macros for building commands for indirect addressing modes.  These are valid
+ * for both the indirect multichip addressing mode and the PHY indirection
+ * required for the writes to any PHY register.
+ */
+#define SMI_BUSY			BIT(15)
+#define SMI_CMD_CLAUSE_22		BIT(12)
+#define SMI_CMD_CLAUSE_22_OP_READ	(2 << 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE	(1 << 10)
+
+#define SMI_CMD_READ			(SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+					 SMI_CMD_CLAUSE_22_OP_READ)
+#define SMI_CMD_WRITE			(SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+					 SMI_CMD_CLAUSE_22_OP_WRITE)
+
+#define SMI_CMD_ADDR_SHIFT		5
+#define SMI_CMD_ADDR_WIDTH		5
+#define SMI_CMD_REG_SHIFT		0
+#define SMI_CMD_REG_WIDTH		5
+
+/* Check for required macros */
+#ifndef CONFIG_MV88E61XX_PHY_PORTS
+#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
+	to activate
+#endif
+#ifndef CONFIG_MV88E61XX_CPU_PORT
+#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
+#endif
+
+/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6172		0x1720
+#define PORT_SWITCH_ID_6176		0x1760
+#define PORT_SWITCH_ID_6240		0x2400
+#define PORT_SWITCH_ID_6352		0x3520
+
+struct mv88e61xx_phy_priv {
+	struct mii_dev *mdio_bus;
+	int smi_addr;
+	int id;
+};
+
+static inline int smi_cmd(int cmd, int addr, int reg)
+{
+	cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
+			       addr);
+	cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
+	return cmd;
+}
+
+static inline int smi_cmd_read(int addr, int reg)
+{
+	return smi_cmd(SMI_CMD_READ, addr, reg);
+}
+
+static inline int smi_cmd_write(int addr, int reg)
+{
+	return smi_cmd(SMI_CMD_WRITE, addr, reg);
+}
+
+__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	return 0;
+}
+
+/* Wait for the current SMI indirect command to complete */
+static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
+{
+	int val;
+	u32 timeout = 100;
+
+	do {
+		val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
+		if (val >= 0 && (val & SMI_BUSY) == 0)
+			return 0;
+
+		mdelay(1);
+	} while (--timeout);
+
+	puts("SMI busy timeout\n");
+	return -ETIMEDOUT;
+}
+
+/*
+ * The mv88e61xx has three types of addresses: the smi bus address, the device
+ * address, and the register address.  The smi bus address distinguishes it on
+ * the smi bus from other PHYs or switches.  The device address determines
+ * which on-chip register set you are reading/writing (the various PHYs, their
+ * associated ports, or global configuration registers).  The register address
+ * is the offset of the register you are reading/writing.
+ *
+ * When the mv88e61xx is hardware configured to have address zero, it behaves in
+ * single-chip addressing mode, where it responds to all SMI addresses, using
+ * the smi address as its device address.  This obviously only works when this
+ * is the only chip on the SMI bus.  This allows the driver to access device
+ * registers without using indirection.  When the chip is configured to a
+ * non-zero address, it only responds to that SMI address and requires indirect
+ * writes to access the different device addresses.
+ */
+static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
+{
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+	struct mii_dev *mdio_bus = priv->mdio_bus;
+	int smi_addr = priv->smi_addr;
+	int res;
+
+	/* In single-chip mode, the device can be addressed directly */
+	if (smi_addr == 0)
+		return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
+
+	/* Wait for the bus to become free */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Issue the read command */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+			 smi_cmd_read(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for the read command to complete */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Read the data */
+	res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
+	if (res < 0)
+		return res;
+
+	return bitfield_extract(res, 0, 16);
+}
+
+/* See the comment above mv88e61xx_reg_read */
+static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
+			       u16 val)
+{
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+	struct mii_dev *mdio_bus = priv->mdio_bus;
+	int smi_addr = priv->smi_addr;
+	int res;
+
+	/* In single-chip mode, the device can be addressed directly */
+	if (smi_addr == 0) {
+		return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
+				val);
+	}
+
+	/* Wait for the bus to become free */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Set the data to write */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
+				SMI_DATA_REG, val);
+	if (res < 0)
+		return res;
+
+	/* Issue the write command */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+				smi_cmd_write(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for the write command to complete */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_wait(struct phy_device *phydev)
+{
+	int val;
+	u32 timeout = 100;
+
+	do {
+		val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+					 GLOBAL2_REG_PHY_CMD);
+		if (val >= 0 && (val & SMI_BUSY) == 0)
+			return 0;
+
+		mdelay(1);
+	} while (--timeout);
+
+	return -ETIMEDOUT;
+}
+
+static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
+		int devad, int reg)
+{
+	struct phy_device *phydev;
+	int res;
+
+	phydev = (struct phy_device *)smi_wrapper->priv;
+
+	/* Issue command to read */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_CMD,
+				  smi_cmd_read(dev, reg));
+
+	/* Wait for data to be read */
+	res = mv88e61xx_phy_wait(phydev);
+	if (res < 0)
+		return res;
+
+	/* Read retrieved data */
+	return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_DATA);
+}
+
+static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
+		int devad, int reg, u16 data)
+{
+	struct phy_device *phydev;
+	int res;
+
+	phydev = (struct phy_device *)smi_wrapper->priv;
+
+	/* Set the data to write */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_DATA, data);
+	if (res < 0)
+		return res;
+	/* Issue the write command */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_CMD,
+				  smi_cmd_write(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for command to complete */
+	return mv88e61xx_phy_wait(phydev);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
+{
+	return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
+					   MDIO_DEVAD_NONE, reg);
+}
+
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
+		int reg, u16 val)
+{
+	return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
+					    MDIO_DEVAD_NONE, reg, val);
+}
+
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
+{
+	return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
+}
+
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
+								u16 val)
+{
+	return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
+}
+
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
+{
+	return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
+}
+
+static int mv88e61xx_get_switch_id(struct phy_device *phydev)
+{
+	int res;
+
+	res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
+	if (res < 0)
+		return res;
+	return res & 0xfff0;
+}
+
+static bool mv88e61xx_6352_family(struct phy_device *phydev)
+{
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+
+	switch (priv->id) {
+	case PORT_SWITCH_ID_6172:
+	case PORT_SWITCH_ID_6176:
+	case PORT_SWITCH_ID_6240:
+	case PORT_SWITCH_ID_6352:
+		return true;
+	}
+	return false;
+}
+
+static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
+{
+	int res;
+
+	res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+	if (res < 0)
+		return res;
+	return res & PORT_REG_STATUS_CMODE_MASK;
+}
+
+static int mv88e61xx_parse_status(struct phy_device *phydev)
+{
+	unsigned int speed;
+	unsigned int mii_reg;
+
+	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
+
+	if ((mii_reg & PHY_REG_STATUS1_LINK) &&
+	    !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+		int i = 0;
+
+		puts("Waiting for PHY realtime link");
+		while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+			/* Timeout reached ? */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts(" TIMEOUT !\n");
+				phydev->link = 0;
+				break;
+			}
+
+			if ((i++ % 1000) == 0)
+				putc('.');
+			udelay(1000);
+			mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+					PHY_REG_STATUS1);
+		}
+		puts(" done\n");
+		udelay(500000);	/* another 500 ms (results in faster booting) */
+	} else {
+		if (mii_reg & PHY_REG_STATUS1_LINK)
+			phydev->link = 1;
+		else
+			phydev->link = 0;
+	}
+
+	if (mii_reg & PHY_REG_STATUS1_DUPLEX)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
+
+	speed = mii_reg & PHY_REG_STATUS1_SPEED;
+
+	switch (speed) {
+	case PHY_REG_STATUS1_GBIT:
+		phydev->speed = SPEED_1000;
+		break;
+	case PHY_REG_STATUS1_100:
+		phydev->speed = SPEED_100;
+		break;
+	default:
+		phydev->speed = SPEED_10;
+		break;
+	}
+
+	return 0;
+}
+
+static int mv88e61xx_switch_reset(struct phy_device *phydev)
+{
+	int time;
+	int val;
+	u8 port;
+
+	/* Disable all ports */
+	for (port = 0; port < PORT_COUNT; port++) {
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+		if (val < 0)
+			return val;
+		val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+				       PORT_REG_CTRL_PSTATE_WIDTH,
+				       PORT_REG_CTRL_PSTATE_DISABLED);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+		if (val < 0)
+			return val;
+	}
+
+	/* Wait 2 ms for queues to drain */
+	udelay(2000);
+
+	/* Reset switch */
+	val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
+	if (val < 0)
+		return val;
+	val |= GLOBAL1_CTRL_SWRESET;
+	val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+				     GLOBAL1_CTRL, val);
+	if (val < 0)
+		return val;
+
+	/* Wait up to 1 second for switch reset complete */
+	for (time = 1000; time; time--) {
+		val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
+					    GLOBAL1_CTRL);
+		if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
+			break;
+		udelay(1000);
+	}
+	if (!time)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int mv88e61xx_serdes_init(struct phy_device *phydev)
+{
+	int val;
+
+	val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
+	if (val < 0)
+		return val;
+
+	/* Power up serdes module */
+	val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
+	if (val < 0)
+		return val;
+	val &= ~(BMCR_PDOWN);
+	val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
+{
+	int val;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+			       PORT_REG_CTRL_PSTATE_WIDTH,
+			       PORT_REG_CTRL_PSTATE_FORWARD);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
+							u8 mask)
+{
+	int val;
+
+	/* Set VID to port number plus one */
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
+			       PORT_REG_VLAN_ID_DEF_VID_WIDTH,
+			       port + 1);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
+	if (val < 0)
+		return val;
+
+	/* Set VID mask */
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
+			       PORT_REG_VLAN_MAP_TABLE_WIDTH,
+			       mask);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
+{
+	int res;
+	int val;
+	bool forced = false;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+	if (val < 0)
+		return val;
+	if (!(val & PORT_REG_STATUS_LINK)) {
+		/* Temporarily force link to read port configuration */
+		u32 timeout = 100;
+		forced = true;
+
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+		if (val < 0)
+			return val;
+		val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
+				PORT_REG_PHYS_CTRL_LINK_VALUE);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+					   val);
+		if (val < 0)
+			return val;
+
+		/* Wait for status register to reflect forced link */
+		do {
+			val = mv88e61xx_port_read(phydev, port,
+						  PORT_REG_STATUS);
+			if (val < 0)
+				goto unforce;
+			if (val & PORT_REG_STATUS_LINK)
+				break;
+		} while (--timeout);
+
+		if (timeout == 0) {
+			res = -ETIMEDOUT;
+			goto unforce;
+		}
+	}
+
+	if (val & PORT_REG_STATUS_DUPLEX)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
+
+	val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
+			       PORT_REG_STATUS_SPEED_WIDTH);
+	switch (val) {
+	case PORT_REG_STATUS_SPEED_1000:
+		phydev->speed = SPEED_1000;
+		break;
+	case PORT_REG_STATUS_SPEED_100:
+		phydev->speed = SPEED_100;
+		break;
+	default:
+		phydev->speed = SPEED_10;
+		break;
+	}
+
+	res = 0;
+
+unforce:
+	if (forced) {
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+		if (val < 0)
+			return val;
+		val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
+				PORT_REG_PHYS_CTRL_LINK_VALUE);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+					   val);
+		if (val < 0)
+			return val;
+	}
+
+	return res;
+}
+
+static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
+{
+	int val;
+
+	/* Set CPUDest */
+	val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
+			       GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
+			       CONFIG_MV88E61XX_CPU_PORT);
+	val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+				     GLOBAL1_MON_CTRL, val);
+	if (val < 0)
+		return val;
+
+	/* Allow CPU to route to any port */
+	val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
+	val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
+	if (val < 0)
+		return val;
+
+	/* Enable CPU port */
+	val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	/* If CPU is connected to serdes, initialize serdes */
+	if (mv88e61xx_6352_family(phydev)) {
+		val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
+		if (val < 0)
+			return val;
+		if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
+		    val == PORT_REG_STATUS_CMODE_1000BASE_X ||
+		    val == PORT_REG_STATUS_CMODE_SGMII) {
+			val = mv88e61xx_serdes_init(phydev);
+			if (val < 0)
+				return val;
+		}
+	}
+
+	return 0;
+}
+
+static int mv88e61xx_switch_init(struct phy_device *phydev)
+{
+	static int init;
+	int res;
+
+	if (init)
+		return 0;
+
+	res = mv88e61xx_switch_reset(phydev);
+	if (res < 0)
+		return res;
+
+	res = mv88e61xx_set_cpu_port(phydev);
+	if (res < 0)
+		return res;
+
+	init = 1;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
+	if (val < 0)
+		return val;
+	val &= ~(BMCR_PDOWN);
+	val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	/*
+	 * Enable energy-detect sensing on PHY, used to determine when a PHY
+	 * port is physically connected
+	 */
+	val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
+			       PHY_REG_CTRL1_ENERGY_DET_WIDTH,
+			       PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
+	val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	val = mv88e61xx_port_enable(phydev, phy);
+	if (val < 0)
+		return val;
+
+	val = mv88e61xx_port_set_vlan(phydev, phy,
+			1 << CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_probe(struct phy_device *phydev)
+{
+	struct mii_dev *smi_wrapper;
+	struct mv88e61xx_phy_priv *priv;
+	int res;
+
+	res = mv88e61xx_hw_reset(phydev);
+	if (res < 0)
+		return res;
+
+	priv = malloc(sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+
+	/*
+	 * This device requires indirect reads/writes to the PHY registers
+	 * which the generic PHY code can't handle.  Make a wrapper MII device
+	 * to handle reads/writes
+	 */
+	smi_wrapper = mdio_alloc();
+	if (!smi_wrapper) {
+		free(priv);
+		return -ENOMEM;
+	}
+
+	/*
+	 * Store the mdio bus in the private data, as we are going to replace
+	 * the bus with the wrapper bus
+	 */
+	priv->mdio_bus = phydev->bus;
+
+	/*
+	 * Store the smi bus address in private data.  This lets us use the
+	 * phydev addr field for device address instead, as the genphy code
+	 * expects.
+	 */
+	priv->smi_addr = phydev->addr;
+
+	/*
+	 * Store the phy_device in the wrapper mii device. This lets us get it
+	 * back when genphy functions call phy_read/phy_write.
+	 */
+	smi_wrapper->priv = phydev;
+	strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
+	smi_wrapper->read = mv88e61xx_phy_read_indirect;
+	smi_wrapper->write = mv88e61xx_phy_write_indirect;
+
+	/* Replace the bus with the wrapper device */
+	phydev->bus = smi_wrapper;
+
+	phydev->priv = priv;
+
+	priv->id = mv88e61xx_get_switch_id(phydev);
+
+	return 0;
+}
+
+static int mv88e61xx_phy_config(struct phy_device *phydev)
+{
+	int res;
+	int i;
+	int ret = -1;
+
+	res = mv88e61xx_switch_init(phydev);
+	if (res < 0)
+		return res;
+
+	for (i = 0; i < PORT_COUNT; i++) {
+		if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+			phydev->addr = i;
+
+			res = mv88e61xx_phy_enable(phydev, i);
+			if (res < 0) {
+				printf("Error enabling PHY %i\n", i);
+				continue;
+			}
+			res = mv88e61xx_phy_setup(phydev, i);
+			if (res < 0) {
+				printf("Error setting up PHY %i\n", i);
+				continue;
+			}
+			res = mv88e61xx_phy_config_port(phydev, i);
+			if (res < 0) {
+				printf("Error configuring PHY %i\n", i);
+				continue;
+			}
+
+			res = genphy_config_aneg(phydev);
+			if (res < 0) {
+				printf("Error setting PHY %i autoneg\n", i);
+				continue;
+			}
+			res = phy_reset(phydev);
+			if (res < 0) {
+				printf("Error resetting PHY %i\n", i);
+				continue;
+			}
+
+			/* Return success if any PHY succeeds */
+			ret = 0;
+		}
+	}
+
+	return ret;
+}
+
+static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
+{
+	int val;
+
+	val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
+	if (val < 0)
+		return 0;
+
+	/*
+	 * After reset, the energy detect signal remains high for a few seconds
+	 * regardless of whether a cable is connected.  This function will
+	 * return false positives during this time.
+	 */
+	return (val & PHY_REG_STATUS1_ENERGY) == 0;
+}
+
+static int mv88e61xx_phy_startup(struct phy_device *phydev)
+{
+	int i;
+	int link = 0;
+	int res;
+	int speed = phydev->speed;
+	int duplex = phydev->duplex;
+
+	for (i = 0; i < PORT_COUNT; i++) {
+		if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+			phydev->addr = i;
+			if (!mv88e61xx_phy_is_connected(phydev))
+				continue;
+			res = genphy_update_link(phydev);
+			if (res < 0)
+				continue;
+			res = mv88e61xx_parse_status(phydev);
+			if (res < 0)
+				continue;
+			link = (link || phydev->link);
+		}
+	}
+	phydev->link = link;
+
+	/* Restore CPU interface speed and duplex after it was changed for
+	 * other ports */
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+static struct phy_driver mv88e61xx_driver = {
+	.name = "Marvell MV88E61xx",
+	.uid = 0x01410eb1,
+	.mask = 0xfffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.probe = mv88e61xx_probe,
+	.config = mv88e61xx_phy_config,
+	.startup = mv88e61xx_phy_startup,
+	.shutdown = &genphy_shutdown,
+};
+
+int phy_mv88e61xx_init(void)
+{
+	phy_register(&mv88e61xx_driver);
+
+	return 0;
+}
+
+/*
+ * Overload weak get_phy_id definition since we need non-standard functions
+ * to read PHY registers
+ */
+int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
+{
+	struct phy_device temp_phy;
+	struct mv88e61xx_phy_priv temp_priv;
+	struct mii_dev temp_mii;
+	int val;
+
+	/*
+	 * Buid temporary data structures that the chip reading code needs to
+	 * read the ID
+	 */
+	temp_priv.mdio_bus = bus;
+	temp_priv.smi_addr = smi_addr;
+	temp_phy.priv = &temp_priv;
+	temp_mii.priv = &temp_phy;
+
+	val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
+	if (val < 0)
+		return -EIO;
+
+	*phy_id = val << 16;
+
+	val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
+	if (val < 0)
+		return -EIO;
+
+	*phy_id |= (val & 0xffff);
+
+	return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 23c82bb..539319f 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -458,6 +458,9 @@ static LIST_HEAD(phy_drivers);
 
 int phy_init(void)
 {
+#ifdef CONFIG_MV88E61XX_SWITCH
+	phy_mv88e61xx_init();
+#endif
 #ifdef CONFIG_PHY_AQUANTIA
 	phy_aquantia_init();
 #endif
diff --git a/include/phy.h b/include/phy.h
index 21459a8..969992c 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -249,6 +249,7 @@ int gen10g_startup(struct phy_device *phydev);
 int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
+int phy_mv88e61xx_init(void);
 int phy_aquantia_init(void);
 int phy_atheros_init(void);
 int phy_broadcom_init(void);
-- 
cgit v0.10.2


From 73443b9e4c451b17d1e08164ea933ee6a849b2b3 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:02 +0530
Subject: drivers: core: device: add support to check dt compatible for a
 device/machine

Provide an api to check whether the given device or machine is
compatible with the given compat string which helps in making
decisions in drivers based on device or machine compatible.

Idea taken from Linux.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 5c2dc70..45d5e3e 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -721,3 +721,17 @@ int device_set_name(struct udevice *dev, const char *name)
 
 	return 0;
 }
+
+bool of_device_is_compatible(struct udevice *dev, const char *compat)
+{
+	const void *fdt = gd->fdt_blob;
+
+	return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+}
+
+bool of_machine_is_compatible(const char *compat)
+{
+	const void *fdt = gd->fdt_blob;
+
+	return !fdt_node_check_compatible(fdt, 0, compat);
+}
diff --git a/include/dm/device.h b/include/dm/device.h
index e9a8ec7..f03bcd3 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -548,6 +548,29 @@ int device_set_name(struct udevice *dev, const char *name);
 void device_set_name_alloced(struct udevice *dev);
 
 /**
+ * of_device_is_compatible() - check if the device is compatible with the compat
+ *
+ * This allows to check whether the device is comaptible with the compat.
+ *
+ * @dev:	udevice pointer for which compatible needs to be verified.
+ * @compat:	Compatible string which needs to verified in the given
+ *		device
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_device_is_compatible(struct udevice *dev, const char *compat);
+
+/**
+ * of_machine_is_compatible() - check if the machine is compatible with
+ *				the compat
+ *
+ * This allows to check whether the machine is comaptible with the compat.
+ *
+ * @compat:	Compatible string which needs to verified
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_machine_is_compatible(const char *compat);
+
+/**
  * device_is_on_pci_bus - Test if a device is on a PCI bus
  *
  * @dev:	device to test
-- 
cgit v0.10.2


From 3d12e804956ca996b6621cd1e04fabd39b401882 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:03 +0530
Subject: ti_omap5_common: eth: do not define DM_ETH for spl

Since omap's spl doesn't support DM currently, do not define
DM_ETH for spl build.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index b049be4..2135af0 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -153,6 +153,7 @@
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
 #undef CONFIG_TIMER
+#undef CONFIG_DM_ETH
 #endif
 
 #endif /* __CONFIG_TI_OMAP5_COMMON_H */
-- 
cgit v0.10.2


From b2003c5458e883c691f3a7f5f770e6ed36e1b9d7 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:04 +0530
Subject: drivers: net: cpsw: fix cpsw dp parse when num slaves as 1

On some boards number of slaves can be 1 when only one port
ethernet is pinned out. So do not break when slave_index and
num slaves check fails, instead continue to parse the next
child.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 7104754..971ebf0 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -1209,10 +1209,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		if (!strncmp(name, "slave", 5)) {
 			u32 phy_id[2];
 
-			if (slave_index >= priv->data.slaves) {
-				printf("error: num slaves and slave nodes did not match\n");
-				return -EINVAL;
-			}
+			if (slave_index >= priv->data.slaves)
+				continue;
 			phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
 			if (phy_mode)
 				priv->data.slave_data[slave_index].phy_if =
-- 
cgit v0.10.2


From 70c5b7b37e34099c428366bdaf266f472dc24377 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:05 +0530
Subject: ARM: omap5: add platform specific ethernet phy modes configurations

Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index b1513e9..683d905 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,4 +116,16 @@ struct watchdog {
 #define CPSW_BASE			0x48484000
 #define CPSW_MDIO_BASE			0x48485000
 
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		(GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII		(GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII		(GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
 #endif /* _CPU_H */
-- 
cgit v0.10.2


From 66e740cbbdc54b5785046fffa52ed197602d74b1 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:06 +0530
Subject: drivers: net: cpsw: fix get mdio base and gmii_sel reg from DT

Since dra7x platforms address bus is define as 64 bits to support
LAPE, fdtdec_get_addr() returns a invalid address for mdio based
and gmii_sel register address. Fixing this by using
fdtdec_get_addr_size_auto_noparent() which will derive address
cell and size cell from its parent.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 971ebf0..9b1e37b 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -1137,6 +1137,11 @@ static const struct eth_ops cpsw_eth_ops = {
 	.stop		= cpsw_eth_stop,
 };
 
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+	return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -1202,8 +1207,14 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 
 		name = fdt_get_name(fdt, subnode, &len);
 		if (!strncmp(name, "mdio", 4)) {
-			priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
-							       "reg");
+			u32 mdio_base;
+
+			mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+			if (mdio_base == FDT_ADDR_T_NONE) {
+				error("Not able to get MDIO address space\n");
+				return -ENOENT;
+			}
+			priv->data.mdio_base = mdio_base;
 		}
 
 		if (!strncmp(name, "slave", 5)) {
@@ -1221,8 +1232,13 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		}
 
 		if (!strncmp(name, "cpsw-phy-sel", 12)) {
-			priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
-							      "reg");
+			priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+								    subnode);
+
+			if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+				error("Not able to get gmii_sel reg address\n");
+				return -ENOENT;
+			}
 		}
 	}
 
-- 
cgit v0.10.2


From e4310566deb7533301eb0de78d3640f4f307d267 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:07 +0530
Subject: drivers: net: cpsw: add support for reading mac address from efuse

Different TI platforms has to read with different combination to
get the mac address from efuse. So add support to read mac address
based on machine/device compatibles.

The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c
done by Tony Lindgren.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fbedd04..d5e4a97 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,7 +59,7 @@ obj-$(CONFIG_SMC91111) += smc91111.o
 obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
 obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
 obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
 obj-$(CONFIG_ULI526X) += uli526x.o
diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c
new file mode 100644
index 0000000..e828e85
--- /dev/null
+++ b/drivers/net/cpsw-common.c
@@ -0,0 +1,121 @@
+/*
+ * CPSW common - libs used across TI ethernet devices.
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
+
+static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
+				       int slave, u8 *mac_addr)
+{
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	u32 macid_lsb;
+	u32 macid_msb;
+	fdt32_t gmii = 0;
+	int syscon;
+	u32 addr;
+
+	syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+	if (syscon < 0) {
+		error("Syscon offset not found\n");
+		return -ENOENT;
+	}
+
+	addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+				sizeof(u32), MAP_NOCACHE);
+	if (addr == FDT_ADDR_T_NONE) {
+		error("Not able to get syscon address to get mac efuse address\n");
+		return -ENOENT;
+	}
+
+	addr += CTRL_MAC_REG(offset, slave);
+
+	/* try reading mac address from efuse */
+	macid_lsb = readl(addr);
+	macid_msb = readl(addr + 4);
+
+	mac_addr[0] = (macid_msb >> 16) & 0xff;
+	mac_addr[1] = (macid_msb >> 8)  & 0xff;
+	mac_addr[2] = macid_msb & 0xff;
+	mac_addr[3] = (macid_lsb >> 16) & 0xff;
+	mac_addr[4] = (macid_lsb >> 8)  & 0xff;
+	mac_addr[5] = macid_lsb & 0xff;
+
+	return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
+				    u8 *mac_addr)
+{
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	u32 macid_lo;
+	u32 macid_hi;
+	fdt32_t gmii = 0;
+	int syscon;
+	u32 addr;
+
+	syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+	if (syscon < 0) {
+		error("Syscon offset not found\n");
+		return -ENOENT;
+	}
+
+	addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+				sizeof(u32), MAP_NOCACHE);
+	if (addr == FDT_ADDR_T_NONE) {
+		error("Not able to get syscon address to get mac efuse address\n");
+		return -ENOENT;
+	}
+
+	addr += CTRL_MAC_REG(offset, slave);
+
+	/* try reading mac address from efuse */
+	macid_lo = readl(addr);
+	macid_hi = readl(addr + 4);
+
+	mac_addr[5] = (macid_lo >> 8) & 0xff;
+	mac_addr[4] = macid_lo & 0xff;
+	mac_addr[3] = (macid_hi >> 24) & 0xff;
+	mac_addr[2] = (macid_hi >> 16) & 0xff;
+	mac_addr[1] = (macid_hi >> 8) & 0xff;
+	mac_addr[0] = macid_hi & 0xff;
+
+	return 0;
+}
+
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
+{
+	if (of_machine_is_compatible("ti,dm8148"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,am33xx"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_device_is_compatible(dev, "ti,am3517-emac"))
+		return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+	if (of_device_is_compatible(dev, "ti,dm816-emac"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,am4372"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,dra7"))
+		return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
+	dev_err(dev, "incompatible machine/device type for reading mac address\n");
+	return -ENOENT;
+}
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 9b1e37b..b811119 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -26,6 +26,7 @@
 #include <phy.h>
 #include <asm/arch/cpu.h>
 #include <dm.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1151,9 +1152,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 	int node = dev->of_offset;
 	int subnode;
 	int slave_index = 0;
-	uint32_t mac_hi, mac_lo;
-	fdt32_t gmii = 0;
 	int active_slave;
+	int ret;
 
 	pdata->iobase = dev_get_addr(dev);
 	priv->data.version = CPSW_CTRL_VERSION_2;
@@ -1250,20 +1250,11 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
 	}
 
-	subnode = fdtdec_lookup_phandle(fdt, node, "syscon");
-	priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii);
-	priv->data.mac_id += AM335X_GMII_SEL_OFFSET;
-	priv->data.mac_id += active_slave * 8;
-
-	/* try reading mac address from efuse */
-	mac_lo = readl(priv->data.mac_id);
-	mac_hi = readl(priv->data.mac_id + 4);
-	pdata->enetaddr[0] = mac_hi & 0xFF;
-	pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8;
-	pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
-	pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
-	pdata->enetaddr[4] = mac_lo & 0xFF;
-	pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+	ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
+	if (ret < 0) {
+		error("cpsw read efuse mac failed\n");
+		return ret;
+	}
 
 	pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
 	if (pdata->phy_interface == -1) {
@@ -1284,6 +1275,7 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
 		break;
 	}
+
 	return 0;
 }
 
diff --git a/include/cpsw.h b/include/cpsw.h
index cf1d30b..6255cd8 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -51,5 +51,6 @@ struct cpsw_platform_data {
 };
 
 int cpsw_register(struct cpsw_platform_data *data);
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
 
 #endif /* _CPSW_H_  */
-- 
cgit v0.10.2


From dcda79e119cb50d5d4732ef8d22c58889118f559 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:08 +0530
Subject: arm: dts: am4372: add syscon node to cpsw to read mac address

Add syscon node to cpsw device node to read mac address
from efuse.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index c95d1d3..3ffa8e0 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -547,6 +547,7 @@
 			active_slave = <0>;
 			cpts_clock_mult = <0x80000000>;
 			cpts_clock_shift = <29>;
+			syscon = <&scm_conf>;
 			ranges;
 
 			davinci_mdio: mdio@4a101000 {
-- 
cgit v0.10.2


From d7dc888d60b7d7641275bf6211307720b726baf9 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:09 +0530
Subject: arm: dts: dra7: add syscon node to cpsw to read mac address

Add syscon node to cpsw device node to read mac address
from efuse.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e7fecf7..3059273 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1426,6 +1426,7 @@
 			active_slave = <0>;
 			cpts_clock_mult = <0x80000000>;
 			cpts_clock_shift = <29>;
+			syscon = <&scm_conf>;
 			reg = <0x48484000 0x1000
 			       0x48485200 0x2E00>;
 			#address-cells = <1>;
-- 
cgit v0.10.2


From 844f81447886697c14c0ade8077771e0e52907dc Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:10 +0530
Subject: arm: dts: dra7: fix ethernet name with proper device address

Fix typo error for cpsw device name with proper device address

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 3059273..0f242e6 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1411,7 +1411,7 @@
 			ti,irqs-safe-map = <0>;
 		};
 
-		mac: ethernet@4a100000 {
+		mac: ethernet@48484000 {
 			compatible = "ti,cpsw";
 			ti,hwmods = "gmac";
 			clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
-- 
cgit v0.10.2


From 54e3ba993a68d03ff763e1de8cde168552edf79c Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:11 +0530
Subject: defconfig: am437x_gp_evm: enable eth driver model

Enable eth driver model for am437x_gp_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 03b02ac..f098fd3 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -47,3 +47,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From bc705ea1cf12d42f3f10ff2b9f0e037fd56b7410 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:12 +0530
Subject: defconfig: am437x_sk_evm: enable eth driver model

Enable eth driver model for am437x_sk_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 48ec91f..8be0412 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -51,3 +51,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From 641b936fa5ba4f07d8400bd3bc0540f4ad64eeb7 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 28 Apr 2016 15:36:13 +0530
Subject: defconfig: dra74_evm: enable eth driver model

Enable eth driver model for dra74_evm as cpsw supports
driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index a11dcd5..32ffce7 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -50,3 +50,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From cb3862277b73b57ade3774b8fa684d3d7c324ba3 Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:45:56 -0500
Subject: drivers: net: cpsw: Add reading of DT phy-handle node

Add the ability to read the phy-handle node of the
cpsw slave.  Upon reading this handle the phy-id
can be stored based on the reg node in the DT.

The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index b811119..2ce4ec6 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -966,6 +966,11 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 	phydev->supported &= supported;
 	phydev->advertising = phydev->supported;
 
+#ifdef CONFIG_DM_ETH
+	if (slave->data->phy_of_handle)
+		phydev->dev->of_offset = slave->data->phy_of_handle;
+#endif
+
 	priv->phydev = phydev;
 	phy_config(phydev);
 
@@ -1226,8 +1231,22 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 			if (phy_mode)
 				priv->data.slave_data[slave_index].phy_if =
 					phy_get_interface_by_name(phy_mode);
-			fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2);
-			priv->data.slave_data[slave_index].phy_addr = phy_id[1];
+
+			priv->data.slave_data[slave_index].phy_of_handle =
+				fdtdec_lookup_phandle(fdt, subnode,
+						      "phy-handle");
+
+			if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
+				priv->data.slave_data[slave_index].phy_addr =
+						fdtdec_get_int(gd->fdt_blob,
+							       priv->data.slave_data[slave_index].phy_of_handle,
+							       "reg", -1);
+			} else {
+				fdtdec_get_int_array(fdt, subnode, "phy_id",
+						     phy_id, 2);
+				priv->data.slave_data[slave_index].phy_addr =
+						phy_id[1];
+			}
 			slave_index++;
 		}
 
diff --git a/include/cpsw.h b/include/cpsw.h
index 6255cd8..257d12a 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -21,6 +21,7 @@ struct cpsw_slave_data {
 	u32		sliver_reg_ofs;
 	int		phy_addr;
 	int		phy_if;
+	int		phy_of_handle;
 };
 
 enum {
-- 
cgit v0.10.2


From 20671a98960e7a98696bfbca1c902be6ccba013b Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:45:57 -0500
Subject: net: zynq_gem: Add the passing of the phy-handle node

Add the ability to pass the phy-handle node offset
to the phy driver.  This allows the phy driver
to access the DT subnode's data and parse accordingly.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index aec8077..f9b22c4 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -179,6 +179,7 @@ struct zynq_gem_priv {
 	struct zynq_gem_regs *iobase;
 	phy_interface_t interface;
 	struct phy_device *phydev;
+	int phy_of_handle;
 	struct mii_dev *bus;
 };
 
@@ -352,6 +353,10 @@ static int zynq_phy_init(struct udevice *dev)
 	priv->phydev->supported = supported | ADVERTISED_Pause |
 				  ADVERTISED_Asym_Pause;
 	priv->phydev->advertising = priv->phydev->supported;
+
+	if (priv->phy_of_handle > 0)
+		priv->phydev->dev->of_offset = priv->phy_of_handle;
+
 	phy_config(priv->phydev);
 
 	return 0;
@@ -675,7 +680,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
-	int offset = 0;
 	const char *phy_mode;
 
 	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
@@ -684,10 +688,11 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 	priv->emio = 0;
 	priv->phyaddr = -1;
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
-				       "phy-handle");
-	if (offset > 0)
-		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+	priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+					dev->of_offset, "phy-handle");
+	if (priv->phy_of_handle > 0)
+		priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+					priv->phy_of_handle, "reg", -1);
 
 	phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 	if (phy_mode)
-- 
cgit v0.10.2


From c7ba7bdc9d9940313ff5a63644ae3d74c77636cc Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:45:58 -0500
Subject: net: phy: dp83867: Add device tree bindings and documentation

Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.

The original document was from:
    [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
new file mode 100644
index 0000000..cb77fdf
--- /dev/null
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -0,0 +1,25 @@
+* Texas Instruments - dp83867 Giga bit ethernet phy
+
+Required properties:
+	- reg - The ID number for the phy, usually a small integer
+	- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
+		for applicable values
+	- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
+		for applicable values
+	- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
+		for applicable values
+
+Default child nodes are standard Ethernet PHY device
+nodes as described in doc/devicetree/bindings/net/ethernet.txt
+
+Example:
+
+	ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+
+Datasheet can be found:
+http://www.ti.com/product/DP83867IR/datasheet
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644
index 0000000..1843757
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,35 @@
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS	0x0
+#define DP83867_RGMIIDCTL_500_PS	0x1
+#define DP83867_RGMIIDCTL_750_PS	0x2
+#define DP83867_RGMIIDCTL_1_NS		0x3
+#define DP83867_RGMIIDCTL_1_25_NS	0x4
+#define DP83867_RGMIIDCTL_1_50_NS	0x5
+#define DP83867_RGMIIDCTL_1_75_NS	0x6
+#define DP83867_RGMIIDCTL_2_00_NS	0x7
+#define DP83867_RGMIIDCTL_2_25_NS	0x8
+#define DP83867_RGMIIDCTL_2_50_NS	0x9
+#define DP83867_RGMIIDCTL_2_75_NS	0xa
+#define DP83867_RGMIIDCTL_3_00_NS	0xb
+#define DP83867_RGMIIDCTL_3_25_NS	0xc
+#define DP83867_RGMIIDCTL_3_50_NS	0xd
+#define DP83867_RGMIIDCTL_3_75_NS	0xe
+#define DP83867_RGMIIDCTL_4_00_NS	0xf
+
+#endif
-- 
cgit v0.10.2


From 085445ca4104906b94093eed1b5e37630ad3b93d Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:45:59 -0500
Subject: net: phy: ti: Allow the driver to be more configurable

Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 937426b..4c4f0c1 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,14 @@
  */
 #include <common.h>
 #include <phy.h>
+#include <linux/compat.h>
+#include <malloc.h>
+
+#include <fdtdec.h>
+#include <dm.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* TI DP83867 */
 #define DP83867_DEVADDR		0x1f
@@ -71,6 +79,17 @@
 #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */
 #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */
 
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+	int rx_id_delay;
+	int tx_id_delay;
+	int fifo_depth;
+};
+
 /**
  * phy_read_mmd_indirect - reads data from the MMD registers
  * @phydev: The PHY device bus
@@ -148,16 +167,60 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 }
 
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY	8
-#define TX_ID_DELAY	0xa
-#define FIFO_DEPTH	1
+#if defined(CONFIG_DM_ETH)
+/**
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
+ * @phydev: the phy_device struct
+ */
+static int dp83867_of_init(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 = phydev->priv;
+	struct udevice *dev = phydev->dev;
+
+	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,rx-internal-delay", -1);
+
+	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,tx-internal-delay", -1);
+
+	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,fifo-depth", -1);
+
+	return 0;
+}
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 = phydev->priv;
+
+	dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+	dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+	dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+	return 0;
+}
+#endif
 
 static int dp83867_config(struct phy_device *phydev)
 {
+	struct dp83867_private *dp83867;
 	unsigned int val, delay, cfg2;
 	int ret;
 
+	if (!phydev->priv) {
+		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+		if (!dp83867)
+			return -ENOMEM;
+
+		phydev->priv = dp83867;
+		ret = dp83867_of_init(phydev);
+		if (ret)
+			goto err_out;
+	} else {
+		dp83867 = (struct dp83867_private *)phydev->priv;
+	}
+
 	/* Restart the PHY.  */
 	val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 	phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -166,9 +229,9 @@ static int dp83867_config(struct phy_device *phydev)
 	if (phy_interface_is_rgmii(phydev)) {
 		ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 			(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-			(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 		if (ret)
-			return ret;
+			goto err_out;
 	} else {
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
@@ -189,8 +252,8 @@ static int dp83867_config(struct phy_device *phydev)
 			  DP83867_PHYCTRL_SGMIIEN |
 			  (DP83867_MDI_CROSSOVER_MDIX <<
 			  DP83867_MDI_CROSSOVER) |
-			  (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
-			  (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
+			  (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+			  (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 	}
 
@@ -212,8 +275,8 @@ static int dp83867_config(struct phy_device *phydev)
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 				       DP83867_DEVADDR, phydev->addr, val);
 
-		delay = (RX_ID_DELAY |
-			 (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+		delay = (dp83867->rx_id_delay |
+			 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 
 		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 				       DP83867_DEVADDR, phydev->addr, delay);
@@ -221,6 +284,10 @@ static int dp83867_config(struct phy_device *phydev)
 
 	genphy_config_aneg(phydev);
 	return 0;
+
+err_out:
+	kfree(dp83867);
+	return ret;
 }
 
 static struct phy_driver DP83867_driver = {
-- 
cgit v0.10.2


From 3ab72fe8075b137c238665008c356239d1e6bc54 Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:46:00 -0500
Subject: net: phy: Move is_rgmii helper to phy.h

Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.

This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 4c4f0c1..4c19353 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -156,17 +156,6 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
 	phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
-/**
- * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
- * is RGMII (all variants)
- * @phydev: the phy_device struct
- */
-static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
-{
-	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
-		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
-}
-
 #if defined(CONFIG_DM_ETH)
 /**
  * dp83867_data_init - Convenience function for setting PHY specific data
diff --git a/include/phy.h b/include/phy.h
index 969992c..7346da7 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -278,6 +278,17 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
  */
 int phy_get_interface_by_name(const char *str);
 
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_CS4340  0x13e51002
 #define PHY_UID_TN2020	0x00a19410
-- 
cgit v0.10.2


From 3c221af3c3bb4eadc0899f611c8b25bb95a1e09f Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:46:01 -0500
Subject: net: phy: Add phy_interface_is_sgmii to phy.h

Add a helper to phy.h to identify whether the
phy is configured for SGMII all variables.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/include/phy.h b/include/phy.h
index 7346da7..268d9a1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -289,6 +289,17 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 }
 
+/**
+ * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
+ * is SGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+}
+
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_CS4340  0x13e51002
 #define PHY_UID_TN2020	0x00a19410
-- 
cgit v0.10.2


From 0a71cd77290ca317ecf6f15984a91abbee741e09 Mon Sep 17 00:00:00 2001
From: Dan Murphy <dmurphy@ti.com>
Date: Mon, 2 May 2016 15:46:02 -0500
Subject: net: phy: dp83867: Add SGMII helper for configuration

The code assumed that if the interface is not RGMII configured
then it must be SGMII configured.  This device has the ability
to support most of the MII interfaces.  Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 4c19353..c55dd97 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -221,7 +221,7 @@ static int dp83867_config(struct phy_device *phydev)
 			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 		if (ret)
 			goto err_out;
-	} else {
+	} else if (phy_interface_is_sgmii(phydev)) {
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 
-- 
cgit v0.10.2


From 82eda68444fa4d026bcf1f59c7c0d044ddbcb193 Mon Sep 17 00:00:00 2001
From: Aneesh Bansal <aneesh.bansal@nxp.com>
Date: Mon, 18 Apr 2016 22:58:33 +0530
Subject: powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache

While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 82a151a..4c51225 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -720,16 +720,39 @@ enable_l2_cluster_l2:
 	ori	r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
 	sync
 	stw	r4, 0(r3)	/* invalidate L2 */
+	/* Poll till the bits are cleared */
 1:	sync
 	lwz	r0, 0(r3)
 	twi	0, r0, 0
 	isync
 	and.	r1, r0, r4
 	bne	1b
+
+	/* L2PE must be set before L2 cache is enabled */
+	lis	r4, (L2CSR0_L2PE)@h
+	ori	r4, r4, (L2CSR0_L2PE)@l
+	sync
+	stw	r4, 0(r3)	/* enable L2 parity/ECC error checking */
+	/* Poll till the bit is set */
+1:	sync
+	lwz	r0, 0(r3)
+	twi	0, r0, 0
+	isync
+	and.	r1, r0, r4
+	beq	1b
+
 	lis	r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
 	ori	r4, r4, (L2CSR0_L2REP_MODE)@l
 	sync
 	stw	r4, 0(r3)	/* enable L2 */
+	/* Poll till the bit is set */
+1:	sync
+	lwz	r0, 0(r3)
+	twi	0, r0, 0
+	isync
+	and.	r1, r0, r4
+	beq	1b
+
 delete_ccsr_l2_tlb:
 	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif
-- 
cgit v0.10.2


From d1fc8ed485cbf44434a9bc2a02ddf2a94f2183c1 Mon Sep 17 00:00:00 2001
From: Ying Zhang <ying.zhang22455@nxp.com>
Date: Thu, 21 Apr 2016 14:23:46 +0800
Subject: powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDB

Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5,
FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6.

Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index e563a61..ae2451e 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -77,6 +77,9 @@ int board_eth_init(bd_t *bis)
 		puts("Invalid SerDes1 protocol for T4240RDB\n");
 	}
 
+	fm_disable_port(FM1_DTSEC5);
+	fm_disable_port(FM1_DTSEC6);
+
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
@@ -115,6 +118,8 @@ int board_eth_init(bd_t *bis)
 		puts("Invalid SerDes2 protocol for T4240RDB\n");
 	}
 
+	fm_disable_port(FM2_DTSEC5);
+	fm_disable_port(FM2_DTSEC6);
 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
-- 
cgit v0.10.2


From 8ef548d5f13e68e1b3975d9b68920bfa8bf09891 Mon Sep 17 00:00:00 2001
From: Ying Zhang <b40530@freescale.com>
Date: Mon, 18 Apr 2016 17:04:16 +0800
Subject: powerpc:t4240: MAC9 and MAC10 should not be identified as 1G
 interface in some case

When using rcw protocols to support 10G on MAC9 and MAC10, these MACs
should not be identified as 1G interface, otherwise, one MAC will be
listed as two Ethernet ports. For example, MAC9 will be listed as
FM1@TGEC1 and FM1@DTSEC9.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index ae5aca4..70887fa 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -74,7 +74,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
 	    ((is_serdes_configured(XFI_FM1_MAC9)) ||
 	     (is_serdes_configured(XFI_FM1_MAC10))))
-		return PHY_INTERFACE_MODE_XGMII;
+		return PHY_INTERFACE_MODE_NONE;
 
 	if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
 	    ((is_serdes_configured(XAUI_FM2_MAC9))	||
-- 
cgit v0.10.2


From ac985273135762a596482812551221019c319731 Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:07 +0530
Subject: pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices

It is possible to have multiple pin controllers in the system. Use the
DM_UC_FLAG_SEQ_ALIAS flag so that the pinctrl instances are assigned
a sequence number.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index ccc5d30..fd04b26 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -287,5 +287,6 @@ static int pinctrl_post_bind(struct udevice *dev)
 UCLASS_DRIVER(pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.post_bind = pinctrl_post_bind,
+	.flags = DM_UC_FLAG_SEQ_ALIAS,
 	.name = "pinctrl",
 };
-- 
cgit v0.10.2


From 16ca80adc551808b6be1d43f30997f8b4fdfbd39 Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:08 +0530
Subject: pinctrl: Add pinctrl driver support for Exynos7420 SoC

Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes
have been split into Exynos7420 specific and common Exynos specific
portions so that this implementation is reusable on other Exynos
SoCs as well.

The Exynos pinctrl driver supports only device tree based pin
configuration. The bindings used are similar to the ones used in the
linux kernel.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 567b766..1785e3b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -163,5 +163,6 @@ endif
 
 source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/exynos/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index b99ed2f..7f94681 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 
 obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
 obj-$(CONFIG_PIC32_PINCTRL)	+= pinctrl_pic32.o
+obj-$(CONFIG_PINCTRL_EXYNOS)	+= exynos/
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
new file mode 100644
index 0000000..84b6aaa
--- /dev/null
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -0,0 +1,10 @@
+config PINCTRL_EXYNOS
+	bool
+
+config PINCTRL_EXYNOS7420
+	bool "Samsung Exynos7420 pinctrl driver"
+	depends on ARCH_EXYNOS && PINCTRL_FULL
+	select PINCTRL_EXYNOS
+	help
+	  Support pin multiplexing and pin configuration control on
+	  Samsung's Exynos7420 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
new file mode 100644
index 0000000..d9b941a
--- /dev/null
+++ b/drivers/pinctrl/exynos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_PINCTRL_EXYNOS)		+= pinctrl-exynos.o
+obj-$(CONFIG_PINCTRL_EXYNOS7420)	+= pinctrl-exynos7420.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c
new file mode 100644
index 0000000..a28405f
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -0,0 +1,141 @@
+/*
+ * Exynos pinctrl driver common code.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include "pinctrl-exynos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
+ * conf: soc specific pin configuration data array
+ * num_conf: number of configurations in the conf array.
+ * base: base address of the pin controller.
+ */
+void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
+		unsigned int num_conf, unsigned long base)
+{
+	unsigned int idx, val;
+
+	for (idx = 0; idx < num_conf; idx++) {
+		val = readl(base + conf[idx].offset);
+		val &= ~(conf[idx].mask);
+		val |= conf[idx].value;
+		writel(val, base + conf[idx].offset);
+	}
+}
+
+/* given a pin-name, return the address of pin config registers */
+static unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name,
+						u32 *pin)
+{
+	struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl;
+	const struct samsung_pin_bank_data *bank_data = pin_ctrl->pin_banks;
+	u32 nr_banks = pin_ctrl->nr_banks, idx = 0;
+	char bank[10];
+
+	/*
+	 * The format of the pin name is <bank name>-<pin_number>.
+	 * Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
+	 */
+	while (pin_name[idx] != '-') {
+		bank[idx] = pin_name[idx];
+		idx++;
+	}
+	bank[idx] = '\0';
+	*pin = pin_name[++idx] - '0';
+
+	/* lookup the pin bank data using the pin bank name */
+	for (idx = 0; idx < nr_banks; idx++)
+		if (!strcmp(bank, bank_data[idx].name))
+			break;
+
+	return priv->base + bank_data[idx].offset;
+}
+
+/**
+ * exynos_pinctrl_set_state: configure a pin state.
+ * dev: the pinctrl device to be configured.
+ * config: the state to be configured.
+ */
+int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+	const void *fdt = gd->fdt_blob;
+	int node = config->of_offset;
+	unsigned int count, idx, pin_num, ret;
+	unsigned int pinfunc, pinpud, pindrv;
+	unsigned long reg, value;
+	const char *name;
+
+	/*
+	 * refer to the following document for the pinctrl bindings
+	 * linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+	 */
+	count = fdt_count_strings(fdt, node, "samsung,pins");
+	if (count <= 0)
+		return -EINVAL;
+
+	pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
+	pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
+	pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
+
+	for (idx = 0; idx < count; idx++) {
+		ret = fdt_get_string_index(fdt, node, "samsung,pins",
+						idx, &name);
+		if (ret < 0)
+			continue;
+		reg = pin_to_bank_base(dev, name, &pin_num);
+
+		if (pinfunc != -1) {
+			value = readl(reg + PIN_CON);
+			value &= ~(0xf << (pin_num << 2));
+			value |= (pinfunc << (pin_num << 2));
+			writel(value, reg + PIN_CON);
+		}
+
+		if (pinpud != -1) {
+			value = readl(reg + PIN_PUD);
+			value &= ~(0x3 << (pin_num << 1));
+			value |= (pinpud << (pin_num << 1));
+			writel(value, reg + PIN_PUD);
+		}
+
+		if (pindrv != -1) {
+			value = readl(reg + PIN_DRV);
+			value &= ~(0x3 << (pin_num << 1));
+			value |= (pindrv << (pin_num << 1));
+			writel(value, reg + PIN_DRV);
+		}
+	}
+
+	return 0;
+}
+
+int exynos_pinctrl_probe(struct udevice *dev)
+{
+	struct exynos_pinctrl_priv *priv;
+	fdt_addr_t base;
+
+	priv = dev_get_priv(dev);
+	if (!priv)
+		return -EINVAL;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = base;
+	priv->pin_ctrl = (struct samsung_pin_ctrl *)dev_get_driver_data(dev) +
+				dev->req_seq;
+
+	return 0;
+}
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h b/drivers/pinctrl/exynos/pinctrl-exynos.h
new file mode 100644
index 0000000..abd582d
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -0,0 +1,77 @@
+/*
+ * Exynos pinctrl driver header.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PINCTRL_EXYNOS_H_
+#define __PINCTRL_EXYNOS__H_
+
+#define PIN_CON		0x00	/* Offset of pin function register */
+#define PIN_DAT		0x04	/* Offset of pin data register */
+#define PIN_PUD		0x08	/* Offset of pin pull up/down config register */
+#define PIN_DRV		0x0C	/* Offset of pin drive strength register */
+
+/**
+ * struct samsung_pin_bank_data: represent a controller pin-bank data.
+ * @offset: starting offset of the pin-bank registers.
+ * @nr_pins: number of pins included in this bank.
+ * @name: name to be prefixed for each pin in this pin bank.
+ */
+struct samsung_pin_bank_data {
+	u32		offset;
+	u8		nr_pins;
+	const char	*name;
+};
+
+#define EXYNOS_PIN_BANK(pins, reg, id)			\
+	{						\
+		.offset	= reg,				\
+		.nr_pins	= pins,			\
+		.name		= id			\
+	}
+
+/**
+ * struct samsung_pin_ctrl: represent a pin controller.
+ * @pin_banks: list of pin banks included in this controller.
+ * @nr_banks: number of pin banks.
+ */
+struct samsung_pin_ctrl {
+	const struct samsung_pin_bank_data *pin_banks;
+	u32 nr_banks;
+};
+
+/**
+ * struct exynos_pinctrl_priv: exynos pin controller driver private data
+ * @pin_ctrl: pin controller bank information.
+ * @base: base address of the pin controller instance.
+ * @num_banks: number of pin banks included in the pin controller.
+ */
+struct exynos_pinctrl_priv {
+	const struct samsung_pin_ctrl *pin_ctrl;
+	unsigned long base;
+	int num_banks;
+};
+
+/**
+ * struct exynos_pinctrl_config_data: configuration for a peripheral.
+ * @offset: offset of the config registers in the controller.
+ * @mask: value of the register to be masked with.
+ * @value: new value to be programmed.
+ */
+struct exynos_pinctrl_config_data {
+	const unsigned int	offset;
+	const unsigned int	mask;
+	const unsigned int	value;
+};
+
+
+void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
+		unsigned int num_conf, unsigned long base);
+int exynos_pinctrl_set_state(struct udevice *dev,
+		struct udevice *config);
+int exynos_pinctrl_probe(struct udevice *dev);
+
+#endif /* __PINCTRL_EXYNOS_H_ */
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos7420.c b/drivers/pinctrl/exynos/pinctrl-exynos7420.c
new file mode 100644
index 0000000..8ae5ce7
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos7420.c
@@ -0,0 +1,120 @@
+/*
+ * Exynos7420 pinctrl driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
+#include <asm/arch/pinmux.h>
+#include "pinctrl-exynos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	GPD1_OFFSET	0xc0
+
+static struct exynos_pinctrl_config_data serial2_conf[] = {
+	{
+		.offset	= GPD1_OFFSET + PIN_CON,
+		.mask	= 0x00ff0000,
+		.value	= 0x00220000,
+	}, {
+		.offset	= GPD1_OFFSET + PIN_PUD,
+		.mask	= 0x00000f00,
+		.value	= 0x00000f00,
+	},
+};
+
+static int exynos7420_pinctrl_request(struct udevice *dev, int peripheral,
+						int flags)
+{
+	struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+	unsigned long base = priv->base;
+
+	switch (PERIPH_ID_UART2) {
+	case PERIPH_ID_UART2:
+		exynos_pinctrl_setup_peri(serial2_conf,
+					  ARRAY_SIZE(serial2_conf), base);
+		break;
+	default:
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static struct pinctrl_ops exynos7420_pinctrl_ops = {
+	.set_state	= exynos_pinctrl_set_state,
+	.request	= exynos7420_pinctrl_request,
+};
+
+/* pin banks of Exynos7420 pin-controller - BUS0 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks0[] = {
+	EXYNOS_PIN_BANK(5, 0x000, "gpb0"),
+	EXYNOS_PIN_BANK(8, 0x020, "gpc0"),
+	EXYNOS_PIN_BANK(2, 0x040, "gpc1"),
+	EXYNOS_PIN_BANK(6, 0x060, "gpc2"),
+	EXYNOS_PIN_BANK(8, 0x080, "gpc3"),
+	EXYNOS_PIN_BANK(4, 0x0a0, "gpd0"),
+	EXYNOS_PIN_BANK(6, 0x0c0, "gpd1"),
+	EXYNOS_PIN_BANK(8, 0x0e0, "gpd2"),
+	EXYNOS_PIN_BANK(5, 0x100, "gpd4"),
+	EXYNOS_PIN_BANK(4, 0x120, "gpd5"),
+	EXYNOS_PIN_BANK(6, 0x140, "gpd6"),
+	EXYNOS_PIN_BANK(3, 0x160, "gpd7"),
+	EXYNOS_PIN_BANK(2, 0x180, "gpd8"),
+	EXYNOS_PIN_BANK(2, 0x1a0, "gpg0"),
+	EXYNOS_PIN_BANK(4, 0x1c0, "gpg3"),
+};
+
+/* pin banks of Exynos7420 pin-controller - FSYS0 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks1[] = {
+	EXYNOS_PIN_BANK(7, 0x000, "gpr4"),
+};
+
+/* pin banks of Exynos7420 pin-controller - FSYS1 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks2[] = {
+	EXYNOS_PIN_BANK(4, 0x000, "gpr0"),
+	EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
+	EXYNOS_PIN_BANK(5, 0x040, "gpr2"),
+	EXYNOS_PIN_BANK(8, 0x060, "gpr3"),
+};
+
+const struct samsung_pin_ctrl exynos7420_pin_ctrl[] = {
+	{
+		/* pin-controller instance BUS0 data */
+		.pin_banks	= exynos7420_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos7420_pin_banks0),
+	}, {
+		/* pin-controller instance FSYS0 data */
+		.pin_banks	= exynos7420_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos7420_pin_banks1),
+	}, {
+		/* pin-controller instance FSYS1 data */
+		.pin_banks	= exynos7420_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos7420_pin_banks2),
+	},
+};
+
+static const struct udevice_id exynos7420_pinctrl_ids[] = {
+	{ .compatible = "samsung,exynos7420-pinctrl",
+		.data = (ulong)exynos7420_pin_ctrl },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_exynos7420) = {
+	.name		= "pinctrl_exynos7420",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= exynos7420_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv),
+	.ops		= &exynos7420_pinctrl_ops,
+	.probe		= exynos_pinctrl_probe,
+	.flags		= DM_FLAG_PRE_RELOC
+};
-- 
cgit v0.10.2


From 166097e8775343898cab84f1f23b4aacb35783db Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:09 +0530
Subject: clk: exynos: add clock driver for Exynos7420 Soc

Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
are added in this initial version of the driver.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a98b74b..6eee8eb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -21,5 +21,6 @@ config SPL_CLK
 	  used as U-Boot proper.
 
 source "drivers/clk/uniphier/Kconfig"
+source "drivers/clk/exynos/Kconfig"
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c51db15..81fe600 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
new file mode 100644
index 0000000..eb0efa9
--- /dev/null
+++ b/drivers/clk/exynos/Kconfig
@@ -0,0 +1,18 @@
+config CLK_EXYNOS
+	bool
+	select CLK
+	help
+	  This enables support for common clock driver API on Samsung
+	  Exynos SoCs.
+
+menu "Clock drivers for Exynos SoCs"
+	depends on CLK_EXYNOS
+
+config CLK_EXYNOS7420
+	bool "Clock driver for Samsung's Exynos7420 SoC"
+	default y
+	help
+	  This enables common clock driver support for platforms based
+	  on Samsung Exynos7420 SoC.
+
+endmenu
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
new file mode 100644
index 0000000..1df10fe
--- /dev/null
+++ b/drivers/clk/exynos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y				+= clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420)	+= clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
new file mode 100644
index 0000000..bf5d0e6
--- /dev/null
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -0,0 +1,236 @@
+/*
+ * Samsung Exynos7420 clock driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/exynos7420-clk.h>
+#include "clk-pll.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIVIDER(reg, shift, mask)	\
+	(((readl(reg) >> shift) & mask) + 1)
+
+/* CMU TOPC block device structure */
+struct exynos7420_clk_cmu_topc {
+	unsigned int	rsvd1[68];
+	unsigned int	bus0_pll_con[2];
+	unsigned int	rsvd2[2];
+	unsigned int	bus1_pll_con[2];
+	unsigned int	rsvd3[54];
+	unsigned int	mux_sel[6];
+	unsigned int	rsvd4[250];
+	unsigned int	div[4];
+};
+
+/* CMU TOP0 block device structure */
+struct exynos7420_clk_cmu_top0 {
+	unsigned int	rsvd0[128];
+	unsigned int	mux_sel[7];
+	unsigned int	rsvd1[261];
+	unsigned int	div_peric[5];
+};
+
+/**
+ * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
+ *
+ * @topc: base address of the memory mapped CMU TOPC controller.
+ * @fin_freq: frequency of the Oscillator clock.
+ * @sclk_bus0_pll_a: frequency of sclk_bus0_pll_a clock.
+ * @sclk_bus1_pll_a: frequency of sclk_bus1_pll_a clock.
+ */
+struct exynos7420_clk_topc_priv {
+	struct exynos7420_clk_cmu_topc *topc;
+	unsigned long fin_freq;
+	unsigned long sclk_bus0_pll_a;
+	unsigned long sclk_bus1_pll_a;
+};
+
+/**
+ * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
+ *
+ * @top0: base address of the memory mapped CMU TOP0 controller.
+ * @mout_top0_bus0_pll_half: frequency of mout_top0_bus0_pll_half clock
+ * @sclk_uart2: frequency of sclk_uart2 clock.
+ */
+struct exynos7420_clk_top0_priv {
+	struct exynos7420_clk_cmu_top0 *top0;
+	unsigned long mout_top0_bus0_pll_half;
+	unsigned long sclk_uart2;
+};
+
+static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+
+	switch (periph) {
+	case DOUT_SCLK_BUS0_PLL:
+	case SCLK_BUS0_PLL_A:
+	case SCLK_BUS0_PLL_B:
+		return priv->sclk_bus0_pll_a;
+	case DOUT_SCLK_BUS1_PLL:
+	case SCLK_BUS1_PLL_A:
+	case SCLK_BUS1_PLL_B:
+		return priv->sclk_bus1_pll_a;
+	default:
+		return 0;
+	}
+}
+
+static struct clk_ops exynos7420_clk_topc_ops = {
+	.get_periph_rate	= exynos7420_topc_get_periph_rate,
+};
+
+static int exynos7420_clk_topc_probe(struct udevice *dev)
+{
+	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_cmu_topc *topc;
+	struct udevice *clk_dev;
+	unsigned long rate;
+	fdt_addr_t base;
+	int ret;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	topc = (struct exynos7420_clk_cmu_topc *)base;
+	priv->topc = topc;
+
+	ret = clk_get_by_index(dev, 0, &clk_dev);
+	if (ret >= 0)
+		priv->fin_freq = clk_get_rate(clk_dev);
+
+	rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
+	if (readl(&topc->mux_sel[1]) & (1 << 16))
+		rate >>= 1;
+	rate /= DIVIDER(&topc->div[3], 0, 0xf);
+	priv->sclk_bus0_pll_a = rate;
+
+	rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
+			DIVIDER(&topc->div[3], 8, 0xf);
+	priv->sclk_bus1_pll_a = rate;
+
+	return 0;
+}
+
+static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
+
+	switch (periph) {
+	case CLK_SCLK_UART2:
+		return priv->mout_top0_bus0_pll_half /
+			DIVIDER(&top0->div_peric[3], 8, 0xf);
+	default:
+		return 0;
+	}
+}
+
+static struct clk_ops exynos7420_clk_top0_ops = {
+	.get_periph_rate	= exynos7420_top0_get_periph_rate,
+};
+
+static int exynos7420_clk_top0_probe(struct udevice *dev)
+{
+	struct exynos7420_clk_top0_priv *priv;
+	struct exynos7420_clk_cmu_top0 *top0;
+	struct udevice *clk_dev;
+	fdt_addr_t base;
+	int ret;
+
+	priv = dev_get_priv(dev);
+	if (!priv)
+		return -EINVAL;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	top0 = (struct exynos7420_clk_cmu_top0 *)base;
+	priv->top0 = top0;
+
+	ret = clk_get_by_index(dev, 1, &clk_dev);
+	if (ret >= 0) {
+		priv->mout_top0_bus0_pll_half =
+			clk_get_periph_rate(clk_dev, ret);
+		if (readl(&top0->mux_sel[1]) & (1 << 16))
+			priv->mout_top0_bus0_pll_half >>= 1;
+	}
+
+	return 0;
+}
+
+static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct udevice *clk_dev;
+	unsigned int ret;
+	unsigned long freq = 0;
+
+	switch (periph) {
+	case SCLK_UART2:
+		ret = clk_get_by_index(dev, 3, &clk_dev);
+		if (ret < 0)
+			return ret;
+		freq = clk_get_periph_rate(clk_dev, ret);
+		break;
+	}
+
+	return freq;
+}
+
+static struct clk_ops exynos7420_clk_peric1_ops = {
+	.get_periph_rate	= exynos7420_peric1_get_periph_rate,
+};
+
+static const struct udevice_id exynos7420_clk_topc_compat[] = {
+	{ .compatible = "samsung,exynos7-clock-topc" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_topc) = {
+	.name = "exynos7420-clock-topc",
+	.id = UCLASS_CLK,
+	.of_match = exynos7420_clk_topc_compat,
+	.probe = exynos7420_clk_topc_probe,
+	.priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+	.ops = &exynos7420_clk_topc_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id exynos7420_clk_top0_compat[] = {
+	{ .compatible = "samsung,exynos7-clock-top0" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_top0) = {
+	.name = "exynos7420-clock-top0",
+	.id = UCLASS_CLK,
+	.of_match = exynos7420_clk_top0_compat,
+	.probe = exynos7420_clk_top0_probe,
+	.priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+	.ops = &exynos7420_clk_top0_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id exynos7420_clk_peric1_compat[] = {
+	{ .compatible = "samsung,exynos7-clock-peric1" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_peric1) = {
+	.name = "exynos7420-clock-peric1",
+	.id = UCLASS_CLK,
+	.of_match = exynos7420_clk_peric1_compat,
+	.ops = &exynos7420_clk_peric1_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
new file mode 100644
index 0000000..27220c5
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.c
@@ -0,0 +1,33 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define PLL145X_MDIV_SHIFT	16
+#define PLL145X_MDIV_MASK	0x3ff
+#define PLL145X_PDIV_SHIFT	8
+#define PLL145X_PDIV_MASK	0x3f
+#define PLL145X_SDIV_SHIFT	0
+#define PLL145X_SDIV_MASK	0x7
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
+{
+	unsigned long pll_con1 = readl(con1);
+	unsigned long mdiv, sdiv, pdiv;
+	uint64_t fvco = fin_freq;
+
+	mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+	pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+	sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+	fvco *= mdiv;
+	do_div(fvco, (pdiv << sdiv));
+	return (unsigned long)fvco;
+}
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
new file mode 100644
index 0000000..631d035
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.h
@@ -0,0 +1,9 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
new file mode 100644
index 0000000..10c5586
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7420-clk.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define DOUT_SCLK_AUD_PLL		9
+#define FOUT_AUD_PLL			10
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define ACLK_CCORE_133			20
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define CLK_SCLK_SPI0			7
+#define CLK_SCLK_SPI1			8
+#define CLK_SCLK_SPI2			9
+#define CLK_SCLK_SPI3			10
+#define CLK_SCLK_SPI4			11
+#define CLK_SCLK_SPDIF			12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_ACLK_PERIC0_66		15
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define CLK_ACLK_FSYS0_200		9
+#define CLK_ACLK_FSYS1_200		10
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PCLK_SPI0			12
+#define PCLK_SPI1			13
+#define PCLK_SPI2			14
+#define PCLK_SPI3			15
+#define PCLK_SPI4			16
+#define SCLK_SPI0			17
+#define SCLK_SPI1			18
+#define SCLK_SPI2			19
+#define SCLK_SPI3			20
+#define SCLK_SPI4			21
+#define PCLK_I2S1			22
+#define PCLK_PCM1			23
+#define PCLK_SPDIF			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			26
+#define SCLK_SPDIF			27
+#define PERIC1_NR_CLK			28
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
+/* AUD */
+#define SCLK_I2S			1
+#define SCLK_PCM			2
+#define PCLK_I2S			3
+#define PCLK_PCM			4
+#define ACLK_ADMA			5
+#define AUD_NR_CLK			6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
-- 
cgit v0.10.2


From 5ab6c4df27c9188251ff43a536c90ede57ba48fe Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:10 +0530
Subject: serial: s5p: get the port id number from the alias of the device node

The port id, if not specified in the device node, can be obtained from
the alias of the device node listed in the aliases node.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index feba467..8590dfd 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -174,8 +174,8 @@ static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 
 	plat->reg = (struct s5p_uart *)addr;
-	plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
-
+	plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					"id", dev->seq);
 	return 0;
 }
 
-- 
cgit v0.10.2


From cf75cdf96ef288410222737eca98cf28cdbafbe2 Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:11 +0530
Subject: serial: s5p: use clock api to get clock rate

On Exynos platforms that support clock driver API, allow the driver to
use clock api get the SCLK clock rate.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 8590dfd..cb55c5a 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -17,6 +17,7 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/uart.h>
 #include <serial.h>
+#include <clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -90,7 +91,19 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct s5p_serial_platdata *plat = dev->platdata;
 	struct s5p_uart *const uart = plat->reg;
-	u32 uclk = get_uart_clk(plat->port_id);
+	u32 uclk;
+
+#ifdef CONFIG_CLK_EXYNOS
+	struct udevice *clk_dev;
+	u32 ret;
+
+	ret = clk_get_by_index(dev, 1, &clk_dev);
+	if (ret < 0)
+		return ret;
+	uclk = clk_get_periph_rate(clk_dev, ret);
+#else
+	uclk = get_uart_clk(plat->port_id);
+#endif
 
 	s5p_serial_baud(uart, uclk, baudrate);
 
-- 
cgit v0.10.2


From 36aa893775b809ea3b508a225992311582f6379a Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:12 +0530
Subject: arm: exynos: realign the code to allow support for newer 64-bit
 platforms

The existing Exynos 32-bit platform support needs to be realigned in
order to support newer 64-bit Exynos platforms. The driver model will
be utlized for drivers on the 64-bit Exynos platforms and so some of
the older platform support code would not be required for the newer
64-bit Exynos platforms.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 729b181..3eb6e5d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
-	select CPU_V7
 	select DM
 	select DM_SPI_FLASH
 	select DM_SERIAL
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index a6a7597..28a6a60 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -1,9 +1,32 @@
 if ARCH_EXYNOS
 
 choice
-	prompt "EXYNOS board select"
+	prompt "EXYNOS architecture type select"
 	optional
 
+config ARCH_EXYNOS4
+	bool "Exynos4 SoC family"
+	select CPU_V7
+	help
+	  Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
+	  are multiple SoCs in this family including Exynos4210, Exynos4412,
+	  and Exynos4212.
+
+config ARCH_EXYNOS5
+	bool "Exynos5 SoC family"
+	select CPU_V7
+	help
+	  Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
+	  Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
+	  in this family including Exynos5250, Exynos5420 and Exynos5800.
+
+endchoice
+
+if ARCH_EXYNOS4
+
+choice
+	prompt "EXYNOS4 board select"
+
 config TARGET_SMDKV310
 	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
@@ -25,6 +48,14 @@ config TARGET_TRATS2
 config TARGET_ODROID
 	bool "Exynos4412 Odroid board"
 
+endchoice
+endif
+
+if ARCH_EXYNOS5
+
+choice
+	prompt "EXYNOS5 board select"
+
 config TARGET_ODROID_XU3
 	bool "Exynos5422 Odroid board"
 	select OF_CONTROL
@@ -68,6 +99,7 @@ config TARGET_PEACH_PIT
 	select OF_CONTROL
 
 endchoice
+endif
 
 config SYS_SOC
 	default "exynos"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8542f89..f3c07b7 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -5,7 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y	+= soc.o
+obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
 
 obj-$(CONFIG_EXYNOS5420)	+= sec_boot.o
 
@@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y	+= spl_boot.o
+obj-y	+= spl_boot.o tzpc.o
 obj-y	+= lowlevel_init.o
 endif
diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index 14a1692..f12e3d6 100644
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
 IS_EXYNOS_TYPE(exynos5422, 0x5422)
 
 #define SAMSUNG_BASE(device, base)				\
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
 	samsung_get_base_##device(void) \
 {								\
 	if (cpu_is_exynos4()) {				\
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 7fc8e61..81363bd 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
 };
 
 struct gpio_info {
-	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned long reg_addr;	/* Address of register for this part */
 	unsigned int max_gpio;	/* Maximum GPIO in this part */
 };
 
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 0f116b1..737a8dd 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -11,7 +11,9 @@
 
 void reset_cpu(ulong addr)
 {
+#ifdef CONFIG_CPU_V7
 	writel(0x1, samsung_get_base_swreset());
+#endif
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 0cd529e..a026fd6 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_ARNDALE=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 8995cc2..c7708f1 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_ODROID_XU3=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index ff3b339..76ab144 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_ODROID=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index b1740dc..6ad01af 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_ORIGEN=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
 CONFIG_SPL=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index c8c74c0..ce07052 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_PEACH_PI=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index c5fbf8c..4479fe8 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_PEACH_PIT=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 638b728..5eb7a40 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_S5PC210_UNIVERSAL=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 5d88391..7fe410d 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SMDK5250=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 40de7c1..23b9c1e 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SMDK5420=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index b8638e2..5ba6523 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_SMDKV310=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
 CONFIG_SPL=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 97133df..77b97a3 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SNOW=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index b720e04..d3b174a 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SPRING=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index c2ed8c8..1362ffb 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_TRATS2=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 46bfc4e..525bbef 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_TRATS=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
 CONFIG_FIT=y
-- 
cgit v0.10.2


From e39448e8be8389f5ddeabae0ec9c6a3b7b8a2ca6 Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:13 +0530
Subject: arm: exynos: add support for Exynos7420 SoC

Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
and four Cortex-A53 CPUs and includes various peripheral controllers.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi
new file mode 100644
index 0000000..b398021
--- /dev/null
+++ b/arch/arm/dts/exynos7420.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+	compatible = "samsung,exynos7420";
+
+	fin_pll: xxti {
+		compatible = "fixed-clock";
+		clock-output-names = "fin_pll";
+		u-boot,dm-pre-reloc;
+		#clock-cells = <0>;
+	};
+
+	clock_topc: clock-controller@10570000 {
+		compatible = "samsung,exynos7-clock-topc";
+		reg = <0x10570000 0x10000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>;
+		clock-names = "fin_pll";
+	};
+
+	clock_top0: clock-controller@105d0000 {
+		compatible = "samsung,exynos7-clock-top0";
+		reg = <0x105d0000 0xb000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+			 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+			 <&clock_topc DOUT_SCLK_CC_PLL>,
+			 <&clock_topc DOUT_SCLK_MFC_PLL>;
+		clock-names = "fin_pll", "dout_sclk_bus0_pll",
+			      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+			      "dout_sclk_mfc_pll";
+	};
+
+	clock_peric1: clock-controller@14c80000 {
+		compatible = "samsung,exynos7-clock-peric1";
+		reg = <0x14c80000 0xd00>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+			 <&clock_top0 CLK_SCLK_UART1>,
+			 <&clock_top0 CLK_SCLK_UART2>,
+			 <&clock_top0 CLK_SCLK_UART3>;
+		clock-names = "fin_pll", "dout_aclk_peric1_66",
+			      "sclk_uart1", "sclk_uart2", "sclk_uart3";
+	};
+
+	pinctrl@13470000 {
+		compatible = "samsung,exynos7420-pinctrl";
+		reg = <0x13470000 0x1000>;
+		u-boot,dm-pre-reloc;
+
+		serial2_bus: serial2-bus {
+			samsung,pins = "gpd1-4", "gpd1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	serial@14C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x14C30000 0x100>;
+		u-boot,dm-pre-reloc;
+		clocks = <&clock_peric1 PCLK_UART2>,
+			 <&clock_peric1 SCLK_UART2>;
+		clock-names = "uart", "clk_uart_baud0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&serial2_bus>;
+	};
+};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 28a6a60..0a6cb33 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -20,6 +20,14 @@ config ARCH_EXYNOS5
 	  Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
 	  in this family including Exynos5250, Exynos5420 and Exynos5800.
 
+config ARCH_EXYNOS7
+	bool "Exynos7 SoC family"
+	select ARM64
+	help
+	  Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
+	  Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
+	  multiple SoCs in this family including Exynos7420.
+
 endchoice
 
 if ARCH_EXYNOS4
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f3c07b7..0cc6c32 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -7,6 +7,7 @@
 
 obj-y	+= soc.o
 obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
+obj-$(CONFIG_ARM64)	+= mmu-arm64.o
 
 obj-$(CONFIG_EXYNOS5420)	+= sec_boot.o
 
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
new file mode 100644
index 0000000..ba6d99d
--- /dev/null
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+	{
+		.base	= 0x10000000UL,
+		.size	= 0x10000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		.base	= 0x40000000UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* List terminator */
+		.base	= 0,
+		.size	= 0,
+		.attrs	= 0,
+	},
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 737a8dd..f9c7468 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -23,3 +23,11 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+	armv8_switch_to_el2();
+	armv8_switch_to_el1();
+}
+#endif
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
new file mode 100644
index 0000000..c6a756d
--- /dev/null
+++ b/include/configs/espresso7420.h
@@ -0,0 +1,34 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define CONFIG_SPL_STACK		CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING	" for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif	/* __CONFIG_ESPRESSO7420_H */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
new file mode 100644
index 0000000..9e03962
--- /dev/null
+++ b/include/configs/exynos7420-common.h
@@ -0,0 +1,113 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420		/* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		1024	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY		24000000
+
+/* Device Tree */
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE		0x02100000
+#define CONFIG_IRAM_SIZE		0x58000
+#define CONFIG_IRAM_END			(CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT		0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x43300000\0" \
+	"scriptaddr=0x50000000\0" \
+	"pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS
+
+#endif	/* __CONFIG_EXYNOS7420_COMMON_H */
-- 
cgit v0.10.2


From 6c15a2a996214574e8145bff69d110a302edf277 Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Sat, 23 Apr 2016 22:18:14 +0530
Subject: board: samsung: add initial Espresso7420 board support

Espresso7420 is a development/evaluation board for Exynos7420 SoC. It
includes multiple onboard compoments (EMMC/Codec) and various
interconnects (USB/HDMI).

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d1f8e22..da25715 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5420-peach-pit.dtb \
 	exynos5800-peach-pi.dtb \
 	exynos5422-odroidxu3.dtb
+dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-firefly.dtb \
 	rk3288-jerry.dtb \
diff --git a/arch/arm/dts/exynos7420-espresso7420.dts b/arch/arm/dts/exynos7420-espresso7420.dts
new file mode 100644
index 0000000..f17a848
--- /dev/null
+++ b/arch/arm/dts/exynos7420-espresso7420.dts
@@ -0,0 +1,24 @@
+/*
+ * Samsung Espresso7420 board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "exynos7420.dtsi"
+/ {
+	model = "Samsung Espresso7420 board based on Exynos7420";
+	compatible = "samsung,espresso7420", "samsung,exynos7420";
+
+	aliases {
+		serial2 = "/serial@14C30000";
+		console = "/serial@14C30000";
+		pinctrl0 = "/pinctrl@13470000";
+	};
+};
+
+&fin_pll {
+	clock-frequency = <24000000>;
+};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0a6cb33..c25fcf3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -109,6 +109,24 @@ config TARGET_PEACH_PIT
 endchoice
 endif
 
+if ARCH_EXYNOS7
+
+choice
+	prompt "EXYNOS7 board select"
+
+config  TARGET_ESPRESSO7420
+	bool "ESPRESSO7420 board"
+	select ARM64
+	select SUPPORT_SPL
+	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
+	select PINCTRL
+	select PINCTRL_EXYNOS7420
+	select CLK_EXYNOS
+
+endchoice
+endif
+
 config SYS_SOC
 	default "exynos"
 
@@ -121,5 +139,6 @@ source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"
 source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"
+source "board/samsung/espresso7420/Kconfig"
 
 endif
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 1334c22..7995174 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -27,6 +27,8 @@
 #include <usb.h>
 #include <dwc3-uboot.h>
 #include <samsung/misc.h>
+#include <dm/pinctrl.h>
+#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -97,7 +99,7 @@ int board_init(void)
 int dram_init(void)
 {
 	unsigned int i;
-	u32 addr;
+	unsigned long addr;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
@@ -109,7 +111,7 @@ int dram_init(void)
 void dram_init_banksize(void)
 {
 	unsigned int i;
-	u32 addr, size;
+	unsigned long addr, size;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
@@ -122,6 +124,7 @@ void dram_init_banksize(void)
 
 static int board_uart_init(void)
 {
+#ifndef CONFIG_PINCTRL_EXYNOS
 	int err, uart_id, ret = 0;
 
 	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
@@ -133,6 +136,9 @@ static int board_uart_init(void)
 		}
 	}
 	return ret;
+#else
+	return 0;
+#endif
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig
new file mode 100644
index 0000000..62251c5
--- /dev/null
+++ b/board/samsung/espresso7420/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_ESPRESSO7420
+
+config SYS_BOARD
+	default "espresso7420"
+	help
+	  Espresso7420 is a development/evaluation board for Exynos7420 SoC.
+	  It includes multiple onboard compoments (EMMC/Codec) and various
+	  interconnects (USB/HDMI).
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "espresso7420"
+
+endif
diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
new file mode 100644
index 0000000..aaebc4c
--- /dev/null
+++ b/board/samsung/espresso7420/MAINTAINERS
@@ -0,0 +1,5 @@
+ESPRESSO7420 Board
+M:	Thomas Abraham <thomas.ab@samsung.com>
+S:	Maintained
+F:	board/samsung/espresso7420/
+F:	include/configs/espresso7420.h
diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
new file mode 100644
index 0000000..d514dc2
--- /dev/null
+++ b/board/samsung/espresso7420/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y	+= espresso7420.o
+endif
diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c
new file mode 100644
index 0000000..04a83bc
--- /dev/null
+++ b/board/samsung/espresso7420/espresso7420.c
@@ -0,0 +1,16 @@
+/*
+ * Espresso7420 board file
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int exynos_init(void)
+{
+	return 0;
+}
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
new file mode 100644
index 0000000..0fe2759
--- /dev/null
+++ b/configs/espresso7420_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS7=y
+CONFIG_TARGET_ESPRESSO7420=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_PROMPT="ESPRESSO7420 # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
-- 
cgit v0.10.2


From 08a7aa1e5be7059d680fedf0a885655a895f638e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:38 -0700
Subject: exynos: video: Move driver files into their own directory

Move all the exynos video drivers into one place for ease of maintenance.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 2fd0891..3f045fe 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -25,11 +25,6 @@ obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
-obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
-obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
-obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
-				exynos_mipi_dsi_lowlevel.o
-obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
 obj-$(CONFIG_L5F31188) += l5f31188.o
@@ -68,6 +63,7 @@ obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
+obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 
 obj-y += bridge/
diff --git a/drivers/video/exynos/Makefile b/drivers/video/exynos/Makefile
new file mode 100644
index 0000000..d4bdf32
--- /dev/null
+++ b/drivers/video/exynos/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
+obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
+obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
+				exynos_mipi_dsi_lowlevel.o
+obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
new file mode 100644
index 0000000..0d5d090
--- /dev/null
+++ b/drivers/video/exynos/exynos_dp.c
@@ -0,0 +1,961 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <linux/compat.h>
+#include <linux/err.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/dp.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+
+#include "exynos_dp_lowlevel.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __exynos_set_dp_phy(unsigned int onoff)
+{
+}
+void exynos_set_dp_phy(unsigned int onoff)
+	__attribute__((weak, alias("__exynos_set_dp_phy")));
+
+static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
+{
+	disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
+		disp_info->h_back_porch + disp_info->h_front_porch;
+	disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
+		disp_info->v_back_porch + disp_info->v_front_porch;
+
+	return;
+}
+
+static int exynos_dp_init_dp(void)
+{
+	int ret;
+	exynos_dp_reset();
+
+	/* SW defined function Normal operation */
+	exynos_dp_enable_sw_func(DP_ENABLE);
+
+	ret = exynos_dp_init_analog_func();
+	if (ret != EXYNOS_DP_SUCCESS)
+		return ret;
+
+	exynos_dp_init_hpd();
+	exynos_dp_init_aux();
+
+	return ret;
+}
+
+static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+{
+	int i;
+	unsigned char sum = 0;
+
+	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
+		sum = sum + edid_data[i];
+
+	return sum;
+}
+
+static unsigned int exynos_dp_read_edid(void)
+{
+	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned int extend_block = 0;
+	unsigned char sum;
+	unsigned char test_vector;
+	int retval;
+
+	/*
+	 * EDID device address is 0x50.
+	 * However, if necessary, you must have set upper address
+	 * into E-EDID in I2C device, 0x30.
+	 */
+
+	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
+	exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
+			&extend_block);
+
+	if (extend_block > 0) {
+		printf("DP EDID data includes a single extension!\n");
+
+		/* Read EDID data */
+		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+						EDID_HEADER_PATTERN,
+						EDID_BLOCK_LENGTH,
+						&edid[EDID_HEADER_PATTERN]);
+		if (retval != 0) {
+			printf("DP EDID Read failed!\n");
+			return -1;
+		}
+		sum = exynos_dp_calc_edid_check_sum(edid);
+		if (sum != 0) {
+			printf("DP EDID bad checksum!\n");
+			return -1;
+		}
+
+		/* Read additional EDID data */
+		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+				EDID_BLOCK_LENGTH,
+				EDID_BLOCK_LENGTH,
+				&edid[EDID_BLOCK_LENGTH]);
+		if (retval != 0) {
+			printf("DP EDID Read failed!\n");
+			return -1;
+		}
+		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		if (sum != 0) {
+			printf("DP EDID bad checksum!\n");
+			return -1;
+		}
+
+		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+					&test_vector);
+		if (test_vector & DPCD_TEST_EDID_READ) {
+			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+				DPCD_TEST_EDID_CHECKSUM_WRITE);
+		}
+	} else {
+		debug("DP EDID data does not include any extensions.\n");
+
+		/* Read EDID data */
+		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+				EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH,
+				&edid[EDID_HEADER_PATTERN]);
+
+		if (retval != 0) {
+			printf("DP EDID Read failed!\n");
+			return -1;
+		}
+		sum = exynos_dp_calc_edid_check_sum(edid);
+		if (sum != 0) {
+			printf("DP EDID bad checksum!\n");
+			return -1;
+		}
+
+		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+			&test_vector);
+		if (test_vector & DPCD_TEST_EDID_READ) {
+			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+				edid[EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+				DPCD_TEST_EDID_CHECKSUM_WRITE);
+		}
+	}
+
+	debug("DP EDID Read success!\n");
+
+	return 0;
+}
+
+static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
+{
+	unsigned char buf[12];
+	unsigned int ret;
+	unsigned char temp;
+	unsigned char retry_cnt;
+	unsigned char dpcd_rev[16];
+	unsigned char lane_bw[16];
+	unsigned char lane_cnt[16];
+
+	memset(dpcd_rev, 0, 16);
+	memset(lane_bw, 0, 16);
+	memset(lane_cnt, 0, 16);
+	memset(buf, 0, 12);
+
+	retry_cnt = 5;
+	while (retry_cnt) {
+		/* Read DPCD 0x0000-0x000b */
+		ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
+				buf);
+		if (ret != EXYNOS_DP_SUCCESS) {
+			if (retry_cnt == 0) {
+				printf("DP read_byte_from_dpcd() failed\n");
+				return ret;
+			}
+			retry_cnt--;
+		} else
+			break;
+	}
+
+	/* */
+	temp = buf[DPCD_DPCD_REV];
+	if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
+		edp_info->dpcd_rev = temp;
+	else {
+		printf("DP Wrong DPCD Rev : %x\n", temp);
+		return -ENODEV;
+	}
+
+	temp = buf[DPCD_MAX_LINK_RATE];
+	if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
+		edp_info->lane_bw = temp;
+	else {
+		printf("DP Wrong MAX LINK RATE : %x\n", temp);
+		return -EINVAL;
+	}
+
+	/* Refer VESA Display Port Standard Ver1.1a Page 120 */
+	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
+		temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
+		if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
+			edp_info->dpcd_efc = 1;
+		else
+			edp_info->dpcd_efc = 0;
+	} else {
+		temp = buf[DPCD_MAX_LANE_COUNT];
+		edp_info->dpcd_efc = 0;
+	}
+
+	if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
+			temp == DP_LANE_CNT_4) {
+		edp_info->lane_cnt = temp;
+	} else {
+		printf("DP Wrong MAX LANE COUNT : %x\n", temp);
+		return -EINVAL;
+	}
+
+	ret = exynos_dp_read_edid();
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP exynos_dp_read_edid() failed\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static void exynos_dp_init_training(void)
+{
+	/*
+	 * MACRO_RST must be applied after the PLL_LOCK to avoid
+	 * the DP inter pair skew issue for at least 10 us
+	 */
+	exynos_dp_reset_macro();
+
+	/* All DP analog module power up */
+	exynos_dp_set_analog_power_down(POWER_ALL, 0);
+}
+
+static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
+{
+	unsigned char buf[5];
+	unsigned int ret = 0;
+
+	debug("DP: %s was called\n", __func__);
+
+	edp_info->lt_info.lt_status = DP_LT_CR;
+	edp_info->lt_info.ep_loop = 0;
+	edp_info->lt_info.cr_loop[0] = 0;
+	edp_info->lt_info.cr_loop[1] = 0;
+	edp_info->lt_info.cr_loop[2] = 0;
+	edp_info->lt_info.cr_loop[3] = 0;
+
+		/* Set sink to D0 (Sink Not Ready) mode. */
+		ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
+				DPCD_SET_POWER_STATE_D0);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP write_dpcd_byte failed\n");
+		return ret;
+	}
+
+	/* Set link rate and count as you want to establish */
+	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
+	exynos_dp_set_lane_count(edp_info->lane_cnt);
+
+	/* Setup RX configuration */
+	buf[0] = edp_info->lane_bw;
+	buf[1] = edp_info->lane_cnt;
+
+	ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
+			buf);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP write_dpcd_byte failed\n");
+		return ret;
+	}
+
+	exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
+			edp_info->lane_cnt);
+
+	/* Set training pattern 1 */
+	exynos_dp_set_training_pattern(TRAINING_PTN1);
+
+	/* Set RX training pattern */
+	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
+
+	buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+	buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+	buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+
+	ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+			5, buf);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP write_dpcd_byte failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_training_pattern_dis(void)
+{
+	unsigned int ret = EXYNOS_DP_SUCCESS;
+
+	exynos_dp_set_training_pattern(DP_NONE);
+
+	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+			DPCD_TRAINING_PATTERN_DISABLED);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP request_link_training_req failed\n");
+		return -EAGAIN;
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
+{
+	unsigned char data;
+	unsigned int ret = EXYNOS_DP_SUCCESS;
+
+	ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
+			&data);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP read_from_dpcd failed\n");
+		return -EAGAIN;
+	}
+
+	if (enable)
+		data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
+	else
+		data = DPCD_LN_COUNT_SET(data);
+
+	ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
+			data);
+	if (ret != EXYNOS_DP_SUCCESS) {
+			printf("DP write_to_dpcd failed\n");
+			return -EAGAIN;
+
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
+{
+	unsigned int ret = EXYNOS_DP_SUCCESS;
+
+	ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP rx_enhance_mode failed\n");
+		return -EAGAIN;
+	}
+
+	exynos_dp_enable_enhanced_mode(enhance_mode);
+
+	return ret;
+}
+
+static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
+		unsigned char *status)
+{
+	unsigned int ret, i;
+	unsigned char buf[2];
+	unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
+	unsigned char shift_val[DP_LANE_CNT_4] = {0,};
+
+	shift_val[0] = 0;
+	shift_val[1] = 4;
+	shift_val[2] = 0;
+	shift_val[3] = 4;
+
+	ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP read lane status failed\n");
+		return ret;
+	}
+
+	for (i = 0; i < edp_info->lane_cnt; i++) {
+		lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
+		if (lane_stat[0] != lane_stat[i]) {
+			printf("Wrong lane status\n");
+			return -EINVAL;
+		}
+	}
+
+	*status = lane_stat[0];
+
+	return ret;
+}
+
+static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
+		unsigned char *sw, unsigned char *em)
+{
+	unsigned int ret = EXYNOS_DP_SUCCESS;
+	unsigned char buf;
+	unsigned int dpcd_addr;
+	unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
+
+	/* lane_num value is used as array index, so this range 0 ~ 3 */
+	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
+
+	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP read adjust request failed\n");
+		return -EAGAIN;
+	}
+
+	*sw = ((buf >> shift_val[lane_num]) & 0x03);
+	*em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
+
+	return ret;
+}
+
+static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
+{
+	int ret;
+
+	ret = exynos_dp_training_pattern_dis();
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP training_pattern_disable() failed\n");
+		edp_info->lt_info.lt_status = DP_LT_FAIL;
+	}
+
+	ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP set_enhanced_mode() failed\n");
+		edp_info->lt_info.lt_status = DP_LT_FAIL;
+	}
+
+	return ret;
+}
+
+static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
+{
+	int ret;
+
+	if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+		edp_info->lane_bw = DP_LANE_BW_1_62;
+		printf("DP Change lane bw to 1.62Gbps\n");
+		edp_info->lt_info.lt_status = DP_LT_START;
+		ret = EXYNOS_DP_SUCCESS;
+	} else {
+		ret = exynos_dp_training_pattern_dis();
+		if (ret != EXYNOS_DP_SUCCESS)
+			printf("DP training_patter_disable() failed\n");
+
+		ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+		if (ret != EXYNOS_DP_SUCCESS)
+			printf("DP set_enhanced_mode() failed\n");
+
+		edp_info->lt_info.lt_status = DP_LT_FAIL;
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
+							*edp_info)
+{
+	unsigned int ret = EXYNOS_DP_SUCCESS;
+	unsigned char lane_stat;
+	unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
+	unsigned int i;
+	unsigned char adj_req_sw;
+	unsigned char adj_req_em;
+	unsigned char buf[5];
+
+	debug("DP: %s was called\n", __func__);
+	mdelay(1);
+
+	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	if (ret != EXYNOS_DP_SUCCESS) {
+			printf("DP read lane status failed\n");
+			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			return ret;
+	}
+
+	if (lane_stat & DP_LANE_STAT_CR_DONE) {
+		debug("DP clock Recovery training succeed\n");
+		exynos_dp_set_training_pattern(TRAINING_PTN2);
+
+		for (i = 0; i < edp_info->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
+					&adj_req_em);
+			if (ret != EXYNOS_DP_SUCCESS) {
+				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				return ret;
+			}
+
+			lt_ctl_val[i] = 0;
+			lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
+
+			if ((adj_req_sw == VOLTAGE_LEVEL_3)
+				|| (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
+				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
+					MAX_PRE_EMPHASIS_REACH_3;
+			}
+			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+		}
+
+		buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
+		buf[1] = lt_ctl_val[0];
+		buf[2] = lt_ctl_val[1];
+		buf[3] = lt_ctl_val[2];
+		buf[4] = lt_ctl_val[3];
+
+		ret = exynos_dp_write_bytes_to_dpcd(
+				DPCD_TRAINING_PATTERN_SET, 5, buf);
+		if (ret != EXYNOS_DP_SUCCESS) {
+			printf("DP write training pattern1 failed\n");
+			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			return ret;
+		} else
+			edp_info->lt_info.lt_status = DP_LT_ET;
+	} else {
+		for (i = 0; i < edp_info->lane_cnt; i++) {
+			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
+				ret = exynos_dp_read_dpcd_adj_req(i,
+						&adj_req_sw, &adj_req_em);
+			if (ret != EXYNOS_DP_SUCCESS) {
+				printf("DP read adj req failed\n");
+				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				return ret;
+			}
+
+			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
+					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
+				ret = exynos_dp_reduce_link_rate(edp_info);
+
+			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
+						adj_req_sw) &&
+				(PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
+						adj_req_em)) {
+				edp_info->lt_info.cr_loop[i]++;
+				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
+					ret = exynos_dp_reduce_link_rate(
+							edp_info);
+			}
+
+			lt_ctl_val[i] = 0;
+			lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
+
+			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
+					(adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
+				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
+					MAX_PRE_EMPHASIS_REACH_3;
+			}
+			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+		}
+
+		ret = exynos_dp_write_bytes_to_dpcd(
+				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
+		if (ret != EXYNOS_DP_SUCCESS) {
+			printf("DP write training pattern2 failed\n");
+			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
+		*edp_info)
+{
+	unsigned int ret = EXYNOS_DP_SUCCESS;
+	unsigned char lane_stat, adj_req_sw, adj_req_em, i;
+	unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
+	unsigned char interlane_aligned = 0;
+	unsigned char f_bw;
+	unsigned char f_lane_cnt;
+	unsigned char sink_stat;
+
+	mdelay(1);
+
+	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP read lane status failed\n");
+		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		return ret;
+	}
+
+	debug("DP lane stat : %x\n", lane_stat);
+
+	if (lane_stat & DP_LANE_STAT_CR_DONE) {
+		ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
+				&sink_stat);
+		if (ret != EXYNOS_DP_SUCCESS) {
+			edp_info->lt_info.lt_status = DP_LT_FAIL;
+
+			return ret;
+		}
+
+		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
+
+		for (i = 0; i < edp_info->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(i,
+					&adj_req_sw, &adj_req_em);
+			if (ret != EXYNOS_DP_SUCCESS) {
+				printf("DP read adj req 1 failed\n");
+				edp_info->lt_info.lt_status = DP_LT_FAIL;
+
+				return ret;
+			}
+
+			lt_ctl_val[i] = 0;
+			lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
+
+			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
+				(adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
+				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
+				lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
+			}
+		}
+
+		if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
+			(lane_stat&DP_LANE_STAT_SYM_LOCK))
+			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
+			debug("DP Equalizer training succeed\n");
+
+			f_bw = exynos_dp_get_link_bandwidth();
+			f_lane_cnt = exynos_dp_get_lane_count();
+
+			debug("DP final BandWidth : %x\n", f_bw);
+			debug("DP final Lane Count : %x\n", f_lane_cnt);
+
+			edp_info->lt_info.lt_status = DP_LT_FINISHED;
+
+			exynos_dp_equalizer_err_link(edp_info);
+
+		} else {
+			edp_info->lt_info.ep_loop++;
+
+			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
+				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+					ret = exynos_dp_reduce_link_rate(
+							edp_info);
+				} else {
+					edp_info->lt_info.lt_status =
+								DP_LT_FAIL;
+					exynos_dp_equalizer_err_link(edp_info);
+				}
+			} else {
+				for (i = 0; i < edp_info->lane_cnt; i++)
+					exynos_dp_set_lanex_pre_emphasis(
+							lt_ctl_val[i], i);
+
+				ret = exynos_dp_write_bytes_to_dpcd(
+					DPCD_TRAINING_LANE0_SET,
+					4, lt_ctl_val);
+				if (ret != EXYNOS_DP_SUCCESS) {
+					printf("DP set lt pattern failed\n");
+					edp_info->lt_info.lt_status =
+								DP_LT_FAIL;
+					exynos_dp_equalizer_err_link(edp_info);
+				}
+			}
+		}
+	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+		ret = exynos_dp_reduce_link_rate(edp_info);
+	} else {
+		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		exynos_dp_equalizer_err_link(edp_info);
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
+{
+	unsigned int ret = 0;
+	int training_finished;
+
+	/* Turn off unnecessary lane */
+	if (edp_info->lane_cnt == 1)
+		exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
+
+	training_finished = 0;
+
+	edp_info->lt_info.lt_status = DP_LT_START;
+
+	/* Process here */
+	while (!training_finished) {
+		switch (edp_info->lt_info.lt_status) {
+		case DP_LT_START:
+			ret = exynos_dp_link_start(edp_info);
+			if (ret != EXYNOS_DP_SUCCESS) {
+				printf("DP LT:link start failed\n");
+				return ret;
+			}
+			break;
+		case DP_LT_CR:
+			ret = exynos_dp_process_clock_recovery(edp_info);
+			if (ret != EXYNOS_DP_SUCCESS) {
+				printf("DP LT:clock recovery failed\n");
+				return ret;
+			}
+			break;
+		case DP_LT_ET:
+			ret = exynos_dp_process_equalizer_training(edp_info);
+			if (ret != EXYNOS_DP_SUCCESS) {
+				printf("DP LT:equalizer training failed\n");
+				return ret;
+			}
+			break;
+		case DP_LT_FINISHED:
+			training_finished = 1;
+			break;
+		case DP_LT_FAIL:
+			return -1;
+		}
+	}
+
+	return ret;
+}
+
+static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
+{
+	unsigned int ret;
+
+	exynos_dp_init_training();
+
+	ret = exynos_dp_sw_link_training(edp_info);
+	if (ret != EXYNOS_DP_SUCCESS)
+		printf("DP dp_sw_link_training() failed\n");
+
+	return ret;
+}
+
+static void exynos_dp_enable_scramble(unsigned int enable)
+{
+	unsigned char data;
+
+	if (enable) {
+		exynos_dp_enable_scrambling(DP_ENABLE);
+
+		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
+				&data);
+		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+			(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
+	} else {
+		exynos_dp_enable_scrambling(DP_DISABLE);
+		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
+				&data);
+		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+			(u8)(data | DPCD_SCRAMBLING_DISABLED));
+	}
+}
+
+static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
+{
+	unsigned int ret = 0;
+	unsigned int retry_cnt;
+
+	mdelay(1);
+
+	if (edp_info->video_info.master_mode) {
+		printf("DP does not support master mode\n");
+		return -ENODEV;
+	} else {
+		/* debug slave */
+		exynos_dp_config_video_slave_mode(&edp_info->video_info);
+	}
+
+	exynos_dp_set_video_color_format(&edp_info->video_info);
+
+	if (edp_info->video_info.bist_mode) {
+		if (exynos_dp_config_video_bist(edp_info) != 0)
+			return -1;
+	}
+
+	ret = exynos_dp_get_pll_lock_status();
+	if (ret != PLL_LOCKED) {
+		printf("DP PLL is not locked yet\n");
+		return -EIO;
+	}
+
+	if (edp_info->video_info.master_mode == 0) {
+		retry_cnt = 10;
+		while (retry_cnt) {
+			ret = exynos_dp_is_slave_video_stream_clock_on();
+			if (ret != EXYNOS_DP_SUCCESS) {
+				if (retry_cnt == 0) {
+					printf("DP stream_clock_on failed\n");
+					return ret;
+				}
+				retry_cnt--;
+				mdelay(1);
+			} else
+				break;
+		}
+	}
+
+	/* Set to use the register calculated M/N video */
+	exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
+
+	/* For video bist, Video timing must be generated by register */
+	exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
+
+	/* Enable video bist */
+	if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
+		edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
+		edp_info->video_info.bist_pattern != COLOR_SQUARE)
+		exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
+	else
+		exynos_dp_enable_video_bist(DP_DISABLE);
+
+	/* Disable video mute */
+	exynos_dp_enable_video_mute(DP_DISABLE);
+
+	/* Configure video Master or Slave mode */
+	exynos_dp_enable_video_master(edp_info->video_info.master_mode);
+
+	/* Enable video */
+	exynos_dp_start_video();
+
+	if (edp_info->video_info.master_mode == 0) {
+		retry_cnt = 100;
+		while (retry_cnt) {
+			ret = exynos_dp_is_video_stream_on();
+			if (ret != EXYNOS_DP_SUCCESS) {
+				if (retry_cnt == 0) {
+					printf("DP Timeout of video stream\n");
+					return ret;
+				}
+				retry_cnt--;
+				mdelay(5);
+			} else
+				break;
+		}
+	}
+
+	return ret;
+}
+
+int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
+{
+	unsigned int node = fdtdec_next_compatible(blob, 0,
+						COMPAT_SAMSUNG_EXYNOS5_DP);
+	if (node <= 0) {
+		debug("exynos_dp: Can't get device node for dp\n");
+		return -ENODEV;
+	}
+
+	edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
+							"samsung,h-res", 0);
+	edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
+						"samsung,h-sync-width", 0);
+	edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
+						"samsung,h-back-porch", 0);
+	edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
+						"samsung,h-front-porch", 0);
+	edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
+						"samsung,v-res", 0);
+	edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
+						"samsung,v-sync-width", 0);
+	edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
+						"samsung,v-back-porch", 0);
+	edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
+						"samsung,v-front-porch", 0);
+	edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
+						"samsung,v-sync-rate", 0);
+
+	edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
+						"samsung,lt-status", 0);
+
+	edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
+						"samsung,master-mode", 0);
+	edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
+						"samsung,bist-mode", 0);
+	edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
+						"samsung,bist-pattern", 0);
+	edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
+						"samsung,h-sync-polarity", 0);
+	edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
+						"samsung,v-sync-polarity", 0);
+	edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
+						"samsung,interlaced", 0);
+	edp_info->video_info.color_space = fdtdec_get_int(blob, node,
+						"samsung,color-space", 0);
+	edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
+						"samsung,dynamic-range", 0);
+	edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
+						"samsung,ycbcr-coeff", 0);
+	edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
+						"samsung,color-depth", 0);
+	return 0;
+}
+
+unsigned int exynos_init_dp(void)
+{
+	unsigned int ret;
+	struct edp_device_info *edp_info;
+
+	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
+	if (!edp_info) {
+		debug("failed to allocate edp device object.\n");
+		return -EFAULT;
+	}
+
+	if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
+		debug("unable to parse DP DT node\n");
+
+	exynos_dp_set_base_addr();
+
+	exynos_dp_disp_info(&edp_info->disp_info);
+
+	exynos_set_dp_phy(1);
+
+	ret = exynos_dp_init_dp();
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP exynos_dp_init_dp() failed\n");
+		return ret;
+	}
+
+	ret = exynos_dp_handle_edid(edp_info);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("EDP handle_edid fail\n");
+		return ret;
+	}
+
+	ret = exynos_dp_set_link_train(edp_info);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP link training fail\n");
+		return ret;
+	}
+
+	exynos_dp_enable_scramble(DP_ENABLE);
+	exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
+	exynos_dp_enable_enhanced_mode(DP_ENABLE);
+
+	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
+	exynos_dp_set_lane_count(edp_info->lane_cnt);
+
+	exynos_dp_init_video();
+	ret = exynos_dp_config_video(edp_info);
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("Exynos DP init failed\n");
+		return ret;
+	}
+
+	debug("Exynos DP init done\n");
+
+	return ret;
+}
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
new file mode 100644
index 0000000..acb5bc8
--- /dev/null
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -0,0 +1,1257 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/err.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/dp.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+struct exynos_dp *dp_regs;
+
+void exynos_dp_set_base_addr(void)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
+					0, COMPAT_SAMSUNG_EXYNOS5_DP);
+	if (node <= 0)
+		debug("exynos_dp: Can't get device node for dp\n");
+
+	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
+								node, "reg");
+	if (dp_regs == NULL)
+		debug("Can't get the DP base address\n");
+#else
+	dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+#endif
+}
+
+static void exynos_dp_enable_video_input(unsigned int enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->video_ctl1);
+	reg &= ~VIDEO_EN_MASK;
+
+	/* enable video input */
+	if (enable)
+		reg |= VIDEO_EN_MASK;
+
+	writel(reg, &dp_regs->video_ctl1);
+
+	return;
+}
+
+void exynos_dp_enable_video_bist(unsigned int enable)
+{
+	/* enable video bist */
+	unsigned int reg;
+
+	reg = readl(&dp_regs->video_ctl4);
+	reg &= ~VIDEO_BIST_MASK;
+
+	/* enable video bist */
+	if (enable)
+		reg |= VIDEO_BIST_MASK;
+
+	writel(reg, &dp_regs->video_ctl4);
+
+	return;
+}
+
+void exynos_dp_enable_video_mute(unsigned int enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->video_ctl1);
+	reg &= ~(VIDEO_MUTE_MASK);
+	if (enable)
+		reg |= VIDEO_MUTE_MASK;
+
+	writel(reg, &dp_regs->video_ctl1);
+
+	return;
+}
+
+
+static void exynos_dp_init_analog_param(void)
+{
+	unsigned int reg;
+
+	/*
+	 * Set termination
+	 * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
+	 * 24M Phy clock, TX digital logic power is 100:1.0625V
+	 */
+	reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
+		SWING_A_30PER_G_NORMAL;
+	writel(reg, &dp_regs->analog_ctl1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, &dp_regs->analog_ctl2);
+
+	/*
+	 * Set power source for internal clk driver to 1.0625v.
+	 * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
+	 * Set VCO range of PLL +- 0uA
+	 */
+	reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
+	writel(reg, &dp_regs->analog_ctl3);
+
+	/*
+	 * Set AUX TX terminal resistor to 102 ohm
+	 * Set AUX channel amplitude control
+	 */
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
+	writel(reg, &dp_regs->pll_filter_ctl1);
+
+	/*
+	 * PLL loop filter bandwidth
+	 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
+	 * PLL digital power select: 1.2500V
+	 */
+	reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
+
+	writel(reg, &dp_regs->amp_tuning_ctl);
+
+	/*
+	 * PLL loop filter bandwidth
+	 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
+	 * PLL digital power select: 1.1250V
+	 */
+	reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
+	writel(reg, &dp_regs->pll_ctl);
+}
+
+static void exynos_dp_init_interrupt(void)
+{
+	/* Set interrupt registers to initial states */
+
+	/*
+	 * Disable interrupt
+	 * INT pin assertion polarity. It must be configured
+	 * correctly according to ICU setting.
+	 * 1 = assert high, 0 = assert low
+	 */
+	writel(INT_POL, &dp_regs->int_ctl);
+
+	/* Clear pending registers */
+	writel(0xff, &dp_regs->common_int_sta1);
+	writel(0xff, &dp_regs->common_int_sta2);
+	writel(0xff, &dp_regs->common_int_sta3);
+	writel(0xff, &dp_regs->common_int_sta4);
+	writel(0xff, &dp_regs->int_sta);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, &dp_regs->int_sta_mask1);
+	writel(0x00, &dp_regs->int_sta_mask2);
+	writel(0x00, &dp_regs->int_sta_mask3);
+	writel(0x00, &dp_regs->int_sta_mask4);
+	writel(0x00, &dp_regs->int_sta_mask);
+}
+
+void exynos_dp_reset(void)
+{
+	unsigned int reg_func_1;
+
+	/* dp tx sw reset */
+	writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
+
+	exynos_dp_enable_video_input(DP_DISABLE);
+	exynos_dp_enable_video_bist(DP_DISABLE);
+	exynos_dp_enable_video_mute(DP_DISABLE);
+
+	/* software reset */
+	reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+
+	writel(reg_func_1, &dp_regs->func_en1);
+	writel(reg_func_1, &dp_regs->func_en2);
+
+	mdelay(1);
+
+	exynos_dp_init_analog_param();
+	exynos_dp_init_interrupt();
+
+	return;
+}
+
+void exynos_dp_enable_sw_func(unsigned int enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->func_en1);
+	reg &= ~(SW_FUNC_EN_N);
+
+	if (!enable)
+		reg |= SW_FUNC_EN_N;
+
+	writel(reg, &dp_regs->func_en1);
+
+	return;
+}
+
+unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->phy_pd);
+	switch (block) {
+	case AUX_BLOCK:
+		reg &= ~(AUX_PD);
+		if (enable)
+			reg |= AUX_PD;
+		break;
+	case CH0_BLOCK:
+		reg &= ~(CH0_PD);
+		if (enable)
+			reg |= CH0_PD;
+		break;
+	case CH1_BLOCK:
+		reg &= ~(CH1_PD);
+		if (enable)
+			reg |= CH1_PD;
+		break;
+	case CH2_BLOCK:
+		reg &= ~(CH2_PD);
+		if (enable)
+			reg |= CH2_PD;
+		break;
+	case CH3_BLOCK:
+		reg &= ~(CH3_PD);
+		if (enable)
+			reg |= CH3_PD;
+		break;
+	case ANALOG_TOTAL:
+		reg &= ~PHY_PD;
+		if (enable)
+			reg |= PHY_PD;
+		break;
+	case POWER_ALL:
+		reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
+			CH3_PD);
+		if (enable)
+			reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
+				CH2_PD | CH3_PD);
+		break;
+	default:
+		printf("DP undefined block number : %d\n",  block);
+		return -1;
+	}
+
+	writel(reg, &dp_regs->phy_pd);
+
+	return 0;
+}
+
+unsigned int exynos_dp_get_pll_lock_status(void)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->debug_ctl);
+
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+static void exynos_dp_set_pll_power(unsigned int enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->pll_ctl);
+	reg &= ~(DP_PLL_PD);
+
+	if (!enable)
+		reg |= DP_PLL_PD;
+
+	writel(reg, &dp_regs->pll_ctl);
+}
+
+int exynos_dp_init_analog_func(void)
+{
+	int ret = EXYNOS_DP_SUCCESS;
+	unsigned int retry_cnt = 10;
+	unsigned int reg;
+
+	/* Power On All Analog block */
+	exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, &dp_regs->common_int_sta1);
+
+	reg = readl(&dp_regs->debug_ctl);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, &dp_regs->debug_ctl);
+
+	/* Assert DP PLL Reset */
+	reg = readl(&dp_regs->pll_ctl);
+	reg |= DP_PLL_RESET;
+	writel(reg, &dp_regs->pll_ctl);
+
+	mdelay(1);
+
+	/* Deassert DP PLL Reset */
+	reg = readl(&dp_regs->pll_ctl);
+	reg &= ~(DP_PLL_RESET);
+	writel(reg, &dp_regs->pll_ctl);
+
+	exynos_dp_set_pll_power(DP_ENABLE);
+
+	while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
+		mdelay(1);
+		retry_cnt--;
+		if (retry_cnt == 0) {
+			printf("DP dp's pll lock failed : retry : %d\n",
+					retry_cnt);
+			return -EINVAL;
+		}
+	}
+
+	debug("dp's pll lock success(%d)\n", retry_cnt);
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(&dp_regs->func_en2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, &dp_regs->func_en2);
+
+	return ret;
+}
+
+void exynos_dp_init_hpd(void)
+{
+	unsigned int reg;
+
+	/* Clear interrupts related to Hot Plug Detect */
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, &dp_regs->common_int_sta4);
+
+	reg = INT_HPD;
+	writel(reg, &dp_regs->int_sta);
+
+	reg = readl(&dp_regs->sys_ctl3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, &dp_regs->sys_ctl3);
+
+	return;
+}
+
+static inline void exynos_dp_reset_aux(void)
+{
+	unsigned int reg;
+
+	/* Disable AUX channel module */
+	reg = readl(&dp_regs->func_en2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, &dp_regs->func_en2);
+
+	return;
+}
+
+void exynos_dp_init_aux(void)
+{
+	unsigned int reg;
+
+	/* Clear interrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, &dp_regs->int_sta);
+
+	exynos_dp_reset_aux();
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
+		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, &dp_regs->aux_hw_retry_ctl);
+
+	/* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, &dp_regs->aux_ch_defer_ctl);
+
+	/* Enable AUX channel module */
+	reg = readl(&dp_regs->func_en2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, &dp_regs->func_en2);
+
+	return;
+}
+
+void exynos_dp_config_interrupt(void)
+{
+	unsigned int reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, &dp_regs->common_int_mask1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, &dp_regs->common_int_mask2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, &dp_regs->common_int_mask3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, &dp_regs->common_int_mask4);
+
+	reg = INT_STA_MASK;
+	writel(reg, &dp_regs->int_sta_mask);
+
+	return;
+}
+
+unsigned int exynos_dp_get_plug_in_status(void)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->sys_ctl3);
+	if (reg & HPD_STATUS)
+		return 0;
+
+	return -1;
+}
+
+unsigned int exynos_dp_detect_hpd(void)
+{
+	int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
+
+	mdelay(2);
+
+	while (exynos_dp_get_plug_in_status() != 0) {
+		if (timeout_loop == 0)
+			return -EINVAL;
+		mdelay(10);
+		timeout_loop--;
+	}
+
+	return EXYNOS_DP_SUCCESS;
+}
+
+unsigned int exynos_dp_start_aux_transaction(void)
+{
+	unsigned int reg;
+	unsigned int ret = 0;
+	unsigned int retry_cnt;
+
+	/* Enable AUX CH operation */
+	reg = readl(&dp_regs->aux_ch_ctl2);
+	reg |= AUX_EN;
+	writel(reg, &dp_regs->aux_ch_ctl2);
+
+	retry_cnt = 10;
+	while (retry_cnt) {
+		reg = readl(&dp_regs->int_sta);
+		if (!(reg & RPLY_RECEIV)) {
+			if (retry_cnt == 0) {
+				printf("DP Reply Timeout!!\n");
+				ret = -EAGAIN;
+				return ret;
+			}
+			mdelay(1);
+			retry_cnt--;
+		} else
+			break;
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(reg, &dp_regs->int_sta);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(&dp_regs->int_sta);
+	if (reg & AUX_ERR) {
+		printf("DP Aux Access Error\n");
+		writel(AUX_ERR, &dp_regs->int_sta);
+		ret = -EAGAIN;
+		return ret;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(&dp_regs->aux_ch_sta);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
+		ret = -EAGAIN;
+		return ret;
+	}
+
+	return EXYNOS_DP_SUCCESS;
+}
+
+unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
+				unsigned char data)
+{
+	unsigned int reg, ret;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, &dp_regs->buffer_data_ctl);
+
+	/* Select DPCD device address */
+	reg = AUX_ADDR_7_0(reg_addr);
+	writel(reg, &dp_regs->aux_addr_7_0);
+	reg = AUX_ADDR_15_8(reg_addr);
+	writel(reg, &dp_regs->aux_addr_15_8);
+	reg = AUX_ADDR_19_16(reg_addr);
+	writel(reg, &dp_regs->aux_addr_19_16);
+
+	/* Write data buffer */
+	reg = (unsigned int)data;
+	writel(reg, &dp_regs->buf_data0);
+
+	/*
+	 * Set DisplayPort transaction and write 1 byte
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+	writel(reg, &dp_regs->aux_ch_ctl1);
+
+	/* Start AUX transaction */
+	ret = exynos_dp_start_aux_transaction();
+	if (ret != EXYNOS_DP_SUCCESS) {
+		printf("DP Aux transaction failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
+		unsigned char *data)
+{
+	unsigned int reg;
+	int retval;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, &dp_regs->buffer_data_ctl);
+
+	/* Select DPCD device address */
+	reg = AUX_ADDR_7_0(reg_addr);
+	writel(reg, &dp_regs->aux_addr_7_0);
+	reg = AUX_ADDR_15_8(reg_addr);
+	writel(reg, &dp_regs->aux_addr_15_8);
+	reg = AUX_ADDR_19_16(reg_addr);
+	writel(reg, &dp_regs->aux_addr_19_16);
+
+	/*
+	 * Set DisplayPort transaction and read 1 byte
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+	writel(reg, &dp_regs->aux_ch_ctl1);
+
+	/* Start AUX transaction */
+	retval = exynos_dp_start_aux_transaction();
+	if (!retval)
+		debug("DP Aux Transaction fail!\n");
+
+	/* Read data buffer */
+	reg = readl(&dp_regs->buf_data0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	unsigned int reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	unsigned int retry_cnt;
+	unsigned int ret = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, &dp_regs->buffer_data_ctl);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		retry_cnt = 5;
+		while (retry_cnt) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, &dp_regs->aux_addr_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, &dp_regs->aux_addr_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, &dp_regs->aux_addr_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+					cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, (unsigned int)&dp_regs->buf_data0 +
+						(4 * cur_data_idx));
+			}
+			/*
+			* Set DisplayPort transaction and write
+			* If bit 3 is 1, DisplayPort transaction.
+			* If Bit 3 is 0, I2C transaction.
+			*/
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, &dp_regs->aux_ch_ctl1);
+
+			/* Start AUX transaction */
+			ret = exynos_dp_start_aux_transaction();
+			if (ret != EXYNOS_DP_SUCCESS) {
+				if (retry_cnt == 0) {
+					printf("DP Aux Transaction failed\n");
+					return ret;
+				}
+				retry_cnt--;
+			} else
+				break;
+		}
+		start_offset += cur_data_count;
+	}
+
+	return ret;
+}
+
+unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	unsigned int reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	unsigned int retry_cnt;
+	unsigned int ret = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, &dp_regs->buffer_data_ctl);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		retry_cnt = 5;
+		while (retry_cnt) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, &dp_regs->aux_addr_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, &dp_regs->aux_addr_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, &dp_regs->aux_addr_19_16);
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, &dp_regs->aux_ch_ctl1);
+
+			/* Start AUX transaction */
+			ret = exynos_dp_start_aux_transaction();
+			if (ret != EXYNOS_DP_SUCCESS) {
+				if (retry_cnt == 0) {
+					printf("DP Aux Transaction failed\n");
+					return ret;
+				}
+				retry_cnt--;
+			} else
+				break;
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+				cur_data_idx++) {
+			reg = readl((unsigned int)&dp_regs->buf_data0 +
+					4 * cur_data_idx);
+			data[start_offset + cur_data_idx] = (unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return ret;
+}
+
+int exynos_dp_select_i2c_device(unsigned int device_addr,
+				unsigned int reg_addr)
+{
+	unsigned int reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, &dp_regs->aux_addr_7_0);
+	writel(0x0, &dp_regs->aux_addr_15_8);
+	writel(0x0, &dp_regs->aux_addr_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, &dp_regs->buf_data0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, &dp_regs->aux_ch_ctl1);
+
+	/* Start AUX transaction */
+	retval = exynos_dp_start_aux_transaction();
+	if (retval != 0)
+		printf("%s: DP Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data)
+{
+	unsigned int reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 10; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, &dp_regs->buffer_data_ctl);
+
+		/* Select EDID device */
+		retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
+		if (retval != 0) {
+			printf("DP Select EDID device fail. retry !\n");
+			continue;
+		}
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, &dp_regs->aux_ch_ctl1);
+
+		/* Start AUX transaction */
+		retval = exynos_dp_start_aux_transaction();
+		if (retval != EXYNOS_DP_SUCCESS)
+			printf("%s: DP Aux Transaction fail!\n", __func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(&dp_regs->buf_data0);
+
+	return retval;
+}
+
+int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
+		unsigned int reg_addr, unsigned int count, unsigned char edid[])
+{
+	unsigned int reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) { /* use 16 burst */
+		for (j = 0; j < 100; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, &dp_regs->buffer_data_ctl);
+
+			/* Set normal AUX CH command */
+			reg = readl(&dp_regs->aux_ch_ctl2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, &dp_regs->aux_ch_ctl2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending addres
+			 */
+			if (!defer)
+				retval =
+					exynos_dp_select_i2c_device(device_addr,
+							reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == EXYNOS_DP_SUCCESS) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, &dp_regs->aux_ch_ctl1);
+
+				/* Start AUX transaction */
+				retval = exynos_dp_start_aux_transaction();
+				if (retval == 0)
+					break;
+				else
+					printf("DP Aux Transaction fail!\n");
+			}
+			/* Check if Rx sends defer */
+			reg = readl(&dp_regs->aux_rx_comm);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+				reg == AUX_RX_COMM_I2C_DEFER) {
+				printf("DP Defer: %d\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl((unsigned int)&dp_regs->buf_data0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void exynos_dp_reset_macro(void)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->phy_test);
+	reg |= MACRO_RST;
+	writel(reg, &dp_regs->phy_test);
+
+	/* 10 us is the minimum Macro reset time. */
+	mdelay(1);
+
+	reg &= ~MACRO_RST;
+	writel(reg, &dp_regs->phy_test);
+}
+
+void exynos_dp_set_link_bandwidth(unsigned char bwtype)
+{
+	unsigned int reg;
+
+	reg = (unsigned int)bwtype;
+
+	 /* Set bandwidth to 2.7G or 1.62G */
+	if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
+		writel(reg, &dp_regs->link_bw_set);
+}
+
+unsigned char exynos_dp_get_link_bandwidth(void)
+{
+	unsigned char ret;
+	unsigned int reg;
+
+	reg = readl(&dp_regs->link_bw_set);
+	ret = (unsigned char)reg;
+
+	return ret;
+}
+
+void exynos_dp_set_lane_count(unsigned char count)
+{
+	unsigned int reg;
+
+	reg = (unsigned int)count;
+
+	if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
+			(count == DP_LANE_CNT_4))
+		writel(reg, &dp_regs->lane_count_set);
+}
+
+unsigned int exynos_dp_get_lane_count(void)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->lane_count_set);
+
+	return reg;
+}
+
+unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
+{
+	unsigned int reg_list[DP_LANE_CNT_4] = {
+		(unsigned int)&dp_regs->ln0_link_training_ctl,
+		(unsigned int)&dp_regs->ln1_link_training_ctl,
+		(unsigned int)&dp_regs->ln2_link_training_ctl,
+		(unsigned int)&dp_regs->ln3_link_training_ctl,
+	};
+
+	return readl(reg_list[lanecnt]);
+}
+
+void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
+		unsigned char lanecnt)
+{
+	unsigned int reg_list[DP_LANE_CNT_4] = {
+		(unsigned int)&dp_regs->ln0_link_training_ctl,
+		(unsigned int)&dp_regs->ln1_link_training_ctl,
+		(unsigned int)&dp_regs->ln2_link_training_ctl,
+		(unsigned int)&dp_regs->ln3_link_training_ctl,
+	};
+
+	writel(request_val, reg_list[lanecnt]);
+}
+
+void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
+{
+	unsigned char i;
+	unsigned int reg;
+	unsigned int reg_list[DP_LANE_CNT_4] = {
+		(unsigned int)&dp_regs->ln0_link_training_ctl,
+		(unsigned int)&dp_regs->ln1_link_training_ctl,
+		(unsigned int)&dp_regs->ln2_link_training_ctl,
+		(unsigned int)&dp_regs->ln3_link_training_ctl,
+	};
+	unsigned int reg_shift[DP_LANE_CNT_4] = {
+		PRE_EMPHASIS_SET_0_SHIFT,
+		PRE_EMPHASIS_SET_1_SHIFT,
+		PRE_EMPHASIS_SET_2_SHIFT,
+		PRE_EMPHASIS_SET_3_SHIFT
+	};
+
+	for (i = 0; i < lanecnt; i++) {
+		reg = level << reg_shift[i];
+		writel(reg, reg_list[i]);
+	}
+}
+
+void exynos_dp_set_training_pattern(unsigned int pattern)
+{
+	unsigned int reg = 0;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		break;
+	default:
+		break;
+	}
+
+	writel(reg, &dp_regs->training_ptn_set);
+}
+
+void exynos_dp_enable_enhanced_mode(unsigned char enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->sys_ctl4);
+	reg &= ~ENHANCED;
+
+	if (enable)
+		reg |= ENHANCED;
+
+	writel(reg, &dp_regs->sys_ctl4);
+}
+
+void exynos_dp_enable_scrambling(unsigned int enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->training_ptn_set);
+	reg &= ~(SCRAMBLING_DISABLE);
+
+	if (!enable)
+		reg |= SCRAMBLING_DISABLE;
+
+	writel(reg, &dp_regs->training_ptn_set);
+}
+
+int exynos_dp_init_video(void)
+{
+	unsigned int reg;
+
+	/* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, &dp_regs->common_int_sta1);
+
+	/* I_STRM__CLK detect : DE_CTL : Auto detect */
+	reg &= ~DET_CTRL;
+	writel(reg, &dp_regs->sys_ctl1);
+
+	return 0;
+}
+
+void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
+{
+	unsigned int reg;
+
+	/* Video Slave mode setting */
+	reg = readl(&dp_regs->func_en1);
+	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, &dp_regs->func_en1);
+
+	/* Configure Interlaced for slave mode video */
+	reg = readl(&dp_regs->video_ctl10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
+	writel(reg, &dp_regs->video_ctl10);
+
+	/* Configure V sync polarity for slave mode video */
+	reg = readl(&dp_regs->video_ctl10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
+	writel(reg, &dp_regs->video_ctl10);
+
+	/* Configure H sync polarity for slave mode video */
+	reg = readl(&dp_regs->video_ctl10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
+	writel(reg, &dp_regs->video_ctl10);
+
+	/* Set video mode to slave mode */
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, &dp_regs->soc_general_ctl);
+}
+
+void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
+{
+	unsigned int reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(video_info->color_depth << IN_BPC_SHIFT) |
+		(video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, &dp_regs->video_ctl2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(&dp_regs->video_ctl3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, &dp_regs->video_ctl3);
+}
+
+int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
+{
+	unsigned int reg;
+	unsigned int bist_type = 0;
+	struct edp_video_info video_info = edp_info->video_info;
+
+	/* For master mode, you don't need to set the video format */
+	if (video_info.master_mode == 0) {
+		writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
+				&dp_regs->total_ln_cfg_l);
+		writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
+				&dp_regs->total_ln_cfg_h);
+		writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
+				&dp_regs->active_ln_cfg_l);
+		writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
+				&dp_regs->active_ln_cfg_h);
+		writel(edp_info->disp_info.v_sync_width,
+				&dp_regs->vsw_cfg);
+		writel(edp_info->disp_info.v_back_porch,
+				&dp_regs->vbp_cfg);
+		writel(edp_info->disp_info.v_front_porch,
+				&dp_regs->vfp_cfg);
+
+		writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
+				&dp_regs->total_pix_cfg_l);
+		writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
+				&dp_regs->total_pix_cfg_h);
+		writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
+				&dp_regs->active_pix_cfg_l);
+		writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
+				&dp_regs->active_pix_cfg_h);
+		writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
+				&dp_regs->hfp_cfg_l);
+		writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
+				&dp_regs->hfp_cfg_h);
+		writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
+				&dp_regs->hsw_cfg_l);
+		writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
+				&dp_regs->hsw_cfg_h);
+		writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
+				&dp_regs->hbp_cfg_l);
+		writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
+				&dp_regs->hbp_cfg_h);
+
+		/*
+		 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
+		 * HSYNC_P_CFG[0] properly
+		 */
+		reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
+			video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
+			video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
+		writel(reg, &dp_regs->video_ctl10);
+	}
+
+	/* BIST color bar width set--set to each bar is 32 pixel width */
+	switch (video_info.bist_pattern) {
+	case COLORBAR_32:
+		bist_type = BIST_WIDTH_BAR_32_PIXEL |
+			  BIST_TYPE_COLOR_BAR;
+		break;
+	case COLORBAR_64:
+		bist_type = BIST_WIDTH_BAR_64_PIXEL |
+			  BIST_TYPE_COLOR_BAR;
+		break;
+	case WHITE_GRAY_BALCKBAR_32:
+		bist_type = BIST_WIDTH_BAR_32_PIXEL |
+			  BIST_TYPE_WHITE_GRAY_BLACK_BAR;
+		break;
+	case WHITE_GRAY_BALCKBAR_64:
+		bist_type = BIST_WIDTH_BAR_64_PIXEL |
+			  BIST_TYPE_WHITE_GRAY_BLACK_BAR;
+		break;
+	case MOBILE_WHITEBAR_32:
+		bist_type = BIST_WIDTH_BAR_32_PIXEL |
+			  BIST_TYPE_MOBILE_WHITE_BAR;
+		break;
+	case MOBILE_WHITEBAR_64:
+		bist_type = BIST_WIDTH_BAR_64_PIXEL |
+			  BIST_TYPE_MOBILE_WHITE_BAR;
+		break;
+	default:
+		return -1;
+	}
+
+	reg = bist_type;
+	writel(reg, &dp_regs->video_ctl4);
+
+	return 0;
+}
+
+unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
+{
+	unsigned int reg;
+
+	/* Update Video stream clk detect status */
+	reg = readl(&dp_regs->sys_ctl1);
+	writel(reg, &dp_regs->sys_ctl1);
+
+	reg = readl(&dp_regs->sys_ctl1);
+
+	if (!(reg & DET_STA)) {
+		debug("DP Input stream clock not detected.\n");
+		return -EIO;
+	}
+
+	return EXYNOS_DP_SUCCESS;
+}
+
+void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
+		unsigned int n_value)
+{
+	unsigned int reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(&dp_regs->sys_ctl4);
+		reg |= FIX_M_VID;
+		writel(reg, &dp_regs->sys_ctl4);
+		reg = M_VID0_CFG(m_value);
+		writel(reg, &dp_regs->m_vid0);
+		reg = M_VID1_CFG(m_value);
+		writel(reg, &dp_regs->m_vid1);
+		reg = M_VID2_CFG(m_value);
+		writel(reg, &dp_regs->m_vid2);
+
+		reg = N_VID0_CFG(n_value);
+		writel(reg, &dp_regs->n_vid0);
+		reg = N_VID1_CFG(n_value);
+		writel(reg, &dp_regs->n_vid1);
+		reg = N_VID2_CFG(n_value);
+		writel(reg, &dp_regs->n_vid2);
+	} else  {
+		reg = readl(&dp_regs->sys_ctl4);
+		reg &= ~FIX_M_VID;
+		writel(reg, &dp_regs->sys_ctl4);
+	}
+}
+
+void exynos_dp_set_video_timing_mode(unsigned int type)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->video_ctl10);
+	reg &= ~FORMAT_SEL;
+
+	if (type != VIDEO_TIMING_FROM_CAPTURE)
+		reg |= FORMAT_SEL;
+
+	writel(reg, &dp_regs->video_ctl10);
+}
+
+void exynos_dp_enable_video_master(unsigned int enable)
+{
+	unsigned int reg;
+
+	reg = readl(&dp_regs->soc_general_ctl);
+	if (enable) {
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+	} else {
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+	}
+
+	writel(reg, &dp_regs->soc_general_ctl);
+}
+
+void exynos_dp_start_video(void)
+{
+	unsigned int reg;
+
+	/* Enable Video input and disable Mute */
+	reg = readl(&dp_regs->video_ctl1);
+	reg |= VIDEO_EN;
+	writel(reg, &dp_regs->video_ctl1);
+}
+
+unsigned int exynos_dp_is_video_stream_on(void)
+{
+	unsigned int reg;
+
+	/* Update STRM_VALID */
+	reg = readl(&dp_regs->sys_ctl3);
+	writel(reg, &dp_regs->sys_ctl3);
+
+	reg = readl(&dp_regs->sys_ctl3);
+	if (!(reg & STRM_VALID))
+		return -EIO;
+
+	return EXYNOS_DP_SUCCESS;
+}
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.h b/drivers/video/exynos/exynos_dp_lowlevel.h
new file mode 100644
index 0000000..8651681
--- /dev/null
+++ b/drivers/video/exynos/exynos_dp_lowlevel.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_EDP_LOWLEVEL_H
+#define _EXYNOS_EDP_LOWLEVEL_H
+
+void exynos_dp_enable_video_bist(unsigned int enable);
+void exynos_dp_enable_video_mute(unsigned int enable);
+void exynos_dp_reset(void);
+void exynos_dp_enable_sw_func(unsigned int enable);
+unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
+unsigned int exynos_dp_get_pll_lock_status(void);
+int exynos_dp_init_analog_func(void);
+void exynos_dp_init_hpd(void);
+void exynos_dp_init_aux(void);
+void exynos_dp_config_interrupt(void);
+unsigned int exynos_dp_get_plug_in_status(void);
+unsigned int exynos_dp_detect_hpd(void);
+unsigned int exynos_dp_start_aux_transaction(void);
+unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
+				unsigned char data);
+unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
+		unsigned char *data);
+unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
+		unsigned int count,
+		unsigned char data[]);
+unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
+		unsigned int count,
+		unsigned char data[]);
+int exynos_dp_select_i2c_device( unsigned int device_addr,
+		unsigned int reg_addr);
+int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
+		unsigned int reg_addr, unsigned int *data);
+int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
+		unsigned int reg_addr, unsigned int count,
+		unsigned char edid[]);
+void exynos_dp_reset_macro(void);
+void exynos_dp_set_link_bandwidth(unsigned char bwtype);
+unsigned char exynos_dp_get_link_bandwidth(void);
+void exynos_dp_set_lane_count(unsigned char count);
+unsigned int exynos_dp_get_lane_count(void);
+unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt);
+void exynos_dp_set_lane_pre_emphasis(unsigned int level,
+		unsigned char lanecnt);
+void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
+		unsigned char lanecnt);
+void exynos_dp_set_training_pattern(unsigned int pattern);
+void exynos_dp_enable_enhanced_mode(unsigned char enable);
+void exynos_dp_enable_scrambling(unsigned int enable);
+int exynos_dp_init_video(void);
+void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
+void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
+int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
+unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
+void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
+		unsigned int n_value);
+void exynos_dp_set_video_timing_mode(unsigned int type);
+void exynos_dp_enable_video_master(unsigned int enable);
+void exynos_dp_start_video(void);
+unsigned int exynos_dp_is_video_stream_on(void);
+void exynos_dp_set_base_addr(void);
+
+#endif /* _EXYNOS_DP_LOWLEVEL_H */
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
new file mode 100644
index 0000000..69edc3a
--- /dev/null
+++ b/drivers/video/exynos/exynos_fb.c
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <lcd.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/system.h>
+#include <asm/gpio.h>
+#include <asm-generic/errno.h>
+
+#include "exynos_fb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned int panel_width, panel_height;
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+vidinfo_t panel_info  = {
+	/*
+	 * Insert a value here so that we don't end up in the BSS
+	 * Reference: drivers/video/tegra.c
+	 */
+	.vl_col = -1,
+};
+#endif
+
+ushort *configuration_get_cmap(void)
+{
+#if defined(CONFIG_LCD_LOGO)
+	return bmp_logo_palette;
+#else
+	return NULL;
+#endif
+}
+
+static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
+{
+	unsigned long palette_size;
+	unsigned int fb_size;
+
+	fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
+
+	palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
+
+	exynos_fimd_lcd_init_mem((unsigned long)lcdbase,
+			(unsigned long)fb_size, palette_size);
+}
+
+static void exynos_lcd_init(vidinfo_t *vid)
+{
+	exynos_fimd_lcd_init(vid);
+
+	/* Enable flushing after LCD writes if requested */
+	lcd_set_flush_dcache(1);
+}
+
+__weak void exynos_cfg_lcd_gpio(void)
+{
+}
+
+__weak void exynos_backlight_on(unsigned int onoff)
+{
+}
+
+__weak void exynos_reset_lcd(void)
+{
+}
+
+__weak void exynos_lcd_power_on(void)
+{
+}
+
+__weak void exynos_cfg_ldo(void)
+{
+}
+
+__weak void exynos_enable_ldo(unsigned int onoff)
+{
+}
+
+__weak void exynos_backlight_reset(void)
+{
+}
+
+__weak int exynos_lcd_misc_init(vidinfo_t *vid)
+{
+	return 0;
+}
+
+static void lcd_panel_on(vidinfo_t *vid)
+{
+	struct gpio_desc pwm_out_gpio;
+	struct gpio_desc bl_en_gpio;
+	unsigned int node;
+
+	udelay(vid->init_delay);
+
+	exynos_backlight_reset();
+
+	exynos_cfg_lcd_gpio();
+
+	exynos_lcd_power_on();
+
+	udelay(vid->power_on_delay);
+
+	if (vid->dp_enabled)
+		exynos_init_dp();
+
+	exynos_reset_lcd();
+
+	udelay(vid->reset_delay);
+
+	exynos_backlight_on(1);
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+						COMPAT_SAMSUNG_EXYNOS_FIMD);
+	if (node <= 0) {
+		debug("FIMD: Can't get device node for FIMD\n");
+		return;
+	}
+	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
+				   0, &pwm_out_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
+				   &bl_en_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+#endif
+	exynos_cfg_ldo();
+
+	exynos_enable_ldo(1);
+
+	if (vid->mipi_enabled)
+		exynos_mipi_dsi_init();
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+int exynos_lcd_early_init(const void *blob)
+{
+	unsigned int node;
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
+	if (node <= 0) {
+		debug("exynos_fb: Can't get device node for fimd\n");
+		return -ENODEV;
+	}
+
+	panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
+	if (panel_info.vl_col == 0) {
+		debug("Can't get XRES\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
+	if (panel_info.vl_row == 0) {
+		debug("Can't get YRES\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_width = fdtdec_get_int(blob, node,
+						"samsung,vl-width", 0);
+
+	panel_info.vl_height = fdtdec_get_int(blob, node,
+						"samsung,vl-height", 0);
+
+	panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
+	if (panel_info.vl_freq == 0) {
+		debug("Can't get refresh rate\n");
+		return -ENXIO;
+	}
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
+		panel_info.vl_clkp = CONFIG_SYS_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
+		panel_info.vl_oep = CONFIG_SYS_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
+		panel_info.vl_hsp = CONFIG_SYS_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
+		panel_info.vl_vsp = CONFIG_SYS_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
+		panel_info.vl_dp = CONFIG_SYS_LOW;
+
+	panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
+	if (panel_info.vl_bpix == 0) {
+		debug("Can't get bits per pixel\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
+	if (panel_info.vl_hspw == 0) {
+		debug("Can't get hsync width\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
+	if (panel_info.vl_hfpd == 0) {
+		debug("Can't get right margin\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
+							"samsung,vl-hbpd", 0);
+	if (panel_info.vl_hbpd == 0) {
+		debug("Can't get left margin\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
+							"samsung,vl-vspw", 0);
+	if (panel_info.vl_vspw == 0) {
+		debug("Can't get vsync width\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_vfpd = fdtdec_get_int(blob, node,
+							"samsung,vl-vfpd", 0);
+	if (panel_info.vl_vfpd == 0) {
+		debug("Can't get lower margin\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
+	if (panel_info.vl_vbpd == 0) {
+		debug("Can't get upper margin\n");
+		return -ENXIO;
+	}
+
+	panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
+						"samsung,vl-cmd-allow-len", 0);
+
+	panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
+	panel_info.init_delay = fdtdec_get_int(blob, node,
+						"samsung,init-delay", 0);
+	panel_info.power_on_delay = fdtdec_get_int(blob, node,
+						"samsung,power-on-delay", 0);
+	panel_info.reset_delay = fdtdec_get_int(blob, node,
+						"samsung,reset-delay", 0);
+	panel_info.interface_mode = fdtdec_get_int(blob, node,
+						"samsung,interface-mode", 0);
+	panel_info.mipi_enabled = fdtdec_get_int(blob, node,
+						"samsung,mipi-enabled", 0);
+	panel_info.dp_enabled = fdtdec_get_int(blob, node,
+						"samsung,dp-enabled", 0);
+	panel_info.cs_setup = fdtdec_get_int(blob, node,
+						"samsung,cs-setup", 0);
+	panel_info.wr_setup = fdtdec_get_int(blob, node,
+						"samsung,wr-setup", 0);
+	panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
+	panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
+
+	panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
+	if (panel_info.logo_on) {
+		panel_info.logo_width = fdtdec_get_int(blob, node,
+						"samsung,logo-width", 0);
+		panel_info.logo_height = fdtdec_get_int(blob, node,
+						"samsung,logo-height", 0);
+		panel_info.logo_addr = fdtdec_get_int(blob, node,
+						"samsung,logo-addr", 0);
+	}
+
+	panel_info.rgb_mode = fdtdec_get_int(blob, node,
+						"samsung,rgb-mode", 0);
+	panel_info.pclk_name = fdtdec_get_int(blob, node,
+						"samsung,pclk-name", 0);
+	panel_info.sclk_div = fdtdec_get_int(blob, node,
+						"samsung,sclk-div", 0);
+	panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
+						"samsung,dual-lcd-enabled", 0);
+
+	return 0;
+}
+#endif
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	set_system_display_ctrl();
+	set_lcd_clk();
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+	exynos_init_dsim_platform_data(&panel_info);
+#endif
+	exynos_lcd_misc_init(&panel_info);
+#else
+	/* initialize parameters which is specific to panel. */
+	init_panel_info(&panel_info);
+#endif
+
+	panel_width = panel_info.vl_width;
+	panel_height = panel_info.vl_height;
+
+	exynos_lcd_init_mem(lcdbase, &panel_info);
+
+	exynos_lcd_init(&panel_info);
+}
+
+void lcd_enable(void)
+{
+	if (panel_info.logo_on) {
+		memset((void *) gd->fb_base, 0, panel_width * panel_height *
+				(NBITS(panel_info.vl_bpix) >> 3));
+	}
+
+	lcd_panel_on(&panel_info);
+}
+
+/* dummy function */
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+	return;
+}
diff --git a/drivers/video/exynos/exynos_fb.h b/drivers/video/exynos/exynos_fb.h
new file mode 100644
index 0000000..2c2f94b
--- /dev/null
+++ b/drivers/video/exynos/exynos_fb.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_FB_H_
+#define _EXYNOS_FB_H_
+
+#include <asm/arch/fb.h>
+
+#define MAX_CLOCK	(86 * 1000000)
+
+enum exynos_cpu_auto_cmd_rate {
+	DISABLE_AUTO_FRM,
+	PER_TWO_FRM,
+	PER_FOUR_FRM,
+	PER_SIX_FRM,
+	PER_EIGHT_FRM,
+	PER_TEN_FRM,
+	PER_TWELVE_FRM,
+	PER_FOURTEEN_FRM,
+	PER_SIXTEEN_FRM,
+	PER_EIGHTEEN_FRM,
+	PER_TWENTY_FRM,
+	PER_TWENTY_TWO_FRM,
+	PER_TWENTY_FOUR_FRM,
+	PER_TWENTY_SIX_FRM,
+	PER_TWENTY_EIGHT_FRM,
+	PER_THIRTY_FRM,
+};
+
+void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
+	unsigned long palette_size);
+void exynos_fimd_lcd_init(vidinfo_t *vid);
+unsigned long exynos_fimd_calc_fbsize(void);
+
+#endif
diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c
new file mode 100644
index 0000000..ac001a8
--- /dev/null
+++ b/drivers/video/exynos/exynos_fimd.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <lcd.h>
+#include <div64.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include "exynos_fb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long *lcd_base_addr;
+static vidinfo_t *pvid;
+static struct exynos_fb *fimd_ctrl;
+
+void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
+		u_long palette_size)
+{
+	lcd_base_addr = (unsigned long *)screen_base;
+}
+
+static void exynos_fimd_set_dualrgb(unsigned int enabled)
+{
+	unsigned int cfg = 0;
+
+	if (enabled) {
+		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
+			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
+
+		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
+		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
+			EXYNOS_DUALRGB_MAIN_CNT(0);
+	}
+
+	writel(cfg, &fimd_ctrl->dualrgb);
+}
+
+static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
+{
+	unsigned int cfg = 0;
+
+	if (enabled)
+		cfg = EXYNOS_DP_CLK_ENABLE;
+
+	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
+}
+
+static void exynos_fimd_set_par(unsigned int win_id)
+{
+	unsigned int cfg = 0;
+
+	/* set window control */
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
+		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
+		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
+		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
+
+	/* DATAPATH is DMA */
+	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
+
+	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+
+	/* dma burst is 16 */
+	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
+
+	switch (pvid->vl_bpix) {
+	case 4:
+		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+		break;
+	default:
+		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+		break;
+	}
+
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	/* set window position to x=0, y=0*/
+	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
+			EXYNOS_VIDOSD(win_id));
+
+	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
+		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
+		EXYNOS_VIDOSD_RIGHT_X_E(1) |
+		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
+
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
+			EXYNOS_VIDOSD(win_id));
+
+	/* set window size for window0*/
+	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
+			EXYNOS_VIDOSD(win_id));
+}
+
+static void exynos_fimd_set_buffer_address(unsigned int win_id)
+{
+	unsigned long start_addr, end_addr;
+
+	start_addr = (unsigned long)lcd_base_addr;
+	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
+				pvid->vl_row);
+
+	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+}
+
+static void exynos_fimd_set_clock(vidinfo_t *pvid)
+{
+	unsigned int cfg = 0, div = 0, remainder, remainder_div;
+	unsigned long pixel_clock;
+	unsigned long long src_clock;
+
+	if (pvid->dual_lcd_enabled) {
+		pixel_clock = pvid->vl_freq *
+				(pvid->vl_hspw + pvid->vl_hfpd +
+				 pvid->vl_hbpd + pvid->vl_col / 2) *
+				(pvid->vl_vspw + pvid->vl_vfpd +
+				 pvid->vl_vbpd + pvid->vl_row);
+	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
+		pixel_clock = pvid->vl_freq *
+				pvid->vl_width * pvid->vl_height *
+				(pvid->cs_setup + pvid->wr_setup +
+				 pvid->wr_act + pvid->wr_hold + 1);
+	} else {
+		pixel_clock = pvid->vl_freq *
+				(pvid->vl_hspw + pvid->vl_hfpd +
+				 pvid->vl_hbpd + pvid->vl_col) *
+				(pvid->vl_vspw + pvid->vl_vfpd +
+				 pvid->vl_vbpd + pvid->vl_row);
+	}
+
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
+		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
+		EXYNOS_VIDCON0_CLKDIR_MASK);
+	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
+		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
+
+	src_clock = (unsigned long long) get_lcd_clk();
+
+	/* get quotient and remainder. */
+	remainder = do_div(src_clock, pixel_clock);
+	div = src_clock;
+
+	remainder *= 10;
+	remainder_div = remainder / pixel_clock;
+
+	/* round about one places of decimals. */
+	if (remainder_div >= 5)
+		div++;
+
+	/* in case of dual lcd mode. */
+	if (pvid->dual_lcd_enabled)
+		div--;
+
+	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_set_trigger(void)
+{
+	unsigned int cfg = 0;
+
+	cfg = readl(&fimd_ctrl->trigcon);
+
+	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
+
+	writel(cfg, &fimd_ctrl->trigcon);
+}
+
+int exynos_is_i80_frame_done(void)
+{
+	unsigned int cfg = 0;
+	int status;
+
+	cfg = readl(&fimd_ctrl->trigcon);
+
+	/* frame done func is valid only when TRIMODE[0] is set to 1. */
+	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
+			EXYNOS_I80STATUS_TRIG_DONE;
+
+	return status;
+}
+
+static void exynos_fimd_lcd_on(void)
+{
+	unsigned int cfg = 0;
+
+	/* display on */
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+static void exynos_fimd_window_on(unsigned int win_id)
+{
+	unsigned int cfg = 0;
+
+	/* enable window */
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&fimd_ctrl->winshmap);
+	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
+	writel(cfg, &fimd_ctrl->winshmap);
+}
+
+void exynos_fimd_lcd_off(void)
+{
+	unsigned int cfg = 0;
+
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_fimd_window_off(unsigned int win_id)
+{
+	unsigned int cfg = 0;
+
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&fimd_ctrl->winshmap);
+	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
+	writel(cfg, &fimd_ctrl->winshmap);
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+	u32 *sysmmufimd;
+	unsigned int node;
+	int node_list[2];
+	int count;
+	int i;
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+				COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+	for (i = 0; i < count; i++) {
+		node = node_list[i];
+		if (node <= 0) {
+			debug("Can't get device node for fimd sysmmu\n");
+			return;
+		}
+
+		sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+		if (!sysmmufimd) {
+			debug("Can't get base address for sysmmu fimdm0");
+			return;
+		}
+
+		writel(0x0, sysmmufimd);
+	}
+}
+#endif
+
+void exynos_fimd_lcd_init(vidinfo_t *vid)
+{
+	unsigned int cfg = 0, rgb_mode;
+	unsigned int offset;
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	unsigned int node;
+
+	node = fdtdec_next_compatible(gd->fdt_blob,
+					0, COMPAT_SAMSUNG_EXYNOS_FIMD);
+	if (node <= 0)
+		debug("exynos_fb: Can't get device node for fimd\n");
+
+	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
+								node, "reg");
+	if (fimd_ctrl == NULL)
+		debug("Can't get the FIMD base address\n");
+
+	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+		exynos_fimd_disable_sysmmu();
+
+#else
+	fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
+#endif
+
+	offset = exynos_fimd_get_base_offset();
+
+	/* store panel info to global variable */
+	pvid = vid;
+
+	rgb_mode = vid->rgb_mode;
+
+	if (vid->interface_mode == FIMD_RGB_INTERFACE) {
+		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
+		writel(cfg, &fimd_ctrl->vidcon0);
+
+		cfg = readl(&fimd_ctrl->vidcon2);
+		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
+		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
+		writel(cfg, &fimd_ctrl->vidcon2);
+
+		/* set polarity */
+		cfg = 0;
+		if (!pvid->vl_clkp)
+			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
+		if (!pvid->vl_hsp)
+			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
+		if (!pvid->vl_vsp)
+			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
+		if (!pvid->vl_dp)
+			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
+
+		writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
+
+		/* set timing */
+		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
+		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
+
+		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
+
+		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
+
+		/* set lcd size */
+		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
+			EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
+
+		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
+	}
+
+	/* set display mode */
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
+	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
+	writel(cfg, &fimd_ctrl->vidcon0);
+
+	/* set par */
+	exynos_fimd_set_par(pvid->win_id);
+
+	/* set memory address */
+	exynos_fimd_set_buffer_address(pvid->win_id);
+
+	/* set buffer size */
+	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_OFFSIZE(0) |
+		EXYNOS_VIDADDR_OFFSIZE_E(0);
+
+	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
+					EXYNOS_BUFFER_SIZE(pvid->win_id));
+
+	/* set clock */
+	exynos_fimd_set_clock(pvid);
+
+	/* set rgb mode to dual lcd. */
+	exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
+
+	/* display on */
+	exynos_fimd_lcd_on();
+
+	/* window on */
+	exynos_fimd_window_on(pvid->win_id);
+
+	exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
+}
+
+unsigned long exynos_fimd_calc_fbsize(void)
+{
+	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
+}
diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
new file mode 100644
index 0000000..b597acc
--- /dev/null
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <linux/compat.h>
+#include <linux/err.h>
+#include <asm/arch/dsim.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/power.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+#include "exynos_mipi_dsi_common.h"
+
+#define master_to_driver(a)	(a->dsim_lcd_drv)
+#define master_to_device(a)	(a->dsim_lcd_dev)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct exynos_platform_mipi_dsim *dsim_pd;
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static struct mipi_dsim_config dsim_config_dt;
+static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
+#endif
+
+struct mipi_dsim_ddi {
+	int				bus_id;
+	struct list_head		list;
+	struct mipi_dsim_lcd_device	*dsim_lcd_dev;
+	struct mipi_dsim_lcd_driver	*dsim_lcd_drv;
+};
+
+static LIST_HEAD(dsim_ddi_list);
+static LIST_HEAD(dsim_lcd_dev_list);
+
+int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+
+	if (!lcd_dev) {
+		debug("mipi_dsim_lcd_device is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (!lcd_dev->name) {
+		debug("dsim_lcd_device name is NULL.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL);
+	if (!dsim_ddi) {
+		debug("failed to allocate dsim_ddi object.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi->dsim_lcd_dev = lcd_dev;
+
+	list_add_tail(&dsim_ddi->list, &dsim_ddi_list);
+
+	return 0;
+}
+
+struct mipi_dsim_ddi
+	*exynos_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+	struct mipi_dsim_lcd_device *lcd_dev;
+
+	list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+		lcd_dev = dsim_ddi->dsim_lcd_dev;
+		if (!lcd_dev)
+			continue;
+
+		if (lcd_drv->id >= 0) {
+			if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0 &&
+					lcd_drv->id == lcd_dev->id) {
+				/**
+				 * bus_id would be used to identify
+				 * connected bus.
+				 */
+				dsim_ddi->bus_id = lcd_dev->bus_id;
+
+				return dsim_ddi;
+			}
+		} else {
+			if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) {
+				/**
+				 * bus_id would be used to identify
+				 * connected bus.
+				 */
+				dsim_ddi->bus_id = lcd_dev->bus_id;
+
+				return dsim_ddi;
+			}
+		}
+
+		kfree(dsim_ddi);
+		list_del(&dsim_ddi_list);
+	}
+
+	return NULL;
+}
+
+int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+
+	if (!lcd_drv) {
+		debug("mipi_dsim_lcd_driver is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (!lcd_drv->name) {
+		debug("dsim_lcd_driver name is NULL.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi = exynos_mipi_dsi_find_lcd_device(lcd_drv);
+	if (!dsim_ddi) {
+		debug("mipi_dsim_ddi object not found.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi->dsim_lcd_drv = lcd_drv;
+
+	debug("registered panel driver(%s) to mipi-dsi driver.\n",
+		lcd_drv->name);
+
+	return 0;
+
+}
+
+struct mipi_dsim_ddi
+	*exynos_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim,
+			const char *name)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+	struct mipi_dsim_lcd_driver *lcd_drv;
+	struct mipi_dsim_lcd_device *lcd_dev;
+
+	list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+		lcd_drv = dsim_ddi->dsim_lcd_drv;
+		lcd_dev = dsim_ddi->dsim_lcd_dev;
+		if (!lcd_drv || !lcd_dev)
+			continue;
+
+		debug("lcd_drv->id = %d, lcd_dev->id = %d\n",
+					lcd_drv->id, lcd_dev->id);
+
+		if ((strcmp(lcd_drv->name, name) == 0)) {
+			lcd_dev->master = dsim;
+
+			dsim->dsim_lcd_dev = lcd_dev;
+			dsim->dsim_lcd_drv = lcd_drv;
+
+			return dsim_ddi;
+		}
+	}
+
+	return NULL;
+}
+
+/* define MIPI-DSI Master operations. */
+static struct mipi_dsim_master_ops master_ops = {
+	.cmd_write			= exynos_mipi_dsi_wr_data,
+	.get_dsim_frame_done		= exynos_mipi_dsi_get_frame_done_status,
+	.clear_dsim_frame_done		= exynos_mipi_dsi_clear_frame_done,
+};
+
+int exynos_mipi_dsi_init(void)
+{
+	struct mipi_dsim_device *dsim;
+	struct mipi_dsim_config *dsim_config;
+	struct mipi_dsim_ddi *dsim_ddi;
+
+	dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL);
+	if (!dsim) {
+		debug("failed to allocate dsim object.\n");
+		return -EFAULT;
+	}
+
+	/* get mipi_dsim_config. */
+	dsim_config = dsim_pd->dsim_config;
+	if (dsim_config == NULL) {
+		debug("failed to get dsim config data.\n");
+		return -EFAULT;
+	}
+
+	dsim->pd = dsim_pd;
+	dsim->dsim_config = dsim_config;
+	dsim->master_ops = &master_ops;
+
+	/* bind lcd ddi matched with panel name. */
+	dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name);
+	if (!dsim_ddi) {
+		debug("mipi_dsim_ddi object not found.\n");
+		return -ENOSYS;
+	}
+	if (dsim_pd->lcd_power)
+		dsim_pd->lcd_power();
+
+	if (dsim_pd->mipi_power)
+		dsim_pd->mipi_power();
+
+	/* phy_enable(unsigned int dev_index, unsigned int enable) */
+	if (dsim_pd->phy_enable)
+		dsim_pd->phy_enable(0, 1);
+
+	set_mipi_clk();
+
+	exynos_mipi_dsi_init_dsim(dsim);
+	exynos_mipi_dsi_init_link(dsim);
+	exynos_mipi_dsi_set_hs_enable(dsim);
+
+	/* set display timing. */
+	exynos_mipi_dsi_set_display_mode(dsim, dsim->dsim_config);
+
+	/* initialize mipi-dsi client(lcd panel). */
+	if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->mipi_panel_init) {
+		dsim_ddi->dsim_lcd_drv->mipi_panel_init(dsim);
+		dsim_ddi->dsim_lcd_drv->mipi_display_on(dsim);
+	}
+
+	debug("mipi-dsi driver(%s mode) has been probed.\n",
+		(dsim_config->e_interface == DSIM_COMMAND) ?
+			"CPU" : "RGB");
+
+	return 0;
+}
+
+void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
+{
+	if (pd == NULL) {
+		debug("pd is NULL\n");
+		return;
+	}
+
+	dsim_pd = pd;
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+int exynos_dsim_config_parse_dt(const void *blob)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI);
+	if (node <= 0) {
+		printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n");
+		return -ENODEV;
+	}
+
+	dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-interface", 0);
+
+	dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-virtual-ch", 0);
+
+	dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-pixel-format", 0);
+
+	dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-burst-mode", 0);
+
+	dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-no-data-lane", 0);
+
+	dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-e-byte-clk", 0);
+
+	dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-hfp", 0);
+
+	dsim_config_dt.p = fdtdec_get_int(blob, node,
+					  "samsung,dsim-config-p", 0);
+	dsim_config_dt.m = fdtdec_get_int(blob, node,
+					  "samsung,dsim-config-m", 0);
+	dsim_config_dt.s = fdtdec_get_int(blob, node,
+					  "samsung,dsim-config-s", 0);
+
+	dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-pll-stable-time", 0);
+
+	dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-esc-clk", 0);
+
+	dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-stop-holding-cnt", 0);
+
+	dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-bta-timeout", 0);
+
+	dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+				"samsung,dsim-config-rx-timeout", 0);
+
+	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+				"samsung,dsim-device-name");
+
+	mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+				"samsung,dsim-device-id", 0);
+
+	mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+				"samsung,dsim-device-bus_id", 0);
+
+	mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+				"samsung,dsim-device-reverse-panel", 0);
+
+	return 0;
+}
+
+void exynos_init_dsim_platform_data(vidinfo_t *vid)
+{
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+		debug("Can't get proper dsim config.\n");
+
+	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
+	dsim_platform_data_dt.dsim_config = &dsim_config_dt;
+	dsim_platform_data_dt.mipi_power = mipi_power;
+	dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl;
+	dsim_platform_data_dt.lcd_panel_info = (void *)vid;
+
+	mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
+	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
+
+	dsim_pd = &dsim_platform_data_dt;
+}
+#endif
diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c
new file mode 100644
index 0000000..925d515
--- /dev/null
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.c
@@ -0,0 +1,620 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <linux/err.h>
+#include <asm/arch/dsim.h>
+#include <asm/arch/mipi_dsim.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+
+#define MHZ			(1000 * 1000)
+#define FIN_HZ			(24 * MHZ)
+
+#define DFIN_PLL_MIN_HZ		(6 * MHZ)
+#define DFIN_PLL_MAX_HZ		(12 * MHZ)
+
+#define DFVCO_MIN_HZ		(500 * MHZ)
+#define DFVCO_MAX_HZ		(1000 * MHZ)
+
+#define TRY_GET_FIFO_TIMEOUT	(5000 * 2)
+
+/* MIPI-DSIM status types. */
+enum {
+	DSIM_STATE_INIT,	/* should be initialized. */
+	DSIM_STATE_STOP,	/* CPU and LCDC are LP mode. */
+	DSIM_STATE_HSCLKEN,	/* HS clock was enabled. */
+	DSIM_STATE_ULPS
+};
+
+/* define DSI lane types. */
+enum {
+	DSIM_LANE_CLOCK = (1 << 0),
+	DSIM_LANE_DATA0 = (1 << 1),
+	DSIM_LANE_DATA1 = (1 << 2),
+	DSIM_LANE_DATA2 = (1 << 3),
+	DSIM_LANE_DATA3 = (1 << 4)
+};
+
+static unsigned int dpll_table[15] = {
+	100, 120, 170, 220, 270,
+	320, 390, 450, 510, 560,
+	640, 690, 770, 870, 950
+};
+
+static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
+		const unsigned char *data0, unsigned int data1)
+{
+	unsigned int data_cnt = 0, payload = 0;
+
+	/* in case that data count is more then 4 */
+	for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
+		/*
+		 * after sending 4bytes per one time,
+		 * send remainder data less then 4.
+		 */
+		if ((data1 - data_cnt) < 4) {
+			if ((data1 - data_cnt) == 3) {
+				payload = data0[data_cnt] |
+					data0[data_cnt + 1] << 8 |
+					data0[data_cnt + 2] << 16;
+			debug("count = 3 payload = %x, %x %x %x\n",
+				payload, data0[data_cnt],
+				data0[data_cnt + 1],
+				data0[data_cnt + 2]);
+			} else if ((data1 - data_cnt) == 2) {
+				payload = data0[data_cnt] |
+					data0[data_cnt + 1] << 8;
+			debug("count = 2 payload = %x, %x %x\n", payload,
+				data0[data_cnt], data0[data_cnt + 1]);
+			} else if ((data1 - data_cnt) == 1) {
+				payload = data0[data_cnt];
+			}
+		} else {
+			/* send 4bytes per one time. */
+			payload = data0[data_cnt] |
+				data0[data_cnt + 1] << 8 |
+				data0[data_cnt + 2] << 16 |
+				data0[data_cnt + 3] << 24;
+
+			debug("count = 4 payload = %x, %x %x %x %x\n",
+				payload, *(u8 *)(data0 + data_cnt),
+				data0[data_cnt + 1],
+				data0[data_cnt + 2],
+				data0[data_cnt + 3]);
+		}
+		exynos_mipi_dsi_wr_tx_data(dsim, payload);
+	}
+}
+
+int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+	const unsigned char *data0, unsigned int data1)
+{
+	unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
+	unsigned long delay_val, delay;
+	unsigned int check_rx_ack = 0;
+
+	if (dsim->state == DSIM_STATE_ULPS) {
+		debug("state is ULPS.\n");
+
+		return -EINVAL;
+	}
+
+	delay_val = MHZ / dsim->dsim_config->esc_clk;
+	delay = 10 * delay_val;
+
+	mdelay(delay);
+
+	/* only if transfer mode is LPDT, wait SFR becomes empty. */
+	if (dsim->state == DSIM_STATE_STOP) {
+		while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
+				SFR_HEADER_EMPTY)) {
+			if ((timeout--) > 0)
+				mdelay(1);
+			else {
+				debug("SRF header fifo is not empty.\n");
+				return -EINVAL;
+			}
+		}
+	}
+
+	switch (data_id) {
+	/* short packet types of packet types for command. */
+	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
+	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
+	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
+	case MIPI_DSI_DCS_SHORT_WRITE:
+	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
+		debug("data0 = %x data1 = %x\n",
+				data0[0], data0[1]);
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
+		if (check_rx_ack) {
+			/* process response func should be implemented */
+			return 0;
+		} else {
+			return -EINVAL;
+		}
+
+	/* general command */
+	case MIPI_DSI_COLOR_MODE_OFF:
+	case MIPI_DSI_COLOR_MODE_ON:
+	case MIPI_DSI_SHUTDOWN_PERIPHERAL:
+	case MIPI_DSI_TURN_ON_PERIPHERAL:
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
+		if (check_rx_ack) {
+			/* process response func should be implemented. */
+			return 0;
+		} else {
+			return -EINVAL;
+		}
+
+	/* packet types for video data */
+	case MIPI_DSI_V_SYNC_START:
+	case MIPI_DSI_V_SYNC_END:
+	case MIPI_DSI_H_SYNC_START:
+	case MIPI_DSI_H_SYNC_END:
+	case MIPI_DSI_END_OF_TRANSMISSION:
+		return 0;
+
+	/* short and response packet types for command */
+	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
+	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
+	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
+	case MIPI_DSI_DCS_READ:
+		exynos_mipi_dsi_clear_all_interrupt(dsim);
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
+		/* process response func should be implemented. */
+		return 0;
+
+	/* long packet type and null packet */
+	case MIPI_DSI_NULL_PACKET:
+	case MIPI_DSI_BLANKING_PACKET:
+		return 0;
+	case MIPI_DSI_GENERIC_LONG_WRITE:
+	case MIPI_DSI_DCS_LONG_WRITE:
+	{
+		unsigned int payload = 0;
+
+		/* if data count is less then 4, then send 3bytes data.  */
+		if (data1 < 4) {
+			payload = data0[0] |
+				data0[1] << 8 |
+				data0[2] << 16;
+
+			exynos_mipi_dsi_wr_tx_data(dsim, payload);
+
+			debug("count = %d payload = %x,%x %x %x\n",
+				data1, payload, data0[0],
+				data0[1], data0[2]);
+		} else {
+			/* in case that data count is more then 4 */
+			exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
+		}
+
+		/* put data into header fifo */
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
+			(data1 & 0xff00) >> 8);
+
+	}
+	if (check_rx_ack)
+		/* process response func should be implemented. */
+		return 0;
+	else
+		return -EINVAL;
+
+	/* packet typo for video data */
+	case MIPI_DSI_PACKED_PIXEL_STREAM_16:
+	case MIPI_DSI_PACKED_PIXEL_STREAM_18:
+	case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
+	case MIPI_DSI_PACKED_PIXEL_STREAM_24:
+		if (check_rx_ack) {
+			/* process response func should be implemented. */
+			return 0;
+		} else {
+			return -EINVAL;
+		}
+	default:
+		debug("data id %x is not supported current DSI spec.\n",
+			data_id);
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
+{
+	int sw_timeout;
+
+	if (enable) {
+		sw_timeout = 1000;
+
+		exynos_mipi_dsi_clear_interrupt(dsim);
+		exynos_mipi_dsi_enable_pll(dsim, 1);
+		while (1) {
+			sw_timeout--;
+			if (exynos_mipi_dsi_is_pll_stable(dsim))
+				return 0;
+			if (sw_timeout == 0)
+				return -EINVAL;
+		}
+	} else
+		exynos_mipi_dsi_enable_pll(dsim, 0);
+
+	return 0;
+}
+
+unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
+	unsigned int pre_divider, unsigned int main_divider,
+	unsigned int scaler)
+{
+	unsigned long dfin_pll, dfvco, dpll_out;
+	unsigned int i, freq_band = 0xf;
+
+	dfin_pll = (FIN_HZ / pre_divider);
+
+	/******************************************************
+	 *	Serial Clock(=ByteClk X 8)	FreqBand[3:0] *
+	 ******************************************************
+	 *	~ 99.99 MHz			0000
+	 *	100 ~ 119.99 MHz		0001
+	 *	120 ~ 159.99 MHz		0010
+	 *	160 ~ 199.99 MHz		0011
+	 *	200 ~ 239.99 MHz		0100
+	 *	140 ~ 319.99 MHz		0101
+	 *	320 ~ 389.99 MHz		0110
+	 *	390 ~ 449.99 MHz		0111
+	 *	450 ~ 509.99 MHz		1000
+	 *	510 ~ 559.99 MHz		1001
+	 *	560 ~ 639.99 MHz		1010
+	 *	640 ~ 689.99 MHz		1011
+	 *	690 ~ 769.99 MHz		1100
+	 *	770 ~ 869.99 MHz		1101
+	 *	870 ~ 949.99 MHz		1110
+	 *	950 ~ 1000 MHz			1111
+	 ******************************************************/
+	if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
+		debug("fin_pll range should be 6MHz ~ 12MHz\n");
+		exynos_mipi_dsi_enable_afc(dsim, 0, 0);
+	} else {
+		if (dfin_pll < 7 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
+		else if (dfin_pll < 8 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
+		else if (dfin_pll < 9 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
+		else if (dfin_pll < 10 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
+		else if (dfin_pll < 11 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
+		else
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
+	}
+
+	dfvco = dfin_pll * main_divider;
+	debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
+				dfvco, dfin_pll, main_divider);
+	if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
+		debug("fvco range should be 500MHz ~ 1000MHz\n");
+
+	dpll_out = dfvco / (1 << scaler);
+	debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
+		dpll_out, dfvco, scaler);
+
+	for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
+		if (dpll_out < dpll_table[i] * MHZ) {
+			freq_band = i;
+			break;
+		}
+	}
+
+	debug("freq_band = %d\n", freq_band);
+
+	exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
+
+	exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
+	exynos_mipi_dsi_prep_ctrl(dsim, 0);
+
+	/* Freq Band */
+	exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
+
+	/* Stable time */
+	exynos_mipi_dsi_pll_stable_time(dsim,
+				dsim->dsim_config->pll_stable_time);
+
+	/* Enable PLL */
+	debug("FOUT of mipi dphy pll is %luMHz\n",
+		(dpll_out / MHZ));
+
+	return dpll_out;
+}
+
+int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
+	unsigned int byte_clk_sel, unsigned int enable)
+{
+	unsigned int esc_div;
+	unsigned long esc_clk_error_rate;
+	unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
+
+	if (enable) {
+		dsim->e_clk_src = byte_clk_sel;
+
+		/* Escape mode clock and byte clock source */
+		exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
+
+		/* DPHY, DSIM Link : D-PHY clock out */
+		if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
+			hs_clk = exynos_mipi_dsi_change_pll(dsim,
+				dsim->dsim_config->p, dsim->dsim_config->m,
+				dsim->dsim_config->s);
+			if (hs_clk == 0) {
+				debug("failed to get hs clock.\n");
+				return -EINVAL;
+			}
+
+			byte_clk = hs_clk / 8;
+			exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
+			exynos_mipi_dsi_pll_on(dsim, 1);
+		/* DPHY : D-PHY clock out, DSIM link : external clock out */
+		} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
+			debug("not support EXT CLK source for MIPI DSIM\n");
+		else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
+			debug("not support EXT CLK source for MIPI DSIM\n");
+
+		/* escape clock divider */
+		esc_div = byte_clk / (dsim->dsim_config->esc_clk);
+		debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
+			esc_div, byte_clk, dsim->dsim_config->esc_clk);
+		if ((byte_clk / esc_div) >= (20 * MHZ) ||
+			(byte_clk / esc_div) > dsim->dsim_config->esc_clk)
+			esc_div += 1;
+
+		escape_clk = byte_clk / esc_div;
+		debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
+			escape_clk, byte_clk, esc_div);
+
+		/* enable escape clock. */
+		exynos_mipi_dsi_enable_byte_clock(dsim, 1);
+
+		/* enable byte clk and escape clock */
+		exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
+		/* escape clock on lane */
+		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
+			(DSIM_LANE_CLOCK | dsim->data_lane), 1);
+
+		debug("byte clock is %luMHz\n",
+			(byte_clk / MHZ));
+		debug("escape clock that user's need is %lu\n",
+			(dsim->dsim_config->esc_clk / MHZ));
+		debug("escape clock divider is %x\n", esc_div);
+		debug("escape clock is %luMHz\n",
+			((byte_clk / esc_div) / MHZ));
+
+		if ((byte_clk / esc_div) > escape_clk) {
+			esc_clk_error_rate = escape_clk /
+				(byte_clk / esc_div);
+			debug("error rate is %lu over.\n",
+				(esc_clk_error_rate / 100));
+		} else if ((byte_clk / esc_div) < (escape_clk)) {
+			esc_clk_error_rate = (byte_clk / esc_div) /
+				escape_clk;
+			debug("error rate is %lu under.\n",
+				(esc_clk_error_rate / 100));
+		}
+	} else {
+		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
+			(DSIM_LANE_CLOCK | dsim->data_lane), 0);
+		exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
+
+		/* disable escape clock. */
+		exynos_mipi_dsi_enable_byte_clock(dsim, 0);
+
+		if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
+			exynos_mipi_dsi_pll_on(dsim, 0);
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
+{
+	dsim->state = DSIM_STATE_INIT;
+
+	switch (dsim->dsim_config->e_no_data_lane) {
+	case DSIM_DATA_LANE_1:
+		dsim->data_lane = DSIM_LANE_DATA0;
+		break;
+	case DSIM_DATA_LANE_2:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
+		break;
+	case DSIM_DATA_LANE_3:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+			DSIM_LANE_DATA2;
+		break;
+	case DSIM_DATA_LANE_4:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+			DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
+		break;
+	default:
+		debug("data lane is invalid.\n");
+		return -EINVAL;
+	};
+
+	exynos_mipi_dsi_sw_reset(dsim);
+	exynos_mipi_dsi_dp_dn_swap(dsim, 0);
+
+	return 0;
+}
+
+int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	/* enable only frame done interrupt */
+	exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
+
+	return 0;
+}
+
+static void convert_to_fb_videomode(struct fb_videomode *mode1,
+				vidinfo_t *mode2)
+{
+	mode1->xres = mode2->vl_width;
+	mode1->yres = mode2->vl_height;
+	mode1->upper_margin = mode2->vl_vfpd;
+	mode1->lower_margin = mode2->vl_vbpd;
+	mode1->left_margin = mode2->vl_hfpd;
+	mode1->right_margin = mode2->vl_hbpd;
+	mode1->vsync_len = mode2->vl_vspw;
+	mode1->hsync_len = mode2->vl_hspw;
+}
+
+int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
+	struct mipi_dsim_config *dsim_config)
+{
+	struct exynos_platform_mipi_dsim *dsim_pd;
+	struct fb_videomode lcd_video;
+	vidinfo_t *vid;
+
+	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
+	vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
+
+	convert_to_fb_videomode(&lcd_video, vid);
+
+	/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
+	if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
+		if (dsim->dsim_config->auto_vertical_cnt == 0) {
+			exynos_mipi_dsi_set_main_disp_vporch(dsim,
+				vid->vl_cmd_allow_len,
+				lcd_video.upper_margin,
+				lcd_video.lower_margin);
+			exynos_mipi_dsi_set_main_disp_hporch(dsim,
+				lcd_video.left_margin,
+				lcd_video.right_margin);
+			exynos_mipi_dsi_set_main_disp_sync_area(dsim,
+				lcd_video.vsync_len,
+				lcd_video.hsync_len);
+		}
+	}
+
+	exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
+			lcd_video.yres);
+
+	exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
+
+	debug("lcd panel ==> width = %d, height = %d\n",
+			lcd_video.xres, lcd_video.yres);
+
+	return 0;
+}
+
+int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
+{
+	unsigned int time_out = 100;
+
+	switch (dsim->state) {
+	case DSIM_STATE_INIT:
+		exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
+
+		/* dsi configuration */
+		exynos_mipi_dsi_init_config(dsim);
+		exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
+		exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
+
+		/* set clock configuration */
+		exynos_mipi_dsi_set_clock(dsim,
+					dsim->dsim_config->e_byte_clk, 1);
+
+		/* check clock and data lane state are stop state */
+		while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
+			time_out--;
+			if (time_out == 0) {
+				debug("DSI Master is not stop state.\n");
+				debug("Check initialization process\n");
+
+				return -EINVAL;
+			}
+		}
+
+		dsim->state = DSIM_STATE_STOP;
+
+		/* BTA sequence counters */
+		exynos_mipi_dsi_set_stop_state_counter(dsim,
+			dsim->dsim_config->stop_holding_cnt);
+		exynos_mipi_dsi_set_bta_timeout(dsim,
+			dsim->dsim_config->bta_timeout);
+		exynos_mipi_dsi_set_lpdr_timeout(dsim,
+			dsim->dsim_config->rx_timeout);
+
+		return 0;
+	default:
+		debug("DSI Master is already init.\n");
+		return 0;
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
+{
+	if (dsim->state == DSIM_STATE_STOP) {
+		if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
+			dsim->state = DSIM_STATE_HSCLKEN;
+
+			 /* set LCDC and CPU transfer mode to HS. */
+			exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
+			exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
+
+			exynos_mipi_dsi_enable_hs_clock(dsim, 1);
+
+			return 0;
+		} else
+			debug("clock source is external bypass.\n");
+	} else
+		debug("DSIM is not stop state.\n");
+
+	return 0;
+}
+
+int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int mode)
+{
+	if (mode) {
+		if (dsim->state != DSIM_STATE_HSCLKEN) {
+			debug("HS Clock lane is not enabled.\n");
+			return -EINVAL;
+		}
+
+		exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
+	} else {
+		if (dsim->state == DSIM_STATE_INIT || dsim->state ==
+			DSIM_STATE_ULPS) {
+			debug("DSI Master is not STOP or HSDT state.\n");
+			return -EINVAL;
+		}
+
+		exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
+{
+	return _exynos_mipi_dsi_get_frame_done_status(dsim);
+}
+
+int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
+{
+	_exynos_mipi_dsi_clear_frame_done(dsim);
+
+	return 0;
+}
diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.h b/drivers/video/exynos/exynos_mipi_dsi_common.h
new file mode 100644
index 0000000..98eb78e
--- /dev/null
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/fb.h>
+
+#ifndef _EXYNOS_MIPI_DSI_COMMON_H
+#define _EXYNOS_MIPI_DSI_COMMON_H
+
+int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+	const unsigned char *data0, unsigned int data1);
+int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable);
+unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
+	unsigned int pre_divider, unsigned int main_divider,
+	unsigned int scaler);
+int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
+	unsigned int byte_clk_sel, unsigned int enable);
+int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
+			struct mipi_dsim_config *dsim_info);
+int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int mode);
+int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
+	unsigned int enable);
+int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
+
+#endif /* _EXYNOS_MIPI_DSI_COMMON_H */
diff --git a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
new file mode 100644
index 0000000..fcfdc8d
--- /dev/null
+++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/dsim.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/power.h>
+#include <asm/arch/cpu.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+#include "exynos_mipi_dsi_common.h"
+
+void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
+{
+	unsigned int reg;
+
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->swrst);
+
+	reg |= DSIM_FUNCRST;
+
+	writel(reg, &mipi_dsim->swrst);
+}
+
+void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
+{
+	unsigned int reg = 0;
+
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->swrst);
+
+	reg |= DSIM_SWRST;
+	reg |= DSIM_FUNCRST;
+
+	writel(reg, &mipi_dsim->swrst);
+}
+
+void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	reg |= INTSRC_SWRST_RELEASE;
+
+	writel(reg, &mipi_dsim->intsrc);
+}
+
+void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
+		unsigned int mode, unsigned int mask)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intmsk);
+
+	if (mask)
+		reg |= mode;
+	else
+		reg &= ~mode;
+
+	writel(reg, &mipi_dsim->intmsk);
+}
+
+void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
+		unsigned int cfg)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->fifoctrl);
+
+	writel(reg & ~(cfg), &mipi_dsim->fifoctrl);
+	udelay(10 * 1000);
+	reg |= cfg;
+
+	writel(reg, &mipi_dsim->fifoctrl);
+}
+
+/*
+ * this function set PLL P, M and S value in D-PHY
+ */
+void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+		unsigned int value)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr);
+}
+
+void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
+	unsigned int width_resol, unsigned int height_resol)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	/* standby should be set after configuration so set to not ready*/
+	reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY);
+	writel(reg, &mipi_dsim->mdresol);
+
+	/* reset resolution */
+	reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff));
+	reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
+
+	reg |= DSIM_MAIN_STAND_BY;
+	writel(reg, &mipi_dsim->mdresol);
+}
+
+void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
+	unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->mvporch)) &
+		~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
+		(DSIM_MAIN_VBP_MASK));
+
+	reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |
+		((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |
+		((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);
+
+	writel(reg, &mipi_dsim->mvporch);
+}
+
+void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
+	unsigned int front, unsigned int back)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->mhporch)) &
+		~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
+
+	reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);
+
+	writel(reg, &mipi_dsim->mhporch);
+}
+
+void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
+	unsigned int vert, unsigned int hori)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->msync)) &
+		~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
+
+	reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |
+		(hori << DSIM_MAIN_HSA_SHIFT);
+
+	writel(reg, &mipi_dsim->msync);
+}
+
+void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
+	unsigned int vert, unsigned int hori)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->sdresol)) &
+		~(DSIM_SUB_STANDY_MASK);
+
+	writel(reg, &mipi_dsim->sdresol);
+
+	reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
+	reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |
+		((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);
+	writel(reg, &mipi_dsim->sdresol);
+
+	/* DSIM STANDBY */
+	reg |= (1 << DSIM_SUB_STANDY_SHIFT);
+	writel(reg, &mipi_dsim->sdresol);
+}
+
+void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
+{
+	struct mipi_dsim_config *dsim_config = dsim->dsim_config;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int cfg = (readl(&mipi_dsim->config)) &
+		~((1 << DSIM_EOT_PACKET_SHIFT) |
+		(0x1f << DSIM_HSA_MODE_SHIFT) |
+		(0x3 << DSIM_NUM_OF_DATALANE_SHIFT));
+
+	cfg |=	(dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) |
+		(dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) |
+		(dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |
+		(dsim_config->hse << DSIM_HSE_MODE_SHIFT) |
+		(dsim_config->hfp << DSIM_HFP_MODE_SHIFT) |
+		(dsim_config->hbp << DSIM_HBP_MODE_SHIFT) |
+		(dsim_config->hsa << DSIM_HSA_MODE_SHIFT) |
+		(dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);
+
+	writel(cfg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
+				struct mipi_dsim_config *dsim_config)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	u32 reg = (readl(&mipi_dsim->config)) &
+		~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT)
+		| (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT)
+		| (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT));
+
+	if (dsim_config->e_interface == DSIM_VIDEO)
+		reg |= (1 << DSIM_VIDEO_MODE_SHIFT);
+	else if (dsim_config->e_interface == DSIM_COMMAND)
+		reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT);
+	else {
+		printf("unknown lcd type.\n");
+		return;
+	}
+
+	/* main lcd */
+	reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT
+	| ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT
+	| ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT;
+
+	writel(reg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
+			unsigned int lane, unsigned int enable)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->config);
+
+	if (enable)
+		reg |= DSIM_LANE_ENx(lane);
+	else
+		reg &= ~DSIM_LANE_ENx(lane);
+
+	writel(reg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+	unsigned int count)
+{
+	unsigned int cfg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	/* get the data lane number. */
+	cfg = DSIM_NUM_OF_DATA_LANE(count);
+
+	writel(cfg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
+			unsigned int enable, unsigned int afc_code)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->phyacchr);
+
+	reg = 0;
+
+	if (enable) {
+		reg |= DSIM_AFC_EN;
+		reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT);
+		reg |= DSIM_AFC_CTL(afc_code);
+	} else
+		reg &= ~DSIM_AFC_EN;
+
+	writel(reg, &mipi_dsim->phyacchr);
+}
+
+void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(DSIM_PLL_BYPASS_EXTERNAL);
+
+	reg |= enable << DSIM_PLL_BYPASS_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
+		unsigned int freq_band)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x1f << DSIM_FREQ_BAND_SHIFT);
+
+	reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
+		unsigned int pre_divider, unsigned int main_divider,
+		unsigned int scaler)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x7ffff << 1);
+
+	reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) |
+		((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) |
+		((scaler & 0x7) << DSIM_SCALER_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
+	unsigned int lock_time)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(lock_time, &mipi_dsim->plltmr);
+}
+
+void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
+				unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x1 << DSIM_PLL_EN_SHIFT);
+
+	reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
+		unsigned int src)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);
+
+	reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
+		unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(1 << DSIM_BYTE_CLKEN_SHIFT);
+
+	reg |= enable << DSIM_BYTE_CLKEN_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
+		unsigned int enable, unsigned int prs_val)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff));
+
+	reg |= enable << DSIM_ESC_CLKEN_SHIFT;
+	if (enable)
+		reg |= prs_val;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
+		unsigned int lane_sel, unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->clkctrl);
+
+	if (enable)
+		reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
+	else
+		reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->escmode)) &
+		~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);
+
+	reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->status);
+
+	/**
+	 * check clock and data lane states.
+	 * if MIPI-DSI controller was enabled at bootloader then
+	 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
+	 * so it should be checked for two case.
+	 */
+	if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
+			((reg & DSIM_STOP_STATE_CLK) ||
+			 (reg & DSIM_TX_READY_HS_CLK)))
+		return 1;
+	else
+		return 0;
+}
+
+void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
+		unsigned int cnt_val)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->escmode)) &
+		~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);
+
+	reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
+		unsigned int timeout)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->timeout)) &
+		~(0xff << DSIM_BTA_TOUT_SHIFT);
+
+	reg |= (timeout << DSIM_BTA_TOUT_SHIFT);
+
+	writel(reg, &mipi_dsim->timeout);
+}
+
+void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
+		unsigned int timeout)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->timeout)) &
+		~(0xffff << DSIM_LPDR_TOUT_SHIFT);
+
+	reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);
+
+	writel(reg, &mipi_dsim->timeout);
+}
+
+void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int lp)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->escmode);
+
+	reg &= ~DSIM_CMD_LPDT_LP;
+
+	if (lp)
+		reg |= DSIM_CMD_LPDT_LP;
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int lp)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->escmode);
+
+	reg &= ~DSIM_TX_LPDT_LP;
+
+	if (lp)
+		reg |= DSIM_TX_LPDT_LP;
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
+		unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);
+
+	reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
+		unsigned int swap_en)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->phyacchr1);
+
+	reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT);
+	reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT;
+
+	writel(reg, &mipi_dsim->phyacchr1);
+}
+
+void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
+		unsigned int hs_zero)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0xf << DSIM_ZEROCTRL_SHIFT);
+
+	reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x7 << DSIM_PRECTRL_SHIFT);
+
+	reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	reg |= INTSRC_PLL_STABLE;
+
+	writel(reg, &mipi_dsim->intsrc);
+}
+
+void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(0xffffffff, &mipi_dsim->intsrc);
+}
+
+unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->status);
+
+	return reg & DSIM_PLL_STABLE ? 1 : 0;
+}
+
+unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	return readl(&mipi_dsim->fifoctrl) & ~(0x1f);
+}
+
+void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
+	unsigned int di, const unsigned char data0, const unsigned char data1)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) |
+			DSIM_PKTHDR_DI(di));
+
+	writel(reg, &mipi_dsim->pkthdr);
+}
+
+unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
+						*dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
+}
+
+void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc);
+}
+
+void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
+		unsigned int tx_data)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(tx_data, &mipi_dsim->payload);
+}
diff --git a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.h
new file mode 100644
index 0000000..0bede25
--- /dev/null
+++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_MIPI_DSI_LOWLEVEL_H
+#define _EXYNOS_MIPI_DSI_LOWLEVEL_H
+
+void exynos_mipi_dsi_register(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
+	unsigned int mode, unsigned int mask);
+void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+					unsigned int count);
+void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
+					unsigned int cfg);
+void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+				unsigned int value);
+void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+				unsigned int value);
+void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
+		unsigned int width_resol, unsigned int height_resol);
+void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
+	unsigned int cmd_allow, unsigned int vfront, unsigned int vback);
+void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
+			unsigned int front, unsigned int back);
+void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
+				unsigned int vert, unsigned int hori);
+void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
+				unsigned int vert, unsigned int hori);
+void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
+				struct mipi_dsim_config *dsim_config);
+void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+				unsigned int count);
+void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
+			unsigned int lane, unsigned int enable);
+void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
+			unsigned int enable, unsigned int afc_code);
+void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
+				unsigned int enable);
+void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
+				unsigned int freq_band);
+void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
+			unsigned int pre_divider, unsigned int main_divider,
+			unsigned int scaler);
+void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
+			unsigned int lock_time);
+void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
+					unsigned int enable);
+void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
+					unsigned int src);
+void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
+					unsigned int enable);
+void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
+				unsigned int enable, unsigned int prs_val);
+void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
+				unsigned int lane_sel, unsigned int enable);
+void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
+				unsigned int enable);
+unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
+				unsigned int cnt_val);
+void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
+				unsigned int timeout);
+void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
+				unsigned int timeout);
+void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
+					unsigned int lp);
+void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
+					unsigned int lp);
+void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
+				unsigned int enable);
+void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
+				unsigned int swap_en);
+void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
+				unsigned int hs_zero);
+void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim,
+				unsigned int prep);
+void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim);
+unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim);
+unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim);
+unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
+						*dsim);
+void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
+		unsigned int di, const unsigned char data0, const unsigned char data1);
+void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
+		unsigned int tx_data);
+
+#endif /* _EXYNOS_MIPI_DSI_LOWLEVEL_H */
diff --git a/drivers/video/exynos/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c
new file mode 100644
index 0000000..a6890da
--- /dev/null
+++ b/drivers/video/exynos/exynos_pwm_bl.c
@@ -0,0 +1,45 @@
+/*
+ * PWM BACKLIGHT driver for Board based on EXYNOS.
+ *
+ * Author: Donghwa Lee  <dh09.lee@samsung.com>
+ *
+ * Derived from linux/drivers/video/backlight/pwm_backlight.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <pwm.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/pwm_backlight.h>
+
+static struct pwm_backlight_data *pwm;
+
+static int exynos_pwm_backlight_update_status(void)
+{
+	int brightness = pwm->brightness;
+	int max = pwm->max_brightness;
+
+	if (brightness == 0) {
+		pwm_config(pwm->pwm_id, 0, pwm->period);
+		pwm_disable(pwm->pwm_id);
+	} else {
+		pwm_config(pwm->pwm_id,
+			brightness * pwm->period / max, pwm->period);
+		pwm_enable(pwm->pwm_id);
+	}
+	return 0;
+}
+
+int exynos_pwm_backlight_init(struct pwm_backlight_data *pd)
+{
+	pwm = pd;
+
+	exynos_pwm_backlight_update_status();
+
+	return 0;
+}
diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos_dp.c
deleted file mode 100644
index 0d5d090..0000000
--- a/drivers/video/exynos_dp.c
+++ /dev/null
@@ -1,961 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <linux/compat.h>
-#include <linux/err.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dp_info.h>
-#include <asm/arch/dp.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-
-#include "exynos_dp_lowlevel.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void __exynos_set_dp_phy(unsigned int onoff)
-{
-}
-void exynos_set_dp_phy(unsigned int onoff)
-	__attribute__((weak, alias("__exynos_set_dp_phy")));
-
-static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
-{
-	disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
-		disp_info->h_back_porch + disp_info->h_front_porch;
-	disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
-		disp_info->v_back_porch + disp_info->v_front_porch;
-
-	return;
-}
-
-static int exynos_dp_init_dp(void)
-{
-	int ret;
-	exynos_dp_reset();
-
-	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_func(DP_ENABLE);
-
-	ret = exynos_dp_init_analog_func();
-	if (ret != EXYNOS_DP_SUCCESS)
-		return ret;
-
-	exynos_dp_init_hpd();
-	exynos_dp_init_aux();
-
-	return ret;
-}
-
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
-{
-	int i;
-	unsigned char sum = 0;
-
-	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
-		sum = sum + edid_data[i];
-
-	return sum;
-}
-
-static unsigned int exynos_dp_read_edid(void)
-{
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
-	unsigned int extend_block = 0;
-	unsigned char sum;
-	unsigned char test_vector;
-	int retval;
-
-	/*
-	 * EDID device address is 0x50.
-	 * However, if necessary, you must have set upper address
-	 * into E-EDID in I2C device, 0x30.
-	 */
-
-	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
-			&extend_block);
-
-	if (extend_block > 0) {
-		printf("DP EDID data includes a single extension!\n");
-
-		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
-						EDID_HEADER_PATTERN,
-						EDID_BLOCK_LENGTH,
-						&edid[EDID_HEADER_PATTERN]);
-		if (retval != 0) {
-			printf("DP EDID Read failed!\n");
-			return -1;
-		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
-		if (sum != 0) {
-			printf("DP EDID bad checksum!\n");
-			return -1;
-		}
-
-		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
-				EDID_BLOCK_LENGTH,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_BLOCK_LENGTH]);
-		if (retval != 0) {
-			printf("DP EDID Read failed!\n");
-			return -1;
-		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
-		if (sum != 0) {
-			printf("DP EDID bad checksum!\n");
-			return -1;
-		}
-
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
-					&test_vector);
-		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
-				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
-				DPCD_TEST_EDID_CHECKSUM_WRITE);
-		}
-	} else {
-		debug("DP EDID data does not include any extensions.\n");
-
-		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
-
-		if (retval != 0) {
-			printf("DP EDID Read failed!\n");
-			return -1;
-		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
-		if (sum != 0) {
-			printf("DP EDID bad checksum!\n");
-			return -1;
-		}
-
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
-			&test_vector);
-		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
-				DPCD_TEST_EDID_CHECKSUM_WRITE);
-		}
-	}
-
-	debug("DP EDID Read success!\n");
-
-	return 0;
-}
-
-static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
-{
-	unsigned char buf[12];
-	unsigned int ret;
-	unsigned char temp;
-	unsigned char retry_cnt;
-	unsigned char dpcd_rev[16];
-	unsigned char lane_bw[16];
-	unsigned char lane_cnt[16];
-
-	memset(dpcd_rev, 0, 16);
-	memset(lane_bw, 0, 16);
-	memset(lane_cnt, 0, 16);
-	memset(buf, 0, 12);
-
-	retry_cnt = 5;
-	while (retry_cnt) {
-		/* Read DPCD 0x0000-0x000b */
-		ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
-				buf);
-		if (ret != EXYNOS_DP_SUCCESS) {
-			if (retry_cnt == 0) {
-				printf("DP read_byte_from_dpcd() failed\n");
-				return ret;
-			}
-			retry_cnt--;
-		} else
-			break;
-	}
-
-	/* */
-	temp = buf[DPCD_DPCD_REV];
-	if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
-		edp_info->dpcd_rev = temp;
-	else {
-		printf("DP Wrong DPCD Rev : %x\n", temp);
-		return -ENODEV;
-	}
-
-	temp = buf[DPCD_MAX_LINK_RATE];
-	if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
-		edp_info->lane_bw = temp;
-	else {
-		printf("DP Wrong MAX LINK RATE : %x\n", temp);
-		return -EINVAL;
-	}
-
-	/* Refer VESA Display Port Standard Ver1.1a Page 120 */
-	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
-		temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
-		if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
-			edp_info->dpcd_efc = 1;
-		else
-			edp_info->dpcd_efc = 0;
-	} else {
-		temp = buf[DPCD_MAX_LANE_COUNT];
-		edp_info->dpcd_efc = 0;
-	}
-
-	if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
-			temp == DP_LANE_CNT_4) {
-		edp_info->lane_cnt = temp;
-	} else {
-		printf("DP Wrong MAX LANE COUNT : %x\n", temp);
-		return -EINVAL;
-	}
-
-	ret = exynos_dp_read_edid();
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP exynos_dp_read_edid() failed\n");
-		return -EINVAL;
-	}
-
-	return ret;
-}
-
-static void exynos_dp_init_training(void)
-{
-	/*
-	 * MACRO_RST must be applied after the PLL_LOCK to avoid
-	 * the DP inter pair skew issue for at least 10 us
-	 */
-	exynos_dp_reset_macro();
-
-	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(POWER_ALL, 0);
-}
-
-static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
-{
-	unsigned char buf[5];
-	unsigned int ret = 0;
-
-	debug("DP: %s was called\n", __func__);
-
-	edp_info->lt_info.lt_status = DP_LT_CR;
-	edp_info->lt_info.ep_loop = 0;
-	edp_info->lt_info.cr_loop[0] = 0;
-	edp_info->lt_info.cr_loop[1] = 0;
-	edp_info->lt_info.cr_loop[2] = 0;
-	edp_info->lt_info.cr_loop[3] = 0;
-
-		/* Set sink to D0 (Sink Not Ready) mode. */
-		ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
-				DPCD_SET_POWER_STATE_D0);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP write_dpcd_byte failed\n");
-		return ret;
-	}
-
-	/* Set link rate and count as you want to establish */
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
-
-	/* Setup RX configuration */
-	buf[0] = edp_info->lane_bw;
-	buf[1] = edp_info->lane_cnt;
-
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
-			buf);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP write_dpcd_byte failed\n");
-		return ret;
-	}
-
-	exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
-			edp_info->lane_cnt);
-
-	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(TRAINING_PTN1);
-
-	/* Set RX training pattern */
-	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
-
-	buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
-		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
-	buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
-		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
-	buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
-		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
-	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
-		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
-
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			5, buf);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP write_dpcd_byte failed\n");
-		return ret;
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_training_pattern_dis(void)
-{
-	unsigned int ret = EXYNOS_DP_SUCCESS;
-
-	exynos_dp_set_training_pattern(DP_NONE);
-
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			DPCD_TRAINING_PATTERN_DISABLED);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP request_link_training_req failed\n");
-		return -EAGAIN;
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
-{
-	unsigned char data;
-	unsigned int ret = EXYNOS_DP_SUCCESS;
-
-	ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
-			&data);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP read_from_dpcd failed\n");
-		return -EAGAIN;
-	}
-
-	if (enable)
-		data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
-	else
-		data = DPCD_LN_COUNT_SET(data);
-
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
-			data);
-	if (ret != EXYNOS_DP_SUCCESS) {
-			printf("DP write_to_dpcd failed\n");
-			return -EAGAIN;
-
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
-{
-	unsigned int ret = EXYNOS_DP_SUCCESS;
-
-	ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP rx_enhance_mode failed\n");
-		return -EAGAIN;
-	}
-
-	exynos_dp_enable_enhanced_mode(enhance_mode);
-
-	return ret;
-}
-
-static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
-		unsigned char *status)
-{
-	unsigned int ret, i;
-	unsigned char buf[2];
-	unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
-	unsigned char shift_val[DP_LANE_CNT_4] = {0,};
-
-	shift_val[0] = 0;
-	shift_val[1] = 4;
-	shift_val[2] = 0;
-	shift_val[3] = 4;
-
-	ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP read lane status failed\n");
-		return ret;
-	}
-
-	for (i = 0; i < edp_info->lane_cnt; i++) {
-		lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
-		if (lane_stat[0] != lane_stat[i]) {
-			printf("Wrong lane status\n");
-			return -EINVAL;
-		}
-	}
-
-	*status = lane_stat[0];
-
-	return ret;
-}
-
-static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
-		unsigned char *sw, unsigned char *em)
-{
-	unsigned int ret = EXYNOS_DP_SUCCESS;
-	unsigned char buf;
-	unsigned int dpcd_addr;
-	unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
-
-	/* lane_num value is used as array index, so this range 0 ~ 3 */
-	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
-
-	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP read adjust request failed\n");
-		return -EAGAIN;
-	}
-
-	*sw = ((buf >> shift_val[lane_num]) & 0x03);
-	*em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
-
-	return ret;
-}
-
-static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
-{
-	int ret;
-
-	ret = exynos_dp_training_pattern_dis();
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP training_pattern_disable() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-	}
-
-	ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP set_enhanced_mode() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-	}
-
-	return ret;
-}
-
-static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
-{
-	int ret;
-
-	if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		edp_info->lane_bw = DP_LANE_BW_1_62;
-		printf("DP Change lane bw to 1.62Gbps\n");
-		edp_info->lt_info.lt_status = DP_LT_START;
-		ret = EXYNOS_DP_SUCCESS;
-	} else {
-		ret = exynos_dp_training_pattern_dis();
-		if (ret != EXYNOS_DP_SUCCESS)
-			printf("DP training_patter_disable() failed\n");
-
-		ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
-		if (ret != EXYNOS_DP_SUCCESS)
-			printf("DP set_enhanced_mode() failed\n");
-
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
-							*edp_info)
-{
-	unsigned int ret = EXYNOS_DP_SUCCESS;
-	unsigned char lane_stat;
-	unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
-	unsigned int i;
-	unsigned char adj_req_sw;
-	unsigned char adj_req_em;
-	unsigned char buf[5];
-
-	debug("DP: %s was called\n", __func__);
-	mdelay(1);
-
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
-	if (ret != EXYNOS_DP_SUCCESS) {
-			printf("DP read lane status failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
-			return ret;
-	}
-
-	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		debug("DP clock Recovery training succeed\n");
-		exynos_dp_set_training_pattern(TRAINING_PTN2);
-
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
-					&adj_req_em);
-			if (ret != EXYNOS_DP_SUCCESS) {
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
-				return ret;
-			}
-
-			lt_ctl_val[i] = 0;
-			lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
-
-			if ((adj_req_sw == VOLTAGE_LEVEL_3)
-				|| (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
-				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
-					MAX_PRE_EMPHASIS_REACH_3;
-			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
-		}
-
-		buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
-		buf[1] = lt_ctl_val[0];
-		buf[2] = lt_ctl_val[1];
-		buf[3] = lt_ctl_val[2];
-		buf[4] = lt_ctl_val[3];
-
-		ret = exynos_dp_write_bytes_to_dpcd(
-				DPCD_TRAINING_PATTERN_SET, 5, buf);
-		if (ret != EXYNOS_DP_SUCCESS) {
-			printf("DP write training pattern1 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
-			return ret;
-		} else
-			edp_info->lt_info.lt_status = DP_LT_ET;
-	} else {
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
-				ret = exynos_dp_read_dpcd_adj_req(i,
-						&adj_req_sw, &adj_req_em);
-			if (ret != EXYNOS_DP_SUCCESS) {
-				printf("DP read adj req failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
-				return ret;
-			}
-
-			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
-					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
-				ret = exynos_dp_reduce_link_rate(edp_info);
-
-			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
-						adj_req_sw) &&
-				(PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
-						adj_req_em)) {
-				edp_info->lt_info.cr_loop[i]++;
-				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
-					ret = exynos_dp_reduce_link_rate(
-							edp_info);
-			}
-
-			lt_ctl_val[i] = 0;
-			lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
-
-			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
-					(adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
-				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
-					MAX_PRE_EMPHASIS_REACH_3;
-			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
-		}
-
-		ret = exynos_dp_write_bytes_to_dpcd(
-				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
-		if (ret != EXYNOS_DP_SUCCESS) {
-			printf("DP write training pattern2 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
-			return ret;
-		}
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
-		*edp_info)
-{
-	unsigned int ret = EXYNOS_DP_SUCCESS;
-	unsigned char lane_stat, adj_req_sw, adj_req_em, i;
-	unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
-	unsigned char interlane_aligned = 0;
-	unsigned char f_bw;
-	unsigned char f_lane_cnt;
-	unsigned char sink_stat;
-
-	mdelay(1);
-
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP read lane status failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		return ret;
-	}
-
-	debug("DP lane stat : %x\n", lane_stat);
-
-	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
-				&sink_stat);
-		if (ret != EXYNOS_DP_SUCCESS) {
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
-
-			return ret;
-		}
-
-		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
-
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i,
-					&adj_req_sw, &adj_req_em);
-			if (ret != EXYNOS_DP_SUCCESS) {
-				printf("DP read adj req 1 failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
-
-				return ret;
-			}
-
-			lt_ctl_val[i] = 0;
-			lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
-
-			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
-				(adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
-				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
-				lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
-			}
-		}
-
-		if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
-			(lane_stat&DP_LANE_STAT_SYM_LOCK))
-			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
-			debug("DP Equalizer training succeed\n");
-
-			f_bw = exynos_dp_get_link_bandwidth();
-			f_lane_cnt = exynos_dp_get_lane_count();
-
-			debug("DP final BandWidth : %x\n", f_bw);
-			debug("DP final Lane Count : %x\n", f_lane_cnt);
-
-			edp_info->lt_info.lt_status = DP_LT_FINISHED;
-
-			exynos_dp_equalizer_err_link(edp_info);
-
-		} else {
-			edp_info->lt_info.ep_loop++;
-
-			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
-				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-					ret = exynos_dp_reduce_link_rate(
-							edp_info);
-				} else {
-					edp_info->lt_info.lt_status =
-								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
-				}
-			} else {
-				for (i = 0; i < edp_info->lane_cnt; i++)
-					exynos_dp_set_lanex_pre_emphasis(
-							lt_ctl_val[i], i);
-
-				ret = exynos_dp_write_bytes_to_dpcd(
-					DPCD_TRAINING_LANE0_SET,
-					4, lt_ctl_val);
-				if (ret != EXYNOS_DP_SUCCESS) {
-					printf("DP set lt pattern failed\n");
-					edp_info->lt_info.lt_status =
-								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
-				}
-			}
-		}
-	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		ret = exynos_dp_reduce_link_rate(edp_info);
-	} else {
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		exynos_dp_equalizer_err_link(edp_info);
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
-{
-	unsigned int ret = 0;
-	int training_finished;
-
-	/* Turn off unnecessary lane */
-	if (edp_info->lane_cnt == 1)
-		exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
-
-	training_finished = 0;
-
-	edp_info->lt_info.lt_status = DP_LT_START;
-
-	/* Process here */
-	while (!training_finished) {
-		switch (edp_info->lt_info.lt_status) {
-		case DP_LT_START:
-			ret = exynos_dp_link_start(edp_info);
-			if (ret != EXYNOS_DP_SUCCESS) {
-				printf("DP LT:link start failed\n");
-				return ret;
-			}
-			break;
-		case DP_LT_CR:
-			ret = exynos_dp_process_clock_recovery(edp_info);
-			if (ret != EXYNOS_DP_SUCCESS) {
-				printf("DP LT:clock recovery failed\n");
-				return ret;
-			}
-			break;
-		case DP_LT_ET:
-			ret = exynos_dp_process_equalizer_training(edp_info);
-			if (ret != EXYNOS_DP_SUCCESS) {
-				printf("DP LT:equalizer training failed\n");
-				return ret;
-			}
-			break;
-		case DP_LT_FINISHED:
-			training_finished = 1;
-			break;
-		case DP_LT_FAIL:
-			return -1;
-		}
-	}
-
-	return ret;
-}
-
-static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
-{
-	unsigned int ret;
-
-	exynos_dp_init_training();
-
-	ret = exynos_dp_sw_link_training(edp_info);
-	if (ret != EXYNOS_DP_SUCCESS)
-		printf("DP dp_sw_link_training() failed\n");
-
-	return ret;
-}
-
-static void exynos_dp_enable_scramble(unsigned int enable)
-{
-	unsigned char data;
-
-	if (enable) {
-		exynos_dp_enable_scrambling(DP_ENABLE);
-
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
-	} else {
-		exynos_dp_enable_scrambling(DP_DISABLE);
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			(u8)(data | DPCD_SCRAMBLING_DISABLED));
-	}
-}
-
-static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
-{
-	unsigned int ret = 0;
-	unsigned int retry_cnt;
-
-	mdelay(1);
-
-	if (edp_info->video_info.master_mode) {
-		printf("DP does not support master mode\n");
-		return -ENODEV;
-	} else {
-		/* debug slave */
-		exynos_dp_config_video_slave_mode(&edp_info->video_info);
-	}
-
-	exynos_dp_set_video_color_format(&edp_info->video_info);
-
-	if (edp_info->video_info.bist_mode) {
-		if (exynos_dp_config_video_bist(edp_info) != 0)
-			return -1;
-	}
-
-	ret = exynos_dp_get_pll_lock_status();
-	if (ret != PLL_LOCKED) {
-		printf("DP PLL is not locked yet\n");
-		return -EIO;
-	}
-
-	if (edp_info->video_info.master_mode == 0) {
-		retry_cnt = 10;
-		while (retry_cnt) {
-			ret = exynos_dp_is_slave_video_stream_clock_on();
-			if (ret != EXYNOS_DP_SUCCESS) {
-				if (retry_cnt == 0) {
-					printf("DP stream_clock_on failed\n");
-					return ret;
-				}
-				retry_cnt--;
-				mdelay(1);
-			} else
-				break;
-		}
-	}
-
-	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
-
-	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
-
-	/* Enable video bist */
-	if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
-		edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
-		edp_info->video_info.bist_pattern != COLOR_SQUARE)
-		exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
-	else
-		exynos_dp_enable_video_bist(DP_DISABLE);
-
-	/* Disable video mute */
-	exynos_dp_enable_video_mute(DP_DISABLE);
-
-	/* Configure video Master or Slave mode */
-	exynos_dp_enable_video_master(edp_info->video_info.master_mode);
-
-	/* Enable video */
-	exynos_dp_start_video();
-
-	if (edp_info->video_info.master_mode == 0) {
-		retry_cnt = 100;
-		while (retry_cnt) {
-			ret = exynos_dp_is_video_stream_on();
-			if (ret != EXYNOS_DP_SUCCESS) {
-				if (retry_cnt == 0) {
-					printf("DP Timeout of video stream\n");
-					return ret;
-				}
-				retry_cnt--;
-				mdelay(5);
-			} else
-				break;
-		}
-	}
-
-	return ret;
-}
-
-int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
-{
-	unsigned int node = fdtdec_next_compatible(blob, 0,
-						COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0) {
-		debug("exynos_dp: Can't get device node for dp\n");
-		return -ENODEV;
-	}
-
-	edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
-							"samsung,h-res", 0);
-	edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
-						"samsung,h-sync-width", 0);
-	edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
-						"samsung,h-back-porch", 0);
-	edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
-						"samsung,h-front-porch", 0);
-	edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
-						"samsung,v-res", 0);
-	edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
-						"samsung,v-sync-width", 0);
-	edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
-						"samsung,v-back-porch", 0);
-	edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
-						"samsung,v-front-porch", 0);
-	edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
-						"samsung,v-sync-rate", 0);
-
-	edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
-						"samsung,lt-status", 0);
-
-	edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
-						"samsung,master-mode", 0);
-	edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
-						"samsung,bist-mode", 0);
-	edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
-						"samsung,bist-pattern", 0);
-	edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
-						"samsung,h-sync-polarity", 0);
-	edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
-						"samsung,v-sync-polarity", 0);
-	edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
-						"samsung,interlaced", 0);
-	edp_info->video_info.color_space = fdtdec_get_int(blob, node,
-						"samsung,color-space", 0);
-	edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
-						"samsung,dynamic-range", 0);
-	edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
-						"samsung,ycbcr-coeff", 0);
-	edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
-						"samsung,color-depth", 0);
-	return 0;
-}
-
-unsigned int exynos_init_dp(void)
-{
-	unsigned int ret;
-	struct edp_device_info *edp_info;
-
-	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
-	if (!edp_info) {
-		debug("failed to allocate edp device object.\n");
-		return -EFAULT;
-	}
-
-	if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
-		debug("unable to parse DP DT node\n");
-
-	exynos_dp_set_base_addr();
-
-	exynos_dp_disp_info(&edp_info->disp_info);
-
-	exynos_set_dp_phy(1);
-
-	ret = exynos_dp_init_dp();
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP exynos_dp_init_dp() failed\n");
-		return ret;
-	}
-
-	ret = exynos_dp_handle_edid(edp_info);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("EDP handle_edid fail\n");
-		return ret;
-	}
-
-	ret = exynos_dp_set_link_train(edp_info);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP link training fail\n");
-		return ret;
-	}
-
-	exynos_dp_enable_scramble(DP_ENABLE);
-	exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
-	exynos_dp_enable_enhanced_mode(DP_ENABLE);
-
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
-
-	exynos_dp_init_video();
-	ret = exynos_dp_config_video(edp_info);
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("Exynos DP init failed\n");
-		return ret;
-	}
-
-	debug("Exynos DP init done\n");
-
-	return ret;
-}
diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos_dp_lowlevel.c
deleted file mode 100644
index acb5bc8..0000000
--- a/drivers/video/exynos_dp_lowlevel.c
+++ /dev/null
@@ -1,1257 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <linux/err.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/dp_info.h>
-#include <asm/arch/dp.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-
-/* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
-struct exynos_dp *dp_regs;
-
-void exynos_dp_set_base_addr(void)
-{
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0)
-		debug("exynos_dp: Can't get device node for dp\n");
-
-	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-	if (dp_regs == NULL)
-		debug("Can't get the DP base address\n");
-#else
-	dp_regs = (struct exynos_dp *)samsung_get_base_dp();
-#endif
-}
-
-static void exynos_dp_enable_video_input(unsigned int enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->video_ctl1);
-	reg &= ~VIDEO_EN_MASK;
-
-	/* enable video input */
-	if (enable)
-		reg |= VIDEO_EN_MASK;
-
-	writel(reg, &dp_regs->video_ctl1);
-
-	return;
-}
-
-void exynos_dp_enable_video_bist(unsigned int enable)
-{
-	/* enable video bist */
-	unsigned int reg;
-
-	reg = readl(&dp_regs->video_ctl4);
-	reg &= ~VIDEO_BIST_MASK;
-
-	/* enable video bist */
-	if (enable)
-		reg |= VIDEO_BIST_MASK;
-
-	writel(reg, &dp_regs->video_ctl4);
-
-	return;
-}
-
-void exynos_dp_enable_video_mute(unsigned int enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->video_ctl1);
-	reg &= ~(VIDEO_MUTE_MASK);
-	if (enable)
-		reg |= VIDEO_MUTE_MASK;
-
-	writel(reg, &dp_regs->video_ctl1);
-
-	return;
-}
-
-
-static void exynos_dp_init_analog_param(void)
-{
-	unsigned int reg;
-
-	/*
-	 * Set termination
-	 * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
-	 * 24M Phy clock, TX digital logic power is 100:1.0625V
-	 */
-	reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
-		SWING_A_30PER_G_NORMAL;
-	writel(reg, &dp_regs->analog_ctl1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, &dp_regs->analog_ctl2);
-
-	/*
-	 * Set power source for internal clk driver to 1.0625v.
-	 * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
-	 * Set VCO range of PLL +- 0uA
-	 */
-	reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
-	writel(reg, &dp_regs->analog_ctl3);
-
-	/*
-	 * Set AUX TX terminal resistor to 102 ohm
-	 * Set AUX channel amplitude control
-	 */
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
-	writel(reg, &dp_regs->pll_filter_ctl1);
-
-	/*
-	 * PLL loop filter bandwidth
-	 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
-	 * PLL digital power select: 1.2500V
-	 */
-	reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
-
-	writel(reg, &dp_regs->amp_tuning_ctl);
-
-	/*
-	 * PLL loop filter bandwidth
-	 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
-	 * PLL digital power select: 1.1250V
-	 */
-	reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
-	writel(reg, &dp_regs->pll_ctl);
-}
-
-static void exynos_dp_init_interrupt(void)
-{
-	/* Set interrupt registers to initial states */
-
-	/*
-	 * Disable interrupt
-	 * INT pin assertion polarity. It must be configured
-	 * correctly according to ICU setting.
-	 * 1 = assert high, 0 = assert low
-	 */
-	writel(INT_POL, &dp_regs->int_ctl);
-
-	/* Clear pending registers */
-	writel(0xff, &dp_regs->common_int_sta1);
-	writel(0xff, &dp_regs->common_int_sta2);
-	writel(0xff, &dp_regs->common_int_sta3);
-	writel(0xff, &dp_regs->common_int_sta4);
-	writel(0xff, &dp_regs->int_sta);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, &dp_regs->int_sta_mask1);
-	writel(0x00, &dp_regs->int_sta_mask2);
-	writel(0x00, &dp_regs->int_sta_mask3);
-	writel(0x00, &dp_regs->int_sta_mask4);
-	writel(0x00, &dp_regs->int_sta_mask);
-}
-
-void exynos_dp_reset(void)
-{
-	unsigned int reg_func_1;
-
-	/* dp tx sw reset */
-	writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
-
-	exynos_dp_enable_video_input(DP_DISABLE);
-	exynos_dp_enable_video_bist(DP_DISABLE);
-	exynos_dp_enable_video_mute(DP_DISABLE);
-
-	/* software reset */
-	reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-
-	writel(reg_func_1, &dp_regs->func_en1);
-	writel(reg_func_1, &dp_regs->func_en2);
-
-	mdelay(1);
-
-	exynos_dp_init_analog_param();
-	exynos_dp_init_interrupt();
-
-	return;
-}
-
-void exynos_dp_enable_sw_func(unsigned int enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->func_en1);
-	reg &= ~(SW_FUNC_EN_N);
-
-	if (!enable)
-		reg |= SW_FUNC_EN_N;
-
-	writel(reg, &dp_regs->func_en1);
-
-	return;
-}
-
-unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->phy_pd);
-	switch (block) {
-	case AUX_BLOCK:
-		reg &= ~(AUX_PD);
-		if (enable)
-			reg |= AUX_PD;
-		break;
-	case CH0_BLOCK:
-		reg &= ~(CH0_PD);
-		if (enable)
-			reg |= CH0_PD;
-		break;
-	case CH1_BLOCK:
-		reg &= ~(CH1_PD);
-		if (enable)
-			reg |= CH1_PD;
-		break;
-	case CH2_BLOCK:
-		reg &= ~(CH2_PD);
-		if (enable)
-			reg |= CH2_PD;
-		break;
-	case CH3_BLOCK:
-		reg &= ~(CH3_PD);
-		if (enable)
-			reg |= CH3_PD;
-		break;
-	case ANALOG_TOTAL:
-		reg &= ~PHY_PD;
-		if (enable)
-			reg |= PHY_PD;
-		break;
-	case POWER_ALL:
-		reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
-			CH3_PD);
-		if (enable)
-			reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
-				CH2_PD | CH3_PD);
-		break;
-	default:
-		printf("DP undefined block number : %d\n",  block);
-		return -1;
-	}
-
-	writel(reg, &dp_regs->phy_pd);
-
-	return 0;
-}
-
-unsigned int exynos_dp_get_pll_lock_status(void)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->debug_ctl);
-
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-static void exynos_dp_set_pll_power(unsigned int enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->pll_ctl);
-	reg &= ~(DP_PLL_PD);
-
-	if (!enable)
-		reg |= DP_PLL_PD;
-
-	writel(reg, &dp_regs->pll_ctl);
-}
-
-int exynos_dp_init_analog_func(void)
-{
-	int ret = EXYNOS_DP_SUCCESS;
-	unsigned int retry_cnt = 10;
-	unsigned int reg;
-
-	/* Power On All Analog block */
-	exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, &dp_regs->common_int_sta1);
-
-	reg = readl(&dp_regs->debug_ctl);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, &dp_regs->debug_ctl);
-
-	/* Assert DP PLL Reset */
-	reg = readl(&dp_regs->pll_ctl);
-	reg |= DP_PLL_RESET;
-	writel(reg, &dp_regs->pll_ctl);
-
-	mdelay(1);
-
-	/* Deassert DP PLL Reset */
-	reg = readl(&dp_regs->pll_ctl);
-	reg &= ~(DP_PLL_RESET);
-	writel(reg, &dp_regs->pll_ctl);
-
-	exynos_dp_set_pll_power(DP_ENABLE);
-
-	while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
-		mdelay(1);
-		retry_cnt--;
-		if (retry_cnt == 0) {
-			printf("DP dp's pll lock failed : retry : %d\n",
-					retry_cnt);
-			return -EINVAL;
-		}
-	}
-
-	debug("dp's pll lock success(%d)\n", retry_cnt);
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(&dp_regs->func_en2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, &dp_regs->func_en2);
-
-	return ret;
-}
-
-void exynos_dp_init_hpd(void)
-{
-	unsigned int reg;
-
-	/* Clear interrupts related to Hot Plug Detect */
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, &dp_regs->common_int_sta4);
-
-	reg = INT_HPD;
-	writel(reg, &dp_regs->int_sta);
-
-	reg = readl(&dp_regs->sys_ctl3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, &dp_regs->sys_ctl3);
-
-	return;
-}
-
-static inline void exynos_dp_reset_aux(void)
-{
-	unsigned int reg;
-
-	/* Disable AUX channel module */
-	reg = readl(&dp_regs->func_en2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, &dp_regs->func_en2);
-
-	return;
-}
-
-void exynos_dp_init_aux(void)
-{
-	unsigned int reg;
-
-	/* Clear interrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, &dp_regs->int_sta);
-
-	exynos_dp_reset_aux();
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, &dp_regs->aux_hw_retry_ctl);
-
-	/* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, &dp_regs->aux_ch_defer_ctl);
-
-	/* Enable AUX channel module */
-	reg = readl(&dp_regs->func_en2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, &dp_regs->func_en2);
-
-	return;
-}
-
-void exynos_dp_config_interrupt(void)
-{
-	unsigned int reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, &dp_regs->common_int_mask1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, &dp_regs->common_int_mask2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, &dp_regs->common_int_mask3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, &dp_regs->common_int_mask4);
-
-	reg = INT_STA_MASK;
-	writel(reg, &dp_regs->int_sta_mask);
-
-	return;
-}
-
-unsigned int exynos_dp_get_plug_in_status(void)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->sys_ctl3);
-	if (reg & HPD_STATUS)
-		return 0;
-
-	return -1;
-}
-
-unsigned int exynos_dp_detect_hpd(void)
-{
-	int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
-
-	mdelay(2);
-
-	while (exynos_dp_get_plug_in_status() != 0) {
-		if (timeout_loop == 0)
-			return -EINVAL;
-		mdelay(10);
-		timeout_loop--;
-	}
-
-	return EXYNOS_DP_SUCCESS;
-}
-
-unsigned int exynos_dp_start_aux_transaction(void)
-{
-	unsigned int reg;
-	unsigned int ret = 0;
-	unsigned int retry_cnt;
-
-	/* Enable AUX CH operation */
-	reg = readl(&dp_regs->aux_ch_ctl2);
-	reg |= AUX_EN;
-	writel(reg, &dp_regs->aux_ch_ctl2);
-
-	retry_cnt = 10;
-	while (retry_cnt) {
-		reg = readl(&dp_regs->int_sta);
-		if (!(reg & RPLY_RECEIV)) {
-			if (retry_cnt == 0) {
-				printf("DP Reply Timeout!!\n");
-				ret = -EAGAIN;
-				return ret;
-			}
-			mdelay(1);
-			retry_cnt--;
-		} else
-			break;
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(reg, &dp_regs->int_sta);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(&dp_regs->int_sta);
-	if (reg & AUX_ERR) {
-		printf("DP Aux Access Error\n");
-		writel(AUX_ERR, &dp_regs->int_sta);
-		ret = -EAGAIN;
-		return ret;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(&dp_regs->aux_ch_sta);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
-		ret = -EAGAIN;
-		return ret;
-	}
-
-	return EXYNOS_DP_SUCCESS;
-}
-
-unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
-				unsigned char data)
-{
-	unsigned int reg, ret;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, &dp_regs->buffer_data_ctl);
-
-	/* Select DPCD device address */
-	reg = AUX_ADDR_7_0(reg_addr);
-	writel(reg, &dp_regs->aux_addr_7_0);
-	reg = AUX_ADDR_15_8(reg_addr);
-	writel(reg, &dp_regs->aux_addr_15_8);
-	reg = AUX_ADDR_19_16(reg_addr);
-	writel(reg, &dp_regs->aux_addr_19_16);
-
-	/* Write data buffer */
-	reg = (unsigned int)data;
-	writel(reg, &dp_regs->buf_data0);
-
-	/*
-	 * Set DisplayPort transaction and write 1 byte
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-	writel(reg, &dp_regs->aux_ch_ctl1);
-
-	/* Start AUX transaction */
-	ret = exynos_dp_start_aux_transaction();
-	if (ret != EXYNOS_DP_SUCCESS) {
-		printf("DP Aux transaction failed\n");
-		return ret;
-	}
-
-	return ret;
-}
-
-unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
-		unsigned char *data)
-{
-	unsigned int reg;
-	int retval;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, &dp_regs->buffer_data_ctl);
-
-	/* Select DPCD device address */
-	reg = AUX_ADDR_7_0(reg_addr);
-	writel(reg, &dp_regs->aux_addr_7_0);
-	reg = AUX_ADDR_15_8(reg_addr);
-	writel(reg, &dp_regs->aux_addr_15_8);
-	reg = AUX_ADDR_19_16(reg_addr);
-	writel(reg, &dp_regs->aux_addr_19_16);
-
-	/*
-	 * Set DisplayPort transaction and read 1 byte
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-	writel(reg, &dp_regs->aux_ch_ctl1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction();
-	if (!retval)
-		debug("DP Aux Transaction fail!\n");
-
-	/* Read data buffer */
-	reg = readl(&dp_regs->buf_data0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	unsigned int reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	unsigned int retry_cnt;
-	unsigned int ret = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, &dp_regs->buffer_data_ctl);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		retry_cnt = 5;
-		while (retry_cnt) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, &dp_regs->aux_addr_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, &dp_regs->aux_addr_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, &dp_regs->aux_addr_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-					cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, (unsigned int)&dp_regs->buf_data0 +
-						(4 * cur_data_idx));
-			}
-			/*
-			* Set DisplayPort transaction and write
-			* If bit 3 is 1, DisplayPort transaction.
-			* If Bit 3 is 0, I2C transaction.
-			*/
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, &dp_regs->aux_ch_ctl1);
-
-			/* Start AUX transaction */
-			ret = exynos_dp_start_aux_transaction();
-			if (ret != EXYNOS_DP_SUCCESS) {
-				if (retry_cnt == 0) {
-					printf("DP Aux Transaction failed\n");
-					return ret;
-				}
-				retry_cnt--;
-			} else
-				break;
-		}
-		start_offset += cur_data_count;
-	}
-
-	return ret;
-}
-
-unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	unsigned int reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	unsigned int retry_cnt;
-	unsigned int ret = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, &dp_regs->buffer_data_ctl);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		retry_cnt = 5;
-		while (retry_cnt) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, &dp_regs->aux_addr_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, &dp_regs->aux_addr_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, &dp_regs->aux_addr_19_16);
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, &dp_regs->aux_ch_ctl1);
-
-			/* Start AUX transaction */
-			ret = exynos_dp_start_aux_transaction();
-			if (ret != EXYNOS_DP_SUCCESS) {
-				if (retry_cnt == 0) {
-					printf("DP Aux Transaction failed\n");
-					return ret;
-				}
-				retry_cnt--;
-			} else
-				break;
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-				cur_data_idx++) {
-			reg = readl((unsigned int)&dp_regs->buf_data0 +
-					4 * cur_data_idx);
-			data[start_offset + cur_data_idx] = (unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return ret;
-}
-
-int exynos_dp_select_i2c_device(unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	unsigned int reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, &dp_regs->aux_addr_7_0);
-	writel(0x0, &dp_regs->aux_addr_15_8);
-	writel(0x0, &dp_regs->aux_addr_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, &dp_regs->buf_data0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, &dp_regs->aux_ch_ctl1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction();
-	if (retval != 0)
-		printf("%s: DP Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
-{
-	unsigned int reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 10; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, &dp_regs->buffer_data_ctl);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
-		if (retval != 0) {
-			printf("DP Select EDID device fail. retry !\n");
-			continue;
-		}
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, &dp_regs->aux_ch_ctl1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction();
-		if (retval != EXYNOS_DP_SUCCESS)
-			printf("%s: DP Aux Transaction fail!\n", __func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(&dp_regs->buf_data0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int count, unsigned char edid[])
-{
-	unsigned int reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) { /* use 16 burst */
-		for (j = 0; j < 100; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, &dp_regs->buffer_data_ctl);
-
-			/* Set normal AUX CH command */
-			reg = readl(&dp_regs->aux_ch_ctl2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, &dp_regs->aux_ch_ctl2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending addres
-			 */
-			if (!defer)
-				retval =
-					exynos_dp_select_i2c_device(device_addr,
-							reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == EXYNOS_DP_SUCCESS) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
-				writel(reg, &dp_regs->aux_ch_ctl1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction();
-				if (retval == 0)
-					break;
-				else
-					printf("DP Aux Transaction fail!\n");
-			}
-			/* Check if Rx sends defer */
-			reg = readl(&dp_regs->aux_rx_comm);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
-				printf("DP Defer: %d\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl((unsigned int)&dp_regs->buf_data0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_reset_macro(void)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->phy_test);
-	reg |= MACRO_RST;
-	writel(reg, &dp_regs->phy_test);
-
-	/* 10 us is the minimum Macro reset time. */
-	mdelay(1);
-
-	reg &= ~MACRO_RST;
-	writel(reg, &dp_regs->phy_test);
-}
-
-void exynos_dp_set_link_bandwidth(unsigned char bwtype)
-{
-	unsigned int reg;
-
-	reg = (unsigned int)bwtype;
-
-	 /* Set bandwidth to 2.7G or 1.62G */
-	if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
-		writel(reg, &dp_regs->link_bw_set);
-}
-
-unsigned char exynos_dp_get_link_bandwidth(void)
-{
-	unsigned char ret;
-	unsigned int reg;
-
-	reg = readl(&dp_regs->link_bw_set);
-	ret = (unsigned char)reg;
-
-	return ret;
-}
-
-void exynos_dp_set_lane_count(unsigned char count)
-{
-	unsigned int reg;
-
-	reg = (unsigned int)count;
-
-	if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
-			(count == DP_LANE_CNT_4))
-		writel(reg, &dp_regs->lane_count_set);
-}
-
-unsigned int exynos_dp_get_lane_count(void)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->lane_count_set);
-
-	return reg;
-}
-
-unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
-{
-	unsigned int reg_list[DP_LANE_CNT_4] = {
-		(unsigned int)&dp_regs->ln0_link_training_ctl,
-		(unsigned int)&dp_regs->ln1_link_training_ctl,
-		(unsigned int)&dp_regs->ln2_link_training_ctl,
-		(unsigned int)&dp_regs->ln3_link_training_ctl,
-	};
-
-	return readl(reg_list[lanecnt]);
-}
-
-void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
-		unsigned char lanecnt)
-{
-	unsigned int reg_list[DP_LANE_CNT_4] = {
-		(unsigned int)&dp_regs->ln0_link_training_ctl,
-		(unsigned int)&dp_regs->ln1_link_training_ctl,
-		(unsigned int)&dp_regs->ln2_link_training_ctl,
-		(unsigned int)&dp_regs->ln3_link_training_ctl,
-	};
-
-	writel(request_val, reg_list[lanecnt]);
-}
-
-void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
-{
-	unsigned char i;
-	unsigned int reg;
-	unsigned int reg_list[DP_LANE_CNT_4] = {
-		(unsigned int)&dp_regs->ln0_link_training_ctl,
-		(unsigned int)&dp_regs->ln1_link_training_ctl,
-		(unsigned int)&dp_regs->ln2_link_training_ctl,
-		(unsigned int)&dp_regs->ln3_link_training_ctl,
-	};
-	unsigned int reg_shift[DP_LANE_CNT_4] = {
-		PRE_EMPHASIS_SET_0_SHIFT,
-		PRE_EMPHASIS_SET_1_SHIFT,
-		PRE_EMPHASIS_SET_2_SHIFT,
-		PRE_EMPHASIS_SET_3_SHIFT
-	};
-
-	for (i = 0; i < lanecnt; i++) {
-		reg = level << reg_shift[i];
-		writel(reg, reg_list[i]);
-	}
-}
-
-void exynos_dp_set_training_pattern(unsigned int pattern)
-{
-	unsigned int reg = 0;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		break;
-	default:
-		break;
-	}
-
-	writel(reg, &dp_regs->training_ptn_set);
-}
-
-void exynos_dp_enable_enhanced_mode(unsigned char enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->sys_ctl4);
-	reg &= ~ENHANCED;
-
-	if (enable)
-		reg |= ENHANCED;
-
-	writel(reg, &dp_regs->sys_ctl4);
-}
-
-void exynos_dp_enable_scrambling(unsigned int enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->training_ptn_set);
-	reg &= ~(SCRAMBLING_DISABLE);
-
-	if (!enable)
-		reg |= SCRAMBLING_DISABLE;
-
-	writel(reg, &dp_regs->training_ptn_set);
-}
-
-int exynos_dp_init_video(void)
-{
-	unsigned int reg;
-
-	/* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, &dp_regs->common_int_sta1);
-
-	/* I_STRM__CLK detect : DE_CTL : Auto detect */
-	reg &= ~DET_CTRL;
-	writel(reg, &dp_regs->sys_ctl1);
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
-{
-	unsigned int reg;
-
-	/* Video Slave mode setting */
-	reg = readl(&dp_regs->func_en1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, &dp_regs->func_en1);
-
-	/* Configure Interlaced for slave mode video */
-	reg = readl(&dp_regs->video_ctl10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
-	writel(reg, &dp_regs->video_ctl10);
-
-	/* Configure V sync polarity for slave mode video */
-	reg = readl(&dp_regs->video_ctl10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
-	writel(reg, &dp_regs->video_ctl10);
-
-	/* Configure H sync polarity for slave mode video */
-	reg = readl(&dp_regs->video_ctl10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
-	writel(reg, &dp_regs->video_ctl10);
-
-	/* Set video mode to slave mode */
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, &dp_regs->soc_general_ctl);
-}
-
-void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
-{
-	unsigned int reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(video_info->color_depth << IN_BPC_SHIFT) |
-		(video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, &dp_regs->video_ctl2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(&dp_regs->video_ctl3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, &dp_regs->video_ctl3);
-}
-
-int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
-{
-	unsigned int reg;
-	unsigned int bist_type = 0;
-	struct edp_video_info video_info = edp_info->video_info;
-
-	/* For master mode, you don't need to set the video format */
-	if (video_info.master_mode == 0) {
-		writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
-				&dp_regs->total_ln_cfg_l);
-		writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
-				&dp_regs->total_ln_cfg_h);
-		writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
-				&dp_regs->active_ln_cfg_l);
-		writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
-				&dp_regs->active_ln_cfg_h);
-		writel(edp_info->disp_info.v_sync_width,
-				&dp_regs->vsw_cfg);
-		writel(edp_info->disp_info.v_back_porch,
-				&dp_regs->vbp_cfg);
-		writel(edp_info->disp_info.v_front_porch,
-				&dp_regs->vfp_cfg);
-
-		writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
-				&dp_regs->total_pix_cfg_l);
-		writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
-				&dp_regs->total_pix_cfg_h);
-		writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
-				&dp_regs->active_pix_cfg_l);
-		writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
-				&dp_regs->active_pix_cfg_h);
-		writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
-				&dp_regs->hfp_cfg_l);
-		writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
-				&dp_regs->hfp_cfg_h);
-		writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
-				&dp_regs->hsw_cfg_l);
-		writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
-				&dp_regs->hsw_cfg_h);
-		writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
-				&dp_regs->hbp_cfg_l);
-		writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
-				&dp_regs->hbp_cfg_h);
-
-		/*
-		 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
-		 * HSYNC_P_CFG[0] properly
-		 */
-		reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
-			video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
-			video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
-		writel(reg, &dp_regs->video_ctl10);
-	}
-
-	/* BIST color bar width set--set to each bar is 32 pixel width */
-	switch (video_info.bist_pattern) {
-	case COLORBAR_32:
-		bist_type = BIST_WIDTH_BAR_32_PIXEL |
-			  BIST_TYPE_COLOR_BAR;
-		break;
-	case COLORBAR_64:
-		bist_type = BIST_WIDTH_BAR_64_PIXEL |
-			  BIST_TYPE_COLOR_BAR;
-		break;
-	case WHITE_GRAY_BALCKBAR_32:
-		bist_type = BIST_WIDTH_BAR_32_PIXEL |
-			  BIST_TYPE_WHITE_GRAY_BLACK_BAR;
-		break;
-	case WHITE_GRAY_BALCKBAR_64:
-		bist_type = BIST_WIDTH_BAR_64_PIXEL |
-			  BIST_TYPE_WHITE_GRAY_BLACK_BAR;
-		break;
-	case MOBILE_WHITEBAR_32:
-		bist_type = BIST_WIDTH_BAR_32_PIXEL |
-			  BIST_TYPE_MOBILE_WHITE_BAR;
-		break;
-	case MOBILE_WHITEBAR_64:
-		bist_type = BIST_WIDTH_BAR_64_PIXEL |
-			  BIST_TYPE_MOBILE_WHITE_BAR;
-		break;
-	default:
-		return -1;
-	}
-
-	reg = bist_type;
-	writel(reg, &dp_regs->video_ctl4);
-
-	return 0;
-}
-
-unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
-{
-	unsigned int reg;
-
-	/* Update Video stream clk detect status */
-	reg = readl(&dp_regs->sys_ctl1);
-	writel(reg, &dp_regs->sys_ctl1);
-
-	reg = readl(&dp_regs->sys_ctl1);
-
-	if (!(reg & DET_STA)) {
-		debug("DP Input stream clock not detected.\n");
-		return -EIO;
-	}
-
-	return EXYNOS_DP_SUCCESS;
-}
-
-void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
-		unsigned int n_value)
-{
-	unsigned int reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(&dp_regs->sys_ctl4);
-		reg |= FIX_M_VID;
-		writel(reg, &dp_regs->sys_ctl4);
-		reg = M_VID0_CFG(m_value);
-		writel(reg, &dp_regs->m_vid0);
-		reg = M_VID1_CFG(m_value);
-		writel(reg, &dp_regs->m_vid1);
-		reg = M_VID2_CFG(m_value);
-		writel(reg, &dp_regs->m_vid2);
-
-		reg = N_VID0_CFG(n_value);
-		writel(reg, &dp_regs->n_vid0);
-		reg = N_VID1_CFG(n_value);
-		writel(reg, &dp_regs->n_vid1);
-		reg = N_VID2_CFG(n_value);
-		writel(reg, &dp_regs->n_vid2);
-	} else  {
-		reg = readl(&dp_regs->sys_ctl4);
-		reg &= ~FIX_M_VID;
-		writel(reg, &dp_regs->sys_ctl4);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(unsigned int type)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->video_ctl10);
-	reg &= ~FORMAT_SEL;
-
-	if (type != VIDEO_TIMING_FROM_CAPTURE)
-		reg |= FORMAT_SEL;
-
-	writel(reg, &dp_regs->video_ctl10);
-}
-
-void exynos_dp_enable_video_master(unsigned int enable)
-{
-	unsigned int reg;
-
-	reg = readl(&dp_regs->soc_general_ctl);
-	if (enable) {
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-	} else {
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-	}
-
-	writel(reg, &dp_regs->soc_general_ctl);
-}
-
-void exynos_dp_start_video(void)
-{
-	unsigned int reg;
-
-	/* Enable Video input and disable Mute */
-	reg = readl(&dp_regs->video_ctl1);
-	reg |= VIDEO_EN;
-	writel(reg, &dp_regs->video_ctl1);
-}
-
-unsigned int exynos_dp_is_video_stream_on(void)
-{
-	unsigned int reg;
-
-	/* Update STRM_VALID */
-	reg = readl(&dp_regs->sys_ctl3);
-	writel(reg, &dp_regs->sys_ctl3);
-
-	reg = readl(&dp_regs->sys_ctl3);
-	if (!(reg & STRM_VALID))
-		return -EIO;
-
-	return EXYNOS_DP_SUCCESS;
-}
diff --git a/drivers/video/exynos_dp_lowlevel.h b/drivers/video/exynos_dp_lowlevel.h
deleted file mode 100644
index 8651681..0000000
--- a/drivers/video/exynos_dp_lowlevel.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EXYNOS_EDP_LOWLEVEL_H
-#define _EXYNOS_EDP_LOWLEVEL_H
-
-void exynos_dp_enable_video_bist(unsigned int enable);
-void exynos_dp_enable_video_mute(unsigned int enable);
-void exynos_dp_reset(void);
-void exynos_dp_enable_sw_func(unsigned int enable);
-unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
-unsigned int exynos_dp_get_pll_lock_status(void);
-int exynos_dp_init_analog_func(void);
-void exynos_dp_init_hpd(void);
-void exynos_dp_init_aux(void);
-void exynos_dp_config_interrupt(void);
-unsigned int exynos_dp_get_plug_in_status(void);
-unsigned int exynos_dp_detect_hpd(void);
-unsigned int exynos_dp_start_aux_transaction(void);
-unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
-				unsigned char data);
-unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
-		unsigned char *data);
-unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
-		unsigned int count,
-		unsigned char data[]);
-unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
-		unsigned int count,
-		unsigned char data[]);
-int exynos_dp_select_i2c_device( unsigned int device_addr,
-		unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int count,
-		unsigned char edid[]);
-void exynos_dp_reset_macro(void);
-void exynos_dp_set_link_bandwidth(unsigned char bwtype);
-unsigned char exynos_dp_get_link_bandwidth(void);
-void exynos_dp_set_lane_count(unsigned char count);
-unsigned int exynos_dp_get_lane_count(void);
-unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt);
-void exynos_dp_set_lane_pre_emphasis(unsigned int level,
-		unsigned char lanecnt);
-void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
-		unsigned char lanecnt);
-void exynos_dp_set_training_pattern(unsigned int pattern);
-void exynos_dp_enable_enhanced_mode(unsigned char enable);
-void exynos_dp_enable_scrambling(unsigned int enable);
-int exynos_dp_init_video(void);
-void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
-void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
-int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
-unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
-void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
-		unsigned int n_value);
-void exynos_dp_set_video_timing_mode(unsigned int type);
-void exynos_dp_enable_video_master(unsigned int enable);
-void exynos_dp_start_video(void);
-unsigned int exynos_dp_is_video_stream_on(void);
-void exynos_dp_set_base_addr(void);
-
-#endif /* _EXYNOS_DP_LOWLEVEL_H */
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
deleted file mode 100644
index 69edc3a..0000000
--- a/drivers/video/exynos_fb.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <lcd.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/mipi_dsim.h>
-#include <asm/arch/dp_info.h>
-#include <asm/arch/system.h>
-#include <asm/gpio.h>
-#include <asm-generic/errno.h>
-
-#include "exynos_fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned int panel_width, panel_height;
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-vidinfo_t panel_info  = {
-	/*
-	 * Insert a value here so that we don't end up in the BSS
-	 * Reference: drivers/video/tegra.c
-	 */
-	.vl_col = -1,
-};
-#endif
-
-ushort *configuration_get_cmap(void)
-{
-#if defined(CONFIG_LCD_LOGO)
-	return bmp_logo_palette;
-#else
-	return NULL;
-#endif
-}
-
-static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
-{
-	unsigned long palette_size;
-	unsigned int fb_size;
-
-	fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
-
-	palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-
-	exynos_fimd_lcd_init_mem((unsigned long)lcdbase,
-			(unsigned long)fb_size, palette_size);
-}
-
-static void exynos_lcd_init(vidinfo_t *vid)
-{
-	exynos_fimd_lcd_init(vid);
-
-	/* Enable flushing after LCD writes if requested */
-	lcd_set_flush_dcache(1);
-}
-
-__weak void exynos_cfg_lcd_gpio(void)
-{
-}
-
-__weak void exynos_backlight_on(unsigned int onoff)
-{
-}
-
-__weak void exynos_reset_lcd(void)
-{
-}
-
-__weak void exynos_lcd_power_on(void)
-{
-}
-
-__weak void exynos_cfg_ldo(void)
-{
-}
-
-__weak void exynos_enable_ldo(unsigned int onoff)
-{
-}
-
-__weak void exynos_backlight_reset(void)
-{
-}
-
-__weak int exynos_lcd_misc_init(vidinfo_t *vid)
-{
-	return 0;
-}
-
-static void lcd_panel_on(vidinfo_t *vid)
-{
-	struct gpio_desc pwm_out_gpio;
-	struct gpio_desc bl_en_gpio;
-	unsigned int node;
-
-	udelay(vid->init_delay);
-
-	exynos_backlight_reset();
-
-	exynos_cfg_lcd_gpio();
-
-	exynos_lcd_power_on();
-
-	udelay(vid->power_on_delay);
-
-	if (vid->dp_enabled)
-		exynos_init_dp();
-
-	exynos_reset_lcd();
-
-	udelay(vid->reset_delay);
-
-	exynos_backlight_on(1);
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	node = fdtdec_next_compatible(gd->fdt_blob, 0,
-						COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0) {
-		debug("FIMD: Can't get device node for FIMD\n");
-		return;
-	}
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
-				   0, &pwm_out_gpio,
-				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
-				   &bl_en_gpio,
-				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-#endif
-	exynos_cfg_ldo();
-
-	exynos_enable_ldo(1);
-
-	if (vid->mipi_enabled)
-		exynos_mipi_dsi_init();
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int exynos_lcd_early_init(const void *blob)
-{
-	unsigned int node;
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0) {
-		debug("exynos_fb: Can't get device node for fimd\n");
-		return -ENODEV;
-	}
-
-	panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
-	if (panel_info.vl_col == 0) {
-		debug("Can't get XRES\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
-	if (panel_info.vl_row == 0) {
-		debug("Can't get YRES\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_width = fdtdec_get_int(blob, node,
-						"samsung,vl-width", 0);
-
-	panel_info.vl_height = fdtdec_get_int(blob, node,
-						"samsung,vl-height", 0);
-
-	panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
-	if (panel_info.vl_freq == 0) {
-		debug("Can't get refresh rate\n");
-		return -ENXIO;
-	}
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
-		panel_info.vl_clkp = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
-		panel_info.vl_oep = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
-		panel_info.vl_hsp = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
-		panel_info.vl_vsp = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
-		panel_info.vl_dp = CONFIG_SYS_LOW;
-
-	panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
-	if (panel_info.vl_bpix == 0) {
-		debug("Can't get bits per pixel\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
-	if (panel_info.vl_hspw == 0) {
-		debug("Can't get hsync width\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
-	if (panel_info.vl_hfpd == 0) {
-		debug("Can't get right margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
-							"samsung,vl-hbpd", 0);
-	if (panel_info.vl_hbpd == 0) {
-		debug("Can't get left margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
-							"samsung,vl-vspw", 0);
-	if (panel_info.vl_vspw == 0) {
-		debug("Can't get vsync width\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_vfpd = fdtdec_get_int(blob, node,
-							"samsung,vl-vfpd", 0);
-	if (panel_info.vl_vfpd == 0) {
-		debug("Can't get lower margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
-	if (panel_info.vl_vbpd == 0) {
-		debug("Can't get upper margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
-						"samsung,vl-cmd-allow-len", 0);
-
-	panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
-	panel_info.init_delay = fdtdec_get_int(blob, node,
-						"samsung,init-delay", 0);
-	panel_info.power_on_delay = fdtdec_get_int(blob, node,
-						"samsung,power-on-delay", 0);
-	panel_info.reset_delay = fdtdec_get_int(blob, node,
-						"samsung,reset-delay", 0);
-	panel_info.interface_mode = fdtdec_get_int(blob, node,
-						"samsung,interface-mode", 0);
-	panel_info.mipi_enabled = fdtdec_get_int(blob, node,
-						"samsung,mipi-enabled", 0);
-	panel_info.dp_enabled = fdtdec_get_int(blob, node,
-						"samsung,dp-enabled", 0);
-	panel_info.cs_setup = fdtdec_get_int(blob, node,
-						"samsung,cs-setup", 0);
-	panel_info.wr_setup = fdtdec_get_int(blob, node,
-						"samsung,wr-setup", 0);
-	panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
-	panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
-
-	panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
-	if (panel_info.logo_on) {
-		panel_info.logo_width = fdtdec_get_int(blob, node,
-						"samsung,logo-width", 0);
-		panel_info.logo_height = fdtdec_get_int(blob, node,
-						"samsung,logo-height", 0);
-		panel_info.logo_addr = fdtdec_get_int(blob, node,
-						"samsung,logo-addr", 0);
-	}
-
-	panel_info.rgb_mode = fdtdec_get_int(blob, node,
-						"samsung,rgb-mode", 0);
-	panel_info.pclk_name = fdtdec_get_int(blob, node,
-						"samsung,pclk-name", 0);
-	panel_info.sclk_div = fdtdec_get_int(blob, node,
-						"samsung,sclk-div", 0);
-	panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
-						"samsung,dual-lcd-enabled", 0);
-
-	return 0;
-}
-#endif
-
-void lcd_ctrl_init(void *lcdbase)
-{
-	set_system_display_ctrl();
-	set_lcd_clk();
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-#ifdef CONFIG_EXYNOS_MIPI_DSIM
-	exynos_init_dsim_platform_data(&panel_info);
-#endif
-	exynos_lcd_misc_init(&panel_info);
-#else
-	/* initialize parameters which is specific to panel. */
-	init_panel_info(&panel_info);
-#endif
-
-	panel_width = panel_info.vl_width;
-	panel_height = panel_info.vl_height;
-
-	exynos_lcd_init_mem(lcdbase, &panel_info);
-
-	exynos_lcd_init(&panel_info);
-}
-
-void lcd_enable(void)
-{
-	if (panel_info.logo_on) {
-		memset((void *) gd->fb_base, 0, panel_width * panel_height *
-				(NBITS(panel_info.vl_bpix) >> 3));
-	}
-
-	lcd_panel_on(&panel_info);
-}
-
-/* dummy function */
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-	return;
-}
diff --git a/drivers/video/exynos_fb.h b/drivers/video/exynos_fb.h
deleted file mode 100644
index 2c2f94b..0000000
--- a/drivers/video/exynos_fb.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EXYNOS_FB_H_
-#define _EXYNOS_FB_H_
-
-#include <asm/arch/fb.h>
-
-#define MAX_CLOCK	(86 * 1000000)
-
-enum exynos_cpu_auto_cmd_rate {
-	DISABLE_AUTO_FRM,
-	PER_TWO_FRM,
-	PER_FOUR_FRM,
-	PER_SIX_FRM,
-	PER_EIGHT_FRM,
-	PER_TEN_FRM,
-	PER_TWELVE_FRM,
-	PER_FOURTEEN_FRM,
-	PER_SIXTEEN_FRM,
-	PER_EIGHTEEN_FRM,
-	PER_TWENTY_FRM,
-	PER_TWENTY_TWO_FRM,
-	PER_TWENTY_FOUR_FRM,
-	PER_TWENTY_SIX_FRM,
-	PER_TWENTY_EIGHT_FRM,
-	PER_THIRTY_FRM,
-};
-
-void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
-	unsigned long palette_size);
-void exynos_fimd_lcd_init(vidinfo_t *vid);
-unsigned long exynos_fimd_calc_fbsize(void);
-
-#endif
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
deleted file mode 100644
index ac001a8..0000000
--- a/drivers/video/exynos_fimd.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <lcd.h>
-#include <div64.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include "exynos_fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long *lcd_base_addr;
-static vidinfo_t *pvid;
-static struct exynos_fb *fimd_ctrl;
-
-void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
-		u_long palette_size)
-{
-	lcd_base_addr = (unsigned long *)screen_base;
-}
-
-static void exynos_fimd_set_dualrgb(unsigned int enabled)
-{
-	unsigned int cfg = 0;
-
-	if (enabled) {
-		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
-			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
-
-		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
-		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
-			EXYNOS_DUALRGB_MAIN_CNT(0);
-	}
-
-	writel(cfg, &fimd_ctrl->dualrgb);
-}
-
-static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
-{
-	unsigned int cfg = 0;
-
-	if (enabled)
-		cfg = EXYNOS_DP_CLK_ENABLE;
-
-	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
-}
-
-static void exynos_fimd_set_par(unsigned int win_id)
-{
-	unsigned int cfg = 0;
-
-	/* set window control */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
-		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
-		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
-		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
-
-	/* DATAPATH is DMA */
-	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
-
-	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
-
-	/* dma burst is 16 */
-	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
-
-	switch (pvid->vl_bpix) {
-	case 4:
-		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
-		break;
-	default:
-		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-		break;
-	}
-
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	/* set window position to x=0, y=0*/
-	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
-			EXYNOS_VIDOSD(win_id));
-
-	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
-		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
-		EXYNOS_VIDOSD_RIGHT_X_E(1) |
-		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
-
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
-			EXYNOS_VIDOSD(win_id));
-
-	/* set window size for window0*/
-	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
-			EXYNOS_VIDOSD(win_id));
-}
-
-static void exynos_fimd_set_buffer_address(unsigned int win_id)
-{
-	unsigned long start_addr, end_addr;
-
-	start_addr = (unsigned long)lcd_base_addr;
-	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
-				pvid->vl_row);
-
-	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
-			EXYNOS_BUFFER_OFFSET(win_id));
-	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
-			EXYNOS_BUFFER_OFFSET(win_id));
-}
-
-static void exynos_fimd_set_clock(vidinfo_t *pvid)
-{
-	unsigned int cfg = 0, div = 0, remainder, remainder_div;
-	unsigned long pixel_clock;
-	unsigned long long src_clock;
-
-	if (pvid->dual_lcd_enabled) {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col / 2) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
-		pixel_clock = pvid->vl_freq *
-				pvid->vl_width * pvid->vl_height *
-				(pvid->cs_setup + pvid->wr_setup +
-				 pvid->wr_act + pvid->wr_hold + 1);
-	} else {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	}
-
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
-		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
-		EXYNOS_VIDCON0_CLKDIR_MASK);
-	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
-		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
-
-	src_clock = (unsigned long long) get_lcd_clk();
-
-	/* get quotient and remainder. */
-	remainder = do_div(src_clock, pixel_clock);
-	div = src_clock;
-
-	remainder *= 10;
-	remainder_div = remainder / pixel_clock;
-
-	/* round about one places of decimals. */
-	if (remainder_div >= 5)
-		div++;
-
-	/* in case of dual lcd mode. */
-	if (pvid->dual_lcd_enabled)
-		div--;
-
-	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-void exynos_set_trigger(void)
-{
-	unsigned int cfg = 0;
-
-	cfg = readl(&fimd_ctrl->trigcon);
-
-	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
-
-	writel(cfg, &fimd_ctrl->trigcon);
-}
-
-int exynos_is_i80_frame_done(void)
-{
-	unsigned int cfg = 0;
-	int status;
-
-	cfg = readl(&fimd_ctrl->trigcon);
-
-	/* frame done func is valid only when TRIMODE[0] is set to 1. */
-	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
-			EXYNOS_I80STATUS_TRIG_DONE;
-
-	return status;
-}
-
-static void exynos_fimd_lcd_on(void)
-{
-	unsigned int cfg = 0;
-
-	/* display on */
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-static void exynos_fimd_window_on(unsigned int win_id)
-{
-	unsigned int cfg = 0;
-
-	/* enable window */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg = readl(&fimd_ctrl->winshmap);
-	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
-}
-
-void exynos_fimd_lcd_off(void)
-{
-	unsigned int cfg = 0;
-
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-void exynos_fimd_window_off(unsigned int win_id)
-{
-	unsigned int cfg = 0;
-
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg = readl(&fimd_ctrl->winshmap);
-	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-/*
-* The reset value for FIMD SYSMMU register MMU_CTRL is 3
-* on Exynos5420 and newer versions.
-* This means FIMD SYSMMU is on by default on Exynos5420
-* and newer versions.
-* Since in u-boot we don't use SYSMMU, we should disable
-* those FIMD SYSMMU.
-* Note that there are 2 SYSMMU for FIMD: m0 and m1.
-* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
-* We disable both of them here.
-*/
-void exynos_fimd_disable_sysmmu(void)
-{
-	u32 *sysmmufimd;
-	unsigned int node;
-	int node_list[2];
-	int count;
-	int i;
-
-	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
-				COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
-	for (i = 0; i < count; i++) {
-		node = node_list[i];
-		if (node <= 0) {
-			debug("Can't get device node for fimd sysmmu\n");
-			return;
-		}
-
-		sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
-		if (!sysmmufimd) {
-			debug("Can't get base address for sysmmu fimdm0");
-			return;
-		}
-
-		writel(0x0, sysmmufimd);
-	}
-}
-#endif
-
-void exynos_fimd_lcd_init(vidinfo_t *vid)
-{
-	unsigned int cfg = 0, rgb_mode;
-	unsigned int offset;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	unsigned int node;
-
-	node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0)
-		debug("exynos_fb: Can't get device node for fimd\n");
-
-	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-	if (fimd_ctrl == NULL)
-		debug("Can't get the FIMD base address\n");
-
-	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
-		exynos_fimd_disable_sysmmu();
-
-#else
-	fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
-#endif
-
-	offset = exynos_fimd_get_base_offset();
-
-	/* store panel info to global variable */
-	pvid = vid;
-
-	rgb_mode = vid->rgb_mode;
-
-	if (vid->interface_mode == FIMD_RGB_INTERFACE) {
-		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
-		writel(cfg, &fimd_ctrl->vidcon0);
-
-		cfg = readl(&fimd_ctrl->vidcon2);
-		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
-			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
-			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
-		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
-		writel(cfg, &fimd_ctrl->vidcon2);
-
-		/* set polarity */
-		cfg = 0;
-		if (!pvid->vl_clkp)
-			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
-		if (!pvid->vl_hsp)
-			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
-		if (!pvid->vl_vsp)
-			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
-		if (!pvid->vl_dp)
-			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
-
-		/* set timing */
-		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
-
-		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
-
-		/* set lcd size */
-		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
-			EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
-	}
-
-	/* set display mode */
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
-	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
-	writel(cfg, &fimd_ctrl->vidcon0);
-
-	/* set par */
-	exynos_fimd_set_par(pvid->win_id);
-
-	/* set memory address */
-	exynos_fimd_set_buffer_address(pvid->win_id);
-
-	/* set buffer size */
-	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_OFFSIZE(0) |
-		EXYNOS_VIDADDR_OFFSIZE_E(0);
-
-	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
-					EXYNOS_BUFFER_SIZE(pvid->win_id));
-
-	/* set clock */
-	exynos_fimd_set_clock(pvid);
-
-	/* set rgb mode to dual lcd. */
-	exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
-
-	/* display on */
-	exynos_fimd_lcd_on();
-
-	/* window on */
-	exynos_fimd_window_on(pvid->win_id);
-
-	exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
-}
-
-unsigned long exynos_fimd_calc_fbsize(void)
-{
-	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
-}
diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c
deleted file mode 100644
index b597acc..0000000
--- a/drivers/video/exynos_mipi_dsi.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <linux/compat.h>
-#include <linux/err.h>
-#include <asm/arch/dsim.h>
-#include <asm/arch/mipi_dsim.h>
-#include <asm/arch/power.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-
-#include "exynos_mipi_dsi_lowlevel.h"
-#include "exynos_mipi_dsi_common.h"
-
-#define master_to_driver(a)	(a->dsim_lcd_drv)
-#define master_to_device(a)	(a->dsim_lcd_dev)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct exynos_platform_mipi_dsim *dsim_pd;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static struct mipi_dsim_config dsim_config_dt;
-static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
-static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
-#endif
-
-struct mipi_dsim_ddi {
-	int				bus_id;
-	struct list_head		list;
-	struct mipi_dsim_lcd_device	*dsim_lcd_dev;
-	struct mipi_dsim_lcd_driver	*dsim_lcd_drv;
-};
-
-static LIST_HEAD(dsim_ddi_list);
-static LIST_HEAD(dsim_lcd_dev_list);
-
-int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
-{
-	struct mipi_dsim_ddi *dsim_ddi;
-
-	if (!lcd_dev) {
-		debug("mipi_dsim_lcd_device is NULL.\n");
-		return -EFAULT;
-	}
-
-	if (!lcd_dev->name) {
-		debug("dsim_lcd_device name is NULL.\n");
-		return -EFAULT;
-	}
-
-	dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL);
-	if (!dsim_ddi) {
-		debug("failed to allocate dsim_ddi object.\n");
-		return -EFAULT;
-	}
-
-	dsim_ddi->dsim_lcd_dev = lcd_dev;
-
-	list_add_tail(&dsim_ddi->list, &dsim_ddi_list);
-
-	return 0;
-}
-
-struct mipi_dsim_ddi
-	*exynos_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv)
-{
-	struct mipi_dsim_ddi *dsim_ddi;
-	struct mipi_dsim_lcd_device *lcd_dev;
-
-	list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
-		lcd_dev = dsim_ddi->dsim_lcd_dev;
-		if (!lcd_dev)
-			continue;
-
-		if (lcd_drv->id >= 0) {
-			if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0 &&
-					lcd_drv->id == lcd_dev->id) {
-				/**
-				 * bus_id would be used to identify
-				 * connected bus.
-				 */
-				dsim_ddi->bus_id = lcd_dev->bus_id;
-
-				return dsim_ddi;
-			}
-		} else {
-			if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) {
-				/**
-				 * bus_id would be used to identify
-				 * connected bus.
-				 */
-				dsim_ddi->bus_id = lcd_dev->bus_id;
-
-				return dsim_ddi;
-			}
-		}
-
-		kfree(dsim_ddi);
-		list_del(&dsim_ddi_list);
-	}
-
-	return NULL;
-}
-
-int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
-{
-	struct mipi_dsim_ddi *dsim_ddi;
-
-	if (!lcd_drv) {
-		debug("mipi_dsim_lcd_driver is NULL.\n");
-		return -EFAULT;
-	}
-
-	if (!lcd_drv->name) {
-		debug("dsim_lcd_driver name is NULL.\n");
-		return -EFAULT;
-	}
-
-	dsim_ddi = exynos_mipi_dsi_find_lcd_device(lcd_drv);
-	if (!dsim_ddi) {
-		debug("mipi_dsim_ddi object not found.\n");
-		return -EFAULT;
-	}
-
-	dsim_ddi->dsim_lcd_drv = lcd_drv;
-
-	debug("registered panel driver(%s) to mipi-dsi driver.\n",
-		lcd_drv->name);
-
-	return 0;
-
-}
-
-struct mipi_dsim_ddi
-	*exynos_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim,
-			const char *name)
-{
-	struct mipi_dsim_ddi *dsim_ddi;
-	struct mipi_dsim_lcd_driver *lcd_drv;
-	struct mipi_dsim_lcd_device *lcd_dev;
-
-	list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
-		lcd_drv = dsim_ddi->dsim_lcd_drv;
-		lcd_dev = dsim_ddi->dsim_lcd_dev;
-		if (!lcd_drv || !lcd_dev)
-			continue;
-
-		debug("lcd_drv->id = %d, lcd_dev->id = %d\n",
-					lcd_drv->id, lcd_dev->id);
-
-		if ((strcmp(lcd_drv->name, name) == 0)) {
-			lcd_dev->master = dsim;
-
-			dsim->dsim_lcd_dev = lcd_dev;
-			dsim->dsim_lcd_drv = lcd_drv;
-
-			return dsim_ddi;
-		}
-	}
-
-	return NULL;
-}
-
-/* define MIPI-DSI Master operations. */
-static struct mipi_dsim_master_ops master_ops = {
-	.cmd_write			= exynos_mipi_dsi_wr_data,
-	.get_dsim_frame_done		= exynos_mipi_dsi_get_frame_done_status,
-	.clear_dsim_frame_done		= exynos_mipi_dsi_clear_frame_done,
-};
-
-int exynos_mipi_dsi_init(void)
-{
-	struct mipi_dsim_device *dsim;
-	struct mipi_dsim_config *dsim_config;
-	struct mipi_dsim_ddi *dsim_ddi;
-
-	dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL);
-	if (!dsim) {
-		debug("failed to allocate dsim object.\n");
-		return -EFAULT;
-	}
-
-	/* get mipi_dsim_config. */
-	dsim_config = dsim_pd->dsim_config;
-	if (dsim_config == NULL) {
-		debug("failed to get dsim config data.\n");
-		return -EFAULT;
-	}
-
-	dsim->pd = dsim_pd;
-	dsim->dsim_config = dsim_config;
-	dsim->master_ops = &master_ops;
-
-	/* bind lcd ddi matched with panel name. */
-	dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name);
-	if (!dsim_ddi) {
-		debug("mipi_dsim_ddi object not found.\n");
-		return -ENOSYS;
-	}
-	if (dsim_pd->lcd_power)
-		dsim_pd->lcd_power();
-
-	if (dsim_pd->mipi_power)
-		dsim_pd->mipi_power();
-
-	/* phy_enable(unsigned int dev_index, unsigned int enable) */
-	if (dsim_pd->phy_enable)
-		dsim_pd->phy_enable(0, 1);
-
-	set_mipi_clk();
-
-	exynos_mipi_dsi_init_dsim(dsim);
-	exynos_mipi_dsi_init_link(dsim);
-	exynos_mipi_dsi_set_hs_enable(dsim);
-
-	/* set display timing. */
-	exynos_mipi_dsi_set_display_mode(dsim, dsim->dsim_config);
-
-	/* initialize mipi-dsi client(lcd panel). */
-	if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->mipi_panel_init) {
-		dsim_ddi->dsim_lcd_drv->mipi_panel_init(dsim);
-		dsim_ddi->dsim_lcd_drv->mipi_display_on(dsim);
-	}
-
-	debug("mipi-dsi driver(%s mode) has been probed.\n",
-		(dsim_config->e_interface == DSIM_COMMAND) ?
-			"CPU" : "RGB");
-
-	return 0;
-}
-
-void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
-{
-	if (pd == NULL) {
-		debug("pd is NULL\n");
-		return;
-	}
-
-	dsim_pd = pd;
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int exynos_dsim_config_parse_dt(const void *blob)
-{
-	int node;
-
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI);
-	if (node <= 0) {
-		printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n");
-		return -ENODEV;
-	}
-
-	dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-e-interface", 0);
-
-	dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-e-virtual-ch", 0);
-
-	dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-e-pixel-format", 0);
-
-	dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-e-burst-mode", 0);
-
-	dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-e-no-data-lane", 0);
-
-	dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-e-byte-clk", 0);
-
-	dsim_config_dt.hfp = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-hfp", 0);
-
-	dsim_config_dt.p = fdtdec_get_int(blob, node,
-					  "samsung,dsim-config-p", 0);
-	dsim_config_dt.m = fdtdec_get_int(blob, node,
-					  "samsung,dsim-config-m", 0);
-	dsim_config_dt.s = fdtdec_get_int(blob, node,
-					  "samsung,dsim-config-s", 0);
-
-	dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-pll-stable-time", 0);
-
-	dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-esc-clk", 0);
-
-	dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-stop-holding-cnt", 0);
-
-	dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-bta-timeout", 0);
-
-	dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
-				"samsung,dsim-config-rx-timeout", 0);
-
-	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
-				"samsung,dsim-device-name");
-
-	mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
-				"samsung,dsim-device-id", 0);
-
-	mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
-				"samsung,dsim-device-bus_id", 0);
-
-	mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
-				"samsung,dsim-device-reverse-panel", 0);
-
-	return 0;
-}
-
-void exynos_init_dsim_platform_data(vidinfo_t *vid)
-{
-	if (exynos_dsim_config_parse_dt(gd->fdt_blob))
-		debug("Can't get proper dsim config.\n");
-
-	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
-	dsim_platform_data_dt.dsim_config = &dsim_config_dt;
-	dsim_platform_data_dt.mipi_power = mipi_power;
-	dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl;
-	dsim_platform_data_dt.lcd_panel_info = (void *)vid;
-
-	mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
-	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
-
-	dsim_pd = &dsim_platform_data_dt;
-}
-#endif
diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos_mipi_dsi_common.c
deleted file mode 100644
index 925d515..0000000
--- a/drivers/video/exynos_mipi_dsi_common.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <lcd.h>
-#include <linux/err.h>
-#include <asm/arch/dsim.h>
-#include <asm/arch/mipi_dsim.h>
-
-#include "exynos_mipi_dsi_lowlevel.h"
-
-#define MHZ			(1000 * 1000)
-#define FIN_HZ			(24 * MHZ)
-
-#define DFIN_PLL_MIN_HZ		(6 * MHZ)
-#define DFIN_PLL_MAX_HZ		(12 * MHZ)
-
-#define DFVCO_MIN_HZ		(500 * MHZ)
-#define DFVCO_MAX_HZ		(1000 * MHZ)
-
-#define TRY_GET_FIFO_TIMEOUT	(5000 * 2)
-
-/* MIPI-DSIM status types. */
-enum {
-	DSIM_STATE_INIT,	/* should be initialized. */
-	DSIM_STATE_STOP,	/* CPU and LCDC are LP mode. */
-	DSIM_STATE_HSCLKEN,	/* HS clock was enabled. */
-	DSIM_STATE_ULPS
-};
-
-/* define DSI lane types. */
-enum {
-	DSIM_LANE_CLOCK = (1 << 0),
-	DSIM_LANE_DATA0 = (1 << 1),
-	DSIM_LANE_DATA1 = (1 << 2),
-	DSIM_LANE_DATA2 = (1 << 3),
-	DSIM_LANE_DATA3 = (1 << 4)
-};
-
-static unsigned int dpll_table[15] = {
-	100, 120, 170, 220, 270,
-	320, 390, 450, 510, 560,
-	640, 690, 770, 870, 950
-};
-
-static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
-		const unsigned char *data0, unsigned int data1)
-{
-	unsigned int data_cnt = 0, payload = 0;
-
-	/* in case that data count is more then 4 */
-	for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
-		/*
-		 * after sending 4bytes per one time,
-		 * send remainder data less then 4.
-		 */
-		if ((data1 - data_cnt) < 4) {
-			if ((data1 - data_cnt) == 3) {
-				payload = data0[data_cnt] |
-					data0[data_cnt + 1] << 8 |
-					data0[data_cnt + 2] << 16;
-			debug("count = 3 payload = %x, %x %x %x\n",
-				payload, data0[data_cnt],
-				data0[data_cnt + 1],
-				data0[data_cnt + 2]);
-			} else if ((data1 - data_cnt) == 2) {
-				payload = data0[data_cnt] |
-					data0[data_cnt + 1] << 8;
-			debug("count = 2 payload = %x, %x %x\n", payload,
-				data0[data_cnt], data0[data_cnt + 1]);
-			} else if ((data1 - data_cnt) == 1) {
-				payload = data0[data_cnt];
-			}
-		} else {
-			/* send 4bytes per one time. */
-			payload = data0[data_cnt] |
-				data0[data_cnt + 1] << 8 |
-				data0[data_cnt + 2] << 16 |
-				data0[data_cnt + 3] << 24;
-
-			debug("count = 4 payload = %x, %x %x %x %x\n",
-				payload, *(u8 *)(data0 + data_cnt),
-				data0[data_cnt + 1],
-				data0[data_cnt + 2],
-				data0[data_cnt + 3]);
-		}
-		exynos_mipi_dsi_wr_tx_data(dsim, payload);
-	}
-}
-
-int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
-	const unsigned char *data0, unsigned int data1)
-{
-	unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
-	unsigned long delay_val, delay;
-	unsigned int check_rx_ack = 0;
-
-	if (dsim->state == DSIM_STATE_ULPS) {
-		debug("state is ULPS.\n");
-
-		return -EINVAL;
-	}
-
-	delay_val = MHZ / dsim->dsim_config->esc_clk;
-	delay = 10 * delay_val;
-
-	mdelay(delay);
-
-	/* only if transfer mode is LPDT, wait SFR becomes empty. */
-	if (dsim->state == DSIM_STATE_STOP) {
-		while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
-				SFR_HEADER_EMPTY)) {
-			if ((timeout--) > 0)
-				mdelay(1);
-			else {
-				debug("SRF header fifo is not empty.\n");
-				return -EINVAL;
-			}
-		}
-	}
-
-	switch (data_id) {
-	/* short packet types of packet types for command. */
-	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
-	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
-	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
-	case MIPI_DSI_DCS_SHORT_WRITE:
-	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
-	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
-		debug("data0 = %x data1 = %x\n",
-				data0[0], data0[1]);
-		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
-		if (check_rx_ack) {
-			/* process response func should be implemented */
-			return 0;
-		} else {
-			return -EINVAL;
-		}
-
-	/* general command */
-	case MIPI_DSI_COLOR_MODE_OFF:
-	case MIPI_DSI_COLOR_MODE_ON:
-	case MIPI_DSI_SHUTDOWN_PERIPHERAL:
-	case MIPI_DSI_TURN_ON_PERIPHERAL:
-		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
-		if (check_rx_ack) {
-			/* process response func should be implemented. */
-			return 0;
-		} else {
-			return -EINVAL;
-		}
-
-	/* packet types for video data */
-	case MIPI_DSI_V_SYNC_START:
-	case MIPI_DSI_V_SYNC_END:
-	case MIPI_DSI_H_SYNC_START:
-	case MIPI_DSI_H_SYNC_END:
-	case MIPI_DSI_END_OF_TRANSMISSION:
-		return 0;
-
-	/* short and response packet types for command */
-	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
-	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
-	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
-	case MIPI_DSI_DCS_READ:
-		exynos_mipi_dsi_clear_all_interrupt(dsim);
-		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
-		/* process response func should be implemented. */
-		return 0;
-
-	/* long packet type and null packet */
-	case MIPI_DSI_NULL_PACKET:
-	case MIPI_DSI_BLANKING_PACKET:
-		return 0;
-	case MIPI_DSI_GENERIC_LONG_WRITE:
-	case MIPI_DSI_DCS_LONG_WRITE:
-	{
-		unsigned int payload = 0;
-
-		/* if data count is less then 4, then send 3bytes data.  */
-		if (data1 < 4) {
-			payload = data0[0] |
-				data0[1] << 8 |
-				data0[2] << 16;
-
-			exynos_mipi_dsi_wr_tx_data(dsim, payload);
-
-			debug("count = %d payload = %x,%x %x %x\n",
-				data1, payload, data0[0],
-				data0[1], data0[2]);
-		} else {
-			/* in case that data count is more then 4 */
-			exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
-		}
-
-		/* put data into header fifo */
-		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
-			(data1 & 0xff00) >> 8);
-
-	}
-	if (check_rx_ack)
-		/* process response func should be implemented. */
-		return 0;
-	else
-		return -EINVAL;
-
-	/* packet typo for video data */
-	case MIPI_DSI_PACKED_PIXEL_STREAM_16:
-	case MIPI_DSI_PACKED_PIXEL_STREAM_18:
-	case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
-	case MIPI_DSI_PACKED_PIXEL_STREAM_24:
-		if (check_rx_ack) {
-			/* process response func should be implemented. */
-			return 0;
-		} else {
-			return -EINVAL;
-		}
-	default:
-		debug("data id %x is not supported current DSI spec.\n",
-			data_id);
-
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
-{
-	int sw_timeout;
-
-	if (enable) {
-		sw_timeout = 1000;
-
-		exynos_mipi_dsi_clear_interrupt(dsim);
-		exynos_mipi_dsi_enable_pll(dsim, 1);
-		while (1) {
-			sw_timeout--;
-			if (exynos_mipi_dsi_is_pll_stable(dsim))
-				return 0;
-			if (sw_timeout == 0)
-				return -EINVAL;
-		}
-	} else
-		exynos_mipi_dsi_enable_pll(dsim, 0);
-
-	return 0;
-}
-
-unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
-	unsigned int pre_divider, unsigned int main_divider,
-	unsigned int scaler)
-{
-	unsigned long dfin_pll, dfvco, dpll_out;
-	unsigned int i, freq_band = 0xf;
-
-	dfin_pll = (FIN_HZ / pre_divider);
-
-	/******************************************************
-	 *	Serial Clock(=ByteClk X 8)	FreqBand[3:0] *
-	 ******************************************************
-	 *	~ 99.99 MHz			0000
-	 *	100 ~ 119.99 MHz		0001
-	 *	120 ~ 159.99 MHz		0010
-	 *	160 ~ 199.99 MHz		0011
-	 *	200 ~ 239.99 MHz		0100
-	 *	140 ~ 319.99 MHz		0101
-	 *	320 ~ 389.99 MHz		0110
-	 *	390 ~ 449.99 MHz		0111
-	 *	450 ~ 509.99 MHz		1000
-	 *	510 ~ 559.99 MHz		1001
-	 *	560 ~ 639.99 MHz		1010
-	 *	640 ~ 689.99 MHz		1011
-	 *	690 ~ 769.99 MHz		1100
-	 *	770 ~ 869.99 MHz		1101
-	 *	870 ~ 949.99 MHz		1110
-	 *	950 ~ 1000 MHz			1111
-	 ******************************************************/
-	if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
-		debug("fin_pll range should be 6MHz ~ 12MHz\n");
-		exynos_mipi_dsi_enable_afc(dsim, 0, 0);
-	} else {
-		if (dfin_pll < 7 * MHZ)
-			exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
-		else if (dfin_pll < 8 * MHZ)
-			exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
-		else if (dfin_pll < 9 * MHZ)
-			exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
-		else if (dfin_pll < 10 * MHZ)
-			exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
-		else if (dfin_pll < 11 * MHZ)
-			exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
-		else
-			exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
-	}
-
-	dfvco = dfin_pll * main_divider;
-	debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
-				dfvco, dfin_pll, main_divider);
-	if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
-		debug("fvco range should be 500MHz ~ 1000MHz\n");
-
-	dpll_out = dfvco / (1 << scaler);
-	debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
-		dpll_out, dfvco, scaler);
-
-	for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
-		if (dpll_out < dpll_table[i] * MHZ) {
-			freq_band = i;
-			break;
-		}
-	}
-
-	debug("freq_band = %d\n", freq_band);
-
-	exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
-
-	exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
-	exynos_mipi_dsi_prep_ctrl(dsim, 0);
-
-	/* Freq Band */
-	exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
-
-	/* Stable time */
-	exynos_mipi_dsi_pll_stable_time(dsim,
-				dsim->dsim_config->pll_stable_time);
-
-	/* Enable PLL */
-	debug("FOUT of mipi dphy pll is %luMHz\n",
-		(dpll_out / MHZ));
-
-	return dpll_out;
-}
-
-int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
-	unsigned int byte_clk_sel, unsigned int enable)
-{
-	unsigned int esc_div;
-	unsigned long esc_clk_error_rate;
-	unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
-
-	if (enable) {
-		dsim->e_clk_src = byte_clk_sel;
-
-		/* Escape mode clock and byte clock source */
-		exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
-
-		/* DPHY, DSIM Link : D-PHY clock out */
-		if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
-			hs_clk = exynos_mipi_dsi_change_pll(dsim,
-				dsim->dsim_config->p, dsim->dsim_config->m,
-				dsim->dsim_config->s);
-			if (hs_clk == 0) {
-				debug("failed to get hs clock.\n");
-				return -EINVAL;
-			}
-
-			byte_clk = hs_clk / 8;
-			exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
-			exynos_mipi_dsi_pll_on(dsim, 1);
-		/* DPHY : D-PHY clock out, DSIM link : external clock out */
-		} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
-			debug("not support EXT CLK source for MIPI DSIM\n");
-		else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
-			debug("not support EXT CLK source for MIPI DSIM\n");
-
-		/* escape clock divider */
-		esc_div = byte_clk / (dsim->dsim_config->esc_clk);
-		debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
-			esc_div, byte_clk, dsim->dsim_config->esc_clk);
-		if ((byte_clk / esc_div) >= (20 * MHZ) ||
-			(byte_clk / esc_div) > dsim->dsim_config->esc_clk)
-			esc_div += 1;
-
-		escape_clk = byte_clk / esc_div;
-		debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
-			escape_clk, byte_clk, esc_div);
-
-		/* enable escape clock. */
-		exynos_mipi_dsi_enable_byte_clock(dsim, 1);
-
-		/* enable byte clk and escape clock */
-		exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
-		/* escape clock on lane */
-		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
-			(DSIM_LANE_CLOCK | dsim->data_lane), 1);
-
-		debug("byte clock is %luMHz\n",
-			(byte_clk / MHZ));
-		debug("escape clock that user's need is %lu\n",
-			(dsim->dsim_config->esc_clk / MHZ));
-		debug("escape clock divider is %x\n", esc_div);
-		debug("escape clock is %luMHz\n",
-			((byte_clk / esc_div) / MHZ));
-
-		if ((byte_clk / esc_div) > escape_clk) {
-			esc_clk_error_rate = escape_clk /
-				(byte_clk / esc_div);
-			debug("error rate is %lu over.\n",
-				(esc_clk_error_rate / 100));
-		} else if ((byte_clk / esc_div) < (escape_clk)) {
-			esc_clk_error_rate = (byte_clk / esc_div) /
-				escape_clk;
-			debug("error rate is %lu under.\n",
-				(esc_clk_error_rate / 100));
-		}
-	} else {
-		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
-			(DSIM_LANE_CLOCK | dsim->data_lane), 0);
-		exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
-
-		/* disable escape clock. */
-		exynos_mipi_dsi_enable_byte_clock(dsim, 0);
-
-		if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
-			exynos_mipi_dsi_pll_on(dsim, 0);
-	}
-
-	return 0;
-}
-
-int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
-{
-	dsim->state = DSIM_STATE_INIT;
-
-	switch (dsim->dsim_config->e_no_data_lane) {
-	case DSIM_DATA_LANE_1:
-		dsim->data_lane = DSIM_LANE_DATA0;
-		break;
-	case DSIM_DATA_LANE_2:
-		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
-		break;
-	case DSIM_DATA_LANE_3:
-		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
-			DSIM_LANE_DATA2;
-		break;
-	case DSIM_DATA_LANE_4:
-		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
-			DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
-		break;
-	default:
-		debug("data lane is invalid.\n");
-		return -EINVAL;
-	};
-
-	exynos_mipi_dsi_sw_reset(dsim);
-	exynos_mipi_dsi_dp_dn_swap(dsim, 0);
-
-	return 0;
-}
-
-int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
-	unsigned int enable)
-{
-	/* enable only frame done interrupt */
-	exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
-
-	return 0;
-}
-
-static void convert_to_fb_videomode(struct fb_videomode *mode1,
-				vidinfo_t *mode2)
-{
-	mode1->xres = mode2->vl_width;
-	mode1->yres = mode2->vl_height;
-	mode1->upper_margin = mode2->vl_vfpd;
-	mode1->lower_margin = mode2->vl_vbpd;
-	mode1->left_margin = mode2->vl_hfpd;
-	mode1->right_margin = mode2->vl_hbpd;
-	mode1->vsync_len = mode2->vl_vspw;
-	mode1->hsync_len = mode2->vl_hspw;
-}
-
-int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
-	struct mipi_dsim_config *dsim_config)
-{
-	struct exynos_platform_mipi_dsim *dsim_pd;
-	struct fb_videomode lcd_video;
-	vidinfo_t *vid;
-
-	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
-	vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
-
-	convert_to_fb_videomode(&lcd_video, vid);
-
-	/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
-	if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
-		if (dsim->dsim_config->auto_vertical_cnt == 0) {
-			exynos_mipi_dsi_set_main_disp_vporch(dsim,
-				vid->vl_cmd_allow_len,
-				lcd_video.upper_margin,
-				lcd_video.lower_margin);
-			exynos_mipi_dsi_set_main_disp_hporch(dsim,
-				lcd_video.left_margin,
-				lcd_video.right_margin);
-			exynos_mipi_dsi_set_main_disp_sync_area(dsim,
-				lcd_video.vsync_len,
-				lcd_video.hsync_len);
-		}
-	}
-
-	exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
-			lcd_video.yres);
-
-	exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
-
-	debug("lcd panel ==> width = %d, height = %d\n",
-			lcd_video.xres, lcd_video.yres);
-
-	return 0;
-}
-
-int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
-{
-	unsigned int time_out = 100;
-
-	switch (dsim->state) {
-	case DSIM_STATE_INIT:
-		exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
-
-		/* dsi configuration */
-		exynos_mipi_dsi_init_config(dsim);
-		exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
-		exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
-
-		/* set clock configuration */
-		exynos_mipi_dsi_set_clock(dsim,
-					dsim->dsim_config->e_byte_clk, 1);
-
-		/* check clock and data lane state are stop state */
-		while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
-			time_out--;
-			if (time_out == 0) {
-				debug("DSI Master is not stop state.\n");
-				debug("Check initialization process\n");
-
-				return -EINVAL;
-			}
-		}
-
-		dsim->state = DSIM_STATE_STOP;
-
-		/* BTA sequence counters */
-		exynos_mipi_dsi_set_stop_state_counter(dsim,
-			dsim->dsim_config->stop_holding_cnt);
-		exynos_mipi_dsi_set_bta_timeout(dsim,
-			dsim->dsim_config->bta_timeout);
-		exynos_mipi_dsi_set_lpdr_timeout(dsim,
-			dsim->dsim_config->rx_timeout);
-
-		return 0;
-	default:
-		debug("DSI Master is already init.\n");
-		return 0;
-	}
-
-	return 0;
-}
-
-int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
-{
-	if (dsim->state == DSIM_STATE_STOP) {
-		if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
-			dsim->state = DSIM_STATE_HSCLKEN;
-
-			 /* set LCDC and CPU transfer mode to HS. */
-			exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
-			exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
-
-			exynos_mipi_dsi_enable_hs_clock(dsim, 1);
-
-			return 0;
-		} else
-			debug("clock source is external bypass.\n");
-	} else
-		debug("DSIM is not stop state.\n");
-
-	return 0;
-}
-
-int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
-		unsigned int mode)
-{
-	if (mode) {
-		if (dsim->state != DSIM_STATE_HSCLKEN) {
-			debug("HS Clock lane is not enabled.\n");
-			return -EINVAL;
-		}
-
-		exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
-	} else {
-		if (dsim->state == DSIM_STATE_INIT || dsim->state ==
-			DSIM_STATE_ULPS) {
-			debug("DSI Master is not STOP or HSDT state.\n");
-			return -EINVAL;
-		}
-
-		exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
-	}
-
-	return 0;
-}
-
-int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
-{
-	return _exynos_mipi_dsi_get_frame_done_status(dsim);
-}
-
-int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
-{
-	_exynos_mipi_dsi_clear_frame_done(dsim);
-
-	return 0;
-}
diff --git a/drivers/video/exynos_mipi_dsi_common.h b/drivers/video/exynos_mipi_dsi_common.h
deleted file mode 100644
index 98eb78e..0000000
--- a/drivers/video/exynos_mipi_dsi_common.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/fb.h>
-
-#ifndef _EXYNOS_MIPI_DSI_COMMON_H
-#define _EXYNOS_MIPI_DSI_COMMON_H
-
-int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
-	const unsigned char *data0, unsigned int data1);
-int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable);
-unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
-	unsigned int pre_divider, unsigned int main_divider,
-	unsigned int scaler);
-int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
-	unsigned int byte_clk_sel, unsigned int enable);
-int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim);
-int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
-			struct mipi_dsim_config *dsim_info);
-int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim);
-int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim);
-int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
-		unsigned int mode);
-int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
-	unsigned int enable);
-int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
-int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
-
-#endif /* _EXYNOS_MIPI_DSI_COMMON_H */
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos_mipi_dsi_lowlevel.c
deleted file mode 100644
index fcfdc8d..0000000
--- a/drivers/video/exynos_mipi_dsi_lowlevel.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/dsim.h>
-#include <asm/arch/mipi_dsim.h>
-#include <asm/arch/power.h>
-#include <asm/arch/cpu.h>
-
-#include "exynos_mipi_dsi_lowlevel.h"
-#include "exynos_mipi_dsi_common.h"
-
-void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
-{
-	unsigned int reg;
-
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = readl(&mipi_dsim->swrst);
-
-	reg |= DSIM_FUNCRST;
-
-	writel(reg, &mipi_dsim->swrst);
-}
-
-void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
-{
-	unsigned int reg = 0;
-
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = readl(&mipi_dsim->swrst);
-
-	reg |= DSIM_SWRST;
-	reg |= DSIM_FUNCRST;
-
-	writel(reg, &mipi_dsim->swrst);
-}
-
-void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->intsrc);
-
-	reg |= INTSRC_SWRST_RELEASE;
-
-	writel(reg, &mipi_dsim->intsrc);
-}
-
-void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
-		unsigned int mode, unsigned int mask)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->intmsk);
-
-	if (mask)
-		reg |= mode;
-	else
-		reg &= ~mode;
-
-	writel(reg, &mipi_dsim->intmsk);
-}
-
-void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
-		unsigned int cfg)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = readl(&mipi_dsim->fifoctrl);
-
-	writel(reg & ~(cfg), &mipi_dsim->fifoctrl);
-	udelay(10 * 1000);
-	reg |= cfg;
-
-	writel(reg, &mipi_dsim->fifoctrl);
-}
-
-/*
- * this function set PLL P, M and S value in D-PHY
- */
-void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
-		unsigned int value)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr);
-}
-
-void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
-	unsigned int width_resol, unsigned int height_resol)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	/* standby should be set after configuration so set to not ready*/
-	reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY);
-	writel(reg, &mipi_dsim->mdresol);
-
-	/* reset resolution */
-	reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff));
-	reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
-
-	reg |= DSIM_MAIN_STAND_BY;
-	writel(reg, &mipi_dsim->mdresol);
-}
-
-void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
-	unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = (readl(&mipi_dsim->mvporch)) &
-		~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
-		(DSIM_MAIN_VBP_MASK));
-
-	reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |
-		((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |
-		((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);
-
-	writel(reg, &mipi_dsim->mvporch);
-}
-
-void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
-	unsigned int front, unsigned int back)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = (readl(&mipi_dsim->mhporch)) &
-		~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
-
-	reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);
-
-	writel(reg, &mipi_dsim->mhporch);
-}
-
-void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
-	unsigned int vert, unsigned int hori)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = (readl(&mipi_dsim->msync)) &
-		~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
-
-	reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |
-		(hori << DSIM_MAIN_HSA_SHIFT);
-
-	writel(reg, &mipi_dsim->msync);
-}
-
-void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
-	unsigned int vert, unsigned int hori)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = (readl(&mipi_dsim->sdresol)) &
-		~(DSIM_SUB_STANDY_MASK);
-
-	writel(reg, &mipi_dsim->sdresol);
-
-	reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
-	reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |
-		((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);
-	writel(reg, &mipi_dsim->sdresol);
-
-	/* DSIM STANDBY */
-	reg |= (1 << DSIM_SUB_STANDY_SHIFT);
-	writel(reg, &mipi_dsim->sdresol);
-}
-
-void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
-{
-	struct mipi_dsim_config *dsim_config = dsim->dsim_config;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int cfg = (readl(&mipi_dsim->config)) &
-		~((1 << DSIM_EOT_PACKET_SHIFT) |
-		(0x1f << DSIM_HSA_MODE_SHIFT) |
-		(0x3 << DSIM_NUM_OF_DATALANE_SHIFT));
-
-	cfg |=	(dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) |
-		(dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) |
-		(dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |
-		(dsim_config->hse << DSIM_HSE_MODE_SHIFT) |
-		(dsim_config->hfp << DSIM_HFP_MODE_SHIFT) |
-		(dsim_config->hbp << DSIM_HBP_MODE_SHIFT) |
-		(dsim_config->hsa << DSIM_HSA_MODE_SHIFT) |
-		(dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);
-
-	writel(cfg, &mipi_dsim->config);
-}
-
-void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
-				struct mipi_dsim_config *dsim_config)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	u32 reg = (readl(&mipi_dsim->config)) &
-		~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT)
-		| (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT)
-		| (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT));
-
-	if (dsim_config->e_interface == DSIM_VIDEO)
-		reg |= (1 << DSIM_VIDEO_MODE_SHIFT);
-	else if (dsim_config->e_interface == DSIM_COMMAND)
-		reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT);
-	else {
-		printf("unknown lcd type.\n");
-		return;
-	}
-
-	/* main lcd */
-	reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT
-	| ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT
-	| ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT;
-
-	writel(reg, &mipi_dsim->config);
-}
-
-void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
-			unsigned int lane, unsigned int enable)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = readl(&mipi_dsim->config);
-
-	if (enable)
-		reg |= DSIM_LANE_ENx(lane);
-	else
-		reg &= ~DSIM_LANE_ENx(lane);
-
-	writel(reg, &mipi_dsim->config);
-}
-
-void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
-	unsigned int count)
-{
-	unsigned int cfg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	/* get the data lane number. */
-	cfg = DSIM_NUM_OF_DATA_LANE(count);
-
-	writel(cfg, &mipi_dsim->config);
-}
-
-void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
-			unsigned int enable, unsigned int afc_code)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->phyacchr);
-
-	reg = 0;
-
-	if (enable) {
-		reg |= DSIM_AFC_EN;
-		reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT);
-		reg |= DSIM_AFC_CTL(afc_code);
-	} else
-		reg &= ~DSIM_AFC_EN;
-
-	writel(reg, &mipi_dsim->phyacchr);
-}
-
-void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
-	unsigned int enable)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
-		~(DSIM_PLL_BYPASS_EXTERNAL);
-
-	reg |= enable << DSIM_PLL_BYPASS_SHIFT;
-
-	writel(reg, &mipi_dsim->clkctrl);
-}
-
-void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
-		unsigned int freq_band)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
-		~(0x1f << DSIM_FREQ_BAND_SHIFT);
-
-	reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);
-
-	writel(reg, &mipi_dsim->pllctrl);
-}
-
-void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
-		unsigned int pre_divider, unsigned int main_divider,
-		unsigned int scaler)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
-		~(0x7ffff << 1);
-
-	reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) |
-		((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) |
-		((scaler & 0x7) << DSIM_SCALER_SHIFT);
-
-	writel(reg, &mipi_dsim->pllctrl);
-}
-
-void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
-	unsigned int lock_time)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	writel(lock_time, &mipi_dsim->plltmr);
-}
-
-void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
-				unsigned int enable)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
-		~(0x1 << DSIM_PLL_EN_SHIFT);
-
-	reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
-
-	writel(reg, &mipi_dsim->pllctrl);
-}
-
-void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
-		unsigned int src)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
-		~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);
-
-	reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;
-
-	writel(reg, &mipi_dsim->clkctrl);
-}
-
-void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
-		unsigned int enable)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
-		~(1 << DSIM_BYTE_CLKEN_SHIFT);
-
-	reg |= enable << DSIM_BYTE_CLKEN_SHIFT;
-
-	writel(reg, &mipi_dsim->clkctrl);
-}
-
-void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
-		unsigned int enable, unsigned int prs_val)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
-		~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff));
-
-	reg |= enable << DSIM_ESC_CLKEN_SHIFT;
-	if (enable)
-		reg |= prs_val;
-
-	writel(reg, &mipi_dsim->clkctrl);
-}
-
-void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
-		unsigned int lane_sel, unsigned int enable)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->clkctrl);
-
-	if (enable)
-		reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
-	else
-		reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
-
-	writel(reg, &mipi_dsim->clkctrl);
-}
-
-void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
-	unsigned int enable)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->escmode)) &
-		~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);
-
-	reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);
-
-	writel(reg, &mipi_dsim->escmode);
-}
-
-unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->status);
-
-	/**
-	 * check clock and data lane states.
-	 * if MIPI-DSI controller was enabled at bootloader then
-	 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
-	 * so it should be checked for two case.
-	 */
-	if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
-			((reg & DSIM_STOP_STATE_CLK) ||
-			 (reg & DSIM_TX_READY_HS_CLK)))
-		return 1;
-	else
-		return 0;
-}
-
-void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
-		unsigned int cnt_val)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->escmode)) &
-		~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);
-
-	reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);
-
-	writel(reg, &mipi_dsim->escmode);
-}
-
-void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
-		unsigned int timeout)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->timeout)) &
-		~(0xff << DSIM_BTA_TOUT_SHIFT);
-
-	reg |= (timeout << DSIM_BTA_TOUT_SHIFT);
-
-	writel(reg, &mipi_dsim->timeout);
-}
-
-void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
-		unsigned int timeout)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->timeout)) &
-		~(0xffff << DSIM_LPDR_TOUT_SHIFT);
-
-	reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);
-
-	writel(reg, &mipi_dsim->timeout);
-}
-
-void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
-		unsigned int lp)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->escmode);
-
-	reg &= ~DSIM_CMD_LPDT_LP;
-
-	if (lp)
-		reg |= DSIM_CMD_LPDT_LP;
-
-	writel(reg, &mipi_dsim->escmode);
-}
-
-void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
-		unsigned int lp)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->escmode);
-
-	reg &= ~DSIM_TX_LPDT_LP;
-
-	if (lp)
-		reg |= DSIM_TX_LPDT_LP;
-
-	writel(reg, &mipi_dsim->escmode);
-}
-
-void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
-		unsigned int enable)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
-		~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);
-
-	reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;
-
-	writel(reg, &mipi_dsim->clkctrl);
-}
-
-void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
-		unsigned int swap_en)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->phyacchr1);
-
-	reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT);
-	reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT;
-
-	writel(reg, &mipi_dsim->phyacchr1);
-}
-
-void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
-		unsigned int hs_zero)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
-		~(0xf << DSIM_ZEROCTRL_SHIFT);
-
-	reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT);
-
-	writel(reg, &mipi_dsim->pllctrl);
-}
-
-void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
-		~(0x7 << DSIM_PRECTRL_SHIFT);
-
-	reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT);
-
-	writel(reg, &mipi_dsim->pllctrl);
-}
-
-void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->intsrc);
-
-	reg |= INTSRC_PLL_STABLE;
-
-	writel(reg, &mipi_dsim->intsrc);
-}
-
-void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	writel(0xffffffff, &mipi_dsim->intsrc);
-}
-
-unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
-{
-	unsigned int reg;
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	reg = readl(&mipi_dsim->status);
-
-	return reg & DSIM_PLL_STABLE ? 1 : 0;
-}
-
-unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	return readl(&mipi_dsim->fifoctrl) & ~(0x1f);
-}
-
-void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
-	unsigned int di, const unsigned char data0, const unsigned char data1)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) |
-			DSIM_PKTHDR_DI(di));
-
-	writel(reg, &mipi_dsim->pkthdr);
-}
-
-unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
-						*dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->intsrc);
-
-	return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
-}
-
-void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-	unsigned int reg = readl(&mipi_dsim->intsrc);
-
-	writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc);
-}
-
-void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
-		unsigned int tx_data)
-{
-	struct exynos_mipi_dsim *mipi_dsim =
-		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
-
-	writel(tx_data, &mipi_dsim->payload);
-}
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos_mipi_dsi_lowlevel.h
deleted file mode 100644
index 0bede25..0000000
--- a/drivers/video/exynos_mipi_dsi_lowlevel.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EXYNOS_MIPI_DSI_LOWLEVEL_H
-#define _EXYNOS_MIPI_DSI_LOWLEVEL_H
-
-void exynos_mipi_dsi_register(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
-	unsigned int mode, unsigned int mask);
-void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
-					unsigned int count);
-void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
-					unsigned int cfg);
-void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
-				unsigned int value);
-void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
-				unsigned int value);
-void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
-		unsigned int width_resol, unsigned int height_resol);
-void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
-	unsigned int cmd_allow, unsigned int vfront, unsigned int vback);
-void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
-			unsigned int front, unsigned int back);
-void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
-				unsigned int vert, unsigned int hori);
-void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
-				unsigned int vert, unsigned int hori);
-void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
-				struct mipi_dsim_config *dsim_config);
-void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
-				unsigned int count);
-void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
-			unsigned int lane, unsigned int enable);
-void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
-			unsigned int enable, unsigned int afc_code);
-void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
-				unsigned int enable);
-void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
-				unsigned int freq_band);
-void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
-			unsigned int pre_divider, unsigned int main_divider,
-			unsigned int scaler);
-void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
-			unsigned int lock_time);
-void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
-					unsigned int enable);
-void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
-					unsigned int src);
-void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
-					unsigned int enable);
-void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
-				unsigned int enable, unsigned int prs_val);
-void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
-				unsigned int lane_sel, unsigned int enable);
-void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
-				unsigned int enable);
-unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
-				unsigned int cnt_val);
-void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
-				unsigned int timeout);
-void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
-				unsigned int timeout);
-void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
-					unsigned int lp);
-void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
-					unsigned int lp);
-void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
-				unsigned int enable);
-void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
-				unsigned int swap_en);
-void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
-				unsigned int hs_zero);
-void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim,
-				unsigned int prep);
-void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim);
-unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim);
-unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim);
-unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
-						*dsim);
-void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
-void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
-		unsigned int di, const unsigned char data0, const unsigned char data1);
-void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
-		unsigned int tx_data);
-
-#endif /* _EXYNOS_MIPI_DSI_LOWLEVEL_H */
diff --git a/drivers/video/exynos_pwm_bl.c b/drivers/video/exynos_pwm_bl.c
deleted file mode 100644
index a6890da..0000000
--- a/drivers/video/exynos_pwm_bl.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * PWM BACKLIGHT driver for Board based on EXYNOS.
- *
- * Author: Donghwa Lee  <dh09.lee@samsung.com>
- *
- * Derived from linux/drivers/video/backlight/pwm_backlight.c
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <pwm.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/pwm_backlight.h>
-
-static struct pwm_backlight_data *pwm;
-
-static int exynos_pwm_backlight_update_status(void)
-{
-	int brightness = pwm->brightness;
-	int max = pwm->max_brightness;
-
-	if (brightness == 0) {
-		pwm_config(pwm->pwm_id, 0, pwm->period);
-		pwm_disable(pwm->pwm_id);
-	} else {
-		pwm_config(pwm->pwm_id,
-			brightness * pwm->period / max, pwm->period);
-		pwm_enable(pwm->pwm_id);
-	}
-	return 0;
-}
-
-int exynos_pwm_backlight_init(struct pwm_backlight_data *pd)
-{
-	pwm = pd;
-
-	exynos_pwm_backlight_update_status();
-
-	return 0;
-}
diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c
index 8494817..1bd49ee 100644
--- a/drivers/video/s6e8ax0.c
+++ b/drivers/video/s6e8ax0.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <asm/arch/mipi_dsim.h>
 
-#include "exynos_mipi_dsi_lowlevel.h"
-#include "exynos_mipi_dsi_common.h"
+#include "exynos/exynos_mipi_dsi_lowlevel.h"
+#include "exynos/exynos_mipi_dsi_common.h"
 
 static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
 {
-- 
cgit v0.10.2


From b6feb2675b75c687b9ddb9e5a493cfe4035e387d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:39 -0700
Subject: exynos: video: Drop dead code

We always use device tree with video, so can drop these #ifdefs. Some of the
hardware addresses are not needed either.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index f12e3d6..1f722df 100644
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -288,9 +288,7 @@ static inline unsigned long __attribute__((no_instrument_function)) \
 SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
-SAMSUNG_BASE(dp, DP_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(i2c, I2C_BASE)
 SAMSUNG_BASE(i2s, I2S_BASE)
 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index acb5bc8..e417cf8 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -22,7 +22,6 @@ struct exynos_dp *dp_regs;
 
 void exynos_dp_set_base_addr(void)
 {
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 	unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
 					0, COMPAT_SAMSUNG_EXYNOS5_DP);
 	if (node <= 0)
@@ -32,9 +31,6 @@ void exynos_dp_set_base_addr(void)
 								node, "reg");
 	if (dp_regs == NULL)
 		debug("Can't get the DP base address\n");
-#else
-	dp_regs = (struct exynos_dp *)samsung_get_base_dp();
-#endif
 }
 
 static void exynos_dp_enable_video_input(unsigned int enable)
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 69edc3a..39e3ade 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -28,7 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned int panel_width, panel_height;
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 vidinfo_t panel_info  = {
 	/*
 	 * Insert a value here so that we don't end up in the BSS
@@ -36,7 +35,6 @@ vidinfo_t panel_info  = {
 	 */
 	.vl_col = -1,
 };
-#endif
 
 ushort *configuration_get_cmap(void)
 {
@@ -126,7 +124,6 @@ static void lcd_panel_on(vidinfo_t *vid)
 
 	exynos_backlight_on(1);
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 	node = fdtdec_next_compatible(gd->fdt_blob, 0,
 						COMPAT_SAMSUNG_EXYNOS_FIMD);
 	if (node <= 0) {
@@ -141,7 +138,6 @@ static void lcd_panel_on(vidinfo_t *vid)
 				   &bl_en_gpio,
 				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 
-#endif
 	exynos_cfg_ldo();
 
 	exynos_enable_ldo(1);
@@ -150,7 +146,6 @@ static void lcd_panel_on(vidinfo_t *vid)
 		exynos_mipi_dsi_init();
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 int exynos_lcd_early_init(const void *blob)
 {
 	unsigned int node;
@@ -288,22 +283,16 @@ int exynos_lcd_early_init(const void *blob)
 
 	return 0;
 }
-#endif
 
 void lcd_ctrl_init(void *lcdbase)
 {
 	set_system_display_ctrl();
 	set_lcd_clk();
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 #ifdef CONFIG_EXYNOS_MIPI_DSIM
 	exynos_init_dsim_platform_data(&panel_info);
 #endif
 	exynos_lcd_misc_init(&panel_info);
-#else
-	/* initialize parameters which is specific to panel. */
-	init_panel_info(&panel_info);
-#endif
 
 	panel_width = panel_info.vl_width;
 	panel_height = panel_info.vl_height;
diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c
index ac001a8..019d88f 100644
--- a/drivers/video/exynos/exynos_fimd.c
+++ b/drivers/video/exynos/exynos_fimd.c
@@ -251,7 +251,6 @@ void exynos_fimd_window_off(unsigned int win_id)
 	writel(cfg, &fimd_ctrl->winshmap);
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 /*
 * The reset value for FIMD SYSMMU register MMU_CTRL is 3
 * on Exynos5420 and newer versions.
@@ -289,13 +288,11 @@ void exynos_fimd_disable_sysmmu(void)
 		writel(0x0, sysmmufimd);
 	}
 }
-#endif
 
 void exynos_fimd_lcd_init(vidinfo_t *vid)
 {
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 	unsigned int node;
 
 	node = fdtdec_next_compatible(gd->fdt_blob,
@@ -311,10 +308,6 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
 	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
 		exynos_fimd_disable_sysmmu();
 
-#else
-	fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
-#endif
-
 	offset = exynos_fimd_get_base_offset();
 
 	/* store panel info to global variable */
diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index b597acc..5001e16 100644
--- a/drivers/video/exynos/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -28,11 +28,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct exynos_platform_mipi_dsim *dsim_pd;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 static struct mipi_dsim_config dsim_config_dt;
 static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
-#endif
 
 struct mipi_dsim_ddi {
 	int				bus_id;
@@ -249,7 +247,6 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
 	dsim_pd = pd;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 int exynos_dsim_config_parse_dt(const void *blob)
 {
 	int node;
@@ -334,4 +331,3 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 
 	dsim_pd = &dsim_platform_data_dt;
 }
-#endif
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
index 3969a6a..e1769f0 100644
--- a/include/exynos_lcd.h
+++ b/include/exynos_lcd.h
@@ -77,6 +77,4 @@ typedef struct vidinfo {
 	unsigned int dual_lcd_enabled;
 } vidinfo_t;
 
-void init_panel_info(vidinfo_t *vid);
-
 #endif
-- 
cgit v0.10.2


From aaca5b1902e1d711d34f2fb741417ec7bae59ad6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:40 -0700
Subject: exynos: video: Remove use of vidinfo_t typedef

Use 'struct vidinfo' instead so that we can change this to a struct with a
different name in future.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/mipi_dsim.h b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
index c9e8e06..a77b5c8 100644
--- a/arch/arm/mach-exynos/include/mach/mipi_dsim.h
+++ b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
@@ -369,7 +369,8 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
 						*lcd_dev);
 
 void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
-void exynos_init_dsim_platform_data(vidinfo_t *vid);
+struct vidinfo;
+void exynos_init_dsim_platform_data(struct vidinfo *vid);
 
 /* panel driver init based on mipi dsi interface */
 void s6e8ax0_init(void);
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 39e3ade..90d2038 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned int panel_width, panel_height;
 
-vidinfo_t panel_info  = {
+struct vidinfo panel_info  = {
 	/*
 	 * Insert a value here so that we don't end up in the BSS
 	 * Reference: drivers/video/tegra.c
@@ -45,7 +45,7 @@ ushort *configuration_get_cmap(void)
 #endif
 }
 
-static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
+static void exynos_lcd_init_mem(void *lcdbase, struct vidinfo *vid)
 {
 	unsigned long palette_size;
 	unsigned int fb_size;
@@ -58,7 +58,7 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
 			(unsigned long)fb_size, palette_size);
 }
 
-static void exynos_lcd_init(vidinfo_t *vid)
+static void exynos_lcd_init(struct vidinfo *vid)
 {
 	exynos_fimd_lcd_init(vid);
 
@@ -94,12 +94,12 @@ __weak void exynos_backlight_reset(void)
 {
 }
 
-__weak int exynos_lcd_misc_init(vidinfo_t *vid)
+__weak int exynos_lcd_misc_init(struct vidinfo *vid)
 {
 	return 0;
 }
 
-static void lcd_panel_on(vidinfo_t *vid)
+static void lcd_panel_on(struct vidinfo *vid)
 {
 	struct gpio_desc pwm_out_gpio;
 	struct gpio_desc bl_en_gpio;
diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c
index 019d88f..e6fb5d1 100644
--- a/drivers/video/exynos/exynos_fimd.c
+++ b/drivers/video/exynos/exynos_fimd.c
@@ -22,7 +22,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned long *lcd_base_addr;
-static vidinfo_t *pvid;
+static struct vidinfo *pvid;
 static struct exynos_fb *fimd_ctrl;
 
 void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
@@ -123,7 +123,7 @@ static void exynos_fimd_set_buffer_address(unsigned int win_id)
 			EXYNOS_BUFFER_OFFSET(win_id));
 }
 
-static void exynos_fimd_set_clock(vidinfo_t *pvid)
+static void exynos_fimd_set_clock(struct vidinfo *pvid)
 {
 	unsigned int cfg = 0, div = 0, remainder, remainder_div;
 	unsigned long pixel_clock;
@@ -289,7 +289,7 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(vidinfo_t *vid)
+void exynos_fimd_lcd_init(struct vidinfo *vid)
 {
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c
index 925d515..85c5e0d 100644
--- a/drivers/video/exynos/exynos_mipi_dsi_common.c
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.c
@@ -465,7 +465,7 @@ int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
 }
 
 static void convert_to_fb_videomode(struct fb_videomode *mode1,
-				vidinfo_t *mode2)
+				    struct vidinfo *mode2)
 {
 	mode1->xres = mode2->vl_width;
 	mode1->yres = mode2->vl_height;
@@ -482,10 +482,10 @@ int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
 {
 	struct exynos_platform_mipi_dsim *dsim_pd;
 	struct fb_videomode lcd_video;
-	vidinfo_t *vid;
+	struct vidinfo *vid;
 
 	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
-	vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
+	vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
 
 	convert_to_fb_videomode(&lcd_video, vid);
 
-- 
cgit v0.10.2


From 40d500212f74c92ef014ae8df697416e160ee743 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:41 -0700
Subject: exynos: video: Drop the static lcd_base_addr variable

Drop this and use parameters instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 90d2038..a3acdcc 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -45,22 +45,9 @@ ushort *configuration_get_cmap(void)
 #endif
 }
 
-static void exynos_lcd_init_mem(void *lcdbase, struct vidinfo *vid)
+static void exynos_lcd_init(struct vidinfo *vid, ulong lcd_base)
 {
-	unsigned long palette_size;
-	unsigned int fb_size;
-
-	fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
-
-	palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-
-	exynos_fimd_lcd_init_mem((unsigned long)lcdbase,
-			(unsigned long)fb_size, palette_size);
-}
-
-static void exynos_lcd_init(struct vidinfo *vid)
-{
-	exynos_fimd_lcd_init(vid);
+	exynos_fimd_lcd_init(vid, lcd_base);
 
 	/* Enable flushing after LCD writes if requested */
 	lcd_set_flush_dcache(1);
@@ -297,9 +284,7 @@ void lcd_ctrl_init(void *lcdbase)
 	panel_width = panel_info.vl_width;
 	panel_height = panel_info.vl_height;
 
-	exynos_lcd_init_mem(lcdbase, &panel_info);
-
-	exynos_lcd_init(&panel_info);
+	exynos_lcd_init(&panel_info, (ulong)lcdbase);
 }
 
 void lcd_enable(void)
diff --git a/drivers/video/exynos/exynos_fb.h b/drivers/video/exynos/exynos_fb.h
index 2c2f94b..833be6a 100644
--- a/drivers/video/exynos/exynos_fb.h
+++ b/drivers/video/exynos/exynos_fb.h
@@ -35,7 +35,7 @@ enum exynos_cpu_auto_cmd_rate {
 
 void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
 	unsigned long palette_size);
-void exynos_fimd_lcd_init(vidinfo_t *vid);
+void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address);
 unsigned long exynos_fimd_calc_fbsize(void);
 
 #endif
diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c
index e6fb5d1..a1de9ac 100644
--- a/drivers/video/exynos/exynos_fimd.c
+++ b/drivers/video/exynos/exynos_fimd.c
@@ -21,16 +21,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static unsigned long *lcd_base_addr;
 static struct vidinfo *pvid;
 static struct exynos_fb *fimd_ctrl;
 
-void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
-		u_long palette_size)
-{
-	lcd_base_addr = (unsigned long *)screen_base;
-}
-
 static void exynos_fimd_set_dualrgb(unsigned int enabled)
 {
 	unsigned int cfg = 0;
@@ -47,7 +40,8 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled)
 	writel(cfg, &fimd_ctrl->dualrgb);
 }
 
-static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
+static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
+				      unsigned int enabled)
 {
 	unsigned int cfg = 0;
 
@@ -57,7 +51,7 @@ static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
 	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
 }
 
-static void exynos_fimd_set_par(unsigned int win_id)
+static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
 {
 	unsigned int cfg = 0;
 
@@ -109,11 +103,13 @@ static void exynos_fimd_set_par(unsigned int win_id)
 			EXYNOS_VIDOSD(win_id));
 }
 
-static void exynos_fimd_set_buffer_address(unsigned int win_id)
+static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
+					   unsigned int win_id,
+					   ulong lcd_base_addr)
 {
 	unsigned long start_addr, end_addr;
 
-	start_addr = (unsigned long)lcd_base_addr;
+	start_addr = lcd_base_addr;
 	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
 				pvid->vl_row);
 
@@ -289,7 +285,7 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(struct vidinfo *vid)
+void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address)
 {
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
@@ -367,10 +363,10 @@ void exynos_fimd_lcd_init(struct vidinfo *vid)
 	writel(cfg, &fimd_ctrl->vidcon0);
 
 	/* set par */
-	exynos_fimd_set_par(pvid->win_id);
+	exynos_fimd_set_par(pvid, pvid->win_id);
 
 	/* set memory address */
-	exynos_fimd_set_buffer_address(pvid->win_id);
+	exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address);
 
 	/* set buffer size */
 	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
@@ -393,7 +389,7 @@ void exynos_fimd_lcd_init(struct vidinfo *vid)
 	/* window on */
 	exynos_fimd_window_on(pvid->win_id);
 
-	exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
+	exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
 }
 
 unsigned long exynos_fimd_calc_fbsize(void)
-- 
cgit v0.10.2


From 162fa53c8d3c2f832d791d0bb7a72fec1562fba4 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:42 -0700
Subject: exynos: video: Drop static variables in exynos_fimd.c

Drop these and use parameters instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/exynos_fb.h b/drivers/video/exynos/exynos_fb.h
index 833be6a..f59cce0 100644
--- a/drivers/video/exynos/exynos_fb.h
+++ b/drivers/video/exynos/exynos_fb.h
@@ -36,6 +36,6 @@ enum exynos_cpu_auto_cmd_rate {
 void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
 	unsigned long palette_size);
 void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address);
-unsigned long exynos_fimd_calc_fbsize(void);
+unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid);
 
 #endif
diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c
index a1de9ac..039d4c5 100644
--- a/drivers/video/exynos/exynos_fimd.c
+++ b/drivers/video/exynos/exynos_fimd.c
@@ -21,11 +21,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct vidinfo *pvid;
-static struct exynos_fb *fimd_ctrl;
-
-static void exynos_fimd_set_dualrgb(unsigned int enabled)
+static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	if (enabled) {
@@ -43,6 +41,7 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled)
 static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
 				      unsigned int enabled)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	if (enabled)
@@ -53,6 +52,7 @@ static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
 
 static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	/* set window control */
@@ -107,6 +107,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
 					   unsigned int win_id,
 					   ulong lcd_base_addr)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned long start_addr, end_addr;
 
 	start_addr = lcd_base_addr;
@@ -121,6 +122,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
 
 static void exynos_fimd_set_clock(struct vidinfo *pvid)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0, div = 0, remainder, remainder_div;
 	unsigned long pixel_clock;
 	unsigned long long src_clock;
@@ -172,8 +174,9 @@ static void exynos_fimd_set_clock(struct vidinfo *pvid)
 	writel(cfg, &fimd_ctrl->vidcon0);
 }
 
-void exynos_set_trigger(void)
+void exynos_set_trigger(struct vidinfo *pvid)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	cfg = readl(&fimd_ctrl->trigcon);
@@ -183,8 +186,9 @@ void exynos_set_trigger(void)
 	writel(cfg, &fimd_ctrl->trigcon);
 }
 
-int exynos_is_i80_frame_done(void)
+int exynos_is_i80_frame_done(struct vidinfo *pvid)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 	int status;
 
@@ -197,8 +201,9 @@ int exynos_is_i80_frame_done(void)
 	return status;
 }
 
-static void exynos_fimd_lcd_on(void)
+static void exynos_fimd_lcd_on(struct vidinfo *pvid)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	/* display on */
@@ -207,8 +212,9 @@ static void exynos_fimd_lcd_on(void)
 	writel(cfg, &fimd_ctrl->vidcon0);
 }
 
-static void exynos_fimd_window_on(unsigned int win_id)
+static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	/* enable window */
@@ -223,8 +229,9 @@ static void exynos_fimd_window_on(unsigned int win_id)
 	writel(cfg, &fimd_ctrl->winshmap);
 }
 
-void exynos_fimd_lcd_off(void)
+void exynos_fimd_lcd_off(struct vidinfo *pvid)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	cfg = readl(&fimd_ctrl->vidcon0);
@@ -232,8 +239,9 @@ void exynos_fimd_lcd_off(void)
 	writel(cfg, &fimd_ctrl->vidcon0);
 }
 
-void exynos_fimd_window_off(unsigned int win_id)
+void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id)
 {
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
 	unsigned int cfg = 0;
 
 	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
@@ -285,8 +293,9 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address)
+void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address)
 {
+	struct exynos_fb *fimd_ctrl;
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
 	unsigned int node;
@@ -296,22 +305,20 @@ void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address)
 	if (node <= 0)
 		debug("exynos_fb: Can't get device node for fimd\n");
 
-	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
+	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
+							"reg");
 	if (fimd_ctrl == NULL)
 		debug("Can't get the FIMD base address\n");
+	pvid->fimd_ctrl = fimd_ctrl;
 
 	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
 		exynos_fimd_disable_sysmmu();
 
 	offset = exynos_fimd_get_base_offset();
 
-	/* store panel info to global variable */
-	pvid = vid;
-
-	rgb_mode = vid->rgb_mode;
+	rgb_mode = pvid->rgb_mode;
 
-	if (vid->interface_mode == FIMD_RGB_INTERFACE) {
+	if (pvid->interface_mode == FIMD_RGB_INTERFACE) {
 		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
 		writel(cfg, &fimd_ctrl->vidcon0);
 
@@ -381,18 +388,18 @@ void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address)
 	exynos_fimd_set_clock(pvid);
 
 	/* set rgb mode to dual lcd. */
-	exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
+	exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled);
 
 	/* display on */
-	exynos_fimd_lcd_on();
+	exynos_fimd_lcd_on(pvid);
 
 	/* window on */
-	exynos_fimd_window_on(pvid->win_id);
+	exynos_fimd_window_on(pvid, pvid->win_id);
 
 	exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
 }
 
-unsigned long exynos_fimd_calc_fbsize(void)
+unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid)
 {
 	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
 }
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
index e1769f0..1f6c6c7 100644
--- a/include/exynos_lcd.h
+++ b/include/exynos_lcd.h
@@ -75,6 +75,7 @@ typedef struct vidinfo {
 	unsigned int sclk_div;
 
 	unsigned int dual_lcd_enabled;
+	struct exynos_fb *fimd_ctrl;
 } vidinfo_t;
 
 #endif
-- 
cgit v0.10.2


From 9c4d440e859c34994689504f1a0d028619042ef3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:43 -0700
Subject: exynos: video: Drop static variables in exynos_fb.c

Drop these and use the existing variables instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index a3acdcc..abc6091 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -26,8 +26,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static unsigned int panel_width, panel_height;
-
 struct vidinfo panel_info  = {
 	/*
 	 * Insert a value here so that we don't end up in the BSS
@@ -281,16 +279,14 @@ void lcd_ctrl_init(void *lcdbase)
 #endif
 	exynos_lcd_misc_init(&panel_info);
 
-	panel_width = panel_info.vl_width;
-	panel_height = panel_info.vl_height;
-
 	exynos_lcd_init(&panel_info, (ulong)lcdbase);
 }
 
 void lcd_enable(void)
 {
 	if (panel_info.logo_on) {
-		memset((void *) gd->fb_base, 0, panel_width * panel_height *
+		memset((void *)gd->fb_base, 0,
+		       panel_info.vl_width * panel_info.vl_height *
 				(NBITS(panel_info.vl_bpix) >> 3));
 	}
 
-- 
cgit v0.10.2


From 8c9b8dc05aec6be390dae8a85da7cb56ed8b4ed9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:44 -0700
Subject: exynos: video: Drop static variables in exynos_dp_lowlevel.c

Drop these and use parameters instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 0d5d090..9945c4b 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -38,20 +38,20 @@ static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 	return;
 }
 
-static int exynos_dp_init_dp(void)
+static int exynos_dp_init_dp(struct exynos_dp *dp_regs)
 {
 	int ret;
-	exynos_dp_reset();
+	exynos_dp_reset(dp_regs);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_func(DP_ENABLE);
+	exynos_dp_enable_sw_func(dp_regs, DP_ENABLE);
 
-	ret = exynos_dp_init_analog_func();
+	ret = exynos_dp_init_analog_func(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS)
 		return ret;
 
-	exynos_dp_init_hpd();
-	exynos_dp_init_aux();
+	exynos_dp_init_hpd(dp_regs);
+	exynos_dp_init_aux(dp_regs);
 
 	return ret;
 }
@@ -67,7 +67,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static unsigned int exynos_dp_read_edid(void)
+static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -82,14 +82,15 @@ static unsigned int exynos_dp_read_edid(void)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
-			&extend_block);
+	exynos_dp_read_byte_from_i2c(dp_regs, I2C_EDID_DEVICE_ADDR,
+				     EDID_EXTENSION_FLAG, &extend_block);
 
 	if (extend_block > 0) {
 		printf("DP EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -104,7 +105,8 @@ static unsigned int exynos_dp_read_edid(void)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
 				&edid[EDID_BLOCK_LENGTH]);
@@ -118,19 +120,22 @@ static unsigned int exynos_dp_read_edid(void)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
-					&test_vector);
+		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
+					      &test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
 	} else {
 		debug("DP EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
 				&edid[EDID_HEADER_PATTERN]);
@@ -145,12 +150,13 @@ static unsigned int exynos_dp_read_edid(void)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
@@ -160,7 +166,8 @@ static unsigned int exynos_dp_read_edid(void)
 	return 0;
 }
 
-static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
+					  struct edp_device_info *edp_info)
 {
 	unsigned char buf[12];
 	unsigned int ret;
@@ -178,8 +185,8 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	retry_cnt = 5;
 	while (retry_cnt) {
 		/* Read DPCD 0x0000-0x000b */
-		ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
-				buf);
+		ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_DPCD_REV, 12,
+						     buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			if (retry_cnt == 0) {
 				printf("DP read_byte_from_dpcd() failed\n");
@@ -227,7 +234,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 		return -EINVAL;
 	}
 
-	ret = exynos_dp_read_edid();
+	ret = exynos_dp_read_edid(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_read_edid() failed\n");
 		return -EINVAL;
@@ -236,19 +243,20 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static void exynos_dp_init_training(void)
+static void exynos_dp_init_training(struct exynos_dp *dp_regs)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro();
+	exynos_dp_reset_macro(dp_regs);
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(POWER_ALL, 0);
+	exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, 0);
 }
 
-static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
+					 struct edp_device_info *edp_info)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;
@@ -263,33 +271,32 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	edp_info->lt_info.cr_loop[3] = 0;
 
 		/* Set sink to D0 (Sink Not Ready) mode. */
-		ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
-				DPCD_SET_POWER_STATE_D0);
+	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_SINK_POWER_STATE,
+					   DPCD_SET_POWER_STATE_D0);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
 	/* Set link rate and count as you want to establish */
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
+	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
 
 	/* Setup RX configuration */
 	buf[0] = edp_info->lane_bw;
 	buf[1] = edp_info->lane_cnt;
 
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
-			buf);
+	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_LINK_BW_SET, 2, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
-	exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
+	exynos_dp_set_lane_pre_emphasis(dp_regs, PRE_EMPHASIS_LEVEL_0,
 			edp_info->lane_cnt);
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(TRAINING_PTN1);
+	exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN1);
 
 	/* Set RX training pattern */
 	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
@@ -303,8 +310,8 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			5, buf);
+	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+					    5, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
@@ -313,14 +320,14 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_training_pattern_dis(void)
+static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	exynos_dp_set_training_pattern(DP_NONE);
+	exynos_dp_set_training_pattern(dp_regs, DP_NONE);
 
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			DPCD_TRAINING_PATTERN_DISABLED);
+	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+					   DPCD_TRAINING_PATTERN_DISABLED);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP request_link_training_req failed\n");
 		return -EAGAIN;
@@ -329,13 +336,14 @@ static unsigned int exynos_dp_training_pattern_dis(void)
 	return ret;
 }
 
-static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
+static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
+		struct exynos_dp *dp_regs, unsigned char enable)
 {
 	unsigned char data;
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
-			&data);
+	ret = exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_LANE_COUNT_SET,
+					    &data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read_from_dpcd failed\n");
 		return -EAGAIN;
@@ -346,8 +354,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
 	else
 		data = DPCD_LN_COUNT_SET(data);
 
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
-			data);
+	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_LANE_COUNT_SET, data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write_to_dpcd failed\n");
 			return -EAGAIN;
@@ -357,23 +364,25 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
 	return ret;
 }
 
-static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
+static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
+						unsigned char enhance_mode)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
+	ret = exynos_dp_enable_rx_to_enhanced_mode(dp_regs, enhance_mode);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP rx_enhance_mode failed\n");
 		return -EAGAIN;
 	}
 
-	exynos_dp_enable_enhanced_mode(enhance_mode);
+	exynos_dp_enable_enhanced_mode(dp_regs, enhance_mode);
 
 	return ret;
 }
 
-static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
-		unsigned char *status)
+static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
+					 struct edp_device_info *edp_info,
+					 unsigned char *status)
 {
 	unsigned int ret, i;
 	unsigned char buf[2];
@@ -385,7 +394,8 @@ static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
 	shift_val[2] = 0;
 	shift_val[3] = 4;
 
-	ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
+	ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_LANE0_1_STATUS, 2,
+					     buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		return ret;
@@ -404,8 +414,8 @@ static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
 	return ret;
 }
 
-static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
-		unsigned char *sw, unsigned char *em)
+static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
+		unsigned char lane_num, unsigned char *sw, unsigned char *em)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char buf;
@@ -415,7 +425,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
 	/* lane_num value is used as array index, so this range 0 ~ 3 */
 	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 
-	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
+	ret = exynos_dp_read_byte_from_dpcd(dp_regs, dpcd_addr, &buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read adjust request failed\n");
 		return -EAGAIN;
@@ -427,17 +437,18 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
 	return ret;
 }
 
-static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
+static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
+					struct edp_device_info *edp_info)
 {
 	int ret;
 
-	ret = exynos_dp_training_pattern_dis();
+	ret = exynos_dp_training_pattern_dis(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP training_pattern_disable() failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
 	}
 
-	ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+	ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP set_enhanced_mode() failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
@@ -446,7 +457,8 @@ static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
+static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
+				      struct edp_device_info *edp_info)
 {
 	int ret;
 
@@ -456,11 +468,11 @@ static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
 		edp_info->lt_info.lt_status = DP_LT_START;
 		ret = EXYNOS_DP_SUCCESS;
 	} else {
-		ret = exynos_dp_training_pattern_dis();
+		ret = exynos_dp_training_pattern_dis(dp_regs);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP training_patter_disable() failed\n");
 
-		ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+		ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP set_enhanced_mode() failed\n");
 
@@ -470,8 +482,8 @@ static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
-							*edp_info)
+static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
+					struct edp_device_info *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;
@@ -484,7 +496,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 	debug("DP: %s was called\n", __func__);
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP read lane status failed\n");
 			edp_info->lt_info.lt_status = DP_LT_FAIL;
@@ -493,11 +505,11 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
 		debug("DP clock Recovery training succeed\n");
-		exynos_dp_set_training_pattern(TRAINING_PTN2);
+		exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN2);
 
 		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
-					&adj_req_em);
+			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				edp_info->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
@@ -511,7 +523,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+							 lt_ctl_val[i], i);
 		}
 
 		buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
@@ -520,7 +533,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 		buf[3] = lt_ctl_val[2];
 		buf[4] = lt_ctl_val[3];
 
-		ret = exynos_dp_write_bytes_to_dpcd(
+		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 				DPCD_TRAINING_PATTERN_SET, 5, buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern1 failed\n");
@@ -530,8 +543,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 			edp_info->lt_info.lt_status = DP_LT_ET;
 	} else {
 		for (i = 0; i < edp_info->lane_cnt; i++) {
-			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
-				ret = exynos_dp_read_dpcd_adj_req(i,
+			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
+						dp_regs, i);
+				ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req failed\n");
@@ -541,7 +555,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 
 			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
-				ret = exynos_dp_reduce_link_rate(edp_info);
+				ret = exynos_dp_reduce_link_rate(dp_regs,
+								 edp_info);
 
 			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_sw) &&
@@ -550,7 +565,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				edp_info->lt_info.cr_loop[i]++;
 				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
 					ret = exynos_dp_reduce_link_rate(
-							edp_info);
+							dp_regs, edp_info);
 			}
 
 			lt_ctl_val[i] = 0;
@@ -561,10 +576,11 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+							 lt_ctl_val[i], i);
 		}
 
-		ret = exynos_dp_write_bytes_to_dpcd(
+		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern2 failed\n");
@@ -576,8 +592,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 	return ret;
 }
 
-static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
-		*edp_info)
+static unsigned int exynos_dp_process_equalizer_training(
+		struct exynos_dp *dp_regs, struct edp_device_info *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;
@@ -589,7 +605,7 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
@@ -599,8 +615,9 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 	debug("DP lane stat : %x\n", lane_stat);
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
-				&sink_stat);
+		ret = exynos_dp_read_byte_from_dpcd(dp_regs,
+						    DPCD_LN_ALIGN_UPDATED,
+						    &sink_stat);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			edp_info->lt_info.lt_status = DP_LT_FAIL;
 
@@ -610,7 +627,7 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 
 		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i,
+			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 					&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req 1 failed\n");
@@ -634,15 +651,15 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 			debug("DP Equalizer training succeed\n");
 
-			f_bw = exynos_dp_get_link_bandwidth();
-			f_lane_cnt = exynos_dp_get_lane_count();
+			f_bw = exynos_dp_get_link_bandwidth(dp_regs);
+			f_lane_cnt = exynos_dp_get_lane_count(dp_regs);
 
 			debug("DP final BandWidth : %x\n", f_bw);
 			debug("DP final Lane Count : %x\n", f_lane_cnt);
 
 			edp_info->lt_info.lt_status = DP_LT_FINISHED;
 
-			exynos_dp_equalizer_err_link(edp_info);
+			exynos_dp_equalizer_err_link(dp_regs, edp_info);
 
 		} else {
 			edp_info->lt_info.ep_loop++;
@@ -650,46 +667,49 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
 				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
 					ret = exynos_dp_reduce_link_rate(
-							edp_info);
+							dp_regs, edp_info);
 				} else {
 					edp_info->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
+					exynos_dp_equalizer_err_link(dp_regs,
+								     edp_info);
 				}
 			} else {
 				for (i = 0; i < edp_info->lane_cnt; i++)
 					exynos_dp_set_lanex_pre_emphasis(
-							lt_ctl_val[i], i);
+						dp_regs, lt_ctl_val[i], i);
 
-				ret = exynos_dp_write_bytes_to_dpcd(
-					DPCD_TRAINING_LANE0_SET,
-					4, lt_ctl_val);
+				ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+						DPCD_TRAINING_LANE0_SET,
+						4, lt_ctl_val);
 				if (ret != EXYNOS_DP_SUCCESS) {
 					printf("DP set lt pattern failed\n");
 					edp_info->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
+					exynos_dp_equalizer_err_link(dp_regs,
+								     edp_info);
 				}
 			}
 		}
 	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		ret = exynos_dp_reduce_link_rate(edp_info);
+		ret = exynos_dp_reduce_link_rate(dp_regs, edp_info);
 	} else {
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		exynos_dp_equalizer_err_link(edp_info);
+		exynos_dp_equalizer_err_link(dp_regs, edp_info);
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
+					       struct edp_device_info *edp_info)
 {
 	unsigned int ret = 0;
 	int training_finished;
 
 	/* Turn off unnecessary lane */
 	if (edp_info->lane_cnt == 1)
-		exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
+		exynos_dp_set_analog_power_down(dp_regs, CH1_BLOCK, 1);
 
 	training_finished = 0;
 
@@ -699,21 +719,23 @@ static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
 	while (!training_finished) {
 		switch (edp_info->lt_info.lt_status) {
 		case DP_LT_START:
-			ret = exynos_dp_link_start(edp_info);
+			ret = exynos_dp_link_start(dp_regs, edp_info);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:link start failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_CR:
-			ret = exynos_dp_process_clock_recovery(edp_info);
+			ret = exynos_dp_process_clock_recovery(dp_regs,
+							       edp_info);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:clock recovery failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_ET:
-			ret = exynos_dp_process_equalizer_training(edp_info);
+			ret = exynos_dp_process_equalizer_training(dp_regs,
+								   edp_info);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:equalizer training failed\n");
 				return ret;
@@ -730,40 +752,43 @@ static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs,
+					     struct edp_device_info *edp_info)
 {
 	unsigned int ret;
 
-	exynos_dp_init_training();
+	exynos_dp_init_training(dp_regs);
 
-	ret = exynos_dp_sw_link_training(edp_info);
+	ret = exynos_dp_sw_link_training(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS)
 		printf("DP dp_sw_link_training() failed\n");
 
 	return ret;
 }
 
-static void exynos_dp_enable_scramble(unsigned int enable)
+static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs,
+				      unsigned int enable)
 {
 	unsigned char data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(DP_ENABLE);
+		exynos_dp_enable_scrambling(dp_regs, DP_ENABLE);
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_read_byte_from_dpcd(dp_regs,
+					      DPCD_TRAINING_PATTERN_SET, &data);
+		exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 	} else {
-		exynos_dp_enable_scrambling(DP_DISABLE);
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_enable_scrambling(dp_regs, DP_DISABLE);
+		exynos_dp_read_byte_from_dpcd(dp_regs,
+					      DPCD_TRAINING_PATTERN_SET, &data);
+		exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data | DPCD_SCRAMBLING_DISABLED));
 	}
 }
 
-static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
+					   struct edp_device_info *edp_info)
 {
 	unsigned int ret = 0;
 	unsigned int retry_cnt;
@@ -775,17 +800,18 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 		return -ENODEV;
 	} else {
 		/* debug slave */
-		exynos_dp_config_video_slave_mode(&edp_info->video_info);
+		exynos_dp_config_video_slave_mode(dp_regs,
+						  &edp_info->video_info);
 	}
 
-	exynos_dp_set_video_color_format(&edp_info->video_info);
+	exynos_dp_set_video_color_format(dp_regs, &edp_info->video_info);
 
 	if (edp_info->video_info.bist_mode) {
-		if (exynos_dp_config_video_bist(edp_info) != 0)
+		if (exynos_dp_config_video_bist(dp_regs, edp_info) != 0)
 			return -1;
 	}
 
-	ret = exynos_dp_get_pll_lock_status();
+	ret = exynos_dp_get_pll_lock_status(dp_regs);
 	if (ret != PLL_LOCKED) {
 		printf("DP PLL is not locked yet\n");
 		return -EIO;
@@ -794,7 +820,7 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 	if (edp_info->video_info.master_mode == 0) {
 		retry_cnt = 10;
 		while (retry_cnt) {
-			ret = exynos_dp_is_slave_video_stream_clock_on();
+			ret = exynos_dp_is_slave_video_stream_clock_on(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP stream_clock_on failed\n");
@@ -808,32 +834,34 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
+	exynos_dp_set_video_cr_mn(dp_regs, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
+	exynos_dp_set_video_timing_mode(dp_regs, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Enable video bist */
 	if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
 		edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
 		edp_info->video_info.bist_pattern != COLOR_SQUARE)
-		exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
+		exynos_dp_enable_video_bist(dp_regs,
+					    edp_info->video_info.bist_mode);
 	else
-		exynos_dp_enable_video_bist(DP_DISABLE);
+		exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(DP_DISABLE);
+	exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 
 	/* Configure video Master or Slave mode */
-	exynos_dp_enable_video_master(edp_info->video_info.master_mode);
+	exynos_dp_enable_video_master(dp_regs,
+				      edp_info->video_info.master_mode);
 
 	/* Enable video */
-	exynos_dp_start_video();
+	exynos_dp_start_video(dp_regs);
 
 	if (edp_info->video_info.master_mode == 0) {
 		retry_cnt = 100;
 		while (retry_cnt) {
-			ret = exynos_dp_is_video_stream_on();
+			ret = exynos_dp_is_video_stream_on(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Timeout of video stream\n");
@@ -907,6 +935,8 @@ unsigned int exynos_init_dp(void)
 {
 	unsigned int ret;
 	struct edp_device_info *edp_info;
+	struct exynos_dp *dp_regs;
+	int node;
 
 	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
 	if (!edp_info) {
@@ -917,39 +947,47 @@ unsigned int exynos_init_dp(void)
 	if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
 		debug("unable to parse DP DT node\n");
 
-	exynos_dp_set_base_addr();
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+				      COMPAT_SAMSUNG_EXYNOS5_DP);
+	if (node <= 0)
+		debug("exynos_dp: Can't get device node for dp\n");
+
+	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node,
+						      "reg");
+	if (dp_regs == NULL)
+		debug("Can't get the DP base address\n");
 
 	exynos_dp_disp_info(&edp_info->disp_info);
 
 	exynos_set_dp_phy(1);
 
-	ret = exynos_dp_init_dp();
+	ret = exynos_dp_init_dp(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_init_dp() failed\n");
 		return ret;
 	}
 
-	ret = exynos_dp_handle_edid(edp_info);
+	ret = exynos_dp_handle_edid(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("EDP handle_edid fail\n");
 		return ret;
 	}
 
-	ret = exynos_dp_set_link_train(edp_info);
+	ret = exynos_dp_set_link_train(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP link training fail\n");
 		return ret;
 	}
 
-	exynos_dp_enable_scramble(DP_ENABLE);
-	exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
-	exynos_dp_enable_enhanced_mode(DP_ENABLE);
+	exynos_dp_enable_scramble(dp_regs, DP_ENABLE);
+	exynos_dp_enable_rx_to_enhanced_mode(dp_regs, DP_ENABLE);
+	exynos_dp_enable_enhanced_mode(dp_regs, DP_ENABLE);
 
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
+	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
 
-	exynos_dp_init_video();
-	ret = exynos_dp_config_video(edp_info);
+	exynos_dp_init_video(dp_regs);
+	ret = exynos_dp_config_video(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("Exynos DP init failed\n");
 		return ret;
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index e417cf8..153c1c6 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -14,26 +14,13 @@
 #include <asm/arch/dp.h>
 #include <fdtdec.h>
 #include <libfdt.h>
+#include "exynos_dp_lowlevel.h"
 
 /* Declare global data pointer */
 DECLARE_GLOBAL_DATA_PTR;
 
-struct exynos_dp *dp_regs;
-
-void exynos_dp_set_base_addr(void)
-{
-	unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0)
-		debug("exynos_dp: Can't get device node for dp\n");
-
-	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-	if (dp_regs == NULL)
-		debug("Can't get the DP base address\n");
-}
-
-static void exynos_dp_enable_video_input(unsigned int enable)
+static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
+					 unsigned int enable)
 {
 	unsigned int reg;
 
@@ -49,7 +36,7 @@ static void exynos_dp_enable_video_input(unsigned int enable)
 	return;
 }
 
-void exynos_dp_enable_video_bist(unsigned int enable)
+void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	/* enable video bist */
 	unsigned int reg;
@@ -66,7 +53,7 @@ void exynos_dp_enable_video_bist(unsigned int enable)
 	return;
 }
 
-void exynos_dp_enable_video_mute(unsigned int enable)
+void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	unsigned int reg;
 
@@ -81,7 +68,7 @@ void exynos_dp_enable_video_mute(unsigned int enable)
 }
 
 
-static void exynos_dp_init_analog_param(void)
+static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -130,7 +117,7 @@ static void exynos_dp_init_analog_param(void)
 	writel(reg, &dp_regs->pll_ctl);
 }
 
-static void exynos_dp_init_interrupt(void)
+static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
 {
 	/* Set interrupt registers to initial states */
 
@@ -157,16 +144,16 @@ static void exynos_dp_init_interrupt(void)
 	writel(0x00, &dp_regs->int_sta_mask);
 }
 
-void exynos_dp_reset(void)
+void exynos_dp_reset(struct exynos_dp *dp_regs)
 {
 	unsigned int reg_func_1;
 
 	/* dp tx sw reset */
 	writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
 
-	exynos_dp_enable_video_input(DP_DISABLE);
-	exynos_dp_enable_video_bist(DP_DISABLE);
-	exynos_dp_enable_video_mute(DP_DISABLE);
+	exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
+	exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
+	exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 
 	/* software reset */
 	reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
@@ -178,13 +165,13 @@ void exynos_dp_reset(void)
 
 	mdelay(1);
 
-	exynos_dp_init_analog_param();
-	exynos_dp_init_interrupt();
+	exynos_dp_init_analog_param(dp_regs);
+	exynos_dp_init_interrupt(dp_regs);
 
 	return;
 }
 
-void exynos_dp_enable_sw_func(unsigned int enable)
+void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	unsigned int reg;
 
@@ -199,7 +186,8 @@ void exynos_dp_enable_sw_func(unsigned int enable)
 	return;
 }
 
-unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
+unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
+					     unsigned int block, u32 enable)
 {
 	unsigned int reg;
 
@@ -252,7 +240,7 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
 	return 0;
 }
 
-unsigned int exynos_dp_get_pll_lock_status(void)
+unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -264,7 +252,8 @@ unsigned int exynos_dp_get_pll_lock_status(void)
 		return PLL_UNLOCKED;
 }
 
-static void exynos_dp_set_pll_power(unsigned int enable)
+static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
+				    unsigned int enable)
 {
 	unsigned int reg;
 
@@ -277,14 +266,14 @@ static void exynos_dp_set_pll_power(unsigned int enable)
 	writel(reg, &dp_regs->pll_ctl);
 }
 
-int exynos_dp_init_analog_func(void)
+int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
 {
 	int ret = EXYNOS_DP_SUCCESS;
 	unsigned int retry_cnt = 10;
 	unsigned int reg;
 
 	/* Power On All Analog block */
-	exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
+	exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
 
 	reg = PLL_LOCK_CHG;
 	writel(reg, &dp_regs->common_int_sta1);
@@ -305,9 +294,9 @@ int exynos_dp_init_analog_func(void)
 	reg &= ~(DP_PLL_RESET);
 	writel(reg, &dp_regs->pll_ctl);
 
-	exynos_dp_set_pll_power(DP_ENABLE);
+	exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
 
-	while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
+	while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
 		mdelay(1);
 		retry_cnt--;
 		if (retry_cnt == 0) {
@@ -328,7 +317,7 @@ int exynos_dp_init_analog_func(void)
 	return ret;
 }
 
-void exynos_dp_init_hpd(void)
+void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -346,7 +335,7 @@ void exynos_dp_init_hpd(void)
 	return;
 }
 
-static inline void exynos_dp_reset_aux(void)
+static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -358,7 +347,7 @@ static inline void exynos_dp_reset_aux(void)
 	return;
 }
 
-void exynos_dp_init_aux(void)
+void exynos_dp_init_aux(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -366,7 +355,7 @@ void exynos_dp_init_aux(void)
 	reg = RPLY_RECEIV | AUX_ERR;
 	writel(reg, &dp_regs->int_sta);
 
-	exynos_dp_reset_aux();
+	exynos_dp_reset_aux(dp_regs);
 
 	/* Disable AUX transaction H/W retry */
 	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
@@ -385,7 +374,7 @@ void exynos_dp_init_aux(void)
 	return;
 }
 
-void exynos_dp_config_interrupt(void)
+void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -408,7 +397,7 @@ void exynos_dp_config_interrupt(void)
 	return;
 }
 
-unsigned int exynos_dp_get_plug_in_status(void)
+unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -419,13 +408,13 @@ unsigned int exynos_dp_get_plug_in_status(void)
 	return -1;
 }
 
-unsigned int exynos_dp_detect_hpd(void)
+unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
 {
 	int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 
 	mdelay(2);
 
-	while (exynos_dp_get_plug_in_status() != 0) {
+	while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
 		if (timeout_loop == 0)
 			return -EINVAL;
 		mdelay(10);
@@ -435,7 +424,7 @@ unsigned int exynos_dp_detect_hpd(void)
 	return EXYNOS_DP_SUCCESS;
 }
 
-unsigned int exynos_dp_start_aux_transaction(void)
+unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 	unsigned int ret = 0;
@@ -484,8 +473,9 @@ unsigned int exynos_dp_start_aux_transaction(void)
 	return EXYNOS_DP_SUCCESS;
 }
 
-unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
-				unsigned char data)
+unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
+					  unsigned int reg_addr,
+					  unsigned char data)
 {
 	unsigned int reg, ret;
 
@@ -514,7 +504,7 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
 	writel(reg, &dp_regs->aux_ch_ctl1);
 
 	/* Start AUX transaction */
-	ret = exynos_dp_start_aux_transaction();
+	ret = exynos_dp_start_aux_transaction(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP Aux transaction failed\n");
 		return ret;
@@ -523,8 +513,9 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
 	return ret;
 }
 
-unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
-		unsigned char *data)
+unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned char *data)
 {
 	unsigned int reg;
 	int retval;
@@ -550,7 +541,7 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
 	writel(reg, &dp_regs->aux_ch_ctl1);
 
 	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction();
+	retval = exynos_dp_start_aux_transaction(dp_regs);
 	if (!retval)
 		debug("DP Aux Transaction fail!\n");
 
@@ -561,9 +552,10 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
 	return retval;
 }
 
-unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned int count,
+					   unsigned char data[])
 {
 	unsigned int reg;
 	unsigned int start_offset;
@@ -610,7 +602,7 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
 			writel(reg, &dp_regs->aux_ch_ctl1);
 
 			/* Start AUX transaction */
-			ret = exynos_dp_start_aux_transaction();
+			ret = exynos_dp_start_aux_transaction(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Aux Transaction failed\n");
@@ -626,9 +618,10 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
 	return ret;
 }
 
-unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
+					    unsigned int reg_addr,
+					    unsigned int count,
+					    unsigned char data[])
 {
 	unsigned int reg;
 	unsigned int start_offset;
@@ -668,7 +661,7 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
 			writel(reg, &dp_regs->aux_ch_ctl1);
 
 			/* Start AUX transaction */
-			ret = exynos_dp_start_aux_transaction();
+			ret = exynos_dp_start_aux_transaction(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Aux Transaction failed\n");
@@ -692,8 +685,8 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
 	return ret;
 }
 
-int exynos_dp_select_i2c_device(unsigned int device_addr,
-				unsigned int reg_addr)
+int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
+				unsigned int device_addr, unsigned int reg_addr)
 {
 	unsigned int reg;
 	int retval;
@@ -717,16 +710,16 @@ int exynos_dp_select_i2c_device(unsigned int device_addr,
 	writel(reg, &dp_regs->aux_ch_ctl1);
 
 	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction();
+	retval = exynos_dp_start_aux_transaction(dp_regs);
 	if (retval != 0)
 		printf("%s: DP Aux Transaction fail!\n", __func__);
 
 	return retval;
 }
 
-int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
+				 unsigned int device_addr,
+				 unsigned int reg_addr, unsigned int *data)
 {
 	unsigned int reg;
 	int i;
@@ -738,7 +731,8 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 		writel(reg, &dp_regs->buffer_data_ctl);
 
 		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
+		retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
+						     reg_addr);
 		if (retval != 0) {
 			printf("DP Select EDID device fail. retry !\n");
 			continue;
@@ -754,7 +748,7 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 		writel(reg, &dp_regs->aux_ch_ctl1);
 
 		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction();
+		retval = exynos_dp_start_aux_transaction(dp_regs);
 		if (retval != EXYNOS_DP_SUCCESS)
 			printf("%s: DP Aux Transaction fail!\n", __func__);
 	}
@@ -766,8 +760,10 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 	return retval;
 }
 
-int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int count, unsigned char edid[])
+int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
+				  unsigned int device_addr,
+				  unsigned int reg_addr, unsigned int count,
+				  unsigned char edid[])
 {
 	unsigned int reg;
 	unsigned int i, j;
@@ -791,9 +787,8 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 			 * request without sending addres
 			 */
 			if (!defer)
-				retval =
-					exynos_dp_select_i2c_device(device_addr,
-							reg_addr + i);
+				retval = exynos_dp_select_i2c_device(
+					dp_regs, device_addr, reg_addr + i);
 			else
 				defer = 0;
 
@@ -809,7 +804,8 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 				writel(reg, &dp_regs->aux_ch_ctl1);
 
 				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction();
+				retval = exynos_dp_start_aux_transaction(
+							dp_regs);
 				if (retval == 0)
 					break;
 				else
@@ -834,7 +830,7 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 	return retval;
 }
 
-void exynos_dp_reset_macro(void)
+void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -849,7 +845,8 @@ void exynos_dp_reset_macro(void)
 	writel(reg, &dp_regs->phy_test);
 }
 
-void exynos_dp_set_link_bandwidth(unsigned char bwtype)
+void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
+				  unsigned char bwtype)
 {
 	unsigned int reg;
 
@@ -860,7 +857,7 @@ void exynos_dp_set_link_bandwidth(unsigned char bwtype)
 		writel(reg, &dp_regs->link_bw_set);
 }
 
-unsigned char exynos_dp_get_link_bandwidth(void)
+unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
 {
 	unsigned char ret;
 	unsigned int reg;
@@ -871,7 +868,7 @@ unsigned char exynos_dp_get_link_bandwidth(void)
 	return ret;
 }
 
-void exynos_dp_set_lane_count(unsigned char count)
+void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
 {
 	unsigned int reg;
 
@@ -882,7 +879,7 @@ void exynos_dp_set_lane_count(unsigned char count)
 		writel(reg, &dp_regs->lane_count_set);
 }
 
-unsigned int exynos_dp_get_lane_count(void)
+unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -891,7 +888,8 @@ unsigned int exynos_dp_get_lane_count(void)
 	return reg;
 }
 
-unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
+unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+					       unsigned char lanecnt)
 {
 	unsigned int reg_list[DP_LANE_CNT_4] = {
 		(unsigned int)&dp_regs->ln0_link_training_ctl,
@@ -903,8 +901,9 @@ unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
 	return readl(reg_list[lanecnt]);
 }
 
-void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
-		unsigned char lanecnt)
+void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+				      unsigned char request_val,
+				      unsigned char lanecnt)
 {
 	unsigned int reg_list[DP_LANE_CNT_4] = {
 		(unsigned int)&dp_regs->ln0_link_training_ctl,
@@ -916,7 +915,8 @@ void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
 	writel(request_val, reg_list[lanecnt]);
 }
 
-void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
+void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
+				     unsigned int level, unsigned char lanecnt)
 {
 	unsigned char i;
 	unsigned int reg;
@@ -939,7 +939,8 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
 	}
 }
 
-void exynos_dp_set_training_pattern(unsigned int pattern)
+void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
+				    unsigned int pattern)
 {
 	unsigned int reg = 0;
 
@@ -967,7 +968,8 @@ void exynos_dp_set_training_pattern(unsigned int pattern)
 	writel(reg, &dp_regs->training_ptn_set);
 }
 
-void exynos_dp_enable_enhanced_mode(unsigned char enable)
+void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
+				    unsigned char enable)
 {
 	unsigned int reg;
 
@@ -980,7 +982,7 @@ void exynos_dp_enable_enhanced_mode(unsigned char enable)
 	writel(reg, &dp_regs->sys_ctl4);
 }
 
-void exynos_dp_enable_scrambling(unsigned int enable)
+void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	unsigned int reg;
 
@@ -993,7 +995,7 @@ void exynos_dp_enable_scrambling(unsigned int enable)
 	writel(reg, &dp_regs->training_ptn_set);
 }
 
-int exynos_dp_init_video(void)
+int exynos_dp_init_video(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -1008,7 +1010,8 @@ int exynos_dp_init_video(void)
 	return 0;
 }
 
-void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
+void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
+				       struct edp_video_info *video_info)
 {
 	unsigned int reg;
 
@@ -1041,7 +1044,8 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
 	writel(reg, &dp_regs->soc_general_ctl);
 }
 
-void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
+void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
+				      struct edp_video_info *video_info)
 {
 	unsigned int reg;
 
@@ -1061,7 +1065,8 @@ void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
 	writel(reg, &dp_regs->video_ctl3);
 }
 
-int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
+int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
+				struct edp_device_info *edp_info)
 {
 	unsigned int reg;
 	unsigned int bist_type = 0;
@@ -1151,7 +1156,7 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
 	return 0;
 }
 
-unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
+unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -1169,8 +1174,8 @@ unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
 	return EXYNOS_DP_SUCCESS;
 }
 
-void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
-		unsigned int n_value)
+void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
+			       unsigned int m_value, unsigned int n_value)
 {
 	unsigned int reg;
 
@@ -1198,7 +1203,8 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
 	}
 }
 
-void exynos_dp_set_video_timing_mode(unsigned int type)
+void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
+				     unsigned int type)
 {
 	unsigned int reg;
 
@@ -1211,7 +1217,8 @@ void exynos_dp_set_video_timing_mode(unsigned int type)
 	writel(reg, &dp_regs->video_ctl10);
 }
 
-void exynos_dp_enable_video_master(unsigned int enable)
+void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
+				   unsigned int enable)
 {
 	unsigned int reg;
 
@@ -1227,7 +1234,7 @@ void exynos_dp_enable_video_master(unsigned int enable)
 	writel(reg, &dp_regs->soc_general_ctl);
 }
 
-void exynos_dp_start_video(void)
+void exynos_dp_start_video(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -1237,7 +1244,7 @@ void exynos_dp_start_video(void)
 	writel(reg, &dp_regs->video_ctl1);
 }
 
-unsigned int exynos_dp_is_video_stream_on(void)
+unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.h b/drivers/video/exynos/exynos_dp_lowlevel.h
index 8651681..85459b5 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.h
+++ b/drivers/video/exynos/exynos_dp_lowlevel.h
@@ -9,60 +9,81 @@
 #ifndef _EXYNOS_EDP_LOWLEVEL_H
 #define _EXYNOS_EDP_LOWLEVEL_H
 
-void exynos_dp_enable_video_bist(unsigned int enable);
-void exynos_dp_enable_video_mute(unsigned int enable);
-void exynos_dp_reset(void);
-void exynos_dp_enable_sw_func(unsigned int enable);
-unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
-unsigned int exynos_dp_get_pll_lock_status(void);
-int exynos_dp_init_analog_func(void);
-void exynos_dp_init_hpd(void);
-void exynos_dp_init_aux(void);
-void exynos_dp_config_interrupt(void);
-unsigned int exynos_dp_get_plug_in_status(void);
-unsigned int exynos_dp_detect_hpd(void);
-unsigned int exynos_dp_start_aux_transaction(void);
-unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
-				unsigned char data);
-unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
-		unsigned char *data);
-unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
-		unsigned int count,
-		unsigned char data[]);
-unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
-		unsigned int count,
-		unsigned char data[]);
-int exynos_dp_select_i2c_device( unsigned int device_addr,
-		unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int count,
-		unsigned char edid[]);
-void exynos_dp_reset_macro(void);
-void exynos_dp_set_link_bandwidth(unsigned char bwtype);
-unsigned char exynos_dp_get_link_bandwidth(void);
-void exynos_dp_set_lane_count(unsigned char count);
-unsigned int exynos_dp_get_lane_count(void);
-unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt);
-void exynos_dp_set_lane_pre_emphasis(unsigned int level,
-		unsigned char lanecnt);
-void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
-		unsigned char lanecnt);
-void exynos_dp_set_training_pattern(unsigned int pattern);
-void exynos_dp_enable_enhanced_mode(unsigned char enable);
-void exynos_dp_enable_scrambling(unsigned int enable);
-int exynos_dp_init_video(void);
-void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
-void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
-int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
-unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
-void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
-		unsigned int n_value);
-void exynos_dp_set_video_timing_mode(unsigned int type);
-void exynos_dp_enable_video_master(unsigned int enable);
-void exynos_dp_start_video(void);
-unsigned int exynos_dp_is_video_stream_on(void);
-void exynos_dp_set_base_addr(void);
+void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs,
+				 unsigned int enable);
+void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs,
+				 unsigned int enable);
+void exynos_dp_reset(struct exynos_dp *dp_regs);
+void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable);
+unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
+					     unsigned int block, u32 enable);
+unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs);
+int exynos_dp_init_analog_func(struct exynos_dp *dp_regs);
+void exynos_dp_init_hpd(struct exynos_dp *dp_regs);
+void exynos_dp_init_aux(struct exynos_dp *dp_regs);
+void exynos_dp_config_interrupt(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
+					  unsigned int reg_addr,
+					  unsigned char data);
+unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned char *data);
+unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned int count,
+					   unsigned char data[]);
+unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
+					    unsigned int reg_addr,
+					    unsigned int count,
+					    unsigned char data[]);
+int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
+				 unsigned int device_addr,
+				 unsigned int reg_addr, unsigned int *data);
+int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
+				  unsigned int device_addr,
+				  unsigned int reg_addr, unsigned int count,
+				  unsigned char edid[]);
+void exynos_dp_reset_macro(struct exynos_dp *dp_regs);
+void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
+				  unsigned char bwtype);
+unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs);
+void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count);
+unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs);
+unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+					       unsigned char lanecnt);
+void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
+				     unsigned int level, unsigned char lanecnt);
+void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+				      unsigned char request_val,
+				      unsigned char lanecnt);
+void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
+				    unsigned int pattern);
+void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
+				    unsigned char enable);
+void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs,
+				 unsigned int enable);
+int exynos_dp_init_video(struct exynos_dp *dp_regs);
+void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
+				       struct edp_video_info *video_info);
+void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
+				      struct edp_video_info *video_info);
+int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
+				struct edp_device_info *edp_info);
+unsigned int exynos_dp_is_slave_video_stream_clock_on(
+					struct exynos_dp *dp_regs);
+void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
+			       unsigned int m_value, unsigned int n_value);
+void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
+				     unsigned int type);
+void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
+				   unsigned int enable);
+void exynos_dp_start_video(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs);
 
 #endif /* _EXYNOS_DP_LOWLEVEL_H */
-- 
cgit v0.10.2


From b04135c998b88b0d7c1f21fef64219c508dfbcad Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:45 -0700
Subject: exynos: video: Move dsim_config_dt into a function

In preparation for making this a parameter, move it into the function
that sets it up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index 5001e16..fd96382 100644
--- a/drivers/video/exynos/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -28,7 +28,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct exynos_platform_mipi_dsim *dsim_pd;
-static struct mipi_dsim_config dsim_config_dt;
 static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
 
@@ -247,7 +246,7 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
 	dsim_pd = pd;
 }
 
-int exynos_dsim_config_parse_dt(const void *blob)
+int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 {
 	int node;
 
@@ -257,47 +256,47 @@ int exynos_dsim_config_parse_dt(const void *blob)
 		return -ENODEV;
 	}
 
-	dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+	dt->e_interface = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-interface", 0);
 
-	dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+	dt->e_virtual_ch = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-virtual-ch", 0);
 
-	dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+	dt->e_pixel_format = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-pixel-format", 0);
 
-	dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+	dt->e_burst_mode = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-burst-mode", 0);
 
-	dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+	dt->e_no_data_lane = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-no-data-lane", 0);
 
-	dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+	dt->e_byte_clk = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-byte-clk", 0);
 
-	dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+	dt->hfp = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-hfp", 0);
 
-	dsim_config_dt.p = fdtdec_get_int(blob, node,
+	dt->p = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-p", 0);
-	dsim_config_dt.m = fdtdec_get_int(blob, node,
+	dt->m = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-m", 0);
-	dsim_config_dt.s = fdtdec_get_int(blob, node,
+	dt->s = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-s", 0);
 
-	dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+	dt->pll_stable_time = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-pll-stable-time", 0);
 
-	dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+	dt->esc_clk = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-esc-clk", 0);
 
-	dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+	dt->stop_holding_cnt = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-stop-holding-cnt", 0);
 
-	dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+	dt->bta_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-bta-timeout", 0);
 
-	dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+	dt->rx_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-rx-timeout", 0);
 
 	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
@@ -317,7 +316,9 @@ int exynos_dsim_config_parse_dt(const void *blob)
 
 void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
-	if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+	struct mipi_dsim_config dsim_config_dt;
+
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt))
 		debug("Can't get proper dsim config.\n");
 
 	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
-- 
cgit v0.10.2


From 652d15c06e65ea910bada28925b37483b2a1a0d6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:46 -0700
Subject: exynos: video: Move struct exynos_platform_mipi_dsim into vidinfo

Put the pointer to this structure in struct vidinfo so that we can
reference it without it being global.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/mipi_dsim.h b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
index a77b5c8..df68186 100644
--- a/arch/arm/mach-exynos/include/mach/mipi_dsim.h
+++ b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
@@ -347,9 +347,10 @@ struct mipi_dsim_lcd_driver {
 };
 
 #ifdef CONFIG_EXYNOS_MIPI_DSIM
-int exynos_mipi_dsi_init(void);
+int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd);
 #else
-static inline int exynos_mipi_dsi_init(void)
+static inline int exynos_mipi_dsi_init(
+			struct exynos_platform_mipi_dsim *dsim_pd)
 {
 	return 0;
 }
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index abc6091..22b9723 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -128,7 +128,7 @@ static void lcd_panel_on(struct vidinfo *vid)
 	exynos_enable_ldo(1);
 
 	if (vid->mipi_enabled)
-		exynos_mipi_dsi_init();
+		exynos_mipi_dsi_init(panel_info.dsim_platform_data_dt);
 }
 
 int exynos_lcd_early_init(const void *blob)
diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index fd96382..b39858a 100644
--- a/drivers/video/exynos/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct exynos_platform_mipi_dsim *dsim_pd;
-static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
 
 struct mipi_dsim_ddi {
@@ -175,7 +173,7 @@ static struct mipi_dsim_master_ops master_ops = {
 	.clear_dsim_frame_done		= exynos_mipi_dsi_clear_frame_done,
 };
 
-int exynos_mipi_dsi_init(void)
+int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd)
 {
 	struct mipi_dsim_device *dsim;
 	struct mipi_dsim_config *dsim_config;
@@ -236,16 +234,6 @@ int exynos_mipi_dsi_init(void)
 	return 0;
 }
 
-void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
-{
-	if (pd == NULL) {
-		debug("pd is NULL\n");
-		return;
-	}
-
-	dsim_pd = pd;
-}
-
 int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 {
 	int node;
@@ -316,7 +304,8 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 
 void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
-	struct mipi_dsim_config dsim_config_dt;
+	static struct mipi_dsim_config dsim_config_dt;
+	static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 
 	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt))
 		debug("Can't get proper dsim config.\n");
@@ -330,5 +319,5 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 	mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
 	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
 
-	dsim_pd = &dsim_platform_data_dt;
+	vid->dsim_platform_data_dt = &dsim_platform_data_dt;
 }
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
index 1f6c6c7..0aa0fc7 100644
--- a/include/exynos_lcd.h
+++ b/include/exynos_lcd.h
@@ -76,6 +76,7 @@ typedef struct vidinfo {
 
 	unsigned int dual_lcd_enabled;
 	struct exynos_fb *fimd_ctrl;
+	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
 } vidinfo_t;
 
 #endif
-- 
cgit v0.10.2


From 37ea446b9d7942c0deb5833fede6eb7cabd5bc6d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:47 -0700
Subject: exynos: video: Move mipi_lcd_device_dt into a function

In preparation for making this a parameter, move it into the function
that sets it up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/mipi_dsim.h b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
index df68186..43b5c01 100644
--- a/arch/arm/mach-exynos/include/mach/mipi_dsim.h
+++ b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
@@ -320,7 +320,7 @@ struct mipi_dsim_lcd_device {
 	int			reverse_panel;
 
 	struct mipi_dsim_device *master;
-	void			*platform_data;
+	struct exynos_platform_mipi_dsim *platform_data;
 };
 
 /*
diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index b39858a..a5d9b59 100644
--- a/drivers/video/exynos/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
-
 struct mipi_dsim_ddi {
 	int				bus_id;
 	struct list_head		list;
@@ -234,7 +232,8 @@ int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd)
 	return 0;
 }
 
-int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
+int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt,
+				struct mipi_dsim_lcd_device *lcd_dt)
 {
 	int node;
 
@@ -287,16 +286,16 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 	dt->rx_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-rx-timeout", 0);
 
-	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+	lcd_dt->name = fdtdec_get_config_string(blob,
 				"samsung,dsim-device-name");
 
-	mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+	lcd_dt->id = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-id", 0);
 
-	mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+	lcd_dt->bus_id = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-bus_id", 0);
 
-	mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+	lcd_dt->reverse_panel = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-reverse-panel", 0);
 
 	return 0;
@@ -306,8 +305,10 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
 	static struct mipi_dsim_config dsim_config_dt;
 	static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+	static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
 
-	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt))
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt,
+					&mipi_lcd_device_dt))
 		debug("Can't get proper dsim config.\n");
 
 	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
-- 
cgit v0.10.2


From 0c84358cb240953b467034a52fcc2f459ba4029b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:48 -0700
Subject: exynos: video: Combine LCD driver into one file

At present exynos_fimd.c is the controller and exynos_fb.c is the U-Boot
LCD interface. With driver model we want these in one file, so join them
in preparation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/Makefile b/drivers/video/exynos/Makefile
index d4bdf32..001a80f 100644
--- a/drivers/video/exynos/Makefile
+++ b/drivers/video/exynos/Makefile
@@ -6,7 +6,7 @@
 #
 
 obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
-obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
+obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o
 obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
 				exynos_mipi_dsi_lowlevel.o
 obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 22b9723..e13d35a 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -9,6 +9,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <div64.h>
 #include <lcd.h>
 #include <fdtdec.h>
 #include <libfdt.h>
@@ -34,6 +35,391 @@ struct vidinfo panel_info  = {
 	.vl_col = -1,
 };
 
+static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	if (enabled) {
+		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
+			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
+
+		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
+		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
+			EXYNOS_DUALRGB_MAIN_CNT(0);
+	}
+
+	writel(cfg, &fimd_ctrl->dualrgb);
+}
+
+static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
+				      unsigned int enabled)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	if (enabled)
+		cfg = EXYNOS_DP_CLK_ENABLE;
+
+	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
+}
+
+static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	/* set window control */
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
+		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
+		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
+		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
+
+	/* DATAPATH is DMA */
+	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
+
+	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+
+	/* dma burst is 16 */
+	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
+
+	switch (pvid->vl_bpix) {
+	case 4:
+		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+		break;
+	default:
+		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+		break;
+	}
+
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	/* set window position to x=0, y=0*/
+	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
+			EXYNOS_VIDOSD(win_id));
+
+	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
+		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
+		EXYNOS_VIDOSD_RIGHT_X_E(1) |
+		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
+
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
+			EXYNOS_VIDOSD(win_id));
+
+	/* set window size for window0*/
+	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
+			EXYNOS_VIDOSD(win_id));
+}
+
+static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
+					   unsigned int win_id,
+					   ulong lcd_base_addr)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned long start_addr, end_addr;
+
+	start_addr = lcd_base_addr;
+	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
+				pvid->vl_row);
+
+	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+}
+
+static void exynos_fimd_set_clock(struct vidinfo *pvid)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0, div = 0, remainder, remainder_div;
+	unsigned long pixel_clock;
+	unsigned long long src_clock;
+
+	if (pvid->dual_lcd_enabled) {
+		pixel_clock = pvid->vl_freq *
+				(pvid->vl_hspw + pvid->vl_hfpd +
+				 pvid->vl_hbpd + pvid->vl_col / 2) *
+				(pvid->vl_vspw + pvid->vl_vfpd +
+				 pvid->vl_vbpd + pvid->vl_row);
+	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
+		pixel_clock = pvid->vl_freq *
+				pvid->vl_width * pvid->vl_height *
+				(pvid->cs_setup + pvid->wr_setup +
+				 pvid->wr_act + pvid->wr_hold + 1);
+	} else {
+		pixel_clock = pvid->vl_freq *
+				(pvid->vl_hspw + pvid->vl_hfpd +
+				 pvid->vl_hbpd + pvid->vl_col) *
+				(pvid->vl_vspw + pvid->vl_vfpd +
+				 pvid->vl_vbpd + pvid->vl_row);
+	}
+
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
+		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
+		EXYNOS_VIDCON0_CLKDIR_MASK);
+	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
+		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
+
+	src_clock = (unsigned long long) get_lcd_clk();
+
+	/* get quotient and remainder. */
+	remainder = do_div(src_clock, pixel_clock);
+	div = src_clock;
+
+	remainder *= 10;
+	remainder_div = remainder / pixel_clock;
+
+	/* round about one places of decimals. */
+	if (remainder_div >= 5)
+		div++;
+
+	/* in case of dual lcd mode. */
+	if (pvid->dual_lcd_enabled)
+		div--;
+
+	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_set_trigger(struct vidinfo *pvid)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	cfg = readl(&fimd_ctrl->trigcon);
+
+	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
+
+	writel(cfg, &fimd_ctrl->trigcon);
+}
+
+int exynos_is_i80_frame_done(struct vidinfo *pvid)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+	int status;
+
+	cfg = readl(&fimd_ctrl->trigcon);
+
+	/* frame done func is valid only when TRIMODE[0] is set to 1. */
+	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
+			EXYNOS_I80STATUS_TRIG_DONE;
+
+	return status;
+}
+
+static void exynos_fimd_lcd_on(struct vidinfo *pvid)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	/* display on */
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	/* enable window */
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&fimd_ctrl->winshmap);
+	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
+	writel(cfg, &fimd_ctrl->winshmap);
+}
+
+void exynos_fimd_lcd_off(struct vidinfo *pvid)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id)
+{
+	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	unsigned int cfg = 0;
+
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&fimd_ctrl->winshmap);
+	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
+	writel(cfg, &fimd_ctrl->winshmap);
+}
+
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+	u32 *sysmmufimd;
+	unsigned int node;
+	int node_list[2];
+	int count;
+	int i;
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+				COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+	for (i = 0; i < count; i++) {
+		node = node_list[i];
+		if (node <= 0) {
+			debug("Can't get device node for fimd sysmmu\n");
+			return;
+		}
+
+		sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+		if (!sysmmufimd) {
+			debug("Can't get base address for sysmmu fimdm0");
+			return;
+		}
+
+		writel(0x0, sysmmufimd);
+	}
+}
+
+void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address)
+{
+	struct exynos_fb *fimd_ctrl;
+	unsigned int cfg = 0, rgb_mode;
+	unsigned int offset;
+	unsigned int node;
+
+	node = fdtdec_next_compatible(gd->fdt_blob,
+					0, COMPAT_SAMSUNG_EXYNOS_FIMD);
+	if (node <= 0)
+		debug("exynos_fb: Can't get device node for fimd\n");
+
+	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
+							"reg");
+	if (fimd_ctrl == NULL)
+		debug("Can't get the FIMD base address\n");
+	pvid->fimd_ctrl = fimd_ctrl;
+
+	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+		exynos_fimd_disable_sysmmu();
+
+	offset = exynos_fimd_get_base_offset();
+
+	rgb_mode = pvid->rgb_mode;
+
+	if (pvid->interface_mode == FIMD_RGB_INTERFACE) {
+		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
+		writel(cfg, &fimd_ctrl->vidcon0);
+
+		cfg = readl(&fimd_ctrl->vidcon2);
+		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
+		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
+		writel(cfg, &fimd_ctrl->vidcon2);
+
+		/* set polarity */
+		cfg = 0;
+		if (!pvid->vl_clkp)
+			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
+		if (!pvid->vl_hsp)
+			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
+		if (!pvid->vl_vsp)
+			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
+		if (!pvid->vl_dp)
+			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
+
+		writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
+
+		/* set timing */
+		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
+		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
+
+		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
+
+		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
+
+		/* set lcd size */
+		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
+			EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
+
+		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
+	}
+
+	/* set display mode */
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
+	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
+	writel(cfg, &fimd_ctrl->vidcon0);
+
+	/* set par */
+	exynos_fimd_set_par(pvid, pvid->win_id);
+
+	/* set memory address */
+	exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address);
+
+	/* set buffer size */
+	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col *
+			NBITS(pvid->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col *
+			NBITS(pvid->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_OFFSIZE(0) |
+		EXYNOS_VIDADDR_OFFSIZE_E(0);
+
+	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
+					EXYNOS_BUFFER_SIZE(pvid->win_id));
+
+	/* set clock */
+	exynos_fimd_set_clock(pvid);
+
+	/* set rgb mode to dual lcd. */
+	exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled);
+
+	/* display on */
+	exynos_fimd_lcd_on(pvid);
+
+	/* window on */
+	exynos_fimd_window_on(pvid, pvid->win_id);
+
+	exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
+}
+
+unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid)
+{
+	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
+}
+
 ushort *configuration_get_cmap(void)
 {
 #if defined(CONFIG_LCD_LOGO)
diff --git a/drivers/video/exynos/exynos_fimd.c b/drivers/video/exynos/exynos_fimd.c
deleted file mode 100644
index 039d4c5..0000000
--- a/drivers/video/exynos/exynos_fimd.c
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <lcd.h>
-#include <div64.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include "exynos_fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	if (enabled) {
-		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
-			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
-
-		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
-		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
-			EXYNOS_DUALRGB_MAIN_CNT(0);
-	}
-
-	writel(cfg, &fimd_ctrl->dualrgb);
-}
-
-static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
-				      unsigned int enabled)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	if (enabled)
-		cfg = EXYNOS_DP_CLK_ENABLE;
-
-	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
-}
-
-static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	/* set window control */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
-		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
-		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
-		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
-
-	/* DATAPATH is DMA */
-	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
-
-	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
-
-	/* dma burst is 16 */
-	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
-
-	switch (pvid->vl_bpix) {
-	case 4:
-		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
-		break;
-	default:
-		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-		break;
-	}
-
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	/* set window position to x=0, y=0*/
-	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
-			EXYNOS_VIDOSD(win_id));
-
-	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
-		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
-		EXYNOS_VIDOSD_RIGHT_X_E(1) |
-		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
-
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
-			EXYNOS_VIDOSD(win_id));
-
-	/* set window size for window0*/
-	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
-			EXYNOS_VIDOSD(win_id));
-}
-
-static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
-					   unsigned int win_id,
-					   ulong lcd_base_addr)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned long start_addr, end_addr;
-
-	start_addr = lcd_base_addr;
-	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
-				pvid->vl_row);
-
-	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
-			EXYNOS_BUFFER_OFFSET(win_id));
-	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
-			EXYNOS_BUFFER_OFFSET(win_id));
-}
-
-static void exynos_fimd_set_clock(struct vidinfo *pvid)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0, div = 0, remainder, remainder_div;
-	unsigned long pixel_clock;
-	unsigned long long src_clock;
-
-	if (pvid->dual_lcd_enabled) {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col / 2) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
-		pixel_clock = pvid->vl_freq *
-				pvid->vl_width * pvid->vl_height *
-				(pvid->cs_setup + pvid->wr_setup +
-				 pvid->wr_act + pvid->wr_hold + 1);
-	} else {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	}
-
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
-		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
-		EXYNOS_VIDCON0_CLKDIR_MASK);
-	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
-		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
-
-	src_clock = (unsigned long long) get_lcd_clk();
-
-	/* get quotient and remainder. */
-	remainder = do_div(src_clock, pixel_clock);
-	div = src_clock;
-
-	remainder *= 10;
-	remainder_div = remainder / pixel_clock;
-
-	/* round about one places of decimals. */
-	if (remainder_div >= 5)
-		div++;
-
-	/* in case of dual lcd mode. */
-	if (pvid->dual_lcd_enabled)
-		div--;
-
-	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-void exynos_set_trigger(struct vidinfo *pvid)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	cfg = readl(&fimd_ctrl->trigcon);
-
-	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
-
-	writel(cfg, &fimd_ctrl->trigcon);
-}
-
-int exynos_is_i80_frame_done(struct vidinfo *pvid)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-	int status;
-
-	cfg = readl(&fimd_ctrl->trigcon);
-
-	/* frame done func is valid only when TRIMODE[0] is set to 1. */
-	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
-			EXYNOS_I80STATUS_TRIG_DONE;
-
-	return status;
-}
-
-static void exynos_fimd_lcd_on(struct vidinfo *pvid)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	/* display on */
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	/* enable window */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg = readl(&fimd_ctrl->winshmap);
-	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
-}
-
-void exynos_fimd_lcd_off(struct vidinfo *pvid)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id)
-{
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
-	unsigned int cfg = 0;
-
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg = readl(&fimd_ctrl->winshmap);
-	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
-}
-
-/*
-* The reset value for FIMD SYSMMU register MMU_CTRL is 3
-* on Exynos5420 and newer versions.
-* This means FIMD SYSMMU is on by default on Exynos5420
-* and newer versions.
-* Since in u-boot we don't use SYSMMU, we should disable
-* those FIMD SYSMMU.
-* Note that there are 2 SYSMMU for FIMD: m0 and m1.
-* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
-* We disable both of them here.
-*/
-void exynos_fimd_disable_sysmmu(void)
-{
-	u32 *sysmmufimd;
-	unsigned int node;
-	int node_list[2];
-	int count;
-	int i;
-
-	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
-				COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
-	for (i = 0; i < count; i++) {
-		node = node_list[i];
-		if (node <= 0) {
-			debug("Can't get device node for fimd sysmmu\n");
-			return;
-		}
-
-		sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
-		if (!sysmmufimd) {
-			debug("Can't get base address for sysmmu fimdm0");
-			return;
-		}
-
-		writel(0x0, sysmmufimd);
-	}
-}
-
-void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address)
-{
-	struct exynos_fb *fimd_ctrl;
-	unsigned int cfg = 0, rgb_mode;
-	unsigned int offset;
-	unsigned int node;
-
-	node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0)
-		debug("exynos_fb: Can't get device node for fimd\n");
-
-	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
-							"reg");
-	if (fimd_ctrl == NULL)
-		debug("Can't get the FIMD base address\n");
-	pvid->fimd_ctrl = fimd_ctrl;
-
-	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
-		exynos_fimd_disable_sysmmu();
-
-	offset = exynos_fimd_get_base_offset();
-
-	rgb_mode = pvid->rgb_mode;
-
-	if (pvid->interface_mode == FIMD_RGB_INTERFACE) {
-		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
-		writel(cfg, &fimd_ctrl->vidcon0);
-
-		cfg = readl(&fimd_ctrl->vidcon2);
-		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
-			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
-			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
-		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
-		writel(cfg, &fimd_ctrl->vidcon2);
-
-		/* set polarity */
-		cfg = 0;
-		if (!pvid->vl_clkp)
-			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
-		if (!pvid->vl_hsp)
-			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
-		if (!pvid->vl_vsp)
-			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
-		if (!pvid->vl_dp)
-			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
-
-		/* set timing */
-		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
-
-		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
-
-		/* set lcd size */
-		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
-			EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
-	}
-
-	/* set display mode */
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
-	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
-	writel(cfg, &fimd_ctrl->vidcon0);
-
-	/* set par */
-	exynos_fimd_set_par(pvid, pvid->win_id);
-
-	/* set memory address */
-	exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address);
-
-	/* set buffer size */
-	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_OFFSIZE(0) |
-		EXYNOS_VIDADDR_OFFSIZE_E(0);
-
-	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
-					EXYNOS_BUFFER_SIZE(pvid->win_id));
-
-	/* set clock */
-	exynos_fimd_set_clock(pvid);
-
-	/* set rgb mode to dual lcd. */
-	exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled);
-
-	/* display on */
-	exynos_fimd_lcd_on(pvid);
-
-	/* window on */
-	exynos_fimd_window_on(pvid, pvid->win_id);
-
-	exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
-}
-
-unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid)
-{
-	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
-}
-- 
cgit v0.10.2


From 5c2dd4cd7a41ec971a23eec9e993717e5aed8744 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:49 -0700
Subject: exynos: pwm: Add a driver for the exynos5 PWM

This driver supports the standard PWM API. There are 5 PWMs. Four are used
normally and the last is normally used as a timer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c
index 949abb1..b63036c 100644
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -12,6 +12,9 @@
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
+
+/* Use the old PWM interface for now */
+#undef CONFIG_DM_PWM
 #include <pwm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6f0d61e..37ea2b8 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,15 @@ config DM_PWM
 	  frequency/period can be controlled along with the proportion of that
 	  time that the signal is high.
 
+config PWM_EXYNOS
+	bool "Enable support for the Exynos PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It
+	  supports a programmable period and duty cycle. A 32-bit counter is
+	  used. It provides 5 channels which can be independently
+	  programmed. Channel 4 (the last) is normally used as a timer.
+
 config PWM_ROCKCHIP
 	bool "Enable support for the Rockchip PWM"
 	depends on DM_PWM
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index fd414b1..af39347 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
 obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
 ifdef CONFIG_DM_PWM
 obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
+obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
 endif
diff --git a/drivers/pwm/exynos_pwm.c b/drivers/pwm/exynos_pwm.c
new file mode 100644
index 0000000..a0edafc
--- /dev/null
+++ b/drivers/pwm/exynos_pwm.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct exynos_pwm_priv {
+	struct s5p_timer *regs;
+};
+
+static int exynos_pwm_set_config(struct udevice *dev, uint channel,
+				uint period_ns, uint duty_ns)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+	unsigned int offset, prescaler;
+	uint div = 4, rate, rate_ns;
+	u32 val;
+	u32 tcnt, tcmp, tcon;
+
+	if (channel >= 5)
+		return -EINVAL;
+	debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",
+	      __func__, dev->name, channel, period_ns, duty_ns);
+
+	val = readl(&regs->tcfg0);
+	prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;
+	div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;
+
+	rate = get_pwm_clk() / ((prescaler + 1) * (1 << div));
+	debug("%s: pwm_clk %lu, rate %u\n", __func__, get_pwm_clk(), rate);
+
+	if (channel < 4) {
+		rate_ns = 1000000000 / rate;
+		tcnt = period_ns / rate_ns;
+		tcmp = duty_ns / rate_ns;
+		debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
+		offset = channel * 3;
+		writel(tcnt, &regs->tcntb0 + offset);
+		writel(tcmp, &regs->tcmpb0 + offset);
+	}
+
+	tcon = readl(&regs->tcon);
+	tcon |= TCON_UPDATE(channel);
+	if (channel < 4)
+		tcon |= TCON_AUTO_RELOAD(channel);
+	else
+		tcon |= TCON4_AUTO_RELOAD;
+	writel(tcon, &regs->tcon);
+
+	tcon &= ~TCON_UPDATE(channel);
+	writel(tcon, &regs->tcon);
+
+	return 0;
+}
+
+static int exynos_pwm_set_enable(struct udevice *dev, uint channel,
+				 bool enable)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+	u32 mask;
+
+	if (channel >= 4)
+		return -EINVAL;
+	debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
+	mask = TCON_START(channel);
+	clrsetbits_le32(&regs->tcon, mask, enable ? mask : 0);
+
+	return 0;
+}
+
+static int exynos_pwm_probe(struct udevice *dev)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+
+	writel(PRESCALER_0 | PRESCALER_1 << 8, &regs->tcfg0);
+
+	return 0;
+}
+
+static int exynos_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct s5p_timer *)dev_get_addr(dev);
+
+	return 0;
+}
+
+static const struct pwm_ops exynos_pwm_ops = {
+	.set_config	= exynos_pwm_set_config,
+	.set_enable	= exynos_pwm_set_enable,
+};
+
+static const struct udevice_id exynos_channels[] = {
+	{ .compatible = "samsung,exynos4210-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_pwm) = {
+	.name	= "exynos_pwm",
+	.id	= UCLASS_PWM,
+	.of_match = exynos_channels,
+	.ops	= &exynos_pwm_ops,
+	.probe	= exynos_pwm_probe,
+	.ofdata_to_platdata	= exynos_pwm_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_pwm_priv),
+};
-- 
cgit v0.10.2


From 21c561b7c906a05700534a4e420277e6c6012efb Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:50 -0700
Subject: video: Add an enum for active low/high

This is used for video signals in some drivers so provide a standard way
of representing it in an enum.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/include/video.h b/include/video.h
index c434bc7..0d5bd21 100644
--- a/include/video.h
+++ b/include/video.h
@@ -23,6 +23,11 @@ struct video_uc_platdata {
 	ulong base;
 };
 
+enum video_polarity {
+	VIDEO_ACTIVE_HIGH,	/* Pins are active high */
+	VIDEO_ACTIVE_LOW,	/* Pins are active low */
+};
+
 /*
  * Bits per pixel selector. Each value n is such that the bits-per-pixel is
  * 2 ^ n
-- 
cgit v0.10.2


From 141c74350d1c107a9167e5a78923fcca79413bff Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:51 -0700
Subject: exynos: dts: Add pwm device tree node

Add this node from Linux v4.4 so that PWMs can be used in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 7eef3e3..d44c9f6 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -116,4 +116,11 @@
 		};
 	};
 
+	pwm: pwm@12dd0000 {
+		compatible = "samsung,exynos4210-pwm";
+		reg = <0x12dd0000 0x100>;
+		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+		#pwm-cells = <3>;
+	};
+
 };
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index daa6a33..be99a82 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -197,6 +197,13 @@
 		mem-type = "ddr3";
 	};
 
+	pwm: pwm@12dd0000 {
+		compatible = "samsung,exynos4210-pwm";
+		reg = <0x12dd0000 0x100>;
+		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+		#pwm-cells = <3>;
+	};
+
 	xhci1: xhci@12400000 {
 		compatible = "samsung,exynos5250-xhci";
 		reg = <0x12400000 0x10000>;
-- 
cgit v0.10.2


From c309365089283da1cb32c2a6eeaea9eb3f638f7c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:52 -0700
Subject: exynos: Allow tizen to be built without an LCD

This file currently requires an LCD. Adjust it to work without one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/include/libtizen.h b/include/libtizen.h
index 6490fb5..55dccff 100644
--- a/include/libtizen.h
+++ b/include/libtizen.h
@@ -10,6 +10,8 @@
 
 #define HD_RESOLUTION	0
 
+#ifdef CONFIG_LCD
 void get_tizen_logo_info(vidinfo_t *vid);
+#endif
 
 #endif	/* _LIBTIZEN_H_ */
diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c
index 814ed18..d207f77 100644
--- a/lib/tizen/tizen.c
+++ b/lib/tizen/tizen.c
@@ -12,6 +12,7 @@
 #include "tizen_logo_16bpp.h"
 #include "tizen_logo_16bpp_gzip.h"
 
+#ifdef CONFIG_LCD
 void get_tizen_logo_info(vidinfo_t *vid)
 {
 	switch (vid->vl_bpix) {
@@ -31,3 +32,4 @@ void get_tizen_logo_info(vidinfo_t *vid)
 		break;
 	}
 }
+#endif
-- 
cgit v0.10.2


From 531a4a66424946968b28241adbb41165e78d6d26 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:53 -0700
Subject: exynos: Allow CONFIG_MISC_COMMON to be build without an LCD

This file currently requires LCD support. Adjust it so that it can still be
built without LCD support (even thought it won't work fully).

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index da0d4db..77d0a4e 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -147,6 +147,7 @@ static int key_pressed(int key)
 	return value;
 }
 
+#ifdef CONFIG_LCD
 static int check_keys(void)
 {
 	int keys = 0;
@@ -235,9 +236,11 @@ static void display_board_info(void)
 
 	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
 }
+#endif
 
 static int mode_leave_menu(int mode)
 {
+#ifdef CONFIG_LCD
 	char *exit_option;
 	char *exit_reset = "reset";
 	char *exit_back = "back";
@@ -301,8 +304,12 @@ static int mode_leave_menu(int mode)
 
 	lcd_clear();
 	return leave;
+#else
+	return 0;
+#endif
 }
 
+#ifdef CONFIG_LCD
 static void display_download_menu(int mode)
 {
 	char *selection[BOOT_MODE_EXIT + 1];
@@ -320,9 +327,11 @@ static void display_download_menu(int mode)
 		lcd_printf("\t%s  %s - %s\n\n", selection[i],
 			   mode_name[i][0], mode_info[i]);
 }
+#endif
 
 static void download_menu(void)
 {
+#ifdef CONFIG_LCD
 	int mode = 0;
 	int last_mode = 0;
 	int run;
@@ -393,6 +402,7 @@ static void download_menu(void)
 	}
 
 	lcd_clear();
+#endif
 }
 
 void check_boot_mode(void)
-- 
cgit v0.10.2


From ea743e659fbfa9ba4b00ba076cdbf212d6fff081 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:54 -0700
Subject: exynos: Disable LCD display for boards we can't convert

Some boards have the LCD enabled but I cannot test operation for the driver
model conversion. Disable the LCD on these to avoid build errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 54d01ec..66a54d4 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -596,6 +596,7 @@ int mipi_power(void)
 	return 0;
 }
 
+#ifdef CONFIG_LCD
 void exynos_lcd_misc_init(vidinfo_t *vid)
 {
 #ifdef CONFIG_TIZEN
@@ -606,3 +607,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid)
 	setenv("lcdinfo", "lcd=s6e8ax0");
 #endif
 }
+#endif
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 426ae14..81e35b6 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -367,6 +367,7 @@ int exynos_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_LCD
 void exynos_lcd_misc_init(vidinfo_t *vid)
 {
 #ifdef CONFIG_TIZEN
@@ -379,3 +380,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid)
 
 	setenv("lcdinfo", "lcd=ld9040");
 }
+#endif
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index bdb368e..9915306 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -217,9 +217,6 @@ int universal_spi_read(void);
 /*
  * LCD Settings
  */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_LD9040
 #define CONFIG_VIDEO_BMP_GZIP
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index f66bb12..92a0833 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -13,6 +13,9 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
+#undef CONFIG_LCD
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
 #undef CONFIG_KEYBOARD
 
 #define CONFIG_BOARD_COMMON
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 9cf886c..5fe21d9 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -13,6 +13,10 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
+#undef CONFIG_LCD
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
+
 #undef CONFIG_KEYBOARD
 
 #define CONFIG_BOARD_COMMON
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 0c875cb..22b0c90 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -242,12 +242,8 @@
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
-#define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 492a253..1febaae 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -222,12 +222,8 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
-#define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-- 
cgit v0.10.2


From 7b0789e8fcfe052113bcf06dad1d6da6b4d6b108 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:55 -0700
Subject: dts: Add clock and regulator binding files for max77802

These are used by peach_pit and peach_pi. Add them so they can be referenced
in the device tree files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 0000000..997312e
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP		0
+#define MAX77802_CLK_32K_CP		1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h
new file mode 100644
index 0000000..cf28631
--- /dev/null
+++ b/include/dt-bindings/regulator/maxim,max77802.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for the Maxim 77802 PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+
+/* Regulator operating modes */
+#define MAX77802_OPMODE_LP	1
+#define MAX77802_OPMODE_NORMAL	3
+
+#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */
-- 
cgit v0.10.2


From af5b5eae53d2a9a79fc6fd9df862a75b65d1dccb Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:56 -0700
Subject: exynos: Allow PWM0 pinmux to be set up

This is commonly used for LCD backlight control. Add pinmux support for it
on exynos5250 and 5420.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c
index 12eb79c..fec2df9 100644
--- a/arch/arm/mach-exynos/pinmux.c
+++ b/arch/arm/mach-exynos/pinmux.c
@@ -506,6 +506,9 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 		 */
 		gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
 		break;
+	case PERIPH_ID_PWM0:
+		gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2));
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
@@ -548,6 +551,9 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_I2C10:
 		exynos5420_i2c_config(peripheral);
 		break;
+	case PERIPH_ID_PWM0:
+		gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2));
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
-- 
cgit v0.10.2


From 7eb860df13ed3e40469eebd407b90c6f9216dd2e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:57 -0700
Subject: exynos: Simplify calling of exynos_dp_phy_ctrl()

This function controls enabling the EDP PHY. Rename it and drop the existing
weak functions, which are confusing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h
index 3f97b31..88f70d9 100644
--- a/arch/arm/mach-exynos/include/mach/power.h
+++ b/arch/arm/mach-exynos/include/mach/power.h
@@ -1717,7 +1717,7 @@ void set_usbdrd_phy_ctrl(unsigned int enable);
 #define POWER_USB_DRD_PHY_CTRL_EN		(1 << 0)
 #define POWER_USB_DRD_PHY_CTRL_DISABLE		(0 << 0)
 
-void set_dp_phy_ctrl(unsigned int enable);
+void exynos_dp_phy_ctrl(unsigned int enable);
 
 #define EXYNOS_DP_PHY_ENABLE		(1 << 0)
 
diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c
index cd2d661..c923460 100644
--- a/arch/arm/mach-exynos/power.c
+++ b/arch/arm/mach-exynos/power.c
@@ -147,7 +147,7 @@ static void exynos5_dp_phy_control(unsigned int enable)
 	writel(cfg, &power->dptx_phy_control);
 }
 
-void set_dp_phy_ctrl(unsigned int enable)
+void exynos_dp_phy_ctrl(unsigned int enable)
 {
 	if (cpu_is_exynos5())
 		exynos5_dp_phy_control(enable);
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 4d9e151..0dcea71 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -235,11 +235,6 @@ void exynos_cfg_lcd_gpio(void)
 	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 }
 
-void exynos_set_dp_phy(unsigned int onoff)
-{
-	set_dp_phy_ctrl(onoff);
-}
-
 static int board_dp_set_backlight(int percent)
 {
 	struct udevice *dev;
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 9945c4b..88926b9 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -15,6 +15,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/dp_info.h>
 #include <asm/arch/dp.h>
+#include <asm/arch/power.h>
 #include <fdtdec.h>
 #include <libfdt.h>
 
@@ -22,12 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void __exynos_set_dp_phy(unsigned int onoff)
-{
-}
-void exynos_set_dp_phy(unsigned int onoff)
-	__attribute__((weak, alias("__exynos_set_dp_phy")));
-
 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 {
 	disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
@@ -959,7 +954,7 @@ unsigned int exynos_init_dp(void)
 
 	exynos_dp_disp_info(&edp_info->disp_info);
 
-	exynos_set_dp_phy(1);
+	exynos_dp_phy_ctrl(1);
 
 	ret = exynos_dp_init_dp(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
-- 
cgit v0.10.2


From f948f5de94822a372d01e0903b4fe8c682d230e4 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:58 -0700
Subject: exynos: dts: Add display-related device tree fragments

Bring in device tree pieces related to display from Linux 4.4 for:

- snow
- peach_pit
- peach_pi
- spring

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 179584c..8650800 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -163,13 +163,14 @@
 	};
 
 	fimd@14400000 {
+		u-boot,dm-pre-reloc;
 		compatible = "samsung,exynos-fimd";
 		reg = <0x14400000 0x10000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
 
-	dp@145b0000 {
+	dp: dp@145b0000 {
 		compatible = "samsung,exynos5-dp";
 		reg = <0x145b0000 0x1000>;
 		#address-cells = <1>;
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index bda5499..29c13c1 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -198,6 +198,20 @@
 			reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
 			hotplug-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 			edid-emulation = <5>;
+
+			ports {
+				port@0 {
+					bridge_out: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+
+				port@1 {
+					bridge_in: endpoint {
+						remote-endpoint = <&dp_out>;
+					};
+				};
+			};
 		};
 
 		soundcodec@22 {
@@ -223,6 +237,27 @@
 		};
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
+		power-supply = <&fet1>;
+	};
+
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
+
 	spi@131b0000 {
 		spi-max-frequency = <1000000>;
 		spi-deactivate-delay = <100>;
@@ -337,6 +372,15 @@
 		samsung,dynamic-range = <0>;
 		samsung,ycbcr-coeff = <0>;
 		samsung,color-depth = <1>;
+		samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			port@0 {
+				dp_out: endpoint {
+					remote-endpoint = <&bridge_in>;
+				};
+			};
+		};
 	};
 
 };
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index 81b3d29..693501e 100644
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -158,6 +158,27 @@
 		samsung,ycbcr-coeff = <0>;
 		samsung,color-depth = <1>;
 	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <1>;
+		enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
+		power-supply = <&fet1>;
+	};
+
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
 };
 
 &i2c_0 {
@@ -385,6 +406,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x0a>;
+	samsung,lane-count = <1>;
+	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port@0 {
+			dp_out: endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
+
 &i2c_1 {
 	status = "okay";
 	samsung,i2c-sda-delay = <100>;
@@ -585,6 +625,19 @@
 			0x04 0x59 0x60 /* MPU Clock source: LC => RCO */
 			0x04 0x54 0x14 /* LC -> RCO */
 			0x02 0xa1 0x91>; /* HPD high */
+		ports {
+			port@0 {
+				bridge_out: endpoint {
+					remote-endpoint = <&panel_in>;
+				};
+			};
+
+			port@1 {
+				bridge_in: endpoint {
+					remote-endpoint = <&dp_out>;
+				};
+			};
+		};
 	};
 
 	soundcodec@20 {
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 16d52f4..2db4ad2 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -9,6 +9,8 @@
 
 /dts-v1/;
 #include "exynos54xx.dtsi"
+#include <dt-bindings/clock/maxim,max77802.h>
+#include <dt-bindings/regulator/maxim,max77802.h>
 
 / {
 	model = "Samsung/Google Peach Pit board based on Exynos5420";
@@ -29,6 +31,14 @@
 		i2c104 = &i2c_tunnel;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		power-supply = <&tps65090_fet1>;
+	};
+
 	dmc {
 		mem-manuf = "samsung";
 		mem-type = "ddr3";
@@ -188,6 +198,20 @@
 				0x04 0x59 0x60
 				0x04 0x54 0x14  /* LC -> RCO */
 				0x02 0xa1 0x91>;  /* HPD high */
+
+			ports {
+				port@0 {
+					bridge_out: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+
+				port@1 {
+					bridge_in: endpoint {
+						remote-endpoint = <&dp_out>;
+					};
+				};
+			};
 	        };
 	};
 
@@ -203,6 +227,18 @@
 		};
 	};
 
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&tps65090_fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
+
 	spi@12d30000 { /* spi1 */
 		spi-max-frequency = <50000000>;
 		firmware_storage_spi: flash@0 {
@@ -254,6 +290,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x06>;
+	samsung,lane-count = <2>;
+	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port@0 {
+			dp_out: endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
+
 &spi_2 {
 	spi-max-frequency = <3125000>;
 	spi-deactivate-delay = <200>;
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index be99a82..b4ddf53 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -49,7 +49,7 @@
 		status = "disabled";
 	};
 
-	i2c@12CA0000 {
+	hsi2c_4: i2c@12CA0000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "samsung,exynos5-hsi2c";
@@ -178,7 +178,7 @@
 		samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
 	};
 
-	dp@145b0000 {
+	dp: dp@145b0000 {
 		samsung,lt-status = <0>;
 
 		samsung,master-mode = <0>;
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index 76826dc..4c139bf 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -30,6 +30,27 @@
 		i2c104 = &i2c_tunnel;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
+		power-supply = <&tps65090_fet1>;
+	};
+
+	panel: panel {
+		compatible = "auo,b133htn01";
+		power-supply = <&tps65090_fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&dp_out>;
+			};
+		};
+	};
+
 	dmc {
 		mem-manuf = "samsung";
 		mem-type = "ddr3";
@@ -132,6 +153,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x0a>;
+	samsung,lane-count = <2>;
+	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port {
+			dp_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
 &spi_2 {
 	spi-max-frequency = <3125000>;
 	spi-deactivate-delay = <200>;
-- 
cgit v0.10.2


From 21f8f9bb084e276c490454c401fc23dc42c536bc Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:08:59 -0700
Subject: exynos: video: Rename edp_device_info to exynos_dp_priv

Rename this function to better fit with driver model. It is the private data
for the exynos EDP driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h
index 17e8f56..8ce33d6 100644
--- a/arch/arm/mach-exynos/include/mach/dp_info.h
+++ b/arch/arm/mach-exynos/include/mach/dp_info.h
@@ -61,7 +61,7 @@ struct edp_video_info {
 	unsigned int color_depth;
 };
 
-struct edp_device_info {
+struct exynos_dp_priv {
 	struct edp_disp_info disp_info;
 	struct edp_link_train_info lt_info;
 	struct edp_video_info video_info;
@@ -185,7 +185,7 @@ enum {
 
 
 struct exynos_dp_platform_data {
-	struct edp_device_info *edp_dev_info;
+	struct exynos_dp_priv *edp_dev_info;
 };
 
 #ifdef CONFIG_EXYNOS_DP
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 88926b9..0d4ceef 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -162,7 +162,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 }
 
 static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
-					  struct edp_device_info *edp_info)
+					  struct exynos_dp_priv *edp_info)
 {
 	unsigned char buf[12];
 	unsigned int ret;
@@ -251,7 +251,7 @@ static void exynos_dp_init_training(struct exynos_dp *dp_regs)
 }
 
 static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
-					 struct edp_device_info *edp_info)
+					 struct exynos_dp_priv *edp_info)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;
@@ -376,7 +376,7 @@ static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
 }
 
 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
-					 struct edp_device_info *edp_info,
+					 struct exynos_dp_priv *edp_info,
 					 unsigned char *status)
 {
 	unsigned int ret, i;
@@ -433,7 +433,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 }
 
 static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
-					struct edp_device_info *edp_info)
+					struct exynos_dp_priv *edp_info)
 {
 	int ret;
 
@@ -453,7 +453,7 @@ static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
 }
 
 static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
-				      struct edp_device_info *edp_info)
+				      struct exynos_dp_priv *edp_info)
 {
 	int ret;
 
@@ -478,7 +478,7 @@ static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
-					struct edp_device_info *edp_info)
+					struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;
@@ -588,7 +588,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_process_equalizer_training(
-		struct exynos_dp *dp_regs, struct edp_device_info *edp_info)
+		struct exynos_dp *dp_regs, struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;
@@ -697,7 +697,7 @@ static unsigned int exynos_dp_process_equalizer_training(
 }
 
 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
-					       struct edp_device_info *edp_info)
+					       struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = 0;
 	int training_finished;
@@ -748,7 +748,7 @@ static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs,
-					     struct edp_device_info *edp_info)
+					     struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret;
 
@@ -783,7 +783,7 @@ static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
-					   struct edp_device_info *edp_info)
+					   struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = 0;
 	unsigned int retry_cnt;
@@ -872,7 +872,7 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
+int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info)
 {
 	unsigned int node = fdtdec_next_compatible(blob, 0,
 						COMPAT_SAMSUNG_EXYNOS5_DP);
@@ -929,11 +929,11 @@ int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
 unsigned int exynos_init_dp(void)
 {
 	unsigned int ret;
-	struct edp_device_info *edp_info;
+	struct exynos_dp_priv *edp_info;
 	struct exynos_dp *dp_regs;
 	int node;
 
-	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
+	edp_info = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL);
 	if (!edp_info) {
 		debug("failed to allocate edp device object.\n");
 		return -EFAULT;
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index 153c1c6..00a79ea 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -1066,7 +1066,7 @@ void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
 }
 
 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
-				struct edp_device_info *edp_info)
+				struct exynos_dp_priv *edp_info)
 {
 	unsigned int reg;
 	unsigned int bist_type = 0;
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.h b/drivers/video/exynos/exynos_dp_lowlevel.h
index 85459b5..0a7657e 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.h
+++ b/drivers/video/exynos/exynos_dp_lowlevel.h
@@ -74,7 +74,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
 				      struct edp_video_info *video_info);
 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
-				struct edp_device_info *edp_info);
+				struct exynos_dp_priv *edp_info);
 unsigned int exynos_dp_is_slave_video_stream_clock_on(
 					struct exynos_dp *dp_regs);
 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
-- 
cgit v0.10.2


From 8b449a6639c6bee1a97c0eba2ab142a7c471d9b1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:09:00 -0700
Subject: exynos: video: Rename variables for driver model

Use 'priv' for a private pointer and 'regs' for a register pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 0d4ceef..d7bccc3 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -33,20 +33,20 @@ static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 	return;
 }
 
-static int exynos_dp_init_dp(struct exynos_dp *dp_regs)
+static int exynos_dp_init_dp(struct exynos_dp *regs)
 {
 	int ret;
-	exynos_dp_reset(dp_regs);
+	exynos_dp_reset(regs);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_func(dp_regs, DP_ENABLE);
+	exynos_dp_enable_sw_func(regs, DP_ENABLE);
 
-	ret = exynos_dp_init_analog_func(dp_regs);
+	ret = exynos_dp_init_analog_func(regs);
 	if (ret != EXYNOS_DP_SUCCESS)
 		return ret;
 
-	exynos_dp_init_hpd(dp_regs);
-	exynos_dp_init_aux(dp_regs);
+	exynos_dp_init_hpd(regs);
+	exynos_dp_init_aux(regs);
 
 	return ret;
 }
@@ -62,7 +62,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
+static unsigned int exynos_dp_read_edid(struct exynos_dp *regs)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -77,14 +77,14 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	exynos_dp_read_byte_from_i2c(dp_regs, I2C_EDID_DEVICE_ADDR,
+	exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR,
 				     EDID_EXTENSION_FLAG, &extend_block);
 
 	if (extend_block > 0) {
 		printf("DP EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
 						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
@@ -100,7 +100,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
@@ -115,13 +115,13 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 					      &test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -129,7 +129,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 		debug("DP EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
@@ -145,12 +145,12 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -161,8 +161,8 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 	return 0;
 }
 
-static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
-					  struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs,
+					  struct exynos_dp_priv *priv)
 {
 	unsigned char buf[12];
 	unsigned int ret;
@@ -180,7 +180,7 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 	retry_cnt = 5;
 	while (retry_cnt) {
 		/* Read DPCD 0x0000-0x000b */
-		ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_DPCD_REV, 12,
+		ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12,
 						     buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			if (retry_cnt == 0) {
@@ -195,7 +195,7 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 	/* */
 	temp = buf[DPCD_DPCD_REV];
 	if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
-		edp_info->dpcd_rev = temp;
+		priv->dpcd_rev = temp;
 	else {
 		printf("DP Wrong DPCD Rev : %x\n", temp);
 		return -ENODEV;
@@ -203,33 +203,33 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 
 	temp = buf[DPCD_MAX_LINK_RATE];
 	if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
-		edp_info->lane_bw = temp;
+		priv->lane_bw = temp;
 	else {
 		printf("DP Wrong MAX LINK RATE : %x\n", temp);
 		return -EINVAL;
 	}
 
 	/* Refer VESA Display Port Standard Ver1.1a Page 120 */
-	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
+	if (priv->dpcd_rev == DP_DPCD_REV_11) {
 		temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
 		if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
-			edp_info->dpcd_efc = 1;
+			priv->dpcd_efc = 1;
 		else
-			edp_info->dpcd_efc = 0;
+			priv->dpcd_efc = 0;
 	} else {
 		temp = buf[DPCD_MAX_LANE_COUNT];
-		edp_info->dpcd_efc = 0;
+		priv->dpcd_efc = 0;
 	}
 
 	if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
 			temp == DP_LANE_CNT_4) {
-		edp_info->lane_cnt = temp;
+		priv->lane_cnt = temp;
 	} else {
 		printf("DP Wrong MAX LANE COUNT : %x\n", temp);
 		return -EINVAL;
 	}
 
-	ret = exynos_dp_read_edid(dp_regs);
+	ret = exynos_dp_read_edid(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_read_edid() failed\n");
 		return -EINVAL;
@@ -238,35 +238,35 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static void exynos_dp_init_training(struct exynos_dp *dp_regs)
+static void exynos_dp_init_training(struct exynos_dp *regs)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp_regs);
+	exynos_dp_reset_macro(regs);
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, 0);
+	exynos_dp_set_analog_power_down(regs, POWER_ALL, 0);
 }
 
-static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
-					 struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
+					 struct exynos_dp_priv *priv)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;
 
 	debug("DP: %s was called\n", __func__);
 
-	edp_info->lt_info.lt_status = DP_LT_CR;
-	edp_info->lt_info.ep_loop = 0;
-	edp_info->lt_info.cr_loop[0] = 0;
-	edp_info->lt_info.cr_loop[1] = 0;
-	edp_info->lt_info.cr_loop[2] = 0;
-	edp_info->lt_info.cr_loop[3] = 0;
+	priv->lt_info.lt_status = DP_LT_CR;
+	priv->lt_info.ep_loop = 0;
+	priv->lt_info.cr_loop[0] = 0;
+	priv->lt_info.cr_loop[1] = 0;
+	priv->lt_info.cr_loop[2] = 0;
+	priv->lt_info.cr_loop[3] = 0;
 
 		/* Set sink to D0 (Sink Not Ready) mode. */
-	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_SINK_POWER_STATE,
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE,
 					   DPCD_SET_POWER_STATE_D0);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
@@ -274,24 +274,24 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 	}
 
 	/* Set link rate and count as you want to establish */
-	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
-	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
+	exynos_dp_set_lane_count(regs, priv->lane_cnt);
 
 	/* Setup RX configuration */
-	buf[0] = edp_info->lane_bw;
-	buf[1] = edp_info->lane_cnt;
+	buf[0] = priv->lane_bw;
+	buf[1] = priv->lane_cnt;
 
-	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_LINK_BW_SET, 2, buf);
+	ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
-	exynos_dp_set_lane_pre_emphasis(dp_regs, PRE_EMPHASIS_LEVEL_0,
-			edp_info->lane_cnt);
+	exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0,
+			priv->lane_cnt);
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN1);
+	exynos_dp_set_training_pattern(regs, TRAINING_PTN1);
 
 	/* Set RX training pattern */
 	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
@@ -305,7 +305,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 
-	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+	ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 					    5, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
@@ -315,13 +315,13 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
+static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	exynos_dp_set_training_pattern(dp_regs, DP_NONE);
+	exynos_dp_set_training_pattern(regs, DP_NONE);
 
-	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 					   DPCD_TRAINING_PATTERN_DISABLED);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP request_link_training_req failed\n");
@@ -332,12 +332,12 @@ static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
 }
 
 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
-		struct exynos_dp *dp_regs, unsigned char enable)
+		struct exynos_dp *regs, unsigned char enable)
 {
 	unsigned char data;
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_LANE_COUNT_SET,
+	ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
 					    &data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read_from_dpcd failed\n");
@@ -349,7 +349,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 	else
 		data = DPCD_LN_COUNT_SET(data);
 
-	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_LANE_COUNT_SET, data);
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write_to_dpcd failed\n");
 			return -EAGAIN;
@@ -359,24 +359,24 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 	return ret;
 }
 
-static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
+static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
 						unsigned char enhance_mode)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_enable_rx_to_enhanced_mode(dp_regs, enhance_mode);
+	ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP rx_enhance_mode failed\n");
 		return -EAGAIN;
 	}
 
-	exynos_dp_enable_enhanced_mode(dp_regs, enhance_mode);
+	exynos_dp_enable_enhanced_mode(regs, enhance_mode);
 
 	return ret;
 }
 
-static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
-					 struct exynos_dp_priv *edp_info,
+static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
+					 struct exynos_dp_priv *priv,
 					 unsigned char *status)
 {
 	unsigned int ret, i;
@@ -389,14 +389,14 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
 	shift_val[2] = 0;
 	shift_val[3] = 4;
 
-	ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_LANE0_1_STATUS, 2,
+	ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2,
 					     buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		return ret;
 	}
 
-	for (i = 0; i < edp_info->lane_cnt; i++) {
+	for (i = 0; i < priv->lane_cnt; i++) {
 		lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
 		if (lane_stat[0] != lane_stat[i]) {
 			printf("Wrong lane status\n");
@@ -409,7 +409,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
+static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
 		unsigned char lane_num, unsigned char *sw, unsigned char *em)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
@@ -420,7 +420,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 	/* lane_num value is used as array index, so this range 0 ~ 3 */
 	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 
-	ret = exynos_dp_read_byte_from_dpcd(dp_regs, dpcd_addr, &buf);
+	ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read adjust request failed\n");
 		return -EAGAIN;
@@ -432,53 +432,53 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
-					struct exynos_dp_priv *edp_info)
+static int exynos_dp_equalizer_err_link(struct exynos_dp *regs,
+					struct exynos_dp_priv *priv)
 {
 	int ret;
 
-	ret = exynos_dp_training_pattern_dis(dp_regs);
+	ret = exynos_dp_training_pattern_dis(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP training_pattern_disable() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
-	ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
+	ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP set_enhanced_mode() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
 	return ret;
 }
 
-static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
-				      struct exynos_dp_priv *edp_info)
+static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
+				      struct exynos_dp_priv *priv)
 {
 	int ret;
 
-	if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		edp_info->lane_bw = DP_LANE_BW_1_62;
+	if (priv->lane_bw == DP_LANE_BW_2_70) {
+		priv->lane_bw = DP_LANE_BW_1_62;
 		printf("DP Change lane bw to 1.62Gbps\n");
-		edp_info->lt_info.lt_status = DP_LT_START;
+		priv->lt_info.lt_status = DP_LT_START;
 		ret = EXYNOS_DP_SUCCESS;
 	} else {
-		ret = exynos_dp_training_pattern_dis(dp_regs);
+		ret = exynos_dp_training_pattern_dis(regs);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP training_patter_disable() failed\n");
 
-		ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
+		ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP set_enhanced_mode() failed\n");
 
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
-					struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
+					struct exynos_dp_priv *priv)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;
@@ -491,22 +491,22 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 	debug("DP: %s was called\n", __func__);
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP read lane status failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 	}
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
 		debug("DP clock Recovery training succeed\n");
-		exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN2);
+		exynos_dp_set_training_pattern(regs, TRAINING_PTN2);
 
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+		for (i = 0; i < priv->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
 			}
 
@@ -518,7 +518,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+			exynos_dp_set_lanex_pre_emphasis(regs,
 							 lt_ctl_val[i], i);
 		}
 
@@ -528,39 +528,39 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 		buf[3] = lt_ctl_val[2];
 		buf[4] = lt_ctl_val[3];
 
-		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+		ret = exynos_dp_write_bytes_to_dpcd(regs,
 				DPCD_TRAINING_PATTERN_SET, 5, buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern1 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		} else
-			edp_info->lt_info.lt_status = DP_LT_ET;
+			priv->lt_info.lt_status = DP_LT_ET;
 	} else {
-		for (i = 0; i < edp_info->lane_cnt; i++) {
+		for (i = 0; i < priv->lane_cnt; i++) {
 			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
-						dp_regs, i);
-				ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+						regs, i);
+				ret = exynos_dp_read_dpcd_adj_req(regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
 			}
 
 			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
-				ret = exynos_dp_reduce_link_rate(dp_regs,
-								 edp_info);
+				ret = exynos_dp_reduce_link_rate(regs,
+								 priv);
 
 			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_sw) &&
 				(PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_em)) {
-				edp_info->lt_info.cr_loop[i]++;
-				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
+				priv->lt_info.cr_loop[i]++;
+				if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP)
 					ret = exynos_dp_reduce_link_rate(
-							dp_regs, edp_info);
+							regs, priv);
 			}
 
 			lt_ctl_val[i] = 0;
@@ -571,15 +571,15 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+			exynos_dp_set_lanex_pre_emphasis(regs,
 							 lt_ctl_val[i], i);
 		}
 
-		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+		ret = exynos_dp_write_bytes_to_dpcd(regs,
 				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern2 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		}
 	}
@@ -588,7 +588,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_process_equalizer_training(
-		struct exynos_dp *dp_regs, struct exynos_dp_priv *edp_info)
+		struct exynos_dp *regs, struct exynos_dp_priv *priv)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;
@@ -600,33 +600,33 @@ static unsigned int exynos_dp_process_equalizer_training(
 
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 		return ret;
 	}
 
 	debug("DP lane stat : %x\n", lane_stat);
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		ret = exynos_dp_read_byte_from_dpcd(dp_regs,
+		ret = exynos_dp_read_byte_from_dpcd(regs,
 						    DPCD_LN_ALIGN_UPDATED,
 						    &sink_stat);
 		if (ret != EXYNOS_DP_SUCCESS) {
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 
 			return ret;
 		}
 
 		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+		for (i = 0; i < priv->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(regs, i,
 					&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req 1 failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 
 				return ret;
 			}
@@ -646,91 +646,91 @@ static unsigned int exynos_dp_process_equalizer_training(
 			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 			debug("DP Equalizer training succeed\n");
 
-			f_bw = exynos_dp_get_link_bandwidth(dp_regs);
-			f_lane_cnt = exynos_dp_get_lane_count(dp_regs);
+			f_bw = exynos_dp_get_link_bandwidth(regs);
+			f_lane_cnt = exynos_dp_get_lane_count(regs);
 
 			debug("DP final BandWidth : %x\n", f_bw);
 			debug("DP final Lane Count : %x\n", f_lane_cnt);
 
-			edp_info->lt_info.lt_status = DP_LT_FINISHED;
+			priv->lt_info.lt_status = DP_LT_FINISHED;
 
-			exynos_dp_equalizer_err_link(dp_regs, edp_info);
+			exynos_dp_equalizer_err_link(regs, priv);
 
 		} else {
-			edp_info->lt_info.ep_loop++;
+			priv->lt_info.ep_loop++;
 
-			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
-				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+			if (priv->lt_info.ep_loop > MAX_EQ_LOOP) {
+				if (priv->lane_bw == DP_LANE_BW_2_70) {
 					ret = exynos_dp_reduce_link_rate(
-							dp_regs, edp_info);
+							regs, priv);
 				} else {
-					edp_info->lt_info.lt_status =
+					priv->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(dp_regs,
-								     edp_info);
+					exynos_dp_equalizer_err_link(regs,
+								     priv);
 				}
 			} else {
-				for (i = 0; i < edp_info->lane_cnt; i++)
+				for (i = 0; i < priv->lane_cnt; i++)
 					exynos_dp_set_lanex_pre_emphasis(
-						dp_regs, lt_ctl_val[i], i);
+						regs, lt_ctl_val[i], i);
 
-				ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+				ret = exynos_dp_write_bytes_to_dpcd(regs,
 						DPCD_TRAINING_LANE0_SET,
 						4, lt_ctl_val);
 				if (ret != EXYNOS_DP_SUCCESS) {
 					printf("DP set lt pattern failed\n");
-					edp_info->lt_info.lt_status =
+					priv->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(dp_regs,
-								     edp_info);
+					exynos_dp_equalizer_err_link(regs,
+								     priv);
 				}
 			}
 		}
-	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		ret = exynos_dp_reduce_link_rate(dp_regs, edp_info);
+	} else if (priv->lane_bw == DP_LANE_BW_2_70) {
+		ret = exynos_dp_reduce_link_rate(regs, priv);
 	} else {
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		exynos_dp_equalizer_err_link(dp_regs, edp_info);
+		priv->lt_info.lt_status = DP_LT_FAIL;
+		exynos_dp_equalizer_err_link(regs, priv);
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
-					       struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs,
+					       struct exynos_dp_priv *priv)
 {
 	unsigned int ret = 0;
 	int training_finished;
 
 	/* Turn off unnecessary lane */
-	if (edp_info->lane_cnt == 1)
-		exynos_dp_set_analog_power_down(dp_regs, CH1_BLOCK, 1);
+	if (priv->lane_cnt == 1)
+		exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1);
 
 	training_finished = 0;
 
-	edp_info->lt_info.lt_status = DP_LT_START;
+	priv->lt_info.lt_status = DP_LT_START;
 
 	/* Process here */
 	while (!training_finished) {
-		switch (edp_info->lt_info.lt_status) {
+		switch (priv->lt_info.lt_status) {
 		case DP_LT_START:
-			ret = exynos_dp_link_start(dp_regs, edp_info);
+			ret = exynos_dp_link_start(regs, priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:link start failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_CR:
-			ret = exynos_dp_process_clock_recovery(dp_regs,
-							       edp_info);
+			ret = exynos_dp_process_clock_recovery(regs,
+							       priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:clock recovery failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_ET:
-			ret = exynos_dp_process_equalizer_training(dp_regs,
-								   edp_info);
+			ret = exynos_dp_process_equalizer_training(regs,
+								   priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:equalizer training failed\n");
 				return ret;
@@ -747,75 +747,75 @@ static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs,
-					     struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs,
+					     struct exynos_dp_priv *priv)
 {
 	unsigned int ret;
 
-	exynos_dp_init_training(dp_regs);
+	exynos_dp_init_training(regs);
 
-	ret = exynos_dp_sw_link_training(dp_regs, edp_info);
+	ret = exynos_dp_sw_link_training(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS)
 		printf("DP dp_sw_link_training() failed\n");
 
 	return ret;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs,
+static void exynos_dp_enable_scramble(struct exynos_dp *regs,
 				      unsigned int enable)
 {
 	unsigned char data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp_regs, DP_ENABLE);
+		exynos_dp_enable_scrambling(regs, DP_ENABLE);
 
-		exynos_dp_read_byte_from_dpcd(dp_regs,
+		exynos_dp_read_byte_from_dpcd(regs,
 					      DPCD_TRAINING_PATTERN_SET, &data);
-		exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 	} else {
-		exynos_dp_enable_scrambling(dp_regs, DP_DISABLE);
-		exynos_dp_read_byte_from_dpcd(dp_regs,
+		exynos_dp_enable_scrambling(regs, DP_DISABLE);
+		exynos_dp_read_byte_from_dpcd(regs,
 					      DPCD_TRAINING_PATTERN_SET, &data);
-		exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data | DPCD_SCRAMBLING_DISABLED));
 	}
 }
 
-static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
-					   struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_config_video(struct exynos_dp *regs,
+					   struct exynos_dp_priv *priv)
 {
 	unsigned int ret = 0;
 	unsigned int retry_cnt;
 
 	mdelay(1);
 
-	if (edp_info->video_info.master_mode) {
+	if (priv->video_info.master_mode) {
 		printf("DP does not support master mode\n");
 		return -ENODEV;
 	} else {
 		/* debug slave */
-		exynos_dp_config_video_slave_mode(dp_regs,
-						  &edp_info->video_info);
+		exynos_dp_config_video_slave_mode(regs,
+						  &priv->video_info);
 	}
 
-	exynos_dp_set_video_color_format(dp_regs, &edp_info->video_info);
+	exynos_dp_set_video_color_format(regs, &priv->video_info);
 
-	if (edp_info->video_info.bist_mode) {
-		if (exynos_dp_config_video_bist(dp_regs, edp_info) != 0)
+	if (priv->video_info.bist_mode) {
+		if (exynos_dp_config_video_bist(regs, priv) != 0)
 			return -1;
 	}
 
-	ret = exynos_dp_get_pll_lock_status(dp_regs);
+	ret = exynos_dp_get_pll_lock_status(regs);
 	if (ret != PLL_LOCKED) {
 		printf("DP PLL is not locked yet\n");
 		return -EIO;
 	}
 
-	if (edp_info->video_info.master_mode == 0) {
+	if (priv->video_info.master_mode == 0) {
 		retry_cnt = 10;
 		while (retry_cnt) {
-			ret = exynos_dp_is_slave_video_stream_clock_on(dp_regs);
+			ret = exynos_dp_is_slave_video_stream_clock_on(regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP stream_clock_on failed\n");
@@ -829,34 +829,34 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp_regs, CALCULATED_M, 0, 0);
+	exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp_regs, VIDEO_TIMING_FROM_CAPTURE);
+	exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Enable video bist */
-	if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
-		edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
-		edp_info->video_info.bist_pattern != COLOR_SQUARE)
-		exynos_dp_enable_video_bist(dp_regs,
-					    edp_info->video_info.bist_mode);
+	if (priv->video_info.bist_pattern != COLOR_RAMP &&
+		priv->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
+		priv->video_info.bist_pattern != COLOR_SQUARE)
+		exynos_dp_enable_video_bist(regs,
+					    priv->video_info.bist_mode);
 	else
-		exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
+		exynos_dp_enable_video_bist(regs, DP_DISABLE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
+	exynos_dp_enable_video_mute(regs, DP_DISABLE);
 
 	/* Configure video Master or Slave mode */
-	exynos_dp_enable_video_master(dp_regs,
-				      edp_info->video_info.master_mode);
+	exynos_dp_enable_video_master(regs,
+				      priv->video_info.master_mode);
 
 	/* Enable video */
-	exynos_dp_start_video(dp_regs);
+	exynos_dp_start_video(regs);
 
-	if (edp_info->video_info.master_mode == 0) {
+	if (priv->video_info.master_mode == 0) {
 		retry_cnt = 100;
 		while (retry_cnt) {
-			ret = exynos_dp_is_video_stream_on(dp_regs);
+			ret = exynos_dp_is_video_stream_on(regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Timeout of video stream\n");
@@ -872,7 +872,7 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info)
+int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *priv)
 {
 	unsigned int node = fdtdec_next_compatible(blob, 0,
 						COMPAT_SAMSUNG_EXYNOS5_DP);
@@ -881,47 +881,47 @@ int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info)
 		return -ENODEV;
 	}
 
-	edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
+	priv->disp_info.h_res = fdtdec_get_int(blob, node,
 							"samsung,h-res", 0);
-	edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
+	priv->disp_info.h_sync_width = fdtdec_get_int(blob, node,
 						"samsung,h-sync-width", 0);
-	edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.h_back_porch = fdtdec_get_int(blob, node,
 						"samsung,h-back-porch", 0);
-	edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.h_front_porch = fdtdec_get_int(blob, node,
 						"samsung,h-front-porch", 0);
-	edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
+	priv->disp_info.v_res = fdtdec_get_int(blob, node,
 						"samsung,v-res", 0);
-	edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
+	priv->disp_info.v_sync_width = fdtdec_get_int(blob, node,
 						"samsung,v-sync-width", 0);
-	edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.v_back_porch = fdtdec_get_int(blob, node,
 						"samsung,v-back-porch", 0);
-	edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.v_front_porch = fdtdec_get_int(blob, node,
 						"samsung,v-front-porch", 0);
-	edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
+	priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
 						"samsung,v-sync-rate", 0);
 
-	edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
+	priv->lt_info.lt_status = fdtdec_get_int(blob, node,
 						"samsung,lt-status", 0);
 
-	edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
+	priv->video_info.master_mode = fdtdec_get_int(blob, node,
 						"samsung,master-mode", 0);
-	edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
+	priv->video_info.bist_mode = fdtdec_get_int(blob, node,
 						"samsung,bist-mode", 0);
-	edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
+	priv->video_info.bist_pattern = fdtdec_get_int(blob, node,
 						"samsung,bist-pattern", 0);
-	edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
+	priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
 						"samsung,h-sync-polarity", 0);
-	edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
+	priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
 						"samsung,v-sync-polarity", 0);
-	edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
+	priv->video_info.interlaced = fdtdec_get_int(blob, node,
 						"samsung,interlaced", 0);
-	edp_info->video_info.color_space = fdtdec_get_int(blob, node,
+	priv->video_info.color_space = fdtdec_get_int(blob, node,
 						"samsung,color-space", 0);
-	edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
+	priv->video_info.dynamic_range = fdtdec_get_int(blob, node,
 						"samsung,dynamic-range", 0);
-	edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
+	priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
 						"samsung,ycbcr-coeff", 0);
-	edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
+	priv->video_info.color_depth = fdtdec_get_int(blob, node,
 						"samsung,color-depth", 0);
 	return 0;
 }
@@ -929,17 +929,17 @@ int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info)
 unsigned int exynos_init_dp(void)
 {
 	unsigned int ret;
-	struct exynos_dp_priv *edp_info;
-	struct exynos_dp *dp_regs;
+	struct exynos_dp_priv *priv;
+	struct exynos_dp *regs;
 	int node;
 
-	edp_info = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL);
-	if (!edp_info) {
+	priv = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL);
+	if (!priv) {
 		debug("failed to allocate edp device object.\n");
 		return -EFAULT;
 	}
 
-	if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
+	if (exynos_dp_parse_dt(gd->fdt_blob, priv))
 		debug("unable to parse DP DT node\n");
 
 	node = fdtdec_next_compatible(gd->fdt_blob, 0,
@@ -947,42 +947,42 @@ unsigned int exynos_init_dp(void)
 	if (node <= 0)
 		debug("exynos_dp: Can't get device node for dp\n");
 
-	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node,
+	regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node,
 						      "reg");
-	if (dp_regs == NULL)
+	if (regs == NULL)
 		debug("Can't get the DP base address\n");
 
-	exynos_dp_disp_info(&edp_info->disp_info);
+	exynos_dp_disp_info(&priv->disp_info);
 
 	exynos_dp_phy_ctrl(1);
 
-	ret = exynos_dp_init_dp(dp_regs);
+	ret = exynos_dp_init_dp(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_init_dp() failed\n");
 		return ret;
 	}
 
-	ret = exynos_dp_handle_edid(dp_regs, edp_info);
+	ret = exynos_dp_handle_edid(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("EDP handle_edid fail\n");
 		return ret;
 	}
 
-	ret = exynos_dp_set_link_train(dp_regs, edp_info);
+	ret = exynos_dp_set_link_train(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP link training fail\n");
 		return ret;
 	}
 
-	exynos_dp_enable_scramble(dp_regs, DP_ENABLE);
-	exynos_dp_enable_rx_to_enhanced_mode(dp_regs, DP_ENABLE);
-	exynos_dp_enable_enhanced_mode(dp_regs, DP_ENABLE);
+	exynos_dp_enable_scramble(regs, DP_ENABLE);
+	exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE);
+	exynos_dp_enable_enhanced_mode(regs, DP_ENABLE);
 
-	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
-	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
+	exynos_dp_set_lane_count(regs, priv->lane_cnt);
 
-	exynos_dp_init_video(dp_regs);
-	ret = exynos_dp_config_video(dp_regs, edp_info);
+	exynos_dp_init_video(regs);
+	ret = exynos_dp_config_video(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("Exynos DP init failed\n");
 		return ret;
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index 00a79ea..f978473 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -1066,49 +1066,46 @@ void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
 }
 
 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
-				struct exynos_dp_priv *edp_info)
+				struct exynos_dp_priv *priv)
 {
 	unsigned int reg;
 	unsigned int bist_type = 0;
-	struct edp_video_info video_info = edp_info->video_info;
+	struct edp_video_info video_info = priv->video_info;
 
 	/* For master mode, you don't need to set the video format */
 	if (video_info.master_mode == 0) {
-		writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
-				&dp_regs->total_ln_cfg_l);
-		writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
-				&dp_regs->total_ln_cfg_h);
-		writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
-				&dp_regs->active_ln_cfg_l);
-		writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
-				&dp_regs->active_ln_cfg_h);
-		writel(edp_info->disp_info.v_sync_width,
-				&dp_regs->vsw_cfg);
-		writel(edp_info->disp_info.v_back_porch,
-				&dp_regs->vbp_cfg);
-		writel(edp_info->disp_info.v_front_porch,
-				&dp_regs->vfp_cfg);
-
-		writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
-				&dp_regs->total_pix_cfg_l);
-		writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
-				&dp_regs->total_pix_cfg_h);
-		writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
-				&dp_regs->active_pix_cfg_l);
-		writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
-				&dp_regs->active_pix_cfg_h);
-		writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
-				&dp_regs->hfp_cfg_l);
-		writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
-				&dp_regs->hfp_cfg_h);
-		writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
-				&dp_regs->hsw_cfg_l);
-		writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
-				&dp_regs->hsw_cfg_h);
-		writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
-				&dp_regs->hbp_cfg_l);
-		writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
-				&dp_regs->hbp_cfg_h);
+		writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
+		       &dp_regs->total_ln_cfg_l);
+		writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
+		       &dp_regs->total_ln_cfg_h);
+		writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
+		       &dp_regs->active_ln_cfg_l);
+		writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
+		       &dp_regs->active_ln_cfg_h);
+		writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
+		writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
+		writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
+
+		writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
+		       &dp_regs->total_pix_cfg_l);
+		writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
+		       &dp_regs->total_pix_cfg_h);
+		writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
+		       &dp_regs->active_pix_cfg_l);
+		writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
+		       &dp_regs->active_pix_cfg_h);
+		writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
+		       &dp_regs->hfp_cfg_l);
+		writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
+		       &dp_regs->hfp_cfg_h);
+		writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
+		       &dp_regs->hsw_cfg_l);
+		writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
+		       &dp_regs->hsw_cfg_h);
+		writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
+		       &dp_regs->hbp_cfg_l);
+		writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
+		       &dp_regs->hbp_cfg_h);
 
 		/*
 		 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.h b/drivers/video/exynos/exynos_dp_lowlevel.h
index 0a7657e..e4c867e 100644
--- a/drivers/video/exynos/exynos_dp_lowlevel.h
+++ b/drivers/video/exynos/exynos_dp_lowlevel.h
@@ -74,7 +74,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
 				      struct edp_video_info *video_info);
 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
-				struct exynos_dp_priv *edp_info);
+				struct exynos_dp_priv *priv);
 unsigned int exynos_dp_is_slave_video_stream_clock_on(
 					struct exynos_dp *dp_regs);
 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index e13d35a..83b1187 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -35,9 +35,9 @@ struct vidinfo panel_info  = {
 	.vl_col = -1,
 };
 
-static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled)
+static void exynos_fimd_set_dualrgb(struct vidinfo *priv, unsigned int enabled)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
 	if (enabled) {
@@ -45,32 +45,32 @@ static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled)
 			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
 
 		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
-		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
+		cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
 			EXYNOS_DUALRGB_MAIN_CNT(0);
 	}
 
-	writel(cfg, &fimd_ctrl->dualrgb);
+	writel(cfg, &reg->dualrgb);
 }
 
-static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
+static void exynos_fimd_set_dp_clkcon(struct vidinfo *priv,
 				      unsigned int enabled)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
 	if (enabled)
 		cfg = EXYNOS_DP_CLK_ENABLE;
 
-	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
+	writel(cfg, &reg->dp_mie_clkcon);
 }
 
-static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
+static void exynos_fimd_set_par(struct vidinfo *priv, unsigned int win_id)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
 	/* set window control */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+	cfg = readl((unsigned int)&reg->wincon0 +
 			EXYNOS_WINCON(win_id));
 
 	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
@@ -86,7 +86,7 @@ static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
 	/* dma burst is 16 */
 	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
 
-	switch (pvid->vl_bpix) {
+	switch (priv->vl_bpix) {
 	case 4:
 		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
 		break;
@@ -95,72 +95,72 @@ static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
 		break;
 	}
 
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+	writel(cfg, (unsigned int)&reg->wincon0 +
 			EXYNOS_WINCON(win_id));
 
 	/* set window position to x=0, y=0*/
 	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
+	writel(cfg, (unsigned int)&reg->vidosd0a +
 			EXYNOS_VIDOSD(win_id));
 
-	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
-		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
+	cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) |
+		EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) |
 		EXYNOS_VIDOSD_RIGHT_X_E(1) |
 		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
 
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
+	writel(cfg, (unsigned int)&reg->vidosd0b +
 			EXYNOS_VIDOSD(win_id));
 
 	/* set window size for window0*/
-	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
+	cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row);
+	writel(cfg, (unsigned int)&reg->vidosd0c +
 			EXYNOS_VIDOSD(win_id));
 }
 
-static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
+static void exynos_fimd_set_buffer_address(struct vidinfo *priv,
 					   unsigned int win_id,
 					   ulong lcd_base_addr)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned long start_addr, end_addr;
 
 	start_addr = lcd_base_addr;
-	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
-				pvid->vl_row);
+	end_addr = start_addr + ((priv->vl_col * (NBITS(priv->vl_bpix) / 8)) *
+				priv->vl_row);
 
-	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
+	writel(start_addr, (unsigned int)&reg->vidw00add0b0 +
 			EXYNOS_BUFFER_OFFSET(win_id));
-	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
+	writel(end_addr, (unsigned int)&reg->vidw00add1b0 +
 			EXYNOS_BUFFER_OFFSET(win_id));
 }
 
-static void exynos_fimd_set_clock(struct vidinfo *pvid)
+static void exynos_fimd_set_clock(struct vidinfo *priv)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0, div = 0, remainder, remainder_div;
 	unsigned long pixel_clock;
 	unsigned long long src_clock;
 
-	if (pvid->dual_lcd_enabled) {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col / 2) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
-		pixel_clock = pvid->vl_freq *
-				pvid->vl_width * pvid->vl_height *
-				(pvid->cs_setup + pvid->wr_setup +
-				 pvid->wr_act + pvid->wr_hold + 1);
+	if (priv->dual_lcd_enabled) {
+		pixel_clock = priv->vl_freq *
+				(priv->vl_hspw + priv->vl_hfpd +
+				 priv->vl_hbpd + priv->vl_col / 2) *
+				(priv->vl_vspw + priv->vl_vfpd +
+				 priv->vl_vbpd + priv->vl_row);
+	} else if (priv->interface_mode == FIMD_CPU_INTERFACE) {
+		pixel_clock = priv->vl_freq *
+				priv->vl_width * priv->vl_height *
+				(priv->cs_setup + priv->wr_setup +
+				 priv->wr_act + priv->wr_hold + 1);
 	} else {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
+		pixel_clock = priv->vl_freq *
+				(priv->vl_hspw + priv->vl_hfpd +
+				 priv->vl_hbpd + priv->vl_col) *
+				(priv->vl_vspw + priv->vl_vfpd +
+				 priv->vl_vbpd + priv->vl_row);
 	}
 
-	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg = readl(&reg->vidcon0);
 	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
 		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
 		EXYNOS_VIDCON0_CLKDIR_MASK);
@@ -181,32 +181,32 @@ static void exynos_fimd_set_clock(struct vidinfo *pvid)
 		div++;
 
 	/* in case of dual lcd mode. */
-	if (pvid->dual_lcd_enabled)
+	if (priv->dual_lcd_enabled)
 		div--;
 
 	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
-	writel(cfg, &fimd_ctrl->vidcon0);
+	writel(cfg, &reg->vidcon0);
 }
 
-void exynos_set_trigger(struct vidinfo *pvid)
+void exynos_set_trigger(struct vidinfo *priv)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
-	cfg = readl(&fimd_ctrl->trigcon);
+	cfg = readl(&reg->trigcon);
 
 	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
 
-	writel(cfg, &fimd_ctrl->trigcon);
+	writel(cfg, &reg->trigcon);
 }
 
-int exynos_is_i80_frame_done(struct vidinfo *pvid)
+int exynos_is_i80_frame_done(struct vidinfo *priv)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 	int status;
 
-	cfg = readl(&fimd_ctrl->trigcon);
+	cfg = readl(&reg->trigcon);
 
 	/* frame done func is valid only when TRIMODE[0] is set to 1. */
 	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
@@ -215,58 +215,58 @@ int exynos_is_i80_frame_done(struct vidinfo *pvid)
 	return status;
 }
 
-static void exynos_fimd_lcd_on(struct vidinfo *pvid)
+static void exynos_fimd_lcd_on(struct vidinfo *priv)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
 	/* display on */
-	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg = readl(&reg->vidcon0);
 	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
+	writel(cfg, &reg->vidcon0);
 }
 
-static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id)
+static void exynos_fimd_window_on(struct vidinfo *priv, unsigned int win_id)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
 	/* enable window */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+	cfg = readl((unsigned int)&reg->wincon0 +
 			EXYNOS_WINCON(win_id));
 	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+	writel(cfg, (unsigned int)&reg->wincon0 +
 			EXYNOS_WINCON(win_id));
 
-	cfg = readl(&fimd_ctrl->winshmap);
+	cfg = readl(&reg->winshmap);
 	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
+	writel(cfg, &reg->winshmap);
 }
 
-void exynos_fimd_lcd_off(struct vidinfo *pvid)
+void exynos_fimd_lcd_off(struct vidinfo *priv)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
-	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg = readl(&reg->vidcon0);
 	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
+	writel(cfg, &reg->vidcon0);
 }
 
-void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id)
+void exynos_fimd_window_off(struct vidinfo *priv, unsigned int win_id)
 {
-	struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl;
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
 
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+	cfg = readl((unsigned int)&reg->wincon0 +
 			EXYNOS_WINCON(win_id));
 	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+	writel(cfg, (unsigned int)&reg->wincon0 +
 			EXYNOS_WINCON(win_id));
 
-	cfg = readl(&fimd_ctrl->winshmap);
+	cfg = readl(&reg->winshmap);
 	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
+	writel(cfg, &reg->winshmap);
 }
 
 /*
@@ -307,9 +307,9 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address)
+void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address)
 {
-	struct exynos_fb *fimd_ctrl;
+	struct exynos_fb *reg;
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
 	unsigned int node;
@@ -319,105 +319,105 @@ void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address)
 	if (node <= 0)
 		debug("exynos_fb: Can't get device node for fimd\n");
 
-	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
+	reg = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
 							"reg");
-	if (fimd_ctrl == NULL)
+	if (reg == NULL)
 		debug("Can't get the FIMD base address\n");
-	pvid->fimd_ctrl = fimd_ctrl;
+	priv->reg = reg;
 
 	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
 		exynos_fimd_disable_sysmmu();
 
 	offset = exynos_fimd_get_base_offset();
 
-	rgb_mode = pvid->rgb_mode;
+	rgb_mode = priv->rgb_mode;
 
-	if (pvid->interface_mode == FIMD_RGB_INTERFACE) {
+	if (priv->interface_mode == FIMD_RGB_INTERFACE) {
 		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
-		writel(cfg, &fimd_ctrl->vidcon0);
+		writel(cfg, &reg->vidcon0);
 
-		cfg = readl(&fimd_ctrl->vidcon2);
+		cfg = readl(&reg->vidcon2);
 		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
 			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
 			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
 		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
-		writel(cfg, &fimd_ctrl->vidcon2);
+		writel(cfg, &reg->vidcon2);
 
 		/* set polarity */
 		cfg = 0;
-		if (!pvid->vl_clkp)
+		if (!priv->vl_clkp)
 			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
-		if (!pvid->vl_hsp)
+		if (!priv->vl_hsp)
 			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
-		if (!pvid->vl_vsp)
+		if (!priv->vl_vsp)
 			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
-		if (!pvid->vl_dp)
+		if (!priv->vl_dp)
 			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
 
-		writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
+		writel(cfg, (unsigned int)&reg->vidcon1 + offset);
 
 		/* set timing */
-		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
+		cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1);
+		writel(cfg, (unsigned int)&reg->vidtcon0 + offset);
 
-		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
+		cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1);
 
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
+		writel(cfg, (unsigned int)&reg->vidtcon1 + offset);
 
 		/* set lcd size */
-		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
-			EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
+		cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) |
+			EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1);
 
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
+		writel(cfg, (unsigned int)&reg->vidtcon2 + offset);
 	}
 
 	/* set display mode */
-	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg = readl(&reg->vidcon0);
 	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
 	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
-	writel(cfg, &fimd_ctrl->vidcon0);
+	writel(cfg, &reg->vidcon0);
 
 	/* set par */
-	exynos_fimd_set_par(pvid, pvid->win_id);
+	exynos_fimd_set_par(priv, priv->win_id);
 
 	/* set memory address */
-	exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address);
+	exynos_fimd_set_buffer_address(priv, priv->win_id, lcd_base_address);
 
 	/* set buffer size */
-	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col *
-			NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col *
-			NBITS(pvid->vl_bpix) / 8) |
+	cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
+			NBITS(priv->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
+			NBITS(priv->vl_bpix) / 8) |
 		EXYNOS_VIDADDR_OFFSIZE(0) |
 		EXYNOS_VIDADDR_OFFSIZE_E(0);
 
-	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
-					EXYNOS_BUFFER_SIZE(pvid->win_id));
+	writel(cfg, (unsigned int)&reg->vidw00add2 +
+					EXYNOS_BUFFER_SIZE(priv->win_id));
 
 	/* set clock */
-	exynos_fimd_set_clock(pvid);
+	exynos_fimd_set_clock(priv);
 
 	/* set rgb mode to dual lcd. */
-	exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled);
+	exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled);
 
 	/* display on */
-	exynos_fimd_lcd_on(pvid);
+	exynos_fimd_lcd_on(priv);
 
 	/* window on */
-	exynos_fimd_window_on(pvid, pvid->win_id);
+	exynos_fimd_window_on(priv, priv->win_id);
 
-	exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
+	exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
 }
 
-unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid)
+unsigned long exynos_fimd_calc_fbsize(struct vidinfo *priv)
 {
-	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
+	return priv->vl_col * priv->vl_row * (NBITS(priv->vl_bpix) / 8);
 }
 
 ushort *configuration_get_cmap(void)
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
index 0aa0fc7..ab92ffb 100644
--- a/include/exynos_lcd.h
+++ b/include/exynos_lcd.h
@@ -75,7 +75,7 @@ typedef struct vidinfo {
 	unsigned int sclk_div;
 
 	unsigned int dual_lcd_enabled;
-	struct exynos_fb *fimd_ctrl;
+	struct exynos_fb *reg;
 	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
 } vidinfo_t;
 
-- 
cgit v0.10.2


From bb5930d5c97fa22ed2fe048106fcabb5b7c77c96 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:09:01 -0700
Subject: exynos: video: Convert several boards to driver model for video

Update several boards to use driver model for video. This involves changes
to the EDP and FIMD (frame buffer) drivers. Existing PWM, simple-panel and
pwm-backlight drivers are used. These work without additional configuration
since they use the device tree settings in the same way as Linux.

Boards converted are:
- snow
- spring
- peach-pit
- peach-pi

All have been tested. Not converted:

- MIPI display driver
- s5pc210_universal
- smdk5420
- smdk5250
- trats
- trats2

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h
index 8ce33d6..1079e1e 100644
--- a/arch/arm/mach-exynos/include/mach/dp_info.h
+++ b/arch/arm/mach-exynos/include/mach/dp_info.h
@@ -72,6 +72,7 @@ struct exynos_dp_priv {
 	unsigned char dpcd_rev;
 	/*support enhanced frame cap */
 	unsigned char dpcd_efc;
+	struct exynos_dp *regs;
 };
 
 enum analog_power_block {
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 7995174..0eb066c 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -158,21 +158,6 @@ int board_early_init_f(void)
 	board_i2c_init(gd->fdt_blob);
 #endif
 
-#if defined(CONFIG_EXYNOS_FB)
-	/*
-	 * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
-	 * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix,
-	 * to reserve frame-buffer memory at a very early stage. So, we need
-	 * to fill panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix
-	 * before lcd_setmem() is called.
-	 */
-	err = exynos_lcd_early_init(gd->fdt_blob);
-	if (err) {
-		debug("LCD early init failed\n");
-		return err;
-	}
-#endif
-
 	return exynos_early_init_f();
 }
 #endif
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index ce07052..fea8bde 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -47,6 +47,8 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65090=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_SAMSUNG=y
@@ -56,6 +58,8 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 4479fe8..41c3d12 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -47,6 +47,8 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65090=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_SAMSUNG=y
@@ -56,6 +58,8 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 77b97a3..c16c90c 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -52,6 +52,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_S5P=y
 CONFIG_DEBUG_UART_BASE=0x12c30000
@@ -65,6 +67,8 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index d3b174a..b68cab0 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -52,6 +52,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_S5P=y
 CONFIG_DEBUG_UART_BASE=0x12c30000
@@ -65,6 +67,8 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index d7bccc3..fc39f2c 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -7,17 +7,21 @@
  */
 
 #include <config.h>
+#include <dm.h>
 #include <common.h>
+#include <display.h>
+#include <fdtdec.h>
+#include <libfdt.h>
 #include <malloc.h>
+#include <video_bridge.h>
 #include <linux/compat.h>
 #include <linux/err.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dp_info.h>
 #include <asm/arch/dp.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
-#include <fdtdec.h>
-#include <libfdt.h>
 
 #include "exynos_dp_lowlevel.h"
 
@@ -872,15 +876,19 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *regs,
 	return ret;
 }
 
-int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *priv)
+static int exynos_dp_ofdata_to_platdata(struct udevice *dev)
 {
-	unsigned int node = fdtdec_next_compatible(blob, 0,
-						COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0) {
-		debug("exynos_dp: Can't get device node for dp\n");
-		return -ENODEV;
-	}
+	struct exynos_dp_priv *priv = dev_get_priv(dev);
+	const void *blob = gd->fdt_blob;
+	unsigned int node = dev->of_offset;
+	fdt_addr_t addr;
 
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		debug("Can't get the DP base address\n");
+		return -EINVAL;
+	}
+	priv->regs = (struct exynos_dp *)addr;
 	priv->disp_info.h_res = fdtdec_get_int(blob, node,
 							"samsung,h-res", 0);
 	priv->disp_info.h_sync_width = fdtdec_get_int(blob, node,
@@ -926,34 +934,97 @@ int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *priv)
 	return 0;
 }
 
-unsigned int exynos_init_dp(void)
+static int exynos_dp_bridge_init(struct udevice *dev)
 {
-	unsigned int ret;
-	struct exynos_dp_priv *priv;
-	struct exynos_dp *regs;
-	int node;
+	const int max_tries = 10;
+	int num_tries;
+	int ret;
 
-	priv = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL);
-	if (!priv) {
-		debug("failed to allocate edp device object.\n");
-		return -EFAULT;
+	debug("%s\n", __func__);
+	ret = video_bridge_attach(dev);
+	if (ret) {
+		debug("video bridge init failed: %d\n", ret);
+		return ret;
 	}
 
-	if (exynos_dp_parse_dt(gd->fdt_blob, priv))
-		debug("unable to parse DP DT node\n");
+	/*
+	 * We need to wait for 90ms after bringing up the bridge since there
+	 * is a phantom "high" on the HPD chip during its bootup.  The phantom
+	 * high comes within 7ms of de-asserting PD and persists for at least
+	 * 15ms.  The real high comes roughly 50ms after PD is de-asserted. The
+	 * phantom high makes it hard for us to know when the NXP chip is up.
+	 */
+	mdelay(90);
 
-	node = fdtdec_next_compatible(gd->fdt_blob, 0,
-				      COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0)
-		debug("exynos_dp: Can't get device node for dp\n");
+	for (num_tries = 0; num_tries < max_tries; num_tries++) {
+		/* Check HPD. If it's high, or we don't have it, all is well */
+		ret = video_bridge_check_attached(dev);
+		if (!ret || ret == -ENOENT)
+			return 0;
 
-	regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node,
-						      "reg");
-	if (regs == NULL)
-		debug("Can't get the DP base address\n");
+		debug("%s: eDP bridge failed to come up; try %d of %d\n",
+		      __func__, num_tries, max_tries);
+	}
+
+	/* Immediately go into bridge reset if the hp line is not high */
+	return -EIO;
+}
+
+static int exynos_dp_bridge_setup(const void *blob)
+{
+	const int max_tries = 2;
+	int num_tries;
+	struct udevice *dev;
+	int ret;
+
+	/* Configure I2C registers for Parade bridge */
+	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
+	if (ret) {
+		debug("video bridge init failed: %d\n", ret);
+		return ret;
+	}
+
+	if (strncmp(dev->driver->name, "parade", 6)) {
+		/* Mux HPHPD to the special hotplug detect mode */
+		exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
+	}
+
+	for (num_tries = 0; num_tries < max_tries; num_tries++) {
+		ret = exynos_dp_bridge_init(dev);
+		if (!ret)
+			return 0;
+		if (num_tries == max_tries - 1)
+			break;
+
+		/*
+		* If we're here, the bridge chip failed to initialise.
+		* Power down the bridge in an attempt to reset.
+		*/
+		video_bridge_set_active(dev, false);
+
+		/*
+		* Arbitrarily wait 300ms here with DP_N low.  Don't know for
+		* sure how long we should wait, but we're being paranoid.
+		*/
+		mdelay(300);
+	}
 
+	return ret;
+}
+int exynos_dp_enable(struct udevice *dev, int panel_bpp,
+		     const struct display_timing *timing)
+{
+	struct exynos_dp_priv *priv = dev_get_priv(dev);
+	struct exynos_dp *regs = priv->regs;
+	unsigned int ret;
+
+	debug("%s: start\n", __func__);
 	exynos_dp_disp_info(&priv->disp_info);
 
+	ret = exynos_dp_bridge_setup(gd->fdt_blob);
+	if (ret && ret != -ENODEV)
+		printf("LCD bridge failed to enable: %d\n", ret);
+
 	exynos_dp_phy_ctrl(1);
 
 	ret = exynos_dp_init_dp(regs);
@@ -992,3 +1063,22 @@ unsigned int exynos_init_dp(void)
 
 	return ret;
 }
+
+
+static const struct dm_display_ops exynos_dp_ops = {
+	.enable = exynos_dp_enable,
+};
+
+static const struct udevice_id exynos_dp_ids[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_dp) = {
+	.name	= "eexynos_dp",
+	.id	= UCLASS_DISPLAY,
+	.of_match = exynos_dp_ids,
+	.ops	= &exynos_dp_ops,
+	.ofdata_to_platdata	= exynos_dp_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_dp_priv),
+};
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index 83b1187..c8fef63 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -9,33 +9,98 @@
 
 #include <config.h>
 #include <common.h>
+#include <display.h>
 #include <div64.h>
-#include <lcd.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <libfdt.h>
+#include <panel.h>
+#include <video.h>
+#include <video_bridge.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/mipi_dsim.h>
 #include <asm/arch/dp_info.h>
+#include <asm/arch/fb.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/system.h>
 #include <asm/gpio.h>
 #include <asm-generic/errno.h>
 
-#include "exynos_fb.h"
-
 DECLARE_GLOBAL_DATA_PTR;
 
-struct vidinfo panel_info  = {
-	/*
-	 * Insert a value here so that we don't end up in the BSS
-	 * Reference: drivers/video/tegra.c
-	 */
-	.vl_col = -1,
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
 };
 
-static void exynos_fimd_set_dualrgb(struct vidinfo *priv, unsigned int enabled)
+struct exynos_fb_priv {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int dp_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+	unsigned int logo_on;
+	unsigned int logo_width;
+	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
+	unsigned long logo_addr;
+	unsigned int rgb_mode;
+	unsigned int resolution;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+	struct exynos_fb *reg;
+	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
+};
+
+static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -52,7 +117,7 @@ static void exynos_fimd_set_dualrgb(struct vidinfo *priv, unsigned int enabled)
 	writel(cfg, &reg->dualrgb);
 }
 
-static void exynos_fimd_set_dp_clkcon(struct vidinfo *priv,
+static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv,
 				      unsigned int enabled)
 {
 	struct exynos_fb *reg = priv->reg;
@@ -64,7 +129,8 @@ static void exynos_fimd_set_dp_clkcon(struct vidinfo *priv,
 	writel(cfg, &reg->dp_mie_clkcon);
 }
 
-static void exynos_fimd_set_par(struct vidinfo *priv, unsigned int win_id)
+static void exynos_fimd_set_par(struct exynos_fb_priv *priv,
+				unsigned int win_id)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -117,7 +183,7 @@ static void exynos_fimd_set_par(struct vidinfo *priv, unsigned int win_id)
 			EXYNOS_VIDOSD(win_id));
 }
 
-static void exynos_fimd_set_buffer_address(struct vidinfo *priv,
+static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv,
 					   unsigned int win_id,
 					   ulong lcd_base_addr)
 {
@@ -125,7 +191,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *priv,
 	unsigned long start_addr, end_addr;
 
 	start_addr = lcd_base_addr;
-	end_addr = start_addr + ((priv->vl_col * (NBITS(priv->vl_bpix) / 8)) *
+	end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) *
 				priv->vl_row);
 
 	writel(start_addr, (unsigned int)&reg->vidw00add0b0 +
@@ -134,7 +200,7 @@ static void exynos_fimd_set_buffer_address(struct vidinfo *priv,
 			EXYNOS_BUFFER_OFFSET(win_id));
 }
 
-static void exynos_fimd_set_clock(struct vidinfo *priv)
+static void exynos_fimd_set_clock(struct exynos_fb_priv *priv)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0, div = 0, remainder, remainder_div;
@@ -188,7 +254,7 @@ static void exynos_fimd_set_clock(struct vidinfo *priv)
 	writel(cfg, &reg->vidcon0);
 }
 
-void exynos_set_trigger(struct vidinfo *priv)
+void exynos_set_trigger(struct exynos_fb_priv *priv)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -200,7 +266,7 @@ void exynos_set_trigger(struct vidinfo *priv)
 	writel(cfg, &reg->trigcon);
 }
 
-int exynos_is_i80_frame_done(struct vidinfo *priv)
+int exynos_is_i80_frame_done(struct exynos_fb_priv *priv)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -215,7 +281,7 @@ int exynos_is_i80_frame_done(struct vidinfo *priv)
 	return status;
 }
 
-static void exynos_fimd_lcd_on(struct vidinfo *priv)
+static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -226,7 +292,8 @@ static void exynos_fimd_lcd_on(struct vidinfo *priv)
 	writel(cfg, &reg->vidcon0);
 }
 
-static void exynos_fimd_window_on(struct vidinfo *priv, unsigned int win_id)
+static void exynos_fimd_window_on(struct exynos_fb_priv *priv,
+				  unsigned int win_id)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -243,7 +310,7 @@ static void exynos_fimd_window_on(struct vidinfo *priv, unsigned int win_id)
 	writel(cfg, &reg->winshmap);
 }
 
-void exynos_fimd_lcd_off(struct vidinfo *priv)
+void exynos_fimd_lcd_off(struct exynos_fb_priv *priv)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -253,7 +320,7 @@ void exynos_fimd_lcd_off(struct vidinfo *priv)
 	writel(cfg, &reg->vidcon0);
 }
 
-void exynos_fimd_window_off(struct vidinfo *priv, unsigned int win_id)
+void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id)
 {
 	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0;
@@ -307,24 +374,16 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address)
+void exynos_fimd_lcd_init(struct udevice *dev)
 {
-	struct exynos_fb *reg;
+	struct exynos_fb_priv *priv = dev_get_priv(dev);
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct exynos_fb *reg = priv->reg;
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
 	unsigned int node;
 
-	node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0)
-		debug("exynos_fb: Can't get device node for fimd\n");
-
-	reg = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node,
-							"reg");
-	if (reg == NULL)
-		debug("Can't get the FIMD base address\n");
-	priv->reg = reg;
-
+	node = dev->of_offset;
 	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
 		exynos_fimd_disable_sysmmu();
 
@@ -387,13 +446,13 @@ void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address)
 	exynos_fimd_set_par(priv, priv->win_id);
 
 	/* set memory address */
-	exynos_fimd_set_buffer_address(priv, priv->win_id, lcd_base_address);
+	exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base);
 
 	/* set buffer size */
 	cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
-			NBITS(priv->vl_bpix) / 8) |
+			VNBITS(priv->vl_bpix) / 8) |
 		EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
-			NBITS(priv->vl_bpix) / 8) |
+			VNBITS(priv->vl_bpix) / 8) |
 		EXYNOS_VIDADDR_OFFSIZE(0) |
 		EXYNOS_VIDADDR_OFFSIZE_E(0);
 
@@ -415,26 +474,9 @@ void exynos_fimd_lcd_init(struct vidinfo *priv, ulong lcd_base_address)
 	exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
 }
 
-unsigned long exynos_fimd_calc_fbsize(struct vidinfo *priv)
-{
-	return priv->vl_col * priv->vl_row * (NBITS(priv->vl_bpix) / 8);
-}
-
-ushort *configuration_get_cmap(void)
-{
-#if defined(CONFIG_LCD_LOGO)
-	return bmp_logo_palette;
-#else
-	return NULL;
-#endif
-}
-
-static void exynos_lcd_init(struct vidinfo *vid, ulong lcd_base)
+unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
 {
-	exynos_fimd_lcd_init(vid, lcd_base);
-
-	/* Enable flushing after LCD writes if requested */
-	lcd_set_flush_dcache(1);
+	return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
 }
 
 __weak void exynos_cfg_lcd_gpio(void)
@@ -470,217 +512,242 @@ __weak int exynos_lcd_misc_init(struct vidinfo *vid)
 	return 0;
 }
 
-static void lcd_panel_on(struct vidinfo *vid)
+int exynos_fb_ofdata_to_platdata(struct udevice *dev)
 {
-	struct gpio_desc pwm_out_gpio;
-	struct gpio_desc bl_en_gpio;
-	unsigned int node;
-
-	udelay(vid->init_delay);
-
-	exynos_backlight_reset();
-
-	exynos_cfg_lcd_gpio();
-
-	exynos_lcd_power_on();
-
-	udelay(vid->power_on_delay);
-
-	if (vid->dp_enabled)
-		exynos_init_dp();
-
-	exynos_reset_lcd();
-
-	udelay(vid->reset_delay);
-
-	exynos_backlight_on(1);
-
-	node = fdtdec_next_compatible(gd->fdt_blob, 0,
-						COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0) {
-		debug("FIMD: Can't get device node for FIMD\n");
-		return;
-	}
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
-				   0, &pwm_out_gpio,
-				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
-				   &bl_en_gpio,
-				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-	exynos_cfg_ldo();
+	struct exynos_fb_priv *priv = dev_get_priv(dev);
+	unsigned int node = dev->of_offset;
+	const void *blob = gd->fdt_blob;
+	fdt_addr_t addr;
 
-	exynos_enable_ldo(1);
-
-	if (vid->mipi_enabled)
-		exynos_mipi_dsi_init(panel_info.dsim_platform_data_dt);
-}
-
-int exynos_lcd_early_init(const void *blob)
-{
-	unsigned int node;
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0) {
-		debug("exynos_fb: Can't get device node for fimd\n");
-		return -ENODEV;
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		debug("Can't get the FIMD base address\n");
+		return -EINVAL;
 	}
+	priv->reg = (struct exynos_fb *)addr;
 
-	panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
-	if (panel_info.vl_col == 0) {
+	priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
+	if (priv->vl_col == 0) {
 		debug("Can't get XRES\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
-	if (panel_info.vl_row == 0) {
+	priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
+	if (priv->vl_row == 0) {
 		debug("Can't get YRES\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_width = fdtdec_get_int(blob, node,
+	priv->vl_width = fdtdec_get_int(blob, node,
 						"samsung,vl-width", 0);
 
-	panel_info.vl_height = fdtdec_get_int(blob, node,
+	priv->vl_height = fdtdec_get_int(blob, node,
 						"samsung,vl-height", 0);
 
-	panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
-	if (panel_info.vl_freq == 0) {
+	priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
+	if (priv->vl_freq == 0) {
 		debug("Can't get refresh rate\n");
 		return -ENXIO;
 	}
 
 	if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
-		panel_info.vl_clkp = CONFIG_SYS_LOW;
+		priv->vl_clkp = VIDEO_ACTIVE_LOW;
 
 	if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
-		panel_info.vl_oep = CONFIG_SYS_LOW;
+		priv->vl_oep = VIDEO_ACTIVE_LOW;
 
 	if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
-		panel_info.vl_hsp = CONFIG_SYS_LOW;
+		priv->vl_hsp = VIDEO_ACTIVE_LOW;
 
 	if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
-		panel_info.vl_vsp = CONFIG_SYS_LOW;
+		priv->vl_vsp = VIDEO_ACTIVE_LOW;
 
 	if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
-		panel_info.vl_dp = CONFIG_SYS_LOW;
+		priv->vl_dp = VIDEO_ACTIVE_LOW;
 
-	panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
-	if (panel_info.vl_bpix == 0) {
+	priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
+	if (priv->vl_bpix == 0) {
 		debug("Can't get bits per pixel\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
-	if (panel_info.vl_hspw == 0) {
+	priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
+	if (priv->vl_hspw == 0) {
 		debug("Can't get hsync width\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
-	if (panel_info.vl_hfpd == 0) {
+	priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
+	if (priv->vl_hfpd == 0) {
 		debug("Can't get right margin\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
+	priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node,
 							"samsung,vl-hbpd", 0);
-	if (panel_info.vl_hbpd == 0) {
+	if (priv->vl_hbpd == 0) {
 		debug("Can't get left margin\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
+	priv->vl_vspw = (u_char)fdtdec_get_int(blob, node,
 							"samsung,vl-vspw", 0);
-	if (panel_info.vl_vspw == 0) {
+	if (priv->vl_vspw == 0) {
 		debug("Can't get vsync width\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_vfpd = fdtdec_get_int(blob, node,
+	priv->vl_vfpd = fdtdec_get_int(blob, node,
 							"samsung,vl-vfpd", 0);
-	if (panel_info.vl_vfpd == 0) {
+	if (priv->vl_vfpd == 0) {
 		debug("Can't get lower margin\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
-	if (panel_info.vl_vbpd == 0) {
+	priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
+	if (priv->vl_vbpd == 0) {
 		debug("Can't get upper margin\n");
 		return -ENXIO;
 	}
 
-	panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
+	priv->vl_cmd_allow_len = fdtdec_get_int(blob, node,
 						"samsung,vl-cmd-allow-len", 0);
 
-	panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
-	panel_info.init_delay = fdtdec_get_int(blob, node,
+	priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
+	priv->init_delay = fdtdec_get_int(blob, node,
 						"samsung,init-delay", 0);
-	panel_info.power_on_delay = fdtdec_get_int(blob, node,
+	priv->power_on_delay = fdtdec_get_int(blob, node,
 						"samsung,power-on-delay", 0);
-	panel_info.reset_delay = fdtdec_get_int(blob, node,
+	priv->reset_delay = fdtdec_get_int(blob, node,
 						"samsung,reset-delay", 0);
-	panel_info.interface_mode = fdtdec_get_int(blob, node,
+	priv->interface_mode = fdtdec_get_int(blob, node,
 						"samsung,interface-mode", 0);
-	panel_info.mipi_enabled = fdtdec_get_int(blob, node,
+	priv->mipi_enabled = fdtdec_get_int(blob, node,
 						"samsung,mipi-enabled", 0);
-	panel_info.dp_enabled = fdtdec_get_int(blob, node,
+	priv->dp_enabled = fdtdec_get_int(blob, node,
 						"samsung,dp-enabled", 0);
-	panel_info.cs_setup = fdtdec_get_int(blob, node,
+	priv->cs_setup = fdtdec_get_int(blob, node,
 						"samsung,cs-setup", 0);
-	panel_info.wr_setup = fdtdec_get_int(blob, node,
+	priv->wr_setup = fdtdec_get_int(blob, node,
 						"samsung,wr-setup", 0);
-	panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
-	panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
+	priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
+	priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
 
-	panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
-	if (panel_info.logo_on) {
-		panel_info.logo_width = fdtdec_get_int(blob, node,
+	priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
+	if (priv->logo_on) {
+		priv->logo_width = fdtdec_get_int(blob, node,
 						"samsung,logo-width", 0);
-		panel_info.logo_height = fdtdec_get_int(blob, node,
+		priv->logo_height = fdtdec_get_int(blob, node,
 						"samsung,logo-height", 0);
-		panel_info.logo_addr = fdtdec_get_int(blob, node,
+		priv->logo_addr = fdtdec_get_int(blob, node,
 						"samsung,logo-addr", 0);
 	}
 
-	panel_info.rgb_mode = fdtdec_get_int(blob, node,
+	priv->rgb_mode = fdtdec_get_int(blob, node,
 						"samsung,rgb-mode", 0);
-	panel_info.pclk_name = fdtdec_get_int(blob, node,
+	priv->pclk_name = fdtdec_get_int(blob, node,
 						"samsung,pclk-name", 0);
-	panel_info.sclk_div = fdtdec_get_int(blob, node,
+	priv->sclk_div = fdtdec_get_int(blob, node,
 						"samsung,sclk-div", 0);
-	panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
+	priv->dual_lcd_enabled = fdtdec_get_int(blob, node,
 						"samsung,dual-lcd-enabled", 0);
 
 	return 0;
 }
 
-void lcd_ctrl_init(void *lcdbase)
+static int exynos_fb_probe(struct udevice *dev)
 {
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct exynos_fb_priv *priv = dev_get_priv(dev);
+	struct udevice *panel, *bridge;
+	struct udevice *dp;
+	int ret;
+
+	debug("%s: start\n", __func__);
 	set_system_display_ctrl();
 	set_lcd_clk();
 
 #ifdef CONFIG_EXYNOS_MIPI_DSIM
 	exynos_init_dsim_platform_data(&panel_info);
 #endif
-	exynos_lcd_misc_init(&panel_info);
+	exynos_fimd_lcd_init(dev);
 
-	exynos_lcd_init(&panel_info, (ulong)lcdbase);
-}
+	ret = uclass_first_device(UCLASS_PANEL, &panel);
+	if (ret) {
+		printf("LCD panel failed to probe\n");
+		return ret;
+	}
+	if (!panel) {
+		printf("LCD panel not found\n");
+		return -ENODEV;
+	}
 
-void lcd_enable(void)
-{
-	if (panel_info.logo_on) {
-		memset((void *)gd->fb_base, 0,
-		       panel_info.vl_width * panel_info.vl_height *
-				(NBITS(panel_info.vl_bpix) >> 3));
+	ret = uclass_first_device(UCLASS_DISPLAY, &dp);
+	if (ret) {
+		debug("%s: Display device error %d\n", __func__, ret);
+		return ret;
+	}
+	if (!dev) {
+		debug("%s: Display device missing\n", __func__);
+		return -ENODEV;
+	}
+	ret = display_enable(dp, 18, NULL);
+	if (ret) {
+		debug("%s: Display enable error %d\n", __func__, ret);
+		return ret;
 	}
 
-	lcd_panel_on(&panel_info);
+	/* backlight / pwm */
+	ret = panel_enable_backlight(panel);
+	if (ret) {
+		debug("%s: backlight error: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
+	if (!ret)
+		ret = video_bridge_set_backlight(bridge, 80);
+	if (ret) {
+		debug("%s: No video bridge, or no backlight on bridge\n",
+		      __func__);
+		exynos_pinmux_config(PERIPH_ID_PWM0, 0);
+	}
+
+	uc_priv->xsize = priv->vl_col;
+	uc_priv->ysize = priv->vl_row;
+	uc_priv->bpix = priv->vl_bpix;
+
+	/* Enable flushing after LCD writes if requested */
+	video_set_flush_dcache(dev, true);
+
+	return 0;
 }
 
-/* dummy function */
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+static int exynos_fb_bind(struct udevice *dev)
 {
-	return;
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+	/* This is the maximum panel size we expect to see */
+	plat->size = 1920 * 1080 * 2;
+
+	return 0;
 }
+
+static const struct video_ops exynos_fb_ops = {
+};
+
+static const struct udevice_id exynos_fb_ids[] = {
+	{ .compatible = "samsung,exynos-fimd" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_fb) = {
+	.name	= "exynos_fb",
+	.id	= UCLASS_VIDEO,
+	.of_match = exynos_fb_ids,
+	.ops	= &exynos_fb_ops,
+	.bind	= exynos_fb_bind,
+	.probe	= exynos_fb_probe,
+	.ofdata_to_platdata	= exynos_fb_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_fb_priv),
+};
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 6219300..b2fe345 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -88,6 +88,8 @@ static const struct panel_ops simple_panel_ops = {
 static const struct udevice_id simple_panel_ids[] = {
 	{ .compatible = "simple-panel" },
 	{ .compatible = "auo,b133xtn01" },
+	{ .compatible = "auo,b116xw03" },
+	{ .compatible = "auo,b133htn01" },
 	{ }
 };
 
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index b2ff4dd..311fd09 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -124,7 +124,6 @@
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
-#define CONFIG_I2C_EDID
 
 /* SPI */
 #ifdef CONFIG_SPI_FLASH
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index 8b61a52..3d81f94 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h
@@ -13,8 +13,8 @@
 #undef EXYNOS_DEVICE_SETTINGS
 #define EXYNOS_DEVICE_SETTINGS \
 		"stdin=serial,cros-ec-keyb\0" \
-		"stdout=serial,lcd\0" \
-		"stderr=serial,lcd\0"
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
 
 #define CONFIG_EXYNOS5_DT
 
@@ -32,6 +32,7 @@
 #define CONFIG_EXYNOS_FB
 #define CONFIG_EXYNOS_DP
 #define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
 #endif
 
 /* Enable keyboard */
-- 
cgit v0.10.2


From f4f2fce70ccf793b10a59e48eb12fd8daa0b1f34 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 21 Feb 2016 21:09:02 -0700
Subject: exynos: video: Drop old unused code

Now that we are using driver model, we can drop the weak functions and LCD
init in the board file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 0dcea71..2e3b16d 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -147,159 +147,6 @@ int board_get_revision(void)
 	return 0;
 }
 
-#ifdef CONFIG_LCD
-
-static int board_dp_bridge_init(struct udevice *dev)
-{
-	const int max_tries = 10;
-	int num_tries;
-	int ret;
-
-	debug("%s\n", __func__);
-	ret = video_bridge_attach(dev);
-	if (ret) {
-		debug("video bridge init failed: %d\n", ret);
-		return ret;
-	}
-
-	/*
-	 * We need to wait for 90ms after bringing up the bridge since there
-	 * is a phantom "high" on the HPD chip during its bootup.  The phantom
-	 * high comes within 7ms of de-asserting PD and persists for at least
-	 * 15ms.  The real high comes roughly 50ms after PD is de-asserted. The
-	 * phantom high makes it hard for us to know when the NXP chip is up.
-	 */
-	mdelay(90);
-
-	for (num_tries = 0; num_tries < max_tries; num_tries++) {
-		/* Check HPD. If it's high, or we don't have it, all is well */
-		ret = video_bridge_check_attached(dev);
-		if (!ret || ret == -ENOENT)
-			return 0;
-
-		debug("%s: eDP bridge failed to come up; try %d of %d\n",
-		      __func__, num_tries, max_tries);
-	}
-
-	/* Immediately go into bridge reset if the hp line is not high */
-	return -EIO;
-}
-
-static int board_dp_bridge_setup(const void *blob)
-{
-	const int max_tries = 2;
-	int num_tries;
-	struct udevice *dev;
-	int ret;
-
-	/* Configure I2C registers for Parade bridge */
-	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
-	if (ret) {
-		debug("video bridge init failed: %d\n", ret);
-		return ret;
-	}
-
-	if (strncmp(dev->driver->name, "parade", 6)) {
-		/* Mux HPHPD to the special hotplug detect mode */
-		exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
-	}
-
-	for (num_tries = 0; num_tries < max_tries; num_tries++) {
-		ret = board_dp_bridge_init(dev);
-		if (!ret)
-			return 0;
-		if (num_tries == max_tries - 1)
-			break;
-
-		/*
-		* If we're here, the bridge chip failed to initialise.
-		* Power down the bridge in an attempt to reset.
-		*/
-		video_bridge_set_active(dev, false);
-
-		/*
-		* Arbitrarily wait 300ms here with DP_N low.  Don't know for
-		* sure how long we should wait, but we're being paranoid.
-		*/
-		mdelay(300);
-	}
-
-	return ret;
-}
-
-void exynos_cfg_lcd_gpio(void)
-{
-	/* For Backlight */
-	gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
-	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
-	gpio_set_value(EXYNOS5_GPIO_B20, 1);
-}
-
-static int board_dp_set_backlight(int percent)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
-	if (!ret)
-		ret = video_bridge_set_backlight(dev, percent);
-
-	return ret;
-}
-
-void exynos_backlight_on(unsigned int on)
-{
-	struct udevice *dev;
-	int ret;
-
-	debug("%s(%u)\n", __func__, on);
-	if (!on)
-		return;
-
-	ret = regulator_get_by_platname("vcd_led", &dev);
-	if (!ret)
-		ret = regulator_set_enable(dev, true);
-	if (ret)
-		debug("Failed to enable backlight: ret=%d\n", ret);
-
-	/* T5 in the LCD timing spec (defined as > 10ms) */
-	mdelay(10);
-
-	/* board_dp_backlight_pwm */
-	gpio_direction_output(EXYNOS5_GPIO_B20, 1);
-
-	/* T6 in the LCD timing spec (defined as > 10ms) */
-	mdelay(10);
-
-	/* try to set the backlight in the bridge registers */
-	ret = board_dp_set_backlight(80);
-
-	/* if we have no bridge or it does not support backlight, use a GPIO */
-	if (ret == -ENODEV || ret == -ENOSYS) {
-		gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
-		gpio_direction_output(EXYNOS5_GPIO_X30, 1);
-	}
-}
-
-void exynos_lcd_power_on(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	debug("%s\n", __func__);
-	ret = regulator_get_by_platname("lcd_vdd", &dev);
-	if (!ret)
-		ret = regulator_set_enable(dev, true);
-	if (ret)
-		debug("Failed to enable LCD panel: ret=%d\n", ret);
-
-	ret = board_dp_bridge_setup(gd->fdt_blob);
-	if (ret && ret != -ENODEV)
-		printf("LCD bridge failed to enable: %d\n", ret);
-}
-
-#endif
-
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
 	.maximum_speed = USB_SPEED_SUPER,
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
index c8fef63..97228cd 100644
--- a/drivers/video/exynos/exynos_fb.c
+++ b/drivers/video/exynos/exynos_fb.c
@@ -479,39 +479,6 @@ unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
 	return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
 }
 
-__weak void exynos_cfg_lcd_gpio(void)
-{
-}
-
-__weak void exynos_backlight_on(unsigned int onoff)
-{
-}
-
-__weak void exynos_reset_lcd(void)
-{
-}
-
-__weak void exynos_lcd_power_on(void)
-{
-}
-
-__weak void exynos_cfg_ldo(void)
-{
-}
-
-__weak void exynos_enable_ldo(unsigned int onoff)
-{
-}
-
-__weak void exynos_backlight_reset(void)
-{
-}
-
-__weak int exynos_lcd_misc_init(struct vidinfo *vid)
-{
-	return 0;
-}
-
 int exynos_fb_ofdata_to_platdata(struct udevice *dev)
 {
 	struct exynos_fb_priv *priv = dev_get_priv(dev);
diff --git a/drivers/video/exynos/exynos_fb.h b/drivers/video/exynos/exynos_fb.h
deleted file mode 100644
index f59cce0..0000000
--- a/drivers/video/exynos/exynos_fb.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EXYNOS_FB_H_
-#define _EXYNOS_FB_H_
-
-#include <asm/arch/fb.h>
-
-#define MAX_CLOCK	(86 * 1000000)
-
-enum exynos_cpu_auto_cmd_rate {
-	DISABLE_AUTO_FRM,
-	PER_TWO_FRM,
-	PER_FOUR_FRM,
-	PER_SIX_FRM,
-	PER_EIGHT_FRM,
-	PER_TEN_FRM,
-	PER_TWELVE_FRM,
-	PER_FOURTEEN_FRM,
-	PER_SIXTEEN_FRM,
-	PER_EIGHTEEN_FRM,
-	PER_TWENTY_FRM,
-	PER_TWENTY_TWO_FRM,
-	PER_TWENTY_FOUR_FRM,
-	PER_TWENTY_SIX_FRM,
-	PER_TWENTY_EIGHT_FRM,
-	PER_THIRTY_FRM,
-};
-
-void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
-	unsigned long palette_size);
-void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address);
-unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid);
-
-#endif
-- 
cgit v0.10.2


From 0bd20207ab2d874842161cab37c213310d785b24 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:13:57 +0900
Subject: ARM: uniphier: disable cache in SPL of PH1-LD20

The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table.  Disable D-cache and MMU
before jumping to U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 660ad45..7f66053 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
+	dcache_disable();
+
 	return 0;
 }
-- 
cgit v0.10.2


From 6a555b214b9cf999389fc675689ab3909b949ddf Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:13:58 +0900
Subject: ARM: uniphier: clean up boot mode tables

Tidy up alignment of open parentheses.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
index b092c1b..96a1270 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -43,7 +43,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
 	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
 	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
-	{BOOT_DEVICE_NOR,  "NOR Boot (XECS1)"},
+	{BOOT_DEVICE_NOR,  "NOR  (XECS1)"},
 };
 
 static int get_boot_mode_sel(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
index 0597618..b066ed9 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
@@ -36,14 +36,14 @@ struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (3.3V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NOR,  "NOR Boot"},
+	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
 };
 
 static int get_boot_mode_sel(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
index f9726f1..450c43b 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
@@ -37,7 +37,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128MB, Addr 5)"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
index 4b06f74..20ff773 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
@@ -32,17 +32,17 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 4)"},
-	{BOOT_DEVICE_SPI,  "SPI 3Byte CS0"},
-	{BOOT_DEVICE_SPI,  "SPI 4Byte CS0"},
-	{BOOT_DEVICE_SPI,  "SPI 3Byte CS1"},
-	{BOOT_DEVICE_SPI,  "SPI 4Byte CS1"},
-	{BOOT_DEVICE_SPI,  "SPI 4Byte CS0"},
-	{BOOT_DEVICE_SPI,  "SPI 3Byte CS0"},
+	{BOOT_DEVICE_SPI,  "SPI  (3Byte CS0)"},
+	{BOOT_DEVICE_SPI,  "SPI  (4Byte CS0)"},
+	{BOOT_DEVICE_SPI,  "SPI  (3Byte CS1)"},
+	{BOOT_DEVICE_SPI,  "SPI  (4Byte CS1)"},
+	{BOOT_DEVICE_SPI,  "SPI  (4Byte CS0)"},
+	{BOOT_DEVICE_SPI,  "SPI  (3Byte CS0)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 };
 
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
index a4a3c47..ddf8259 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
@@ -12,7 +12,7 @@
 #include "boot-device.h"
 
 static struct boot_device_info boot_device_table[] = {
-	{BOOT_DEVICE_NOR,  "NOR boot"},
+	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
 	{BOOT_DEVICE_NONE, "External Master"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
-- 
cgit v0.10.2


From 0586e22783ca3d575ad86b1a0656875ee071489a Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:13:59 +0900
Subject: ARM: uniphier: rename umc-ld20-regs.h to umc64-regs.h

This header will be shared between PH1-LD11 and PH1-LD20
(and hopefully new ARMv8 SoCs developed in the future),
so umc64-regs.h would be a better fit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
deleted file mode 100644
index 46e513c..0000000
--- a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- */
-
-#ifndef UMC_LD20_REGS_H
-#define UMC_LD20_REGS_H
-
-#define UMC_CMDCTLA		0x00000000
-#define UMC_CMDCTLB		0x00000004
-#define UMC_CMDCTLC		0x00000008
-#define UMC_INITCTLA		0x00000020
-#define UMC_INITCTLB		0x00000024
-#define UMC_INITCTLC		0x00000028
-#define UMC_DRMMR0		0x00000030
-#define UMC_DRMMR1		0x00000034
-#define UMC_DRMMR2		0x00000038
-#define UMC_DRMMR3		0x0000003C
-#define UMC_INITSET		0x00000040
-#define UMC_INITSTAT		0x00000044
-#define UMC_CMDCTLE		0x00000050
-#define UMC_SPCSETB		0x00000084
-#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
-#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
-#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
-#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
-#define UMC_ACSCTLA		0x000000C0
-#define UMC_ACSSETA		0x000000C4
-#define UMC_MEMCONF0A		0x00000200
-#define UMC_MEMCONF0B		0x00000204
-#define UMC_MEMCONFCH		0x00000240
-#define UMC_MEMMAPSET		0x00000250
-#define UMC_FLOWCTLA		0x00000400
-#define UMC_FLOWCTLB		0x00000404
-#define UMC_FLOWCTLC		0x00000408
-#define UMC_FLOWCTLG		0x00000508
-#define UMC_RDATACTL_D0		0x00000600
-#define UMC_WDATACTL_D0		0x00000604
-#define UMC_RDATACTL_D1		0x00000608
-#define UMC_WDATACTL_D1		0x0000060C
-#define UMC_DATASET		0x00000610
-#define UMC_ODTCTL_D0		0x00000618
-#define UMC_ODTCTL_D1		0x0000061C
-#define UMC_RESPCTL		0x00000624
-#define UMC_DIRECTBUSCTRLA	0x00000680
-#define UMC_DCCGCTL		0x00000720
-#define UMC_DICGCTLA		0x00000724
-#define UMC_DICGCTLB		0x00000728
-#define UMC_ERRMASKA		0x00000958
-#define UMC_ERRMASKB		0x0000095C
-#define UMC_BSICMAPSET		0x00000988
-#define UMC_DIOCTLA		0x00000C00
-#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
-#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
-#define UMC_DFISTCTLC		0x00000C18
-#define UMC_DFICUPDCTLA		0x00000C20
-#define UMC_DFIPUPDCTLA		0x00000C30
-#define UMC_DFICSOVRRD		0x00000C84
-#define UMC_DFITURNOFF          0x00000C88
-
-/* UM registers */
-#define UMC_MBUS0		0x00080004
-#define UMC_MBUS1		0x00081004
-#define UMC_MBUS2		0x00082004
-#define UMC_MBUS3		0x00000C78
-#define UMC_MBUS4		0x00000CF8
-#define UMC_MBUS5		0x00000E78
-#define UMC_MBUS6		0x00000EF8
-#define UMC_MBUS7		0x00001278
-#define UMC_MBUS8		0x000012F8
-#define UMC_MBUS9		0x00002478
-#define UMC_MBUS10		0x000024F8
-
-#endif /* UMC_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index 4614dac..33cd487 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -15,7 +15,7 @@
 
 #include "../init.h"
 #include "ddrphy-ld20-regs.h"
-#include "umc-ld20-regs.h"
+#include "umc64-regs.h"
 
 #define DRAM_CH_NR	3
 
diff --git a/arch/arm/mach-uniphier/dram/umc64-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h
new file mode 100644
index 0000000..46e513c
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc64-regs.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef UMC_LD20_REGS_H
+#define UMC_LD20_REGS_H
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_CMDCTLC		0x00000008
+#define UMC_INITCTLA		0x00000020
+#define UMC_INITCTLB		0x00000024
+#define UMC_INITCTLC		0x00000028
+#define UMC_DRMMR0		0x00000030
+#define UMC_DRMMR1		0x00000034
+#define UMC_DRMMR2		0x00000038
+#define UMC_DRMMR3		0x0000003C
+#define UMC_INITSET		0x00000040
+#define UMC_INITSTAT		0x00000044
+#define UMC_CMDCTLE		0x00000050
+#define UMC_SPCSETB		0x00000084
+#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
+#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
+#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
+#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
+#define UMC_ACSCTLA		0x000000C0
+#define UMC_ACSSETA		0x000000C4
+#define UMC_MEMCONF0A		0x00000200
+#define UMC_MEMCONF0B		0x00000204
+#define UMC_MEMCONFCH		0x00000240
+#define UMC_MEMMAPSET		0x00000250
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_ODTCTL_D0		0x00000618
+#define UMC_ODTCTL_D1		0x0000061C
+#define UMC_RESPCTL		0x00000624
+#define UMC_DIRECTBUSCTRLA	0x00000680
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_ERRMASKA		0x00000958
+#define UMC_ERRMASKB		0x0000095C
+#define UMC_BSICMAPSET		0x00000988
+#define UMC_DIOCTLA		0x00000C00
+#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
+#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
+#define UMC_DFISTCTLC		0x00000C18
+#define UMC_DFICUPDCTLA		0x00000C20
+#define UMC_DFIPUPDCTLA		0x00000C30
+#define UMC_DFICSOVRRD		0x00000C84
+#define UMC_DFITURNOFF          0x00000C88
+
+/* UM registers */
+#define UMC_MBUS0		0x00080004
+#define UMC_MBUS1		0x00081004
+#define UMC_MBUS2		0x00082004
+#define UMC_MBUS3		0x00000C78
+#define UMC_MBUS4		0x00000CF8
+#define UMC_MBUS5		0x00000E78
+#define UMC_MBUS6		0x00000EF8
+#define UMC_MBUS7		0x00001278
+#define UMC_MBUS8		0x000012F8
+#define UMC_MBUS9		0x00002478
+#define UMC_MBUS10		0x000024F8
+
+#endif /* UMC_LD20_REGS_H */
-- 
cgit v0.10.2


From 7381db86a90bb36d6e615da835ae6964af68f260 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:14:00 +0900
Subject: ARM: uniphier: rename UMC register macros of PH1-LD20

Correct some register names.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index 33cd487..186a398 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -200,9 +200,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
 	writel(umc_dataset[freq], dc_base + UMC_DATASET);
 
 	writel(0x00400020, dc_base + UMC_DCCGCTL);
-	writel(0x00000003, dc_base + UMC_ACSCTLA);
+	writel(0x00000003, dc_base + UMC_ACSSETA);
 	writel(0x00000103, dc_base + UMC_FLOWCTLG);
-	writel(0x00010200, dc_base + UMC_ACSSETA);
+	writel(0x00010200, dc_base + UMC_ACSSETB);
 
 	writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
 	writel(0x00004444, dc_base + UMC_FLOWCTLC);
diff --git a/arch/arm/mach-uniphier/dram/umc64-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h
index 46e513c..1b6a838 100644
--- a/arch/arm/mach-uniphier/dram/umc64-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc64-regs.h
@@ -23,8 +23,8 @@
 #define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
 #define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
 #define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
-#define UMC_ACSCTLA		0x000000C0
-#define UMC_ACSSETA		0x000000C4
+#define UMC_ACSSETA		0x000000C0
+#define UMC_ACSSETB		0x000000C4
 #define UMC_MEMCONF0A		0x00000200
 #define UMC_MEMCONF0B		0x00000204
 #define UMC_MEMCONFCH		0x00000240
-- 
cgit v0.10.2


From 667dbcd01d35a69a0a01ecd09b9f18d9aa0efe72 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:14:01 +0900
Subject: ARM: uniphier: add PH1-LD11 SoC support

This is a low-cost ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 87d1675..ae763ad 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
 	bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
 	select CPU_V7
 
+config ARCH_UNIPHIER_LD11
+	bool "UniPhier PH1-LD11 SoC"
+	select ARM64
+	select SPL_SEPARATE_BSS
+
 config ARCH_UNIPHIER_LD20
 	bool "UniPhier PH1-LD20 SoC"
 	select ARM64
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 2a7ae1b..f853701 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -62,6 +62,13 @@ int board_early_init_f(void)
 		uniphier_pxs2_clk_init();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	case SOC_UNIPHIER_LD11:
+		uniphier_ld20_pin_init();
+		led_puts("U1");
+		uniphier_ld11_clk_init();
+		break;
+#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	case SOC_UNIPHIER_LD20:
 		uniphier_ld20_pin_init();
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index f0547c3..ed308f3 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -165,6 +165,23 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+static const struct uniphier_board_data uniphier_ld11_data = {
+	.dram_freq = 1600,
+	.dram_nr_ch = 2,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x20000000,
+		.width = 16,
+	},
+	.dram_ch[1] = {
+		.base = 0xa0000000,
+		.size = 0x20000000,
+		.width = 16,
+	},
+};
+#endif
+
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 static const struct uniphier_board_data uniphier_ld20_data = {
 	.dram_freq = 1866,
@@ -216,6 +233,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	{ "socionext,ph1-ld11", &uniphier_ld11_data, },
+#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
 #endif
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 6cd096e..d7fefc5 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-mode-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-mode-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-mode-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= boot-mode-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
 
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index b180f44..4b744da 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -39,7 +39,8 @@ u32 spl_boot_device_raw(void)
 	case SOC_UNIPHIER_LD6B:
 		return uniphier_pxs2_boot_device();
 #endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD11:
 	case SOC_UNIPHIER_LD20:
 		return uniphier_ld20_boot_device();
 #endif
diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
index fa97dc5..a8ee382 100644
--- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
@@ -39,7 +39,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		uniphier_pxs2_boot_mode_show();
 		break;
 #endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD11:
 	case SOC_UNIPHIER_LD20:
 		uniphier_ld20_boot_mode_show();
 		break;
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 93e9d91..1428e0c 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
new file mode 100644
index 0000000..92a0733
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld11_clk_init(void)
+{
+	if (readl(SG_PINMON0) & BIT(27)) {
+		/* if booted without stand-by MPU */
+
+		writel(1, SG_ETPHYPSHUT);
+		writel(1, SG_ETPHYCNT);
+
+		udelay(1); /* wait for regulator level 1.1V -> 2.5V */
+
+		writel(3, SG_ETPHYCNT);
+		writel(3, SG_ETPHYPSHUT);
+		writel(7, SG_ETPHYCNT);
+	}
+}
diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c
index f9646c0..6ad4c76 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -45,7 +45,7 @@ int print_cpuinfo(void)
 		puts("PH1-LD6b (MN2WS0320)");
 		break;
 	case 0x31:
-		puts("PH1-LD11 ()");
+		puts("PH1-LD11 (SC1405AP1)");
 		break;
 	case 0x32:
 		puts("PH1-LD20 (SC1401AJ1)");
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 41aa53b..5b9d892 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= umc-sld8.o \
 					   ddrphy-training.o ddrphy-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= umc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= umc-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= umc-ld20.o
 
 else
diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c
new file mode 100644
index 0000000..1be18a8
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld11.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "umc64-regs.h"
+
+#define CONFIG_DDR_FREQ		1866
+
+#define DRAM_CH_NR	2
+
+enum dram_freq {
+	DRAM_FREQ_1600M,
+	DRAM_FREQ_NR,
+};
+
+enum dram_size {
+	DRAM_SZ_256M,
+	DRAM_SZ_512M,
+	DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
+static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
+static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+		       unsigned long size, int ch)
+{
+	writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+	writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+	writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+	writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
+	writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
+	writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
+
+	writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+	writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+	writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+	writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+
+	writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+	writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+
+	writel(0x00000003, dc_base + UMC_ACSSETA);
+	writel(0x00000103, dc_base + UMC_FLOWCTLG);
+	writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
+	writel(0x02020200, dc_base + UMC_SPCSETB);
+	writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+	writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
+
+	return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base,
+		       enum dram_freq freq, unsigned long size, int ch)
+{
+	void __iomem *dc_base  = umc_ch_base;
+
+	return umc_dc_init(dc_base, freq, size, ch);
+}
+
+static void um_init(void __iomem *um_base)
+{
+	writel(0x00000001, um_base + UMC_SIORST);
+	writel(0x00000001, um_base + UMC_VO0RST);
+	writel(0x00000001, um_base + UMC_VPERST);
+	writel(0x00000001, um_base + UMC_RGLRST);
+	writel(0x00000001, um_base + UMC_A2DRST);
+	writel(0x00000001, um_base + UMC_DMDRST);
+}
+
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
+{
+	void __iomem *um_base = (void __iomem *)0x5B800000;
+	void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
+	enum dram_freq freq;
+	int ch, ret;
+
+	switch (bd->dram_freq) {
+	case 1600:
+		freq = DRAM_FREQ_1600M;
+		break;
+	default:
+		pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+		return -EINVAL;
+	}
+
+	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+		unsigned long size = bd->dram_ch[ch].size;
+		unsigned int width = bd->dram_ch[ch].width;
+
+		ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
+		if (ret) {
+			pr_err("failed to initialize UMC ch%d\n", ch);
+			return ret;
+		}
+
+		umc_ch_base += 0x00200000;
+	}
+
+	um_init(um_base);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/dram/umc64-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h
index 1b6a838..860d04e 100644
--- a/arch/arm/mach-uniphier/dram/umc64-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc64-regs.h
@@ -18,6 +18,8 @@
 #define UMC_INITSET		0x00000040
 #define UMC_INITSTAT		0x00000044
 #define UMC_CMDCTLE		0x00000050
+#define UMC_CMDCTLF		0x00000054
+#define UMC_CMDCTLG		0x00000058
 #define UMC_SPCSETB		0x00000084
 #define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
 #define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
@@ -32,6 +34,7 @@
 #define UMC_FLOWCTLA		0x00000400
 #define UMC_FLOWCTLB		0x00000404
 #define UMC_FLOWCTLC		0x00000408
+#define UMC_ACFETCHCTRL		0x00000460
 #define UMC_FLOWCTLG		0x00000508
 #define UMC_RDATACTL_D0		0x00000600
 #define UMC_WDATACTL_D0		0x00000604
@@ -42,6 +45,7 @@
 #define UMC_ODTCTL_D1		0x0000061C
 #define UMC_RESPCTL		0x00000624
 #define UMC_DIRECTBUSCTRLA	0x00000680
+#define UMC_DEBUGC		0x00000718
 #define UMC_DCCGCTL		0x00000720
 #define UMC_DICGCTLA		0x00000724
 #define UMC_DICGCTLB		0x00000728
@@ -70,4 +74,12 @@
 #define UMC_MBUS9		0x00002478
 #define UMC_MBUS10		0x000024F8
 
+/* UMC1 register */
+#define UMC_SIORST		0x00000728
+#define UMC_VO0RST		0x0000073c
+#define UMC_VPERST		0x00000744
+#define UMC_RGLRST		0x00000750
+#define UMC_A2DRST		0x00000764
+#define UMC_DMDRST		0x00000770
+
 #endif /* UMC_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 9242b41..755a361 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
new file mode 100644
index 0000000..c94d83c
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL7);
+	tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
+	writel(tmp, SC_RSTCTRL7);
+
+	/* provide clocks */
+	tmp = readl(SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_PERI;
+	writel(tmp, SC_CLKCTRL4);
+
+	tmp = readl(SC_CLKCTRL7);
+	tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
+	writel(tmp, SC_CLKCTRL7);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
index a103902..7177a8c 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -3,4 +3,5 @@
 #
 
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= early-pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-pinctrl-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index ab0a68d..cba0bc9 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
@@ -81,6 +82,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
@@ -91,6 +93,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
 
 void uniphier_sld3_pin_init(void);
 void uniphier_ld4_pin_init(void);
@@ -105,6 +108,7 @@ void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
+void uniphier_ld11_clk_init(void);
 void uniphier_ld20_clk_init(void);
 
 void cci500_init(int nr_slaves);
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index b58e6c8..dcaa445 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= init-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= init-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= init-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= init-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= init-ld20.o
diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c
new file mode 100644
index 0000000..de2dc62
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ld11.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld11_init(const struct uniphier_board_data *bd)
+{
+	uniphier_sbc_init_savepin(bd);
+	uniphier_pxs2_sbc_init(bd);
+	uniphier_ld20_early_pin_init(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+
+	led_puts("L1");
+
+	uniphier_ld11_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	{
+		int res;
+
+		res = uniphier_ld11_umc_init(bd);
+		if (res < 0) {
+			while (1)
+				;
+		}
+	}
+
+	led_puts("L5");
+
+	dcache_disable();
+
+	led_puts("L6");
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index 15a53ce..77e5b99 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -55,6 +55,11 @@ void spl_board_init(void)
 		uniphier_pxs2_init(param);
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	case SOC_UNIPHIER_LD11:
+		uniphier_ld11_init(param);
+		break;
+#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	case SOC_UNIPHIER_LD20:
 		uniphier_ld20_init(param);
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index b579cb0..7f4d9f7 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pinctrl-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= pinctrl-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= pinctrl-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= pinctrl-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 38da253..ec3c22c 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o sbc-pxs2.o
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 1d71ce8..a179d61 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -59,6 +59,9 @@
 
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
 
+#define SG_ETPHYPSHUT			(SG_CTRL_BASE | 0x554)
+#define SG_ETPHYCNT			(SG_CTRL_BASE | 0x550)
+
 /* Pin Control */
 #define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
 
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
new file mode 100644
index 0000000..ffcac79
--- /dev/null
+++ b/configs/uniphier_ld11_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_LD11=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 18cb963..10fd8c2 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -104,7 +104,11 @@
 #define COUNTER_FREQUENCY			50000000
 #define CONFIG_GICV3
 #define GICD_BASE				0x5fe00000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define GICR_BASE				0x5fe40000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
 #define GICR_BASE				0x5fe80000
+#endif
 #else
 /* Time clock 1MHz */
 #define CONFIG_SYS_TIMER_RATE			1000000
@@ -270,7 +274,9 @@
 #define CONFIG_SPL_TEXT_BASE		0x00100000
 #endif
 
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_STACK		(0x30014c00)
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
 #define CONFIG_SPL_STACK		(0x3001c000)
 #else
 #define CONFIG_SPL_STACK		(0x00100000)
@@ -301,7 +307,11 @@
 #define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
 #define CONFIG_SPL_MAX_FOOTPRINT		0x10000
 #define CONFIG_SPL_MAX_SIZE			0x10000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_BSS_START_ADDR		0x30012000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
 #define CONFIG_SPL_BSS_START_ADDR		0x30016000
+#endif
 #define CONFIG_SPL_BSS_MAX_SIZE			0x2000
 
 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */
-- 
cgit v0.10.2


From ae932cf67e457a9a937a8913f2c2cf2b13b68833 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:14:02 +0900
Subject: clk: uniphier: add Media I/O clock driver support for PH1-LD11

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index a2b0e80..c6ecd11 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -165,6 +165,10 @@ static const struct udevice_id uniphier_mio_clk_match[] = {
 		.data = (ulong)&uniphier_mio_clk_data,
 	},
 	{
+		.compatible = "socionext,ph1-ld11-mioctrl",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
 		.compatible = "socionext,ph1-ld20-mioctrl",
 		.data = (ulong)&uniphier_mio_clk_data,
 	},
-- 
cgit v0.10.2


From d7e103c08f5bb29d8126eaef3b7b6d6bafacea80 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 24 May 2016 21:14:03 +0900
Subject: ARM: uniphier: add EHCI nodes for PH1-LD11

Make the USB feature really available.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index 88e7f53..b148e9f 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -49,6 +49,18 @@
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
 /* for U-Boot only */
 / {
 	soc {
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index 7d498ce..e485f90 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -190,6 +190,42 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		usb0: usb@5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 243 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&mio 3>, <&mio 6>;
+		};
+
+		usb1: usb@5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 244 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&mio 4>, <&mio 6>;
+		};
+
+		usb2: usb@5a820100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+			interrupts = <0 245 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio 5>, <&mio 6>;
+		};
+
+		mio: mioctrl@5b3e0000 {
+			compatible = "socionext,ph1-ld11-mioctrl";
+			reg = <0x5b3e0000 0x800>;
+			#clock-cells = <1>;
+		};
+
 		pinctrl: pinctrl@5f801000 {
 			compatible = "socionext,ph1-ld11-pinctrl", "syscon";
 			reg = <0x5f801000 0xe00>;
-- 
cgit v0.10.2


From 1a5f0de08e86f2f127aaac928fee5ea0f2a9236e Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:06 +0800
Subject: sunxi: make SoC variant choice mandatory

The user should always select an SoC variant to support. Not choosing
one doesn't make sense for a bootloader.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index fa78720..95500a1 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -18,7 +18,6 @@ config SUNXI_GEN_SUN6I
 
 choice
 	prompt "Sunxi SoC Variant"
-	optional
 
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
-- 
cgit v0.10.2


From a81b79950e16182862e31ad86a97b6a8a6891476 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:07 +0800
Subject: sunxi: Sort SoC variants by family (sunXi) first, chip name second

In most other places, we sort SoC descriptions by family (sunXi) first,
then by the chip name (A20).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 95500a1..49a937a 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -67,6 +67,12 @@ config MACH_SUN8I_A33
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
+config MACH_SUN8I_A83T
+	bool "sun8i (Allwinner A83T)"
+	select CPU_V7
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+
 config MACH_SUN8I_H3
 	bool "sun8i (Allwinner H3)"
 	select CPU_V7
@@ -76,22 +82,16 @@ config MACH_SUN8I_H3
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
-config MACH_SUN50I
-	bool "sun50i (Allwinner A64)"
-	select ARM64
-	select SUNXI_GEN_SUN6I
-
-config MACH_SUN8I_A83T
-	bool "sun8i (Allwinner A83T)"
-	select CPU_V7
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
 	select SUNXI_GEN_SUN6I
 
+config MACH_SUN50I
+	bool "sun50i (Allwinner A64)"
+	select ARM64
+	select SUNXI_GEN_SUN6I
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
-- 
cgit v0.10.2


From acdab175c0853ed1f389bca467765dc98f9e4bcb Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:08 +0800
Subject: sunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCs

A83T, H3, and A64 have a dedicated pin for card detect on the PF
pingroup. This is used in all designs. Set it as the default.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 49a937a..a24d5c2 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -260,6 +260,7 @@ config MMC
 
 config MMC0_CD_PIN
 	string "Card detect pin for mmc0"
+	default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
 	default ""
 	---help---
 	Set the card detect pin for mmc0, leave empty to not use cd. This
-- 
cgit v0.10.2


From 5af116b560d8a6e0b11d6239b5a8f783f9ac6fd1 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:09 +0800
Subject: sunxi: Disable VIDEO for SoCs without display support

The newer chips use a newer display pipeline, which is not supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index a24d5c2..059e914 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -419,7 +419,7 @@ config AXP_GPIO
 
 config VIDEO
 	boolean "Enable graphical uboot console on HDMI, LCD or VGA"
-	depends on !MACH_SUN8I_A83T
+	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD
-- 
cgit v0.10.2


From aa23f539c88418333fb5300051642bc9b99d17b2 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:10 +0800
Subject: power: axp221: Remove switch case to simplify axp_set_eldo

The ELDO enable bits and registers are contiguous for axp221. Instead
of a switch case testing against the index, just use the index to shift
the bit or register offset.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index cb1f88b..727ab09 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -191,33 +191,20 @@ int axp_set_eldo(int eldo_num, unsigned int mvolt)
 {
 	int ret;
 	u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
-	u8 addr, bits;
-
-	switch (eldo_num) {
-	case 3:
-		addr = AXP221_ELDO3_CTRL;
-		bits = AXP221_OUTPUT_CTRL2_ELDO3_EN;
-		break;
-	case 2:
-		addr = AXP221_ELDO2_CTRL;
-		bits = AXP221_OUTPUT_CTRL2_ELDO2_EN;
-		break;
-	case 1:
-		addr = AXP221_ELDO1_CTRL;
-		bits = AXP221_OUTPUT_CTRL2_ELDO1_EN;
-		break;
-	default:
+
+	if (eldo_num < 1 || eldo_num > 3)
 		return -EINVAL;
-	}
 
 	if (mvolt == 0)
-		return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, bits);
+		return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+				AXP221_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
 
-	ret = pmic_bus_write(addr, cfg);
+	ret = pmic_bus_write(AXP221_ELDO1_CTRL + (eldo_num - 1), cfg);
 	if (ret)
 		return ret;
 
-	return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits);
+	return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+				AXP221_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
 }
 
 int axp_init(void)
-- 
cgit v0.10.2


From a696253c1daf3424408868fc76840c83a896acfe Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:11 +0800
Subject: power: axp818: Fix typo for fldo2 Kconfig description

Description said eldo2 instead of fldo2, a copy-paste error.

Fixes: 38491d9c6515 ("power: axp818: Add support for FLDOs")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3c41bca..b365fd4 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -249,7 +249,7 @@ config AXP_FLDO1_VOLT
 	used.
 
 config AXP_FLDO2_VOLT
-	int "axp pmic eldo2 voltage"
+	int "axp pmic fldo2 voltage"
 	depends on AXP818_POWER
 	default 900 if MACH_SUN8I_A83T
 	---help---
-- 
cgit v0.10.2


From 15278ccb848dbcd8825874f943bc21afda987219 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:12 +0800
Subject: sunxi: power: axp818: Add support for switch SW

The AXP818 has a switchable output, SW. This is commonly used for
controlling power to the LCD backlight.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3cf3614..6a0a8db 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -523,6 +523,7 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
 	power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
 	power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
+	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
 #endif
 #endif
 	printf("DRAM:");
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index b365fd4..02cb8e7 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -265,6 +265,13 @@ config AXP_FLDO3_VOLT
 	Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to
 	disable fldo3.
 
+config AXP_SW_ON
+	bool "axp pmic sw on"
+	depends on AXP818_POWER
+	default n
+	---help---
+	Enable to turn on axp pmic sw.
+
 config SY8106A_VOUT1_VOLT
 	int "SY8106A pmic VOUT1 voltage"
 	depends on SY8106A_POWER
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 3ac05ff..bf6ecd6 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -225,6 +225,16 @@ int axp_set_fldo(int fldo_num, unsigned int mvolt)
 				AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
 }
 
+int axp_set_sw(bool on)
+{
+	if (on)
+		return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+					AXP818_OUTPUT_CTRL2_SW_EN);
+
+	return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+				AXP818_OUTPUT_CTRL2_SW_EN);
+}
+
 int axp_init(void)
 {
 	u8 axp_chip_id;
diff --git a/include/axp818.h b/include/axp818.h
index 5630eed..f7f343a 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -24,6 +24,7 @@
 #define AXP818_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
 #define AXP818_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
 #define AXP818_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2_SW_EN	(1 << 7)
 #define AXP818_OUTPUT_CTRL3	0x13
 #define AXP818_OUTPUT_CTRL3_FLDO1_EN	(1 << 2)
 #define AXP818_OUTPUT_CTRL3_FLDO2_EN	(1 << 3)
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index b203cc8..2ed5196 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -32,6 +32,7 @@ int axp_set_aldo4(unsigned int mvolt);
 int axp_set_dldo(int dldo_num, unsigned int mvolt);
 int axp_set_eldo(int eldo_num, unsigned int mvolt);
 int axp_set_fldo(int fldo_num, unsigned int mvolt);
+int axp_set_sw(bool on);
 int axp_init(void);
 int axp_get_sid(unsigned int *sid);
 
-- 
cgit v0.10.2


From 9850e201481dcc13db7b144c609db4480bd47543 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:13 +0800
Subject: sunxi: Enable AXP818 SW for Sinovoip BPI M3

The SW output of the PMIC supplies the ethernet PHY with power.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 13dbb98..29694ce 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -30,5 +30,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_AXP_SW_ON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
-- 
cgit v0.10.2


From 511992695de9309b53a291caa5ff9bce62d44ae4 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:14 +0800
Subject: sunxi: Implement poweroff support for axp818 pmic

Adds poweroff support for axp818 pmic.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 02cb8e7..d137536 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -44,6 +44,7 @@ config AXP221_POWER
 config AXP818_POWER
 	boolean "axp818 pmic support"
 	depends on MACH_SUN8I_A83T
+	select CMD_POWEROFF
 	---help---
 	Say y here to enable support for the axp818 pmic found on
 	A83T dev board.
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index bf6ecd6..af4d7a6 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -255,3 +255,14 @@ int axp_init(void)
 
 	return 0;
 }
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmic_bus_write(AXP818_SHUTDOWN, AXP818_SHUTDOWN_POWEROFF);
+
+	/* infinite loop during shutdown */
+	while (1) {}
+
+	/* not reached */
+	return 0;
+}
diff --git a/include/axp818.h b/include/axp818.h
index f7f343a..959774c 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -55,6 +55,9 @@
 #define AXP818_ALDO2_CTRL	0x29
 #define AXP818_ALDO3_CTRL	0x2a
 
+#define AXP818_SHUTDOWN		0x32
+#define AXP818_SHUTDOWN_POWEROFF	(1 << 7)
+
 /* For axp_gpio.c */
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
-- 
cgit v0.10.2


From 795857df413aea278af95305d4b6ffc48089d6e8 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Mon, 2 May 2016 10:28:15 +0800
Subject: sunxi: power: add AXP809 support

The A80 uses the AXP809 as its primary PMIC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index ad3d6c4..25367cf 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o
 obj-$(CONFIG_AXP152_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
+obj-$(CONFIG_AXP809_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP818_POWER)	+= pmic_bus.o
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 5b81a8d..7c57f02 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,7 @@ int pmic_bus_init(void)
 	if (!needs_init)
 		return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
 # else
@@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
 # else
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6a0a8db..103aafe 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -483,10 +483,12 @@ void sunxi_board_init(void)
 #endif
 
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-	defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+	defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed = axp_init();
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
@@ -494,11 +496,13 @@ void sunxi_board_init(void)
 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
 #endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 #endif
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 #endif
 	power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
@@ -509,11 +513,14 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
 #endif
 
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
+	defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
 	power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
+#if !defined CONFIG_AXP809_POWER
 	power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
 	power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
+#endif
 	power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
 	power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
 	power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
@@ -523,6 +530,9 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
 	power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
 	power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
+#endif
+
+#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
 #endif
 #endif
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index d137536..3c44167 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -41,6 +41,13 @@ config AXP221_POWER
 	Select this to enable support for the axp221/axp223 pmic found on most
 	A23 and A31 boards.
 
+config AXP809_POWER
+	boolean "axp809 pmic support"
+	depends on MACH_SUN9I
+	select CMD_POWEROFF
+	---help---
+	Say y here to enable support for the axp809 pmic found on A80 boards.
+
 config AXP818_POWER
 	boolean "axp818 pmic support"
 	depends on MACH_SUN8I_A83T
@@ -60,36 +67,39 @@ endchoice
 
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 3300 if AXP818_POWER
-	default 3000 if MACH_SUN6I || MACH_SUN8I
+	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
 	disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for
 	generic 3.3V IO voltage for external devices like the lcd-panal and
 	sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
-	safe battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
-	dcdc1 is used for VCC-IO, nand, usb0, sd , etc.
+	save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
+	dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally
+	powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG.
 
 config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 900 if AXP818_POWER
 	default 1400 if AXP152_POWER || AXP209_POWER
 	default 1200 if MACH_SUN6I
 	default 1100 if MACH_SUN8I
+	default 0 if MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to
 	disable dcdc2.
 	On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V.
 	On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V.
 	On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
+	On A80 boards dcdc2 powers the GPU and can be left off.
 	On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 
 config AXP_DCDC3_VOLT
 	int "axp pmic dcdc3 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
-	default 900 if AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 900 if AXP809_POWER || AXP818_POWER
 	default 1500 if AXP152_POWER
 	default 1250 if AXP209_POWER
 	default 1200 if MACH_SUN6I || MACH_SUN8I
@@ -100,51 +110,55 @@ config AXP_DCDC3_VOLT
 	should be 1.25V.
 	On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
 	On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
+	On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 	On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
 
 config AXP_DCDC4_VOLT
 	int "axp pmic dcdc4 voltage"
-	depends on AXP152_POWER || AXP221_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 1250 if AXP152_POWER
 	default 1200 if MACH_SUN6I
 	default 0 if MACH_SUN8I
+	default 900 if MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to
 	disable dcdc4.
 	On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V.
 	On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V.
 	On A23 / A33 boards dcdc4 is unused and should be disabled.
+	On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V.
 	On A83T boards dcdc4 is used for VDD-GPU.
 
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
-	depends on AXP221_POWER || AXP818_POWER
-	default 1500 if MACH_SUN6I || MACH_SUN8I
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
 	disable dcdc5.
-	On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V,
-	1.35V if DDR3L is used.
+	On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and
+	should be 1.5V, 1.35V if DDR3L is used.
 
 config AXP_ALDO1_VOLT
 	int "axp pmic (a)ldo1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0 if MACH_SUN6I
 	default 1800 if MACH_SUN8I_A83T
-	default 3000 if MACH_SUN8I
+	default 3000 if MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
 	disable aldo1.
 	On A31 boards aldo1 is often used to power the wifi module.
 	On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V.
+	On A80 boards aldo1 powers the USB hosts and should be 3.0V.
 	On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and
 	should be 1.8V.
 
 config AXP_ALDO2_VOLT
 	int "axp pmic (a)ldo2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 3000 if AXP152_POWER || AXP209_POWER
-	default 0 if MACH_SUN6I
+	default 0 if MACH_SUN6I || MACH_SUN9I
 	default 1800 if MACH_SUN8I_A83T
 	default 2500 if MACH_SUN8I
 	---help---
@@ -154,19 +168,21 @@ config AXP_ALDO2_VOLT
 	On A31 boards aldo2 is typically unused and should be disabled.
 	On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
 	On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V.
+	On A80 boards aldo2 powers PB pingroup and camera IO and can be left off.
 	On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
 	LPDDR2, and the codec. It should be 1.8V.
 
 config AXP_ALDO3_VOLT
 	int "axp pmic (a)ldo3 voltage"
-	depends on AXP209_POWER || AXP221_POWER || AXP818_POWER
-	default 0 if AXP209_POWER
+	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 0 if AXP209_POWER || MACH_SUN9I
 	default 3000 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
 	disable aldo3.
 	On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
 	On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
+	On A80 boards aldo3 is normally not used.
 	On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
 	3.0V.
 
@@ -181,21 +197,23 @@ config AXP_ALDO4_VOLT
 
 config AXP_DLDO1_VOLT
 	int "axp pmic dldo1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
 	disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used
-	to power the ethernet phy. On sun8i (A23) boards this is often used to
-	power the wifi.
+	to power the ethernet phy. On A23, A33 and A80 boards this is often
+	used to power the wifi.
 
 config AXP_DLDO2_VOLT
 	int "axp pmic dldo2 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 3000 if MACH_SUN9I
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to
 	disable dldo2.
+	On A80 boards dldo2 normally powers the PL pins and should be 3.0V.
 
 config AXP_DLDO3_VOLT
 	int "axp pmic dldo3 voltage"
@@ -215,7 +233,7 @@ config AXP_DLDO4_VOLT
 
 config AXP_ELDO1_VOLT
 	int "axp pmic eldo1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to
@@ -223,7 +241,7 @@ config AXP_ELDO1_VOLT
 
 config AXP_ELDO2_VOLT
 	int "axp pmic eldo2 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to
@@ -231,13 +249,15 @@ config AXP_ELDO2_VOLT
 
 config AXP_ELDO3_VOLT
 	int "axp pmic eldo3 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 3000 if MACH_SUN9I
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to
 	disable eldo3. On some A31(s) tablets it might be used to supply
 	1.2V for the SSD2828 chip (converter of parallel LCD interface
 	into MIPI DSI).
+	On A80 boards it powers the PM pingroup and should be 3.0V.
 
 config AXP_FLDO1_VOLT
 	int "axp pmic fldo1 voltage"
@@ -268,7 +288,7 @@ config AXP_FLDO3_VOLT
 
 config AXP_SW_ON
 	bool "axp pmic sw on"
-	depends on AXP818_POWER
+	depends on AXP809_POWER || AXP818_POWER
 	default n
 	---help---
 	Enable to turn on axp pmic sw.
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 690faa0..b43523e 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER)	+= as3722.o
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP221_POWER)	+= axp221.o
+obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
new file mode 100644
index 0000000..c8b76cf
--- /dev/null
+++ b/drivers/power/axp809.c
@@ -0,0 +1,238 @@
+/*
+ * AXP809 driver based on AXP221 driver
+ *
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on axp221.c
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+static u8 axp809_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return (mvolt - min) / div;
+}
+
+int axp_set_dcdc1(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC1_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	ret = pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+			       AXP809_OUTPUT_CTRL2_DC1SW_EN);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC1_EN);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC2_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC2_EN);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC3_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC3_EN);
+}
+
+int axp_set_dcdc4(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+	if (mvolt >= 1540)
+		cfg = 0x30 + axp809_mvolt_to_cfg(mvolt, 1800, 2600, 100);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC4_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC4_EN);
+}
+
+int axp_set_dcdc5(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 1000, 2550, 50);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC5_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC5_EN);
+}
+
+int axp_set_aldo(int aldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (aldo_num < 1 || aldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0 && aldo_num == 3)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+					AXP809_OUTPUT_CTRL2_ALDO3_EN);
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
+
+	cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+	ret = pmic_bus_write(AXP809_ALDO1_CTRL + (aldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	if (aldo_num == 3)
+		return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+					AXP809_OUTPUT_CTRL2_ALDO3_EN);
+	return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
+}
+
+/* TODO: re-work other AXP drivers to consolidate ALDO functions. */
+int axp_set_aldo1(unsigned int mvolt)
+{
+	return axp_set_aldo(1, mvolt);
+}
+
+int axp_set_aldo2(unsigned int mvolt)
+{
+	return axp_set_aldo(2, mvolt);
+}
+
+int axp_set_aldo3(unsigned int mvolt)
+{
+	return axp_set_aldo(3, mvolt);
+}
+
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+	int ret;
+
+	if (dldo_num < 1 || dldo_num > 2)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+	if (dldo_num == 1 && mvolt > 3300)
+		cfg += 1 + axp809_mvolt_to_cfg(mvolt, 3400, 4200, 200);
+	ret = pmic_bus_write(AXP809_DLDO1_CTRL + (dldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
+int axp_set_eldo(int eldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+	if (eldo_num < 1 || eldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+
+	ret = pmic_bus_write(AXP809_ELDO1_CTRL + (eldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+}
+
+int axp_set_sw(bool on)
+{
+	if (on)
+		return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+					AXP809_OUTPUT_CTRL2_SWOUT_EN);
+
+	return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_SWOUT_EN);
+}
+
+int axp_init(void)
+{
+	int ret;
+
+	ret = pmic_bus_init();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmic_bus_write(AXP809_SHUTDOWN, AXP809_SHUTDOWN_POWEROFF);
+
+	/* infinite loop during shutdown */
+	while (1) {}
+
+	/* not reached */
+	return 0;
+}
diff --git a/include/axp809.h b/include/axp809.h
new file mode 100644
index 0000000..d27fb97
--- /dev/null
+++ b/include/axp809.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * X-Powers AXP809 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define AXP809_CHIP_ID		0x03
+
+#define AXP809_OUTPUT_CTRL1	0x10
+#define AXP809_OUTPUT_CTRL1_DC5LDO_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL1_DCDC1_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL1_DCDC2_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL1_DCDC3_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL1_DCDC4_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL1_DCDC5_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
+#define AXP809_OUTPUT_CTRL2	0x12
+#define AXP809_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL2_ALDO3_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL2_SWOUT_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL2_DC1SW_EN	(1 << 7)
+
+#define AXP809_DLDO1_CTRL	0x15
+#define AXP809_DLDO2_CTRL	0x16
+#define AXP809_ELDO1_CTRL	0x19
+#define AXP809_ELDO2_CTRL	0x1a
+#define AXP809_ELDO3_CTRL	0x1b
+#define AXP809_DC5LDO_CTRL	0x1c
+#define AXP809_DCDC1_CTRL	0x21
+#define AXP809_DCDC2_CTRL	0x22
+#define AXP809_DCDC3_CTRL	0x23
+#define AXP809_DCDC4_CTRL	0x24
+#define AXP809_DCDC5_CTRL	0x25
+#define AXP809_ALDO1_CTRL	0x28
+#define AXP809_ALDO2_CTRL	0x29
+#define AXP809_ALDO3_CTRL	0x2a
+#define AXP809_SHUTDOWN		0x32
+#define AXP809_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index 2ed5196..d789ad8 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -16,6 +16,9 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
+#ifdef CONFIG_AXP809_POWER
+#include <axp809.h>
+#endif
 #ifdef CONFIG_AXP818_POWER
 #include <axp818.h>
 #endif
-- 
cgit v0.10.2


From b19236fd1c1ef289bab9e243ee5b50d658fcac3f Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Sat, 14 May 2016 04:13:26 +0300
Subject: sunxi: Increase SPL header size to 64 bytes to avoid code corruption

The current SPL header, created by the 'mksunxiboot' tool, has size
32 bytes. But the code in the boot ROM stores the information about
the boot media at the offset 0x28 before passing control to the SPL.
For example, when booting from the SD card, the magic number written
by the boot ROM is 0. And when booting from the SPI flash, the magic
number is 3. NAND and eMMC probably have their own special magic
numbers too.

Currently the corrupted byte is a part of one of the instructions in
the reset vectors table:

    b     reset
    ldr   pc, _undefined_instruction
    ldr   pc, _software_interrupt      <- Corruption happens here
    ldr   pc, _prefetch_abort
    ldr   pc, _data_abort
    ldr   pc, _not_used
    ldr   pc, _irq
    ldr   pc, _fiq

In practice this does not cause any visible problems, but it's still
better to fix it. As a bonus, the reported boot media type can be
later used in the 'spl_boot_device' function, but this is out of
the scope of this patch.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index ca9a4f9..a0f33b0 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -18,6 +18,10 @@
 #define SPL_ADDR		0x0
 #endif
 
+/* The low 8-bits of the 'boot_media' field in the SPL header */
+#define SUNXI_BOOTED_FROM_MMC0	0
+#define SUNXI_BOOTED_FROM_SPI	3
+
 /* boot head definition from sun4i boot code */
 struct boot_file_head {
 	uint32_t b_instruction;	/* one intruction jumping to real code */
@@ -45,7 +49,9 @@ struct boot_file_head {
 		uint8_t spl_signature[4];
 	};
 	uint32_t fel_script_address;
-	uint32_t reserved;		/* padding, align to 32 bytes */
+	uint32_t reserved1[3];
+	uint32_t boot_media;		/* written here by the boot ROM */
+	uint32_t reserved2[5];		/* padding, align to 64 bytes */
 };
 
 #define is_boot0_magic(addr)	(memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ac2d931..12b3958 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -189,14 +189,14 @@
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 
 #if defined(CONFIG_MACH_SUN9I)
-#define CONFIG_SPL_TEXT_BASE		0x10020		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x5fe0		/* ? KiB on sun9i */
+#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* ? KiB on sun9i */
 #elif defined(CONFIG_MACH_SUN50I)
-#define CONFIG_SPL_TEXT_BASE		0x10020		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x7fe0		/* 32 KiB on sun50i */
+#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun50i */
 #else
-#define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
+#define CONFIG_SPL_TEXT_BASE		0x40		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* 24KB on sun4i/sun7i */
 #endif
 
 #define CONFIG_SPL_LIBDISK_SUPPORT
-- 
cgit v0.10.2


From 28d68045cc9f146a8c4aa2c8921eb95330ccc754 Mon Sep 17 00:00:00 2001
From: Bernhard Nortmann <bernhard.nortmann@web.de>
Date: Sun, 3 Apr 2016 13:58:00 +0200
Subject: sunxi: Properly announce BOOT_DEVICE_BOARD as "FEL"

This addresses a cosmetic issue when booting a sunxi device
over USB (FEL mode), where the SPL currently would just print
"Trying to boot from ". The patch fixes that to properly read
"Trying to boot from FEL".

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 20149da..bd15b9b 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -247,6 +247,15 @@ u32 spl_boot_device(void)
 	return -1;		/* Never reached */
 }
 
+/*
+ * Properly announce BOOT_DEVICE_BOARD as "FEL".
+ * Overrides weak function from common/spl/spl.c
+ */
+void spl_board_announce_boot_device(void)
+{
+	printf("FEL");
+}
+
 /* No confirmation data available in SPL yet. Hardcode bootmode */
 u32 spl_boot_mode(void)
 {
-- 
cgit v0.10.2


From 087504958a6c509b95e2967d7f78883728cf7b05 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 4 May 2016 22:15:30 +0100
Subject: Revert "sunxi: Reserve ATF memory space on A64"

The ARM Trusted Firmware (ATF) code now lives in SRAM on the Pine64/A64,
so we can claim the whole of DRAM for OS use.

This reverts commit 3ffe39ed2b66af71c7271d0cef2a248b5bf7dfdb.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 103aafe..d09cf6d 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,15 +133,6 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_MACH_SUN50I
-void dram_init_banksize(void)
-{
-	/* We need to reserve the first 16MB of RAM for ATF */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
-	gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024);
-}
-#endif
-
 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
 static void nand_pinmux_setup(void)
 {
-- 
cgit v0.10.2


From 671f9ad8aa61ac5163bfc8d80f9b707b336b4376 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 4 May 2016 22:15:32 +0100
Subject: arm64: sunxi: adjust default load addresses

As arm64 has slightly different expectations about load addresses, lets
use a different set of default addresses for things like the kernel.
As arm64 kernels don't come with a decompressor right now, reserve some
more space for really big uncompressed kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 12b3958..b33cfb8 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -390,6 +390,23 @@ extern int soft_i2c_gpio_scl;
 #define CONFIG_PRE_CONSOLE_BUFFER
 #define CONFIG_PRE_CON_BUF_SZ		4096 /* Aprox 2 80*25 screens */
 
+#ifdef CONFIG_ARM64
+/*
+ * Boards seem to come with at least 512MB of DRAM.
+ * The kernel should go at 512K, which is the default text offset (that will
+ * be adjusted at runtime if needed).
+ * There is no compression for arm64 kernels (yet), so leave some space
+ * for really big kernels, say 256MB for now.
+ * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
+ * Align the initrd to a 2MB page.
+ */
+#define KERNEL_ADDR_R	__stringify(SDRAM_OFFSET(0080000))
+#define FDT_ADDR_R	__stringify(SDRAM_OFFSET(FA00000))
+#define SCRIPT_ADDR_R	__stringify(SDRAM_OFFSET(FC00000))
+#define PXEFILE_ADDR_R	__stringify(SDRAM_OFFSET(FD00000))
+#define RAMDISK_ADDR_R	__stringify(SDRAM_OFFSET(FE00000))
+
+#else
 /*
  * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
  * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
@@ -401,6 +418,7 @@ extern int soft_i2c_gpio_scl;
 #define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(3100000))
 #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
 #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+#endif
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0xa000000\0" \
-- 
cgit v0.10.2


From c1fd2441872722edeacf4b04c80b9a8926ee3042 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 4 May 2016 22:15:33 +0100
Subject: arm64: Pine64: update FDT files

The originally committed .dts files for the Pine64 were from an early
proof-of-concept version and should have never been committed upstream.
Replace them with much more mature versions, which also use a different
naming scheme.
Please note that at this point there is at least one binding which has
not been agreed upon, so this is subject to change.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d1f8e22..bd68698 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -218,7 +218,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
-	pine64_plus.dtb
+	sun50i-a64-pine64-plus.dtb \
+	sun50i-a64-pine64.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/dts/a64.dtsi b/arch/arm/dts/a64.dtsi
deleted file mode 100644
index f3ad000..0000000
--- a/arch/arm/dts/a64.dtsi
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * Copyright (C) 2016 ARM Ltd.
- * based on the Allwinner H3 dtsi:
- * 	Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-/ {
-	compatible = "allwinner,a64";
-	interrupt-parent = <&gic>;
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0>;
-			enable-method = "psci";
-		};
-
-		cpu@1 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <1>;
-			enable-method = "psci";
-		};
-
-		cpu@2 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <2>;
-			enable-method = "psci";
-		};
-
-		cpu@3 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <3>;
-			enable-method = "psci";
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2", "arm,psci";
-		method = "smc";
-		cpu_suspend = <0xc4000001>;
-		cpu_off = <0x84000002>;
-		cpu_on = <0xc4000003>;
-	};
-
-        memory {
-		device_type = "memory";
-		reg = <0x40000000 0>;
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		osc24M: osc24M_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-			clock-output-names = "osc24M";
-		};
-
-		osc32k: osc32k_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			clock-output-names = "osc32k";
-		};
-
-		pll1: clk@01c20000 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun8i-a23-pll1-clk";
-			reg = <0x01c20000 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll1";
-		};
-
-		pll6: clk@01c20028 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun6i-a31-pll6-clk";
-			reg = <0x01c20028 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll6", "pll6x2";
-		};
-
-		pll6d2: pll6d2_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
-			clock-div = <2>;
-			clock-mult = <1>;
-			clocks = <&pll6 0>;
-			clock-output-names = "pll6d2";
-		};
-
-		/* dummy clock until pll6 can be reused */
-		pll8: pll8_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <1>;
-			clock-output-names = "pll8";
-		};
-
-		cpu: cpu_clk@01c20050 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-cpu-clk";
-			reg = <0x01c20050 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
-			clock-output-names = "cpu";
-		};
-
-		axi: axi_clk@01c20050 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-axi-clk";
-			reg = <0x01c20050 0x4>;
-			clocks = <&cpu>;
-			clock-output-names = "axi";
-		};
-
-		ahb1: ahb1_clk@01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun6i-a31-ahb1-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
-			clock-output-names = "ahb1";
-		};
-
-		ahb2: ahb2_clk@01c2005c {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun8i-h3-ahb2-clk";
-			reg = <0x01c2005c 0x4>;
-			clocks = <&ahb1>, <&pll6d2>;
-			clock-output-names = "ahb2";
-		};
-
-		apb1: apb1_clk@01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-apb0-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&ahb1>;
-			clock-output-names = "apb1";
-		};
-
-		apb2: apb2_clk@01c20058 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-apb1-clk";
-			reg = <0x01c20058 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
-			clock-output-names = "apb2";
-		};
-
-		bus_gates: clk@01c20060 {
-			#clock-cells = <1>;
-			compatible = "allwinner,a64-bus-gates-clk",
-				     "allwinner,sun8i-h3-bus-gates-clk";
-			reg = <0x01c20060 0x14>;
-			clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
-			clock-names = "ahb1", "ahb2", "apb1", "apb2";
-			clock-indices = <1>,
-					<5>, <6>, <8>,
-					<9>, <10>, <13>,
-					<14>, <17>, <18>,
-					<19>, <20>,
-					<21>, <23>,
-					<24>, <25>,
-					<28>, <29>,
-					<32>, <35>,
-					<36>, <37>,
-					<40>, <43>,
-					<44>, <52>, <53>,
-					<54>, <64>,
-					<65>, <69>, <72>,
-					<76>, <77>, <78>,
-					<96>, <97>, <98>,
-					<101>,
-					<112>, <113>,
-					<114>, <115>,
-					<116>, <135>;
-			clock-output-names = "bus_mipidsi",
-					     "bus_ce", "bus_dma", "bus_mmc0",
-					     "bus_mmc1", "bus_mmc2", "bus_nand",
-					     "bus_sdram", "bus_gmac", "bus_ts",
-					     "bus_hstimer", "bus_spi0",
-					     "bus_spi1", "bus_otg",
-					     "bus_otg_ehci0", "bus_ehci0",
-					     "bus_otg_ohci0", "bus_ohci0",
-					     "bus_ve", "bus_lcd0",
-					     "bus_lcd1", "bus_deint",
-					     "bus_csi", "bus_hdmi",
-					     "bus_de", "bus_gpu", "bus_msgbox",
-					     "bus_spinlock", "bus_codec",
-					     "bus_spdif", "bus_pio", "bus_ths",
-					     "bus_i2s0", "bus_i2s1", "bus_i2s2",
-					     "bus_i2c0", "bus_i2c1", "bus_i2c2",
-					     "bus_scr",
-					     "bus_uart0", "bus_uart1",
-					     "bus_uart2", "bus_uart3",
-					     "bus_uart4", "bus_dbg";
-		};
-
-		mmc0_clk: clk@01c20088 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
-			clock-output-names = "mmc0",
-					     "mmc0_output",
-					     "mmc0_sample";
-		};
-
-		mmc1_clk: clk@01c2008c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
-			clock-output-names = "mmc1",
-					     "mmc1_output",
-					     "mmc1_sample";
-		};
-
-		mmc2_clk: clk@01c20090 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
-			clock-output-names = "mmc2",
-					     "mmc2_output",
-					     "mmc2_sample";
-		};
-	};
-
-	regulators {
-		reg_vcc3v3: vcc3v3 {
-			compatible = "regulator-fixed";
-			regulator-name = "vcc3v3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
-			reg = <0x01c0f000 0x1000>;
-			clocks = <&bus_gates 8>,
-				 <&mmc0_clk 0>,
-				 <&mmc0_clk 1>,
-				 <&mmc0_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ahb_rst 8>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
-			reg = <0x01c10000 0x1000>;
-			clocks = <&bus_gates 9>,
-				 <&mmc1_clk 0>,
-				 <&mmc1_clk 1>,
-				 <&mmc1_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ahb_rst 9>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
-			reg = <0x01c11000 0x1000>;
-			clocks = <&bus_gates 10>,
-				 <&mmc2_clk 0>,
-				 <&mmc2_clk 1>,
-				 <&mmc2_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ahb_rst 10>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		pio: pinctrl@01c20800 {
-			compatible = "allwinner,a64-pinctrl";
-			reg = <0x01c20800 0x400>;
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&bus_gates 69>;
-			gpio-controller;
-			#gpio-cells = <3>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-
-			uart0_pins_a: uart0@0 {
-				allwinner,pins = "PB8", "PB9";
-				allwinner,function = "uart0";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart0_pins_b: uart0@1 {
-				allwinner,pins = "PF2", "PF3";
-				allwinner,function = "uart0";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart1_pins: uart1@0 {
-				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
-				allwinner,function = "uart1";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart2_pins: uart2@0 {
-				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
-				allwinner,function = "uart2";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart3_pins_a: uart3@0 {
-				allwinner,pins = "PD0", "PD1";
-				allwinner,function = "uart3";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart3_pins_b: uart3@1 {
-				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
-				allwinner,function = "uart3";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart4_pins: uart4@0 {
-				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
-				allwinner,function = "uart4";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			mmc0_pins: mmc0@0 {
-				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
-						 "PF4", "PF5";
-				allwinner,function = "mmc0";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			mmc0_default_cd_pin: mmc0_cd_pin@0 {
-				allwinner,pins = "PF6";
-				allwinner,function = "gpio_in";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-			};
-
-			mmc1_pins: mmc1@0 {
-				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
-						 "PG4", "PG5";
-				allwinner,function = "mmc1";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			mmc2_pins: mmc2@0 {
-				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
-						 "PC9", "PC10";
-				allwinner,function = "mmc2";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-		};
-
-		ahb_rst: reset@01c202c0 {
-			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-ahb1-reset";
-			reg = <0x01c202c0 0xc>;
-		};
-
-		apb1_rst: reset@01c202d0 {
-			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-clock-reset";
-			reg = <0x01c202d0 0x4>;
-		};
-
-		apb2_rst: reset@01c202d8 {
-			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-clock-reset";
-			reg = <0x01c202d8 0x4>;
-		};
-
-		uart0: serial@01c28000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28000 0x400>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&bus_gates 112>;
-			resets = <&apb2_rst 16>;
-			reset-names = "apb2";
-			status = "disabled";
-		};
-
-		uart1: serial@01c28400 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28400 0x400>;
-			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&bus_gates 113>;
-			resets = <&apb2_rst 17>;
-			reset-names = "apb2";
-			status = "disabled";
-		};
-
-		uart2: serial@01c28800 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28800 0x400>;
-			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&bus_gates 114>;
-			resets = <&apb2_rst 18>;
-			reset-names = "apb2";
-			status = "disabled";
-		};
-
-		uart3: serial@01c28c00 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28c00 0x400>;
-			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&bus_gates 115>;
-			resets = <&apb2_rst 19>;
-			reset-names = "apb2";
-			status = "disabled";
-		};
-
-		uart4: serial@01c29000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c29000 0x400>;
-			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&bus_gates 116>;
-			resets = <&apb2_rst 20>;
-			reset-names = "apb2";
-			status = "disabled";
-		};
-
-		rtc: rtc@01f00000 {
-			compatible = "allwinner,sun6i-a31-rtc";
-			reg = <0x01f00000 0x54>;
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gic: interrupt-controller@{
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-
-		reg = <0x01C81000 0x1000>,
-		      <0x01C82000 0x2000>,
-		      <0x01C84000 0x2000>,
-		      <0x01C86000 0x2000>;
-		interrupts = <GIC_PPI 9
-		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-};
diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/pine64.dts
deleted file mode 100644
index dcc998f..0000000
--- a/arch/arm/dts/pine64.dts
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2016 ARM Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
-
-/ {
-	model = "Pine64";
-	compatible = "pine64,pine64", "allwinner,a64";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0x40000000 0x20000000>;
-	};
-};
diff --git a/arch/arm/dts/pine64_common.dtsi b/arch/arm/dts/pine64_common.dtsi
deleted file mode 100644
index d968d76..0000000
--- a/arch/arm/dts/pine64_common.dtsi
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2016 ARM Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "a64.dtsi"
-
-&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
-	vmmc-supply = <&reg_vcc3v3>;
-	cd-gpios = <&pio 5 6 0>;
-	cd-inverted;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_a>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/pine64_plus.dts b/arch/arm/dts/pine64_plus.dts
deleted file mode 100644
index 5daff51..0000000
--- a/arch/arm/dts/pine64_plus.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2016 ARM Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
-
-/ {
-	model = "Pine64+";
-	compatible = "pine64,pine64_plus", "allwinner,a64";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
-	memory {
-		reg = <0x40000000 0x40000000>;
-	};
-};
diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
new file mode 100644
index 0000000..d5a7249
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun50i-a64.dtsi"
+
+/ {
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	cd-gpios = <&pio 5 6 0>;
+	cd-inverted;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
new file mode 100644
index 0000000..549dc15
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-pine64-common.dtsi"
+
+/ {
+	model = "Pine64+";
+	compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+};
diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
new file mode 100644
index 0000000..ebe029e
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64-pine64-common.dtsi"
+
+/ {
+	model = "Pine64";
+	compatible = "pine64,pine64", "allwinner,sun50i-a64";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x40000000 0x20000000>;
+	};
+};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
new file mode 100644
index 0000000..1bd436f
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -0,0 +1,624 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0>;
+			enable-method = "psci";
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <1>;
+			enable-method = "psci";
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <2>;
+			enable-method = "psci";
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <3>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x40000000 0>;
+	};
+
+	gic: interrupt-controller@1c81000 {
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+
+		reg = <0x01c81000 0x1000>,
+		      <0x01c82000 0x2000>,
+		      <0x01c84000 0x2000>,
+		      <0x01c86000 0x2000>;
+		interrupts = <GIC_PPI 9
+		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: osc24M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: osc32k_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+
+		pll1: pll1_clk@1c20000 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-a23-pll1-clk";
+			reg = <0x01c20000 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll1";
+		};
+
+		pll6: pll6_clk@1c20028 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c20028 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll6", "pll6x2";
+		};
+
+		pll6d2: pll6d2_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll6 0>;
+			clock-output-names = "pll6d2";
+		};
+
+		pll7: pll7_clk@1c2002c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c2002c 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll7", "pll7x2";
+		};
+
+		cpu: cpu_clk@1c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-cpu-clk";
+			reg = <0x01c20050 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+			clock-output-names = "cpu";
+			critical-clocks = <0>;
+		};
+
+		axi: axi_clk@1c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-axi-clk";
+			reg = <0x01c20050 0x4>;
+			clocks = <&cpu>;
+			clock-output-names = "axi";
+		};
+
+		ahb1: ahb1_clk@1c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-ahb1-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+			clock-output-names = "ahb1";
+		};
+
+		ahb2: ahb2_clk@1c2005c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-h3-ahb2-clk";
+			reg = <0x01c2005c 0x4>;
+			clocks = <&ahb1>, <&pll6d2>;
+			clock-output-names = "ahb2";
+		};
+
+		apb1: apb1_clk@1c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb0-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&ahb1>;
+			clock-output-names = "apb1";
+		};
+
+		apb2: apb2_clk@1c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
+			clock-output-names = "apb2";
+		};
+
+		bus_gates: bus_gates_clk@1c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun50i-a64-bus-gates-clk",
+				     "allwinner,sunxi-multi-bus-gates-clk";
+			reg = <0x01c20060 0x14>;
+			ahb1_parent {
+				clocks = <&ahb1>;
+				clock-indices = <1>, <5>,
+						<6>, <8>,
+						<9>, <10>,
+						<13>, <14>,
+						<18>, <19>,
+						<20>, <21>,
+						<23>, <24>,
+						<25>, <28>,
+						<32>, <35>,
+						<36>, <37>,
+						<40>, <43>,
+						<44>, <52>,
+						<53>, <54>,
+						<135>;
+				clock-output-names = "bus_mipidsi", "bus_ce",
+						"bus_dma", "bus_mmc0",
+						"bus_mmc1", "bus_mmc2",
+						"bus_nand", "bus_sdram",
+						"bus_ts", "bus_hstimer",
+						"bus_spi0", "bus_spi1",
+						"bus_otg", "bus_otg_ehci0",
+						"bus_ehci0", "bus_otg_ohci0",
+						"bus_ve", "bus_lcd0",
+						"bus_lcd1", "bus_deint",
+						"bus_csi", "bus_hdmi",
+						"bus_de", "bus_gpu",
+						"bus_msgbox", "bus_spinlock",
+						"bus_dbg";
+			};
+			ahb2_parent {
+				clocks = <&ahb2>;
+				clock-indices = <17>, <29>;
+				clock-output-names = "bus_gmac", "bus_ohci0";
+			};
+			apb1_parent {
+				clocks = <&apb1>;
+				clock-indices = <64>, <65>,
+						<69>, <72>,
+						<76>, <77>,
+						<78>;
+				clock-output-names = "bus_codec", "bus_spdif",
+						"bus_pio", "bus_ths",
+						"bus_i2s0", "bus_i2s1",
+						"bus_i2s2";
+			};
+			abp2_parent {
+				clocks = <&apb2>;
+				clock-indices = <96>, <97>,
+						<98>, <101>,
+						<112>, <113>,
+						<114>, <115>,
+						<116>;
+				clock-output-names = "bus_i2c0", "bus_i2c1",
+						"bus_i2c2", "bus_scr",
+						"bus_uart0", "bus_uart1",
+						"bus_uart2", "bus_uart3",
+						"bus_uart4";
+			};
+		};
+
+		mmc0_clk: mmc0_clk@1c20088 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+			clock-output-names = "mmc0";
+                };
+
+		mmc1_clk: mmc1_clk@1c2008c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c2008c 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+			clock-output-names = "mmc1";
+		};
+
+		mmc2_clk: mmc2_clk@1c20090 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20090 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+			clock-output-names = "mmc2";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&bus_gates 8>, <&mmc0_clk>,
+				 <&mmc0_clk>, <&mmc0_clk>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
+			resets = <&ahb_rst 8>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@1c10000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&bus_gates 9>, <&mmc1_clk>,
+				 <&mmc1_clk>, <&mmc1_clk>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
+			resets = <&ahb_rst 9>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@1c11000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&bus_gates 10>, <&mmc2_clk>,
+				 <&mmc2_clk>, <&mmc2_clk>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
+			resets = <&ahb_rst 10>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		pio: pinctrl@1c20800 {
+			compatible = "allwinner,sun50i-a64-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 69>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PB8", "PB9";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart0_pins_b: uart0@1 {
+				allwinner,pins = "PF2", "PF3";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart1_2pins: uart1_2@0 {
+				allwinner,pins = "PG6", "PG7";
+				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart1_4pins: uart1_4@0 {
+				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart2_2pins: uart2_2@0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "uart2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart2_4pins: uart2_4@0 {
+				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
+				allwinner,function = "uart2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_pins_a: uart3@0 {
+				allwinner,pins = "PD0", "PD1";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_2pins_b: uart3_2@1 {
+				allwinner,pins = "PH4", "PH5";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_4pins_b: uart3_4@1 {
+				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart4_2pins: uart4_2@0 {
+				allwinner,pins = "PD2", "PD3";
+				allwinner,function = "uart4";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart4_4pins: uart4_4@0 {
+				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
+				allwinner,function = "uart4";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_pins: mmc0@0 {
+				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+						 "PF4", "PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_default_cd_pin: mmc0_cd_pin@0 {
+				allwinner,pins = "PF6";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			};
+
+			mmc1_pins: mmc1@0 {
+				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+						 "PG4", "PG5";
+				allwinner,function = "mmc1";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc2_pins: mmc2@0 {
+				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
+						 "PC9", "PC10";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c0_pins: i2c0_pins {
+				allwinner,pins = "PH0", "PH1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c1_pins: i2c1_pins {
+				allwinner,pins = "PH2", "PH3";
+				allwinner,function = "i2c1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c2_pins: i2c2_pins {
+				allwinner,pins = "PE14", "PE15";
+				allwinner,function = "i2c2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
+
+		ahb_rst: reset@1c202c0 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202c0 0xc>;
+		};
+
+		apb1_rst: reset@1c202d0 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202d0 0x4>;
+		};
+
+		apb2_rst: reset@1c202d8 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202d8 0x4>;
+		};
+
+		uart0: serial@1c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 112>;
+			resets = <&apb2_rst 16>;
+			status = "disabled";
+		};
+
+		uart1: serial@1c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 113>;
+			resets = <&apb2_rst 17>;
+			status = "disabled";
+		};
+
+		uart2: serial@1c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 114>;
+			resets = <&apb2_rst 18>;
+			status = "disabled";
+		};
+
+		uart3: serial@1c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 115>;
+			resets = <&apb2_rst 19>;
+			status = "disabled";
+		};
+
+		uart4: serial@1c29000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29000 0x400>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 116>;
+			resets = <&apb2_rst 20>;
+			status = "disabled";
+		};
+
+		rtc: rtc@1f00000 {
+			compatible = "allwinner,sun6i-a31-rtc";
+			reg = <0x01f00000 0x54>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		i2c0: i2c@1c2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 96>;
+			resets = <&apb2_rst 0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@1c2b000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 97>;
+			resets = <&apb2_rst 1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@1c2b400 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 98>;
+			resets = <&apb2_rst 2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0494a9f..0977334 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -4,7 +4,7 @@ CONFIG_MACH_SUN50I=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881915
 # CONFIG_VIDEO is not set
-CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From 0878a8a7dbb71fb5b1e10007cfc6203844b029c2 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 15 May 2016 13:51:58 +0200
Subject: sunxi: Enable a bunch of commands by default on sunxi

Recently a set of CONFIG_CMD_FOO defines was moved from being defined
in config_distro_defaults to Kconfig, and added to all sunxi defconfigs
to compensate.

Instead of explictly selecting these in all sunxi defconfigs,
simply always select these for sunxi boards. This makes the defconfigs
simpler and ensures a consistent set of available commands across all
sunxi boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 729b181..5fd20b9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -538,7 +538,16 @@ config TARGET_CM_T43
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
+	select CMD_BOOTZ
+	select CMD_DHCP
+	select CMD_EXT2
+	select CMD_EXT4
+	select CMD_FAT
+	select CMD_FS_GENERIC
 	select CMD_GPIO
+	select CMD_MII
+	select CMD_MMC if MMC
+	select CMD_PING
 	select CMD_USB
 	select DM
 	select DM_ETH
@@ -546,6 +555,7 @@ config ARCH_SUNXI
 	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_USB
+	select HUSH_PARSER
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 059e914..c1ae6f5 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -368,6 +368,7 @@ config I2C0_ENABLE
 	bool "Enable I2C/TWI controller 0"
 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default n if MACH_SUN6I || MACH_SUN8I
+	select CMD_I2C
 	---help---
 	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 	its clock and setting up the bus. This is especially useful on devices
@@ -377,12 +378,14 @@ config I2C0_ENABLE
 config I2C1_ENABLE
 	bool "Enable I2C/TWI controller 1"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 
 config I2C2_ENABLE
 	bool "Enable I2C/TWI controller 2"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 
@@ -390,6 +393,7 @@ if MACH_SUN6I || MACH_SUN7I
 config I2C3_ENABLE
 	bool "Enable I2C/TWI controller 3"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 endif
@@ -399,6 +403,7 @@ config R_I2C_ENABLE
 	bool "Enable the PRCM I2C/TWI controller"
 	# This is used for the pmic on H3
 	default y if SY8106A_POWER
+	select CMD_I2C
 	---help---
 	Set this to y to enable the I2C controller which is part of the PRCM.
 endif
@@ -407,6 +412,7 @@ if MACH_SUN7I
 config I2C4_ENABLE
 	bool "Enable I2C/TWI controller 4"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 endif
@@ -535,6 +541,7 @@ config VIDEO_LCD_PANEL_I2C
 	bool "LCD panel needs to be configured via i2c"
 	depends on VIDEO
 	default n
+	select CMD_I2C
 	---help---
 	Say y here if the LCD panel needs to be configured via i2c. This
 	will add a bitbang i2c controller using gpios to talk to the LCD.
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index d7725e4..8cb7ac7 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -9,20 +9,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index c39daf1..6a0d815 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -10,19 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 955b6cf..a790856 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -14,19 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 30ea836..d12a3cc 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -16,22 +16,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 546c84c..cc5858e 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -9,20 +9,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 5dc4ba3..7b0309c 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -7,20 +7,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index e952562..9507b87 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -10,19 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index cecf4c2..40f8c98 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -12,20 +12,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 7479f7f..fc1be7d 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,18 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index fde84ac..8262be5 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 45539c1..44f3982 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,19 +8,8 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 52dfdf2..9d5365d 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,19 +6,8 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index fd6b8de..d9b1bd6 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -8,20 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index ae38583..496c20e 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -10,20 +10,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO4_VOLT=2500
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index cbbec47..3e8c0a1 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -8,19 +8,9 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
-CONFIG_CMD_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index ab6f329..1cb010d 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 080bfbd..3257aae 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,20 +14,9 @@ CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 6380a22..2ce8cb1 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -18,20 +18,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 683f7f9..4b9d722 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index f8c7107..c884115 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -7,18 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 0d43c53..4e25392 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -12,22 +12,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index b5959ee..725652d 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -15,20 +15,9 @@ CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 7cc162b..5f01760 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -17,18 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index f424557..02bcdbf 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -10,19 +10,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 4ff0a6b..fef3685 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,18 +15,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index f4832a7..cb6dfe4 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 1227994..d2111c6 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -8,19 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 3b0d8cf..378abce 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -9,19 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 28768ec..c3f0421 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 11bb709..9d8d325 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -7,18 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index ca61e5c..49bb26a 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,18 +5,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index a9d5aae..5559444 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,17 +10,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 14db5ae..3d71bf5 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,19 +13,9 @@ CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index cb9ca3b..cef9794 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -5,19 +5,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index bae638f..b3f825e 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 9311799..f076e30 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -7,18 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 831578e..eccf372 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index d628c7c..d72dcc0 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -10,19 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 35df225..0d1ba15 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,19 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 8a4980e..f0b4384 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 842db29..53e023a 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -8,16 +8,6 @@ CONFIG_MMC0_CD_PIN="PH18"
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 102b96c..53f9bfe 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,19 +6,8 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 212f98c..00c671b 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -11,19 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 148b4fa..a865255 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -13,19 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 4136841..ae1f1e8 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -12,19 +12,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 03cef97..013c35e 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,16 +6,6 @@ CONFIG_DRAM_ZQ=15291
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index dc781db..181e1e2 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 29694ce..77b0525 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -15,19 +15,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_SW_ON=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index 948107c..d36a5dc 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,19 +20,8 @@ CONFIG_VIDEO_LCD_TL059WV5C0=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index d754ccd..5f3d624 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,19 +13,8 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 4a7dbdb..bfc8cba 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,19 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 0b40b83..fc43cc5 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,18 +7,7 @@ CONFIG_USB1_VBUS_PIN="PG12"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index fab74f4..65c1d8e 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,18 +19,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 71f01db..958104e 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,18 +16,8 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index b61b15c..1cfb380 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -10,19 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 655a0e7..ae67c37 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,19 +16,9 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO2_VOLT=1800
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 2b6dba8..c76af0e 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index b0791b9..f8155b2 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -14,18 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 03cdb17..34e74af 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -18,19 +18,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index c11aed8..a14de0d 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 7c731b3..e04d96b 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -11,19 +11,9 @@ CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 266015a..54fa819 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index e9ec810..7ec54a7 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,18 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 64da00f..5e68769 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,18 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 8b64678..3dea793 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,18 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index d432ff0..548a07e 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -14,19 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index b0f244d..a8b32cb 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,19 +14,8 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a953795..0b03e16 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,18 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index dace876..27b5019 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 35d9d7c..153450f 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,18 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 79f3cfb..9cb8b1d 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -8,19 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 9a44466..ce81309 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,19 +9,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 5e545d0..720aefa 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,19 +7,8 @@ CONFIG_USB1_VBUS_PIN="PB10"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index a76a699..d38bc7f 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -6,19 +6,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index bdfb597..de1b73f 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,18 +4,7 @@ CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index f33ac36..8b1082c 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -10,19 +10,8 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index de6e9c8..be8afca 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -9,17 +9,7 @@ CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7bade8f..7eaa795 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -8,19 +8,8 @@ CONFIG_DRAM_ODT_EN=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 2df5859..9ff4332 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -12,19 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0977334..489b75c 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -6,15 +6,6 @@ CONFIG_DRAM_ZQ=3881915
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index cedbf53..04c99b9 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index aad9619..9aa5280 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,18 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 97232ce..b467b62 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 79dcc33..7391464 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index ff29e81..16f8600 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index d87700c..6378918 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 4e1c393..9d9d4bf 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,19 +6,8 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 3677da7..6d39dec 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,18 +11,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
-- 
cgit v0.10.2


From 0e6e34ac8dbb597a34e1eca4fb640c3eb5e52467 Mon Sep 17 00:00:00 2001
From: Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
Date: Mon, 23 May 2016 09:49:47 +0300
Subject: sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulators

Sets LDO3 and LDO4 regulators at 2.8V. In the current config
these are off. This causes kernel to hang during
axp209 initialization.

Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 9507b87..e4168fa 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -15,3 +15,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 40f8c98..6430606 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -18,3 +18,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
-- 
cgit v0.10.2


From f9a90ace21c52a5a6948b9f3a0d8fe088e47a595 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 25 May 2016 09:48:14 +0100
Subject: arm64: fix arm64 Linux boot image header field sizes

The arm64 Linux boot protocol [1] describes the fields in the Image
header as being 64-bit little endian values.
So fix the endianess conversion to use 64-bit sized operations, for
both image_size and text_offset.
Also we use a local variable for the image_size to avoid both writing
to the header and also accessing it after we actually unmapped it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.txt

diff --git a/cmd/bootm.c b/cmd/bootm.c
index 1bca6fa..ee3b460 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -655,6 +655,7 @@ static int booti_setup(bootm_headers_t *images)
 {
 	struct Image_header *ih;
 	uint64_t dst;
+	uint64_t image_size;
 
 	ih = (struct Image_header *)map_sysmem(images->ep, 0);
 
@@ -665,14 +666,16 @@ static int booti_setup(bootm_headers_t *images)
 	
 	if (ih->image_size == 0) {
 		puts("Image lacks image_size field, assuming 16MiB\n");
-		ih->image_size = (16 << 20);
+		image_size = 16 << 20;
+	} else {
+		image_size = le64_to_cpu(ih->image_size);
 	}
 
 	/*
 	 * If we are not at the correct run-time location, set the new
 	 * correct location and then move the image there.
 	 */
-	dst = gd->bd->bi_dram[0].start + le32_to_cpu(ih->text_offset);
+	dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
 
 	unmap_sysmem(ih);
 
@@ -683,7 +686,7 @@ static int booti_setup(bootm_headers_t *images)
 
 		src = (void *)images->ep;
 		images->ep = dst;
-		memmove((void *)dst, src, le32_to_cpu(ih->image_size));
+		memmove((void *)dst, src, image_size);
 	}
 
 	return 0;
-- 
cgit v0.10.2


From 0a222d53d81cbd4f7a440a6f83e243a7b4e80544 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:24 +0100
Subject: fdt: Support for ISA busses

Support ISA busses in much the same way as Linux does. This allows for
ISA bus addresses to be translated, and only if CONFIG_OF_ISA_BUS is
selected in order to avoid including the code in builds which won't need
it.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42e5d8a..96b5d0a 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -964,10 +964,21 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na)
 static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
 #endif
 
-/* Callbacks for bus specific translators */
+/**
+ * struct of_bus - Callbacks for bus specific translators
+ * @match:	Return non-zero if the node whose parent is at
+ *		parentoffset in the FDT blob corresponds to a bus
+ *		of this type, otherwise return zero. If NULL a match
+ *		is assumed.
+ *
+ * Each bus type will include a struct of_bus in the of_busses array,
+ * providing implementations of some or all of the functions used to
+ * match the bus & handle address translation for its children.
+ */
 struct of_bus {
 	const char	*name;
 	const char	*addresses;
+	int		(*match)(void *blob, int parentoffset);
 	void		(*count_cells)(void *blob, int parentoffset,
 				int *addrc, int *sizec);
 	u64		(*map)(fdt32_t *addr, const fdt32_t *range,
@@ -1022,8 +1033,70 @@ static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na)
 	return 0;
 }
 
+#ifdef CONFIG_OF_ISA_BUS
+
+/* ISA bus translator */
+static int of_bus_isa_match(void *blob, int parentoffset)
+{
+	const char *name;
+
+	name = fdt_get_name(blob, parentoffset, NULL);
+	if (!name)
+		return 0;
+
+	return !strcmp(name, "isa");
+}
+
+static void of_bus_isa_count_cells(void *blob, int parentoffset,
+				   int *addrc, int *sizec)
+{
+	if (addrc)
+		*addrc = 2;
+	if (sizec)
+		*sizec = 1;
+}
+
+static u64 of_bus_isa_map(fdt32_t *addr, const fdt32_t *range,
+			  int na, int ns, int pna)
+{
+	u64 cp, s, da;
+
+	/* Check address type match */
+	if ((addr[0] ^ range[0]) & cpu_to_be32(1))
+		return OF_BAD_ADDR;
+
+	cp = of_read_number(range + 1, na - 1);
+	s  = of_read_number(range + na + pna, ns);
+	da = of_read_number(addr + 1, na - 1);
+
+	debug("OF: ISA map, cp=%" PRIu64 ", s=%" PRIu64
+	      ", da=%" PRIu64 "\n", cp, s, da);
+
+	if (da < cp || da >= (cp + s))
+		return OF_BAD_ADDR;
+	return da - cp;
+}
+
+static int of_bus_isa_translate(fdt32_t *addr, u64 offset, int na)
+{
+	return of_bus_default_translate(addr + 1, offset, na - 1);
+}
+
+#endif /* CONFIG_OF_ISA_BUS */
+
 /* Array of bus specific translators */
 static struct of_bus of_busses[] = {
+#ifdef CONFIG_OF_ISA_BUS
+	/* ISA */
+	{
+		.name = "isa",
+		.addresses = "reg",
+		.match = of_bus_isa_match,
+		.count_cells = of_bus_isa_count_cells,
+		.map = of_bus_isa_map,
+		.translate = of_bus_isa_translate,
+	},
+#endif /* CONFIG_OF_ISA_BUS */
 	/* Default */
 	{
 		.name = "default",
@@ -1034,6 +1107,28 @@ static struct of_bus of_busses[] = {
 	},
 };
 
+static struct of_bus *of_match_bus(void *blob, int parentoffset)
+{
+	struct of_bus *bus;
+
+	if (ARRAY_SIZE(of_busses) == 1)
+		return of_busses;
+
+	for (bus = of_busses; bus; bus++) {
+		if (!bus->match || bus->match(blob, parentoffset))
+			return bus;
+	}
+
+	/*
+	 * We should always have matched the default bus at least, since
+	 * it has a NULL match field. If we didn't then it somehow isn't
+	 * in the of_busses array or something equally catastrophic has
+	 * gone wrong.
+	 */
+	assert(0);
+	return NULL;
+}
+
 static int of_translate_one(void * blob, int parent, struct of_bus *bus,
 			    struct of_bus *pbus, fdt32_t *addr,
 			    int na, int ns, int pna, const char *rprop)
@@ -1113,7 +1208,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
 	parent = fdt_parent_offset(blob, node_offset);
 	if (parent < 0)
 		goto bail;
-	bus = &of_busses[0];
+	bus = of_match_bus(blob, parent);
 
 	/* Cound address cells & copy address locally */
 	bus->count_cells(blob, parent, &na, &ns);
@@ -1142,7 +1237,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
 		}
 
 		/* Get new parent bus and counts */
-		pbus = &of_busses[0];
+		pbus = of_match_bus(blob, parent);
 		pbus->count_cells(blob, parent, &pna, &pns);
 		if (!OF_CHECK_COUNTS(pna, pns)) {
 			printf("%s: Bad cell count for %s\n", __FUNCTION__,
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index c5c9d2a..8749561 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -178,4 +178,27 @@ config SPL_OF_TRANSLATE
 	  used for the address translation. This function is faster and
 	  smaller in size than fdt_translate_address().
 
+config OF_ISA_BUS
+	bool
+	depends on OF_TRANSLATE
+	help
+	  Is this option is enabled then support for the ISA bus will
+	  be included for addresses read from DT. This is something that
+	  should be known to be required or not based upon the board
+	  being targetted, and whether or not it makes use of an ISA bus.
+
+	  The bus is matched based upon its node name equalling "isa". The
+	  busses #address-cells should equal 2, with the first cell being
+	  used to hold flags & flag 0x1 indicating that the address range
+	  should be accessed using I/O port in/out accessors. The second
+	  cell holds the offset into ISA bus address space. The #size-cells
+	  property should equal 1, and of course holds the size of the
+	  address range used by a device.
+
+	  If this option is not enabled then support for the ISA bus is
+	  not included and any such busses used in DT will be treated as
+	  typical simple-bus compatible busses. This will lead to
+	  mistranslation of device addresses, so ensure that this is
+	  enabled if your board does include an ISA bus.
+
 endmenu
-- 
cgit v0.10.2


From 49717b18be6760cc560767ed3a0c72ecfd3cb076 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:25 +0100
Subject: fdt: Document the rest of struct of_bus

Provide some documentation for the fields of struct of_bus, for
consistency with that provided for the new match field.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 96b5d0a..5d8eb12 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -966,10 +966,29 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
 
 /**
  * struct of_bus - Callbacks for bus specific translators
+ * @name:	A string used to identify this bus in debug output.
+ * @addresses:	The name of the DT property from which addresses are
+ *		to be read, typically "reg".
  * @match:	Return non-zero if the node whose parent is at
  *		parentoffset in the FDT blob corresponds to a bus
  *		of this type, otherwise return zero. If NULL a match
  *		is assumed.
+ * @count_cells:Count how many cells (be32 values) a node whose parent
+ *		is at parentoffset in the FDT blob will require to
+ *		represent its address (written to *addrc) & size
+ *		(written to *sizec).
+ * @map:	Map the address addr from the address space of this
+ *		bus to that of its parent, making use of the ranges
+ *		read from DT to an array at range. na and ns are the
+ *		number of cells (be32 values) used to hold and address
+ *		or size, respectively, for this bus. pna is the number
+ *		of cells used to hold an address for the parent bus.
+ *		Returns the address in the address space of the parent
+ *		bus.
+ * @translate:	Update the value of the address cells at addr within an
+ *		FDT by adding offset to it. na specifies the number of
+ *		cells used to hold the address being translated. Returns
+ *		zero on success, non-zero on error.
  *
  * Each bus type will include a struct of_bus in the of_busses array,
  * providing implementations of some or all of the functions used to
-- 
cgit v0.10.2


From df8ec55d52c74a9c73df549da846f5e6c5acb5ab Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:26 +0100
Subject: dm: ns16550: Don't map_physmem for I/O ports

If the UART is to be accessed using I/O port accessors (inb & outb) then
using map_physmem doesn't make sense, since it operates in a different
memory space. Remove the call to map_physmem when
CONFIG_SYS_NS16550_PORT_MAPPED is defined, allowing I/O port addresses
to not be mangled by the incorrect mapping.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 28da9dd..d7a3cf6 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -100,7 +100,8 @@ static void ns16550_writeb(NS16550_t port, int offset, int value)
 	unsigned char *addr;
 
 	offset *= 1 << plat->reg_shift;
-	addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+	addr = (unsigned char *)plat->base + offset;
+
 	/*
 	 * As far as we know it doesn't make sense to support selection of
 	 * these options at run-time, so use the existing CONFIG options.
@@ -114,7 +115,7 @@ static int ns16550_readb(NS16550_t port, int offset)
 	unsigned char *addr;
 
 	offset *= 1 << plat->reg_shift;
-	addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+	addr = (unsigned char *)plat->base + offset;
 
 	return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
 }
@@ -400,7 +401,12 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 	plat->base = addr;
+#else
+	plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+
 	plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 				     "reg-offset", 0);
 	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-- 
cgit v0.10.2


From 2e7eb12e5c81dedaff12b0cea2341dc681d8c726 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:27 +0100
Subject: malta: Tidy up UART address selection

The address of the UART differs based upon the system controller because
it's actually within the I/O port region, which is in a different
location for each system controller. Rather than handling this as 2
UARTs with the correct one selected at runtime, use I/O port accessors
for the UART such that access to it gets translated into the I/O port
region automatically.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 3a9e780..4955043 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -12,7 +12,6 @@
 #include <pci_gt64120.h>
 #include <pci_msc01.h>
 #include <rtc.h>
-#include <serial.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
@@ -161,18 +160,6 @@ int misc_init_r(void)
 	return 0;
 }
 
-struct serial_device *default_serial_console(void)
-{
-	switch (malta_sys_con()) {
-	case SYSCON_GT64120:
-		return &eserial1_device;
-
-	default:
-	case SYSCON_MSC01:
-		return &eserial2_device;
-	}
-}
-
 void pci_init_board(void)
 {
 	pci_dev_t bdf;
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 04dca71..1c3c83c 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -67,10 +67,10 @@
 #define CONFIG_BAUDRATE			115200
 
 #define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_PORT_MAPPED
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(115200 * 16)
-#define CONFIG_SYS_NS16550_COM1		0xb80003f8
-#define CONFIG_SYS_NS16550_COM2		0xbb0003f8
+#define CONFIG_SYS_NS16550_COM1		0x3f8
 #define CONFIG_CONS_INDEX		1
 
 /*
-- 
cgit v0.10.2


From 6242aa137427f6da6ca47e7a8c9a9f78ad63e00d Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 07:43:28 +0100
Subject: malta: Use device model & tree for UART

Make use of device model & device tree to probe the UART driver. This is
the initial step in bringing Malta up to date with driver model, and
allows for cleaner handling of the different I/O addresses for different
system controllers by specifying the ISA bus address instead of a
translated memory address.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dc34c18..53363e3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -23,7 +23,11 @@ config TARGET_QEMU_MIPS
 
 config TARGET_MALTA
 	bool "Support malta"
+	select DM
+	select DM_SERIAL
 	select DYNAMIC_IO_PORT_BASE
+	select OF_CONTROL
+	select OF_ISA_BUS
 	select SUPPORTS_BIG_ENDIAN
 	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index a94b745..2f04d73 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -4,6 +4,7 @@
 
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
new file mode 100644
index 0000000..d339229
--- /dev/null
+++ b/arch/mips/dts/mti,malta.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000;	/* Exception vectors */
+/memreserve/ 0x000f0000 0x00010000;	/* PIIX4 ISA memory */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "mti,malta";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	isa@0 {
+		compatible = "isa";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <1 0 0 0x1000>;
+
+		uart0: serial@3f8 {
+			compatible = "ns16550a";
+
+			reg = <1 0x3f8 0x40>;
+			reg-shift = <0>;
+
+			clock-frequency = <1843200>;
+
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index a16f10b..3c3bb16 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,5 +1,6 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="malta # "
 # CONFIG_CMD_LOADB is not set
@@ -9,5 +10,6 @@ CONFIG_SYS_PROMPT="malta # "
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 5289797..b245d91 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
 CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="maltael # "
 # CONFIG_CMD_LOADB is not set
@@ -10,5 +11,6 @@ CONFIG_SYS_PROMPT="maltael # "
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 1c3c83c..e03935b 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -65,13 +65,7 @@
  * Serial driver
  */
 #define CONFIG_BAUDRATE			115200
-
-#define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_PORT_MAPPED
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(115200 * 16)
-#define CONFIG_SYS_NS16550_COM1		0x3f8
-#define CONFIG_CONS_INDEX		1
 
 /*
  * Flash configuration
-- 
cgit v0.10.2


From ec35e12331512cf5ed0f22005d7b6fb4ccc35969 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Tue, 17 May 2016 11:56:39 +0100
Subject: MIPS: Move CONFIG_SYS_TEXT_BASE to Kconfig

Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board
Kconfig files matching what was present in their config headers. This
will make it cleaner to conditionalise the value for Malta based on 32
vs 64 bit builds.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/Kconfig b/Kconfig
index f53759a..4b46216 100644
--- a/Kconfig
+++ b/Kconfig
@@ -268,7 +268,7 @@ config SYS_EXTRA_OPTIONS
 
 config SYS_TEXT_BASE
 	depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
-		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE
+		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
 	depends on !EFI_APP
 	hex "Text Base"
 	help
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index b813adb..342ec59 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -9,6 +9,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "dbau1x00"
 
+config SYS_TEXT_BASE
+	default 0xbfc00000
+
 menu "dbau1x00 board options"
 
 choice
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 4c06d0c..2bb8e8b 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -9,4 +9,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "malta"
 
+config SYS_TEXT_BASE
+	default 0xbe000000
+
 endif
diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig
index 8acb393..4f08e98 100644
--- a/board/microchip/pic32mzda/Kconfig
+++ b/board/microchip/pic32mzda/Kconfig
@@ -10,4 +10,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "pic32mzdask"
 
+config SYS_TEXT_BASE
+	default 0x9d004000
+
 endif
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index c518079..535a77b 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -9,6 +9,9 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "vct"
 
+config SYS_TEXT_BASE
+	default 0x87000000
+
 menu "vct board options"
 
 choice
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 251db6a..236a410 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -9,4 +9,7 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "pb1x00"
 
+config SYS_TEXT_BASE
+	default 0x83800000
+
 endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index f7e768a..c3ecc8f 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -9,4 +9,7 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "ap121"
 
+config SYS_TEXT_BASE
+	default 0x9f000000
+
 endif
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 4cdac0d..5ea5d6f 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -9,4 +9,7 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "ap143"
 
+config SYS_TEXT_BASE
+	default 0x9f000000
+
 endif
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 18d78b5..3de1f44 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -7,4 +7,8 @@ config SYS_CONFIG_NAME
 	default "qemu-mips" if 32BIT
 	default "qemu-mips64" if 64BIT
 
+config SYS_TEXT_BASE
+	default 0xbfc00000 if 32BIT
+	default 0xffffffffbfc00000 if 64BIT
+
 endif
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 902abf5..65785bd 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -12,4 +12,7 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "tplink_wdr4300"
 
+config SYS_TEXT_BASE
+	default 0xa1000000
+
 endif
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 2beffa4..6f69f31 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_TEXT_BASE            0x9f000000
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 7b69e10..f907c02 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_TEXT_BASE            0x9f000000
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index eb0a87c..68d9e36 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -139,12 +139,6 @@
 #define CONFIG_SYS_FLASH_CFI           1
 #define CONFIG_FLASH_CFI_DRIVER    1
 
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-#define CONFIG_SYS_TEXT_BASE		0xbfc00000
-/* RAM version */
-/* #define CONFIG_SYS_TEXT_BASE		0x80100000 */
-
 #define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
diff --git a/include/configs/malta.h b/include/configs/malta.h
index e03935b..a369678 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -37,7 +37,6 @@
 /*
  * Memory map
  */
-#define CONFIG_SYS_TEXT_BASE		0xbe000000 /* Rom version */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index caf75a6..869768a 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -80,12 +80,6 @@
 #define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
 
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-/* #define CONFIG_SYS_TEXT_BASE		0xbfc00000 */
-/* SDRAM version */
-#define CONFIG_SYS_TEXT_BASE		0x83800000
-
 #define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 108c6a2..fb2e41f 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -10,7 +10,6 @@
 #define __PIC32MZDASK_CONFIG_H
 
 /* System Configuration */
-#define CONFIG_SYS_TEXT_BASE		0x9d004000 /* .text */
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*--------------------------------------------
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 702967c..246ee01 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -107,7 +107,6 @@
  * FLASH and environment organization
  */
 /* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE		0xbfc00000 /* Rom version */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 2394549..60a3a71 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -107,7 +107,6 @@
  * FLASH and environment organization
  */
 /* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE		0xffffffffbfc00000 /* Rom version */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 2b9e92e..09a69fe 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_TEXT_BASE		0xa1000000
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 6489e08..68eb089 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -32,7 +32,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
 
-#define CONFIG_SYS_TEXT_BASE		0x87000000
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
-- 
cgit v0.10.2


From ecc9d26062c9dd6d0752c988a54b95453c20c749 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:17:42 +0200
Subject: mips: Allow overriding start.S in SPL

Certain chips, like the JZ47xx, have extreme size constraints on the
SPL size and require custom start.S . Allow overriding the start.S
the same way ARM MXS does it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 655a493..0b5dbb6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -4,6 +4,12 @@
 
 head-y := arch/mips/cpu/start.o
 
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
 libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
-- 
cgit v0.10.2


From 1ad3a6fb5b9eb8444281c3975de6c6b7e1549c53 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:17:07 +0200
Subject: mips: Drop JZ4740 remnants

Remove the remnants of JZ4740 support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 3f230b0..37f8ed5 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -15,14 +15,6 @@ struct arch_global_data {
 #ifdef CONFIG_DYNAMIC_IO_PORT_BASE
 	unsigned long io_port_base;
 #endif
-#ifdef CONFIG_JZSOC
-	/* There are other clocks in the jz4740 */
-	unsigned long per_clk;	/* Peripheral bus clock */
-	unsigned long dev_clk;	/* Device clock */
-	unsigned long sys_clk;
-	unsigned long tbl;
-	unsigned long lastinc;
-#endif
 #ifdef CONFIG_ARCH_ATH79
 	unsigned long id;
 	unsigned long soc;
diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
deleted file mode 100644
index 7a7cfff..0000000
--- a/arch/mips/include/asm/jz4740.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
- * head file for Ingenic Semiconductor's JZ4740 CPU.
- */
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-/* Boot ROM Specification  */
-/* NOR Boot config */
-#define JZ4740_NORBOOT_8BIT	0x00000000	/* 8-bit data bus flash */
-#define JZ4740_NORBOOT_16BIT	0x10101010	/* 16-bit data bus flash */
-#define JZ4740_NORBOOT_32BIT	0x20202020	/* 32-bit data bus flash */
-/* NAND Boot config */
-#define JZ4740_NANDBOOT_B8R3	0xffffffff	/* 8-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B8R2	0xf0f0f0f0	/* 8-bit bus & 2 row cycles */
-#define JZ4740_NANDBOOT_B16R3	0x0f0f0f0f	/* 16-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B16R2	0x00000000	/* 16-bit bus & 2 row cycles */
-
-/* 1st-level interrupts */
-#define JZ4740_IRQ_I2C		1
-#define JZ4740_IRQ_UHC		3
-#define JZ4740_IRQ_UART0	9
-#define JZ4740_IRQ_SADC		12
-#define JZ4740_IRQ_MSC		14
-#define JZ4740_IRQ_RTC		15
-#define JZ4740_IRQ_SSI		16
-#define JZ4740_IRQ_CIM		17
-#define JZ4740_IRQ_AIC		18
-#define JZ4740_IRQ_ETH		19
-#define JZ4740_IRQ_DMAC		20
-#define JZ4740_IRQ_TCU2		21
-#define JZ4740_IRQ_TCU1		22
-#define JZ4740_IRQ_TCU0		23
-#define JZ4740_IRQ_UDC		24
-#define JZ4740_IRQ_GPIO3	25
-#define JZ4740_IRQ_GPIO2	26
-#define JZ4740_IRQ_GPIO1	27
-#define JZ4740_IRQ_GPIO0	28
-#define JZ4740_IRQ_IPU		29
-#define JZ4740_IRQ_LCD		30
-/* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA_0	32  /* 32 to 37 for DMAC channel 0 to 5 */
-#define JZ4740_IRQ_GPIO_0	48  /* 48 to 175 for GPIO pin 0 to 127 */
-
-/* Register Definitions */
-#define JZ4740_CPM_BASE		0x10000000
-#define JZ4740_INTC_BASE	0x10001000
-#define JZ4740_TCU_BASE		0x10002000
-#define JZ4740_WDT_BASE		0x10002000
-#define JZ4740_RTC_BASE		0x10003000
-#define JZ4740_GPIO_BASE	0x10010000
-#define JZ4740_AIC_BASE		0x10020000
-#define JZ4740_ICDC_BASE	0x10020000
-#define JZ4740_MSC_BASE		0x10021000
-#define JZ4740_UART0_BASE	0x10030000
-#define JZ4740_I2C_BASE		0x10042000
-#define JZ4740_SSI_BASE		0x10043000
-#define JZ4740_SADC_BASE	0x10070000
-#define JZ4740_EMC_BASE		0x13010000
-#define JZ4740_DMAC_BASE	0x13020000
-#define JZ4740_UHC_BASE		0x13030000
-#define JZ4740_UDC_BASE		0x13040000
-#define JZ4740_LCD_BASE		0x13050000
-#define JZ4740_SLCD_BASE	0x13050000
-#define JZ4740_CIM_BASE		0x13060000
-#define JZ4740_ETH_BASE		0x13100000
-
-/* 8bit Mode Register of SDRAM bank 0 */
-#define JZ4740_EMC_SDMR0	(JZ4740_EMC_BASE + 0xa000)
-
-/* GPIO (General-Purpose I/O Ports) */
-/*  = 0,1,2,3 */
-#define GPIO_PXPIN(n)	\
-	(JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
-#define GPIO_PXDAT(n)	\
-	(JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
-#define GPIO_PXDATS(n)	\
-	(JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
-#define GPIO_PXDATC(n)	\
-	(JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
-#define GPIO_PXIM(n)	\
-	(JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
-#define GPIO_PXIMS(n)	\
-	(JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
-#define GPIO_PXIMC(n)	\
-	(JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
-#define GPIO_PXPE(n)	\
-	(JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
-#define GPIO_PXPES(n)	\
-	(JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
-#define GPIO_PXPEC(n)	\
-	(JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
-#define GPIO_PXFUN(n)	\
-	(JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
-#define GPIO_PXFUNS(n)	\
-	(JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
-#define GPIO_PXFUNC(n)	\
-	(JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
-#define GPIO_PXSEL(n)	\
-	(JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
-#define GPIO_PXSELS(n)	\
-	(JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
-#define GPIO_PXSELC(n)	\
-	(JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
-#define GPIO_PXDIR(n)	\
-	(JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
-#define GPIO_PXDIRS(n)	\
-	(JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
-#define GPIO_PXDIRC(n)	\
-	(JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
-#define GPIO_PXTRG(n)	\
-	(JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
-#define GPIO_PXTRGS(n)	\
-	(JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
-#define GPIO_PXTRGC(n)	\
-	(JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT	24
-#define EMC_SMCR_STRV_MASK	(0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT	20
-#define EMC_SMCR_TAW_MASK	(0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT	16
-#define EMC_SMCR_TBP_MASK	(0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT	12
-#define EMC_SMCR_TAH_MASK	(0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT	8
-#define EMC_SMCR_TAS_MASK	(0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT		6
-#define EMC_SMCR_BW_MASK	(0x03 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_8BIT	(0 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_16BIT	(1 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_32BIT	(2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM		(1 << 3)
-#define EMC_SMCR_BL_BIT		1
-#define EMC_SMCR_BL_MASK	(0x03 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_4		(0 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_8		(1 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_16	(2 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_32	(3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT		(1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT	8
-#define EMC_SACR_BASE_MASK	(0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT	0
-#define EMC_SACR_MASK_MASK	(0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3		(1 << 5)
-#define EMC_NFCSR_NFE3		(1 << 4)
-#define EMC_NFCSR_NFCE2		(1 << 3)
-#define EMC_NFCSR_NFE2		(1 << 2)
-#define EMC_NFCSR_NFCE1		(1 << 1)
-#define EMC_NFCSR_NFE1		(1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY		(1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING	(0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING	(1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING	(0 << 2) /* Use HAMMING Correction Algorithm */
-#define EMC_NFECR_RS		(1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST		(1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE		(1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT	16
-#define EMC_NFECC_ECC2_MASK	(0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT	8
-#define EMC_NFECC_ECC1_MASK	(0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT	0
-#define EMC_NFECC_ECC0_MASK	(0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT	29       /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK	(0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF		(1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF		(1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF		(1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR	(1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR		(1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE	(1 << 4) /* Padding Finished Interrupt */
-#define EMC_NFINTE_DECFE	(1 << 3) /* Decoding Finished Interrupt */
-#define EMC_NFINTE_ENCFE	(1 << 2) /* Encoding Finished Interrupt */
-#define EMC_NFINTE_UNCORE	(1 << 1) /* Uncorrectable Error Occurred Intr */
-#define EMC_NFINTE_ERRE		(1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT	16       /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK	(0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT	0        /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK	(0x1ff << EMC_NFERR_MASK_BIT)
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT		31
-#define EMC_DMCR_BW		(1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT		26
-#define EMC_DMCR_CA_MASK	(0x07 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_8		(0 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_9		(1 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_10	(2 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_11	(3 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_12	(4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE		(1 << 25)
-#define EMC_DMCR_RFSH		(1 << 24)
-#define EMC_DMCR_MRSET		(1 << 23)
-#define EMC_DMCR_RA_BIT		20
-#define EMC_DMCR_RA_MASK	(0x03 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_11	(0 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_12	(1 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_13	(2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT		19
-#define EMC_DMCR_BA		(1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM		(1 << 18)
-#define EMC_DMCR_EPIN		(1 << 17)
-#define EMC_DMCR_TRAS_BIT	13
-#define EMC_DMCR_TRAS_MASK	(0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT	11
-#define EMC_DMCR_RCD_MASK	(0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT	8
-#define EMC_DMCR_TPC_MASK	(0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT	5
-#define EMC_DMCR_TRWL_MASK	(0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT	2
-#define EMC_DMCR_TRC_MASK	(0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT	0
-#define EMC_DMCR_TCL_MASK	(0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF		(1 << 7)
-#define EMC_RTCSR_CKS_BIT	0
-#define EMC_RTCSR_CKS_MASK	(0x07 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_DISABLE	(0 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4	(1 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_16	(2 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_64	(3 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_256	(4 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_1024	(5 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_2048	(6 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4096	(7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT	8
-#define EMC_DMAR_BASE_MASK	(0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT	0
-#define EMC_DMAR_MASK_MASK	(0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM		(1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT		7        /* Operating Mode */
-#define EMC_SDMR_OM_MASK	(3 << EMC_SDMR_OM_BIT)
-  #define EMC_SDMR_OM_NORMAL	(0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT	4        /* CAS Latency */
-#define EMC_SDMR_CAS_MASK	(7 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_1	(1 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_2	(2 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_3	(3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT		3        /* Burst Type */
-#define EMC_SDMR_BT_MASK	(1 << EMC_SDMR_BT_BIT)
-  #define EMC_SDMR_BT_SEQ	(0 << EMC_SDMR_BT_BIT) /* Sequential */
-  #define EMC_SDMR_BT_INT	(1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT		0        /* Burst Length */
-#define EMC_SDMR_BL_MASK	(7 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_1		(0 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_2		(1 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_4		(2 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_8		(3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
-	(EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
-	(EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
-	(EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
-	(EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY	(1 << 7)  /* Write Ready Flag */
-#define RTC_RCR_HZ	(1 << 6)  /* 1Hz Flag */
-#define RTC_RCR_HZIE	(1 << 5)  /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF	(1 << 4)  /* Alarm Flag */
-#define RTC_RCR_AIE	(1 << 3)  /* Alarm Interrupt Enable */
-#define RTC_RCR_AE	(1 << 2)  /* Alarm Enable */
-#define RTC_RCR_RTCE	(1 << 0)  /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK		(1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT	16
-#define RTC_RGR_ADJC_MASK	(0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT	0
-#define RTC_RGR_NC1HZ_MASK	(0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD		(1 << 0)  /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT		5
-#define RTC_HWFCR_MASK		(0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT		5
-#define RTC_HRCR_MASK		(0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM		(1 << 0)  /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR		(1 << 5)  /* Hibernate reset */
-#define RTC_HWRSR_PPR		(1 << 4)  /* PPR reset */
-#define RTC_HWRSR_PIN		(1 << 1)  /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM		(1 << 0)  /* RTC alarm status bit */
-
-/* Clock Control Register */
-#define CPM_CPCCR_I2CS		(1 << 31)
-#define CPM_CPCCR_CLKOEN	(1 << 30)
-#define CPM_CPCCR_UCS		(1 << 29)
-#define CPM_CPCCR_UDIV_BIT	23
-#define CPM_CPCCR_UDIV_MASK	(0x3f << CPM_CPCCR_UDIV_BIT)
-#define CPM_CPCCR_CE		(1 << 22)
-#define CPM_CPCCR_PCS		(1 << 21)
-#define CPM_CPCCR_LDIV_BIT	16
-#define CPM_CPCCR_LDIV_MASK	(0x1f << CPM_CPCCR_LDIV_BIT)
-#define CPM_CPCCR_MDIV_BIT	12
-#define CPM_CPCCR_MDIV_MASK	(0x0f << CPM_CPCCR_MDIV_BIT)
-#define CPM_CPCCR_PDIV_BIT	8
-#define CPM_CPCCR_PDIV_MASK	(0x0f << CPM_CPCCR_PDIV_BIT)
-#define CPM_CPCCR_HDIV_BIT	4
-#define CPM_CPCCR_HDIV_MASK	(0x0f << CPM_CPCCR_HDIV_BIT)
-#define CPM_CPCCR_CDIV_BIT	0
-#define CPM_CPCCR_CDIV_MASK	(0x0f << CPM_CPCCR_CDIV_BIT)
-
-/* I2S Clock Divider Register */
-#define CPM_I2SCDR_I2SDIV_BIT	0
-#define CPM_I2SCDR_I2SDIV_MASK	(0x1ff << CPM_I2SCDR_I2SDIV_BIT)
-
-/* LCD Pixel Clock Divider Register */
-#define CPM_LPCDR_PIXDIV_BIT	0
-#define CPM_LPCDR_PIXDIV_MASK	(0x1ff << CPM_LPCDR_PIXDIV_BIT)
-
-/* MSC Clock Divider Register */
-#define CPM_MSCCDR_MSCDIV_BIT	0
-#define CPM_MSCCDR_MSCDIV_MASK	(0x1f << CPM_MSCCDR_MSCDIV_BIT)
-
-/* PLL Control Register */
-#define CPM_CPPCR_PLLM_BIT	23
-#define CPM_CPPCR_PLLM_MASK	(0x1ff << CPM_CPPCR_PLLM_BIT)
-#define CPM_CPPCR_PLLN_BIT	18
-#define CPM_CPPCR_PLLN_MASK	(0x1f << CPM_CPPCR_PLLN_BIT)
-#define CPM_CPPCR_PLLOD_BIT	16
-#define CPM_CPPCR_PLLOD_MASK	(0x03 << CPM_CPPCR_PLLOD_BIT)
-#define CPM_CPPCR_PLLS		(1 << 10)
-#define CPM_CPPCR_PLLBP		(1 << 9)
-#define CPM_CPPCR_PLLEN		(1 << 8)
-#define CPM_CPPCR_PLLST_BIT	0
-#define CPM_CPPCR_PLLST_MASK	(0xff << CPM_CPPCR_PLLST_BIT)
-
-/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT	3
-#define CPM_LCR_DOZE_DUTY_MASK	(0x1f << CPM_LCR_DOZE_DUTY_BIT)
-#define CPM_LCR_DOZE_ON		(1 << 2)
-#define CPM_LCR_LPM_BIT		0
-#define CPM_LCR_LPM_MASK	(0x3 << CPM_LCR_LPM_BIT)
-  #define CPM_LCR_LPM_IDLE	(0x0 << CPM_LCR_LPM_BIT)
-  #define CPM_LCR_LPM_SLEEP	(0x1 << CPM_LCR_LPM_BIT)
-
-/* Clock Gate Register */
-#define CPM_CLKGR_UART1		(1 << 15)
-#define CPM_CLKGR_UHC		(1 << 14)
-#define CPM_CLKGR_IPU		(1 << 13)
-#define CPM_CLKGR_DMAC		(1 << 12)
-#define CPM_CLKGR_UDC		(1 << 11)
-#define CPM_CLKGR_LCD		(1 << 10)
-#define CPM_CLKGR_CIM		(1 << 9)
-#define CPM_CLKGR_SADC		(1 << 8)
-#define CPM_CLKGR_MSC		(1 << 7)
-#define CPM_CLKGR_AIC1		(1 << 6)
-#define CPM_CLKGR_AIC2		(1 << 5)
-#define CPM_CLKGR_SSI		(1 << 4)
-#define CPM_CLKGR_I2C		(1 << 3)
-#define CPM_CLKGR_RTC		(1 << 2)
-#define CPM_CLKGR_TCU		(1 << 1)
-#define CPM_CLKGR_UART0		(1 << 0)
-
-/* Sleep Control Register */
-#define CPM_SCR_O1ST_BIT	8
-#define CPM_SCR_O1ST_MASK	(0xff << CPM_SCR_O1ST_BIT)
-#define CPM_SCR_UDCPHY_ENABLE	(1 << 6)
-#define CPM_SCR_USBPHY_DISABLE	(1 << 7)
-#define CPM_SCR_OSC_ENABLE	(1 << 4)
-
-/* Hibernate Control Register */
-#define CPM_HCR_PD		(1 << 0)
-
-/* Wakeup Filter Counter Register in Hibernate Mode */
-#define CPM_HWFCR_TIME_BIT	0
-#define CPM_HWFCR_TIME_MASK	(0x3ff << CPM_HWFCR_TIME_BIT)
-
-/* Reset Counter Register in Hibernate Mode */
-#define CPM_HRCR_TIME_BIT	0
-#define CPM_HRCR_TIME_MASK	(0x7f << CPM_HRCR_TIME_BIT)
-
-/* Wakeup Control Register in Hibernate Mode */
-#define CPM_HWCR_WLE_LOW	(0 << 2)
-#define CPM_HWCR_WLE_HIGH	(1 << 2)
-#define CPM_HWCR_PIN_WAKEUP	(1 << 1)
-#define CPM_HWCR_RTC_WAKEUP	(1 << 0)
-
-/* Wakeup Status Register in Hibernate Mode */
-#define CPM_HWSR_WSR_PIN	(1 << 1)
-#define CPM_HWSR_WSR_RTC	(1 << 0)
-
-/* Reset Status Register */
-#define CPM_RSR_HR		(1 << 2)
-#define CPM_RSR_WR		(1 << 1)
-#define CPM_RSR_PR		(1 << 0)
-
-/* Register definitions */
-#define TCU_TCSR_PWM_SD		(1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH	(1 << 8)
-#define TCU_TCSR_PWM_EN		(1 << 7)
-#define TCU_TCSR_PRESCALE_BIT	3
-#define TCU_TCSR_PRESCALE_MASK	(0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1	(0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4	(0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16	(0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64	(0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256	(0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024	(0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN		(1 << 2)
-#define TCU_TCSR_RTC_EN		(1 << 1)
-#define TCU_TCSR_PCK_EN		(1 << 0)
-
-#define TCU_TER_TCEN5		(1 << 5)
-#define TCU_TER_TCEN4		(1 << 4)
-#define TCU_TER_TCEN3		(1 << 3)
-#define TCU_TER_TCEN2		(1 << 2)
-#define TCU_TER_TCEN1		(1 << 1)
-#define TCU_TER_TCEN0		(1 << 0)
-
-#define TCU_TESR_TCST5		(1 << 5)
-#define TCU_TESR_TCST4		(1 << 4)
-#define TCU_TESR_TCST3		(1 << 3)
-#define TCU_TESR_TCST2		(1 << 2)
-#define TCU_TESR_TCST1		(1 << 1)
-#define TCU_TESR_TCST0		(1 << 0)
-
-#define TCU_TECR_TCCL5		(1 << 5)
-#define TCU_TECR_TCCL4		(1 << 4)
-#define TCU_TECR_TCCL3		(1 << 3)
-#define TCU_TECR_TCCL2		(1 << 2)
-#define TCU_TECR_TCCL1		(1 << 1)
-#define TCU_TECR_TCCL0		(1 << 0)
-
-#define TCU_TFR_HFLAG5		(1 << 21)
-#define TCU_TFR_HFLAG4		(1 << 20)
-#define TCU_TFR_HFLAG3		(1 << 19)
-#define TCU_TFR_HFLAG2		(1 << 18)
-#define TCU_TFR_HFLAG1		(1 << 17)
-#define TCU_TFR_HFLAG0		(1 << 16)
-#define TCU_TFR_FFLAG5		(1 << 5)
-#define TCU_TFR_FFLAG4		(1 << 4)
-#define TCU_TFR_FFLAG3		(1 << 3)
-#define TCU_TFR_FFLAG2		(1 << 2)
-#define TCU_TFR_FFLAG1		(1 << 1)
-#define TCU_TFR_FFLAG0		(1 << 0)
-
-#define TCU_TFSR_HFLAG5		(1 << 21)
-#define TCU_TFSR_HFLAG4		(1 << 20)
-#define TCU_TFSR_HFLAG3		(1 << 19)
-#define TCU_TFSR_HFLAG2		(1 << 18)
-#define TCU_TFSR_HFLAG1		(1 << 17)
-#define TCU_TFSR_HFLAG0		(1 << 16)
-#define TCU_TFSR_FFLAG5		(1 << 5)
-#define TCU_TFSR_FFLAG4		(1 << 4)
-#define TCU_TFSR_FFLAG3		(1 << 3)
-#define TCU_TFSR_FFLAG2		(1 << 2)
-#define TCU_TFSR_FFLAG1		(1 << 1)
-#define TCU_TFSR_FFLAG0		(1 << 0)
-
-#define TCU_TFCR_HFLAG5		(1 << 21)
-#define TCU_TFCR_HFLAG4		(1 << 20)
-#define TCU_TFCR_HFLAG3		(1 << 19)
-#define TCU_TFCR_HFLAG2		(1 << 18)
-#define TCU_TFCR_HFLAG1		(1 << 17)
-#define TCU_TFCR_HFLAG0		(1 << 16)
-#define TCU_TFCR_FFLAG5		(1 << 5)
-#define TCU_TFCR_FFLAG4		(1 << 4)
-#define TCU_TFCR_FFLAG3		(1 << 3)
-#define TCU_TFCR_FFLAG2		(1 << 2)
-#define TCU_TFCR_FFLAG1		(1 << 1)
-#define TCU_TFCR_FFLAG0		(1 << 0)
-
-#define TCU_TMR_HMASK5		(1 << 21)
-#define TCU_TMR_HMASK4		(1 << 20)
-#define TCU_TMR_HMASK3		(1 << 19)
-#define TCU_TMR_HMASK2		(1 << 18)
-#define TCU_TMR_HMASK1		(1 << 17)
-#define TCU_TMR_HMASK0		(1 << 16)
-#define TCU_TMR_FMASK5		(1 << 5)
-#define TCU_TMR_FMASK4		(1 << 4)
-#define TCU_TMR_FMASK3		(1 << 3)
-#define TCU_TMR_FMASK2		(1 << 2)
-#define TCU_TMR_FMASK1		(1 << 1)
-#define TCU_TMR_FMASK0		(1 << 0)
-
-#define TCU_TMSR_HMST5		(1 << 21)
-#define TCU_TMSR_HMST4		(1 << 20)
-#define TCU_TMSR_HMST3		(1 << 19)
-#define TCU_TMSR_HMST2		(1 << 18)
-#define TCU_TMSR_HMST1		(1 << 17)
-#define TCU_TMSR_HMST0		(1 << 16)
-#define TCU_TMSR_FMST5		(1 << 5)
-#define TCU_TMSR_FMST4		(1 << 4)
-#define TCU_TMSR_FMST3		(1 << 3)
-#define TCU_TMSR_FMST2		(1 << 2)
-#define TCU_TMSR_FMST1		(1 << 1)
-#define TCU_TMSR_FMST0		(1 << 0)
-
-#define TCU_TMCR_HMCL5		(1 << 21)
-#define TCU_TMCR_HMCL4		(1 << 20)
-#define TCU_TMCR_HMCL3		(1 << 19)
-#define TCU_TMCR_HMCL2		(1 << 18)
-#define TCU_TMCR_HMCL1		(1 << 17)
-#define TCU_TMCR_HMCL0		(1 << 16)
-#define TCU_TMCR_FMCL5		(1 << 5)
-#define TCU_TMCR_FMCL4		(1 << 4)
-#define TCU_TMCR_FMCL3		(1 << 3)
-#define TCU_TMCR_FMCL2		(1 << 2)
-#define TCU_TMCR_FMCL1		(1 << 1)
-#define TCU_TMCR_FMCL0		(1 << 0)
-
-#define TCU_TSR_WDTS		(1 << 16)
-#define TCU_TSR_STOP5		(1 << 5)
-#define TCU_TSR_STOP4		(1 << 4)
-#define TCU_TSR_STOP3		(1 << 3)
-#define TCU_TSR_STOP2		(1 << 2)
-#define TCU_TSR_STOP1		(1 << 1)
-#define TCU_TSR_STOP0		(1 << 0)
-
-#define TCU_TSSR_WDTSS		(1 << 16)
-#define TCU_TSSR_STPS5		(1 << 5)
-#define TCU_TSSR_STPS4		(1 << 4)
-#define TCU_TSSR_STPS3		(1 << 3)
-#define TCU_TSSR_STPS2		(1 << 2)
-#define TCU_TSSR_STPS1		(1 << 1)
-#define TCU_TSSR_STPS0		(1 << 0)
-
-#define TCU_TSSR_WDTSC		(1 << 16)
-#define TCU_TSSR_STPC5		(1 << 5)
-#define TCU_TSSR_STPC4		(1 << 4)
-#define TCU_TSSR_STPC3		(1 << 3)
-#define TCU_TSSR_STPC2		(1 << 2)
-#define TCU_TSSR_STPC1		(1 << 1)
-#define TCU_TSSR_STPC0		(1 << 0)
-
-/* Register definition */
-#define WDT_TCSR_PRESCALE_BIT	3
-#define WDT_TCSR_PRESCALE_MASK	(0x7 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1	(0x0 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE4	(0x1 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE16	(0x2 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE64	(0x3 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE256	(0x4 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1024	(0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN		(1 << 2)
-#define WDT_TCSR_RTC_EN		(1 << 1)
-#define WDT_TCSR_PCK_EN		(1 << 0)
-#define WDT_TCER_TCEN		(1 << 0)
-
-/*
- * Define macros for UART_IER
- * UART Interrupt Enable Register
- */
-#define UART_IER_RIE	(1 << 0) /* 0: receive fifo full interrupt disable */
-#define UART_IER_TIE	(1 << 1) /* 0: transmit fifo empty interrupt disable */
-#define UART_IER_RLIE	(1 << 2) /* 0: receive line status interrupt disable */
-#define UART_IER_MIE	(1 << 3) /* 0: modem status interrupt disable */
-#define UART_IER_RTIE	(1 << 4) /* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UART_ISR
- * UART Interrupt Status Register
- */
-#define UART_ISR_IP	(1 << 0) /* 0: interrupt is pending 1: no interrupt */
-#define UART_ISR_IID	(7 << 1) /* Source of Interrupt */
-#define UART_ISR_IID_MSI  (0 << 1) /* Modem status interrupt */
-#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
-#define UART_ISR_IID_RDI  (2 << 1) /* Receiver data interrupt */
-#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
-/* FIFO mode select, set when UART_FCR.FE is set to 1 */
-#define UART_ISR_FFMS	(3 << 6)
-#define UART_ISR_FFMS_NO_FIFO	(0 << 6)
-#define UART_ISR_FFMS_FIFO_MODE	(3 << 6)
-
-/*
- * Define macros for UART_FCR
- * UART FIFO Control Register
- */
-#define UART_FCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
-#define UART_FCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
-#define UART_FCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
-#define UART_FCR_DMS	(1 << 3)	/* 0: disable DMA mode */
-#define UART_FCR_UUE	(1 << 4)	/* 0: disable UART */
-#define UART_FCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
-#define UART_FCR_RTRG_1	(0 << 6)
-#define UART_FCR_RTRG_4	(1 << 6)
-#define UART_FCR_RTRG_8	(2 << 6)
-#define UART_FCR_RTRG_15	(3 << 6)
-
-/*
- * Define macros for UART_LCR
- * UART Line Control Register
- */
-#define UART_LCR_WLEN	(3 << 0)	/* word length */
-#define UART_LCR_WLEN_5	(0 << 0)
-#define UART_LCR_WLEN_6	(1 << 0)
-#define UART_LCR_WLEN_7	(2 << 0)
-#define UART_LCR_WLEN_8	(3 << 0)
-#define UART_LCR_STOP	(1 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_1	(0 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_2	(1 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-
-#define UART_LCR_PE	(1 << 3) /* 0: parity disable */
-#define UART_LCR_PROE	(1 << 4) /* 0: even parity  1: odd parity */
-#define UART_LCR_SPAR	(1 << 5) /* 0: sticky parity disable */
-#define UART_LCR_SBRK	(1 << 6) /* write 0 normal, write 1 send break */
-/* 0: access UART_RDR/TDR/IER  1: access UART_DLLR/DLHR */
-#define UART_LCR_DLAB	(1 << 7)
-
-/*
- * Define macros for UART_LSR
- * UART Line Status Register
- */
-/* 0: receive FIFO is empty  1: receive data is ready */
-#define UART_LSR_DR	(1 << 0)
-/* 0: no overrun error */
-#define UART_LSR_ORER	(1 << 1)
-/* 0: no parity error */
-#define UART_LSR_PER	(1 << 2)
-/* 0; no framing error */
-#define UART_LSR_FER	(1 << 3)
-/* 0: no break detected  1: receive a break signal */
-#define UART_LSR_BRK	(1 << 4)
-/* 1: transmit FIFO half "empty" */
-#define UART_LSR_TDRQ	(1 << 5)
-/* 1: transmit FIFO and shift registers empty */
-#define UART_LSR_TEMT	(1 << 6)
-/* 0: no receive error  1: receive error in FIFO mode */
-#define UART_LSR_RFER	(1 << 7)
-
-/*
- * Define macros for UART_MCR
- * UART Modem Control Register
- */
-#define UART_MCR_DTR	(1 << 0) /* 0: DTR_ ouput high */
-#define UART_MCR_RTS	(1 << 1) /* 0: RTS_ output high */
-/* 0: UART_MSR.RI is set to 0 and RI_ input high */
-#define UART_MCR_OUT1	(1 << 2)
-/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
-#define UART_MCR_OUT2	(1 << 3)
-#define UART_MCR_LOOP	(1 << 4) /* 0: normal  1: loopback mode */
-#define UART_MCR_MCE	(1 << 7) /* 0: modem function is disable */
-
-/*
- * Define macros for UART_MSR
- * UART Modem Status Register
- */
-#define UART_MSR_DCTS	(1 << 0) /* 0: no change on CTS_ since last read */
-#define UART_MSR_DDSR	(1 << 1) /* 0: no change on DSR_ since last read */
-#define UART_MSR_DRI	(1 << 2) /* 0: no change on RI_  since last read */
-#define UART_MSR_DDCD	(1 << 3) /* 0: no change on DCD_ since last read */
-#define UART_MSR_CTS	(1 << 4) /* 0: CTS_ pin is high */
-#define UART_MSR_DSR	(1 << 5) /* 0: DSR_ pin is high */
-#define UART_MSR_RI	(1 << 6) /* 0: RI_ pin is high */
-#define UART_MSR_DCD	(1 << 7) /* 0: DCD_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
-#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
-#define SIRCR_TPWS  (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
-				1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TXPL  (1 << 3) /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RXPL  (1 << 4) /* 0: decoder interprets positive pulse as 0 */
-
-/* MSC Clock and Control Register (MSC_STRPCL) */
-#define MSC_STRPCL_EXIT_MULTIPLE	(1 << 7)
-#define MSC_STRPCL_EXIT_TRANSFER	(1 << 6)
-#define MSC_STRPCL_START_READWAIT	(1 << 5)
-#define MSC_STRPCL_STOP_READWAIT	(1 << 4)
-#define MSC_STRPCL_RESET		(1 << 3)
-#define MSC_STRPCL_START_OP		(1 << 2)
-#define MSC_STRPCL_CLOCK_CONTROL_BIT	0
-#define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_STOP	(0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_START	(0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-
-/* MSC Status Register (MSC_STAT) */
-#define MSC_STAT_IS_RESETTING		(1 << 15)
-#define MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)
-#define MSC_STAT_PRG_DONE		(1 << 13)
-#define MSC_STAT_DATA_TRAN_DONE		(1 << 12)
-#define MSC_STAT_END_CMD_RES		(1 << 11)
-#define MSC_STAT_DATA_FIFO_AFULL	(1 << 10)
-#define MSC_STAT_IS_READWAIT		(1 << 9)
-#define MSC_STAT_CLK_EN			(1 << 8)
-#define MSC_STAT_DATA_FIFO_FULL		(1 << 7)
-#define MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)
-#define MSC_STAT_CRC_RES_ERR		(1 << 5)
-#define MSC_STAT_CRC_READ_ERROR		(1 << 4)
-#define MSC_STAT_CRC_WRITE_ERROR_BIT	2
-#define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No error on transmission of data */
-  #define MSC_STAT_CRC_WRITE_ERROR_NO	(0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* Card observed erroneous transmission of data */
-  #define MSC_STAT_CRC_WRITE_ERROR	(1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No CRC status is sent back */
-  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-#define MSC_STAT_TIME_OUT_RES		(1 << 1)
-#define MSC_STAT_TIME_OUT_READ		(1 << 0)
-
-/* MSC Bus Clock Control Register (MSC_CLKRT) */
-#define MSC_CLKRT_CLK_RATE_BIT		0
-#define MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_1  (0x0 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_2  (0x1 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_4  (0x2 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_8  (0x3 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_16  (0x4 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_32  (0x5 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_64  (0x6 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
-
-/* MSC Command Sequence Control Register (MSC_CMDAT) */
-#define MSC_CMDAT_IO_ABORT	(1 << 11)
-#define MSC_CMDAT_BUS_WIDTH_BIT	9
-#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_DMA_EN	(1 << 8)
-#define MSC_CMDAT_INIT		(1 << 7)
-#define MSC_CMDAT_BUSY		(1 << 6)
-#define MSC_CMDAT_STREAM_BLOCK	(1 << 5)
-#define MSC_CMDAT_WRITE		(1 << 4)
-#define MSC_CMDAT_READ		(0 << 4)
-#define MSC_CMDAT_DATA_EN	(1 << 3)
-#define MSC_CMDAT_RESPONSE_BIT	0
-#define MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_NONE	(0x0 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R1	(0x1 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R2	(0x2 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R3	(0x3 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R4	(0x4 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R5	(0x5 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R6	(0x6 << MSC_CMDAT_RESPONSE_BIT)
-
-/* MSC Interrupts Mask Register (MSC_IMASK) */
-#define MSC_IMASK_SDIO			(1 << 7)
-#define MSC_IMASK_TXFIFO_WR_REQ		(1 << 6)
-#define MSC_IMASK_RXFIFO_RD_REQ		(1 << 5)
-#define MSC_IMASK_END_CMD_RES		(1 << 2)
-#define MSC_IMASK_PRG_DONE		(1 << 1)
-#define MSC_IMASK_DATA_TRAN_DONE	(1 << 0)
-
-#ifndef __ASSEMBLY__
-/* INTC (Interrupt Controller) */
-struct jz4740_intc {
-	uint32_t isr;		/* interrupt source register */
-	uint32_t imr;		/* interrupt mask register */
-	uint32_t imsr;		/* interrupt mask set register */
-	uint32_t imcr;		/* interrupt mask clear register */
-	uint32_t ipr;		/* interrupt pending register */
-};
-
-/* RTC */
-struct jz4740_rtc {
-	uint32_t rcr;		/* rtc control register */
-	uint32_t rsr;		/* rtc second register */
-	uint32_t rsar;		/* rtc second alarm register */
-	uint32_t rgr;		/* rtc regulator register */
-	uint32_t hcr;		/* hibernate control register */
-	uint32_t hwfcr;		/* hibernate wakeup filter counter reg */
-	uint32_t hrcr;		/* hibernate reset counter reg */
-	uint32_t hwcr;		/* hibernate wakeup control register */
-	uint32_t hwrsr;		/* hibernate wakeup status reg */
-	uint32_t hspr;		/* scratch pattern register */
-};
-
-/* CPM (Clock reset and Power control Management) */
-struct jz4740_cpm {
-	uint32_t cpccr; /* 0x00 clock control reg */
-	uint32_t lcr;	/* 0x04 low power control reg */
-	uint32_t rsr;	/* 0x08 reset status reg */
-	uint32_t pad00;
-	uint32_t cppcr; /* 0x10 pll control reg */
-	uint32_t pad01[3];
-	uint32_t clkgr;	/* 0x20 clock gate reg */
-	uint32_t scr;	/* 0x24 sleep control reg */
-	uint32_t pad02[14];
-	uint32_t i2scd; /* 0x60 I2S device clock divider reg */
-	uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
-	uint32_t msccdr; /* 0x68 MSC device clock divider reg */
-	uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
-	uint32_t uhcts; /* 0x70 UHC PHY test point reg */
-	uint32_t ssicd; /* 0x74 SSI clock divider reg */
-};
-
-/* TCU (Timer Counter Unit) */
-struct jz4740_tcu {
-	uint32_t pad00[4];
-	uint32_t ter;	/* 0x10  Timer Counter Enable Register */
-	uint32_t tesr;	/* 0x14  Timer Counter Enable Set Register */
-	uint32_t tecr;	/* 0x18  Timer Counter Enable Clear Register */
-	uint32_t tsr;	/* 0x1C  Timer Stop Register */
-	uint32_t tfr;	/* 0x20  Timer Flag Register */
-	uint32_t tfsr;	/* 0x24  Timer Flag Set Register */
-	uint32_t tfcr;	/* 0x28  Timer Flag Clear Register */
-	uint32_t tssr;	/* 0x2C  Timer Stop Set Register */
-	uint32_t tmr;	/* 0x30  Timer Mask Register */
-	uint32_t tmsr;	/* 0x34  Timer Mask Set Register */
-	uint32_t tmcr;	/* 0x38  Timer Mask Clear Register */
-	uint32_t tscr;	/* 0x3C  Timer Stop Clear Register */
-	uint32_t tdfr0;	/* 0x40  Timer Data Full Register */
-	uint32_t tdhr0;	/* 0x44  Timer Data Half Register */
-	uint32_t tcnt0;	/* 0x48  Timer Counter Register */
-	uint32_t tcsr0;	/* 0x4C  Timer Control Register */
-	uint32_t tdfr1;	/* 0x50 */
-	uint32_t tdhr1;	/* 0x54 */
-	uint32_t tcnt1;	/* 0x58 */
-	uint32_t tcsr1;	/* 0x5C */
-	uint32_t tdfr2;	/* 0x60 */
-	uint32_t tdhr2;	/* 0x64 */
-	uint32_t tcnt2;	/* 0x68 */
-	uint32_t tcsr2;	/* 0x6C */
-	uint32_t tdfr3;	/* 0x70 */
-	uint32_t tdhr3;	/* 0x74 */
-	uint32_t tcnt3;	/* 0x78 */
-	uint32_t tcsr3;	/* 0x7C */
-	uint32_t tdfr4;	/* 0x80 */
-	uint32_t tdhr4;	/* 0x84 */
-	uint32_t tcnt4;	/* 0x88 */
-	uint32_t tcsr4;	/* 0x8C */
-	uint32_t tdfr5;	/* 0x90 */
-	uint32_t tdhr5;	/* 0x94 */
-	uint32_t tcnt5;	/* 0x98 */
-	uint32_t tcsr5;	/* 0x9C */
-};
-
-/* WDT (WatchDog Timer) */
-struct jz4740_wdt {
-	uint16_t tdr; /* 0x00 watchdog timer data reg*/
-	uint16_t pad00;
-	uint8_t tcer; /* 0x04 watchdog counter enable reg*/
-	uint8_t pad01[3];
-	uint16_t tcnt; /* 0x08 watchdog timer counter*/
-	uint16_t pad02;
-	uint16_t tcsr; /* 0x0C watchdog timer control reg*/
-	uint16_t pad03;
-};
-
-struct jz4740_uart {
-	uint8_t rbr_thr_dllr;
-		/* 0x00 R  8b receive buffer reg */
-		/* 0x00 W  8b transmit hold reg */
-		/* 0x00 RW 8b divisor latch low reg */
-	uint8_t pad00[3];
-	uint8_t dlhr_ier;
-		/* 0x04 RW 8b divisor latch high reg */
-		/* 0x04 RW 8b interrupt enable reg */
-	uint8_t pad01[3];
-	uint8_t iir_fcr;
-		/* 0x08 R  8b interrupt identification reg */
-		/* 0x08 W  8b FIFO control reg */
-	uint8_t pad02[3];
-	uint8_t lcr;	/* 0x0C RW 8b Line control reg */
-	uint8_t pad03[3];
-	uint8_t mcr;	/* 0x10 RW 8b modem control reg */
-	uint8_t pad04[3];
-	uint8_t lsr;	/* 0x14 R  8b line status reg */
-	uint8_t pad05[3];
-	uint8_t msr;	/* 0x18 R  8b modem status reg */
-	uint8_t pad06[3];
-	uint8_t spr;	/* 0x1C RW 8b scratch pad reg */
-	uint8_t pad07[3];
-	uint8_t isr;	/* 0x20 RW 8b infrared selection reg */
-	uint8_t pad08[3];
-	uint8_t umr;	/* 0x24 RW 8b */
-};
-
-/* MSC */
-struct jz4740_msc {
-	uint16_t strpcl;/* 0x00 */
-	uint32_t stat;	/* 0x04 */
-	uint16_t clkrt;	/* 0x08 */
-	uint32_t cmdat;	/* 0x0C */
-	uint16_t resto;	/* 0x10 */
-	uint16_t rdto;	/* 0x14 */
-	uint16_t blklen;/* 0x18 */
-	uint16_t nob;	/* 0x1C */
-	uint16_t snob;	/* 0x20 */
-	uint16_t imask;	/* 0x24 */
-	uint16_t ireg;	/* 0x28 */
-	uint8_t  cmd;	/* 0x2C */
-	uint32_t arg;	/* 0x30 */
-	uint16_t res;	/* 0x34 */
-	uint32_t rxfifo;/* 0x38 */
-	uint32_t txfifo;/* 0x3C */
-};
-
-/* External Memory Controller */
-struct jz4740_emc {
-	uint32_t bcr; /* 0x00 BCR */
-	uint32_t pad00[3];
-	uint32_t smcr[5];
-		/* x10 Static Memory Control Register 0 */
-		/* x14 Static Memory Control Register 1 */
-		/* x18 Static Memory Control Register 2 */
-		/* x1c Static Memory Control Register 3 */
-		/* x20 Static Memory Control Register 4 */
-	uint32_t pad01[3];
-	uint32_t sacr[5];
-		/* x30 Static Memory Bank 0 Addr Config Reg */
-		/* x34 Static Memory Bank 1 Addr Config Reg */
-		/* x38 Static Memory Bank 2 Addr Config Reg */
-		/* x3c Static Memory Bank 3 Addr Config Reg */
-		/* x40 Static Memory Bank 4 Addr Config Reg */
-	uint32_t pad02[3];
-	uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
-
-	uint32_t pad03[11];
-	uint32_t dmcr; /* x80 DRAM Control Register */
-	uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
-	uint16_t pad04;
-	uint16_t rtcnt; /* x88 Refresh Timer Counter */
-	uint16_t pad05;
-	uint16_t rtcor; /* x8c Refresh Time Constant Register */
-	uint16_t pad06;
-	uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
-	uint32_t pad07[27];
-	uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
-	uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
-	uint8_t nfpar[12];
-		/* x108 NAND Flash RS Parity 0 Register */
-		/* x10c NAND Flash RS Parity 1 Register */
-		/* x110 NAND Flash RS Parity 2 Register */
-	uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
-	uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
-	uint32_t nferr[4];
-		/* x11c NAND Flash RS Error Report 0 Register */
-		/* x120 NAND Flash RS Error Report 1 Register */
-		/* x124 NAND Flash RS Error Report 2 Register */
-		/* x128 NAND Flash RS Error Report 3 Register */
-};
-
-#define __gpio_as_nand()			\
-do {						\
-	writel(0x02018000, GPIO_PXFUNS(1));	\
-	writel(0x02018000, GPIO_PXSELC(1));	\
-	writel(0x02018000, GPIO_PXPES(1));	\
-	writel(0x30000000, GPIO_PXFUNS(2));	\
-	writel(0x30000000, GPIO_PXSELC(2));	\
-	writel(0x30000000, GPIO_PXPES(2));	\
-	writel(0x40000000, GPIO_PXFUNC(2));	\
-	writel(0x40000000, GPIO_PXSELC(2));	\
-	writel(0x40000000, GPIO_PXDIRC(2));	\
-	writel(0x40000000, GPIO_PXPES(2));	\
-	writel(0x00400000, GPIO_PXFUNS(1));	\
-	writel(0x00400000, GPIO_PXSELC(1));	\
-} while (0)
-
-#define __gpio_as_sdram_16bit_4720()		\
-do {						\
-	writel(0x5442bfaa, GPIO_PXFUNS(0));	\
-	writel(0x5442bfaa, GPIO_PXSELC(0));	\
-	writel(0x5442bfaa, GPIO_PXPES(0));	\
-	writel(0x81f9ffff, GPIO_PXFUNS(1));	\
-	writel(0x81f9ffff, GPIO_PXSELC(1));	\
-	writel(0x81f9ffff, GPIO_PXPES(1));	\
-	writel(0x01000000, GPIO_PXFUNS(2));	\
-	writel(0x01000000, GPIO_PXSELC(2));	\
-	writel(0x01000000, GPIO_PXPES(2));	\
-} while (0)
-
-#define __gpio_as_lcd_18bit()			\
-do {						\
-	writel(0x003fffff, GPIO_PXFUNS(2));	\
-	writel(0x003fffff, GPIO_PXSELC(2));	\
-	writel(0x003fffff, GPIO_PXPES(2));	\
-} while (0)
-
-/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
-#define __gpio_as_msc()				\
-do {						\
-	writel(0x00003f00, GPIO_PXFUNS(3));	\
-	writel(0x00003f00, GPIO_PXSELC(3));	\
-	writel(0x00003f00, GPIO_PXPES(3));	\
-} while (0)
-
-#define __gpio_get_port(p)	(readl(GPIO_PXPIN(p)))
-
-#define __gpio_disable_pull(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXPES(p));	\
-} while (0)
-
-#define __gpio_enable_pull(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel(1 << (o), GPIO_PXPEC(p));	\
-} while (0)
-
-#define __gpio_port_as_output(p, o)		\
-do {						\
-	writel(1 << (o), GPIO_PXFUNC(p));	\
-	writel(1 << (o), GPIO_PXSELC(p));	\
-	writel(1 << (o), GPIO_PXDIRS(p));	\
-} while (0)
-
-#define __gpio_port_as_input(p, o)		\
-do {						\
-	writel(1 << (o), GPIO_PXFUNC(p));	\
-	writel(1 << (o), GPIO_PXSELC(p));	\
-	writel(1 << (o), GPIO_PXDIRC(p));	\
-} while (0)
-
-#define __gpio_as_output(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	__gpio_port_as_output(p, o);		\
-} while (0)
-
-#define __gpio_as_input(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	__gpio_port_as_input(p, o);		\
-} while (0)
-
-#define __gpio_set_pin(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXDATS(p));	\
-} while (0)
-
-#define __gpio_clear_pin(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXDATC(p));	\
-} while (0)
-
-#define __gpio_get_pin(n)			\
-({						\
-	unsigned int p, o, v;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	if (__gpio_get_port(p) & (1 << o))	\
-		v = 1;				\
-	else					\
-		v = 0;				\
-	v;					\
-})
-
-#define __gpio_as_uart0()			\
-do {						\
-	writel(0x06000000, GPIO_PXFUNS(3));	\
-	writel(0x06000000, GPIO_PXSELS(3));	\
-	writel(0x06000000, GPIO_PXPES(3));	\
-} while (0)
-
-#define __gpio_jtag_to_uart0()			\
-do {						\
-	writel(0x80000000, GPIO_PXSELS(2));	\
-} while (0)
-
-/* Clock Control Register */
-#define __cpm_get_pllm()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK)	\
-	 >> CPM_CPPCR_PLLM_BIT)
-#define __cpm_get_plln()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK)	\
-	 >> CPM_CPPCR_PLLN_BIT)
-#define __cpm_get_pllod()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK)	\
-	 >> CPM_CPPCR_PLLOD_BIT)
-#define __cpm_get_hdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK)	\
-	 >> CPM_CPCCR_HDIV_BIT)
-#define __cpm_get_pdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK)	\
-	 >> CPM_CPCCR_PDIV_BIT)
-#define __cpm_get_cdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK)	\
-	 >> CPM_CPCCR_CDIV_BIT)
-#define __cpm_get_mdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK)	\
-	 >> CPM_CPCCR_MDIV_BIT)
-
-static inline unsigned int __cpm_get_pllout(void)
-{
-	uint32_t m, n, no, pllout;
-	uint32_t od[4] = {1, 2, 2, 4};
-
-	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
-	uint32_t cppcr = readl(&cpm->cppcr);
-
-	if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
-		m = __cpm_get_pllm() + 2;
-		n = __cpm_get_plln() + 2;
-		no = od[__cpm_get_pllod()];
-		pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
-	} else
-		pllout = CONFIG_SYS_EXTAL;
-
-	return pllout;
-}
-
-extern void pll_init(void);
-extern void sdram_init(void);
-extern void calc_clocks(void);
-extern void rtc_init(void);
-
-#endif	/* !__ASSEMBLY__ */
-#endif	/* __JZ4740_H__ */
-- 
cgit v0.10.2


From 42a3f3e6ebbac4d93892d2b870502743d7308988 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Sun, 22 May 2016 11:59:50 +0800
Subject: mips: ath79: ar933x: Fix ethernet PHY mismatch

We need reset the Ethernet Switch analog part before operation,
or the build-in Ethernet PHY don't work.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a8e51cb..dabcad0 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -660,6 +660,7 @@
 
 #define AR933X_RESET_GE1_MDIO				BIT(23)
 #define AR933X_RESET_GE0_MDIO				BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG			BIT(14)
 #define AR933X_RESET_GE1_MAC				BIT(13)
 #define AR933X_RESET_WMAC				BIT(11)
 #define AR933X_RESET_GE0_MAC				BIT(9)
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 188eccb..a88bcbc 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -81,7 +81,8 @@ static int eth_init_ar933x(void)
 					  MAP_NOCACHE);
 	const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
 			 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
-			 AR933X_RESET_ETH_SWITCH;
+			 AR933X_RESET_ETH_SWITCH |
+			 AR933X_RESET_ETH_SWITCH_ANALOG;
 
 	/* Clear MDIO slave EN bit. */
 	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
-- 
cgit v0.10.2


From 4349b55b9953d0bb591f13ca9985edf591348ced Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Sun, 22 May 2016 11:59:49 +0800
Subject: mips: ath79: ar933x: Avoid warning with gcc5

GCC 5.3 report a warning: 'upper' and 'lower' may be used
uninitialized in this function [-Wmaybe-uninitialized].
Compiler might need explicit initializer.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 91452bc..7f20d34 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -268,6 +268,8 @@ void ddr_tap_tuning(void)
 	dir = 1;
 	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
 	val = tap;
+	upper = tap;
+	lower = tap;
 	while (!done) {
 		err = 0;
 
-- 
cgit v0.10.2


From c06bbab65b79c2a1c077d78269ed2bfa87f6e923 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 1 May 2016 00:36:11 +0200
Subject: ARM: exynos: Fix build error if SERIAL is disabled in SPL

If CONFIG_SPL_SERIAL_SUPPORT is not defined in include/configs/exynos5-common.h
the following error is produced during the build of the SPL:

arch/arm/mach-exynos/built-in.o: In function `do_lowlevel_init':
...u-boot/arch/arm/mach-exynos/lowlevel_init.c:221: undefined reference to `debug_uart_init'

Add additional condition to check if SPL build is in progress and
in that case check if CONFIG_SPL_SERIAL_SUPPORT is also set before
enabling the debug UART.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c
index 6c39cb2..1e090fd 100644
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@@ -216,9 +216,12 @@ int do_lowlevel_init(void)
 	if (actions & DO_CLOCKS) {
 		system_clock_init();
 #ifdef CONFIG_DEBUG_UART
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
+    !defined(CONFIG_SPL_BUILD)
 		exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 		debug_uart_init();
 #endif
+#endif
 		mem_ctrl_init(actions & DO_MEM_RESET);
 		tzpc_init();
 	}
-- 
cgit v0.10.2


From 086e13c5f6f79a68246d6b803cf4736cb6815e44 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 1 May 2016 00:36:12 +0200
Subject: ARM: exynos: Disable serial support in SPL

The exynos5 platforms use DM in U-Boot and do not use DM in SPL. The serial
driver, serial_s5p.c, is DM-only. This is OK for U-Boot, but in SPL, this
will fail with the following compile error:

drivers/built-in.o: In function `get_current':
...u-boot/drivers/serial/serial.c:387: undefined reference to `default_serial_console'

This warning happens because common/console.c is compiled into U-Boot SPL
if CONFIG_SPL_SERIAL_SUPPORT . The common/console.c invokes serial_*()
functions and since exynos5 does not use DM in SPL, these functions come
from drivers/serial/serial.c . The serial_*() locate default serial port
by calling default_serial_console(), but because the serial_s5p.c is DM-only,
it does no longer define default_serial_console(). Thus the error.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 311fd09..061cac4 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -60,7 +60,6 @@
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
 /* specific .lds file */
-- 
cgit v0.10.2


From daac3bfee57247013cb8373683e9babb191abd75 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 11 May 2016 15:26:24 -0600
Subject: dm: allow setting driver_data before/during bind

This will allow a driver's bind function to use the driver data. One
example is the Tegra186 GPIO driver, which instantiates child devices
for each of its GPIO ports, yet supports two different HW instances each
with a different set of ports, and identified by the udevice_id .data
field.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index 7a24552..1b5ccec 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -606,19 +606,24 @@ methods actually defined.
 
 1. Bind stage
 
-A device and its driver are bound using one of these two methods:
+U-Boot discovers devices using one of these two methods:
 
-   - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the
-name specified by each, to find the appropriate driver. It then calls
-device_bind() to create a new device and bind' it to its driver. This will
-call the device's bind() method.
+   - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
+by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
+there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
+may provide platdata.
 
    - Scan through the device tree definitions. U-Boot looks at top-level
 nodes in the the device tree. It looks at the compatible string in each node
-and uses the of_match part of the U_BOOT_DRIVER() structure to find the
-right driver for each node. It then calls device_bind() to bind the
-newly-created device to its driver (thereby creating a device structure).
-This will also call the device's bind() method.
+and uses the of_match table of the U_BOOT_DRIVER() structure to find the
+right driver for each node. In this case, the of_match table may provide a
+driver_data value, but platdata cannot be provided until later.
+
+For each device that is discovered, U-Boot then calls device_bind() to create a
+new device, initializes various core fields of the device object such as name,
+uclass & driver, initializes any optional fields of the device object that are
+applicable such as of_offset, driver_data & platdata, and finally calls the
+driver's bind() method if one is defined.
 
 At this point all the devices are known, and bound to their drivers. There
 is a 'struct udevice' allocated for all devices. However, nothing has been
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 45d5e3e..eb75b17 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -26,9 +26,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int device_bind(struct udevice *parent, const struct driver *drv,
-		const char *name, void *platdata, int of_offset,
-		struct udevice **devp)
+static int device_bind_common(struct udevice *parent, const struct driver *drv,
+			      const char *name, void *platdata,
+			      ulong driver_data, int of_offset,
+			      struct udevice **devp)
 {
 	struct udevice *dev;
 	struct uclass *uc;
@@ -56,6 +57,7 @@ int device_bind(struct udevice *parent, const struct driver *drv,
 	INIT_LIST_HEAD(&dev->devres_head);
 #endif
 	dev->platdata = platdata;
+	dev->driver_data = driver_data;
 	dev->name = name;
 	dev->of_offset = of_offset;
 	dev->parent = parent;
@@ -193,6 +195,23 @@ fail_alloc1:
 	return ret;
 }
 
+int device_bind_with_driver_data(struct udevice *parent,
+				 const struct driver *drv, const char *name,
+				 ulong driver_data, int of_offset,
+				 struct udevice **devp)
+{
+	return device_bind_common(parent, drv, name, NULL, driver_data,
+				  of_offset, devp);
+}
+
+int device_bind(struct udevice *parent, const struct driver *drv,
+		const char *name, void *platdata, int of_offset,
+		struct udevice **devp)
+{
+	return device_bind_common(parent, drv, name, platdata, 0, of_offset,
+				  devp);
+}
+
 int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
 			const struct driver_info *info, struct udevice **devp)
 {
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index a72db13..0c27717 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -170,7 +170,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 		}
 
 		dm_dbg("   - found match at '%s'\n", entry->name);
-		ret = device_bind(parent, entry, name, NULL, offset, &dev);
+		ret = device_bind_with_driver_data(parent, entry, name,
+						   id->data, offset, &dev);
 		if (ret == -ENODEV) {
 			dm_dbg("Driver '%s' refuses to bind\n", entry->name);
 			continue;
@@ -180,7 +181,6 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 				ret);
 			return ret;
 		} else {
-			dev->driver_data = id->data;
 			found = true;
 			if (devp)
 				*devp = dev;
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index b348ad5..0bf8707 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -39,6 +39,30 @@ int device_bind(struct udevice *parent, const struct driver *drv,
 		struct udevice **devp);
 
 /**
+ * device_bind_with_driver_data() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver, in the case where the
+ * driver was matched to the device by means of a match table that provides
+ * driver_data.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @driver_data: The driver_data field from the driver's match table.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_with_driver_data(struct udevice *parent,
+				 const struct driver *drv, const char *name,
+				 ulong driver_data, int of_offset,
+				 struct udevice **devp);
+
+/**
  * device_bind_by_name: Create a device and bind it to a driver
  *
  * This is a helper function used to bind devices which do not use device
-- 
cgit v0.10.2


From 6f82fac2f278173f5afe5b4b5dbc269646d11c0b Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 11 May 2016 15:26:25 -0600
Subject: sunxi: gpio: convert bind() to use driver data

Now that the DM core sets driver_data before calling bind(), this driver
can make use of driver_data to determine the set of child devices to
create, rather than manually re-implementing the matching logic in code.

Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index a7cec18..94abbeb 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -258,43 +258,30 @@ static int gpio_sunxi_probe(struct udevice *dev)
 
 	return 0;
 }
+
+struct sunxi_gpio_soc_data {
+	int start;
+	int no_banks;
+};
+
 /**
  * We have a top-level GPIO device with no actual GPIOs. It has a child
  * device for each Sunxi bank.
  */
 static int gpio_sunxi_bind(struct udevice *parent)
 {
+	struct sunxi_gpio_soc_data *soc_data =
+		(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
 	struct sunxi_gpio_platdata *plat = parent->platdata;
 	struct sunxi_gpio_reg *ctlr;
-	int bank, no_banks, ret, start;
+	int bank, ret;
 
 	/* If this is a child device, there is nothing to do here */
 	if (plat)
 		return 0;
 
-	if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun6i-a31-r-pinctrl") == 0) {
-		start = 'L' - 'A';
-		no_banks = 2; /* L & M */
-	} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-a23-r-pinctrl") == 0 ||
-		   fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-a83t-r-pinctrl") == 0 ||
-		   fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-h3-r-pinctrl") == 0) {
-		start = 'L' - 'A';
-		no_banks = 1; /* L only */
-	} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun9i-a80-r-pinctrl") == 0) {
-		start = 'L' - 'A';
-		no_banks = 3; /* L, M & N */
-	} else {
-		start = 0;
-		no_banks = SUNXI_GPIO_BANKS;
-	}
-
 	ctlr = (struct sunxi_gpio_reg *)dev_get_addr(parent);
-	for (bank = 0; bank < no_banks; bank++) {
+	for (bank = 0; bank < soc_data->no_banks; bank++) {
 		struct sunxi_gpio_platdata *plat;
 		struct udevice *dev;
 
@@ -302,7 +289,7 @@ static int gpio_sunxi_bind(struct udevice *parent)
 		if (!plat)
 			return -ENOMEM;
 		plat->regs = &ctlr->gpio_bank[bank];
-		plat->bank_name = gpio_bank_name(start + bank);
+		plat->bank_name = gpio_bank_name(soc_data->start + bank);
 		plat->gpio_count = SUNXI_GPIOS_PER_BANK;
 
 		ret = device_bind(parent, parent->driver,
@@ -315,23 +302,46 @@ static int gpio_sunxi_bind(struct udevice *parent)
 	return 0;
 }
 
+static const struct sunxi_gpio_soc_data soc_data_a_all = {
+	.start = 0,
+	.no_banks = SUNXI_GPIO_BANKS,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_1 = {
+	.start = 'L' - 'A',
+	.no_banks = 1,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_2 = {
+	.start = 'L' - 'A',
+	.no_banks = 2,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_3 = {
+	.start = 'L' - 'A',
+	.no_banks = 3,
+};
+
+#define ID(_compat_, _soc_data_) \
+	{ .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
+
 static const struct udevice_id sunxi_gpio_ids[] = {
-	{ .compatible = "allwinner,sun4i-a10-pinctrl" },
-	{ .compatible = "allwinner,sun5i-a10s-pinctrl" },
-	{ .compatible = "allwinner,sun5i-a13-pinctrl" },
-	{ .compatible = "allwinner,sun6i-a31-pinctrl" },
-	{ .compatible = "allwinner,sun6i-a31s-pinctrl" },
-	{ .compatible = "allwinner,sun7i-a20-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a23-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a33-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a83t-pinctrl", },
-	{ .compatible = "allwinner,sun8i-h3-pinctrl" },
-	{ .compatible = "allwinner,sun9i-a80-pinctrl" },
-	{ .compatible = "allwinner,sun6i-a31-r-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a23-r-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a83t-r-pinctrl" },
-	{ .compatible = "allwinner,sun8i-h3-r-pinctrl", },
-	{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
+	ID("allwinner,sun4i-a10-pinctrl",	a_all),
+	ID("allwinner,sun5i-a10s-pinctrl",	a_all),
+	ID("allwinner,sun5i-a13-pinctrl",	a_all),
+	ID("allwinner,sun6i-a31-pinctrl",	a_all),
+	ID("allwinner,sun6i-a31s-pinctrl",	a_all),
+	ID("allwinner,sun7i-a20-pinctrl",	a_all),
+	ID("allwinner,sun8i-a23-pinctrl",	a_all),
+	ID("allwinner,sun8i-a33-pinctrl",	a_all),
+	ID("allwinner,sun8i-a83t-pinctrl",	a_all),
+	ID("allwinner,sun8i-h3-pinctrl",	a_all),
+	ID("allwinner,sun9i-a80-pinctrl",	a_all),
+	ID("allwinner,sun6i-a31-r-pinctrl",	l_2),
+	ID("allwinner,sun8i-a23-r-pinctrl",	l_1),
+	ID("allwinner,sun8i-a83t-r-pinctrl",	l_1),
+	ID("allwinner,sun8i-h3-r-pinctrl",	l_1),
+	ID("allwinner,sun9i-a80-r-pinctrl",	l_3),
 	{ }
 };
 
-- 
cgit v0.10.2


From 11636258981a083957c19f3979796fde5e7e8080 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:03:35 -0600
Subject: Rename reset to sysreset

The current reset API implements a method to reset the entire system.
In the near future, I'd like to introduce code that implements the device
tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
This controls resets to individual HW blocks or external chips with reset
signals. It doesn't make sense to merge the two APIs into one since they
have different semantic purposes. Resolve the naming conflict by renaming
the existing reset API to sysreset instead, so the new reset API can be
called just reset.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 7a0fb58..b535dbe 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -46,7 +46,7 @@ obj-y	+= interrupts_64.o
 else
 obj-y	+= interrupts.o
 endif
-ifndef CONFIG_RESET
+ifndef CONFIG_SYSRESET
 obj-y	+= reset.o
 endif
 
diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
index fefb568..b3d2113 100644
--- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
@@ -7,24 +7,24 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3036.h>
 #include <asm/arch/hardware.h>
 #include <linux/err.h>
 
-int rk3036_reset_request(struct udevice *dev, enum reset_t type)
+int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct rk3036_cru *cru = rockchip_get_cru();
 
 	if (IS_ERR(cru))
 		return PTR_ERR(cru);
 	switch (type) {
-	case RESET_WARM:
+	case SYSRESET_WARM:
 		writel(0xeca8, &cru->cru_glb_srst_snd_value);
 		break;
-	case RESET_COLD:
+	case SYSRESET_COLD:
 		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
 		break;
 	default:
@@ -34,12 +34,12 @@ int rk3036_reset_request(struct udevice *dev, enum reset_t type)
 	return -EINPROGRESS;
 }
 
-static struct reset_ops rk3036_reset = {
-	.request	= rk3036_reset_request,
+static struct sysreset_ops rk3036_sysreset = {
+	.request	= rk3036_sysreset_request,
 };
 
-U_BOOT_DRIVER(reset_rk3036) = {
-	.name	= "rk3036_reset",
-	.id	= UCLASS_RESET,
-	.ops	= &rk3036_reset,
+U_BOOT_DRIVER(sysreset_rk3036) = {
+	.name	= "rk3036_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rk3036_sysreset,
 };
diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
index bf7540a..0aad1c2 100644
--- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
@@ -7,25 +7,25 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3288.h>
 #include <asm/arch/hardware.h>
 #include <linux/err.h>
 
-int rk3288_reset_request(struct udevice *dev, enum reset_t type)
+int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct rk3288_cru *cru = rockchip_get_cru();
 
 	if (IS_ERR(cru))
 		return PTR_ERR(cru);
 	switch (type) {
-	case RESET_WARM:
+	case SYSRESET_WARM:
 		rk_clrreg(&cru->cru_mode_con, 0xffff);
 		writel(0xeca8, &cru->cru_glb_srst_snd_value);
 		break;
-	case RESET_COLD:
+	case SYSRESET_COLD:
 		rk_clrreg(&cru->cru_mode_con, 0xffff);
 		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
 		break;
@@ -36,12 +36,12 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t type)
 	return -EINPROGRESS;
 }
 
-static struct reset_ops rk3288_reset = {
-	.request	= rk3288_reset_request,
+static struct sysreset_ops rk3288_sysreset = {
+	.request	= rk3288_sysreset_request,
 };
 
-U_BOOT_DRIVER(reset_rk3288) = {
-	.name	= "rk3288_reset",
-	.id	= UCLASS_RESET,
-	.ops	= &rk3288_reset,
+U_BOOT_DRIVER(sysreset_rk3288) = {
+	.name	= "rk3288_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rk3288_sysreset,
 };
diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c
index 2627eec..a6cabfb 100644
--- a/arch/arm/mach-snapdragon/reset.c
+++ b/arch/arm/mach-snapdragon/reset.c
@@ -9,12 +9,12 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int msm_reset_request(struct udevice *dev, enum reset_t type)
+static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	phys_addr_t addr = dev_get_addr(dev);
 	if (!addr)
@@ -23,18 +23,18 @@ static int msm_reset_request(struct udevice *dev, enum reset_t type)
 	return -EINPROGRESS;
 }
 
-static struct reset_ops msm_reset_ops = {
-	.request	= msm_reset_request,
+static struct sysreset_ops msm_sysreset_ops = {
+	.request	= msm_sysreset_request,
 };
 
-static const struct udevice_id msm_reset_ids[] = {
+static const struct udevice_id msm_sysreset_ids[] = {
 	{ .compatible = "qcom,pshold" },
 	{ }
 };
 
 U_BOOT_DRIVER(msm_reset) = {
-	.name		= "msm_reset",
-	.id		= UCLASS_RESET,
-	.of_match	= msm_reset_ids,
-	.ops		= &msm_reset_ops,
+	.name		= "msm_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.of_match	= msm_sysreset_ids,
+	.ops		= &msm_sysreset_ops,
 };
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index d2a7dc9..2b4dbd3 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -360,8 +360,8 @@ int state_init(void)
 	assert(state->ram_buf);
 
 	/* No reset yet, so mark it as such. Always allow power reset */
-	state->last_reset = RESET_COUNT;
-	state->reset_allowed[RESET_POWER] = true;
+	state->last_sysreset = SYSRESET_COUNT;
+	state->sysreset_allowed[SYSRESET_POWER] = true;
 
 	/*
 	 * Example of how to use GPIOs:
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 11856c2..149f28d 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -7,7 +7,7 @@
 #define __SANDBOX_STATE_H
 
 #include <config.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <stdbool.h>
 #include <linux/stringify.h>
 
@@ -60,8 +60,8 @@ struct sandbox_state {
 	bool write_state;		/* Write sandbox state on exit */
 	bool ignore_missing_state_on_read;	/* No error if state missing */
 	bool show_lcd;			/* Show LCD on start-up */
-	enum reset_t last_reset;	/* Last reset type */
-	bool reset_allowed[RESET_COUNT];	/* Allowed reset types */
+	enum sysreset_t last_sysreset;	/* Last system reset type */
+	bool sysreset_allowed[SYSRESET_COUNT];	/* Allowed system reset types */
 	enum state_terminal_raw term_raw;	/* Terminal raw/cooked */
 	bool skip_delays;		/* Ignore any time delays (for test) */
 	bool show_test_output;		/* Don't suppress stdout in tests */
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 25ead92..d5bc515 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -47,7 +47,7 @@ CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 2566ded..37c5ea77 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -23,7 +23,7 @@ CONFIG_MSM_GPIO=y
 CONFIG_PM8916_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_MSM_SDHCI=y
 CONFIG_DM_PMIC=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 4dd4586..9894fff 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -28,7 +28,7 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0995f9b..0cbc539 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -40,7 +40,7 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 50fbe65..0ff6c6b 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -28,7 +28,7 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index fd32fb5..3e16b80 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -38,7 +38,7 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 9e4a92d..6e30c5d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -97,7 +97,7 @@ CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_SANDBOX_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 93167c2..60c7339 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -94,7 +94,7 @@ CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index bd5f22a..7ec65bd 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -407,7 +407,7 @@ static int rk3036_clk_bind(struct udevice *dev)
 	}
 
 	/* The reset driver does not have a device node, so bind it here */
-	ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev);
+	ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
 	if (ret)
 		debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
 
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 2a85e93..e763a1c 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -877,7 +877,7 @@ static int rk3288_clk_bind(struct udevice *dev)
 	}
 
 	/* The reset driver does not have a device node, so bind it here */
-	ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
+	ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
 	if (ret)
 		debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c40f6b5..2373037 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -121,13 +121,13 @@ config PCA9551_I2C_ADDR
 	help
 	  The I2C address of the PCA9551 LED controller.
 
-config RESET
-	bool "Enable support for reset drivers"
+config SYSRESET
+	bool "Enable support for system reset drivers"
 	depends on DM
 	help
-	  Enable reset drivers which can be used to reset the CPU or board.
-	  Each driver can provide a reset method which will be called to
-	  effect a reset. The uclass will try all available drivers when
+	  Enable system reset drivers which can be used to reset the CPU or
+	  board. Each driver can provide a reset method which will be called
+	  to effect a reset. The uclass will try all available drivers when
 	  reset_walk() is called.
 
 config WINBOND_W83627
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 98704f2..066639b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_PDSP188x) += pdsp188x.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_SANDBOX) += reset_sandbox.o
+obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 ifdef CONFIG_DM_I2C
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
 endif
@@ -40,7 +40,7 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
 obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
-obj-$(CONFIG_RESET) += reset-uclass.o
+obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/reset-uclass.c b/drivers/misc/reset-uclass.c
deleted file mode 100644
index fdb5c6f..0000000
--- a/drivers/misc/reset-uclass.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <reset.h>
-#include <dm.h>
-#include <errno.h>
-#include <regmap.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
-#include <dm/root.h>
-#include <linux/err.h>
-
-int reset_request(struct udevice *dev, enum reset_t type)
-{
-	struct reset_ops *ops = reset_get_ops(dev);
-
-	if (!ops->request)
-		return -ENOSYS;
-
-	return ops->request(dev, type);
-}
-
-int reset_walk(enum reset_t type)
-{
-	struct udevice *dev;
-	int ret = -ENOSYS;
-
-	while (ret != -EINPROGRESS && type < RESET_COUNT) {
-		for (uclass_first_device(UCLASS_RESET, &dev);
-		     dev;
-		     uclass_next_device(&dev)) {
-			ret = reset_request(dev, type);
-			if (ret == -EINPROGRESS)
-				break;
-		}
-		type++;
-	}
-
-	return ret;
-}
-
-void reset_walk_halt(enum reset_t type)
-{
-	int ret;
-
-	ret = reset_walk(type);
-
-	/* Wait for the reset to take effect */
-	if (ret == -EINPROGRESS)
-		mdelay(100);
-
-	/* Still no reset? Give up */
-	printf("Reset not supported on this platform\n");
-	hang();
-}
-
-/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
- */
-void reset_cpu(ulong addr)
-{
-	reset_walk_halt(RESET_WARM);
-}
-
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	reset_walk_halt(RESET_WARM);
-
-	return 0;
-}
-
-UCLASS_DRIVER(reset) = {
-	.id		= UCLASS_RESET,
-	.name		= "reset",
-};
diff --git a/drivers/misc/reset_sandbox.c b/drivers/misc/reset_sandbox.c
deleted file mode 100644
index 2691bb0..0000000
--- a/drivers/misc/reset_sandbox.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int sandbox_warm_reset_request(struct udevice *dev, enum reset_t type)
-{
-	struct sandbox_state *state = state_get_current();
-
-	switch (type) {
-	case RESET_WARM:
-		state->last_reset = type;
-		break;
-	default:
-		return -ENOSYS;
-	}
-	if (!state->reset_allowed[type])
-		return -EACCES;
-
-	return -EINPROGRESS;
-}
-
-static int sandbox_reset_request(struct udevice *dev, enum reset_t type)
-{
-	struct sandbox_state *state = state_get_current();
-
-	/*
-	 * If we have a device tree, the device we created from platform data
-	 * (see the U_BOOT_DEVICE() declaration below) should not do anything.
-	 * If we are that device, return an error.
-	 */
-	if (state->fdt_fname && dev->of_offset == -1)
-		return -ENODEV;
-
-	switch (type) {
-	case RESET_COLD:
-		state->last_reset = type;
-		break;
-	case RESET_POWER:
-		state->last_reset = type;
-		if (!state->reset_allowed[type])
-			return -EACCES;
-		sandbox_exit();
-		break;
-	default:
-		return -ENOSYS;
-	}
-	if (!state->reset_allowed[type])
-		return -EACCES;
-
-	return -EINPROGRESS;
-}
-
-static struct reset_ops sandbox_reset_ops = {
-	.request	= sandbox_reset_request,
-};
-
-static const struct udevice_id sandbox_reset_ids[] = {
-	{ .compatible = "sandbox,reset" },
-	{ }
-};
-
-U_BOOT_DRIVER(reset_sandbox) = {
-	.name		= "reset_sandbox",
-	.id		= UCLASS_RESET,
-	.of_match	= sandbox_reset_ids,
-	.ops		= &sandbox_reset_ops,
-};
-
-static struct reset_ops sandbox_warm_reset_ops = {
-	.request	= sandbox_warm_reset_request,
-};
-
-static const struct udevice_id sandbox_warm_reset_ids[] = {
-	{ .compatible = "sandbox,warm-reset" },
-	{ }
-};
-
-U_BOOT_DRIVER(warm_reset_sandbox) = {
-	.name		= "warm_reset_sandbox",
-	.id		= UCLASS_RESET,
-	.of_match	= sandbox_warm_reset_ids,
-	.ops		= &sandbox_warm_reset_ops,
-};
-
-/* This is here in case we don't have a device tree */
-U_BOOT_DEVICE(reset_sandbox_non_fdt) = {
-	.name = "reset_sandbox",
-};
diff --git a/drivers/misc/sysreset-uclass.c b/drivers/misc/sysreset-uclass.c
new file mode 100644
index 0000000..e41efca
--- /dev/null
+++ b/drivers/misc/sysreset-uclass.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <sysreset.h>
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <linux/err.h>
+
+int sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct sysreset_ops *ops = sysreset_get_ops(dev);
+
+	if (!ops->request)
+		return -ENOSYS;
+
+	return ops->request(dev, type);
+}
+
+int sysreset_walk(enum sysreset_t type)
+{
+	struct udevice *dev;
+	int ret = -ENOSYS;
+
+	while (ret != -EINPROGRESS && type < SYSRESET_COUNT) {
+		for (uclass_first_device(UCLASS_SYSRESET, &dev);
+		     dev;
+		     uclass_next_device(&dev)) {
+			ret = sysreset_request(dev, type);
+			if (ret == -EINPROGRESS)
+				break;
+		}
+		type++;
+	}
+
+	return ret;
+}
+
+void sysreset_walk_halt(enum sysreset_t type)
+{
+	int ret;
+
+	ret = sysreset_walk(type);
+
+	/* Wait for the reset to take effect */
+	if (ret == -EINPROGRESS)
+		mdelay(100);
+
+	/* Still no reset? Give up */
+	printf("System reset not supported on this platform\n");
+	hang();
+}
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr)
+{
+	sysreset_walk_halt(SYSRESET_WARM);
+}
+
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	sysreset_walk_halt(SYSRESET_WARM);
+
+	return 0;
+}
+
+UCLASS_DRIVER(sysreset) = {
+	.id		= UCLASS_SYSRESET,
+	.name		= "sysreset",
+};
diff --git a/drivers/misc/sysreset_sandbox.c b/drivers/misc/sysreset_sandbox.c
new file mode 100644
index 0000000..7ae7f38
--- /dev/null
+++ b/drivers/misc/sysreset_sandbox.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_warm_sysreset_request(struct udevice *dev,
+					 enum sysreset_t type)
+{
+	struct sandbox_state *state = state_get_current();
+
+	switch (type) {
+	case SYSRESET_WARM:
+		state->last_sysreset = type;
+		break;
+	default:
+		return -ENOSYS;
+	}
+	if (!state->sysreset_allowed[type])
+		return -EACCES;
+
+	return -EINPROGRESS;
+}
+
+static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct sandbox_state *state = state_get_current();
+
+	/*
+	 * If we have a device tree, the device we created from platform data
+	 * (see the U_BOOT_DEVICE() declaration below) should not do anything.
+	 * If we are that device, return an error.
+	 */
+	if (state->fdt_fname && dev->of_offset == -1)
+		return -ENODEV;
+
+	switch (type) {
+	case SYSRESET_COLD:
+		state->last_sysreset = type;
+		break;
+	case SYSRESET_POWER:
+		state->last_sysreset = type;
+		if (!state->sysreset_allowed[type])
+			return -EACCES;
+		sandbox_exit();
+		break;
+	default:
+		return -ENOSYS;
+	}
+	if (!state->sysreset_allowed[type])
+		return -EACCES;
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops sandbox_sysreset_ops = {
+	.request	= sandbox_sysreset_request,
+};
+
+static const struct udevice_id sandbox_sysreset_ids[] = {
+	{ .compatible = "sandbox,reset" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_sandbox) = {
+	.name		= "sysreset_sandbox",
+	.id		= UCLASS_SYSRESET,
+	.of_match	= sandbox_sysreset_ids,
+	.ops		= &sandbox_sysreset_ops,
+};
+
+static struct sysreset_ops sandbox_warm_sysreset_ops = {
+	.request	= sandbox_warm_sysreset_request,
+};
+
+static const struct udevice_id sandbox_warm_sysreset_ids[] = {
+	{ .compatible = "sandbox,warm-reset" },
+	{ }
+};
+
+U_BOOT_DRIVER(warm_sysreset_sandbox) = {
+	.name		= "warm_sysreset_sandbox",
+	.id		= UCLASS_SYSRESET,
+	.of_match	= sandbox_warm_sysreset_ids,
+	.ops		= &sandbox_warm_sysreset_ops,
+};
+
+/* This is here in case we don't have a device tree */
+U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = {
+	.name = "sysreset_sandbox",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a5cf6e2..f9ff45e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -61,7 +61,6 @@ enum uclass_id {
 	UCLASS_PWM,		/* Pulse-width modulator */
 	UCLASS_PWRSEQ,		/* Power sequence device */
 	UCLASS_REGULATOR,	/* Regulator device */
-	UCLASS_RESET,		/* Reset device */
 	UCLASS_REMOTEPROC,	/* Remote Processor device */
 	UCLASS_RTC,		/* Real time clock device */
 	UCLASS_SERIAL,		/* Serial UART */
@@ -70,6 +69,7 @@ enum uclass_id {
 	UCLASS_SPI_FLASH,	/* SPI flash */
 	UCLASS_SPI_GENERIC,	/* Generic SPI flash target */
 	UCLASS_SYSCON,		/* System configuration device */
+	UCLASS_SYSRESET,	/* System reset device */
 	UCLASS_THERMAL,		/* Thermal sensor */
 	UCLASS_TIMER,		/* Timer device */
 	UCLASS_TPM,		/* Trusted Platform Module TIS interface */
diff --git a/include/reset.h b/include/reset.h
deleted file mode 100644
index 383761e..0000000
--- a/include/reset.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __RESET_H
-#define __RESET_H
-
-enum reset_t {
-	RESET_WARM,	/* Reset CPU, keep GPIOs active */
-	RESET_COLD,	/* Reset CPU and GPIOs */
-	RESET_POWER,	/* Reset PMIC (remove and restore power) */
-
-	RESET_COUNT,
-};
-
-struct reset_ops {
-	/**
-	 * request() - request a reset of the given type
-	 *
-	 * Note that this function may return before the reset takes effect.
-	 *
-	 * @type:	Reset type to request
-	 * @return -EINPROGRESS if the reset has been started and
-	 *		will complete soon, -EPROTONOSUPPORT if not supported
-	 *		by this device, 0 if the reset has already happened
-	 *		(in which case this method will not actually return)
-	 */
-	int (*request)(struct udevice *dev, enum reset_t type);
-};
-
-#define reset_get_ops(dev)        ((struct reset_ops *)(dev)->driver->ops)
-
-/**
- * reset_request() - request a reset
- *
- * @type:	Reset type to request
- * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
- */
-int reset_request(struct udevice *dev, enum reset_t type);
-
-/**
- * reset_walk() - cause a reset
- *
- * This works through the available reset devices until it finds one that can
- * perform a reset. If the provided reset type is not available, the next one
- * will be tried.
- *
- * If this function fails to reset, it will display a message and halt
- *
- * @type:	Reset type to request
- * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
- */
-int reset_walk(enum reset_t type);
-
-/**
- * reset_walk_halt() - try to reset, otherwise halt
- *
- * This calls reset_walk(). If it returns, indicating that reset is not
- * supported, it prints a message and halts.
- */
-void reset_walk_halt(enum reset_t type);
-
-/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
- */
-void reset_cpu(ulong addr);
-
-#endif
diff --git a/include/sysreset.h b/include/sysreset.h
new file mode 100644
index 0000000..393c7be
--- /dev/null
+++ b/include/sysreset.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SYSRESET_H
+#define __SYSRESET_H
+
+enum sysreset_t {
+	SYSRESET_WARM,	/* Reset CPU, keep GPIOs active */
+	SYSRESET_COLD,	/* Reset CPU and GPIOs */
+	SYSRESET_POWER,	/* Reset PMIC (remove and restore power) */
+
+	SYSRESET_COUNT,
+};
+
+struct sysreset_ops {
+	/**
+	 * request() - request a sysreset of the given type
+	 *
+	 * Note that this function may return before the reset takes effect.
+	 *
+	 * @type:	Reset type to request
+	 * @return -EINPROGRESS if the reset has been started and
+	 *		will complete soon, -EPROTONOSUPPORT if not supported
+	 *		by this device, 0 if the reset has already happened
+	 *		(in which case this method will not actually return)
+	 */
+	int (*request)(struct udevice *dev, enum sysreset_t type);
+};
+
+#define sysreset_get_ops(dev)        ((struct sysreset_ops *)(dev)->driver->ops)
+
+/**
+ * sysreset_request() - request a sysreset
+ *
+ * @type:	Reset type to request
+ * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ */
+int sysreset_request(struct udevice *dev, enum sysreset_t type);
+
+/**
+ * sysreset_walk() - cause a system reset
+ *
+ * This works through the available sysreset devices until it finds one that can
+ * perform a reset. If the provided sysreset type is not available, the next one
+ * will be tried.
+ *
+ * If this function fails to reset, it will display a message and halt
+ *
+ * @type:	Reset type to request
+ * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ */
+int sysreset_walk(enum sysreset_t type);
+
+/**
+ * sysreset_walk_halt() - try to reset, otherwise halt
+ *
+ * This calls sysreset_walk(). If it returns, indicating that reset is not
+ * supported, it prints a message and halts.
+ */
+void sysreset_walk_halt(enum sysreset_t type);
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr);
+
+#endif
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 9a11ae0..fd781e8 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
 obj-$(CONFIG_REMOTEPROC) += remoteproc.o
-obj-$(CONFIG_RESET) += reset.o
+obj-$(CONFIG_SYSRESET) += sysreset.o
 obj-$(CONFIG_DM_RTC) += rtc.o
 obj-$(CONFIG_DM_SPI_FLASH) += sf.o
 obj-$(CONFIG_DM_SPI) += spi.o
diff --git a/test/dm/reset.c b/test/dm/reset.c
deleted file mode 100644
index 5d53f25..0000000
--- a/test/dm/reset.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-#include <dm/test.h>
-#include <test/ut.h>
-
-/* Test that we can use particular reset devices */
-static int dm_test_reset_base(struct unit_test_state *uts)
-{
-	struct sandbox_state *state = state_get_current();
-	struct udevice *dev;
-
-	/* Device 0 is the platform data device - it should never respond */
-	ut_assertok(uclass_get_device(UCLASS_RESET, 0, &dev));
-	ut_asserteq(-ENODEV, reset_request(dev, RESET_WARM));
-	ut_asserteq(-ENODEV, reset_request(dev, RESET_COLD));
-	ut_asserteq(-ENODEV, reset_request(dev, RESET_POWER));
-
-	/* Device 1 is the warm reset device */
-	ut_assertok(uclass_get_device(UCLASS_RESET, 1, &dev));
-	ut_asserteq(-EACCES, reset_request(dev, RESET_WARM));
-	ut_asserteq(-ENOSYS, reset_request(dev, RESET_COLD));
-	ut_asserteq(-ENOSYS, reset_request(dev, RESET_POWER));
-
-	state->reset_allowed[RESET_WARM] = true;
-	ut_asserteq(-EINPROGRESS, reset_request(dev, RESET_WARM));
-	state->reset_allowed[RESET_WARM] = false;
-
-	/* Device 2 is the cold reset device */
-	ut_assertok(uclass_get_device(UCLASS_RESET, 2, &dev));
-	ut_asserteq(-ENOSYS, reset_request(dev, RESET_WARM));
-	ut_asserteq(-EACCES, reset_request(dev, RESET_COLD));
-	state->reset_allowed[RESET_POWER] = false;
-	ut_asserteq(-EACCES, reset_request(dev, RESET_POWER));
-	state->reset_allowed[RESET_POWER] = true;
-
-	return 0;
-}
-DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-
-/* Test that we can walk through the reset devices */
-static int dm_test_reset_walk(struct unit_test_state *uts)
-{
-	struct sandbox_state *state = state_get_current();
-
-	/* If we generate a power reset, we will exit sandbox! */
-	state->reset_allowed[RESET_POWER] = false;
-	ut_asserteq(-EACCES, reset_walk(RESET_WARM));
-	ut_asserteq(-EACCES, reset_walk(RESET_COLD));
-	ut_asserteq(-EACCES, reset_walk(RESET_POWER));
-
-	/*
-	 * Enable cold reset - this should make cold reset work, plus a warm
-	 * reset should be promoted to cold, since this is the next step
-	 * along.
-	 */
-	state->reset_allowed[RESET_COLD] = true;
-	ut_asserteq(-EINPROGRESS, reset_walk(RESET_WARM));
-	ut_asserteq(-EINPROGRESS, reset_walk(RESET_COLD));
-	ut_asserteq(-EACCES, reset_walk(RESET_POWER));
-	state->reset_allowed[RESET_COLD] = false;
-	state->reset_allowed[RESET_POWER] = true;
-
-	return 0;
-}
-DM_TEST(dm_test_reset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
new file mode 100644
index 0000000..5e94c07
--- /dev/null
+++ b/test/dm/sysreset.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Test that we can use particular sysreset devices */
+static int dm_test_sysreset_base(struct unit_test_state *uts)
+{
+	struct sandbox_state *state = state_get_current();
+	struct udevice *dev;
+
+	/* Device 0 is the platform data device - it should never respond */
+	ut_assertok(uclass_get_device(UCLASS_SYSRESET, 0, &dev));
+	ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_WARM));
+	ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_COLD));
+	ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_POWER));
+
+	/* Device 1 is the warm sysreset device */
+	ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
+	ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
+	ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
+	ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+
+	state->sysreset_allowed[SYSRESET_WARM] = true;
+	ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
+	state->sysreset_allowed[SYSRESET_WARM] = false;
+
+	/* Device 2 is the cold sysreset device */
+	ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
+	ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+	ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
+	state->sysreset_allowed[SYSRESET_POWER] = false;
+	ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_POWER));
+	state->sysreset_allowed[SYSRESET_POWER] = true;
+
+	return 0;
+}
+DM_TEST(dm_test_sysreset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can walk through the sysreset devices */
+static int dm_test_sysreset_walk(struct unit_test_state *uts)
+{
+	struct sandbox_state *state = state_get_current();
+
+	/* If we generate a power sysreset, we will exit sandbox! */
+	state->sysreset_allowed[SYSRESET_POWER] = false;
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_WARM));
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_COLD));
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+
+	/*
+	 * Enable cold system reset - this should make cold system reset work,
+	 * plus a warm system reset should be promoted to cold, since this is
+	 * the next step along.
+	 */
+	state->sysreset_allowed[SYSRESET_COLD] = true;
+	ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_WARM));
+	ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_COLD));
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+	state->sysreset_allowed[SYSRESET_COLD] = false;
+	state->sysreset_allowed[SYSRESET_POWER] = true;
+
+	return 0;
+}
+DM_TEST(dm_test_sysreset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-- 
cgit v0.10.2


From 6238935d018042d332aa7e90eae3addfeb11abdc Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 13 May 2016 15:50:29 -0600
Subject: Add a mailbox driver framework/uclass

A mailbox is a hardware mechanism for transferring small message and/or
notifications between the CPU on which U-Boot runs and some other device
such as an auxilliary CPU running firmware or a hardware module.

This patch defines a standard API that connects mailbox clients to mailbox
providers (drivers). Initially, DT is the only supported method for
connecting the two.

The DT binding specification (mailbox.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/device-tree-bindings/mailbox/mailbox.txt b/doc/device-tree-bindings/mailbox/mailbox.txt
new file mode 100644
index 0000000..be05b97
--- /dev/null
+++ b/doc/device-tree-bindings/mailbox/mailbox.txt
@@ -0,0 +1,32 @@
+* Generic Mailbox Controller and client driver bindings
+
+Generic binding to provide a way for Mailbox controller drivers to
+assign appropriate mailbox channel to client drivers.
+
+* Mailbox Controller
+
+Required property:
+- #mbox-cells: Must be at least 1. Number of cells in a mailbox
+		specifier.
+
+Example:
+	mailbox: mailbox {
+		...
+		#mbox-cells = <1>;
+	};
+
+
+* Mailbox Client
+
+Required property:
+- mboxes: List of phandle and mailbox channel specifiers.
+
+Optional property:
+- mbox-names: List of identifier strings for each mailbox channel.
+
+Example:
+	pwr_cntrl: power {
+		...
+		mbox-names = "pwr-ctrl", "rpc";
+		mboxes = <&mailbox 0 &mailbox 1>;
+	};
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 118b66e..f2a137a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -30,6 +30,8 @@ source "drivers/input/Kconfig"
 
 source "drivers/led/Kconfig"
 
+source "drivers/mailbox/Kconfig"
+
 source "drivers/memory/Kconfig"
 
 source "drivers/misc/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 99dd07f..f6295d2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -64,6 +64,7 @@ obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
 obj-$(CONFIG_U_QE) += qe/
+obj-y += mailbox/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
new file mode 100644
index 0000000..295e6db
--- /dev/null
+++ b/drivers/mailbox/Kconfig
@@ -0,0 +1,13 @@
+menu "Mailbox Controller Support"
+
+config DM_MAILBOX
+	bool "Enable mailbox controllers using Driver Model"
+	depends on DM && OF_CONTROL
+	help
+	  Enable support for the mailbox driver class. Mailboxes provide the
+	  ability to transfer small messages and/or notifications from one
+	  CPU to another CPU, or sometimes to dedicated HW modules. They form
+	  the basis of a variety of inter-process/inter-CPU communication
+	  protocols.
+
+endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
new file mode 100644
index 0000000..a2d96a4
--- /dev/null
+++ b/drivers/mailbox/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
new file mode 100644
index 0000000..73fa328
--- /dev/null
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <mailbox_client.h>
+#include <mailbox_uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
+{
+	return (struct mbox_ops *)dev->driver->ops;
+}
+
+static int mbox_of_xlate_default(struct mbox_chan *chan,
+				 struct fdtdec_phandle_args *args)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	if (args->args_count != 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	chan->id = args->args[0];
+
+	return 0;
+}
+
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan)
+{
+	struct fdtdec_phandle_args args;
+	int ret;
+	struct udevice *dev_mbox;
+	struct mbox_ops *ops;
+
+	debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
+
+	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+					     "mboxes", "#mbox-cells", 0,
+					     index, &args);
+	if (ret) {
+		debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_MAILBOX, args.node,
+					     &dev_mbox);
+	if (ret) {
+		debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+	ops = mbox_dev_ops(dev_mbox);
+
+	chan->dev = dev_mbox;
+	if (ops->of_xlate)
+		ret = ops->of_xlate(chan, &args);
+	else
+		ret = mbox_of_xlate_default(chan, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ops->request(chan);
+	if (ret) {
+		debug("ops->request() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
+
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names",
+				name);
+	if (index < 0) {
+		debug("fdt_find_string() failed: %d\n", index);
+		return index;
+	}
+
+	return mbox_get_by_index(dev, index, chan);
+}
+
+int mbox_free(struct mbox_chan *chan)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return ops->free(chan);
+}
+
+int mbox_send(struct mbox_chan *chan, const void *data)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	return ops->send(chan, data);
+}
+
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+	ulong start_time;
+	int ret;
+
+	debug("%s(chan=%p, data=%p, timeout_us=%ld)\n", __func__, chan, data,
+	      timeout_us);
+
+	start_time = timer_get_us();
+	/*
+	 * Account for partial us ticks, but if timeout_us is 0, ensure we
+	 * still don't wait at all.
+	 */
+	if (timeout_us)
+		timeout_us++;
+
+	for (;;) {
+		ret = ops->recv(chan, data);
+		if (ret != -ENODATA)
+			return ret;
+		if ((timer_get_us() - start_time) >= timeout_us)
+			return -ETIMEDOUT;
+	}
+}
+
+UCLASS_DRIVER(mailbox) = {
+	.id		= UCLASS_MAILBOX,
+	.name		= "mailbox",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index f9ff45e..0777cbe 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -44,6 +44,7 @@ enum uclass_id {
 	UCLASS_KEYBOARD,	/* Keyboard input device */
 	UCLASS_LED,		/* Light-emitting diode (LED) */
 	UCLASS_LPC,		/* x86 'low pin count' interface */
+	UCLASS_MAILBOX,		/* Mailbox controller */
 	UCLASS_MASS_STORAGE,	/* Mass storage device */
 	UCLASS_MISC,		/* Miscellaneous device */
 	UCLASS_MMC,		/* SD / MMC card or chip */
diff --git a/include/mailbox_client.h b/include/mailbox_client.h
new file mode 100644
index 0000000..8345ea0
--- /dev/null
+++ b/include/mailbox_client.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_CLIENT_H
+#define _MAILBOX_CLIENT_H
+
+/**
+ * A mailbox is a hardware mechanism for transferring small fixed-size messages
+ * and/or notifications between the CPU on which U-Boot runs and some other
+ * device such as an auxiliary CPU running firmware or a hardware module.
+ *
+ * Data transfer is optional; a mailbox may consist solely of a notification
+ * mechanism. When data transfer is implemented, it is via HW registers or
+ * FIFOs, rather than via RAM-based buffers. The mailbox API generally
+ * implements any communication protocol enforced solely by hardware, and
+ * leaves any higher-level protocols to other layers.
+ *
+ * A mailbox channel is a bi-directional mechanism that can send a message or
+ * notification to a single specific remote entity, and receive messages or
+ * notifications from that entity. The size, content, and format of such
+ * messages is defined by the mailbox implementation, or the remote entity with
+ * which it communicates; there is no general standard at this API level.
+ *
+ * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
+ * will often implement multiple separate mailbox channels, since the hardware
+ * it manages often has this capability. mailbox_uclass.h describes the
+ * interface which mailbox providers must implement.
+ *
+ * Mailbox consumers/clients generate and send, or receive and process,
+ * messages. This header file describes the API used by clients.
+ */
+
+struct udevice;
+
+/**
+ * struct mbox_chan - A handle to a single mailbox channel.
+ *
+ * Clients provide storage for channels. The content of the channel structure
+ * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
+ * is initialized by "get"ing the mailbox. The channel struct is passed to all
+ * other mailbox APIs to identify which mailbox to operate upon.
+ *
+ * @dev: The device which implements the mailbox.
+ * @id: The mailbox channel ID within the provider.
+ *
+ * Currently, the mailbox API assumes that a single integer ID is enough to
+ * identify and configure any mailbox channel for any mailbox provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow mailbox providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct mbox_chan {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+/**
+ * mbox_get_by_index - Get/request a mailbox by integer index
+ *
+ * This looks up and requests a mailbox channel. The index is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel indices to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the mailbox channel to request, within the
+ *		client's list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
+
+/**
+ * mbox_get_by_name - Get/request a mailbox by name
+ *
+ * This looks up and requests a mailbox channel. The name is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel names to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the mailbox channel to request, within the client's
+ *		list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan);
+
+/**
+ * mbox_free - Free a previously requested mailbox channel.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_free(struct mbox_chan *chan);
+
+/**
+ * mbox_send - Send a message over a mailbox channel
+ *
+ * This function will send a message to the remote entity. It may return before
+ * the remote entity has received and/or processed the message.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the message to transfer. The format and size of
+ *		the memory region pointed at by @data is determined by the
+ *		mailbox provider. Providers that solely transfer notifications
+ *		will ignore this parameter.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_send(struct mbox_chan *chan, const void *data);
+
+/**
+ * mbox_recv - Receive any available message from a mailbox channel
+ *
+ * This function will wait (up to the specified @timeout_us) for a message to
+ * be sent by the remote entity, and write the content of any such message
+ * into a caller-provided buffer.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the buffer to receive the message. The format and
+ *		size of the memory region pointed at by @data is determined by
+ *		the mailbox provider. Providers that solely transfer
+ *		notifications will ignore this parameter.
+ * @timeout_us:	The maximum time to wait for a message to be available, in
+ *		micro-seconds. A value of 0 does not wait at all.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative error
+ * code.
+ */
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
+
+#endif
diff --git a/include/mailbox_uclass.h b/include/mailbox_uclass.h
new file mode 100644
index 0000000..6a2994c
--- /dev/null
+++ b/include/mailbox_uclass.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_UCLASS_H
+#define _MAILBOX_UCLASS_H
+
+/* See mailbox_client.h for background documentation. */
+
+#include <mailbox_client.h>
+
+struct udevice;
+
+/**
+ * struct mbox_ops - The functions that a mailbox driver must implement.
+ */
+struct mbox_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
+	 *
+	 * The mailbox core calls this function as the first step in
+	 * implementing a client's mbox_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the mailbox core will use
+	 * a default implementation, which assumes #mbox-cells = <1>, and that
+	 * the DT cell contains a simple integer channel ID.
+	 *
+	 * At present, the mailbox API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @chan:	The channel to hold the translation result.
+	 * @args:	The mailbox specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct mbox_chan *chan,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated channel.
+	 *
+	 * The mailbox core calls this function as the second step in
+	 * implementing a client's mbox_get_by_*() call, following a successful
+	 * xxx_xlate() call.
+	 *
+	 * @chan:	The channel to request; this has been filled in by a
+	 *		previoux xxx_xlate() function call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct mbox_chan *chan);
+	/**
+	 * free - Free a previously requested channel.
+	 *
+	 * This is the implementation of the client mbox_free() API.
+	 *
+	 * @chan:	The channel to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct mbox_chan *chan);
+	/**
+	* send - Send a message over a mailbox channel
+	*
+	* @chan:	The channel to send to the message to.
+	* @data:	A pointer to the message to send.
+	* @return 0 if OK, or a negative error code.
+	*/
+	int (*send)(struct mbox_chan *chan, const void *data);
+	/**
+	* recv - Receive any available message from the channel.
+	*
+	* This function does not block. If not message is immediately
+	* available, the function should return an error.
+	*
+	* @chan:	The channel to receive to the message from.
+	* @data:	A pointer to the buffer to hold the received message.
+	* @return 0 if OK, -ENODATA if no message was available, or a negative
+	* error code.
+	*/
+	int (*recv)(struct mbox_chan *chan, void *data);
+};
+
+#endif
-- 
cgit v0.10.2


From 8961b524240f40ac2fefcdee0818af10899832f2 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 16 May 2016 17:41:37 -0600
Subject: mailbox: implement a sandbox test

This adds a sandbox mailbox implementation (provider), a test client
device, instantiates them both from Sandbox's DT, and adds a DM test
that excercises everything.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org> # v1

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8930009..686c215 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -216,6 +216,17 @@
 		};
 	};
 
+	mbox: mbox {
+		compatible = "sandbox,mbox";
+		#mbox-cells = <1>;
+	};
+
+	mbox-test {
+		compatible = "sandbox,mbox-test";
+		mboxes = <&mbox 100>, <&mbox 1>;
+		mbox-names = "other", "test";
+	};
+
 	mmc {
 		compatible = "sandbox,mmc";
 	};
diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h
new file mode 100644
index 0000000..2d7b7d0
--- /dev/null
+++ b/arch/sandbox/include/asm/mbox.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_MBOX_H
+#define __SANDBOX_MBOX_H
+
+#include <common.h>
+
+#define SANDBOX_MBOX_PING_XOR 0x12345678
+
+struct udevice;
+
+int sandbox_mbox_test_get(struct udevice *dev);
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg);
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg);
+int sandbox_mbox_test_free(struct udevice *dev);
+
+#endif
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 6e30c5d..4eb3c22 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -170,3 +170,6 @@ CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
+CONFIG_MISC=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 295e6db..9087512 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -10,4 +10,11 @@ config DM_MAILBOX
 	  the basis of a variety of inter-process/inter-CPU communication
 	  protocols.
 
+config SANDBOX_MBOX
+	bool "Enable the sandbox mailbox test driver"
+	depends on DM_MAILBOX && SANDBOX
+	help
+	  Enable support for a test mailbox implementation, which simply echos
+	  back a modified version of any message that is sent.
+
 endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index a2d96a4..bbae4de 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -3,3 +3,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
diff --git a/drivers/mailbox/sandbox-mbox-test.c b/drivers/mailbox/sandbox-mbox-test.c
new file mode 100644
index 0000000..02d161a
--- /dev/null
+++ b/drivers/mailbox/sandbox-mbox-test.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_client.h>
+#include <asm/io.h>
+
+struct sandbox_mbox_test {
+	struct mbox_chan chan;
+};
+
+int sandbox_mbox_test_get(struct udevice *dev)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_get_by_name(dev, "test", &sbmt->chan);
+}
+
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_send(&sbmt->chan, &msg);
+}
+
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_recv(&sbmt->chan, msg, 100);
+}
+
+int sandbox_mbox_test_free(struct udevice *dev)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_free(&sbmt->chan);
+}
+
+static const struct udevice_id sandbox_mbox_test_ids[] = {
+	{ .compatible = "sandbox,mbox-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_mbox_test) = {
+	.name = "sandbox_mbox_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_mbox_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_mbox_test),
+};
diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c
new file mode 100644
index 0000000..1b7ac23
--- /dev/null
+++ b/drivers/mailbox/sandbox-mbox.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_uclass.h>
+#include <asm/io.h>
+#include <asm/mbox.h>
+
+#define SANDBOX_MBOX_CHANNELS 2
+
+struct sandbox_mbox_chan {
+	bool rx_msg_valid;
+	uint32_t rx_msg;
+};
+
+struct sandbox_mbox {
+	struct sandbox_mbox_chan chans[SANDBOX_MBOX_CHANNELS];
+};
+
+static int sandbox_mbox_request(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	if (chan->id >= SANDBOX_MBOX_CHANNELS)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sandbox_mbox_free(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return 0;
+}
+
+static int sandbox_mbox_send(struct mbox_chan *chan, const void *data)
+{
+	struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+	const uint32_t *pmsg = data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR;
+	sbm->chans[chan->id].rx_msg_valid = true;
+
+	return 0;
+}
+
+static int sandbox_mbox_recv(struct mbox_chan *chan, void *data)
+{
+	struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+	uint32_t *pmsg = data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	if (!sbm->chans[chan->id].rx_msg_valid)
+		return -ENODATA;
+
+	*pmsg = sbm->chans[chan->id].rx_msg;
+	sbm->chans[chan->id].rx_msg_valid = false;
+
+	return 0;
+}
+
+static int sandbox_mbox_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int sandbox_mbox_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_mbox_ids[] = {
+	{ .compatible = "sandbox,mbox" },
+	{ }
+};
+
+struct mbox_ops sandbox_mbox_mbox_ops = {
+	.request = sandbox_mbox_request,
+	.free = sandbox_mbox_free,
+	.send = sandbox_mbox_send,
+	.recv = sandbox_mbox_recv,
+};
+
+U_BOOT_DRIVER(sandbox_mbox) = {
+	.name = "sandbox_mbox",
+	.id = UCLASS_MAILBOX,
+	.of_match = sandbox_mbox_ids,
+	.bind = sandbox_mbox_bind,
+	.probe = sandbox_mbox_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_mbox),
+	.ops = &sandbox_mbox_mbox_ops,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index fd781e8..9eaf04b 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_DM_ETH) += eth.o
 obj-$(CONFIG_DM_GPIO) += gpio.o
 obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_LED) += led.o
+obj-$(CONFIG_DM_MAILBOX) += mailbox.o
 obj-$(CONFIG_DM_MMC) += mmc.o
 obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_RAM) += ram.o
diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c
new file mode 100644
index 0000000..be7bd6d
--- /dev/null
+++ b/test/dm/mailbox.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <asm/mbox.h>
+#include <test/ut.h>
+
+static int dm_test_mailbox(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	uint32_t msg;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "mbox-test", &dev));
+	ut_assertok(sandbox_mbox_test_get(dev));
+
+	ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+	ut_assertok(sandbox_mbox_test_send(dev, 0xaaff9955UL));
+	ut_assertok(sandbox_mbox_test_recv(dev, &msg));
+	ut_asserteq(msg, 0xaaff9955UL ^ SANDBOX_MBOX_PING_XOR);
+	ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+
+	ut_assertok(sandbox_mbox_test_free(dev));
+
+	return 0;
+}
+DM_TEST(dm_test_mailbox, DM_TESTF_SCAN_FDT);
-- 
cgit v0.10.2


From d0375f3cc55ce740836f9ba6fe081ed0fdc19a3c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 7 Aug 2015 07:42:22 -0600
Subject: arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size info

This shows a proper progress display and the total amount of data
transferred. Enable it for Raspberry Pi.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>

diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index af58182..9ef5eae 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -106,6 +106,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
 #define CONFIG_MISC_INIT_R
 #define CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
-- 
cgit v0.10.2


From 1fb67608b309bd7f49842fbdfb1dc2b18a250965 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:52 -0600
Subject: tiny-printf: Tidy up a few nits

- Rename 'w' to 'width' to make it more obvious what it is used for
- Use bool and int types instead of char to avoid register-masking on
32-bit machines

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index a06abed..fbd5368 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -52,8 +52,8 @@ int vprintf(const char *fmt, va_list va)
 		if (ch != '%') {
 			putc(ch);
 		} else {
-			char lz = 0;
-			char w = 0;
+			bool lz = false;
+			int width = 0;
 
 			ch = *(fmt++);
 			if (ch == '0') {
@@ -62,9 +62,9 @@ int vprintf(const char *fmt, va_list va)
 			}
 
 			if (ch >= '0' && ch <= '9') {
-				w = 0;
+				width = 0;
 				while (ch >= '0' && ch <= '9') {
-					w = (w * 10) + ch - '0';
+					width = (width * 10) + ch - '0';
 					ch = *fmt++;
 				}
 			}
@@ -73,7 +73,7 @@ int vprintf(const char *fmt, va_list va)
 			zs = 0;
 
 			switch (ch) {
-			case 0:
+			case '\0':
 				goto abort;
 			case 'u':
 			case 'd':
@@ -112,9 +112,9 @@ int vprintf(const char *fmt, va_list va)
 
 			*bf = 0;
 			bf = p;
-			while (*bf++ && w > 0)
-				w--;
-			while (w-- > 0)
+			while (*bf++ && width > 0)
+				width--;
+			while (width-- > 0)
 				putc(lz ? '0' : ' ');
 			if (p) {
 				while ((ch = *p++))
-- 
cgit v0.10.2


From 5c411d88be8df5f6a8a1ea0c961f7c35ba82c064 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:53 -0600
Subject: tiny-printf: Support snprintf()

Add a simple version of this function for SPL. It does not check the buffer
size as this would add to the code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index fbd5368..4b70263 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -16,6 +16,9 @@
 static char *bf;
 static char zs;
 
+/* Current position in sprintf() output string */
+static char *outstr;
+
 static void out(char c)
 {
 	*bf++ = c;
@@ -40,7 +43,7 @@ static void div_out(unsigned int *num, unsigned int div)
 		out_dgt(dgt);
 }
 
-int vprintf(const char *fmt, va_list va)
+int _vprintf(const char *fmt, va_list va, void (*putc)(const char ch))
 {
 	char ch;
 	char *p;
@@ -133,8 +136,28 @@ int printf(const char *fmt, ...)
 	int ret;
 
 	va_start(va, fmt);
-	ret = vprintf(fmt, va);
+	ret = _vprintf(fmt, va, putc);
+	va_end(va);
+
+	return ret;
+}
+
+static void putc_outstr(char ch)
+{
+	*outstr++ = ch;
+}
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+	va_list va;
+	int ret;
+
+	va_start(va, fmt);
+	outstr = buf;
+	ret = _vprintf(fmt, va, putc_outstr);
 	va_end(va);
+	*outstr = '\0';
 
 	return ret;
 }
-- 
cgit v0.10.2


From 5c0862155c883b9e134fae72d25f1b5a93260510 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:54 -0600
Subject: reset: Drop the reset failure message

This adds to code size and is not needed, since hang() will print a message.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/misc/sysreset-uclass.c b/drivers/misc/sysreset-uclass.c
index e41efca..3566d17 100644
--- a/drivers/misc/sysreset-uclass.c
+++ b/drivers/misc/sysreset-uclass.c
@@ -55,7 +55,7 @@ void sysreset_walk_halt(enum sysreset_t type)
 		mdelay(100);
 
 	/* Still no reset? Give up */
-	printf("System reset not supported on this platform\n");
+	debug("System reset not supported on this platform\n");
 	hang();
 }
 
-- 
cgit v0.10.2


From e98dd20ccec30311dddd165f945c7ce0dedef6db Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:55 -0600
Subject: mmc: Drop mmc_register()

This function is no longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 74b3d68..1ddeff4 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1531,15 +1531,6 @@ static int mmc_send_if_cond(struct mmc *mmc)
 	return 0;
 }
 
-/* not used any more */
-int __deprecated mmc_register(struct mmc *mmc)
-{
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-	printf("%s is deprecated! use mmc_create() instead.\n", __func__);
-#endif
-	return -1;
-}
-
 #ifdef CONFIG_BLK
 int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 {
diff --git a/include/mmc.h b/include/mmc.h
index a5c6573..056296e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -411,7 +411,6 @@ enum mmc_hwpart_conf_mode {
 	MMC_HWPART_CONF_COMPLETE,
 };
 
-int mmc_register(struct mmc *mmc);
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 
 /**
-- 
cgit v0.10.2


From 9cf7b1a74c8c17145e39d34893cce763e098efd2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:56 -0600
Subject: mmc: Drop dead mmc code for non-generic MMC

All boards that use MMC define CONFIG_GENERIC_MMC now, so we can drop this
old code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/mmc.c b/cmd/mmc.c
index eb4a547..b2761e9 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -11,66 +11,6 @@
 #include <mmc.h>
 
 static int curr_device = -1;
-#ifndef CONFIG_GENERIC_MMC
-int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int dev;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-
-	if (strcmp(argv[1], "init") == 0) {
-		if (argc == 2) {
-			if (curr_device < 0)
-				dev = 1;
-			else
-				dev = curr_device;
-		} else if (argc == 3) {
-			dev = (int)simple_strtoul(argv[2], NULL, 10);
-		} else {
-			return CMD_RET_USAGE;
-		}
-
-		if (mmc_legacy_init(dev) != 0) {
-			puts("No MMC card found\n");
-			return 1;
-		}
-
-		curr_device = dev;
-		printf("mmc%d is available\n", curr_device);
-	} else if (strcmp(argv[1], "device") == 0) {
-		if (argc == 2) {
-			if (curr_device < 0) {
-				puts("No MMC device available\n");
-				return 1;
-			}
-		} else if (argc == 3) {
-			dev = (int)simple_strtoul(argv[2], NULL, 10);
-
-#ifdef CONFIG_SYS_MMC_SET_DEV
-			if (mmc_set_dev(dev) != 0)
-				return 1;
-#endif
-			curr_device = dev;
-		} else {
-			return CMD_RET_USAGE;
-		}
-
-		printf("mmc%d is current device\n", curr_device);
-	} else {
-		return CMD_RET_USAGE;
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	mmc, 3, 1, do_mmc,
-	"MMC sub-system",
-	"init [dev] - init MMC sub system\n"
-	"mmc device [dev] - show or set current device"
-);
-#else /* !CONFIG_GENERIC_MMC */
 
 static void print_mmcinfo(struct mmc *mmc)
 {
@@ -881,5 +821,3 @@ U_BOOT_CMD(
 	"display MMC info",
 	"- display info of the current MMC device"
 );
-
-#endif /* !CONFIG_GENERIC_MMC */
diff --git a/include/mmc.h b/include/mmc.h
index 056296e..7fdfc32 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -491,16 +491,12 @@ int mmc_start_init(struct mmc *mmc);
  */
 void mmc_set_preinit(struct mmc *mmc, int preinit);
 
-#ifdef CONFIG_GENERIC_MMC
 #ifdef CONFIG_MMC_SPI
 #define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
 #else
 #define mmc_host_is_spi(mmc)	0
 #endif
 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
-#else
-int mmc_legacy_init(int verbose);
-#endif
 
 void board_mmc_power_init(void);
 int board_mmc_init(bd_t *bis);
-- 
cgit v0.10.2


From 61fe076f0fceaa00bcbb8901504aedf1d1096293 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:57 -0600
Subject: mmc: Use byte array for multipliers

We don't need an int since no value is over 80. This saves a small amount of
SPL space (about 44 bytes).

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1ddeff4..b7c936c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -984,7 +984,7 @@ static const int fbase[] = {
 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
  * to platforms without floating point.
  */
-static const int multipliers[] = {
+static const u8 multipliers[] = {
 	0,	/* reserved */
 	10,
 	12,
-- 
cgit v0.10.2


From dcdc1f6a9bd8abaa41b5eacd9310787cf96f4c4e Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Tue, 19 Apr 2016 22:43:39 +0200
Subject: tools/env: pass key as argument to env_aes_cbc_crypt

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 06cf63d..0c44807 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -106,7 +106,7 @@ static struct environment environment = {
 	.flag_scheme = FLAG_NONE,
 };
 
-static int env_aes_cbc_crypt(char *data, const int enc);
+static int env_aes_cbc_crypt(char *data, const int enc, uint8_t *key);
 
 static int HaveRedundEnv = 0;
 
@@ -304,7 +304,8 @@ int fw_env_close(void)
 {
 	int ret;
 	if (common_args.aes_flag) {
-		ret = env_aes_cbc_crypt(environment.data, 1);
+		ret = env_aes_cbc_crypt(environment.data, 1,
+					common_args.aes_key);
 		if (ret) {
 			fprintf(stderr,
 				"Error: can't encrypt env for flash\n");
@@ -949,7 +950,7 @@ static int flash_flag_obsolete (int dev, int fd, off_t offset)
 }
 
 /* Encrypt or decrypt the environment before writing or reading it. */
-static int env_aes_cbc_crypt(char *payload, const int enc)
+static int env_aes_cbc_crypt(char *payload, const int enc, uint8_t *key)
 {
 	uint8_t *data = (uint8_t *)payload;
 	const int len = getenvsize();
@@ -957,7 +958,7 @@ static int env_aes_cbc_crypt(char *payload, const int enc)
 	uint32_t aes_blocks;
 
 	/* First we expand the key. */
-	aes_expand_key(common_args.aes_key, key_exp);
+	aes_expand_key(key, key_exp);
 
 	/* Calculate the number of AES blocks to encrypt. */
 	aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
@@ -1186,7 +1187,8 @@ int fw_env_open(void)
 	crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
 
 	if (common_args.aes_flag) {
-		ret = env_aes_cbc_crypt(environment.data, 0);
+		ret = env_aes_cbc_crypt(environment.data, 0,
+					common_args.aes_key);
 		if (ret)
 			return ret;
 	}
@@ -1243,7 +1245,8 @@ int fw_env_open(void)
 		crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
 
 		if (common_args.aes_flag) {
-			ret = env_aes_cbc_crypt(redundant->data, 0);
+			ret = env_aes_cbc_crypt(redundant->data, 0,
+						common_args.aes_key);
 			if (ret)
 				return ret;
 		}
-- 
cgit v0.10.2


From c3a23e8b5f7c13d9de389d25d756a7da64bc5144 Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Tue, 19 Apr 2016 22:43:40 +0200
Subject: tools/env: remove 'extern' from function prototype in fw_env.h

checkpatch complains about in succeding patch. Prefer to fix all
declarations in a dedicated patch.

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 57149e7..7345922 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -78,12 +78,12 @@ extern struct setenv_args setenv_args;
 
 int parse_aes_key(char *key, uint8_t *bin_key);
 
-extern int   fw_printenv(int argc, char *argv[]);
-extern char *fw_getenv  (char *name);
-extern int fw_setenv  (int argc, char *argv[]);
-extern int fw_parse_script(char *fname);
-extern int fw_env_open(void);
-extern int fw_env_write(char *name, char *value);
-extern int fw_env_close(void);
+int   fw_printenv(int argc, char *argv[]);
+char *fw_getenv(char *name);
+int fw_setenv(int argc, char *argv[]);
+int fw_parse_script(char *fname);
+int fw_env_open(void);
+int fw_env_write(char *name, char *value);
+int fw_env_close(void);
 
-extern unsigned	long  crc32	 (unsigned long, const unsigned char *, unsigned);
+unsigned long crc32(unsigned long, const unsigned char *, unsigned);
-- 
cgit v0.10.2


From cedb341e7f44f4686c8c0afb149a9f7940be110a Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Tue, 19 Apr 2016 22:43:41 +0200
Subject: tools/env: fw_printenv pass value_only as argument

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 0c44807..aa39485 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -239,7 +239,7 @@ int parse_aes_key(char *key, uint8_t *bin_key)
  * Print the current definition of one, or more, or all
  * environment variables
  */
-int fw_printenv (int argc, char *argv[])
+int fw_printenv(int argc, char *argv[], int value_only)
 {
 	char *env, *nxt;
 	int i, rc = 0;
@@ -262,7 +262,7 @@ int fw_printenv (int argc, char *argv[])
 		return 0;
 	}
 
-	if (printenv_args.name_suppress && argc != 1) {
+	if (value_only && argc != 1) {
 		fprintf(stderr,
 			"## Error: `-n' option requires exactly one argument\n");
 		return -1;
@@ -283,7 +283,7 @@ int fw_printenv (int argc, char *argv[])
 			}
 			val = envmatch (name, env);
 			if (val) {
-				if (!printenv_args.name_suppress) {
+				if (!value_only) {
 					fputs (name, stdout);
 					putc ('=', stdout);
 				}
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 7345922..d4daeea 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -67,7 +67,7 @@ struct common_args {
 extern struct common_args common_args;
 
 struct printenv_args {
-	int name_suppress;
+	int value_only;
 };
 extern struct printenv_args printenv_args;
 
@@ -78,7 +78,7 @@ extern struct setenv_args setenv_args;
 
 int parse_aes_key(char *key, uint8_t *bin_key);
 
-int   fw_printenv(int argc, char *argv[]);
+int fw_printenv(int argc, char *argv[], int value_only);
 char *fw_getenv(char *name);
 int fw_setenv(int argc, char *argv[]);
 int fw_parse_script(char *fname);
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 3706d8f..2a45a0d 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -151,7 +151,7 @@ int parse_printenv_args(int argc, char *argv[])
 	       EOF) {
 		switch (c) {
 		case 'n':
-			printenv_args.name_suppress = 1;
+			printenv_args.value_only = 1;
 			break;
 		case 'a':
 		case 'c':
@@ -240,7 +240,7 @@ int main(int argc, char *argv[])
 	}
 
 	if (do_printenv) {
-		if (fw_printenv(argc, argv) != 0)
+		if (fw_printenv(argc, argv, printenv_args.value_only))
 			retval = EXIT_FAILURE;
 	} else {
 		if (!setenv_args.script_file) {
-- 
cgit v0.10.2


From f71cee4bfc9a8f9be40a49ec2da84f4344e398fc Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Tue, 19 Apr 2016 22:43:42 +0200
Subject: tools/env: compute size of usable area only once

for double buffering to work, redundant buffers must have equal size

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index aa39485..1654ac0 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -75,7 +75,8 @@ static int dev_current;
 
 #define CUR_ENVSIZE ENVSIZE(dev_current)
 
-#define ENV_SIZE      getenvsize()
+static unsigned long usable_envsize;
+#define ENV_SIZE      usable_envsize
 
 struct env_image_single {
 	uint32_t	crc;	/* CRC32 over data bytes    */
@@ -124,18 +125,6 @@ static int parse_config (void);
 #if defined(CONFIG_FILE)
 static int get_config (char *);
 #endif
-static inline ulong getenvsize (void)
-{
-	ulong rc = CUR_ENVSIZE - sizeof(uint32_t);
-
-	if (HaveRedundEnv)
-		rc -= sizeof (char);
-
-	if (common_args.aes_flag)
-		rc &= ~(AES_KEY_LENGTH - 1);
-
-	return rc;
-}
 
 static char *skip_chars(char *s)
 {
@@ -953,7 +942,7 @@ static int flash_flag_obsolete (int dev, int fd, off_t offset)
 static int env_aes_cbc_crypt(char *payload, const int enc, uint8_t *key)
 {
 	uint8_t *data = (uint8_t *)payload;
-	const int len = getenvsize();
+	const int len = usable_envsize;
 	uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
 	uint32_t aes_blocks;
 
@@ -1382,6 +1371,21 @@ static int parse_config ()
 			DEVNAME (1), strerror (errno));
 		return -1;
 	}
+
+	if (HaveRedundEnv && ENVSIZE(0) != ENVSIZE(1)) {
+		ENVSIZE(0) = ENVSIZE(1) = min(ENVSIZE(0), ENVSIZE(1));
+		fprintf(stderr,
+			"Redundant environments have inequal size, set to 0x%08lx\n",
+			ENVSIZE(1));
+	}
+
+	usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
+	if (HaveRedundEnv)
+		usable_envsize -= sizeof(char);
+
+	if (common_args.aes_flag)
+		usable_envsize &= ~(AES_KEY_LENGTH - 1);
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From 71db3270dbee381ebdbc183cf88dde46d9a59afb Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 25 Apr 2016 15:25:37 +0200
Subject: dm: gpio: pca953x: Support PCA953X with 40 GPIOs

A DM driver for PCA953x was recently introduced by Peng Fan, which lacked
support for the 40 GPIO versions.

This patch adds support for these chips.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Peng Fan  <van.freenix@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 987d10e..065b181 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -16,8 +16,8 @@
  *
  * TODO:
  * 1. Support PCA957X_TYPE
- * 2. Support max 40 gpio pins
- * 3. Support Plolarity Inversion
+ * 2. Support 24 gpio pins
+ * 3. Support Polarity Inversion
  */
 
 #include <common.h>
@@ -47,7 +47,7 @@ enum {
 	PCA953X_DIRECTION_OUT,
 };
 
-#define MAX_BANK 3
+#define MAX_BANK 5
 #define BANK_SZ 8
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -121,6 +121,9 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
 		ret = dm_i2c_read(dev, reg, val, 1);
 	} else if (info->gpio_count <= 16) {
 		ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+	} else if (info->gpio_count == 40) {
+		/* Auto increment */
+		ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
 	} else {
 		dev_err(dev, "Unsupported now\n");
 		return -EINVAL;
-- 
cgit v0.10.2


From 90a7417602e89889a703538e47e323051ecea1fd Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 28 Apr 2016 10:36:11 +0200
Subject: SPL: FIT: Align loading address for header

If bl_len is not aligned it can caused a problem because another code
expects that start is aligned.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 26842ba..90acbb2 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -123,6 +123,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * be before CONFIG_SYS_TEXT_BASE.
 	 */
 	fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
+	fit = (void *)ALIGN((ulong)fit, 8);
 	sectors = (size + info->bl_len - 1) / info->bl_len;
 	count = info->read(info, sector, sectors, fit);
 	debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
-- 
cgit v0.10.2


From 04681cb3a4d2ef5351f94132e325fb8841d37961 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 1 May 2016 00:35:54 +0200
Subject: cmd: disk: Fix unused variable warning

If serial support is not compiled into U-Boot, which may be the case
for some SPL builds, the following warning will be generated in disk.c:

cmd/disk.c: In function 'common_diskboot':
cmd/disk.c:16:6: warning: variable 'dev' set but not used [-Wunused-but-set-variable]
  int dev, part;
      ^
The warning is a result of printf() calls being optimized away, and
thus the whole dev variable becomes indeed unused. Mark the variable
as __maybe_unused .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/disk.c b/cmd/disk.c
index fcc4123..92de3af 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -13,7 +13,8 @@
 int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
 		    char *const argv[])
 {
-	int dev, part;
+	__maybe_unused int dev;
+	int part;
 	ulong addr = CONFIG_SYS_LOAD_ADDR;
 	ulong cnt;
 	disk_partition_t info;
-- 
cgit v0.10.2


From a565386762162019c297b8537f17bb3f4d4d4d88 Mon Sep 17 00:00:00 2001
From: Patrick Delaunay <patrick.delaunay73@gmail.com>
Date: Mon, 2 May 2016 14:43:33 +0200
Subject: disk: part_efi: fix check of the max partition size

the last value acceptable value for offset is last_usable_lba + 1
and not last_usable_lba - 1

issue found with SDCARD partition commands on u-boot 2015.10
but this part of code don't change

1- create GPT partion on all the card
  > gpt write mmc 0 name=test,start=0,size=0
  > part list mmc 0

Partition Map for MMC device 0  --   Partition Type: EFI

Part      Start LBA          End LBA                       Name
            Attributes
            Type GUID
            Partition GUID
  1        0x00000022       0x003a9fde       "test"
            attrs:     0x0000000000000000
            type:     ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
            type:     data
            guid:     b710eb04-45b9-e94a-8d0b-21458d596f54

=> Start = 0x22*512 = 0x4400
=> Size = (0x003a9fde-0x22+1) * 512  = 0x753F7A00

2- try to recreate the same partition with the next command
   (block size:512 bytes = 0x200)

  > gpt write mmc 0 name=test,start=0x4400,size=0x753F7A00
    Writing GPT: Partitions layout exceds disk size

  > gpt write mmc 0 name=test,start=0x4400,size=0x753F7800
    Writing GPT: Partitions layout exceds disk size

  > gpt write mmc 0 name=test,start=0x4400,size=0x753F7600
    Writing GPT: success!

Partition Map for MMC device 0  --   Partition Type: EFI

Part      Start LBA          End LBA                       Name
            Attributes
            Type GUID
            Partition GUID
  1        0x00000022       0x003a9fdc       "test"
            attrs:     0x0000000000000000
            type:     ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
            type:     data
            guid:     36ec30ef-7ca4-cd48-97cd-ea9fb95185d0

the max LBA when the size is indicated (0x003a9fdc) is lower than
when u-boot compute the max allowed value with size=0 (0x003a9fde)

in the code :

     /* partition ending lba */
     if ((i == parts - 1) && (partitions[i].size == 0))
		/* extend the last partition to maximuim */
		gpt_e[i].ending_lba = gpt_h->last_usable_lba;
     else
		gpt_e[i].ending_lba = cpu_to_le64(offset - 1);

so offset = gpt_h->last_usable_lba + 1 is acceptable !
but the test (offset >= last_usable_lba) cause the error

END

Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>disk: part_efi: fix check of the max partition size
the last value acceptable value for offset is (last_usable_lba + 1)
and not (last_usable_lba - 1)

issue found with SDCARD partition commands on u-boot 2015.10
but this part of code don't change

1- I create GPT partion on all the card (start and size undefined)

  > gpt write mmc 0 name=test,start=0,size=0
  > part list mmc 0

Partition Map for MMC device 0  --   Partition Type: EFI

Part      Start LBA          End LBA                       Name
            Attributes
            Type GUID
            Partition GUID
  1        0x00000022       0x003a9fde       "test"
            attrs:     0x0000000000000000
            type:     ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
            type:     data
            guid:     b710eb04-45b9-e94a-8d0b-21458d596f54

=> Start = 0x22*512 = 0x4400
=> Size = (0x003a9fde-0x22+1) * 512  = 0x753F7A00

2- I try to recreate the same partition with the command gpt write
   and with start and size values (block size:512 bytes = 0x200)

  > gpt write mmc 0 name=test,start=0x4400,size=0x753F7A00
    Writing GPT: Partitions layout exceds disk size

  > gpt write mmc 0 name=test,start=0x4400,size=0x753F7800
    Writing GPT: Partitions layout exceds disk size

  > gpt write mmc 0 name=test,start=0x4400,size=0x753F7600
    Writing GPT: success!

  I check the partition created :

  > part list mmc 0

Partition Map for MMC device 0  --   Partition Type: EFI

Part      Start LBA          End LBA                       Name
            Attributes
            Type GUID
            Partition GUID
  1        0x00000022       0x003a9fdc       "test"
            attrs:     0x0000000000000000
            type:     ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
            type:     data
            guid:     36ec30ef-7ca4-cd48-97cd-ea9fb95185d0

=> but the max LBA when the size is indicated (0x003a9fdc) is lower than
   when u-boot compute the max allowed value with size=0 (0x003a9fde)

3- in the code, just after my patch, line 446

     /* partition ending lba */
     if ((i == parts - 1) && (partitions[i].size == 0))
		/* extend the last partition to maximuim */
		gpt_e[i].ending_lba = gpt_h->last_usable_lba;
     else
		gpt_e[i].ending_lba = cpu_to_le64(offset - 1);

  so offset = gpt_h->last_usable_lba + 1 is acceptable !
  (it the value used when size is 0)

  but today the test (offset >= last_usable_lba) cause the error
  my patch only solve this issue

END

Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>

diff --git a/disk/part_efi.c b/disk/part_efi.c
index fe308d7..0af1e92 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -439,7 +439,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
 			gpt_e[i].starting_lba = cpu_to_le64(offset);
 			offset += partitions[i].size;
 		}
-		if (offset >= last_usable_lba) {
+		if (offset > (last_usable_lba + 1)) {
 			printf("Partitions layout exceds disk size\n");
 			return -1;
 		}
-- 
cgit v0.10.2


From dafd64888c21abc43edbe7634b8edaacf9e2fe5c Mon Sep 17 00:00:00 2001
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Date: Wed, 4 May 2016 14:20:04 +0900
Subject: cmd: replace the cast of the memory access to a fixed bit type in
 itest

This patch fixes a bug that long word(.l) memory access in 'itest'
command reads the 8bytes of the actual memory on 64-bit architecture.
The cast to the memory pointer should use a fixed bit type.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/itest.c b/cmd/itest.c
index fb4d797..60626c7 100644
--- a/cmd/itest.c
+++ b/cmd/itest.c
@@ -65,13 +65,13 @@ static long evalexp(char *s, int w)
 		}
 		switch (w) {
 		case 1:
-			l = (long)(*(unsigned char *)buf);
+			l = (long)(*(u8 *)buf);
 			break;
 		case 2:
-			l = (long)(*(unsigned short *)buf);
+			l = (long)(*(u16 *)buf);
 			break;
 		case 4:
-			l = (long)(*(unsigned long *)buf);
+			l = (long)(*(u32 *)buf);
 			break;
 		}
 		unmap_physmem(buf, w);
-- 
cgit v0.10.2


From 7e6621a1cae2d2442d3d7641ff1df17b3f03ad4b Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Fri, 6 May 2016 07:33:51 +0200
Subject: test/py: fix NameError exception if bdi cmd is not supported

test/py raises an error, if a board has not enabled bdi command

>           pytest.skip('bdinfo command not supported')
E           NameError: global name 'pytest' is not defined

import pytest in test/py/u_boot_utils.py fixes this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 9d243e0..6a6b2ec 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -10,6 +10,7 @@ import os.path
 import pytest
 import sys
 import time
+import pytest
 
 def md5sum_data(data):
     """Calculate the MD5 hash of some data.
-- 
cgit v0.10.2


From 0efe1bcf5c2ce89d7c2467550e2823d7f95733e0 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 6 May 2016 21:01:01 +0200
Subject: efi_loader: Add network access support

We can now successfully boot EFI applications from disk, but users
may want to also run them from a PXE setup.

This patch implements rudimentary network support, allowing a payload
to send and receive network packets.

With this patch, I was able to successfully run grub2 with network
access inside of QEMU's -M xlnx-ep108.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 7f552fc..d3a2331 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -197,6 +197,13 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt)
 #ifdef CONFIG_LCD
 	efi_gop_register();
 #endif
+#ifdef CONFIG_NET
+	void *nethandle = loaded_image_info.device_handle;
+	efi_net_register(&nethandle);
+
+	if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
+		loaded_image_info.device_handle = nethandle;
+#endif
 
 	/* Call our payload! */
 #ifdef DEBUG_EFI
diff --git a/include/efi_api.h b/include/efi_api.h
index 51d7586..20035d7 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -412,4 +412,123 @@ struct efi_gop
 	struct efi_gop_mode *mode;
 };
 
+#define EFI_SIMPLE_NETWORK_GUID \
+	EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \
+		 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_mac_address {
+	char mac_addr[32];
+};
+
+struct efi_ip_address {
+	u8 ip_addr[16];
+};
+
+enum efi_simple_network_state {
+	EFI_NETWORK_STOPPED,
+	EFI_NETWORK_STARTED,
+	EFI_NETWORK_INITIALIZED,
+};
+
+struct efi_simple_network_mode {
+	enum efi_simple_network_state state;
+	u32 hwaddr_size;
+	u32 media_header_size;
+	u32 max_packet_size;
+	u32 nvram_size;
+	u32 nvram_access_size;
+	u32 receive_filter_mask;
+	u32 receive_filter_setting;
+	u32 max_mcast_filter_count;
+	u32 mcast_filter_count;
+	struct efi_mac_address mcast_filter[16];
+	struct efi_mac_address current_address;
+	struct efi_mac_address broadcast_address;
+	struct efi_mac_address permanent_address;
+	u8 if_type;
+	u8 mac_changeable;
+	u8 multitx_supported;
+	u8 media_present_supported;
+	u8 media_present;
+};
+
+#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST               0x01,
+#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST             0x02,
+#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST             0x04,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS           0x08,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10,
+
+struct efi_simple_network
+{
+	u64 revision;
+	efi_status_t (EFIAPI *start)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *stop)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this,
+			ulong extra_rx, ulong extra_tx);
+	efi_status_t (EFIAPI *reset)(struct efi_simple_network *this,
+			int extended_verification);
+	efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this,
+			u32 enable, u32 disable, int reset_mcast_filter,
+			ulong mcast_filter_count,
+			struct efi_mac_address *mcast_filter);
+	efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this,
+			int reset, struct efi_mac_address *new_mac);
+	efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this,
+			int reset, ulong *stat_size, void *stat_table);
+	efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this,
+			int ipv6, struct efi_ip_address *ip,
+			struct efi_mac_address *mac);
+	efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this,
+			int read_write, ulong offset, ulong buffer_size,
+			char *buffer);
+	efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this,
+			u32 *int_status, void **txbuf);
+	efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this,
+			ulong header_size, ulong buffer_size, void *buffer,
+			struct efi_mac_address *src_addr,
+			struct efi_mac_address *dest_addr, u16 *protocol);
+	efi_status_t (EFIAPI *receive)(struct efi_simple_network *this,
+			ulong *header_size, ulong *buffer_size, void *buffer,
+			struct efi_mac_address *src_addr,
+			struct efi_mac_address *dest_addr, u16 *protocol);
+	void (EFIAPI *waitforpacket)(void);
+	struct efi_simple_network_mode *mode;
+};
+
+#define EFI_PXE_GUID \
+	EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
+		 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_pxe_packet {
+	u8 packet[1472];
+};
+
+struct efi_pxe_mode
+{
+	u8 unused[52];
+	struct efi_pxe_packet dhcp_discover;
+	struct efi_pxe_packet dhcp_ack;
+	struct efi_pxe_packet proxy_offer;
+	struct efi_pxe_packet pxe_discover;
+	struct efi_pxe_packet pxe_reply;
+};
+
+struct efi_pxe {
+	u64 rev;
+	void (EFIAPI *start)(void);
+	void (EFIAPI *stop)(void);
+	void (EFIAPI *dhcp)(void);
+	void (EFIAPI *discover)(void);
+	void (EFIAPI *mftp)(void);
+	void (EFIAPI *udpwrite)(void);
+	void (EFIAPI *udpread)(void);
+	void (EFIAPI *setipfilter)(void);
+	void (EFIAPI *arp)(void);
+	void (EFIAPI *setparams)(void);
+	void (EFIAPI *setstationip)(void);
+	void (EFIAPI *setpackets)(void);
+	struct efi_pxe_mode *mode;
+};
+
 #endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 88b8149..8005454 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -91,6 +91,12 @@ extern struct list_head efi_obj_list;
 int efi_disk_register(void);
 /* Called by bootefi to make GOP (graphical) interface available */
 int efi_gop_register(void);
+/* Called by bootefi to make the network interface available */
+int efi_net_register(void **handle);
+
+/* Called by networking code to memorize the dhcp ack package */
+void efi_net_set_dhcp_ack(void *pkt, int len);
+
 /*
  * Stub implementation for a protocol opener that just returns the handle as
  * interface
@@ -157,5 +163,6 @@ static inline void ascii2unicode(u16 *unicode, char *ascii)
 static inline void efi_restore_gd(void) { }
 static inline void efi_set_bootdev(const char *dev, const char *devnr,
 				   const char *path) { }
+static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
 
 #endif
diff --git a/include/net.h b/include/net.h
index 05800c4..5ee5929 100644
--- a/include/net.h
+++ b/include/net.h
@@ -269,7 +269,7 @@ int eth_getenv_enetaddr_by_index(const char *base_name, int index,
 int eth_init(void);			/* Initialize the device */
 int eth_send(void *packet, int length);	   /* Send a packet */
 
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
 int eth_receive(void *packet, int length); /* Receive a packet*/
 extern void (*push_packet)(void *packet, int length);
 #endif
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 83e31f6..2a3849e 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -11,3 +11,4 @@ obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
 obj-y += efi_memory.o
 obj-$(CONFIG_LCD) += efi_gop.o
 obj-$(CONFIG_PARTITIONS) += efi_disk.o
+obj-$(CONFIG_NET) += efi_net.o
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
new file mode 100644
index 0000000..dd3b485
--- /dev/null
+++ b/lib/efi_loader/efi_net.c
@@ -0,0 +1,291 @@
+/*
+ *  EFI application network access support
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <lcd.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
+static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
+static struct efi_pxe_packet *dhcp_ack;
+static bool new_rx_packet;
+static void *new_tx_packet;
+
+struct efi_net_obj {
+	/* Generic EFI object parent class data */
+	struct efi_object parent;
+	/* EFI Interface callback struct for network */
+	struct efi_simple_network net;
+	struct efi_simple_network_mode net_mode;
+	/* Device path to the network adapter */
+	struct efi_device_path_file_path dp[2];
+	/* PXE struct to transmit dhcp data */
+	struct efi_pxe pxe;
+	struct efi_pxe_mode pxe_mode;
+};
+
+static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this)
+{
+	EFI_ENTRY("%p", this);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this)
+{
+	EFI_ENTRY("%p", this);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
+					      ulong extra_rx, ulong extra_tx)
+{
+	EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx);
+
+	eth_init();
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this,
+					 int extended_verification)
+{
+	EFI_ENTRY("%p, %x", this, extended_verification);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
+{
+	EFI_ENTRY("%p", this);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_receive_filters(
+		struct efi_simple_network *this, u32 enable, u32 disable,
+		int reset_mcast_filter, ulong mcast_filter_count,
+		struct efi_mac_address *mcast_filter)
+{
+	EFI_ENTRY("%p, %x, %x, %x, %lx, %p", this, enable, disable,
+		  reset_mcast_filter, mcast_filter_count, mcast_filter);
+
+	/* XXX Do we care? */
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_station_address(
+		struct efi_simple_network *this, int reset,
+		struct efi_mac_address *new_mac)
+{
+	EFI_ENTRY("%p, %x, %p", this, reset, new_mac);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this,
+					      int reset, ulong *stat_size,
+					      void *stat_table)
+{
+	EFI_ENTRY("%p, %x, %p, %p", this, reset, stat_size, stat_table);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this,
+						int ipv6,
+						struct efi_ip_address *ip,
+						struct efi_mac_address *mac)
+{
+	EFI_ENTRY("%p, %x, %p, %p", this, ipv6, ip, mac);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this,
+					  int read_write, ulong offset,
+					  ulong buffer_size, char *buffer)
+{
+	EFI_ENTRY("%p, %x, %lx, %lx, %p", this, read_write, offset, buffer_size,
+		  buffer);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
+					      u32 *int_status, void **txbuf)
+{
+	EFI_ENTRY("%p, %p, %p", this, int_status, txbuf);
+
+	/* We send packets synchronously, so nothing is outstanding */
+	if (int_status)
+		*int_status = 0;
+	if (txbuf)
+		*txbuf = new_tx_packet;
+
+	new_tx_packet = NULL;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_transmit(struct efi_simple_network *this,
+		ulong header_size, ulong buffer_size, void *buffer,
+		struct efi_mac_address *src_addr,
+		struct efi_mac_address *dest_addr, u16 *protocol)
+{
+	EFI_ENTRY("%p, %lx, %lx, %p, %p, %p, %p", this, header_size,
+		  buffer_size, buffer, src_addr, dest_addr, protocol);
+
+	if (header_size) {
+		/* We would need to create the header if header_size != 0 */
+		return EFI_EXIT(EFI_INVALID_PARAMETER);
+	}
+
+	net_send_packet(buffer, buffer_size);
+	new_tx_packet = buffer;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void efi_net_push(void *pkt, int len)
+{
+	new_rx_packet = true;
+}
+
+static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this,
+		ulong *header_size, ulong *buffer_size, void *buffer,
+		struct efi_mac_address *src_addr,
+		struct efi_mac_address *dest_addr, u16 *protocol)
+{
+	EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size,
+		  buffer_size, buffer, src_addr, dest_addr, protocol);
+
+	push_packet = efi_net_push;
+	eth_rx();
+	push_packet = NULL;
+
+	if (!new_rx_packet)
+		return EFI_EXIT(EFI_NOT_READY);
+
+	if (*buffer_size < net_rx_packet_len) {
+		/* Packet doesn't fit, try again with bigger buf */
+		*buffer_size = net_rx_packet_len;
+		return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+	}
+
+	memcpy(buffer, net_rx_packet, net_rx_packet_len);
+	*buffer_size = net_rx_packet_len;
+	new_rx_packet = false;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t efi_net_open_dp(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct efi_simple_network *net = handle;
+	struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+	*protocol_interface = netobj->dp;
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t efi_net_open_pxe(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct efi_simple_network *net = handle;
+	struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+	*protocol_interface = &netobj->pxe;
+
+	return EFI_SUCCESS;
+}
+
+void efi_net_set_dhcp_ack(void *pkt, int len)
+{
+	int maxsize = sizeof(*dhcp_ack);
+
+	if (!dhcp_ack)
+		dhcp_ack = malloc(maxsize);
+
+	memcpy(dhcp_ack, pkt, min(len, maxsize));
+}
+
+/* This gets called from do_bootefi_exec(). */
+int efi_net_register(void **handle)
+{
+	struct efi_net_obj *netobj;
+	struct efi_device_path_file_path dp_net = {
+		.dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+		.dp.length = sizeof(dp_net),
+		.str = { 'N', 'e', 't' },
+	};
+	struct efi_device_path_file_path dp_end = {
+		.dp.type = DEVICE_PATH_TYPE_END,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+		.dp.length = sizeof(dp_end),
+	};
+
+	if (!eth_get_dev()) {
+		/* No eth device active, don't expose any */
+		return 0;
+	}
+
+	/* We only expose the "active" eth device, so one is enough */
+	netobj = calloc(1, sizeof(*netobj));
+
+	/* Fill in object data */
+	netobj->parent.protocols[0].guid = &efi_net_guid;
+	netobj->parent.protocols[0].open = efi_return_handle;
+	netobj->parent.protocols[1].guid = &efi_guid_device_path;
+	netobj->parent.protocols[1].open = efi_net_open_dp;
+	netobj->parent.protocols[2].guid = &efi_pxe_guid;
+	netobj->parent.protocols[2].open = efi_net_open_pxe;
+	netobj->parent.handle = &netobj->net;
+	netobj->net.start = efi_net_start;
+	netobj->net.stop = efi_net_stop;
+	netobj->net.initialize = efi_net_initialize;
+	netobj->net.reset = efi_net_reset;
+	netobj->net.shutdown = efi_net_shutdown;
+	netobj->net.receive_filters = efi_net_receive_filters;
+	netobj->net.station_address = efi_net_station_address;
+	netobj->net.statistics = efi_net_statistics;
+	netobj->net.mcastiptomac = efi_net_mcastiptomac;
+	netobj->net.nvdata = efi_net_nvdata;
+	netobj->net.get_status = efi_net_get_status;
+	netobj->net.transmit = efi_net_transmit;
+	netobj->net.receive = efi_net_receive;
+	netobj->net.mode = &netobj->net_mode;
+	netobj->net_mode.state = EFI_NETWORK_STARTED;
+	netobj->dp[0] = dp_net;
+	netobj->dp[1] = dp_end;
+	memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
+	netobj->net_mode.max_packet_size = PKTSIZE;
+
+	netobj->pxe.mode = &netobj->pxe_mode;
+	if (dhcp_ack)
+		netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+
+	/* Hook net up to the device list */
+	list_add_tail(&netobj->parent.link, &efi_obj_list);
+
+	if (handle)
+		*handle = &netobj->net;
+
+	return 0;
+}
diff --git a/net/bootp.c b/net/bootp.c
index d7852db..d91b307 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <efi_loader.h>
 #include <net.h>
 #include <net/tftp.h>
 #include "bootp.h"
@@ -1025,6 +1026,7 @@ static void dhcp_handler(uchar *pkt, unsigned dest, struct in_addr sip,
 			    strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
 #endif	/* CONFIG_SYS_BOOTFILE_PREFIX */
 			dhcp_packet_process_options(bp);
+			efi_net_set_dhcp_ack(pkt, len);
 
 			debug("TRANSITIONING TO REQUESTING STATE\n");
 			dhcp_state = REQUESTING;
diff --git a/net/net.c b/net/net.c
index fba111e..1e1d23d 100644
--- a/net/net.c
+++ b/net/net.c
@@ -146,7 +146,7 @@ static unsigned	net_ip_id;
 /* Ethernet bcast address */
 const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 const u8 net_null_ethaddr[6];
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
 void (*push_packet)(void *, int len) = 0;
 #endif
 /* Network loop state */
@@ -1054,7 +1054,7 @@ void net_process_received_packet(uchar *in_packet, int len)
 	if (len < ETHER_HDR_SIZE)
 		return;
 
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
 	if (push_packet) {
 		(*push_packet)(in_packet, len);
 		return;
diff --git a/net/tftp.c b/net/tftp.c
index f2889fe..ced45ec 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <efi_loader.h>
 #include <mapmem.h>
 #include <net.h>
 #include <net/tftp.h>
@@ -804,6 +805,7 @@ void tftp_start(enum proto_t protocol)
 		printf("Load address: 0x%lx\n", load_addr);
 		puts("Loading: *\b");
 		tftp_state = STATE_SEND_RRQ;
+		efi_set_bootdev("Net", "", tftp_filename);
 	}
 
 	time_start = get_timer(0);
-- 
cgit v0.10.2


From 4570a993d5f330ab05081f7b1070da9bcde9289e Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 6 May 2016 21:01:02 +0200
Subject: bootp: Move vendor class identifier set to function

Both the dhcp as well as the bootp case add vendor class identifier
parameters into their packets. Let's move that into a separate function
to make overlaying easier.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/net/bootp.c b/net/bootp.c
index d91b307..d718e35 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -411,6 +411,17 @@ static void bootp_timeout_handler(void)
 		e += vci_strlen;				\
 	} while (0)
 
+static u8 *add_vci(u8 *e)
+{
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
+	put_vci(e, CONFIG_SPL_NET_VCI_STRING);
+#elif defined(CONFIG_BOOTP_VCI_STRING)
+	put_vci(e, CONFIG_BOOTP_VCI_STRING);
+#endif
+
+	return e;
+}
+
 /*
  *	Initialize BOOTP extension fields in the request.
  */
@@ -508,11 +519,7 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 	}
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
-	put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#elif defined(CONFIG_BOOTP_VCI_STRING)
-	put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
+	e = add_vci(e);
 
 #if defined(CONFIG_BOOTP_VENDOREX)
 	x = dhcp_vendorex_prep(e);
@@ -598,14 +605,7 @@ static int bootp_extended(u8 *e)
 	*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
 #endif
 
-#if defined(CONFIG_BOOTP_VCI_STRING) || \
-	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING))
-#ifdef CONFIG_SPL_BUILD
-	put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#else
-	put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
-#endif
+	add_vci(e);
 
 #if defined(CONFIG_BOOTP_SUBNETMASK)
 	*e++ = 1;		/* Subnet mask request */
-- 
cgit v0.10.2


From 0dac6b4e850cdd934f9b04cecc79fc395127ab29 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 6 May 2016 21:01:03 +0200
Subject: net: Move the VCI and client arch values to Kconfig

We have a bunch of boards that define their vendor class identifier and
client archs in the board files or in the distro config. Move everything
to the generic Kconfig options.

We're missing the distinction between i386 and x86_64, as I couldn't find
any config variable that would tell us the difference. Is that really important
to people? I guess not, so I left it out.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index f9b4eac..30a6381 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -25,3 +25,4 @@ CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU"
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 728fa25..a095b8a 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -28,3 +28,4 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU"
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index b7078e0..cb33f60 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -22,3 +22,4 @@ CONFIG_DEBUG_UART_BASE=0x87e024000000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_REGEX=y
+CONFIG_BOOTP_VCI_STRING="Diagnostics"
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 989f068..c0708b2 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index c70851f..5af9f58 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index b0a2f67..379dff2 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 2f141dd..c39faaa 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2"
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index c495ee5..e71d45e 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2"
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index fcd6e26..20100a3 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4"
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 766a212..dfc2cbc 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -20,27 +20,6 @@
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
 
-#if defined(__arm__) || defined(__aarch64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
-#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING         "U-Boot.armv7"
-#endif
-#elif defined(__aarch64__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING         "U-Boot.armv8"
-#endif
-#else
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING         "U-Boot.arm"
-#endif
-#endif
-#elif defined(__i386__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x0
-#elif defined(__x86_64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x9
-#endif
-
 #ifdef CONFIG_ARM64
 #define CONFIG_CMD_BOOTI
 #endif
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
index f4ace85..16e37bf 100644
--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@@ -10,7 +10,6 @@
 #include "ls2080a_common.h"
 
 #define CONFIG_IDENT_STRING		" LS2080A-EMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.LS2080A-EMU"
 
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index bc0d678..7563aaf 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -10,7 +10,6 @@
 #include "ls2080a_common.h"
 
 #define CONFIG_IDENT_STRING		" LS2080A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.LS2080A-SIMU"
 
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 7c35d8c..e43a7fd 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -17,7 +17,6 @@
 
 #define CONFIG_IDENT_STRING	\
 	" for Cavium Thunder CN88XX ARM v8 Multi-Core"
-#define CONFIG_BOOTP_VCI_STRING		"Diagnostics"
 
 #define MEM_BASE			0x00500000
 
@@ -62,7 +61,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		(MEM_BASE)
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 1b5fc2e..6a37582 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -23,7 +23,6 @@
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.armv8.vexpress_aemv8a"
 
 /* Link Definitions */
 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
@@ -146,7 +145,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index 883e58e..b509a9c 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -12,7 +12,6 @@
 #define __VEXPRESS_CA15X2_TC2_h
 
 #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING     "U-Boot.armv7.vexpress_ca15x2_tc2"
 #include "vexpress_common.h"
 
 #define CONFIG_SYSFLAGS_ADDR	0x1c010030
diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h
index 4385027..20b92dc 100644
--- a/include/configs/vexpress_ca5x2.h
+++ b/include/configs/vexpress_ca5x2.h
@@ -12,7 +12,6 @@
 #define __VEXPRESS_CA5X2_h
 
 #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING     "U-Boot.armv7.vexpress_ca5x2"
 #include "vexpress_common.h"
 
 #endif /* __VEXPRESS_CA5X2_h */
diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h
index 99be50a..993398c 100644
--- a/include/configs/vexpress_ca9x4.h
+++ b/include/configs/vexpress_ca9x4.h
@@ -12,7 +12,6 @@
 #define __VEXPRESS_CA9X4_H
 
 #define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING     "U-Boot.armv7.vexpress_ca9x4"
 #include "vexpress_common.h"
 
 #endif /* VEXPRESS_CA9X4_H */
diff --git a/net/Kconfig b/net/Kconfig
index a44a783..64fd0f9 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -32,4 +32,16 @@ config NET_TFTP_VARS
 	  If unset, timeout and maximum are hard-defined as 1 second
 	  and 10 timouts per TFTP transfer.
 
+config BOOTP_PXE_CLIENTARCH
+	hex
+        default 0x100 if ARM
+        default 0 if X86
+
+config BOOTP_VCI_STRING
+	string
+	default "U-Boot.armv7" if CPU_V7 || CPU_V7M
+	default "U-Boot.armv8" if ARM64
+	default "U-Boot.arm" if ARM
+	default "U-Boot"
+
 endif   # if NET
-- 
cgit v0.10.2


From 90b7fc924adfe7f1745dcf6a1dabb9e77aa762a7 Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:24:55 +0100
Subject: net: designware: support phy reset device-tree bindings

Add support for the snps,reset-gpio, snps,reset-active-low (optional) and
snps,reset-delays-us device-tree bindings. The combination of these
three define how the PHY should be reset to ensure it's in a sane state.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ca58f34..14dd7b8 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -24,7 +24,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
+#ifdef CONFIG_DM_ETH
+	struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
 	struct eth_mac_regs *mac_p = bus->priv;
+#endif
 	ulong start;
 	u16 miiaddr;
 	int timeout = CONFIG_MDIO_TIMEOUT;
@@ -47,7 +52,12 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 			u16 val)
 {
+#ifdef CONFIG_DM_ETH
+	struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
 	struct eth_mac_regs *mac_p = bus->priv;
+#endif
 	ulong start;
 	u16 miiaddr;
 	int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
@@ -70,7 +80,41 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	return ret;
 }
 
-static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
+#if CONFIG_DM_ETH
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+	struct udevice *dev = bus->priv;
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	struct dw_eth_pdata *pdata = dev_get_platdata(dev);
+	int ret;
+
+	if (!dm_gpio_is_valid(&priv->reset_gpio))
+		return 0;
+
+	/* reset the phy */
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[0]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[1]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[2]);
+
+	return 0;
+}
+#endif
+
+static int dw_mdio_init(const char *name, void *priv)
 {
 	struct mii_dev *bus = mdio_alloc();
 
@@ -82,8 +126,11 @@ static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
 	bus->read = dw_mdio_read;
 	bus->write = dw_mdio_write;
 	snprintf(bus->name, sizeof(bus->name), "%s", name);
+#ifdef CONFIG_DM_ETH
+	bus->reset = dw_mdio_reset;
+#endif
 
-	bus->priv = (void *)mac_regs_p;
+	bus->priv = priv;
 
 	return mdio_register(bus);
 }
@@ -606,7 +653,7 @@ static int designware_eth_probe(struct udevice *dev)
 	priv->interface = pdata->phy_interface;
 	priv->max_speed = pdata->max_speed;
 
-	dw_mdio_init(dev->name, priv->mac_regs_p);
+	dw_mdio_init(dev->name, dev);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
 
 	ret = dw_phy_init(priv, dev);
@@ -637,9 +684,13 @@ static const struct eth_ops designware_eth_ops = {
 
 static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = &dw_pdata->eth_pdata;
 	const char *phy_mode;
 	const fdt32_t *cell;
+	int reset_flags = GPIOD_IS_OUT;
+	int ret = 0;
 
 	pdata->iobase = dev_get_addr(dev);
 	pdata->phy_interface = -1;
@@ -656,7 +707,20 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	if (cell)
 		pdata->max_speed = fdt32_to_cpu(*cell);
 
-	return 0;
+	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+			    "snps,reset-active-low"))
+		reset_flags |= GPIOD_ACTIVE_LOW;
+
+	ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+		&priv->reset_gpio, reset_flags);
+	if (ret == 0) {
+		ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+			"snps,reset-delays-us", dw_pdata->reset_delays, 3);
+	} else if (ret == -ENOENT) {
+		ret = 0;
+	}
+
+	return ret;
 }
 
 static const struct udevice_id designware_eth_ids[] = {
@@ -675,7 +739,7 @@ U_BOOT_DRIVER(eth_designware) = {
 	.remove	= designware_eth_remove,
 	.ops	= &designware_eth_ops,
 	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
-	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
 };
 
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ed6344c..04a45e0 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -8,6 +8,8 @@
 #ifndef _DW_ETH_H
 #define _DW_ETH_H
 
+#include <asm/gpio.h>
+
 #define CONFIG_TX_DESCR_NUM	16
 #define CONFIG_RX_DESCR_NUM	16
 #define CONFIG_ETH_BUFSIZE	2048
@@ -232,8 +234,16 @@ struct dw_eth_dev {
 #ifndef CONFIG_DM_ETH
 	struct eth_device *dev;
 #endif
+	struct gpio_desc reset_gpio;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 };
 
+#ifdef CONFIG_DM_ETH
+struct dw_eth_pdata {
+	struct eth_pdata eth_pdata;
+	u32 reset_delays[3];
+};
+#endif
+
 #endif
-- 
cgit v0.10.2


From 70f7a2cdac6a7f75f27848d689a13ca244b0792b Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:24:58 +0100
Subject: rockchip: rk3288: pinctrl: support more pins

The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size
of the cell array to accomedate that, otherwise only the first 10 get
configured.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 7c769bd..1fa1daa 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -623,7 +623,7 @@ static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 {
 	const void *blob = gd->fdt_blob;
 	int pcfg_node, ret, flags, count, i;
-	u32 cell[40], *ptr;
+	u32 cell[60], *ptr;
 
 	debug("%s: %s %s\n", __func__, dev->name, config->name);
 	ret = fdtdec_get_int_array_count(blob, config->of_offset,
-- 
cgit v0.10.2


From 0aefc0b0c7eba963c88eca893a546f3e786615ac Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:24:59 +0100
Subject: rockchip: rk3288: Add clock support for the gmac ethernet interface

Setup the clocks for the gmac ethernet interface. This assumes the mac
clock is fed by an external clock which is common on RK3288 based
devices.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d2690c7..8a8ca9c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -90,6 +90,23 @@ enum {
 	SDIO0_DIV_MASK		= 0x3f,
 };
 
+/* CRU_CLKSEL21_CON */
+enum {
+	MAC_DIV_CON_SHIFT = 0xf,
+	MAC_DIV_CON_MASK = 0x1f,
+
+	RMII_EXTCLK_SHIFT = 4,
+	RMII_EXTCLK_MASK = 1,
+	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+	RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+	EMAC_PLL_SHIFT = 0,
+	EMAC_PLL_MASK = 0x3,
+	EMAC_PLL_SELECT_NEW = 0x0,
+	EMAC_PLL_SELECT_CODEC = 0x1,
+	EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
 /* CRU_CLKSEL25_CON */
 enum {
 	SPI1_PLL_SHIFT		= 0xf,
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 2a85e93..a110a1c 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -326,6 +326,17 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 	return 0;
 }
 
+static int rockchip_mac_set_clk(struct rk3288_cru *cru,
+				  int periph, uint freq)
+{
+	/* Assuming mac_clk is fed by an external clock */
+	rk_clrsetreg(&cru->cru_clksel_con[21],
+		     RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
+		     RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+
+	 return 0;
+}
+
 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 				int periph, unsigned int rate_hz)
 {
@@ -759,6 +770,9 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 		new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
 		break;
 #ifndef CONFIG_SPL_BUILD
+	case SCLK_MAC:
+		new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
+		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
 		new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
-- 
cgit v0.10.2


From 2f3920047ae7d70fef7bb9a0c7c5c0eee677d9f7 Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:25:00 +0100
Subject: rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3

Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various
GMAC related fields.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 0117a17..aaffd19 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -718,6 +718,40 @@ enum {
 	MSCH0_MAINPARTIALPOP_MASK = 1,
 };
 
+/* GRF_SOC_CON1 */
+enum {
+	RMII_MODE_SHIFT = 0xe,
+	RMII_MODE_MASK = 1,
+	RMII_MODE = 1,
+
+	GMAC_CLK_SEL_SHIFT	= 0xc,
+	GMAC_CLK_SEL_MASK	= 3,
+	GMAC_CLK_SEL_125M	= 0,
+	GMAC_CLK_SEL_25M	= 0x3,
+	GMAC_CLK_SEL_2_5M	= 0x2,
+
+	RMII_CLK_SEL_SHIFT	= 0xb,
+	RMII_CLK_SEL_MASK	= 1,
+	RMII_CLK_SEL_2_5M	= 0,
+	RMII_CLK_SEL_25M,
+
+	GMAC_SPEED_SHIFT	= 0xa,
+	GMAC_SPEED_MASK		= 1,
+	GMAC_SPEED_10M		= 0,
+	GMAC_SPEED_100M,
+
+	GMAC_FLOWCTRL_SHIFT	= 0x9,
+	GMAC_FLOWCTRL_MASK	= 1,
+
+	GMAC_PHY_INTF_SEL_SHIFT	= 0x6,
+	GMAC_PHY_INTF_SEL_MASK	= 0x7,
+	GMAC_PHY_INTF_SEL_RGMII	= 0x1,
+	GMAC_PHY_INTF_SEL_RMII	= 0x4,
+
+	HOST_REMAP_SHIFT	= 0x5,
+	HOST_REMAP_MASK		= 1
+};
+
 /* GRF_SOC_CON2 */
 enum {
 	UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
@@ -765,4 +799,23 @@ enum {
 	PWM_PWM			= 0,
 };
 
+/* GRF_SOC_CON3 */
+enum {
+	RXCLK_DLY_ENA_GMAC_SHIFT	= 0xf,
+	RXCLK_DLY_ENA_GMAC_MASK		= 1,
+	RXCLK_DLY_ENA_GMAC_DISABLE	= 0,
+	RXCLK_DLY_ENA_GMAC_ENABLE,
+
+	TXCLK_DLY_ENA_GMAC_SHIFT	= 0xe,
+	TXCLK_DLY_ENA_GMAC_MASK		= 1,
+	TXCLK_DLY_ENA_GMAC_DISABLE	= 0,
+	TXCLK_DLY_ENA_GMAC_ENABLE,
+
+	CLK_RX_DL_CFG_GMAC_SHIFT	= 0x7,
+	CLK_RX_DL_CFG_GMAC_MASK		= 0x7f,
+
+	CLK_TX_DL_CFG_GMAC_SHIFT	= 0x0,
+	CLK_TX_DL_CFG_GMAC_MASK		= 0x7f,
+};
+
 #endif
-- 
cgit v0.10.2


From 1c09a7fb9831278849eae4dfb153ddd570eb8c4c Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:25:02 +0100
Subject: rockchip: rk3288-firefly: Add gmac definition

Add a definition for the gmac interface to the firefly device-tree.
Copied verbatim from the linux kernel.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
index 5aec1b8..072eaa6 100644
--- a/arch/arm/dts/rk3288-firefly.dtsi
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -146,6 +146,22 @@
 	status = "okay";
 };
 
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
 &hdmi {
 	ddc-i2c-bus = <&i2c5>;
 	status = "okay";
-- 
cgit v0.10.2


From 2ed6dc83380ea2f49ec09556c14c6eddd3f5c27a Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:25:03 +0100
Subject: rockchip: rock2: dts: use status = "okay" not ok

u-boot only recognize okay to enable a node (Linux seems to be more
lenient here). So use okay instead.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 8d7446f..34073c9 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -111,7 +111,7 @@
 };
 
 &gmac {
-	status = "ok";
+	status = "okay";
 };
 
 &hdmi {
-- 
cgit v0.10.2


From 9217d93bc45668815ebaab0ad9280ace166b7348 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:02:59 -0600
Subject: rockchip: Check image name for the rksd image

We need a correct name (rk3288, rk3036) so check this to avoid a crash
later.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/rkimage.c b/tools/rkimage.c
index f9fdcfa..ef31cb6 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -13,11 +13,6 @@
 
 static uint32_t header;
 
-static int rkimage_check_params(struct image_tool_params *params)
-{
-	return 0;
-}
-
 static int rkimage_verify_header(unsigned char *buf, int size,
 				 struct image_tool_params *params)
 {
@@ -56,7 +51,7 @@ U_BOOT_IMAGE_TYPE(
 	"Rockchip Boot Image support",
 	4,
 	&header,
-	rkimage_check_params,
+	rkcommon_check_params,
 	rkimage_verify_header,
 	rkimage_print_header,
 	rkimage_set_header,
-- 
cgit v0.10.2


From 56d6977121732e4efe6cd48872e874e40f4916a0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:00 -0600
Subject: rockchip: Drop unnecessary SPL properties

While we consider whether to drop use of DT in SPL, remove some unwanted
properties. This reduces SPL size by about 250 bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0cbc539..4af9120 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -28,7 +28,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
-- 
cgit v0.10.2


From b55e04a021ee256aaba118a547f13a4722538623 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:01 -0600
Subject: rockchip: video: Flush the cache when the display is updated

Enable this option to correct display artifacts when a write-back cache is
in use.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index a54af17..db09d9a 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -326,6 +326,7 @@ static int rk_vop_probe(struct udevice *dev)
 		if (!ret)
 			break;
 	}
+	video_set_flush_dcache(dev, 1);
 
 	return ret;
 }
-- 
cgit v0.10.2


From 3c2d75269cb4c94c445be2f77adcbca4add70893 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:02 -0600
Subject: rockchip: Drop SPL GPIO support for rk3288

This is not currently used and saves a little over 1KB of SPL image size.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 8a81397..9d50d83 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -69,7 +69,6 @@
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
 
 #define CONFIG_SPL_PINCTRL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_RAM_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 
-- 
cgit v0.10.2


From 5461acba44b7da8292ba2cbeaf961279d9b8c187 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:03 -0600
Subject: dm: env: mmc: Convert env_mmc to support CONFIG_BLK

Update the MMC environment code so that it works with driver-model enabled
for block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/env_mmc.c b/common/env_mmc.c
index c7fef18..16f6a17 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -128,12 +128,12 @@ static inline int write_env(struct mmc *mmc, unsigned long size,
 			    unsigned long offset, const void *buffer)
 {
 	uint blk_start, blk_cnt, n;
+	struct blk_desc *desc = mmc_get_blk_desc(mmc);
 
 	blk_start	= ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
 	blk_cnt		= ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
 
-	n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
-					blk_cnt, (u_char *)buffer);
+	n = blk_dwrite(desc, blk_start, blk_cnt, (u_char *)buffer);
 
 	return (n == blk_cnt) ? 0 : -1;
 }
@@ -197,12 +197,12 @@ static inline int read_env(struct mmc *mmc, unsigned long size,
 			   unsigned long offset, const void *buffer)
 {
 	uint blk_start, blk_cnt, n;
+	struct blk_desc *desc = mmc_get_blk_desc(mmc);
 
 	blk_start	= ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 	blk_cnt		= ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
 
-	n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
-				      (uchar *)buffer);
+	n = blk_dread(desc, blk_start, blk_cnt, (uchar *)buffer);
 
 	return (n == blk_cnt) ? 0 : -1;
 }
-- 
cgit v0.10.2


From 19d2e34237d5c077b2dc395522a1559e4b5c62df Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:04 -0600
Subject: dm: mmc: Convert sdhci to support CONFIG_BLK

Update sdhci.c so that it works with driver model enabled for block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index ef7e615..5c71ab8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -137,7 +137,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	int trans_bytes = 0, is_aligned = 1;
 	u32 mask, flags, mode;
 	unsigned int time = 0, start_addr = 0;
-	int mmc_dev = mmc->block_dev.devnum;
+	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 	unsigned start = get_timer(0);
 
 	/* Timeout unit - ms */
-- 
cgit v0.10.2


From 487d756f78629f5e9465c7ace2c14ef51401bc3b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:05 -0600
Subject: dm: efi: Update for CONFIG_BLK

This code does not currently build with driver model enabled for block
devices. Update it to correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexander Graf <agraf@suse.de>

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 88b8149..44a950f 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -134,7 +134,7 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 int efi_memory_init(void);
 
 /* Convert strings from normal C strings to uEFI strings */
-static inline void ascii2unicode(u16 *unicode, char *ascii)
+static inline void ascii2unicode(u16 *unicode, const char *ascii)
 {
 	while (*ascii)
 		*(unicode++) = *(ascii++);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 075fd34..3095bcf 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <blk.h>
+#include <dm.h>
 #include <efi_loader.h>
 #include <inttypes.h>
 #include <part.h>
@@ -96,9 +97,9 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
 	if (direction == EFI_DISK_READ)
-		n = desc->block_read(desc, lba, blocks, buffer);
+		n = blk_dread(desc, lba, blocks, buffer);
 	else
-		n = desc->block_write(desc, lba, blocks, buffer);
+		n = blk_dwrite(desc, lba, blocks, buffer);
 
 	/* We don't do interrupts, so check for timers cooperatively */
 	efi_timer_check();
@@ -142,8 +143,8 @@ static const struct efi_block_io block_io_disk_template = {
 	.flush_blocks = &efi_disk_flush_blocks,
 };
 
-static void efi_disk_add_dev(char *name,
-			     const struct blk_driver *cur_drvr,
+static void efi_disk_add_dev(const char *name,
+			     const char *if_typename,
 			     const struct blk_desc *desc,
 			     int dev_index,
 			     lbaint_t offset)
@@ -161,7 +162,7 @@ static void efi_disk_add_dev(char *name,
 	diskobj->parent.protocols[1].open = efi_disk_open_dp;
 	diskobj->parent.handle = diskobj;
 	diskobj->ops = block_io_disk_template;
-	diskobj->ifname = cur_drvr->if_typename;
+	diskobj->ifname = if_typename;
 	diskobj->dev_index = dev_index;
 	diskobj->offset = offset;
 
@@ -190,7 +191,7 @@ static void efi_disk_add_dev(char *name,
 }
 
 static int efi_disk_create_eltorito(struct blk_desc *desc,
-				    const struct blk_driver *cur_drvr,
+				    const char *if_typename,
 				    int diskid)
 {
 	int disks = 0;
@@ -203,9 +204,10 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
 		return 0;
 
 	while (!part_get_info(desc, part, &info)) {
-		snprintf(devname, sizeof(devname), "%s%d:%d",
-			 cur_drvr->if_typename, diskid, part);
-		efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
+		snprintf(devname, sizeof(devname), "%s%d:%d", if_typename,
+			 diskid, part);
+		efi_disk_add_dev(devname, if_typename, desc, diskid,
+				 info.start);
 		part++;
 		disks++;
 	}
@@ -219,21 +221,49 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
  * EFI payload, we scan through all of the potentially available ones and
  * store them in our object pool.
  *
+ * TODO(sjg@chromium.org): Actually with CONFIG_BLK, U-Boot does have this.
+ * Consider converting the code to look up devices as needed. The EFI device
+ * could be a child of the UCLASS_BLK block device, perhaps.
+ *
  * This gets called from do_bootefi_exec().
  */
 int efi_disk_register(void)
 {
-	const struct blk_driver *cur_drvr;
-	int i, if_type;
 	int disks = 0;
+#ifdef CONFIG_BLK
+	struct udevice *dev;
+
+	for (uclass_first_device(UCLASS_BLK, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+		const char *if_typename = dev->driver->name;
+
+		printf("Scanning disk %s...\n", dev->name);
+		efi_disk_add_dev(dev->name, if_typename, desc, desc->devnum, 0);
+		disks++;
+
+		/*
+		* El Torito images show up as block devices in an EFI world,
+		* so let's create them here
+		*/
+		disks += efi_disk_create_eltorito(desc, if_typename,
+						  desc->devnum);
+	}
+#else
+	int i, if_type;
 
 	/* Search for all available disk devices */
 	for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+		const struct blk_driver *cur_drvr;
+		const char *if_typename;
+
 		cur_drvr = blk_driver_lookup_type(if_type);
 		if (!cur_drvr)
 			continue;
 
-		printf("Scanning disks on %s...\n", cur_drvr->if_typename);
+		if_typename = cur_drvr->if_typename;
+		printf("Scanning disks on %s...\n", if_typename);
 		for (i = 0; i < 4; i++) {
 			struct blk_desc *desc;
 			char devname[32] = { 0 }; /* dp->str is u16[32] long */
@@ -245,17 +275,18 @@ int efi_disk_register(void)
 				continue;
 
 			snprintf(devname, sizeof(devname), "%s%d",
-				 cur_drvr->if_typename, i);
-			efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
+				 if_typename, i);
+			efi_disk_add_dev(devname, if_typename, desc, i, 0);
 			disks++;
 
 			/*
 			 * El Torito images show up as block devices
 			 * in an EFI world, so let's create them here
 			 */
-			disks += efi_disk_create_eltorito(desc, cur_drvr, i);
+			disks += efi_disk_create_eltorito(desc, if_typename, i);
 		}
 	}
+#endif
 	printf("Found %d disks\n", disks);
 
 	return 0;
-- 
cgit v0.10.2


From ef5609c33fc6a8323613a296f08c8efa3161d77f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:06 -0600
Subject: dm: mmc: spl: Add support for CONFIG_BLK

Allow driver model to be used for block devices in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 5676acd..6adfc9b 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -34,9 +34,8 @@ static int mmc_load_legacy(struct mmc *mmc, ulong sector,
 			     mmc->read_bl_len;
 
 	/* Read the header too to avoid extra memcpy */
-	count = mmc->block_dev.block_read(&mmc->block_dev, sector,
-					  image_size_sectors,
-					  (void *)(ulong)spl_image.load_addr);
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
+			  (void *)(ulong)spl_image.load_addr);
 	debug("read %x sectors to %x\n", image_size_sectors,
 	      spl_image.load_addr);
 	if (count != image_size_sectors)
@@ -50,7 +49,7 @@ static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
 {
 	struct mmc *mmc = load->dev;
 
-	return mmc->block_dev.block_read(&mmc->block_dev, sector, count, buf);
+	return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
 }
 
 static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
@@ -63,7 +62,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 					 sizeof(struct image_header));
 
 	/* read image header to find the image size & load address */
-	count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
 	debug("hdr read sector %lx, count=%lu\n", sector, count);
 	if (count == 0) {
 		ret = -EIO;
-- 
cgit v0.10.2


From 5e6ff810c3bfeec2e81cc1117a2c1514416d947d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:07 -0600
Subject: dm: mmc: dwmmc: Support CONFIG_BLK

Add support for using driver model for block devices in this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7329f40..74a2663 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -454,27 +454,40 @@ static const struct mmc_ops dwmci_ops = {
 	.init		= dwmci_init,
 };
 
-int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+		     uint caps, u32 max_clk, u32 min_clk)
 {
-	host->cfg.name = host->name;
-	host->cfg.ops = &dwmci_ops;
-	host->cfg.f_min = min_clk;
-	host->cfg.f_max = max_clk;
+	cfg->name = name;
+	cfg->ops = &dwmci_ops;
+	cfg->f_min = min_clk;
+	cfg->f_max = max_clk;
 
-	host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 
-	host->cfg.host_caps = host->caps;
+	cfg->host_caps = caps;
 
-	if (host->buswidth == 8) {
-		host->cfg.host_caps |= MMC_MODE_8BIT;
-		host->cfg.host_caps &= ~MMC_MODE_4BIT;
+	if (buswidth == 8) {
+		cfg->host_caps |= MMC_MODE_8BIT;
+		cfg->host_caps &= ~MMC_MODE_4BIT;
 	} else {
-		host->cfg.host_caps |= MMC_MODE_4BIT;
-		host->cfg.host_caps &= ~MMC_MODE_8BIT;
+		cfg->host_caps |= MMC_MODE_4BIT;
+		cfg->host_caps &= ~MMC_MODE_8BIT;
 	}
-	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+	cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
 
-	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+#ifdef CONFIG_BLK
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+	return mmc_bind(dev, mmc, cfg);
+}
+#else
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+{
+	dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
+			max_clk, min_clk);
 
 	host->mmc = mmc_create(&host->cfg, host);
 	if (host->mmc == NULL)
@@ -482,3 +495,4 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 
 	return 0;
 }
+#endif
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 05b0817..335af51 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -180,8 +180,9 @@ struct dwmci_host {
 	 * @freq:	Frequency the host is trying to achieve
 	 */
 	unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
-
+#ifndef CONFIG_BLK
 	struct mmc_config cfg;
+#endif
 
 	/* use fifo mode to read and write data */
 	bool fifo_mode;
@@ -223,5 +224,9 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
 	return readb(host->ioaddr + reg);
 }
 
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+		     uint caps, u32 max_clk, u32 min_clk);
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 #endif	/* __DWMMC_HW_H */
-- 
cgit v0.10.2


From f6e41d17ababd72479d2dfdb40be63beb359de1d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:08 -0600
Subject: dm: rockchip: mmc: Allow use of CONFIG_BLK

Allow driver model to be used for block devices in the rockchip mmc driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 0a261c5..750ab9f 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -18,6 +18,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct rockchip_mmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
 struct rockchip_dwmmc_priv {
 	struct udevice *clk;
 	int periph;
@@ -62,6 +67,9 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 
 static int rockchip_dwmmc_probe(struct udevice *dev)
 {
+#ifdef CONFIG_BLK
+	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+#endif
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
@@ -100,16 +108,37 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 			return ret;
 	}
 #endif
+#ifdef CONFIG_BLK
+	dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
+			minmax[1], minmax[0]);
+	host->mmc = &plat->mmc;
+#else
 	ret = add_dwmci(host, minmax[1], minmax[0]);
 	if (ret)
 		return ret;
 
+#endif
+	host->mmc->priv = &priv->host;
 	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
 
 	return 0;
 }
 
+static int rockchip_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
 static const struct udevice_id rockchip_dwmmc_ids[] = {
 	{ .compatible = "rockchip,rk3288-dw-mshc" },
 	{ }
@@ -120,8 +149,10 @@ U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= rockchip_dwmmc_ids,
 	.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+	.bind		= rockchip_dwmmc_bind,
 	.probe		= rockchip_dwmmc_probe,
 	.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
+	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
 };
 
 #ifdef CONFIG_PWRSEQ
-- 
cgit v0.10.2


From e419a3ec1aa3f094268976b6c10e9b636a97c64d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:09 -0600
Subject: dm: mmc: Fix up mmc_bread/bwrite() prototypes for SPL

When these functions are not compiled in, we still need to declare the
correct function signature to avoid a build warnings in SPL. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 27b9e5f..9f0d5c2 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -37,6 +37,19 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 
 /* SPL will never write or erase, declare dummies to reduce code size. */
 
+#ifdef CONFIG_BLK
+static inline unsigned long mmc_berase(struct udevice *dev,
+				       lbaint_t start, lbaint_t blkcnt)
+{
+	return 0;
+}
+
+static inline ulong mmc_bwrite(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *src)
+{
+	return 0;
+}
+#else
 static inline unsigned long mmc_berase(struct blk_desc *block_dev,
 				       lbaint_t start, lbaint_t blkcnt)
 {
@@ -48,6 +61,7 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
 {
 	return 0;
 }
+#endif
 
 #endif /* CONFIG_SPL_BUILD */
 
-- 
cgit v0.10.2


From e6c28073f94be357d8e55beefd67ccf0c925c90e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:10 -0600
Subject: dm: mmc: Use cfg directly in mmc_bind()

This small change tidies up the code slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b7c936c..94f19ad 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1557,7 +1557,7 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 	bdesc->removable = 1;
 
 	/* setup initial part type */
-	bdesc->part_type = mmc->cfg->part_type;
+	bdesc->part_type = cfg->part_type;
 	mmc->dev = dev;
 
 	return 0;
-- 
cgit v0.10.2


From 3c27b6ad540828c44a62d209030df5ba86896df0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 14:03:11 -0600
Subject: dm: rockchip: Enable CONFIG_BLK

Enable CONFIG_BLK to move to using driver model for block devices. This
affects MMC booting in SPL, as well as MMC access in U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d3bddb7..2a8afac 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -41,6 +41,9 @@ config DM_I2C
 config DM_GPIO
 	default y
 
+config BLK
+	default y
+
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 endif
-- 
cgit v0.10.2


From fa96f37ec5835aa685f7beb0af4fef12e9001027 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 6 May 2016 21:01:04 +0200
Subject: net: Fix client identifiers for ARM

There are client identifiers specifically reserved for ARM U-Boot
according to http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml#processor-architecture.

So let's actually make use of them rather than the bogus 0x100 that
we emitted so far.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Drop the Xilinx define to 0x100 as it's not the correct value to
use].
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index b2fa164..ffb6b34 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -80,7 +80,6 @@
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
 
 /* Diff from config_distro_defaults.h */
 #define CONFIG_SUPPORT_RAW_INITRD
diff --git a/net/Kconfig b/net/Kconfig
index 64fd0f9..414c549 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -34,7 +34,8 @@ config NET_TFTP_VARS
 
 config BOOTP_PXE_CLIENTARCH
 	hex
-        default 0x100 if ARM
+        default 0x16 if ARM64
+        default 0x15 if ARM
         default 0 if X86
 
 config BOOTP_VCI_STRING
-- 
cgit v0.10.2


From 210be5c4cb0e1bf22bd0e0438cc8e52e3ccbcf5e Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 6 May 2016 21:01:05 +0200
Subject: net: Move CONFIG_SPL_NET_VCI_STRING into Kconfig

This patch also adds the SPL time VCI string into Kconfig.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 62f26b5..2430381 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -42,3 +42,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index f230671..76a004e 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 3fbc07b..99fc555 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -35,3 +35,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 65d88d8..d5aa3a2 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index eee5e9b..cba5e84 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index c227ef4..3cd40e9 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -25,3 +25,4 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index f098fd3..ef4c248 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -48,3 +48,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_DM_ETH=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 8be0412..8c1e09a 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -52,3 +52,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_DM_ETH=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index a6ae011..4911b61 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -39,3 +39,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 662556a..ee4716d 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 00fa6be..4d18231 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -37,3 +37,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index e3d6b57..c336419 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 44ed671..bb5db5c 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 861bdcf..39cc222 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 7f29119..27f681f 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -30,3 +30,4 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index eff099c..b277b3a 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -30,3 +30,4 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/net/Kconfig b/net/Kconfig
index 414c549..c393269 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -45,4 +45,7 @@ config BOOTP_VCI_STRING
 	default "U-Boot.arm" if ARM
 	default "U-Boot"
 
+config SPL_NET_VCI_STRING
+	string
+
 endif   # if NET
-- 
cgit v0.10.2


From 20898ea9340a4fd1631a4057b8de011b9f166255 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 6 May 2016 21:01:07 +0200
Subject: distro: Add efi pxe boot code

Now that we can expose network functionality to EFI applications,
the logical next step is to load them via pxe to execute them as
well.

This patch adds the necessary bits to the distro script to automatically
load and execute EFI payloads. It identifies the dhcp client as a uEFI
capable PXE client, hoping the server returns a tftp path to a workable
EFI binary that we can then execute.

To enable boards that don't come with a working device tree preloaded,
this patch also adds support to load a device tree from the /dtb directory
on the remote tftp server.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 5a8d7f2..4db6faa 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -230,13 +230,58 @@
 #endif
 
 #if defined(CONFIG_CMD_DHCP)
+#if defined(CONFIG_EFI_LOADER)
+#if defined(CONFIG_ARM64)
+#define BOOTENV_EFI_PXE_ARCH "0xb"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
+#elif defined(CONFIG_ARM)
+#define BOOTENV_EFI_PXE_ARCH "0xa"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
+#elif defined(CONFIG_X86)
+/* Always assume we're running 64bit */
+#define BOOTENV_EFI_PXE_ARCH "0x7"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#else
+#error Please specify an EFI client identifier
+#endif
+
+/*
+ * Ask the dhcp server for an EFI binary. If we get one, check for a
+ * device tree in the same folder. Then boot everything. If the file was
+ * not an EFI binary, we just return from the bootefi command and continue.
+ */
+#define BOOTENV_EFI_RUN_DHCP \
+	"setenv efi_fdtfile ${fdtfile}; "                                 \
+	BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"setenv efi_old_vci ${bootp_vci};"                                \
+	"setenv efi_old_arch ${bootp_arch};"                              \
+	"setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";"                       \
+	"setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";"                     \
+	"if dhcp ${kernel_addr_r}; then "                                 \
+		"tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};"              \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r}; "        \
+		"else "                                                   \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi;"                                                     \
+	"fi;"                                                             \
+	"setenv bootp_vci ${efi_old_vci};"                                \
+	"setenv bootp_arch ${efi_old_arch};"                              \
+	"setenv efi_fdtfile;"                                             \
+	"setenv efi_old_arch;"                                            \
+	"setenv efi_old_vci;"
+#else
+#define BOOTENV_EFI_RUN_DHCP
+#endif
 #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
 	"bootcmd_dhcp=" \
 		BOOTENV_RUN_NET_USB_START \
 		BOOTENV_RUN_NET_PCI_ENUM \
 		"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
 			"source ${scriptaddr}; " \
-		"fi\0"
+		"fi;" \
+		BOOTENV_EFI_RUN_DHCP \
+		"\0"
 #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
 	"dhcp "
 #else
diff --git a/net/bootp.c b/net/bootp.c
index d718e35..85dc524 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -413,12 +413,21 @@ static void bootp_timeout_handler(void)
 
 static u8 *add_vci(u8 *e)
 {
+	char *vci = NULL;
+	char *env_vci = getenv("bootp_vci");
+
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
-	put_vci(e, CONFIG_SPL_NET_VCI_STRING);
+	vci = CONFIG_SPL_NET_VCI_STRING;
 #elif defined(CONFIG_BOOTP_VCI_STRING)
-	put_vci(e, CONFIG_BOOTP_VCI_STRING);
+	vci = CONFIG_BOOTP_VCI_STRING;
 #endif
 
+	if (env_vci)
+		vci = env_vci;
+
+	if (vci)
+		put_vci(e, vci);
+
 	return e;
 }
 
-- 
cgit v0.10.2


From 5a07abb3705f561221e7ae351beba746b6ae6eb7 Mon Sep 17 00:00:00 2001
From: Beniamino Galvani <b.galvani@gmail.com>
Date: Sun, 8 May 2016 08:30:14 +0200
Subject: arm: implement generic PSCI reset call for armv8

Add a psci_system_reset() which calls the SYSTEM_RESET function of
PSCI 0.2 and can be used by boards that support it to implement
reset_cpu().

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 9efcc5a..079e250 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -8,6 +8,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/macro.h>
+#include <asm/psci.h>
 #include <asm/system.h>
 
 /*
@@ -73,3 +74,18 @@ void smc_call(struct pt_regs *args)
 		  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
 		  "x16", "x17");
 }
+
+void __noreturn psci_system_reset(bool conduit_smc)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
+
+	if (conduit_smc)
+		smc_call(&regs);
+	else
+		hvc_call(&regs);
+
+	while (1)
+		;
+}
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606..3704f07 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,7 +18,7 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
-/* PSCI interface */
+/* PSCI 0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
 #define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
 
@@ -32,6 +32,21 @@
 #define ARM_PSCI_RET_INVAL		(-2)
 #define ARM_PSCI_RET_DENIED		(-3)
 
+/* PSCI 0.2 interface */
+#define ARM_PSCI_0_2_FN_BASE			0x84000000
+#define ARM_PSCI_0_2_FN(n)			(ARM_PSCI_0_2_FN_BASE + (n))
+
+#define ARM_PSCI_0_2_FN_PSCI_VERSION		ARM_PSCI_0_2_FN(0)
+#define ARM_PSCI_0_2_FN_CPU_SUSPEND		ARM_PSCI_0_2_FN(1)
+#define ARM_PSCI_0_2_FN_CPU_OFF			ARM_PSCI_0_2_FN(2)
+#define ARM_PSCI_0_2_FN_CPU_ON			ARM_PSCI_0_2_FN(3)
+#define ARM_PSCI_0_2_FN_AFFINITY_INFO		ARM_PSCI_0_2_FN(4)
+#define ARM_PSCI_0_2_FN_MIGRATE			ARM_PSCI_0_2_FN(5)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE	ARM_PSCI_0_2_FN(6)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN(7)
+#define ARM_PSCI_0_2_FN_SYSTEM_OFF		ARM_PSCI_0_2_FN(8)
+#define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
+
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9ae890a..2bdc0be 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -128,6 +128,8 @@ void hvc_call(struct pt_regs *args);
  */
 void smc_call(struct pt_regs *args);
 
+void __noreturn psci_system_reset(bool smc);
+
 #endif	/* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
-- 
cgit v0.10.2


From 0e1a3e30deb089cba3f1c01a48443cf8a86b5398 Mon Sep 17 00:00:00 2001
From: Beniamino Galvani <b.galvani@gmail.com>
Date: Sun, 8 May 2016 08:30:15 +0200
Subject: net: designware: fix descriptor layout and warnings on 64-bit archs

All members of the DMA descriptor must be 32-bit, even on 64-bit
architectures: change the type to u32 to ensure this. Also, fix
other warnings.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Use phys_addr_t not unsigned long long to test that we're within
DMA'able memory]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ca58f34..1673167 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -98,8 +98,8 @@ static void tx_descs_init(struct dw_eth_dev *priv)
 
 	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
-		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
-		desc_p->dmamac_next = &desc_table_p[idx + 1];
+		desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
 
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 		desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
@@ -117,11 +117,11 @@ static void tx_descs_init(struct dw_eth_dev *priv)
 	}
 
 	/* Correcting the last pointer of the chain */
-	desc_p->dmamac_next = &desc_table_p[0];
+	desc_p->dmamac_next = (ulong)&desc_table_p[0];
 
 	/* Flush all Tx buffer descriptors at once */
-	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
-			   (unsigned int)priv->tx_mac_descrtable +
+	flush_dcache_range((ulong)priv->tx_mac_descrtable,
+			   (ulong)priv->tx_mac_descrtable +
 			   sizeof(priv->tx_mac_descrtable));
 
 	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
@@ -142,13 +142,12 @@ static void rx_descs_init(struct dw_eth_dev *priv)
 	 * Otherwise there's a chance to get some of them flushed in RAM when
 	 * GMAC is already pushing data to RAM via DMA. This way incoming from
 	 * GMAC data will be corrupted. */
-	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
-			   RX_TOTAL_BUFSIZE);
+	flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
 
 	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
-		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
-		desc_p->dmamac_next = &desc_table_p[idx + 1];
+		desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
 
 		desc_p->dmamac_cntl =
 			(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
@@ -158,11 +157,11 @@ static void rx_descs_init(struct dw_eth_dev *priv)
 	}
 
 	/* Correcting the last pointer of the chain */
-	desc_p->dmamac_next = &desc_table_p[0];
+	desc_p->dmamac_next = (ulong)&desc_table_p[0];
 
 	/* Flush all Rx buffer descriptors at once */
-	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
-			   (unsigned int)priv->rx_mac_descrtable +
+	flush_dcache_range((ulong)priv->rx_mac_descrtable,
+			   (ulong)priv->rx_mac_descrtable +
 			   sizeof(priv->rx_mac_descrtable));
 
 	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
@@ -290,12 +289,11 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
 	struct eth_dma_regs *dma_p = priv->dma_regs_p;
 	u32 desc_num = priv->tx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
-	uint32_t desc_start = (uint32_t)desc_p;
-	uint32_t desc_end = desc_start +
+	ulong desc_start = (ulong)desc_p;
+	ulong desc_end = desc_start +
 		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
-	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
-	uint32_t data_end = data_start +
-		roundup(length, ARCH_DMA_MINALIGN);
+	ulong data_start = desc_p->dmamac_addr;
+	ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
 	/*
 	 * Strictly we only need to invalidate the "txrx_status" field
 	 * for the following check, but on some platforms we cannot
@@ -312,7 +310,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
 		return -EPERM;
 	}
 
-	memcpy(desc_p->dmamac_addr, packet, length);
+	memcpy((void *)data_start, packet, length);
 
 	/* Flush data to be sent */
 	flush_dcache_range(data_start, data_end);
@@ -352,11 +350,11 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
 	u32 status, desc_num = priv->rx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
 	int length = -EAGAIN;
-	uint32_t desc_start = (uint32_t)desc_p;
-	uint32_t desc_end = desc_start +
+	ulong desc_start = (ulong)desc_p;
+	ulong desc_end = desc_start +
 		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
-	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
-	uint32_t data_end;
+	ulong data_start = desc_p->dmamac_addr;
+	ulong data_end;
 
 	/* Invalidate entire buffer descriptor */
 	invalidate_dcache_range(desc_start, desc_end);
@@ -372,7 +370,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
 		/* Invalidate received data */
 		data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
 		invalidate_dcache_range(data_start, data_end);
-		*packetp = desc_p->dmamac_addr;
+		*packetp = (uchar *)(ulong)desc_p->dmamac_addr;
 	}
 
 	return length;
@@ -382,8 +380,8 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
 {
 	u32 desc_num = priv->rx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
-	uint32_t desc_start = (uint32_t)desc_p;
-	uint32_t desc_end = desc_start +
+	ulong desc_start = (ulong)desc_p;
+	ulong desc_end = desc_start +
 		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
 
 	/*
@@ -488,6 +486,11 @@ int designware_initialize(ulong base_addr, u32 interface)
 		return -ENOMEM;
 	}
 
+	if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
+		printf("designware: buffers are outside DMA memory\n");
+		return -EINVAL;
+	}
+
 	memset(dev, 0, sizeof(struct eth_device));
 	memset(priv, 0, sizeof(struct dw_eth_dev));
 
@@ -583,6 +586,7 @@ static int designware_eth_probe(struct udevice *dev)
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct dw_eth_dev *priv = dev_get_priv(dev);
 	u32 iobase = pdata->iobase;
+	ulong ioaddr;
 	int ret;
 
 #ifdef CONFIG_DM_PCI
@@ -601,8 +605,9 @@ static int designware_eth_probe(struct udevice *dev)
 #endif
 
 	debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
-	priv->mac_regs_p = (struct eth_mac_regs *)iobase;
-	priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
+	ioaddr = iobase;
+	priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
+	priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
 	priv->interface = pdata->phy_interface;
 	priv->max_speed = pdata->max_speed;
 
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ed6344c..d48df7b 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -110,8 +110,8 @@ struct eth_dma_regs {
 struct dmamacdescr {
 	u32 txrx_status;
 	u32 dmamac_cntl;
-	void *dmamac_addr;
-	struct dmamacdescr *dmamac_next;
+	u32 dmamac_addr;
+	u32 dmamac_next;
 } __aligned(ARCH_DMA_MINALIGN);
 
 /*
-- 
cgit v0.10.2


From bfcef28ae4cf04e7c1fd3aea1d60a17bd046f153 Mon Sep 17 00:00:00 2001
From: Beniamino Galvani <b.galvani@gmail.com>
Date: Sun, 8 May 2016 08:30:16 +0200
Subject: arm: add initial support for Amlogic Meson and ODROID-C2

This adds platform code for the Amlogic Meson GXBaby (S905) SoC and a
board definition for ODROID-C2. This initial submission only supports
UART and Ethernet (through the existing Designware driver). DTS files
are the ones submitted to Linux arm-soc for 4.7 [1].

[1] https://patchwork.ozlabs.org/patch/603583/

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5fd20b9..7e45642 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -456,6 +456,13 @@ config ARCH_KEYSTONE
 	select SUPPORT_SPL
 	select CMD_POWEROFF
 
+config ARCH_MESON
+	bool "Amlogic Meson"
+	help
+	  Support for the Meson SoC family developed by Amlogic Inc.,
+	  targeted at media players and tablet computers. We currently
+	  support the S905 (GXBaby) 64-bit SoC.
+
 config ARCH_MX7
 	bool "Freescale MX7"
 	select CPU_V7
@@ -792,6 +799,8 @@ source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/cpu/armv7/rmobile/Kconfig"
 
+source "arch/arm/mach-meson/Kconfig"
+
 source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-s5pc1xx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d516345..ecd1887 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -50,6 +50,7 @@ machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)		+= kirkwood
+machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bd68698..751bbd1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -26,6 +26,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-jerry.dtb \
 	rk3288-rock2-square.dtb \
 	rk3036-sdk.dtb
+dtb-$(CONFIG_ARCH_MESON) += \
+	meson-gxbb-odroidc2.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
new file mode 100644
index 0000000..653c2fa
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+
+/ {
+	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
+	model = "Hardkernel ODROID-C2";
+
+	aliases {
+		serial0 = &uart_AO;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart_AO {
+	status = "okay";
+};
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
new file mode 100644
index 0000000..832815d
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "amlogic,meson-gxbb";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cbus: cbus@c1100000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xc1100000 0x0 0x100000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+
+			uart_A: serial@84c0 {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x084c0 0x0 0x14>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller@c4301000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xc4301000 0 0x1000>,
+			      <0x0 0xc4302000 0 0x2000>,
+			      <0x0 0xc4304000 0 0x2000>,
+			      <0x0 0xc4306000 0 0x2000>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+		};
+
+		aobus: aobus@c8100000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xc8100000 0x0 0x100000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+
+			uart_AO: serial@4c0 {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x004c0 0x0 0x14>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+		};
+
+		apb: apb@d0000000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xd0000000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
new file mode 100644
index 0000000..f90f632
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GXBB_H__
+#define __GXBB_H__
+
+#define GXBB_PERIPHS_BASE	0xc8834400
+#define GXBB_HIU_BASE		0xc883c000
+#define GXBB_ETH_BASE		0xc9410000
+
+/* Peripherals registers */
+#define GXBB_PERIPHS_ADDR(off)	(GXBB_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GXBB_GPIO_OFF(n)	((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GXBB_GPIO_EN(n)		GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
+#define GXBB_GPIO_IN(n)		GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
+#define GXBB_GPIO_OUT(n)	GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
+
+/* Pinmux registers 0 to 12 */
+#define GXBB_PINMUX(n)		GXBB_PERIPHS_ADDR(0x2c + (n))
+
+#define GXBB_ETH_REG_0		GXBB_PERIPHS_ADDR(0x50)
+#define GXBB_ETH_REG_1		GXBB_PERIPHS_ADDR(0x51)
+
+#define GXBB_ETH_REG_0_PHY_INTF		BIT(0)
+#define GXBB_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define GXBB_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define GXBB_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define GXBB_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define GXBB_HIU_ADDR(off)	(GXBB_HIU_BASE + ((off) << 2))
+
+#define GXBB_MEM_PD_REG_0	GXBB_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GXBB_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+/* Clock gates */
+#define GXBB_GCLK_MPEG_0	GXBB_HIU_ADDR(0x50)
+#define GXBB_GCLK_MPEG_1	GXBB_HIU_ADDR(0x51)
+#define GXBB_GCLK_MPEG_2	GXBB_HIU_ADDR(0x52)
+#define GXBB_GCLK_MPEG_OTHER	GXBB_HIU_ADDR(0x53)
+#define GXBB_GCLK_MPEG_AO	GXBB_HIU_ADDR(0x54)
+
+#define GXBB_GCLK_MPEG_1_ETH	BIT(3)
+
+#endif /* __GXBB_H__ */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
new file mode 100644
index 0000000..77d3cfe
--- /dev/null
+++ b/arch/arm/mach-meson/Kconfig
@@ -0,0 +1,31 @@
+if ARCH_MESON
+
+config MESON_GXBB
+	bool "Support Meson GXBaby"
+	select ARM64
+	select DM
+	select DM_SERIAL
+	help
+	  The Amlogic Meson GXBaby (S905) is an ARM SoC with a
+	  quad-core Cortex-A53 CPU and a Mali-450 GPU.
+
+if MESON_GXBB
+
+config TARGET_ODROID_C2
+	bool "ODROID-C2"
+	help
+	  ODROID-C2 is a single board computer based on Meson GXBaby
+	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
+	  slot, eMMC, IR receiver and a 40-pin GPIO header.
+
+endif
+
+config SYS_SOC
+	default "meson"
+
+config SYS_MALLOC_F_LEN
+	default 0x1000
+
+source "board/hardkernel/odroid-c2/Kconfig"
+
+endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
new file mode 100644
index 0000000..44e3d63
--- /dev/null
+++ b/arch/arm/mach-meson/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += board.o
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
new file mode 100644
index 0000000..782f86c
--- /dev/null
+++ b/arch/arm/mach-meson/board.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+#include <asm/arch/gxbb.h>
+#include <asm/armv8/mmu.h>
+#include <asm/unaligned.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	const fdt64_t *val;
+	int offset;
+	int len;
+
+	offset = fdt_path_offset(gd->fdt_blob, "/memory");
+	if (offset < 0)
+		return -EINVAL;
+
+	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+	if (len < sizeof(*val) * 2)
+		return -EINVAL;
+
+	/* Use unaligned access since cache is still disabled */
+	gd->ram_size = get_unaligned_be64(&val[1]);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	/* Reserve first 16 MiB of RAM for firmware */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
+	gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset(true);
+}
+
+static struct mm_region gxbb_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = gxbb_mem_map;
diff --git a/board/hardkernel/odroid-c2/Kconfig b/board/hardkernel/odroid-c2/Kconfig
new file mode 100644
index 0000000..687d9c6
--- /dev/null
+++ b/board/hardkernel/odroid-c2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_C2
+
+config SYS_BOARD
+	default "odroid-c2"
+
+config SYS_VENDOR
+	default "hardkernel"
+
+config SYS_CONFIG_NAME
+	default "odroid-c2"
+
+endif
diff --git a/board/hardkernel/odroid-c2/MAINTAINERS b/board/hardkernel/odroid-c2/MAINTAINERS
new file mode 100644
index 0000000..23ae1e7
--- /dev/null
+++ b/board/hardkernel/odroid-c2/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID-C2
+M:	Beniamino Galvani <b.galvani@gmail.com>
+S:	Maintained
+F:	board/hardkernel/odroid-c2/
+F:	include/configs/odroid-c2.h
+F:	configs/odroid-c2_defconfig
diff --git a/board/hardkernel/odroid-c2/Makefile b/board/hardkernel/odroid-c2/Makefile
new file mode 100644
index 0000000..571044b
--- /dev/null
+++ b/board/hardkernel/odroid-c2/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= odroid-c2.o
diff --git a/board/hardkernel/odroid-c2/README b/board/hardkernel/odroid-c2/README
new file mode 100644
index 0000000..d6d266a
--- /dev/null
+++ b/board/hardkernel/odroid-c2/README
@@ -0,0 +1,60 @@
+U-Boot for ODROID-C2
+====================
+
+ODROID-C2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-c2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > DIR=odroid-c2
+ > git clone --depth 1 \
+       https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
+       $DIR
+ > $DIR/fip/fip_create --bl30  $DIR/fip/gxb/bl30.bin \
+                       --bl301 $DIR/fip/gxb/bl301.bin \
+                       --bl31  $DIR/fip/gxb/bl31.bin \
+                       --bl33  u-boot.bin \
+                       $DIR/fip.bin
+ > $DIR/fip/fip_create --dump $DIR/fip.bin
+ > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
+ > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
+                                --input $DIR/boot_new.bin \
+                                --output $DIR/u-boot.img
+ > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > BL1=$DIR/sd_fuse/bl1.bin.hardkernel
+ > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
+ > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
+ > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
new file mode 100644
index 0000000..c258d4f
--- /dev/null
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <dm/platdata.h>
+#include <phy.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+static const struct eth_pdata gxbb_eth_pdata = {
+	.iobase = GXBB_ETH_BASE,
+	.phy_interface = PHY_INTERFACE_MODE_RGMII,
+};
+
+U_BOOT_DEVICE(meson_eth) = {
+	.name = "eth_designware",
+	.platdata = &gxbb_eth_pdata,
+};
+
+int misc_init_r(void)
+{
+	/* Select Ethernet function */
+	setbits_le32(GXBB_PINMUX(6), 0x3fff);
+
+	/* Set RGMII mode */
+	setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
+				     GXBB_ETH_REG_0_TX_PHASE(1) |
+				     GXBB_ETH_REG_0_TX_RATIO(4) |
+				     GXBB_ETH_REG_0_PHY_CLK_EN |
+				     GXBB_ETH_REG_0_CLK_EN);
+
+	/* Enable power and clock gate */
+	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+	/* Reset PHY on GPIOZ_14 */
+	clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
+	clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+	mdelay(10);
+	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+
+	return 0;
+}
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
new file mode 100644
index 0000000..a771b20
--- /dev/null
+++ b/configs/odroid-c2_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_MESON_GXBB=y
+CONFIG_TARGET_ODROID_C2=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2497ae9..0e38903 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -121,6 +121,14 @@ config DEBUG_UART_S5P
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 
+config DEBUG_UART_MESON
+	bool "Amlogic Meson"
+	depends on MESON_SERIAL
+	help
+	  Select this to enable a debug UART using the serial_meson driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver-model serial is running.
+
 config DEBUG_UART_UARTLITE
 	bool "Xilinx Uartlite"
 	help
@@ -338,6 +346,13 @@ config XILINX_UARTLITE
 	  If you have a Xilinx based board and want to use the uartlite
 	  serial ports, say Y to this option. If unsure, say N.
 
+config MESON_SERIAL
+	bool "Support for Amlogic Meson UART"
+	depends on DM_SERIAL && ARCH_MESON
+	help
+	  If you have an Amlogic Meson based board and want to use the on-chip
+	  serial ports, say Y to this option. If unsure, say N.
+
 config MSM_SERIAL
 	bool "Qualcomm on-chip UART"
 	depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9def128..e1e28de 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
+obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
 obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
new file mode 100644
index 0000000..1b49426
--- /dev/null
+++ b/drivers/serial/serial_meson.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/compiler.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct meson_uart {
+	u32 wfifo;
+	u32 rfifo;
+	u32 control;
+	u32 status;
+	u32 misc;
+};
+
+struct meson_serial_platdata {
+	struct meson_uart *reg;
+};
+
+/* AML_UART_STATUS bits */
+#define AML_UART_PARITY_ERR		BIT(16)
+#define AML_UART_FRAME_ERR		BIT(17)
+#define AML_UART_TX_FIFO_WERR		BIT(18)
+#define AML_UART_RX_EMPTY		BIT(20)
+#define AML_UART_TX_FULL		BIT(21)
+#define AML_UART_TX_EMPTY		BIT(22)
+#define AML_UART_XMIT_BUSY		BIT(25)
+#define AML_UART_ERR			(AML_UART_PARITY_ERR | \
+					 AML_UART_FRAME_ERR  | \
+					 AML_UART_TX_FIFO_WERR)
+
+/* AML_UART_CONTROL bits */
+#define AML_UART_TX_EN			BIT(12)
+#define AML_UART_RX_EN			BIT(13)
+#define AML_UART_TX_RST			BIT(22)
+#define AML_UART_RX_RST			BIT(23)
+#define AML_UART_CLR_ERR		BIT(24)
+
+static void meson_serial_init(struct meson_uart *uart)
+{
+	u32 val;
+
+	val = readl(&uart->control);
+	val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+	writel(val, &uart->control);
+	val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+	writel(val, &uart->control);
+	val |= (AML_UART_RX_EN | AML_UART_TX_EN);
+	writel(val, &uart->control);
+}
+
+static int meson_serial_probe(struct udevice *dev)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+
+	meson_serial_init(uart);
+
+	return 0;
+}
+
+static int meson_serial_getc(struct udevice *dev)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+
+	if (readl(&uart->status) & AML_UART_RX_EMPTY)
+		return -EAGAIN;
+
+	return readl(&uart->rfifo) & 0xff;
+}
+
+static int meson_serial_putc(struct udevice *dev, const char ch)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+
+	if (readl(&uart->status) & AML_UART_TX_FULL)
+		return -EAGAIN;
+
+	writel(ch, &uart->wfifo);
+
+	return 0;
+}
+
+static int meson_serial_pending(struct udevice *dev, bool input)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+	uint32_t status = readl(&uart->status);
+
+	if (input)
+		return !(status & AML_UART_RX_EMPTY);
+	else
+		return !(status & AML_UART_TX_FULL);
+}
+
+static int meson_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->reg = (struct meson_uart *)addr;
+
+	return 0;
+}
+
+static const struct dm_serial_ops meson_serial_ops = {
+	.putc = meson_serial_putc,
+	.pending = meson_serial_pending,
+	.getc = meson_serial_getc,
+};
+
+static const struct udevice_id meson_serial_ids[] = {
+	{ .compatible = "amlogic,meson-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_meson) = {
+	.name		= "serial_meson",
+	.id		= UCLASS_SERIAL,
+	.of_match	= meson_serial_ids,
+	.probe		= meson_serial_probe,
+	.ops		= &meson_serial_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+	.ofdata_to_platdata = meson_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct meson_serial_platdata),
+};
+
+#ifdef CONFIG_DEBUG_UART_MESON
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
+
+	while (readl(&regs->status) & AML_UART_TX_FULL)
+		;
+
+	writel(ch, &regs->wfifo);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
new file mode 100644
index 0000000..37a5671
--- /dev/null
+++ b/include/configs/odroid-c2.h
@@ -0,0 +1,51 @@
+/*
+ * Configuration for ODROID-C2
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
+
+#define CONFIG_IDENT_STRING		" odroid-c2"
+
+/* Serial setup */
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_CMD_ENV
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#include <config_distro_defaults.h>
+
+#endif /* __CONFIG_H */
-- 
cgit v0.10.2


From c7757d46958463542f3c5cc359d53769f83b9148 Mon Sep 17 00:00:00 2001
From: Beniamino Galvani <b.galvani@gmail.com>
Date: Sun, 8 May 2016 08:30:17 +0200
Subject: arm: meson: implement calls to secure monitor

Implement calls to secure monitor to read the MAC address from e-fuse.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>

diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
new file mode 100644
index 0000000..225438d
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MESON_SM_H__
+#define __MESON_SM_H__
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+
+#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 44e3d63..bf49b8b 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += board.o
+obj-y += board.o sm.o
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index 782f86c..64fa3c1 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -8,6 +8,7 @@
 #include <libfdt.h>
 #include <linux/err.h>
 #include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
 #include <asm/armv8/mmu.h>
 #include <asm/unaligned.h>
 
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
new file mode 100644
index 0000000..1b35a22
--- /dev/null
+++ b/arch/arm/mach-meson/sm.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Secure monitor calls.
+ */
+
+#include <common.h>
+#include <asm/arch/gxbb.h>
+#include <linux/kernel.h>
+
+#define FN_GET_SHARE_MEM_INPUT_BASE	0x82000020
+#define FN_GET_SHARE_MEM_OUTPUT_BASE	0x82000021
+#define FN_EFUSE_READ			0x82000030
+#define FN_EFUSE_WRITE			0x82000031
+
+static void *shmem_input;
+static void *shmem_output;
+
+static void meson_init_shmem(void)
+{
+	struct pt_regs regs;
+
+	if (shmem_input && shmem_output)
+		return;
+
+	regs.regs[0] = FN_GET_SHARE_MEM_INPUT_BASE;
+	smc_call(&regs);
+	shmem_input = (void *)regs.regs[0];
+
+	regs.regs[0] = FN_GET_SHARE_MEM_OUTPUT_BASE;
+	smc_call(&regs);
+	shmem_output = (void *)regs.regs[0];
+
+	debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output);
+}
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size)
+{
+	struct pt_regs regs;
+
+	meson_init_shmem();
+
+	regs.regs[0] = FN_EFUSE_READ;
+	regs.regs[1] = offset;
+	regs.regs[2] = size;
+
+	smc_call(&regs);
+
+	if (regs.regs[0] == 0)
+		return -1;
+
+	memcpy(buffer, shmem_output, min(size, regs.regs[0]));
+
+	return regs.regs[0];
+}
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
index c258d4f..bd72100 100644
--- a/board/hardkernel/odroid-c2/odroid-c2.c
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -7,9 +7,15 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
 #include <dm/platdata.h>
 #include <phy.h>
 
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
 int board_init(void)
 {
 	return 0;
@@ -27,6 +33,9 @@ U_BOOT_DEVICE(meson_eth) = {
 
 int misc_init_r(void)
 {
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	ssize_t len;
+
 	/* Select Ethernet function */
 	setbits_le32(GXBB_PINMUX(6), 0x3fff);
 
@@ -47,5 +56,12 @@ int misc_init_r(void)
 	mdelay(10);
 	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
 
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
 	return 0;
 }
-- 
cgit v0.10.2


From 851bda81487b0e2b5b43c9c2dc2582214751953e Mon Sep 17 00:00:00 2001
From: Lukasz Majewski <l.majewski@majess.pl>
Date: Sun, 8 May 2016 08:52:21 +0200
Subject: cosmetic: debug: Replace #ifdef DEBUG with debug() macro

Replace #ifdef DEBUG with dedicated debug() macro.

Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>

diff --git a/common/bootm_os.c b/common/bootm_os.c
index cb83f4a..9ec84bd 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -484,9 +484,8 @@ int boot_selected_os(int argc, char * const argv[], int state,
 	    state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
 		return 0;
 	bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
-#ifdef DEBUG
-	puts("\n## Control returned to monitor - resetting...\n");
-#endif
+	debug("\n## Control returned to monitor - resetting...\n");
+
 	return BOOTM_ERR_RESET;
 }
 
-- 
cgit v0.10.2


From 51735ae0ea2f5d67c0f7cc4d1f938f36955e1fe7 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 11 May 2016 18:25:48 +0200
Subject: efi_loader: Add bounce buffer support

Some hardware that is supported by U-Boot can not handle DMA above 32bits.
For these systems, we need to come up with a way to expose the disk interface
in a safe way.

This patch implements EFI specific bounce buffers. For non-EFI cases, this
apparently was no issue so far, since we can just define our environment
variables conveniently.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 8005454..b1ca4ba 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -139,6 +139,11 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 /* Called by board init to initialize the EFI memory map */
 int efi_memory_init(void);
 
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+extern void *efi_bounce_buffer;
+#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
+#endif
+
 /* Convert strings from normal C strings to uEFI strings */
 static inline void ascii2unicode(u16 *unicode, char *ascii)
 {
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 14c99ec..37a0dd6 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -7,3 +7,12 @@ config EFI_LOADER
 	  on top of U-Boot. If this option is enabled, U-Boot will expose EFI
 	  interfaces to a loaded EFI application, enabling it to reuse U-Boot's
 	  device drivers.
+
+config EFI_LOADER_BOUNCE_BUFFER
+	bool "EFI Applications use bounce buffers for DMA operations"
+	depends on EFI_LOADER && ARM64
+	default n
+	help
+	  Some hardware does not support DMA to full 64bit addresses. For this
+	  hardware we can create a bounce buffer so that payloads don't have to
+	  worry about platform details.
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 075fd34..c7d4515 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -76,9 +76,6 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 	int blocks;
 	unsigned long n;
 
-	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
-		  buffer_size, buffer);
-
 	diskobj = container_of(this, struct efi_disk_obj, ops);
 	if (!(desc = blk_get_dev(diskobj->ifname, diskobj->dev_index)))
 		return EFI_EXIT(EFI_DEVICE_ERROR);
@@ -95,10 +92,11 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 	if (buffer_size & (blksz - 1))
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
-	if (direction == EFI_DISK_READ)
+	if (direction == EFI_DISK_READ) {
 		n = desc->block_read(desc, lba, blocks, buffer);
-	else
+	} else {
 		n = desc->block_write(desc, lba, blocks, buffer);
+	}
 
 	/* We don't do interrupts, so check for timers cooperatively */
 	efi_timer_check();
@@ -116,16 +114,70 @@ static efi_status_t efi_disk_read_blocks(struct efi_block_io *this,
 			u32 media_id, u64 lba, unsigned long buffer_size,
 			void *buffer)
 {
-	return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
-				  EFI_DISK_READ);
+	void *real_buffer = buffer;
+	efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+	if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+		r = efi_disk_read_blocks(this, media_id, lba,
+			EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+		if (r != EFI_SUCCESS)
+			return r;
+		return efi_disk_read_blocks(this, media_id, lba +
+			EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+			buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+			buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+	}
+
+	real_buffer = efi_bounce_buffer;
+#endif
+
+	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+		  buffer_size, buffer);
+
+	r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+			       EFI_DISK_READ);
+
+	/* Copy from bounce buffer to real buffer if necessary */
+	if ((r == EFI_SUCCESS) && (real_buffer != buffer))
+		memcpy(buffer, real_buffer, buffer_size);
+
+	return EFI_EXIT(r);
 }
 
 static efi_status_t efi_disk_write_blocks(struct efi_block_io *this,
 			u32 media_id, u64 lba, unsigned long buffer_size,
 			void *buffer)
 {
-	return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
-				  EFI_DISK_WRITE);
+	void *real_buffer = buffer;
+	efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+	if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+		r = efi_disk_write_blocks(this, media_id, lba,
+			EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+		if (r != EFI_SUCCESS)
+			return r;
+		return efi_disk_write_blocks(this, media_id, lba +
+			EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+			buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+			buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+	}
+
+	real_buffer = efi_bounce_buffer;
+#endif
+
+	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+		  buffer_size, buffer);
+
+	/* Populate bounce buffer if necessary */
+	if (real_buffer != buffer)
+		memcpy(real_buffer, buffer, buffer_size);
+
+	r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+			       EFI_DISK_WRITE);
+
+	return EFI_EXIT(r);
 }
 
 static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 71a3d19..9e669f5 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -27,6 +27,10 @@ struct efi_mem_list {
 /* This list contains all memory map items */
 LIST_HEAD(efi_mem);
 
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+void *efi_bounce_buffer;
+#endif
+
 /*
  * Sorts the memory list from highest address to lowest address
  *
@@ -349,5 +353,17 @@ int efi_memory_init(void)
 	efi_add_memory_map(runtime_start, runtime_pages,
 			   EFI_RUNTIME_SERVICES_CODE, false);
 
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+	/* Request a 32bit 64MB bounce buffer region */
+	uint64_t efi_bounce_buffer_addr = 0xffffffff;
+
+	if (efi_allocate_pages(1, EFI_LOADER_DATA,
+			       (64 * 1024 * 1024) >> EFI_PAGE_SHIFT,
+			       &efi_bounce_buffer_addr) != EFI_SUCCESS)
+		return -1;
+
+	efi_bounce_buffer = (void*)(uintptr_t)efi_bounce_buffer_addr;
+#endif
+
 	return 0;
 }
-- 
cgit v0.10.2


From 6a6187efd238373a351369d23966e7e1759b5ad9 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 11 May 2016 18:25:49 +0200
Subject: efi_loader: Select bounce buffers for known-bad boards

We know for certain that we have 32bit DMA hardware, but 64bit addresses
on LS2085A and ZynqMP, so let's enable EFI bounce buffers for all defconfigs
on these SoCs.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index 30a6381..56922dc 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -26,3 +26,4 @@ CONFIG_CMD_CACHE=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
 CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU"
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index a095b8a..f27fbb7 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -29,3 +29,4 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
 CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU"
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 216559c..04a84ab 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -30,3 +30,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 854630a..3b6504b 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -29,3 +29,4 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 4f385a1..1302313 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -23,3 +23,4 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 41d30a6..f974d88 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -30,3 +30,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 2b775cd..0168dbb 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -29,3 +29,4 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 0f184c0..718a651 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -23,3 +23,4 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 37b8052..f342ed2 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -64,3 +64,4 @@ CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03fd
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
 # CONFIG_REGEX is not set
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index fa761e5..5d641a5 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -58,3 +58,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 2811d4b..77e6180 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -50,3 +50,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 3711084..f7c671b 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -32,3 +32,4 @@ CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_DM_ETH=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 46a5dd0..b370bc1 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 96a2be1..9764452 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
cgit v0.10.2


From bc6fc28b8604eddb527217b450d86d368cc25d13 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 12 May 2016 15:51:45 +0200
Subject: net: Optionally use pxe client arch from variable

The client architecture that we pass to a dhcp server depends on the target
payload that we want to execute. An EFI binary has a different client arch
than a legacy binary or a u-boot binary.

So let's parameterize the pxe client arch field to allow an override via
the distro script, so that our efi boot path can tell the dhcp server that
it's actually an efi firmware.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/net/bootp.c b/net/bootp.c
index 85dc524..aa6cdf0 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -440,10 +440,10 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 {
 	u8 *start = e;
 	u8 *cnt;
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_LIB_UUID
 	char *uuid;
-	u16 clientarch;
 #endif
+	int clientarch = -1;
 
 #if defined(CONFIG_BOOTP_VENDOREX)
 	u8 *x;
@@ -499,12 +499,19 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 	}
 #endif
 
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_BOOTP_PXE_CLIENTARCH
 	clientarch = CONFIG_BOOTP_PXE_CLIENTARCH;
-	*e++ = 93;	/* Client System Architecture */
-	*e++ = 2;
-	*e++ = (clientarch >> 8) & 0xff;
-	*e++ = clientarch & 0xff;
+#endif
+
+	if (getenv("bootp_arch"))
+		clientarch = getenv_ulong("bootp_arch", 16, clientarch);
+
+	if (clientarch > 0) {
+		*e++ = 93;	/* Client System Architecture */
+		*e++ = 2;
+		*e++ = (clientarch >> 8) & 0xff;
+		*e++ = clientarch & 0xff;
+	}
 
 	*e++ = 94;	/* Client Network Interface Identifier */
 	*e++ = 3;
@@ -512,6 +519,7 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 	*e++ = 0;	/* major revision */
 	*e++ = 0;	/* minor revision */
 
+#ifdef CONFIG_LIB_UUID
 	uuid = getenv("pxeuuid");
 
 	if (uuid) {
-- 
cgit v0.10.2


From 3ac8d1ee12dcc59942c22f76ccce5537fc3a198a Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Fri, 13 May 2016 15:17:52 +0300
Subject: usb: dwc3: Makefile: Don't build gadget code if USB_GADGET is
 disabled

It is pointless to build gadget driver if USB_GADGET is disabled.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 0cd7302..2964bae 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_USB_DWC3)			+= dwc3.o
 
 dwc3-y					:= core.o
 
-dwc3-y					+= gadget.o ep0.o
+obj-$(CONFIG_USB_DWC3_GADGET)		+= gadget.o ep0.o
 
 obj-$(CONFIG_USB_DWC3_OMAP)		+= dwc3-omap.o
 obj-$(CONFIG_USB_DWC3_PHY_OMAP)		+= ti_usb_phy.o
-- 
cgit v0.10.2


From feee28f7d744fec50f61b4d46d3dfac165316fbc Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:26 -0600
Subject: openrisc: Drop the arch-specific board init

It is well past the deadline for conversion to generic board init. Remove
the old code.

Stefan, can you test this please and perhaps send a follow-up patch if needed?

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index dfa72d9..3a2f6ec 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -5,6 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= board.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= timer.o
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c
deleted file mode 100644
index b7fbd2f..0000000
--- a/arch/openrisc/lib/board.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2011
- * Julius Baxter, julius@opencores.org
- *
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <stdio_dev.h>
-#include <watchdog.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <net.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#ifdef CONFIG_CMD_NAND
-#include <nand.h>	/* cannot even include nand.h if it isnt configured */
-#endif
-
-#include <timestamp.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-
-extern int cache_init(void);
-
-/*
- * Initialization sequence
- */
-static int (* const init_sequence[])(void) = {
-	cache_init,
-	timer_init,		/* initialize timer */
-	env_init,
-	serial_init,
-	console_init_f,
-	display_options,
-	checkcpu,
-	checkboard,
-};
-
-
-/***********************************************************************/
-void board_init(void)
-{
-	bd_t *bd;
-	int i;
-
-	gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
-
-	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-
-	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
-	gd->baudrate = CONFIG_BAUDRATE;
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
-	bd = gd->bd;
-	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
-	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
-	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
-	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
-		WATCHDOG_RESET();
-		if (init_sequence[i]())
-			hang();
-	}
-
-	WATCHDOG_RESET();
-
-	/* The Malloc area is immediately below the monitor copy in RAM */
-	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
-	WATCHDOG_RESET();
-	bd->bi_flashsize = flash_init();
-#endif
-
-#ifdef CONFIG_CMD_NAND
-	puts("NAND:  ");
-	nand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-	puts("MMC:   ");
-	mmc_initialize(bd);
-#endif
-
-	WATCHDOG_RESET();
-	env_relocate();
-
-	WATCHDOG_RESET();
-	stdio_init();
-	jumptable_init();
-	console_init_r();
-
-	WATCHDOG_RESET();
-	interrupt_init();
-
-#if defined(CONFIG_BOARD_LATE_INIT)
-	board_late_init();
-#endif
-
-#if defined(CONFIG_CMD_NET)
-	puts("NET:   ");
-	eth_initialize();
-#endif
-
-	/* main_loop */
-	for (;;) {
-		WATCHDOG_RESET();
-		main_loop();
-	}
-}
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index dfb8d3a..14e44b0 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -10,6 +10,7 @@
 /*
  * BOARD/CPU
  */
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_SYS_CLK_FREQ		50000000
 #define CONFIG_SYS_RESET_ADDR		0x00000100
-- 
cgit v0.10.2


From 89b199c3d4416e63d025e4927da8d4fde1de8b2a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:27 -0600
Subject: Remove/update old generic-board documentation and warning
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Remove the warning from the Makefile, since boards that do not use generic
board will no longer build. Also update documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/Makefile b/Makefile
index 4dc179b..742b165 100644
--- a/Makefile
+++ b/Makefile
@@ -801,13 +801,6 @@ quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
 all:		$(ALL-y)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
-	@echo "===================== WARNING ======================"
-	@echo "Please convert this board to generic board."
-	@echo "Otherwise it will be removed by the end of 2014."
-	@echo "See doc/README.generic-board for further information"
-	@echo "===================================================="
-endif
 ifeq ($(CONFIG_DM_I2C_COMPAT),y)
 	@echo "===================== WARNING ======================"
 	@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -1257,13 +1250,6 @@ prepare2: prepare3 outputmakefile
 
 prepare1: prepare2 $(version_h) $(timestamp_h) \
                    include/config/auto.conf
-ifeq ($(CONFIG_HAVE_GENERIC_BOARD),)
-ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
-	@echo >&2 "  Your architecture does not support generic board."
-	@echo >&2 "  Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
-	@/bin/false
-endif
-endif
 ifeq ($(wildcard $(LDSCRIPT)),)
 	@echo >&2 "  Could not find linker script."
 	@/bin/false
diff --git a/README b/README
index 6f4c09a..1d0b946 100644
--- a/README
+++ b/README
@@ -4048,16 +4048,6 @@ Configuration Settings:
 	If defined, don't allow the -f switch to env set override variable
 	access flags.
 
-- CONFIG_SYS_GENERIC_BOARD
-	This selects the architecture-generic board system instead of the
-	architecture-specific board files. It is intended to move boards
-	to this new framework over time. Defining this will disable the
-	arch/foo/lib/board.c file and use common/board_f.c and
-	common/board_r.c instead. To use this option your architecture
-	must support it (i.e. must select HAVE_GENERIC_BOARD in arch/Kconfig).
-	If you find problems enabling this option on your board please report
-	the problem and send patches!
-
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index fa1842b..9fe3bf1 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -186,8 +186,7 @@ U-Boot sandbox supports these emulations:
 A wide range of commands is implemented. Filesystems which use a block
 device are supported.
 
-Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
-driver model (CONFIG_DM) and associated commands.
+Also sandbox supports driver model (CONFIG_DM) and associated commands.
 
 
 Linux RAW Networking Bridge
diff --git a/doc/README.fdt-control b/doc/README.fdt-control
index 29fd56a..2913fcb 100644
--- a/doc/README.fdt-control
+++ b/doc/README.fdt-control
@@ -33,12 +33,6 @@ the features of each board in the device tree file, and have a single
 generic source base.
 
 To enable this feature, add CONFIG_OF_CONTROL to your board config file.
-It is currently supported on ARM, x86 and Microblaze - other architectures
-will need to add code to their arch/xxx/lib/board.c file to locate the
-FDT. Alternatively you can enable generic board support on your board
-(with CONFIG_SYS_GENERIC_BOARD) if this is available (as it is for
-PowerPC). For ARM, Tegra and Exynos5 have device trees available for
-common devices.
 
 
 What is a Flat Device Tree?
diff --git a/doc/README.generic-board b/doc/README.generic-board
index 734f1aa..6858c4d 100644
--- a/doc/README.generic-board
+++ b/doc/README.generic-board
@@ -5,29 +5,22 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-DEPRECATION NOTICE FOR arch/<arch>/lib/board.c
-
-For board maintainers: Please submit patches for boards you maintain before
-July 2014, to make them use generic board.
-
-For architecture maintainers: Please submit patches to remove your
-architecture-specific board.c file before October 2014.
-
-
 Background
 ----------
 
-U-Boot has traditionally had a board.c file for each architecture. This has
-introduced quite a lot of duplication, with each architecture tending to do
+U-Boot traditionally had a board.c file for each architecture. This introduced
+quite a lot of duplication, with each architecture tending to do
 initialisation slightly differently. To address this, a new 'generic board
-init' feature was introduced a year ago in March 2013 (further motivation is
+init' feature was introduced in March 2013 (further motivation is
 provided in the cover letter below).
 
+All boards and architectures have moved to this as of mid 2016.
+
 
 What has changed?
 -----------------
 
-The main change is that the arch/<arch>/lib/board.c file is being removed in
+The main change is that the arch/<arch>/lib/board.c file is removed in
 favour of common/board_f.c (for pre-relocation init) and common/board_r.c
 (for post-relocation init).
 
@@ -36,55 +29,6 @@ fields which are common to all architectures. Architecture-specific fields
 have been moved to separate structures.
 
 
-Supported Architectures
-------------------------
-
-If you are unlucky then your architecture may not support generic board.
-The following architectures are supported now:
-
-   arc
-   arm
-   avr32
-   blackfin
-   m68k
-   microblaze
-   mips
-   nios2
-   powerpc
-   sandbox
-   x86
-
-If your architecture is not supported, you need to select
-HAVE_GENERIC_BOARD in arch/Kconfig
-and test it with a suitable board, as follows.
-
-
-Adding Support for your Board
------------------------------
-
-To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in
-your board config header file.
-
-Test that U-Boot still functions correctly on your board, and fix any
-problems you find. Don't be surprised if there are no problems - generic
-board has had a reasonable amount of testing with common boards.
-
-
-DeadLine
---------
-
-Please don't take this the wrong way - there is no intent to make your life
-miserable, and we have the greatest respect and admiration for U-Boot users.
-However, with any migration there has to be a period where the old way is
-deprecated and removed. Every patch to the deprecated code introduces a
-potential breakage in the new unused code. Therefore:
-
-Boards or architectures not converted over to general board by the
-end of 2014 may be forcibly changed over (potentially causing run-time
-breakage) or removed.
-
-
-
 Further Background
 ------------------
 
@@ -190,3 +134,4 @@ convenience.
 
 Simon Glass, sjg@chromium.org
 March 2014
+Updated after final removal, May 2016
-- 
cgit v0.10.2


From b0b359536e2bcdf9e049e36a9ad5e4f7174bdc74 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:28 -0600
Subject: board_f: Don't require CONFIG_SYS_MONITOR_BASE

Allow this to be unset, such that gd->mon_len is invalid. This seems to be
what the sh architecture does.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/board_f.c b/common/board_f.c
index 109025a..d405b5b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -274,7 +274,7 @@ static int setup_mon_len(void)
 	gd->mon_len = CONFIG_SYS_MONITOR_LEN;
 #elif defined(CONFIG_NDS32)
 	gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
-#else
+#elif defined(CONFIG_SYS_MONITOR_BASE)
 	/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
 	gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
 #endif
-- 
cgit v0.10.2


From f41e6088eb1a32fdb717110dde66165728e484aa Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:29 -0600
Subject: sh: Fix build errors for generic board

This includes the following fixes:
- Define needed __init_end symbol - see initr_reloc_global_data()
- Drop SH-specific struct bd_info
- Add an empty relocate_code() function

This prevents build errors with generic board, but the code will still need
work. Perhaps this is a better alternative than deleting the code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index a2f856f..9a93cf5 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -83,3 +83,9 @@ int dcache_status(void)
 {
 	return 0;
 }
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+	/* TODO(sh maintainer): Implement this */
+	while (1);
+}
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
index ebf731a..6171edc 100644
--- a/arch/sh/cpu/sh2/start.S
+++ b/arch/sh/cpu/sh2/start.S
@@ -46,8 +46,9 @@ _init:
 	mov.l	._gd_init, r13		/* global data */
 	mov.l	._stack_init, r15	/* stack */
 
-	mov.l	._sh_generic_init, r0
-	jsr	@r0
+	#TODO(sh maintainer): Fix this up to call the correct code
+	#mov.l	._sh_generic_init, r0
+	#jsr	@r0
 	nop
 
 loop:
@@ -62,4 +63,4 @@ loop:
 ._bss_end:		.long	bss_end
 ._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
 ._stack_init:	.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init:	.long	sh_generic_init
+#._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c
index ea0006a..494f908 100644
--- a/arch/sh/cpu/sh3/cpu.c
+++ b/arch/sh/cpu/sh3/cpu.c
@@ -66,3 +66,9 @@ int dcache_status(void)
 {
 	return 0;
 }
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+	/* TODO(sh maintainer): Implement this */
+	while (1);
+}
diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S
index 7a934e2..9ed7198 100644
--- a/arch/sh/cpu/sh3/start.S
+++ b/arch/sh/cpu/sh3/start.S
@@ -45,8 +45,9 @@ _sh_start:
 	mov.l	._gd_init, r13		/* global data */
 	mov.l	._stack_init, r15	/* stack */
 
-	mov.l	._sh_generic_init, r0
-	jsr	@r0
+	#TODO(sh maintainer): Fix this up to call the correct code
+	#mov.l	._sh_generic_init, r0
+	#jsr	@r0
 	nop
 
 loop:
@@ -61,4 +62,4 @@ loop:
 ._bss_end:		.long	bss_end
 ._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
 ._stack_init:	.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init:	.long	sh_generic_init
+#._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index e8ee0a4..de90ca7 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -75,3 +75,9 @@ int cpu_eth_init(bd_t *bis)
 #endif
 	return 0;
 }
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+	/* TODO(sh maintainer): Implement this */
+	while (1);
+}
diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S
index 21644b5..77fc221 100644
--- a/arch/sh/cpu/sh4/start.S
+++ b/arch/sh/cpu/sh4/start.S
@@ -42,8 +42,9 @@ _sh_start:
 	mov.l	._gd_init, r13		/* global data */
 	mov.l	._stack_init, r15	/* stack */
 
-	mov.l	._sh_generic_init, r0
-	jsr	@r0
+	#TODO(sh maintainer): Fix this up to call the correct code
+	#mov.l	._sh_generic_init, r0
+	#jsr	@r0
 	nop
 
 loop:
@@ -58,4 +59,4 @@ loop:
 ._bss_end:		.long	bss_end
 ._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
 ._stack_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init:	.long	sh_generic_init
+#._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 30c7a9d..78611c2 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -67,6 +67,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
index ea37c24..716d8e9 100644
--- a/arch/sh/include/asm/u-boot.h
+++ b/arch/sh/include/asm/u-boot.h
@@ -12,16 +12,8 @@
 #ifndef __ASM_SH_U_BOOT_H_
 #define __ASM_SH_U_BOOT_H_
 
-typedef struct bd_info {
-	unsigned long   bi_memstart;    /* start of DRAM memory */
-	phys_size_t	bi_memsize;     /* size  of DRAM memory in bytes */
-	unsigned long   bi_flashstart;  /* start of FLASH memory */
-	unsigned long   bi_flashsize;   /* size  of FLASH memory */
-	unsigned long   bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long   bi_sramstart;   /* start of SRAM memory */
-	unsigned long   bi_sramsize;    /* size  of SRAM memory */
-	unsigned long	bi_boot_params; /* where this board expects params */
-} bd_t;
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_SH
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
index 053df64..6cd4056 100644
--- a/board/renesas/sh7752evb/u-boot.lds
+++ b/board/renesas/sh7752evb/u-boot.lds
@@ -65,6 +65,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
index 053df64..6cd4056 100644
--- a/board/renesas/sh7753evb/u-boot.lds
+++ b/board/renesas/sh7753evb/u-boot.lds
@@ -65,6 +65,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
index 4027fe3..d701367 100644
--- a/board/renesas/sh7757lcr/u-boot.lds
+++ b/board/renesas/sh7757lcr/u-boot.lds
@@ -66,6 +66,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
-- 
cgit v0.10.2


From b61e90e6fd83a8bc80209a19b77b925bcdc342df Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:30 -0600
Subject: sh: Drop the arch-specific board init

It is well past the deadline for conversion to generic board init. Remove
the old code.

Please test this and perhaps send a follow-up patch if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index cd29734..dd1329e 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -7,4 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #endif
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index f7ae4f8..c5cf89f 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -6,7 +6,6 @@
 #
 
 
-obj-y	+= board.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 ifeq ($(CONFIG_CPU_SH2),y)
 obj-y	+= time_sh2.o
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
deleted file mode 100644
index 69cdca3..0000000
--- a/arch/sh/lib/board.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (C) 2007, 2008, 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <watchdog.h>
-#include <net.h>
-#include <mmc.h>
-#include <environment.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int cpu_init(void);
-extern int board_init(void);
-extern int dram_init(void);
-extern int timer_init(void);
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-#ifndef CONFIG_SYS_NO_FLASH
-static int sh_flash_init(void)
-{
-	gd->bd->bi_flashsize = flash_init();
-
-	if (gd->bd->bi_flashsize >= (1024 * 1024))
-		printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
-	else
-		printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024);
-
-	return 0;
-}
-#endif /* CONFIG_SYS_NO_FLASH */
-
-#if defined(CONFIG_CMD_NAND)
-# include <nand.h>
-# define INIT_FUNC_NAND_INIT nand_init,
-#else
-# define INIT_FUNC_NAND_INIT
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_WATCHDOG)
-extern int watchdog_init(void);
-extern int watchdog_disable(void);
-# undef INIT_FUNC_WATCHDOG_INIT
-# define INIT_FUNC_WATCHDOG_INIT	watchdog_init,
-# define WATCHDOG_DISABLE       	watchdog_disable
-#else
-# define INIT_FUNC_WATCHDOG_INIT
-# define WATCHDOG_DISABLE
-#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_CMD_IDE)
-# include <ide.h>
-# define INIT_FUNC_IDE_INIT	ide_init,
-#else
-# define INIT_FUNC_IDE_INIT
-#endif /* CONFIG_CMD_IDE */
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-static int sh_pci_init(void)
-{
-	pci_init();
-	return 0;
-}
-# define INIT_FUNC_PCI_INIT sh_pci_init,
-#else
-# define INIT_FUNC_PCI_INIT
-#endif /* CONFIG_PCI */
-
-static int sh_mem_env_init(void)
-{
-	mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
-			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
-	env_relocate();
-	jumptable_init();
-	return 0;
-}
-
-#if defined(CONFIG_CMD_MMC)
-static int sh_mmc_init(void)
-{
-	puts("MMC:   ");
-	mmc_initialize(gd->bd);
-	return 0;
-}
-#endif
-
-typedef int (init_fnc_t) (void);
-
-init_fnc_t *init_sequence[] =
-{
-	cpu_init,		/* basic cpu dependent setup */
-	board_init,		/* basic board dependent setup */
-	interrupt_init,	/* set up exceptions */
-	env_init,		/* event init */
-	serial_init,	/* SCIF init */
-	INIT_FUNC_WATCHDOG_INIT	/* watchdog init */
-	console_init_f,
-	display_options,
-	checkcpu,
-	checkboard,		/* Check support board */
-	dram_init,		/* SDRAM init */
-	timer_init,		/* SuperH Timer (TCNT0 only) init */
-	sh_mem_env_init,
-#ifndef CONFIG_SYS_NO_FLASH
-	sh_flash_init,	/* Flash memory init*/
-#endif
-	INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
-	INIT_FUNC_PCI_INIT	/* PCI init */
-	stdio_init,
-	console_init_r,
-	interrupt_init,
-#ifdef CONFIG_BOARD_LATE_INIT
-	board_late_init,
-#endif
-#if defined(CONFIG_CMD_MMC)
-	sh_mmc_init,
-#endif
-	NULL			/* Terminate this list */
-};
-
-void sh_generic_init(void)
-{
-	bd_t *bd;
-	init_fnc_t **init_fnc_ptr;
-
-	memset(gd, 0, GENERATED_GBL_DATA_SIZE);
-
-	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
-
-	gd->bd = (bd_t *)(gd + 1);	/* At end of global data */
-	gd->baudrate = CONFIG_BAUDRATE;
-
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
-	bd = gd->bd;
-	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
-	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
-	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
-#endif
-
-	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		WATCHDOG_RESET();
-		if ((*init_fnc_ptr) () != 0)
-			hang();
-	}
-
-#ifdef CONFIG_WATCHDOG
-	/* disable watchdog if environment is set */
-	{
-		char *s = getenv("watchdog");
-		if (s != NULL)
-			if (strncmp(s, "off", 3) == 0)
-				WATCHDOG_DISABLE();
-	}
-#endif /* CONFIG_WATCHDOG*/
-
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-	puts("Net:   ");
-	eth_initialize();
-#endif /* CONFIG_CMD_NET */
-
-	while (1) {
-		WATCHDOG_RESET();
-		main_loop();
-	}
-}
-- 
cgit v0.10.2


From 1c29a382e13af1471282ebff3a74afabea5b8ff8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:31 -0600
Subject: avr32: Drop unused code in u-boot.h
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 8b047ec..7d48e9a 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -6,28 +6,8 @@
 #ifndef __ASM_U_BOOT_H__
 #define __ASM_U_BOOT_H__ 1
 
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-typedef struct bd_info {
-	unsigned char		bi_phy_id[4];
-	unsigned long		bi_board_number;
-	void			*bi_boot_params;
-	struct {
-		unsigned long	start;
-		unsigned long	size;
-	}			bi_dram[CONFIG_NR_DRAM_BANKS];
-	unsigned long		bi_flashstart;
-	unsigned long		bi_flashsize;
-	unsigned long		bi_flashoffset;
-} bd_t;
-
-#define bi_memstart bi_dram[0].start
-#define bi_memsize bi_dram[0].size
-
-#endif
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_AVR32
-- 
cgit v0.10.2


From b977fefcf74700601db37fb5040544bfc16b4237 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:32 -0600
Subject: m68k: Drop unused code in u-boot.h

Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Angelo Dureghello <angelo@sysam.it>

diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 911c0d3..8203844 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -14,47 +14,8 @@
 #ifndef __U_BOOT_H__
 #define __U_BOOT_H__
 
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
-	unsigned long bi_memstart;	/* start of DRAM memory */
-	phys_size_t bi_memsize;		/* size  of DRAM memory in bytes */
-	unsigned long bi_flashstart;	/* start of FLASH memory */
-	unsigned long bi_flashsize;	/* size  of FLASH memory */
-	unsigned long bi_flashoffset;	/* reserved area for startup monitor */
-	unsigned long bi_sramstart;	/* start of SRAM memory */
-	unsigned long bi_sramsize;	/* size  of SRAM memory */
-	unsigned long bi_mbar_base;	/* base of internal registers */
-	unsigned long bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long bi_boot_params;	/* where this board expects params */
-	unsigned short bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long bi_busfreq;	/* Bus Freq, in MHz */
-#ifdef CONFIG_PCI
-	unsigned long bi_pcifreq;	/* pci Freq in MHz */
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
-	unsigned long bi_inpfreq;	/* input Freq in MHz */
-	unsigned long bi_vcofreq;	/* vco Freq in MHz */
-	unsigned long bi_flbfreq;	/* Flexbus Freq in MHz */
-#endif
-} bd_t;
-
-#endif				/* __ASSEMBLY__ */
-
-#endif				/* !CONFIG_SYS_GENERIC_BOARD */
-
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_M68K
-- 
cgit v0.10.2


From 3e085c9946323a6ad17c32150adf67348afeff97 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:33 -0600
Subject: mips: Drop unused code in u-boot.h

Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index 4909a2a..af03e8d 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -15,25 +15,9 @@
 #ifndef _U_BOOT_H_
 #define _U_BOOT_H_	1
 
-#ifdef CONFIG_SYS_GENERIC_BOARD
-
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
 
-#else /* !CONFIG_SYS_GENERIC_BOARD */
-
-typedef struct bd_info {
-	unsigned long	bi_arch_number;	/* unique id for this board */
-	unsigned long	bi_boot_params;	/* where this board expects params */
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size  of FLASH memory */
-	unsigned long	bi_flashoffset;	/* reserved area for startup monitor */
-} bd_t;
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_MIPS
 
-- 
cgit v0.10.2


From 14c67ebaefec6d477603454aa2998c36da40453b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:34 -0600
Subject: powerpc: Drop unused code related to generic board

Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 54793f0..b4c5543 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -83,8 +83,7 @@ _start:
 	 * This function is called when the platform is build with SPL
 	 * support from the main (full-blown) U-Boot. And the GD needs
 	 * to get cleared (again) so that the following generic
-	 * board support code, defined via CONFIG_SYS_GENERIC_BOARD,
-	 * initializes all variables correctly.
+	 * board support code initializes all variables correctly.
 	 */
 	mr	r3, r2		/* parameter 1:	 GD pointer		*/
 	li	r4,0		/* parameter 2:	 value to fill		*/
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 5f5c720..4013a0c 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -449,13 +449,6 @@ cpu_init_f (void)
 	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
 	      PLB4Ax_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
-
-#ifndef CONFIG_SYS_GENERIC_BOARD
-	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	memset((void *)gd, 0, sizeof(gd_t));
-#endif
 }
 
 /*
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 137afce..b432b18 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -760,7 +760,6 @@ _start:
 #endif
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
 	mr	r3, r1
 	bl	board_init_f_alloc_reserve
 	mr	r1, r3
@@ -768,7 +767,6 @@ _start:
 	li	r0,0
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
-#endif
 	li	r3, 0
 	bl	board_init_f
 	/* NOTREACHED - board_init_f() does not return */
@@ -1037,14 +1035,12 @@ _start:
 	GET_GOT			/* initialize GOT access			*/
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
 	mr	r3, r1
 	bl	board_init_f_alloc_reserve
 	mr	r1, r3
 	bl	board_init_f_init_reserve
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
-#endif
 	li	r3, 0
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 	/* NOTREACHED - board_init_f() does not return */
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index a61e998..74b6202 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -14,112 +14,8 @@
 #ifndef __U_BOOT_H__
 #define __U_BOOT_H__
 
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
-	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long	bi_sramstart;	/* start of SRAM memory */
-	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
-	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-	unsigned long	bi_immr_base;	/* base of IMMR register */
-#endif
-#if defined(CONFIG_MPC5xxx)
-	unsigned long	bi_mbar_base;	/* base of internal registers */
-#endif
-#if defined(CONFIG_MPC83xx)
-	unsigned long	bi_immrbar;
-#endif
-	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
-	unsigned long	bi_ip_addr;	/* IP Address */
-	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
-	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
-	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
-	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
-	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
-	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
-#endif
-#if defined(CONFIG_MPC512X)
-	unsigned long	bi_ipsfreq;	/* IPS Bus Freq, in MHz */
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
-	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
-	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
-#endif
-#if defined(CONFIG_405)   || \
-    defined(CONFIG_405GP) || \
-    defined(CONFIG_405EP) || \
-    defined(CONFIG_405EZ) || \
-    defined(CONFIG_405EX) || \
-    defined(CONFIG_440)
-	unsigned char	bi_s_version[4];	/* Version of this structure */
-	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
-	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
-	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
-	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
-	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH2
-	unsigned char	bi_enet2addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH3
-	unsigned char   bi_enet3addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH4
-	unsigned char   bi_enet4addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH5
-	unsigned char   bi_enet5addr[6];	/* OLD: see README.enetaddr */
-#endif
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
-    defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
-	int		bi_iic_fast[2];		/* Use fast i2c mode */
-#endif
-#if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	int		bi_phynum[4];           /* Determines phy mapping */
-	int		bi_phymode[4];          /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
-	int		bi_phynum[2];           /* Determines phy mapping */
-	int		bi_phymode[2];          /* Determines phy mode */
-#else
-	int		bi_phynum[1];           /* Determines phy mapping */
-	int		bi_phymode[1];          /* Determines phy mode */
-#endif
-#endif /* defined(CONFIG_4xx) */
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_PPC
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 05b22bb..3c97476 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -29,11 +29,6 @@ obj-y	+= ticks.o
 obj-y	+= reloc.o
 
 obj-$(CONFIG_BAT_RW) += bat_rw.o
-ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y	+= board.o
-endif
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cache.o
 obj-y	+= extable.o
-- 
cgit v0.10.2


From 9be2e790eb28cbb30fb16a939cb95f82ad73efe5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:35 -0600
Subject: Drop use of CONFIG_SYS_GENERIC_BOARD in U-Boot
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This option is always enabled and is about to be removed. Drop references
to it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/common/Makefile b/common/Makefile
index 0562d5c..1557a04 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -26,8 +26,8 @@ obj-y += bootretry.o
 endif
 
 # boards
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+obj-y += board_f.o
+obj-y += board_r.o
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
 
diff --git a/common/main.c b/common/main.c
index 42bbb50..2116a9e 100644
--- a/common/main.c
+++ b/common/main.c
@@ -47,12 +47,6 @@ void main_loop(void)
 
 	bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
 
-#ifndef CONFIG_SYS_GENERIC_BOARD
-	puts("Warning: Your board does not use generic board. Please read\n");
-	puts("doc/README.generic-board and take action. Boards not\n");
-	puts("upgraded by the late 2014 may break or be removed.\n");
-#endif
-
 #ifdef CONFIG_VERSION_VARIABLE
 	setenv("ver", version_string);  /* set version variable */
 #endif /* CONFIG_VERSION_VARIABLE */
diff --git a/include/watchdog.h b/include/watchdog.h
index 9273fa1..174c894 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -21,8 +21,7 @@
 int init_func_watchdog_reset(void);
 #endif
 
-#if defined(CONFIG_SYS_GENERIC_BOARD) && \
-	(defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG))
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
 #define INIT_FUNC_WATCHDOG_INIT	init_func_watchdog_init,
 #define INIT_FUNC_WATCHDOG_RESET	init_func_watchdog_reset,
 #else
-- 
cgit v0.10.2


From 4c794525d5c662e6b18afe69835da6662c046e08 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:36 -0600
Subject: Drop references to CONFIG_SYS_GENERIC_BOARD in config files

This option is no longer used so need not be enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index dd1329e..cd29734 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -7,6 +7,4 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_BOARD
-
 #endif
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index f3361d0..e6b7953 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -14,7 +14,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 94eb7ac..956c0e2 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -15,7 +15,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index dcb72c9..908d545 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 3e81f0d..6a88901 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index ab1e11d..0ebded6 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index 14e44b0..913256a 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -10,8 +10,6 @@
 /*
  * BOARD/CPU
  */
-#define CONFIG_SYS_GENERIC_BOARD
-
 #define CONFIG_SYS_CLK_FREQ		50000000
 #define CONFIG_SYS_RESET_ADDR		0x00000100
 
-- 
cgit v0.10.2


From 2507854e46654042839bf0dcf0d9a291f60c31cf Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 14 May 2016 18:49:37 -0600
Subject: Drop HAVE_GENERIC_BOARD and SYS_GENERIC_BOARD options
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

These are no longer used. The migration is complete. Drop these options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/Kconfig b/arch/Kconfig
index ec12013..566f044 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1,13 +1,6 @@
 config CREATE_ARCH_SYMLINK
 	bool
 
-config HAVE_GENERIC_BOARD
-	bool
-
-config SYS_GENERIC_BOARD
-	bool
-	depends on HAVE_GENERIC_BOARD
-
 choice
 	prompt "Architecture select"
 	default SANDBOX
@@ -15,57 +8,39 @@ choice
 config ARC
 	bool "ARC architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config ARM
 	bool "ARM architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config AVR32
 	bool "AVR32 architecture"
 	select CREATE_ARCH_SYMLINK
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config BLACKFIN
 	bool "Blackfin architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config MIPS
 	bool "MIPS architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config NDS32
 	bool "NDS32 architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config NIOS2
 	bool "Nios II architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 	select OF_CONTROL
 	select DM
@@ -77,14 +52,10 @@ config OPENRISC
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config SANDBOX
 	bool "Sandbox"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 	select DM
 	select DM_SPI_FLASH
@@ -99,15 +70,12 @@ config SH
 
 config SPARC
 	bool "SPARC architecture"
-	select HAVE_GENERIC_BOARD
 	select CREATE_ARCH_SYMLINK
 
 config X86
 	bool "x86 architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 	select DM
 	select DM_SERIAL
-- 
cgit v0.10.2


From 367d789d87cd562cfe4f28c865dd6d342f595baf Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Sun, 15 May 2016 12:12:07 -0400
Subject: MARVELL: Delete now-superfluous board/Marvell/{common, include} dirs.

With dropping support for some boards and the deletion of some source
files, it appears that both of these directories are now superfluous.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
deleted file mode 100644
index 6cae9ea..0000000
--- a/board/Marvell/common/bootseq.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-(cpu/mpc7xxx/start.S)
-
-start:
-    b boot_cold
-
-start_warm:
-    b boot_warm
-
-
-boot_cold:
-boot_warm:
-    clear bats
-    init l2 (if enabled)
-    init altivec (if enabled)
-    invalidate l2 (if enabled)
-    setup bats (from defines in config_EVB)
-    enable_addr_trans: (if MMU enabled)
-	enable MSR_IR and MSR_DR
-    jump to in_flash
-
-in_flash:
-    enable l1 dcache
-    gal_low_init: (board/evb64260/sdram_init.S)
-	config SDRAM (CFG, TIMING, DECODE)
-	init scratch regs (810 + 814)
-
-	detect DIMM0 (bank 0 only)
-	config SDRAM_PARA0 to 256/512Mbit
-	bl sdram_op_mode
-	detect bank0 width
-	    write scratch reg 810
-	config SDRAM_PARA0 with results
-	config SDRAM_PARA1 with results
-
-	detect DIMM1 (bank 2 only)
-	config SDRAM_PARA2 to 256/512Mbit
-	detect bank2 width
-	    write scratch reg 814
-	config SDRAM_PARA2 with results
-	config SDRAM_PARA3 with results
-
-	setup device bus timings/width
-	setup boot device timings/width
-
-	setup CPU_CONF (0x0)
-	setup cpu master control register 0x160
-	setup PCI0 TIMEOUT
-	setup PCI1 TIMEOUT
-	setup PCI0 BAR
-	setup PCI1 BAR
-
-	setup MPP control 0-3
-	setup GPP level control
-	setup Serial ports multiplex
-
-    setup stack pointer (r1)
-    setup GOT
-    call cpu_init_f
-	debug leds
-    board_init_f: (common/board.c)
-	board_early_init_f:
-	    remap gt regs?
-	    map PCI mem/io
-	    map device space
-	    clear out interrupts
-	init_timebase
-	env_init
-	serial_init
-	console_init_f
-	display_options
-	initdram: (board/evb64260/evb64260.c)
-	    detect memory
-	    for each bank:
-		dram_size()
-		setup PCI slave memory mappings
-		setup SCS
-	setup monitor
-	alloc board info struct
-	init bd struct
-	relocate_code: (cpu/mpc7xxx/start.S)
-	    copy,got,clearbss
-	    board_init_r(bd, dest_addr) (common/board.c)
-		setup bd function pointers
-		trap_init
-		flash_init: (board/evb64260/flash.c)
-		setup bd flash info
-		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
-		    nothing
-		mem_malloc_init
-		malloc_bin_reloc
-		spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
-		env_relocated
-		misc_init_r(bd): (board/evb64260/evb64260.c)
-		    mpsc_init2
diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h
deleted file mode 100644
index a879ea9..0000000
--- a/board/Marvell/common/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
deleted file mode 100644
index 5531f95..0000000
--- a/board/Marvell/common/intel_flash.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
-#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
-#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
-#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST		0xFF		/* reset flash */
-#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
-#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
-#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
-#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
-#define CHIP_CMD_PROG		0x40		/* program word command */
-#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
-#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
-#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
-#define CHIP_STAT_VPPS		0x08		/* VPP Status */
-#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
-#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
-				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
-#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS		128
-#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
-#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS		CHIP_NBLOCKS
-#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS		1		/* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
-				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
-				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
-				    (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
-				    (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
-				    BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
-				    BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o)	((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c
deleted file mode 100644
index 610b411..0000000
--- a/board/Marvell/common/memory.c
+++ /dev/null
@@ -1,1374 +0,0 @@
-/*
- * Copyright - Galileo technology.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-
-#include <common.h>
-#include "../include/core.h"
-#include "../include/memory.h"
-
-/*******************************************************************************
-* memoryGetBankBaseAddress - Returns the base address of a memory bank.
-* DESCRIPTION:
-*       This function returns the base address of one of the SDRAM's memory
-*       banks. There are 4 memory banks and each one represents one DIMM side.
-* INPUT:
-*       MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit Memory bank base address.
-*******************************************************************************/
-static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
-{
-	switch (bank) {
-	case BANK0:
-		return SCS_0_LOW_DECODE_ADDRESS;
-	case BANK1:
-		return SCS_1_LOW_DECODE_ADDRESS;
-	case BANK2:
-		return SCS_2_LOW_DECODE_ADDRESS;
-	case BANK3:
-		return SCS_3_LOW_DECODE_ADDRESS;
-
-	}
-	return SCS_0_LOW_DECODE_ADDRESS;	/* default value */
-}
-
-unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
-{
-	unsigned int base;
-	unsigned int regOffset = memoryGetBankRegOffset (bank);
-
-	GT_REG_READ (regOffset, &base);
-	base = base << 16;	/* MV6436x */
-	return base;
-}
-
-/*******************************************************************************
-* memoryGetDeviceBaseAddress - Returns the base address of a device.
-* DESCRIPTION:
-*       This function returns the base address of a device on the system. There
-*       are 5 possible devices (0 - 4 and one boot device) as defined in
-*       gtMemory.h. Each of the device parameters is maped to one of the CS
-*       (Devices chip selects) base address register.
-* INPUT:
-*       device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit Device base address.
-*
-*******************************************************************************/
-static unsigned int memoryGetDeviceRegOffset (DEVICE device)
-{
-	switch (device) {
-	case DEVICE0:
-		return CS_0_LOW_DECODE_ADDRESS;
-	case DEVICE1:
-		return CS_1_LOW_DECODE_ADDRESS;
-	case DEVICE2:
-		return CS_2_LOW_DECODE_ADDRESS;
-	case DEVICE3:
-		return CS_3_LOW_DECODE_ADDRESS;
-	case BOOT_DEVICE:
-		return BOOTCS_LOW_DECODE_ADDRESS;
-	}
-	return CS_0_LOW_DECODE_ADDRESS;	/* default value */
-}
-
-unsigned int memoryGetDeviceBaseAddress (DEVICE device)
-{
-	unsigned int regBase;
-	unsigned int regOffset = memoryGetDeviceRegOffset (device);
-
-	GT_REG_READ (regOffset, &regBase);
-
-	regBase = regBase << 16;	/* MV6436x */
-	return regBase;
-}
-
-/*******************************************************************************
-* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
-* DESCRIPTION:
-*       This function returns the base address of a PCI window. There are 5
-*       possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
-*       interface as defined in gtMemory.h, used by the CPU's address decoding
-*       mechanism.
-*	New in MV6436x
-* INPUT:
-*       pciWindow - Selects one of the PCI windows as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit PCI window base address.
-*******************************************************************************/
-unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
-{
-	unsigned int baseAddrReg, base;
-
-	switch (pciWindow) {
-	case PCI_0_IO:
-		baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR;  */
-		break;
-	case PCI_0_MEM0:
-		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
-		break;
-	case PCI_0_MEM1:
-		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
-		break;
-	case PCI_0_MEM2:
-		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR;  */
-		break;
-	case PCI_0_MEM3:
-		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR;  */
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR;  */
-		break;
-	case PCI_1_MEM0:
-		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
-		break;
-	case PCI_1_MEM1:
-		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
-		break;
-	case PCI_1_MEM2:
-		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
-		break;
-	case PCI_1_MEM3:
-		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		return 0xffffffff;
-	}
-	GT_REG_READ (baseAddrReg, &base);
-	return (base << 16);
-}
-
-/*******************************************************************************
-* memoryGetBankSize - Returns the size of a memory bank.
-* DESCRIPTION:
-*       This function returns the size of memory bank as described in
-*       'gtMemoryGetBankBaseAddress' function.
-* INPUT:
-*       bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit size memory bank size or 0 for a closed or non populated bank.
-*
-*******************************************************************************/
-unsigned int memoryGetBankSize (MEMORY_BANK bank)
-{
-	unsigned int sizeReg, size;
-	MEMORY_WINDOW window;
-
-	switch (bank) {
-	case BANK0:
-		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/* CS_0_SIZE; */
-		window = CS_0_WINDOW;
-		break;
-	case BANK1:
-		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/* CS_1_SIZE; */
-		window = CS_1_WINDOW;
-		break;
-	case BANK2:
-		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/* CS_2_SIZE; */
-		window = CS_2_WINDOW;
-		break;
-	case BANK3:
-		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/* CS_3_SIZE; */
-		window = CS_3_WINDOW;
-		break;
-	default:
-		return 0;
-		break;
-	}
-	/* If the window is closed, a size of 0 is returned */
-	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
-		return 0;
-	GT_REG_READ (sizeReg, &size);
-	size = ((size << 16) | 0xffff) + 1;
-	return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceSize - Returns the size of a device memory space.
-* DESCRIPTION:
-*       This function returns the memory space size of a given device.
-* INPUT:
-*       device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit size of a device memory space.
-*******************************************************************************/
-unsigned int memoryGetDeviceSize (DEVICE device)
-{
-	unsigned int sizeReg, size;
-	MEMORY_WINDOW window;
-
-	switch (device) {
-	case DEVICE0:
-		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
-		window = DEVCS_0_WINDOW;
-		break;
-	case DEVICE1:
-		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
-		window = DEVCS_1_WINDOW;
-		break;
-	case DEVICE2:
-		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
-		window = DEVCS_2_WINDOW;
-		break;
-	case DEVICE3:
-		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
-		window = DEVCS_3_WINDOW;
-		break;
-	case BOOT_DEVICE:
-		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
-		window = BOOT_CS_WINDOW;
-		break;
-	default:
-		return 0;
-		break;
-	}
-	/* If the window is closed, a size of 0 is returned */
-	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
-		return 0;
-	GT_REG_READ (sizeReg, &size);
-	size = ((size << 16) | 0xffff) + 1;
-	return size;
-}
-
-/*******************************************************************************
-* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
-* DESCRIPTION:
-*       This function returns the size of a PCI window.
-* INPUT:
-*       pciWindow - Selects one of the PCI memory windows as defined in
-*       Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit size of a PCI memory window.
-*******************************************************************************/
-unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
-{
-	unsigned int sizeReg, size;
-
-	switch (pciWindow) {
-	case PCI_0_IO:
-		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
-		break;
-	case PCI_0_MEM0:
-		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
-		break;
-	case PCI_0_MEM1:
-		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
-		break;
-	case PCI_0_MEM2:
-		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
-		break;
-	case PCI_0_MEM3:
-		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
-		break;
-	case PCI_1_MEM0:
-		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
-		break;
-	case PCI_1_MEM1:
-		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE;  */
-		break;
-	case PCI_1_MEM2:
-		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE;  */
-		break;
-	case PCI_1_MEM3:
-		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		return 0x0;
-	}
-	/* If the memory window is disabled, retrun size = 0 */
-	if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
-	    == MEM_WINDOW_DISABLED)
-		return 0;
-	GT_REG_READ (sizeReg, &size);
-	size = ((size << 16) | 0xffff) + 1;
-	return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceWidth - Returns the width of a given device.
-* DESCRIPTION:
-*       The MV's device interface supports up to 32 Bit wide devices. A device
-*       can have a  1, 2, 4 or 8 Bytes data width. This function returns the
-*       width of a device as defined by the user or the operating system.
-* INPUT:
-*       device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
-*******************************************************************************/
-unsigned int memoryGetDeviceWidth (DEVICE device)
-{
-	unsigned int width;
-	unsigned int regValue;
-
-	GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, &regValue);
-	width = (regValue & (BIT20 | BIT21)) >> 20;
-	return (BIT0 << width);
-}
-
-/*******************************************************************************
-* memoryMapBank - Set new base address and size for one of the memory
-*                         banks.
-*
-* DESCRIPTION:
-*       The CPU interface address decoding map consists of 21 address windows
-*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-*       space. Each address window is defined by two registers - base and size.
-*       The CPU address is compared with the values in the various CPU windows
-*       until a match is found and the address is than targeted to that window.
-*       This function sets new base and size for one the memory banks
-*       (CS0 - CS3). It is the programmer`s responsibility to make sure that
-*       there are no conflicts with other memory spaces. When two memory spaces
-*       overlap, the MV's behavior is not defined .If a bank needs to be closed,
-*       set the 'bankLength' parameter size to 0x0.
-*
-* INPUT:
-*       bank      - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
-*       bankBase  - The memory bank base address.
-*       bankLength  - The memory bank size. This function will decrement the
-*                   'bankLength' parameter by one and then check if the size is
-*                   valid. A valid size must be programed from LSB to MSB as
-*                   sequence of '1's followed by sequence of '0's.
-*                   To close a memory window simply set the size to 0.
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-* OUTPUT:
-*       None.
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
-		    unsigned int bankLength)
-{
-	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/*    PCI_INTERNAL_BAR pciBAR; */
-
-	switch (bank) {
-	case BANK0:
-		baseReg = SCS_0_LOW_DECODE_ADDRESS;	/*CS_0_BASE_ADDR; */
-		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/*CS_0_SIZE; */
-/*        pciBAR = PCI_CS0_BAR; */
-		break;
-	case BANK1:
-		baseReg = SCS_1_LOW_DECODE_ADDRESS;	/*CS_1_BASE_ADDR; */
-		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/*CS_1_SIZE; */
-		/*        pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
-		break;
-	case BANK2:
-		baseReg = SCS_2_LOW_DECODE_ADDRESS;	/*CS_2_BASE_ADDR; */
-		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/*CS_2_SIZE; */
-/*        pciBAR = PCI_CS2_BAR;*/
-		break;
-	case BANK3:
-		baseReg = SCS_3_LOW_DECODE_ADDRESS;	/*CS_3_BASE_ADDR; */
-		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/*CS_3_SIZE; */
-/*        pciBAR = PCI_CS3_BAR; */
-		break;
-	default:
-		return false;
-	}
-	/* If the size is 0, the window will be disabled */
-	if (bankLength == 0) {
-		MemoryDisableWindow (CS_0_WINDOW << bank);
-		/* Disable the BAR from the PCI slave side */
-/*        gtPci0DisableInternalBAR(pciBAR); */
-/*        gtPci1DisableInternalBAR(pciBAR); */
-		return true;
-	}
-	/* The base address must be aligned to the size */
-	if ((bankBase % bankLength) != 0) {
-		return false;
-	}
-	if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
-		newBase = bankBase >> 16;
-		newSize = bankLength >> 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = newSize - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid	 */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-#ifdef DEBUG
-		{
-			unsigned int oldBase, oldSize;
-
-			GT_REG_READ (baseReg, &oldBase);
-			GT_REG_READ (sizeReg + 8, &oldSize);
-
-			printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
-				bank, oldBase, oldSize, newBase, newSize);
-		}
-#endif
-		/* writing the new values */
-		GT_REG_WRITE (baseReg, newBase);
-		GT_REG_WRITE (sizeReg, newSize - 1);
-		/* Enable back the window */
-		MemoryEnableWindow (CS_0_WINDOW << bank);
-		/* Enable the BAR from the PCI slave side */
-/*        gtPci0EnableInternalBAR(pciBAR); */
-/*        gtPci1EnableInternalBAR(pciBAR); */
-		return true;
-	}
-	return false;
-}
-
-
-/*******************************************************************************
-* memoryMapDeviceSpace - Set new base address and size for one of the device
-*                           windows.
-*
-* DESCRIPTION:
-*       The CPU interface address decoding map consists of 21 address windows
-*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-*       space. Each address window is defined by two registers - base and size.
-*       The CPU address is compared with the values in the various CPU windows
-*       until a match is found and the address is than targeted to that window.
-*       This function sets new base and size for one the device windows
-*       (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
-*       that there are no conflicts with other memory spaces. When two memory
-*       spaces overlap, the MV's behavior is not defined .If a device window
-*       needs to be closed, set the 'deviceLength' parameter size to 0x0.
-*
-* INPUT:
-*       device           - One of the device windows (DEV_CS0-DEV_CS3) as
-*                          defined in gtMemory.h.
-*       deviceBase - The device window base address.
-*       deviceLength - The device window size. This function will decrement
-*                          the 'deviceLength' parameter by one and then
-*                          check if the size is valid. A valid size must be
-*                          programed from LSB to MSB as sequence of '1's
-*                          followed by sequence of '0's.
-*                          To close a memory window simply set the size to 0.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
-			   unsigned int deviceLength)
-{
-	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/*    PCI_INTERNAL_BAR pciBAR;*/
-
-	switch (device) {
-	case DEVICE0:
-		baseReg = CS_0_LOW_DECODE_ADDRESS;	/*DEV_CS0_BASE_ADDR; */
-		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
-/*        pciBAR = PCI_DEV_CS0_BAR; */
-		break;
-	case DEVICE1:
-		baseReg = CS_1_LOW_DECODE_ADDRESS;	/*DEV_CS1_BASE_ADDR; */
-		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
-/*        pciBAR = PCI_DEV_CS1_BAR; */
-		break;
-	case DEVICE2:
-		baseReg = CS_2_LOW_DECODE_ADDRESS;	/*DEV_CS2_BASE_ADDR; */
-		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
-/*        pciBAR = PCI_DEV_CS2_BAR; */
-		break;
-	case DEVICE3:
-		baseReg = CS_3_LOW_DECODE_ADDRESS;	/*DEV_CS3_BASE_ADDR; */
-		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
-/*        pciBAR = PCI_DEV_CS3_BAR; */
-		break;
-	case BOOT_DEVICE:
-		baseReg = BOOTCS_LOW_DECODE_ADDRESS;	/*BOOTCS_BASE_ADDR; */
-		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
-/*        pciBAR = PCI_BOOT_CS_BAR; */
-		break;
-	default:
-		return false;
-	}
-	if (deviceLength == 0) {
-		MemoryDisableWindow (DEVCS_0_WINDOW << device);
-		/* Disable the BAR from the PCI slave side */
-/*        gtPci0DisableInternalBAR(pciBAR); */
-/*        gtPci1DisableInternalBAR(pciBAR); */
-		return true;
-	}
-	/* The base address must be aligned to the size */
-	if ((deviceBase % deviceLength) != 0) {
-		return false;
-	}
-	if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
-		newBase = deviceBase >> 16;
-		newSize = deviceLength >> 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = newSize - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid       */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-		/* writing the new values */
-		GT_REG_WRITE (baseReg, newBase);
-		GT_REG_WRITE (sizeReg, newSize - 1);
-		MemoryEnableWindow (DEVCS_0_WINDOW << device);
-		/* Enable the BAR from the PCI slave side */
-/*        gtPci0EnableInternalBAR(pciBAR); */
-/*        gtPci1EnableInternalBAR(pciBAR); */
-		return true;
-	}
-	return false;
-}
-
-/*******************************************************************************
-* MemorySetPciWindow - Set new base address and size for one of the PCI
-*                        windows.
-*
-* DESCRIPTION:
-*       The CPU interface address decoding map consists of 21 address windows
-*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-*       space. Each address window is defined by two registers - base and size.
-*       The CPU address is compared with the values in the various CPU windows
-*       until a match is found and the address is than targeted to that window.
-*       This function sets new base and size for one the PCI windows
-*       (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
-*       that there are no conflicts with other memory spaces. When two memory
-*       spaces overlap, the MV's behavior is not defined. If a PCI window
-*       needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
-*
-* INPUT:
-*       pciWindow     - One of the PCI windows as defined in gtMemory.h.
-*       pciWindowBase - The PCI window base address.
-*       pciWindowSize - The PCI window size. This function will decrement the
-*                       'pciWindowSize' parameter by one and then check if the
-*                       size is valid. A valid size must be programed from LSB
-*                       to MSB as sequence of '1's followed by sequence of '0's.
-*                       To close a memory window simply set the size to 0.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
-			 unsigned int pciWindowSize)
-{
-	unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
-
-	switch (pciWindow) {
-	case PCI_0_IO:
-		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR; */
-		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
-		break;
-	case PCI_0_MEM0:
-		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
-		break;
-	case PCI_0_MEM1:
-		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
-		break;
-	case PCI_0_MEM2:
-		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
-		break;
-	case PCI_0_MEM3:
-		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR; */
-		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
-		break;
-	case PCI_1_MEM0:
-		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
-		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
-		break;
-	case PCI_1_MEM1:
-		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
-		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE; */
-		break;
-	case PCI_1_MEM2:
-		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
-		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE; */
-		break;
-	case PCI_1_MEM3:
-		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
-		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		return false;
-	}
-	if (pciWindowSize == 0) {
-		MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
-		return true;
-	}
-	/* The base address must be aligned to the size */
-	if ((pciWindowBase % pciWindowSize) != 0) {
-		return false;
-	}
-	if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
-		pciWindowBase >>= 16;
-		pciWindowSize >>= 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = pciWindowSize - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid       */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-		GT_REG_WRITE (sizeReg, pciWindowSize - 1);
-		GT_REG_READ (baseAddrReg, &currentLow);
-		pciWindowBase =
-			(pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
-		GT_REG_WRITE (baseAddrReg, pciWindowBase);
-		MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
-		return true;
-	}
-	return false;
-}
-
-/*******************************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internal
-*                                  registers memory space.
-*
-* DESCRIPTION:
-*       This function set new base address for the internal registers memory
-*       space (the size is fixed and cannot be modified). The function does not
-*       handle overlapping with other memory spaces, it is the programer's
-*       responsibility to ensure that overlapping does not occur.
-*       When two memory spaces overlap, the MV's behavior is not defined.
-*
-* INPUT:
-*       internalRegBase - new base address for the internal registers memory
-*                         space.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*        true on success, false on failure
-*
-*******************************************************************************/
-/********************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internals
-*                                   registers.
-*
-* INPUTS:  unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
-{
-	unsigned int currentValue;
-	unsigned int internalValue = internalRegBase;
-
-	internalRegBase = (internalRegBase >> 16);
-	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
-	internalRegBase = (currentValue & 0xff000000) | internalRegBase;
-	GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
-	/* initializing also the global variable 'internalRegBaseAddr' */
-/*    gtInternalRegBaseAddr = internalValue; */
-	INTERNAL_REG_BASE_ADDR = internalValue;
-	return true;
-}
-
-/*******************************************************************************
-* memoryGetInternalRegistersSpace - Returns the internal registers Base
-*                                     address.
-*
-* DESCRIPTION:
-*       This function returns the base address of  the internal registers
-*       memory space .
-*
-* INPUT:
-*       None.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       32 bit base address of the internal registers memory space.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalRegistersSpace (void)
-{
-	unsigned int currentValue = 0;
-
-	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
-	return ((currentValue & 0x000fffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
-*
-* DESCRIPTION:
-*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-*       funcnion return the SRAM's base address.
-* INPUT:
-*       None.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit SRAM's base address.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalSramBaseAddr (void)
-{
-	return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
-*
-* DESCRIPTION:
-*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-*       function sets a new base address to the SRAM .
-* INPUT:
-*       sramBaseAddress - The SRAM's base address.
-* OUTPUT:
-*       None.
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
-{
-	GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
-}
-
-/*******************************************************************************
-* memorySetProtectRegion - Set protection mode for one of the 8 regions.
-*
-* DESCRIPTION:
-*       The CPU interface supports configurable access protection. This includes
-*       up to eight address ranges defined to a different protection type :
-*       whether the address range is cacheable or not, whether it is writable or
-*       not , and whether it is accessible or not. A Low and High registers
-*       define each window while the minimum address range of each window is
-*       1Mbyte. An address driven by the CPU, in addition to the address
-*       decoding and remapping process, is compared against the eight Access
-*       Protection Low/High registers , if an address matches one of the windows
-*       , the MV device checks the transaction type against the protection bits
-*       defined in CPU Access Protection register, to determine if the access is
-*       allowed. This function set a protection mode to one of the 8 possible
-*       regions.
-*      NOTE:
-*       The CPU address windows are restricted to a size of  2 power n and the
-*       start address must be aligned to the window size. For example, if using
-*       a 16 MB window, the start address bits [23:0] must be 0.The MV's
-*       internal registers space is not protected, even if the access protection
-*       windows contain this space.
-*
-* INPUT:
-*       region - selects which region to be configured. The values defined in
-*                gtMemory.h:
-*
-*                 - MEM_REGION0
-*                 - MEM_REGION1
-*                 - etc.
-*
-*       memAccess - Allows or forbids access (read or write ) to the region. The
-*                   values defined in gtMemory.h:
-*
-*                    - MEM_ACCESS_ALLOWED
-*                    - MEM_ACCESS_FORBIDEN
-*
-*       memWrite - CPU write protection to the region. The values defined in
-*                  gtMemory.h:
-*
-*                   - MEM_WRITE_ALLOWED
-*                   - MEM_WRITE_FORBIDEN
-*
-*       cacheProtection - Defines whether caching the region is allowed or not.
-*                         The values defined in gtMemory.h:
-*
-*                          - MEM_CACHE_ALLOWED
-*                          - MEM_CACHE_FORBIDEN
-*
-*       baseAddress - the region's base Address.
-*       regionSize  - The region's size. This function will decrement the
-*                     'regionSize' parameter by one and then check if the size
-*                     is valid. A valid size must be programed from LSB to MSB
-*                     as sequence of '1's followed by sequence of '0's.
-*                     To close a memory window simply set the size to 0.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
-			     MEMORY_ACCESS memAccess,
-			     MEMORY_ACCESS_WRITE memWrite,
-			     MEMORY_CACHE_PROTECT cacheProtection,
-			     unsigned int baseAddress, unsigned int size)
-{
-	unsigned int dataForReg, temp, rShift;
-
-	if (size == 0) {
-		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
-			      0x0);
-		return true;
-	}
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return false;
-	}
-	if (size >= MINIMUM_ACCESS_WIN_SIZE) {
-		baseAddress = ((baseAddress >> 16) & 0xfffff);
-		dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
-			((memWrite << 21) & BIT21) | ((cacheProtection << 22)
-						      & BIT22) | BIT31;
-		GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
-			      dataForReg);
-		size >>= 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = size - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid       */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
-			      size - 1);
-		return true;
-	}
-	return false;
-}
-
-/*******************************************************************************
-* gtMemoryDisableProtectRegion - Disable a protected window.
-*
-* DESCRIPTION:
-*       This function disable a protected window set by
-*       'gtMemorySetProtectRegion' function.
-*
-* INPUT:
-*       window - one of the 4 windows ( defined in gtMemory.h ).
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
-{
-	RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
-			BIT31);
-}
-
-/*******************************************************************************
-* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
-*
-* DESCRIPTION:
-*       In addition to the address decoding mechanism, the CPU has an address
-*       remapping mechanism to be used by every PCI decoding window. Each PCI
-*       window can be remaped to a desired address target according to the remap
-*       value within the remap register. The address remapping is useful when a
-*       CPU address range must be reallocated to a different location on the
-*       PCI bus. Also, it enables CPU access to a PCI agent located above the
-*       4Gbyte space. On system boot, each of the PCI memory spaces is maped to
-*       a defualt value (see CPU interface section in the MV spec for the
-*       default values). The remap mechanism does not always produce the desired
-*       address on the PCI bus because of the remap mechanism way of working
-*       (to fully understand why, please see the 'Address Remapping' section in
-*       the MV's spec). Therefor, this function sets a desired remap value to
-*       one of the PCI memory windows and return the effective address that
-*       should be used when exiting the PCI memory window. You should ALWAYS use
-*       the returned value by this function when remapping a PCI window and
-*       exiting it. If for example the base address of PCI0 memory 0 is
-*       0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
-*       the function will return the value of 0x91000000 that MUST
-*       be used to exit this memory window in order to achive the deisred
-*       remapping.
-*
-* INPUT:
-*       memoryWindow   - One of the PCI memory windows as defined in Memory.h
-*       remapValueLow  - The low remap value.
-*       remapValueHigh - The high remap value.
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       The effective base address to exit the PCI, or 0xffffffff if one of the
-*       parameters is erroneous or the effective base address is higher the top
-*       decode value.
-*
-*******************************************************************************/
-unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
-				     unsigned int remapValueHigh,
-				     unsigned int remapValueLow)
-{
-	unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
-	unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
-	unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
-
-	/* Initializing the base and size variables of the PCI
-	   memory windows */
-	switch (memoryWindow) {
-	case PCI_0_IO:
-		pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_IO_SIZE;
-		remapRegLow = PCI_0_IO_ADDR_REMAP;
-		remapRegHigh = PCI_0_IO_ADDR_REMAP;
-		break;
-	case PCI_0_MEM0:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
-		remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
-		break;
-	case PCI_0_MEM1:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
-		remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
-		break;
-	case PCI_0_MEM2:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
-		remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
-		break;
-	case PCI_0_MEM3:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
-		remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_IO_SIZE;
-		remapRegLow = PCI_1_IO_ADDR_REMAP;
-		remapRegHigh = PCI_1_IO_ADDR_REMAP;
-		break;
-	case PCI_1_MEM0:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
-		remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
-		break;
-	case PCI_1_MEM1:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
-		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
-		break;
-	case PCI_1_MEM2:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
-		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
-		break;
-	case PCI_1_MEM3:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
-		remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		/* Retrun an invalid effective base address */
-		return 0xffffffff;
-	}
-	/* Writing the remap value to the remap regisers */
-	GT_REG_WRITE (remapRegHigh, remapValueHigh);
-	GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
-	/* Reading the values from the base address and size registers */
-	baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
-	windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
-	/* Start calculating the effective Base Address */
-	effectiveBaseAddress = baseAddrValue << 16;
-	/* The effective base address will be combined from the chopped (if any)
-	   remap value (according to the size value and remap mechanism) and the
-	   window's base address */
-	effectiveBaseAddress |=
-		(((windowSizeValue << 16) | 0xffff) & remapValueLow);
-	/* If the effectiveBaseAddress exceed the window boundaries return an
-	   invalid value. */
-	if (effectiveBaseAddress >
-	    ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
-		return 0xffffffff;
-	return effectiveBaseAddress;
-}
-
-/********************************************************************
-* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
-*                            supports Cache Coherency.
-*
-*
-* Inputs: SNOOP_REGION region - One of the four regions.
-*         SNOOP_TYPE snoopType - There is four optional Types:
-*                               1. No Snoop.
-*                               2. Snoop to WT region.
-*                               3. Snoop to WB region.
-*                               4. Snoop & Invalidate to WB region.
-*         unsigned int baseAddress - Base Address of this region.
-*         unsigned int topAddress - Top Address of this region.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-/* evb6260 code */
-#if 0
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
-			      MEMORY_SNOOP_TYPE snoopType,
-			      unsigned int baseAddress,
-			      unsigned int regionLength)
-{
-    unsigned int snoopXbaseAddress;
-    unsigned int snoopXtopAddress;
-    unsigned int data;
-    unsigned int snoopHigh = baseAddress + regionLength;
-
-    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
-	return false;
-    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
-    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
-				 if(regionLength == 0) /* closing the region */
-    {
-	GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
-	GT_REG_WRITE(snoopXtopAddress,0);
-	return true;
-    }
-    baseAddress = baseAddress & 0xffff0000;
-    data = (baseAddress >> 16) | snoopType << 16;
-    GT_REG_WRITE(snoopXbaseAddress,data);
-    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
-    return true;
-}
-#endif
-
-/********************************************************************
-* memoryRemapAddress - This fubction used for address remapping.
-*
-*
-* Inputs: regOffset: remap register
-*         remapValue :
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*
-* Not needed function To_do !!!!
-*********************************************************************/
-bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
-{
-	unsigned int valueForReg;
-
-	valueForReg = (remapValue & 0xfff00000) >> 20;
-	GT_REG_WRITE (remapReg, valueForReg);
-	return true;
-}
-
-/*******************************************************************************
-* memoryGetDeviceParam - Extract the device parameters from the device bank
-*                          parameters register.
-*
-* DESCRIPTION:
-*       To allow interfacing with very slow devices and fast synchronous SRAMs,
-*       each device can be programed to different timing parameters. Each bank
-*       has its own parameters register. Bank width can be programmed to 8, 16,
-*       or 32-bits. Bank timing parameters can be programmed to support
-*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-*       Controllers). The MV allows you to set timing parameters and width for
-*       each device through parameters register .
-*       This function extracts the parameters described from the Device Bank
-*       parameters register and fills the given 'deviceParam' (defined in
-*       gtMemory.h) structure with the read data.
-*
-* INPUT:
-*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
-*                      Memory.h).For details about each structure field please
-*                      see the device timing parameter section in the MV
-*                      datasheet.
-*       deviceNum  -   Select on of the five device banks (defined in
-*                      Memory.h) :
-*
-*                       - DEVICE0
-*                       - DEVICE1
-*                       - DEVICE2
-*                       - etc.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memoryGetDeviceParam - This function used for getting device parameters from
-*                        DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
-*                  PARAMETERS REGISTER
-*                - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-
-bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
-	unsigned int valueOfReg;
-	unsigned int calcData;
-
-	if (deviceNum > 4)
-		return false;
-	GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
-	calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
-	deviceParam->turnOff = calcData;	/* Turn Off */
-
-	calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
-	deviceParam->acc2First = calcData;	/* Access To First */
-
-	calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
-	deviceParam->acc2Next = calcData;	/* Access To Next */
-
-	calcData =
-		((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
-	deviceParam->ale2Wr = calcData;	/* Ale To Write */
-
-	calcData = ((0x1c000 & valueOfReg) >> 14) +
-		((BIT26 & valueOfReg) >> 23);
-	deviceParam->wrLow = calcData;	/* Write Active */
-
-	calcData = ((0xe0000 & valueOfReg) >> 17) +
-		((BIT27 & valueOfReg) >> 24);
-	deviceParam->wrHigh = calcData;	/* Write High */
-
-	calcData = ((0x300000 & valueOfReg) >> 20);
-	deviceParam->deviceWidth = (BIT0 << calcData);	/* In bytes */
-	calcData = ((0x30000000 & valueOfReg) >> 28);
-	deviceParam->badrSkew = calcData;	/* Cycles gap between BAdr
-						   toggle to read data sample. */
-	calcData = ((0x40000000 & valueOfReg) >> 30);
-	deviceParam->DPEn = calcData;	/*  Data Parity enable  */
-	return true;
-}
-
-/*******************************************************************************
-* memorySetDeviceParam - Set new parameters for a device.
-*
-*
-* DESCRIPTION:
-*       To allow interfacing with very slow devices and fast synchronous SRAMs,
-*       each device can be programed to different timing parameters. Each bank
-*       has its own parameters register. Bank width can be programmed to 8, 16,
-*       or 32-bits. Bank timing parameters can be programmed to support
-*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-*       Controllers). The MV allows you to set timing parameters and width for
-*       each device through parameters register. This function set new
-*       parameters to a device Bank from the delivered structure 'deviceParam'
-*       (defined in gtMemory.h). The structure must be initialized with data
-*       prior to the use of these function.
-*
-* INPUT:
-*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
-*                      Memory.h).For details about each structure field please
-*                      see the device timing parameter section in the MV
-*                      datasheet.
-*       deviceNum  -   Select on of the five device banks (defined in
-*                      Memory.h) :
-*
-*                       - DEVICE0
-*                       - DEVICE1
-*                       - DEVICE2
-*                       - etc.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memorySetDeviceParam - This function used for setting device parameters to
-*                        DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
-*                  PARAMETERS REGISTER
-*                - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
-	unsigned int valueForReg;
-
-	if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
-	    (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
-	    (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
-	    (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
-		return false;
-	}
-	valueForReg = (((deviceParam->turnOff) & 0x7) |
-		       (((deviceParam->turnOff) & 0x8) << 19) |
-		       (((deviceParam->acc2First) & 0xf) << 3) |
-		       (((deviceParam->acc2First) & 0x10) << 19) |
-		       (((deviceParam->acc2Next) & 0xf) << 7) |
-		       (((deviceParam->acc2Next) & 0x10) << 20) |
-		       (((deviceParam->ale2Wr) & 0x7) << 11) |
-		       (((deviceParam->ale2Wr) & 0xf) << 22) |
-		       (((deviceParam->wrLow) & 0x7) << 14) |
-		       (((deviceParam->wrLow) & 0xf) << 23) |
-		       (((deviceParam->wrHigh) & 0x7) << 17) |
-		       (((deviceParam->wrHigh) & 0xf) << 24) |
-		       (((deviceParam->badrSkew) & 0x3) << 28) |
-		       (((deviceParam->DPEn) & 0x1) << 30));
-
-	/* insert the device width: */
-	switch (deviceParam->deviceWidth) {
-	case 1:
-		valueForReg = valueForReg | _8BIT;
-		break;
-	case 2:
-		valueForReg = valueForReg | _16BIT;
-		break;
-	case 4:
-		valueForReg = valueForReg | _32BIT;
-		break;
-	default:
-		valueForReg = valueForReg | _8BIT;
-		break;
-	}
-	GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
-	return true;
-}
-
-/*******************************************************************************
-* MemoryDisableWindow - Disable a memory space by the disable bit.
-* DESCRIPTION:
-*       This function disables one of the 21 availiable windows dedicated for
-*       the CPU decoding mechanism. Its possible to combine several windows with
-*       the OR command.
-* INPUT:
-*       window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-*       None.
-* RETURN:
-*       None.
-*******************************************************************************/
-void MemoryDisableWindow (MEMORY_WINDOW window)
-{
-	SET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryEnableWindow - Enable a memory space that was disabled by
-*                       'MemoryDisableWindow'.
-* DESCRIPTION:
-*       This function enables one of the 21 availiable windows dedicated for the
-*       CPU decoding mechanism. Its possible to combine several windows with the
-*       OR command.
-* INPUT:
-*       window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-*       None.
-* RETURN:
-*       None.
-*******************************************************************************/
-void MemoryEnableWindow (MEMORY_WINDOW window)
-{
-	RESET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryGetMemWindowStatus - This function check whether the memory window is
-*                              disabled or not.
-* DESCRIPTION:
-*       This function checks if the given memory window is closed .
-* INPUT:
-*       window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-*       None.
-* RETURN:
-*       true for a closed window, false otherwise .
-*******************************************************************************/
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
-{
-	if (GTREGREAD (BASE_ADDR_ENABLE) & window)
-		return MEM_WINDOW_DISABLED;
-	return MEM_WINDOW_ENABLED;
-}
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
deleted file mode 100644
index 7839b68..0000000
--- a/board/Marvell/common/ns16550.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- *
- * further modified by Josh Huber <huber@mclx.com> to support
- * the DUART on the Galileo Eval board. (db64360)
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-#ifdef ZUMA_NTL
-/* no 16550 device */
-#else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
-	(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
-};
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
-	volatile struct NS16550 *com_port;
-
-	com_port = (struct NS16550 *) COM_PORTS[chan];
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
-
-	/* Clear & enable FIFOs */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-	return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
-
-	/* Clear & enable FIFOs */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
-	while ((com_port->lsr & LSR_THRE) == 0);
-	com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
-	while ((com_port->lsr & LSR_DR) == 0);
-	return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
-	return ((com_port->lsr & LSR_DR) != 0);
-}
-#endif
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
deleted file mode 100644
index 9306381..0000000
--- a/board/Marvell/common/ns16550.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * further modified to support the DUART in the Galileo eval board
- * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- */
-
-#ifndef __NS16550_H__
-#define __NS16550_H__
-
-/* the padding is necessary because on the galileo board the UART is
-   wired in with the 3 address lines shifted over by 2 bits */
-struct NS16550
-{
-	unsigned char rbr;  /* 0 = 0-3*/
-	int pad1:24;
-
-	unsigned char ier;  /* 1 = 4-7*/
-	int pad2:24;
-
-	unsigned char fcr;  /* 2 = 8-b*/
-	int pad3:24;
-
-	unsigned char lcr;  /* 3 = c-f*/
-	int pad4:24;
-
-	unsigned char mcr;  /* 4 = 10-13*/
-	int pad5:24;
-
-	unsigned char lsr;  /* 5 = 14-17*/
-	int pad6:24;
-
-	unsigned char msr;  /* 6 =18-1b*/
-	int pad7:24;
-
-	unsigned char scr;  /* 7 =1c-1f*/
-	int pad8:24;
-} __attribute__ ((packed));
-
-/* aliases */
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-#define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*receiver soft reset*/
-#define FCR_TXSR        0x04    /*transmitter soft reset*/
-
-
-#define MCR_DTR         0x01
-#define MCR_RTS         0x02
-#define MCR_DMA_EN      0x04
-#define MCR_TX_DFR      0x08
-
-
-#define LCR_WLS_MSK 0x03    /* character length slect mask*/
-#define LCR_WLS_5   0x00    /* 5 bit character length */
-#define LCR_WLS_6   0x01    /* 6 bit character length */
-#define LCR_WLS_7   0x02    /* 7 bit character length */
-#define LCR_WLS_8   0x03    /* 8 bit character length */
-#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08    /* Parity eneble*/
-#define LCR_EPS     0x10    /* Even Parity Select*/
-#define LCR_STKP    0x20    /* Stick Parity*/
-#define LCR_SBRK    0x40    /* Set Break*/
-#define LCR_BKSE    0x80    /* Bank select enable*/
-
-#define LSR_DR      0x01    /* Data ready */
-#define LSR_OE      0x02    /* Overrun */
-#define LSR_PE      0x04    /* Parity error */
-#define LSR_FE      0x08    /* Framing error */
-#define LSR_BI      0x10    /* Break */
-#define LSR_THRE    0x20    /* Xmit holding register empty */
-#define LSR_TEMT    0x40    /* Xmitter empty */
-#define LSR_ERR     0x80    /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1     0x03
-
-
-#define COM1 0x03F8
-#define COM2 0x02F8
-
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
-typedef struct NS16550 *NS16550_t;
-
-extern const NS16550_t COM_PORTS[];
-
-#endif
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
deleted file mode 100644
index 432aa06..0000000
--- a/board/Marvell/common/serial.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../include/memory.h"
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_MPSC
-static int marvell_serial_init(void)
-{
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-	int clock_divisor = 230400 / gd->baudrate;
-#endif
-
-	mpsc_init (gd->baudrate);
-
-	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CONFIG_SYS_INIT_CHAN1
-	NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
-	NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-	return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
-	if (c == '\n')
-		mpsc_putchar ('\r');
-
-	mpsc_putchar (c);
-}
-
-static int marvell_serial_getc(void)
-{
-	return mpsc_getchar ();
-}
-
-static int marvell_serial_tstc(void)
-{
-	return mpsc_test_char ();
-}
-
-static void marvell_serial_setbrg(void)
-{
-	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else  /* ! CONFIG_MPSC */
-
-static int marvell_serial_init(void)
-{
-	int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
-	(void) NS16550_init (0, clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
-	(void) NS16550_init (1, clock_divisor);
-#endif
-	return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
-	if (c == '\n')
-		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
-	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-static int marvell_serial_getc(void)
-{
-	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static int marvell_serial_tstc(void)
-{
-	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static void marvell_serial_setbrg(void)
-{
-	int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
-	NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
-	NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-static struct serial_device marvell_serial_drv = {
-	.name	= "marvell_serial",
-	.start	= marvell_serial_init,
-	.stop	= NULL,
-	.setbrg	= marvell_serial_setbrg,
-	.putc	= marvell_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= marvell_serial_getc,
-	.tstc	= marvell_serial_tstc,
-};
-
-void marvell_serial_initialize(void)
-{
-	serial_register(&marvell_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &marvell_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h
deleted file mode 100644
index 0947b6e..0000000
--- a/board/Marvell/include/memory.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY	0xffffffff
-#define PARITY_SUPPORT	0x40000000
-#define MINIMUM_MEM_BANK_SIZE		0x10000
-#define MINIMUM_DEVICE_WINDOW_SIZE	0x10000
-#define MINIMUM_PCI_WINDOW_SIZE		0x10000
-#define MINIMUM_ACCESS_WIN_SIZE		0x10000
-
-#define _8BIT		0x00000000
-#define _16BIT		0x00100000
-#define _32BIT		0x00200000
-#define _64BIT		0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{						/* boundary values  */
-    unsigned int    turnOff;			/* 0x0 - 0xf	    */
-    unsigned int    acc2First;			/* 0x0 - 0x1f	    */
-    unsigned int    acc2Next;		/* 0x0 - 0x1f	    */
-    unsigned int    ale2Wr;			/* 0x0 - 0xf	    */
-    unsigned int    wrLow;			/* 0x0 - 0xf	    */
-    unsigned int    wrHigh;			/* 0x0 - 0xf	    */
-    unsigned int    badrSkew;		/* 0x0 - 0x2	   */
-    unsigned int    DPEn;			/* 0x0 - 0x1	   */
-    unsigned int    deviceWidth;	/* in Bytes  */
-} DEVICE_PARAM;
-
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,	\
-				   MEM_REGION3,MEM_REGION4,MEM_REGION5,	      \
-				   MEM_REGION6,MEM_REGION7}		      \
-				   MEMORY_PROTECT_REGION;*/
-/* There are four possible windows that can be defined as protected */
-typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
-				  MEM_WINDOW3
-				 } MEMORY_PROTECT_WINDOW;
-/* When defining a protected window , this paramter indicates whether it
-   is accessible or not */
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}	      \
-			    MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}	      \
-			   MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}	      \
-				  MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}	      \
-			       MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,	      \
-				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}	      \
-				 MEMORY_SNOOP_REGION;
-
-/* There are 21 memory windows dedicated for the varios interfaces (PCI,
-   devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
-   address decoding mechanism. */
-typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
-			    CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
-			    DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
-			    DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
-			    BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
-			    PCI_0_MEM0_WINDOW = BIT10,
-			    PCI_0_MEM1_WINDOW = BIT11,
-			    PCI_0_MEM2_WINDOW = BIT12,
-			    PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
-			    PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
-			    PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
-			    INTEGRATED_SRAM_WINDOW = BIT19,
-			    INTERNAL_SPACE_WINDOW = BIT20,
-			    ALL_WINDOWS = 0X1FFFFF
-			   } MEMORY_WINDOW;
-
-typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
-				 } MEMORY_WINDOW_STATUS;
-
-
-typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
-#ifdef INCLUDE_PCI_1
-			  ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
-#endif /* INCLUDE_PCI_1 */
-			  } PCI_MEM_WINDOW;
-
-
-/* -------------------------------------------------------------------------------------------------*/
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-/* New at MV6436x */
-unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-/* New at MV6436x */
-unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-/* Set a new base and size for one of the memory banks (CS0 - CS3) */
-bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
-			   unsigned int bankSize);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-
-/* Returns the integrated SRAM Base Address. */
-unsigned int memoryGetInternalSramBaseAddr(void);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Set new base address for the integrated SRAM. */
-void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Delete a protection feature to a given space. */
-void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Writes a new remap value to the remap register */
-unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
-				      unsigned int remapValueHigh,
-				      unsigned int remapValueLow);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
-			      MEMORY_ACCESS gtMemoryAccess,
-			      MEMORY_ACCESS_WRITE gtMemoryWrite,
-			      MEMORY_CACHE_PROTECT cacheProtection,
-			      unsigned int baseAddress,
-			      unsigned int size);
-
-/* Configurate the protection feature to a given space. */
-/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
-			    MEMORY_ACCESS memoryAccess,
-			    MEMORY_ACCESS_WRITE memoryWrite,
-			    MEMORY_CACHE_PROTECT cacheProtection,
-			    unsigned int baseAddress,
-			    unsigned int regionLength); */
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
-			      MEMORY_SNOOP_TYPE snoopType,
-			      unsigned int baseAddress,
-			      unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-/* Set a new base and size for one of the PCI windows. */
-bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
-			  unsigned int pciWindowSize);
-
-/* Disable or enable one of the 21 windows dedicated for the CPU's
-   address decoding mechanism */
-void MemoryDisableWindow(MEMORY_WINDOW window);
-void MemoryEnableWindow (MEMORY_WINDOW window);
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
-#endif	/* __INCmemoryh */
diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
deleted file mode 100644
index 572e0d3..0000000
--- a/board/Marvell/include/pci.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-
-/* The next Macros configurate the initiator board (SELF) or any any agent on
-   the PCI to become: MASTER, response to MEMORY transactions , response to
-   IO transactions or TWO both MEMORY_IO transactions. Those configuration
-   are for both PCI0 and PCI1. */
-
-#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host,		       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
-
-#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |		     \
-	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host,	      \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &		     \
-	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define		MASTER_ENABLE			BIT2
-#define		MEMORY_ENABLE			BIT1
-#define		I_O_ENABLE			BIT0
-#define	    SELF		    32
-
-/* Agent on the PCI bus may have up to 6 BARS. */
-#define	    BAR0		    0x10
-#define	    BAR1		    0x14
-#define	    BAR2		    0x18
-#define	    BAR3		    0x1c
-#define	    BAR4		    0x20
-#define	    BAR5		    0x24
-#define		BAR_SEL_MEM_IO			BIT0
-#define		BAR_MEM_TYPE_32_BIT		NO_BIT
-#define		BAR_MEM_TYPE_BELOW_1M		       BIT1
-#define		BAR_MEM_TYPE_64_BIT			      BIT2
-#define		BAR_MEM_TYPE_RESERVED		      (BIT1 | BIT2)
-#define		BAR_MEM_TYPE_MASK		      (BIT1 | BIT2)
-#define		BAR_PREFETCHABLE				      BIT3
-#define		BAR_CONFIG_MASK			(BIT0 | BIT1 | BIT2 | BIT3)
-
-/* Defines for the access regions. */
-#define	    PREFETCH_ENABLE		    BIT12
-#define	    PREFETCH_DISABLE		    NO_BIT
-#define	    DELAYED_READ_ENABLE		    BIT13
-/* #define     CACHING_ENABLE		       BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define	    AGGRESSIVE_PREFETCH		     BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define	    READ_LINE_AGGRESSIVE_PREFETCH   BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define	    READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
-#define	    MAX_BURST_4			    NO_BIT
-#define	    MAX_BURST_8			    BIT20  /* Bits[21:20] = 01 */
-#define	    MAX_BURST_16		    BIT21  /* Bits[21:20] = 10 */
-#define	    PCI_BYTE_SWAP		    NO_BIT /* Bits[25:24] = 00 */
-#define	    PCI_NO_SWAP			    BIT24  /* Bits[25:24] = 01 */
-#define	    PCI_BYTE_AND_WORD_SWAP	    BIT25  /* Bits[25:24] = 10 */
-#define	    PCI_WORD_SWAP		   (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define	    PCI_ACCESS_PROTECT		    BIT28
-#define	    PCI_WRITE_PROTECT		    BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
-				REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
-			    PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
-			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
-			      PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
-			 PCI_REGION2,PCI_REGION3,
-			 PCI_IO}
-			 PCI_REGION;
-
-/*ronen 7/Dec/03 */
-typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
-			       PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
-			       PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
-			       PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
-			       PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
-			       PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
-			       PCI_LAST_BAR} PCI_INTERNAL_BAR;
-
-typedef struct pciBar {
-    unsigned int detectBase;
-    unsigned int base;
-    unsigned int size;
-    unsigned int type;
-} PCI_BAR;
-
-typedef struct pciDevice {
-    PCI_HOST	     host;
-    char	    type[40];
-    unsigned int    deviceNum;
-    unsigned int    venID;
-    unsigned int    deviceID;
-    PCI_BAR bar[6];
-} PCI_DEVICE;
-
-typedef struct pciSelfBars {
-    unsigned int    SCS0Base;
-    unsigned int    SCS0Size;
-    unsigned int    SCS1Base;
-    unsigned int    SCS1Size;
-    unsigned int    SCS2Base;
-    unsigned int    SCS2Size;
-    unsigned int    SCS3Base;
-    unsigned int    SCS3Size;
-    unsigned int    internalMemBase;
-    unsigned int    internalIOBase;
-    unsigned int    CS0Base;
-    unsigned int    CS0Size;
-    unsigned int    CS1Base;
-    unsigned int    CS1Size;
-    unsigned int    CS2Base;
-    unsigned int    CS2Size;
-    unsigned int    CS3Base;
-    unsigned int    CS3Size;
-    unsigned int    CSBootBase;
-    unsigned int    CSBootSize;
-    unsigned int    P2PMem0Base;
-    unsigned int    P2PMem0Size;
-    unsigned int    P2PMem1Base;
-    unsigned int    P2PMem1Size;
-    unsigned int    P2PIOBase;
-    unsigned int    P2PIOSize;
-    unsigned int    CPUBase;
-    unsigned int    CPUSize;
-} PCI_SELF_BARS;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
-		       unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
-				 unsigned int regOffset,
-				 unsigned int pciDevNum,
-				 unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
-					unsigned int regOffset,
-					unsigned int pciDevNum,
-					unsigned int busNum);
-
-/* Performs full scane on both PCI and returns all detail possible on the
-   agents which exist on the bus. */
-void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
-		    unsigned int numberOfElment);
-
-/*	Master`s memory space	*/
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
-		unsigned int remapBase,
-		unsigned int deviceBase,
-		unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/*	Slave`s memory space   */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
-		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-#if 0 /* GARBAGE routines - dont use till they get cleaned up */
-void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
-void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
-void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
-void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
-void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
-			       unsigned int pci0Dev0Length);
-void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
-			       unsigned int pci1Dev0Length);
-void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
-			       unsigned int pci0Dev1Length);
-void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
-			       unsigned int pci1Dev1Length);
-void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
-			       unsigned int pci0Dev2Length);
-void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
-			       unsigned int pci1Dev2Length);
-void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
-			       unsigned int pci0Dev3Length);
-void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
-			       unsigned int pci1Dev3Length);
-void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
-				  unsigned int pci0DevBootLength);
-void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
-				  unsigned int pci1DevBootLength);
-void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
-			 unsigned int pci0P2pMem0Length);
-void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
-			 unsigned int pci1P2pMem0Length);
-void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
-			 unsigned int pci0P2pMem1Length);
-void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
-			 unsigned int pci1P2pMem1Length);
-void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
-		       unsigned int pci0P2pIoLength);
-void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
-		       unsigned int pci1P2pIoLength);
-
-void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
-void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
-#endif
-
-/* PCI region options */
-
-bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
-	unsigned int features, unsigned int baseAddress,
-	unsigned int regionLength);
-
-void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-
-/* PCI-to-PCI (P2P) */
-
-bool pciP2PConfig(PCI_HOST host,
-		  unsigned int SecondBusLow,unsigned int SecondBusHigh,
-		  unsigned int busNum,unsigned int devNum);
-/* PCI Cache-coherency */
-
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength);
-
-PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
-
-#endif /* __INCpcih */
-- 
cgit v0.10.2


From 81974f4479d19c441c4a089aedd238c251626b3e Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Tue, 5 Apr 2016 23:13:42 +0200
Subject: tools/env: no global variable sharing between application and library

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 1654ac0..52e0bec 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -35,10 +35,6 @@
 
 #include "fw_env.h"
 
-struct common_args common_args;
-struct printenv_args printenv_args;
-struct setenv_args setenv_args;
-
 #define DIV_ROUND_UP(n, d)	(((n) + (d) - 1) / (d))
 
 #define min(x, y) ({				\
@@ -120,7 +116,7 @@ static unsigned char obsolete_flag = 0;
 
 static int flash_io (int mode);
 static char *envmatch (char * s1, char * s2);
-static int parse_config (void);
+static int parse_config(struct env_opts *opts);
 
 #if defined(CONFIG_FILE)
 static int get_config (char *);
@@ -228,12 +224,12 @@ int parse_aes_key(char *key, uint8_t *bin_key)
  * Print the current definition of one, or more, or all
  * environment variables
  */
-int fw_printenv(int argc, char *argv[], int value_only)
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 {
 	char *env, *nxt;
 	int i, rc = 0;
 
-	if (fw_env_open())
+	if (fw_env_open(opts))
 		return -1;
 
 	if (argc == 0) {		/* Print all env variables  */
@@ -289,12 +285,13 @@ int fw_printenv(int argc, char *argv[], int value_only)
 	return rc;
 }
 
-int fw_env_close(void)
+int fw_env_close(struct env_opts *opts)
 {
 	int ret;
-	if (common_args.aes_flag) {
+
+	if (opts->aes_flag) {
 		ret = env_aes_cbc_crypt(environment.data, 1,
-					common_args.aes_key);
+					opts->aes_key);
 		if (ret) {
 			fprintf(stderr,
 				"Error: can't encrypt env for flash\n");
@@ -447,7 +444,7 @@ int fw_env_write(char *name, char *value)
  *	    modified or deleted
  *
  */
-int fw_setenv(int argc, char *argv[])
+int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 {
 	int i;
 	size_t len;
@@ -461,7 +458,7 @@ int fw_setenv(int argc, char *argv[])
 		return -1;
 	}
 
-	if (fw_env_open()) {
+	if (fw_env_open(opts)) {
 		fprintf(stderr, "Error: environment not initialized\n");
 		return -1;
 	}
@@ -497,7 +494,7 @@ int fw_setenv(int argc, char *argv[])
 
 	free(value);
 
-	return fw_env_close();
+	return fw_env_close(opts);
 }
 
 /*
@@ -517,7 +514,7 @@ int fw_setenv(int argc, char *argv[])
  * 0	  - OK
  * -1     - Error
  */
-int fw_parse_script(char *fname)
+int fw_parse_script(char *fname, struct env_opts *opts)
 {
 	FILE *fp;
 	char dump[1024];	/* Maximum line length in the file */
@@ -527,7 +524,7 @@ int fw_parse_script(char *fname)
 	int len;
 	int ret = 0;
 
-	if (fw_env_open()) {
+	if (fw_env_open(opts)) {
 		fprintf(stderr, "Error: environment not initialized\n");
 		return -1;
 	}
@@ -615,10 +612,9 @@ int fw_parse_script(char *fname)
 	if (strcmp(fname, "-") != 0)
 		fclose(fp);
 
-	ret |= fw_env_close();
+	ret |= fw_env_close(opts);
 
 	return ret;
-
 }
 
 /*
@@ -1128,7 +1124,7 @@ static char *envmatch (char * s1, char * s2)
 /*
  * Prevent confusion if running from erased flash memory
  */
-int fw_env_open(void)
+int fw_env_open(struct env_opts *opts)
 {
 	int crc0, crc0_ok;
 	unsigned char flag0;
@@ -1143,7 +1139,7 @@ int fw_env_open(void)
 	struct env_image_single *single;
 	struct env_image_redundant *redundant;
 
-	if (parse_config ())		/* should fill envdevices */
+	if (parse_config(opts))		/* should fill envdevices */
 		return -1;
 
 	addr0 = calloc(1, CUR_ENVSIZE);
@@ -1175,9 +1171,9 @@ int fw_env_open(void)
 
 	crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
 
-	if (common_args.aes_flag) {
+	if (opts->aes_flag) {
 		ret = env_aes_cbc_crypt(environment.data, 0,
-					common_args.aes_key);
+					opts->aes_key);
 		if (ret)
 			return ret;
 	}
@@ -1233,9 +1229,9 @@ int fw_env_open(void)
 
 		crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
 
-		if (common_args.aes_flag) {
+		if (opts->aes_flag) {
 			ret = env_aes_cbc_crypt(redundant->data, 0,
-						common_args.aes_key);
+						opts->aes_key);
 			if (ret)
 				return ret;
 		}
@@ -1312,7 +1308,7 @@ int fw_env_open(void)
 }
 
 
-static int parse_config ()
+static int parse_config(struct env_opts *opts)
 {
 	struct stat st;
 
@@ -1321,9 +1317,9 @@ static int parse_config ()
 		common_args.config_file = CONFIG_FILE;
 
 	/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
-	if (get_config(common_args.config_file)) {
+	if (get_config(opts->config_file)) {
 		fprintf(stderr, "Cannot parse config file '%s': %m\n",
-			common_args.config_file);
+			opts->config_file);
 		return -1;
 	}
 #else
@@ -1383,7 +1379,7 @@ static int parse_config ()
 	if (HaveRedundEnv)
 		usable_envsize -= sizeof(char);
 
-	if (common_args.aes_flag)
+	if (opts->aes_flag)
 		usable_envsize &= ~(AES_KEY_LENGTH - 1);
 
 	return 0;
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index d4daeea..dac964d 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -57,33 +57,22 @@
 	"bootm"
 #endif
 
-struct common_args {
+struct env_opts {
 #ifdef CONFIG_FILE
 	char *config_file;
 #endif
-	uint8_t aes_key[AES_KEY_LENGTH];
 	int aes_flag; /* Is AES encryption used? */
+	uint8_t aes_key[AES_KEY_LENGTH];
 };
-extern struct common_args common_args;
-
-struct printenv_args {
-	int value_only;
-};
-extern struct printenv_args printenv_args;
-
-struct setenv_args {
-	char *script_file;
-};
-extern struct setenv_args setenv_args;
 
 int parse_aes_key(char *key, uint8_t *bin_key);
 
-int fw_printenv(int argc, char *argv[], int value_only);
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts);
 char *fw_getenv(char *name);
-int fw_setenv(int argc, char *argv[]);
-int fw_parse_script(char *fname);
-int fw_env_open(void);
+int fw_setenv(int argc, char *argv[], struct env_opts *opts);
+int fw_parse_script(char *fname, struct env_opts *opts);
+int fw_env_open(struct env_opts *opts);
 int fw_env_write(char *name, char *value);
-int fw_env_close(void);
+int fw_env_close(struct env_opts *opts);
 
 unsigned long crc32(unsigned long, const unsigned char *, unsigned);
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 2a45a0d..7a17b28 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -49,6 +49,14 @@ static struct option long_options[] = {
 	{NULL, 0, NULL, 0}
 };
 
+static struct env_opts env_opts;
+
+/* setenv options */
+static int noheader;
+
+/* getenv options */
+static char *script_file;
+
 void usage_printenv(void)
 {
 
@@ -108,22 +116,22 @@ static void parse_common_args(int argc, char *argv[])
 	int c;
 
 #ifdef CONFIG_FILE
-	common_args.config_file = CONFIG_FILE;
+	env_opts.config_file = CONFIG_FILE;
 #endif
 
 	while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) !=
 	       EOF) {
 		switch (c) {
 		case 'a':
-			if (parse_aes_key(optarg, common_args.aes_key)) {
+			if (parse_aes_key(optarg, env_opts.aes_key)) {
 				fprintf(stderr, "AES key parse error\n");
 				exit(EXIT_FAILURE);
 			}
-			common_args.aes_flag = 1;
+			env_opts.aes_flag = 1;
 			break;
 #ifdef CONFIG_FILE
 		case 'c':
-			common_args.config_file = optarg;
+			env_opts.config_file = optarg;
 			break;
 #endif
 		case 'h':
@@ -151,7 +159,7 @@ int parse_printenv_args(int argc, char *argv[])
 	       EOF) {
 		switch (c) {
 		case 'n':
-			printenv_args.value_only = 1;
+			noheader = 1;
 			break;
 		case 'a':
 		case 'c':
@@ -177,7 +185,7 @@ int parse_setenv_args(int argc, char *argv[])
 	       EOF) {
 		switch (c) {
 		case 's':
-			setenv_args.script_file = optarg;
+			script_file = optarg;
 			break;
 		case 'a':
 		case 'c':
@@ -240,14 +248,14 @@ int main(int argc, char *argv[])
 	}
 
 	if (do_printenv) {
-		if (fw_printenv(argc, argv, printenv_args.value_only))
+		if (fw_printenv(argc, argv, noheader, &env_opts) != 0)
 			retval = EXIT_FAILURE;
 	} else {
-		if (!setenv_args.script_file) {
-			if (fw_setenv(argc, argv) != 0)
+		if (!script_file) {
+			if (fw_setenv(argc, argv, &env_opts) != 0)
 				retval = EXIT_FAILURE;
 		} else {
-			if (fw_parse_script(setenv_args.script_file) != 0)
+			if (fw_parse_script(script_file, &env_opts) != 0)
 				retval = EXIT_FAILURE;
 		}
 	}
-- 
cgit v0.10.2


From ae87440578369456b55e54125e101d27c332bc5a Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 18 May 2016 00:54:47 +0200
Subject: efi_loader: Clean up system table on exit

We put the system table into our runtime services data section so that
payloads may still access it after exit_boot_services. However, most fields
in it are quite useless once we're in that state, so let's just patch them
out.

With this patch we don't get spurious warnings when running EFI binaries
anymore.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 3ee27ca..11d0126 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -125,6 +125,22 @@ static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
 		/* RTC accessors are gone */
 		.ptr = &efi_runtime_services.get_time,
 		.patchto = &efi_device_error,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.con_in,
+		.patchto = NULL,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.con_out,
+		.patchto = NULL,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.std_err,
+		.patchto = NULL,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.boottime,
+		.patchto = NULL,
 	},
 };
 
-- 
cgit v0.10.2


From c9cfac5d3023e9b2993578400fbc7f03aa6919af Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 18 May 2016 02:04:24 +0200
Subject: efi_loader: gop: Don't expose fb address

Recently Linux is gaining support for efifb on AArch64 and that support actually
tries to make use of the frame buffer address we expose to it via gop.

While this wouldn't be bad in theory, in practice it means a few bad things

  1) We expose 16bit frame buffers as 32bit today
  2) Linux can't deal with overlapping non-PCI regions between efifb and
     a different frame buffer driver

For now, let's just disable exposure of the frame buffer address. Most OSs that
get booted will have a native driver for the GPU anyway.

Signed-off-by: Alexander Graf <agraf@suse.de>
[trini: Remove line_len entirely]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index bdd62bc..dc6e261 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -111,7 +111,6 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 int efi_gop_register(void)
 {
 	struct efi_gop_obj *gopobj;
-	int line_len;
 
 	switch (panel_info.vl_bpix) {
 	case LCD_COLOR32:
@@ -136,8 +135,6 @@ int efi_gop_register(void)
 	gopobj->mode.max_mode = 1;
 	gopobj->mode.info = &gopobj->info;
 	gopobj->mode.info_size = sizeof(gopobj->info);
-	gopobj->mode.fb_base = gd->fb_base;
-	gopobj->mode.fb_size = lcd_get_size(&line_len);
 
 	gopobj->info.version = 0;
 	gopobj->info.width = panel_info.vl_col;
-- 
cgit v0.10.2


From 87861c1970d9e1c475e62304b8e249aa3edf8c39 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 19 May 2016 07:57:41 +0200
Subject: test/py: Support setting up specific timeout

Large file transfers, flash erasing and more complicated tests
requires more time to finish. Provide a way to setup specific
timeout directly in test.

For example description for 50s test:
timeout = 50000
with u_boot_console.temporary_timeout(timeout):
  u_boot_console.run_command(...)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index f743436..815fa64 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -56,6 +56,22 @@ class ConsoleDisableCheck(object):
         self.console.disable_check_count[self.check_type] -= 1
         self.console.eval_bad_patterns()
 
+class ConsoleSetupTimeout(object):
+    """Context manager (for Python's with statement) that temporarily sets up
+    timeout for specific command. This is useful when execution time is greater
+    then default 30s."""
+
+    def __init__(self, console, timeout):
+        self.p = console.p
+        self.orig_timeout = self.p.timeout
+        self.p.timeout = timeout
+
+    def __enter__(self):
+        return self
+
+    def __exit__(self, extype, value, traceback):
+        self.p.timeout = self.orig_timeout
+
 class ConsoleBase(object):
     """The interface through which test functions interact with the U-Boot
     console. This primarily involves executing shell commands, capturing their
@@ -391,3 +407,18 @@ class ConsoleBase(object):
         """
 
         return ConsoleDisableCheck(self, check_type)
+
+    def temporary_timeout(self, timeout):
+        """Temporarily set up different timeout for commands.
+
+        Create a new context manager (for use with the "with" statement) which
+        temporarily change timeout.
+
+        Args:
+            timeout: Time in milliseconds.
+
+        Returns:
+            A context manager object.
+        """
+
+        return ConsoleSetupTimeout(self, timeout)
-- 
cgit v0.10.2


From 7ffe3cd62e5af2cda1e18c6d896cab58bfb0c811 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Thu, 19 May 2016 15:23:12 -0400
Subject: Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUP

Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:

  config OF_BOARD_SETUP
          bool "Set up board-specific details in device tree before boot"
          depends on OF_LIBFDT
          ...

remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index 79f72aa..a44f51a 100644
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
@@ -12,7 +12,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>
 
@@ -35,4 +35,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	 */
 	fdt_fixup_ethernet(blob);
 }
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
index 7a463b5..84fabbd 100644
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -96,7 +96,7 @@ unsigned long get_tbclk (void)
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
@@ -117,7 +117,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
 	do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
 #endif
-#if defined(CONFIG_OF_IDE_FIXUP)
+#ifdef CONFIG_OF_IDE_FIXUP
 	if (!ide_device_present(0)) {
 		/* NO CF card detected -> delete ata node in DTS */
 		int nodeoffset = 0;
@@ -132,10 +132,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		}
 	}
 
-#endif
+#endif /* CONFIG_OF_IDE_FIXUP */
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #ifdef CONFIG_MPC5xxx_FEC
 /* Default initializations for FEC controllers.  To override,
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 6eed6f5..9f2be3c 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -284,7 +284,7 @@ void watchdog_reset (void)
 #endif /* CONFIG_WATCHDOG */
 
 /* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 void ft_cpu_setup (void *blob, bd_t *bd)
 {
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
@@ -303,7 +303,7 @@ void ft_cpu_setup (void *blob, bd_t *bd)
 		"clock-frequency", bd->bi_intfreq, 1);
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 /*
  * Initializes on-chip ethernet controllers.
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index eef9c5a..c73509b 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -11,7 +11,7 @@
 #include <asm/cache.h>
 #include <asm/ppc4xx.h>
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/4xx_pcie.h>
@@ -160,4 +160,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	 */
 	fdt_pcie_setup(blob);
 }
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index ee1681b..55d0bc8 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -391,14 +391,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #ifdef CONFIG_SPL_OS_BOOT
 /*
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index c5d161b..20d8b80 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -170,14 +170,14 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 int board_eth_init(bd_t *bis)
 {
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index c5cc4ff..dc2e3ba 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -489,7 +489,7 @@ int misc_init_r(void)
 }
 #endif	/* !defined(CONFIG_ARCHES) */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 extern int __ft_board_setup(void *blob, bd_t *bd);
 
 int ft_board_setup(void *blob, bd_t *bd)
@@ -518,4 +518,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 5276907..fce998d 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -237,7 +237,7 @@ static void compose_hostname(hw_id_t hw_id, char *buf)
 }
 
 
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#ifdef CONFIG_OF_BOARD_SETUP
 /*
  * Update 'model' and 'memory' properties in the blob according to the module
  * that we are running on.
@@ -255,7 +255,7 @@ static void ft_blob_update(void *blob, bd_t *bd)
 	printf("ft_blob_update(): cannot set /model property err:%s\n",
 		fdt_strerror(ret));
 }
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 
 /*
@@ -358,7 +358,7 @@ int last_stage_init(void)
 #endif /* CONFIG_LAST_STAGE_INIT */
 
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
@@ -366,4 +366,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index a15a9ed..1b6c40f 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -106,11 +106,11 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index ca9a944..c510ab1 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -471,7 +471,7 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int rc;
@@ -493,4 +493,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index cda1d7b..656f0fa 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -198,11 +198,11 @@ int checkboard(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 24e4977..31ac728 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -300,7 +300,7 @@ int pci_pre_init(struct pci_controller *hose)
 	return 1;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int rc;
@@ -322,7 +322,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 7e35c19..0d43505 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -882,7 +882,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 }
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int rc;
@@ -903,4 +903,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 40bd55d..7c44282 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -274,11 +274,11 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 3b7c82b..e2eeef3 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -738,7 +738,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 
 static int ft_sethdmiinfmt(void *blob, char *mode)
 {
@@ -939,7 +939,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART2_BASE,
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 8d01d8b..2d7d789 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -203,7 +203,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 extern void __ft_board_setup(void *blob, bd_t *bd);
 
 int ft_board_setup(void *blob, bd_t *bd)
@@ -218,4 +218,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
index 72932ca..75bf1bb 100644
--- a/board/ifm/ac14xx/ac14xx.c
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -607,11 +607,11 @@ int checkboard(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
index ca09767..4fc6809 100644
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -303,7 +303,7 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 static void ft_adapt_flash_base(void *blob)
 {
@@ -383,4 +383,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 4ab7160..2e52d51 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -378,7 +378,7 @@ void ide_set_reset(int idereset)
 #endif /* CONFIG_IDE_RESET */
 #endif /* CONFIG_CMD_IDE */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 static void ft_delete_node(void *fdt, const char *compat)
 {
 	int off = -1;
@@ -481,4 +481,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
index 2078f53..2e62355 100644
--- a/board/ipek01/ipek01.c
+++ b/board/ipek01/ipek01.c
@@ -195,7 +195,7 @@ void pci_init_board (void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup (blob, bd);
@@ -203,7 +203,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 int board_eth_init(bd_t *bis)
 {
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 8856393..d56902b 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -282,11 +282,11 @@ void ide_set_reset (int idereset)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 4d0ebaa..dc237c1 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -184,14 +184,14 @@ int checkboard(void)
 }
 
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 
 #if defined(CONFIG_STATUS_LED)
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 23d0f56..8f292ea 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -145,11 +145,11 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 81f3024..d91d427 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -429,7 +429,7 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 struct node_info nodes[] = {
 	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
@@ -529,7 +529,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 /*
  * If argument is NULL, set the LCD brightness to the
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
index ed41de1..8a9de0d 100644
--- a/board/phytec/pcm030/pcm030.c
+++ b/board/phytec/pcm030/pcm030.c
@@ -163,14 +163,14 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 953a43f..8b34a80 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -217,7 +217,7 @@ int board_early_init_r (void)
 }
 #endif /* CONFIG_BOARD_EARLY_INIT_R */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	u32 val[12];
@@ -253,7 +253,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #define DEFAULT_BRIGHTNESS	25
 #define BACKLIGHT_ENABLE	(1 << 31)
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 9e8ad93..1de7df0 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -131,7 +131,7 @@ u32 spl_boot_device(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int lpae;
@@ -273,4 +273,4 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 
 	ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
-- 
cgit v0.10.2


From 98350f7f37c32dd5edcd87ee79f7f5e1bcf5819f Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:41 -0500
Subject: doc: Add info on using secure devices from TI

Adds doc/README.ti-secure file to explain in generic terms
how boot images need to be created for secure devices from
Texas Instruments.

Specific details for creating secure boot images for the
AM43xx, DRA7xx and AM57xx secure devices from Texas
Instruments are also provided in the README file.

Secure devices require a security development package (SECDEV)
package that can be downloaded from:

	http://www.ti.com/mysecuresoftware

Login is required and access is granted under appropriate NDA
and export control restrictions.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/doc/README.ti-secure b/doc/README.ti-secure
new file mode 100644
index 0000000..7fc9b9b
--- /dev/null
+++ b/doc/README.ti-secure
@@ -0,0 +1,91 @@
+README on how boot images are created for secure TI devices
+
+CONFIG_TI_SECURE_DEVICE:
+Secure TI devices require a boot image that is authenticated by ROM
+code to function. Without this, even JTAG remains locked and the
+device is essentially useless. In order to create a valid boot image for
+a secure device from TI, the initial public software image must be signed
+and combined with various headers, certificates, and other binary images.
+
+Information on the details on the complete boot image format can be obtained
+from Texas Instruments. The tools used to generate boot images for secure
+devices are part of a secure development package (SECDEV) that can be
+downloaded from:
+
+	http://www.ti.com/mysecuresoftware (login required)
+
+The secure development package is access controlled due to NDA and export
+control restrictions. Access must be requested and granted by TI before the
+package is viewable and downloadable. Contact TI, either online or by way
+of a local TI representative, to request access.
+
+When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process requires
+the presence and use of these tools in order to create a viable boot image.
+The build process will look for the environment variable TI_SECURE_DEV_PKG,
+which should be the path of the installed SECDEV package. If the
+TI_SECURE_DEV_PKG variable is not defined or if it is defined but doesn't
+point to a valid SECDEV package, a warning is issued during the build to
+indicate that a final secure bootable image was not created.
+
+Within the SECDEV package exists an image creation script:
+
+${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
+
+This is called as part of the SPL/u-boot build process. As the secure boot
+image formats and requirements differ between secure SOC from TI, the
+purpose of this script is to abstract these details as much as possible.
+
+The script is basically the only required interface to the TI SECDEV package
+for secure TI devices.
+
+Invoking the script for AM43xx Secure Devices
+=============================================
+
+create-boot-image.sh <IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
+
+<IMAGE_FLAG> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+	SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
+	XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
+	ISSW - Generates an image for all other boot modes
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (depending on the boot media, this is usually either
+u-boot-spl.bin or u-boot.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+	u-boot-spl_HS_SPI_X-LOADER - byte swapped boot image for SPI flash
+	u-boot_HS_XIP_X-LOADER - boot image for NOR or QSPI flash
+	u-boot-spl_HS_ISSW - boot image for all other boot media
+
+<SPL_LOAD_ADDR> is the address at which SOC ROM should load the <INPUT_FILE>
+
+Invoking the script for DRA7xx/AM57xx Secure Devices
+====================================================
+
+create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE>
+
+<IMAGE_TYPE> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+	X-LOADER - Generates an image for NOR or QSPI boot modes
+	MLO - Generates an image for SD/MMC/eMMC boot modes
+	ULO - Generates an image for USB/UART peripheral boot modes
+	Note: ULO is not yet used by the u-boot build process
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (for this platform, this is always u-boot-spl.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+	u-boot-spl_HS_MLO - boot image for SD/MMC/eMMC. This image is
+		copied to a file named MLO, which is the name that
+		the device ROM bootloader requires for loading from
+		the FAT partition of an SD card (same as on
+		non-secure devices)
+	u-boot-spl_HS_X-LOADER - boot image for all other flash memories
+		including QSPI and NOR flash
-- 
cgit v0.10.2


From ce31ac7f724aaafd2760bd9d7c4d93a563505511 Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Thu, 19 May 2016 19:10:42 -0500
Subject: arm: am33xx: Kconfig: Add secure device definitions

Adds a new Kconfig file for AM33xx class devices. We
need a common place to define CONFIG parameters
for these SOCs, especially for adding support
for secure devices.

a) Adds a definition for ISW_ENTRY_ADDR. This is the
address to which the ROM branches when the SOC
ROM hands off execution to the boot loader.
CONFIG_SYS_TEXT_BASE and CONFIG_SPL_TEXT_BASE are set
to this value for AM43xx devices.

b) Adds CONFIG_PUB_ROM_DATA_SIZE which is used to
calculate CONFIG_SPL_MAX_SIZE. This value indicates the
amount of memory needed by the ROM to store data during
the boot process.

Currently, these CONFIG options are used only by AM43xx,
but in future other AM33xx class SOCs will also use them.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig
new file mode 100644
index 0000000..39759cd
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/Kconfig
@@ -0,0 +1,27 @@
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP flash of bootloader entry point"
+	help
+	  After any reset, the boot ROM on the AM43XX SOC
+	  searches the boot media for a valid boot image.
+	  For non-XIP devices, the ROM then copies the
+	  image into internal memory.
+	  For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry
+	  point address depending on the device type
+	  (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+	default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+	hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+	help
+	  During the device boot, the public ROM uses the top of
+	  the public L3 OCMC RAM to store r/w data like stack,
+	  heap, globals etc. When the ROM is copying the boot
+	  image from the boot media into memory, the image must
+	  not spill over into this area. This value can be used
+	  during compile time to determine the maximum size of a
+	  boot image. Once the ROM transfers control to the boot
+	  image, this area is no longer used, and can be reclaimed
+	  for run time use by the boot image.
+	default 0x8400
-- 
cgit v0.10.2


From 6384726d2dd941411bfb3253f37f61eb1afa1c21 Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Thu, 19 May 2016 19:10:43 -0500
Subject: arm: Kconfig: Add support for AM43xx SoC specific Kconfig

Adding support for AM43xx secure devices require the addition
of some SOC specific config options like the amount of memory
used by public ROM and the address of the entry point of u-boot
or SPL, as seen by the ROM code, for the image to be built
correctly.

This mandates the addition of am AM43xx CONFIG option and the
ARM Kconfig file has been modified to source this SOC Kconfig
file. Moving the TARGET_AM43XX_EVM config option to the SOC
KConfig and out of the arch/arm/Kconfig.

Updating defconfigs to add the CONFIG_AM43XX=y statement and
removing the #define CONFIG_AM43XX from the header file.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>

Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7e45642..2f1b300 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -381,12 +381,6 @@ config TARGET_AM335X_SL50
 	select DM
 	select DM_SERIAL
 
-config TARGET_AM43XX_EVM
-	bool "Support am43xx_evm"
-	select CPU_V7
-	select SUPPORT_SPL
-	select TI_I2C_BOARD_DETECT
-
 config TARGET_BAV335X
 	bool "Support bav335x"
 	select CPU_V7
@@ -514,6 +508,17 @@ config OMAP54XX
 	select CPU_V7
 	select SUPPORT_SPL
 
+config AM43XX
+	bool "AM43XX SoC"
+	select CPU_V7
+	select SUPPORT_SPL
+	help
+	  Support for AM43xx SOC from Texas Instruments.
+	  The AM43xx high performance SOC features a Cortex-A9
+	  ARM core, a quad core PRU-ICSS for industrial Ethernet
+	  protocols, dual camera support, optional 3D graphics
+	  and an optional customer programmable secure boot.
+
 config RMOBILE
 	bool "Renesas ARM SoCs"
 	select CPU_V7
@@ -795,6 +800,8 @@ source "arch/arm/cpu/armv7/omap4/Kconfig"
 
 source "arch/arm/cpu/armv7/omap5/Kconfig"
 
+source "arch/arm/cpu/armv7/am33xx/Kconfig"
+
 source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/cpu/armv7/rmobile/Kconfig"
diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig
index 39759cd..dc51e9b 100644
--- a/arch/arm/cpu/armv7/am33xx/Kconfig
+++ b/arch/arm/cpu/armv7/am33xx/Kconfig
@@ -1,3 +1,15 @@
+if AM43XX
+config TARGET_AM43XX_EVM
+	bool "Support am43xx_evm"
+	select TI_I2C_BOARD_DETECT
+	help
+	  This option specifies support for the AM43xx
+	  GP and HS EVM development platforms.The AM437x
+	  GP EVM is a standalone test, development, and
+	  evaluation module system that enables developers
+	  to write software and develop hardware around
+	  an AM43xx processor subsystem.
+
 config ISW_ENTRY_ADDR
 	hex "Address in memory or XIP flash of bootloader entry point"
 	help
@@ -25,3 +37,4 @@ config PUB_ROM_DATA_SIZE
 	  image, this area is no longer used, and can be reclaimed
 	  for run time use by the boot image.
 	default 0x8400
+endif
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index ef4c248..e98412a 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 8c1e09a..b665331 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_SPI=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 4911b61..12d3fb7 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index ee4716d..33fb552 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 4d18231..4bc75e7 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index c336419..32a07ed 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5b49988..a35541b 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_AM43XX_EVM_H
 #define __CONFIG_AM43XX_EVM_H
 
-#define CONFIG_AM43XX
-
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_CACHELINE_SIZE       32
-- 
cgit v0.10.2


From a774e08858b12d6c022020541f6f2d7dc8b1c737 Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Thu, 19 May 2016 19:10:44 -0500
Subject: ti: omap-common: Add Kconfig file for secure device support

Defines CONFIG_TI_SECURE_DEVICE which needs to be turned on
when building images for secure devices. This flag is used
to invoke the secure image creation tools for creating a
boot image that can be used on secure devices. This flag
may also be used to conditionally compile code specific
to secure devices.

This terminology will be used by all OMAP architecture devices,
hence introducing to a common location.

With the creation of Kconfig for omap-common, moved the
sourcing of the Kconfig files for the omap3/4/5 and am33xx
devices from arch/arm/KConfig to the omap-common one.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f1b300..7a77b6a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -794,13 +794,7 @@ source "arch/arm/cpu/armv7/mx6/Kconfig"
 
 source "arch/arm/cpu/armv7/mx5/Kconfig"
 
-source "arch/arm/cpu/armv7/omap3/Kconfig"
-
-source "arch/arm/cpu/armv7/omap4/Kconfig"
-
-source "arch/arm/cpu/armv7/omap5/Kconfig"
-
-source "arch/arm/cpu/armv7/am33xx/Kconfig"
+source "arch/arm/cpu/armv7/omap-common/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig
new file mode 100644
index 0000000..7b39506
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/Kconfig
@@ -0,0 +1,17 @@
+config TI_SECURE_DEVICE
+	bool "HS Device Type Support"
+	depends on OMAP54XX || AM43XX
+	help
+	  If a high secure (HS) device type is being used, this config
+	  must be set. This option impacts various aspects of the
+	  build system (to create signed boot images that can be
+	  authenticated) and the code. See the doc/README.ti-secure
+	  file for further details.
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/armv7/am33xx/Kconfig"
-- 
cgit v0.10.2


From 0a0c534b338199237b094af4134a3c1642ad1b21 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:45 -0500
Subject: ti: omap-common: Add commands for generating secure SPL images

Adds a centralized config_secure.mk in omap-common for
OMAP-style TI secure devices to use for boot image generation

Depending on the boot media, different images are needed for
secure devices. These commands generates u-boot*_HS_* files that
need to be used to boot secure devices.

Please refer to README.ti-secure for more information.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk
new file mode 100644
index 0000000..c7bb101
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/config_secure.mk
@@ -0,0 +1,66 @@
+#
+# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+quiet_cmd_mkomapsecimg = MKIMAGE $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
+ifneq ($(CONFIG_SPL_BUILD),)
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+	$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+    $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+    $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+endif
+else
+cmd_mkomapsecimg = echo "WARNING:" \
+	"$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
+	"$@ was NOT created!"
+endif
+else
+cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+	"variable must be defined for TI secure devices. $@ was NOT created!"
+endif
+
+# Standard X-LOADER target (QPSI, NOR flash)
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# For MLO targets (SD card boot) the final file name
+# that is copied to the SD card fAT partition must
+# be MLO, so we make a copy of the output file to a
+# new file with that name
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+	@if [ -f $@ ]; then \
+		cp -f $@ MLO; \
+	fi
+
+# Standard 2ND target (certain peripheral boot modes)
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# Standard ULO target (certain peripheral boot modes)
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# Standard ISSW target (certain devices, various boot modes)
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# For SPI flash on AM335x and AM43xx, these
+# require special byte swap handling so we use
+# the SPI_X-LOADER target instead of X-LOADER
+# and let the create-boot-image.sh script handle
+# that
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# For supporting single stage XiP QSPI on AM43xx, the
+# image is a full u-boot file, not an SPL. In this case
+# the mkomapsecimg command looks for a u-boot-HS_* prefix
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
+	$(call if_changed,mkomapsecimg)
-- 
cgit v0.10.2


From 883dfd15536e41d2b994099dd478be5a18660960 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:46 -0500
Subject: ti: AM43xx: config.mk: Add support for generating secure boot images

Modifies the config.mk to build secure images when building
the SPL for secure devices.

Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes. The same u-boot
binary file is processed slightly differently to produce a
different boot image, depending on whether the user wants to
boot off SPI, QSPI or other boot media.

Refer to README.ti-secure for more information.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 5294d16..6d95d32 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -3,9 +3,29 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
+
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
 ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y	+= u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
 ALL-y	+= MLO
 ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
 else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+endif
 ALL-y	+= u-boot.img
 endif
-- 
cgit v0.10.2


From 9aac7d0ec96923a39f8d234f82b82bec5c13f183 Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Thu, 19 May 2016 19:10:47 -0500
Subject: ti: AM43xx: Use CONFIG options from SOC Kconfig

Updates configs/am43xx_evm.h to use CONFIG options from
SOC specific Kconfig file for various calculations.

On AM43x devices, the address of SPL entry point  depends on
the device type, i.e. whether it is secure or non-secure.

Further, for non-secure devices, the SPL entry point is different
between  USB HOST boot mode, other "memory" boot modes (MMC, NAND)
and "peripheral" boot modes (UART, USB)

To add to the complexity, on secure devices, in addition to the
above differences, the SPL entry point can change because of the
space occupied by other components (other than u-boot or spl)
that go into a secure boot image.

To prevent the user from having to modify source files every time
any component of the secure image changes, the value of
CONFIG_SPL_TEXT_BASE has been set using a Kconfig option that
is supplied in the am43xx_*_defconfig files

Using the CONFIG options also enables us to do away with some
compile time flags that were used to specify CONFIG_SPL_TEXT_BASE
for different boot modes.

On QSPI devices, the same problem described above occurs w.r.t. the
address of the u-boot entry point in flash, when booting secure
devices. To handle this, CONFIG_SYS_TEXT_BASE is also setup via
a Kconfig option and the defconfig files.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 4bc75e7..5f90e2b 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x30000000
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 32a07ed..1f73114 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index a35541b..8a48a9a 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -37,17 +37,10 @@
 #define CONFIG_POWER_TPS62362
 
 /* SPL defines. */
-#ifdef CONFIG_SPL_USB_HOST_SUPPORT
-/*
- * For USB host boot, ROM uses DMA for copying MLO from USB storage
- * and ARM internal ram is not accessible for DMA, so SPL text base
- * should be in OCMC ram
- */
-#define CONFIG_SPL_TEXT_BASE		0x40300350
-#else
-#define CONFIG_SPL_TEXT_BASE		0x402F4000
-#endif
-#define CONFIG_SPL_MAX_SIZE		(220 << 10)	/* 220KB */
+#define CONFIG_SPL_TEXT_BASE		CONFIG_ISW_ENTRY_ADDR
+#define CONFIG_SPL_MAX_SIZE		(NON_SECURE_SRAM_END - \
+					CONFIG_PUB_ROM_DATA_SIZE - \
+					CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
 					 (128 << 20))
 #define CONFIG_SPL_POWER_SUPPORT
@@ -190,7 +183,9 @@
 #endif
 
 #ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_TEXT_BASE           0x30000000
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		CONFIG_ISW_ENTRY_ADDR
+#endif
 #undef CONFIG_ENV_IS_IN_FAT
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-- 
cgit v0.10.2


From a5051b727eaf098a18cf0e77f2cd8e61b71c888a Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Thu, 19 May 2016 19:10:48 -0500
Subject: ti: AM43xx: board: Detect AM43xx HS EVM

Adds code to detect AM43xx HS EVMS - the string in the
I2C EEPROM for HS EVMs differs from GP EVMs. Adds code to
for evm detection, regardless of whether the evm is for
GP or HS parts, and updates board init to use that.

Modifies findfdt command to pick up am437x-gp-evm.dtb for
the HS EVMs also, as the boards are similar except for
some security specific changes around power supply and
enclosure protection.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d208d2f..7247107 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -341,7 +341,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
 
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr[ind];
-	else if (board_is_gpevm() || board_is_sk())
+	else if (board_is_evm() || board_is_sk())
 		return &gp_evm_dpll_ddr;
 	else if (board_is_idk())
 		return &idk_dpll_ddr;
@@ -553,7 +553,7 @@ void sdram_init(void)
 		enable_vtt_regulator();
 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
 			   &ddr3_emif_regs_400Mhz_beta, 0);
-	} else if (board_is_gpevm()) {
+	} else if (board_is_evm()) {
 		enable_vtt_regulator();
 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
 			   &ddr3_emif_regs_400Mhz, 0);
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 2cf7a77..3f93d13 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -37,14 +37,24 @@ static inline int board_is_idk(void)
 	return board_ti_is("AM43_IDK");
 }
 
+static inline int board_is_hsevm(void)
+{
+	return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+	return board_is_gpevm() || board_is_hsevm();
+}
+
 static inline int board_is_evm_14_or_later(void)
 {
-	return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0);
+	return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
 }
 
 static inline int board_is_evm_12_or_later(void)
 {
-	return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0);
+	return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
 }
 
 void enable_uart0_pin_mux(void);
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index e03b1bc..f26b21e 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -126,7 +126,7 @@ void enable_board_pin_mux(void)
 	configure_module_pin_mux(i2c0_pin_mux);
 	configure_module_pin_mux(mdio_pin_mux);
 
-	if (board_is_gpevm()) {
+	if (board_is_evm()) {
 		configure_module_pin_mux(gpio5_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);
 #if defined(CONFIG_NAND)
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 8a48a9a..a54303d 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -289,6 +289,8 @@
 			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
 		"if test $board_name = AM43__GP; then " \
 			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43XXHS; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
 		"if test $board_name = AM43__SK; then " \
 			"setenv fdtfile am437x-sk-evm.dtb; fi; " \
 		"if test $board_name = AM43_IDK; then " \
-- 
cgit v0.10.2


From df277e66b3fbaaf989ef14f74a8351b32189d134 Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Thu, 19 May 2016 19:10:49 -0500
Subject: defconfig: Add a config for AM43xx secure part

Adds a new defconfig file for the AM43xx secure device.
This is the same as for the non-secure part, except for:
	CONFIG_TI_SECURE_DEVICE option set to 'y'
	CONFIG_ISW_ENTRY_ADDR updated for secure images.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
new file mode 100644
index 0000000..c4accb6
--- /dev/null
+++ b/configs/am437x_hs_evm_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+# Device tree file can be same on HS evm
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-- 
cgit v0.10.2


From b9b8403f4934c3236a6c8f515c6672e4714236f9 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:50 -0500
Subject: ti_omap5_common: Update SPL start address on secure parts

Updated the CONFIG_SPL_TEXT_BASE to support secure parts (moving
the start address past secure reserved memory and the size of the
security certificate that precedes the boot image on secure devices).
Updated the related CONFIG_SPL_MAX_SIZE to properly reflect the
internal memory actually available on the various device flavors
(Common minimum internal RAM guaranteed for various flavors of
DRA7xx/AM57xx is 512KB).

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 2135af0..5c5a12d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -130,13 +130,35 @@
 
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
- * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
- * (dra7xx is larger, but we do not need to be larger at this time).  We
- * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
+ * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
+ * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
  * print some information.
  */
-#define CONFIG_SPL_TEXT_BASE		0x40300000
-#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
+#ifdef CONFIG_TI_SECURE_DEVICE
+/*
+ * For memory booting on HS parts, the first 4KB of the internal RAM is
+ * reserved for secure world use and the flash loader image is
+ * preceded by a secure certificate. The SPL will therefore run in internal
+ * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
+ */
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ	0x1000
+#define CONFIG_SPL_TEXT_BASE	0x40301350
+#else
+/*
+ * For all booting on GP parts, the flash loader image is
+ * downloaded into internal RAM at address 0x40300000.
+ */
+#define CONFIG_SPL_TEXT_BASE	0x40300000
+#endif
+
+/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#define TI_ROM_BOOT_LOAD_END		0x4037E000
+#else
+#define TI_ROM_BOOT_LOAD_END		0x4031E000
+#endif
+#define CONFIG_SPL_MAX_SIZE     (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
-- 
cgit v0.10.2


From 410f52579498ebe7863c0b88f417eb2d9fb25551 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:51 -0500
Subject: spl: build: ti: add support for secure boot images

Updates the SPL build so that when CONFIG_TI_SECURE_DEVICE
is in use (which it should be when building for secure parts),
the TI secure development package is used to create a valid
secure boot image. The u-boot SPL build processes is NOT aware
of the details of creating the boot image - all of that information
is encapsulated in the TI secure development package, which is
available from TI. More info can be found in README.ti-secure

Right now, two image types are generated, MLO and X-LOADER. The types
are important, as certain boot modes implemented by the device's ROM
boot loader require one or the other (they are not equivalent). The
output filenames are u-boot-spl_HS_MLO and u-boot-spl_HS_X-LOADER. The
u-boot-spl_HS_MLO image is also copied to a file named MLO, which is
the name that the device ROM bootloader requires for loading from the
FAT partition of an SD card (same as on non-secure devices).

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
index ef2725a..a7e55a5 100644
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -6,8 +6,14 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
 ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-y	+= u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
+else
 ALL-y	+= MLO
+endif
 else
 ALL-y	+= u-boot.img
 endif
-- 
cgit v0.10.2


From 47c331ede1ef339425348cdc762e1feab6779d06 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:52 -0500
Subject: ARM: omap-common: Add device type to CPU string

Update the CPU string output so that the device
type is now included as part of the CPU string that
is printed as the SPL or u-boot comes up. This update
adds a suffix of the form "-GP" or "-HS" for production
devices, so that general purpose (GP) and high security
(HS) can be distiguished. Applies to all OMAP5 variants.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 01c2d57..078bdd8 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -65,12 +65,30 @@ static void omap_rev_string(void)
 	u32 major_rev = (omap_rev & 0x00000F00) >> 8;
 	u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
+	const char *sec_s;
+
+	switch (get_device_type()) {
+	case TST_DEVICE:
+		sec_s = "TST";
+		break;
+	case EMU_DEVICE:
+		sec_s = "EMU";
+		break;
+	case HS_DEVICE:
+		sec_s = "HS";
+		break;
+	case GP_DEVICE:
+		sec_s = "GP";
+		break;
+	default:
+		sec_s = "?";
+	}
+
 	if (soc_variant)
 		printf("OMAP");
 	else
 		printf("DRA");
-	printf("%x ES%x.%x\n", omap_variant, major_rev,
-	       minor_rev);
+	printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
 }
 
 #ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 53cc2b0..e8aa786 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -59,13 +59,8 @@ struct ctrl_id {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
-/* device type */
-#define DEVICE_MASK		(0x7 << 8)
+/* boot pin mask */
 #define SYSBOOT_MASK		0x1F
-#define TST_DEVICE		0x0
-#define EMU_DEVICE		0x1
-#define HS_DEVICE		0x2
-#define GP_DEVICE		0x3
 
 /* device speed */
 #define SKUID_CLK_MASK		0xf
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8fb05e1..ac34b0e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -717,6 +717,17 @@ static inline u8 is_dra72x(void)
 #define DRA722_ES2_0	0x07220200
 
 /*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK         (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE          0x0
+#define EMU_DEVICE          0x1
+#define HS_DEVICE           0x2
+#define GP_DEVICE           0x3
+
+
+/*
  * SRAM scratch space entries
  */
 #define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
-- 
cgit v0.10.2


From 1aad38f6e614f129fc987e9dd310cb6727e42363 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:53 -0500
Subject: ARM: omap5: add hooks for cpu/SoC fdt fixups

Adds an fdt.c file in that defines the ft_cpu_setup() function,
which should be called from a board-specific ft_board_setup()).
This ft_cpu_setup() will currently do nothing for non-secure (GP)
devices	but contains pertinent updates for booting on secure (HS)
devices.

Update the omap5 Makefile to include the fdt.c in the build.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index f2930d5..3caba86 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -12,4 +12,5 @@ obj-y	+= sdram.o
 obj-y	+= prcm-regs.o
 obj-y	+= hw_data.o
 obj-y	+= abb.o
+obj-y	+= fdt.o
 obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c
new file mode 100644
index 0000000..0493cd1
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/fdt.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2016 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <malloc.h>
+
+#include <asm/omap_common.h>
+#include <asm/arch-omap5/sys_proto.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+/* Give zero values if not already defined */
+#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
+#endif
+#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#endif
+
+static u32 hs_irq_skip[] = {
+	8,	/* Secure violation reporting interrupt */
+	15,	/* One interrupt for SDMA by secure world */
+	118	/* One interrupt for Crypto DMA by secure world */
+};
+
+static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
+{
+	const char *path;
+	int offs;
+	int ret;
+	int len, i, old_cnt, new_cnt;
+	u32 *temp;
+	const u32 *p_data;
+
+	/*
+	 * Increase the size of the fdt
+	 * so we have some breathing room
+	 */
+	ret = fdt_increase_size(fdt, 512);
+	if (ret < 0) {
+		printf("Could not increase size of device tree: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	/* Reserve IRQs that are used/needed by secure world */
+	path = "/ocp/crossbar";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		debug("Node %s not found.\n", path);
+		return 0;
+	}
+
+	/* Get current entries */
+	p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
+	if (p_data)
+		old_cnt = len / sizeof(u32);
+	else
+		old_cnt = 0;
+
+	new_cnt = sizeof(hs_irq_skip) /
+				sizeof(hs_irq_skip[0]);
+
+	/* Create new/updated skip list for HS parts */
+	temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
+	for (i = 0; i < new_cnt; i++)
+		temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
+	for (i = 0; i < old_cnt; i++)
+		temp[i + new_cnt] = p_data[i];
+
+	/* Blow away old data and set new data */
+	fdt_delprop(fdt, offs, "ti,irqs-skip");
+	ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
+			  temp,
+			  (old_cnt + new_cnt) * sizeof(u32));
+	free(temp);
+
+	/* Check if the update worked */
+	if (ret < 0) {
+		printf("Could not add ti,irqs-skip property to node %s: %s\n",
+		       path, fdt_strerror(ret));
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ft_hs_disable_rng(void *fdt, bd_t *bd)
+{
+	const char *path;
+	int offs;
+	int ret;
+
+	/* Make HW RNG reserved for secure world use */
+	path = "/ocp/rng";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		debug("Node %s not found.\n", path);
+		return 0;
+	}
+	ret = fdt_setprop_string(fdt, offs,
+				 "status", "disabled");
+	if (ret < 0) {
+		printf("Could not add status property to node %s: %s\n",
+		       path, fdt_strerror(ret));
+		return ret;
+	}
+	return 0;
+}
+
+#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
+    (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
+{
+	const char *path;
+	int offs;
+	int ret;
+	u32 temp[2];
+
+	/*
+	 * Update SRAM reservations on secure devices. The OCMC RAM
+	 * is always reserved for secure use from the start of that
+	 * memory region
+	 */
+	path = "/ocp/ocmcram@40300000/sram-hs";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		debug("Node %s not found.\n", path);
+		return 0;
+	}
+
+	/* relative start offset */
+	temp[0] = cpu_to_fdt32(0);
+	/* reservation size */
+	temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
+				   CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+	fdt_delprop(fdt, offs, "reg");
+	ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
+	if (ret < 0) {
+		printf("Could not add reg property to node %s: %s\n",
+		       path, fdt_strerror(ret));
+		return ret;
+	}
+
+	return 0;
+}
+#else
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+	/* Check we are running on an HS/EMU device type */
+	if (GP_DEVICE != get_device_type()) {
+		if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
+		    (ft_hs_disable_rng(fdt, bd) == 0) &&
+		    (ft_hs_fixup_sram(fdt, bd) == 0))
+			return;
+	} else {
+		printf("ERROR: Incorrect device type (GP) detected!");
+	}
+	/* Fixup failed or wrong device type */
+	hang();
+}
+#else
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+}
+#endif
+
+/*
+ * Place for general cpu/SoC FDT fixups. Board specific
+ * fixups should remain in the board files which is where
+ * this function should be called from.
+ */
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+	ft_hs_fixups(fdt, bd);
+}
-- 
cgit v0.10.2


From 62a09f0535b223c8acbf85da8d4b1acf1667826e Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:54 -0500
Subject: ARM: omap5: add ft_board_setup for dra7xx/am57xx

Adds the board specific ft_board_setup() functions that
are called when CONFIG_OF_BOARD_SETUP is defined. These functions
will currently just call the ft_cpu_setup() function.

Adds CONFIG_OF_BOARD_SETUP to the defconfig files
for dra72_evm, dra74_evm, and am57xx_evm.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 86b8f6e..9904047 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -686,3 +686,12 @@ int board_early_init_f(void)
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9bd71d8..d01c785 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -718,3 +718,12 @@ int board_early_init_f(void)
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 8fc3ebb..cccdc10 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 00c6ac3..c85c0fb 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 32ffce7..a8462ca 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
-- 
cgit v0.10.2


From 53d150b1412bc1b2da07dfdeb2aa834ab62ec7ad Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Thu, 19 May 2016 19:10:55 -0500
Subject: defconfig: ti: Add configs for OMAP5-class secure parts

Adds new defconfig files for DRA7xx and AM57xx secure devices.
These are the same as the non-secure parts, but with the addition
of the CONFIG_TI_SECURE_DEVICE option set to 'y'.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
new file mode 100644
index 0000000..60525cd
--- /dev/null
+++ b/configs/am57xx_hs_evm_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/dra72_hs_evm_defconfig b/configs/dra72_hs_evm_defconfig
new file mode 100644
index 0000000..01f985e
--- /dev/null
+++ b/configs/dra72_hs_evm_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra74_hs_evm_defconfig b/configs/dra74_hs_evm_defconfig
new file mode 100644
index 0000000..1b30ad4
--- /dev/null
+++ b/configs/dra74_hs_evm_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
-- 
cgit v0.10.2


From 4d9d34a7f280ba0e14896d4157ede677899f83a2 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:37 +0530
Subject: spl: fit: Fix the number of bytes read when reading fdt from fit

sectors field is not being updated when reading fdt from fit image. Because of
this size_of(u-boot.bin) is being read when reading fdt. Fixing it by updating
the sectors field properly.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 90acbb2..79cc06e 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -182,6 +182,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 */
 	dst = load_ptr + data_size;
 	fdt_offset += base_offset;
+	sectors = (fdt_len + info->bl_len - 1) / info->bl_len;
 	count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
 			   dst);
 	debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
-- 
cgit v0.10.2


From eafd5410af2ade58f25da707edaba85e44999621 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:38 +0530
Subject: spl: Allow to load a FIT containing U-Boot from FS

This provides a way to load a FIT containing U-Boot and a selection of device
tree files from a File system. Making sure that all the reads and writes
are aligned to their respective needs.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Make this still apply with Michal's alignment change for 'fit']
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 79cc06e..fb69f1d 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -87,6 +87,42 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 	return -ENOENT;
 }
 
+static int get_aligned_image_offset(struct spl_load_info *info, int offset)
+{
+	/*
+	 * If it is a FS read, get the first address before offset which is
+	 * aligned to ARCH_DMA_MINALIGN. If it is raw read return the
+	 * block number to which offset belongs.
+	 */
+	if (info->filename)
+		return offset & ~(ARCH_DMA_MINALIGN - 1);
+
+	return offset / info->bl_len;
+}
+
+static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
+{
+	/*
+	 * If it is a FS read, get the difference between the offset and
+	 * the first address before offset which is aligned to
+	 * ARCH_DMA_MINALIGN. If it is raw read return the offset within the
+	 * block.
+	 */
+	if (info->filename)
+		return offset & (ARCH_DMA_MINALIGN - 1);
+
+	return offset % info->bl_len;
+}
+
+static int get_aligned_image_size(struct spl_load_info *info, int data_size,
+				  int offset)
+{
+	if (info->filename)
+		return data_size + get_aligned_image_overhead(info, offset);
+
+	return (data_size + info->bl_len - 1) / info->bl_len;
+}
+
 int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 {
 	int sectors;
@@ -96,7 +132,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	void *load_ptr;
 	int fdt_offset, fdt_len;
 	int data_offset, data_size;
-	int base_offset;
+	int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
 	int src_sector;
 	void *dst;
 
@@ -124,7 +160,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 */
 	fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
 	fit = (void *)ALIGN((ulong)fit, 8);
-	sectors = (size + info->bl_len - 1) / info->bl_len;
+	sectors = get_aligned_image_size(info, size, 0);
 	count = info->read(info, sector, sectors, fit);
 	debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
 	      sector, sectors, fit, count);
@@ -157,19 +193,23 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * byte will be at 'load'. This may mean we need to load it starting
 	 * before then, since we can only read whole blocks.
 	 */
-	sectors = (data_size + info->bl_len - 1) / info->bl_len;
 	data_offset += base_offset;
+	sectors = get_aligned_image_size(info, data_size, data_offset);
 	load_ptr = (void *)load;
 	debug("U-Boot size %x, data %p\n", data_size, load_ptr);
-	dst = load_ptr - (data_offset % info->bl_len);
+	dst = load_ptr;
 
 	/* Read the image */
-	src_sector = sector + data_offset / info->bl_len;
-	debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n",
-	      data_offset, dst, src_sector, sectors);
+	src_sector = sector + get_aligned_image_offset(info, data_offset);
+	debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n",
+	      dst, src_sector, sectors);
 	count = info->read(info, src_sector, sectors, dst);
 	if (count != sectors)
 		return -EIO;
+	debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
+	      data_size);
+	memcpy(dst, dst + get_aligned_image_overhead(info, data_offset),
+	       data_size);
 
 	/* Figure out which device tree the board wants to use */
 	fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
@@ -179,14 +219,15 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	/*
 	 * Read the device tree and place it after the image. There may be
 	 * some extra data before it since we can only read entire blocks.
+	 * And also align the destination address to ARCH_DMA_MINALIGN.
 	 */
-	dst = load_ptr + data_size;
+	dst = (void *)((load + data_size + align_len) & ~align_len);
 	fdt_offset += base_offset;
-	sectors = (fdt_len + info->bl_len - 1) / info->bl_len;
-	count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
-			   dst);
-	debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
-	      sectors, spl_image.load_addr, dst, fdt_offset);
+	sectors = get_aligned_image_size(info, fdt_len, fdt_offset);
+	src_sector = sector + get_aligned_image_offset(info, fdt_offset);
+	count = info->read(info, src_sector, sectors, dst);
+	debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n",
+	      dst, src_sector, sectors);
 	if (count != sectors)
 		return -EIO;
 
@@ -195,7 +236,10 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * After this we will have the U-Boot image and its device tree ready
 	 * for us to start.
 	 */
-	memcpy(dst, dst + fdt_offset % info->bl_len, fdt_len);
+	debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset,
+	      fdt_len);
+	memcpy(load_ptr + data_size,
+	       dst + get_aligned_image_overhead(info, fdt_offset), fdt_len);
 
 	return 0;
 }
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 5676acd..d8058d6 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -77,6 +77,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 		debug("Found FIT\n");
 		load.dev = mmc;
 		load.priv = NULL;
+		load.filename = NULL;
 		load.bl_len = mmc->read_bl_len;
 		load.read = h_spl_load_read;
 		ret = spl_load_simple_fit(&load, sector, header);
diff --git a/include/spl.h b/include/spl.h
index 335b76a..0ae1605 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -35,16 +35,28 @@ struct spl_image_info {
  * @dev: Pointer to the device, e.g. struct mmc *
  * @priv: Private data for the device
  * @bl_len: Block length for reading in bytes
+ * @filename: Name of the fit image file.
  * @read: Function to call to read from the device
  */
 struct spl_load_info {
 	void *dev;
 	void *priv;
 	int bl_len;
+	const char *filename;
 	ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
 		      void *buf);
 };
 
+/**
+ * spl_load_simple_fit() - Loads a fit image from a device.
+ * @info:	Structure containing the information required to load data.
+ * @sector:	Sector number where FIT image is located in the device
+ * @fdt:	Pointer to the copied FIT header.
+ *
+ * Reads the FIT image @sector in the device. Loads u-boot image to
+ * specified load address and copies the dtb to end of u-boot image.
+ * Returns 0 on success.
+ */
 int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt);
 
 #define SPL_COPY_PAYLOAD_ONLY	1
-- 
cgit v0.10.2


From 97ca364fafe31dd986774d282674a3fe925a546a Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:39 +0530
Subject: spl: Support loading a FIT from FAT FS

Detect a FIT when loading from a FAT File system and handle it using the
new FIT SPL support.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 5b0d969..db67618 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -15,6 +15,7 @@
 #include <fat.h>
 #include <errno.h>
 #include <image.h>
+#include <libfdt.h>
 
 static int fat_registered;
 
@@ -39,6 +40,20 @@ static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 	return err;
 }
 
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+			  ulong size, void *buf)
+{
+	loff_t actread;
+	int ret;
+	char *filename = (char *)load->filename;
+
+	ret = fat_read_file(filename, buf, file_offset, size, &actread);
+	if (ret)
+		return ret;
+
+	return actread;
+}
+
 int spl_load_image_fat(struct blk_desc *block_dev,
 						int partition,
 						const char *filename)
@@ -57,11 +72,24 @@ int spl_load_image_fat(struct blk_desc *block_dev,
 	if (err <= 0)
 		goto end;
 
-	err = spl_parse_image_header(header);
-	if (err)
-		goto end;
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.read = spl_fit_read;
+		load.bl_len = 1;
+		load.filename = (void *)filename;
+		load.priv = NULL;
 
-	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+		return spl_load_simple_fit(&load, 0, header);
+	} else {
+		err = spl_parse_image_header(header);
+		if (err)
+			goto end;
+
+		err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+	}
 
 end:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-- 
cgit v0.10.2


From 00d559561ea7f774a7758c70b79e1e7e38b62459 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:40 +0530
Subject: spl: Support loading a FIT from SPI

Detect a FIT when loading from SPI and handle it using the
new FIT SPL support.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 46c98a9..bac1e85 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -48,6 +48,18 @@ static int spi_load_image_os(struct spi_flash *flash,
 }
 #endif
 
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+			      ulong count, void *buf)
+{
+	struct spi_flash *flash = load->dev;
+	ulong ret;
+
+	ret = spi_flash_read(flash, sector, count, buf);
+	if (!ret)
+		return count;
+	else
+		return 0;
+}
 /*
  * The main entry for SPI booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -85,11 +97,26 @@ int spl_spi_load_image(void)
 		if (err)
 			return err;
 
-		err = spl_parse_image_header(header);
-		if (err)
-			return err;
-		err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
-			       spl_image.size, (void *)spl_image.load_addr);
+		if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+			struct spl_load_info load;
+
+			debug("Found FIT\n");
+			load.dev = flash;
+			load.priv = NULL;
+			load.filename = NULL;
+			load.bl_len = 1;
+			load.read = spl_spi_fit_read;
+			err = spl_load_simple_fit(&load,
+						  CONFIG_SYS_SPI_U_BOOT_OFFS,
+						  header);
+		} else {
+			err = spl_parse_image_header(header);
+			if (err)
+				return err;
+			err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+					     spl_image.size,
+					     (void *)spl_image.load_addr);
+		}
 	}
 
 	return err;
-- 
cgit v0.10.2


From 0985294604bb713d56c8dbedf1da462c7f86f90f Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:41 +0530
Subject: mtd: nand: am335x: spl: Fix copying of image

When offset is not aligned to page address, it is possible that extra offset
will be read from nand. Adjust the image such that first byte of the image
is at load address after the first page is read.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index bf8b2ee..31c7825 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -173,7 +173,7 @@ static int nand_read_page(int block, int page, void *dst)
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
 	unsigned int block, lastblock;
-	unsigned int page;
+	unsigned int page, page_offset;
 
 	/*
 	 * offs has to be aligned to a page address!
@@ -181,6 +181,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+	page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
 
 	while (block <= lastblock) {
 		if (!nand_is_bad_block(block)) {
@@ -189,6 +190,18 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 			 */
 			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 				nand_read_page(block, page, dst);
+				/*
+				 * When offs is not aligned to page address the
+				 * extra offset is copied to dst as well. Copy
+				 * the image such that its first byte will be
+				 * at the dst.
+				 */
+				if (unlikely(page_offset)) {
+					memmove(dst, dst + page_offset,
+						CONFIG_SYS_NAND_PAGE_SIZE);
+					dst = (void *)((int)dst - page_offset);
+					page_offset = 0;
+				}
 				dst += CONFIG_SYS_NAND_PAGE_SIZE;
 				page++;
 			}
-- 
cgit v0.10.2


From 8bd887727913e9393ef467cdf8b0146babb2673d Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:42 +0530
Subject: spl: Support loading a FIT from NAND

Detect a FIT when loading from NAND and handle it using the
new FIT SPL support.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Make sure we continue to use (void *)(unsigned long) for
load_addr].
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index bbd9546..7cf0d1b 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -9,6 +9,8 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <nand.h>
+#include <libfdt_env.h>
+#include <fdt.h>
 
 #if defined(CONFIG_SPL_NAND_RAW_ONLY)
 int spl_nand_load_image(void)
@@ -24,6 +26,19 @@ int spl_nand_load_image(void)
 	return 0;
 }
 #else
+
+static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
+			       ulong size, void *dst)
+{
+	int ret;
+
+	ret = nand_spl_load_image(offs, size, dst);
+	if (!ret)
+		return size;
+	else
+		return 0;
+}
+
 static int spl_nand_load_element(int offset, struct image_header *header)
 {
 	int err;
@@ -32,12 +47,24 @@ static int spl_nand_load_element(int offset, struct image_header *header)
 	if (err)
 		return err;
 
-	err = spl_parse_image_header(header);
-	if (err)
-		return err;
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
 
-	return nand_spl_load_image(offset, spl_image.size,
-				   (void *)(unsigned long)spl_image.load_addr);
+		debug("Found FIT\n");
+		load.dev = NULL;
+		load.priv = NULL;
+		load.filename = NULL;
+		load.bl_len = 1;
+		load.read = spl_nand_fit_read;
+		return spl_load_simple_fit(&load, offset, header);
+	} else {
+		err = spl_parse_image_header(header);
+		if (err)
+			return err;
+		return nand_spl_load_image(offset, spl_image.size,
+					   (void *)(ulong)spl_image.load_addr);
+	}
 }
 
 int spl_nand_load_image(void)
-- 
cgit v0.10.2


From cfe32a4be24da8cf51bbbfa57ddd7cbddade2f43 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:43 +0530
Subject: spl: fit: Do not print selected dtb during fit load

No prints should be allowed during UART load.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index fb69f1d..a828f72 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -67,9 +67,7 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 
 		*fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
 		len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		printf("FIT: Selected '%s'\n", name);
-#endif
+		debug("FIT: Selected '%s'\n", name);
 
 		return len;
 	}
-- 
cgit v0.10.2


From fa715193c083bbde4985c4ff1e49e288ec29763a Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 24 May 2016 10:34:44 +0530
Subject: spl: Add an option to load a FIT containing U-Boot from UART

This provides a way to load a FIT containing U-Boot and a selection of device
tree files from UART.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 4f26ea5..5402301 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -14,15 +14,60 @@
 #include <xyzModem.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
+#include <libfdt.h>
 
 #define BUF_SIZE 1024
 
+/*
+ * Information required to load image using ymodem.
+ *
+ * @image_read: Now of bytes read from the image.
+ * @buf: pointer to the previous read block.
+ */
+struct ymodem_fit_info {
+	int image_read;
+	char *buf;
+};
+
 static int getcymodem(void) {
 	if (tstc())
 		return (getc());
 	return -1;
 }
 
+static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset,
+			     ulong size, void *addr)
+{
+	int res, err;
+	struct ymodem_fit_info *info = load->priv;
+	char *buf = info->buf;
+
+	while (info->image_read < offset) {
+		res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+		if (res <= 0)
+			return res;
+		info->image_read += res;
+	}
+
+	if (info->image_read > offset) {
+		res = info->image_read - offset;
+		memcpy(addr, &buf[BUF_SIZE - res], res);
+		addr = addr + res;
+	}
+
+	while (info->image_read < offset + size) {
+		res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+		if (res <= 0)
+			return res;
+
+		memcpy(addr, buf, res);
+		info->image_read += res;
+		addr += res;
+	}
+
+	return size;
+}
+
 int spl_ymodem_load_image(void)
 {
 	int size = 0;
@@ -31,30 +76,55 @@ int spl_ymodem_load_image(void)
 	int ret;
 	connection_info_t info;
 	char buf[BUF_SIZE];
-	ulong store_addr = ~0;
 	ulong addr = 0;
 
 	info.mode = xyzModem_ymodem;
 	ret = xyzModem_stream_open(&info, &err);
+	if (ret) {
+		printf("spl: ymodem err - %s\n", xyzModem_error(err));
+		return ret;
+	}
+
+	res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+	if (res <= 0)
+		goto end_stream;
+
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
+		struct spl_load_info load;
+		struct ymodem_fit_info info;
+
+		debug("Found FIT\n");
+		load.dev = NULL;
+		load.priv = (void *)&info;
+		load.filename = NULL;
+		load.bl_len = 1;
+		info.buf = buf;
+		info.image_read = BUF_SIZE;
+		load.read = ymodem_read_fit;
+		ret =  spl_load_simple_fit(&load, 0, (void *)buf);
+		size = info.image_read;
 
-	if (!ret) {
-		while ((res =
-			xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
-			if (addr == 0) {
-				ret = spl_parse_image_header((struct image_header *)buf);
-				if (ret)
-					return ret;
-			}
-			store_addr = addr + spl_image.load_addr;
+		while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0)
+			size += res;
+	} else {
+		spl_parse_image_header((struct image_header *)buf);
+		ret = spl_parse_image_header((struct image_header *)buf);
+		if (ret)
+			return ret;
+		addr = spl_image.load_addr;
+		memcpy((void *)addr, buf, res);
+		size += res;
+		addr += res;
+
+		while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+			memcpy((void *)addr, buf, res);
 			size += res;
 			addr += res;
-			memcpy((char *)(store_addr), buf, res);
 		}
-	} else {
-		printf("spl: ymodem err - %s\n", xyzModem_error(err));
-		return ret;
 	}
 
+end_stream:
 	xyzModem_stream_close(&err);
 	xyzModem_stream_terminate(false, &getcymodem);
 
-- 
cgit v0.10.2


From e35eb0391a2c77848a422b1b02ee29bc7f0a3e6d Mon Sep 17 00:00:00 2001
From: Chris Packham <judge.packham@gmail.com>
Date: Fri, 13 May 2016 13:08:56 +1200
Subject: Remove unused BOOTFLAG definitions

This follows on from commit d98b052 ("powerpc: Cleanup BOOTFLAG_*
references") and commit fc3d297 ("Drop bogus BOOTFLAG_* definitions").
Remove the definitions that have crept in since.

Signed-off-by: Chris Packham <judge.packham@gmail.com>

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f398b37..4d08555 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -822,14 +822,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 
 /*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-/*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index bcf6942..f0b5b3e 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -449,14 +449,6 @@
 
 #define CONFIG_HIGH_BATS		1	/* High BATs supported */
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD			0x01
-#define BOOTFLAG_WARM			0x02
-
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
 #endif
-- 
cgit v0.10.2


From 09da87dafddef530e62ca1dc2655819dda1d28ee Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 10:51:23 +0530
Subject: board: dra7: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index d01c785..3fbbc9b 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -727,3 +727,15 @@ int ft_board_setup(void *blob, bd_t *bd)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_dra72x() && !strcmp(name, "dra72-evm"))
+		return 0;
+	else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
+		return 0;
+	else
+		return -1;
+}
+#endif
-- 
cgit v0.10.2


From bd7245849f7ce1c0d2707b7f213d5df1f99284c8 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 10:51:24 +0530
Subject: ARM: DRA7: Enable FIT

Use a single defconfig for all DRA7 platforms by enabling FIT and delete
the platform specific defconfigs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
index 3f638d0..5ec6769 100644
--- a/board/ti/dra7xx/MAINTAINERS
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -3,8 +3,6 @@ M:	Lokesh Vutla <lokeshvutla@ti.com>
 S:	Maintained
 F:	board/ti/dra7xx/
 F:	include/configs/dra7xx_evm.h
-F:	configs/dra72_evm_defconfig
-F:	configs/dra74_evm_defconfig
 F:	configs/dra7xx_evm_defconfig
 F:	configs/dra7xx_evm_qspiboot_defconfig
 F:	configs/dra7xx_evm_uart3_defconfig
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
deleted file mode 100644
index c85c0fb..0000000
--- a/configs/dra72_evm_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
deleted file mode 100644
index a8462ca..0000000
--- a/configs/dra74_evm_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_DM_ETH=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index b6458ae..288f8b3 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -1,11 +1,17 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
@@ -25,11 +31,16 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
@@ -40,4 +51,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
-- 
cgit v0.10.2


From cfd921f7cc8cb54320e2b2ac4dc9ec13fc4f96c3 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 10:51:25 +0530
Subject: ARM: DRA7: configs: Remove obsolete configs

Removing:
uart3_defconfig:
Now uart3 can be selected using menuconfig, removing separate
config for uart mode. Doing uart boot is not straight forward as ROM uses
uart3 as default serial console. In order to boot to prompt, concole in both
u-boot and kernel needs to be changed.

qspiboot_defconfig:
The only advantage of enabling QSPI_BOOT is selecting env in QSPI.
Eventually env needs to be selected by menuconfig so removing
qspiboot_defconfig. qspiboot can be done using dra7xx_evm_defconfig.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
index 5ec6769..907cb13 100644
--- a/board/ti/dra7xx/MAINTAINERS
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -4,5 +4,3 @@ S:	Maintained
 F:	board/ti/dra7xx/
 F:	include/configs/dra7xx_evm.h
 F:	configs/dra7xx_evm_defconfig
-F:	configs/dra7xx_evm_qspiboot_defconfig
-F:	configs/dra7xx_evm_uart3_defconfig
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig
deleted file mode 100644
index 8ebfe49..0000000
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
deleted file mode 100644
index 54c7ba9..0000000
--- a/configs/dra7xx_evm_uart3_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
-- 
cgit v0.10.2


From 5a3775a4222df71bb5da38961c76ef7bcadac1cd Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:11:15 +0530
Subject: board: AM43xx: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 7247107..34f5d06 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -846,3 +846,15 @@ int board_eth_init(bd_t *bis)
 	return rv;
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+		return 0;
+	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+		return 0;
+	else
+		return -1;
+}
+#endif
-- 
cgit v0.10.2


From 4c4e3b37750f3fa1300ce2b69b148d21f6802051 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:11:16 +0530
Subject: ARM: AM43xx: Enable FIT

Use a single defconfig for all AM43xx platforms by enabling FIT and delete
the platform specific defconfigs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
index 96ef85b..3d40b17 100644
--- a/board/ti/am43xx/MAINTAINERS
+++ b/board/ti/am43xx/MAINTAINERS
@@ -7,5 +7,3 @@ F:	configs/am43xx_evm_defconfig
 F:	configs/am43xx_evm_qspiboot_defconfig
 F:	configs/am43xx_evm_ethboot_defconfig
 F:	configs/am43xx_evm_usbhost_boot_defconfig
-F:	configs/am437x_gp_evm_defconfig
-F:	configs/am437x_sk_evm_defconfig
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
deleted file mode 100644
index e98412a..0000000
--- a/configs/am437x_gp_evm_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_ARM=y
-CONFIG_AM43XX=y
-CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0403
-CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_DM_ETH=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
deleted file mode 100644
index b665331..0000000
--- a/configs/am437x_sk_evm_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_AM43XX=y
-CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DMA=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0403
-CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_DM_ETH=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 12d3fb7..1f88e68 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -1,8 +1,15 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -24,11 +31,16 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
@@ -39,5 +51,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_SPL_OF_LIBFDT=y
-- 
cgit v0.10.2


From 7dd12830482bd145861578e37b39735abefdaa8f Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:11:17 +0530
Subject: ARM: dts: AM43x-EPOS Initial Support

Add initial DTS support for AM43-EPOS evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 751bbd1..5884d8d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -92,7 +92,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
-dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
+dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
+	am43x-epos-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts
new file mode 100644
index 0000000..fa4d1e3
--- /dev/null
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -0,0 +1,806 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM43x EPOS EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
+
+/ {
+	model = "TI AM43x EPOS EVM";
+	compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
+
+	aliases {
+		display0 = &lcd0;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	vmmcsd_fixed: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcsd_fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	lcd0: display {
+		compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+		label = "lcd";
+
+		panel-timing {
+			clock-frequency = <33000000>;
+			hactive = <800>;
+			vactive = <480>;
+			hfront-porch = <210>;
+			hback-porch = <16>;
+			hsync-len = <30>;
+			vback-porch = <10>;
+			vfront-porch = <22>;
+			vsync-len = <13>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <1>;
+		};
+
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+
+	matrix_keypad: matrix_keypad@0 {
+		compatible = "gpio-matrix-keypad";
+		debounce-delay-ms = <5>;
+		col-scan-delay-us = <2>;
+
+		row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH		/* Bank0, pin12 */
+			     &gpio0 13 GPIO_ACTIVE_HIGH		/* Bank0, pin13 */
+			     &gpio0 14 GPIO_ACTIVE_HIGH		/* Bank0, pin14 */
+			     &gpio0 15 GPIO_ACTIVE_HIGH>;	/* Bank0, pin15 */
+
+		col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH		/* Bank3, pin9 */
+			     &gpio3 10 GPIO_ACTIVE_HIGH		/* Bank3, pin10 */
+			     &gpio2 18 GPIO_ACTIVE_HIGH		/* Bank2, pin18 */
+			     &gpio2 19 GPIO_ACTIVE_HIGH>;	/* Bank2, pin19 */
+
+		linux,keymap = <0x00000201	/* P1 */
+			0x01000204	/* P4 */
+			0x02000207	/* P7 */
+			0x0300020a	/* NUMERIC_STAR */
+			0x00010202	/* P2 */
+			0x01010205	/* P5 */
+			0x02010208	/* P8 */
+			0x03010200	/* P0 */
+			0x00020203	/* P3 */
+			0x01020206	/* P6 */
+			0x02020209	/* P9 */
+			0x0302020b	/* NUMERIC_POUND */
+			0x00030067	/* UP */
+			0x0103006a	/* RIGHT */
+			0x0203006c	/* DOWN */
+			0x03030069>;	/* LEFT */
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 51 53 56 62 75 101 152 255>;
+		default-brightness-level = <8>;
+	};
+
+	sound0: sound@0 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "AM43-EPOS-EVM";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"MIC1LP", "Microphone Jack",
+			"MIC1RP", "Microphone Jack",
+			"MIC1LP", "MICBIAS",
+			"MIC1RP", "MICBIAS",
+			"Headphone Jack", "HPL",
+			"Headphone Jack", "HPR",
+			"Speaker", "SPL",
+			"Speaker", "SPR";
+		simple-audio-card,format = "dsp_b";
+		simple-audio-card,bitclock-master = <&sound0_master>;
+		simple-audio-card,frame-master = <&sound0_master>;
+		simple-audio-card,bitclock-inversion;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+			system-clock-frequency = <12000000>;
+		};
+
+		sound0_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic3111>;
+			system-clock-frequency = <12000000>;
+		};
+	};
+};
+
+&am43xx_pinmux {
+		cpsw_default: cpsw_default {
+			pinctrl-single,pins = <
+				/* Slave 1 */
+				AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs */
+				AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+				AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
+				AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxdv.rmii1_rxdv */
+				AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
+				AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
+				AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
+				AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
+				AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
+			>;
+		};
+
+		cpsw_sleep: cpsw_sleep {
+			pinctrl-single,pins = <
+				/* Slave 1 reset value */
+				AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+
+		davinci_mdio_default: davinci_mdio_default {
+			pinctrl-single,pins = <
+				/* MDIO */
+				AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+				AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			>;
+		};
+
+		davinci_mdio_sleep: davinci_mdio_sleep {
+			pinctrl-single,pins = <
+				/* MDIO reset value */
+				AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+
+		i2c0_pins: pinmux_i2c0_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			>;
+		};
+
+		nand_flash_x8: nand_flash_x8 {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.SELQSPIorNAND/GPIO */
+				AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+				AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+				AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+				AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+				AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+				AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+				AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+				AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+				AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+				AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
+				AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+				AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+				AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+				AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+				AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			>;
+		};
+
+		ecap0_pins: backlight_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x964, MUX_MODE0)         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+			>;
+		};
+
+		i2c2_pins: pinmux_i2c2_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
+				AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
+			>;
+		};
+
+		spi0_pins: pinmux_spi0_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
+				AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
+				AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
+				AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
+			>;
+		};
+
+		spi1_pins: pinmux_spi1_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
+				AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
+				AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
+				AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
+			>;
+		};
+
+		mmc1_pins: pinmux_mmc1_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			>;
+		};
+
+		qspi1_default: qspi1_default {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
+				AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
+			>;
+		};
+
+		pixcir_ts_pins: pixcir_ts_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a1.gpio1_17 */
+			>;
+		};
+
+		hdq_pins: pinmux_hdq_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
+			>;
+		};
+
+		dss_pins: dss_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+				AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+				AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+				AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+				AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+				AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+				AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+				AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+			>;
+		};
+
+		display_mux_pins: display_mux_pins {
+			pinctrl-single,pins = <
+				/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
+				AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
+			>;
+		};
+
+		vpfe1_pins_default: vpfe1_pins_default {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0 */
+				AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0 */
+				AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0 */
+				AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0 */
+				AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0 */
+				AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0 */
+				AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0 */
+				AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0 */
+				AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0 */
+				AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0 */
+				AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0 */
+				AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0 */
+				AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0 */
+			>;
+		};
+
+		vpfe1_pins_sleep: vpfe1_pins_sleep {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			>;
+		};
+
+		mcasp1_pins: mcasp1_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
+				AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
+				AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
+				AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
+			>;
+		};
+
+		mcasp1_sleep_pins: mcasp1_sleep_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmcsd_fixed>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <16>;
+	phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rmii";
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+
+	tps65218: tps65218@24 {
+		reg = <0x24>;
+		compatible = "ti,tps65218";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		dcdc1: regulator-dcdc1 {
+			compatible = "ti,tps65218-dcdc1";
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc2: regulator-dcdc2 {
+			compatible = "ti,tps65218-dcdc2";
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1378000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3: regulator-dcdc3 {
+			compatible = "ti,tps65218-dcdc3";
+			regulator-name = "vdcdc3";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc4: regulator-dcdc4 {
+			compatible = "ti,tps65218-dcdc4";
+			regulator-name = "vdcdc4";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc5: regulator-dcdc5 {
+			compatible = "ti,tps65218-dcdc5";
+			regulator-name = "v1_0bat";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+		};
+
+		dcdc6: regulator-dcdc6 {
+			compatible = "ti,tps65218-dcdc6";
+			regulator-name = "v1_8bat";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		ldo1: regulator-ldo1 {
+			compatible = "ti,tps65218-ldo1";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+
+	at24@50 {
+		compatible = "at24,24c256";
+		pagesize = <64>;
+		reg = <0x50>;
+	};
+
+	pixcir_ts@5c {
+		compatible = "pixcir,pixcir_tangoc";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pixcir_ts_pins>;
+		reg = <0x5c>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+
+		attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+
+		touchscreen-size-x = <1024>;
+		touchscreen-size-y = <600>;
+	};
+
+	tlv320aic3111: tlv320aic3111@18 {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3111";
+		reg = <0x18>;
+		status = "okay";
+
+		ai31xx-micbias-vg = <MICBIAS_2_0V>;
+
+		/* Regulators */
+		HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+		SPRVDD-supply = <&vbat>; /* vbat */
+		SPLVDD-supply = <&vbat>; /* vbat */
+		AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+		IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
+		DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&display_mux_pins>;
+	status = "okay";
+
+	p1 {
+		/*
+		 * SelLCDorHDMI selects between display and audio paths:
+		 * Low: HDMI display with audio via HDMI
+		 * High: LCD display with analog audio via aic3111 codec
+		 */
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "SelLCDorHDMI";
+	};
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";	/* Disable QSPI when enabling GPMC (NAND) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x8>;
+	ranges = <0 0 0x08000000 0x01000000>;	/* CS0 space. Min partition = 16MB */
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		ti,nand-ecc-opt = "bch16";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
+		gpmc,cs-wr-off-ns = <40>;
+		gpmc,adv-on-ns = <0>;  /* cs-on-ns */
+		gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
+		gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
+		gpmc,we-on-ns = <0>;   /* cs-on-ns */
+		gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
+		gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
+		gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
+		gpmc,access-ns = <30>; /* tCEA + 4*/
+		gpmc,rd-cycle-ns = <40>;
+		gpmc,wr-cycle-ns = <40>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x000C0000 0x00040000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00100000 0x00080000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x00180000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x00280000 0x00040000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x002C0000 0x00040000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00300000 0x00700000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x1f600000>;
+		};
+	};
+};
+
+&epwmss0 {
+	status = "okay";
+};
+
+&tscadc {
+	status = "okay";
+
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&ecap0 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap0_pins>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+	status = "okay";
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_phy2 {
+	status = "okay";
+};
+
+&usb2 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&qspi {
+	status = "disabled";	/* Disable GPMC (NAND) when enabling QSPI */
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_default>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first 512KiB
+		 * for a valid file to boot(XIP).
+		 */
+		partition@0 {
+			label = "QSPI.U_BOOT";
+			reg = <0x00000000 0x000080000>;
+		};
+		partition@1 {
+			label = "QSPI.U_BOOT.backup";
+			reg = <0x00080000 0x00080000>;
+		};
+		partition@2 {
+			label = "QSPI.U-BOOT-SPL_OS";
+			reg = <0x00100000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.U_BOOT_ENV";
+			reg = <0x00110000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.U-BOOT-ENV.backup";
+			reg = <0x00120000 0x00010000>;
+		};
+		partition@5 {
+			label = "QSPI.KERNEL";
+			reg = <0x00130000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.FILESYSTEM";
+			reg = <0x00930000 0x36D0000>;
+		};
+	};
+};
+
+&hdq {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdq_pins>;
+};
+
+&dss {
+	status = "ok";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&dss_pins>;
+
+	port {
+		dpi_out: endpoint@0 {
+			remote-endpoint = <&lcd_in>;
+			data-lines = <24>;
+		};
+	};
+};
+
+&vpfe1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&vpfe1_pins_default>;
+	pinctrl-1 = <&vpfe1_pins_sleep>;
+
+	port {
+		vpfe1_ep: endpoint {
+			/* remote-endpoint = <&sensor>; add once we have it */
+			ti,am437x-vpfe-interface = <0>;
+			bus-width = <8>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+		};
+	};
+};
+
+&mcasp1 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mcasp1_pins>;
+	pinctrl-1 = <&mcasp1_sleep_pins>;
+
+	status = "okay";
+
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	/* 4 serializer */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+		1 2 0 0
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
+
+&synctimer_32kclk {
+	assigned-clocks = <&mux_synctimer32k_ck>;
+	assigned-clock-parents = <&clkdiv32k_ick>;
+};
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 34f5d06..c0d5335 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -854,6 +854,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 		return 0;
+	else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 1f88e68..57f70ab 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm"
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
index 7203687..292c2eb 100644
--- a/include/dt-bindings/pinctrl/am43xx.h
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -30,4 +30,10 @@
 #define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
 #define PIN_INPUT_PULLDOWN	(INPUT_EN)
 
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define AM4372_IOPAD(pa, val)	(((pa) & 0xffff) - 0x0800) (val)
+
 #endif
diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
new file mode 100644
index 0000000..f5cb772
--- /dev/null
+++ b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
@@ -0,0 +1,8 @@
+#ifndef __DT_TLV320AIC31XX_MICBIAS_H
+#define __DT_TLV320AIC31XX_MICBIAS_H
+
+#define MICBIAS_2_0V		1
+#define MICBIAS_2_5V		2
+#define MICBIAS_AVDDV		3
+
+#endif /* __DT_TLV320AIC31XX_MICBIAS_H */
-- 
cgit v0.10.2


From 54a92e1ad8c699299abf12beecc0b9448df2623d Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:11:18 +0530
Subject: ARM: dts: AM437x-IDK Initial Support

Add initial DTS support for AM437x-IDK evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5884d8d..a833a68 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,7 +93,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
-	am43x-epos-evm.dtb
+	am43x-epos-evm.dtb \
+	am437x-idk-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
new file mode 100644
index 0000000..478f0a6
--- /dev/null
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "TI AM437x Industrial Development Kit";
+	compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	v24_0d: fixed-regulator-v24_0d {
+		compatible = "regulator-fixed";
+		regulator-name = "V24_0D";
+		regulator-min-microvolt = <24000000>;
+		regulator-max-microvolt = <24000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	v3_3d: fixed-regulator-v3_3d {
+		compatible = "regulator-fixed";
+		regulator-name = "V3_3D";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	vdd_corereg: fixed-regulator-vdd_corereg {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_COREREG";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	vdd_core: fixed-regulator-vdd_core {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_CORE";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vdd_corereg>;
+	};
+
+	v1_8dreg: fixed-regulator-v1_8dreg{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_8DREG";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	v1_8d: fixed-regulator-v1_8d{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_8D";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v1_8dreg>;
+	};
+
+	v1_5dreg: fixed-regulator-v1_5dreg{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_5DREG";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	v1_5d: fixed-regulator-v1_5d{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_5D";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v1_5dreg>;
+	};
+
+	gpio_keys: gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_keys_pins_default>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0 {
+			label = "power-button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	/* fixed 32k external oscillator clock */
+	clk_32k_rtc: clk_32k_rtc {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+};
+
+&am43xx_pinmux {
+	gpio_keys_pins_default: gpio_keys_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7)	/* cam0_field.gpio4_2 */
+		>;
+	};
+
+	i2c0_pins_default: i2c0_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+			AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c0_pins_sleep: i2c0_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	i2c2_pins_default: i2c2_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+			AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
+		>;
+	};
+
+	i2c2_pins_sleep: i2c2_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	mmc1_pins_default: pinmux_mmc1_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+			AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+			AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+			AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+			AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+			AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+			AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	ecap0_pins_default: backlight_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td2 */
+			AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td3 */
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd2 */
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd3 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	qspi_pins_default: qspi_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3)	/* gpmc_csn0.qspi_csn */
+			AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2)		/* gpmc_csn3.qspi_clk */
+			AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_advn_ale.qspi_d0 */
+			AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_oen_ren.qspi_d1 */
+			AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_wen.qspi_d2 */
+			AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_be0n_cle.qspi_d3 */
+		>;
+	};
+
+	qspi_pins_sleep: qspi_pins_sleep{
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c0_pins_default>;
+	pinctrl-1 = <&i2c0_pins_sleep>;
+	clock-frequency = <400000>;
+
+	at24@50 {
+		compatible = "at24,24c256";
+		pagesize = <64>;
+		reg = <0x50>;
+	};
+
+	tps: tps62362@60 {
+		compatible = "ti,tps62362";
+		reg = <0x60>;
+		regulator-name = "VDD_MPU";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1330000>;
+		regulator-boot-on;
+		regulator-always-on;
+		ti,vsel0-state-high;
+		ti,vsel1-state-high;
+		vin-supply = <&v3_3d>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c2_pins_default>;
+	pinctrl-1 = <&i2c2_pins_sleep>;
+	clock-frequency = <100000>;
+};
+
+&epwmss0 {
+	status = "okay";
+};
+
+&ecap0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&ecap0_pins_default>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&mmc1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mmc1_pins_default>;
+	pinctrl-1 = <&mmc1_pins_sleep>;
+	vmmc-supply = <&v3_3d>;
+	bus-width = <4>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&qspi_pins_default>;
+	pinctrl-1 = <&qspi_pins_sleep>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * MTD partition table.  The ROM checks the first 512KiB for a
+		 * valid file to boot(XIP).
+		 */
+		partition@0 {
+			label = "QSPI.U_BOOT";
+			reg = <0x00000000 0x000080000>;
+		};
+		partition@1 {
+			label = "QSPI.U_BOOT.backup";
+			reg = <0x00080000 0x00080000>;
+		};
+		partition@2 {
+			label = "QSPI.U-BOOT-SPL_OS";
+			reg = <0x00100000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.U_BOOT_ENV";
+			reg = <0x00110000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.U-BOOT-ENV.backup";
+			reg = <0x00120000 0x00010000>;
+		};
+		partition@5 {
+			label = "QSPI.KERNEL";
+			reg = <0x00130000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.FILESYSTEM";
+			reg = <0x00930000 0x36D0000>;
+		};
+	};
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii";
+};
+
+&rtc {
+	clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+	clock-names = "ext-clk", "int-clk";
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&cpu {
+	cpu0-supply = <&tps>;
+};
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index c0d5335..b42546a 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -856,6 +856,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 		return 0;
+	else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 57f70ab..3955612 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm"
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
-- 
cgit v0.10.2


From 3c5835955aecaacc5abd8af043a7becda009eddb Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:11:19 +0530
Subject: ARM: AM43xx: configs: Update usb host boot defconfig

Convert usb host boot defconfig to use DM, DT. Also enable FIT
support.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 1f73114..72f4ad8 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,8 +1,13 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
 CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -25,10 +30,15 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
@@ -41,3 +51,7 @@ CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
-- 
cgit v0.10.2


From 505ea6e82a3c7eafd946cee788f8985e7573bf52 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:24:24 +0530
Subject: board: am33xx: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs a way to
detect the right dtb to be used. Adding support for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 4330be6..a3d1e2b 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -632,3 +632,17 @@ int board_eth_init(bd_t *bis)
 #endif
 
 #endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
+		return 0;
+	else if (board_is_bone() && !strcmp(name, "am335x-bone"))
+		return 0;
+	else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+		return 0;
+	else
+		return -1;
+}
+#endif
-- 
cgit v0.10.2


From a1b4885153c5fbc26ace38292dee3b3f2b86e3e8 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:24:25 +0530
Subject: ARM: dts: am335x-bone: Enable uart and timer

Allow am335x-bone.dts to be built and enable uart and timer
for all beaglebones.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a833a68..5d2910d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -91,7 +91,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index fec7834..a00c0cd 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -13,6 +13,11 @@
 		};
 	};
 
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts
index 81441cc..6b84937 100644
--- a/arch/arm/dts/am335x-bone.dts
+++ b/arch/arm/dts/am335x-bone.dts
@@ -13,9 +13,6 @@
 / {
 	model = "TI AM335x BeagleBone";
 	compatible = "ti,am335x-bone", "ti,am33xx";
-	chosen {
-		stdout-path = &uart0;
-	};
 };
 
 &ldo3_reg {
-- 
cgit v0.10.2


From 80b24fcd3083515e6b9615868debb8891181e1e4 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:24:26 +0530
Subject: ARM: AM335x: Enable FIT

Use a single defconfig for all AM335x platforms by enabling FIT

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index 7dc2b83..c99e06d 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -6,7 +6,6 @@ F:	include/configs/am335x_evm.h
 F:	configs/am335x_boneblack_defconfig
 F:	configs/am335x_boneblack_vboot_defconfig
 F:	configs/am335x_evm_defconfig
-F:	configs/am335x_gp_evm_defconfig
 F:	configs/am335x_evm_nor_defconfig
 F:	configs/am335x_evm_norboot_defconfig
 F:	configs/am335x_evm_spiboot_defconfig
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 2430381..3e68744 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,15 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_AM335X_EVM=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
@@ -30,9 +26,14 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
@@ -43,3 +44,8 @@ CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
 CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
+CONFIG_RSA=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack"
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
deleted file mode 100644
index d7f126e..0000000
--- a/configs/am335x_gp_evm_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_AM335X_EVM=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_RSA=y
-- 
cgit v0.10.2


From 2c6485bc7cdf3d7d7449c0cda87eb8512c0e5ef5 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 16 May 2016 11:24:27 +0530
Subject: ARM: dts: am335x: fix cd-gpios definition as per hardware design and
 dt binding docs

As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.

In AM335x the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index a00c0cd..40a3c35 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -388,8 +388,7 @@
 	bus-width = <0x4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
-	cd-inverted;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &aes {
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index c0bc2af..a6f20af 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -717,7 +717,7 @@
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &mmc3 {
-- 
cgit v0.10.2


From 3819ea70635d15595df5bc2d0b1cc81245b1e1cf Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:24:28 +0530
Subject: ARM: dts: AM335x-evmsk: Add initial support

Add initial DTS support for AM335x-evm sk.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5d2910d..587d220 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -91,7 +91,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
+	am335x-evmsk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
new file mode 100644
index 0000000..b3e9b61
--- /dev/null
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -0,0 +1,720 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x Starter Kit
+ * http://www.ti.com/tool/tmdssk3358
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "TI AM335x EVM-SK";
+	compatible = "ti,am335x-evmsk", "ti,am33xx";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	lis3_reg: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "lis3_reg";
+		regulator-boot-on;
+	};
+
+	wl12xx_vmmc: fixedregulator@2 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&wl12xx_gpio>;
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1271";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 29 0>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	vtt_fixed: fixedregulator@3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds_s0>;
+
+		compatible = "gpio-leds";
+
+		led@1 {
+			label = "evmsk:green:usr0";
+			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "evmsk:green:usr1";
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "evmsk:green:mmc0";
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "evmsk:green:heartbeat";
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+		};
+	};
+
+	gpio_buttons: gpio_buttons@0 {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@1 {
+			label = "button0";
+			linux,code = <0x100>;
+			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		switch@2 {
+			label = "button1";
+			linux,code = <0x101>;
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		switch@3 {
+			label = "button2";
+			linux,code = <0x102>;
+			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+			wakeup-source;
+		};
+
+		switch@4 {
+			label = "button3";
+			linux,code = <0x103>;
+			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 58 61 66 75 90 125 170 255>;
+		default-brightness-level = <8>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "AM335x-EVMSK";
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"Headphone Jack",	"HPLOUT",
+			"Headphone Jack",	"HPROUT";
+		simple-audio-card,format = "dsp_b";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+		simple-audio-card,bitclock-inversion;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+		};
+
+		sound_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic3106>;
+			system-clock-frequency = <24000000>;
+		};
+	};
+
+	panel {
+		compatible = "ti,tilcdc,panel";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&lcd_pins_default>;
+		pinctrl-1 = <&lcd_pins_sleep>;
+		status = "okay";
+		panel-info {
+			ac-bias           = <255>;
+			ac-bias-intrpt    = <0>;
+			dma-burst-sz      = <16>;
+			bpp               = <32>;
+			fdd               = <0x80>;
+			sync-edge         = <0>;
+			sync-ctrl         = <1>;
+			raster-order      = <0>;
+			fifo-th           = <0>;
+		};
+		display-timings {
+			480x272 {
+				hactive         = <480>;
+				vactive         = <272>;
+				hback-porch     = <43>;
+				hfront-porch    = <8>;
+				hsync-len       = <4>;
+				vback-porch     = <12>;
+				vfront-porch    = <4>;
+				vsync-len       = <10>;
+				clock-frequency = <9000000>;
+				hsync-active    = <0>;
+				vsync-active    = <0>;
+			};
+		};
+	};
+};
+
+&am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
+
+	lcd_pins_default: lcd_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
+			AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
+			AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
+			AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
+			AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
+			AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
+			AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
+			AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
+			AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data0.lcd_data0 */
+			AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data1.lcd_data1 */
+			AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data2.lcd_data2 */
+			AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)	/* lcd_data3.lcd_data3 */
+			AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data4.lcd_data4 */
+			AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data5.lcd_data5 */
+			AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data6.lcd_data6 */
+			AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data7.lcd_data7 */
+			AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data8.lcd_data8 */
+			AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data9.lcd_data9 */
+			AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data10.lcd_data10 */
+			AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data11.lcd_data11 */
+			AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data12.lcd_data12 */
+			AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data13.lcd_data13 */
+			AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data14.lcd_data14 */
+			AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data15.lcd_data15 */
+			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
+			AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
+			AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
+			AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+		>;
+	};
+
+	lcd_pins_sleep: lcd_pins_sleep {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad8.lcd_data23 */
+			AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad9.lcd_data22 */
+			AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad10.lcd_data21 */
+			AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad11.lcd_data20 */
+			AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad12.lcd_data19 */
+			AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad13.lcd_data18 */
+			AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad14.lcd_data17 */
+			AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad15.lcd_data16 */
+			AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)	/* lcd_data0.lcd_data0 */
+			AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)	/* lcd_data1.lcd_data1 */
+			AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)	/* lcd_data2.lcd_data2 */
+			AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)	/* lcd_data3.lcd_data3 */
+			AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)	/* lcd_data4.lcd_data4 */
+			AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)	/* lcd_data5.lcd_data5 */
+			AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)	/* lcd_data6.lcd_data6 */
+			AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)	/* lcd_data7.lcd_data7 */
+			AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)	/* lcd_data8.lcd_data8 */
+			AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)	/* lcd_data9.lcd_data9 */
+			AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)	/* lcd_data10.lcd_data10 */
+			AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)	/* lcd_data11.lcd_data11 */
+			AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)	/* lcd_data12.lcd_data12 */
+			AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)	/* lcd_data13.lcd_data13 */
+			AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)	/* lcd_data14.lcd_data14 */
+			AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)	/* lcd_data15.lcd_data15 */
+			AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_vsync.lcd_vsync */
+			AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.lcd_hsync */
+			AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_pclk.lcd_pclk */
+			AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+		>;
+	};
+
+
+	user_leds_s0: user_leds_s0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
+			AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
+			AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
+			AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
+		>;
+	};
+
+	gpio_keys_s0: gpio_keys_s0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
+			AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
+			AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
+			AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
+		>;
+	};
+
+	i2c0_pins: pinmux_i2c0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+		>;
+	};
+
+	clkout2_pin: pinmux_clkout2_pin {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+		>;
+	};
+
+	ecap2_pins: backlight_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x99c, MUX_MODE4)	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
+			AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
+			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+
+			/* Slave 2 */
+			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
+			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
+			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
+			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
+			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
+			AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+			/* Slave 2 reset value*/
+			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	mcasp1_pins: mcasp1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+			AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+		>;
+	};
+
+	mcasp1_pins_sleep: mcasp1_pins_sleep {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+		>;
+	};
+
+	wl12xx_gpio: pinmux_wl12xx_gpio {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+		>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: tps@2d {
+		reg = <0x2d>;
+	};
+
+	lis331dlh: lis331dlh@18 {
+		compatible = "st,lis331dlh", "st,lis3lv02d";
+		reg = <0x18>;
+		Vdd-supply = <&lis3_reg>;
+		Vdd_IO-supply = <&lis3_reg>;
+
+		st,click-single-x;
+		st,click-single-y;
+		st,click-single-z;
+		st,click-thresh-x = <10>;
+		st,click-thresh-y = <10>;
+		st,click-thresh-z = <10>;
+		st,irq1-click;
+		st,irq2-click;
+		st,wakeup-x-lo;
+		st,wakeup-x-hi;
+		st,wakeup-y-lo;
+		st,wakeup-y-hi;
+		st,wakeup-z-lo;
+		st,wakeup-z-hi;
+		st,min-limit-x = <120>;
+		st,min-limit-y = <120>;
+		st,min-limit-z = <140>;
+		st,max-limit-x = <550>;
+		st,max-limit-y = <550>;
+		st,max-limit-z = <750>;
+	};
+
+	tlv320aic3106: tlv320aic3106@1b {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3106";
+		reg = <0x1b>;
+		status = "okay";
+
+		/* Regulators */
+		AVDD-supply = <&vaux2_reg>;
+		IOVDD-supply = <&vaux2_reg>;
+		DRVDD-supply = <&vaux2_reg>;
+		DVDD-supply = <&vbat>;
+	};
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb1_phy {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&cppi41dma  {
+	status = "okay";
+};
+
+&epwmss2 {
+	status = "okay";
+
+	ecap2: ecap@48304100 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap2_pins>;
+	};
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1312500>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	dual_emac = <1>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii-txid";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rgmii-txid";
+	dual_emac_res_vlan = <2>;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmc_reg>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+	status = "okay";
+};
+
+&aes {
+	status = "okay";
+};
+
+&gpio0 {
+	ti,no-reset-on-init;
+};
+
+&mmc2 {
+	status = "okay";
+	vmmc-supply = <&wl12xx_vmmc>;
+	ti,non-removable;
+	bus-width = <4>;
+	cap-power-off-card;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1271";
+		reg = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+		ref-clock-frequency = <38400000>;
+	};
+};
+
+&mcasp1 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mcasp1_pins>;
+	pinctrl-1 = <&mcasp1_pins_sleep>;
+
+	status = "okay";
+
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	/* 4 serializers */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+		0 0 1 2
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
+
+&tscadc {
+	status = "okay";
+	tsc {
+		ti,wires = <4>;
+		ti,x-plate-resistance = <200>;
+		ti,coordinate-readouts = <5>;
+		ti,wire-config = <0x00 0x11 0x22 0x33>;
+	};
+};
+
+&lcdc {
+      status = "okay";
+};
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index a3d1e2b..89b12a5 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -642,6 +642,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 		return 0;
+	else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 3e68744..a2794c2 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -48,4 +48,4 @@ CONFIG_RSA=y
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk"
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index 1dd7636..672a136 100644
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -53,5 +53,42 @@
 #define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
 #define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
 
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define DM814X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DM816X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+
+/*
+ * Macros to allow using the offset from the padconf physical address
+ * instead  of the offset from padconf base.
+ */
+#define OMAP_PADCONF_OFFSET(offset, base_offset)	((offset) - (base_offset))
+
+#define OMAP4_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+#define OMAP5_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+
+/*
+ * Define some commonly used pins configured by the boards.
+ * Note that some boards use alternative pins, so check
+ * the schematics before using these.
+ */
+#define OMAP3_UART1_RX		0x152
+#define OMAP3_UART2_RX		0x14a
+#define OMAP3_UART3_RX		0x16e
+#define OMAP4_UART2_RX		0xdc
+#define OMAP4_UART3_RX		0x104
+#define OMAP4_UART4_RX		0x11c
+
 #endif
 
-- 
cgit v0.10.2


From da9d9599acc81c424bcdddafaa888cd90b97df3d Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:24:29 +0530
Subject: ARM: dts: AM335x-BBG: Add initial support

Add initial DTS support for AM335x-BBG

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 587d220..e12f8d3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -92,7 +92,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
-	am335x-evmsk.dtb
+	am335x-evmsk.dtb \
+	am335x-bonegreen.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb
diff --git a/arch/arm/dts/am335x-bonegreen.dts b/arch/arm/dts/am335x-bonegreen.dts
new file mode 100644
index 0000000..9c59da9
--- /dev/null
+++ b/arch/arm/dts/am335x-bonegreen.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+/ {
+	model = "TI AM335x BeagleBone Green";
+	compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+};
+
+&ldo3_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+	vmmc-supply = <&vmmcsd_fixed>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&am33xx_pinmux {
+	uart2_pins: uart2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)	/* spi0_sclk.uart2_rxd */
+			AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)	/* spi0_d0.uart2_txd */
+		>;
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&rtc {
+	system-power-controller;
+};
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 89b12a5..579b4ef 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -644,6 +644,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 		return 0;
+	else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index a2794c2..6a25bf5 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -48,4 +48,4 @@ CONFIG_RSA=y
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen"
-- 
cgit v0.10.2


From 61bb825cd9edddc44c5a0c8897d400f213ce9e10 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@ti.com>
Date: Mon, 16 May 2016 11:32:49 +0530
Subject: configs: am335x_evm: Switch to env on FAT SD by default

Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility

Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 16935a1..dfd00de 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -249,11 +249,6 @@
 					"8m(NAND.kernel)," \
 					"-(NAND.file-system)"
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET		0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
-#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 /* NAND: SPL related configs */
 #ifdef CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_AM33XX_BCH
@@ -415,7 +410,6 @@
 					"128k(u-boot-env2),3464k(kernel)," \
 					"-(rootfs)"
 #elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SYS_MMC_ENV_DEV		1
@@ -423,6 +417,27 @@
 #define CONFIG_ENV_OFFSET		0x0
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#elif defined(CONFIG_NOR_BOOT)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
+#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT		"mtdparts=physmap-flash.0:" \
+					"512k(u-boot)," \
+					"128k(u-boot-env1)," \
+					"128k(u-boot-env2)," \
+					"4m(kernel),-(rootfs)"
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#elif !defined(CONFIG_ENV_IS_NOWHERE)
+/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE		"mmc"
+#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_FILE			"uboot.env"
 #endif
 
 /* SPI flash. */
@@ -458,19 +473,6 @@
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_SIZE		0x01000000
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
-#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
-#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT		"mtdparts=physmap-flash.0:" \
-					"512k(u-boot)," \
-					"128k(u-boot-env1)," \
-					"128k(u-boot-env2)," \
-					"4m(kernel),-(rootfs)"
-#endif
 #endif  /* NOR support */
 
 #endif	/* ! __CONFIG_AM335X_EVM_H */
-- 
cgit v0.10.2


From a9643324723ccd8c885b45b39d74b496f6e24c50 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:22 +0530
Subject: board: AM335x-ICEv2: Add epprom support

Similar to other TI's AM335x platforms, AM335x ICEv2 also has an
eeprom populated for its unique identification. Adding this info
so that AM335x ICEv2 specific initialization can be done.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 062c345..9776df7 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -47,6 +47,11 @@ static inline int board_is_evm_15_or_later(void)
 		strncmp("1.5", board_ti_get_rev(), 3) <= 0);
 }
 
+static inline int board_is_icev2(void)
+{
+	return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
 /*
  * We have three pin mux functions that must exist.  We must be able to enable
  * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
-- 
cgit v0.10.2


From 866b178bd13639e3960e78acf91ac80a6bd06689 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:23 +0530
Subject: board: AM335x-ICEv2: Add pinmux support

Add necessary pinmux support for AM335x ICEv2 board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index fdf827f..8afa5f9 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -135,6 +135,11 @@ static struct module_pin_mux gpio0_7_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux gpio0_18_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)},	/* GPIO0_18 */
+	{-1},
+};
+
 static struct module_pin_mux rgmii1_pin_mux[] = {
 	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
@@ -172,6 +177,20 @@ static struct module_pin_mux mii1_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},			/* MII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* MII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
 #ifdef CONFIG_NAND
 static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
@@ -237,6 +256,12 @@ static struct module_pin_mux bone_norcape_pin_mux[] = {
 };
 #endif
 
+static struct module_pin_mux uart3_icev2_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(mii1_rxd2), MODE(1) | PULLUDEN},		/* UART3_TXD */
+	{-1},
+};
+
 #if defined(CONFIG_NOR_BOOT)
 void enable_norboot_pin_mux(void)
 {
@@ -365,6 +390,12 @@ void enable_board_pin_mux(void)
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
+	} else if (board_is_icev2()) {
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(gpio0_18_pin_mux);
+		configure_module_pin_mux(uart3_icev2_pin_mux);
+		configure_module_pin_mux(rmii1_pin_mux);
+		configure_module_pin_mux(spi0_pin_mux);
 	} else {
 		puts("Unknown board, cannot configure pinmux.");
 		hang();
-- 
cgit v0.10.2


From d8ff4fdb103a7964a3351c0b26b256e8ba53319e Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:24 +0530
Subject: board: AM335x-ICEv2: Add DDR data

AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125),
capable of running at 400MHz. Adding this specific DDR configuration
details running at 400MHz.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 97bbfe2..43e122e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -54,6 +54,21 @@
 #define MT41J128MJT125_PHY_FIFO_WE		0x100
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz	0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz		0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz		0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz		0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz	0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz	0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz		0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz		0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz	0x0
+#define MT41J128MJT125_RD_DQS_400MHz		0x3A
+#define MT41J128MJT125_WR_DQS_400MHz		0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz	0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz	0x96
+
 /* Micron MT41K128M16JT-187E */
 #define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
 #define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 579b4ef..51c4358 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* GPIO that controls power to DDR on EVM-SK */
 #define GPIO_DDR_VTT_EN		7
+#define ICE_GPIO_DDR_VTT_EN	18
 
 #if defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
@@ -97,6 +98,13 @@ static const struct ddr_data ddr3_evm_data = {
 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 };
 
+static const struct ddr_data ddr3_icev2_data = {
+	.datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
+	.datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
+	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
+	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
+};
+
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
@@ -130,6 +138,17 @@ static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 };
 
+static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
+	.cmd0csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+	.cmd1csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+	.cmd2csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+};
+
 static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -162,6 +181,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 				PHY_EN_DYN_PWRDN,
 };
 
+static struct emif_regs ddr3_icev2_emif_reg_data = {
+	.sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
+	.ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
+	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
+	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
+	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
+	.zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
+				PHY_EN_DYN_PWRDN,
+};
+
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
@@ -339,7 +369,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
 
 	if (board_is_evm_sk())
 		return &dpll_ddr_evm_sk;
-	else if (board_is_bone_lt())
+	else if (board_is_bone_lt() || board_is_icev2())
 		return &dpll_ddr_bone_black;
 	else if (board_is_evm_15_or_later())
 		return &dpll_ddr_evm_sk;
@@ -418,6 +448,11 @@ void sdram_init(void)
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 
+	if (board_is_icev2()) {
+		gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
+		gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
+	}
+
 	if (board_is_evm_sk())
 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
@@ -429,6 +464,10 @@ void sdram_init(void)
 	else if (board_is_evm_15_or_later())
 		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+	else if (board_is_icev2())
+		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
+			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
+			   0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-- 
cgit v0.10.2


From 3164f3c68941a1665090bca903d56754ac36f89d Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:25 +0530
Subject: ARM: AM33xx: Add support for Clock Synthesizer

The CDCE913 and CDCEL913 devices are modular PLL-based, low cost,
high performance , programmable clock synthesizers. They generate
upto 3 output clocks from a single input frequency. Each output can
be programmed for any clock-frequency.

Adding support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index aae3f09..6fda482 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,3 +18,5 @@ obj-y	+= ddr.o
 obj-y	+= emif4.o
 obj-y	+= board.o
 obj-y	+= mux.o
+
+obj-$(CONFIG_CLOCK_SYNTHESIZER)	+= clk_synthesizer.o
diff --git a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
new file mode 100644
index 0000000..316e677
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
@@ -0,0 +1,104 @@
+/*
+ * clk-synthesizer.c
+ *
+ * Clock synthesizer apis
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <i2c.h>
+
+/**
+ * clk_synthesizer_reg_read - Read register from synthesizer.
+ * @addr:	addr within the i2c device
+ * buf:		Buffer to which value is to be read.
+ *
+ * For reading the register from this clock synthesizer, a command needs to
+ * be send along with enabling byte read more, and then read can happen.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_read(int addr, uint8_t *buf)
+{
+	int rc;
+
+	/* Enable Bye read */
+	addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
+
+	/* Send the command byte */
+	rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+	if (rc)
+		printf("Failed to send command to clock synthesizer\n");
+
+	/* Read the Data */
+	return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+}
+
+/**
+ * clk_synthesizer_reg_write - Write a value to register in synthesizer.
+ * @addr:	addr within the i2c device
+ * val:		Value to be written in the addr.
+ *
+ * Enable the byte read mode in the address and start the i2c transfer.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_write(int addr, uint8_t val)
+{
+	uint8_t cmd[2];
+	int rc = 0;
+
+	/* Enable byte write */
+	cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
+	cmd[1] = val;
+
+	rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
+	if (rc)
+		printf("Clock synthesizer reg write failed at addr = 0x%x\n",
+		       addr);
+	return rc;
+}
+
+/**
+ * setup_clock_syntherizer - Program the clock synthesizer to get the desired
+ *				frequency.
+ * @data: Data containing the desired output
+ *
+ * This is a PLL-based high performance synthesizer which gives 3 outputs
+ * as per the PLL_DIV and load capacitor programmed.
+ */
+int setup_clock_synthesizer(struct clk_synth *data)
+{
+	int rc;
+	uint8_t val;
+
+	rc =  i2c_probe(CLK_SYNTHESIZER_I2C_ADDR);
+	if (rc) {
+		printf("i2c probe failed at address 0x%x\n",
+		       CLK_SYNTHESIZER_I2C_ADDR);
+		return rc;
+	}
+
+	rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val);
+	if (val != data->id)
+		return rc;
+
+	/* Crystal Load capacitor selection */
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor);
+	if (rc)
+		return rc;
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux);
+	if (rc)
+		return rc;
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2);
+	if (rc)
+		return rc;
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3);
+	if (rc)
+		return rc;
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
new file mode 100644
index 0000000..a5af012
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -0,0 +1,43 @@
+/*
+ * clk-synthesizer.h
+ *
+ * Clock synthesizer header
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CLK_SYNTHESIZER_H
+#define __CLK_SYNTHESIZER_H
+
+#include <common.h>
+
+#define CLK_SYNTHESIZER_ID_REG		0x0
+#define CLK_SYNTHESIZER_XCSEL		0x05
+#define CLK_SYNTHESIZER_MUX_REG		0x14
+#define CLK_SYNTHESIZER_PDIV2_REG	0x16
+#define CLK_SYNTHESIZER_PDIV3_REG	0x17
+
+#define CLK_SYNTHESIZER_BYTE_MODE	0x80
+
+/**
+ * struct clk_synth: This structure holds data neeed for configuring
+ *		     for clock synthesizer.
+ * @id: The id of synthesizer
+ * @capacitor: value of the capacitor attached
+ * @mux: mux settings.
+ * @pdiv2: Div to be applied to second output
+ * @pdiv3: Div to be applied to third output
+ */
+struct clk_synth {
+	u32 id;
+	u32 capacitor;
+	u32 mux;
+	u32 pdiv2;
+	u32 pdiv3;
+};
+
+int setup_clock_synthesizer(struct clk_synth *data);
+
+#endif
-- 
cgit v0.10.2


From 97f3a178b2a3d5a7767cb6cb15ba9c40ba804ebb Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:26 +0530
Subject: board: AM335x-ICEv2: Add cpsw support

In order to enable cpsw on AM335x ICEv2 board, the following needs to be done:

1)There are few on board jumper settings which gives a choice between
cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting
this, there are few GPIOs which control these muxes that needs to be held high.

2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected
via I2C. This needs to properly programmed and locked for PHY operation.
And PHY needs to be reset before before being used, which is also held by
a GPIO.

3) RMII mode needs to be selected.

[1] http://www.ti.com/lit/zip/tidr336
[2] http://www.ti.com/lit/ds/symlink/cdce913.pdf

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 51c4358..8f47692 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -16,6 +16,7 @@
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
@@ -37,8 +38,13 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN		7
-#define ICE_GPIO_DDR_VTT_EN	18
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
 
 #if defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
@@ -474,6 +480,49 @@ void sdram_init(void)
 }
 #endif
 
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void request_and_set_gpio(int gpio, char *name)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, 1);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N);
+
+/**
+ * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
+ * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
+ * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
+ * give 50MHz output for Eth0 and 1.
+ */
+static struct clk_synth cdce913_data = {
+	.id = 0x81,
+	.capacitor = 0x90,
+	.mux = 0x6d,
+	.pdiv2 = 0x2,
+	.pdiv3 = 0x2,
+};
+#endif
+
 /*
  * Basic board specific setup.  Pinmux has been handled already.
  */
@@ -487,6 +536,23 @@ int board_init(void)
 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
 #endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
+	int rv;
+
+	if (board_is_icev2()) {
+		REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
+		REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+		REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+		REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+
+		rv = setup_clock_synthesizer(&cdce913_data);
+		if (rv) {
+			printf("Clock synthesizer setup failed %d\n", rv);
+			return rv;
+		}
+	}
+#endif
+
 	return 0;
 }
 
@@ -554,6 +620,12 @@ static struct cpsw_platform_data cpsw_data = {
 };
 #endif
 
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+
 /*
  * This function will:
  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
@@ -565,11 +637,6 @@ static struct cpsw_platform_data cpsw_data = {
  * Build in only these cases to avoid warnings about unused variables
  * when we build an SPL that has neither option but full U-Boot will.
  */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
-		&& defined(CONFIG_SPL_BUILD)) || \
-	((defined(CONFIG_DRIVER_TI_CPSW) || \
-	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
-	 !defined(CONFIG_SPL_BUILD))
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
@@ -620,6 +687,12 @@ int board_eth_init(bd_t *bis)
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;
+	} else if (board_is_icev2()) {
+		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[0].phy_addr = 1;
+		cpsw_slaves[1].phy_addr = 3;
 	} else {
 		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index dfd00de..7c7f197 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -475,4 +475,9 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #endif  /* NOR support */
 
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
 #endif	/* ! __CONFIG_AM335X_EVM_H */
-- 
cgit v0.10.2


From 426af3848fdd383e0cb141142b3f0d9a7edb334e Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:27 +0530
Subject: config: env: Set AM335x-ICEv2 board specific env

Populate the right dtb file and console for AM335x-ICEv2 board.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 7c7f197..ba4c215 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -91,6 +91,7 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt; " \
+	"run init_console; " \
 	"run envboot; " \
 	"run distro_bootcmd"
 
@@ -169,8 +170,16 @@
 			"setenv fdtfile am335x-evm.dtb; fi; " \
 		"if test $board_name = A335X_SK; then " \
 			"setenv fdtfile am335x-evmsk.dtb; fi; " \
+		"if test $board_name = A335_ICE; then " \
+			"setenv fdtfile am335x-icev2.dtb; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"init_console=" \
+		"if test $board_name = A335_ICE; then "\
+			"setenv console ttyO3,115200n8;" \
+		"else " \
+			"setenv console ttyO0,115200n8;" \
+		"fi;\0" \
 	NANDARGS \
 	NETARGS \
 	DFUARGS \
-- 
cgit v0.10.2


From 73ec6960591c57838694ab4056b33438cd2b42c9 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:28 +0530
Subject: ARM: dts: AM335x-ICEv2: Add minimal dts support

Add minimal dts support for AM335x-ICEv2 board

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e12f8d3..92c7545 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,7 +93,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
 	am335x-evmsk.dtb \
-	am335x-bonegreen.dtb
+	am335x-bonegreen.dtb \
+	am335x-icev2.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
new file mode 100644
index 0000000..debc6f6
--- /dev/null
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -0,0 +1,430 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x ICE V2 board
+ * http://www.ti.com/tool/tmdsice3359
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+	model = "TI AM3359 ICE-V2";
+	compatible = "ti,am3359-icev2", "ti,am33xx";
+
+	chosen {
+		stdout-path = &uart3;
+		tick-timer = &timer2;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	vtt_fixed: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	leds@0 {
+		compatible = "gpio-leds";
+
+		led@0 {
+			label = "out0";
+			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@1 {
+			label = "out1";
+			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "out2";
+			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "out3";
+			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "out4";
+			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "out5";
+			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@6 {
+			label = "out6";
+			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@7 {
+			label = "out7";
+			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	/* Tricolor status LEDs */
+	leds@1 {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds>;
+
+		led@0 {
+			label = "status0:red:cpu0";
+			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu0";
+		};
+
+		led@1 {
+			label = "status0:green:usr";
+			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "status0:yellow:usr";
+			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "status1:red:mmc0";
+			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+
+		led@4 {
+			label = "status1:green:usr";
+			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "status1:yellow:usr";
+			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&am33xx_pinmux {
+	user_leds: user_leds {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+			AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+			AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+		>;
+	};
+
+	mmc0_pins_default: mmc0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
+			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
+			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
+			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
+			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
+		>;
+	};
+
+	i2c0_pins_default: i2c0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+		>;
+	};
+
+	spi0_pins_default: spi0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
+			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
+			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+		>;
+	};
+
+	uart3_pins_default: uart3_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1, RMII mode */
+			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_crs.rmii1_crs_dv */
+			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))	/* rmii1_refclk.rmii1_refclk */
+			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txen.rmii1_txen */
+			/* Slave 2, RMII mode */
+			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wait0.rmii2_crs_dv */
+			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_col.rmii2_refclk */
+			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a11.rmii2_rxd0 */
+			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a10.rmii2_rxd1 */
+			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wpn.rmii2_rxerr */
+			AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a5.rmii2_txd0 */
+			AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a4.rmii2_txd1 */
+			AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a0.rmii2_txen */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+
+			/* Slave 2 reset value */
+			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+		>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_default>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: power-controller@2d {
+		reg = <0x2d>;
+	};
+
+	tpic2810: gpio@60 {
+		compatible = "ti,tpic2810";
+		reg = <0x60>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1326000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmc_reg>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+};
+
+&gpio0 {
+	/* Do not idle the GPIO used for holding the VTT regulator */
+	ti,no-reset-on-init;
+	ti,no-idle-on-init;
+
+	p7 {
+		gpio-hog;
+		gpios = <7 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "FET_SWITCH_CTRL";
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_default>;
+	status = "okay";
+};
+
+&gpio3 {
+	p4 {
+		gpio-hog;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "PR1_MII_CTRL";
+	};
+
+	p10 {
+		gpio-hog;
+		gpios = <10 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "MUX_MII_CTRL";
+	};
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <3>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <2>;
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+	dual_emac;
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
+};
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 8f47692..ff52314 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -758,6 +758,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 		return 0;
+	else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 6a25bf5..696024c 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -48,4 +48,4 @@ CONFIG_RSA=y
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
-- 
cgit v0.10.2


From 3d16389c909657a5fd1017e771ce5acf8aed6189 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 16 May 2016 11:47:29 +0530
Subject: board: am335x: Allow to choose serial device dynamically

Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ff52314..56f4984 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <errno.h>
 #include <spl.h>
+#include <serial.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
@@ -59,6 +60,16 @@ static inline int __maybe_unused read_eeprom(void)
 	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
 }
 
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+	if (board_is_icev2())
+		return &eserial4_device;
+	else
+		return &eserial1_device;
+}
+#endif
+
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
diff --git a/include/serial.h b/include/serial.h
index e490f9a..47332c5 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -40,6 +40,10 @@ extern struct serial_device serial1_device;
 
 extern struct serial_device eserial1_device;
 extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+extern struct serial_device eserial5_device;
+extern struct serial_device eserial6_device;
 
 extern void serial_register(struct serial_device *);
 extern void serial_initialize(void);
-- 
cgit v0.10.2


From 25828588412c1f951d72e1eda9e4320d422b7be5 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 17 May 2016 16:38:06 +0900
Subject: arm64: optimize __asm_{flush, invalidate}_dcache_all

__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.

We do not have to waste x16 register here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index a9f4fec..1c71a2f 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -104,19 +104,13 @@ finished:
 ENDPROC(__asm_dcache_all)
 
 ENTRY(__asm_flush_dcache_all)
-	mov	x16, lr
 	mov	x0, #0
-	bl	__asm_dcache_all
-	mov	lr, x16
-	ret
+	b	__asm_dcache_all
 ENDPROC(__asm_flush_dcache_all)
 
 ENTRY(__asm_invalidate_dcache_all)
-	mov	x16, lr
 	mov	x0, #0x1
-	bl	__asm_dcache_all
-	mov	lr, x16
-	ret
+	b	__asm_dcache_all
 ENDPROC(__asm_invalidate_dcache_all)
 
 /*
-- 
cgit v0.10.2


From 1a021230d37d4f87ec0ca9f4103b582e415f1b76 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 17 May 2016 16:38:07 +0900
Subject: arm64: fix comment "flush & invalidate"

We should say "clean & invalidate", or simply "flush".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 1c71a2f..6aaecf3 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -19,7 +19,7 @@
  * clean and invalidate one level cache.
  *
  * x0: cache level
- * x1: 0 flush & invalidate, 1 invalidate only
+ * x1: 0 clean & invalidate, 1 invalidate only
  * x2~x9: clobbered
  */
 ENTRY(__asm_flush_dcache_level)
@@ -62,7 +62,7 @@ ENDPROC(__asm_flush_dcache_level)
 /*
  * void __asm_flush_dcache_all(int invalidate_only)
  *
- * x0: 0 flush & invalidate, 1 invalidate only
+ * x0: 0 clean & invalidate, 1 invalidate only
  *
  * clean and invalidate all data cache by SET/WAY.
  */
-- 
cgit v0.10.2


From ba9eb6c7eb3490f72f07bc712f7196fb4e0fe80c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 17 May 2016 16:38:08 +0900
Subject: arm64: rename __asm_flush_dcache_level to __asm_dcache_level

Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation.  So, it is better to not include "flush" in
this routine name.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 6aaecf3..46f25e6 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -14,15 +14,15 @@
 #include <linux/linkage.h>
 
 /*
- * void __asm_flush_dcache_level(level)
+ * void __asm_dcache_level(level)
  *
- * clean and invalidate one level cache.
+ * flush or invalidate one level cache.
  *
  * x0: cache level
  * x1: 0 clean & invalidate, 1 invalidate only
  * x2~x9: clobbered
  */
-ENTRY(__asm_flush_dcache_level)
+ENTRY(__asm_dcache_level)
 	lsl	x12, x0, #1
 	msr	csselr_el1, x12		/* select cache level */
 	isb				/* sync change of cssidr_el1 */
@@ -57,14 +57,14 @@ loop_way:
 	b.ge	loop_set
 
 	ret
-ENDPROC(__asm_flush_dcache_level)
+ENDPROC(__asm_dcache_level)
 
 /*
  * void __asm_flush_dcache_all(int invalidate_only)
  *
  * x0: 0 clean & invalidate, 1 invalidate only
  *
- * clean and invalidate all data cache by SET/WAY.
+ * flush or invalidate all data cache by SET/WAY.
  */
 ENTRY(__asm_dcache_all)
 	mov	x1, x0
@@ -87,7 +87,7 @@ loop_level:
 	and	x12, x12, #7		/* x12 <- cache type */
 	cmp	x12, #2
 	b.lt	skip			/* skip if no cache or icache */
-	bl	__asm_flush_dcache_level	/* x1 = 0 flush, 1 invalidate */
+	bl	__asm_dcache_level	/* x1 = 0 flush, 1 invalidate */
 skip:
 	add	x0, x0, #1		/* increment cache level */
 	cmp	x11, x0
-- 
cgit v0.10.2


From 56adbb38727320375b2f695bd04600d766d8a1b3 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Sat, 21 May 2016 05:06:31 -0400
Subject: image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro.

In order for CONFIG_IS_ENABLED(FOO) to work we need to move the changes
that CONFIG_FIT_DISABLE_SHA256 makes to be prior to the evaluation by
CONFIG_IS_ENABLED(foo)

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Move CONFIG_FIT_DISABLE_SHA256 parts to fix build breakage]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/include/image.h b/include/image.h
index a8f6bd1..80a4454 100644
--- a/include/image.h
+++ b/include/image.h
@@ -52,19 +52,15 @@ struct lmb;
 #include <hash.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+# ifdef CONFIG_FIT_DISABLE_SHA256
+#  undef CONFIG_SHA256
+#  undef IMAGE_ENABLE_SHA256
+# endif
 # ifdef CONFIG_SPL_BUILD
-#  ifdef CONFIG_SPL_CRC32_SUPPORT
-#   define IMAGE_ENABLE_CRC32	1
-#  endif
-#  ifdef CONFIG_SPL_MD5_SUPPORT
-#   define IMAGE_ENABLE_MD5	1
-#  endif
-#  ifdef CONFIG_SPL_SHA1_SUPPORT
-#   define IMAGE_ENABLE_SHA1	1
-#  endif
-#  ifdef CONFIG_SPL_SHA256_SUPPORT
-#   define IMAGE_ENABLE_SHA256	1
-#  endif
+#  define IMAGE_ENABLE_CRC32	CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT)
+#  define IMAGE_ENABLE_MD5	CONFIG_IS_ENABLED(SPL_MD5_SUPPORT)
+#  define IMAGE_ENABLE_SHA1	CONFIG_IS_ENABLED(SPL_SHA1_SUPPORT)
+#  define IMAGE_ENABLE_SHA256	CONFIG_IS_ENABLED(SPL_SHA256_SUPPORT)
 # else
 #  define CONFIG_CRC32		/* FIT images need CRC32 support */
 #  define CONFIG_MD5		/* and MD5 */
@@ -75,53 +71,12 @@ struct lmb;
 #  define IMAGE_ENABLE_SHA1	1
 #  define IMAGE_ENABLE_SHA256	1
 # endif
-
-#ifdef CONFIG_FIT_DISABLE_SHA256
-#undef CONFIG_SHA256
-#undef IMAGE_ENABLE_SHA256
-#endif
-
-#ifndef IMAGE_ENABLE_CRC32
-#define IMAGE_ENABLE_CRC32	0
-#endif
-
-#ifndef IMAGE_ENABLE_MD5
-#define IMAGE_ENABLE_MD5	0
-#endif
-
-#ifndef IMAGE_ENABLE_SHA1
-#define IMAGE_ENABLE_SHA1	0
-#endif
-
-#ifndef IMAGE_ENABLE_SHA256
-#define IMAGE_ENABLE_SHA256	0
-#endif
-
 #endif /* IMAGE_ENABLE_FIT */
 
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
-# define IMAGE_ENABLE_RAMDISK_HIGH	1
-#else
-# define IMAGE_ENABLE_RAMDISK_HIGH	0
-#endif
-
-#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
-# define IMAGE_BOOT_GET_CMDLINE		1
-#else
-# define IMAGE_BOOT_GET_CMDLINE		0
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-# define IMAGE_OF_BOARD_SETUP		1
-#else
-# define IMAGE_OF_BOARD_SETUP		0
-#endif
-
-#ifdef CONFIG_OF_SYSTEM_SETUP
-# define IMAGE_OF_SYSTEM_SETUP	1
-#else
-# define IMAGE_OF_SYSTEM_SETUP	0
-#endif
+#define IMAGE_ENABLE_RAMDISK_HIGH	CONFIG_IS_ENABLED(SYS_BOOT_RAMDISK_HIGH)
+#define IMAGE_BOOT_GET_CMDLINE		CONFIG_IS_ENABLED(SYS_BOOT_GET_CMDLINE)
+#define IMAGE_OF_BOARD_SETUP		CONFIG_IS_ENABLED(OF_BOARD_SETUP)
+#define IMAGE_OF_SYSTEM_SETUP		CONFIG_IS_ENABLED(OF_SYSTEM_SETUP)
 
 /*
  * Operating System Codes
-- 
cgit v0.10.2


From d339df522beb6d9268231069fd9e1d3e73af49ed Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sun, 22 May 2016 15:16:47 +0900
Subject: tools/genboardscfg.py: remove bogus import subprocess

Since f6c8f38ec601 ("tools/genboardscfg.py: improve performance more
with Kconfiglib"), this tool does not use the subprocess module.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
index 23c956b..c2efad5 100755
--- a/tools/genboardscfg.py
+++ b/tools/genboardscfg.py
@@ -21,7 +21,6 @@ import glob
 import multiprocessing
 import optparse
 import os
-import subprocess
 import sys
 import tempfile
 import time
-- 
cgit v0.10.2


From 87c2f76f3fae11bf559996505e23b37d03f4c5dc Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Sun, 22 May 2016 05:46:05 -0400
Subject: tools: Add entry for generated tools/bin2header to tools/.gitignore

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/tools/.gitignore b/tools/.gitignore
index ff07680..cb1e722 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -1,4 +1,5 @@
 /atmel_pmecc_params
+/bin2header
 /bmp_logo
 /envcrc
 /fdtgrep
-- 
cgit v0.10.2


From 9b77b19178446393fce2e74554815c17454f8da8 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 23 May 2016 13:31:19 +0530
Subject: ARM: OMAP4+: Fix DPLL programming sequence

All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index ef2ac98..2de9935 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 			/* Dpll locked with ideal values for nominal opps. */
 			debug("\n %s Dpll already locked with ideal"
 						"nominal opp values", dpll);
+
+			bypass_dpll(base);
 			goto setup_post_dividers;
 		}
 	}
@@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 
 	writel(temp, &dpll_regs->cm_clksel_dpll);
 
+setup_post_dividers:
+	setup_post_dividers(base, params);
+
 	/* Lock */
 	if (lock)
 		do_lock_dpll(base);
 
-setup_post_dividers:
-	setup_post_dividers(base, params);
-
 	/* Wait till the DPLL locks */
 	if (lock)
 		wait_for_lock(base);
-- 
cgit v0.10.2


From 0d71511a2ae03aeb3794a0461bd8c14752438c7f Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:06 -0700
Subject: x86: acpi: Create a common irqlinks ASL file

Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
new file mode 100644
index 0000000..84c1e53
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -0,0 +1,486 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
+
+Device (LNKA)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 1)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTA)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTA */
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTA, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 2)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTB)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTB */
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTB, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 3)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTC)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTC */
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTC, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 4)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTD)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTD */
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTD, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 5)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTE)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTE */
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTE, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 6)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTF)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTF */
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTF, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 7)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTG)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTG */
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTG, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 8)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTH)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTH */
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTH, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
deleted file mode 100644
index 0affa23..0000000
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
- *
- * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-Scope (\)
-{
-	/* Intel Legacy Block */
-	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
-	Field(ILBS, AnyAcc, NoLock, Preserve) {
-		Offset (0x8),
-		PRTA, 8,
-		PRTB, 8,
-		PRTC, 8,
-		PRTD, 8,
-		PRTE, 8,
-		PRTF, 8,
-		PRTG, 8,
-		PRTH, 8,
-		Offset (0x88),
-		    , 3,
-		UI3E, 1,
-		UI4E, 1
-	}
-}
-
-Device (LNKA)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 1)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTA)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLA, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLA, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTA */
-		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
-
-		Return (RTLA)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTA)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTA, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKB)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 2)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTB)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLB, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLB, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTB */
-		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
-
-		Return (RTLB)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTB)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTB, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKC)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 3)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTC)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLC, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLC, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTC */
-		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
-
-		Return (RTLC)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTC)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTC, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKD)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 4)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTD)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLD, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLD, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTD */
-		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
-
-		Return (RTLD)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTD)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTD, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKE)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 5)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTE)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLE, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLE, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTE */
-		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
-
-		Return (RTLE)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTE)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTE, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKF)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 6)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTF)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLF, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLF, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTF */
-		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
-
-		Return (RTLF)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTF)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTF, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKG)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 7)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTG)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLG, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLG, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTG */
-		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
-
-		Return (RTLG)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTG)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTG, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
-
-Device (LNKH)
-{
-	Name(_HID, EISAID("PNP0C0F"))
-	Name(_UID, 8)
-
-	/* Disable method */
-	Method(_DIS, 0, Serialized)
-	{
-		Store(0x80, PRTH)
-	}
-
-	/* Possible Resource Settings for this Link */
-	Name(_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
-	})
-
-	/* Current Resource Settings for this link */
-	Method(_CRS, 0, Serialized)
-	{
-		Name(RTLH, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLH, 1, IRQ0)
-
-		/* Clear the WordField */
-		Store(Zero, IRQ0)
-
-		/* Set the bit from PRTH */
-		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
-
-		Return (RTLH)
-	}
-
-	/* Set Resource Setting for this IRQ link */
-	Method(_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		/* Which bit is set? */
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTH)
-	}
-
-	/* Status */
-	Method(_STA, 0, Serialized)
-	{
-		If (And(PRTH, 0x80)) {
-			Return (STA_DISABLED)
-		} Else {
-			Return (STA_INVISIBLE)
-		}
-	}
-}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 385671c..22f0d68 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -10,6 +10,27 @@
 
 /* Intel LPC Bus Device - 0:1f.0 */
 
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
+	}
+}
+
 Device (LPCB)
 {
 	Name(_ADR, 0x001f0000)
@@ -23,7 +44,7 @@ Device (LPCB)
 		Offset(0x84)
 	}
 
-	#include "irqlinks.asl"
+	#include <asm/acpi/irqlinks.asl>
 
 	/* Firmware Hub */
 	Device (FWH)
-- 
cgit v0.10.2


From 3498cc9775e255875ae30ecfb4e29ea1220923a3 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:07 -0700
Subject: x86: acpi: Make irqroute.asl common

The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h
new file mode 100644
index 0000000..f0b3a6b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+	RP_METHOD(prefix_, dev_, 0) \
+	RP_METHOD(prefix_, dev_, 1) \
+	RP_METHOD(prefix_, dev_, 2) \
+	RP_METHOD(prefix_, dev_, 3) \
+	RP_METHOD(prefix_, dev_, 4) \
+	RP_METHOD(prefix_, dev_, 5) \
+	RP_METHOD(prefix_, dev_, 6) \
+	RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_IRQ(dev_, 0, a_), \
+	ACPI_DEV_IRQ(dev_, 1, b_), \
+	ACPI_DEV_IRQ(dev_, 2, c_), \
+	ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+	Name(_ADR, dev_ ## 000 ## func_) \
+	Name(_PRW, Package() { 0, 0 }) \
+	Method(_PRT) { \
+		If (PICM) { \
+			Return (prefix_ ## func_ ## A) \
+		} Else { \
+			Return (prefix_ ## func_ ## P) \
+		} \
+	} \
+}
+
+/* SoC specific PIRQ route configuration */
+#include <asm/arch/acpi/irqroute.h>
diff --git a/arch/x86/include/asm/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl
new file mode 100644
index 0000000..64d3820
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice */
+	Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
deleted file mode 100644
index 2c3585a..0000000
--- a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronics Engineering, LLC.
- * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
- *
- * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * This file intentionally gets included multiple times, to set pic and apic
- * modes, so should not have guard statements added.
- */
-
-/*
- * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
- * routing for the platform being compiled.
- *
- * This method uses #defines in irqroute.h along with the macros contained
- * in this file to generate an IRQ routing for each PCI device in the system.
- */
-
-#undef PCI_DEV_PIRQ_ROUTES
-#undef PCI_DEV_PIRQ_ROUTE
-#undef ACPI_DEV_IRQ
-#undef PCIE_BRIDGE_DEV
-#undef RP_IRQ_ROUTES
-#undef ROOTPORT_METHODS
-#undef ROOTPORT_IRQ_ROUTES
-#undef RP_METHOD
-
-#if defined(PIC_MODE)
-
-#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
-	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
-
-#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
-Name(prefix_ ## func_ ## P, Package() \
-{ \
-	ACPI_DEV_IRQ(0x0000, 0, a_), \
-	ACPI_DEV_IRQ(0x0000, 1, b_), \
-	ACPI_DEV_IRQ(0x0000, 2, c_), \
-	ACPI_DEV_IRQ(0x0000, 3, d_), \
-})
-
-/* define as blank so ROOTPORT_METHODS only gets inserted once */
-#define ROOTPORT_METHODS(prefix_, dev_)
-
-#else /* defined(PIC_MODE) */
-
-#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
-	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
-
-#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
-Name(prefix_ ## func_ ## A, Package() \
-{ \
-	ACPI_DEV_IRQ(0x0000, 0, a_), \
-	ACPI_DEV_IRQ(0x0000, 1, b_), \
-	ACPI_DEV_IRQ(0x0000, 2, c_), \
-	ACPI_DEV_IRQ(0x0000, 3, d_), \
-})
-
-#define ROOTPORT_METHODS(prefix_, dev_) \
-	RP_METHOD(prefix_, dev_, 0) \
-	RP_METHOD(prefix_, dev_, 1) \
-	RP_METHOD(prefix_, dev_, 2) \
-	RP_METHOD(prefix_, dev_, 3) \
-	RP_METHOD(prefix_, dev_, 4) \
-	RP_METHOD(prefix_, dev_, 5) \
-	RP_METHOD(prefix_, dev_, 6) \
-	RP_METHOD(prefix_, dev_, 7)
-
-#endif /* defined(PIC_MODE) */
-
-#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
-	ACPI_DEV_IRQ(dev_, 0, a_), \
-	ACPI_DEV_IRQ(dev_, 1, b_), \
-	ACPI_DEV_IRQ(dev_, 2, c_), \
-	ACPI_DEV_IRQ(dev_, 3, d_)
-
-#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
-	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
-	ROOTPORT_METHODS(prefix_, dev_)
-
-#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
-	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
-	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
-	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
-	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
-	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
-	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
-	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
-	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
-
-#define RP_METHOD(prefix_, dev_, func_)\
-Device (prefix_ ## 0 ## func_) \
-{ \
-	Name(_ADR, dev_ ## 000 ## func_) \
-	Name(_PRW, Package() { 0, 0 }) \
-	Method(_PRT) { \
-		If (PICM) { \
-			Return (prefix_ ## func_ ## A) \
-		} Else { \
-			Return (prefix_ ## func_ ## P) \
-		} \
-	} \
-}
-
-/* SoC specific PIRQ route configuration */
-#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
deleted file mode 100644
index 64d3820..0000000
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
- *
- * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-Name(\PICM, 0)
-
-/*
- * The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local APIC/IOAPIC configuration.
- */
-Method(\_PIC, 1)
-{
-	/* Remember the OS' IRQ routing choice */
-	Store(Arg0, PICM)
-}
-
-/* PCI interrupt routing */
-Method(_PRT) {
-	If (PICM) {
-		Return (Package() {
-			#undef PIC_MODE
-			#include "irq_helper.h"
-			PCI_DEV_PIRQ_ROUTES
-		})
-	} Else {
-		Return (Package() {
-			#define PIC_MODE
-			#include "irq_helper.h"
-			PCI_DEV_PIRQ_ROUTES
-		})
-	}
-
-}
-
-/* PCIe downstream ports interrupt routing */
-PCIE_BRIDGE_IRQ_ROUTES
-#undef PIC_MODE
-#include "irq_helper.h"
-PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
index 34d3951..e89ff26 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -207,5 +207,5 @@ Device (PCI0)
 	#include "xhci.asl"
 
 	/* IRQ routing for each PCI device */
-	#include "irqroute.asl"
+	#include <asm/acpi/irqroute.asl>
 }
-- 
cgit v0.10.2


From 6683584c08cd58ed88a6b60d613bca9086bf8fab Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:08 -0700
Subject: acpi: Pass -D__ASSEMBLY__ when compiling ASL files

ASL files may include various U-Boot header files, but IASL compiler
does not understand any C language embedded in these header files.
To reuse those header files for ASL compiling, use __ASSEMBLY__ in
the header files to exclude everything that is not liked by IASL.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 97a09a2..e720562 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -325,7 +325,7 @@ $(obj)/%.S: $(src)/%.ttf
 # ---------------------------------------------------------------------------
 quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
-	$(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+	$(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
 	iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-- 
cgit v0.10.2


From ec3791322159accacb06213a660a63b9ffb84f31 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:09 -0700
Subject: x86: quark: Prepare device.h for inclusion by ASL

There is a device.h for quark on-chip devices, mainly for definitions
of internal PCI device numbers, but it's not ready to be included by
ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
index 7882f33..4760aa2 100644
--- a/arch/x86/include/asm/arch-quark/device.h
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -7,12 +7,17 @@
 #ifndef _QUARK_DEVICE_H_
 #define _QUARK_DEVICE_H_
 
-#include <pci.h>
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
 
-#define QUARK_HOST_BRIDGE_DEV	0
+#define QUARK_HOST_BRIDGE_DEV	0x00
 #define QUARK_HOST_BRIDGE_FUNC	0
 
-#define QUARK_DEV_20		20
+#define QUARK_DEV_20		0x14
 #define QUARK_MMC_SDIO_FUNC	0
 #define QUARK_UART0_FUNC	1
 #define QUARK_USB_DEVICE_FUNC	2
@@ -22,18 +27,21 @@
 #define QUARK_EMAC0_FUNC	6
 #define QUARK_EMAC1_FUNC	7
 
-#define QUARK_DEV_21		21
+#define QUARK_DEV_21		0x15
 #define QUARK_SPI0_FUNC		0
 #define QUARK_SPI1_FUNC		1
 #define QUARK_I2C_GPIO_FUNC	2
 
-#define QUARK_DEV_23		23
+#define QUARK_DEV_23		0x17
 #define QUARK_PCIE0_FUNC	0
 #define QUARK_PCIE1_FUNC	1
 
-#define QUARK_LGC_BRIDGE_DEV	31
+#define QUARK_LGC_BRIDGE_DEV	0x1f
 #define QUARK_LGC_BRIDGE_FUNC	0
 
+#ifndef __ASSEMBLY__
+#include <pci.h>
+
 #define QUARK_HOST_BRIDGE	\
 	PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
 #define QUARK_MMC_SDIO		\
@@ -64,5 +72,6 @@
 	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
 #define QUARK_LEGACY_BRIDGE	\
 	PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
+#endif /* __ASSEMBLY__ */
 
 #endif /* _QUARK_DEVICE_H_ */
-- 
cgit v0.10.2


From 48cf8b834603253440496a2356d192f8e4138d14 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:10 -0700
Subject: x86: quark: Add platform ASL files

This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
new file mode 100644
index 0000000..5ba31da
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
new file mode 100644
index 0000000..c3b0b1d
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(PRTX, PCI_Config, 0x60, 8)
+	Field(PRTX, AnyAcc, NoLock, Preserve) {
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+
+	#include <asm/acpi/irqlinks.asl>
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			IRQNoFlags() { 8 }
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
new file mode 100644
index 0000000..bd72842
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
new file mode 100644
index 0000000..63c82fa
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
new file mode 100644
index 0000000..a89cfaf
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
+			IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
+			IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* IRQ routing for each PCI device */
+	#include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644
index 0000000..fd1ef98
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/iomap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS		CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE			ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE			0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS		CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE		0x10
+
+#define ACPI_PBLK_BASE_ADDRESS		CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE		0x10
+
+#define SPI_DMA_BASE_ADDRESS		CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE		0x10
+
+#define GPIO_BASE_ADDRESS		CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE			0x80
+
+#define ACPI_GPE0_BASE_ADDRESS		CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE		0x40
+
+#define WDT_BASE_ADDRESS		CONFIG_WDT_BASE
+#define WDT_BASE_SIZE			0x40
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644
index 0000000..21e6830
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/irq.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUARK_IRQ_H_
+#define _QUARK_IRQ_H_
+
+#define PIRQA_APIC_IRQ	16
+#define PIRQB_APIC_IRQ	17
+#define PIRQC_APIC_IRQ	18
+#define PIRQD_APIC_IRQ	19
+#define PIRQE_APIC_IRQ	20
+#define PIRQF_APIC_IRQ	21
+#define PIRQG_APIC_IRQ	22
+#define PIRQH_APIC_IRQ	23
+
+#endif /* _QUARK_IRQ_H_ */
-- 
cgit v0.10.2


From 7ee371063f3cf779740bb35e0c31dc04fc132e9b Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:11 -0700
Subject: x86: quark: Generate ACPI FADT/MADT tables

Generate quark platform-specific FADT/MADT tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 6d670d7..93ce412 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += car.o dram.o irq.o msg_port.o quark.o
 obj-y += mrc.o mrc_util.o hte.o smc.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
new file mode 100644
index 0000000..8f69829
--- /dev/null
+++ b/arch/x86/cpu/quark/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_PM1_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0x00;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
-- 
cgit v0.10.2


From e6ddb6b0135949e67bf5face7bdff522e493e1e2 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:12 -0700
Subject: x86: galileo: Enable ACPI table generation

Enable ACPI table generation by creating a DSDT table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/intel/galileo/.gitignore b/board/intel/galileo/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/intel/galileo/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile
index 8356df1..bbe2f8b 100644
--- a/board/intel/galileo/Makefile
+++ b/board/intel/galileo/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= galileo.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/galileo/acpi/mainboard.asl b/board/intel/galileo/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/intel/galileo/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/galileo/dsdt.asl b/board/intel/galileo/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/intel/galileo/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index f8d3c3b..080c2ed 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/doc/README.x86 b/doc/README.x86
index 4d50feb..a548b54 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -1028,12 +1028,15 @@ Features that are optional:
    those legacy stuff into U-Boot. ACPI spec allows a system that does not
    support SMI (a legacy-free system).
 
-So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+ACPI was initially enabled on BayTrail based boards. Testing was done by booting
 a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
 Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
 devices seem to work correctly and the board can respond a reboot/shutdown
 command from the OS.
 
+For other platform boards, ACPI support status can be checked by examining their
+board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
+
 TODO List
 ---------
 - Audio
-- 
cgit v0.10.2


From d3d664725b4a05cf32d905ff806b44bb01fa61c0 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 25 May 2016 19:19:13 -0700
Subject: x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 1d54f7d..5ee4868 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -155,7 +155,7 @@ u32 acpi_fill_madt(u32 current)
 	current += acpi_create_madt_lapics(current);
 
 	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
-			2, IO_APIC_ADDR, 0);
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irq_overrides(current);
 
-- 
cgit v0.10.2


From 452b3813f99538ebd54407e911733c4b26efd1a4 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Thu, 26 May 2016 09:48:24 +0100
Subject: clearfog: add HUSH parser

In the big move of CONFIG_HUSH_PARSER to config files the clearfog
somehow missed out.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 0fde640..75ea200 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
+CONFIG_HUSH_PARSER=y
 CONFIG_SPL=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From f7c32e8ece7fefd950382a7522aff9939a218b91 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 27 Apr 2016 09:10:42 +0200
Subject: arm: spear: x600: Add support for Micrel KSZ9031 PHY

As the old ethernet PHY is not available any more, the x600 board has
been redesigned with the Micrel KSZ9031 PHY. This patch adds support
to autodetect the PHY and configure the Micrel PHY correctly.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
index b8edfcd..f8e9fdd 100644
--- a/board/spear/x600/x600.c
+++ b/board/spear/x600/x600.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <micrel.h>
 #include <nand.h>
 #include <netdev.h>
 #include <phy.h>
@@ -69,27 +70,64 @@ void board_nand_init(void)
 
 int board_phy_config(struct phy_device *phydev)
 {
-	/* Extended PHY control 1, select GMII */
-	phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
-
-	/* Software reset necessary after GMII mode selction */
-	phy_reset(phydev);
-
-	/* Enable extended page register access */
-	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
-
-	/* 17e: Enhanced LED behavior, needs to be written twice */
-	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-
-	/* 16e: Enhanced LED method select */
-	phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
-
-	/* Disable extended page register access */
-	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
-
-	/* Enable clock output pin */
-	phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+	unsigned short id1, id2;
+
+	/* check whether KSZ9031 or AR8035 has to be configured */
+	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
+	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
+
+	if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
+		/* PHY configuration for Micrel KSZ9031 */
+		printf("PHY KSZ9031 detected - ");
+
+		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03FF);
+	} else {
+		/* PHY configuration for Vitesse VSC8641 */
+		printf("PHY VSC8641 detected - ");
+
+		/* Extended PHY control 1, select GMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
+
+		/* Software reset necessary after GMII mode selction */
+		phy_reset(phydev);
+
+		/* Enable extended page register access */
+		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
+
+		/* 17e: Enhanced LED behavior, needs to be written twice */
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+
+		/* 16e: Enhanced LED method select */
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
+
+		/* Disable extended page register access */
+		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
+
+		/* Enable clock output pin */
+		phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+	}
 
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 5fdd2be..07c8abe 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -80,6 +80,8 @@
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 #define CONFIG_PHY_ADDR		0	/* PHY address */
 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_SPEAR_GPIO
 
-- 
cgit v0.10.2


From e084fd922f7483d591c623823452fff7879c9d71 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 27 Apr 2016 09:10:43 +0200
Subject: arm: spear: x600: Remove EFI support to reduce image size

EFI is not needed on x600. So lets remove the EFI support to make it fit
into the 0x60000 image size limit again.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index ace620b..14977dc 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -22,3 +22,4 @@ CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
-- 
cgit v0.10.2


From 2e4cc1c5d4fabee86fc2985fac18f9a2023e39f8 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 26 May 2016 14:49:33 +0100
Subject: MIPS: Use CPHYSADDR to implement mips32 virt_to_phys

Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.

This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:

    https://patchwork.linux-mips.org/patch/12564/

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 723a60a..5b86386 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -92,11 +92,8 @@ static inline unsigned long virt_to_phys(volatile const void *address)
 #ifdef CONFIG_64BIT
 	if (addr < CKSEG0)
 		return XPHYSADDR(addr);
-
-	return CPHYSADDR(addr);
-#else
-	return addr - PAGE_OFFSET + PHYS_OFFSET;
 #endif
+	return CPHYSADDR(addr);
 }
 
 /*
-- 
cgit v0.10.2


From 4677d665a7cba420597dd46606735f86416ce552 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 26 May 2016 14:49:34 +0100
Subject: net: pcnet: Stop converting kseg1->kseg0 addresses

Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop
manually converting addresses to their kseg0 equivalents in the pcnet
driver.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 16a7512..efa4afb 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -135,14 +135,11 @@ static void pcnet_halt (struct eth_device *dev);
 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 
 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
-						void *addr, bool uncached)
+						void *addr)
 {
 	pci_dev_t devbusfn = (pci_dev_t)dev->priv;
 	void *virt_addr = addr;
 
-	if (uncached)
-		virt_addr = (void *)CKSEG0ADDR(addr);
-
 	return pci_virt_to_mem(devbusfn, virt_addr);
 }
 
@@ -361,7 +358,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 	 */
 	lp->cur_rx = 0;
 	for (i = 0; i < RX_RING_SIZE; i++) {
-		addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+		addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
 		uc->rx_ring[i].base = cpu_to_le32(addr);
 		uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 		uc->rx_ring[i].status = cpu_to_le16(0x8000);
@@ -393,9 +390,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 
 	uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 					       RX_RING_LEN_BITS);
-	addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+	addr = pcnet_virt_to_mem(dev, uc->rx_ring);
 	uc->init_block.rx_ring = cpu_to_le32(addr);
-	addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+	addr = pcnet_virt_to_mem(dev, uc->tx_ring);
 	uc->init_block.tx_ring = cpu_to_le32(addr);
 
 	PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
@@ -406,7 +403,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 	 * Tell the controller where the Init Block is located.
 	 */
 	barrier();
-	addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
+	addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
 	pcnet_write_csr(dev, 1, addr & 0xffff);
 	pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 
@@ -464,7 +461,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 	 * Setup Tx ring. Caution: the write order is important here,
 	 * set the status with the "ownership" bits last.
 	 */
-	addr = pcnet_virt_to_mem(dev, packet, false);
+	addr = pcnet_virt_to_mem(dev, packet);
 	writew(-pkt_len, &entry->length);
 	writel(0, &entry->misc);
 	writel(addr, &entry->base);
-- 
cgit v0.10.2


From 442d2e0149c4f3f2dadcf6ebc28b58d317fc5aa0 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 26 May 2016 14:49:35 +0100
Subject: net: pcnet: Make 64 bit safe

Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index efa4afb..d1fd4e4 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -137,7 +137,7 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
 						void *addr)
 {
-	pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+	pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
 	void *virt_addr = addr;
 
 	return pci_virt_to_mem(devbusfn, virt_addr);
@@ -176,7 +176,7 @@ int pcnet_initialize(bd_t *bis)
 			break;
 		}
 		memset(dev, 0, sizeof(*dev));
-		dev->priv = (void *)devbusfn;
+		dev->priv = (void *)(unsigned long)devbusfn;
 		sprintf(dev->name, "pcnet#%d", dev_nr);
 
 		/*
@@ -187,8 +187,8 @@ int pcnet_initialize(bd_t *bis)
 		dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
 		dev->iobase &= ~0xf;
 
-		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
-			     dev->name, devbusfn, dev->iobase);
+		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
+			     dev->name, devbusfn, (unsigned long)dev->iobase);
 
 		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
 		pci_write_config_word(devbusfn, PCI_COMMAND, command);
@@ -295,7 +295,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 {
 	struct pcnet_uncached_priv *uc;
 	int i, val;
-	u32 addr;
+	unsigned long addr;
 
 	PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 
@@ -333,16 +333,18 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 	 * must be aligned on 16-byte boundaries.
 	 */
 	if (lp == NULL) {
-		addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
+		addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
 		addr = (addr + 0xf) & ~0xf;
 		lp = (pcnet_priv_t *)addr;
 
-		addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
+		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+					       sizeof(*lp->uc));
 		flush_dcache_range(addr, addr + sizeof(*lp->uc));
 		addr = UNCACHED_SDRAM(addr);
 		lp->uc = (struct pcnet_uncached_priv *)addr;
 
-		addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf));
+		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+					       sizeof(*lp->rx_buf));
 		flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
 		lp->rx_buf = (void *)addr;
 	}
-- 
cgit v0.10.2


From bed1ca322da9b597aa59723a02a1dd647bf8bde4 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 26 May 2016 17:32:29 +0100
Subject: net: pcnet: Fix init on big endian 64 bit

If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index d1fd4e4..1da9996 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -155,6 +155,7 @@ int pcnet_initialize(bd_t *bis)
 	struct eth_device *dev;
 	u16 command, status;
 	int dev_nr = 0;
+	u32 bar;
 
 	PCNET_DEBUG1("\npcnet_initialize...\n");
 
@@ -182,9 +183,8 @@ int pcnet_initialize(bd_t *bis)
 		/*
 		 * Setup the PCI device.
 		 */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
-				      (unsigned int *)&dev->iobase);
-		dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
+		dev->iobase = pci_io_to_phys(devbusfn, bar);
 		dev->iobase &= ~0xf;
 
 		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
-- 
cgit v0.10.2


From 0f832b9cdcbe8a024b53c585622d70129652d20b Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 26 May 2016 14:49:36 +0100
Subject: malta: Allow MIPS64 builds

Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 53363e3..abaeaf0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -33,6 +33,9 @@ config TARGET_MALTA
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_CPU_MIPS32_R6
+	select SUPPORTS_CPU_MIPS64_R1
+	select SUPPORTS_CPU_MIPS64_R2
+	select SUPPORTS_CPU_MIPS64_R6
 	select SWAP_IO_SPACE
 	select MIPS_L1_CACHE_SHIFT_6
 
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 2bb8e8b..98eb4d1 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -10,6 +10,7 @@ config SYS_CONFIG_NAME
 	default "malta"
 
 config SYS_TEXT_BASE
-	default 0xbe000000
+	default 0xbe000000 if 32BIT
+	default 0xffffffffbe000000 if 64BIT
 
 endif
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 534db1d..3d48cdc 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -10,6 +10,7 @@
 #include <pci.h>
 
 #include <asm/addrspace.h>
+#include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/malta.h>
 #include <asm/mipsregs.h>
@@ -34,7 +35,7 @@ lowlevel_init:
 	mtc0	t0, CP0_CONFIG, 2
 
 	/* detect the core card */
-	li	t0, KSEG1ADDR(MALTA_REVISION)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_REVISION)
 	lw	t0, 0(t0)
 	srl	t0, t0, MALTA_REVISION_CORID_SHF
 	andi	t0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -68,12 +69,12 @@ lowlevel_init:
 	 */
 _gt64120:
 	/* move GT64120 registers from 0x14000000 to 0x1be00000 */
-	li	t1, KSEG1ADDR(GT_DEF_BASE)
+	PTR_LI	t1, CKSEG1ADDR(GT_DEF_BASE)
 	li	t0, CPU_TO_GT32(0xdf000000)
 	sw	t0, GT_ISD_OFS(t1)
 
 	/* setup MEM-to-PCI0 mapping */
-	li	t1, KSEG1ADDR(MALTA_GT_BASE)
+	PTR_LI	t1, CKSEG1ADDR(MALTA_GT_BASE)
 
 	/* setup PCI0 io window to 0x18000000-0x181fffff */
 	li	t0, CPU_TO_GT32(0xc0000000)
@@ -100,7 +101,7 @@ _gt64120:
 	 */
 _msc01:
 	/* setup peripheral bus controller clock divide */
-	li	t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
 	li	t1, 0x1 << MSC01_PBC_CLKCFG_SHF
 	sw	t1, MSC01_PBC_CLKCFG_OFS(t0)
 
@@ -122,7 +123,7 @@ _msc01:
 	sw	t1, MSC01_PBC_CS0CFG_OFS(t0)
 
 	/* setup basic address decode */
-	li	t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
 	li	t1, 0x0
 	li	t2, -CONFIG_SYS_MEM_SIZE
 	sw	t1, MSC01_BIU_MCBAS1L_OFS(t0)
@@ -157,7 +158,7 @@ _msc01:
 	sw	t2, MSC01_BIU_IP3MSK2L_OFS(t0)
 
 	/* setup PCI memory */
-	li	t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
 	li	t1, MALTA_MSC01_PCIMEM_BASE
 	li	t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
 	li	t3, MALTA_MSC01_PCIMEM_MAP
diff --git a/include/configs/malta.h b/include/configs/malta.h
index a369678..fc4baba 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -39,14 +39,18 @@
  */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE		0x80000000
+#endif
 #define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
-#define CONFIG_SYS_LOAD_ADDR		0x81000000
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x00800000)
 
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
@@ -69,7 +73,11 @@
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE		0xbe000000
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE		0xffffffffbe000000
+#else
+# define CONFIG_SYS_FLASH_BASE		0xbe000000
+#endif
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	128
 #define CONFIG_SYS_FLASH_CFI
-- 
cgit v0.10.2


From 07f5b966aa2a4fe3a9bed8e90103cb0fe83c8748 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Thu, 26 May 2016 15:28:38 +0200
Subject: MIPS: provide a default u-boot-spl.lds

Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 609a998..dcd3460 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -65,7 +65,7 @@ else
 PF_ABICALLS			:= -mabicalls
 PF_PIC				:= -fpic
 PF_PIE				:= -pie
-PF_OBJCOPY			:= -j .got -j .u_boot_list -j .rel.dyn -j .padding
+PF_OBJCOPY			:= -j .got -j .rel.dyn -j .padding
 PF_OBJCOPY			+= -j .dtb.init.rodata
 endif
 
@@ -74,4 +74,5 @@ PLATFORM_CPPFLAGS		+= -msoft-float
 PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
 LDFLAGS_FINAL			+= --gc-sections $(PF_PIE)
-OBJCOPYFLAGS			+= -j .text -j .rodata -j .data $(PF_OBJCOPY)
+OBJCOPYFLAGS			+= -j .text -j .rodata -j .data -j .u_boot_list
+OBJCOPYFLAGS			+= $(PF_OBJCOPY)
diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds
new file mode 100644
index 0000000..07004ea
--- /dev/null
+++ b/arch/mips/cpu/u-boot-spl.lds
@@ -0,0 +1,90 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text : {
+		*(.text*)
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.data : {
+		*(SORT_BY_ALIGNMENT(.data*))
+		*(SORT_BY_ALIGNMENT(.sdata*))
+	} > .spl_mem
+
+#ifdef CONFIG_SPL_DM
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .spl_mem
+#endif
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.bss (NOLOAD) : {
+		__bss_start = .;
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .bss_mem
+
+	.rel.dyn (NOLOAD) : {
+		*(.rel.dyn)
+	}
+
+	.dynsym : {
+		*(.dynsym)
+	}
+
+	.dynbss : {
+		*(.dynbss)
+	}
+
+	.dynstr : {
+		*(.dynstr)
+	}
+
+	.dynamic : {
+		*(.dynamic)
+	}
+
+	.plt : {
+		*(.plt)
+	}
+
+	.interp : {
+		*(.interp)
+	}
+
+	.gnu : {
+		*(.gnu*)
+	}
+
+	.MIPS.stubs : {
+		*(.MIPS.stubs)
+	}
+
+	.hash : {
+		*(.hash)
+	}
+}
-- 
cgit v0.10.2


From 5f9cc363ed9b68245cacc6408c793f150992f4d9 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Fri, 27 May 2016 15:39:39 +0200
Subject: MIPS: add tune for MIPS 34kc

Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index abaeaf0..a929452 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -228,6 +228,9 @@ config MIPS_TUNE_14KC
 config MIPS_TUNE_24KC
 	bool
 
+config MIPS_TUNE_34KC
+	bool
+
 config MIPS_TUNE_74KC
 	bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0b5dbb6..efe7e44 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -34,6 +34,7 @@ arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
 tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
 tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
 tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
 
 # Include default header files
-- 
cgit v0.10.2


From e40095f63b4bc0edd747c7f104d3e54db61e7d3d Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 24 May 2016 23:29:09 +0200
Subject: net: Add ag7xxx driver for Atheros MIPS

Add ethernet driver for the AR933x and AR934x Atheros MIPS machines.
The driver could be easily extended to other WiSoCs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Wills Wang <wills.wang@live.com>
[fixed Kconfig dependency]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 91b7690..c1cb689 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -46,6 +46,15 @@ menuconfig NETDEVICES
 
 if NETDEVICES
 
+config AG7XXX
+	bool "Atheros AG7xxx Ethernet MAC support"
+	depends on DM_ETH && ARCH_ATH79
+	select PHYLIB
+	help
+	  This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
+	  present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips.
+
+
 config ALTERA_TSE
 	bool "Altera Triple-Speed Ethernet MAC support"
 	depends on DM_ETH
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d5e4a97..5702592 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
 obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
+obj-$(CONFIG_AG7XXX) += ag7xxx.o
 obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
 obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
 obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
new file mode 100644
index 0000000..346f138
--- /dev/null
+++ b/drivers/net/ag7xxx.c
@@ -0,0 +1,980 @@
+/*
+ * Atheros AR71xx / AR9xxx GMAC driver
+ *
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/mii.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+#include <mach/ath79.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ag7xxx_model {
+	AG7XXX_MODEL_AG933X,
+	AG7XXX_MODEL_AG934X,
+};
+
+#define AG7XXX_ETH_CFG1				0x00
+#define AG7XXX_ETH_CFG1_SOFT_RST		BIT(31)
+#define AG7XXX_ETH_CFG1_RX_RST			BIT(19)
+#define AG7XXX_ETH_CFG1_TX_RST			BIT(18)
+#define AG7XXX_ETH_CFG1_LOOPBACK		BIT(8)
+#define AG7XXX_ETH_CFG1_RX_EN			BIT(2)
+#define AG7XXX_ETH_CFG1_TX_EN			BIT(0)
+
+#define AG7XXX_ETH_CFG2				0x04
+#define AG7XXX_ETH_CFG2_IF_1000			BIT(9)
+#define AG7XXX_ETH_CFG2_IF_10_100		BIT(8)
+#define AG7XXX_ETH_CFG2_IF_SPEED_MASK		(3 << 8)
+#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN		BIT(5)
+#define AG7XXX_ETH_CFG2_LEN_CHECK		BIT(4)
+#define AG7XXX_ETH_CFG2_PAD_CRC_EN		BIT(2)
+#define AG7XXX_ETH_CFG2_FDX			BIT(0)
+
+#define AG7XXX_ETH_MII_MGMT_CFG			0x20
+#define AG7XXX_ETH_MII_MGMT_CFG_RESET		BIT(31)
+
+#define AG7XXX_ETH_MII_MGMT_CMD			0x24
+#define AG7XXX_ETH_MII_MGMT_CMD_READ		0x1
+
+#define AG7XXX_ETH_MII_MGMT_ADDRESS		0x28
+#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT	8
+
+#define AG7XXX_ETH_MII_MGMT_CTRL		0x2c
+
+#define AG7XXX_ETH_MII_MGMT_STATUS		0x30
+
+#define AG7XXX_ETH_MII_MGMT_IND			0x34
+#define AG7XXX_ETH_MII_MGMT_IND_INVALID		BIT(2)
+#define AG7XXX_ETH_MII_MGMT_IND_BUSY		BIT(0)
+
+#define AG7XXX_ETH_ADDR1			0x40
+#define AG7XXX_ETH_ADDR2			0x44
+
+#define AG7XXX_ETH_FIFO_CFG_0			0x48
+#define AG7XXX_ETH_FIFO_CFG_1			0x4c
+#define AG7XXX_ETH_FIFO_CFG_2			0x50
+#define AG7XXX_ETH_FIFO_CFG_3			0x54
+#define AG7XXX_ETH_FIFO_CFG_4			0x58
+#define AG7XXX_ETH_FIFO_CFG_5			0x5c
+
+#define AG7XXX_ETH_DMA_TX_CTRL			0x180
+#define AG7XXX_ETH_DMA_TX_CTRL_TXE		BIT(0)
+
+#define AG7XXX_ETH_DMA_TX_DESC			0x184
+
+#define AG7XXX_ETH_DMA_TX_STATUS		0x188
+
+#define AG7XXX_ETH_DMA_RX_CTRL			0x18c
+#define AG7XXX_ETH_DMA_RX_CTRL_RXE		BIT(0)
+
+#define AG7XXX_ETH_DMA_RX_DESC			0x190
+
+#define AG7XXX_ETH_DMA_RX_STATUS		0x194
+
+/* Custom register at 0x18070000 */
+#define AG7XXX_GMAC_ETH_CFG			0x00
+#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP		BIT(8)
+#define AG7XXX_ETH_CFG_SW_PHY_SWAP		BIT(7)
+#define AG7XXX_ETH_CFG_SW_ONLY_MODE		BIT(6)
+#define AG7XXX_ETH_CFG_GE0_ERR_EN		BIT(5)
+#define AG7XXX_ETH_CFG_MII_GE0_SLAVE		BIT(4)
+#define AG7XXX_ETH_CFG_MII_GE0_MASTER		BIT(3)
+#define AG7XXX_ETH_CFG_GMII_GE0			BIT(2)
+#define AG7XXX_ETH_CFG_MII_GE0			BIT(1)
+#define AG7XXX_ETH_CFG_RGMII_GE0		BIT(0)
+
+#define CONFIG_TX_DESCR_NUM	8
+#define CONFIG_RX_DESCR_NUM	8
+#define CONFIG_ETH_BUFSIZE	2048
+#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+/* DMA descriptor. */
+struct ag7xxx_dma_desc {
+	u32	data_addr;
+#define AG7XXX_DMADESC_IS_EMPTY			BIT(31)
+#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET	16
+#define AG7XXX_DMADESC_PKT_SIZE_OFFSET		0
+#define AG7XXX_DMADESC_PKT_SIZE_MASK		0xfff
+	u32	config;
+	u32	next_desc;
+	u32	_pad[5];
+};
+
+struct ar7xxx_eth_priv {
+	struct ag7xxx_dma_desc	tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+	struct ag7xxx_dma_desc	rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+	char		txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+	char		rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+
+	void __iomem		*regs;
+	void __iomem		*phyregs;
+
+	struct eth_device	*dev;
+	struct phy_device	*phydev;
+	struct mii_dev		*bus;
+
+	u32			interface;
+	u32			tx_currdescnum;
+	u32			rx_currdescnum;
+	enum ag7xxx_model	model;
+};
+
+/*
+ * Switch and MDIO access
+ */
+static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	void __iomem *regs = priv->phyregs;
+	int ret;
+
+	writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
+	writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
+	       regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
+	writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
+	       regs + AG7XXX_ETH_MII_MGMT_CMD);
+
+	ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
+			   AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+	if (ret)
+		return ret;
+
+	*val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
+	writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
+
+	return 0;
+}
+
+static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	void __iomem *regs = priv->phyregs;
+	int ret;
+
+	writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
+	       regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
+	writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
+
+	ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
+			   AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+
+	return ret;
+}
+
+static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	u32 phy_addr;
+	u32 reg_addr;
+	u32 phy_temp;
+	u32 reg_temp;
+	u16 rv = 0;
+	int ret;
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		phy_addr = 0x1f;
+		reg_addr = 0x10;
+	} else if (priv->model == AG7XXX_MODEL_AG934X) {
+		phy_addr = 0x18;
+		reg_addr = 0x00;
+	} else
+		return -EINVAL;
+
+	ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+	if (ret)
+		return ret;
+
+	phy_temp = ((reg >> 6) & 0x7) | 0x10;
+	reg_temp = (reg >> 1) & 0x1e;
+	*val = 0;
+
+	ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
+	if (ret < 0)
+		return ret;
+	*val |= rv;
+
+	ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
+	if (ret < 0)
+		return ret;
+	*val |= (rv << 16);
+
+	return 0;
+}
+
+static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	u32 phy_addr;
+	u32 reg_addr;
+	u32 phy_temp;
+	u32 reg_temp;
+	int ret;
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		phy_addr = 0x1f;
+		reg_addr = 0x10;
+	} else if (priv->model == AG7XXX_MODEL_AG934X) {
+		phy_addr = 0x18;
+		reg_addr = 0x00;
+	} else
+		return -EINVAL;
+
+	ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+	if (ret)
+		return ret;
+
+	phy_temp = ((reg >> 6) & 0x7) | 0x10;
+	reg_temp = (reg >> 1) & 0x1e;
+
+	/*
+	 * The switch on AR933x has some special register behavior, which
+	 * expects particular write order of their nibbles:
+	 *   0x40 ..... MSB first, LSB second
+	 *   0x50 ..... MSB first, LSB second
+	 *   0x98 ..... LSB first, MSB second
+	 *   others ... don't care
+	 */
+	if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
+		if (ret < 0)
+			return ret;
+
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
+		if (ret < 0)
+			return ret;
+	} else {
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
+		if (ret < 0)
+			return ret;
+
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
+{
+	u32 data;
+
+	/* Dummy read followed by PHY read/write command. */
+	ag7xxx_switch_reg_read(bus, 0x98, &data);
+	data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
+	ag7xxx_switch_reg_write(bus, 0x98, data);
+
+	/* Wait for operation to finish */
+	do {
+		ag7xxx_switch_reg_read(bus, 0x98, &data);
+	} while (data & BIT(31));
+
+	return data & 0xffff;
+}
+
+static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+	return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
+}
+
+static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+			     u16 val)
+{
+	ag7xxx_mdio_rw(bus, addr, reg, val);
+	return 0;
+}
+
+/*
+ * DMA ring handlers
+ */
+static void ag7xxx_dma_clean_tx(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr, *next;
+	u32 start, end;
+	int i;
+
+	for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+		curr = &priv->tx_mac_descrtable[i];
+		next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
+
+		curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
+		curr->config = AG7XXX_DMADESC_IS_EMPTY;
+		curr->next_desc = virt_to_phys(next);
+	}
+
+	priv->tx_currdescnum = 0;
+
+	/* Cache: Flush descriptors, don't care about buffers. */
+	start = (u32)(&priv->tx_mac_descrtable[0]);
+	end = start + sizeof(priv->tx_mac_descrtable);
+	flush_dcache_range(start, end);
+}
+
+static void ag7xxx_dma_clean_rx(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr, *next;
+	u32 start, end;
+	int i;
+
+	for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+		curr = &priv->rx_mac_descrtable[i];
+		next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
+
+		curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
+		curr->config = AG7XXX_DMADESC_IS_EMPTY;
+		curr->next_desc = virt_to_phys(next);
+	}
+
+	priv->rx_currdescnum = 0;
+
+	/* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
+	start = (u32)(&priv->rx_mac_descrtable[0]);
+	end = start + sizeof(priv->rx_mac_descrtable);
+	flush_dcache_range(start, end);
+	invalidate_dcache_range(start, end);
+
+	start = (u32)&priv->rxbuffs;
+	end = start + sizeof(priv->rxbuffs);
+	invalidate_dcache_range(start, end);
+}
+
+/*
+ * Ethernet I/O
+ */
+static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr;
+	u32 start, end;
+
+	curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
+
+	/* Cache: Invalidate descriptor. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	invalidate_dcache_range(start, end);
+
+	if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
+		printf("ag7xxx: Out of TX DMA descriptors!\n");
+		return -EPERM;
+	}
+
+	/* Copy the packet into the data buffer. */
+	memcpy(phys_to_virt(curr->data_addr), packet, length);
+	curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
+
+	/* Cache: Flush descriptor, Flush buffer. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	flush_dcache_range(start, end);
+	start = (u32)phys_to_virt(curr->data_addr);
+	end = start + length;
+	flush_dcache_range(start, end);
+
+	/* Load the DMA descriptor and start TX DMA. */
+	writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
+	       priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
+
+	/* Switch to next TX descriptor. */
+	priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
+
+	return 0;
+}
+
+static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr;
+	u32 start, end, length;
+
+	curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
+
+	/* Cache: Invalidate descriptor. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	invalidate_dcache_range(start, end);
+
+	/* No packets received. */
+	if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
+		return -EAGAIN;
+
+	length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
+
+	/* Cache: Invalidate buffer. */
+	start = (u32)phys_to_virt(curr->data_addr);
+	end = start + length;
+	invalidate_dcache_range(start, end);
+
+	/* Receive one packet and return length. */
+	*packetp = phys_to_virt(curr->data_addr);
+	return length;
+}
+
+static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
+				   int length)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr;
+	u32 start, end;
+
+	curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
+
+	curr->config = AG7XXX_DMADESC_IS_EMPTY;
+
+	/* Cache: Flush descriptor. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	flush_dcache_range(start, end);
+
+	/* Switch to next RX descriptor. */
+	priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
+
+	return 0;
+}
+
+static int ag7xxx_eth_start(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	/* FIXME: Check if link up */
+
+	/* Clear the DMA rings. */
+	ag7xxx_dma_clean_tx(dev);
+	ag7xxx_dma_clean_rx(dev);
+
+	/* Load DMA descriptors and start the RX DMA. */
+	writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
+	       priv->regs + AG7XXX_ETH_DMA_TX_DESC);
+	writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
+	       priv->regs + AG7XXX_ETH_DMA_RX_DESC);
+	writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
+	       priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
+
+	return 0;
+}
+
+static void ag7xxx_eth_stop(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	/* Stop the TX DMA. */
+	writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
+	wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+		     1000, 0);
+
+	/* Stop the RX DMA. */
+	writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
+	wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+		     1000, 0);
+}
+
+/*
+ * Hardware setup
+ */
+static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	unsigned char *mac = pdata->enetaddr;
+	u32 macid_lo, macid_hi;
+
+	macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
+	macid_lo = (mac[5] << 16) | (mac[4] << 24);
+
+	writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
+	writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
+
+	return 0;
+}
+
+static void ag7xxx_hw_setup(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	u32 speed;
+
+	setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
+		     AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
+		     AG7XXX_ETH_CFG1_SOFT_RST);
+
+	mdelay(10);
+
+	writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
+	       priv->regs + AG7XXX_ETH_CFG1);
+
+	if (priv->interface == PHY_INTERFACE_MODE_RMII)
+		speed = AG7XXX_ETH_CFG2_IF_10_100;
+	else
+		speed = AG7XXX_ETH_CFG2_IF_1000;
+
+	clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
+			AG7XXX_ETH_CFG2_IF_SPEED_MASK,
+			speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
+			AG7XXX_ETH_CFG2_LEN_CHECK);
+
+	writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
+	writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
+
+	writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
+	setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
+	writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
+	writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
+	writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
+	writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
+}
+
+static int ag7xxx_mii_get_div(void)
+{
+	ulong freq = get_bus_freq(0);
+
+	switch (freq / 1000000) {
+	case 150:	return 0x7;
+	case 175:	return 0x5;
+	case 200:	return 0x4;
+	case 210:	return 0x9;
+	case 220:	return 0x9;
+	default:	return 0x7;
+	}
+}
+
+static int ag7xxx_mii_setup(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret, div = ag7xxx_mii_get_div();
+	u32 reg;
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		/* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
+		if (priv->interface == PHY_INTERFACE_MODE_RMII)
+			return 0;
+	}
+
+	if (priv->model == AG7XXX_MODEL_AG934X) {
+		writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4,
+		       priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+		writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+		return 0;
+	}
+
+	for (i = 0; i < 10; i++) {
+		writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
+		       priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+		writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+
+		/* Check the switch */
+		ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg);
+		if (ret)
+			continue;
+
+		if (reg != 0x18007fff)
+			continue;
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static int ag933x_phy_setup_wan(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	/* Configure switch port 4 (GMAC0) */
+	return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
+}
+
+static int ag933x_phy_setup_lan(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret;
+	u32 reg;
+
+	/* Reset the switch */
+	ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
+	if (ret)
+		return ret;
+	reg |= BIT(31);
+	ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
+	if (ret)
+		return ret;
+
+	do {
+		ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
+		if (ret)
+			return ret;
+	} while (reg & BIT(31));
+
+	/* Configure switch ports 0...3 (GMAC1) */
+	for (i = 0; i < 4; i++) {
+		ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
+		if (ret)
+			return ret;
+	}
+
+	/* Enable CPU port */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
+	if (ret)
+		return ret;
+
+	for (i = 0; i < 4; i++) {
+		ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
+		if (ret)
+			return ret;
+	}
+
+	/* QM Control */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
+	if (ret)
+		return ret;
+
+	/* Disable Atheros header */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
+	if (ret)
+		return ret;
+
+	/* Tag priority mapping */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
+	if (ret)
+		return ret;
+
+	/* Enable ARP packets to the CPU */
+	ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
+	if (ret)
+		return ret;
+	reg |= 0x100000;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
+				ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
+				ADVERTISE_PAUSE_ASYM);
+	if (ret)
+		return ret;
+
+	if (priv->model == AG7XXX_MODEL_AG934X) {
+		ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
+					ADVERTISE_1000FULL);
+		if (ret)
+			return ret;
+	}
+
+	return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
+				 BMCR_ANENABLE | BMCR_RESET);
+}
+
+static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	do {
+		ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
+		if (ret < 0)
+			return ret;
+		mdelay(10);
+	} while (ret & BMCR_RESET);
+
+	return 0;
+}
+
+static int ag933x_phy_setup_common(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret, phymax;
+
+	if (priv->model == AG7XXX_MODEL_AG933X)
+		phymax = 4;
+	else if (priv->model == AG7XXX_MODEL_AG934X)
+		phymax = 5;
+	else
+		return -EINVAL;
+
+	if (priv->interface == PHY_INTERFACE_MODE_RMII) {
+		ret = ag933x_phy_setup_reset_set(dev, phymax);
+		if (ret)
+			return ret;
+
+		ret = ag933x_phy_setup_reset_fin(dev, phymax);
+		if (ret)
+			return ret;
+
+		/* Read out link status */
+		ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
+		if (ret < 0)
+			return ret;
+
+		return 0;
+	}
+
+	/* Switch ports */
+	for (i = 0; i < phymax; i++) {
+		ret = ag933x_phy_setup_reset_set(dev, i);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < phymax; i++) {
+		ret = ag933x_phy_setup_reset_fin(dev, i);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < phymax; i++) {
+		/* Read out link status */
+		ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ag934x_phy_setup(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret;
+	u32 reg;
+
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
+	if (ret)
+		return ret;
+
+	/* AR8327/AR8328 v1.0 fixup */
+	ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
+	if (ret)
+		return ret;
+	if ((reg & 0xffff) == 0x1201) {
+		for (i = 0; i < 5; i++) {
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
+			if (ret)
+				return ret;
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
+			if (ret)
+				return ret;
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
+			if (ret)
+				return ret;
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
+			if (ret)
+				return ret;
+		}
+	}
+
+	ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg);
+	if (ret)
+		return ret;
+	reg &= ~0x70000;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ag7xxx_mac_probe(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ag7xxx_hw_setup(dev);
+	ret = ag7xxx_mii_setup(dev);
+	if (ret)
+		return ret;
+
+	ag7xxx_eth_write_hwaddr(dev);
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		if (priv->interface == PHY_INTERFACE_MODE_RMII)
+			ret = ag933x_phy_setup_wan(dev);
+		else
+			ret = ag933x_phy_setup_lan(dev);
+	} else if (priv->model == AG7XXX_MODEL_AG934X) {
+		ret = ag934x_phy_setup(dev);
+	} else {
+		return -EINVAL;
+	}
+
+	if (ret)
+		return ret;
+
+	return ag933x_phy_setup_common(dev);
+}
+
+static int ag7xxx_mdio_probe(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus)
+		return -ENOMEM;
+
+	bus->read = ag7xxx_mdio_read;
+	bus->write = ag7xxx_mdio_write;
+	snprintf(bus->name, sizeof(bus->name), dev->name);
+
+	bus->priv = (void *)priv;
+
+	return mdio_register(bus);
+}
+
+static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
+{
+	int offset;
+
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy");
+	if (offset <= 0) {
+		debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
+		return -EINVAL;
+	}
+
+	offset = fdt_parent_offset(gd->fdt_blob, offset);
+	if (offset <= 0) {
+		debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
+		      __func__, offset);
+		return -EINVAL;
+	}
+
+	offset = fdt_parent_offset(gd->fdt_blob, offset);
+	if (offset <= 0) {
+		debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
+		      __func__, offset);
+		return -EINVAL;
+	}
+
+	return offset;
+}
+
+static int ag7xxx_eth_probe(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	void __iomem *iobase, *phyiobase;
+	int ret, phyreg;
+
+	/* Decoding of convoluted PHY wiring on Atheros MIPS. */
+	ret = ag7xxx_get_phy_iface_offset(dev);
+	if (ret <= 0)
+		return ret;
+	phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
+
+	iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
+	phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
+
+	debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
+	      __func__, iobase, phyiobase, priv);
+	priv->regs = iobase;
+	priv->phyregs = phyiobase;
+	priv->interface = pdata->phy_interface;
+	priv->model = dev_get_driver_data(dev);
+
+	ret = ag7xxx_mdio_probe(dev);
+	if (ret)
+		return ret;
+
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	ret = ag7xxx_mac_probe(dev);
+	debug("%s, ret=%d\n", __func__, ret);
+
+	return ret;
+}
+
+static int ag7xxx_eth_remove(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	free(priv->phydev);
+	mdio_unregister(priv->bus);
+	mdio_free(priv->bus);
+
+	return 0;
+}
+
+static const struct eth_ops ag7xxx_eth_ops = {
+	.start			= ag7xxx_eth_start,
+	.send			= ag7xxx_eth_send,
+	.recv			= ag7xxx_eth_recv,
+	.free_pkt		= ag7xxx_eth_free_pkt,
+	.stop			= ag7xxx_eth_stop,
+	.write_hwaddr		= ag7xxx_eth_write_hwaddr,
+};
+
+static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	const char *phy_mode;
+	int ret;
+
+	pdata->iobase = dev_get_addr(dev);
+	pdata->phy_interface = -1;
+
+	/* Decoding of convoluted PHY wiring on Atheros MIPS. */
+	ret = ag7xxx_get_phy_iface_offset(dev);
+	if (ret <= 0)
+		return ret;
+
+	phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
+	if (phy_mode)
+		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+	if (pdata->phy_interface == -1) {
+		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ag7xxx_eth_ids[] = {
+	{ .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
+	{ .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_ag7xxx) = {
+	.name		= "eth_ag7xxx",
+	.id		= UCLASS_ETH,
+	.of_match	= ag7xxx_eth_ids,
+	.ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
+	.probe		= ag7xxx_eth_probe,
+	.remove		= ag7xxx_eth_remove,
+	.ops		= &ag7xxx_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
cgit v0.10.2


From 83b0face8c710f719445f3c282c2ca6fad326bd7 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Fri, 27 May 2016 15:31:34 +0200
Subject: MIPS: remove dead code from asm/u-boot-mips.h

Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index a5b2fc0..1f527bb 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -1,23 +1,8 @@
 /*
  * SPDX-License-Identifier:	GPL-2.0+
- *
- * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  */
 
-static inline unsigned long bss_start(void)
-{
-	extern char __bss_start[];
-	return (unsigned long) &__bss_start;
-}
+#ifndef _U_BOOT_MIPS_H_
+#define _U_BOOT_MIPS_H_
 
-static inline unsigned long bss_end(void)
-{
-	extern ulong __bss_end;
-	return (unsigned long) &__bss_end;
-}
-
-static inline unsigned long image_copy_end(void)
-{
-	extern char __image_copy_end[];
-	return (unsigned long) &__image_copy_end;
-}
+#endif /* _U_BOOT_MIPS_H_ */
-- 
cgit v0.10.2


From ace3be4f15875d74344336b9754c14274f940969 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Fri, 27 May 2016 14:28:04 +0100
Subject: MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a929452..a79224e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -246,6 +246,34 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 	bool
 
+config SYS_DCACHE_SIZE
+	int
+	default 0
+	help
+	  The total size of the L1 Dcache, if known at compile time.
+
+config SYS_ICACHE_SIZE
+	int
+	default 0
+	help
+	  The total size of the L1 ICache, if known at compile time.
+
+config SYS_CACHELINE_SIZE
+	int
+	default 0
+	help
+	  The size of L1 cache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+		SYS_CACHELINE_SIZE = 0
+	help
+	  Select this (or let it be auto-selected by not defining any cache
+	  sizes) in order to allow U-Boot to automatically detect the sizes
+	  of caches at runtime. This has a small cost in code size & runtime
+	  so if you know the cache configuration for your system at compile
+	  time it would be beneficial to configure it.
+
 config MIPS_L1_CACHE_SHIFT_4
 	bool
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005..fbaafee 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,7 +9,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 
 static inline unsigned long icache_line_size(void)
 {
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3a..4bb9a17 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,14 +99,14 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t2, CONFIG_SYS_ICACHE_SIZE
 	li	t8, CONFIG_SYS_CACHELINE_SIZE
 #else
 	l1_info	t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t3, CONFIG_SYS_DCACHE_SIZE
 	li	t9, CONFIG_SYS_CACHELINE_SIZE
 #else
@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
 	/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
 	li	v0, CONFIG_SYS_ICACHE_SIZE
 #else
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 342ec59..1715a28 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0xbfc00000
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 menu "dbau1x00 board options"
 
 choice
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 535a77b..5bb6f03 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x87000000
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 menu "vct board options"
 
 choice
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 236a410..27b2ef0 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x83800000
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index c3ecc8f..f28ea1c 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x9f000000
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 5ea5d6f..ff02236 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x9f000000
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 3de1f44..66957e7 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -11,4 +11,13 @@ config SYS_TEXT_BASE
 	default 0xbfc00000 if 32BIT
 	default 0xffffffffbfc00000 if 64BIT
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 65785bd..ded7f9b 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -15,4 +15,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0xa1000000
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 6f69f31..f069d50 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  200
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index f907c02..e45f743 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  325
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 68d9e36..68ff025 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -202,11 +202,4 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 #endif /* CONFIG_DBAU1550 */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 869768a..b907419 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -144,12 +144,6 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * BOOTP options
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 246ee01..f58fc4c 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 60a3a71..2190d16 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 09a69fe..6273711 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ			280
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		0x8000
-#define CONFIG_SYS_ICACHE_SIZE		0x10000
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN		0x40000
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 68eb089..cc5e354 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -204,13 +204,6 @@
 #endif /* CONFIG_VCT_ONENAND */
 
 /*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
  * I2C/EEPROM
  */
 #define CONFIG_SYS_I2C
-- 
cgit v0.10.2


From 372286217f050bfd57695001d59f618c52822f40 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Fri, 27 May 2016 14:28:05 +0100
Subject: MIPS: Split I & D cache line size config

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a79224e..5c30ae9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -252,21 +252,27 @@ config SYS_DCACHE_SIZE
 	help
 	  The total size of the L1 Dcache, if known at compile time.
 
+config SYS_DCACHE_LINE_SIZE
+	hex
+	default 0
+	help
+	  The size of L1 Dcache lines, if known at compile time.
+
 config SYS_ICACHE_SIZE
 	int
 	default 0
 	help
 	  The total size of the L1 ICache, if known at compile time.
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	int
 	default 0
 	help
-	  The size of L1 cache lines, if known at compile time.
+	  The size of L1 Icache lines, if known at compile time.
 
 config SYS_CACHE_SIZE_AUTO
 	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-		SYS_CACHELINE_SIZE = 0
+		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
 	help
 	  Select this (or let it be auto-selected by not defining any cache
 	  sizes) in order to allow U-Boot to automatically detect the sizes
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 806bd26..0cea581 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -12,4 +12,11 @@
 
 #define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
 
+/*
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
 #endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index fbaafee..19a42ff 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,23 +9,13 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
-
 static inline unsigned long icache_line_size(void)
 {
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
+	unsigned long conf1, il;
 
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+	if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+		return CONFIG_SYS_ICACHE_LINE_SIZE;
 
-static inline unsigned long icache_line_size(void)
-{
-	unsigned long conf1, il;
 	conf1 = read_c0_config1();
 	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
 	if (!il)
@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
 static inline unsigned long dcache_line_size(void)
 {
 	unsigned long conf1, dl;
+
+	if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+		return CONFIG_SYS_DCACHE_LINE_SIZE;
+
 	conf1 = read_c0_config1();
 	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
 	if (!dl)
@@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
 	return 2 << dl;
 }
 
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
-
 void flush_cache(ulong start_addr, ulong size)
 {
 	unsigned long ilsize = icache_line_size();
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 4bb9a17..bc8ab27 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -101,14 +101,14 @@
 LEAF(mips_cache_reset)
 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t2, CONFIG_SYS_ICACHE_SIZE
-	li	t8, CONFIG_SYS_CACHELINE_SIZE
+	li	t8, CONFIG_SYS_ICACHE_LINE_SIZE
 #else
 	l1_info	t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t3, CONFIG_SYS_DCACHE_SIZE
-	li	t9, CONFIG_SYS_CACHELINE_SIZE
+	li	t9, CONFIG_SYS_DCACHE_LINE_SIZE
 #else
 	l1_info	t3, t9, MIPS_CONF1_DA_SHF
 #endif
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 1715a28..448176d 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 menu "dbau1x00 board options"
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 5bb6f03..df7c029 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 menu "vct board options"
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 27b2ef0..ef8905d 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index f28ea1c..4fd6a71 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 32768
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index ff02236..74c632a 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 32768
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 66957e7..e696a12 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -14,10 +14,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index ded7f9b..67a0228 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -18,10 +18,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 32768
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index fb2e41f..319e3b5 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -100,7 +100,6 @@
  * USB Configuration
  */
 #define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * File System Configuration
-- 
cgit v0.10.2


From fb64cda579985e21610672eae44faf40eadd71ea Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Fri, 27 May 2016 14:28:06 +0100
Subject: MIPS: Abstract cache op loops with a macro

The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 19a42ff..5f520c0 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -37,82 +37,59 @@ static inline unsigned long dcache_line_size(void)
 	return 2 << dl;
 }
 
+#define cache_loop(start, end, lsize, ops...) do {			\
+	const void *addr = (const void *)(start & ~(lsize - 1));	\
+	const void *aend = (const void *)((end - 1) & ~(lsize - 1));	\
+	const unsigned int cache_ops[] = { ops };			\
+	unsigned int i;							\
+									\
+	for (; addr <= aend; addr += lsize) {				\
+		for (i = 0; i < ARRAY_SIZE(cache_ops); i++)		\
+			mips_cache(cache_ops[i], addr);			\
+	}								\
+} while (0)
+
 void flush_cache(ulong start_addr, ulong size)
 {
 	unsigned long ilsize = icache_line_size();
 	unsigned long dlsize = dcache_line_size();
-	const void *addr, *aend;
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (size == 0)
 		return;
 
-	addr = (const void *)(start_addr & ~(dlsize - 1));
-	aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
-
 	if (ilsize == dlsize) {
 		/* flush I-cache & D-cache simultaneously */
-		while (1) {
-			mips_cache(HIT_WRITEBACK_INV_D, addr);
-			mips_cache(HIT_INVALIDATE_I, addr);
-			if (addr == aend)
-				break;
-			addr += dlsize;
-		}
+		cache_loop(start_addr, start_addr + size, ilsize,
+			   HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
 		return;
 	}
 
 	/* flush D-cache */
-	while (1) {
-		mips_cache(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += dlsize;
-	}
+	cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
 
 	/* flush I-cache */
-	addr = (const void *)(start_addr & ~(ilsize - 1));
-	aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
-	while (1) {
-		mips_cache(HIT_INVALIDATE_I, addr);
-		if (addr == aend)
-			break;
-		addr += ilsize;
-	}
+	cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
-	const void *addr = (const void *)(start_addr & ~(lsize - 1));
-	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (start_addr == stop)
 		return;
 
-	while (1) {
-		mips_cache(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
+	cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
-	const void *addr = (const void *)(start_addr & ~(lsize - 1));
-	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (start_addr == stop)
 		return;
 
-	while (1) {
-		mips_cache(HIT_INVALIDATE_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
+	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
 }
-- 
cgit v0.10.2


From d58de3157e3d04ebbf8e928cff9bfc2b3be22ad7 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 30 May 2016 13:00:21 +0200
Subject: MIPS: malta: add defconfigs for MIPS64

Add defconfigs for recently introduced MIPS64 support on
Malta boards to get more build coverage for MIPS64.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
new file mode 100644
index 0000000..7bef84c
--- /dev/null
+++ b/configs/malta64_defconfig
@@ -0,0 +1,16 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_MALTA=y
+CONFIG_CPU_MIPS64_R2=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="malta # "
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
new file mode 100644
index 0000000..47ded9e
--- /dev/null
+++ b/configs/malta64el_defconfig
@@ -0,0 +1,17 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R2=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="maltael # "
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
-- 
cgit v0.10.2


From 375239174c6bc6a9966db333fa79f578154828f5 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 22:54:50 +0800
Subject: mips: ath79: Rename get_bootstrap into ath79_get_bootstrap

Add a platform prefix for function name in order to make more readable,
and move it into ath79.h

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
index 9fcd496..6d98efc 100644
--- a/arch/mips/mach-ath79/ar933x/clk.c
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -17,7 +17,7 @@ static u32 ar933x_get_xtal(void)
 {
 	u32 val;
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
 		return 40000000;
 	else
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 7f20d34..2a25e23 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -10,7 +10,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -114,7 +114,7 @@ void ddr_init(void)
 	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
 	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & AR933X_BOOTSTRAP_DDR2) {
 		/* AHB maximum timeout */
 		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9c65184..9b41d3d 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 #include <wait_bit.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -119,7 +119,7 @@ void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
 	writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
 
 	/* Test for 40MHz XTAL */
-	reg = get_bootstrap();
+	reg = ath79_get_bootstrap();
 	if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
 		xtal_40 = 1;
 		cpu_srif = 0x41c00000;
@@ -214,7 +214,7 @@ static u32 ar934x_get_xtal(void)
 {
 	u32 val;
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & AR934X_BOOTSTRAP_REF_CLK_40)
 		return 40000000;
 	else
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
index 4621d58..2ba1efa 100644
--- a/arch/mips/mach-ath79/ar934x/ddr.c
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -11,7 +11,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,7 +45,7 @@ void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
 	ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 			       MAP_NOCACHE);
 
-	reg = get_bootstrap();
+	reg = ath79_get_bootstrap();
 	if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) {	/* DDR */
 		if (reg & AR934X_BOOTSTRAP_DDR1) {	/* DDR 1 */
 			memtype = AR934X_DDR1;
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
index 17af082..582c028 100644
--- a/arch/mips/mach-ath79/include/mach/ath79.h
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void)
 	return soc_is_tp9343() || soc_is_qca9561();
 }
 
+u32 ath79_get_bootstrap(void);
 int ath79_eth_reset(void);
 int ath79_usb_reset(void);
 
diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h
deleted file mode 100644
index c383bfe..0000000
--- a/arch/mips/mach-ath79/include/mach/reset.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_MACH_RESET_H
-#define __ASM_MACH_RESET_H
-
-#include <linux/types.h>
-
-u32 get_bootstrap(void);
-
-#endif /* __ASM_MACH_RESET_H */
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
index ef0a28e..533356c 100644
--- a/arch/mips/mach-ath79/qca953x/clk.c
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -17,7 +17,7 @@ static u32 qca953x_get_xtal(void)
 {
 	u32 val;
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
 		return 40000000;
 	else
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
index ac0130c..c6049d8 100644
--- a/arch/mips/mach-ath79/qca953x/ddr.c
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -10,7 +10,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -226,7 +226,7 @@ void ddr_init(void)
 
 	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 			   MAP_NOCACHE);
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & QCA953X_BOOTSTRAP_DDR1) {
 		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
 		udelay(10);
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index a88bcbc..33bf979 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -45,7 +45,7 @@ void _machine_restart(void)
 		/* NOP */;
 }
 
-u32 get_bootstrap(void)
+u32 ath79_get_bootstrap(void)
 {
 	void __iomem *base;
 	u32 reg = 0;
-- 
cgit v0.10.2


From 04583c686e61e6883158549603d60741ebf249fe Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 22:54:51 +0800
Subject: mips: ath79: ap121: Enable ethernet

This patch enable network function for ap121 board.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
index e31f601..a934a58 100644
--- a/arch/mips/dts/ap121.dts
+++ b/arch/mips/dts/ap121.dts
@@ -41,3 +41,8 @@
 		reg = <0>;
 	};
 };
+
+&gmac0 {
+	phy-mode = "rmii";
+	status = "okay";
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 00896b2..971f13e 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -75,7 +75,7 @@
 			};
 
 			gmac0: eth@0x19000000 {
-				compatible = "qca,ag7240-mac";
+				compatible = "qca,ag933x-mac";
 				reg = <0x19000000 0x200>;
 				phy = <&phy0>;
 				phy-mode = "rmii";
@@ -92,7 +92,7 @@
 			};
 
 			gmac1: eth@0x1a000000 {
-				compatible = "qca,ag7240-mac";
+				compatible = "qca,ag933x-mac";
 				reg = <0x1a000000 0x200>;
 				phy = <&phy0>;
 				phy-mode = "rgmii";
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
index d6c60fe..e245faa 100644
--- a/board/qca/ap121/ap121.c
+++ b/board/qca/ap121/ap121.c
@@ -10,6 +10,7 @@
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ddr.h>
+#include <mach/ath79.h>
 #include <debug_uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -46,5 +47,6 @@ int board_early_init_f(void)
 	debug_uart_init();
 #endif
 	ddr_init();
+	ath79_eth_reset();
 	return 0;
 }
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index 7604e2e..91fa734 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -19,8 +19,13 @@ CONFIG_SYS_PROMPT="ap121 # "
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_ATMEL=y
-- 
cgit v0.10.2


From ad5b48abfe7729d7e0eefcea8693d879af9915b7 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 22:54:52 +0800
Subject: mips: ath79: Use 8MB flash profile for mtd partition by default

Change bootm flash address and mtd partition table for 8MB flash profile.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index f069d50..b01031c 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -40,13 +40,13 @@
 					"rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND              "sf probe;" \
 					"mtdparts default;" \
-					"bootm 0x9f300000"
+					"bootm 0x9f650000"
 #define CONFIG_LZMA
 
 #define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
 #define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
 					"256k(u-boot),64k(u-boot-env)," \
-					"2752k(rootfs),896k(uImage)," \
+					"6144k(rootfs),1600k(uImage)," \
 					"64k(NVRAM),64k(ART)"
 
 #define CONFIG_ENV_SPI_MAX_HZ           25000000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index e45f743..0fa73a7 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -44,14 +44,14 @@
 					"rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND              "sf probe;" \
 					"mtdparts default;" \
-					"bootm 0x9f300000"
+					"bootm 0x9f680000"
 #define CONFIG_LZMA
 
 #define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
 #define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
 					"256k(u-boot),64k(u-boot-env)," \
-					"2752k(rootfs),896k(uImage)," \
-					"64k(NVRAM),64k(ART)"
+					"6336k(rootfs),1472k(uImage)," \
+					"64k(ART)"
 
 #define CONFIG_ENV_SPI_MAX_HZ           25000000
 #define CONFIG_ENV_IS_IN_SPI_FLASH
-- 
cgit v0.10.2


From cdeb68e292358f9dedeaea167f6eba894c58823e Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 22:54:53 +0800
Subject: mips: ath79: Add support for ungating USB and ethernet on qca953x

Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 33bf979..a5ee141 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
 	return 0;
 }
 
+static int eth_init_qca953x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+			 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+			 QCA953X_RESET_ETH_SWITCH_ANALOG |
+			 QCA953X_RESET_ETH_SWITCH;
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_eth_reset(void)
 {
 	/*
@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
 		return eth_init_ar933x();
 	if (soc_is_ar934x())
 		return eth_init_ar934x();
+	if (soc_is_qca953x())
+		return eth_init_qca953x();
 
 	return -EINVAL;
 }
@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
 	return 0;
 }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+
+	clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0xf00, 0x200);
+	mdelay(10);
+
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_usb_reset(void)
 {
 	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
 		return usb_reset_ar933x(reset_regs);
 	if (soc_is_ar934x())
 		return usb_reset_ar934x(reset_regs);
+	if (soc_is_qca953x())
+		return usb_reset_qca953x(reset_regs);
 
 	return -EINVAL;
 }
-- 
cgit v0.10.2


From ca09e66b04cd2b80f95d5acc1cc7f61487034faf Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 22:54:54 +0800
Subject: mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index dabcad0..7b48524 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -331,6 +331,7 @@
 #define AR933X_PLL_CPU_CONFIG_REG			0x00
 #define AR933X_PLL_CLK_CTRL_REG				0x08
 #define AR933X_PLL_DITHER_FRAC_REG			0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
 
 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT		10
 #define AR933X_PLL_CPU_CONFIG_NINT_MASK			0x3f
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index a5ee141..073a179 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -89,7 +89,7 @@ static int eth_init_ar933x(void)
 	mdelay(10);
 
 	/* Get Atheros S26 PHY out of reset. */
-	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+	clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
 			0x1f, 0x10);
 	mdelay(10);
 
-- 
cgit v0.10.2


From f1b65c98b0a134ce92c38141b917fd3a210ee535 Mon Sep 17 00:00:00 2001
From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 22:54:55 +0800
Subject: mips: ath79: ap143: Reset ethernet on boot

This patch reset the ethernet controller for ap143 board

Signed-off-by: Wills Wang <wills.wang@live.com>

diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
index 1572472..e921ea5 100644
--- a/board/qca/ap143/ap143.c
+++ b/board/qca/ap143/ap143.c
@@ -10,6 +10,7 @@
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ddr.h>
+#include <mach/ath79.h>
 #include <debug_uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -62,5 +63,6 @@ int board_early_init_f(void)
 	debug_uart_init();
 #endif
 	ddr_init();
+	ath79_eth_reset();
 	return 0;
 }
-- 
cgit v0.10.2


From 6f41751f4683aaf310b31b29c26e3da5f478dc07 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 31 May 2016 20:41:54 +0900
Subject: Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED()
 macro."

This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3.

Since commit 56adbb387273 ("image.h: Tighten up content using handy
CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
because the commit changed the logic of macros it touched.  Now,
IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
the boards.

As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
IS_ENABLED() as well) can only take a macro that is either defined
as 1 or undefined.  This is met for boolean options defined in
Kconfig.  On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
arch/*/include/asm/config.h .  This kind of clean-up is welcome,
but the options should be moved to Kconfig beforehand.

Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird.
It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or
IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT).  But, I see no define for
CONFIG_SPL_CRC32_SUPPORT anywhere.  Likewise for the other three.

The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were
also changed for SPL.  This can be a problem for boards defining
CONFIG_SPL_OF_LIBFDT.  I guess it should have been changed to
IS_ENABLED(CONFIG_OF_BOARD_SETUP).

In the first place, if we replace the references in C code,
the macros IMAGE_* will go away.

  if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) {
          ...
  }

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/image.h b/include/image.h
index 80a4454..a8f6bd1 100644
--- a/include/image.h
+++ b/include/image.h
@@ -52,15 +52,19 @@ struct lmb;
 #include <hash.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-# ifdef CONFIG_FIT_DISABLE_SHA256
-#  undef CONFIG_SHA256
-#  undef IMAGE_ENABLE_SHA256
-# endif
 # ifdef CONFIG_SPL_BUILD
-#  define IMAGE_ENABLE_CRC32	CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT)
-#  define IMAGE_ENABLE_MD5	CONFIG_IS_ENABLED(SPL_MD5_SUPPORT)
-#  define IMAGE_ENABLE_SHA1	CONFIG_IS_ENABLED(SPL_SHA1_SUPPORT)
-#  define IMAGE_ENABLE_SHA256	CONFIG_IS_ENABLED(SPL_SHA256_SUPPORT)
+#  ifdef CONFIG_SPL_CRC32_SUPPORT
+#   define IMAGE_ENABLE_CRC32	1
+#  endif
+#  ifdef CONFIG_SPL_MD5_SUPPORT
+#   define IMAGE_ENABLE_MD5	1
+#  endif
+#  ifdef CONFIG_SPL_SHA1_SUPPORT
+#   define IMAGE_ENABLE_SHA1	1
+#  endif
+#  ifdef CONFIG_SPL_SHA256_SUPPORT
+#   define IMAGE_ENABLE_SHA256	1
+#  endif
 # else
 #  define CONFIG_CRC32		/* FIT images need CRC32 support */
 #  define CONFIG_MD5		/* and MD5 */
@@ -71,12 +75,53 @@ struct lmb;
 #  define IMAGE_ENABLE_SHA1	1
 #  define IMAGE_ENABLE_SHA256	1
 # endif
+
+#ifdef CONFIG_FIT_DISABLE_SHA256
+#undef CONFIG_SHA256
+#undef IMAGE_ENABLE_SHA256
+#endif
+
+#ifndef IMAGE_ENABLE_CRC32
+#define IMAGE_ENABLE_CRC32	0
+#endif
+
+#ifndef IMAGE_ENABLE_MD5
+#define IMAGE_ENABLE_MD5	0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA1
+#define IMAGE_ENABLE_SHA1	0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA256
+#define IMAGE_ENABLE_SHA256	0
+#endif
+
 #endif /* IMAGE_ENABLE_FIT */
 
-#define IMAGE_ENABLE_RAMDISK_HIGH	CONFIG_IS_ENABLED(SYS_BOOT_RAMDISK_HIGH)
-#define IMAGE_BOOT_GET_CMDLINE		CONFIG_IS_ENABLED(SYS_BOOT_GET_CMDLINE)
-#define IMAGE_OF_BOARD_SETUP		CONFIG_IS_ENABLED(OF_BOARD_SETUP)
-#define IMAGE_OF_SYSTEM_SETUP		CONFIG_IS_ENABLED(OF_SYSTEM_SETUP)
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+# define IMAGE_ENABLE_RAMDISK_HIGH	1
+#else
+# define IMAGE_ENABLE_RAMDISK_HIGH	0
+#endif
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+# define IMAGE_BOOT_GET_CMDLINE		1
+#else
+# define IMAGE_BOOT_GET_CMDLINE		0
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+# define IMAGE_OF_BOARD_SETUP		1
+#else
+# define IMAGE_OF_BOARD_SETUP		0
+#endif
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+# define IMAGE_OF_SYSTEM_SETUP	1
+#else
+# define IMAGE_OF_SYSTEM_SETUP	0
+#endif
 
 /*
  * Operating System Codes
-- 
cgit v0.10.2


From 14070e69ad6d01abf65c06150dc9302bca1b7973 Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Tue, 31 May 2016 09:21:56 +0200
Subject: tools/env: allow to pass NULL for environment options

If users of the library are happy with the default, e.g. config file
name. They can pass NULL as the opts pointer. This simplifies the
transition of existing library users.
FIXES a compile error. since common_args has been removed by
a previous patch

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 52e0bec..692abda 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -35,6 +35,12 @@
 
 #include "fw_env.h"
 
+struct env_opts default_opts = {
+#ifdef CONFIG_FILE
+	.config_file = CONFIG_FILE
+#endif
+};
+
 #define DIV_ROUND_UP(n, d)	(((n) + (d) - 1) / (d))
 
 #define min(x, y) ({				\
@@ -229,6 +235,9 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 	char *env, *nxt;
 	int i, rc = 0;
 
+	if (!opts)
+		opts = &default_opts;
+
 	if (fw_env_open(opts))
 		return -1;
 
@@ -289,6 +298,9 @@ int fw_env_close(struct env_opts *opts)
 {
 	int ret;
 
+	if (!opts)
+		opts = &default_opts;
+
 	if (opts->aes_flag) {
 		ret = env_aes_cbc_crypt(environment.data, 1,
 					opts->aes_key);
@@ -452,6 +464,9 @@ int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 	char *value = NULL;
 	int valc;
 
+	if (!opts)
+		opts = &default_opts;
+
 	if (argc < 1) {
 		fprintf(stderr, "## Error: variable name missing\n");
 		errno = EINVAL;
@@ -524,6 +539,9 @@ int fw_parse_script(char *fname, struct env_opts *opts)
 	int len;
 	int ret = 0;
 
+	if (!opts)
+		opts = &default_opts;
+
 	if (fw_env_open(opts)) {
 		fprintf(stderr, "Error: environment not initialized\n");
 		return -1;
@@ -1139,6 +1157,9 @@ int fw_env_open(struct env_opts *opts)
 	struct env_image_single *single;
 	struct env_image_redundant *redundant;
 
+	if (!opts)
+		opts = &default_opts;
+
 	if (parse_config(opts))		/* should fill envdevices */
 		return -1;
 
@@ -1312,10 +1333,10 @@ static int parse_config(struct env_opts *opts)
 {
 	struct stat st;
 
-#if defined(CONFIG_FILE)
-	if (!common_args.config_file)
-		common_args.config_file = CONFIG_FILE;
+	if (!opts)
+		opts = &default_opts;
 
+#if defined(CONFIG_FILE)
 	/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
 	if (get_config(opts->config_file)) {
 		fprintf(stderr, "Cannot parse config file '%s': %m\n",
-- 
cgit v0.10.2


From 7698cdfddd1563bb7c625166a132f2d3c9526579 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:42 -0700
Subject: imx: ventana: config: add env vars for disk and part

In order to make the default boot scripts more flexible, use the variable
'disk' to specify the disk device number and the variable 'part' to specify
the partition number.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 874bb04..3aeb0df 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -281,6 +281,8 @@
 	\
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"disk=0\0" \
+	"part=1\0" \
 	\
 	"fdt_high=0xffffffff\0" \
 	"fdt_addr=0x18000000\0" \
@@ -304,8 +306,8 @@
 	"uimage=uImage\0" \
 	"mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
 	"mmc_boot=" \
-		"setenv fsload 'ext2load mmc 0:1'; " \
-		"mmc dev 0 && mmc rescan && " \
+		"setenv fsload \"ext2load mmc ${disk}:${part}\"; " \
+		"mmc dev ${disk} && mmc rescan && " \
 		"setenv dtype mmc; run loadscript; " \
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
@@ -319,7 +321,8 @@
 		"fi\0" \
 	\
 	"sata_boot=" \
-		"setenv fsload 'ext2load sata 0:1'; sata init && " \
+		"setenv fsload \"ext2load sata ${disk}:${part}\"; " \
+		"sata init && " \
 		"setenv dtype sata; run loadscript; " \
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
@@ -332,7 +335,8 @@
 			"fi; " \
 		"fi\0" \
 	"usb_boot=" \
-		"setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+		"setenv fsload \"ext2load usb ${disk}:${part}\"; " \
+		"usb start && usb dev ${disk} && " \
 		"setenv dtype usb; run loadscript; " \
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
-- 
cgit v0.10.2


From 4df0bff3ce5c37ac27faed1fe90bf0cc0a741750 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:43 -0700
Subject: imx: ventana: config: add fixfdt script to apply manual fdt fixups

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 3aeb0df..e57b120 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -287,14 +287,19 @@
 	"fdt_high=0xffffffff\0" \
 	"fdt_addr=0x18000000\0" \
 	"initrd_high=0xffffffff\0" \
+	"fixfdt=" \
+		"fdt addr ${fdt_addr}\0" \
 	"bootdir=boot\0" \
 	"loadfdt=" \
-		"if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
-			"echo Loaded DTB from ${bootdir}/${fdt_file}; " \
-		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
-			"echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
-		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
-			"echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
+		"if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
+			"echo Loaded DTB from boot/${fdt_file}; " \
+			"run fixfdt; " \
+		"elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
+			"echo Loaded DTB from boot/${fdt_file1}; " \
+			"run fixfdt; " \
+		"elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
+			"echo Loaded DTB from boot/${fdt_file2}; " \
+			"run fixfdt; " \
 		"fi\0" \
 	\
 	"script=6x_bootscript-ventana\0" \
@@ -313,7 +318,7 @@
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=/dev/mmcblk0p1 rootfstype=ext4 " \
 				"rootwait rw ${video} ${extra}; " \
-			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+			"if run loadfdt; then " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"bootm; " \
@@ -328,7 +333,7 @@
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=/dev/sda1 rootfstype=ext4 " \
 				"rootwait rw ${video} ${extra}; " \
-			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+			"if run loadfdt; then " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"bootm; " \
@@ -342,7 +347,7 @@
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=/dev/sda1 rootfstype=ext4 " \
 				"rootwait rw ${video} ${extra}; " \
-			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+			"if run loadfdt; then " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"bootm; " \
@@ -405,7 +410,7 @@
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
 				"root=${root} ${video} ${extra}; " \
-			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+			"if run loadfdt; then " \
 				"ubifsumount; " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
 			"else " \
-- 
cgit v0.10.2


From 1b7400011e62188734814df6b28e8d55f2bf752d Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:44 -0700
Subject: imx: ventana: config: use bootdir env var for directory of fdt files

In order to make the default boot scripts more flexible, use the variable
'bootdir' to specify the filesystem directory to look for fdt files in.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index e57b120..dff4303 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -291,14 +291,14 @@
 		"fdt addr ${fdt_addr}\0" \
 	"bootdir=boot\0" \
 	"loadfdt=" \
-		"if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
-			"echo Loaded DTB from boot/${fdt_file}; " \
+		"if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file}; " \
 			"run fixfdt; " \
-		"elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
-			"echo Loaded DTB from boot/${fdt_file1}; " \
+		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
 			"run fixfdt; " \
-		"elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
-			"echo Loaded DTB from boot/${fdt_file2}; " \
+		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
 			"run fixfdt; " \
 		"fi\0" \
 	\
-- 
cgit v0.10.2


From 543a4aba7fa88452e7749af5aad7e4b676901f57 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:45 -0700
Subject: imx: ventana: config: use fs env var for block dev filesystem type

In order to make the default boot scripts more flexible, use the variable
'fs' to specify the filesystem type to use for block storage devices
(USB/MMC/SATA) when loading files.

Additionally default this to ext4 and enable ext4 filesystem support
(which encompasses ext2 support) instead of just ext2 support.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index dff4303..fe81cbd 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -302,6 +302,7 @@
 			"run fixfdt; " \
 		"fi\0" \
 	\
+	"fs=ext4\0" \
 	"script=6x_bootscript-ventana\0" \
 	"loadscript=" \
 		"if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
@@ -309,14 +310,14 @@
 		"fi\0" \
 	\
 	"uimage=uImage\0" \
-	"mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+	"mmc_root=/dev/mmcblk0p1 rootfstype=${fs} rootwait rw\0" \
 	"mmc_boot=" \
-		"setenv fsload \"ext2load mmc ${disk}:${part}\"; " \
+		"setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
 		"mmc dev ${disk} && mmc rescan && " \
 		"setenv dtype mmc; run loadscript; " \
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
-				"root=/dev/mmcblk0p1 rootfstype=ext4 " \
+				"root=/dev/mmcblk0p1 rootfstype=${fs} " \
 				"rootwait rw ${video} ${extra}; " \
 			"if run loadfdt; then " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
@@ -326,12 +327,12 @@
 		"fi\0" \
 	\
 	"sata_boot=" \
-		"setenv fsload \"ext2load sata ${disk}:${part}\"; " \
+		"setenv fsload \"${fs}load sata ${disk}:${part}\"; " \
 		"sata init && " \
 		"setenv dtype sata; run loadscript; " \
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
-				"root=/dev/sda1 rootfstype=ext4 " \
+				"root=/dev/sda1 rootfstype=${fs} " \
 				"rootwait rw ${video} ${extra}; " \
 			"if run loadfdt; then " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
@@ -340,12 +341,12 @@
 			"fi; " \
 		"fi\0" \
 	"usb_boot=" \
-		"setenv fsload \"ext2load usb ${disk}:${part}\"; " \
+		"setenv fsload \"${fs}load usb ${disk}:${part}\"; " \
 		"usb start && usb dev ${disk} && " \
 		"setenv dtype usb; run loadscript; " \
 		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
 			"setenv bootargs console=${console},${baudrate} " \
-				"root=/dev/sda1 rootfstype=ext4 " \
+				"root=/dev/sda1 rootfstype=${fs} " \
 				"rootwait rw ${video} ${extra}; " \
 			"if run loadfdt; then " \
 				"bootm ${loadaddr} - ${fdt_addr}; " \
-- 
cgit v0.10.2


From 509870958dd18b18fd3d45dd69afb9c350964131 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:46 -0700
Subject: imx: ventana: config: use explicit addr in loadscript

If we are loading a script to ${loadaddr} then we need to use that address
explicitly when calling the source command in case user has changed loadaddr

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index fe81cbd..435ca0a 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -306,7 +306,7 @@
 	"script=6x_bootscript-ventana\0" \
 	"loadscript=" \
 		"if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
-			"source; " \
+			"source ${loadaddr}; " \
 		"fi\0" \
 	\
 	"uimage=uImage\0" \
-- 
cgit v0.10.2


From 899f589bcd3e0f97efa07b112f0d1d5c419b72b5 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:47 -0700
Subject: imx: ventana: config: add PREBOOT support

This allows the 'preboot' env variable to be executed prior to bootcmd
if defined.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 435ca0a..982ddba 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -201,6 +201,7 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_HWCONFIG
+#define CONFIG_PREBOOT
 
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-- 
cgit v0.10.2


From 1b99103fba8f75337d36701f05bb0f656d2ff729 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:48 -0700
Subject: imx: ventana: SPL: only disable boot watchdog if Falcon mode

If not booting Falcon mode, leave the boot watchdog enabled as a work-around
for other non-resolved bootloader hangs.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index ed42b86..c045d74 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -527,9 +527,6 @@ void board_init_f(ulong dummy)
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* disable boot watchdog */
-	gsc_boot_wd_disable();
 }
 
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
@@ -575,6 +572,9 @@ int spl_start_uboot(void)
 	i2c_set_bus_num(0);
 	gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 #endif
+	if (!ret)
+		gsc_boot_wd_disable();
+
 	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
 	return ret;
 }
-- 
cgit v0.10.2


From 6052b1c6f4fadee751dd7c90a4148943f65ab7b0 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:49 -0700
Subject: imx: ventana: SPL: added support for 32bit IMX6DQ 8Gb density DRAM
 config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index c045d74..e7f699a 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -190,6 +190,20 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
 	.trasmin = 3500,
 };
 
+/* MT41K512M16HA-125 (8Gb density) */
+static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
+	.mem_speed = 1600,
+	.density = 8,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 16,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
 /*
  * calibration - these are the various CPU/DDR3 combinations we support
  */
@@ -341,6 +355,19 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 	.p1_mpwrdlctl = 0X40304239,
 };
 
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x002A0025,
+	.p0_mpwldectrl1 = 0x003A002A,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x43430356,
+	.p0_mpdgctrl1 = 0x033C0335,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x4B373F42,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x303E3C36,
+};
+
 static void spl_dram_init(int width, int size_mb, int board_model)
 {
 	struct mx6_ddr3_cfg *mem = NULL;
@@ -420,6 +447,11 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 		else
 			calib = &mx6sdl_256x32_mmdc_calib;
 		debug("4gB density\n");
+	} else if (width == 32 && size_mb == 2048) {
+		mem = &mt41k512m16ha_125;
+		if (is_cpu_type(MXC_CPU_MX6Q))
+			calib = &mx6dq_512x32_mmdc_calib;
+		debug("8gB density\n");
 	} else if (width == 64 && size_mb == 512) {
 		mem = &mt41k64m16jt_125;
 		debug("1gB density\n");
-- 
cgit v0.10.2


From efa7ed7236ee5bfab871f35ce70f3e3e1d39b4f6 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:50 -0700
Subject: imx: ventana: gsc: add gsc sleep command

The Gateworks System Controller on Ventana boards has the ability to
disable the board's primary power supply until the RTC hits a specific
time. When sleeping a button-down event on the GSC user pushbutton will
wake the board before it's wake time has been reached. This feature is
referred to as GSC sleep.

Add a command to invoke sleep mode for a specified number of seconds.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 4f26bfd..2555824 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -160,6 +160,48 @@ int gsc_boot_wd_disable(void)
 }
 
 #ifdef CONFIG_CMD_GSC
+static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	unsigned char reg;
+	unsigned long secs = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	secs = simple_strtoul(argv[1], NULL, 10);
+	printf("GSC Sleeping for %ld seconds\n", secs);
+
+	i2c_set_bus_num(0);
+	reg = (secs >> 24) & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, &reg, 1))
+		goto error;
+	reg = (secs >> 16) & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, &reg, 1))
+		goto error;
+	reg = (secs >> 8) & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, &reg, 1))
+		goto error;
+	reg = secs & 0xff;
+	if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, &reg, 1))
+		goto error;
+	if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+		goto error;
+	reg |= (1 << 2);
+	if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+		goto error;
+	reg &= ~(1 << 2);
+	reg |= 0x3;
+	if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
+		goto error;
+
+	return CMD_RET_SUCCESS;
+
+error:
+	printf("i2c error\n");
+	return CMD_RET_FAILURE;
+}
+
 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	unsigned char reg;
@@ -206,13 +248,15 @@ static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	if (strcasecmp(argv[1], "wd") == 0)
 		return do_gsc_wd(cmdtp, flag, --argc, ++argv);
+	else if (strcasecmp(argv[1], "sleep") == 0)
+		return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
 
 	return CMD_RET_USAGE;
 }
 
 U_BOOT_CMD(
 	gsc, 4, 1, do_gsc, "GSC configuration",
-	"[wd enable [30|60]]|[wd disable]\n"
+	"[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
 	);
 
 #endif /* CONFIG_CMD_GSC */
-- 
cgit v0.10.2


From 82a17e75da0d812c2e583e733efd1e67e7488933 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:51 -0700
Subject: imx: ventana: gsc: fix negative temperature readings

The GSC Temperature sensor is a 2's complement value - adjust accordingly
for negative temperatures.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 2555824..c626ba2 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -71,6 +71,8 @@ static void read_hwmon(const char *name, uint reg, uint size)
 		puts("fRD\n");
 	} else {
 		ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+		if (reg == GSC_HWMON_TEMP && ui > 0x8000)
+			ui -= 0xffff;
 		if (ui == 0xffffff)
 			puts("invalid\n");
 		else
-- 
cgit v0.10.2


From ca628b74c97f3a6620e6f18aad5f917d51c2cdda Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:52 -0700
Subject: imx: ventana: gsc: show board temp on boot

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index c626ba2..042f55a 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -98,6 +98,12 @@ int gsc_info(int verbose)
 		gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
 			      &buf[GSC_SC_STATUS], 1);
 	}
+	if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
+		int ui = buf[0] | buf[1]<<8;
+		if (ui > 0x8000)
+			ui -= 0xffff;
+		printf(" board temp at %dC", ui / 10);
+	}
 	puts("\n");
 	if (!verbose)
 		return CMD_RET_SUCCESS;
-- 
cgit v0.10.2


From 78532623303e089e7d36b3a11d293e618b927655 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:53 -0700
Subject: imx: ventana: export backlight gpio after gpio driver is available

Calling request_gpio to register bklt_gpio with the GPIO driver had no effect
in setup_display called from early board init (although pinmuxing it and
configuring it as output-low does do what it should). Therefore move the
request_gpio later in enable_lvds so that its registered for use by the
gpio command if LVDS is actually enabled.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 3b7c82b..7a3d96a 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -317,6 +317,8 @@ static void enable_lvds(struct display_info_t const *dev)
 	writel(reg, &iomux->gpr[2]);
 
 	/* Enable Backlight */
+	gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+	gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 	gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 	SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 	gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
@@ -456,8 +458,7 @@ static void setup_display(void)
 	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 	writel(reg, &iomux->gpr[3]);
 
-	/* Backlight CABEN on LVDS connector */
-	gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+	/* LVDS Backlight GPIO on LVDS connector - output low */
 	SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 	gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 }
-- 
cgit v0.10.2


From 83e00f193e766337254c490c2b28118b75cc575a Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:54 -0700
Subject: imx: ventana: fix invalid dio configuration for pwm mode

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index a20190e..7610381 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -760,7 +760,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 					       ctrl);
 			gpio_requestf(cfg->gpio_param, "dio%d", i);
 			gpio_direction_input(cfg->gpio_param);
-		} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+		} else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
 			   cfg->pwm_padmux) {
 			if (!quiet)
 				printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
-- 
cgit v0.10.2


From f17a9af84645f5b820da2e7d017b014923ce1b88 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:55 -0700
Subject: imx: ventana: enable pwm device-tree property based on hwconfig

Most Ventana boards have a connector with off-board digital-I/O signals
including some that can be pinmuxed as either a PWM or a GPIO. The hwconfig
env variable is used to configure these and they will be pinmuxed according
to this configuration in the bootloader.

This patch adds a device-tree fixup that will enable the pwm controller
nodes appropriately for digital-I/O's that are configured as pwm via hwconfig
so that the pin can be used with the Linux kernel /sys/class/pwm API.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 7610381..44ee73f 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -762,6 +762,11 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 			gpio_direction_input(cfg->gpio_param);
 		} else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
 			   cfg->pwm_padmux) {
+			if (!cfg->pwm_param) {
+				printf("DIO%d:  Error: pwm config invalid\n",
+					i);
+				continue;
+			}
 			if (!quiet)
 				printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
 			imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 7a3d96a..feb2df8 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -21,6 +21,7 @@
 #include <asm/io.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
+#include <hwconfig.h>
 #include <i2c.h>
 #include <fdt_support.h>
 #include <fsl_esdhc.h>
@@ -777,6 +778,16 @@ static int ft_sethdmiinfmt(void *blob, char *mode)
 	return 0;
 }
 
+/* enable a property of a node if the node is found */
+static inline void ft_enable_path(void *blob, const char *path)
+{
+	int i = fdt_path_offset(blob, path);
+	if (i >= 0) {
+		debug("enabling %s\n", path);
+		fdt_status_okay(blob, i);
+	}
+}
+
 /*
  * called prior to booting kernel or by 'fdt boardsetup' command
  *
@@ -920,6 +931,25 @@ int ft_board_setup(void *blob, bd_t *bd)
 		ft_sethdmiinfmt(blob, "yuv422bt656");
 	}
 
+	/* Configure DIO */
+	for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
+		struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
+		char arg[10];
+
+		sprintf(arg, "dio%d", i);
+		if (!hwconfig(arg))
+			continue;
+		if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
+		{
+			char path[48];
+			sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
+				0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
+			printf("   Enabling pwm%d for DIO%d\n",
+			       cfg->pwm_param, i);
+			ft_enable_path(blob, path);
+		}
+	}
+
 	/*
 	 * Peripheral Config:
 	 *  remove nodes by alias path if EEPROM config tells us the
-- 
cgit v0.10.2


From 5c55572ff70d71b707e68b0fb811de27814626c0 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:56 -0700
Subject: imx: ventana: remove dependence on EECONFIG_SATA eeprom feature bit

The MSATA feature is a board-specific feature on Gateworks Ventana boards.

In most cases a 2:1 mux will steer either PCIe or SATA to a miniPCIe socket
through an MSATA_EN gpio. In these such cases assign the gpio in the board
specific struct and use its presence to determine if we default the GPIO to
PCIe and if we later steer it according to hwconfig.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 44ee73f..5a8bacd 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -132,8 +132,6 @@ void setup_ventana_i2c(void)
 
 /* common to add baseboards */
 static iomux_v3_cfg_t const gw_gpio_pads[] = {
-	/* MSATA_EN */
-	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* RS232_EN# */
 	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 };
@@ -183,6 +181,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* PANLEDG# */
 	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 	/* PANLEDR# */
@@ -212,6 +212,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* CAN_STBY */
 	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 	/* USB_HUBRST# */
@@ -241,6 +243,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* CAN_STBY */
 	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 	/* PANLEDG# */
@@ -283,6 +287,8 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+	/* MSATA_EN */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* USBOTG_SEL */
 	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
 	/* USB_HUBRST# */
@@ -445,6 +451,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.vidin_en = IMX_GPIO_NR(3, 31),
 		.usb_sel = IMX_GPIO_NR(1, 2),
 		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
 	},
 
 	/* GW53xx */
@@ -489,6 +496,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.gps_shdn = IMX_GPIO_NR(1, 27),
 		.vidin_en = IMX_GPIO_NR(3, 31),
 		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
 	},
 
 	/* GW54xx */
@@ -535,6 +543,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.dioi2c_en = IMX_GPIO_NR(4,  5),
 		.pcie_sson = IMX_GPIO_NR(1, 20),
 		.wdis = IMX_GPIO_NR(5, 17),
+		.msata_en = GP_MSATA_SEL,
 	},
 
 	/* GW551x */
@@ -602,6 +611,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.pcie_rst = IMX_GPIO_NR(1, 29),
 		.usb_sel = IMX_GPIO_NR(1, 7),
 		.wdis = IMX_GPIO_NR(7, 12),
+		.msata_en = GP_MSATA_SEL,
 	},
 };
 
@@ -616,10 +626,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 	gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
 	gpio_direction_output(GP_USB_OTG_PWR, 0);
 
-	/* MSATA Enable - default to PCI */
-	gpio_request(GP_MSATA_SEL, "msata_en");
-	gpio_direction_output(GP_MSATA_SEL, 0);
-
 	/* RS232_EN# */
 	gpio_request(GP_RS232_EN, "rs232_en");
 	gpio_direction_output(GP_RS232_EN, 0);
@@ -649,6 +655,12 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 		}
 	}
 
+	/* MSATA Enable - default to PCI */
+	if (gpio_cfg[board].msata_en) {
+		gpio_request(gpio_cfg[board].msata_en, "msata_en");
+		gpio_direction_output(gpio_cfg[board].msata_en, 0);
+	}
+
 	/* Expansion Mezzanine IO */
 	if (gpio_cfg[board].mezz_pwren) {
 		gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
@@ -718,10 +730,9 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 	gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 
 	/* MSATA Enable */
-	if (is_cpu_type(MXC_CPU_MX6Q) &&
-	    test_bit(EECONFIG_SATA, info->config)) {
+	if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
 		gpio_direction_output(GP_MSATA_SEL,
-				      (hwconfig("msata")) ?  1 : 0);
+				      (hwconfig("msata")) ? 1 : 0);
 	}
 
 	/* USBOTG Select (PCISKT or FrontPanel) */
@@ -775,8 +786,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 	}
 
 	if (!quiet) {
-		if (is_cpu_type(MXC_CPU_MX6Q) &&
-		    (test_bit(EECONFIG_SATA, info->config))) {
+		if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
 			printf("MSATA: %s\n", (hwconfig("msata") ?
 			       "enabled" : "disabled"));
 		}
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 28f5816..58ad5ff 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -76,6 +76,7 @@ struct ventana {
 	int pcie_sson;
 	int usb_sel;
 	int wdis;
+	int msata_en;
 };
 
 extern struct ventana gpio_cfg[GW_UNKNOWN];
-- 
cgit v0.10.2


From fe63fcb6cafc1d5597b747dd673bf092f116b6d6 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:57 -0700
Subject: imx: ventana: remove several EEPROM config bit dependence

Removed several EEPROM bit dependencies:
 - for dt aliases that don't exist and thus don't ever do anything
   (pcie,lvds1,uart*,vpu,csi*,hdmi_in,hdmi_out,cvbs_in,cvbs_out,gps)
 - for features that don't effect bus ordering or have no detrimental affect
   if erroneously enabled when not present (ahci,nand,i2c*)
 - for features that have little to no impact on being erroneously enabled
   but high impact if erroneously disabled (can*, spi*)
 - for features that have an high adverse affect of not being set when they
   should and no adverse affect of being set when they
   shouldn't (ipu*).

Removing these means the following:
 - these no longer are supported with the econfig command
 - these no longer affect the device-tree in any way

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index ba15969..e86c98e 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -100,43 +100,12 @@ read_eeprom(int bus, struct ventana_board_info *info)
 /* list of config bits that the bootloader will remove from dtb if not set */
 struct ventana_eeprom_config econfig[] = {
 	{ "eth0", "ethernet0", EECONFIG_ETH0 },
-	{ "eth1", "ethernet1", EECONFIG_ETH1 },
-	{ "sata", "ahci0", EECONFIG_SATA },
-	{ "pcie", NULL, EECONFIG_PCIE},
-	{ "lvds0", NULL, EECONFIG_LVDS0 },
-	{ "lvds1", NULL, EECONFIG_LVDS1 },
 	{ "usb0", NULL, EECONFIG_USB0 },
 	{ "usb1", NULL, EECONFIG_USB1 },
 	{ "mmc0", NULL, EECONFIG_SD0 },
 	{ "mmc1", NULL, EECONFIG_SD1 },
 	{ "mmc2", NULL, EECONFIG_SD2 },
 	{ "mmc3", NULL, EECONFIG_SD3 },
-	{ "uart0", NULL, EECONFIG_UART0 },
-	{ "uart1", NULL, EECONFIG_UART1 },
-	{ "uart2", NULL, EECONFIG_UART2 },
-	{ "uart3", NULL, EECONFIG_UART3 },
-	{ "uart4", NULL, EECONFIG_UART4 },
-	{ "ipu0", NULL, EECONFIG_IPU0 },
-	{ "ipu1", NULL, EECONFIG_IPU1 },
-	{ "can0", NULL, EECONFIG_FLEXCAN },
-	{ "i2c0", NULL, EECONFIG_I2C0 },
-	{ "i2c1", NULL, EECONFIG_I2C1 },
-	{ "i2c2", NULL, EECONFIG_I2C2 },
-	{ "vpu", NULL, EECONFIG_VPU },
-	{ "csi0", NULL, EECONFIG_CSI0 },
-	{ "csi1", NULL, EECONFIG_CSI1 },
-	{ "spi0", NULL, EECONFIG_ESPCI0 },
-	{ "spi1", NULL, EECONFIG_ESPCI1 },
-	{ "spi2", NULL, EECONFIG_ESPCI2 },
-	{ "spi3", NULL, EECONFIG_ESPCI3 },
-	{ "spi4", NULL, EECONFIG_ESPCI4 },
-	{ "spi5", NULL, EECONFIG_ESPCI5 },
-	{ "gps", "pps", EECONFIG_GPS },
-	{ "hdmi_in", NULL, EECONFIG_HDMI_IN },
-	{ "hdmi_out", NULL, EECONFIG_HDMI_OUT },
-	{ "cvbs_in", NULL, EECONFIG_VID_IN },
-	{ "cvbs_out", NULL, EECONFIG_VID_OUT },
-	{ "nand", NULL, EECONFIG_NAND },
 	{ /* Sentinel */ }
 };
 
-- 
cgit v0.10.2


From 385575bcb6013e8151fd98d80b8dc2b5bd732cfb Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:58 -0700
Subject: imx: ventana: add GW553x support

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 5a8bacd..2c3ac93 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -316,6 +316,20 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 };
 
+static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
+
+	/* VID_PWR */
+	IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
 
 /*
  * Board Specific GPIO
@@ -613,6 +627,46 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.wdis = IMX_GPIO_NR(7, 12),
 		.msata_en = GP_MSATA_SEL,
 	},
+
+	/* GW553x */
+	{
+		.gpio_pads = gw553x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
+		.dio_cfg = {
+			{
+				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+				IMX_GPIO_NR(1, 16),
+				{ 0, 0 },
+				0
+			},
+			{
+				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+				IMX_GPIO_NR(1, 19),
+				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+				2
+			},
+			{
+				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+				IMX_GPIO_NR(1, 17),
+				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+				3
+			},
+			{
+				{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+				IMX_GPIO_NR(1, 18),
+				{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+				4
+			},
+		},
+		.num_gpios = 4,
+		.leds = {
+			IMX_GPIO_NR(4, 10),
+			IMX_GPIO_NR(4, 11),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.vidin_en = IMX_GPIO_NR(5, 20),
+		.wdis = IMX_GPIO_NR(7, 12),
+	},
 };
 
 void setup_iomux_gpio(int board, struct ventana_board_info *info)
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index e86c98e..1382e5d 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -87,6 +87,9 @@ read_eeprom(int bus, struct ventana_board_info *info)
 		} else if (info->model[4] == '2') {
 			type = GW552x;
 			break;
+		} else if (info->model[4] == '3') {
+			type = GW553x;
+			break;
 		}
 		/* fall through */
 	default:
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 042f55a..2ca6d5c 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -117,7 +117,8 @@ int gsc_info(int verbose)
 	read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
 	read_hwmon("VDD_DDR",  GSC_HWMON_VDD_DDR, 3);
 	read_hwmon("VDD_5P0",  GSC_HWMON_VDD_5P0, 3);
-	read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
+	if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
+		read_hwmon("VDD_2P5",  GSC_HWMON_VDD_2P5, 3);
 	read_hwmon("VDD_1P8",  GSC_HWMON_VDD_1P8, 3);
 	read_hwmon("VDD_IO2",  GSC_HWMON_VDD_IO2, 3);
 	switch (ventana_info.model[3]) {
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index feb2df8..15e4bf1 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -267,7 +267,9 @@ int board_phy_config(struct phy_device *phydev)
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FEC_MXC
-	if (board_type != GW551x && board_type != GW552x) {
+	struct ventana_board_info *info = &ventana_info;
+
+	if (test_bit(EECONFIG_ETH0, info->config)) {
 		setup_iomux_enet(GP_PHY_RST);
 		cpu_eth_init(bis);
 	}
@@ -699,7 +701,9 @@ int misc_init_r(void)
 			setenv("model_base", str);
 			sprintf(fdt, "%s-%s.dtb", cputype, str);
 			setenv("fdt_file1", fdt);
-			if (board_type != GW551x && board_type != GW552x)
+			if (board_type != GW551x &&
+			    board_type != GW552x &&
+			    board_type != GW553x)
 				str[4] = 'x';
 			str[5] = 'x';
 			str[6] = 0;
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index daff375..9ffad58 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -111,6 +111,7 @@ enum {
 	GW54xx,
 	GW551x,
 	GW552x,
+	GW553x,
 	GW_UNKNOWN,
 	GW_BADCRC,
 };
-- 
cgit v0.10.2


From 34b080b79ccb59e144619179b4cd57a2f146f8d3 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 11:03:59 -0700
Subject: imx: ventana: add fdt fixup to enable UHS-I support on selected
 boards

UHS-I support is available on Ventana boards with micro-SD sockets depending
on the board revision. For backwards compatibility to not break users
who have old bootloaders and newer kernels the device-tree on boards with
microSD disables UHS-I support by default by defining the no-1-8-v property
in the esdhc controller node. For models/revisions that support switchable
1.8V/3.3V I/O which is detectable by the presence of a pull-down on the
SD3_VSELECT pin we remove that property to enable support in the kernel.

Additionally we add SD3_VSELECT to the pinmux for clarity (even though U-Boot
does not currently support UHS-I modes requiring 1.8V I/O).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 2c3ac93..929dde9 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -134,6 +134,8 @@ void setup_ventana_i2c(void)
 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 	/* RS232_EN# */
 	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 };
 
 /* prototype */
@@ -766,6 +768,11 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 		gpio_request(gpio_cfg[board].wdis, "wlan_dis");
 		gpio_direction_output(gpio_cfg[board].wdis, 1);
 	}
+
+	/* sense vselect pin to see if we support uhs-i */
+	gpio_request(GP_SD3_VSELECT, "sd3_vselect");
+	gpio_direction_input(GP_SD3_VSELECT);
+	gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
 }
 
 /* setup GPIO pinmux and default configuration per baseboard and env */
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 58ad5ff..d037767 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -17,6 +17,7 @@
 #define GP_SD3_CD	IMX_GPIO_NR(7, 0)
 #define GP_RS232_EN	IMX_GPIO_NR(2, 11)
 #define GP_MSATA_SEL	IMX_GPIO_NR(2, 8)
+#define GP_SD3_VSELECT	IMX_GPIO_NR(6, 14)
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
@@ -77,6 +78,7 @@ struct ventana {
 	int usb_sel;
 	int wdis;
 	int msata_en;
+	bool usd_vsel;
 };
 
 extern struct ventana gpio_cfg[GW_UNKNOWN];
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 15e4bf1..82313e8 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -60,8 +60,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	/* CD */
-	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 };
 
 /* ENET */
@@ -792,6 +791,17 @@ static inline void ft_enable_path(void *blob, const char *path)
 	}
 }
 
+/* remove a property of a node if the node is found */
+static inline void ft_delprop_path(void *blob, const char *path,
+				   const char *name)
+{
+	int i = fdt_path_offset(blob, path);
+	if (i) {
+		debug("removing %s/%s\n", path, name);
+		fdt_delprop(blob, i, name);
+	}
+}
+
 /*
  * called prior to booting kernel or by 'fdt boardsetup' command
  *
@@ -895,6 +905,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 				range[1] = cpu_to_fdt32(23);
 			}
 		}
+
+		/* these have broken usd_vsel */
+		if (strstr((const char *)info->model, "SP318-B") ||
+		    strstr((const char *)info->model, "SP331-B"))
+			gpio_cfg[board_type].usd_vsel = 0;
 	}
 
 	/*
@@ -954,6 +969,13 @@ int ft_board_setup(void *blob, bd_t *bd)
 		}
 	}
 
+	/* remove no-1-8-v if UHS-I support is present */
+	if (gpio_cfg[board_type].usd_vsel) {
+		debug("Enabling UHS-I support\n");
+		ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
+				"no-1-8-v");
+	}
+
 	/*
 	 * Peripheral Config:
 	 *  remove nodes by alias path if EEPROM config tells us the
-- 
cgit v0.10.2


From 73f366bb5bec7c728dcfed51110818fa412dd878 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Tue, 24 May 2016 20:28:47 +0800
Subject: imx: mx6qsabreauto: drop duplicated net phy configuration

In 'commit d584c68ce0f5bf2f430ccfb2ba00bd506206fb91',
ar8031 is changed to use ar8035_config. ar8035_config
actually does the same thing as mx6_rgmii_rework, so
drop mx6_rgmii_rework and board_phy_config.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 0712f08..d63a979 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -321,39 +321,6 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	unsigned short val;
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	val |= 0x0100;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 static void setup_fec(void)
 {
 	if (is_mx6dqp()) {
-- 
cgit v0.10.2


From cb82c38eff193d6b0685e26020109ca5cac9f0ea Mon Sep 17 00:00:00 2001
From: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Date: Fri, 20 May 2016 14:19:52 -0400
Subject: cosmetic: mx6slevk: Minor coding-style fix

Fix the brace indentation in board_mmc_init().

Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index f1915a8..256d602 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -230,14 +230,14 @@ int board_mmc_init(bd_t *bis)
 			printf("Warning: you configured more USDHC controllers"
 				"(%d) than supported by the board\n", i + 1);
 			return -EINVAL;
-			}
-
-			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-			if (ret) {
-				printf("Warning: failed to initialize "
-					"mmc dev %d\n", i);
-				return ret;
-			}
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize "
+				"mmc dev %d\n", i);
+			return ret;
+		}
 	}
 
 	return 0;
-- 
cgit v0.10.2


From 9f8fa184fc1acb6fe8e15e3bbbfcb916e6bc4cc1 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Thu, 19 May 2016 13:02:16 +0800
Subject: imx: mx7: implement reset_misc

We need to power down lcdif to make 'reset' can pass stress test.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 073bbc6..ef46c92 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -441,3 +441,11 @@ void s_init(void)
 
 	return;
 }
+
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+	lcdif_power_down();
+#endif
+}
+
-- 
cgit v0.10.2


From 01a97a11db75c1a006da7b40d8ba4a325f05960c Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:07:39 -0600
Subject: ARM: tegra: use DT bindings for GPIO naming

There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index daf5698..db60864 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -6,6 +6,8 @@
 #ifndef _TEGRA_GPIO_H_
 #define _TEGRA_GPIO_H_
 
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #define TEGRA_GPIOS_PER_PORT	8
 #define TEGRA_PORTS_PER_BANK	4
 #define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
index 1a6dcb8..ba748a5 100644
--- a/arch/arm/include/asm/arch-tegra124/gpio.h
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -41,263 +41,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,
-	GPIO_PFF0,	/* pin 248 */
-	GPIO_PFF1,
-	GPIO_PFF2,
-	GPIO_PFF3,
-	GPIO_PFF4,
-	GPIO_PFF5,
-	GPIO_PFF6,
-	GPIO_PFF7,	/* pin 255 */
-};
-
 #endif	/* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
index b40b1ff..af301e7 100644
--- a/arch/arm/include/asm/arch-tegra20/gpio.h
+++ b/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -33,231 +33,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,	/* pin 223 */
-};
-
 #endif	/* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
index 71af423..389d5b6 100644
--- a/arch/arm/include/asm/arch-tegra210/gpio.h
+++ b/arch/arm/include/asm/arch-tegra210/gpio.h
@@ -41,263 +41,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,
-	GPIO_PFF0,	/* pin 248 */
-	GPIO_PFF1,
-	GPIO_PFF2,
-	GPIO_PFF3,
-	GPIO_PFF4,
-	GPIO_PFF5,
-	GPIO_PFF6,
-	GPIO_PFF7,	/* pin 255 */
-};
-
 #endif	/* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
index d2c6c78..e384327 100644
--- a/arch/arm/include/asm/arch-tegra30/gpio.h
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -40,255 +40,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,	/* pin 247 */
-};
-
 #endif	/* _TEGRA30_GPIO_H_ */
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
index 1704627..106be9b 100644
--- a/board/avionic-design/common/tamonten-ng.c
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -42,12 +42,12 @@ void pinmux_init(void)
 void gpio_early_init(void)
 {
 	/* Turn on the alive signal */
-	gpio_request(GPIO_PV2, "ALIVE");
-	gpio_direction_output(GPIO_PV2, 1);
+	gpio_request(TEGRA_GPIO(V, 2), "ALIVE");
+	gpio_direction_output(TEGRA_GPIO(V, 2), 1);
 
 	/* Remove the reset on the external periph */
-	gpio_request(GPIO_PI4, "nRST_PERIPH");
-	gpio_direction_output(GPIO_PI4, 1);
+	gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH");
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
 }
 
 void pmu_write(uchar reg, uchar data)
@@ -73,8 +73,8 @@ void board_sdmmc_voltage_init(void)
 	pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
 
 	/* Switch the power on */
-	gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
-	gpio_direction_output(GPIO_PJ2, 1);
+	gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC");
+	gpio_direction_output(TEGRA_GPIO(J, 2), 1);
 }
 
 /*
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 9c86779..4fb36a2 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -23,8 +23,8 @@
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)
 {
-	gpio_request(GPIO_PI4, NULL);
-	gpio_direction_output(GPIO_PI4, 1);
+	gpio_request(TEGRA_GPIO(I, 4), NULL);
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
 }
 #endif
 
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index ba15e2e..f04f843 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -110,11 +110,11 @@ int tegra_pcie_board_init(void)
 	}
 
 	/* GPIO: PEX = 3.3V */
-	err = gpio_request(GPIO_PL7, "PEX");
+	err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
 	if (err < 0)
 		return err;
 
-	gpio_direction_output(GPIO_PL7, 1);
+	gpio_direction_output(TEGRA_GPIO(L, 7), 1);
 
 	/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
 	data[0] = 0x15;
diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
index 7eb1e6c..7955ca5 100644
--- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
+++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
@@ -15,71 +15,71 @@
 #ifndef _PINMUX_CONFIG_E2220_1170_H_
 #define _PINMUX_CONFIG_E2220_1170_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(A6,   IN),
-	GPIO_INIT(B4,   IN),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(G2,   OUT0),
-	GPIO_INIT(G3,   OUT0),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H1,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   OUT0),
-	GPIO_INIT(H7,   OUT0),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I3,   OUT0),
-	GPIO_INIT(K0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   OUT0),
-	GPIO_INIT(K3,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   OUT0),
-	GPIO_INIT(L0,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V3,   IN),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y0,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(BB4,  IN),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC5,  OUT0),
-	GPIO_INIT(CC6,  IN),
-	GPIO_INIT(CC7,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(A,    6,   IN),
+	GPIO_INIT(B,    4,   IN),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(G,    2,   OUT0),
+	GPIO_INIT(G,    3,   OUT0),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    1,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   OUT0),
+	GPIO_INIT(H,    7,   OUT0),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    3,   OUT0),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   OUT0),
+	GPIO_INIT(K,    3,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   OUT0),
+	GPIO_INIT(L,    0,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    3,   IN),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    0,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   4,   IN),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   5,   OUT0),
+	GPIO_INIT(CC,   6,   IN),
+	GPIO_INIT(CC,   7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index 00e0cdc..01237db 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -15,63 +15,63 @@
 #ifndef _PINMUX_CONFIG_JETSON_TK1_H_
 #define _PINMUX_CONFIG_JETSON_TK1_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(G4,   IN),
-	GPIO_INIT(H2,   OUT0),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H7,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(O1,   IN),
-	GPIO_INIT(O4,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q5,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R2,   OUT0),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(R7,   IN),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U0,   IN),
-	GPIO_INIT(U1,   IN),
-	GPIO_INIT(U2,   IN),
-	GPIO_INIT(U3,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(V1,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(BB5,  OUT0),
-	GPIO_INIT(BB6,  OUT0),
-	GPIO_INIT(BB7,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC2,  IN),
-	GPIO_INIT(EE2,  OUT1),
+	/*        port, pin, init_val */
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(G,    4,   IN),
+	GPIO_INIT(H,    2,   OUT0),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    1,   IN),
+	GPIO_INIT(O,    4,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    5,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    2,   OUT0),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    0,   IN),
+	GPIO_INIT(U,    1,   IN),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   5,   OUT0),
+	GPIO_INIT(BB,   6,   OUT0),
+	GPIO_INIT(BB,   7,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   2,   IN),
+	GPIO_INIT(EE,   2,   OUT1),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ba96401..8f68ae9 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -36,8 +36,9 @@ void pinmux_init(void)
 
 int tegra_board_id(void)
 {
-	static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
-					GPIO_PX4, -1};
+	static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+					TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+					-1};
 
 	gpio_claim_vector(vector, "board_id%d");
 	return gpio_get_values_as_int(vector);
diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
index dca0171..fd7f1d1 100644
--- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h
+++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
@@ -15,59 +15,59 @@
 #ifndef _PINMUX_CONFIG_NYAN_BIG_H_
 #define _PINMUX_CONFIG_NYAN_BIG_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(C7,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   OUT1),
-	GPIO_INIT(I0,   IN),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I5,   OUT1),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(I7,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(J7,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q2,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q6,   IN),
-	GPIO_INIT(Q7,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R1,   IN),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(R7,   IN),
-	GPIO_INIT(S3,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(W3,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(I,    7,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
index 35706b4..24acbcc 100644
--- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
+++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
@@ -15,62 +15,62 @@
 #ifndef _PINMUX_CONFIG_P2371_0000_H_
 #define _PINMUX_CONFIG_P2371_0000_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(E4,   OUT0),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G3,   OUT0),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   OUT0),
-	GPIO_INIT(H7,   OUT0),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I3,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   OUT0),
-	GPIO_INIT(L0,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(V7,   OUT1),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC6,  IN),
-	GPIO_INIT(CC7,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(E,    4,   OUT0),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    3,   OUT0),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   OUT0),
+	GPIO_INIT(H,    7,   OUT0),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    3,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   OUT0),
+	GPIO_INIT(L,    0,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(V,    7,   OUT1),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   6,   IN),
+	GPIO_INIT(CC,   7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
index d5be6ec..601728e 100644
--- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
+++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
@@ -15,73 +15,73 @@
 #ifndef _PINMUX_CONFIG_P2371_2180_H_
 #define _PINMUX_CONFIG_P2371_2180_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(B0,   IN),
-	GPIO_INIT(B1,   IN),
-	GPIO_INIT(B2,   IN),
-	GPIO_INIT(B3,   IN),
-	GPIO_INIT(C0,   IN),
-	GPIO_INIT(C1,   IN),
-	GPIO_INIT(C2,   IN),
-	GPIO_INIT(C3,   IN),
-	GPIO_INIT(C4,   IN),
-	GPIO_INIT(E4,   IN),
-	GPIO_INIT(E5,   IN),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H1,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(L1,   IN),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(U2,   IN),
-	GPIO_INIT(U3,   IN),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V3,   IN),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y0,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z2,   IN),
-	GPIO_INIT(Z3,   OUT0),
-	GPIO_INIT(BB0,  IN),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  IN),
-	GPIO_INIT(CC1,  IN),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(B,    0,   IN),
+	GPIO_INIT(B,    1,   IN),
+	GPIO_INIT(B,    2,   IN),
+	GPIO_INIT(B,    3,   IN),
+	GPIO_INIT(C,    0,   IN),
+	GPIO_INIT(C,    1,   IN),
+	GPIO_INIT(C,    2,   IN),
+	GPIO_INIT(C,    3,   IN),
+	GPIO_INIT(C,    4,   IN),
+	GPIO_INIT(E,    4,   IN),
+	GPIO_INIT(E,    5,   IN),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    1,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(L,    1,   IN),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    3,   IN),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    0,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    2,   IN),
+	GPIO_INIT(Z,    3,   OUT0),
+	GPIO_INIT(BB,   0,   IN),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   IN),
+	GPIO_INIT(CC,   1,   IN),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index d80a7d0..7ce656f 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -58,6 +58,6 @@ void pinmux_init(void)
 void start_cpu_fan(void)
 {
 	/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
-	gpio_request(GPIO_PE4, "FAN_VDD");
-	gpio_direction_output(GPIO_PE4, 1);
+	gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
+	gpio_direction_output(TEGRA_GPIO(E, 4), 1);
 }
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
index d323301..dd4228f 100644
--- a/board/nvidia/p2571/pinmux-config-p2571.h
+++ b/board/nvidia/p2571/pinmux-config-p2571.h
@@ -15,37 +15,37 @@
 #ifndef _PINMUX_CONFIG_P2571_H_
 #define _PINMUX_CONFIG_P2571_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2571_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(D4,   IN),
-	GPIO_INIT(E4,   OUT0),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V6,   OUT1),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC3,  IN),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(D,    4,   IN),
+	GPIO_INIT(E,    4,   OUT0),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    6,   OUT1),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   3,   IN),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 2d07001..fc9c1c9 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,8 +20,8 @@
 void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-	gpio_request(GPIO_PI3, "uart_en");
-	gpio_direction_output(GPIO_PI3, 0);
+	gpio_request(TEGRA_GPIO(I, 3), "uart_en");
+	gpio_direction_output(TEGRA_GPIO(I, 3), 0);
 }
 #endif
 
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
index fb444b3..59d53ef 100644
--- a/board/nvidia/venice2/pinmux-config-venice2.h
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -15,70 +15,70 @@
 #ifndef _PINMUX_CONFIG_VENICE2_H_
 #define _PINMUX_CONFIG_VENICE2_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config venice2_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(C7,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H5,   OUT0),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   OUT1),
-	GPIO_INIT(I0,   IN),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I4,   OUT0),
-	GPIO_INIT(I5,   OUT1),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(J7,   IN),
-	GPIO_INIT(K0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K3,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(O2,   IN),
-	GPIO_INIT(O5,   IN),
-	GPIO_INIT(O6,   OUT0),
-	GPIO_INIT(O7,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q2,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q6,   IN),
-	GPIO_INIT(Q7,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R1,   IN),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(S0,   IN),
-	GPIO_INIT(S3,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(V1,   IN),
-	GPIO_INIT(W3,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
-	GPIO_INIT(CC5,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    5,   OUT0),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    4,   OUT0),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    3,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    2,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(O,    6,   OUT0),
+	GPIO_INIT(O,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(S,    0,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(CC,   5,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 879f25a..68fbf49 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -103,11 +103,11 @@ void pin_mux_usb(void)
 	pinmux_tristate_disable(PMUX_PINGRP_DTE);
 
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PV4, "LAN_RESET");
-	gpio_direction_output(GPIO_PV4, 0);
+	gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(V, 4), 0);
 	pinmux_tristate_disable(PMUX_PINGRP_GPV);
 	udelay(5);
-	gpio_set_value(GPIO_PV4, 1);
+	gpio_set_value(TEGRA_GPIO(V, 4), 1);
 
 	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
 	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index 44b5beb..e32362a 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -47,8 +47,8 @@ void pinmux_init(void)
 void pin_mux_usb(void)
 {
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PDD0, "LAN_RESET");
-	gpio_direction_output(GPIO_PDD0, 0);
+	gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
 	udelay(5);
-	gpio_set_value(GPIO_PDD0, 1);
+	gpio_set_value(TEGRA_GPIO(DD, 0), 1);
 }
-- 
cgit v0.10.2


From e6bf0ca0e2ef8d87d754f788be1b9b5d58c01860 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:07:40 -0600
Subject: ARM: tegra: fix naming in GPIO DT binding header

According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix <dt-bindings/gpio/tegra-gpio.h> to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips. This mirrors an identical commit in the Linux kernel.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 197dc28..a1c09e8 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -12,40 +12,40 @@
 
 #include <dt-bindings/gpio/gpio.h>
 
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
 
-#define TEGRA_GPIO(bank, offset) \
-	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+	((TEGRA_GPIO_PORT_##port * 8) + offset)
 
 #endif
-- 
cgit v0.10.2


From 601800be22a37cc518e023adc8e32ad15f00a2c6 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:07:41 -0600
Subject: ARM: tegra: convert CONFIG_TEGRA_GPIO to Kconfig

Future chips will contain different GPIO HW. This change will enable
future SoC support to select the appropriate GPIO driver for their HW,
in a future-looking fashion, using Kconfig.

TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all
current Tegra chips used this GPIO HW) to simplify the later addition
of support for Tegra SoCs that use different GPIO HW.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ba6983f..616a1c3 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -22,6 +22,7 @@ config TEGRA_ARMV7_COMMON
 	select SPL
 	select SUPPORT_SPL
 	select TEGRA_COMMON
+	select TEGRA_GPIO
 
 config TEGRA_ARMV8_COMMON
 	bool "Tegra 64-bit common options"
@@ -50,6 +51,7 @@ config TEGRA124
 
 config TEGRA210
 	bool "Tegra210 family"
+	select TEGRA_GPIO
 	select TEGRA_ARMV8_COMMON
 
 endchoice
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c..f730744 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,6 +109,13 @@ config SANDBOX_GPIO_COUNT
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
 
+config TEGRA_GPIO
+	bool "Tegra20..210 GPIO driver"
+	depends on DM_GPIO
+	help
+	  Support for the GPIO controller contained in NVIDIA Tegra20 through
+	  Tegra210.
+
 config GPIO_UNIPHIER
 	bool "UniPhier GPIO"
 	depends on ARCH_UNIPHIER
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 92d4dd8..7b0940a 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -111,7 +111,6 @@
 						CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_ENTERRCM
 
 /* Defines for SPL */
-- 
cgit v0.10.2


From 074a1fdd27953aacb59346c83baaf443335ea04e Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 25 May 2016 14:38:51 -0600
Subject: gpio: add Tegra186 GPIO driver

Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.

The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org> # v1
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
new file mode 100644
index 0000000..c82a2e2
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
@@ -0,0 +1,161 @@
+NVIDIA Tegra186 GPIO controllers
+
+Tegra186 contains two GPIO controllers; a main controller and an "AON"
+controller. This binding document applies to both controllers. The register
+layouts for the controllers share many similarities, but also some significant
+differences. Hence, this document describes closely related but different
+bindings and compatible values.
+
+The Tegra186 GPIO controller allows software to set the IO direction of, and
+read/write the value of, numerous GPIO signals. Routing of GPIO signals to
+package balls is under the control of a separate pin controller HW block. Two
+major sets of registers exist:
+
+a) Security registers, which allow configuration of allowed access to the GPIO
+register set. These registers exist in a single contiguous block of physical
+address space. The size of this block, and the security features available,
+varies between the different GPIO controllers.
+
+Access to this set of registers is not necessary in all circumstances. Code
+that wishes to configure access to the GPIO registers needs access to these
+registers to do so. Code which simply wishes to read or write GPIO data does not
+need access to these registers.
+
+b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
+controllers, these registers are exposed via multiple "physical aliases" in
+address space, each of which access the same underlying state. See the hardware
+documentation for rationale. Any particular GPIO client is expected to access
+just one of these physical aliases.
+
+Tegra HW documentation describes a unified naming convention for all GPIOs
+implemented by the SoC. Each GPIO is assigned to a port, and a port may control
+a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
+name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
+or GPIO_PCC3.
+
+The number of ports implemented by each GPIO controller varies. The number of
+implemented GPIOs within each port varies. GPIO registers within a controller
+are grouped and laid out according to the port they affect.
+
+The mapping from port name to the GPIO controller that implements that port, and
+the mapping from port name to register offset within a controller, are both
+extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
+describes the port-level mapping. In that file, the naming convention for ports
+matches the HW documentation. The values chosen for the names are alphabetically
+sorted within a particular controller. Drivers need to map between the DT GPIO
+IDs and HW register offsets using a lookup table.
+
+Each GPIO controller can generate a number of interrupt signals. Each signal
+represents the aggregate status for all GPIOs within a set of ports. Thus, the
+number of interrupt signals generated by a controller varies as a rough function
+of the number of ports it implements. Note that the HW documentation refers to
+both the overall controller HW module and the sets-of-ports as "controllers".
+
+Each GPIO controller in fact generates multiple interrupts signals for each set
+of ports. Each GPIO may be configured to feed into a specific one of the
+interrupt signals generated by a set-of-ports. The intent is for each generated
+signal to be routed to a different CPU, thus allowing different CPUs to each
+handle subsets of the interrupts within a port. The status of each of these
+per-port-set signals is reported via a separate register. Thus, a driver needs
+to know which status register to observe. This binding currently defines no
+configuration mechanism for this. By default, drivers should use register
+GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
+define a property to configure this.
+
+Required properties:
+- compatible
+    Array of strings.
+    One of:
+    - "nvidia,tegra186-gpio".
+    - "nvidia,tegra186-gpio-aon".
+- reg-names
+    Array of strings.
+    Contains a list of names for the register spaces described by the reg
+    property. May contain the following entries, in any order:
+    - "gpio": Mandatory. GPIO control registers. This may cover either:
+        a) The single physical alias that this OS should use.
+        b) All physical aliases that exist in the controller. This is
+           appropriate when the OS is responsible for managing assignment of
+           the physical aliases.
+    - "security": Optional. Security configuration registers.
+    Users of this binding MUST look up entries in the reg property by name,
+    using this reg-names property to do so.
+- reg
+    Array of (physical base address, length) tuples.
+    Must contain one entry per entry in the reg-names property, in a matching
+    order.
+- interrupts
+    Array of interrupt specifiers.
+    The interrupt outputs from the HW block, one per set of ports, in the
+    order the HW manual describes them. The number of entries required varies
+    depending on compatible value:
+    - "nvidia,tegra186-gpio": 6 entries.
+    - "nvidia,tegra186-gpio-aon": 1 entry.
+- gpio-controller
+    Boolean.
+    Marks the device node as a GPIO controller/provider.
+- #gpio-cells
+    Single-cell integer.
+    Must be <2>.
+    Indicates how many cells are used in a consumer's GPIO specifier.
+    In the specifier:
+    - The first cell is the pin number.
+        See <dt-bindings/gpio/tegra186-gpio.h>.
+    - The second cell contains flags:
+        - Bit 0 specifies polarity
+            - 0: Active-high (normal).
+            - 1: Active-low (inverted).
+- interrupt-controller
+    Boolean.
+    Marks the device node as an interrupt controller/provider.
+- #interrupt-cells
+    Single-cell integer.
+    Must be <2>.
+    Indicates how many cells are used in a consumer's interrupt specifier.
+    In the specifier:
+    - The first cell is the GPIO number.
+        See <dt-bindings/gpio/tegra186-gpio.h>.
+    - The second cell is contains flags:
+        - Bits [3:0] indicate trigger type and level:
+            - 1: Low-to-high edge triggered.
+            - 2: High-to-low edge triggered.
+            - 4: Active high level-sensitive.
+            - 8: Active low level-sensitive.
+            Valid combinations are 1, 2, 3, 4, 8.
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+gpio@2200000 {
+	compatible = "nvidia,tegra186-gpio";
+	reg-names = "security", "gpio";
+	reg =
+		<0x0 0x2200000 0x0 0x10000>,
+		<0x0 0x2210000 0x0 0x10000>;
+	interrupts =
+		<0 47 IRQ_TYPE_LEVEL_HIGH>,
+		<0 50 IRQ_TYPE_LEVEL_HIGH>,
+		<0 53 IRQ_TYPE_LEVEL_HIGH>,
+		<0 56 IRQ_TYPE_LEVEL_HIGH>,
+		<0 59 IRQ_TYPE_LEVEL_HIGH>,
+		<0 180 IRQ_TYPE_LEVEL_HIGH>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
+
+gpio@c2f0000 {
+	compatible = "nvidia,tegra186-gpio-aon";
+	reg-names = "security", "gpio";
+	reg =
+		<0x0 0xc2f0000 0x0 0x1000>,
+		<0x0 0xc2f1000 0x0 0x1000>;
+	interrupts =
+		<0 60 IRQ_TYPE_LEVEL_HIGH>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f730744..32219ed 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -116,6 +116,14 @@ config TEGRA_GPIO
 	  Support for the GPIO controller contained in NVIDIA Tegra20 through
 	  Tegra210.
 
+config TEGRA186_GPIO
+	bool "Tegra186 GPIO driver"
+	depends on DM_GPIO
+	help
+	  Support for the GPIO controller contained in NVIDIA Tegra186. This
+	  covers both the "main" and "AON" controller instances, even though
+	  they have slightly different register layout.
+
 config GPIO_UNIPHIER
 	bool "UniPhier GPIO"
 	depends on ARCH_UNIPHIER
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef..3c43101 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_S5P)		+= s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
 obj-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
 obj-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
+obj-$(CONFIG_TEGRA186_GPIO)	+= tegra186_gpio.o
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index fefe3ca..64abcba 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -8,7 +8,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
 #include <syscon.h>
 #include <asm/errno.h>
diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c
new file mode 100644
index 0000000..1c68151
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.
+ * (based on tegra_gpio.c)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "tegra186_gpio_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_gpio_port_data {
+	const char *name;
+	uint32_t offset;
+};
+
+struct tegra186_gpio_ctlr_data {
+	const struct tegra186_gpio_port_data *ports;
+	uint32_t port_count;
+};
+
+struct tegra186_gpio_platdata {
+	const char *name;
+	uint32_t *regs;
+};
+
+static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
+				   uint32_t gpio)
+{
+	struct tegra186_gpio_platdata *plat = dev->platdata;
+	uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
+
+	return &(plat->regs[index]);
+}
+
+static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
+				 bool output)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
+	rval = readl(reg);
+	if (output)
+		rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+	else
+		rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+	writel(rval, reg);
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+	if (output)
+		rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+	else
+		rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+	rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
+	writel(rval, reg);
+
+	return 0;
+}
+
+static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
+	rval = readl(reg);
+	if (val)
+		rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+	else
+		rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+	writel(rval, reg);
+
+	return 0;
+}
+
+static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	return tegra186_gpio_set_out(dev, offset, false);
+}
+
+static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	int ret;
+
+	ret = tegra186_gpio_set_val(dev, offset, value != 0);
+	if (ret)
+		return ret;
+	return tegra186_gpio_set_out(dev, offset, true);
+}
+
+static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+
+	if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+		reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
+					offset);
+	else
+		reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
+
+	rval = readl(reg);
+	return !!rval;
+}
+
+static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
+				   int value)
+{
+	return tegra186_gpio_set_val(dev, offset, value != 0);
+}
+
+static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+	if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+			    struct fdtdec_phandle_args *args)
+{
+	int gpio, port, ret;
+
+	gpio = args->args[0];
+	port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
+	ret = device_get_child(dev, port, &desc->dev);
+	if (ret)
+		return ret;
+	desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops tegra186_gpio_ops = {
+	.direction_input	= tegra186_gpio_direction_input,
+	.direction_output	= tegra186_gpio_direction_output,
+	.get_value		= tegra186_gpio_get_value,
+	.set_value		= tegra186_gpio_set_value,
+	.get_function		= tegra186_gpio_get_function,
+	.xlate			= tegra186_gpio_xlate,
+};
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child device
+ * for each port within the controller.
+ */
+static int tegra186_gpio_bind(struct udevice *parent)
+{
+	struct tegra186_gpio_platdata *parent_plat = parent->platdata;
+	struct tegra186_gpio_ctlr_data *ctlr_data =
+		(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
+	uint32_t *regs;
+	int port, ret;
+
+	/* If this is a child device, there is nothing to do here */
+	if (parent_plat)
+		return 0;
+
+	regs = (uint32_t *)dev_get_addr_name(parent, "gpio");
+	if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	for (port = 0; port < ctlr_data->port_count; port++) {
+		struct tegra186_gpio_platdata *plat;
+		struct udevice *dev;
+
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		plat->name = ctlr_data->ports[port].name;
+		plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
+
+		ret = device_bind(parent, parent->driver, plat->name, plat,
+				  -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static int tegra186_gpio_probe(struct udevice *dev)
+{
+	struct tegra186_gpio_platdata *plat = dev->platdata;
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	/* Only child devices have ports */
+	if (!plat)
+		return 0;
+
+	uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
+	uc_priv->bank_name = plat->name;
+
+	return 0;
+}
+
+static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
+	{"A",  0x2000},
+	{"B",  0x3000},
+	{"C",  0x3200},
+	{"D",  0x3400},
+	{"E",  0x2200},
+	{"F",  0x2400},
+	{"G",  0x4200},
+	{"H",  0x1000},
+	{"I",  0x0800},
+	{"J",  0x5000},
+	{"K",  0x5200},
+	{"L",  0x1200},
+	{"M",  0x5600},
+	{"N",  0x0000},
+	{"O",  0x0200},
+	{"P",  0x4000},
+	{"Q",  0x0400},
+	{"R",  0x0a00},
+	{"T",  0x0600},
+	{"X",  0x1400},
+	{"Y",  0x1600},
+	{"BB", 0x2600},
+	{"CC", 0x5400},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
+	.ports = tegra186_gpio_main_ports,
+	.port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
+};
+
+static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
+	{"S",  0x0200},
+	{"U",  0x0400},
+	{"V",  0x0800},
+	{"W",  0x0a00},
+	{"Z",  0x0e00},
+	{"AA", 0x0c00},
+	{"EE", 0x0600},
+	{"FF", 0x0000},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
+	.ports = tegra186_gpio_aon_ports,
+	.port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
+};
+
+static const struct udevice_id tegra186_gpio_ids[] = {
+	{
+		.compatible = "nvidia,tegra186-gpio",
+		.data = (ulong)&tegra186_gpio_main_data,
+	},
+	{
+		.compatible = "nvidia,tegra186-gpio-aon",
+		.data = (ulong)&tegra186_gpio_aon_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(tegra186_gpio) = {
+	.name = "tegra186_gpio",
+	.id = UCLASS_GPIO,
+	.of_match = tegra186_gpio_ids,
+	.bind = tegra186_gpio_bind,
+	.probe = tegra186_gpio_probe,
+	.ops = &tegra186_gpio_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/gpio/tegra186_gpio_priv.h b/drivers/gpio/tegra186_gpio_priv.h
new file mode 100644
index 0000000..9e85a434
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio_priv.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_PRIV_H_
+#define _TEGRA186_GPIO_PRIV_H_
+
+/*
+ * For each GPIO, there are a set of registers than affect it, all packed
+ * back-to-back.
+ */
+#define TEGRA186_GPIO_ENABLE_CONFIG				0x00
+#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE			BIT(0)
+#define TEGRA186_GPIO_ENABLE_CONFIG_OUT				BIT(1)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT		2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK		3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE		0
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL		1
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE	2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE	3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING	BIT(4)
+#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE		BIT(5)
+#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE		BIT(6)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE		BIT(7)
+
+#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD			0x04
+
+#define TEGRA186_GPIO_INPUT					0x08
+
+#define TEGRA186_GPIO_OUTPUT_CONTROL				0x0c
+#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED			BIT(0)
+
+#define TEGRA186_GPIO_OUTPUT_VALUE				0x10
+#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH				1
+
+#define TEGRA186_GPIO_INTERRUPT_CLEAR				0x14
+
+/*
+ * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
+ * port's address space.
+ */
+#define TEGRA186_GPIO_PER_GPIO_STRIDE				0x20
+#define TEGRA186_GPIO_PER_GPIO_COUNT				8
+
+/*
+ * Per-port registers are packed immediately following all of a port's
+ * per-GPIO registers.
+ */
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G			0x100
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE			4
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT			8
+
+/*
+ * The registers for multiple ports are packed together back-to-back to form
+ * the overall controller.
+ */
+#define TEGRA186_GPIO_PER_PORT_STRIDE				0x200
+
+#endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 0000000..7e6fb95
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+	((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
-- 
cgit v0.10.2


From 39f633320c569a5d975d2d051ff2683db27bd021 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 12:11:23 -0600
Subject: mmc: tegra: add basic Tegra186 support

Tegra186's MMC controller needs to be explicitly identified. Add another
compatible value for it.

Tegra186 will use an entirely different clock/reset control mechanism to
existing chips, and will use standard clock/reset APIs rather than the
existing Tegra-specific custom APIs. The driver support for that isn't
ready yet, so simply disable all clock/reset usage if compiling for
Tegra186. This must happen at compile time rather than run-time since the
custom APIs won't even be compiled in on Tegra186. In the long term, the
plan would be to convert the existing custom APIs to standard APIs and get
rid of the ifdefs completely.

The system's main eMMC will work without any clock/reset support, since
the firmware will have already initialized the controller in order to
load U-Boot. Hence the driver is useful even in this apparently crippled
state.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a20bdaa..75e56c4 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -134,7 +134,9 @@ struct mmc_host {
 	int id;			/* device id/number, 0-3 */
 	int enabled;		/* 1 to enable, 0 to disable */
 	int width;		/* Bus Width, 1, 4 or 8 */
+#ifndef CONFIG_TEGRA186
 	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
+#endif
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	struct gpio_desc pwr_gpio;	/* Power GPIO */
 	struct gpio_desc wp_gpio;	/* Write Protect GPIO */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 573819a..c9d9432 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -11,8 +11,10 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#ifndef CONFIG_TEGRA186
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
+#endif
 #include <asm/arch-tegra/mmc.h>
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
@@ -357,8 +359,12 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
 	 */
 	if (clock == 0)
 		goto out;
+#ifndef CONFIG_TEGRA186
 	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 				    &div);
+#else
+	div = (20000000 + clock - 1) / clock;
+#endif
 	debug("div = %d\n", div);
 
 	writew(0, &host->reg->clkcon);
@@ -543,7 +549,9 @@ static int do_mmc_init(int dev_index, bool removable)
 	      gpio_get_number(&host->cd_gpio));
 
 	host->clock = 0;
+#ifndef CONFIG_TEGRA186
 	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
+#endif
 
 	if (dm_gpio_is_valid(&host->pwr_gpio))
 		dm_gpio_set_value(&host->pwr_gpio, 1);
@@ -568,7 +576,11 @@ static int do_mmc_init(int dev_index, bool removable)
 	 *  (actually 52MHz)
 	 */
 	host->cfg.f_min = 375000;
+#ifndef CONFIG_TEGRA186
 	host->cfg.f_max = 48000000;
+#else
+	host->cfg.f_max = 375000;
+#endif
 
 	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
@@ -600,11 +612,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 		return -FDT_ERR_NOTFOUND;
 	}
 
+#ifndef CONFIG_TEGRA186
 	host->mmc_id = clock_decode_periph_id(blob, node);
 	if (host->mmc_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id\n", __func__);
 		return -FDT_ERR_NOTFOUND;
 	}
+#endif
 
 	/*
 	 * NOTE: mmc->bus_width is determined by mmc.c dynamically.
@@ -624,7 +638,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 	*removablep = !fdtdec_get_bool(blob, node, "non-removable");
 
 	debug("%s: found controller at %p, width = %d, periph_id = %d\n",
-		__func__, host->reg, host->width, host->mmc_id);
+		__func__, host->reg, host->width,
+#ifndef CONFIG_TEGRA186
+		host->mmc_id
+#else
+		-1
+#endif
+	);
 	return 0;
 }
 
@@ -668,6 +688,16 @@ void tegra_mmc_init(void)
 	const void *blob = gd->fdt_blob;
 	debug("%s entry\n", __func__);
 
+	/* See if any Tegra186 MMC controllers are present */
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
+		CONFIG_SYS_MMC_MAX_DEVICE);
+	debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing T186 mmc node(s)!\n", __func__);
+		return;
+	}
+
 	/* See if any Tegra210 MMC controllers are present */
 	count = fdtdec_find_aliases_for_id(blob, "sdhci",
 		COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 37d482a..54e3d81 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -123,6 +123,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA124_SOR,	/* Tegra 124 Serial Output Resource */
 	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA186_SDMMC,	/* Tegra186 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 70acc29..ab002e9 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -30,6 +30,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
 	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
 	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
 	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
-- 
cgit v0.10.2


From c7ba99c8c18a606b95a89366bc4fd94a8295772f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 13:32:55 -0600
Subject: ARM: tegra: add core Tegra186 support

This adds the bare minimum code to support Tegra186, with UART and eMMC
working.

The empty gpio.h is required because <asm/gpio.h> includes it. A future
cleanup round may be able to solve this for all Tegra generations at once.

mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but
instead to defer everything to mach-tegra/tegra186/Makefile. This allows
the SoC code to pick-and-choose which of the C files in the "common"
mach-tegra/ directory to compile in based on the SoC's needs. Most of the
code is not valid for Tegra186, and this approach removes the need for
mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach
may be applied to all other Tegra SoCs in a future cleanup round.

board186.c is introduced to replace board.c and board2.c. These files
currently contain a slew of SoC- and board-specific code that is not
valid for Tegra186. This approach avoids adding yet more ifdefs to those
files. A future cleanup round may refactor most of board*.c into board-/
SoC-specific functions files thus allowing the top-level functions like
board_init_early_f to be shared again.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
new file mode 100644
index 0000000..18b6a26
--- /dev/null
+++ b/arch/arm/dts/tegra186.dtsi
@@ -0,0 +1,56 @@
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "nvidia,tegra186";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	gpio@2200000 {
+		compatible = "nvidia,tegra186-gpio";
+		reg-names = "security", "gpio";
+		reg =
+			<0x0 0x2200000 0x0 0x10000>,
+			<0x0 0x2210000 0x0 0x10000>;
+		interrupts =
+			<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	uarta: serial@3100000 {
+		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x03100000 0x0 0x10000>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	sdhci@3460000 {
+		compatible = "nvidia,tegra186-sdhci";
+		reg = <0x0 0x03460000 0x0 0x200>;
+		interrupts = <GIC_SPI 31 0x04>;
+		status = "disabled";
+	};
+
+	gpio@c2f0000 {
+		compatible = "nvidia,tegra186-gpio-aon";
+		reg-names = "security", "gpio";
+		reg =
+			<0x0 0xc2f0000 0x0 0x1000>,
+			<0x0 0xc2f1000 0x0 0x1000>;
+		interrupts =
+			<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h
new file mode 100644
index 0000000..aaecfc7
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h
new file mode 100644
index 0000000..8031f23
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/tegra.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE		0x03881000	/* Generic Int Cntrlr Distrib */
+#define GICC_BASE		0x03882000	/* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE	0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 616a1c3..b18a12e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -54,6 +54,11 @@ config TEGRA210
 	select TEGRA_GPIO
 	select TEGRA_ARMV8_COMMON
 
+config TEGRA186
+	bool "Tegra186 family"
+	select TEGRA186_GPIO
+	select TEGRA_ARMV8_COMMON
+
 endchoice
 
 config TEGRA_DISCONNECT_UDC_ON_BOOT
@@ -77,5 +82,6 @@ source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"
 source "arch/arm/mach-tegra/tegra124/Kconfig"
 source "arch/arm/mach-tegra/tegra210/Kconfig"
+source "arch/arm/mach-tegra/tegra186/Kconfig"
 
 endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b2dbc69..12ee1cd 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifndef CONFIG_TEGRA186
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 obj-y += cpu.o
@@ -30,9 +31,11 @@ obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
 endif
+endif
 
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_TEGRA30) += tegra30/
 obj-$(CONFIG_TEGRA114) += tegra114/
 obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA186) += tegra186/
 obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
new file mode 100644
index 0000000..f4b6152
--- /dev/null
+++ b/arch/arm/mach-tegra/board186.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = (1.5 * 1024 * 1024 * 1024);
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+}
+
+int board_mmc_init(bd_t *bd)
+{
+	tegra_mmc_init();
+
+	return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
new file mode 100644
index 0000000..124d8e5
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TEGRA186
+
+choice
+	prompt "Tegra186 board select"
+
+endchoice
+
+config SYS_SOC
+	default "tegra186"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
new file mode 100644
index 0000000..ce4610d
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -0,0 +1,8 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += ../arm64-mmu.o
+obj-y += ../board186.o
+obj-y += ../lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
new file mode 100644
index 0000000..aa7b9d0
--- /dev/null
+++ b/include/configs/tegra186-common.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_TEXT_BASE	0x80080000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+#endif
-- 
cgit v0.10.2


From 10a03382f0f8e774e58df7143e1a8ea52903ae1f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 12 May 2016 13:32:56 -0600
Subject: ARM: tegra: add p2771-0000 board support

P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B
port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion
headers.

Currently, due to U-Boot's level of support for Tegra186, the only
features supported by U-Boot are the console UART and the on-board eMMC.
Additional features will be added over time.

U-Boot has so far been tested by replacing the kernel image on the device
with a U-Boot binary. It is anticipated that U-Boot will eventually
replace the CCPLEX bootloader binary, as on previous chips. This hasn't
yet been tested.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 92c7545..818d24e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-nyan-big.dtb \
 	tegra124-venice2.dtb \
+	tegra186-p2771-0000.dtb \
 	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts
new file mode 100644
index 0000000..5f29ee4
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "tegra186.dtsi"
+
+/ {
+	model = "NVIDIA P2771-0000";
+	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		sdhci0 = "/sdhci@3460000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x60000000>;
+	};
+
+	sdhci@3460000 {
+		status = "okay";
+		bus-width = <8>;
+	};
+};
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
index 124d8e5..97cf23f 100644
--- a/arch/arm/mach-tegra/tegra186/Kconfig
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -7,9 +7,19 @@ if TEGRA186
 choice
 	prompt "Tegra186 board select"
 
+config TARGET_P2771_0000
+	bool "NVIDIA Tegra186 P2771-0000 board"
+	help
+	  P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
+	  combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+	  micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
+	  expansion headers.
+
 endchoice
 
 config SYS_SOC
 	default "tegra186"
 
+source "board/nvidia/p2771-0000/Kconfig"
+
 endif
diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig
new file mode 100644
index 0000000..1b1116f
--- /dev/null
+++ b/board/nvidia/p2771-0000/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TARGET_P2771_0000
+
+config SYS_BOARD
+	default "p2771-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2771-0000"
+
+endif
diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS
new file mode 100644
index 0000000..4fc4ebd
--- /dev/null
+++ b/board/nvidia/p2771-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P2771-0000 BOARD
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2771-0000/
+F:	include/configs/p2771-0000.h
+F:	configs/p2771-0000_defconfig
diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile
new file mode 100644
index 0000000..b28a47d
--- /dev/null
+++ b/board/nvidia/p2771-0000/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y	+= p2771-0000.o
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
new file mode 100644
index 0000000..4ba8ebc
--- /dev/null
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
new file mode 100644
index 0000000..9f2c418
--- /dev/null
+++ b/configs/p2771-0000_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
new file mode 100644
index 0000000..257283f
--- /dev/null
+++ b/include/configs/p2771-0000.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _P2771_0000_H
+#define _P2771_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra186-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2771-0000"
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY	19200000
+
+#endif
-- 
cgit v0.10.2


From 8b528709c5bba6a8d0ec83b20545bbd75f082704 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Wed, 1 Jun 2016 10:28:31 +0530
Subject: spl: fit: Fix load address of fit header

When loading fit header, it should be loaded to a previous address
aligned to ARCH_DMA_MINALIGN and not 8. Fixing the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index a828f72..c9eb020 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -156,8 +156,8 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * In fact the FIT has its own load address, but we assume it cannot
 	 * be before CONFIG_SYS_TEXT_BASE.
 	 */
-	fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
-	fit = (void *)ALIGN((ulong)fit, 8);
+	fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
+			align_len) & ~align_len);
 	sectors = get_aligned_image_size(info, size, 0);
 	count = info->read(info, sector, sectors, fit);
 	debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
-- 
cgit v0.10.2


From 569a191a864cee66e3d0763179e8688499de0377 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 1 Dec 2015 18:09:52 +0100
Subject: arm: socfpga: Add samtec VIN|ING board

Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
 - 1 GiB of DRAM
 - 1 Gigabit ethernet
 - 1 USB gadget port
 - 1 USB host port with an on-board hub
 - 2 QSPI NORs connected to the Cadence QSPI core
 - Multiple I2C EEPROMs and one I2C temperature sensor

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 92c7545..e76f56b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -107,7 +107,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
-	socfpga_cyclone5_sr1500.dtb
+	socfpga_cyclone5_sr1500.dtb			\
+	socfpga_cyclone5_vining_fpga.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
new file mode 100644
index 0000000..f168e4f
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "samtec VIN|ING FPGA";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb0;
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rtc: rtc@68 {
+		compatible = "stm,m41t82";
+		reg = <0x68>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	flash0: n25q128@0 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q128", "spi-flash";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+
+	flash1: n25q00@1 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00", "spi-flash";
+		reg = <1>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index dea4ce5..1484607 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -35,6 +35,10 @@ config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+	bool "samtec VIN|ING FPGA (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -53,12 +57,14 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
@@ -73,5 +79,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS
new file mode 100644
index 0000000..c2002fe
--- /dev/null
+++ b/board/samtec/vining_fpga/MAINTAINERS
@@ -0,0 +1,5 @@
+VINING FPGA BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_vining_fpga.h
+F:	configs/socfpga_vining_fpga_defconfig
diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile
new file mode 100644
index 0000000..86f9b78
--- /dev/null
+++ b/board/samtec/vining_fpga/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h
new file mode 100644
index 0000000..fe5cb61
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00000000,
+	0x300C0000,
+	0x000000C0,
+	0x00000000,
+	0x00000000,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00601806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x300C0000,
+	0x0FF00000,
+	0x00000000,
+	0x000300C0,
+	0x00008000,
+	0x18060180,
+	0x18060000,
+	0x00000000,
+	0x00000000,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x00000030,
+	0x00000000,
+	0x0300C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680A28,
+	0x41034051,
+	0x12481A00,
+	0x80A280D0,
+	0x34051406,
+	0x01A02490,
+	0x080D0000,
+	0x51406802,
+	0x02490340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x49034051,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x5140680A,
+	0x02490340,
+	0xD012481A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F36080,
+	0x1A041404,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3D5,
+	0xF6D1451E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xD569A47A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00035292,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F36080,
+	0x1A041404,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3D5,
+	0xF4D1451E,
+	0x034AD348,
+	0x821A0186,
+	0x0000D000,
+	0x00000680,
+	0xD569A47A,
+	0x1EF228A3,
+	0x48F4D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F36080,
+	0x1A041404,
+	0x00D00000,
+	0x0C864000,
+	0x59647A03,
+	0xCB2CA3DD,
+	0xF6D9651E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1E8A28A3,
+	0x48F6D965,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F16080,
+	0x1A041404,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0xF228A3D5,
+	0xF4D1451E,
+	0x03529248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h
new file mode 100644
index 0000000..9680365
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	2, /* FLASHIO0 */
+	2, /* FLASHIO1 */
+	2, /* FLASHIO2 */
+	2, /* FLASHIO3 */
+	2, /* FLASHIO4 */
+	2, /* FLASHIO5 */
+	2, /* FLASHIO6 */
+	2, /* FLASHIO7 */
+	2, /* FLASHIO8 */
+	2, /* FLASHIO9 */
+	2, /* FLASHIO10 */
+	2, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	2, /* GENERALIO15 */
+	2, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	2, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	1, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	1, /* SPIS1USEFPGA */
+	1, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h
new file mode 100644
index 0000000..c8a6e96
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/pll_config.h
@@ -0,0 +1,91 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h
new file mode 100644
index 0000000..74cb405
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -0,0 +1,341 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0		0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090046,
+	0x100a0088,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0026,
+	0x10090110,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c
new file mode 100644
index 0000000..f3a92b5
--- /dev/null
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -0,0 +1,100 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_late_init(void)
+{
+	const unsigned int phy_nrst_gpio = 0;
+	const unsigned int usb_nrst_gpio = 35;
+	int ret;
+
+	status_led_set(1, STATUS_LED_ON);
+	status_led_set(2, STATUS_LED_ON);
+
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
+	if (!ret)
+		gpio_direction_output(phy_nrst_gpio, 1);
+	else
+		printf("Cannot remove PHY from reset!\n");
+
+	ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
+	if (!ret)
+		gpio_direction_output(usb_nrst_gpio, 1);
+	else
+		printf("Cannot remove USB from reset!\n");
+
+	mdelay(50);
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+	uchar data[128];
+	char str[32];
+	u32 serial;
+	int ret;
+
+	/* EEPROM is at bus 0. */
+	ret = i2c_set_bus_num(0);
+	if (ret) {
+		puts("Cannot select EEPROM I2C bus.\n");
+		return 0;
+	}
+
+	/* EEPROM is at address 0x50. */
+	ret = eeprom_read(0x50, 0, data, sizeof(data));
+	if (ret) {
+		puts("Cannot read I2C EEPROM.\n");
+		return 0;
+	}
+
+	/* Check EEPROM signature. */
+	if (!(data[0] == 0xa5 && data[1] == 0x5a)) {
+		puts("Invalid I2C EEPROM signature.\n");
+		setenv("unit_serial", "invalid");
+		setenv("unit_ident", "VINing-xxxx-STD");
+		setenv("hostname", "vining-invalid");
+		return 0;
+	}
+
+	/* If 'unit_serial' is already set, do nothing. */
+	if (!getenv("unit_serial")) {
+		/* This field is Big Endian ! */
+		serial = (data[0x54] << 24) | (data[0x55] << 16) |
+			 (data[0x56] << 8) | (data[0x57] << 0);
+		memset(str, 0, sizeof(str));
+		sprintf(str, "%07i", serial);
+		setenv("unit_serial", str);
+	}
+
+	if (!getenv("unit_ident")) {
+		memset(str, 0, sizeof(str));
+		memcpy(str, &data[0x2e], 18);
+		setenv("unit_ident", str);
+	}
+
+	/* Set ethernet address from EEPROM. */
+	if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62]))
+		eth_setenv_enetaddr("ethaddr", &data[0x62]);
+
+	return 0;
+}
+#endif
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
new file mode 100644
index 0000000..f8bb9a6
--- /dev/null
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="samtec"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
new file mode 100644
index 0000000..1ccde1a
--- /dev/null
+++ b/include/configs/socfpga_vining_fpga.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
+#define __CONFIG_SAMTEC_VINING_FPGA_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_LED
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on VINING_FPGA */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTFILE		"openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND	"run selboot"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_I2C_EEPROM_BUS		0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+#endif
+
+/*
+ * Status LEDs:
+ *   0 ... Top Green
+ *   1 ... Top Red
+ *   2 ... Bottom Green
+ *   3 ... Bottom Red
+ */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT		48
+#define STATUS_LED_STATE	STATUS_LED_OFF
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1		53
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2		54
+#define STATUS_LED_STATE2	STATUS_LED_OFF
+#define STATUS_LED_PERIOD2	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT3		65
+#define STATUS_LED_STATE3	STATUS_LED_OFF
+#define STATUS_LED_PERIOD3	(CONFIG_SYS_HZ / 2)
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME			socfpga_vining_fpga
+
+/*
+ * Active LOW GPIO buttons:
+ * A: GPIO 77 ... the button between USB B and ethernet
+ * B: GPIO 78 ... the button between USB A ports
+ *
+ * The logic:
+ *  if button B is not pressed, boot normal Linux system immediatelly
+ *  if button B is pressed, wait $bootdelay and boot recovery system
+ */
+#define CONFIG_PREBOOT						\
+	"setenv hostname vining-${unit_serial} ; "		\
+	"setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; "	\
+	"if gpio input 78 ; then "			\
+		"setenv bootdelay 10 ; "		\
+		"setenv boottype rcvr ; "		\
+	"else "						\
+		"setenv bootdelay 5 ; "			\
+		"setenv boottype norm ; "		\
+	"fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"consdev=ttyS0\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"ubimtdnr=5\0"							\
+	"ubimtd=rootfs\0"						\
+	"ubipart=ubi0:rootfs\0"						\
+	"ubisfcs=1\0"		/* Default is flash at CS#1 */		\
+	"netdev=eth0\0"							\
+	"hostname=vining_fpga\0"						\
+	"kernel_addr_r=0x10000000\0"					\
+	"mtdparts_0=ff705000.spi.0:"					\
+		"1m(u-boot),"						\
+		"64k(env1),"						\
+		"64k(env2),"						\
+		"256k(samtec1),"					\
+		"256k(samtec2),"					\
+		"-(rcvrfs)\0"	/* Recovery */				\
+	"mtdparts_1=ff705000.spi.1:"					\
+		"32m(rootfs),"						\
+		"-(userfs)\0"						\
+	"update_filename=u-boot-with-spl-dtb.sfp\0"			\
+	"update_qspi_offset=0x0\0"					\
+	"update_qspi="		/* Update the QSPI firmware */		\
+		"if sf probe ; then "					\
+		"if tftp ${update_filename} ; then "			\
+		"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+		"fi ; "							\
+		"fi\0"							\
+	"fpga_filename=output_file.rbf\0"				\
+	"load_fpga="		/* Load FPGA bitstream */		\
+		"if tftp ${fpga_filename} ; then "			\
+		"fpga load 0 $loadaddr $filesize ; "			\
+		"bridge enable ; "					\
+		"fi\0"							\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addmtd="							\
+		"setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; "	\
+		"setenv bootargs ${bootargs} mtdparts=${mtdparts}\0"	\
+	"addargs=run addcons addmtd addmisc\0"				\
+	"ubiload="							\
+		"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; "		\
+		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"ubiargs="							\
+		"setenv bootargs ubi.mtd=${ubimtdnr} "			\
+		"root=${ubipart} rootfstype=ubifs\0"			\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"ubi_sfsel="							\
+		"if test \"${boottype}\" = \"rcvr\" ; then "		\
+			"setenv ubisfcs 0 ; "				\
+			"setenv ubimtd rcvrfs ; "			\
+			"setenv ubimtdnr 5 ; "				\
+			"setenv mtdparts mtdparts=${mtdparts_0} ; "	\
+			"setenv mtdids nor0=ff705000.spi.0 ; "		\
+			"setenv ubipart ubi0:rootfs ; "			\
+		"else "							\
+			"setenv ubisfcs 1 ; "				\
+			"setenv ubimtd rootfs ; "			\
+			"setenv ubimtdnr 6 ; "				\
+			"setenv mtdparts mtdparts=${mtdparts_1} ; "	\
+			"setenv mtdids nor0=ff705000.spi.1 ; "		\
+			"setenv ubipart ubi0:rootfs ; "			\
+		"fi ; "							\
+		"sf probe 0:${ubisfcs}\0"				\
+	"ubi_ubi="							\
+		"run ubi_sfsel ubiload ubiargs addargs ; "		\
+		"bootm ${kernel_addr_r}\0"				\
+	"ubi_nfs="							\
+		"run ubiload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_ubi="							\
+		"run netload ubiargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"selboot="	/* Select from where to boot. */		\
+		"if test \"${bootmode}\" = \"qspi\" ; then "		\
+			"led all off ; "				\
+			"if test \"${boottype}\" = \"rcvr\" ; then "	\
+				"echo \"Booting recovery system\" ; "	\
+				"led 3 on ; "	/* Bottom RED */	\
+			"fi ; "						\
+			"led 1 on ; "		/* Top RED */		\
+			"run ubi_ubi ; "				\
+		"else echo \"Unsupported boot mode: \"${bootmode} ; "	\
+		"fi\0"							\
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDPARTS_DEFAULT			\
+	"mtdparts=ff705000.spi.0:"		\
+		"1m(u-boot),"			\
+		"64k(env1),"			\
+		"64k(env2),"			\
+		"256k(samtec1),"		\
+		"256k(samtec2),"		\
+		"-(rcvrfs);"	/* Recovery */	\
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+/* Enable DFU to SF and RAM */
+#define CONFIG_DFU_RAM
+#define CONFIG_DFU_SF
+
+/* Support changing the prompt string */
+#define CONFIG_CMDLINE_PS_SUPPORT
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SAMTEC_VINING_FPGA_H__ */
-- 
cgit v0.10.2


From 1254667689a5a4accc149fef6ff69da760001b2b Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 30 May 2016 17:10:53 +0200
Subject: spl: Remove bogus GD_FLG_SPL_INIT check

Remove the check for GD_FLG_SPL_INIT in spl_relocate_stack_gd().
The check will always fail. This is because spl_relocate_stack_gd()
is called from ARM's crt0.S and it is called before board_init_r().
The board_init_r() calls spl_init(), which sets the GD_FLG_SPL_INIT
flag.

Note that reserving the malloc area in RAM is not a problem even
if the GD_FLG_SPL_INIT flag is not set.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index bdde716..8b10bdf 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -486,9 +486,6 @@ ulong spl_relocate_stack_gd(void)
 
 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
 	if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
-		if (!(gd->flags & GD_FLG_SPL_INIT))
-			panic_str("spl_init must be called before heap reloc");
-
 		ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
 		gd->malloc_base = ptr;
 		gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
-- 
cgit v0.10.2


From 5bb4050df36f016de106c0ab129319795acabc06 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 30 May 2016 17:09:48 +0200
Subject: arm: socfpga: Enable tiny printf and simple malloc in SPL

Enable both features to reduce the SPL size by 6 kiB.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index a662e72..ec40ec7 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b2933f7..8e5c527 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index f197b6d..034a215 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 6624f9e..133a6eb 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index c6414f8..8b1bcfc 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index b47a560..56284a1 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index aab4498..d66f7c6 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SR1500=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index f8bb9a6..6ce4def 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f657766..aee4012 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -324,9 +324,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
-- 
cgit v0.10.2


From 77cd5368cee8b6a5684877e1bf4d544bf271ef08 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 1 Jun 2016 13:24:58 +0200
Subject: arm: socfpga: Add missing ',' in CONFIG_BOOTARGS

Somehow the sr1500 is missing this comma in the CONFIG_BOOTARGS
definition. This patch adds it to.

Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Pavel Machek <pavel@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>

diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index efa9e42..c097f47 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -22,7 +22,7 @@
 /* Booting Linux */
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
-- 
cgit v0.10.2


From d31e9c575f24f4b7f5f382ccae70d7a86bbc379d Mon Sep 17 00:00:00 2001
From: Sylvain Lesne <lesne@alse-fr.com>
Date: Wed, 1 Jun 2016 11:14:54 +0200
Subject: arm: socfpga: improve raw MMC SPL boot

Before this patch, when booting from MMC (no filesystem), the SPL
loaded U-Boot from a fixed offset.
It will now load U-Boot from an offset of 256kB (which is 4 times the
padded SPL image) in the third partition.

This behaviour is similar to what the vendor SPL (based on
U-Boot 2013.01) does, and allows to directly 'dd' the
u-boot-with-spl.sfp file to the A2 partition.

Signed-off-by: Sylvain Lesne <lesne@alse-fr.com>

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index aee4012..1f8b7b3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -346,9 +346,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #else
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	3
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0xa00 /* offset 2560 sect (1M+256k) */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200 /* offset 512 sect (256k) */
+#define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
 #endif
 
-- 
cgit v0.10.2


From 626f6e4f575b24e2e8c5cfec39e56563c4003598 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 30 Apr 2016 14:45:59 +0200
Subject: arm: Treat arm946es as v5te

The arm946es is armv5te , so use -march=armv5te instead of armv4t.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ecd1887..6a07cd1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -11,7 +11,7 @@ endif
 arch-$(CONFIG_CPU_ARM720T)	=-march=armv4
 arch-$(CONFIG_CPU_ARM920T)	=-march=armv4t
 arch-$(CONFIG_CPU_ARM926EJS)	=-march=armv5te
-arch-$(CONFIG_CPU_ARM946ES)	=-march=armv4
+arch-$(CONFIG_CPU_ARM946ES)	=-march=armv5te
 arch-$(CONFIG_CPU_SA1100)	=-march=armv4
 arch-$(CONFIG_CPU_PXA)		=
 arch-$(CONFIG_CPU_ARM1136)	=-march=armv5
-- 
cgit v0.10.2


From 307c0b518979ff77876b880da88c388e4add692d Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:12:32 +0200
Subject: gpio: mxs: Remove netdev.h

The MXS certainly does not support any sort of networking in GPIO code,
remove the netdev.h header.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index b54a10b..c25b4c1 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -8,7 +8,6 @@
  */
 
 #include <common.h>
-#include <netdev.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/iomux.h>
-- 
cgit v0.10.2


From fa4ce72316547753451528728491d31e6c7b18f0 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:13:03 +0200
Subject: serial: 16550: Make serial_io/out_shift available to debug mode

The ns16550 driver needs serial_in_shift() and serial_out_shift()
when compiled in debug UART mode, so shift the DM_SERIAL check a
little to make these functions available.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index d7a3cf6..4763a1c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -54,12 +54,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_NS16550_IER  0x00
 #endif /* CONFIG_SYS_NS16550_IER */
 
-#ifdef CONFIG_DM_SERIAL
-
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK  0
-#endif
-
 static inline void serial_out_shift(void *addr, int shift, int value)
 {
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
@@ -94,6 +88,12 @@ static inline int serial_in_shift(void *addr, int shift)
 #endif
 }
 
+#ifdef CONFIG_DM_SERIAL
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK  0
+#endif
+
 static void ns16550_writeb(NS16550_t port, int offset, int value)
 {
 	struct ns16550_platdata *plat = port->plat;
-- 
cgit v0.10.2


From 03c6f1761ede305637ed54fb238b2059c597451e Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:13:16 +0200
Subject: serial: 16550: Drop OMAP1510 support

The CONFIG_OMAP1510 is no longer defined, so remove this dead code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Nishanth Menon <nm@ti.com>

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 4763a1c..c6cb3eb 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -129,27 +129,13 @@ static int ns16550_readb(NS16550_t port, int offset)
 		(unsigned char *)addr - (unsigned char *)com_port)
 #endif
 
-static inline int calc_divisor(NS16550_t port, int clock, int baudrate)
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
 {
 	const unsigned int mode_x_div = 16;
 
 	return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
 }
 
-int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
-{
-#ifdef CONFIG_OMAP1510
-	/* If can't cleanly clock 115200 set div to 1 */
-	if ((clock == 12000000) && (baudrate == 115200)) {
-		port->osc_12m_sel = OSC_12M_SEL;  /* enable 6.5 * divisor */
-		return 1;			/* return 1 for base divisor */
-	}
-	port->osc_12m_sel = 0;			/* clear if previsouly set */
-#endif
-
-	return calc_divisor(port, clock, baudrate);
-}
-
 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
 {
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
@@ -272,8 +258,8 @@ static inline void _debug_uart_init(void)
 	 * feasible. The better fix is to move all users of this driver to
 	 * driver model.
 	 */
-	baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
-				    CONFIG_BAUDRATE);
+	baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+					    CONFIG_BAUDRATE);
 	serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
 	serial_dout(&com_port->mcr, UART_MCRVAL);
 	serial_dout(&com_port->fcr, UART_FCRVAL);
-- 
cgit v0.10.2


From 94b9e22e5036a2d8ad76956785e55754d4a980ad Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 25 May 2016 02:14:56 +0200
Subject: spl: Allow settings malloc_f base address

Allow configuring the begining of the malloc_f area in SPL.
This patch uses the same CONFIG_MALLOC_F_ADDR established by
the sandbox.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index bdde716..780c081 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -192,6 +192,9 @@ int spl_init(void)
 
 	debug("spl_init()\n");
 #if defined(CONFIG_SYS_MALLOC_F_LEN)
+#ifdef CONFIG_MALLOC_F_ADDR
+	gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
 	gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
 	gd->malloc_ptr = 0;
 #endif
-- 
cgit v0.10.2


From 35016e39fe545420260ec487859aaaeb80bf3be0 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 1 Jun 2016 00:00:02 +0200
Subject: mips: wdr4300: Move the CONFIG_USE_PRIVATE_LIBGCC to Kconfig

This fixes the last remaining libgcc warning, where the symbol was
defined twice.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index b1af2f6..3eec4c2 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_ARCH_ATH79=y
 CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SERIAL=y
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 6273711..abe1da2 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -78,8 +78,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x83f00000
 #define CONFIG_CMD_MEMTEST
 
-#define CONFIG_USE_PRIVATE_LIBGCC
-
 #define CONFIG_CMD_MII
 #define CONFIG_PHY_GIGE
 
-- 
cgit v0.10.2


From b4ba1693ef25aa0050c5aa254a0d1c4ed0af65f3 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 1 Jun 2016 02:33:53 +0200
Subject: arm: Select CONFIG_ARM64 for Cavium ThunderX

Select the config option, since this board is ARM64.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a77b6a..e5463d2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -766,6 +766,7 @@ config ARCH_ROCKCHIP
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
+	select ARM64
 	select OF_CONTROL
 
 endchoice
-- 
cgit v0.10.2


From abeb272d22217481c214495818c3ceabad57b9c0 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 31 May 2016 23:12:46 +0200
Subject: tiny-printf: Support sprintf()

Add a simple version of this function for SPL. It does not check the buffer
size as this would add to the code size.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: lesne@alse-fr.com
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Sylvain Lesne <lesne@alse-fr.com>
Tested-by: Sylvain Lesne <lesne@alse-fr.com>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 4b70263..5ea2555 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -147,8 +147,7 @@ static void putc_outstr(char ch)
 	*outstr++ = ch;
 }
 
-/* Note that size is ignored */
-int snprintf(char *buf, size_t size, const char *fmt, ...)
+int sprintf(char *buf, const char *fmt, ...)
 {
 	va_list va;
 	int ret;
@@ -161,3 +160,16 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
 
 	return ret;
 }
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+	va_list va;
+	int ret;
+
+	va_start(va, fmt);
+	ret = sprintf(buf, fmt, va);
+	va_end(va);
+
+	return ret;
+}
-- 
cgit v0.10.2


From e68df9994eaa6bdb81d9dac11a0c0b799416c91e Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 31 May 2016 23:12:47 +0200
Subject: ARM: omap: Enable tiny printf on omap3_logic

Enable support for tiny printf on the omap3_logic board to trim down
the SPL size. This makes the SPL actually build again and fit into
the SRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: lesne@alse-fr.com
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 3226247..e7bf385 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
-- 
cgit v0.10.2


From 66020a67c18ff78e1ca25d9ffeebab0b91d064a7 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:36 +0200
Subject: arm: config: Introduce CONFIG_SYS_ARM_ARCH

Introduce new helper Kconfig option, which is automatically set to
the version of ARM architecture for which the U-Boot is built. This
is useful when selecting tuning options in the libgcc imported from
Linux kernel.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e5463d2..77eab66 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,20 @@ config SYS_CPU
         default "sa1100" if CPU_SA1100
 	default "armv8" if ARM64
 
+config SYS_ARM_ARCH
+	int
+	default 4 if CPU_ARM720T
+	default 4 if CPU_ARM920T
+	default 5 if CPU_ARM926EJS
+	default 5 if CPU_ARM946ES
+	default 6 if CPU_ARM1136
+	default 6 if CPU_ARM1176
+	default 7 if CPU_V7
+	default 7 if CPU_V7M
+	default 5 if CPU_PXA
+	default 4 if CPU_SA1100
+	default 8 if ARM64
+
 config SEMIHOSTING
 	bool "support boot from semihosting"
 	help
-- 
cgit v0.10.2


From c0db6f8d202a4f9a926c4f5792e1eefb774356e1 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:37 +0200
Subject: arm: include: Import unified.h from Linux kernel

Import unified.h from Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains
macros used in libgcc functions in Linux kernel on ARM and will be
needed for the libgcc sync.

Since unified.h defines the W(instr) macro, we must drop this from
the macro from memcpy.S , otherwise this triggers a warning about
symbol redefinition. In order to keep the changes to unified.h to
the minimum, tweak arch/arm/lib/Makefile such that it defines the
CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all
of the assembler files. This is mandatory.

Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and
only if Thumb2 build is enabled. This macro is checked by unified.h
and toggles between ARM and Thumb2 variant of the instructions in the
assembler source files.

Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the
new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between
more optimal and more dense codepaths which work on armv5 and newer
and less optimal codepaths which work on armv4 and possible armv3m.
Tegra2 needs the same special handling as it does in arch/arm/Makefile
to cater for the arm720t boot core.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 11b80fb..ae1e42f 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -15,6 +15,7 @@
  */
 
 #include <config.h>
+#include <asm/unified.h>
 
 /*
  * Endian independent macros for shifting bytes within registers.
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 0000000..1b26002
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,129 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+	.syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...)	x
+#else
+#define AR_CLASS(x...)	x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE	PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)	x
+#ifdef __ASSEMBLY__
+#define W(instr)	instr.w
+#else
+#define WASM(instr)	#instr ".w"
+#endif
+
+#else	/* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE	0
+
+#define ARM(x...)	x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr)	instr
+#else
+#define WASM(instr)	#instr
+#endif
+
+#endif	/* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+	.macro	it, cond
+	.endm
+	.macro	itt, cond
+	.endm
+	.macro	ite, cond
+	.endm
+	.macro	ittt, cond
+	.endm
+	.macro	itte, cond
+	.endm
+	.macro	itet, cond
+	.endm
+	.macro	itee, cond
+	.endm
+	.macro	itttt, cond
+	.endm
+	.macro	ittte, cond
+	.endm
+	.macro	ittet, cond
+	.endm
+	.macro	ittee, cond
+	.endm
+	.macro	itett, cond
+	.endm
+	.macro	itete, cond
+	.endm
+	.macro	iteet, cond
+	.endm
+	.macro	iteee, cond
+	.endm
+#else	/* !__ASSEMBLY__ */
+__asm__(
+"	.macro	it, cond\n"
+"	.endm\n"
+"	.macro	itt, cond\n"
+"	.endm\n"
+"	.macro	ite, cond\n"
+"	.endm\n"
+"	.macro	ittt, cond\n"
+"	.endm\n"
+"	.macro	itte, cond\n"
+"	.endm\n"
+"	.macro	itet, cond\n"
+"	.endm\n"
+"	.macro	itee, cond\n"
+"	.endm\n"
+"	.macro	itttt, cond\n"
+"	.endm\n"
+"	.macro	ittte, cond\n"
+"	.endm\n"
+"	.macro	ittet, cond\n"
+"	.endm\n"
+"	.macro	ittee, cond\n"
+"	.endm\n"
+"	.macro	itett, cond\n"
+"	.endm\n"
+"	.macro	itete, cond\n"
+"	.endm\n"
+"	.macro	iteet, cond\n"
+"	.endm\n"
+"	.macro	iteee, cond\n"
+"	.endm\n");
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* CONFIG_ARM_ASM_UNIFIED */
+
+#endif	/* !__ASM_UNIFIED_H */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index b535dbe..49adce3 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -62,9 +62,17 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
 endif
 
+asflags-y += -DCONFIG_ARM_ASM_UNIFIED
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+asflags-y += -D__LINUX_ARM_ARCH__=4
+else
+asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
 # some files can only build in ARM or THUMB2, not THUMB1
 
 ifdef CONFIG_SYS_THUMB_BUILD
+asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL
 ifndef CONFIG_HAS_THUMB2
 
 # for C files, just apend -marm, which will override previous -mthumb*
@@ -82,6 +90,5 @@ AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
 AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
 AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
 AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
-
 endif
 endif
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 7d9fc0f..00602e9 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,12 +13,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
-#define W(instr)	instr.w
-#else
-#define W(instr)	instr
-#endif
-
 #define LDR1W_SHIFT	0
 #define STR1W_SHIFT	0
 
-- 
cgit v0.10.2


From 11b1a9b2c0fecb7334ccb23f29200da0be0cc156 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:38 +0200
Subject: arm: lib: Drop underscore from private libgcc filenames

Drop the underscore from the filenames of files implementing libgcc
routines. There is no functional change. This change is done to make
sync with Linux kernel easier.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 49adce3..f54ce8c 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
-			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
-			_uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o divsi3.o \
+			lshrdi3.o modsi3.o udivsi3.o umodsi3.o div0.o \
+			uldivmod.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/_ashldi3.S
deleted file mode 100644
index 9c34c21..0000000
--- a/arch/arm/lib/_ashldi3.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
-   Free Software Foundation, Inc.
-
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __ashldi3
-__ashldi3:
-ENTRY(__aeabi_llsl)
-
-	subs	r3, r2, #32
-	rsb	ip, r2, #32
-	movmi	ah, ah, lsl r2
-	movpl	ah, al, lsl r3
-	orrmi	ah, ah, al, lsr ip
-	mov	al, al, lsl r2
-	mov	pc, lr
-ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S
deleted file mode 100644
index c74fd64..0000000
--- a/arch/arm/lib/_ashrdi3.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
-   Free Software Foundation, Inc.
-
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __ashrdi3
-__ashrdi3:
-ENTRY(__aeabi_lasr)
-
-	subs	r3, r2, #32
-	rsb	ip, r2, #32
-	movmi	al, al, lsr r2
-	movpl	al, ah, asr r3
-	orrmi	al, al, ah, lsl ip
-	mov	ah, ah, asr r2
-	mov	pc, lr
-ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S
deleted file mode 100644
index c463c68..0000000
--- a/arch/arm/lib/_divsi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\curbit, \divisor
-	clz	\result, \dividend
-	sub	\result, \curbit, \result
-	mov	\curbit, #1
-	mov	\divisor, \divisor, lsl \result
-	mov	\curbit, \curbit, lsl \result
-	mov	\result, #0
-
-#else
-
-	@ Initially shift the divisor left 3 bits if possible,
-	@ set curbit accordingly.  This allows for curbit to be located
-	@ at the left end of each 4 bit nibbles in the division loop
-	@ to save one loop in most cases.
-	tst	\divisor, #0xe0000000
-	moveq	\divisor, \divisor, lsl #3
-	moveq	\curbit, #8
-	movne	\curbit, #1
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	movlo	\curbit, \curbit, lsl #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	movlo	\curbit, \curbit, lsl #1
-	blo	1b
-
-	mov	\result, #0
-
-#endif
-
-	@ Division loop
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	orrhs	\result,   \result,   \curbit
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	orrhs	\result,   \result,   \curbit,  lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	orrhs	\result,   \result,   \curbit,  lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	orrhs	\result,   \result,   \curbit,  lsr #3
-	cmp	\dividend, #0			@ Early termination?
-	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
-	movne	\divisor,  \divisor, lsr #4
-	bne	1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	rsb	\order, \order, #31
-
-#else
-
-	cmp	\divisor, #(1 << 16)
-	movhs	\divisor, \divisor, lsr #16
-	movhs	\order, #16
-	movlo	\order, #0
-
-	cmp	\divisor, #(1 << 8)
-	movhs	\divisor, \divisor, lsr #8
-	addhs	\order, \order, #8
-
-	cmp	\divisor, #(1 << 4)
-	movhs	\divisor, \divisor, lsr #4
-	addhs	\order, \order, #4
-
-	cmp	\divisor, #(1 << 2)
-	addhi	\order, \order, #3
-	addls	\order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
-	.align	5
-.globl __divsi3
-__divsi3:
-ENTRY(__aeabi_idiv)
-	cmp	r1, #0
-	eor	ip, r0, r1			@ save the sign of the result.
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	subs	r2, r1, #1			@ division by 1 or -1 ?
-	beq	10f
-	movs	r3, r0
-	rsbmi	r3, r0, #0			@ positive dividend value
-	cmp	r3, r1
-	bls	11f
-	tst	r1, r2				@ divisor is power of 2 ?
-	beq	12f
-
-	ARM_DIV_BODY r3, r1, r0, r2
-
-	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-10:	teq	ip, r0				@ same sign ?
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-11:	movlo	r0, #0
-	moveq	r0, ip, asr #31
-	orreq	r0, r0, #1
-	mov	pc, lr
-
-12:	ARM_DIV2_ORDER r1, r2
-
-	cmp	ip, #0
-	mov	r0, r3, lsr r2
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
-ENDPROC(__aeabi_idiv)
diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S
deleted file mode 100644
index 1f9b916..0000000
--- a/arch/arm/lib/_lshrdi3.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
-   Free Software Foundation, Inc.
-
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-#ifdef __ARMEB__
-#define al r1
-#define ah r0
-#else
-#define al r0
-#define ah r1
-#endif
-
-.globl __lshrdi3
-__lshrdi3:
-ENTRY(__aeabi_llsr)
-
-	subs	r3, r2, #32
-	rsb	ip, r2, #32
-	movmi	al, al, lsr r2
-	movpl	al, ah, lsr r3
-	orrmi	al, al, ah, lsl ip
-	mov	ah, ah, lsr r2
-	mov	pc, lr
-ENDPROC(__aeabi_llsr)
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S
deleted file mode 100644
index c5e1c22..0000000
--- a/arch/arm/lib/_modsi3.S
+++ /dev/null
@@ -1,99 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	clz	\spare, \dividend
-	sub	\order, \order, \spare
-	mov	\divisor, \divisor, lsl \order
-
-#else
-
-	mov	\order, #0
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	addlo	\order, \order, #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	addlo	\order, \order, #1
-	blo	1b
-
-#endif
-
-	@ Perform all needed substractions to keep only the reminder.
-	@ Do comparisons in batch of 4 first.
-	subs	\order, \order, #3		@ yes, 3 is intended here
-	blt	2f
-
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	cmp	\dividend, #1
-	mov	\divisor, \divisor, lsr #4
-	subges	\order, \order, #4
-	bge	1b
-
-	tst	\order, #3
-	teqne	\dividend, #0
-	beq	5f
-
-	@ Either 1, 2 or 3 comparison/substractions are left.
-2:	cmn	\order, #2
-	blt	4f
-	beq	3f
-	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-3:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-4:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-5:
-.endm
-
-	.align	5
-ENTRY(__modsi3)
-	cmp	r1, #0
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	movs	ip, r0				@ preserve sign of dividend
-	rsbmi	r0, r0, #0			@ if negative make positive
-	subs	r2, r1, #1			@ compare divisor with 1
-	cmpne	r0, r1				@ compare dividend with divisor
-	moveq	r0, #0
-	tsthi	r1, r2				@ see if divisor is power of 2
-	andeq	r0, r0, r2
-	bls	10f
-
-	ARM_MOD_BODY r0, r1, r2, r3
-
-10:	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-ENDPROC(__modsi3)
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S
deleted file mode 100644
index 3b653be..0000000
--- a/arch/arm/lib/_udivsi3.S
+++ /dev/null
@@ -1,95 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend	.req	r0
-divisor		.req	r1
-result		.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __udivsi3
-	.type	__udivsi3 ,function
-	.globl	__aeabi_uidiv
-	.type	__aeabi_uidiv ,function
-	.align	0
- __udivsi3:
- __aeabi_uidiv:
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	mov	result, #0
-	cmp	dividend, divisor
-	bcc	Lgot_result
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions, and note which bits
-	@ are done in the result.  On the final pass, this may subtract
-	@ too much from the dividend, but the result will be ok, since the
-	@ "bit" will have been shifted out at the bottom.
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	orrcs	result, result, curbit
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	result, result, curbit, lsr #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	result, result, curbit, lsr #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	result, result, curbit, lsr #3
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-Lgot_result:
-	mov	r0, result
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __udivsi3       , . -  __udivsi3
-
-ENTRY(__aeabi_uidivmod)
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_uidiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-ENDPROC(__aeabi_uidivmod)
-
-ENTRY(__aeabi_idivmod)
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_idiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-ENDPROC(__aeabi_idivmod)
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/_uldivmod.S
deleted file mode 100644
index 426c2f2..0000000
--- a/arch/arm/lib/_uldivmod.S
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Copyright 2010, Google Inc.
- *
- * Brought in from coreboot uldivmod.S
- *
- * SPDX-License-Identifier:     GPL-2.0
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-/* We don't use Thumb instructions for now */
-#define ARM(x...)	x
-#define THUMB(x...)
-
-/*
- * A, Q = r0 + (r1 << 32)
- * B, R = r2 + (r3 << 32)
- * A / B = Q ... R
- */
-
-A_0	.req	r0
-A_1	.req	r1
-B_0	.req	r2
-B_1	.req	r3
-C_0	.req	r4
-C_1	.req	r5
-D_0	.req	r6
-D_1	.req	r7
-
-Q_0	.req	r0
-Q_1	.req	r1
-R_0	.req	r2
-R_1	.req	r3
-
-THUMB(
-TMP	.req	r8
-)
-
-ENTRY(__aeabi_uldivmod)
-	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
-	@ Test if B == 0
-	orrs	ip, B_0, B_1		@ Z set -> B == 0
-	beq	L_div_by_0
-	@ Test if B is power of 2: (B & (B - 1)) == 0
-	subs	C_0, B_0, #1
-	sbc	C_1, B_1, #0
-	tst	C_0, B_0
-	tsteq	B_1, C_1
-	beq	L_pow2
-	@ Test if A_1 == B_1 == 0
-	orrs	ip, A_1, B_1
-	beq	L_div_32_32
-
-L_div_64_64:
-/* CLZ only exists in ARM architecture version 5 and above. */
-#ifdef HAVE_CLZ
-	mov	C_0, #1
-	mov	C_1, #0
-	@ D_0 = clz A
-	teq	A_1, #0
-	clz	D_0, A_1
-	clzeq	ip, A_0
-	addeq	D_0, D_0, ip
-	@ D_1 = clz B
-	teq	B_1, #0
-	clz	D_1, B_1
-	clzeq	ip, B_0
-	addeq	D_1, D_1, ip
-	@ if clz B - clz A > 0
-	subs	D_0, D_1, D_0
-	bls	L_done_shift
-	@ B <<= (clz B - clz A)
-	subs	D_1, D_0, #32
-	rsb	ip, D_0, #32
-	movmi	B_1, B_1, lsl D_0
-ARM(	orrmi	B_1, B_1, B_0, lsr ip	)
-THUMB(	lsrmi	TMP, B_0, ip		)
-THUMB(	orrmi	B_1, B_1, TMP		)
-	movpl	B_1, B_0, lsl D_1
-	mov	B_0, B_0, lsl D_0
-	@ C = 1 << (clz B - clz A)
-	movmi	C_1, C_1, lsl D_0
-ARM(	orrmi	C_1, C_1, C_0, lsr ip	)
-THUMB(	lsrmi	TMP, C_0, ip		)
-THUMB(	orrmi	C_1, C_1, TMP		)
-	movpl	C_1, C_0, lsl D_1
-	mov	C_0, C_0, lsl D_0
-L_done_shift:
-	mov	D_0, #0
-	mov	D_1, #0
-	@ C: current bit; D: result
-#else
-	@ C: current bit; D: result
-	mov	C_0, #1
-	mov	C_1, #0
-	mov	D_0, #0
-	mov	D_1, #0
-L_lsl_4:
-	cmp	B_1, #0x10000000
-	cmpcc	B_1, A_1
-	cmpeq	B_0, A_0
-	bcs	L_lsl_1
-	@ B <<= 4
-	mov	B_1, B_1, lsl #4
-	orr	B_1, B_1, B_0, lsr #28
-	mov	B_0, B_0, lsl #4
-	@ C <<= 4
-	mov	C_1, C_1, lsl #4
-	orr	C_1, C_1, C_0, lsr #28
-	mov	C_0, C_0, lsl #4
-	b	L_lsl_4
-L_lsl_1:
-	cmp	B_1, #0x80000000
-	cmpcc	B_1, A_1
-	cmpeq	B_0, A_0
-	bcs	L_subtract
-	@ B <<= 1
-	mov	B_1, B_1, lsl #1
-	orr	B_1, B_1, B_0, lsr #31
-	mov	B_0, B_0, lsl #1
-	@ C <<= 1
-	mov	C_1, C_1, lsl #1
-	orr	C_1, C_1, C_0, lsr #31
-	mov	C_0, C_0, lsl #1
-	b	L_lsl_1
-#endif
-L_subtract:
-	@ if A >= B
-	cmp	A_1, B_1
-	cmpeq	A_0, B_0
-	bcc	L_update
-	@ A -= B
-	subs	A_0, A_0, B_0
-	sbc	A_1, A_1, B_1
-	@ D |= C
-	orr	D_0, D_0, C_0
-	orr	D_1, D_1, C_1
-L_update:
-	@ if A == 0: break
-	orrs	ip, A_1, A_0
-	beq	L_exit
-	@ C >>= 1
-	movs	C_1, C_1, lsr #1
-	movs	C_0, C_0, rrx
-	@ if C == 0: break
-	orrs	ip, C_1, C_0
-	beq	L_exit
-	@ B >>= 1
-	movs	B_1, B_1, lsr #1
-	mov	B_0, B_0, rrx
-	b	L_subtract
-L_exit:
-	@ Note: A, B & Q, R are aliases
-	mov	R_0, A_0
-	mov	R_1, A_1
-	mov	Q_0, D_0
-	mov	Q_1, D_1
-	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-
-L_div_32_32:
-	@ Note:	A_0 &	r0 are aliases
-	@	Q_1	r1
-	mov	r1, B_0
-	bl	__aeabi_uidivmod
-	mov	R_0, r1
-	mov	R_1, #0
-	mov	Q_1, #0
-	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-
-L_pow2:
-#ifdef HAVE_CLZ
-	@ Note: A, B and Q, R are aliases
-	@ R = A & (B - 1)
-	and	C_0, A_0, C_0
-	and	C_1, A_1, C_1
-	@ Q = A >> log2(B)
-	@ Note: B must not be 0 here!
-	clz	D_0, B_0
-	add	D_1, D_0, #1
-	rsbs	D_0, D_0, #31
-	bpl	L_1
-	clz	D_0, B_1
-	rsb	D_0, D_0, #31
-	mov	A_0, A_1, lsr D_0
-	add	D_0, D_0, #32
-L_1:
-	movpl	A_0, A_0, lsr D_0
-ARM(	orrpl	A_0, A_0, A_1, lsl D_1	)
-THUMB(	lslpl	TMP, A_1, D_1		)
-THUMB(	orrpl	A_0, A_0, TMP		)
-	mov	A_1, A_1, lsr D_0
-	@ Mov back C to R
-	mov	R_0, C_0
-	mov	R_1, C_1
-	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-#else
-	@ Note: A, B and Q, R are aliases
-	@ R = A & (B - 1)
-	and	C_0, A_0, C_0
-	and	C_1, A_1, C_1
-	@ Q = A >> log2(B)
-	@ Note: B must not be 0 here!
-	@ Count the leading zeroes in B.
-	mov	D_0, #0
-	orrs	B_0, B_0, B_0
-	@ If B is greater than 1 << 31, divide A and B by 1 << 32.
-	moveq	A_0, A_1
-	moveq	A_1, #0
-	moveq	B_0, B_1
-	@ Count the remaining leading zeroes in B.
-	movs	B_1, B_0, lsl #16
-	addeq	D_0, #16
-	moveq	B_0, B_0, lsr #16
-	tst	B_0, #0xff
-	addeq	D_0, #8
-	moveq	B_0, B_0, lsr #8
-	tst	B_0, #0xf
-	addeq	D_0, #4
-	moveq	B_0, B_0, lsr #4
-	tst	B_0, #0x3
-	addeq	D_0, #2
-	moveq	B_0, B_0, lsr #2
-	tst	B_0, #0x1
-	addeq	D_0, #1
-	@ Shift A to the right by the appropriate amount.
-	rsb	D_1, D_0, #32
-	mov	Q_0, A_0, lsr D_0
-	orr	Q_0, A_1, lsl D_1
-	mov	Q_1, A_1, lsr D_0
-	@ Move C to R
-	mov	R_0, C_0
-	mov	R_1, C_1
-	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-#endif
-
-L_div_by_0:
-	bl	__div0
-	@ As wrong as it could be
-	mov	Q_0, #0
-	mov	Q_1, #0
-	mov	R_0, #0
-	mov	R_1, #0
-	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-ENDPROC(__aeabi_uldivmod)
diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S
deleted file mode 100644
index b166737..0000000
--- a/arch/arm/lib/_umodsi3.S
+++ /dev/null
@@ -1,90 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend	.req	r0
-divisor		.req	r1
-overdone	.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.type  __umodsi3       ,function
-	.align 0
- ENTRY(__umodsi3)
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	cmp	dividend, divisor
-	movcc	pc, lr
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions.  On the final pass, this may
-	@ subtract too much from the dividend, so keep track of which
-	@ subtractions are done, we can fix them up afterwards...
-	mov	overdone, #0
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	overdone, overdone, curbit, ror #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	overdone, overdone, curbit, ror #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	overdone, overdone, curbit, ror #3
-	mov	ip, curbit
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-	@ Any subtractions that we should not have done will be recorded in
-	@ the top three bits of "overdone".  Exactly which were not needed
-	@ are governed by the position of the bit, stored in ip.
-	@ If we terminated early, because dividend became zero,
-	@ then none of the below will match, since the bit in ip will not be
-	@ in the bottom nibble.
-	ands	overdone, overdone, #0xe0000000
-	moveq	pc, lr				@ No fixups needed
-	tst	overdone, ip, ror #3
-	addne	dividend, dividend, divisor, lsr #3
-	tst	overdone, ip, ror #2
-	addne	dividend, dividend, divisor, lsr #2
-	tst	overdone, ip, ror #1
-	addne	dividend, dividend, divisor, lsr #1
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __umodsi3       , . -  __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
-ENDPROC(__umodsi3)
diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
new file mode 100644
index 0000000..9c34c21
--- /dev/null
+++ b/arch/arm/lib/ashldi3.S
@@ -0,0 +1,28 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __ashldi3
+__ashldi3:
+ENTRY(__aeabi_llsl)
+
+	subs	r3, r2, #32
+	rsb	ip, r2, #32
+	movmi	ah, ah, lsl r2
+	movpl	ah, al, lsl r3
+	orrmi	ah, ah, al, lsr ip
+	mov	al, al, lsl r2
+	mov	pc, lr
+ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
new file mode 100644
index 0000000..c74fd64
--- /dev/null
+++ b/arch/arm/lib/ashrdi3.S
@@ -0,0 +1,28 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __ashrdi3
+__ashrdi3:
+ENTRY(__aeabi_lasr)
+
+	subs	r3, r2, #32
+	rsb	ip, r2, #32
+	movmi	al, al, lsr r2
+	movpl	al, ah, asr r3
+	orrmi	al, al, ah, lsl ip
+	mov	ah, ah, asr r2
+	mov	pc, lr
+ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/divsi3.S b/arch/arm/lib/divsi3.S
new file mode 100644
index 0000000..c463c68
--- /dev/null
+++ b/arch/arm/lib/divsi3.S
@@ -0,0 +1,143 @@
+#include <linux/linkage.h>
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\curbit, \divisor
+	clz	\result, \dividend
+	sub	\result, \curbit, \result
+	mov	\curbit, #1
+	mov	\divisor, \divisor, lsl \result
+	mov	\curbit, \curbit, lsl \result
+	mov	\result, #0
+
+#else
+
+	@ Initially shift the divisor left 3 bits if possible,
+	@ set curbit accordingly.  This allows for curbit to be located
+	@ at the left end of each 4 bit nibbles in the division loop
+	@ to save one loop in most cases.
+	tst	\divisor, #0xe0000000
+	moveq	\divisor, \divisor, lsl #3
+	moveq	\curbit, #8
+	movne	\curbit, #1
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	movlo	\curbit, \curbit, lsl #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	movlo	\curbit, \curbit, lsl #1
+	blo	1b
+
+	mov	\result, #0
+
+#endif
+
+	@ Division loop
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	orrhs	\result,   \result,   \curbit
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	orrhs	\result,   \result,   \curbit,  lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	orrhs	\result,   \result,   \curbit,  lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	orrhs	\result,   \result,   \curbit,  lsr #3
+	cmp	\dividend, #0			@ Early termination?
+	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+	movne	\divisor,  \divisor, lsr #4
+	bne	1b
+
+.endm
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	rsb	\order, \order, #31
+
+#else
+
+	cmp	\divisor, #(1 << 16)
+	movhs	\divisor, \divisor, lsr #16
+	movhs	\order, #16
+	movlo	\order, #0
+
+	cmp	\divisor, #(1 << 8)
+	movhs	\divisor, \divisor, lsr #8
+	addhs	\order, \order, #8
+
+	cmp	\divisor, #(1 << 4)
+	movhs	\divisor, \divisor, lsr #4
+	addhs	\order, \order, #4
+
+	cmp	\divisor, #(1 << 2)
+	addhi	\order, \order, #3
+	addls	\order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+	.align	5
+.globl __divsi3
+__divsi3:
+ENTRY(__aeabi_idiv)
+	cmp	r1, #0
+	eor	ip, r0, r1			@ save the sign of the result.
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	subs	r2, r1, #1			@ division by 1 or -1 ?
+	beq	10f
+	movs	r3, r0
+	rsbmi	r3, r0, #0			@ positive dividend value
+	cmp	r3, r1
+	bls	11f
+	tst	r1, r2				@ divisor is power of 2 ?
+	beq	12f
+
+	ARM_DIV_BODY r3, r1, r0, r2
+
+	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+10:	teq	ip, r0				@ same sign ?
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+11:	movlo	r0, #0
+	moveq	r0, ip, asr #31
+	orreq	r0, r0, #1
+	mov	pc, lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	cmp	ip, #0
+	mov	r0, r3, lsr r2
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+Ldiv0:
+
+	str	lr, [sp, #-4]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #4
+ENDPROC(__aeabi_idiv)
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
new file mode 100644
index 0000000..1f9b916
--- /dev/null
+++ b/arch/arm/lib/lshrdi3.S
@@ -0,0 +1,28 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __lshrdi3
+__lshrdi3:
+ENTRY(__aeabi_llsr)
+
+	subs	r3, r2, #32
+	rsb	ip, r2, #32
+	movmi	al, al, lsr r2
+	movpl	al, ah, lsr r3
+	orrmi	al, al, ah, lsl ip
+	mov	ah, ah, lsr r2
+	mov	pc, lr
+ENDPROC(__aeabi_llsr)
diff --git a/arch/arm/lib/modsi3.S b/arch/arm/lib/modsi3.S
new file mode 100644
index 0000000..c5e1c22
--- /dev/null
+++ b/arch/arm/lib/modsi3.S
@@ -0,0 +1,99 @@
+#include <linux/linkage.h>
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	clz	\spare, \dividend
+	sub	\order, \order, \spare
+	mov	\divisor, \divisor, lsl \order
+
+#else
+
+	mov	\order, #0
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	addlo	\order, \order, #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	addlo	\order, \order, #1
+	blo	1b
+
+#endif
+
+	@ Perform all needed substractions to keep only the reminder.
+	@ Do comparisons in batch of 4 first.
+	subs	\order, \order, #3		@ yes, 3 is intended here
+	blt	2f
+
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	cmp	\dividend, #1
+	mov	\divisor, \divisor, lsr #4
+	subges	\order, \order, #4
+	bge	1b
+
+	tst	\order, #3
+	teqne	\dividend, #0
+	beq	5f
+
+	@ Either 1, 2 or 3 comparison/substractions are left.
+2:	cmn	\order, #2
+	blt	4f
+	beq	3f
+	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+3:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+4:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+5:
+.endm
+
+	.align	5
+ENTRY(__modsi3)
+	cmp	r1, #0
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	movs	ip, r0				@ preserve sign of dividend
+	rsbmi	r0, r0, #0			@ if negative make positive
+	subs	r2, r1, #1			@ compare divisor with 1
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq	r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	bls	10f
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+10:	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+ENDPROC(__modsi3)
+
+Ldiv0:
+
+	str	lr, [sp, #-4]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #4
diff --git a/arch/arm/lib/udivsi3.S b/arch/arm/lib/udivsi3.S
new file mode 100644
index 0000000..3b653be
--- /dev/null
+++ b/arch/arm/lib/udivsi3.S
@@ -0,0 +1,95 @@
+#include <linux/linkage.h>
+
+/* # 1 "libgcc1.S" */
+@ libgcc1 routines for ARM cpu.
+@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
+dividend	.req	r0
+divisor		.req	r1
+result		.req	r2
+curbit		.req	r3
+/* ip		.req	r12	*/
+/* sp		.req	r13	*/
+/* lr		.req	r14	*/
+/* pc		.req	r15	*/
+	.text
+	.globl	 __udivsi3
+	.type	__udivsi3 ,function
+	.globl	__aeabi_uidiv
+	.type	__aeabi_uidiv ,function
+	.align	0
+ __udivsi3:
+ __aeabi_uidiv:
+	cmp	divisor, #0
+	beq	Ldiv0
+	mov	curbit, #1
+	mov	result, #0
+	cmp	dividend, divisor
+	bcc	Lgot_result
+Loop1:
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+	cmp	divisor, #0x10000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #4
+	movcc	curbit, curbit, lsl #4
+	bcc	Loop1
+Lbignum:
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+	cmp	divisor, #0x80000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #1
+	movcc	curbit, curbit, lsl #1
+	bcc	Lbignum
+Loop3:
+	@ Test for possible subtractions, and note which bits
+	@ are done in the result.  On the final pass, this may subtract
+	@ too much from the dividend, but the result will be ok, since the
+	@ "bit" will have been shifted out at the bottom.
+	cmp	dividend, divisor
+	subcs	dividend, dividend, divisor
+	orrcs	result, result, curbit
+	cmp	dividend, divisor, lsr #1
+	subcs	dividend, dividend, divisor, lsr #1
+	orrcs	result, result, curbit, lsr #1
+	cmp	dividend, divisor, lsr #2
+	subcs	dividend, dividend, divisor, lsr #2
+	orrcs	result, result, curbit, lsr #2
+	cmp	dividend, divisor, lsr #3
+	subcs	dividend, dividend, divisor, lsr #3
+	orrcs	result, result, curbit, lsr #3
+	cmp	dividend, #0			@ Early termination?
+	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
+	movne	divisor, divisor, lsr #4
+	bne	Loop3
+Lgot_result:
+	mov	r0, result
+	mov	pc, lr
+Ldiv0:
+	str	lr, [sp, #-4]!
+	bl	 __div0       (PLT)
+	mov	r0, #0			@ about as wrong as it could be
+	ldmia	sp!, {pc}
+	.size  __udivsi3       , . -  __udivsi3
+
+ENTRY(__aeabi_uidivmod)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_uidiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	mov	pc, lr
+ENDPROC(__aeabi_uidivmod)
+
+ENTRY(__aeabi_idivmod)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_idiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	mov	pc, lr
+ENDPROC(__aeabi_idivmod)
diff --git a/arch/arm/lib/uldivmod.S b/arch/arm/lib/uldivmod.S
new file mode 100644
index 0000000..426c2f2
--- /dev/null
+++ b/arch/arm/lib/uldivmod.S
@@ -0,0 +1,245 @@
+/*
+ * Copyright 2010, Google Inc.
+ *
+ * Brought in from coreboot uldivmod.S
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/* We don't use Thumb instructions for now */
+#define ARM(x...)	x
+#define THUMB(x...)
+
+/*
+ * A, Q = r0 + (r1 << 32)
+ * B, R = r2 + (r3 << 32)
+ * A / B = Q ... R
+ */
+
+A_0	.req	r0
+A_1	.req	r1
+B_0	.req	r2
+B_1	.req	r3
+C_0	.req	r4
+C_1	.req	r5
+D_0	.req	r6
+D_1	.req	r7
+
+Q_0	.req	r0
+Q_1	.req	r1
+R_0	.req	r2
+R_1	.req	r3
+
+THUMB(
+TMP	.req	r8
+)
+
+ENTRY(__aeabi_uldivmod)
+	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
+	@ Test if B == 0
+	orrs	ip, B_0, B_1		@ Z set -> B == 0
+	beq	L_div_by_0
+	@ Test if B is power of 2: (B & (B - 1)) == 0
+	subs	C_0, B_0, #1
+	sbc	C_1, B_1, #0
+	tst	C_0, B_0
+	tsteq	B_1, C_1
+	beq	L_pow2
+	@ Test if A_1 == B_1 == 0
+	orrs	ip, A_1, B_1
+	beq	L_div_32_32
+
+L_div_64_64:
+/* CLZ only exists in ARM architecture version 5 and above. */
+#ifdef HAVE_CLZ
+	mov	C_0, #1
+	mov	C_1, #0
+	@ D_0 = clz A
+	teq	A_1, #0
+	clz	D_0, A_1
+	clzeq	ip, A_0
+	addeq	D_0, D_0, ip
+	@ D_1 = clz B
+	teq	B_1, #0
+	clz	D_1, B_1
+	clzeq	ip, B_0
+	addeq	D_1, D_1, ip
+	@ if clz B - clz A > 0
+	subs	D_0, D_1, D_0
+	bls	L_done_shift
+	@ B <<= (clz B - clz A)
+	subs	D_1, D_0, #32
+	rsb	ip, D_0, #32
+	movmi	B_1, B_1, lsl D_0
+ARM(	orrmi	B_1, B_1, B_0, lsr ip	)
+THUMB(	lsrmi	TMP, B_0, ip		)
+THUMB(	orrmi	B_1, B_1, TMP		)
+	movpl	B_1, B_0, lsl D_1
+	mov	B_0, B_0, lsl D_0
+	@ C = 1 << (clz B - clz A)
+	movmi	C_1, C_1, lsl D_0
+ARM(	orrmi	C_1, C_1, C_0, lsr ip	)
+THUMB(	lsrmi	TMP, C_0, ip		)
+THUMB(	orrmi	C_1, C_1, TMP		)
+	movpl	C_1, C_0, lsl D_1
+	mov	C_0, C_0, lsl D_0
+L_done_shift:
+	mov	D_0, #0
+	mov	D_1, #0
+	@ C: current bit; D: result
+#else
+	@ C: current bit; D: result
+	mov	C_0, #1
+	mov	C_1, #0
+	mov	D_0, #0
+	mov	D_1, #0
+L_lsl_4:
+	cmp	B_1, #0x10000000
+	cmpcc	B_1, A_1
+	cmpeq	B_0, A_0
+	bcs	L_lsl_1
+	@ B <<= 4
+	mov	B_1, B_1, lsl #4
+	orr	B_1, B_1, B_0, lsr #28
+	mov	B_0, B_0, lsl #4
+	@ C <<= 4
+	mov	C_1, C_1, lsl #4
+	orr	C_1, C_1, C_0, lsr #28
+	mov	C_0, C_0, lsl #4
+	b	L_lsl_4
+L_lsl_1:
+	cmp	B_1, #0x80000000
+	cmpcc	B_1, A_1
+	cmpeq	B_0, A_0
+	bcs	L_subtract
+	@ B <<= 1
+	mov	B_1, B_1, lsl #1
+	orr	B_1, B_1, B_0, lsr #31
+	mov	B_0, B_0, lsl #1
+	@ C <<= 1
+	mov	C_1, C_1, lsl #1
+	orr	C_1, C_1, C_0, lsr #31
+	mov	C_0, C_0, lsl #1
+	b	L_lsl_1
+#endif
+L_subtract:
+	@ if A >= B
+	cmp	A_1, B_1
+	cmpeq	A_0, B_0
+	bcc	L_update
+	@ A -= B
+	subs	A_0, A_0, B_0
+	sbc	A_1, A_1, B_1
+	@ D |= C
+	orr	D_0, D_0, C_0
+	orr	D_1, D_1, C_1
+L_update:
+	@ if A == 0: break
+	orrs	ip, A_1, A_0
+	beq	L_exit
+	@ C >>= 1
+	movs	C_1, C_1, lsr #1
+	movs	C_0, C_0, rrx
+	@ if C == 0: break
+	orrs	ip, C_1, C_0
+	beq	L_exit
+	@ B >>= 1
+	movs	B_1, B_1, lsr #1
+	mov	B_0, B_0, rrx
+	b	L_subtract
+L_exit:
+	@ Note: A, B & Q, R are aliases
+	mov	R_0, A_0
+	mov	R_1, A_1
+	mov	Q_0, D_0
+	mov	Q_1, D_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_div_32_32:
+	@ Note:	A_0 &	r0 are aliases
+	@	Q_1	r1
+	mov	r1, B_0
+	bl	__aeabi_uidivmod
+	mov	R_0, r1
+	mov	R_1, #0
+	mov	Q_1, #0
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_pow2:
+#ifdef HAVE_CLZ
+	@ Note: A, B and Q, R are aliases
+	@ R = A & (B - 1)
+	and	C_0, A_0, C_0
+	and	C_1, A_1, C_1
+	@ Q = A >> log2(B)
+	@ Note: B must not be 0 here!
+	clz	D_0, B_0
+	add	D_1, D_0, #1
+	rsbs	D_0, D_0, #31
+	bpl	L_1
+	clz	D_0, B_1
+	rsb	D_0, D_0, #31
+	mov	A_0, A_1, lsr D_0
+	add	D_0, D_0, #32
+L_1:
+	movpl	A_0, A_0, lsr D_0
+ARM(	orrpl	A_0, A_0, A_1, lsl D_1	)
+THUMB(	lslpl	TMP, A_1, D_1		)
+THUMB(	orrpl	A_0, A_0, TMP		)
+	mov	A_1, A_1, lsr D_0
+	@ Mov back C to R
+	mov	R_0, C_0
+	mov	R_1, C_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#else
+	@ Note: A, B and Q, R are aliases
+	@ R = A & (B - 1)
+	and	C_0, A_0, C_0
+	and	C_1, A_1, C_1
+	@ Q = A >> log2(B)
+	@ Note: B must not be 0 here!
+	@ Count the leading zeroes in B.
+	mov	D_0, #0
+	orrs	B_0, B_0, B_0
+	@ If B is greater than 1 << 31, divide A and B by 1 << 32.
+	moveq	A_0, A_1
+	moveq	A_1, #0
+	moveq	B_0, B_1
+	@ Count the remaining leading zeroes in B.
+	movs	B_1, B_0, lsl #16
+	addeq	D_0, #16
+	moveq	B_0, B_0, lsr #16
+	tst	B_0, #0xff
+	addeq	D_0, #8
+	moveq	B_0, B_0, lsr #8
+	tst	B_0, #0xf
+	addeq	D_0, #4
+	moveq	B_0, B_0, lsr #4
+	tst	B_0, #0x3
+	addeq	D_0, #2
+	moveq	B_0, B_0, lsr #2
+	tst	B_0, #0x1
+	addeq	D_0, #1
+	@ Shift A to the right by the appropriate amount.
+	rsb	D_1, D_0, #32
+	mov	Q_0, A_0, lsr D_0
+	orr	Q_0, A_1, lsl D_1
+	mov	Q_1, A_1, lsr D_0
+	@ Move C to R
+	mov	R_0, C_0
+	mov	R_1, C_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#endif
+
+L_div_by_0:
+	bl	__div0
+	@ As wrong as it could be
+	mov	Q_0, #0
+	mov	Q_1, #0
+	mov	R_0, #0
+	mov	R_1, #0
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+ENDPROC(__aeabi_uldivmod)
diff --git a/arch/arm/lib/umodsi3.S b/arch/arm/lib/umodsi3.S
new file mode 100644
index 0000000..b166737
--- /dev/null
+++ b/arch/arm/lib/umodsi3.S
@@ -0,0 +1,90 @@
+#include <linux/linkage.h>
+
+/* # 1 "libgcc1.S" */
+@ libgcc1 routines for ARM cpu.
+@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
+/* # 145 "libgcc1.S" */
+dividend	.req	r0
+divisor		.req	r1
+overdone	.req	r2
+curbit		.req	r3
+/* ip		.req	r12	*/
+/* sp		.req	r13	*/
+/* lr		.req	r14	*/
+/* pc		.req	r15	*/
+	.text
+	.type  __umodsi3       ,function
+	.align 0
+ ENTRY(__umodsi3)
+	cmp	divisor, #0
+	beq	Ldiv0
+	mov	curbit, #1
+	cmp	dividend, divisor
+	movcc	pc, lr
+Loop1:
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+	cmp	divisor, #0x10000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #4
+	movcc	curbit, curbit, lsl #4
+	bcc	Loop1
+Lbignum:
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+	cmp	divisor, #0x80000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #1
+	movcc	curbit, curbit, lsl #1
+	bcc	Lbignum
+Loop3:
+	@ Test for possible subtractions.  On the final pass, this may
+	@ subtract too much from the dividend, so keep track of which
+	@ subtractions are done, we can fix them up afterwards...
+	mov	overdone, #0
+	cmp	dividend, divisor
+	subcs	dividend, dividend, divisor
+	cmp	dividend, divisor, lsr #1
+	subcs	dividend, dividend, divisor, lsr #1
+	orrcs	overdone, overdone, curbit, ror #1
+	cmp	dividend, divisor, lsr #2
+	subcs	dividend, dividend, divisor, lsr #2
+	orrcs	overdone, overdone, curbit, ror #2
+	cmp	dividend, divisor, lsr #3
+	subcs	dividend, dividend, divisor, lsr #3
+	orrcs	overdone, overdone, curbit, ror #3
+	mov	ip, curbit
+	cmp	dividend, #0			@ Early termination?
+	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
+	movne	divisor, divisor, lsr #4
+	bne	Loop3
+	@ Any subtractions that we should not have done will be recorded in
+	@ the top three bits of "overdone".  Exactly which were not needed
+	@ are governed by the position of the bit, stored in ip.
+	@ If we terminated early, because dividend became zero,
+	@ then none of the below will match, since the bit in ip will not be
+	@ in the bottom nibble.
+	ands	overdone, overdone, #0xe0000000
+	moveq	pc, lr				@ No fixups needed
+	tst	overdone, ip, ror #3
+	addne	dividend, dividend, divisor, lsr #3
+	tst	overdone, ip, ror #2
+	addne	dividend, dividend, divisor, lsr #2
+	tst	overdone, ip, ror #1
+	addne	dividend, dividend, divisor, lsr #1
+	mov	pc, lr
+Ldiv0:
+	str	lr, [sp, #-4]!
+	bl	 __div0       (PLT)
+	mov	r0, #0			@ about as wrong as it could be
+	ldmia	sp!, {pc}
+	.size  __umodsi3       , . -  __umodsi3
+/* # 320 "libgcc1.S" */
+/* # 421 "libgcc1.S" */
+/* # 433 "libgcc1.S" */
+/* # 456 "libgcc1.S" */
+/* # 500 "libgcc1.S" */
+/* # 580 "libgcc1.S" */
+ENDPROC(__umodsi3)
-- 
cgit v0.10.2


From 06b36cb7752f64232e15a53864a97861de0aab7f Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:39 +0200
Subject: arm: lib: Sync libgcc shift operations

Sync the libgcc shift operations with Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three
files is easy, as there is almost no change in them, except the
addition of Thumb support.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 9c34c21..a4f5ebb 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -5,6 +5,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __ashldi3
-__ashldi3:
+ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	ah, ah, lsl r2
 	movpl	ah, al, lsl r3
-	orrmi	ah, ah, al, lsr ip
+ ARM(	orrmi	ah, ah, al, lsr ip	)
+ THUMB(	lsrmi	r3, al, ip		)
+ THUMB(	orrmi	ah, ah, r3		)
 	mov	al, al, lsl r2
-	mov	pc, lr
+	ret	lr
+
+ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index c74fd64..c6e1ed3 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __ashrdi3
-__ashrdi3:
+ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	al, al, lsr r2
 	movpl	al, ah, asr r3
-	orrmi	al, al, ah, lsl ip
+ ARM(	orrmi	al, al, ah, lsl ip	)
+ THUMB(	lslmi	r3, ah, ip		)
+ THUMB(	orrmi	al, al, r3		)
 	mov	ah, ah, asr r2
-	mov	pc, lr
+	ret	lr
+
+ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 1f9b916..9c51141 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __lshrdi3
-__lshrdi3:
+ENTRY(__lshrdi3)
 ENTRY(__aeabi_llsr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	al, al, lsr r2
 	movpl	al, ah, lsr r3
-	orrmi	al, al, ah, lsl ip
+ ARM(	orrmi	al, al, ah, lsl ip	)
+ THUMB(	lslmi	r3, ah, ip		)
+ THUMB(	orrmi	al, al, r3		)
 	mov	ah, ah, lsr r2
-	mov	pc, lr
+	ret	lr
+
+ENDPROC(__lshrdi3)
 ENDPROC(__aeabi_llsr)
-- 
cgit v0.10.2


From c5a543ea2d4bcedd87754b78babb68929cf8ab33 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:40 +0200
Subject: arm: lib: Sync libgcc 32b division/modulo operations

Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 ,
commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these
four files are present in lib1funcs.S in Linux, so replace these files
with lib1funcs.S from Linux.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro
in lib1funcs.S . Moreover, to make all of the functions available, define
CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM
EABI.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f54ce8c..a1ab297 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o divsi3.o \
-			lshrdi3.o modsi3.o udivsi3.o umodsi3.o div0.o \
-			uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
+				    lib1funcs.o uldivmod.o div0.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
diff --git a/arch/arm/lib/divsi3.S b/arch/arm/lib/divsi3.S
deleted file mode 100644
index c463c68..0000000
--- a/arch/arm/lib/divsi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\curbit, \divisor
-	clz	\result, \dividend
-	sub	\result, \curbit, \result
-	mov	\curbit, #1
-	mov	\divisor, \divisor, lsl \result
-	mov	\curbit, \curbit, lsl \result
-	mov	\result, #0
-
-#else
-
-	@ Initially shift the divisor left 3 bits if possible,
-	@ set curbit accordingly.  This allows for curbit to be located
-	@ at the left end of each 4 bit nibbles in the division loop
-	@ to save one loop in most cases.
-	tst	\divisor, #0xe0000000
-	moveq	\divisor, \divisor, lsl #3
-	moveq	\curbit, #8
-	movne	\curbit, #1
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	movlo	\curbit, \curbit, lsl #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	movlo	\curbit, \curbit, lsl #1
-	blo	1b
-
-	mov	\result, #0
-
-#endif
-
-	@ Division loop
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	orrhs	\result,   \result,   \curbit
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	orrhs	\result,   \result,   \curbit,  lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	orrhs	\result,   \result,   \curbit,  lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	orrhs	\result,   \result,   \curbit,  lsr #3
-	cmp	\dividend, #0			@ Early termination?
-	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
-	movne	\divisor,  \divisor, lsr #4
-	bne	1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	rsb	\order, \order, #31
-
-#else
-
-	cmp	\divisor, #(1 << 16)
-	movhs	\divisor, \divisor, lsr #16
-	movhs	\order, #16
-	movlo	\order, #0
-
-	cmp	\divisor, #(1 << 8)
-	movhs	\divisor, \divisor, lsr #8
-	addhs	\order, \order, #8
-
-	cmp	\divisor, #(1 << 4)
-	movhs	\divisor, \divisor, lsr #4
-	addhs	\order, \order, #4
-
-	cmp	\divisor, #(1 << 2)
-	addhi	\order, \order, #3
-	addls	\order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
-	.align	5
-.globl __divsi3
-__divsi3:
-ENTRY(__aeabi_idiv)
-	cmp	r1, #0
-	eor	ip, r0, r1			@ save the sign of the result.
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	subs	r2, r1, #1			@ division by 1 or -1 ?
-	beq	10f
-	movs	r3, r0
-	rsbmi	r3, r0, #0			@ positive dividend value
-	cmp	r3, r1
-	bls	11f
-	tst	r1, r2				@ divisor is power of 2 ?
-	beq	12f
-
-	ARM_DIV_BODY r3, r1, r0, r2
-
-	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-10:	teq	ip, r0				@ same sign ?
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-11:	movlo	r0, #0
-	moveq	r0, ip, asr #31
-	orreq	r0, r0, #1
-	mov	pc, lr
-
-12:	ARM_DIV2_ORDER r1, r2
-
-	cmp	ip, #0
-	mov	r0, r3, lsr r2
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
-ENDPROC(__aeabi_idiv)
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
new file mode 100644
index 0000000..5871dbe
--- /dev/null
+++ b/arch/arm/lib/lib1funcs.S
@@ -0,0 +1,351 @@
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ *
+ * Author: Nicolas Pitre <nico@fluxnic.net>
+ *   - contributed to gcc-3.4 on Sep 30, 2003
+ *   - adapted for the Linux kernel on Oct 2, 2003
+ */
+
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * U-Boot compatibility bit, define empty UNWIND() macro as, since we
+ * do not support stack unwinding and define CONFIG_AEABI to make all
+ * of the functions available without diverging from Linux code.
+ */
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#define CONFIG_AEABI
+#endif
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\curbit, \divisor
+	clz	\result, \dividend
+	sub	\result, \curbit, \result
+	mov	\curbit, #1
+	mov	\divisor, \divisor, lsl \result
+	mov	\curbit, \curbit, lsl \result
+	mov	\result, #0
+	
+#else
+
+	@ Initially shift the divisor left 3 bits if possible,
+	@ set curbit accordingly.  This allows for curbit to be located
+	@ at the left end of each 4 bit nibbles in the division loop
+	@ to save one loop in most cases.
+	tst	\divisor, #0xe0000000
+	moveq	\divisor, \divisor, lsl #3
+	moveq	\curbit, #8
+	movne	\curbit, #1
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is 
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	movlo	\curbit, \curbit, lsl #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	movlo	\curbit, \curbit, lsl #1
+	blo	1b
+
+	mov	\result, #0
+
+#endif
+
+	@ Division loop
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	orrhs	\result,   \result,   \curbit
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	orrhs	\result,   \result,   \curbit,  lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	orrhs	\result,   \result,   \curbit,  lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	orrhs	\result,   \result,   \curbit,  lsr #3
+	cmp	\dividend, #0			@ Early termination?
+	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+	movne	\divisor,  \divisor, lsr #4
+	bne	1b
+
+.endm
+
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	rsb	\order, \order, #31
+
+#else
+
+	cmp	\divisor, #(1 << 16)
+	movhs	\divisor, \divisor, lsr #16
+	movhs	\order, #16
+	movlo	\order, #0
+
+	cmp	\divisor, #(1 << 8)
+	movhs	\divisor, \divisor, lsr #8
+	addhs	\order, \order, #8
+
+	cmp	\divisor, #(1 << 4)
+	movhs	\divisor, \divisor, lsr #4
+	addhs	\order, \order, #4
+
+	cmp	\divisor, #(1 << 2)
+	addhi	\order, \order, #3
+	addls	\order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	clz	\spare, \dividend
+	sub	\order, \order, \spare
+	mov	\divisor, \divisor, lsl \order
+
+#else
+
+	mov	\order, #0
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is 
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	addlo	\order, \order, #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	addlo	\order, \order, #1
+	blo	1b
+
+#endif
+
+	@ Perform all needed subtractions to keep only the reminder.
+	@ Do comparisons in batch of 4 first.
+	subs	\order, \order, #3		@ yes, 3 is intended here
+	blt	2f
+
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	cmp	\dividend, #1
+	mov	\divisor, \divisor, lsr #4
+	subges	\order, \order, #4
+	bge	1b
+
+	tst	\order, #3
+	teqne	\dividend, #0
+	beq	5f
+
+	@ Either 1, 2 or 3 comparison/subtractions are left.
+2:	cmn	\order, #2
+	blt	4f
+	beq	3f
+	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+3:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+4:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+5:
+.endm
+
+
+ENTRY(__udivsi3)
+ENTRY(__aeabi_uidiv)
+UNWIND(.fnstart)
+
+	subs	r2, r1, #1
+	reteq	lr
+	bcc	Ldiv0
+	cmp	r0, r1
+	bls	11f
+	tst	r1, r2
+	beq	12f
+
+	ARM_DIV_BODY r0, r1, r2, r3
+
+	mov	r0, r2
+	ret	lr
+
+11:	moveq	r0, #1
+	movne	r0, #0
+	ret	lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	mov	r0, r0, lsr r2
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
+
+ENTRY(__umodsi3)
+UNWIND(.fnstart)
+
+	subs	r2, r1, #1			@ compare divisor with 1
+	bcc	Ldiv0
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq   r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	retls	lr
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__umodsi3)
+
+ENTRY(__divsi3)
+ENTRY(__aeabi_idiv)
+UNWIND(.fnstart)
+
+	cmp	r1, #0
+	eor	ip, r0, r1			@ save the sign of the result.
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	subs	r2, r1, #1			@ division by 1 or -1 ?
+	beq	10f
+	movs	r3, r0
+	rsbmi	r3, r0, #0			@ positive dividend value
+	cmp	r3, r1
+	bls	11f
+	tst	r1, r2				@ divisor is power of 2 ?
+	beq	12f
+
+	ARM_DIV_BODY r3, r1, r0, r2
+
+	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	ret	lr
+
+10:	teq	ip, r0				@ same sign ?
+	rsbmi	r0, r0, #0
+	ret	lr
+
+11:	movlo	r0, #0
+	moveq	r0, ip, asr #31
+	orreq	r0, r0, #1
+	ret	lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	cmp	ip, #0
+	mov	r0, r3, lsr r2
+	rsbmi	r0, r0, #0
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
+
+ENTRY(__modsi3)
+UNWIND(.fnstart)
+
+	cmp	r1, #0
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	movs	ip, r0				@ preserve sign of dividend
+	rsbmi	r0, r0, #0			@ if negative make positive
+	subs	r2, r1, #1			@ compare divisor with 1
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq	r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	bls	10f
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+10:	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__modsi3)
+
+#ifdef CONFIG_AEABI
+
+ENTRY(__aeabi_uidivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr}	)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_uidiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_uidivmod)
+
+ENTRY(__aeabi_idivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr}	)
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_idiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_idivmod)
+
+#endif
+
+Ldiv0:
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+	str	lr, [sp, #-8]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #8
+UNWIND(.fnend)
+ENDPROC(Ldiv0)
diff --git a/arch/arm/lib/modsi3.S b/arch/arm/lib/modsi3.S
deleted file mode 100644
index c5e1c22..0000000
--- a/arch/arm/lib/modsi3.S
+++ /dev/null
@@ -1,99 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	clz	\spare, \dividend
-	sub	\order, \order, \spare
-	mov	\divisor, \divisor, lsl \order
-
-#else
-
-	mov	\order, #0
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	addlo	\order, \order, #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	addlo	\order, \order, #1
-	blo	1b
-
-#endif
-
-	@ Perform all needed substractions to keep only the reminder.
-	@ Do comparisons in batch of 4 first.
-	subs	\order, \order, #3		@ yes, 3 is intended here
-	blt	2f
-
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	cmp	\dividend, #1
-	mov	\divisor, \divisor, lsr #4
-	subges	\order, \order, #4
-	bge	1b
-
-	tst	\order, #3
-	teqne	\dividend, #0
-	beq	5f
-
-	@ Either 1, 2 or 3 comparison/substractions are left.
-2:	cmn	\order, #2
-	blt	4f
-	beq	3f
-	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-3:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-4:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-5:
-.endm
-
-	.align	5
-ENTRY(__modsi3)
-	cmp	r1, #0
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	movs	ip, r0				@ preserve sign of dividend
-	rsbmi	r0, r0, #0			@ if negative make positive
-	subs	r2, r1, #1			@ compare divisor with 1
-	cmpne	r0, r1				@ compare dividend with divisor
-	moveq	r0, #0
-	tsthi	r1, r2				@ see if divisor is power of 2
-	andeq	r0, r0, r2
-	bls	10f
-
-	ARM_MOD_BODY r0, r1, r2, r3
-
-10:	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-ENDPROC(__modsi3)
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
diff --git a/arch/arm/lib/udivsi3.S b/arch/arm/lib/udivsi3.S
deleted file mode 100644
index 3b653be..0000000
--- a/arch/arm/lib/udivsi3.S
+++ /dev/null
@@ -1,95 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend	.req	r0
-divisor		.req	r1
-result		.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __udivsi3
-	.type	__udivsi3 ,function
-	.globl	__aeabi_uidiv
-	.type	__aeabi_uidiv ,function
-	.align	0
- __udivsi3:
- __aeabi_uidiv:
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	mov	result, #0
-	cmp	dividend, divisor
-	bcc	Lgot_result
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions, and note which bits
-	@ are done in the result.  On the final pass, this may subtract
-	@ too much from the dividend, but the result will be ok, since the
-	@ "bit" will have been shifted out at the bottom.
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	orrcs	result, result, curbit
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	result, result, curbit, lsr #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	result, result, curbit, lsr #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	result, result, curbit, lsr #3
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-Lgot_result:
-	mov	r0, result
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __udivsi3       , . -  __udivsi3
-
-ENTRY(__aeabi_uidivmod)
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_uidiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-ENDPROC(__aeabi_uidivmod)
-
-ENTRY(__aeabi_idivmod)
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_idiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-ENDPROC(__aeabi_idivmod)
diff --git a/arch/arm/lib/umodsi3.S b/arch/arm/lib/umodsi3.S
deleted file mode 100644
index b166737..0000000
--- a/arch/arm/lib/umodsi3.S
+++ /dev/null
@@ -1,90 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend	.req	r0
-divisor		.req	r1
-overdone	.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.type  __umodsi3       ,function
-	.align 0
- ENTRY(__umodsi3)
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	cmp	dividend, divisor
-	movcc	pc, lr
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions.  On the final pass, this may
-	@ subtract too much from the dividend, so keep track of which
-	@ subtractions are done, we can fix them up afterwards...
-	mov	overdone, #0
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	overdone, overdone, curbit, ror #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	overdone, overdone, curbit, ror #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	overdone, overdone, curbit, ror #3
-	mov	ip, curbit
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-	@ Any subtractions that we should not have done will be recorded in
-	@ the top three bits of "overdone".  Exactly which were not needed
-	@ are governed by the position of the bit, stored in ip.
-	@ If we terminated early, because dividend became zero,
-	@ then none of the below will match, since the bit in ip will not be
-	@ in the bottom nibble.
-	ands	overdone, overdone, #0xe0000000
-	moveq	pc, lr				@ No fixups needed
-	tst	overdone, ip, ror #3
-	addne	dividend, dividend, divisor, lsr #3
-	tst	overdone, ip, ror #2
-	addne	dividend, dividend, divisor, lsr #2
-	tst	overdone, ip, ror #1
-	addne	dividend, dividend, divisor, lsr #1
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __umodsi3       , . -  __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
-ENDPROC(__umodsi3)
-- 
cgit v0.10.2


From e64d75948446b14ff817c10ae5a65c84b1d24ba7 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:41 +0200
Subject: arm: lib: Fix uldivmod.S build on Thumb2

This assembler source won't build in Thumb2 mode, so fix it adding
the necessary Thumb2 conditional macros from unified.h .

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/uldivmod.S b/arch/arm/lib/uldivmod.S
index 426c2f2..2efcd73 100644
--- a/arch/arm/lib/uldivmod.S
+++ b/arch/arm/lib/uldivmod.S
@@ -9,10 +9,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-/* We don't use Thumb instructions for now */
-#define ARM(x...)	x
-#define THUMB(x...)
-
 /*
  * A, Q = r0 + (r1 << 32)
  * B, R = r2 + (r3 << 32)
@@ -226,7 +222,9 @@ THUMB(	orrpl	A_0, A_0, TMP		)
 	@ Shift A to the right by the appropriate amount.
 	rsb	D_1, D_0, #32
 	mov	Q_0, A_0, lsr D_0
-	orr	Q_0, A_1, lsl D_1
+ ARM(   orr     Q_0, Q_0, A_1, lsl D_1	)
+ THUMB(	lsl	A_1, D_1		)
+ THUMB(	orr	Q_0, A_1		)
 	mov	Q_1, A_1, lsr D_0
 	@ Move C to R
 	mov	R_0, C_0
-- 
cgit v0.10.2


From 7b9f9c5d3bae666359143cf5a681f90e998b5a80 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:42 +0200
Subject: arm: lib: Import __do_div64 from Linux

Import __do_div64 from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This function is for some toolchains, which generate _udivmoddi4()
for 64 bit division.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index a1ab297..de933ab 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,7 +6,7 @@
 #
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
-				    lib1funcs.o uldivmod.o div0.o
+				    lib1funcs.o uldivmod.o div0.o div64.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
new file mode 100644
index 0000000..03986c2
--- /dev/null
+++ b/arch/arm/lib/div64.S
@@ -0,0 +1,212 @@
+/*
+ *  linux/arch/arm/lib/div64.S
+ *
+ *  Optimized computation of 64-bit dividend / 32-bit divisor
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Oct 5, 2003
+ *  Copyright:	Monta Vista Software, Inc.
+ *
+ *  SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#endif
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+/*
+ * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
+ *
+ * Note: Calling convention is totally non standard for optimal code.
+ *       This is meant to be used by do_div() from include/asm/div64.h only.
+ *
+ * Input parameters:
+ * 	xh-xl	= dividend (clobbered)
+ * 	r4	= divisor (preserved)
+ *
+ * Output values:
+ * 	yh-yl	= result
+ * 	xh	= remainder
+ *
+ * Clobbered regs: xl, ip
+ */
+
+ENTRY(__do_div64)
+UNWIND(.fnstart)
+
+	@ Test for easy paths first.
+	subs	ip, r4, #1
+	bls	9f			@ divisor is 0 or 1
+	tst	ip, r4
+	beq	8f			@ divisor is power of 2
+
+	@ See if we need to handle upper 32-bit result.
+	cmp	xh, r4
+	mov	yh, #0
+	blo	3f
+
+	@ Align divisor with upper part of dividend.
+	@ The aligned divisor is stored in yl preserving the original.
+	@ The bit position is stored in ip.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	yl, r4
+	clz	ip, xh
+	sub	yl, yl, ip
+	mov	ip, #1
+	mov	ip, ip, lsl yl
+	mov	yl, r4, lsl yl
+
+#else
+
+	mov	yl, r4
+	mov	ip, #1
+1:	cmp	yl, #0x80000000
+	cmpcc	yl, xh
+	movcc	yl, yl, lsl #1
+	movcc	ip, ip, lsl #1
+	bcc	1b
+
+#endif
+
+	@ The division loop for needed upper bit positions.
+ 	@ Break out early if dividend reaches 0.
+2:	cmp	xh, yl
+	orrcs	yh, yh, ip
+	subcss	xh, xh, yl
+	movnes	ip, ip, lsr #1
+	mov	yl, yl, lsr #1
+	bne	2b
+
+	@ See if we need to handle lower 32-bit result.
+3:	cmp	xh, #0
+	mov	yl, #0
+	cmpeq	xl, r4
+	movlo	xh, xl
+	retlo	lr
+
+	@ The division loop for lower bit positions.
+	@ Here we shift remainer bits leftwards rather than moving the
+	@ divisor for comparisons, considering the carry-out bit as well.
+	mov	ip, #0x80000000
+4:	movs	xl, xl, lsl #1
+	adcs	xh, xh, xh
+	beq	6f
+	cmpcc	xh, r4
+5:	orrcs	yl, yl, ip
+	subcs	xh, xh, r4
+	movs	ip, ip, lsr #1
+	bne	4b
+	ret	lr
+
+	@ The top part of remainder became zero.  If carry is set
+	@ (the 33th bit) this is a false positive so resume the loop.
+	@ Otherwise, if lower part is also null then we are done.
+6:	bcs	5b
+	cmp	xl, #0
+	reteq	lr
+
+	@ We still have remainer bits in the low part.  Bring them up.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	xh, xl			@ we know xh is zero here so...
+	add	xh, xh, #1
+	mov	xl, xl, lsl xh
+	mov	ip, ip, lsr xh
+
+#else
+
+7:	movs	xl, xl, lsl #1
+	mov	ip, ip, lsr #1
+	bcc	7b
+
+#endif
+
+	@ Current remainder is now 1.  It is worthless to compare with
+	@ divisor at this point since divisor can not be smaller than 3 here.
+	@ If possible, branch for another shift in the division loop.
+	@ If no bit position left then we are done.
+	movs	ip, ip, lsr #1
+	mov	xh, #1
+	bne	4b
+	ret	lr
+
+8:	@ Division by a power of 2: determine what that divisor order is
+	@ then simply shift values around
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	ip, r4
+	rsb	ip, ip, #31
+
+#else
+
+	mov	yl, r4
+	cmp	r4, #(1 << 16)
+	mov	ip, #0
+	movhs	yl, yl, lsr #16
+	movhs	ip, #16
+
+	cmp	yl, #(1 << 8)
+	movhs	yl, yl, lsr #8
+	addhs	ip, ip, #8
+
+	cmp	yl, #(1 << 4)
+	movhs	yl, yl, lsr #4
+	addhs	ip, ip, #4
+
+	cmp	yl, #(1 << 2)
+	addhi	ip, ip, #3
+	addls	ip, ip, yl, lsr #1
+
+#endif
+
+	mov	yh, xh, lsr ip
+	mov	yl, xl, lsr ip
+	rsb	ip, ip, #32
+ ARM(	orr	yl, yl, xh, lsl ip	)
+ THUMB(	lsl	xh, xh, ip		)
+ THUMB(	orr	yl, yl, xh		)
+	mov	xh, xl, lsl ip
+	mov	xh, xh, lsr ip
+	ret	lr
+
+	@ eq -> division by 1: obvious enough...
+9:	moveq	yl, xl
+	moveq	yh, xh
+	moveq	xh, #0
+	reteq	lr
+UNWIND(.fnend)
+
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+Ldiv0_64:
+	@ Division by 0:
+	str	lr, [sp, #-8]!
+	bl	__div0
+
+	@ as wrong as it could be...
+	mov	yl, #0
+	mov	yh, #0
+	mov	xh, #0
+	ldr	pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(__do_div64)
-- 
cgit v0.10.2


From 40d67c75e47e2e76cc310515c55d758151b9fdde Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:43 +0200
Subject: arm: lib: Repair Warning: conditional infixes are deprecated in
 unified syntax

Fix the following warning when building for thumb2 target by tweaking the
instruction syntax:

Warning: conditional infixes are deprecated in unified syntax

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 03986c2..a42a0f0 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -88,8 +88,8 @@ UNWIND(.fnstart)
  	@ Break out early if dividend reaches 0.
 2:	cmp	xh, yl
 	orrcs	yh, yh, ip
-	subcss	xh, xh, yl
-	movnes	ip, ip, lsr #1
+	subscs	xh, xh, yl
+	movsne	ip, ip, lsr #1
 	mov	yl, yl, lsr #1
 	bne	2b
 
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 5871dbe..c343ea9 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -84,7 +84,7 @@
 	subhs	\dividend, \dividend, \divisor, lsr #3
 	orrhs	\result,   \result,   \curbit,  lsr #3
 	cmp	\dividend, #0			@ Early termination?
-	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+	movsne	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
 	movne	\divisor,  \divisor, lsr #4
 	bne	1b
 
@@ -170,7 +170,7 @@
 	subhs	\dividend, \dividend, \divisor, lsr #3
 	cmp	\dividend, #1
 	mov	\divisor, \divisor, lsr #4
-	subges	\order, \order, #4
+	subsge	\order, \order, #4
 	bge	1b
 
 	tst	\order, #3
-- 
cgit v0.10.2


From 0bf65c6422d51768bc30735dbd97cf66f09a0450 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:44 +0200
Subject: arm: lib: import muldi3.S from Linux

Import muldi3.S from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which
is needed when doing Thumb1 builds.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index de933ab..0e05e87 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,7 +6,8 @@
 #
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
-				    lib1funcs.o uldivmod.o div0.o div64.o
+				    lib1funcs.o uldivmod.o div0.o \
+				    div64.o muldi3.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
new file mode 100644
index 0000000..daa5704
--- /dev/null
+++ b/arch/arm/lib/muldi3.S
@@ -0,0 +1,46 @@
+/*
+ *  linux/arch/arm/lib/muldi3.S
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Oct 19, 2005
+ *  Copyright:  Monta Vista Software, Inc.
+ *
+ *  SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+ENTRY(__muldi3)
+ENTRY(__aeabi_lmul)
+
+	mul	xh, yl, xh
+	mla	xh, xl, yh, xh
+	mov	ip, xl, lsr #16
+	mov	yh, yl, lsr #16
+	bic	xl, xl, ip, lsl #16
+	bic	yl, yl, yh, lsl #16
+	mla	xh, yh, ip, xh
+	mul	yh, xl, yh
+	mul	xl, yl, xl
+	mul	ip, yl, ip
+	adds	xl, xl, yh, lsl #16
+	adc	xh, xh, yh, lsr #16
+	adds	xl, xl, ip, lsl #16
+	adc	xh, xh, ip, lsr #16
+	ret	lr
+
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
-- 
cgit v0.10.2


From 806f86bd826e7a0fbefd4f34c550df400905992a Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:45 +0200
Subject: arm: lib: Import Thumb1 functions

Import functions into lib1funcs.S which are required for Thumb1
build. These functions come from gcc 5.3.1 release.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index c343ea9..408839b 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -349,3 +349,56 @@ UNWIND(.save {lr})
 	ldr	pc, [sp], #8
 UNWIND(.fnend)
 ENDPROC(Ldiv0)
+
+/* Thumb-1 specialities */
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
+ENTRY(__gnu_thumb1_case_sqi)
+	push	{r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r1, r1, #1
+	ldrsb	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_sqi)
+
+ENTRY(__gnu_thumb1_case_uqi)
+	push	{r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r1, r1, #1
+	ldrb	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_uqi)
+
+ENTRY(__gnu_thumb1_case_shi)
+	push	{r0, r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r0, r0, #1
+	lsls	r1, r1, #1
+	ldrsh	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r0, r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_shi)
+
+ENTRY(__gnu_thumb1_case_uhi)
+	push	{r0, r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r0, r0, #1
+	lsls	r1, r1, #1
+	ldrh	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r0, r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_uhi)
+#endif
-- 
cgit v0.10.2


From 13b0a91a6d48736d2927edd63e59f3a9e76f6d34 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:46 +0200
Subject: arm: lib: Split asm symbols into different .text subsections

Split each symbol in lib1funcs into different .text.foo section instead
of placing all of them into plain .text . This allows the linker to collect
and discard unused assembler symbols.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index a4f5ebb..6c9ae91 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -17,6 +17,7 @@
 
 ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
+.pushsection .text.__ashldi3, "ax"
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -28,5 +29,6 @@ ENTRY(__aeabi_llsl)
 	mov	al, al, lsl r2
 	ret	lr
 
+.popsection
 ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index c6e1ed3..3eb59ec 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -17,6 +17,7 @@
 
 ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
+.pushsection .text.__ashrdi3, "ax"
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -28,5 +29,6 @@ ENTRY(__aeabi_lasr)
 	mov	ah, ah, asr r2
 	ret	lr
 
+.popsection
 ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index a42a0f0..5bfb41d 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -47,6 +47,7 @@
 
 ENTRY(__do_div64)
 UNWIND(.fnstart)
+.pushsection .text.__do_div64, "ax"
 
 	@ Test for easy paths first.
 	subs	ip, r4, #1
@@ -192,6 +193,7 @@ UNWIND(.fnstart)
 	moveq	yh, xh
 	moveq	xh, #0
 	reteq	lr
+.popsection
 UNWIND(.fnend)
 
 UNWIND(.fnstart)
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 408839b..f1becda 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -196,6 +196,7 @@
 ENTRY(__udivsi3)
 ENTRY(__aeabi_uidiv)
 UNWIND(.fnstart)
+.pushsection .text.__udivsi3, "ax"
 
 	subs	r2, r1, #1
 	reteq	lr
@@ -219,12 +220,14 @@ UNWIND(.fnstart)
 	mov	r0, r0, lsr r2
 	ret	lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__udivsi3)
 ENDPROC(__aeabi_uidiv)
 
 ENTRY(__umodsi3)
 UNWIND(.fnstart)
+.pushsection .text.__umodsi3, "ax"
 
 	subs	r2, r1, #1			@ compare divisor with 1
 	bcc	Ldiv0
@@ -238,12 +241,14 @@ UNWIND(.fnstart)
 
 	ret	lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__umodsi3)
 
 ENTRY(__divsi3)
 ENTRY(__aeabi_idiv)
 UNWIND(.fnstart)
+.pushsection .text.__divsi3, "ax"
 
 	cmp	r1, #0
 	eor	ip, r0, r1			@ save the sign of the result.
@@ -280,12 +285,14 @@ UNWIND(.fnstart)
 	rsbmi	r0, r0, #0
 	ret	lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__divsi3)
 ENDPROC(__aeabi_idiv)
 
 ENTRY(__modsi3)
 UNWIND(.fnstart)
+.pushsection .text.__modsi3, "ax"
 
 	cmp	r1, #0
 	beq	Ldiv0
@@ -305,6 +312,7 @@ UNWIND(.fnstart)
 	rsbmi	r0, r0, #0
 	ret	lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__modsi3)
 
@@ -313,6 +321,7 @@ ENDPROC(__modsi3)
 ENTRY(__aeabi_uidivmod)
 UNWIND(.fnstart)
 UNWIND(.save {r0, r1, ip, lr}	)
+.pushsection .text.__aeabi_uidivmod, "ax"
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_uidiv
@@ -321,12 +330,15 @@ UNWIND(.save {r0, r1, ip, lr}	)
 	sub	r1, r1, r3
 	ret	lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__aeabi_uidivmod)
 
 ENTRY(__aeabi_idivmod)
 UNWIND(.fnstart)
 UNWIND(.save {r0, r1, ip, lr}	)
+.pushsection .text.__aeabi_uidivmod, "ax"
+
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_idiv
 	ldmfd	sp!, {r1, r2, ip, lr}
@@ -334,6 +346,7 @@ UNWIND(.save {r0, r1, ip, lr}	)
 	sub	r1, r1, r3
 	ret	lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__aeabi_idivmod)
 
@@ -343,16 +356,21 @@ Ldiv0:
 UNWIND(.fnstart)
 UNWIND(.pad #4)
 UNWIND(.save {lr})
+.pushsection .text.Ldiv0, "ax"
+
 	str	lr, [sp, #-8]!
 	bl	__div0
 	mov	r0, #0			@ About as wrong as it could be.
 	ldr	pc, [sp], #8
+
+.popsection
 UNWIND(.fnend)
 ENDPROC(Ldiv0)
 
 /* Thumb-1 specialities */
 #if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
 ENTRY(__gnu_thumb1_case_sqi)
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
 	push	{r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -362,9 +380,11 @@ ENTRY(__gnu_thumb1_case_sqi)
 	add	lr, lr, r1
 	pop	{r1}
 	bx	lr
+.popsection
 ENDPROC(__gnu_thumb1_case_sqi)
 
 ENTRY(__gnu_thumb1_case_uqi)
+.pushsection .text.__gnu_thumb1_case_uqi, "ax"
 	push	{r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -374,9 +394,11 @@ ENTRY(__gnu_thumb1_case_uqi)
 	add	lr, lr, r1
 	pop	{r1}
 	bx	lr
+.popsection
 ENDPROC(__gnu_thumb1_case_uqi)
 
 ENTRY(__gnu_thumb1_case_shi)
+.pushsection .text.__gnu_thumb1_case_shi, "ax"
 	push	{r0, r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -387,9 +409,11 @@ ENTRY(__gnu_thumb1_case_shi)
 	add	lr, lr, r1
 	pop	{r0, r1}
 	bx	lr
+.popsection
 ENDPROC(__gnu_thumb1_case_shi)
 
 ENTRY(__gnu_thumb1_case_uhi)
+.pushsection .text.__gnu_thumb1_case_uhi, "ax"
 	push	{r0, r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -400,5 +424,6 @@ ENTRY(__gnu_thumb1_case_uhi)
 	add	lr, lr, r1
 	pop	{r0, r1}
 	bx	lr
+.popsection
 ENDPROC(__gnu_thumb1_case_uhi)
 #endif
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 9c51141..f710ccb 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -17,6 +17,7 @@
 
 ENTRY(__lshrdi3)
 ENTRY(__aeabi_llsr)
+.pushsection .text.__lshldi3, "ax"
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -28,5 +29,6 @@ ENTRY(__aeabi_llsr)
 	mov	ah, ah, lsr r2
 	ret	lr
 
+.popsection
 ENDPROC(__lshrdi3)
 ENDPROC(__aeabi_llsr)
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
index daa5704..bc255c5 100644
--- a/arch/arm/lib/muldi3.S
+++ b/arch/arm/lib/muldi3.S
@@ -25,6 +25,7 @@
 
 ENTRY(__muldi3)
 ENTRY(__aeabi_lmul)
+.pushsection .text.__muldi3, "ax"
 
 	mul	xh, yl, xh
 	mla	xh, xl, yh, xh
@@ -42,5 +43,6 @@ ENTRY(__aeabi_lmul)
 	adc	xh, xh, ip, lsr #16
 	ret	lr
 
+.popsection
 ENDPROC(__muldi3)
 ENDPROC(__aeabi_lmul)
diff --git a/arch/arm/lib/uldivmod.S b/arch/arm/lib/uldivmod.S
index 2efcd73..bbc44c6 100644
--- a/arch/arm/lib/uldivmod.S
+++ b/arch/arm/lib/uldivmod.S
@@ -34,6 +34,8 @@ TMP	.req	r8
 )
 
 ENTRY(__aeabi_uldivmod)
+.pushsection .text.__aeabi_uldivmod, "ax"
+
 	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
 	@ Test if B == 0
 	orrs	ip, B_0, B_1		@ Z set -> B == 0
@@ -240,4 +242,5 @@ L_div_by_0:
 	mov	R_0, #0
 	mov	R_1, #0
 	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+.popsection
 ENDPROC(__aeabi_uldivmod)
-- 
cgit v0.10.2


From 91b86e21564de01c0e3deafc72702897993d63ae Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 26 May 2016 18:01:47 +0200
Subject: lib: Enable private libgcc by default

This patch decouples U-Boot binary from the toolchain on systems where
private libgcc is available. Instead of pulling in functions provided
by the libgcc from the toolchain, U-Boot will use it's own set of libgcc
functions. These functions are usually imported from Linux kernel, which
also uses it's own libgcc functions instead of the ones provided by the
toolchain.

This patch solves a rather common problem. The toolchain can usually
generate code for many variants of target architecture and often even
different endianness. The libgcc on the other hand is usually compiled
for one particular configuration and the functions provided by it may
or may not be suited for use in U-Boot. This can manifest in two ways,
either the U-Boot fails to compile altogether and linker will complain
or, in the much worse case, the resulting U-Boot will build, but will
misbehave in very subtle and hard to debug ways.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/lib/Kconfig b/lib/Kconfig
index 2b97c2b..02ca405 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -14,6 +14,7 @@ config HAVE_PRIVATE_LIBGCC
 config USE_PRIVATE_LIBGCC
 	bool "Use private libgcc"
 	depends on HAVE_PRIVATE_LIBGCC
+	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
 	help
 	  This option allows you to use the built-in libgcc implementation
 	  of U-Boot instead of the one provided by the compiler.
-- 
cgit v0.10.2


From 383f4a0ec78ee92c89a7ce135acbde47c84c6201 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Mon, 23 May 2016 17:37:47 +0300
Subject: ARM: OMAP5+: Provide enable/disable_usb_clocks() for
 CONFIG_USB_XHCI_OMAP

CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.

Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 5c2a2ab..73ea955 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -160,7 +160,7 @@ void disable_edma3_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 void enable_usb_clocks(int index)
 {
 	u32 *usbclkctrl = 0;
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 88e8920..8734815 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -602,7 +602,7 @@ void disable_edma3_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 void enable_usb_clocks(int index)
 {
 	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
-- 
cgit v0.10.2


From 55efadde7edee407a14c7cbf418c82b30a94faa8 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Mon, 23 May 2016 17:37:48 +0300
Subject: ARM: AM57xx: AM43xx: Fix USB host

CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.

Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.

Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index b42546a..bde5ac7 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -678,71 +678,71 @@ static struct ti_usb_phy_device usb_phy2_device = {
 	.index = 1,
 };
 
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
 	switch (index) {
 	case 0:
 		if (init == USB_INIT_DEVICE) {
 			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+			dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+			ti_usb_phy_uboot_init(&usb_phy1_device);
+			dwc3_uboot_init(&usb_otg_ss1);
 		}
-
-		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
-		ti_usb_phy_uboot_init(&usb_phy1_device);
-		dwc3_uboot_init(&usb_otg_ss1);
 		break;
 	case 1:
 		if (init == USB_INIT_DEVICE) {
 			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+			ti_usb_phy_uboot_init(&usb_phy2_device);
+			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+			dwc3_uboot_init(&usb_otg_ss2);
 		}
-
-		ti_usb_phy_uboot_init(&usb_phy2_device);
-		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-		dwc3_uboot_init(&usb_otg_ss2);
 		break;
 	default:
 		printf("Invalid Controller Index\n");
 	}
+#endif
 
 	return 0;
 }
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_USB_DWC3
 	switch (index) {
 	case 0:
 	case 1:
-		ti_usb_phy_uboot_exit(index);
-		dwc3_uboot_exit(index);
-		dwc3_omap_uboot_exit(index);
+		if (init == USB_INIT_DEVICE) {
+			ti_usb_phy_uboot_exit(index);
+			dwc3_uboot_exit(index);
+			dwc3_omap_uboot_exit(index);
+		}
 		break;
 	default:
 		printf("Invalid Controller Index\n");
 	}
+#endif
 	disable_usb_clocks(index);
 
 	return 0;
 }
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 9904047..7142a92 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -439,6 +439,19 @@ static struct ti_usb_phy_device usb_phy2_device = {
 	.index = 1,
 };
 
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
@@ -448,31 +461,23 @@ int board_usb_init(int index, enum usb_init_type init)
 			printf("port %d can't be used as device\n", index);
 			disable_usb_clocks(index);
 			return -EINVAL;
-		} else {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-			setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-				     OTG_SS_CLKCTRL_MODULEMODE_HW |
-				     OPTFCLKEN_REFCLK960M);
 		}
-
-		ti_usb_phy_uboot_init(&usb_phy1_device);
-		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
-		dwc3_uboot_init(&usb_otg_ss1);
 		break;
 	case 1:
 		if (init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_DWC3
 			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+			ti_usb_phy_uboot_init(&usb_phy2_device);
+			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+			dwc3_uboot_init(&usb_otg_ss2);
+#endif
 		} else {
 			printf("port %d can't be used as host\n", index);
 			disable_usb_clocks(index);
 			return -EINVAL;
 		}
 
-		ti_usb_phy_uboot_init(&usb_phy2_device);
-		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-		dwc3_uboot_init(&usb_otg_ss2);
 		break;
 	default:
 		printf("Invalid Controller Index\n");
@@ -483,31 +488,24 @@ int board_usb_init(int index, enum usb_init_type init)
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_USB_DWC3
 	switch (index) {
 	case 0:
 	case 1:
-		ti_usb_phy_uboot_exit(index);
-		dwc3_uboot_exit(index);
-		dwc3_omap_uboot_exit(index);
+		if (init == USB_INIT_DEVICE) {
+			ti_usb_phy_uboot_exit(index);
+			dwc3_uboot_exit(index);
+			dwc3_omap_uboot_exit(index);
+		}
 		break;
 	default:
 		printf("Invalid Controller Index\n");
 	}
+#endif
 	disable_usb_clocks(index);
 	return 0;
 }
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 
-- 
cgit v0.10.2


From 3599774eec9d06812c6124bcd0b34cebd7ec5e1c Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Mon, 23 May 2016 17:37:49 +0300
Subject: dra7xx: Enable USB_PHY3 32KHz clock

DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 8734815..fe59c25 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -614,9 +614,14 @@ void enable_usb_clocks(int index)
 		setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 			     OPTFCLKEN_REFCLK960M);
 
-		/* Enable 32 KHz clock for dwc3 */
+		/* Enable 32 KHz clock for USB_PHY1 */
 		setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+		/* Enable 32 KHz clock for USB_PHY3 */
+		if (is_dra7xx())
+			setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 	} else if (index == 1) {
 		cm_l3init_usb_otg_ss_clkctrl =
 			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
@@ -664,9 +669,14 @@ void disable_usb_clocks(int index)
 		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 			     OPTFCLKEN_REFCLK960M);
 
-		/* Disable 32 KHz clock for dwc3 */
+		/* Disable 32 KHz clock for USB_PHY1 */
 		clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+		/* Disable 32 KHz clock for USB_PHY3 */
+		if (is_dra7xx())
+			clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 	} else if (index == 1) {
 		cm_l3init_usb_otg_ss_clkctrl =
 			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 655e92b..b5f1d70 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
 	.cm_coreaon_usb_phy1_core_clkctrl	= 0x4a008640,
 	.cm_coreaon_usb_phy2_core_clkctrl	= 0x4a008688,
+	.cm_coreaon_usb_phy3_core_clkctrl	= 0x4a008698,
 	.cm_coreaon_l3init_60m_gfclk_clkctrl	= 0x4a0086c0,
 
 	/* cm1.mpu */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index ac34b0e..07f3848 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -145,6 +145,7 @@ struct prcm_regs {
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
 	u32 cm_coreaon_usb_phy1_core_clkctrl;
 	u32 cm_coreaon_usb_phy2_core_clkctrl;
+	u32 cm_coreaon_usb_phy3_core_clkctrl;
 	u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
 
 	/* cm2.core */
-- 
cgit v0.10.2


From 68a775a7665f8cec3c0f6f38179ef5b7eeb2fee0 Mon Sep 17 00:00:00 2001
From: Roger Quadros <rogerq@ti.com>
Date: Mon, 23 May 2016 17:37:50 +0300
Subject: usb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration

The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.

This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.

Signed-off-by: Roger Quadros <rogerq@ti.com>

diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f9069c7..1993da1 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -23,7 +23,7 @@
 #include "../host/xhci.h"
 
 #ifdef CONFIG_OMAP_USB3PHY1_HOST
-struct usb_dpll_params {
+struct usb3_dpll_params {
 	u16	m;
 	u8	n;
 	u8	freq:3;
@@ -31,17 +31,39 @@ struct usb_dpll_params {
 	u32	mf;
 };
 
-#define	NUM_USB_CLKS		6
+struct usb3_dpll_map {
+	unsigned long rate;
+	struct usb3_dpll_params params;
+	struct usb3_dpll_map *dpll_map;
+};
 
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
-	{1250, 5, 4, 20, 0},		/* 12 MHz */
-	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
-	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
-	{1250, 12, 4, 20, 0},		/* 26 MHz */
-	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
-	{1000, 7, 4, 10, 0},        /* 20 MHz */
+static struct usb3_dpll_map dpll_map_usb[] = {
+	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
+	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
+	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
+	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
+	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
+	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
+	{ },					/* Terminator */
 };
 
+static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
+{
+	unsigned long rate;
+	struct usb3_dpll_map *dpll_map = dpll_map_usb;
+
+	rate = get_sys_clk_freq();
+
+	for (; dpll_map->rate; dpll_map++) {
+		if (rate == dpll_map->rate)
+			return &dpll_map->params;
+	}
+
+	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+
+	return NULL;
+}
+
 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
 {
 	u32 val;
@@ -56,32 +78,36 @@ static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
 
 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
 {
-	u32 clk_index = get_sys_clk_index();
+	struct usb3_dpll_params	*dpll_params;
 	u32 val;
 
+	dpll_params = omap_usb3_get_dpll_params();
+	if (!dpll_params)
+		return;
+
 	val = readl(&phy_regs->pll_config_1);
 	val &= ~PLL_REGN_MASK;
-	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+	val |= dpll_params->n << PLL_REGN_SHIFT;
 	writel(val, &phy_regs->pll_config_1);
 
 	val = readl(&phy_regs->pll_config_2);
 	val &= ~PLL_SELFREQDCO_MASK;
-	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 	writel(val, &phy_regs->pll_config_2);
 
 	val = readl(&phy_regs->pll_config_1);
 	val &= ~PLL_REGM_MASK;
-	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+	val |= dpll_params->m << PLL_REGM_SHIFT;
 	writel(val, &phy_regs->pll_config_1);
 
 	val = readl(&phy_regs->pll_config_4);
 	val &= ~PLL_REGM_F_MASK;
-	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 	writel(val, &phy_regs->pll_config_4);
 
 	val = readl(&phy_regs->pll_config_3);
 	val &= ~PLL_SD_MASK;
-	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+	val |= dpll_params->sd << PLL_SD_SHIFT;
 	writel(val, &phy_regs->pll_config_3);
 
 	omap_usb_dpll_relock(phy_regs);
-- 
cgit v0.10.2


From 36080228edfdad69299bb6cc2a59ceb17190fcec Mon Sep 17 00:00:00 2001
From: "Anna, Suman" <s-anna@ti.com>
Date: Mon, 23 May 2016 13:32:14 -0500
Subject: ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values

The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.

The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 38d50d6..9180c67 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -240,17 +240,17 @@
 #define VDD_MM_ES2_LOW 880
 
 /* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752		1100
+#define VDD_MPU_DRA752		1150
+#define VDD_CORE_DRA752		1150
 #define VDD_EVE_DRA752		1060
 #define VDD_GPU_DRA752		1060
-#define VDD_CORE_DRA752		1060
 #define VDD_IVA_DRA752		1060
 
 /* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x		1100
+#define VDD_MPU_DRA72x		1150
+#define VDD_CORE_DRA72x		1150
 #define VDD_EVE_DRA72x		1060
 #define VDD_GPU_DRA72x		1060
-#define VDD_CORE_DRA72x		1060
 #define VDD_IVA_DRA72x		1060
 
 /* Efuse register offsets for DRA7xx platform */
-- 
cgit v0.10.2


From 27c9596f680ecea01beb52181da72b7d7fab0d8c Mon Sep 17 00:00:00 2001
From: "Anna, Suman" <s-anna@ti.com>
Date: Mon, 23 May 2016 13:32:15 -0500
Subject: ARM: DRA7: Define common macros for efuse register offsets

Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index fe59c25..5db17c4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -366,34 +366,34 @@ struct vcores_data omap5430_volts_es2 = {
 
 struct vcores_data dra752_volts = {
 	.mpu.value	= VDD_MPU_DRA752,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.eve.value	= VDD_EVE_DRA752,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.gpu.value	= VDD_GPU_DRA752,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
 	.core.value	= VDD_CORE_DRA752,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS659038_REG_ADDR_SMPS7,
 	.core.pmic	= &tps659038,
 
 	.iva.value	= VDD_IVA_DRA752,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic	= &tps659038,
@@ -402,14 +402,14 @@ struct vcores_data dra752_volts = {
 
 struct vcores_data dra722_volts = {
 	.mpu.value	= VDD_MPU_DRA72x,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.core.value	= VDD_CORE_DRA72x,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS65917_REG_ADDR_SMPS2,
 	.core.pmic	= &tps659038,
@@ -419,21 +419,21 @@ struct vcores_data dra722_volts = {
 	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 	 */
 	.gpu.value	= VDD_GPU_DRA72x,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
 	.eve.value	= VDD_EVE_DRA72x,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.iva.value	= VDD_IVA_DRA72x,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
 	.iva.pmic	= &tps659038,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 9180c67..a850043 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -283,6 +283,13 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
 
+/* Common Efuse register macros */
+#define STD_FUSE_OPP_VMIN_MPU		STD_FUSE_OPP_VMIN_MPU_NOM
+#define STD_FUSE_OPP_VMIN_CORE		STD_FUSE_OPP_VMIN_CORE_NOM
+#define STD_FUSE_OPP_VMIN_DSPEVE	STD_FUSE_OPP_VMIN_DSPEVE_NOM
+#define STD_FUSE_OPP_VMIN_GPU		STD_FUSE_OPP_VMIN_GPU_NOM
+#define STD_FUSE_OPP_VMIN_IVA		STD_FUSE_OPP_VMIN_IVA_NOM
+
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 7142a92..28db532 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -217,34 +217,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 
 struct vcores_data beagle_x15_volts = {
 	.mpu.value		= VDD_MPU_DRA752,
-	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.eve.value		= VDD_EVE_DRA752,
-	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
 	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
 
 	.gpu.value		= VDD_GPU_DRA752,
-	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
 	.gpu.pmic		= &tps659038,
 	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
 
 	.core.value		= VDD_CORE_DRA752,
-	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.core.addr		= TPS659038_REG_ADDR_SMPS6,
 	.core.pmic		= &tps659038,
 
 	.iva.value		= VDD_IVA_DRA752,
-	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
 	.iva.pmic		= &tps659038,
-- 
cgit v0.10.2


From e42523f54434119609744a62dcc9173b3a50dc29 Mon Sep 17 00:00:00 2001
From: "Anna, Suman" <s-anna@ti.com>
Date: Mon, 23 May 2016 13:32:16 -0500
Subject: ARM: DRA7: Consolidate voltage macros across different SoCs

The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.

This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5db17c4..5b91446a 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,34 +365,34 @@ struct vcores_data omap5430_volts_es2 = {
 };
 
 struct vcores_data dra752_volts = {
-	.mpu.value	= VDD_MPU_DRA752,
+	.mpu.value	= VDD_MPU_DRA7,
 	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value	= VDD_EVE_DRA752,
+	.eve.value	= VDD_EVE_DRA7,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value	= VDD_GPU_DRA752,
+	.gpu.value	= VDD_GPU_DRA7,
 	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value	= VDD_CORE_DRA752,
+	.core.value	= VDD_CORE_DRA7,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS659038_REG_ADDR_SMPS7,
 	.core.pmic	= &tps659038,
 
-	.iva.value	= VDD_IVA_DRA752,
+	.iva.value	= VDD_IVA_DRA7,
 	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
@@ -401,14 +401,14 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-	.mpu.value	= VDD_MPU_DRA72x,
+	.mpu.value	= VDD_MPU_DRA7,
 	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.core.value	= VDD_CORE_DRA72x,
+	.core.value	= VDD_CORE_DRA7,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS65917_REG_ADDR_SMPS2,
@@ -418,21 +418,21 @@ struct vcores_data dra722_volts = {
 	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 	 */
-	.gpu.value	= VDD_GPU_DRA72x,
+	.gpu.value	= VDD_GPU_DRA7,
 	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-	.eve.value	= VDD_EVE_DRA72x,
+	.eve.value	= VDD_EVE_DRA7,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-	.iva.value	= VDD_IVA_DRA72x,
+	.iva.value	= VDD_IVA_DRA7,
 	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index a850043..8c121d6 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -239,19 +239,12 @@
 #define VDD_MPU_ES2_LOW 880
 #define VDD_MM_ES2_LOW 880
 
-/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752		1150
-#define VDD_CORE_DRA752		1150
-#define VDD_EVE_DRA752		1060
-#define VDD_GPU_DRA752		1060
-#define VDD_IVA_DRA752		1060
-
-/* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x		1150
-#define VDD_CORE_DRA72x		1150
-#define VDD_EVE_DRA72x		1060
-#define VDD_GPU_DRA72x		1060
-#define VDD_IVA_DRA72x		1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7		1150
+#define VDD_CORE_DRA7		1150
+#define VDD_EVE_DRA7		1060
+#define VDD_GPU_DRA7		1060
+#define VDD_IVA_DRA7		1060
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE	0x4A002000
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 28db532..da5f499 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -216,34 +216,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 }
 
 struct vcores_data beagle_x15_volts = {
-	.mpu.value		= VDD_MPU_DRA752,
+	.mpu.value		= VDD_MPU_DRA7,
 	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value		= VDD_EVE_DRA752,
+	.eve.value		= VDD_EVE_DRA7,
 	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
 	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value		= VDD_GPU_DRA752,
+	.gpu.value		= VDD_GPU_DRA7,
 	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
 	.gpu.pmic		= &tps659038,
 	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value		= VDD_CORE_DRA752,
+	.core.value		= VDD_CORE_DRA7,
 	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.core.addr		= TPS659038_REG_ADDR_SMPS6,
 	.core.pmic		= &tps659038,
 
-	.iva.value		= VDD_IVA_DRA752,
+	.iva.value		= VDD_IVA_DRA7,
 	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
-- 
cgit v0.10.2


From 88730f19280d2d89816be8a7ab4faf8248e6b7b4 Mon Sep 17 00:00:00 2001
From: "Anna, Suman" <s-anna@ti.com>
Date: Mon, 23 May 2016 13:32:17 -0500
Subject: ARM: DRA7: Add macros for voltage values for all OPPs

Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.

The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 8c121d6..551c927 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -240,11 +240,21 @@
 #define VDD_MM_ES2_LOW 880
 
 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA7		1150
-#define VDD_CORE_DRA7		1150
-#define VDD_EVE_DRA7		1060
-#define VDD_GPU_DRA7		1060
-#define VDD_IVA_DRA7		1060
+#define VDD_MPU_DRA7_NOM	1150
+#define VDD_CORE_DRA7_NOM	1150
+#define VDD_EVE_DRA7_NOM	1060
+#define VDD_GPU_DRA7_NOM	1060
+#define VDD_IVA_DRA7_NOM	1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD		1150
+#define VDD_GPU_DRA7_OD		1150
+#define VDD_IVA_DRA7_OD		1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH	1250
+#define VDD_GPU_DRA7_HIGH	1250
+#define VDD_IVA_DRA7_HIGH	1250
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE	0x4A002000
@@ -276,7 +286,14 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
 
-/* Common Efuse register macros */
+/* Common voltage and Efuse register macros */
+/* DRA74x/DRA75x/DRA72x */
+#define VDD_MPU_DRA7			VDD_MPU_DRA7_NOM
+#define VDD_CORE_DRA7			VDD_CORE_DRA7_NOM
+#define VDD_EVE_DRA7			VDD_EVE_DRA7_NOM
+#define VDD_GPU_DRA7			VDD_GPU_DRA7_NOM
+#define VDD_IVA_DRA7			VDD_IVA_DRA7_NOM
+
 #define STD_FUSE_OPP_VMIN_MPU		STD_FUSE_OPP_VMIN_MPU_NOM
 #define STD_FUSE_OPP_VMIN_CORE		STD_FUSE_OPP_VMIN_CORE_NOM
 #define STD_FUSE_OPP_VMIN_DSPEVE	STD_FUSE_OPP_VMIN_DSPEVE_NOM
-- 
cgit v0.10.2


From 61462cd77277060318480abe5b0aba1adf5e76f4 Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Tue, 24 May 2016 11:45:05 +0530
Subject: arm: omap: Introduce vcores_init function

The pmic registers for variants of am57xx boards are different
hence we need to assign them carefully based on the board type.
Add a function to assign omap_vcores after the board detection.

Signed-off-by: Keerthy <j-keerthy@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 078bdd8..2f9693f 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -112,6 +112,16 @@ void __weak do_board_detect(void)
 {
 }
 
+/**
+ * vcores_init() - Assign omap_vcores based on board
+ *
+ * Function to pick the vcores based on board. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak vcores_init(void)
+{
+}
+
 void s_init(void)
 {
 }
@@ -149,6 +159,7 @@ void early_system_init(void)
 #endif
 	setup_early_clocks();
 	do_board_detect();
+	vcores_init();
 	prcm_init();
 }
 
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 804266a..ab0e7fa 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -51,6 +51,7 @@ void sdelay(unsigned long);
 void setup_early_clocks(void);
 void prcm_init(void);
 void do_board_detect(void);
+void vcores_init(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
-- 
cgit v0.10.2


From d60198dac2026ca6b6732e5cd6892d3b3bebddaa Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Tue, 24 May 2016 11:45:06 +0530
Subject: arm: am57xx: Fix omap_vcores assignment for am572x-idk

Currently omap_vcores is wrongly assigned a default value of
beagle_x15_volts. Hence populating a new structure for am572x-idk
and assigning it to omap_vcores in the vcores_init function.

Fixes: c020d355c45ed40fe12a ("board: ti: am57xx: Add support for am572x idk in SPL")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index da5f499..f533b1a 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -251,6 +251,42 @@ struct vcores_data beagle_x15_volts = {
 	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
 };
 
+struct vcores_data am572x_idk_volts = {
+	.mpu.value		= VDD_MPU_DRA7,
+	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value		= VDD_EVE_DRA7,
+	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value		= VDD_GPU_DRA7,
+	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value		= VDD_CORE_DRA7,
+	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic		= &tps659038,
+
+	.iva.value		= VDD_IVA_DRA7,
+	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
+};
+
 #ifdef CONFIG_SPL_BUILD
 /* No env to setup for SPL */
 static inline void setup_board_eeprom_env(void) { }
@@ -315,11 +351,18 @@ invalid_eeprom:
 
 #endif	/* CONFIG_SPL_BUILD */
 
+void vcores_init(void)
+{
+	if (board_is_am572x_idk())
+		*omap_vcores = &am572x_idk_volts;
+	else
+		*omap_vcores = &beagle_x15_volts;
+}
+
 void hw_data_init(void)
 {
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
-	*omap_vcores = &beagle_x15_volts;
 	*ctrl = &dra7xx_ctrl;
 }
 
-- 
cgit v0.10.2


From eafd4644c0edc140f034d5eb7cb07529ab0a6dc7 Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Tue, 24 May 2016 11:45:07 +0530
Subject: arm: am57xx: Fix alignment where necessary

This just fixes alignment for better readability.

Signed-off-by: Keerthy <j-keerthy@ti.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index f533b1a..ccf97b2 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -63,28 +63,28 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 }
 
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
-	.sdram_config_init	= 0x61851b32,
-	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x08000000,
-	.ref_ctrl		= 0x000040F1,
-	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36ab,
-	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x409f88a8,
-	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x5007190b,
-	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
-	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
-	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
-	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
-	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
-	.emif_rd_wr_lvl_ctl	= 0x00000000,
-	.emif_rd_wr_exec_thresh	= 0x00000305
+	.sdram_config_init		= 0x61851b32,
+	.sdram_config			= 0x61851b32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1			= 0xcccf36ab,
+	.sdram_tim2			= 0x308f7fda,
+	.sdram_tim3			= 0x409f88a8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
 };
 
 /* Ext phy ctrl regs 1-35 */
@@ -127,28 +127,28 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 };
 
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
-	.sdram_config_init	= 0x61851b32,
-	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x08000000,
-	.ref_ctrl		= 0x000040F1,
-	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36b3,
-	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x407f88a8,
-	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x5007190b,
-	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
-	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
-	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
-	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
-	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
-	.emif_rd_wr_lvl_ctl	= 0x00000000,
-	.emif_rd_wr_exec_thresh	= 0x00000305
+	.sdram_config_init		= 0x61851b32,
+	.sdram_config			= 0x61851b32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1			= 0xcccf36b3,
+	.sdram_tim2			= 0x308f7fda,
+	.sdram_tim3			= 0x407f88a8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
 };
 
 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
@@ -221,7 +221,7 @@ struct vcores_data beagle_x15_volts = {
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
 
 	.eve.value		= VDD_EVE_DRA7,
 	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
-- 
cgit v0.10.2


From e2924e5904ae413e0b4a2a0d407267e7bbc2c7c4 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Thu, 26 May 2016 19:05:44 +0530
Subject: ARM: k2g: Configure reset mux to device reset

BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.

Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.

Right now to give a default watchdog behaviour "Device reset" is
being selected.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index ca2a119..0f6bf61 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -74,4 +74,16 @@
 #define K2G_GPIO_DIR_OFFSET		0x0
 #define K2G_GPIO_SETDATA_OFFSET		0x8
 
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8			(KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT		0x0
+#define RSTMUX_LOCK8_MASK		(0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT		0x1
+#define RSTMUX_OMODE8_MASK		(0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET		0x2
+#define RSTMUX_OMODE8_INT		0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET	0x4
+
 #endif /* __ASM_ARCH_HARDWARE_K2G_H */
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index b62c412..8f16845 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+	/* Unlock the reset mux register */
+	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+	/* lock the reset mux register to prevent any spurious writes. */
+	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
 int board_early_init_f(void)
 {
 	init_plls();
 
 	k2g_mux_config();
 
+	k2g_reset_mux_config();
+
 	/* deassert FLASH_HOLD */
 	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 		     BIT(9));
-- 
cgit v0.10.2


From b2f1858455e99a91aeafe59ac73c6c047106d5e8 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 3 Jun 2016 13:05:11 -0600
Subject: arm: lib: fix push/pop-section directives

With the existing code, function symbols are defined in .text, and the
body is defined in .text.xxx. This causes (at least some version of) the
linker not to emit the function body into the final binary, since it's
part of a different section to the symbols being referenced. This of
course causes a wide variety of failures.

This change moves the push/pop-section directives before the function
symbols, and after any relate ENDPROC macro invocations, so that symbols
and bodies are all in the "pushed" sections, and thus the function bodies
are emitted into the binary.

This solves (at least) the boot problems currently seen on Tegra systems
that use SPL (i.e. all ARMv7 Tegras).

Fixes: 13b0a91a6d48 ("arm: lib: Split asm symbols into different .text subsections")
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 6c9ae91..e9ec890 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -15,9 +15,9 @@
 #define ah r1
 #endif
 
+.pushsection .text.__ashldi3, "ax"
 ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
-.pushsection .text.__ashldi3, "ax"
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -29,6 +29,6 @@ ENTRY(__aeabi_llsl)
 	mov	al, al, lsl r2
 	ret	lr
 
-.popsection
 ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
+.popsection
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index 3eb59ec..6e15774 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -15,9 +15,9 @@
 #define ah r1
 #endif
 
+.pushsection .text.__ashrdi3, "ax"
 ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
-.pushsection .text.__ashrdi3, "ax"
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -29,6 +29,6 @@ ENTRY(__aeabi_lasr)
 	mov	ah, ah, asr r2
 	ret	lr
 
-.popsection
 ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
+.popsection
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 5bfb41d..b417db2 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -45,9 +45,9 @@
  * Clobbered regs: xl, ip
  */
 
+.pushsection .text.__do_div64, "ax"
 ENTRY(__do_div64)
 UNWIND(.fnstart)
-.pushsection .text.__do_div64, "ax"
 
 	@ Test for easy paths first.
 	subs	ip, r4, #1
@@ -193,7 +193,6 @@ UNWIND(.fnstart)
 	moveq	yh, xh
 	moveq	xh, #0
 	reteq	lr
-.popsection
 UNWIND(.fnend)
 
 UNWIND(.fnstart)
@@ -212,3 +211,4 @@ Ldiv0_64:
 
 UNWIND(.fnend)
 ENDPROC(__do_div64)
+.popsection
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index f1becda..9bf93ce 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -193,10 +193,10 @@
 .endm
 
 
+.pushsection .text.__udivsi3, "ax"
 ENTRY(__udivsi3)
 ENTRY(__aeabi_uidiv)
 UNWIND(.fnstart)
-.pushsection .text.__udivsi3, "ax"
 
 	subs	r2, r1, #1
 	reteq	lr
@@ -220,14 +220,14 @@ UNWIND(.fnstart)
 	mov	r0, r0, lsr r2
 	ret	lr
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(__udivsi3)
 ENDPROC(__aeabi_uidiv)
+.popsection
 
+.pushsection .text.__umodsi3, "ax"
 ENTRY(__umodsi3)
 UNWIND(.fnstart)
-.pushsection .text.__umodsi3, "ax"
 
 	subs	r2, r1, #1			@ compare divisor with 1
 	bcc	Ldiv0
@@ -241,14 +241,14 @@ UNWIND(.fnstart)
 
 	ret	lr
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(__umodsi3)
+.popsection
 
+.pushsection .text.__divsi3, "ax"
 ENTRY(__divsi3)
 ENTRY(__aeabi_idiv)
 UNWIND(.fnstart)
-.pushsection .text.__divsi3, "ax"
 
 	cmp	r1, #0
 	eor	ip, r0, r1			@ save the sign of the result.
@@ -285,14 +285,14 @@ UNWIND(.fnstart)
 	rsbmi	r0, r0, #0
 	ret	lr
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(__divsi3)
 ENDPROC(__aeabi_idiv)
+.popsection
 
+.pushsection .text.__modsi3, "ax"
 ENTRY(__modsi3)
 UNWIND(.fnstart)
-.pushsection .text.__modsi3, "ax"
 
 	cmp	r1, #0
 	beq	Ldiv0
@@ -312,16 +312,16 @@ UNWIND(.fnstart)
 	rsbmi	r0, r0, #0
 	ret	lr
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(__modsi3)
+.popsection
 
 #ifdef CONFIG_AEABI
 
+.pushsection .text.__aeabi_uidivmod, "ax"
 ENTRY(__aeabi_uidivmod)
 UNWIND(.fnstart)
 UNWIND(.save {r0, r1, ip, lr}	)
-.pushsection .text.__aeabi_uidivmod, "ax"
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_uidiv
@@ -330,14 +330,14 @@ UNWIND(.save {r0, r1, ip, lr}	)
 	sub	r1, r1, r3
 	ret	lr
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(__aeabi_uidivmod)
+.popsection
 
+.pushsection .text.__aeabi_uidivmod, "ax"
 ENTRY(__aeabi_idivmod)
 UNWIND(.fnstart)
 UNWIND(.save {r0, r1, ip, lr}	)
-.pushsection .text.__aeabi_uidivmod, "ax"
 
 	stmfd	sp!, {r0, r1, ip, lr}
 	bl	__aeabi_idiv
@@ -346,31 +346,31 @@ UNWIND(.save {r0, r1, ip, lr}	)
 	sub	r1, r1, r3
 	ret	lr
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(__aeabi_idivmod)
+.popsection
 
 #endif
 
+.pushsection .text.Ldiv0, "ax"
 Ldiv0:
 UNWIND(.fnstart)
 UNWIND(.pad #4)
 UNWIND(.save {lr})
-.pushsection .text.Ldiv0, "ax"
 
 	str	lr, [sp, #-8]!
 	bl	__div0
 	mov	r0, #0			@ About as wrong as it could be.
 	ldr	pc, [sp], #8
 
-.popsection
 UNWIND(.fnend)
 ENDPROC(Ldiv0)
+.popsection
 
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
 /* Thumb-1 specialities */
 #if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
 ENTRY(__gnu_thumb1_case_sqi)
-.pushsection .text.__gnu_thumb1_case_sqi, "ax"
 	push	{r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -380,11 +380,11 @@ ENTRY(__gnu_thumb1_case_sqi)
 	add	lr, lr, r1
 	pop	{r1}
 	bx	lr
-.popsection
 ENDPROC(__gnu_thumb1_case_sqi)
+.popsection
 
+_.pushsection .text.__gnu_thumb1_case_uqi, "ax"
 ENTRY(__gnu_thumb1_case_uqi)
-.pushsection .text.__gnu_thumb1_case_uqi, "ax"
 	push	{r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -394,11 +394,11 @@ ENTRY(__gnu_thumb1_case_uqi)
 	add	lr, lr, r1
 	pop	{r1}
 	bx	lr
-.popsection
 ENDPROC(__gnu_thumb1_case_uqi)
+.popsection
 
-ENTRY(__gnu_thumb1_case_shi)
 .pushsection .text.__gnu_thumb1_case_shi, "ax"
+ENTRY(__gnu_thumb1_case_shi)
 	push	{r0, r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -409,11 +409,11 @@ ENTRY(__gnu_thumb1_case_shi)
 	add	lr, lr, r1
 	pop	{r0, r1}
 	bx	lr
-.popsection
 ENDPROC(__gnu_thumb1_case_shi)
+.popsection
 
-ENTRY(__gnu_thumb1_case_uhi)
 .pushsection .text.__gnu_thumb1_case_uhi, "ax"
+ENTRY(__gnu_thumb1_case_uhi)
 	push	{r0, r1}
 	mov	r1, lr
 	lsrs	r1, r1, #1
@@ -424,6 +424,6 @@ ENTRY(__gnu_thumb1_case_uhi)
 	add	lr, lr, r1
 	pop	{r0, r1}
 	bx	lr
-.popsection
 ENDPROC(__gnu_thumb1_case_uhi)
+.popsection
 #endif
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index f710ccb..ead33e5 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -15,9 +15,9 @@
 #define ah r1
 #endif
 
+.pushsection .text.__lshldi3, "ax"
 ENTRY(__lshrdi3)
 ENTRY(__aeabi_llsr)
-.pushsection .text.__lshldi3, "ax"
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -29,6 +29,6 @@ ENTRY(__aeabi_llsr)
 	mov	ah, ah, lsr r2
 	ret	lr
 
-.popsection
 ENDPROC(__lshrdi3)
 ENDPROC(__aeabi_llsr)
+.popsection
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
index bc255c5..d7c93e7 100644
--- a/arch/arm/lib/muldi3.S
+++ b/arch/arm/lib/muldi3.S
@@ -23,9 +23,9 @@
 #define yh r3
 #endif
 
+.pushsection .text.__muldi3, "ax"
 ENTRY(__muldi3)
 ENTRY(__aeabi_lmul)
-.pushsection .text.__muldi3, "ax"
 
 	mul	xh, yl, xh
 	mla	xh, xl, yh, xh
@@ -43,6 +43,6 @@ ENTRY(__aeabi_lmul)
 	adc	xh, xh, ip, lsr #16
 	ret	lr
 
-.popsection
 ENDPROC(__muldi3)
 ENDPROC(__aeabi_lmul)
+.popsection
diff --git a/arch/arm/lib/uldivmod.S b/arch/arm/lib/uldivmod.S
index bbc44c6..7246996 100644
--- a/arch/arm/lib/uldivmod.S
+++ b/arch/arm/lib/uldivmod.S
@@ -33,8 +33,8 @@ THUMB(
 TMP	.req	r8
 )
 
-ENTRY(__aeabi_uldivmod)
 .pushsection .text.__aeabi_uldivmod, "ax"
+ENTRY(__aeabi_uldivmod)
 
 	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
 	@ Test if B == 0
@@ -242,5 +242,5 @@ L_div_by_0:
 	mov	R_0, #0
 	mov	R_1, #0
 	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
-.popsection
 ENDPROC(__aeabi_uldivmod)
+.popsection
-- 
cgit v0.10.2


From d8e5163ad81a2810c66a9a98e5111769378f5f5f Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Wed, 4 May 2016 10:20:21 +0800
Subject: drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9073917..b26269c 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 	/* Per FSL Application Note: AN2805 */
 	ss_en = 1;
 #endif
-	clk_adjust = popts->clk_adjust;
+	if (fsl_ddr_get_version(0) >= 0x40701) {
+		/* clk_adjust in 5-bits on T-series and LS-series */
+		clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+	} else {
+		/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+		clk_adjust = (popts->clk_adjust & 0xF) << 23;
+	}
+
 	ddr->ddr_sdram_clk_cntl = (0
 				   | ((ss_en & 0x1) << 31)
-				   | ((clk_adjust & 0xF) << 23)
+				   | clk_adjust
 				   );
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
-- 
cgit v0.10.2


From e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Wed, 4 May 2016 10:20:22 +0800
Subject: board/freescale: Update ddr clk_adjust

This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index f819c99..b39b561 100644
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     8, 0x090A0B0B, 0x0C0D0E0C,},
+	{1,  1900, 0, 8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0, 8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index d3f4082..ad709ba 100644
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -34,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E0A,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0,  8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0,  8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0,  8,     6, 0x0708090B, 0x0C0D0E0A,},
+	{1,  1900, 0,  8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0,  8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index 8ca166b..a77ddf3 100644
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{1,  1666, 0, 6,     7, 0x07090800, 0x00000000,},
-	{1,  1900, 0, 6,     7, 0x07090800, 0x00000000,},
-	{1,  2200, 0, 6,     7, 0x07090800, 0x00000000,},
+	{1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
 #endif
 	{}
 };
diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
index b76ea61..eba62c3 100644
--- a/board/freescale/ls2080aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
 	{}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index b3c6306..8d5a490 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 5,     9, 0x090A0B0E, 0x0F11110C,},
-	{2,  1900, 0, 6,   0xA, 0x0B0C0E11, 0x1214140F,},
-	{2,  2300, 0, 6,   0xB, 0x0C0D0F12, 0x14161610,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 10,    9, 0x090A0B0E, 0x0F11110C,},
+	{2,  1900, 0, 12,  0xA, 0x0B0C0E11, 0x1214140F,},
+	{2,  2300, 0, 12,  0xB, 0x0C0D0F12, 0x14161610,},
 	{}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
 	{}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 2d4d10f..912d6a9 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 #if defined(CONFIG_SYS_FSL_DDR4)
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
-	{1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+	{1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
+	{1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+	{1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index adf9fd5..60ab9ff 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 	{}
 };
 
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
index a6e1673..1e08746 100644
--- a/board/freescale/t1040qds/ddr.h
+++ b/board/freescale/t1040qds/ddr.h
@@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{1,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  2200, 0, 4,     7, 0x08090A0D, 0x0F0F100C,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index b9c02f7..012991c 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},
+	{2,  1600, 4, 8,     6, 0x07090A0c, 0x0e0f100a},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{2,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9c26fdf..255ab2c 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
 	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
 	 */
-	{2,  1200,  0,  5,  7,  0x0708090a,  0x0b0c0d09},
-	{2,  1400,  0,  5,  7,  0x08090a0c,  0x0d0e0f0a},
-	{2,  1700,  0,  5,  8,  0x090a0b0c,  0x0e10110c},
-	{2,  1900,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-	{2,  2140,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-	{1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
-	{1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
-	{1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
-	{1,  1700,  0,  4,  8,  0x080a0a0c,  0x0c0d0e0a},
-	{1,  1900,  0,  5,  8,  0x090a0c0d,  0x0e0f110c},
-	{1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
+	{2,  1200,  0, 10,  7,  0x0708090a,  0x0b0c0d09},
+	{2,  1400,  0, 10,  7,  0x08090a0c,  0x0d0e0f0a},
+	{2,  1700,  0, 10,  8,  0x090a0b0c,  0x0e10110c},
+	{2,  1900,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{2,  2140,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{1,  1200,  0, 10,  7,  0x0808090a,  0x0b0c0c0a},
+	{1,  1500,  0, 10,  6,  0x07070809,  0x0a0b0b09},
+	{1,  1600,  0, 10,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{1,  1700,  0,  8,  8,  0x080a0a0c,  0x0c0d0e0a},
+	{1,  1900,  0, 10,  8,  0x090a0c0d,  0x0e0f110c},
+	{1,  2140,  0,  8,  8,  0x090a0b0d,  0x0e0f110b},
 	{}
 };
 
@@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 	/* TODO: need tuning these parameters if RDIMM is used */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
 	{}
 };
 
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
index 08cbb60..175cf56 100644
--- a/board/freescale/t208xrdb/ddr.h
+++ b/board/freescale/t208xrdb/ddr.h
@@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{2,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
+	{2,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{2,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
+	{1,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{1,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
 	{}
 };
 
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 4d0e3c4..0b0cc9a 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
 	{}
 };
 
@@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
 	{}
 };
 
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
index 7b85476..f01ebb2 100644
--- a/board/freescale/t4rdb/ddr.h
+++ b/board/freescale/t4rdb/ddr.h
@@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
 	{}
 };
 
@@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
 	{}
 };
 
-- 
cgit v0.10.2


From cc634e283659096e792f9515e6a9268b58179954 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Thu, 12 May 2016 19:12:58 +0800
Subject: mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function

In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3acf9e8..57ad975 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -308,14 +308,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
 	(struct mmc_cmd *cmd,
 	 struct mmc_data *data) {
-#ifdef CONFIG_FSL_LAYERSCAPE
 	unsigned start = 0;
-#else
-	unsigned start = (unsigned)data->dest ;
-#endif
+	unsigned end = 0;
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
-	unsigned end = start+size ;
 #ifdef CONFIG_FSL_LAYERSCAPE
 	dma_addr_t addr;
 
@@ -324,7 +320,10 @@ static void check_and_invalidate_dcache_range
 		printf("Error found for upper 32 bits\n");
 	else
 		start = lower_32_bits(addr);
+#else
+	start = (unsigned)data->dest;
 #endif
+	end = start + size;
 	invalidate_dcache_range(start, end);
 }
 
-- 
cgit v0.10.2


From c4f97b1f53a48ab52efc221b73a235797375fbfb Mon Sep 17 00:00:00 2001
From: Vincent Siles <vincent.siles@provenrun.com>
Date: Wed, 18 May 2016 14:41:14 +0200
Subject: board: ls102xa: Fix ICID setup

LS102A ref manual dictates that ICID have to be written to the MSB
of the ICID register, not to the LSB.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>

diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index 3d5404e..0abaffb 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -12,9 +12,12 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
 {
 	void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int i;
+	u32 icid;
 
-	for (i = 0; i < num; i++)
-		out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
+	for (i = 0; i < num; i++) {
+		icid = (id[i].stream_id & 0xff) << 24;
+		out_be32((u32 *)(scfg + id[i].offset), icid);
+	}
 }
 
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
-- 
cgit v0.10.2


From 5605dc6135f6f26560ef3b0c6ebc5141c531179a Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Wed, 18 May 2016 21:11:19 -0700
Subject: drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index b26269c..1d5cec6 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 14)
+		| ((wr_lat & 0x10) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)
-- 
cgit v0.10.2


From 3378727d13dac410d8ef2d8426d4c9bfc4974405 Mon Sep 17 00:00:00 2001
From: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Date: Tue, 17 May 2016 07:18:40 +0000
Subject: pcie/layerscape: fix bug in bus number computation when setting
 msi-map

When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.

The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose->first_busno, so that has to be
subtracted from the PCI device id.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Acked-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0ba960e..2e6b986 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -569,7 +569,7 @@ static void fdt_fixup_pcie(void *blob)
 	unsigned char header_type;
 	int index;
 	u32 streamid;
-	pci_dev_t dev;
+	pci_dev_t dev, bdf;
 	int bus;
 	unsigned short id;
 	struct pci_controller *hose;
@@ -611,12 +611,15 @@ static void fdt_fixup_pcie(void *blob)
 					continue;
 				}
 
+				/* the DT fixup must be relative to the hose first_busno */
+				bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
+
 				/* map PCI b.d.f to streamID in LUT */
-				ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+				ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
 							streamid);
 
 				/* update msi-map in device tree */
-				fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+				fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
 							   streamid);
 			}
 		}
-- 
cgit v0.10.2


From 931e8751af8ca9ff4395c3f033c5217d48f5698f Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 26 May 2016 13:59:03 -0700
Subject: board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not
 defined

U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..897793d 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
 	int err;
+#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index fb39af6..52e5e3f 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -156,7 +156,9 @@ int board_init(void)
 {
 	char *env_hwconfig;
 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
 	u32 val;
 
 	init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
 
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_MC_ENET
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
 
 	return 0;
 }
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
 	int err;
+#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
-- 
cgit v0.10.2


From b06f6f2f0347b6010943fa2ca2f26d1786fdba78 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 26 May 2016 12:19:03 -0700
Subject: drivers/ddr/fsl: Disabling data init if ECC is not enabled

If ECC is not enabled, data init can be disabled to speed up booting.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index d0075ff..793d12a 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -886,7 +886,8 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 	} else
 		popts->ecc_mode = 1;
 #endif
-	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+	/* 1 = use memory controler to init data */
+	popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
 
 	/*
 	 * Choose DQS config
-- 
cgit v0.10.2


From d36740462a35aaaaa7e01e43c6ff666467070427 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Wed, 25 May 2016 16:15:00 +0800
Subject: driver/ddr/fsl: Check condition for erratum A-009803

Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 5039f5d..d37e247 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -206,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 	/* part 1 of 2 */
-	if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
-		ddr_out32(&ddr->ddr_sdram_rcw_2,
-			  regs->ddr_sdram_rcw_2 & ~0x0f000000);
+	if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+			ddr_out32(&ddr->ddr_sdram_rcw_2,
+				  regs->ddr_sdram_rcw_2 & ~0x0f000000);
+		}
+		ddr_out32(&ddr->err_disable, regs->err_disable |
+			  DDR_ERR_DISABLE_APED);
 	}
-
-	ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 #else
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
@@ -395,22 +397,24 @@ step2:
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-		/* if it's RDIMM */
-		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-			for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-				if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-					continue;
-				set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-							MD_CNTL_MD_EN |
-							MD_CNTL_CS_SEL(i) |
-							0x070000ed,
-							MD_CNTL_MD_EN);
-				udelay(1);
+		if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+			/* if it's RDIMM */
+			if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+				for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+					if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+						continue;
+					set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+								MD_CNTL_MD_EN |
+								MD_CNTL_CS_SEL(i) |
+								0x070000ed,
+								MD_CNTL_MD_EN);
+					udelay(1);
+				}
 			}
-		}
 
-		ddr_out32(&ddr->err_disable,
-			  regs->err_disable & ~DDR_ERR_DISABLE_APED);
+			ddr_out32(&ddr->err_disable,
+				  regs->err_disable & ~DDR_ERR_DISABLE_APED);
+		}
 #endif
 	}
 #endif
-- 
cgit v0.10.2


From 3e06ba8f25521cb385c2fe9d2b312244f788a02a Mon Sep 17 00:00:00 2001
From: Shaohui Xie <Shaohui.Xie@nxp.com>
Date: Mon, 30 May 2016 14:26:55 +0800
Subject: armv8: ls1043aqds: fix usb PWRFAULT setting

SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should
be used for USB 3 & 2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index ca393e8..7e47ef0 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -238,8 +238,8 @@ int board_early_init_f(void)
 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 	usb_pwrfault =
-		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
-		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif
-- 
cgit v0.10.2


From 1e49a2318ad22ad842bf4c768398f0f5f9872dc0 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:26 +0530
Subject: armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE

It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.

So put SMMU configuration code under SMMU_BASE.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 04831ca..d743ffe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
 	bl	ccn504_set_qos
 #endif
 
+#ifdef SMMU_BASE
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
 	ldr	w0, [x1, #0x10]
 	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
 	str	w0, [x1, #0x10]
+#endif
 
 	/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-- 
cgit v0.10.2


From 22a44d087acdfe55c48c0f096a0238fb7ed49762 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:27 +0530
Subject: armv8: fsl-layerscape: Avoid LS1043A specifc defines

Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..0ae61d6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -224,7 +224,7 @@ int sata_init(void)
 }
 #endif
 
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index f71c2c1..c4fb7c9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -55,7 +55,7 @@ enum srds {
 	FSL_SRDS_1  = 0,
 	FSL_SRDS_2  = 1,
 };
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,
-- 
cgit v0.10.2


From d074c06ba7a2eec4fac099d4c9830509803bcf8f Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:28 +0530
Subject: driver: mtd: spi: Adding support for QSPI flash

Serial number, vendor id and page size are added for QSPI flash
common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..c577d9e 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,		     WR_QPP},
 	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_FULL,		     WR_QPP},
+	{"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL,                   WR_QPP},
 	{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,		     WR_QPP},
 	{"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index fa0e799..64d4e0f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1072,7 +1072,8 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * sector that is not overlaid by the parameter sectors.
 	 * The uniform sector erase command has no effect on parameter sectors.
 	 */
-	if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+	if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+	    (ext_jedec & 0xff00) == 0x4d00) {
 		int ret;
 		u8 id[6];
 
@@ -1146,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * have 256b pages.
 	 */
 	if (ext_jedec == 0x4d00) {
-		if ((jedec == 0x0215) || (jedec == 0x216))
+		if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
 			flash->page_size = 256;
 		else
 			flash->page_size = 512;
-- 
cgit v0.10.2


From d9d9c977ec96ce74e558012ffda8ba590fcb9591 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:29 +0530
Subject: armv8: fsl-layerscape: fix compile warning "rcw_tmp"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
  u32 rcw_tmp;

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 453a93d..4fc3186 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+	defined(CONFIG_SYS_DPAA_FMAN)
+
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
-- 
cgit v0.10.2


From ddd8a08052052561af38ecbe30930001a2ae940b Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:30 +0530
Subject: armv8: fsl-layerscape: Organize SoC overview at common location

SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc

Also move README.lsch2 and README.lsch3 in same folder.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
deleted file mode 100644
index a6ef830..0000000
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2015 Freescale Semiconductor
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-Freescale LayerScape with Chassis Generation 2
-
-This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
-for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
deleted file mode 100644
index f9323c1..0000000
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ /dev/null
@@ -1,325 +0,0 @@
-#
-# Copyright 2014-2015 Freescale Semiconductor
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-Freescale LayerScape with Chassis Generation 3
-
-This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2080A.
-
-DDR Layout
-============
-Entire DDR region splits into two regions.
- - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
- - Region 2 is at 0x80_8000_0000 to the top of total memory,
-   for example 16GB, 0x83_ffff_ffff.
-
-All DDR memory is marked as cache-enabled.
-
-When MC and Debug server is enabled, they carve 512MB away from the high
-end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
-with MC and Debug server enabled. Linux only sees 15.5GB.
-
-The reserved 512MB layout looks like
-
-   +---------------+ <-- top/end of memory
-   |    256MB      |  debug server
-   +---------------+
-   |    256MB      |  MC
-   +---------------+
-   |     ...       |
-
-MC requires the memory to be aligned with 512MB, so even debug server is
-not enabled, 512MB is reserved, not 256MB.
-
-Flash Layout
-============
-
-(1) A typical layout of various images (including Linux and other firmware images)
-   is shown below considering a 32MB NOR flash device present on most
-   pre-silicon platforms (simulator and emulator):
-
-	-------------------------
-	| 	FIT Image	|
-	| (linux + DTB + RFS)	|
-	------------------------- ----> 0x0120_0000
-	| 	Debug Server FW |
-	------------------------- ----> 0x00C0_0000
-	|	AIOP FW 	|
-	------------------------- ----> 0x0070_0000
-	|	MC FW 		|
-	------------------------- ----> 0x006C_0000
-	| 	MC DPL Blob 	|
-	------------------------- ----> 0x0020_0000
-	| 	BootLoader + Env|
-	------------------------- ----> 0x0000_1000
-	|	PBI 		|
-	------------------------- ----> 0x0000_0080
-	|	RCW 		|
-	------------------------- ----> 0x0000_0000
-
-	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
-
-(2) A typical layout of various images (including Linux and other firmware images)
-    is shown below considering a 128MB NOR flash device present on QDS and RDB
-    boards:
-	----------------------------------------- ----> 0x5_8800_0000 ---
-	|	.. Unused .. (7M)		|			|
-	----------------------------------------- ----> 0x5_8790_0000	|
-	| FIT Image (linux + DTB + RFS)	(40M)	|			|
-	----------------------------------------- ----> 0x5_8510_0000	|
-	|	PHY firmware (2M)	 	|			|
-	----------------------------------------- ----> 0x5_84F0_0000	| 64K
-	|	Debug Server FW (2M)		|			| Alt
-	----------------------------------------- ----> 0x5_84D0_0000	| Bank
-	|	AIOP FW (4M)			|			|
-	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
-	|	MC DPC Blob (1M) 		|			|
-	----------------------------------------- ----> 0x5_8480_0000	|
-	|	MC DPL Blob (1M)		|			|
-	----------------------------------------- ----> 0x5_8470_0000	|
-	| 	MC FW (4M)			|			|
-	----------------------------------------- ----> 0x5_8430_0000	|
-	|	BootLoader Environment (1M) 	|			|
-	----------------------------------------- ----> 0x5_8420_0000	|
-	|	BootLoader (1M)			|			|
-	----------------------------------------- ----> 0x5_8410_0000	|
-	|	RCW and PBI (1M) 		|			|
-	----------------------------------------- ----> 0x5_8400_0000 ---
-	|	.. Unused .. (7M)		|			|
-	----------------------------------------- ----> 0x5_8390_0000	|
-	| FIT Image (linux + DTB + RFS)	(40M)	|			|
-	----------------------------------------- ----> 0x5_8110_0000	|
-	|	PHY firmware (2M)	 	|			|
-	----------------------------------------- ----> 0x5_80F0_0000	| 64K
-	|	Debug Server FW (2M)		|			| Bank
-	----------------------------------------- ----> 0x5_80D0_0000	|
-	|	AIOP FW (4M)			|			|
-	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
-	|	MC DPC Blob (1M) 		|			|
-	----------------------------------------- ----> 0x5_8080_0000	|
-	|	MC DPL Blob (1M)		|			|
-	----------------------------------------- ----> 0x5_8070_0000	|
-	| 	MC FW (4M)			|			|
-	----------------------------------------- ----> 0x5_8030_0000	|
-	|	BootLoader Environment (1M) 	|			|
-	----------------------------------------- ----> 0x5_8020_0000	|
-	|	BootLoader (1M)			|			|
-	----------------------------------------- ----> 0x5_8010_0000	|
-	|	RCW and PBI (1M) 		|			|
-	----------------------------------------- ----> 0x5_8000_0000 ---
-
-	128-MB NOR flash layout for QDS and RDB boards
-
-Environment Variables
-=====================
-mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
-		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
-
-mcmemsize:	MC DRAM block size. If this variable is not defined, the value
-		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
-
-Booting from NAND
--------------------
-Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
-The difference between NAND boot RCW image and NOR boot image is the PBI
-command sequence. Below is one example for PBI commands for QDS which uses
-NAND device with 2KB/page, block size 128KB.
-
-1) CCSR 4-byte write to 0x00e00404, data=0x00000000
-2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
-The above two commands set bootloc register to 0x00000000_1800a000 where
-the u-boot code will be running in OCRAM.
-
-3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
-BLOCK_SIZE=0x00014000
-This command copies u-boot image from NAND device into OCRAM. The values need
-to adjust accordingly.
-
-SRC		should match the cfg_rcw_src, the reset config pins. It depends
-		on the NAND device. See reference manual for cfg_rcw_src.
-SRC_ADDR	is the offset of u-boot-with-spl.bin image in NAND device. In
-		the example above, 128KB. For easy maintenance, we put it at
-		the beginning of next block from RCW.
-DEST_ADDR	is fixed at 0x1800a000, matching bootloc set above.
-BLOCK_SIZE	is the size to be copied by PBI.
-
-RCW image should be written to the beginning of NAND device. Example of using
-u-boot command
-
-nand write <rcw image in memory> 0 <size of rcw image>
-
-To form the NAND image, build u-boot with NAND config, for example,
-ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
-The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
-
-nand write <u-boot image in memory> 200000 <size of u-boot image>
-
-With these two images in NAND device, the board can boot from NAND.
-
-Another example for RDB boards,
-
-1) CCSR 4-byte write to 0x00e00404, data=0x00000000
-2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
-3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
-BLOCK_SIZE=0x00014000
-
-nand write <rcw image in memory> 0 <size of rcw image>
-nand write <u-boot image in memory> 80000 <size of u-boot image>
-
-Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
-to match board NAND device with 4KB/page, block size 512KB.
-
-MMU Translation Tables
-======================
-
-(1) Early MMU Tables:
-
-     Level 0                   Level 1                   Level 2
-------------------        ------------------        ------------------
-| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
-------------------        ------------------        ------------------
-| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
-------------------   |    ------------------        ------------------
-|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
-------------------   |    ------------------        ------------------
-                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
-                     |    ------------------        ------------------
-                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
-                     |    ------------------        ------------------
-                     |            ...                      ...
-                     |    ------------------
-                     |    | 0x05_8000_0000 |  --|
-                     |    ------------------    |
-                     |    | 0x05_c000_0000 |    |
-                     |    ------------------    |
-                     |            ...           |
-                     |    ------------------    |   ------------------
-                     |--> | 0x80_0000_0000 |    |-> | 0x00_3000_0000 |
-                          ------------------        ------------------
-                          | 0x80_4000_0000 |        | 0x00_3020_0000 |
-                          ------------------        ------------------
-                          | 0x80_8000_0000 |        | 0x00_3040_0000 |
-                          ------------------        ------------------
-                          | 0x80_c000_0000 |        | 0x00_3060_0000 |
-                          ------------------        ------------------
-                          | 0x81_0000_0000 |        | 0x00_3080_0000 |
-                          ------------------        ------------------
-			         ...	                   ...
-
-(2) Final MMU Tables:
-
-     Level 0                   Level 1                   Level 2
-------------------        ------------------        ------------------
-| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
-------------------        ------------------        ------------------
-| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
-------------------   |    ------------------        ------------------
-|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
-------------------   |    ------------------        ------------------
-                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
-                     |    ------------------        ------------------
-                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
-                     |    ------------------        ------------------
-                     |            ...                      ...
-                     |    ------------------
-                     |    | 0x08_0000_0000 | --|
-                     |    ------------------   |
-                     |    | 0x08_4000_0000 |   |
-                     |    ------------------   |
-                     |            ...          |
-                     |    ------------------   |    ------------------
-                     |--> | 0x80_0000_0000 |   |--> | 0x08_0000_0000 |
-                          ------------------        ------------------
-                          | 0x80_4000_0000 |        | 0x08_0020_0000 |
-                          ------------------        ------------------
-                          | 0x80_8000_0000 |        | 0x08_0040_0000 |
-                          ------------------        ------------------
-                          | 0x80_c000_0000 |        | 0x08_0060_0000 |
-                          ------------------        ------------------
-                          | 0x81_0000_0000 |        | 0x08_0080_0000 |
-                          ------------------        ------------------
-			         ...	                   ...
-
-
-DPAA2 commands to manage Management Complex (MC)
-------------------------------------------------
-DPAA2 commands has been introduced to manage Management Complex
-(MC). These commands are used to start mc, aiop and apply DPL
-from u-boot command prompt.
-
-Please note Management complex Firmware(MC), DPL and DPC are no
-more deployed during u-boot boot-sequence.
-
-Commands:
-a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
-c) fsl_mc start aiop <FW_addr> - Start AIOP
-
-How to use commands :-
-1. Command sequence for u-boot ethernet:
-   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-   b) DPMAC net-devices are now available for use
-
-   Example-
-	Assumption: MC firmware, DPL and DPC dtb is already programmed
-	on NOR flash.
-
-	=> fsl_mc start mc 580300000 580800000
-	=> setenv ethact DPMAC1@xgmii
-	=> ping $serverip
-
-2. Command sequence for Linux boot:
-   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-   b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
-   c) No DPMAC net-devices are available for use in u-boot
-   d) boot Linux
-
-   Example-
-	Assumption: MC firmware, DPL and DPC dtb is already programmed
-	on NOR flash.
-
-	=> fsl_mc start mc 580300000 580800000
-	=> setenv ethact DPMAC1@xgmii
-	=> tftp a0000000 kernel.itb
-	=> fsl_mc apply dpl 580700000
-	=> bootm a0000000
-
-3. Command sequence for AIOP boot:
-   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
-   b) fsl_mc start aiop <FW_addr> - Start AIOP
-   c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
-   d) No DPMAC net-devices are availabe for use in u-boot
-  Please note actual AIOP start will happen during DPL parsing of
-  Management complex
-
-  Example-
-	Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
-	programmed on NOR flash.
-
-	=> fsl_mc start mc 580300000 580800000
-	=> fsl_mc start aiop 0x580900000
-	=> setenv ethact DPMAC1@xgmii
-	=> fsl_mc apply dpl 580700000
-
-Errata A009635
----------------
-If the core runs at higher than x3 speed of the platform, there is
-possiblity about sev instruction to getting missed by other cores.
-This is because of SoC Run Control block may not able to sample
-the EVENTI(Sev) signals.
-
-Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
-wake up A57 cores
-
-Errata workaround uses Env variable "a009635_interval_val". It uses decimal
-value.
-- Default value of env variable is platform clock (MHz)
-
-- User can modify default value by updating the env variable
-  setenv a009635_interval_val 600; saveenv;
-  It configure platform clock as 600 MHz
-
-- Env variable as 0 signifies no workaround
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
new file mode 100644
index 0000000..a6ef830
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
new file mode 100644
index 0000000..f9323c1
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -0,0 +1,325 @@
+#
+# Copyright 2014-2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 3
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
+for example LS2080A.
+
+DDR Layout
+============
+Entire DDR region splits into two regions.
+ - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
+ - Region 2 is at 0x80_8000_0000 to the top of total memory,
+   for example 16GB, 0x83_ffff_ffff.
+
+All DDR memory is marked as cache-enabled.
+
+When MC and Debug server is enabled, they carve 512MB away from the high
+end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
+with MC and Debug server enabled. Linux only sees 15.5GB.
+
+The reserved 512MB layout looks like
+
+   +---------------+ <-- top/end of memory
+   |    256MB      |  debug server
+   +---------------+
+   |    256MB      |  MC
+   +---------------+
+   |     ...       |
+
+MC requires the memory to be aligned with 512MB, so even debug server is
+not enabled, 512MB is reserved, not 256MB.
+
+Flash Layout
+============
+
+(1) A typical layout of various images (including Linux and other firmware images)
+   is shown below considering a 32MB NOR flash device present on most
+   pre-silicon platforms (simulator and emulator):
+
+	-------------------------
+	| 	FIT Image	|
+	| (linux + DTB + RFS)	|
+	------------------------- ----> 0x0120_0000
+	| 	Debug Server FW |
+	------------------------- ----> 0x00C0_0000
+	|	AIOP FW 	|
+	------------------------- ----> 0x0070_0000
+	|	MC FW 		|
+	------------------------- ----> 0x006C_0000
+	| 	MC DPL Blob 	|
+	------------------------- ----> 0x0020_0000
+	| 	BootLoader + Env|
+	------------------------- ----> 0x0000_1000
+	|	PBI 		|
+	------------------------- ----> 0x0000_0080
+	|	RCW 		|
+	------------------------- ----> 0x0000_0000
+
+	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
+
+(2) A typical layout of various images (including Linux and other firmware images)
+    is shown below considering a 128MB NOR flash device present on QDS and RDB
+    boards:
+	----------------------------------------- ----> 0x5_8800_0000 ---
+	|	.. Unused .. (7M)		|			|
+	----------------------------------------- ----> 0x5_8790_0000	|
+	| FIT Image (linux + DTB + RFS)	(40M)	|			|
+	----------------------------------------- ----> 0x5_8510_0000	|
+	|	PHY firmware (2M)	 	|			|
+	----------------------------------------- ----> 0x5_84F0_0000	| 64K
+	|	Debug Server FW (2M)		|			| Alt
+	----------------------------------------- ----> 0x5_84D0_0000	| Bank
+	|	AIOP FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
+	|	MC DPC Blob (1M) 		|			|
+	----------------------------------------- ----> 0x5_8480_0000	|
+	|	MC DPL Blob (1M)		|			|
+	----------------------------------------- ----> 0x5_8470_0000	|
+	| 	MC FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8430_0000	|
+	|	BootLoader Environment (1M) 	|			|
+	----------------------------------------- ----> 0x5_8420_0000	|
+	|	BootLoader (1M)			|			|
+	----------------------------------------- ----> 0x5_8410_0000	|
+	|	RCW and PBI (1M) 		|			|
+	----------------------------------------- ----> 0x5_8400_0000 ---
+	|	.. Unused .. (7M)		|			|
+	----------------------------------------- ----> 0x5_8390_0000	|
+	| FIT Image (linux + DTB + RFS)	(40M)	|			|
+	----------------------------------------- ----> 0x5_8110_0000	|
+	|	PHY firmware (2M)	 	|			|
+	----------------------------------------- ----> 0x5_80F0_0000	| 64K
+	|	Debug Server FW (2M)		|			| Bank
+	----------------------------------------- ----> 0x5_80D0_0000	|
+	|	AIOP FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
+	|	MC DPC Blob (1M) 		|			|
+	----------------------------------------- ----> 0x5_8080_0000	|
+	|	MC DPL Blob (1M)		|			|
+	----------------------------------------- ----> 0x5_8070_0000	|
+	| 	MC FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8030_0000	|
+	|	BootLoader Environment (1M) 	|			|
+	----------------------------------------- ----> 0x5_8020_0000	|
+	|	BootLoader (1M)			|			|
+	----------------------------------------- ----> 0x5_8010_0000	|
+	|	RCW and PBI (1M) 		|			|
+	----------------------------------------- ----> 0x5_8000_0000 ---
+
+	128-MB NOR flash layout for QDS and RDB boards
+
+Environment Variables
+=====================
+mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
+		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+mcmemsize:	MC DRAM block size. If this variable is not defined, the value
+		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting from NAND
+-------------------
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands for QDS which uses
+NAND device with 2KB/page, block size 128KB.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+
+3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+
+SRC		should match the cfg_rcw_src, the reset config pins. It depends
+		on the NAND device. See reference manual for cfg_rcw_src.
+SRC_ADDR	is the offset of u-boot-with-spl.bin image in NAND device. In
+		the example above, 128KB. For easy maintenance, we put it at
+		the beginning of next block from RCW.
+DEST_ADDR	is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE	is the size to be copied by PBI.
+
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+
+nand write <rcw image in memory> 0 <size of rcw image>
+
+To form the NAND image, build u-boot with NAND config, for example,
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
+
+nand write <u-boot image in memory> 200000 <size of u-boot image>
+
+With these two images in NAND device, the board can boot from NAND.
+
+Another example for RDB boards,
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+
+nand write <rcw image in memory> 0 <size of rcw image>
+nand write <u-boot image in memory> 80000 <size of u-boot image>
+
+Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
+to match board NAND device with 4KB/page, block size 512KB.
+
+MMU Translation Tables
+======================
+
+(1) Early MMU Tables:
+
+     Level 0                   Level 1                   Level 2
+------------------        ------------------        ------------------
+| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
+------------------        ------------------        ------------------
+| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
+------------------   |    ------------------        ------------------
+|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
+------------------   |    ------------------        ------------------
+                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
+                     |    ------------------        ------------------
+                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
+                     |    ------------------        ------------------
+                     |            ...                      ...
+                     |    ------------------
+                     |    | 0x05_8000_0000 |  --|
+                     |    ------------------    |
+                     |    | 0x05_c000_0000 |    |
+                     |    ------------------    |
+                     |            ...           |
+                     |    ------------------    |   ------------------
+                     |--> | 0x80_0000_0000 |    |-> | 0x00_3000_0000 |
+                          ------------------        ------------------
+                          | 0x80_4000_0000 |        | 0x00_3020_0000 |
+                          ------------------        ------------------
+                          | 0x80_8000_0000 |        | 0x00_3040_0000 |
+                          ------------------        ------------------
+                          | 0x80_c000_0000 |        | 0x00_3060_0000 |
+                          ------------------        ------------------
+                          | 0x81_0000_0000 |        | 0x00_3080_0000 |
+                          ------------------        ------------------
+			         ...	                   ...
+
+(2) Final MMU Tables:
+
+     Level 0                   Level 1                   Level 2
+------------------        ------------------        ------------------
+| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
+------------------        ------------------        ------------------
+| 0x80_0000_0000 | --|    | 0x00_4000_0000 |        | 0x00_0020_0000 |
+------------------   |    ------------------        ------------------
+|    invalid     |   |    | 0x00_8000_0000 |        | 0x00_0040_0000 |
+------------------   |    ------------------        ------------------
+                     |    | 0x00_c000_0000 |        | 0x00_0060_0000 |
+                     |    ------------------        ------------------
+                     |    | 0x01_0000_0000 |        | 0x00_0080_0000 |
+                     |    ------------------        ------------------
+                     |            ...                      ...
+                     |    ------------------
+                     |    | 0x08_0000_0000 | --|
+                     |    ------------------   |
+                     |    | 0x08_4000_0000 |   |
+                     |    ------------------   |
+                     |            ...          |
+                     |    ------------------   |    ------------------
+                     |--> | 0x80_0000_0000 |   |--> | 0x08_0000_0000 |
+                          ------------------        ------------------
+                          | 0x80_4000_0000 |        | 0x08_0020_0000 |
+                          ------------------        ------------------
+                          | 0x80_8000_0000 |        | 0x08_0040_0000 |
+                          ------------------        ------------------
+                          | 0x80_c000_0000 |        | 0x08_0060_0000 |
+                          ------------------        ------------------
+                          | 0x81_0000_0000 |        | 0x08_0080_0000 |
+                          ------------------        ------------------
+			         ...	                   ...
+
+
+DPAA2 commands to manage Management Complex (MC)
+------------------------------------------------
+DPAA2 commands has been introduced to manage Management Complex
+(MC). These commands are used to start mc, aiop and apply DPL
+from u-boot command prompt.
+
+Please note Management complex Firmware(MC), DPL and DPC are no
+more deployed during u-boot boot-sequence.
+
+Commands:
+a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+c) fsl_mc start aiop <FW_addr> - Start AIOP
+
+How to use commands :-
+1. Command sequence for u-boot ethernet:
+   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+   b) DPMAC net-devices are now available for use
+
+   Example-
+	Assumption: MC firmware, DPL and DPC dtb is already programmed
+	on NOR flash.
+
+	=> fsl_mc start mc 580300000 580800000
+	=> setenv ethact DPMAC1@xgmii
+	=> ping $serverip
+
+2. Command sequence for Linux boot:
+   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+   b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+   c) No DPMAC net-devices are available for use in u-boot
+   d) boot Linux
+
+   Example-
+	Assumption: MC firmware, DPL and DPC dtb is already programmed
+	on NOR flash.
+
+	=> fsl_mc start mc 580300000 580800000
+	=> setenv ethact DPMAC1@xgmii
+	=> tftp a0000000 kernel.itb
+	=> fsl_mc apply dpl 580700000
+	=> bootm a0000000
+
+3. Command sequence for AIOP boot:
+   a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+   b) fsl_mc start aiop <FW_addr> - Start AIOP
+   c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+   d) No DPMAC net-devices are availabe for use in u-boot
+  Please note actual AIOP start will happen during DPL parsing of
+  Management complex
+
+  Example-
+	Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
+	programmed on NOR flash.
+
+	=> fsl_mc start mc 580300000 580800000
+	=> fsl_mc start aiop 0x580900000
+	=> setenv ethact DPMAC1@xgmii
+	=> fsl_mc apply dpl 580700000
+
+Errata A009635
+---------------
+If the core runs at higher than x3 speed of the platform, there is
+possiblity about sev instruction to getting missed by other cores.
+This is because of SoC Run Control block may not able to sample
+the EVENTI(Sev) signals.
+
+Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
+wake up A57 cores
+
+Errata workaround uses Env variable "a009635_interval_val". It uses decimal
+value.
+- Default value of env variable is platform clock (MHz)
+
+- User can modify default value by updating the env variable
+  setenv a009635_interval_val 600; saveenv;
+  It configure platform clock as 600 MHz
+
+- Env variable as 0 signifies no workaround
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
new file mode 100644
index 0000000..a4130ce
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -0,0 +1,86 @@
+SoC overview
+
+	1. LS1043A
+	2. LS2080A
+
+LS1043A
+---------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+--------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index a6fd7a3..913537d 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -8,41 +8,8 @@ debugging environment.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043AQDS board Overview
  -----------------------
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 0556e73..709ddbb 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043ARDB board Overview
  -----------------------
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 6ddad92..5c98866 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 6708ca9..b1613ba 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
-- 
cgit v0.10.2


From b7f2bbfff6dcc2d5989bb1d20500c431f7927daf Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:31 +0530
Subject: armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.

This patch add support of LS1012A SoC along with
 - Update platform & DDR clock read logic as per SVR
 - Define MMDC controller register set.
 - Update LUT base address for PCIe
 - Avoid L3 platform cache compilation
 - Update USB address, errata
 - SerDes table
 - Added CSU IDs for SDHC2, SAI-1 to SAI-4

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5f86ef9..eb2cbc3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,3 +28,7 @@ endif
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index a4130ce..8eee016 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -2,6 +2,7 @@ SoC overview
 
 	1. LS1043A
 	2. LS2080A
+	3. LS1012A
 
 LS1043A
 ---------
@@ -84,3 +85,45 @@ The LS2080A SoC includes the following function and features:
  - QorIQ platform's trust architecture 3.0
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
+
+LS1012A
+--------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)
+    - Two FlexTimers
+    - Five synchronous audio interfaces (SAI)
+    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+    - Single-source clocking solution enabling generation of core, platform,
+    DDR, SerDes, and USB clocks from a single external crystal and internal
+    crystaloscillator
+    - Thermal monitor unit (TMU) with +/- 3C accuracy
+    - Two WatchDog timers
+    - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 4fc3186..3a77b21 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -59,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
 
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -83,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+	sys_info->freq_ddrbus *= 2;
+#endif
+
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index d743ffe..5af6b73 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -183,6 +183,7 @@ ENTRY(lowlevel_init)
 	ret
 ENDPROC(lowlevel_init)
 
+#ifdef CONFIG_FSL_LSCH3
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
 	 * clobber x1, x2, x3, x4, x6, x7
@@ -260,6 +261,7 @@ ENTRY(__asm_flush_l3_cache)
 	mov	lr, x29
 	ret
 ENDPROC(__asm_flush_l3_cache)
+#endif
 
 #ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
new file mode 100644
index 0000000..ff0903c
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	{0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
+	{0x0008, {NONE, NONE, NONE, SATA1} },
+	{0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
+	{0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
+	{0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
+	{0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
+	{0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0ae61d6..dd633f3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,8 +12,10 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
+#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index fbdaa52..44fe0c0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -14,8 +14,11 @@
 #else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
 #endif
+
+#ifndef CONFIG_LS1012A
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+#endif
 
 /*
  * Reserve secure memory
@@ -200,6 +203,32 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS                         1
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
+#undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
+
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES		4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..1cebe2f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index c4fb7c9..487cba8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -134,6 +134,7 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	TX_CLK,
 	SERDES_PRCTL_COUNT
 };
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..e98e055 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -60,7 +60,11 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE				0xC0000
+#else
 #define PCIE_LUT_BASE				0x10000
+#endif
 #define PCIE_LUT_LCTRL0				0x7F8
 #define PCIE_LUT_DBG				0x7FC
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index a3ccdb0..db76066 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -69,7 +69,12 @@ enum csu_cslx_ind {
 	CSU_CSLX_IIC4 = 77,
 	CSU_CSLX_WDT4,
 	CSU_CSLX_WDT3,
+	CSU_CSLX_ESDHC2 = 80,
 	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
 	CSU_CSLX_FTM2 = 86,
 	CSU_CSLX_FTM1,
 	CSU_CSLX_FTM4,
@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
 	 {CSU_CSLX_IIC4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC2, CSU_ALL_RW},
 	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_SAI2, CSU_ALL_RW},
+	 {CSU_CSLX_SAI1, CSU_ALL_RW},
+	 {CSU_CSLX_SAI4, CSU_ALL_RW},
+	 {CSU_CSLX_SAI3, CSU_ALL_RW},
 	 {CSU_CSLX_FTM2, CSU_ALL_RW},
 	 {CSU_CSLX_FTM1, CSU_ALL_RW},
 	 {CSU_CSLX_FTM4, CSU_ALL_RW},
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 831d817..02ecc62 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -41,6 +41,7 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
+#define SVR_LS1012		0x870400
 #define SVR_LS1043		0x879200
 #define SVR_LS1023		0x879208
 #define SVR_LS2045		0x870120
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
new file mode 100644
index 0000000..281a819
--- /dev/null
+++ b/include/fsl_mmdc.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING		0x12554000
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0	0xbabf7954
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1	0xff328f64
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2	0x01ff00db
+
+#define CONFIG_SYS_MMDC_CORE_MISC		0x00000680
+#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT	0x00000800
+#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY	0x00002000
+#define CONFIG_SYS_MMDC_PHY_ODT_CTRL		0x0000022a
+
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY	0x00bf1023
+
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION	0x0000007f
+
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL		0xa1390003
+
+#define	FORCE_ZQ_AUTO_CALIBRATION		(0x1 << 16)
+
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
+#define WR_LVL_HW_EN				0x00000001
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPR_COMPARE_EN				0x00000001
+
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG	0x40404040
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN	0x10000000
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define AUTO_RD_CALIBRATION_EN			0x00000010
+
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL	0x00030035
+
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT	0x00001067
+
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL	0x103e8000
+
+#define START_REFRESH				0x00000001
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
+
+#define  CMD_ADDR_LSB_MR_ADDR(x)    (x << 16)
+
+#define DISABLE_CFG_REQ		0x0
+#define CONFIGURATION_REQ	(0x1  << 15)
+#define WL_EN			(0x1  << 9)
+
+#define	CMD_NORMAL		(0x0 << 4)
+#define	CMD_PRECHARGE		(0x1 << 4)
+#define	CMD_AUTO_REFRESH	(0x2 << 4)
+#define	CMD_LOAD_MODE_REG	(0x3 << 4)
+#define	CMD_ZQ_CALIBRATION	(0x4 << 4)
+#define	CMD_PRECHARGE_BANK_OPEN	(0x5 << 4)
+#define	CMD_MRR			(0x6 << 4)
+
+#define CMD_BANK_ADDR_0		0x0
+#define CMD_BANK_ADDR_1		0x1
+#define CMD_BANK_ADDR_2		0x2
+#define CMD_BANK_ADDR_3		0x3
+#define CMD_BANK_ADDR_4		0x4
+#define CMD_BANK_ADDR_5		0x5
+#define CMD_BANK_ADDR_6		0x6
+#define CMD_BANK_ADDR_7		0x7
+
+/* MMDC Registers */
+struct mmdc_p_regs {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdscr;
+	u32 mdref;
+	u32 res1[2];
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdmrr;
+	u32 mdcfg3lp;
+	u32 mdmr4;
+	u32 mdasp;
+	u32 res2[239];
+	u32 maarcr;
+	u32 mapsr;
+	u32 maexidr0;
+	u32 maexidr1;
+	u32 madpcr0;
+	u32 madpcr1;
+	u32 madpsr0;
+	u32 madpsr1;
+	u32 madpsr2;
+	u32 madpsr3;
+	u32 madpsr4;
+	u32 madpsr5;
+	u32 masbs0;
+	u32 masbs1;
+	u32 res3[2];
+	u32 magenp;
+	u32 res4[239];
+	u32 mpzqhwctrl;
+	u32 mpzqswctrl;
+	u32 mpwlgcr;
+	u32 mpwldectrl0;
+	u32 mpwldectrl1;
+	u32 mpwldlst;
+	u32 mpodtctrl;
+	u32 mprddqby0dl;
+	u32 mprddqby1dl;
+	u32 mprddqby2dl;
+	u32 mprddqby3dl;
+	u32 res5[4];
+	u32 mpdgctrl0;
+	u32 mpdgctrl1;
+	u32 mpdgdlst0;
+	u32 mprddlctl;
+	u32 mprddlst;
+	u32 mpwrdlctl;
+	u32 mpwrdlst;
+	u32 mpsdctrl;
+	u32 mpzqlp2ctl;
+	u32 mprddlhwctl;
+	u32 mpwrdlhwctl;
+	u32 mprddlhwst0;
+	u32 mprddlhwst1;
+	u32 mpwrdlhwst0;
+	u32 mpwrdlhwst1;
+	u32 mpwlhwerr;
+	u32 mpdghwst0;
+	u32 mpdghwst1;
+	u32 mpdghwst2;
+	u32 mpdghwst3;
+	u32 mppdcmpr1;
+	u32 mppdcmpr2;
+	u32 mpswdar0;
+	u32 mpswdrdr0;
+	u32 mpswdrdr1;
+	u32 mpswdrdr2;
+	u32 mpswdrdr3;
+	u32 mpswdrdr4;
+	u32 mpswdrdr5;
+	u32 mpswdrdr6;
+	u32 mpswdrdr7;
+	u32 mpmur0;
+	u32 mpwrcadl;
+	u32 mpdccr;
+};
+
+#endif /* FSL_MMDC_H */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index c5e42e6..253eddf 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -59,10 +59,14 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
-- 
cgit v0.10.2


From 3faaa24b1138e720e065ae7ee6c63f751e6867be Mon Sep 17 00:00:00 2001
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Fri, 3 Jun 2016 18:41:32 +0530
Subject: board: freescale: common: Conditionally compile IFC QXIS func

Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..2e35d41 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
 	void *p = (void *)QIXIS_BASE;
@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
 
 	out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {
-- 
cgit v0.10.2


From 16dacb26a5e5ec58e00ec9d1a83d0ccceb8b0de5 Mon Sep 17 00:00:00 2001
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Fri, 3 Jun 2016 18:41:33 +0530
Subject: board: freescale: common: Add flag for LBMAP brdcfg reg offset

Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2e35d41..0db0ed6 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,6 +14,13 @@
 #include <i2c.h>
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
 {
 	u8 reg;
 
-	reg = QIXIS_READ(brdcfg[0]);
+	reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
 	reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-	QIXIS_WRITE(brdcfg[0], reg);
+	QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
 static void __maybe_unused set_rcw_src(int rcw_src)
-- 
cgit v0.10.2


From 9d044fcb8c4558d7ec28089375d2de565bfd2619 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:34 +0530
Subject: armv8: ls1012a: Add support of ls1012aqds board

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a77b6a..30fc32a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -696,6 +696,15 @@ config TARGET_HIKEY
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+	bool "Support ls1012aqds"
+	select ARM64
+	help
+	  Support for Freescale LS1012AQDS platform.
+	  The LS1012A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -852,6 +861,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 92c7545..47ec7a2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -120,7 +120,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
-	fsl-ls1043a-rdb.dtb
+	fsl-ls1043a-rdb.dtb \
+	fsl-ls1012a-qds.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000..76db36c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dts
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644
index 0000000..dde7134
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A QDS Board";
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi0;
+	};
+};
+
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <1000000>; /* input clock */
+	};
+
+	dflash1: sst25wf040b {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3500000>;
+		reg = <1>;
+	};
+
+	dflash2: en25s64 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3500000>;
+		reg = <2>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pca9547@77 {
+		compatible = "philips,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				/* IRQ10_B */
+				interrupts = <0 150 0x4>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			ina220@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+
+			ina220@41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			eeprom@56 {
+				compatible = "at24,24c512";
+				reg = <0x56>;
+			};
+
+			eeprom@57 {
+				compatible = "at24,24c512";
+				reg = <0x57>;
+			};
+
+			adt7461a@4c {
+				compatible = "adt7461a";
+				reg = <0x4c>;
+			};
+		};
+	};
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
new file mode 100644
index 0000000..546a87a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+	compatible = "fsl,ls1012a";
+	interrupt-parent = <&gic>;
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			clocks = <&clockgen 1 0>;
+		};
+
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	gic: interrupt-controller@1400000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+		      <0x0 0x1402000 0 0x2000>, /* GICC */
+		      <0x0 0x1404000 0 0x2000>, /* GICH */
+		      <0x0 0x1406000 0 0x2000>; /* GICV */
+		interrupts = <1 9 0xf08>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clockgen: clocking@1ee1000 {
+			compatible = "fsl,ls1012a-clockgen";
+			reg = <0x0 0x1ee1000 0x0 0x1000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
+		};
+
+		dspi0: dspi@2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <0 64 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
+
+		i2c0: i2c@2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2180000 0x0 0x10000>;
+			interrupts = <0 56 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2190000 0x0 0x10000>;
+			interrupts = <0 57 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		duart0: serial@21c0500 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0500 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		duart1: serial@21c0600 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0600 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		qspi: quadspi@1550000 {
+			compatible = "fsl,vf610-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			num-cs = <2>;
+			big-endian;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644
index 0000000..1257ec8
--- /dev/null
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+	default "ls1012aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644
index 0000000..27c4aff
--- /dev/null
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012aqds/
+F:	include/configs/ls1012aqds.h
+F:	configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644
index 0000000..0b813f9
--- /dev/null
+++ b/board/freescale/ls1012aqds/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644
index 0000000..dee4b30
--- /dev/null
+++ b/board/freescale/ls1012aqds/README
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+	• Provides MIC bias
+	• Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644
index 0000000..71eea82
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+	if (sw & QIXIS_LBMAP_ALTBANK)
+		printf("flash: 2\n");
+	else
+		printf("flash: 1\n");
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 mux_sdhc_cd = 0x80;
+
+	i2c_set_bus_num(0);
+
+	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+				   CONFIG_SYS_CCI400_ADDR;
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	out_le32(&cci->ctrl_ord,
+		 CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644
index 0000000..584f604
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
new file mode 100644
index 0000000..2bc178c
--- /dev/null
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644
index 0000000..ccd94ec
--- /dev/null
+++ b/include/configs/ls1012a_common.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define	CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE		0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ/4	/* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		1000000
+#define CONFIG_ENV_SPI_MODE		0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE		0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"initrd_high=0xffffffff\0"		\
+	"verify=no\0"				\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0xa00000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
+				"earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
+					"$kernel_start $kernel_size && "\
+					"bootm $kernel_load"
+#define CONFIG_BOOTDELAY		10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644
index 0000000..2d84095
--- /dev/null
+++ b/include/configs/ls1012aqds.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_BRDCFG_REG		0x04
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0xf7
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x08
+#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+#define I2C_MUX_CH5			0xD
+#define I2C_MUX_CH7			0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM    0
+#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI          DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0   1
+
+#define CONFIG_SYS_DSPI_CTAR1	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED      10000000
+#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS        1
+#define CONFIG_SF_DEFAULT_CS         0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */
-- 
cgit v0.10.2


From 3b6e3898c2c68fa8340794c8abf5d47859069f98 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:35 +0530
Subject: armv8: ls1012a: Add support of ls1012ardb board

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 30fc32a..9be8c2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -705,6 +705,15 @@ config TARGET_LS1012AQDS
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1012ARDB
+	bool "Support ls1012ardb"
+	select ARM64
+	help
+	  Support for Freescale LS1012ARDB platform.
+	  The LS1012A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -862,6 +871,7 @@ source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47ec7a2..f021699 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -121,7 +121,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
-	fsl-ls1012a-qds.dtb
+	fsl-ls1012a-qds.dtb \
+	fsl-ls1012a-rdb.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000..f683812
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
new file mode 100644
index 0000000..bf407ae
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A RDB Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
new file mode 100644
index 0000000..3f67c28
--- /dev/null
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+	default "ls1012ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012ardb"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644
index 0000000..79a2a7d
--- /dev/null
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012ardb/
+F:	include/configs/ls1012ardb.h
+F:	configs/ls1012ardb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
new file mode 100644
index 0000000..05fa9d9
--- /dev/null
+++ b/board/freescale/ls1012ardb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
new file mode 100644
index 0000000..453b432
--- /dev/null
+++ b/board/freescale/ls1012ardb/README
@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory (2 virtual banks)
+    - the QSPI emulator.s
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: Three dual 1:4 mux/demux devices,
+    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+    SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644
index 0000000..f69768d
--- /dev/null
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	u8 in1;
+
+	puts("Board: LS1012ARDB ");
+
+	/* Initialize i2c early for Serial flash bank information */
+	i2c_set_bus_num(0);
+
+	if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+
+	puts("Version");
+	if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+		puts(": RevA");
+	else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+		puts(": RevB");
+	else
+		puts(": unknown");
+
+	printf(", boot from QSPI");
+	if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+		puts(": emu\n");
+	else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+		puts(": bank1\n");
+	else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+		puts(": bank2\n");
+	else
+		puts("unknown\n");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
new file mode 100644
index 0000000..456eebd
--- /dev/null
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
new file mode 100644
index 0000000..f63c66a
--- /dev/null
+++ b/include/configs/ls1012ardb.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR	0x24
+#define __SW_BOOT_MASK		0xFC
+#define __SW_BOOT_EMU		0x10
+#define __SW_BOOT_BANK1		0x00
+#define __SW_BOOT_BANK2		0x01
+#define __SW_REV_MASK		0x07
+#define __SW_REV_A		0xF8
+#define __SW_REV_B		0xF0
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
-- 
cgit v0.10.2


From ff78aa2ba19cda755b01818fb3caf2aca9236865 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 3 Jun 2016 18:41:36 +0530
Subject: armv8: ls1012a: Add support of ls1012afrdm board

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9be8c2b..71169b2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -714,6 +714,15 @@ config TARGET_LS1012ARDB
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1012AFRDM
+	bool "Support ls1012afrdm"
+	select ARM64
+	help
+	  Support for Freescale LS1012AFRDM platform.
+	  The LS1012A Freedom  board (FRDM) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f021699..e8ad6c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
 	fsl-ls1012a-qds.dtb \
-	fsl-ls1012a-rdb.dtb
+	fsl-ls1012a-rdb.dtb \
+	fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..983e599
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &duart0;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644
index 0000000..25dcdd2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A FREEDOM Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000..a34521c
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000..842f86f
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000..dbfa2ce
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000..181c461
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+	operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000..a94a458
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	puts("Board: LS1012AFRDM ");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
new file mode 100644
index 0000000..349758b
--- /dev/null
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644
index 0000000..3e7c430
--- /dev/null
+++ b/include/configs/ls1012afrdm.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
-- 
cgit v0.10.2


From 4835c737ff8ca65aa2bf206dcddd6407f4bc40cf Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 12 May 2016 08:57:13 +0200
Subject: usb: dwc3: Correct datatype of base to unsigned long

Correct type of varibale base to unsigned long as
keeping it as int causes usb failures if MSB of
the base address is set.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 09ff8a7..7af2ad1 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -13,7 +13,7 @@
 #include <linux/usb/otg.h>
 
 struct dwc3_device {
-	int base;
+	unsigned long base;
 	enum usb_dr_mode dr_mode;
 	u32 maximum_speed;
 	unsigned tx_fifo_resize:1;
-- 
cgit v0.10.2


From 0ff27eb25f027602261fd009b1cf588f7918f02c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 4 Jun 2016 07:35:02 +0900
Subject: configs: blackfin: move CONFIG_USB to defconfig

These Blackfin boards are the last ones that define CONFIG_USB in
their headers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index 85c2a6b..ea4f8e4 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -17,3 +17,4 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index ff797f8..faac28d 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -17,4 +17,5 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index eff2a12..d69b146 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -17,3 +17,4 @@ CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_NET_TFTP_VARS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index 6d398ac..e4fa136 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -16,5 +16,6 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 74c3464..cf8ef8a 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -125,7 +125,6 @@
  * USB Settings
  */
 #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB
 #define CONFIG_USB_MUSB_HCD
 #define CONFIG_USB_BLACKFIN
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index e268473..c958a94 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -128,7 +128,6 @@
  * USB Settings
  */
 #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB
 #define CONFIG_USB_MUSB_HCD
 #define CONFIG_USB_BLACKFIN
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 6830e4d..be28ea3 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -151,7 +151,6 @@
  * USB Settings
  */
 #if !defined(__ADSPBF544__)
-#define CONFIG_USB
 #define CONFIG_USB_MUSB_HCD
 #define CONFIG_USB_BLACKFIN
 #define CONFIG_USB_STORAGE
-- 
cgit v0.10.2


From 0a8cc1a3a4206d556da784a0e98598190dfe5408 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 4 Jun 2016 07:35:03 +0900
Subject: usb: move CONFIG_USB_XHCI to Kconfig with renaming

Move CONFIG_USB_XHCI to defconfig files for all boards, renaming it
into CONFIG_USB_XHCI_HCD.

As commented in the help of "config USB_XHCI" entry, this has been
a TODO for a long time; now CONFIG_USB_XHCI_HCD and CONFIG_USB_XHCI
have been unified in favor of the former.

Note:
Some boards define CONFIG_USB_XHCI in their headers without
CONFIG_USB, which does not meet the "depends on" in Kconfig.
I added CONFIG_USB=y for those boards when converting.
Otherwise, they would fail to build.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/common/usb.c b/common/usb.c
index 8d9efe5..b3ba487 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1182,7 +1182,7 @@ int usb_new_device(struct usb_device *dev)
 	 * with the device. So a get_descriptor will fail before any
 	 * of that is done for XHCI unlike EHCI.
 	 */
-#ifdef CONFIG_USB_XHCI
+#ifdef CONFIG_USB_XHCI_HCD
 	do_read = false;
 #endif
 	err = usb_setup_device(dev, do_read, dev->parent);
diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
index c4accb6..a7d4041 100644
--- a/configs/am437x_hs_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -42,6 +42,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 3955612..e8a3d75 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -42,6 +42,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 33fb552..2a85a34 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 5f90e2b..b4f1228 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -29,6 +29,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 72f4ad8..e88a9e3 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -40,6 +40,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index cccdc10..815811f 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -33,3 +33,5 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 47d103b..373aa9e 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -22,4 +22,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 60525cd..aa3d627 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -34,3 +34,5 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index c926a3a..a8ffea7 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -37,4 +37,6 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_hs_evm_defconfig b/configs/dra72_hs_evm_defconfig
index 01f985e..767e067 100644
--- a/configs/dra72_hs_evm_defconfig
+++ b/configs/dra72_hs_evm_defconfig
@@ -44,6 +44,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/dra74_hs_evm_defconfig b/configs/dra74_hs_evm_defconfig
index 1b30ad4..e05efe0 100644
--- a/configs/dra74_hs_evm_defconfig
+++ b/configs/dra74_hs_evm_defconfig
@@ -43,6 +43,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 288f8b3..9ee579c 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -42,6 +42,7 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 044a9bf..b1d4018 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -32,3 +32,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index d0b45ce..2c7167e 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -32,3 +32,5 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 3975e80..410de64 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -32,3 +32,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 844dd57..91d7a04 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -32,3 +32,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 04ded54..92f7796 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -27,3 +27,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 7915200..338dbf4 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -27,3 +27,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 9002a01..b3edd0a 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 30c2ca5..499fece 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -22,6 +22,8 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index a30153a..cf4f79d 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -26,3 +26,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 217cf88..5ad9082 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -27,3 +27,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 15b0b0d..33484ed 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -33,3 +33,5 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index ef42d3d..0992718 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -25,3 +25,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 69f5b61..abb3287 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -32,3 +32,5 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 1c0ae06..f3a9e35 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -22,6 +22,8 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 10cc576..be68631 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -26,3 +26,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index f56f931..ec165b1 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -27,3 +27,5 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index bc419fb..c0a7967 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -34,3 +34,5 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index e27758b..1900c1a 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 01856d4..272dabd 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -34,3 +34,5 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 346faf4..fa4270a 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -25,3 +25,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 2c6ac35..2a845b6 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index cc8d8fa..20dc98b 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 7d0646c..829ed32 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -24,3 +24,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 8ea1416..b6b98e3 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 7e5949d..40ae837 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -26,3 +26,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 609fd63..8228d22 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -27,3 +27,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index cacee2f..9e4ab65 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -21,4 +21,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_RSA=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 49d0740..37a67b9 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -21,3 +21,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index d240cde..e847312 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -22,3 +22,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index f853685..e8a516b 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -22,3 +22,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 04a84ab..14619fb 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -29,5 +29,7 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 3b6504b..2ca0117 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -29,4 +29,6 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 1302313..2af3687 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -22,5 +22,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index f974d88..76a9c3d 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -29,5 +29,7 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 0168dbb..82d14be 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -29,4 +29,6 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 718a651..17f0f6d 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -22,5 +22,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 8995cc2..e78f973 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -36,6 +36,7 @@ CONFIG_PMIC_S2MPS11=y
 CONFIG_DM_REGULATOR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_PHY_SAMSUNG=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index c8c74c0..9a815d0 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -55,6 +55,7 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index c5fbf8c..5bea937 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -55,6 +55,7 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 40de7c1..ad599fc 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -36,4 +36,5 @@ CONFIG_DM_REGULATOR=y
 CONFIG_EXYNOS_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index f342ed2..2a5b2d9 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -56,6 +56,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=25000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 5d641a5..457393a 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -49,6 +49,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 77e6180..fe415cd 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -41,6 +41,7 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index b370bc1..6b76dbc 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -47,6 +47,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 9764452..1a3fb21 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -47,6 +47,7 @@ CONFIG_DEBUG_UART_BASE=0xff000000
 CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d2363c8..8a6f732 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -9,12 +9,6 @@ config USB_XHCI_HCD
 	  The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
 	  "SuperSpeed" host controller hardware.
 
-config USB_XHCI
-	bool
-	default USB_XHCI_HCD
-	---help---
-	  TODO: rename after most boards switch to Kconfig
-
 if USB_XHCI_HCD
 
 config USB_XHCI_UNIPHIER
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 507519e..620d114 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,7 +54,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
-obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index a54303d..170d069 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -99,7 +99,6 @@
 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d53b0fd..6a3d8e5 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -65,7 +65,6 @@
 /* USB xHCI HOST */
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index c2dbd31..51eac93 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -61,7 +61,6 @@
 
 /* USB support */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8a0cd66..0571dc0 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -211,7 +211,6 @@
 
 /* USB xHCI HOST */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 64c546c..23373cd 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -71,12 +71,11 @@
  * - USB init fails, controller does not respond in time */
 #if 0
 #undef CONFIG_DM_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_PCI
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
 #endif
 
-#if !defined(CONFIG_USB_XHCI)
+#if !defined(CONFIG_USB_XHCI_HCD)
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MARVELL
 #define CONFIG_EHCI_IS_TDI
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index cd86e06..16153eb 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -48,7 +48,6 @@
  */
 #define CONFIG_CORE_COUNT		0x8
 
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
 
 #endif	/* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index f605ca6..ac32240 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -451,7 +451,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 32d2acc..c38d680 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -58,7 +58,6 @@
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
 #endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index af1f73d..103bb2e 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -388,7 +388,6 @@ unsigned long get_board_ddr_clk(void);
 /* USB */
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index aca8d95..0a71637 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -278,7 +278,6 @@
 /* USB */
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 4b27114..743473f 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -383,7 +383,6 @@ unsigned long get_board_ddr_clk(void);
  * USB
  */
 #define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 3baca64..1fe4138 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -316,7 +316,6 @@ unsigned long get_board_sys_clk(void);
  * USB
  */
 #define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 9cf886c..c15acec 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -31,7 +31,6 @@
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
 /* USB */
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
 
 /* DRAM Memory Banks */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 2c9028c..2292eb2 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -191,7 +191,6 @@
 					"-(ubifs)"
 
 /* USB Configuration */
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_KEYSTONE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ffb6b34..b0e0c22 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -118,7 +118,6 @@
 
 #if defined(CONFIG_ZYNQMP_USB)
 #define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_STORAGE
-- 
cgit v0.10.2


From 10db7500369ea000af4c4c5b039b7946c2865ae9 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 4 Jun 2016 07:35:04 +0900
Subject: usb: move CONFIG_USB_XHCI_DWC3 to Kconfig

Create an entry for "config USB_XHCI_DWC3" in Kconfig and
switch over to it for all boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
index a7d4041..3cd39eb 100644
--- a/configs/am437x_hs_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -43,6 +43,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index e8a3d75..cb3de11 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -43,6 +43,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 2a85a34..3b958d7 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -30,6 +30,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index b4f1228..5264332 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -30,6 +30,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index e88a9e3..34c875e 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -41,6 +41,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 815811f..6743b84 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -35,3 +35,4 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 373aa9e..1cf82d2 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -24,4 +24,5 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index aa3d627..c109939 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -36,3 +36,4 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index a8ffea7..b80ca0d 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -39,4 +39,5 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra72_hs_evm_defconfig b/configs/dra72_hs_evm_defconfig
index 767e067..1a4082c 100644
--- a/configs/dra72_hs_evm_defconfig
+++ b/configs/dra72_hs_evm_defconfig
@@ -45,6 +45,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/dra74_hs_evm_defconfig b/configs/dra74_hs_evm_defconfig
index e05efe0..edcdca0 100644
--- a/configs/dra74_hs_evm_defconfig
+++ b/configs/dra74_hs_evm_defconfig
@@ -44,6 +44,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 9ee579c..756af63 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -43,6 +43,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index b1d4018..9fcdfe9 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -34,3 +34,4 @@ CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 2c7167e..8efa58c 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -34,3 +34,4 @@ CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 410de64..278eaf3 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -34,3 +34,4 @@ CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 91d7a04..8417e0a 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -34,3 +34,4 @@ CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 92f7796..efaa7a9 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -29,3 +29,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 338dbf4..9fa5cb9 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -29,3 +29,4 @@ CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index b3edd0a..24b7a15 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -23,6 +23,7 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 499fece..5d2b57d 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -24,6 +24,7 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index cf4f79d..426a4be 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -28,3 +28,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 5ad9082..4f5c1e8 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -29,3 +29,4 @@ CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 33484ed..6a791c0 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -35,3 +35,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 0992718..33e5c0c 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -27,3 +27,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index abb3287..45f0f73 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -34,3 +34,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index f3a9e35..16243ee 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -24,6 +24,7 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index be68631..3158340 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -28,3 +28,4 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index ec165b1..bbeb4bf 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -29,3 +29,4 @@ CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index c0a7967..6910c4e 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -36,3 +36,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 1900c1a..f59ad74 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -22,6 +22,7 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 272dabd..90f810a 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -36,3 +36,4 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index fa4270a..1fbfd38 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -27,3 +27,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 2a845b6..6b628d3 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 20dc98b..90f870a 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 829ed32..813c269 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -26,3 +26,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index b6b98e3..e665ba4 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 40ae837..03a263a 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -28,3 +28,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 8228d22..0062f5c 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -29,3 +29,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 9e4ab65..bace827 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -23,4 +23,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 37a67b9..48a89ab 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -23,3 +23,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index e847312..627a90d 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index e8a516b..c676a91 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 14619fb..49a4a26 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -31,5 +31,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 2ca0117..c305345 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -31,4 +31,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 2af3687..8a6dd14 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -24,5 +24,6 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 76a9c3d..a2d88cc 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -31,5 +31,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 82d14be..dc2b872 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -31,4 +31,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 17f0f6d..dbba8ab 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -24,5 +24,6 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index e78f973..49cfa8c 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -37,6 +37,7 @@ CONFIG_DM_REGULATOR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_PHY_SAMSUNG=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 9a815d0..3c403ba 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -56,6 +56,7 @@ CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 5bea937..bfa3614 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -56,6 +56,7 @@ CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index ad599fc..3bda611 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -37,4 +37,5 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 2a5b2d9..ad94d56 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -57,6 +57,7 @@ CONFIG_DEBUG_UART_CLOCK=25000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 457393a..ad1566d 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -50,6 +50,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index fe415cd..3aa80cb 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -42,6 +42,7 @@ CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 6b76dbc..a216f11 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -48,6 +48,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 1a3fb21..514176d 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -48,6 +48,7 @@ CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 8a6f732..89580cc 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -18,6 +18,12 @@ config USB_XHCI_UNIPHIER
 	---help---
 	  Enables support for the on-chip xHCI controller on UniPhier SoCs.
 
+config USB_XHCI_DWC3
+	bool "DesignWare USB3 DRD Core Support"
+	help
+	  Say Y or if your system has a Dual Role SuperSpeed
+	  USB controller based on the DesignWare USB3 IP Core.
+
 endif
 
 config USB_OHCI_GENERIC
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 170d069..361704b 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -99,7 +99,6 @@
 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 6a3d8e5..2db199d 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -64,7 +64,6 @@
 
 /* USB xHCI HOST */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 51eac93..5076540 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -62,7 +62,6 @@
 /* USB support */
 #define CONFIG_USB_HOST
 #define CONFIG_USB_XHCI_OMAP
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
 #define CONFIG_OMAP_USB_PHY
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0571dc0..0d51aeb 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -211,7 +211,6 @@
 
 /* USB xHCI HOST */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index b2ff4dd..e614a7f 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -157,7 +157,6 @@
 
 /* USB */
 #define CONFIG_USB_STORAGE
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index ac32240..1edf798 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -450,7 +450,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index c38d680..30f5655 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -57,7 +57,6 @@
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
 #endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 103bb2e..a19eaee 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -389,7 +389,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 0a71637..94ddfb1 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -279,7 +279,6 @@
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 743473f..b44066c 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -384,7 +384,6 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 1fe4138..86a49a5 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -317,7 +317,6 @@ unsigned long get_board_sys_clk(void);
  */
 #define CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 2292eb2..707106f 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -191,7 +191,6 @@
 					"-(ubifs)"
 
 /* USB Configuration */
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_KEYSTONE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index b0e0c22..8a1142b 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -117,7 +117,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x8000000
 
 #if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_STORAGE
-- 
cgit v0.10.2


From a39d14406a1e8dfbbbd3b549d411edbba40fd454 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Wed, 25 May 2016 15:20:38 +0530
Subject: mtd: nand: arasan_nfc: Correct nand ecc initialization

Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 2d73a05..caa7982 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -1058,20 +1058,20 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	if (found < 0)
 		return 1;
 
-	regval = ecc_matrix[i].eccaddr |
-		 (ecc_matrix[i].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
-		 (ecc_matrix[i].bch << ARASAN_NAND_ECC_BCH_SHIFT);
+	regval = ecc_matrix[found].eccaddr |
+		 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
+		 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
 	writel(regval, &arasan_nand_base->ecc_reg);
 
-	if (ecc_matrix[i].bch) {
+	if (ecc_matrix[found].bch) {
 		regval = readl(&arasan_nand_base->memadr_reg2);
 		regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
-		regval |= (ecc_matrix[i].bchval <<
+		regval |= (ecc_matrix[found].bchval <<
 			   ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
 		writel(regval, &arasan_nand_base->memadr_reg2);
 	}
 
-	nand_oob.eccbytes = ecc_matrix[i].eccsize;
+	nand_oob.eccbytes = ecc_matrix[found].eccsize;
 	eccpos_start = mtd->oobsize - nand_oob.eccbytes;
 
 	for (i = 0; i < nand_oob.eccbytes; i++)
@@ -1080,9 +1080,9 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	nand_oob.oobfree[0].offset = 2;
 	nand_oob.oobfree[0].length = eccpos_start - 2;
 
-	nand_chip->ecc.size = ecc_matrix[i].ecc_codeword_size;
-	nand_chip->ecc.strength = ecc_matrix[i].eccbits;
-	nand_chip->ecc.bytes = ecc_matrix[i].eccsize;
+	nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
+	nand_chip->ecc.strength = ecc_matrix[found].eccbits;
+	nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
 	nand_chip->ecc.layout = &nand_oob;
 
 	return 0;
-- 
cgit v0.10.2


From 5d74e3a6f1ad8b7e3b7db070908ce7b080ea78ac Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 30 May 2016 13:57:52 -0500
Subject: mtd: nand: Remove jz4740 driver

This driver is not used by anyone, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Scott Wood <oss@buserror.net>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6fb3718..aea6a93 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -50,7 +50,6 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
-obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
deleted file mode 100644
index abcedc2..0000000
--- a/drivers/mtd/nand/jz4740_nand.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Platform independend driver for JZ4740.
- *
- * Copyright (c) 2007 Ingenic Semiconductor Inc.
- * Author: <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
-#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
-#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
-
-#define JZ_NAND_ECC_CTRL_ENCODING	BIT(3)
-#define JZ_NAND_ECC_CTRL_RS		BIT(2)
-#define JZ_NAND_ECC_CTRL_RESET		BIT(1)
-#define JZ_NAND_ECC_CTRL_ENABLE		BIT(0)
-
-#define EMC_SMCR1_OPT_NAND	0x094c4400
-/* Optimize the timing of nand */
-
-static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
-
-static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
-	.eccbytes = 72,
-	.eccpos = {
-		12, 13, 14, 15, 16, 17, 18, 19,
-		20, 21, 22, 23, 24, 25, 26, 27,
-		28, 29, 30, 31, 32, 33, 34, 35,
-		36, 37, 38, 39, 40, 41, 42, 43,
-		44, 45, 46, 47, 48, 49, 50, 51,
-		52, 53, 54, 55, 56, 57, 58, 59,
-		60, 61, 62, 63, 64, 65, 66, 67,
-		68, 69, 70, 71, 72, 73, 74, 75,
-		76, 77, 78, 79, 80, 81, 82, 83 },
-	.oobfree = {
-		{.offset = 2,
-		 .length = 10 },
-		{.offset = 84,
-		 .length = 44 } }
-};
-
-static int is_reading;
-
-static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-	uint32_t reg;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if (ctrl & NAND_ALE)
-			this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
-		else if (ctrl & NAND_CLE)
-			this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
-		else
-			this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
-
-		reg = readl(&emc->nfcsr);
-		if (ctrl & NAND_NCE)
-			reg |= EMC_NFCSR_NFCE1;
-		else
-			reg &= ~EMC_NFCSR_NFCE1;
-		writel(reg, &emc->nfcsr);
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static int jz_nand_device_ready(struct mtd_info *mtd)
-{
-	return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	/*
-	 * Don't use "chip" to address the NAND device,
-	 * generate the cs from the address where it is encoded.
-	 */
-}
-
-static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
-				u_char *ecc_code)
-{
-	uint32_t status;
-	int i;
-
-	if (is_reading)
-		return 0;
-
-	do {
-		status = readl(&emc->nfints);
-	} while (!(status & EMC_NFINTS_ENCF));
-
-	/* disable ecc */
-	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
-
-	for (i = 0; i < 9; i++)
-		ecc_code[i] = readb(&emc->nfpar[i]);
-
-	return 0;
-}
-
-static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
-{
-	uint32_t reg;
-
-	writel(0, &emc->nfints);
-	reg = readl(&emc->nfecr);
-	reg |= JZ_NAND_ECC_CTRL_RESET;
-	reg |= JZ_NAND_ECC_CTRL_ENABLE;
-	reg |= JZ_NAND_ECC_CTRL_RS;
-
-	switch (mode) {
-	case NAND_ECC_READ:
-		reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
-		is_reading = 1;
-		break;
-	case NAND_ECC_WRITE:
-		reg |= JZ_NAND_ECC_CTRL_ENCODING;
-		is_reading = 0;
-		break;
-	default:
-		break;
-	}
-
-	writel(reg, &emc->nfecr);
-}
-
-/* Correct 1~9-bit errors in 512-bytes data */
-static void jz_rs_correct(unsigned char *dat, int idx, int mask)
-{
-	int i;
-
-	idx--;
-
-	i = idx + (idx >> 3);
-	if (i >= 512)
-		return;
-
-	mask <<= (idx & 0x7);
-
-	dat[i] ^= mask & 0xff;
-	if (i < 511)
-		dat[i + 1] ^= (mask >> 8) & 0xff;
-}
-
-static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
-				   u_char *read_ecc, u_char *calc_ecc)
-{
-	int k;
-	uint32_t errcnt, index, mask, status;
-
-	/* Set PAR values */
-	const uint8_t all_ff_ecc[] = {
-		0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
-
-	if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
-	    read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
-	    read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
-	    read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
-	    read_ecc[8] == 0xff) {
-		for (k = 0; k < 9; k++)
-			writeb(all_ff_ecc[k], &emc->nfpar[k]);
-	} else {
-		for (k = 0; k < 9; k++)
-			writeb(read_ecc[k], &emc->nfpar[k]);
-	}
-	/* Set PRDY */
-	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
-
-	/* Wait for completion */
-	do {
-		status = readl(&emc->nfints);
-	} while (!(status & EMC_NFINTS_DECF));
-
-	/* disable ecc */
-	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
-
-	/* Check decoding */
-	if (!(status & EMC_NFINTS_ERR))
-		return 0;
-
-	if (status & EMC_NFINTS_UNCOR) {
-		printf("uncorrectable ecc\n");
-		return -1;
-	}
-
-	errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
-
-	switch (errcnt) {
-	case 4:
-		index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	case 3:
-		index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	case 2:
-		index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	case 1:
-		index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	default:
-		break;
-	}
-
-	return errcnt;
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	uint32_t reg;
-
-	reg = readl(&emc->nfcsr);
-	reg |= EMC_NFCSR_NFE1;	/* EMC setup, Set NFE bit */
-	writel(reg, &emc->nfcsr);
-
-	writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
-
-	nand->IO_ADDR_R		= JZ_NAND_DATA_ADDR;
-	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
-	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
-	nand->dev_ready		= jz_nand_device_ready;
-	nand->ecc.hwctl		= jz_nand_hwctl;
-	nand->ecc.correct	= jz_nand_rs_correct_data;
-	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;
-	nand->ecc.mode		= NAND_ECC_HW_OOB_FIRST;
-	nand->ecc.size		= CONFIG_SYS_NAND_ECCSIZE;
-	nand->ecc.bytes		= CONFIG_SYS_NAND_ECCBYTES;
-	nand->ecc.strength	= 4;
-	nand->ecc.layout	= &qi_lb60_ecclayout_2gb;
-	nand->chip_delay	= 50;
-	nand->bbt_options	|= NAND_BBT_USE_FLASH;
-
-	return 0;
-}
-- 
cgit v0.10.2


From ea7d1eec66898b233ac49f8a60391b96afa25477 Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Mon, 30 May 2016 13:57:53 -0500
Subject: mtd: nand: Remove docg4 driver and palmtreo680 flashing tool

Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only
user of the docg4 driver and the palmtreo680 image flashing tool.  This
patch removes them.

Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Mike Dunn <mikedunn@newsguy.com>
Cc: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index aea6a93..837d397 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -13,7 +13,6 @@ endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
 obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
-obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
@@ -67,7 +66,6 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
-obj-$(CONFIG_NAND_DOCG4) += docg4.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
deleted file mode 100644
index c1c1ff8..0000000
--- a/drivers/mtd/nand/docg4.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-/*
- * drivers/mtd/nand/docg4.c
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * mtd nand driver for M-Systems DiskOnChip G4
- *
- * Tested on the Palm Treo 680.  The G4 is also present on Toshiba Portege, Asus
- * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
- * Should work on these as well.  Let me know!
- *
- * TODO:
- *
- *  Mechanism for management of password-protected areas
- *
- *  Hamming ecc when reading oob only
- *
- *  According to the M-Sys documentation, this device is also available in a
- *  "dual-die" configuration having a 256MB capacity, but no mechanism for
- *  detecting this variant is documented.  Currently this driver assumes 128MB
- *  capacity.
- *
- *  Support for multiple cascaded devices ("floors").  Not sure which gadgets
- *  contain multiple G4s in a cascaded configuration, if any.
- */
-
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <asm/errno.h>
-#include <malloc.h>
-#include <nand.h>
-#include <linux/bch.h>
-#include <linux/bitrev.h>
-#include <linux/mtd/docg4.h>
-
-/*
- * The device has a nop register which M-Sys claims is for the purpose of
- * inserting precise delays.  But beware; at least some operations fail if the
- * nop writes are replaced with a generic delay!
- */
-static inline void write_nop(void __iomem *docptr)
-{
-	writew(0, docptr + DOC_NOP);
-}
-
-
-static int poll_status(void __iomem *docptr)
-{
-	/*
-	 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
-	 * register.  Operations known to take a long time (e.g., block erase)
-	 * should sleep for a while before calling this.
-	 */
-
-	uint8_t flash_status;
-
-	/* hardware quirk requires reading twice initially */
-	flash_status = readb(docptr + DOC_FLASHCONTROL);
-
-	do {
-		flash_status = readb(docptr + DOC_FLASHCONTROL);
-	} while (!(flash_status & DOC_CTRL_FLASHREADY));
-
-	return 0;
-}
-
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* write the four address bytes packed in docg4_addr to the device */
-
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-/*
- * This is a module parameter in the linux kernel version of this driver.  It is
- * hard-coded to 'off' for u-boot.  This driver uses oob to mark bad blocks.
- * This can be problematic when dealing with data not intended for the mtd/nand
- * subsystem.  For example, on boards that boot from the docg4 and use the IPL
- * to load an spl + u-boot image, the blocks containing the image will be
- * reported as "bad" because the oob of the first page of each block contains a
- * magic number that the IPL looks for, which causes the badblock scan to
- * erroneously add them to the bad block table.  To erase such a block, use
- * u-boot's 'nand scrub'.  scrub is safe for the docg4.  The device does have a
- * factory bad block table, but it is read-only, and is used in conjunction with
- * oob bad block markers that are written by mtd/nand when a block is deemed to
- * be bad.  To read data from "bad" blocks, use 'read.raw'.  Unfortunately,
- * read.raw does not use ecc, which would still work fine on such misidentified
- * bad blocks.  TODO: u-boot nand utilities need the ability to ignore bad
- * blocks.
- */
-static const int ignore_badblocks; /* remains false */
-
-struct docg4_priv {
-	int status;
-	struct {
-		unsigned int command;
-		int column;
-		int page;
-	} last_command;
-	uint8_t oob_buf[16];
-	uint8_t ecc_buf[7];
-	int oob_page;
-	struct bch_control *bch;
-};
-/*
- * Oob bytes 0 - 6 are available to the user.
- * Byte 7 is hamming ecc for first 7 bytes.  Bytes 8 - 14 are hw-generated ecc.
- * Byte 15 (the last) is used by the driver as a "page written" flag.
- */
-static struct nand_ecclayout docg4_oobinfo = {
-	.eccbytes = 9,
-	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
-	.oobavail = 7,
-	.oobfree = { {0, 7} }
-};
-
-static void reset(void __iomem *docptr)
-{
-	/* full device reset */
-
-	writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN, docptr + DOC_ASICMODE);
-	writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
-	       docptr + DOC_ASICMODECONFIRM);
-	write_nop(docptr);
-
-	writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
-	       docptr + DOC_ASICMODE);
-	writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
-	       docptr + DOC_ASICMODECONFIRM);
-
-	writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
-
-	poll_status(docptr);
-}
-
-static void docg4_select_chip(struct mtd_info *mtd, int chip)
-{
-	/*
-	 * Select among multiple cascaded chips ("floors").  Multiple floors are
-	 * not yet supported, so the only valid non-negative value is 0.
-	 */
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-
-	if (chip < 0)
-		return;		/* deselected */
-
-	if (chip > 0)
-		printf("multiple floors currently unsupported\n");
-
-	writew(0, docptr + DOC_DEVICESELECT);
-}
-
-static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
-{
-	/* read the 7 hw-generated ecc bytes */
-
-	int i;
-	for (i = 0; i < 7; i++) { /* hw quirk; read twice */
-		ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
-		ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
-	}
-}
-
-static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
-{
-	/*
-	 * Called after a page read when hardware reports bitflips.
-	 * Up to four bitflips can be corrected.
-	 */
-
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	int i, numerrs;
-	unsigned int errpos[4];
-	const uint8_t blank_read_hwecc[8] = {
-		0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
-
-	read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
-
-	/* check if read error is due to a blank page */
-	if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
-		return 0;	/* yes */
-
-	/* skip additional check of "written flag" if ignore_badblocks */
-	if (!ignore_badblocks) {
-		/*
-		 * If the hw ecc bytes are not those of a blank page, there's
-		 * still a chance that the page is blank, but was read with
-		 * errors.  Check the "written flag" in last oob byte, which
-		 * is set to zero when a page is written.  If more than half
-		 * the bits are set, assume a blank page.  Unfortunately, the
-		 * bit flips(s) are not reported in stats.
-		 */
-
-		if (doc->oob_buf[15]) {
-			int bit, numsetbits = 0;
-			unsigned long written_flag = doc->oob_buf[15];
-
-			for (bit = 0; bit < 8; bit++) {
-				if (written_flag & 0x01)
-					numsetbits++;
-				written_flag >>= 1;
-			}
-			if (numsetbits > 4) { /* assume blank */
-				printf("errors in blank page at offset %08x\n",
-				       page * DOCG4_PAGE_SIZE);
-				return 0;
-			}
-		}
-	}
-
-	/*
-	 * The hardware ecc unit produces oob_ecc ^ calc_ecc.  The kernel's bch
-	 * algorithm is used to decode this.  However the hw operates on page
-	 * data in a bit order that is the reverse of that of the bch alg,
-	 * requiring that the bits be reversed on the result.  Thanks to Ivan
-	 * Djelic for his analysis!
-	 */
-	for (i = 0; i < 7; i++)
-		doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
-
-	numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
-			     doc->ecc_buf, NULL, errpos);
-
-	if (numerrs == -EBADMSG) {
-		printf("uncorrectable errors at offset %08x\n",
-		       page * DOCG4_PAGE_SIZE);
-		return -EBADMSG;
-	}
-
-	BUG_ON(numerrs < 0);	/* -EINVAL, or anything other than -EBADMSG */
-
-	/* undo last step in BCH alg (modulo mirroring not needed) */
-	for (i = 0; i < numerrs; i++)
-		errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
-
-	/* fix the errors */
-	for (i = 0; i < numerrs; i++) {
-		/* ignore if error within oob ecc bytes */
-		if (errpos[i] > DOCG4_USERDATA_LEN * 8)
-			continue;
-
-		/* if error within oob area preceeding ecc bytes... */
-		if (errpos[i] > DOCG4_PAGE_SIZE * 8)
-			__change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
-				     (unsigned long *)doc->oob_buf);
-
-		else    /* error in page data */
-			__change_bit(errpos[i], (unsigned long *)buf);
-	}
-
-	printf("%d error(s) corrected at offset %08x\n",
-	       numerrs, page * DOCG4_PAGE_SIZE);
-
-	return numerrs;
-}
-
-static int read_progstatus(struct docg4_priv *doc, void __iomem *docptr)
-{
-	/*
-	 * This apparently checks the status of programming.  Done after an
-	 * erasure, and after page data is written.  On error, the status is
-	 * saved, to be later retrieved by the nand infrastructure code.
-	 */
-
-	/* status is read from the I/O reg */
-	uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
-	uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
-	uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s: %02x %02x %02x\n",
-	    __func__, status1, status2, status3);
-
-	if (status1 != DOCG4_PROGSTATUS_GOOD ||
-	    status2 != DOCG4_PROGSTATUS_GOOD_2 ||
-	    status3 != DOCG4_PROGSTATUS_GOOD_2) {
-		doc->status = NAND_STATUS_FAIL;
-		printf("read_progstatus failed: %02x, %02x, %02x\n",
-		       status1, status2, status3);
-		return -EIO;
-	}
-	return 0;
-}
-
-static int pageprog(struct mtd_info *mtd)
-{
-	/*
-	 * Final step in writing a page.  Writes the contents of its
-	 * internal buffer out to the flash array, or some such.
-	 */
-
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	int retval = 0;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s\n", __func__);
-
-	writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* Just busy-wait; usleep_range() slows things down noticeably. */
-	poll_status(docptr);
-
-	writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
-	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	retval = read_progstatus(doc, docptr);
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-
-	return retval;
-}
-
-static void sequence_reset(void __iomem *docptr)
-{
-	/* common starting sequence for all operations */
-
-	writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
-	writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-}
-
-static void read_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* first step in reading a page */
-
-	sequence_reset(docptr);
-
-	writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-
-	write_addr(docptr, docg4_addr);
-
-	write_nop(docptr);
-	writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	poll_status(docptr);
-}
-
-static void write_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* first step in writing a page */
-
-	sequence_reset(docptr);
-	writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_addr(docptr, docg4_addr);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-}
-
-static uint32_t mtd_to_docg4_address(int page, int column)
-{
-	/*
-	 * Convert mtd address to format used by the device, 32 bit packed.
-	 *
-	 * Some notes on G4 addressing... The M-Sys documentation on this device
-	 * claims that pages are 2K in length, and indeed, the format of the
-	 * address used by the device reflects that.  But within each page are
-	 * four 512 byte "sub-pages", each with its own oob data that is
-	 * read/written immediately after the 512 bytes of page data.  This oob
-	 * data contains the ecc bytes for the preceeding 512 bytes.
-	 *
-	 * Rather than tell the mtd nand infrastructure that page size is 2k,
-	 * with four sub-pages each, we engage in a little subterfuge and tell
-	 * the infrastructure code that pages are 512 bytes in size.  This is
-	 * done because during the course of reverse-engineering the device, I
-	 * never observed an instance where an entire 2K "page" was read or
-	 * written as a unit.  Each "sub-page" is always addressed individually,
-	 * its data read/written, and ecc handled before the next "sub-page" is
-	 * addressed.
-	 *
-	 * This requires us to convert addresses passed by the mtd nand
-	 * infrastructure code to those used by the device.
-	 *
-	 * The address that is written to the device consists of four bytes: the
-	 * first two are the 2k page number, and the second is the index into
-	 * the page.  The index is in terms of 16-bit half-words and includes
-	 * the preceeding oob data, so e.g., the index into the second
-	 * "sub-page" is 0x108, and the full device address of the start of mtd
-	 * page 0x201 is 0x00800108.
-	 */
-	int g4_page = page / 4;	                      /* device's 2K page */
-	int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
-	return (g4_page << 16) | g4_index;	      /* pack */
-}
-
-static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
-			  int page_addr)
-{
-	/* handle standard nand commands */
-
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s %x, page_addr=%x, column=%x\n",
-	    __func__, command, page_addr, column);
-
-	/*
-	 * Save the command and its arguments.  This enables emulation of
-	 * standard flash devices, and also some optimizations.
-	 */
-	doc->last_command.command = command;
-	doc->last_command.column = column;
-	doc->last_command.page = page_addr;
-
-	switch (command) {
-	case NAND_CMD_RESET:
-		reset(CONFIG_SYS_NAND_BASE);
-		break;
-
-	case NAND_CMD_READ0:
-		read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-		break;
-
-	case NAND_CMD_STATUS:
-		/* next call to read_byte() will expect a status */
-		break;
-
-	case NAND_CMD_SEQIN:
-		write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-
-		/* hack for deferred write of oob bytes */
-		if (doc->oob_page == page_addr)
-			memcpy(nand->oob_poi, doc->oob_buf, 16);
-		break;
-
-	case NAND_CMD_PAGEPROG:
-		pageprog(mtd);
-		break;
-
-	/* we don't expect these, based on review of nand_base.c */
-	case NAND_CMD_READOOB:
-	case NAND_CMD_READID:
-	case NAND_CMD_ERASE1:
-	case NAND_CMD_ERASE2:
-		printf("docg4_command: unexpected nand command 0x%x\n",
-		       command);
-		break;
-	}
-}
-
-static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *nand = mtd->priv;
-	uint16_t *p = (uint16_t *)buf;
-	len >>= 1;
-
-	for (i = 0; i < len; i++)
-		p[i] = readw(nand->IO_ADDR_R);
-}
-
-static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
-			  int page)
-{
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint16_t status;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %x\n", __func__, page);
-
-	/*
-	 * Oob bytes are read as part of a normal page read.  If the previous
-	 * nand command was a read of the page whose oob is now being read, just
-	 * copy the oob bytes that we saved in a local buffer and avoid a
-	 * separate oob read.
-	 */
-	if (doc->last_command.command == NAND_CMD_READ0 &&
-	    doc->last_command.page == page) {
-		memcpy(nand->oob_poi, doc->oob_buf, 16);
-		return 0;
-	}
-
-	/*
-	 * Separate read of oob data only.
-	 */
-	docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
-
-	writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* the 1st byte from the I/O reg is a status; the rest is oob data */
-	status = readw(docptr + DOC_IOSPACE_DATA);
-	if (status & DOCG4_READ_ERROR) {
-		printf("docg4_read_oob failed: status = 0x%02x\n", status);
-		return -EIO;
-	}
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: status = 0x%x\n", __func__, status);
-
-	docg4_read_buf(mtd, nand->oob_poi, 16);
-
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-
-	return 0;
-}
-
-static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
-			   int page)
-{
-	/*
-	 * Writing oob-only is not really supported, because MLC nand must write
-	 * oob bytes at the same time as page data.  Nonetheless, we save the
-	 * oob buffer contents here, and then write it along with the page data
-	 * if the same page is subsequently written.  This allows user space
-	 * utilities that write the oob data prior to the page data to work
-	 * (e.g., nandwrite).  The disdvantage is that, if the intention was to
-	 * write oob only, the operation is quietly ignored.  Also, oob can get
-	 * corrupted if two concurrent processes are running nandwrite.
-	 */
-
-	/* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
-	struct docg4_priv *doc = nand->priv;
-	doc->oob_page = page;
-	memcpy(doc->oob_buf, nand->oob_poi, 16);
-	return 0;
-}
-
-static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
-{
-	/* only called when module_param ignore_badblocks is set */
-	return 0;
-}
-
-static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *nand = mtd->priv;
-	uint16_t *p = (uint16_t *)buf;
-	len >>= 1;
-
-	for (i = 0; i < len; i++)
-		writew(p[i], nand->IO_ADDR_W);
-}
-
-static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
-		       const uint8_t *buf, int use_ecc)
-{
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint8_t ecc_buf[8];
-
-	writew(DOC_ECCCONF0_ECC_ENABLE |
-	       DOC_ECCCONF0_UNKNOWN |
-	       DOCG4_BCH_SIZE,
-	       docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-
-	/* write the page data */
-	docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
-
-	/* oob bytes 0 through 5 are written to I/O reg */
-	docg4_write_buf16(mtd, nand->oob_poi, 6);
-
-	/* oob byte 6 written to a separate reg */
-	writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
-
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* write hw-generated ecc bytes to oob */
-	if (likely(use_ecc)) {
-		/* oob byte 7 is hamming code */
-		uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
-		hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
-		writew(hamming, docptr + DOCG4_OOB_6_7);
-		write_nop(docptr);
-
-		/* read the 7 bch bytes from ecc regs */
-		read_hw_ecc(docptr, ecc_buf);
-		ecc_buf[7] = 0;         /* clear the "page written" flag */
-	}
-
-	/* write user-supplied bytes to oob */
-	else {
-		writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
-		write_nop(docptr);
-		memcpy(ecc_buf, &nand->oob_poi[8], 8);
-	}
-
-	docg4_write_buf16(mtd, ecc_buf, 8);
-	write_nop(docptr);
-	write_nop(docptr);
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-
-	return 0;
-}
-
-static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-				 const uint8_t *buf, int oob_required)
-{
-	return write_page(mtd, nand, buf, 0);
-}
-
-static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
-			     const uint8_t *buf, int oob_required)
-{
-	return write_page(mtd, nand, buf, 1);
-}
-
-static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
-		     uint8_t *buf, int page, int use_ecc)
-{
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint16_t status, edc_err, *buf16;
-
-	writew(DOC_ECCCONF0_READ_MODE |
-	       DOC_ECCCONF0_ECC_ENABLE |
-	       DOC_ECCCONF0_UNKNOWN |
-	       DOCG4_BCH_SIZE,
-	       docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* the 1st byte from the I/O reg is a status; the rest is page data */
-	status = readw(docptr + DOC_IOSPACE_DATA);
-	if (status & DOCG4_READ_ERROR) {
-		printf("docg4_read_page: bad status: 0x%02x\n", status);
-		writew(0, docptr + DOC_DATAEND);
-		return -EIO;
-	}
-
-	docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
-
-	/* first 14 oob bytes read from I/O reg */
-	docg4_read_buf(mtd, nand->oob_poi, 14);
-
-	/* last 2 read from another reg */
-	buf16 = (uint16_t *)(nand->oob_poi + 14);
-	*buf16 = readw(docptr + DOCG4_MYSTERY_REG);
-
-	/*
-	 * Diskonchips read oob immediately after a page read.  Mtd
-	 * infrastructure issues a separate command for reading oob after the
-	 * page is read.  So we save the oob bytes in a local buffer and just
-	 * copy it if the next command reads oob from the same page.
-	 */
-	memcpy(doc->oob_buf, nand->oob_poi, 16);
-
-	write_nop(docptr);
-
-	if (likely(use_ecc)) {
-		/* read the register that tells us if bitflip(s) detected  */
-		edc_err = readw(docptr + DOC_ECCCONF1);
-		edc_err = readw(docptr + DOC_ECCCONF1);
-
-		/* If bitflips are reported, attempt to correct with ecc */
-		if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
-			int bits_corrected = correct_data(mtd, buf, page);
-			if (bits_corrected == -EBADMSG)
-				mtd->ecc_stats.failed++;
-			else
-				mtd->ecc_stats.corrected += bits_corrected;
-		}
-	}
-
-	writew(0, docptr + DOC_DATAEND);
-	return 0;
-}
-
-
-static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-			       uint8_t *buf, int oob_required, int page)
-{
-	return read_page(mtd, nand, buf, page, 0);
-}
-
-static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
-			   uint8_t *buf, int oob_required, int page)
-{
-	return read_page(mtd, nand, buf, page, 1);
-}
-
-static int docg4_erase_block(struct mtd_info *mtd, int page)
-{
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint16_t g4_page;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %04x\n", __func__, page);
-
-	sequence_reset(docptr);
-
-	writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-
-	/* only 2 bytes of address are written to specify erase block */
-	g4_page = (uint16_t)(page / 4);  /* to g4's 2k page addressing */
-	writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
-	g4_page >>= 8;
-	writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
-	write_nop(docptr);
-
-	/* start the erasure */
-	writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	poll_status(docptr);
-	writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
-	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	read_progstatus(doc, docptr);
-
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-
-	return nand->waitfunc(mtd, nand);
-}
-
-static int read_factory_bbt(struct mtd_info *mtd)
-{
-	/*
-	 * The device contains a read-only factory bad block table.  Read it and
-	 * update the memory-based bbt accordingly.
-	 */
-
-	struct nand_chip *nand = mtd->priv;
-	uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
-	uint8_t *buf;
-	int i, block, status;
-
-	buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
-	if (buf == NULL)
-		return -ENOMEM;
-
-	read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-	status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
-	if (status)
-		goto exit;
-
-	/*
-	 * If no memory-based bbt was created, exit.  This will happen if module
-	 * parameter ignore_badblocks is set.  Then why even call this function?
-	 * For an unknown reason, block erase always fails if it's the first
-	 * operation after device power-up.  The above read ensures it never is.
-	 * Ugly, I know.
-	 */
-	if (nand->bbt == NULL)  /* no memory-based bbt */
-		goto exit;
-
-	/*
-	 * Parse factory bbt and update memory-based bbt.  Factory bbt format is
-	 * simple: one bit per block, block numbers increase left to right (msb
-	 * to lsb).  Bit clear means bad block.
-	 */
-	for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
-		int bitnum;
-		uint8_t mask;
-		for (bitnum = 0, mask = 0x80;
-		     bitnum < 8; bitnum++, mask >>= 1) {
-			if (!(buf[i] & mask)) {
-				int badblock = block + bitnum;
-				nand->bbt[badblock / 4] |=
-					0x03 << ((badblock % 4) * 2);
-				mtd->ecc_stats.badblocks++;
-				printf("factory-marked bad block: %d\n",
-				       badblock);
-			}
-		}
-	}
- exit:
-	kfree(buf);
-	return status;
-}
-
-static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
-{
-	/*
-	 * Mark a block as bad.  Bad blocks are marked in the oob area of the
-	 * first page of the block.  The default scan_bbt() in the nand
-	 * infrastructure code works fine for building the memory-based bbt
-	 * during initialization, as does the nand infrastructure function that
-	 * checks if a block is bad by reading the bbt.  This function replaces
-	 * the nand default because writes to oob-only are not supported.
-	 */
-
-	int ret, i;
-	uint8_t *buf;
-	struct nand_chip *nand = mtd->priv;
-	struct nand_bbt_descr *bbtd = nand->badblock_pattern;
-	int block = (int)(ofs >> nand->bbt_erase_shift);
-	int page = (int)(ofs >> nand->page_shift);
-	uint32_t g4_addr = mtd_to_docg4_address(page, 0);
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: %08llx\n", __func__, ofs);
-
-	if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
-		printf("%s: ofs %llx not start of block!\n",
-		       __func__, ofs);
-
-	/* allocate blank buffer for page data */
-	buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
-	if (buf == NULL)
-		return -ENOMEM;
-
-	/* update bbt in memory */
-	nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
-
-	/* write bit-wise negation of pattern to oob buffer */
-	memset(nand->oob_poi, 0xff, mtd->oobsize);
-	for (i = 0; i < bbtd->len; i++)
-		nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
-
-	/* write first page of block */
-	write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-	docg4_write_page(mtd, nand, buf, 1);
-	ret = pageprog(mtd);
-	if (!ret)
-		mtd->ecc_stats.badblocks++;
-
-	kfree(buf);
-
-	return ret;
-}
-
-static uint8_t docg4_read_byte(struct mtd_info *mtd)
-{
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__);
-
-	if (doc->last_command.command == NAND_CMD_STATUS) {
-		int status;
-
-		/*
-		 * Previous nand command was status request, so nand
-		 * infrastructure code expects to read the status here.  If an
-		 * error occurred in a previous operation, report it.
-		 */
-		doc->last_command.command = 0;
-
-		if (doc->status) {
-			status = doc->status;
-			doc->status = 0;
-		}
-
-		/* why is NAND_STATUS_WP inverse logic?? */
-		else
-			status = NAND_STATUS_WP | NAND_STATUS_READY;
-
-		return status;
-	}
-
-	printf("unexpectd call to read_byte()\n");
-
-	return 0;
-}
-
-static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
-{
-	struct docg4_priv *doc = nand->priv;
-	int status = NAND_STATUS_WP;       /* inverse logic?? */
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s...\n", __func__);
-
-	/* report any previously unreported error */
-	if (doc->status) {
-		status |= doc->status;
-		doc->status = 0;
-		return status;
-	}
-
-	status |= poll_status(CONFIG_SYS_NAND_BASE);
-	return status;
-}
-
-int docg4_nand_init(struct mtd_info *mtd, struct nand_chip *nand, int devnum)
-{
-	uint16_t id1, id2;
-	struct docg4_priv *docg4;
-	int retval;
-
-	docg4 = kzalloc(sizeof(*docg4), GFP_KERNEL);
-	if (!docg4)
-		return -1;
-
-	mtd->priv = nand;
-	nand->priv = docg4;
-
-	/* These must be initialized here because the docg4 is non-standard
-	 * and doesn't produce an id that the nand code can use to look up
-	 * these values (nand_scan_ident() not called).
-	 */
-	mtd->size = DOCG4_CHIP_SIZE;
-	mtd->name = "Msys_Diskonchip_G4";
-	mtd->writesize = DOCG4_PAGE_SIZE;
-	mtd->erasesize = DOCG4_BLOCK_SIZE;
-	mtd->oobsize = DOCG4_OOB_SIZE;
-
-	nand->IO_ADDR_R =
-		(void __iomem *)CONFIG_SYS_NAND_BASE + DOC_IOSPACE_DATA;
-	nand->IO_ADDR_W = nand->IO_ADDR_R;
-	nand->chipsize = DOCG4_CHIP_SIZE;
-	nand->chip_shift = DOCG4_CHIP_SHIFT;
-	nand->bbt_erase_shift = DOCG4_ERASE_SHIFT;
-	nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
-	nand->chip_delay = 20;
-	nand->page_shift = DOCG4_PAGE_SHIFT;
-	nand->pagemask = 0x3ffff;
-	nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
-	nand->badblockbits = 8;
-	nand->ecc.layout = &docg4_oobinfo;
-	nand->ecc.mode = NAND_ECC_HW_SYNDROME;
-	nand->ecc.size = DOCG4_PAGE_SIZE;
-	nand->ecc.prepad = 8;
-	nand->ecc.bytes	= 8;
-	nand->ecc.strength = DOCG4_T;
-	nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
-	nand->controller = &nand->hwcontrol;
-
-	/* methods */
-	nand->cmdfunc = docg4_command;
-	nand->waitfunc = docg4_wait;
-	nand->select_chip = docg4_select_chip;
-	nand->read_byte = docg4_read_byte;
-	nand->block_markbad = docg4_block_markbad;
-	nand->read_buf = docg4_read_buf;
-	nand->write_buf = docg4_write_buf16;
-	nand->scan_bbt = nand_default_bbt;
-	nand->erase = docg4_erase_block;
-	nand->ecc.read_page = docg4_read_page;
-	nand->ecc.write_page = docg4_write_page;
-	nand->ecc.read_page_raw = docg4_read_page_raw;
-	nand->ecc.write_page_raw = docg4_write_page_raw;
-	nand->ecc.read_oob = docg4_read_oob;
-	nand->ecc.write_oob = docg4_write_oob;
-
-	/*
-	 * The way the nand infrastructure code is written, a memory-based bbt
-	 * is not created if NAND_SKIP_BBTSCAN is set.  With no memory bbt,
-	 * nand->block_bad() is used.  So when ignoring bad blocks, we skip the
-	 * scan and define a dummy block_bad() which always returns 0.
-	 */
-	if (ignore_badblocks) {
-		nand->options |= NAND_SKIP_BBTSCAN;
-		nand->block_bad	= docg4_block_neverbad;
-	}
-
-	reset(CONFIG_SYS_NAND_BASE);
-
-	/* check for presence of g4 chip by reading id registers */
-	id1 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID);
-	id1 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
-	id2 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID_INV);
-	id2 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
-	if (id1 != DOCG4_IDREG1_VALUE || id2 != DOCG4_IDREG2_VALUE)
-		return -1;
-
-	/* initialize bch algorithm */
-	docg4->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
-	if (docg4->bch == NULL)
-		return -1;
-
-	retval = nand_scan_tail(mtd);
-	if (retval)
-		return -1;
-
-	/*
-	 * Scan for bad blocks and create bbt here, then add the factory-marked
-	 * bad blocks to the bbt.
-	 */
-	nand->scan_bbt(mtd);
-	nand->options |= NAND_BBT_SCANNED;
-	retval = read_factory_bbt(mtd);
-	if (retval)
-		return -1;
-
-	retval = nand_register(devnum);
-	if (retval)
-		return -1;
-
-	return 0;
-}
diff --git a/drivers/mtd/nand/docg4_spl.c b/drivers/mtd/nand/docg4_spl.c
deleted file mode 100644
index 351b75a..0000000
--- a/drivers/mtd/nand/docg4_spl.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * SPL driver for Diskonchip G4 nand flash
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This driver basically mimics the load functionality of a typical IPL (initial
- * program loader) resident in the 2k NOR-like region of the docg4 that is
- * mapped to the reset vector.  It allows the u-boot SPL to continue loading if
- * the IPL loads a fixed number of flash blocks that is insufficient to contain
- * the entire u-boot image.  In this case, a concatenated spl + u-boot image is
- * written at the flash offset from which the IPL loads an image, and when the
- * IPL jumps to the SPL, the SPL resumes loading where the IPL left off.  See
- * the palmtreo680 for an example.
- *
- * This driver assumes that the data was written to the flash using the device's
- * "reliable" mode, and also assumes that each 512 byte page is stored
- * redundantly in the subsequent page.  This storage format is likely to be used
- * by all boards that boot from the docg4.  The format compensates for the lack
- * of ecc in the IPL.
- *
- * Reliable mode reduces the capacity of a block by half, and the redundant
- * pages reduce it by half again.  As a result, the normal 256k capacity of a
- * block is reduced to 64k for the purposes of the IPL/SPL.
- */
-
-#include <asm/io.h>
-#include <linux/mtd/docg4.h>
-
-/* forward declarations */
-static inline void write_nop(void __iomem *docptr);
-static int poll_status(void __iomem *docptr);
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr);
-static void address_sequence(unsigned int g4_page, unsigned int g4_index,
-			     void __iomem *docptr);
-static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr);
-
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
-{
-	void *load_addr = dst;
-	uint32_t flash_offset = offs;
-	const unsigned int block_count =
-		(size + DOCG4_BLOCK_CAPACITY_SPL - 1)
-		/ DOCG4_BLOCK_CAPACITY_SPL;
-	int i;
-
-	for (i = 0; i < block_count; i++) {
-		int ret = docg4_load_block_reliable(flash_offset, load_addr);
-		if (ret)
-			return ret;
-		load_addr += DOCG4_BLOCK_CAPACITY_SPL;
-		flash_offset += DOCG4_BLOCK_SIZE;
-	}
-	return 0;
-}
-
-static inline void write_nop(void __iomem *docptr)
-{
-	writew(0, docptr + DOC_NOP);
-}
-
-static int poll_status(void __iomem *docptr)
-{
-	/*
-	 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
-	 * register.  Operations known to take a long time (e.g., block erase)
-	 * should sleep for a while before calling this.
-	 */
-
-	uint8_t flash_status;
-
-	/* hardware quirk requires reading twice initially */
-	flash_status = readb(docptr + DOC_FLASHCONTROL);
-
-	do {
-		flash_status = readb(docptr + DOC_FLASHCONTROL);
-	} while (!(flash_status & DOC_CTRL_FLASHREADY));
-
-	return 0;
-}
-
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* write the four address bytes packed in docg4_addr to the device */
-
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-static void address_sequence(unsigned int g4_page, unsigned int g4_index,
-			     void __iomem *docptr)
-{
-	writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index);
-	write_nop(docptr);
-}
-
-static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
-{
-	void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
-	unsigned int g4_page = flash_offset >> 11; /* 2k page */
-	const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
-	int g4_index = 0;
-	uint16_t flash_status;
-	uint16_t *buf;
-
-	/* flash_offset must be aligned to the start of a block */
-	if (flash_offset & 0x3ffff)
-		return -1;
-
-	writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-	writew(0x45, docptr + DOC_FLASHSEQUENCE);
-	writew(0xa3, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	writew(0x22, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-
-	/* read 1st 4 oob bytes of first subpage of block */
-	address_sequence(g4_page, 0x0100, docptr); /* index at oob */
-	write_nop(docptr);
-	flash_status = readw(docptr + DOC_FLASHCONTROL);
-	flash_status = readw(docptr + DOC_FLASHCONTROL);
-	if (flash_status & 0x06) /* sequence or protection errors */
-		return -1;
-	writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/*
-	 * Here we read the first four oob bytes of the first page of the block.
-	 * The IPL on the palmtreo680 requires that this contain a 32 bit magic
-	 * number, or the load aborts.  We'll ignore it.
-	 */
-	readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
-	readw(docptr + 0x103c);	/* lower 16 bits of magic number */
-	readw(docptr + DOCG4_MYSTERY_REG); /* upper 16 bits of magic number */
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* load contents of block to memory */
-	buf = (uint16_t *)dest_addr;
-	do {
-		int i;
-
-		address_sequence(g4_page, g4_index, docptr);
-		writew(DOCG4_CMD_READ2,
-		       docptr + DOC_FLASHCOMMAND);
-		write_nop(docptr);
-		write_nop(docptr);
-		poll_status(docptr);
-		writew(DOC_ECCCONF0_READ_MODE |
-		       DOC_ECCCONF0_ECC_ENABLE |
-		       DOCG4_BCH_SIZE,
-		       docptr + DOC_ECCCONF0);
-		write_nop(docptr);
-		write_nop(docptr);
-		write_nop(docptr);
-		write_nop(docptr);
-		write_nop(docptr);
-
-		/* read the 512 bytes of page data, 2 bytes at a time */
-		readw(docptr + 0x103c); /* hw quirk */
-		for (i = 0; i < 256; i++)
-			*buf++ = readw(docptr + 0x103c);
-
-		/* read oob, but discard it */
-		for (i = 0; i < 7; i++)
-			readw(docptr + 0x103c);
-		readw(docptr + DOCG4_OOB_6_7);
-		readw(docptr + DOCG4_OOB_6_7);
-
-		writew(0, docptr + DOC_DATAEND);
-		write_nop(docptr);
-		write_nop(docptr);
-
-		if (!(g4_index & 0x100)) {
-			/* not redundant subpage read; check for ecc error */
-			write_nop(docptr);
-			flash_status = readw(docptr + DOC_ECCCONF1);
-			flash_status = readw(docptr + DOC_ECCCONF1);
-			if (flash_status & 0x80) { /* ecc error */
-				g4_index += 0x108; /* read redundant subpage */
-				buf -= 256;        /* back up ram ptr */
-				continue;
-			} else                       /* no ecc error */
-				g4_index += 0x210; /* skip redundant subpage */
-		} else  /* redundant page was just read; skip ecc error check */
-			g4_index += 0x108;
-
-		if (g4_index == 0x420) { /* finished with 2k page */
-			g4_index = 0;
-			g4_page += 2; /* odd-numbered 2k pages skipped */
-		}
-
-	} while (g4_page != last_g4_page); /* while still on same block */
-
-	return 0;
-}
diff --git a/include/linux/mtd/docg4.h b/include/linux/mtd/docg4.h
deleted file mode 100644
index 741fc0d..0000000
--- a/include/linux/mtd/docg4.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __DOCG4_H__
-#define __DOCG4_H__
-
-#include <common.h>
-#include <linux/mtd/nand.h>
-
-extern int docg4_nand_init(struct mtd_info *mtd,
-			   struct nand_chip *nand, int devnum);
-
-/* SPL-related definitions */
-#define DOCG4_IPL_LOAD_BLOCK_COUNT 2  /* number of blocks that IPL loads */
-#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */
-
-#define DOC_IOSPACE_DATA		0x0800
-
-/* register offsets */
-#define DOC_CHIPID			0x1000
-#define DOC_DEVICESELECT		0x100a
-#define DOC_ASICMODE			0x100c
-#define DOC_DATAEND			0x101e
-#define DOC_NOP				0x103e
-
-#define DOC_FLASHSEQUENCE		0x1032
-#define DOC_FLASHCOMMAND		0x1034
-#define DOC_FLASHADDRESS		0x1036
-#define DOC_FLASHCONTROL		0x1038
-#define DOC_ECCCONF0			0x1040
-#define DOC_ECCCONF1			0x1042
-#define DOC_HAMMINGPARITY		0x1046
-#define DOC_BCH_SYNDROM(idx)		(0x1048 + idx)
-
-#define DOC_ASICMODECONFIRM		0x1072
-#define DOC_CHIPID_INV			0x1074
-#define DOC_POWERMODE			0x107c
-
-#define DOCG4_MYSTERY_REG		0x1050
-
-/* apparently used only to write oob bytes 6 and 7 */
-#define DOCG4_OOB_6_7			0x1052
-
-/* DOC_FLASHSEQUENCE register commands */
-#define DOC_SEQ_RESET			0x00
-#define DOCG4_SEQ_PAGE_READ		0x03
-#define DOCG4_SEQ_FLUSH			0x29
-#define DOCG4_SEQ_PAGEWRITE		0x16
-#define DOCG4_SEQ_PAGEPROG		0x1e
-#define DOCG4_SEQ_BLOCKERASE		0x24
-
-/* DOC_FLASHCOMMAND register commands */
-#define DOCG4_CMD_PAGE_READ             0x00
-#define DOC_CMD_ERASECYCLE2		0xd0
-#define DOCG4_CMD_FLUSH                 0x70
-#define DOCG4_CMD_READ2                 0x30
-#define DOC_CMD_PROG_BLOCK_ADDR		0x60
-#define DOCG4_CMD_PAGEWRITE		0x80
-#define DOC_CMD_PROG_CYCLE2		0x10
-#define DOC_CMD_RESET			0xff
-
-/* DOC_POWERMODE register bits */
-#define DOC_POWERDOWN_READY		0x80
-
-/* DOC_FLASHCONTROL register bits */
-#define DOC_CTRL_CE			0x10
-#define DOC_CTRL_UNKNOWN		0x40
-#define DOC_CTRL_FLASHREADY		0x01
-
-/* DOC_ECCCONF0 register bits */
-#define DOC_ECCCONF0_READ_MODE		0x8000
-#define DOC_ECCCONF0_UNKNOWN		0x2000
-#define DOC_ECCCONF0_ECC_ENABLE	        0x1000
-#define DOC_ECCCONF0_DATA_BYTES_MASK	0x07ff
-
-/* DOC_ECCCONF1 register bits */
-#define DOC_ECCCONF1_BCH_SYNDROM_ERR	0x80
-#define DOC_ECCCONF1_ECC_ENABLE         0x07
-#define DOC_ECCCONF1_PAGE_IS_WRITTEN	0x20
-
-/* DOC_ASICMODE register bits */
-#define DOC_ASICMODE_RESET		0x00
-#define DOC_ASICMODE_NORMAL		0x01
-#define DOC_ASICMODE_POWERDOWN		0x02
-#define DOC_ASICMODE_MDWREN		0x04
-#define DOC_ASICMODE_BDETCT_RESET	0x08
-#define DOC_ASICMODE_RSTIN_RESET	0x10
-#define DOC_ASICMODE_RAM_WE		0x20
-
-/* good status values read after read/write/erase operations */
-#define DOCG4_PROGSTATUS_GOOD          0x51
-#define DOCG4_PROGSTATUS_GOOD_2        0xe0
-
-/*
- * On read operations (page and oob-only), the first byte read from I/O reg is a
- * status.  On error, it reads 0x73; otherwise, it reads either 0x71 (first read
- * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
- */
-#define DOCG4_READ_ERROR           0x02 /* bit 1 indicates read error */
-
-/* anatomy of the device */
-#define DOCG4_CHIP_SIZE        0x8000000
-#define DOCG4_PAGE_SIZE        0x200
-#define DOCG4_PAGES_PER_BLOCK  0x200
-#define DOCG4_BLOCK_SIZE       (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
-#define DOCG4_NUMBLOCKS        (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
-#define DOCG4_OOB_SIZE         0x10
-#define DOCG4_CHIP_SHIFT       27    /* log_2(DOCG4_CHIP_SIZE) */
-#define DOCG4_PAGE_SHIFT       9     /* log_2(DOCG4_PAGE_SIZE) */
-#define DOCG4_ERASE_SHIFT      18    /* log_2(DOCG4_BLOCK_SIZE) */
-
-/* all but the last byte is included in ecc calculation */
-#define DOCG4_BCH_SIZE         (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
-
-#define DOCG4_USERDATA_LEN     520 /* 512 byte page plus 8 oob avail to user */
-
-/* expected values from the ID registers */
-#define DOCG4_IDREG1_VALUE     0x0400
-#define DOCG4_IDREG2_VALUE     0xfbff
-
-/* primitive polynomial used to build the Galois field used by hw ecc gen */
-#define DOCG4_PRIMITIVE_POLY   0x4443
-
-#define DOCG4_M                14  /* Galois field is of order 2^14 */
-#define DOCG4_T                4   /* BCH alg corrects up to 4 bit errors */
-
-#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
-
-#endif	/* __DOCG4_H__ */
diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c
deleted file mode 100644
index 832d3fe..0000000
--- a/tools/palmtreo680/flash_u-boot.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- *
- * This is a userspace Linux utility that, when run on the Treo 680, will
- * program u-boot to flash.  The docg4 driver *must* be loaded with the
- * reliable_mode and ignore_badblocks parameters enabled:
- *
- *        modprobe docg4 ignore_badblocks=1 reliable_mode=1
- *
- * This utility writes the concatenated spl + u-boot image to the start of the
- * mtd device in the format expected by the IPL/SPL.  The image file and mtd
- * device node are passed to the utility as arguments.  The blocks must have
- * been erased beforehand.
- *
- * When you compile this, note that it links to libmtd from mtd-utils, so ensure
- * that your include and lib paths include this.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <errno.h>
-#include <mtd/mtd-user.h>
-#include "libmtd.h"
-
-#define RELIABLE_BLOCKSIZE  0x10000 /* block capacity in reliable mode */
-#define STANDARD_BLOCKSIZE  0x40000 /* block capacity in normal mode */
-#define PAGESIZE 512
-#define PAGES_PER_BLOCK 512
-#define OOBSIZE 7		/* available to user (16 total) */
-
-uint8_t ff_oob[OOBSIZE] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
-/* this is the magic number the IPL looks for (ASCII "BIPO") */
-uint8_t page0_oob[OOBSIZE] = {'B', 'I', 'P', 'O', 0xff, 0xff, 0xff};
-
-int main(int argc, char * const argv[])
-{
-	int devfd, datafd, num_blocks, block;
-	off_t file_size;
-	libmtd_t mtd_desc;
-	struct mtd_dev_info devinfo;
-	uint8_t *blockbuf;
-	char response[8];
-
-	if (argc != 3) {
-		printf("usage: %s <image file> <mtd dev node>\n", argv[0]);
-		return -EINVAL;
-	}
-
-	mtd_desc = libmtd_open();
-	if (mtd_desc == NULL) {
-		int errsv = errno;
-		fprintf(stderr, "can't initialize libmtd\n");
-		return -errsv;
-	}
-
-	/* open the spl image file and mtd device */
-	datafd = open(argv[1], O_RDONLY);
-	if (datafd == -1) {
-		int errsv = errno;
-		perror(argv[1]);
-		return -errsv;
-	}
-	devfd = open(argv[2], O_WRONLY);
-	if (devfd == -1) {
-		int errsv = errno;
-		perror(argv[2]);
-		return -errsv;
-	}
-	if (mtd_get_dev_info(mtd_desc, argv[2], &devinfo) < 0) {
-		int errsv = errno;
-		perror(argv[2]);
-		return -errsv;
-	}
-
-	/* determine the number of blocks needed by the image */
-	file_size = lseek(datafd, 0, SEEK_END);
-	if (file_size == (off_t)-1) {
-		int errsv = errno;
-		perror("lseek");
-		return -errsv;
-	}
-	num_blocks = (file_size + RELIABLE_BLOCKSIZE - 1) / RELIABLE_BLOCKSIZE;
-	file_size = lseek(datafd, 0, SEEK_SET);
-	if (file_size == (off_t)-1) {
-		int errsv = errno;
-		perror("lseek");
-		return -errsv;
-	}
-	printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt);
-	printf("U-Boot will occupy %d blocks\n", num_blocks);
-	if (num_blocks > devinfo.eb_cnt) {
-		fprintf(stderr, "Insufficient blocks on partition\n");
-		return -EINVAL;
-	}
-
-	printf("IMPORTANT: These blocks must be in an erased state!\n");
-	printf("Do you want to proceed?\n");
-	scanf("%s", response);
-	if ((response[0] != 'y') && (response[0] != 'Y')) {
-		printf("Exiting\n");
-		close(devfd);
-		close(datafd);
-		return 0;
-	}
-
-	blockbuf = calloc(RELIABLE_BLOCKSIZE, 1);
-	if (blockbuf == NULL) {
-		int errsv = errno;
-		perror("calloc");
-		return -errsv;
-	}
-
-	for (block = 0; block < num_blocks; block++) {
-		int ofs, page;
-		uint8_t *pagebuf = blockbuf, *buf = blockbuf;
-		uint8_t *oobbuf = page0_oob; /* magic num in oob of 1st page */
-		size_t len = RELIABLE_BLOCKSIZE;
-		int ret;
-
-		/* read data for one block from file */
-		while (len) {
-			ssize_t read_ret = read(datafd, buf, len);
-			if (read_ret == -1) {
-				int errsv = errno;
-				if (errno == EINTR)
-					continue;
-				perror("read");
-				return -errsv;
-			} else if (read_ret == 0) {
-				break; /* EOF */
-			}
-			len -= read_ret;
-			buf += read_ret;
-		}
-
-		printf("Block %d: writing\r", block + 1);
-		fflush(stdout);
-
-		for (page = 0, ofs = 0;
-		     page < PAGES_PER_BLOCK;
-		     page++, ofs += PAGESIZE) {
-			if (page & 0x04)  /* Odd-numbered 2k page */
-				continue; /* skipped in reliable mode */
-
-			ret = mtd_write(mtd_desc, &devinfo, devfd, block, ofs,
-					pagebuf, PAGESIZE, oobbuf, OOBSIZE,
-					MTD_OPS_PLACE_OOB);
-			if (ret) {
-				fprintf(stderr,
-					"\nmtd_write returned %d on block %d, ofs %x\n",
-					ret, block + 1, ofs);
-				return -EIO;
-			}
-			oobbuf = ff_oob;  /* oob for subsequent pages */
-
-			if (page & 0x01)  /* odd-numbered subpage */
-				pagebuf += PAGESIZE;
-		}
-	}
-
-	printf("\nDone\n");
-
-	close(devfd);
-	close(datafd);
-	free(blockbuf);
-	return 0;
-}
-- 
cgit v0.10.2


From 151c06ec61d74b77cf27d6d622bab6370c949c66 Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Mon, 30 May 2016 13:57:54 -0500
Subject: mtd: nand: Remove nand_info_t typedef

This typedef serves no purpose other than causing confusion with
struct nand_chip.

Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/cmd/bootm.c b/cmd/bootm.c
index ee3b460..24f1054 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -372,8 +372,8 @@ next_bank:	;
 #endif
 
 #if defined(CONFIG_CMD_IMLS_NAND)
-static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
-		size_t len)
+static int nand_imls_legacyimage(struct mtd_info *mtd, int nand_dev,
+				 loff_t off, size_t len)
 {
 	void *imgdata;
 	int ret;
@@ -386,8 +386,7 @@ static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
 		return -ENOMEM;
 	}
 
-	ret = nand_read_skip_bad(nand, off, &len,
-			imgdata);
+	ret = nand_read_skip_bad(mtd, off, &len, imgdata);
 	if (ret < 0 && ret != -EUCLEAN) {
 		free(imgdata);
 		return ret;
@@ -413,8 +412,8 @@ static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
 	return 0;
 }
 
-static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
-		size_t len)
+static int nand_imls_fitimage(struct mtd_info *mtd, int nand_dev, loff_t off,
+			      size_t len)
 {
 	void *imgdata;
 	int ret;
@@ -427,8 +426,7 @@ static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
 		return -ENOMEM;
 	}
 
-	ret = nand_read_skip_bad(nand, off, &len,
-			imgdata);
+	ret = nand_read_skip_bad(mtd, off, &len, imgdata);
 	if (ret < 0 && ret != -EUCLEAN) {
 		free(imgdata);
 		return ret;
@@ -449,7 +447,7 @@ static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
 
 static int do_imls_nand(void)
 {
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 	int nand_dev = nand_curr_device;
 	size_t len;
 	loff_t off;
@@ -463,20 +461,20 @@ static int do_imls_nand(void)
 	printf("\n");
 
 	for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
-		nand = &nand_info[nand_dev];
-		if (!nand->name || !nand->size)
+		mtd = &nand_info[nand_dev];
+		if (!mtd->name || !mtd->size)
 			continue;
 
-		for (off = 0; off < nand->size; off += nand->erasesize) {
+		for (off = 0; off < mtd->size; off += mtd->erasesize) {
 			const image_header_t *header;
 			int ret;
 
-			if (nand_block_isbad(nand, off))
+			if (nand_block_isbad(mtd, off))
 				continue;
 
 			len = sizeof(buffer);
 
-			ret = nand_read(nand, off, &len, (u8 *)buffer);
+			ret = nand_read(mtd, off, &len, (u8 *)buffer);
 			if (ret < 0 && ret != -EUCLEAN) {
 				printf("NAND read error %d at offset %08llX\n",
 						ret, off);
@@ -489,13 +487,13 @@ static int do_imls_nand(void)
 				header = (const image_header_t *)buffer;
 
 				len = image_get_image_size(header);
-				nand_imls_legacyimage(nand, nand_dev, off, len);
+				nand_imls_legacyimage(mtd, nand_dev, off, len);
 				break;
 #endif
 #if defined(CONFIG_FIT)
 			case IMAGE_FORMAT_FIT:
 				len = fit_get_size(buffer);
-				nand_imls_fitimage(nand, nand_dev, off, len);
+				nand_imls_fitimage(mtd, nand_dev, off, len);
 				break;
 #endif
 			}
diff --git a/cmd/jffs2.c b/cmd/jffs2.c
index 0b2eefa..e4eaa48 100644
--- a/cmd/jffs2.c
+++ b/cmd/jffs2.c
@@ -242,11 +242,11 @@ static int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *d
 static inline u32 get_part_sector_size_nand(struct mtdids *id)
 {
 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 
-	nand = &nand_info[id->num];
+	mtd = &nand_info[id->num];
 
-	return nand->erasesize;
+	return mtd->erasesize;
 #else
 	BUG();
 	return 0;
diff --git a/cmd/nand.c b/cmd/nand.c
index a6b67e2..0439607 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -38,7 +38,8 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
 		      u8 *part_num, struct part_info **part);
 #endif
 
-static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
+static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob,
+		     int repeat)
 {
 	int i;
 	u_char *datbuf, *oobbuf, *p;
@@ -46,32 +47,32 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	int ret = 0;
 
 	if (repeat)
-		off = last + nand->writesize;
+		off = last + mtd->writesize;
 
 	last = off;
 
-	datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+	datbuf = memalign(ARCH_DMA_MINALIGN, mtd->writesize);
 	if (!datbuf) {
 		puts("No memory for page buffer\n");
 		return 1;
 	}
 
-	oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
+	oobbuf = memalign(ARCH_DMA_MINALIGN, mtd->oobsize);
 	if (!oobbuf) {
 		puts("No memory for page buffer\n");
 		ret = 1;
 		goto free_dat;
 	}
-	off &= ~(nand->writesize - 1);
+	off &= ~(mtd->writesize - 1);
 	loff_t addr = (loff_t) off;
 	struct mtd_oob_ops ops;
 	memset(&ops, 0, sizeof(ops));
 	ops.datbuf = datbuf;
 	ops.oobbuf = oobbuf;
-	ops.len = nand->writesize;
-	ops.ooblen = nand->oobsize;
+	ops.len = mtd->writesize;
+	ops.ooblen = mtd->oobsize;
 	ops.mode = MTD_OPS_RAW;
-	i = mtd_read_oob(nand, addr, &ops);
+	i = mtd_read_oob(mtd, addr, &ops);
 	if (i < 0) {
 		printf("Error (%d) reading page %08lx\n", i, off);
 		ret = 1;
@@ -80,7 +81,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	printf("Page %08lx dump:\n", off);
 
 	if (!only_oob) {
-		i = nand->writesize >> 4;
+		i = mtd->writesize >> 4;
 		p = datbuf;
 
 		while (i--) {
@@ -94,7 +95,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	}
 
 	puts("OOB:\n");
-	i = nand->oobsize >> 3;
+	i = mtd->oobsize >> 3;
 	p = oobbuf;
 	while (i--) {
 		printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
@@ -152,32 +153,32 @@ static void print_status(ulong start, ulong end, ulong erasesize, int status)
 		((status & NAND_LOCK_STATUS_UNLOCK) ?  "UNLOCK " : ""));
 }
 
-static void do_nand_status(nand_info_t *nand)
+static void do_nand_status(struct mtd_info *mtd)
 {
 	ulong block_start = 0;
 	ulong off;
 	int last_status = -1;
 
-	struct nand_chip *nand_chip = nand->priv;
+	struct nand_chip *nand_chip = mtd->priv;
 	/* check the WP bit */
-	nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1);
+	nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 	printf("device is %swrite protected\n",
-		(nand_chip->read_byte(nand) & 0x80 ?
-		"NOT " : ""));
+		(nand_chip->read_byte(mtd) & 0x80 ?
+		 "NOT " : ""));
 
-	for (off = 0; off < nand->size; off += nand->erasesize) {
-		int s = nand_get_lock_status(nand, off);
+	for (off = 0; off < mtd->size; off += mtd->erasesize) {
+		int s = nand_get_lock_status(mtd, off);
 
 		/* print message only if status has changed */
 		if (s != last_status && off != 0) {
-			print_status(block_start, off, nand->erasesize,
+			print_status(block_start, off, mtd->erasesize,
 					last_status);
 			block_start = off;
 		}
 		last_status = s;
 	}
 	/* Print the last block info */
-	print_status(block_start, off, nand->erasesize, last_status);
+	print_status(block_start, off, mtd->erasesize, last_status);
 }
 #endif
 
@@ -188,10 +189,10 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 {
 	int ret;
 	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
-	nand_info_t *nand = &nand_info[0];
+	struct mtd_info *mtd = &nand_info[0];
 	char *cmd = argv[1];
 
-	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
+	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) {
 		puts("no devices available\n");
 		return 1;
 	}
@@ -199,7 +200,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 	set_dev(0);
 
 	if (!strcmp(cmd, "get")) {
-		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		ret = get_nand_env_oob(mtd, &nand_env_oob_offset);
 		if (ret)
 			return 1;
 
@@ -229,15 +230,15 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 			return 1;
 		}
 
-		if (nand->oobavail < ENV_OFFSET_SIZE) {
+		if (mtd->oobavail < ENV_OFFSET_SIZE) {
 			printf("Insufficient available OOB bytes:\n"
 			       "%d OOB bytes available but %d required for "
 			       "env.oob support\n",
-			       nand->oobavail, ENV_OFFSET_SIZE);
+			       mtd->oobavail, ENV_OFFSET_SIZE);
 			return 1;
 		}
 
-		if ((addr & (nand->erasesize - 1)) != 0) {
+		if ((addr & (mtd->erasesize - 1)) != 0) {
 			printf("Environment offset must be block-aligned\n");
 			return 1;
 		}
@@ -249,15 +250,15 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 		ops.oobbuf = (void *) oob_buf;
 
 		oob_buf[0] = ENV_OOB_MARKER;
-		oob_buf[1] = addr / nand->erasesize;
+		oob_buf[1] = addr / mtd->erasesize;
 
-		ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+		ret = mtd->write_oob(mtd, ENV_OFFSET_SIZE, &ops);
 		if (ret) {
 			printf("Error writing OOB block 0\n");
 			return ret;
 		}
 
-		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		ret = get_nand_env_oob(mtd, &nand_env_oob_offset);
 		if (ret) {
 			printf("Error reading env offset in OOB\n");
 			return ret;
@@ -283,29 +284,29 @@ usage:
 
 static void nand_print_and_set_info(int idx)
 {
-	nand_info_t *nand = &nand_info[idx];
-	struct nand_chip *chip = nand->priv;
+	struct mtd_info *mtd = &nand_info[idx];
+	struct nand_chip *chip = mtd->priv;
 
 	printf("Device %d: ", idx);
 	if (chip->numchips > 1)
 		printf("%dx ", chip->numchips);
 	printf("%s, sector size %u KiB\n",
-	       nand->name, nand->erasesize >> 10);
-	printf("  Page size   %8d b\n", nand->writesize);
-	printf("  OOB size    %8d b\n", nand->oobsize);
-	printf("  Erase size  %8d b\n", nand->erasesize);
+	       mtd->name, mtd->erasesize >> 10);
+	printf("  Page size   %8d b\n", mtd->writesize);
+	printf("  OOB size    %8d b\n", mtd->oobsize);
+	printf("  Erase size  %8d b\n", mtd->erasesize);
 	printf("  subpagesize %8d b\n", chip->subpagesize);
 	printf("  options     0x%8x\n", chip->options);
 	printf("  bbt options 0x%8x\n", chip->bbt_options);
 
 	/* Set geometry info */
-	setenv_hex("nand_writesize", nand->writesize);
-	setenv_hex("nand_oobsize", nand->oobsize);
-	setenv_hex("nand_erasesize", nand->erasesize);
+	setenv_hex("nand_writesize", mtd->writesize);
+	setenv_hex("nand_oobsize", mtd->oobsize);
+	setenv_hex("nand_erasesize", mtd->erasesize);
 }
 
-static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
-			int read)
+static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
+		      ulong count, int read)
 {
 	int ret = 0;
 
@@ -313,18 +314,18 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
 		/* Raw access */
 		mtd_oob_ops_t ops = {
 			.datbuf = (u8 *)addr,
-			.oobbuf = ((u8 *)addr) + nand->writesize,
-			.len = nand->writesize,
-			.ooblen = nand->oobsize,
+			.oobbuf = ((u8 *)addr) + mtd->writesize,
+			.len = mtd->writesize,
+			.ooblen = mtd->oobsize,
 			.mode = MTD_OPS_RAW
 		};
 
 		if (read) {
-			ret = mtd_read_oob(nand, off, &ops);
+			ret = mtd_read_oob(mtd, off, &ops);
 		} else {
-			ret = mtd_write_oob(nand, off, &ops);
+			ret = mtd_write_oob(mtd, off, &ops);
 			if (!ret)
-				ret = nand_verify_page_oob(nand, &ops, off);
+				ret = nand_verify_page_oob(mtd, &ops, off);
 		}
 
 		if (ret) {
@@ -333,8 +334,8 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
 			break;
 		}
 
-		addr += nand->writesize + nand->oobsize;
-		off += nand->writesize;
+		addr += mtd->writesize + mtd->oobsize;
+		off += mtd->writesize;
 	}
 
 	return ret;
@@ -348,18 +349,18 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev)
 	/* We grab the nand info object here fresh because this is usually
 	 * called after arg_off_size() which can change the value of dev.
 	 */
-	nand_info_t *nand = &nand_info[dev];
+	struct mtd_info *mtd = &nand_info[dev];
 	loff_t maxoffset = offset + *size;
 	int badblocks = 0;
 
 	/* count badblocks in NAND from offset to offset + size */
-	for (; offset < maxoffset; offset += nand->erasesize) {
-		if (nand_block_isbad(nand, offset))
+	for (; offset < maxoffset; offset += mtd->erasesize) {
+		if (nand_block_isbad(mtd, offset))
 			badblocks++;
 	}
 	/* adjust size if any bad blocks found */
 	if (badblocks) {
-		*size -= badblocks * nand->erasesize;
+		*size -= badblocks * mtd->erasesize;
 		printf("size adjusted to 0x%llx (%d bad blocks)\n",
 		       (unsigned long long)*size, badblocks);
 	}
@@ -371,7 +372,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	ulong addr;
 	loff_t off, size, maxsize;
 	char *cmd, *s;
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 #ifdef CONFIG_SYS_NAND_QUIET
 	int quiet = CONFIG_SYS_NAND_QUIET;
 #else
@@ -437,12 +438,12 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		puts("\nno devices available\n");
 		return 1;
 	}
-	nand = &nand_info[dev];
+	mtd = &nand_info[dev];
 
 	if (strcmp(cmd, "bad") == 0) {
 		printf("\nDevice %d bad blocks:\n", dev);
-		for (off = 0; off < nand->size; off += nand->erasesize)
-			if (nand_block_isbad(nand, off))
+		for (off = 0; off < mtd->size; off += mtd->erasesize)
+			if (nand_block_isbad(mtd, off))
 				printf("  %08llx\n", (unsigned long long)off);
 		return 0;
 	}
@@ -502,7 +503,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if (set_dev(dev))
 			return 1;
 
-		nand = &nand_info[dev];
+		mtd = &nand_info[dev];
 
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = off;
@@ -524,7 +525,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				}
 			}
 		}
-		ret = nand_erase_opts(nand, &opts);
+		ret = nand_erase_opts(mtd, &opts);
 		printf("%s\n", ret ? "ERROR" : "OK");
 
 		return ret == 0 ? 0 : 1;
@@ -535,7 +536,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			goto usage;
 
 		off = (int)simple_strtoul(argv[2], NULL, 16);
-		ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
+		ret = nand_dump(mtd, off, !strcmp(&cmd[4], ".oob"), repeat);
 
 		return ret == 0 ? 1 : 0;
 	}
@@ -567,19 +568,19 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			if (set_dev(dev))
 				return 1;
 
-			nand = &nand_info[dev];
+			mtd = &nand_info[dev];
 
 			if (argc > 4 && !str2long(argv[4], &pagecount)) {
 				printf("'%s' is not a number\n", argv[4]);
 				return 1;
 			}
 
-			if (pagecount * nand->writesize > size) {
+			if (pagecount * mtd->writesize > size) {
 				puts("Size exceeds partition or device limit\n");
 				return -1;
 			}
 
-			rwsize = pagecount * (nand->writesize + nand->oobsize);
+			rwsize = pagecount * (mtd->writesize + mtd->oobsize);
 		} else {
 			if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
 					     &size, &maxsize,
@@ -596,16 +597,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			rwsize = size;
 		}
 
-		nand = &nand_info[dev];
+		mtd = &nand_info[dev];
 
 		if (!s || !strcmp(s, ".jffs2") ||
 		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
 			if (read)
-				ret = nand_read_skip_bad(nand, off, &rwsize,
+				ret = nand_read_skip_bad(mtd, off, &rwsize,
 							 NULL, maxsize,
 							 (u_char *)addr);
 			else
-				ret = nand_write_skip_bad(nand, off, &rwsize,
+				ret = nand_write_skip_bad(mtd, off, &rwsize,
 							  NULL, maxsize,
 							  (u_char *)addr,
 							  WITH_WR_VERIFY);
@@ -615,7 +616,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				printf("Unknown nand command suffix '%s'\n", s);
 				return 1;
 			}
-			ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
+			ret = nand_write_skip_bad(mtd, off, &rwsize, NULL,
 						maxsize, (u_char *)addr,
 						WITH_DROP_FFS | WITH_WR_VERIFY);
 #endif
@@ -628,11 +629,11 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			};
 
 			if (read)
-				ret = mtd_read_oob(nand, off, &ops);
+				ret = mtd_read_oob(mtd, off, &ops);
 			else
-				ret = mtd_write_oob(nand, off, &ops);
+				ret = mtd_write_oob(mtd, off, &ops);
 		} else if (raw) {
-			ret = raw_access(nand, addr, off, pagecount, read);
+			ret = raw_access(mtd, addr, off, pagecount, read);
 		} else {
 			printf("Unknown nand command suffix '%s'.\n", s);
 			return 1;
@@ -655,8 +656,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		}
 
 		printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
-			dev, off, nand->erasesize);
-		ret = nand_torture(nand, off);
+			dev, off, mtd->erasesize);
+		ret = nand_torture(mtd, off);
 		printf(" %s\n", ret ? "Failed" : "Passed");
 
 		return ret == 0 ? 0 : 1;
@@ -673,7 +674,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		while (argc > 0) {
 			addr = simple_strtoul(*argv, NULL, 16);
 
-			if (mtd_block_markbad(nand, addr)) {
+			if (mtd_block_markbad(mtd, addr)) {
 				printf("block 0x%08lx NOT marked "
 					"as bad! ERROR %d\n",
 					addr, ret);
@@ -705,9 +706,9 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				status = 1;
 		}
 		if (status) {
-			do_nand_status(nand);
+			do_nand_status(mtd);
 		} else {
-			if (!nand_lock(nand, tight)) {
+			if (!nand_lock(mtd, tight)) {
 				puts("NAND flash successfully locked\n");
 			} else {
 				puts("Error locking NAND flash\n");
@@ -801,7 +802,7 @@ U_BOOT_CMD(
 	"NAND sub-system", nand_help_text
 );
 
-static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
+static int nand_load_image(cmd_tbl_t *cmdtp, struct mtd_info *mtd,
 			   ulong offset, ulong addr, char *cmd)
 {
 	int r;
@@ -822,11 +823,11 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 		return 1;
 	}
 
-	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
+	printf("\nLoading from %s, offset 0x%lx\n", mtd->name, offset);
 
-	cnt = nand->writesize;
-	r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size,
-			(u_char *)addr);
+	cnt = mtd->writesize;
+	r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size,
+			       (u_char *)addr);
 	if (r) {
 		puts("** Read error\n");
 		bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ);
@@ -860,8 +861,8 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 	}
 	bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
 
-	r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size,
-			(u_char *)addr);
+	r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size,
+			       (u_char *)addr);
 	if (r) {
 		puts("** Read error\n");
 		bootstage_error(BOOTSTAGE_ID_NAND_READ);
diff --git a/common/env_nand.c b/common/env_nand.c
index b32eeac..0debc2c 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -276,7 +276,7 @@ static int readenv(size_t offset, u_char *buf)
 #endif /* #if defined(CONFIG_SPL_BUILD) */
 
 #ifdef CONFIG_ENV_OFFSET_OOB
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result)
 {
 	struct mtd_oob_ops ops;
 	uint32_t oob_buf[ENV_OFFSET_SIZE / sizeof(uint32_t)];
@@ -288,14 +288,14 @@ int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
 	ops.ooblen	= ENV_OFFSET_SIZE;
 	ops.oobbuf	= (void *)oob_buf;
 
-	ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops);
+	ret = mtd->read_oob(mtd, ENV_OFFSET_SIZE, &ops);
 	if (ret) {
 		printf("error reading OOB block 0\n");
 		return ret;
 	}
 
 	if (oob_buf[0] == ENV_OOB_MARKER) {
-		*result = oob_buf[1] * nand->erasesize;
+		*result = oob_buf[1] * mtd->erasesize;
 	} else if (oob_buf[0] == ENV_OOB_MARKER_OLD) {
 		*result = oob_buf[1];
 	} else {
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 9ca8602..c770eff 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -19,7 +19,7 @@
 static char *response_str;
 
 struct fb_nand_sparse {
-	nand_info_t		*nand;
+	struct mtd_info		*nand;
 	struct part_info	*part;
 };
 
@@ -34,7 +34,7 @@ __weak int board_fastboot_write_partition_setup(char *name)
 }
 
 static int fb_nand_lookup(const char *partname, char *response,
-			  nand_info_t **nand,
+			  struct mtd_info **nand,
 			  struct part_info **part)
 {
 	struct mtd_device *dev;
@@ -62,12 +62,12 @@ static int fb_nand_lookup(const char *partname, char *response,
 		return -EINVAL;
 	}
 
-	*nand = &nand_info[dev->id->num];
+	*mtd = &nand_info[dev->id->num];
 
 	return 0;
 }
 
-static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
+static int _fb_nand_erase(struct mtd_info *mtd, struct part_info *part)
 {
 	nand_erase_options_t opts;
 	int ret;
@@ -80,7 +80,7 @@ static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
 	printf("Erasing blocks 0x%llx to 0x%llx\n",
 	       part->offset, part->offset + part->size);
 
-	ret = nand_erase_opts(nand, &opts);
+	ret = nand_erase_opts(mtd, &opts);
 	if (ret)
 		return ret;
 
@@ -90,7 +90,7 @@ static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
 	return 0;
 }
 
-static int _fb_nand_write(nand_info_t *nand, struct part_info *part,
+static int _fb_nand_write(struct mtd_info *mtd, struct part_info *part,
 			  void *buffer, unsigned int offset,
 			  unsigned int length, size_t *written)
 {
@@ -100,7 +100,7 @@ static int _fb_nand_write(nand_info_t *nand, struct part_info *part,
 	flags |= WITH_DROP_FFS;
 #endif
 
-	return nand_write_skip_bad(nand, offset, &length, written,
+	return nand_write_skip_bad(mtd, offset, &length, written,
 				   part->size - (offset - part->offset),
 				   buffer, flags);
 }
@@ -131,13 +131,13 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 			 char *response)
 {
 	struct part_info *part;
-	nand_info_t *nand = NULL;
+	struct mtd_info *mtd = NULL;
 	int ret;
 
 	/* initialize the response buffer */
 	response_str = response;
 
-	ret = fb_nand_lookup(partname, response, &nand, &part);
+	ret = fb_nand_lookup(partname, response, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
 		fastboot_fail(response_str, "invalid NAND device");
@@ -152,10 +152,10 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 		struct fb_nand_sparse sparse_priv;
 		sparse_storage_t sparse;
 
-		sparse_priv.nand = nand;
+		sparse_priv.nand = mtd;
 		sparse_priv.part = part;
 
-		sparse.block_sz = nand->writesize;
+		sparse.block_sz = mtd->writesize;
 		sparse.start = part->offset / sparse.block_sz;
 		sparse.size = part->size  / sparse.block_sz;
 		sparse.name = part->name;
@@ -167,7 +167,7 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 		printf("Flashing raw image at offset 0x%llx\n",
 		       part->offset);
 
-		ret = _fb_nand_write(nand, part, download_buffer, part->offset,
+		ret = _fb_nand_write(mtd, part, download_buffer, part->offset,
 				     download_bytes, NULL);
 
 		printf("........ wrote %u bytes to '%s'\n",
@@ -185,13 +185,13 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 void fb_nand_erase(const char *partname, char *response)
 {
 	struct part_info *part;
-	nand_info_t *nand = NULL;
+	struct mtd_info *mtd = NULL;
 	int ret;
 
 	/* initialize the response buffer */
 	response_str = response;
 
-	ret = fb_nand_lookup(partname, response, &nand, &part);
+	ret = fb_nand_lookup(partname, response, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
 		fastboot_fail(response_str, "invalid NAND device");
@@ -202,9 +202,9 @@ void fb_nand_erase(const char *partname, char *response)
 	if (ret)
 		return;
 
-	ret = _fb_nand_erase(nand, part);
+	ret = _fb_nand_erase(mtd, part);
 	if (ret) {
-		error("failed erasing from device %s", nand->name);
+		error("failed erasing from device %s", mtd->name);
 		fastboot_fail(response_str, "failed erasing from device");
 		return;
 	}
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index a975492..4652541 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -25,7 +25,7 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 	loff_t start, lim;
 	size_t count, actual;
 	int ret;
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 
 	/* if buf == NULL return total size of the area */
 	if (buf == NULL) {
@@ -44,11 +44,11 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 		return -1;
 	}
 
-	nand = &nand_info[nand_curr_device];
+	mtd = &nand_info[nand_curr_device];
 
 	if (op == DFU_OP_READ) {
-		ret = nand_read_skip_bad(nand, start, &count, &actual,
-				lim, buf);
+		ret = nand_read_skip_bad(mtd, start, &count, &actual,
+					 lim, buf);
 	} else {
 		nand_erase_options_t opts;
 
@@ -59,12 +59,12 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 		opts.quiet = 1;
 		opts.lim = lim;
 		/* first erase */
-		ret = nand_erase_opts(nand, &opts);
+		ret = nand_erase_opts(mtd, &opts);
 		if (ret)
 			return ret;
 		/* then write */
-		ret = nand_write_skip_bad(nand, start, &count, &actual,
-				lim, buf, WITH_WR_VERIFY);
+		ret = nand_write_skip_bad(mtd, start, &count, &actual,
+					  lim, buf, WITH_WR_VERIFY);
 	}
 
 	if (ret != 0) {
@@ -142,7 +142,7 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 
 	/* in case of ubi partition, erase rest of the partition */
 	if (dfu->data.nand.ubi) {
-		nand_info_t *nand;
+		struct mtd_info *mtd;
 		nand_erase_options_t opts;
 
 		if (nand_curr_device < 0 ||
@@ -152,14 +152,14 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 			return -1;
 		}
 
-		nand = &nand_info[nand_curr_device];
+		mtd = &nand_info[nand_curr_device];
 
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = dfu->data.nand.start + dfu->offset +
 				dfu->bad_skip;
 		opts.length = dfu->data.nand.start +
 				dfu->data.nand.size - opts.offset;
-		ret = nand_erase_opts(nand, &opts);
+		ret = nand_erase_opts(mtd, &opts);
 		if (ret != 0)
 			printf("Failure erase: %d\n", ret);
 	}
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index 31c7825..b8f68c0 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/nand_ecc.h>
 
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-nand_info_t nand_info[1];
+struct mtd_info nand_info[1];
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 7cc1de0..e6b3fe8 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1238,7 +1238,7 @@ static int at91_nand_ready(struct mtd_info *mtd)
 
 #ifdef CONFIG_SPL_BUILD
 /* The following code is for SPL */
-static nand_info_t mtd;
+static struct mtd_info mtd;
 static struct nand_chip nand_chip;
 
 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index 0e7c364..4d691d1 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -8,7 +8,7 @@
 #include <nand.h>
 #include <malloc.h>
 
-static nand_info_t mtd;
+static struct mtd_info mtd;
 static struct nand_chip nand_chip;
 
 static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 8f0a921..46f2654 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int nand_curr_device = -1;
 
 
-nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
 
 #ifndef CONFIG_SYS_NAND_SELF_INIT
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index e69f662..b3978e9 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -11,7 +11,7 @@
 #include <linux/mtd/nand_ecc.h>
 
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static nand_info_t mtd;
+static struct mtd_info mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 71285b6..90bf798 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -42,25 +42,26 @@ typedef struct mtd_info		mtd_info_t;
  * nand_erase_opts: - erase NAND flash with support for various options
  *		      (jffs2 formatting)
  *
- * @param meminfo	NAND device to erase
+ * @param mtd		nand mtd instance to erase
  * @param opts		options,  @see struct nand_erase_options
  * @return		0 in case of success
  *
  * This code is ported from flash_eraseall.c from Linux mtd utils by
  * Arcom Control System Ltd.
  */
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
+int nand_erase_opts(struct mtd_info *mtd,
+		    const nand_erase_options_t *opts)
 {
 	struct jffs2_unknown_node cleanmarker;
 	erase_info_t erase;
 	unsigned long erase_length, erased_length; /* in blocks */
 	int result;
 	int percent_complete = -1;
-	const char *mtd_device = meminfo->name;
+	const char *mtd_device = mtd->name;
 	struct mtd_oob_ops oob_opts;
-	struct nand_chip *chip = meminfo->priv;
+	struct nand_chip *chip = mtd->priv;
 
-	if ((opts->offset & (meminfo->erasesize - 1)) != 0) {
+	if ((opts->offset & (mtd->erasesize - 1)) != 0) {
 		printf("Attempt to erase non block-aligned data\n");
 		return -1;
 	}
@@ -68,11 +69,11 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 	memset(&erase, 0, sizeof(erase));
 	memset(&oob_opts, 0, sizeof(oob_opts));
 
-	erase.mtd = meminfo;
-	erase.len  = meminfo->erasesize;
+	erase.mtd = mtd;
+	erase.len = mtd->erasesize;
 	erase.addr = opts->offset;
-	erase_length = lldiv(opts->length + meminfo->erasesize - 1,
-			     meminfo->erasesize);
+	erase_length = lldiv(opts->length + mtd->erasesize - 1,
+			     mtd->erasesize);
 
 	cleanmarker.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK);
 	cleanmarker.nodetype = cpu_to_je16(JFFS2_NODETYPE_CLEANMARKER);
@@ -97,7 +98,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 
 	for (erased_length = 0;
 	     erased_length < erase_length;
-	     erase.addr += meminfo->erasesize) {
+	     erase.addr += mtd->erasesize) {
 
 		WATCHDOG_RESET();
 
@@ -106,7 +107,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			return -EFBIG;
 		}
 		if (!opts->scrub) {
-			int ret = mtd_block_isbad(meminfo, erase.addr);
+			int ret = mtd_block_isbad(mtd, erase.addr);
 			if (ret > 0) {
 				if (!opts->quiet)
 					printf("\rSkipping bad block at  "
@@ -129,7 +130,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 
 		erased_length++;
 
-		result = mtd_erase(meminfo, &erase);
+		result = mtd_erase(mtd, &erase);
 		if (result != 0) {
 			printf("\n%s: MTD Erase failure: %d\n",
 			       mtd_device, result);
@@ -145,9 +146,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			ops.ooboffs = 0;
 			ops.mode = MTD_OPS_AUTO_OOB;
 
-			result = mtd_write_oob(meminfo,
-						    erase.addr,
-						    &ops);
+			result = mtd_write_oob(mtd, erase.addr, &ops);
 			if (result != 0) {
 				printf("\n%s: MTD writeoob failure: %d\n",
 				       mtd_device, result);
@@ -303,7 +302,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
  * @param mtd		nand mtd instance
  * @param start		start byte address
  * @param length	number of bytes to unlock (must be a multiple of
- *			page size nand->writesize)
+ *			page size mtd->writesize)
  * @param allexcept	if set, unlock everything not selected
  *
  * @return		0 on success, -1 in case of error
@@ -399,7 +398,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
  * Check if there are any bad blocks, and whether length including bad
  * blocks fits into device
  *
- * @param nand NAND device
+ * @param mtd nand mtd instance
  * @param offset offset in flash
  * @param length image length
  * @param used length of flash needed for the requested length
@@ -407,8 +406,8 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
  *         1 if the image fits, but there are bad blocks
  *        -1 if the image does not fit
  */
-static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
-		size_t *used)
+static int check_skip_len(struct mtd_info *mtd, loff_t offset, size_t length,
+			  size_t *used)
 {
 	size_t len_excl_bad = 0;
 	int ret = 0;
@@ -417,14 +416,14 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
 		size_t block_len, block_off;
 		loff_t block_start;
 
-		if (offset >= nand->size)
+		if (offset >= mtd->size)
 			return -1;
 
-		block_start = offset & ~(loff_t)(nand->erasesize - 1);
-		block_off = offset & (nand->erasesize - 1);
-		block_len = nand->erasesize - block_off;
+		block_start = offset & ~(loff_t)(mtd->erasesize - 1);
+		block_off = offset & (mtd->erasesize - 1);
+		block_len = mtd->erasesize - block_off;
 
-		if (!nand_block_isbad(nand, block_start))
+		if (!nand_block_isbad(mtd, block_start))
 			len_excl_bad += block_len;
 		else
 			ret = 1;
@@ -441,7 +440,7 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
 }
 
 #ifdef CONFIG_CMD_NAND_TRIMFFS
-static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
+static size_t drop_ffs(const struct mtd_info *mtd, const u_char *buf,
 			const size_t *len)
 {
 	size_t l = *len;
@@ -453,8 +452,8 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
 
 	/* The resulting length must be aligned to the minimum flash I/O size */
 	l = i + 1;
-	l = (l + nand->writesize - 1) / nand->writesize;
-	l *=  nand->writesize;
+	l = (l + mtd->writesize - 1) / mtd->writesize;
+	l *=  mtd->writesize;
 
 	/*
 	 * since the input length may be unaligned, prevent access past the end
@@ -471,16 +470,17 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
  * Reads page of NAND and verifies the contents and OOB against the
  * values in ops.
  *
- * @param nand		NAND device
+ * @param mtd		nand mtd instance
  * @param ops		MTD operations, including data to verify
  * @param ofs		offset in flash
  * @return		0 in case of success
  */
-int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+			 loff_t ofs)
 {
 	int rval;
 	struct mtd_oob_ops vops;
-	size_t verlen = nand->writesize + nand->oobsize;
+	size_t verlen = mtd->writesize + mtd->oobsize;
 
 	memcpy(&vops, ops, sizeof(vops));
 
@@ -489,9 +489,9 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
 	if (!vops.datbuf)
 		return -ENOMEM;
 
-	vops.oobbuf = vops.datbuf + nand->writesize;
+	vops.oobbuf = vops.datbuf + mtd->writesize;
 
-	rval = mtd_read_oob(nand, ofs, &vops);
+	rval = mtd_read_oob(mtd, ofs, &vops);
 	if (!rval)
 		rval = memcmp(ops->datbuf, vops.datbuf, vops.len);
 	if (!rval)
@@ -510,17 +510,17 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
  * the contents of a buffer.  The offset into the NAND must be
  * page-aligned, and the function doesn't handle skipping bad blocks.
  *
- * @param nand		NAND device
+ * @param mtd		nand mtd instance
  * @param ofs		offset in flash
  * @param len		buffer length
  * @param buf		buffer to read from
  * @return		0 in case of success
  */
-int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf)
 {
 	int rval = 0;
 	size_t verofs;
-	size_t verlen = nand->writesize;
+	size_t verlen = mtd->writesize;
 	uint8_t *verbuf = memalign(ARCH_DMA_MINALIGN, verlen);
 
 	if (!verbuf)
@@ -529,8 +529,8 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
 	/* Read the NAND back in page-size groups to limit malloc size */
 	for (verofs = ofs; verofs < ofs + len;
 	     verofs += verlen, buf += verlen) {
-		verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs));
-		rval = nand_read(nand, verofs, &verlen, verbuf);
+		verlen = min(mtd->writesize, (uint32_t)(ofs + len - verofs));
+		rval = nand_read(mtd, verofs, &verlen, verbuf);
 		if (!rval || (rval == -EUCLEAN))
 			rval = memcmp(buf, verbuf, verlen);
 
@@ -558,7 +558,7 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
  * beyond the limit we are passed, length is set to 0 and actual is set
  * to the required length.
  *
- * @param nand  	NAND device
+ * @param mtd		nand mtd instance
  * @param offset	offset in flash
  * @param length	buffer length
  * @param actual	set to size required to write length worth of
@@ -569,8 +569,8 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
  * @param flags		flags modifying the behaviour of the write to NAND
  * @return		0 in case of success
  */
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-		size_t *actual, loff_t lim, u_char *buffer, int flags)
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+			size_t *actual, loff_t lim, u_char *buffer, int flags)
 {
 	int rval = 0, blocksize;
 	size_t left_to_write = *length;
@@ -581,7 +581,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	if (actual)
 		*actual = 0;
 
-	blocksize = nand->erasesize;
+	blocksize = mtd->erasesize;
 
 	/*
 	 * nand_write() handles unaligned, partial page writes.
@@ -594,13 +594,13 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	 * you should only start a block skipping access at a
 	 * partition boundary).  So don't try to handle that.
 	 */
-	if ((offset & (nand->writesize - 1)) != 0) {
+	if ((offset & (mtd->writesize - 1)) != 0) {
 		printf("Attempt to write non page-aligned data\n");
 		*length = 0;
 		return -EINVAL;
 	}
 
-	need_skip = check_skip_len(nand, offset, *length, &used_for_write);
+	need_skip = check_skip_len(mtd, offset, *length, &used_for_write);
 
 	if (actual)
 		*actual = used_for_write;
@@ -618,10 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	if (!need_skip && !(flags & WITH_DROP_FFS)) {
-		rval = nand_write(nand, offset, length, buffer);
+		rval = nand_write(mtd, offset, length, buffer);
 
 		if ((flags & WITH_WR_VERIFY) && !rval)
-			rval = nand_verify(nand, offset, *length, buffer);
+			rval = nand_verify(mtd, offset, *length, buffer);
 
 		if (rval == 0)
 			return 0;
@@ -633,15 +633,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	while (left_to_write > 0) {
-		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t block_offset = offset & (mtd->erasesize - 1);
 		size_t write_size, truncated_write_size;
 
 		WATCHDOG_RESET();
 
-		if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+		if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
 			printf("Skip bad block 0x%08llx\n",
-				offset & ~(nand->erasesize - 1));
-			offset += nand->erasesize - block_offset;
+				offset & ~(mtd->erasesize - 1));
+			offset += mtd->erasesize - block_offset;
 			continue;
 		}
 
@@ -653,15 +653,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		truncated_write_size = write_size;
 #ifdef CONFIG_CMD_NAND_TRIMFFS
 		if (flags & WITH_DROP_FFS)
-			truncated_write_size = drop_ffs(nand, p_buffer,
+			truncated_write_size = drop_ffs(mtd, p_buffer,
 					&write_size);
 #endif
 
-		rval = nand_write(nand, offset, &truncated_write_size,
+		rval = nand_write(mtd, offset, &truncated_write_size,
 				p_buffer);
 
 		if ((flags & WITH_WR_VERIFY) && !rval)
-			rval = nand_verify(nand, offset,
+			rval = nand_verify(mtd, offset,
 				truncated_write_size, p_buffer);
 
 		offset += write_size;
@@ -693,7 +693,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
  * the limit we are passed, length is set to 0 and actual is set to the
  * required length.
  *
- * @param nand NAND device
+ * @param mtd nand mtd instance
  * @param offset offset in flash
  * @param length buffer length, on return holds number of read bytes
  * @param actual set to size required to read length worth of buffer or 0
@@ -703,8 +703,8 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
  * @param buffer buffer to write to
  * @return 0 in case of success
  */
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-		size_t *actual, loff_t lim, u_char *buffer)
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+		       size_t *actual, loff_t lim, u_char *buffer)
 {
 	int rval;
 	size_t left_to_read = *length;
@@ -712,7 +712,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	u_char *p_buffer = buffer;
 	int need_skip;
 
-	if ((offset & (nand->writesize - 1)) != 0) {
+	if ((offset & (mtd->writesize - 1)) != 0) {
 		printf("Attempt to read non page-aligned data\n");
 		*length = 0;
 		if (actual)
@@ -720,7 +720,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		return -EINVAL;
 	}
 
-	need_skip = check_skip_len(nand, offset, *length, &used_for_read);
+	need_skip = check_skip_len(mtd, offset, *length, &used_for_read);
 
 	if (actual)
 		*actual = used_for_read;
@@ -738,7 +738,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	if (!need_skip) {
-		rval = nand_read(nand, offset, length, buffer);
+		rval = nand_read(mtd, offset, length, buffer);
 		if (!rval || rval == -EUCLEAN)
 			return 0;
 
@@ -749,24 +749,24 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	while (left_to_read > 0) {
-		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t block_offset = offset & (mtd->erasesize - 1);
 		size_t read_length;
 
 		WATCHDOG_RESET();
 
-		if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+		if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
 			printf("Skipping bad block 0x%08llx\n",
-				offset & ~(nand->erasesize - 1));
-			offset += nand->erasesize - block_offset;
+				offset & ~(mtd->erasesize - 1));
+			offset += mtd->erasesize - block_offset;
 			continue;
 		}
 
-		if (left_to_read < (nand->erasesize - block_offset))
+		if (left_to_read < (mtd->erasesize - block_offset))
 			read_length = left_to_read;
 		else
-			read_length = nand->erasesize - block_offset;
+			read_length = mtd->erasesize - block_offset;
 
-		rval = nand_read(nand, offset, &read_length, p_buffer);
+		rval = nand_read(mtd, offset, &read_length, p_buffer);
 		if (rval && rval != -EUCLEAN) {
 			printf("NAND read from offset %llx failed %d\n",
 				offset, rval);
@@ -812,57 +812,57 @@ static int check_pattern(const u_char *buf, u_char patt, int size)
  * This is useful to determine if a block that caused a write error is still
  * good or should be marked as bad.
  *
- * @param nand NAND device
+ * @param mtd nand mtd instance
  * @param offset offset in flash
  * @return 0 if the block is still good
  */
-int nand_torture(nand_info_t *nand, loff_t offset)
+int nand_torture(struct mtd_info *mtd, loff_t offset)
 {
 	u_char patterns[] = {0xa5, 0x5a, 0x00};
 	struct erase_info instr = {
 		.mtd = nand,
 		.addr = offset,
-		.len = nand->erasesize,
+		.len = mtd->erasesize,
 	};
 	size_t retlen;
 	int err, ret = -1, i, patt_count;
 	u_char *buf;
 
-	if ((offset & (nand->erasesize - 1)) != 0) {
+	if ((offset & (mtd->erasesize - 1)) != 0) {
 		puts("Attempt to torture a block at a non block-aligned offset\n");
 		return -EINVAL;
 	}
 
-	if (offset + nand->erasesize > nand->size) {
+	if (offset + mtd->erasesize > mtd->size) {
 		puts("Attempt to torture a block outside the flash area\n");
 		return -EINVAL;
 	}
 
 	patt_count = ARRAY_SIZE(patterns);
 
-	buf = malloc_cache_aligned(nand->erasesize);
+	buf = malloc_cache_aligned(mtd->erasesize);
 	if (buf == NULL) {
 		puts("Out of memory for erase block buffer\n");
 		return -ENOMEM;
 	}
 
 	for (i = 0; i < patt_count; i++) {
-		err = nand->erase(nand, &instr);
+		err = mtd->erase(mtd, &instr);
 		if (err) {
 			printf("%s: erase() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
 		/* Make sure the block contains only 0xff bytes */
-		err = nand->read(nand, offset, nand->erasesize, &retlen, buf);
-		if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
+		err = mtd->read(mtd, offset, mtd->erasesize, &retlen, buf);
+		if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
 			printf("%s: read() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = check_pattern(buf, 0xff, nand->erasesize);
+		err = check_pattern(buf, 0xff, mtd->erasesize);
 		if (!err) {
 			printf("Erased block at 0x%llx, but a non-0xff byte was found\n",
 				offset);
@@ -871,22 +871,22 @@ int nand_torture(nand_info_t *nand, loff_t offset)
 		}
 
 		/* Write a pattern and check it */
-		memset(buf, patterns[i], nand->erasesize);
-		err = nand->write(nand, offset, nand->erasesize, &retlen, buf);
-		if (err || retlen != nand->erasesize) {
+		memset(buf, patterns[i], mtd->erasesize);
+		err = mtd->write(mtd, offset, mtd->erasesize, &retlen, buf);
+		if (err || retlen != mtd->erasesize) {
 			printf("%s: write() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = nand->read(nand, offset, nand->erasesize, &retlen, buf);
-		if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
+		err = mtd->read(mtd, offset, mtd->erasesize, &retlen, buf);
+		if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
 			printf("%s: read() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = check_pattern(buf, patterns[i], nand->erasesize);
+		err = check_pattern(buf, patterns[i], mtd->erasesize);
 		if (!err) {
 			printf("Pattern 0x%.2x checking failed for block at "
 					"0x%llx\n", patterns[i], offset);
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
index 740f787..9b7af09 100644
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -23,7 +23,7 @@
 # define DEBUGF(fmt,args...)
 #endif
 
-static nand_info_t *nand;
+static struct mtd_info *mtd;
 
 /* Compression names */
 static char *compr_names[] = {
@@ -304,7 +304,7 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest,
 			len = sizeof(struct jffs2_raw_inode);
 			if (dest)
 				len += jNode->csize;
-			nand_read(nand, jNode->offset, &len, inode);
+			nand_read(mtd, jNode->offset, &len, inode);
 			/* ignore data behind latest known EOF */
 			if (inode->offset > totalSize)
 				continue;
@@ -450,7 +450,7 @@ dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i)
 
 	if(!d || !i) return -1;
 	len = d->nsize;
-	nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent),
+	nand_read(mtd, d->offset + sizeof(struct jffs2_raw_dirent),
 		  &len, &fname);
 	fname[d->nsize] = '\0';
 
@@ -592,7 +592,9 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
 		if (jNode->ino == jDirFoundIno) {
 			size_t len = jNode->csize;
-			nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp);
+			nand_read(mtd,
+				  jNode->offset + sizeof(struct jffs2_raw_inode),
+				  &len, &tmp);
 			tmp[jNode->csize] = '\0';
 			break;
 		}
@@ -760,14 +762,14 @@ dump_dirents(struct b_lists *pL)
 #endif
 
 static int
-jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf,
+jffs2_fill_scan_buf(struct mtd_info *mtd, unsigned char *buf,
 		    unsigned ofs, unsigned len)
 {
 	int ret;
 	unsigned olen;
 
 	olen = len;
-	ret = nand_read(nand, ofs, &olen, buf);
+	ret = nand_read(mtd, ofs, &olen, buf);
 	if (ret) {
 		printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret);
 		return ret;
@@ -794,7 +796,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 	u32 counterN = 0;
 
 	struct mtdids *id = part->dev->id;
-	nand = nand_info + id->num;
+	mtd = nand_info + id->num;
 
 	/* if we are building a list we need to refresh the cache. */
 	jffs_init_1pass_list(part);
@@ -802,7 +804,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 	pL->partOffset = part->offset;
 	puts ("Scanning JFFS2 FS:   ");
 
-	sectorsize = nand->erasesize;
+	sectorsize = mtd->erasesize;
 	nr_blocks = part->size / sectorsize;
 	buf = malloc(sectorsize);
 	if (!buf)
@@ -813,10 +815,10 @@ jffs2_1pass_build_lists(struct part_info * part)
 
 		offset = part->offset + i * sectorsize;
 
-		if (nand_block_isbad(nand, offset))
+		if (nand_block_isbad(mtd, offset))
 			continue;
 
-		if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE))
+		if (jffs2_fill_scan_buf(mtd, buf, offset, EMPTY_SCAN_SIZE))
 			return 0;
 
 		ofs = 0;
@@ -826,7 +828,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 		if (ofs == EMPTY_SCAN_SIZE)
 			continue;
 
-		if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
+		if (jffs2_fill_scan_buf(mtd, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
 			return 0;
 		offset += ofs;
 
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index 50000a1..5e99025 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -141,7 +141,7 @@ static const char *yaffs_error_str(void)
 	}
 }
 
-extern nand_info_t nand_info[];
+extern struct mtd_info nand_info[];
 
 void cmd_yaffs_tracemask(unsigned set, unsigned mask)
 {
diff --git a/include/nand.h b/include/nand.h
index 7cbbbd3..eb2d76d 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -40,27 +40,27 @@ int nand_register(int devnum);
 extern int board_nand_init(struct nand_chip *nand);
 #endif
 
-typedef struct mtd_info nand_info_t;
-
 extern int nand_curr_device;
-extern nand_info_t nand_info[];
+extern struct mtd_info nand_info[];
 
-static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
+			    u_char *buf)
 {
 	return mtd_read(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_write(struct mtd_info *info, loff_t ofs, size_t *len,
+			     u_char *buf)
 {
 	return mtd_write(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
+static inline int nand_block_isbad(struct mtd_info *info, loff_t ofs)
 {
 	return mtd_block_isbad(info, ofs);
 }
 
-static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
+static inline int nand_erase(struct mtd_info *info, loff_t off, size_t size)
 {
 	struct erase_info instr;
 
@@ -96,27 +96,28 @@ struct nand_erase_options {
 
 typedef struct nand_erase_options nand_erase_options_t;
 
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
 		       size_t *actual, loff_t lim, u_char *buffer);
 
 #define WITH_DROP_FFS	(1 << 0) /* drop trailing all-0xff pages */
 #define WITH_WR_VERIFY	(1 << 1) /* verify data was written correctly */
 
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
 			size_t *actual, loff_t lim, u_char *buffer, int flags);
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
-int nand_torture(nand_info_t *nand, loff_t offset);
-int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops,
-			loff_t ofs);
-int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf);
+int nand_erase_opts(struct mtd_info *mtd,
+		    const nand_erase_options_t *opts);
+int nand_torture(struct mtd_info *mtd, loff_t offset);
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+			 loff_t ofs);
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf);
 
 #define NAND_LOCK_STATUS_TIGHT	0x01
 #define NAND_LOCK_STATUS_UNLOCK 0x04
 
-int nand_lock(nand_info_t *meminfo, int tight);
-int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length,
-	int allexcept);
-int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
+int nand_lock(struct mtd_info *mtd, int tight);
+int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
+		int allexcept);
+int nand_get_lock_status(struct mtd_info *mtd, loff_t offset);
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
 void nand_deselect(void);
@@ -135,6 +136,6 @@ __attribute__((noreturn)) void nand_boot(void);
 #define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
 					stored as byte number */
 #define ENV_OFFSET_SIZE 8
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result);
 #endif
 int spl_nand_erase_one(int block, int page);
-- 
cgit v0.10.2


From b616d9b0a708eb90eb474e1b6ec6dfe4c48a1678 Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Mon, 30 May 2016 13:57:55 -0500
Subject: nand: Embed mtd_info in struct nand_chip

nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.

This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip.  It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].

Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index ce4acc1..e947e54 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -259,7 +259,7 @@ static int load_devicetree(void)
 	}
 #ifdef CONFIG_NAND
 	dtbsize = 0x20000;
-	rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize,
+	rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
 				NULL, 0x20000, (u_char *)dtbaddr);
 #else
 	char *dtbname = getenv("dtb");
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 7b7cd2c..6398bcb 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -212,7 +212,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index af68e10..04e5812 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -191,7 +191,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #ifndef CONFIG_SYS_NO_FLASH
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 4c64312..6871916 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -272,7 +272,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index d3555bb..fc4f50d 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -124,7 +124,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20);
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 9ef2864..994f246 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -151,7 +151,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index c14df30..b0d440d 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -196,7 +196,7 @@ void lcd_show_board_info(void)
 			dram_size += gd->bd->bi_dram[i].size;
 		nand_size = 0;
 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-			nand_size += nand_info[i].size;
+			nand_size += nand_info[i]->size;
 		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 			dram_size >> 20,
 			nand_size >> 20);
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index e8ee612..fa90270 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -207,7 +207,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index f4eef96..23ec274 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -191,7 +191,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index aee6217..72bad23 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -187,7 +187,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 3cc01cb..e2cb94e 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -194,7 +194,7 @@ void lcd_show_board_info(void)
 
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 276ff80..e9f9b67 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -293,7 +293,7 @@ void lcd_show_board_info(void)
 
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/cmd/bootm.c b/cmd/bootm.c
index 24f1054..f5e91f4 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -461,7 +461,7 @@ static int do_imls_nand(void)
 	printf("\n");
 
 	for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
-		mtd = &nand_info[nand_dev];
+		mtd = nand_info[nand_dev];
 		if (!mtd->name || !mtd->size)
 			continue;
 
diff --git a/cmd/jffs2.c b/cmd/jffs2.c
index e4eaa48..f00d53a 100644
--- a/cmd/jffs2.c
+++ b/cmd/jffs2.c
@@ -167,7 +167,7 @@ static int mtd_device_validate(u8 type, u8 num, u32 *size)
 	} else if (type == MTD_DEV_TYPE_NAND) {
 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
 		if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
-			*size = nand_info[num].size;
+			*size = nand_info[num]->size;
 			return 0;
 		}
 
@@ -244,7 +244,7 @@ static inline u32 get_part_sector_size_nand(struct mtdids *id)
 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
 	struct mtd_info *mtd;
 
-	mtd = &nand_info[id->num];
+	mtd = nand_info[id->num];
 
 	return mtd->erasesize;
 #else
diff --git a/cmd/nand.c b/cmd/nand.c
index 0439607..f1d5a11 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -116,7 +116,7 @@ free_dat:
 static int set_dev(int dev)
 {
 	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[dev].name) {
+	    !nand_info[dev]->name) {
 		puts("No such device\n");
 		return -1;
 	}
@@ -124,12 +124,12 @@ static int set_dev(int dev)
 	if (nand_curr_device == dev)
 		return 0;
 
-	printf("Device %d: %s", dev, nand_info[dev].name);
+	printf("Device %d: %s", dev, nand_info[dev]->name);
 	puts("... is now current device\n");
 	nand_curr_device = dev;
 
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
-	board_nand_select_device(nand_info[dev].priv, dev);
+	board_nand_select_device(nand_info[dev]->priv, dev);
 #endif
 
 	return 0;
@@ -189,7 +189,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 {
 	int ret;
 	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
-	struct mtd_info *mtd = &nand_info[0];
+	struct mtd_info *mtd = nand_info[0];
 	char *cmd = argv[1];
 
 	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) {
@@ -216,7 +216,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 
 		/* We don't care about size, or maxsize. */
 		if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
-				MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+				MTD_DEV_TYPE_NAND, nand_info[idx]->size)) {
 			puts("Offset or partition name expected\n");
 			return 1;
 		}
@@ -284,7 +284,7 @@ usage:
 
 static void nand_print_and_set_info(int idx)
 {
-	struct mtd_info *mtd = &nand_info[idx];
+	struct mtd_info *mtd = nand_info[idx];
 	struct nand_chip *chip = mtd->priv;
 
 	printf("Device %d: ", idx);
@@ -349,7 +349,7 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev)
 	/* We grab the nand info object here fresh because this is usually
 	 * called after arg_off_size() which can change the value of dev.
 	 */
-	struct mtd_info *mtd = &nand_info[dev];
+	struct mtd_info *mtd = nand_info[dev];
 	loff_t maxoffset = offset + *size;
 	int badblocks = 0;
 
@@ -399,7 +399,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		putc('\n');
 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
-			if (nand_info[i].name)
+			if (nand_info[i]->name)
 				nand_print_and_set_info(i);
 		}
 		return 0;
@@ -434,11 +434,11 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	 * for another device is to be used.
 	 */
 	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[dev].name) {
+	    !nand_info[dev]->name) {
 		puts("\nno devices available\n");
 		return 1;
 	}
-	mtd = &nand_info[dev];
+	mtd = nand_info[dev];
 
 	if (strcmp(cmd, "bad") == 0) {
 		printf("\nDevice %d bad blocks:\n", dev);
@@ -497,13 +497,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		/* skip first two or three arguments, look for offset and size */
 		if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
 				     &maxsize, MTD_DEV_TYPE_NAND,
-				     nand_info[dev].size) != 0)
+				     nand_info[dev]->size) != 0)
 			return 1;
 
 		if (set_dev(dev))
 			return 1;
 
-		mtd = &nand_info[dev];
+		mtd = nand_info[dev];
 
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = off;
@@ -562,13 +562,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 			if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
 					MTD_DEV_TYPE_NAND,
-					nand_info[dev].size))
+					nand_info[dev]->size))
 				return 1;
 
 			if (set_dev(dev))
 				return 1;
 
-			mtd = &nand_info[dev];
+			mtd = nand_info[dev];
 
 			if (argc > 4 && !str2long(argv[4], &pagecount)) {
 				printf("'%s' is not a number\n", argv[4]);
@@ -585,7 +585,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
 					     &size, &maxsize,
 					     MTD_DEV_TYPE_NAND,
-					     nand_info[dev].size) != 0)
+					     nand_info[dev]->size) != 0)
 				return 1;
 
 			if (set_dev(dev))
@@ -597,7 +597,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			rwsize = size;
 		}
 
-		mtd = &nand_info[dev];
+		mtd = nand_info[dev];
 
 		if (!s || !strcmp(s, ".jffs2") ||
 		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
@@ -728,13 +728,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
 				     &maxsize, MTD_DEV_TYPE_NAND,
-				     nand_info[dev].size) < 0)
+				     nand_info[dev]->size) < 0)
 			return 1;
 
 		if (set_dev(dev))
 			return 1;
 
-		if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
+		if (!nand_unlock(nand_info[dev], off, size, allexcept)) {
 			puts("NAND flash successfully unlocked\n");
 		} else {
 			puts("Error unlocking NAND flash, "
@@ -915,7 +915,7 @@ static int do_nandboot(cmd_tbl_t *cmdtp, int flag, int argc,
 				addr = simple_strtoul(argv[1], NULL, 16);
 			else
 				addr = CONFIG_SYS_LOAD_ADDR;
-			return nand_load_image(cmdtp, &nand_info[dev->id->num],
+			return nand_load_image(cmdtp, nand_info[dev->id->num],
 					       part->offset, addr, argv[0]);
 		}
 	}
@@ -958,14 +958,14 @@ usage:
 
 	idx = simple_strtoul(boot_device, NULL, 16);
 
-	if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
+	if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) {
 		printf("\n** Device %d not available\n", idx);
 		bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
 		return 1;
 	}
 	bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
 
-	return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
+	return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]);
 }
 
 U_BOOT_CMD(nboot, 4, 1, do_nandboot,
diff --git a/common/env_nand.c b/common/env_nand.c
index 0debc2c..fc99a5e 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -132,15 +132,15 @@ static int writeenv(size_t offset, u_char *buf)
 	size_t blocksize, len;
 	u_char *char_ptr;
 
-	blocksize = nand_info[0].erasesize;
+	blocksize = nand_info[0]->erasesize;
 	len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
 
 	while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
-		if (nand_block_isbad(&nand_info[0], offset)) {
+		if (nand_block_isbad(nand_info[0], offset)) {
 			offset += blocksize;
 		} else {
 			char_ptr = &buf[amount_saved];
-			if (nand_write(&nand_info[0], offset, &len, char_ptr))
+			if (nand_write(nand_info[0], offset, &len, char_ptr))
 				return 1;
 
 			offset += blocksize;
@@ -164,7 +164,7 @@ static int erase_and_write_env(const struct env_location *location,
 	int ret = 0;
 
 	printf("Erasing %s...\n", location->name);
-	if (nand_erase_opts(&nand_info[0], &location->erase_opts))
+	if (nand_erase_opts(nand_info[0], &location->erase_opts))
 		return 1;
 
 	printf("Writing to %s... ", location->name);
@@ -247,20 +247,20 @@ static int readenv(size_t offset, u_char *buf)
 	size_t blocksize, len;
 	u_char *char_ptr;
 
-	blocksize = nand_info[0].erasesize;
+	blocksize = nand_info[0]->erasesize;
 	if (!blocksize)
 		return 1;
 
 	len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
 
 	while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
-		if (nand_block_isbad(&nand_info[0], offset)) {
+		if (nand_block_isbad(nand_info[0], offset)) {
 			offset += blocksize;
 		} else {
 			char_ptr = &buf[amount_loaded];
-			if (nand_read_skip_bad(&nand_info[0], offset,
+			if (nand_read_skip_bad(nand_info[0], offset,
 					       &len, NULL,
-					       nand_info[0].size, char_ptr))
+					       nand_info[0]->size, char_ptr))
 				return 1;
 
 			offset += blocksize;
@@ -387,7 +387,7 @@ void env_relocate_spec(void)
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
 
 #if defined(CONFIG_ENV_OFFSET_OOB)
-	ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
+	ret = get_nand_env_oob(nand_info[0], &nand_env_oob_offset);
 	/*
 	 * If unable to read environment offset from NAND OOB then fall through
 	 * to the normal environment reading code below
diff --git a/common/fb_nand.c b/common/fb_nand.c
index c770eff..e55ea38 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -62,7 +62,7 @@ static int fb_nand_lookup(const char *partname, char *response,
 		return -EINVAL;
 	}
 
-	*mtd = &nand_info[dev->id->num];
+	*mtd = nand_info[dev->id->num];
 
 	return 0;
 }
diff --git a/common/splash_source.c b/common/splash_source.c
index a09dd4b..f86a78a 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -45,9 +45,9 @@ static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 #ifdef CONFIG_CMD_NAND
 static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 {
-	return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
+	return nand_read_skip_bad(nand_info[nand_curr_device], offset,
 				  &read_size, NULL,
-				  nand_info[nand_curr_device].size,
+				  nand_info[nand_curr_device]->size,
 				  (u_char *)bmp_load_addr);
 }
 #else
diff --git a/doc/README.nand b/doc/README.nand
index 545d88c..96ffc48 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -136,15 +136,8 @@ Configuration Options:
       Example of new init to be added to the end of an existing driver
       init:
 
-	/*
-	 * devnum is the device number to be used in nand commands
-	 * and in mtd->name.  Must be less than
-	 * CONFIG_SYS_NAND_MAX_DEVICE.
-	 */
-	mtd = &nand_info[devnum];
-
 	/* chip is struct nand_chip, and is now provided by the driver. */
-	mtd->priv = &chip;
+	mtd = &chip.mtd;
 
 	/*
 	 * Fill in appropriate values if this driver uses these fields,
@@ -165,7 +158,11 @@ Configuration Options:
 	if (nand_scan_tail(mtd))
 		error out
 
-	if (nand_register(devnum))
+	/*
+	 * devnum is the device number to be used in nand commands
+	 * and in mtd->name.  Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
+	 */
+	if (nand_register(devnum, mtd))
 		error out
 
       In addition to providing more flexibility to the driver, it reduces
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index 4652541..ab782be 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -39,12 +39,12 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+	    !nand_info[nand_curr_device]->name) {
 		printf("%s: invalid nand device\n", __func__);
 		return -1;
 	}
 
-	mtd = &nand_info[nand_curr_device];
+	mtd = nand_info[nand_curr_device];
 
 	if (op == DFU_OP_READ) {
 		ret = nand_read_skip_bad(mtd, start, &count, &actual,
@@ -147,12 +147,12 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 
 		if (nand_curr_device < 0 ||
 		    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-		    !nand_info[nand_curr_device].name) {
+		    !nand_info[nand_curr_device]->name) {
 			printf("%s: invalid nand device\n", __func__);
 			return -1;
 		}
 
-		mtd = &nand_info[nand_curr_device];
+		mtd = nand_info[nand_curr_device];
 
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = dfu->data.nand.start + dfu->offset +
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index b8f68c0..b280f87 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/nand_ecc.h>
 
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-struct mtd_info nand_info[1];
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
@@ -30,12 +30,12 @@ static struct nand_chip nand_chip;
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = nand_info[0].priv;
+	struct nand_chip *this = mtd->priv;
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (!this->dev_ready(&nand_info[0]))
+	while (!this->dev_ready(mtd))
 		;
 
 	/* Emulate NAND_CMD_READOOB */
@@ -45,11 +45,11 @@ static int nand_command(int block, int page, uint32_t offs,
 	}
 
 	/* Begin command latch cycle */
-	hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 
 	if (cmd == NAND_CMD_RESET) {
-		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-		while (!this->dev_ready(&nand_info[0]))
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		while (!this->dev_ready(mtd))
 			;
 		return 0;
 	}
@@ -60,39 +60,39 @@ static int nand_command(int block, int page, uint32_t offs,
 
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	hwctrl(&nand_info[0], offs & 0xff,
+	hwctrl(mtd, offs & 0xff,
 		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
-	hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
 	if (cmd != NAND_CMD_RNDOUT) {
-		hwctrl(&nand_info[0], (page_addr & 0xff),
+		hwctrl(mtd, (page_addr & 0xff),
 		       NAND_CTRL_ALE); /* A[19:12] */
-		hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+		hwctrl(mtd, ((page_addr >> 8) & 0xff),
 		       NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 		/* One more address cycle for devices > 128MiB */
-		hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+		hwctrl(mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
 	}
 
-	hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	if (cmd == NAND_CMD_READ0) {
 		/* Latch in address */
-		hwctrl(&nand_info[0], NAND_CMD_READSTART,
+		hwctrl(mtd, NAND_CMD_READSTART,
 			   NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 		/*
 		 * Wait a while for the data to be ready
 		 */
-		while (!this->dev_ready(&nand_info[0]))
+		while (!this->dev_ready(mtd))
 			;
 	} else if (cmd == NAND_CMD_RNDOUT) {
-		hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+		hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
 					NAND_CTRL_CHANGE);
-		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 	}
 
 	return 0;
@@ -100,7 +100,7 @@ static int nand_command(int block, int page, uint32_t offs,
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = nand_info[0].priv;
+	struct nand_chip *this = mtd->priv;
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		NAND_CMD_READOOB);
@@ -121,7 +121,7 @@ static int nand_is_bad_block(int block)
 
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = nand_info[0].priv;
+	struct nand_chip *this = mtd->priv;
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -137,15 +137,15 @@ static int nand_read_page(int block, int page, void *dst)
 	nand_command(block, page, 0, NAND_CMD_READ0);
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
+		this->ecc.hwctl(mtd, NAND_ECC_READ);
 		nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
 
-		this->read_buf(&nand_info[0], p, eccsize);
+		this->read_buf(mtd, p, eccsize);
 
 		nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
 
-		this->read_buf(&nand_info[0], oob, eccbytes);
-		this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
+		this->read_buf(mtd, oob, eccbytes);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 		data_pos += eccsize;
 		oob_pos += eccbytes;
@@ -164,7 +164,7 @@ static int nand_read_page(int block, int page, void *dst)
 		 * from correct_data(). We just hope that all possible errors
 		 * are corrected by this routine.
 		 */
-		this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 	}
 
 	return 0;
@@ -223,13 +223,13 @@ void nand_init(void)
 	/*
 	 * Init board specific nand support
 	 */
-	nand_info[0].priv = &nand_chip;
+	mtd = &nand_chip.mtd;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&nand_info[0], 0);
+		nand_chip.select_chip(mtd, 0);
 
 	/* NAND chip may require reset after power-on */
 	nand_command(0, 0, 0, NAND_CMD_RESET);
@@ -239,5 +239,5 @@ void nand_init(void)
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&nand_info[0], -1);
+		nand_chip.select_chip(mtd, -1);
 }
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index caa7982..8f0ae4c 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -1101,7 +1101,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 	}
 
 	nand->nand_base = arasan_nand_base;
-	mtd = &nand_info[0];
+	mtd = &nand_chip->mtd;
 	nand_chip->priv = nand;
 	mtd->priv = nand_chip;
 
@@ -1134,7 +1134,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 		goto fail;
 	}
 
-	if (nand_register(devnum)) {
+	if (nand_register(devnum, mtd)) {
 		printf("Nand Register Fail\n");
 		goto fail;
 	}
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index e6b3fe8..9c2cb44 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1238,17 +1238,17 @@ static int at91_nand_ready(struct mtd_info *mtd)
 
 #ifdef CONFIG_SPL_BUILD
 /* The following code is for SPL */
-static struct mtd_info mtd;
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	if (cmd == NAND_CMD_READOOB) {
@@ -1256,24 +1256,24 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 		cmd = NAND_CMD_READ0;
 	}
 
-	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 
 	if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
 		offs >>= 1;
 
-	hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+	hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+	hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+	hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
 #endif
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	return 0;
@@ -1281,7 +1281,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 
@@ -1304,7 +1304,7 @@ static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
 
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -1317,11 +1317,11 @@ static int nand_read_page(int block, int page, void *dst)
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		if (this->ecc.mode != NAND_ECC_SOFT)
-			this->ecc.hwctl(&mtd, NAND_ECC_READ);
-		this->read_buf(&mtd, p, eccsize);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+			this->ecc.hwctl(mtd, NAND_ECC_READ);
+		this->read_buf(mtd, p, eccsize);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
 	}
-	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 
 	for (i = 0; i < ECCTOTAL; i++)
 		ecc_code[i] = oob_data[nand_ecc_pos[i]];
@@ -1330,35 +1330,35 @@ static int nand_read_page(int block, int page, void *dst)
 	p = dst;
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 
 	return 0;
 }
 
 int spl_nand_erase_one(int block, int page)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 	int page_addr;
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(mtd, 0);
 
 	page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
-	hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	/* Row address */
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, ((page_addr >> 8) & 0xff),
 	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 	/* One more address cycle for devices > 128MiB */
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	hwctrl(mtd, (page_addr >> 16) & 0x0f,
 	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
 #endif
-	hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	nand_deselect();
@@ -1368,10 +1368,10 @@ int spl_nand_erase_one(int block, int page)
 #else
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 
 	nand_command(block, page, 0, NAND_CMD_READ0);
-	atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+	atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
 
 	return 0;
 }
@@ -1438,7 +1438,7 @@ int board_nand_init(struct nand_chip *nand)
 
 #ifdef CONFIG_ATMEL_NAND_HWECC
 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
-	ret = atmel_pmecc_nand_init_params(nand, &mtd);
+	ret = atmel_pmecc_nand_init_params(nand, mtd);
 #endif
 #endif
 
@@ -1447,9 +1447,10 @@ int board_nand_init(struct nand_chip *nand)
 
 void nand_init(void)
 {
-	mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
-	mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
-	mtd.priv = &nand_chip;
+	mtd = &nand_chip.mtd;
+	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
+	mtd->priv = &nand_chip;
 	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
@@ -1462,13 +1463,13 @@ void nand_init(void)
 #endif
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(mtd, 0);
 }
 
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, -1);
+		nand_chip.select_chip(mtd, -1);
 }
 
 #else
@@ -1482,8 +1483,8 @@ static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
 int atmel_nand_chip_init(int devnum, ulong base_addr)
 {
 	int ret;
-	struct mtd_info *mtd = &nand_info[devnum];
 	struct nand_chip *nand = &nand_chip[devnum];
+	struct mtd_info *mtd = &nand->mtd;
 
 	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
@@ -1521,7 +1522,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
 
 	ret = nand_scan_tail(mtd);
 	if (!ret)
-		nand_register(devnum);
+		nand_register(devnum, mtd);
 
 	return ret;
 }
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 5894fcc..13d10ae 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -1263,7 +1263,7 @@ static int denali_init(struct denali_nand_info *denali)
 		goto fail;
 	}
 
-	ret = nand_register(0);
+	ret = nand_register(0, denali->mtd);
 
 fail:
 	return ret;
@@ -1282,7 +1282,7 @@ static int __board_nand_init(void)
 	 * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
 	 * still provides a "struct mtd_info nand_info" instance.
 	 */
-	denali->mtd = &nand_info[0];
+	denali->mtd = &denali->nand.mtd;
 
 	/*
 	 * In the future, these base addresses should be taken from
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index d457d53..523aee3 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -656,7 +656,7 @@ static void fsl_elbc_ctrl_init(void)
 
 static int fsl_elbc_chip_init(int devnum, u8 *addr)
 {
-	struct mtd_info *mtd = &nand_info[devnum];
+	struct mtd_info *mtd;
 	struct nand_chip *nand;
 	struct fsl_elbc_mtd *priv;
 	uint32_t br = 0, or = 0;
@@ -697,6 +697,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand = &priv->chip;
+	mtd = &nand->mtd;
 	mtd->priv = nand;
 
 	elbc_ctrl->chips[priv->bank] = priv;
@@ -787,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	if (ret)
 		return ret;
 
-	ret = nand_register(devnum);
+	ret = nand_register(devnum, mtd);
 	if (ret)
 		return ret;
 
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 975b0d4..d5fd3ee 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -880,7 +880,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
 
 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 {
-	struct mtd_info *mtd = &nand_info[devnum];
+	struct mtd_info *mtd;
 	struct nand_chip *nand;
 	struct fsl_ifc_mtd *priv;
 	struct nand_ecclayout *layout;
@@ -925,6 +925,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand = &priv->chip;
+	mtd = &nand->mtd;
 	mtd->priv = nand;
 
 	ifc_ctrl->chips[priv->bank] = priv;
@@ -1044,7 +1045,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	if (ret)
 		return ret;
 
-	ret = nand_register(devnum);
+	ret = nand_register(devnum, mtd);
 	if (ret)
 		return ret;
 	return 0;
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index e0e9e1e..0b8b56f 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -409,7 +409,7 @@ int fsmc_nand_switch_ecc(uint32_t eccstrength)
 	 * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
 	 * function, as it doesn't need to switch to a different ECC layout.
 	 */
-	mtd = &nand_info[nand_curr_device];
+	mtd = nand_info[nand_curr_device];
 	nand = mtd->priv;
 
 	/* Setup the ecc configurations again */
@@ -443,7 +443,6 @@ int fsmc_nand_init(struct nand_chip *nand)
 {
 	static int chip_nr;
 	struct mtd_info *mtd;
-	int i;
 	u32 peripid2 = readl(&fsmc_regs_p->peripid2);
 
 	fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
@@ -480,7 +479,7 @@ int fsmc_nand_init(struct nand_chip *nand)
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	nand->badblockbits = 7;
 
-	mtd = &nand_info[chip_nr++];
+	mtd = &nand->mtd;
 	mtd->priv = nand;
 
 	switch (fsmc_version) {
@@ -514,9 +513,8 @@ int fsmc_nand_init(struct nand_chip *nand)
 	if (nand_scan_tail(mtd))
 		return -ENXIO;
 
-	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		if (nand_register(i))
-			return -ENXIO;
+	if (nand_register(chip_nr++, mtd))
+		return -ENXIO;
 
 	return 0;
 }
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index 8156fe9..236b0be 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -539,13 +539,11 @@ static struct nand_chip lpc32xx_chip;
 
 void board_nand_init(void)
 {
-	/* we have only one device anyway */
-	struct mtd_info *mtd = &nand_info[0];
-	/* chip is struct nand_chip, and is now provided by the driver. */
-	mtd->priv = &lpc32xx_chip;
-	/* to store return status in case we need to print it */
+	struct mtd_info *mtd = &lpc32xx_chip.mtd;
 	int ret;
 
+	mtd->priv = &lpc32xx_chip;
+
 	/* Set all BOARDSPECIFIC (actually core-specific) fields  */
 
 	lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
@@ -597,7 +595,7 @@ void board_nand_init(void)
 	}
 
 	/* chip is good, register it */
-	ret = nand_register(0);
+	ret = nand_register(0, mtd);
 	if (ret)
 		error("nand_register returned %i", ret);
 }
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index e621c36..d836130 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -549,7 +549,6 @@ int board_nand_init(struct nand_chip *chip)
 	int resettime = 0;
 	int retval = 0;
 	int rev;
-	static int chip_nr = 0;
 
 	/*
 	 * Check SoC revision. This driver supports only NFC
@@ -568,7 +567,7 @@ int board_nand_init(struct nand_chip *chip)
 		return -ENOMEM;
 	}
 
-	mtd = &nand_info[chip_nr++];
+	mtd = &chip->mtd;
 	mtd->priv = chip;
 	chip->priv = prv;
 
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index f12b07e..5e7b9cf 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1164,7 +1164,7 @@ int board_nand_init(struct nand_chip *this)
 #endif
 
 	/* structures must be linked */
-	mtd = &host->mtd;
+	mtd = &this->mtd;
 	mtd->priv = this;
 	host->nand = this;
 
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index 4d691d1..0b3a604 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -8,7 +8,7 @@
 #include <nand.h>
 #include <malloc.h>
 
-static struct mtd_info mtd;
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
@@ -147,14 +147,15 @@ static int mxs_nand_init(void)
 
 	/* init mxs nand driver */
 	board_nand_init(&nand_chip);
-	mtd.priv = &nand_chip;
+	mtd = &nand_chip.mtd;
+	mtd->priv = &nand_chip;
 	/* set mtd functions */
 	nand_chip.cmdfunc = mxs_nand_command;
 	nand_chip.numchips = 1;
 
 	/* identify flash device */
 	puts("NAND : ");
-	if (mxs_flash_ident(&mtd)) {
+	if (mxs_flash_ident(mtd)) {
 		printf("Failed to identify\n");
 		return -1;
 	}
@@ -162,12 +163,12 @@ static int mxs_nand_init(void)
 	/* allocate and initialize buffers */
 	nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
 				     sizeof(*nand_chip.buffers));
-	nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
+	nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize;
 	/* setup flash layout (does not scan as we override that) */
-	mtd.size = nand_chip.chipsize;
-	nand_chip.scan_bbt(&mtd);
+	mtd->size = nand_chip.chipsize;
+	nand_chip.scan_bbt(mtd);
 
-	printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
+	printf("%llu MiB\n", (mtd->size / (1024 * 1024)));
 	return 0;
 }
 
@@ -180,20 +181,20 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 
 	if (mxs_nand_init())
 		return -ENODEV;
-	chip = mtd.priv;
+	chip = mtd->priv;
 	page = offs >> chip->page_shift;
-	nand_page_per_block = mtd.erasesize / mtd.writesize;
+	nand_page_per_block = mtd->erasesize / mtd->writesize;
 
 	debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
 
-	size = roundup(size, mtd.writesize);
+	size = roundup(size, mtd->writesize);
 	while (sz < size) {
-		if (mxs_read_page_ecc(&mtd, buf, page) < 0)
+		if (mxs_read_page_ecc(mtd, buf, page) < 0)
 			return -1;
-		sz += mtd.writesize;
-		offs += mtd.writesize;
+		sz += mtd->writesize;
+		offs += mtd->writesize;
 		page++;
-		buf += mtd.writesize;
+		buf += mtd->writesize;
 
 		/*
 		 * Check if we have crossed a block boundary, and if so
@@ -204,10 +205,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 			 * Yes, new block. See if this block is good. If not,
 			 * loop until we find a good block.
 			 */
-			while (is_badblock(&mtd, offs, 1)) {
+			while (is_badblock(mtd, offs, 1)) {
 				page = page + nand_page_per_block;
 				/* Check i we've reached the end of flash. */
-				if (page >= mtd.size >> chip->page_shift)
+				if (page >= mtd->size >> chip->page_shift)
 					return -ENOMEM;
 			}
 		}
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 46f2654..ddd8249 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int nand_curr_device = -1;
 
 
-struct mtd_info nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
 
 #ifndef CONFIG_SYS_NAND_SELF_INIT
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -30,15 +30,25 @@ static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
 
 static unsigned long total_nand_size; /* in kiB */
 
-/* Register an initialized NAND mtd device with the U-Boot NAND command. */
-int nand_register(int devnum)
+int nand_mtd_to_devnum(struct mtd_info *mtd)
 {
-	struct mtd_info *mtd;
+	int i;
 
+	for (i = 0; i < ARRAY_SIZE(nand_info); i++) {
+		if (mtd && nand_info[i] == mtd)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+/* Register an initialized NAND mtd device with the U-Boot NAND command. */
+int nand_register(int devnum, struct mtd_info *mtd)
+{
 	if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
 		return -EINVAL;
 
-	mtd = &nand_info[devnum];
+	nand_info[devnum] = mtd;
 
 	sprintf(dev_name[devnum], "nand%d", devnum);
 	mtd->name = dev_name[devnum];
@@ -62,8 +72,8 @@ int nand_register(int devnum)
 #ifndef CONFIG_SYS_NAND_SELF_INIT
 static void nand_init_chip(int i)
 {
-	struct mtd_info *mtd = &nand_info[i];
 	struct nand_chip *nand = &nand_chip[i];
+	struct mtd_info *mtd = &nand->mtd;
 	ulong base_addr = base_address[i];
 	int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
 
@@ -79,7 +89,7 @@ static void nand_init_chip(int i)
 	if (nand_scan(mtd, maxchips))
 		return;
 
-	nand_register(i);
+	nand_register(i, mtd);
 }
 #endif
 
@@ -100,6 +110,7 @@ void nand_init(void)
 	/*
 	 * Select the chip in the board/cpu specific driver
 	 */
-	board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
+	board_nand_select_device(nand_info[nand_curr_device]->priv,
+				 nand_curr_device);
 #endif
 }
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index b3978e9..bc6a09a 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -11,7 +11,7 @@
 #include <linux/mtd/nand_ecc.h>
 
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static struct mtd_info mtd;
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
@@ -26,32 +26,32 @@ static struct nand_chip nand_chip;
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv();
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	/* Begin command latch cycle */
-	this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-	this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
-	this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
+	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
+	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
 		       NAND_CTRL_ALE); /* A[24:17] */
 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
 	/* One more address cycle for devices > 32MiB */
-	this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
+	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[28:25] */
 #endif
 	/* Latch in address */
-	this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
 	 * Wait a while for the data to be ready
 	 */
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	return 0;
@@ -63,12 +63,12 @@ static int nand_command(int block, int page, uint32_t offs,
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	/* Emulate NAND_CMD_READOOB */
@@ -82,30 +82,30 @@ static int nand_command(int block, int page, uint32_t offs,
 		offs >>= 1;
 
 	/* Begin command latch cycle */
-	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	hwctrl(&mtd, offs & 0xff,
-		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
-	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+	hwctrl(mtd, offs & 0xff,
+		    NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
-		       NAND_CTRL_ALE); /* A[27:20] */
+	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+	hwctrl(mtd, ((page_addr >> 8) & 0xff),
+		    NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 	/* One more address cycle for devices > 128MiB */
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	hwctrl(mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
 	/* Latch in address */
-	hwctrl(&mtd, NAND_CMD_READSTART,
-		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_READSTART,
+		    NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
 	 * Wait a while for the data to be ready
 	 */
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	return 0;
@@ -114,7 +114,7 @@ static int nand_command(int block, int page, uint32_t offs,
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	u_char bb_data[2];
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -124,11 +124,11 @@ static int nand_is_bad_block(int block)
 	 * Read one byte (or two if it's a 16 bit chip).
 	 */
 	if (this->options & NAND_BUSWIDTH_16) {
-		this->read_buf(&mtd, bb_data, 2);
+		this->read_buf(mtd, bb_data, 2);
 		if (bb_data[0] != 0xff || bb_data[1] != 0xff)
 			return 1;
 	} else {
-		this->read_buf(&mtd, bb_data, 1);
+		this->read_buf(mtd, bb_data, 1);
 		if (bb_data[0] != 0xff)
 			return 1;
 	}
@@ -139,7 +139,7 @@ static int nand_is_bad_block(int block)
 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
 static int nand_read_page(int block, int page, uchar *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -150,7 +150,7 @@ static int nand_read_page(int block, int page, uchar *dst)
 	uint8_t *p = dst;
 
 	nand_command(block, page, 0, NAND_CMD_READOOB);
-	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 	nand_command(block, page, 0, NAND_CMD_READ0);
 
 	/* Pick the ECC bytes out of the oob data */
@@ -159,10 +159,10 @@ static int nand_read_page(int block, int page, uchar *dst)
 
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		this->ecc.hwctl(&mtd, NAND_ECC_READ);
-		this->read_buf(&mtd, p, eccsize);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.hwctl(mtd, NAND_ECC_READ);
+		this->read_buf(mtd, p, eccsize);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 	}
 
 	return 0;
@@ -170,7 +170,7 @@ static int nand_read_page(int block, int page, uchar *dst)
 #else
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd->priv;
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -184,11 +184,11 @@ static int nand_read_page(int block, int page, void *dst)
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		if (this->ecc.mode != NAND_ECC_SOFT)
-			this->ecc.hwctl(&mtd, NAND_ECC_READ);
-		this->read_buf(&mtd, p, eccsize);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+			this->ecc.hwctl(mtd, NAND_ECC_READ);
+		this->read_buf(mtd, p, eccsize);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
 	}
-	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 
 	/* Pick the ECC bytes out of the oob data */
 	for (i = 0; i < ECCTOTAL; i++)
@@ -202,7 +202,7 @@ static int nand_read_page(int block, int page, void *dst)
 		 * from correct_data(). We just hope that all possible errors
 		 * are corrected by this routine.
 		 */
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 	}
 
 	return 0;
@@ -249,7 +249,8 @@ void nand_init(void)
 	/*
 	 * Init board specific nand support
 	 */
-	mtd.priv = &nand_chip;
+	mtd = &nand_chip.mtd;
+	mtd->priv = &nand_chip;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
@@ -262,12 +263,12 @@ void nand_init(void)
 #endif
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(mtd, 0);
 }
 
 /* Unselect after operation */
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, -1);
+		nand_chip.select_chip(mtd, -1);
 }
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 6a45d28..f2ee90e 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -898,12 +898,12 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+	    !nand_info[nand_curr_device]->name) {
 		printf("nand: error: no NAND devices found\n");
 		return -ENODEV;
 	}
 
-	mtd = &nand_info[nand_curr_device];
+	mtd = nand_info[nand_curr_device];
 	nand = mtd->priv;
 	nand->options |= NAND_OWN_BUFFERS;
 	nand->options &= ~NAND_SUBPAGE_READ;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d529467..125dbe7 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1477,9 +1477,9 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
 
 	info->variant = pxa3xx_nand_get_variant();
 	for (cs = 0; cs < pdata->num_cs; cs++) {
-		mtd = &nand_info[cs];
 		chip = (struct nand_chip *)
 			((u8 *)&info[1] + sizeof(*host) * cs);
+		mtd = &chip->mtd;
 		host = (struct pxa3xx_nand_host *)chip;
 		info->host[cs] = host;
 		host->mtd = mtd;
@@ -1573,8 +1573,10 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
 			continue;
 		}
 
-		if (!ret)
-			probe_success = 1;
+		if (nand_register(cs, mtd))
+			continue;
+
+		probe_success = 1;
 	}
 
 	if (!probe_success)
@@ -1601,6 +1603,4 @@ void board_nand_init(void)
 	ret = pxa3xx_nand_probe(info);
 	if (ret)
 		return;
-
-	nand_register(0);
 }
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index a77db7b..b20fb1e 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -976,7 +976,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 
 	dm_gpio_set_value(&config->wp_gpio, 1);
 
-	our_mtd = &nand_info[devnum];
+	our_mtd = &nand->mtd;
 	our_mtd->priv = nand;
 	ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 	if (ret)
@@ -989,7 +989,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 	if (ret)
 		return ret;
 
-	ret = nand_register(devnum);
+	ret = nand_register(devnum, our_mtd);
 	if (ret)
 		return ret;
 
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 1faec5e..3be8b02 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -630,7 +630,7 @@ struct vf610_nfc_config {
 
 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 {
-	struct mtd_info *mtd = &nand_info[devnum];
+	struct mtd_info *mtd;
 	struct nand_chip *chip;
 	struct vf610_nfc *nfc;
 	int err = 0;
@@ -653,6 +653,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 	chip = &nfc->chip;
 	nfc->regs = addr;
 
+	mtd = &chip->mtd;
 	mtd->priv = chip;
 	chip->priv = nfc;
 
@@ -753,7 +754,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 	if (err)
 		return err;
 
-	err = nand_register(devnum);
+	err = nand_register(devnum, mtd);
 	if (err)
 		return err;
 
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index e2a8ed3..00cdfd4 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -360,7 +360,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
 	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 
-	rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+	rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
 		       &fw_length, (u_char *)addr);
 	if (rc == -EUCLEAN) {
 		printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index f975fd8..fd130d5 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -139,8 +139,8 @@ void cs4340_upload_firmware(struct phy_device *phydev)
 	size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 
 	addr = malloc(CONFIG_CORTINA_FW_LENGTH);
-	ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
-		       &fw_length, (u_char *)addr);
+	ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
+			&fw_length, (u_char *)addr);
 	if (ret == -EUCLEAN) {
 		printf("NAND read of Cortina firmware at 0x%x failed %d\n",
 		       CONFIG_CORTINA_FW_ADDR, ret);
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index ba038b1..f771e94 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -195,7 +195,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
 			}
 
 			retlen = NAND_CACHE_SIZE;
-			if (nand_read(&nand_info[id->num], nand_cache_off,
+			if (nand_read(nand_info[id->num], nand_cache_off,
 						&retlen, nand_cache) != 0 ||
 					retlen != NAND_CACHE_SIZE) {
 				printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
index 9b7af09..d94c48f 100644
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -796,7 +796,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 	u32 counterN = 0;
 
 	struct mtdids *id = part->dev->id;
-	mtd = nand_info + id->num;
+	mtd = nand_info[id->num];
 
 	/* if we are building a list we need to refresh the cache. */
 	jffs_init_1pass_list(part);
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index 5e99025..6d86871 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -141,8 +141,6 @@ static const char *yaffs_error_str(void)
 	}
 }
 
-extern struct mtd_info nand_info[];
-
 void cmd_yaffs_tracemask(unsigned set, unsigned mask)
 {
 	if (set)
@@ -171,7 +169,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev,
 	dev = calloc(1, sizeof(*dev));
 	mp = strdup(_mp);
 
-	mtd = &nand_info[flash_dev];
+	mtd = nand_info[flash_dev];
 
 	if (!dev || !mp) {
 		/* Alloc error */
@@ -260,9 +258,7 @@ void cmd_yaffs_dev_ls(void)
 		dev = yaffs_next_dev();
 		if (!dev)
 			return;
-		flash_dev =
-			((unsigned) dev->driver_context - (unsigned) nand_info)/
-				sizeof(nand_info[0]);
+		flash_dev = nand_mtd_to_devnum(dev->driver_context);
 		printf("%-10s %5d 0x%05x 0x%05x %s",
 			dev->param.name, flash_dev,
 			dev->param.start_block, dev->param.end_block,
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 23072fd..fe8ac9d 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -659,6 +659,7 @@ struct nand_buffers {
  */
 
 struct nand_chip {
+	struct mtd_info mtd;
 	void __iomem *IO_ADDR_R;
 	void __iomem *IO_ADDR_W;
 
diff --git a/include/nand.h b/include/nand.h
index eb2d76d..a4f0f92 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -33,15 +33,17 @@ extern void nand_init(void);
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 
+int nand_mtd_to_devnum(struct mtd_info *mtd);
+
 #ifdef CONFIG_SYS_NAND_SELF_INIT
 void board_nand_init(void);
-int nand_register(int devnum);
+int nand_register(int devnum, struct mtd_info *mtd);
 #else
 extern int board_nand_init(struct nand_chip *nand);
 #endif
 
 extern int nand_curr_device;
-extern struct mtd_info nand_info[];
+extern struct mtd_info *nand_info[];
 
 static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
 			    u_char *buf)
-- 
cgit v0.10.2


From 17cb4b8f327eb983cef7c510fcf77f1635a00e48 Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Mon, 30 May 2016 13:57:56 -0500
Subject: mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data

These functions are part of the Linux 4.6 sync.  They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index f46936c..51ac10c 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -16,7 +16,7 @@
  */
 static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	if (ctrl & NAND_CTRL_CHANGE) {
 		if ( ctrl & NAND_CLE )
 			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 8d88bc0..8849681 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 92cef2a..a96a599 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 15e6ea6..a67d812 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -48,7 +48,7 @@ static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
 static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	for (i = 0; i < len; i++) {
 		out_be32(this->IO_ADDR_W,
@@ -88,7 +88,7 @@ static u16 sc_nand_read_word(struct mtd_info *mtd)
 static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int val;
 
 	val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
@@ -105,7 +105,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  */
 static int sc_nand_device_ready(struct mtd_info *mtdinfo)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 
 	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
 		return 0; /* busy */
diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c
index bf896fe..d1f3668 100644
--- a/board/xes/common/actl_nand.c
+++ b/board/xes/common/actl_nand.c
@@ -16,7 +16,7 @@
  */
 static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	ulong IO_ADDR_W;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/cmd/nand.c b/cmd/nand.c
index f1d5a11..583a18f 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -159,7 +159,7 @@ static void do_nand_status(struct mtd_info *mtd)
 	ulong off;
 	int last_status = -1;
 
-	struct nand_chip *nand_chip = mtd->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 	/* check the WP bit */
 	nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 	printf("device is %swrite protected\n",
@@ -285,7 +285,7 @@ usage:
 static void nand_print_and_set_info(int idx)
 {
 	struct mtd_info *mtd = nand_info[idx];
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	printf("Device %d: ", idx);
 	if (chip->numchips > 1)
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index b280f87..f8770e0 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -30,7 +30,7 @@ static struct nand_chip nand_chip;
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
@@ -100,7 +100,7 @@ static int nand_command(int block, int page, uint32_t offs,
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		NAND_CMD_READOOB);
@@ -121,7 +121,7 @@ static int nand_is_bad_block(int block)
 
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 8f0ae4c..6f3b71e 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -230,7 +230,7 @@ static void arasan_nand_enable_ecc(void)
 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
 {
 	u8 addrcycles;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	switch (curr_cmd->addr_cycles) {
 	case NAND_ADDR_CYCL_NONE:
@@ -264,7 +264,7 @@ static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
 
 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 reg_val, i, pktsize, pktnum;
 	u32 *bufptr = (u32 *)buf;
 	u32 timeout;
@@ -441,7 +441,7 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 	u32 size = mtd->writesize;
 	u32 rdcount = 0;
 	u8 column_addr_cycles;
-	struct arasan_nand_info *nand = chip->priv;
+	struct arasan_nand_info *nand = nand_get_controller_data(chip);
 
 	if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
 		pktsize = ARASAN_NAND_PKTSIZE_1K;
@@ -944,7 +944,7 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
 
 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 size;
 	u8 val;
 	struct nand_onfi_params *p;
@@ -976,8 +976,8 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 				     int column, int page_addr)
 {
 	u32 i, ret = 0;
-	struct nand_chip *chip = mtd->priv;
-	struct arasan_nand_info *nand = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct arasan_nand_info *nand = nand_get_controller_data(chip);
 
 	curr_cmd = NULL;
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
@@ -1033,7 +1033,7 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 {
 	int found = -1;
 	u32 regval, eccpos_start, i;
-	struct nand_chip *nand_chip = mtd->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 
 	nand_chip->ecc.mode = NAND_ECC_HW;
 	nand_chip->ecc.hwctl = NULL;
@@ -1101,9 +1101,8 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 	}
 
 	nand->nand_base = arasan_nand_base;
-	mtd = &nand_chip->mtd;
-	nand_chip->priv = nand;
-	mtd->priv = nand_chip;
+	mtd = nand_to_mtd(nand_chip);
+	nand_set_controller_data(nand_chip, nand);
 
 	/* Set the driver entry points for MTD */
 	nand_chip->cmdfunc = arasan_nand_cmd_function;
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 9c2cb44..b1adff0 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -160,8 +160,8 @@ static int pmecc_data_alloc(struct atmel_nand_host *host)
 
 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int i;
 	uint32_t value;
 
@@ -177,8 +177,8 @@ static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 
 static void pmecc_substitute(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 	int16_t __iomem *index_of = host->pmecc_index_of;
 	int16_t *partial_syn = host->pmecc_partial_syn;
@@ -227,8 +227,8 @@ static void pmecc_substitute(struct mtd_info *mtd)
  */
 static void pmecc_get_sigma(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 
 	int16_t *lmu = host->pmecc_lmu;
 	int16_t *si = host->pmecc_si;
@@ -383,8 +383,8 @@ static void pmecc_get_sigma(struct mtd_info *mtd)
 
 static int pmecc_err_location(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	const int cap = host->pmecc_corr_cap;
 	const int num = 2 * cap + 1;
 	int sector_size = host->pmecc_sector_size;
@@ -437,8 +437,8 @@ static int pmecc_err_location(struct mtd_info *mtd)
 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 		int sector_num, int extra_bytes, int err_nbr)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int i = 0;
 	int byte_pos, bit_pos, sector_size, pos;
 	uint32_t tmp;
@@ -483,8 +483,8 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 	u8 *ecc)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int i, err_nbr, eccbytes;
 	uint8_t *buf_pos;
 
@@ -529,7 +529,7 @@ normal_check:
 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
-	struct atmel_nand_host *host = chip->priv;
+	struct atmel_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
 	uint8_t *oob = chip->oob_poi;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
@@ -571,7 +571,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 		struct nand_chip *chip, const uint8_t *buf,
 		int oob_required)
 {
-	struct atmel_nand_host *host = chip->priv;
+	struct atmel_nand_host *host = nand_get_controller_data(chip);
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 	int i, j;
 	int timeout = PMECC_MAX_TIMEOUT_US;
@@ -615,8 +615,8 @@ out:
 
 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	uint32_t val = 0;
 	struct nand_ecclayout *ecc_layout;
 
@@ -808,7 +808,8 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 	struct atmel_nand_host *host;
 	int cap, sector_size;
 
-	host = nand->priv = &pmecc_host;
+	host = &pmecc_host;
+	nand_set_controller_data(nand, host);
 
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.calculate = NULL;
@@ -1080,7 +1081,7 @@ static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		u_char *read_ecc, u_char *isnull)
 {
-	struct nand_chip *nand_chip = mtd->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 	unsigned int ecc_status;
 	unsigned int ecc_word, ecc_bit;
 
@@ -1207,7 +1208,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
 static void at91_nand_hwcontrol(struct mtd_info *mtd,
 					 int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
@@ -1243,7 +1244,7 @@ static struct nand_chip nand_chip;
 
 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
@@ -1281,7 +1282,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 
@@ -1304,7 +1305,7 @@ static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
 
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -1337,7 +1338,7 @@ static int nand_read_page(int block, int page, void *dst)
 
 int spl_nand_erase_one(int block, int page)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 	int page_addr;
@@ -1368,7 +1369,7 @@ int spl_nand_erase_one(int block, int page)
 #else
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	nand_command(block, page, 0, NAND_CMD_READ0);
 	atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
@@ -1407,7 +1408,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 
 int at91_nand_wait_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	udelay(this->chip_delay);
 
@@ -1450,7 +1451,6 @@ void nand_init(void)
 	mtd = &nand_chip.mtd;
 	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
 	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
-	mtd->priv = &nand_chip;
 	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
@@ -1484,9 +1484,8 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
 {
 	int ret;
 	struct nand_chip *nand = &nand_chip[devnum];
-	struct mtd_info *mtd = &nand->mtd;
+	struct mtd_info *mtd = nand_to_mtd(nand);
 
-	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
 
 #ifdef CONFIG_NAND_ECC_BCH
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index a397074..5e0c7bf 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -54,7 +54,7 @@
  */
 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	const u32 *nand = chip->IO_ADDR_R;
 
 	/* Make sure that buf is 32 bit aligned */
@@ -99,7 +99,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 				   int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	const u32 *nand = chip->IO_ADDR_W;
 
 	/* Make sure that buf is 32 bit aligned */
@@ -144,7 +144,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 		unsigned int ctrl)
 {
-	struct		nand_chip *this = mtd->priv;
+	struct		nand_chip *this = mtd_to_nand(mtd);
 	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
@@ -223,7 +223,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 		u_char *read_ecc, u_char *calc_ecc)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
 					  (read_ecc[2] << 16);
 	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 13d10ae..d9bcd72 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -48,7 +48,8 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
  * this macro allows us to convert from an MTD structure to our own
  * device context (denali) structure.
  */
-#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand)
+#define mtd_to_denali(m) \
+	container_of(mtd_to_nand(m), struct denali_nand_info, nand)
 
 /*
  * These constants are defined by the driver to enable common driver
@@ -1179,7 +1180,6 @@ static int denali_init(struct denali_nand_info *denali)
 
 	denali->mtd->name = "denali-nand";
 	denali->mtd->owner = THIS_MODULE;
-	denali->mtd->priv = &denali->nand;
 
 	/* register the driver with the NAND core subsystem */
 	denali->nand.select_chip = denali_select_chip;
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 523aee3..aafff67 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -154,8 +154,8 @@ static struct nand_bbt_descr bbt_mirror_descr = {
  */
 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 	int buf_num;
@@ -194,8 +194,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  */
 static int fsl_elbc_run_command(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -246,7 +246,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 
 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 
@@ -279,8 +279,8 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			     int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 
@@ -489,8 +489,8 @@ static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
  */
 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
 
@@ -526,8 +526,8 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  */
 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 
 	/* If there are still bytes in the FCM, then use the next byte. */
@@ -543,8 +543,8 @@ static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
  */
 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	int avail;
 
@@ -566,7 +566,7 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  */
 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 
@@ -697,8 +697,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand = &priv->chip;
-	mtd = &nand->mtd;
-	mtd->priv = nand;
+	mtd = nand_to_mtd(nand);
 
 	elbc_ctrl->chips[priv->bank] = priv;
 
@@ -720,7 +719,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	nand->bbt_options = NAND_BBT_USE_FLASH;
 
 	nand->controller = &elbc_ctrl->controller;
-	nand->priv = priv;
+	nand_set_controller_data(nand, priv);
 
 	nand->ecc.read_page = fsl_elbc_read_page;
 	nand->ecc.write_page = fsl_elbc_write_page;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index d5fd3ee..f28602e 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -222,8 +222,8 @@ static struct nand_bbt_descr bbt_mirror_descr = {
  */
 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	int buf_num;
@@ -247,8 +247,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 		    unsigned int bufnum)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 	u32 __iomem *main = (u32 *)addr;
 	u8 __iomem *oob = addr + mtd->writesize;
@@ -286,8 +286,8 @@ static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  */
 static int fsl_ifc_run_command(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -367,7 +367,7 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 			    int oob,
 			    struct mtd_info *mtd)
 {
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 
@@ -404,8 +404,8 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			     int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 
@@ -607,8 +607,8 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  */
 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
 
@@ -635,8 +635,8 @@ static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  */
 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	unsigned int offset;
 
@@ -659,8 +659,8 @@ static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
  */
 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	uint16_t data;
 
@@ -683,8 +683,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  */
 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	int avail;
 
@@ -706,7 +706,7 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  */
 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	u32 nand_fsr;
@@ -739,7 +739,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 			     uint8_t *buf, int oob_required, int page)
 {
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 
 	fsl_ifc_read_buf(mtd, buf, mtd->writesize);
@@ -925,8 +925,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand = &priv->chip;
-	mtd = &nand->mtd;
-	mtd->priv = nand;
+	mtd = nand_to_mtd(nand);
 
 	ifc_ctrl->chips[priv->bank] = priv;
 
@@ -955,7 +954,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand->controller = &ifc_ctrl->controller;
-	nand->priv = priv;
+	nand_set_controller_data(nand, priv);
 
 	nand->ecc.read_page = fsl_ifc_read_page;
 	nand->ecc.write_page = fsl_ifc_write_page;
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 5426c32..d2b3881 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -64,8 +64,8 @@ static void fun_wait(struct fsl_upm_nand *fun)
 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 
 	if (chip_nr >= 0) {
 		fun->chip_nr = chip_nr;
@@ -79,8 +79,8 @@ static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
 
 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 	void __iomem *io_addr;
 	u32 mar;
 
@@ -123,7 +123,7 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 
 static u8 upm_nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	return in_8(chip->IO_ADDR_R);
 }
@@ -131,8 +131,8 @@ static u8 upm_nand_read_byte(struct mtd_info *mtd)
 static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 
 	for (i = 0; i < len; i++) {
 		out_8(chip->IO_ADDR_W, buf[i]);
@@ -147,7 +147,7 @@ static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	for (i = 0; i < len; i++)
 		buf[i] = in_8(chip->IO_ADDR_R);
@@ -155,8 +155,8 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 
 static int nand_dev_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 
 	return fun->dev_ready(fun->chip_nr);
 }
@@ -168,7 +168,7 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
 
 	fun->last_ctrl = NAND_CLE;
 
-	chip->priv = fun;
+	nand_set_controller_data(chip, fun);
 	chip->chip_delay = fun->chip_delay;
 	chip->ecc.mode = NAND_ECC_SOFT;
 	chip->cmd_ctrl = fun_cmd_ctrl;
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 0b8b56f..a1f2cba 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -165,7 +165,7 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
 
 static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	ulong IO_ADDR_W;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
@@ -410,7 +410,7 @@ int fsmc_nand_switch_ecc(uint32_t eccstrength)
 	 * function, as it doesn't need to switch to a different ECC layout.
 	 */
 	mtd = nand_info[nand_curr_device];
-	nand = mtd->priv;
+	nand = mtd_to_nand(mtd);
 
 	/* Setup the ecc configurations again */
 	if (eccstrength == 1) {
@@ -479,8 +479,7 @@ int fsmc_nand_init(struct nand_chip *nand)
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	nand->badblockbits = 7;
 
-	mtd = &nand->mtd;
-	mtd->priv = nand;
+	mtd = nand_to_mtd(nand);
 
 	switch (fsmc_version) {
 	case FSMC_VER8:
diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c
index 22c5625..e978cf8 100644
--- a/drivers/mtd/nand/kb9202_nand.c
+++ b/drivers/mtd/nand/kb9202_nand.c
@@ -35,7 +35,7 @@
  */
 static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index d734113..d0a68bd 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -33,7 +33,7 @@ static u32 nand_mpp_backup[9] = { 0 };
 static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 			      unsigned int ctrl)
 {
-	struct nand_chip *nc = mtd->priv;
+	struct nand_chip *nc = mtd_to_nand(mtd);
 	u32 offs;
 
 	if (cmd == NAND_CMD_NONE)
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index 236b0be..9475208 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -542,8 +542,6 @@ void board_nand_init(void)
 	struct mtd_info *mtd = &lpc32xx_chip.mtd;
 	int ret;
 
-	mtd->priv = &lpc32xx_chip;
-
 	/* Set all BOARDSPECIFIC (actually core-specific) fields  */
 
 	lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
index 4e1be36..89b48cb 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -291,7 +291,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
 static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
 			      int len, int read)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 config;
 	int ret;
 
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index d836130..362d393 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -117,8 +117,8 @@ static void mpc5121_nfc_done(struct mtd_info *mtd);
 /* Read NFC register */
 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 
 	return in_be16(prv->regs + reg);
 }
@@ -126,8 +126,8 @@ static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
 /* Write NFC register */
 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 
 	out_be16(prv->regs + reg, val);
 }
@@ -211,7 +211,7 @@ static void mpc5121_nfc_done(struct mtd_info *mtd)
 /* Do address cycle(s) */
 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 pagemask = chip->pagemask;
 
 	if (column != -1) {
@@ -283,8 +283,8 @@ static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
 static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
 				int column, int page)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 
 	prv->column = (column >= 0) ? column : 0;
 	prv->spareonly = 0;
@@ -357,8 +357,8 @@ static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 				   u8 * buffer, uint size, int wr)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mpc5121_nfc_prv *prv = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
 	uint o, s, sbsize, blksize;
 
 	/*
@@ -410,8 +410,8 @@ static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len,
 				 int wr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 	uint c = prv->column;
 	uint l;
 
@@ -489,7 +489,7 @@ static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint rcw_pagesize = 0;
 	uint rcw_sparesize = 0;
 	uint rcw_width;
@@ -568,8 +568,7 @@ int board_nand_init(struct nand_chip *chip)
 	}
 
 	mtd = &chip->mtd;
-	mtd->priv = chip;
-	chip->priv = prv;
+	nand_set_controller_data(chip, prv);
 
 	/* Read NFC configuration from Reset Config Word */
 	retval = mpc5121_nfc_read_hw_config(mtd);
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 5e7b9cf..f935055 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -351,8 +351,8 @@ static int mxc_nand_dev_ready(struct mtd_info *mtd)
 
 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 	uint16_t tmp = readnfc(&host->regs->config1);
 
@@ -386,7 +386,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 				      struct nand_chip *chip,
 				      int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	uint8_t *buf = chip->oob_poi;
 	int length = mtd->oobsize;
 	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -441,7 +441,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 					   int oob_required,
 					   int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -486,7 +486,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 				       int oob_required,
 				       int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int n, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -550,7 +550,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 				       struct nand_chip *chip, int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 	int length = mtd->oobsize;
 	int i, len, status, steps = chip->ecc.steps;
@@ -578,7 +578,7 @@ static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					     const uint8_t *buf,
 					     int oob_required)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -618,7 +618,7 @@ static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 					 const uint8_t *buf,
 					 int oob_required)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int i, n, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -661,8 +661,8 @@ static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				 u_char *read_ecc, u_char *calc_ecc)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 	int subpages = mtd->writesize / nand_chip->subpagesize;
 	int pg2blk_shift = nand_chip->phys_erase_shift -
@@ -700,8 +700,8 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				 u_char *read_ecc, u_char *calc_ecc)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 
 	/*
 	 * 1-Bit errors are automatically corrected in HW.  No need for
@@ -729,8 +729,8 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 
 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	uint8_t ret = 0;
 	uint16_t col;
 	uint16_t __iomem *main_buf =
@@ -769,8 +769,8 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 
 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	uint16_t col, ret;
 	uint16_t __iomem *p;
 
@@ -821,8 +821,8 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 static void mxc_nand_write_buf(struct mtd_info *mtd,
 				const u_char *buf, int len)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	int n, col, i = 0;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3,
@@ -895,8 +895,8 @@ static void mxc_nand_write_buf(struct mtd_info *mtd,
  */
 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	int n, col, i = 0;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3,
@@ -955,8 +955,8 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  */
 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 
 	switch (chip) {
 	case -1:
@@ -982,8 +982,8 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 				int column, int page_addr)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3,
 	      "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
@@ -1165,13 +1165,12 @@ int board_nand_init(struct nand_chip *this)
 
 	/* structures must be linked */
 	mtd = &this->mtd;
-	mtd->priv = this;
 	host->nand = this;
 
 	/* 5 us command delay time */
 	this->chip_delay = 5;
 
-	this->priv = host;
+	nand_set_controller_data(this, host);
 	this->dev_ready = mxc_nand_dev_ready;
 	this->cmdfunc = mxc_nand_command;
 	this->select_chip = mxc_nand_select_chip;
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index b5bbd88..7053ff2 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -264,8 +264,8 @@ static int mxs_nand_wait_for_bch_complete(void)
  */
 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -343,8 +343,8 @@ static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
  */
 static int mxs_nand_device_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	struct mxs_gpmi_regs *gpmi_regs =
 		(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
 	uint32_t tmp;
@@ -360,8 +360,8 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
  */
 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 
 	nand_info->cur_chip = chip;
 }
@@ -410,8 +410,8 @@ static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
  */
 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -494,8 +494,8 @@ rtn:
 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 				int length)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -559,7 +559,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
 					uint8_t *buf, int oob_required,
 					int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	uint32_t corrected = 0, failed = 0;
@@ -709,7 +709,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
 				struct nand_chip *nand, const uint8_t *buf,
 				int oob_required)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -775,8 +775,8 @@ rtn:
 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
 					struct mtd_oob_ops *ops)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	int ret;
 
 	if (ops->mode == MTD_OPS_RAW)
@@ -800,8 +800,8 @@ static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
 					struct mtd_oob_ops *ops)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	int ret;
 
 	if (ops->mode == MTD_OPS_RAW)
@@ -824,8 +824,8 @@ static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
  */
 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	int ret;
 
 	nand_info->marking_block_bad = 1;
@@ -884,7 +884,7 @@ static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
 				int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 
 	/*
 	 * First, fill in the OOB buffer. If we're doing a raw read, we need to
@@ -919,7 +919,7 @@ static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
 					int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	uint8_t block_mark = 0;
 
 	/*
@@ -982,8 +982,8 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  */
 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
 	uint32_t tmp;
 
@@ -1175,7 +1175,7 @@ int board_nand_init(struct nand_chip *nand)
 
 	memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
 
-	nand->priv = nand_info;
+	nand_set_controller_data(nand, nand_info);
 	nand->options |= NAND_NO_SUBPAGE_WRITE;
 
 	nand->cmd_ctrl		= mxs_nand_cmd_ctrl;
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index 0b3a604..a8a3084 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -14,7 +14,7 @@ static struct nand_chip nand_chip;
 static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
 			     int column, int page_addr)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 timeo, time_start;
 
 	/* write out the command to the device */
@@ -51,7 +51,7 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
 
 static int mxs_flash_ident(struct mtd_info *mtd)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	int i;
 	u8 mfg_id, dev_id;
 	u8 id_data[8];
@@ -111,7 +111,7 @@ static int mxs_flash_ident(struct mtd_info *mtd)
 
 static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	int ret;
 
 	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
@@ -125,7 +125,7 @@ static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
 
 static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	unsigned int block = offs >> chip->phys_erase_shift;
 	unsigned int page = offs >> chip->page_shift;
 
@@ -148,7 +148,6 @@ static int mxs_nand_init(void)
 	/* init mxs nand driver */
 	board_nand_init(&nand_chip);
 	mtd = &nand_chip.mtd;
-	mtd->priv = &nand_chip;
 	/* set mtd functions */
 	nand_chip.cmdfunc = mxs_nand_command;
 	nand_chip.numchips = 1;
@@ -181,7 +180,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 
 	if (mxs_nand_init())
 		return -ENODEV;
-	chip = mtd->priv;
+	chip = mtd_to_nand(mtd);
 	page = offs >> chip->page_shift;
 	nand_page_per_block = mtd->erasesize / mtd->writesize;
 
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index ddd8249..f449316 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -73,14 +73,13 @@ int nand_register(int devnum, struct mtd_info *mtd)
 static void nand_init_chip(int i)
 {
 	struct nand_chip *nand = &nand_chip[i];
-	struct mtd_info *mtd = &nand->mtd;
+	struct mtd_info *mtd = nand_to_mtd(nand);
 	ulong base_addr = base_address[i];
 	int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
 
 	if (maxchips < 1)
 		maxchips = 1;
 
-	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
 
 	if (board_nand_init(nand))
@@ -110,7 +109,7 @@ void nand_init(void)
 	/*
 	 * Select the chip in the board/cpu specific driver
 	 */
-	board_nand_select_device(nand_info[nand_curr_device]->priv,
+	board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]),
 				 nand_curr_device);
 #endif
 }
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 9e8fc1f..92f581e 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -105,7 +105,7 @@ DEFINE_LED_TRIGGER(nand_led_trigger);
 static int check_offs_len(struct mtd_info *mtd,
 					loff_t ofs, uint64_t len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int ret = 0;
 
 	/* Start address must align on block boundary */
@@ -131,7 +131,7 @@ static int check_offs_len(struct mtd_info *mtd,
  */
 static void nand_release_device(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* De-select the NAND device */
 	chip->select_chip(mtd, -1);
@@ -145,7 +145,7 @@ static void nand_release_device(struct mtd_info *mtd)
  */
 uint8_t nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	return readb(chip->IO_ADDR_R);
 }
 
@@ -158,7 +158,7 @@ uint8_t nand_read_byte(struct mtd_info *mtd)
  */
 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 }
 
@@ -170,7 +170,7 @@ static uint8_t nand_read_byte16(struct mtd_info *mtd)
  */
 static u16 nand_read_word(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	return readw(chip->IO_ADDR_R);
 }
 
@@ -183,7 +183,7 @@ static u16 nand_read_word(struct mtd_info *mtd)
  */
 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	switch (chipnr) {
 	case -1:
@@ -206,7 +206,7 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  */
 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	chip->write_buf(mtd, &byte, 1);
 }
@@ -220,7 +220,7 @@ static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
  */
 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint16_t word = byte;
 
 	/*
@@ -287,7 +287,7 @@ static void iowrite16_rep(void *addr, void *buf, int len)
  */
 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	iowrite8_rep(chip->IO_ADDR_W, buf, len);
 }
@@ -302,7 +302,7 @@ void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  */
 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	ioread8_rep(chip->IO_ADDR_R, buf, len);
 }
@@ -317,7 +317,7 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  */
 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 *p = (u16 *) buf;
 
 	iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
@@ -333,7 +333,7 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  */
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 *p = (u16 *) buf;
 
 	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
@@ -350,7 +350,7 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 {
 	int page, chipnr, res = 0, i = 0;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 bad;
 
 	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
@@ -410,7 +410,7 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  */
 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtd_oob_ops ops;
 	uint8_t buf[2] = { 0, 0 };
 	int ret = 0, res, i = 0;
@@ -460,7 +460,7 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 */
 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int res, ret = 0;
 
 	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
@@ -501,7 +501,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
  */
 static int nand_check_wp(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* Broken xD cards report WP despite being writable */
 	if (chip->options & NAND_BROKEN_XD)
@@ -521,7 +521,7 @@ static int nand_check_wp(struct mtd_info *mtd)
  */
 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if (!chip->bbt)
 		return 0;
@@ -542,7 +542,7 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 			       int allowbbt)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if (!(chip->options & NAND_SKIP_BBTSCAN) &&
 	    !(chip->options & NAND_BBT_SCANNED)) {
@@ -560,7 +560,7 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 /* Wait for the ready pin, after a command. The timeout is caught later. */
 void nand_wait_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 	u32 time_start;
 
@@ -583,7 +583,7 @@ EXPORT_SYMBOL_GPL(nand_wait_ready);
  */
 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 time_start;
 
 	timeo = (CONFIG_SYS_HZ * timeo) / 1000;
@@ -608,7 +608,7 @@ static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
 static void nand_command(struct mtd_info *mtd, unsigned int command,
 			 int column, int page_addr)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 
 	/* Write out the command to the device */
@@ -711,7 +711,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 			    int column, int page_addr)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* Emulate NAND_CMD_READOOB */
 	if (command == NAND_CMD_READOOB) {
@@ -835,7 +835,7 @@ static void panic_nand_get_device(struct nand_chip *chip,
 static int
 nand_get_device(struct mtd_info *mtd, int new_state)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	chip->state = new_state;
 	return 0;
 }
@@ -1332,7 +1332,7 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  */
 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	pr_debug("setting READ RETRY mode %d\n", retry_mode);
 
@@ -1357,7 +1357,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
 	int chipnr, page, realpage, col, bytes, aligned, oob_required;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int ret = 0;
 	uint32_t readlen = ops->len;
 	uint32_t oobreadlen = ops->ooblen;
@@ -1700,7 +1700,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
 	int page, realpage, chipnr;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtd_ecc_stats stats;
 	int readlen = ops->ooblen;
 	int len;
@@ -2139,7 +2139,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
 			      struct mtd_oob_ops *ops)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/*
 	 * Initialise to all 0xFF, to avoid the possibility of left over OOB
@@ -2199,7 +2199,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
 {
 	int chipnr, realpage, page, blockmask, column;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint32_t writelen = ops->len;
 
 	uint32_t oobwritelen = ops->ooblen;
@@ -2328,7 +2328,7 @@ err_out:
 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
 			    size_t *retlen, const uint8_t *buf)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtd_oob_ops ops;
 	int ret;
 
@@ -2388,7 +2388,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
 {
 	int chipnr, page, status, len;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	pr_debug("%s: to = 0x%08x, len = %i\n",
 			 __func__, (unsigned int)to, (int)ops->ooblen);
@@ -2513,7 +2513,7 @@ out:
  */
 static int single_erase(struct mtd_info *mtd, int page)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	/* Send commands to erase a block */
 	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
 	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
@@ -2545,7 +2545,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 		    int allowbbt)
 {
 	int page, status, pages_per_block, ret, chipnr;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	loff_t len;
 
 	pr_debug("%s: start = 0x%012llx, len = %llu\n",
@@ -2908,7 +2908,7 @@ ext_out:
 
 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
 
 	return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
@@ -3616,7 +3616,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
 		    struct nand_flash_dev *table)
 {
 	int i, nand_maf_id, nand_dev_id;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_flash_dev *type;
 
 	/* Set the default functions */
@@ -3680,7 +3680,7 @@ EXPORT_SYMBOL(nand_scan_ident);
  */
 static bool nand_ecc_strength_good(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	int corr, ds_corr;
 
@@ -3709,7 +3709,7 @@ static bool nand_ecc_strength_good(struct mtd_info *mtd)
 int nand_scan_tail(struct mtd_info *mtd)
 {
 	int i;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	struct nand_buffers *nbuf;
 
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 00f28a4..152f3bc 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -173,7 +173,7 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
 		struct nand_bbt_descr *td, int offs)
 {
 	int res, ret = 0, i, j, act = 0;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	size_t retlen, len, totlen;
 	loff_t from;
 	int bits = td->options & NAND_BBT_NRBITS_MSK;
@@ -264,7 +264,7 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
  */
 static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int res = 0, i;
 
 	if (td->options & NAND_BBT_PERCHIP) {
@@ -389,7 +389,7 @@ static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td)
 static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
 			  struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	/* Read the primary version, if available */
 	if (td->options & NAND_BBT_VERSION) {
@@ -455,7 +455,7 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
 static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 	struct nand_bbt_descr *bd, int chip)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int i, numblocks, numpages;
 	int startblock;
 	loff_t from;
@@ -524,7 +524,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
  */
 static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int i, chips;
 	int startblock, block, dir;
 	int scanlen = mtd->writesize + mtd->oobsize;
@@ -619,7 +619,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		     struct nand_bbt_descr *td, struct nand_bbt_descr *md,
 		     int chipsel)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	struct erase_info einfo;
 	int i, res, chip = 0;
 	int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
@@ -820,7 +820,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
  */
 static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	return create_bbt(mtd, this->buffers->databuf, bd, -1);
 }
@@ -839,7 +839,7 @@ static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *b
 static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
 {
 	int i, chips, writeops, create, chipsel, res, res2;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
 	struct nand_bbt_descr *rd, *rd2;
@@ -963,7 +963,7 @@ static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc
  */
 static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int i, j, chips, block, nrblocks, update;
 	uint8_t oldval;
 
@@ -1023,7 +1023,7 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
  */
 static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u32 pattern_len;
 	u32 bits;
 	u32 table_size;
@@ -1075,7 +1075,7 @@ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
  */
 int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int len, res = 0;
 	uint8_t *buf;
 	struct nand_bbt_descr *td = this->bbt_td;
@@ -1143,7 +1143,7 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
  */
 static int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int len, res = 0;
 	int chip, chipsel;
 	uint8_t *buf;
@@ -1277,7 +1277,7 @@ static int nand_create_badblock_pattern(struct nand_chip *this)
  */
 int nand_default_bbt(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int ret;
 
 	/* Is a flash based bad block table requested? */
@@ -1313,7 +1313,7 @@ int nand_default_bbt(struct mtd_info *mtd)
  */
 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int block;
 
 	block = (int)(offs >> this->bbt_erase_shift);
@@ -1328,7 +1328,7 @@ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
  */
 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int block, res;
 
 	block = (int)(offs >> this->bbt_erase_shift);
@@ -1355,7 +1355,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
  */
 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int block, ret = 0;
 
 	block = (int)(offs >> this->bbt_erase_shift);
diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c
index 35d2140..d7f6ce0 100644
--- a/drivers/mtd/nand/nand_bch.c
+++ b/drivers/mtd/nand/nand_bch.c
@@ -41,7 +41,7 @@ struct nand_bch_control {
 int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
 			   unsigned char *code)
 {
-	const struct nand_chip *chip = mtd->priv;
+	const struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_bch_control *nbc = chip->ecc.priv;
 	unsigned int i;
 
@@ -67,7 +67,7 @@ int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
 int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 			  unsigned char *read_ecc, unsigned char *calc_ecc)
 {
-	const struct nand_chip *chip = mtd->priv;
+	const struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_bch_control *nbc = chip->ecc.priv;
 	unsigned int *errloc = nbc->errloc;
 	int i, count;
diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c
index 37a0206..335c3e3 100644
--- a/drivers/mtd/nand/nand_plat.c
+++ b/drivers/mtd/nand/nand_plat.c
@@ -25,7 +25,7 @@
 
 static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	if (cmd == NAND_CMD_NONE)
 		return;
@@ -39,7 +39,7 @@ static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 #ifdef NAND_PLAT_DEV_READY
 static int plat_dev_ready(struct mtd_info *mtd)
 {
-	return NAND_PLAT_DEV_READY((struct nand_chip *)mtd->priv);
+	return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd));
 }
 #else
 # define plat_dev_ready NULL
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index bc6a09a..b023e00 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -26,7 +26,7 @@ static struct nand_chip nand_chip;
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd->priv();
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 
 	while (!this->dev_ready(mtd))
@@ -63,7 +63,7 @@ static int nand_command(int block, int page, uint32_t offs,
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
@@ -114,7 +114,7 @@ static int nand_command(int block, int page, uint32_t offs,
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char bb_data[2];
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -139,7 +139,7 @@ static int nand_is_bad_block(int block)
 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
 static int nand_read_page(int block, int page, uchar *dst)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -170,7 +170,7 @@ static int nand_read_page(int block, int page, uchar *dst)
 #else
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -250,7 +250,6 @@ void nand_init(void)
 	 * Init board specific nand support
 	 */
 	mtd = &nand_chip.mtd;
-	mtd->priv = &nand_chip;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 90bf798..9b61087 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -59,7 +59,7 @@ int nand_erase_opts(struct mtd_info *mtd,
 	int percent_complete = -1;
 	const char *mtd_device = mtd->name;
 	struct mtd_oob_ops oob_opts;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if ((opts->offset & (mtd->erasesize - 1)) != 0) {
 		printf("Attempt to erase non block-aligned data\n");
@@ -217,7 +217,7 @@ int nand_lock(struct mtd_info *mtd, int tight)
 {
 	int ret = 0;
 	int status;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* select the NAND device */
 	chip->select_chip(mtd, 0);
@@ -267,7 +267,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
 	int ret = 0;
 	int chipnr;
 	int page;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* select the NAND device */
 	chipnr = (int)(offset >> chip->chip_shift);
@@ -314,7 +314,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
 	int chipnr;
 	int status;
 	int page;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	debug("nand_unlock%s: start: %08llx, length: %zd!\n",
 		allexcept ? " (allexcept)" : "", start, length);
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 8a68cb0..ee353c7 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -37,7 +37,7 @@ static int ndfc_cs[NDFC_MAX_BANKS];
 
 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 
 	if (cmd == NAND_CMD_NONE)
@@ -51,7 +51,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 
 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 
 	return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
@@ -59,7 +59,7 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
 
 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	u32 ccr;
 
@@ -71,7 +71,7 @@ static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
 			      const u_char *dat, u_char *ecc_code)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	u32 ecc;
 	u8 *p = (u8 *)&ecc;
@@ -96,7 +96,7 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
  */
 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	uint32_t *p = (uint32_t *) buf;
 
@@ -110,7 +110,7 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
  */
 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	uint32_t *p = (uint32_t *) buf;
 
@@ -124,7 +124,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 static uint8_t ndfc_read_byte(struct mtd_info *mtd)
 {
 
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
 	return (uint8_t) readw(chip->IO_ADDR_R);
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index f2ee90e..cac9eea 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -58,8 +58,8 @@ static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 				uint32_t ctrl)
 {
-	register struct nand_chip *this = mtd->priv;
-	struct omap_nand_info *info = this->priv;
+	register struct nand_chip *this = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(this);
 	int cs = info->cs;
 
 	/*
@@ -85,8 +85,8 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 /* Check wait pin as dev ready indicator */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
-	register struct nand_chip *this = mtd->priv;
-	struct omap_nand_info *info = this->priv;
+	register struct nand_chip *this = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(this);
 	return gpmc_cfg->status & (1 << (8 + info->ws));
 }
 
@@ -177,8 +177,8 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 __maybe_unused
 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 {
-	struct nand_chip	*nand	= mtd->priv;
-	struct omap_nand_info	*info	= nand->priv;
+	struct nand_chip	*nand	= mtd_to_nand(mtd);
+	struct omap_nand_info	*info	= nand_get_controller_data(nand);
 	unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 	unsigned int ecc_algo = 0;
 	unsigned int bch_type = 0;
@@ -262,8 +262,8 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 				uint8_t *ecc_code)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 	uint32_t *ptr, val = 0;
 	int8_t i = 0, j;
 
@@ -392,7 +392,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
 {
 	int ret;
 	uint32_t cnt;
-	struct omap_nand_info *info = chip->priv;
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 
 	ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
 	if (ret < 0)
@@ -417,7 +417,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
 
 static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if (chip->options & NAND_BUSWIDTH_16)
 		nand_read_buf16(mtd, buf, len);
@@ -429,7 +429,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int ret;
 	uint32_t head, tail;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/*
 	 * If the destination buffer is unaligned, start with reading
@@ -491,8 +491,8 @@ static void omap_reverse_list(u8 *list, unsigned int length)
 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 				uint8_t *read_ecc, uint8_t *calc_ecc)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	uint32_t error_count = 0, error_max;
 	uint32_t error_loc[ELM_MAX_ERROR_COUNT];
@@ -652,8 +652,8 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 	int i, count;
 	/* cannot correct more than 8 errors */
 	unsigned int errloc[8];
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 
 	count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 							NULL, errloc);
@@ -691,8 +691,8 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
  */
 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 
 	if (info->control) {
 		free_bch(info->control);
@@ -710,7 +710,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
  */
 static int omap_select_ecc_scheme(struct nand_chip *nand,
 	enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
-	struct omap_nand_info	*info		= nand->priv;
+	struct omap_nand_info	*info		= nand_get_controller_data(nand);
 	struct nand_ecclayout	*ecclayout	= &omap_ecclayout;
 	int eccsteps = pagesize / SECTOR_BYTES;
 	int i;
@@ -904,7 +904,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 	}
 
 	mtd = nand_info[nand_curr_device];
-	nand = mtd->priv;
+	nand = mtd_to_nand(mtd);
 	nand->options |= NAND_OWN_BUFFERS;
 	nand->options &= ~NAND_SUBPAGE_READ;
 	/* Setup the ecc configurations again */
@@ -994,7 +994,7 @@ int board_nand_init(struct nand_chip *nand)
 	omap_nand_info[cs].control = NULL;
 	omap_nand_info[cs].cs = cs;
 	omap_nand_info[cs].ws = wscfg[cs];
-	nand->priv	= &omap_nand_info[cs];
+	nand_set_controller_data(nand, &omap_nand_info[cs]);
 	nand->cmd_ctrl	= omap_nand_hwcontrol;
 	nand->options	|= NAND_NO_PADDING | NAND_CACHEPRG;
 	nand->chip_delay = 100;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 125dbe7..03bf046 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -900,7 +900,8 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
 static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 			 int column, int page_addr)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int exec_cmd;
 
@@ -960,7 +961,8 @@ static void nand_cmdfunc_extended(struct mtd_info *mtd,
 				  const unsigned command,
 				  int column, int page_addr)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int exec_cmd, ext_cmd_type;
 
@@ -1091,7 +1093,7 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, uint8_t *buf, int oob_required,
 		int page)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 
 	chip->read_buf(mtd, buf, mtd->writesize);
@@ -1117,7 +1119,8 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 
 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	char retval = 0xFF;
 
@@ -1130,7 +1133,8 @@ static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 
 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	u16 retval = 0xFFFF;
 
@@ -1143,7 +1147,8 @@ static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 
 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
@@ -1154,7 +1159,8 @@ static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 		const uint8_t *buf, int len)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
@@ -1169,7 +1175,8 @@ static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 
 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 
 	if (info->need_wait) {
@@ -1210,7 +1217,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
 {
 	struct pxa3xx_nand_host *host = info->host[info->cs];
 	struct mtd_info *mtd = host->mtd;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 	info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
@@ -1262,7 +1269,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
 	int ret;
 
 	mtd = info->host[info->cs]->mtd;
-	chip = mtd->priv;
+	chip = mtd_to_nand(mtd);
 
 	/* configure default flash values */
 	info->reg_ndcr = 0x0; /* enable all interrupts */
@@ -1354,10 +1361,10 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
 
 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	struct pxa3xx_nand_platform_data *pdata = info->pdata;
-	struct nand_chip *chip = mtd->priv;
 	int ret;
 	uint16_t ecc_strength, ecc_step;
 
@@ -1479,14 +1486,13 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
 	for (cs = 0; cs < pdata->num_cs; cs++) {
 		chip = (struct nand_chip *)
 			((u8 *)&info[1] + sizeof(*host) * cs);
-		mtd = &chip->mtd;
+		mtd = nand_to_mtd(chip);
 		host = (struct pxa3xx_nand_host *)chip;
 		info->host[cs] = host;
 		host->mtd = mtd;
 		host->cs = cs;
 		host->info_data = info;
 		host->read_id_bytes = 4;
-		mtd->priv = host;
 		mtd->owner = THIS_MODULE;
 
 		chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index b3a2a60..2a0da6e 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -31,7 +31,7 @@
 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	for (i = 0; i < len; i++)
 		buf[i] = readb(this->IO_ADDR_R);
@@ -40,7 +40,7 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 
 static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 
 	debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index b20fb1e..3eae4cb 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -143,10 +143,10 @@ static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
  */
 static uint8_t read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
 	       &info->reg->command);
@@ -169,8 +169,8 @@ static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int i, s;
 	unsigned int reg;
-	struct nand_chip *chip = mtd->priv;
-	struct nand_drv *info = (struct nand_drv *)chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	for (i = 0; i < len; i += 4) {
 		s = (len - i) > 4 ? 4 : len - i;
@@ -194,11 +194,11 @@ static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  */
 static int nand_dev_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int reg_val;
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	reg_val = readl(&info->reg->status);
 	if (reg_val & STATUS_RBSY0)
@@ -245,10 +245,10 @@ static void nand_clear_interrupt_status(struct nand_ctlr *reg)
 static void nand_command(struct mtd_info *mtd, unsigned int command,
 	int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	/*
 	 * Write out the command to the device.
@@ -512,7 +512,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EINVAL;
 	}
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 	config = &info->config;
 	if (set_bus_width_page_size(config, &reg_val))
 		return -EINVAL;
@@ -662,7 +662,7 @@ static int nand_write_page_hwecc(struct mtd_info *mtd,
 	int page;
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	page = (readl(&info->reg->addr_reg1) >> 16) |
 		(readl(&info->reg->addr_reg2) << 16);
@@ -702,7 +702,7 @@ static int nand_write_page_raw(struct mtd_info *mtd,
 	int page;
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 	page = (readl(&info->reg->addr_reg1) >> 16) |
 		(readl(&info->reg->addr_reg2) << 16);
 
@@ -734,7 +734,7 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 
 	if (((int)chip->oob_poi) & 0x03)
 		return -EINVAL;
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 	if (set_bus_width_page_size(&info->config, &reg_val))
 		return -EINVAL;
 
@@ -963,7 +963,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 	nand->ecc.strength = 1;
 	nand->select_chip = nand_select_chip;
 	nand->dev_ready  = nand_dev_ready;
-	nand->priv = &nand_ctrl;
+	nand_set_controller_data(nand, &nand_ctrl);
 
 	/* Disable subpage writes as we do not provide ecc->hwctl */
 	nand->options |= NAND_NO_SUBPAGE_WRITE;
@@ -976,8 +976,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 
 	dm_gpio_set_value(&config->wp_gpio, 1);
 
-	our_mtd = &nand->mtd;
-	our_mtd->priv = nand;
+	our_mtd = nand_to_mtd(nand);
 	ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 	if (ret)
 		return ret;
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 3be8b02..a4d5a62 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -155,8 +155,7 @@ struct vf610_nfc {
 	enum vf610_nfc_alt_buf alt_buf;
 };
 
-#define mtd_to_nfc(_mtd) \
-	(struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
+#define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
 
 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
 #define ECC_HW_MODE ECC_45_BYTE
@@ -653,9 +652,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 	chip = &nfc->chip;
 	nfc->regs = addr;
 
-	mtd = &chip->mtd;
-	mtd->priv = chip;
-	chip->priv = nfc;
+	mtd = nand_to_mtd(chip);
+	nand_set_controller_data(chip, nfc);
 
 	if (cfg.width == 16)
 		chip->options |= NAND_BUSWIDTH_16;
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index 6d86871..25aa6d1 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -190,7 +190,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev,
 		goto err;
 	}
 
-	chip =  mtd->priv;
+	chip =  mtd_to_nand(mtd);
 
 	/* Check for any conflicts */
 	yaffs_dev_rewind();
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index fe8ac9d..e1df66b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -740,6 +740,26 @@ struct nand_chip {
 	void *priv;
 };
 
+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
+{
+	return container_of(mtd, struct nand_chip, mtd);
+}
+
+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
+{
+	return &chip->mtd;
+}
+
+static inline void *nand_get_controller_data(struct nand_chip *chip)
+{
+	return chip->priv;
+}
+
+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
+{
+	chip->priv = priv;
+}
+
 /*
  * NAND Flash Manufacturer ID Codes
  */
-- 
cgit v0.10.2


From 81c772521ff26054a3fe75efa87d8daeae83e9b4 Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Mon, 30 May 2016 13:57:57 -0500
Subject: mtd: nand: Add page argument to write_page() etc.

This change is part of the Linux 4.6 sync.  It is being done before the
main sync patch in order to make it easier to address the issue across
all NAND drivers (many/most of which do not closely track their Linux
counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 6f3b71e..320cbaa 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -433,7 +433,8 @@ static void arasan_nand_fill_tx(const u8 *buf, int len)
 }
 
 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, const u8 *buf, int oob_required)
+		struct nand_chip *chip, const u8 *buf, int oob_required,
+		int page)
 {
 	u32 reg_val, i, pktsize, pktnum;
 	const u32 *bufptr = (const u32 *)buf;
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index b1adff0..a81b96d 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -569,7 +569,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 
 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 		struct nand_chip *chip, const uint8_t *buf,
-		int oob_required)
+		int oob_required, int page)
 {
 	struct atmel_nand_host *host = nand_get_controller_data(chip);
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 5e0c7bf..be9d666 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -380,10 +380,13 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 
-	if (unlikely(raw))
-		status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
-	else
-		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+	if (unlikely(raw)) {
+		status = chip->ecc.write_page_raw(mtd, chip, buf,
+						  oob_required, page);
+	} else {
+		status = chip->ecc.write_page(mtd, chip, buf,
+					      oob_required, page);
+	}
 
 	if (status < 0) {
 		ret = status;
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index d9bcd72..3ae7545 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -866,7 +866,8 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * by write_page above.
  */
 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required,
+				int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
@@ -890,7 +891,8 @@ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * write_page() function above.
  */
 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-					const uint8_t *buf, int oob_required)
+					const uint8_t *buf, int oob_required,
+					int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index aafff67..f621f14 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -611,7 +611,8 @@ static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  * waitfunc.
  */
 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required,
+				int page)
 {
 	fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -626,7 +627,7 @@ static struct fsl_elbc_ctrl *elbc_ctrl;
  */
 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 				uint32_t offset, uint32_t data_len,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required, int page)
 {
 	fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index f28602e..7001cbd 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -755,7 +755,7 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  * waitfunc.
  */
 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			       const uint8_t *buf, int oob_required)
+			       const uint8_t *buf, int oob_required, int page)
 {
 	fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 	fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index 9475208..4262029 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -378,7 +378,8 @@ static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  */
 
 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required,
+	int page)
 {
 	unsigned int i, status, timeout;
 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
@@ -435,7 +436,8 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
  */
 
 static int lpc32xx_write_page_raw(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required,
+	int page)
 {
 	unsigned int i;
 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
index 89b48cb..daa1e7a 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -486,7 +486,8 @@ static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 /* Reuse the logic from "nand_write_page_hwecc()" */
 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
 				    struct nand_chip *chip,
-				    const uint8_t *buf, int oob_required)
+				    const uint8_t *buf, int oob_required,
+				    int page)
 {
 	int i;
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index f935055..d4e14b5 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -576,7 +576,7 @@ static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					     struct nand_chip *chip,
 					     const uint8_t *buf,
-					     int oob_required)
+					     int oob_required, int page)
 {
 	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
@@ -616,7 +616,7 @@ static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 					 struct nand_chip *chip,
 					 const uint8_t *buf,
-					 int oob_required)
+					 int oob_required, int page)
 {
 	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int i, n, eccsize = chip->ecc.size;
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7053ff2..5291330 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -707,7 +707,7 @@ rtn:
  */
 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
 				struct nand_chip *nand, const uint8_t *buf,
-				int oob_required)
+				int oob_required, int page)
 {
 	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 92f581e..62e70a7 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1840,11 +1840,13 @@ out:
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  *
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required,
+				int page)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
 	if (oob_required)
@@ -1864,7 +1866,8 @@ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  */
 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					struct nand_chip *chip,
-					const uint8_t *buf, int oob_required)
+					const uint8_t *buf, int oob_required,
+					int page)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1901,9 +1904,11 @@ static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  */
 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf, int oob_required)
+				  const uint8_t *buf, int oob_required,
+				  int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1919,7 +1924,7 @@ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 	for (i = 0; i < chip->ecc.total; i++)
 		chip->oob_poi[eccpos[i]] = ecc_calc[i];
 
-	return chip->ecc.write_page_raw(mtd, chip, buf, 1);
+	return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 }
 
 /**
@@ -1928,9 +1933,11 @@ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  */
 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf, int oob_required)
+				  const uint8_t *buf, int oob_required,
+				  int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1962,11 +1969,12 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @data_len:	data length
  * @buf:	data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  */
 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
 				struct nand_chip *chip, uint32_t offset,
 				uint32_t data_len, const uint8_t *buf,
-				int oob_required)
+				int oob_required, int page)
 {
 	uint8_t *oob_buf  = chip->oob_poi;
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
@@ -2027,7 +2035,8 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  */
 static int nand_write_page_syndrome(struct mtd_info *mtd,
 				    struct nand_chip *chip,
-				    const uint8_t *buf, int oob_required)
+				    const uint8_t *buf, int oob_required,
+				    int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -2091,12 +2100,13 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 	if (unlikely(raw))
 		status = chip->ecc.write_page_raw(mtd, chip, buf,
-							oob_required);
+						  oob_required, page);
 	else if (subpage)
 		status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
-							 buf, oob_required);
+						  buf, oob_required, page);
 	else
-		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+		status = chip->ecc.write_page(mtd, chip, buf, oob_required,
+					      page);
 
 	if (status < 0)
 		return status;
@@ -2135,6 +2145,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * @oob: oob data buffer
  * @len: oob data write length
  * @ops: oob ops structure
+ * @page: page number to write
  */
 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
 			      struct mtd_oob_ops *ops)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 03bf046..d3ac539 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1081,7 +1081,8 @@ static void nand_cmdfunc_extended(struct mtd_info *mtd,
 }
 
 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, const uint8_t *buf, int oob_required)
+		struct nand_chip *chip, const uint8_t *buf, int oob_required,
+		int page)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 3eae4cb..2032f65 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -657,16 +657,9 @@ static int nand_read_page_hwecc(struct mtd_info *mtd,
  * @param buf	data buffer
  */
 static int nand_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required,
+	int page)
 {
-	int page;
-	struct nand_drv *info;
-
-	info = (struct nand_drv *)nand_get_controller_data(chip);
-
-	page = (readl(&info->reg->addr_reg1) >> 16) |
-		(readl(&info->reg->addr_reg2) << 16);
-
 	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 	return 0;
 }
@@ -697,15 +690,9 @@ static int nand_read_page_raw(struct mtd_info *mtd,
  * @param buf	data buffer
  */
 static int nand_write_page_raw(struct mtd_info *mtd,
-		struct nand_chip *chip,	const uint8_t *buf, int oob_required)
+		struct nand_chip *chip,	const uint8_t *buf,
+		int oob_required, int page)
 {
-	int page;
-	struct nand_drv *info;
-
-	info = (struct nand_drv *)nand_get_controller_data(chip);
-	page = (readl(&info->reg->addr_reg1) >> 16) |
-		(readl(&info->reg->addr_reg2) << 16);
-
 	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
 	return 0;
 }
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index a4d5a62..dfbefc6 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -607,7 +607,7 @@ static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  * ECC will be calculated automatically
  */
 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			       const uint8_t *buf, int oob_required)
+			       const uint8_t *buf, int oob_required, int page)
 {
 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
 
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index e1df66b..34945fd 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -519,16 +519,16 @@ struct nand_ecc_ctrl {
 	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint8_t *buf, int oob_required, int page);
 	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf, int oob_required);
+			const uint8_t *buf, int oob_required, int page);
 	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint8_t *buf, int oob_required, int page);
 	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offs, uint32_t len, uint8_t *buf, int page);
 	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offset, uint32_t data_len,
-			const uint8_t *data_buf, int oob_required);
+			const uint8_t *data_buf, int oob_required, int page);
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf, int oob_required);
+			const uint8_t *buf, int oob_required, int page);
 	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			int page);
 	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
-- 
cgit v0.10.2


From ceee07b65875bb01bef55cba06940ef7afc1afba Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Mon, 30 May 2016 13:57:58 -0500
Subject: mtd: nand: Sync with Linux v4.6

Updates the NAND code to match Linux v4.6.  The previous sync was from
Linux v4.1 in commit d3963721d93fafa.

Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.

Signed-off-by: Scott Wood <oss@buserror.net>
Tested-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index a81b96d..75e8307 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -513,7 +513,7 @@ normal_check:
 			if (err_nbr == -1) {
 				dev_err(host->dev, "PMECC: Too many errors\n");
 				mtd->ecc_stats.failed++;
-				return -EIO;
+				return -EBADMSG;
 			} else {
 				pmecc_correct_data(mtd, buf_pos, ecc, i,
 					host->pmecc_bytes_per_sector, err_nbr);
@@ -562,7 +562,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	stat = pmecc_readl(host->pmecc, isr);
 	if (stat != 0)
 		if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
-			return -EIO;
+			return -EBADMSG;
 
 	return 0;
 }
@@ -1112,7 +1112,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		 * We can't correct so many errors */
 		dev_warn(host->dev, "atmel_nand : multiple errors detected."
 				" Unable to correct.\n");
-		return -EIO;
+		return -EBADMSG;
 	}
 
 	/* if there's a single bit error : we can correct it */
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index be9d666..48a8ca7 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -243,7 +243,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 					 "%d\n", find_byte, find_bit);
 				return 1;
 			} else {
-				return -1;
+				return -EBADMSG;
 			}
 		} else if (!(diff & (diff - 1))) {
 			/* Single bit ECC error in the ECC itself,
@@ -254,7 +254,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 		} else {
 			/* Uncorrectable error */
 			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
-			return -1;
+			return -EBADMSG;
 		}
 	}
 	return 0;
@@ -701,7 +701,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		return 0;
 	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
 		val = __raw_readl(&davinci_emif_regs->nanderrval1);
-		return -1;
+		return -EBADMSG;
 	}
 
 	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 3ae7545..601e744 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -48,8 +48,10 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
  * this macro allows us to convert from an MTD structure to our own
  * device context (denali) structure.
  */
-#define mtd_to_denali(m) \
-	container_of(mtd_to_nand(m), struct denali_nand_info, nand)
+static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
+{
+	return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
+}
 
 /*
  * These constants are defined by the driver to enable common driver
@@ -866,8 +868,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * by write_page above.
  */
 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required,
-				int page)
+				const uint8_t *buf, int oob_required, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
@@ -891,8 +892,8 @@ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * write_page() function above.
  */
 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-					const uint8_t *buf, int oob_required,
-					int page)
+				 const uint8_t *buf, int oob_required,
+				 int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
@@ -991,7 +992,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 			debug("  ECC error cause by erased block\n");
 			/* false alarm, return the 0xFF */
 		} else {
-			return -EIO;
+			return -EBADMSG;
 		}
 	}
 	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
@@ -1176,12 +1177,13 @@ static struct nand_ecclayout nand_oob;
 
 static int denali_init(struct denali_nand_info *denali)
 {
+	struct mtd_info *mtd = nand_to_mtd(&denali->nand);
 	int ret;
 
 	denali_hw_init(denali);
 
-	denali->mtd->name = "denali-nand";
-	denali->mtd->owner = THIS_MODULE;
+	mtd->name = "denali-nand";
+	mtd->owner = THIS_MODULE;
 
 	/* register the driver with the NAND core subsystem */
 	denali->nand.select_chip = denali_select_chip;
@@ -1195,7 +1197,7 @@ static int denali_init(struct denali_nand_info *denali)
 	 * this is the first stage in a two step process to register
 	 * with the nand subsystem
 	 */
-	if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) {
+	if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
 		ret = -ENXIO;
 		goto fail;
 	}
@@ -1241,13 +1243,13 @@ static int denali_init(struct denali_nand_info *denali)
 	nand_oob.eccbytes = denali->nand.ecc.bytes;
 	denali->nand.ecc.layout = &nand_oob;
 
-	writel(denali->mtd->erasesize / denali->mtd->writesize,
+	writel(mtd->erasesize / mtd->writesize,
 	       denali->flash_reg + PAGES_PER_BLOCK);
 	writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
 	       denali->flash_reg + DEVICE_WIDTH);
-	writel(denali->mtd->writesize,
+	writel(mtd->writesize,
 	       denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
-	writel(denali->mtd->oobsize,
+	writel(mtd->oobsize,
 	       denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
 	if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
 		writel(1, denali->flash_reg + DEVICES_CONNECTED);
@@ -1260,12 +1262,12 @@ static int denali_init(struct denali_nand_info *denali)
 	denali->nand.ecc.read_oob = denali_read_oob;
 	denali->nand.ecc.write_oob = denali_write_oob;
 
-	if (nand_scan_tail(denali->mtd)) {
+	if (nand_scan_tail(mtd)) {
 		ret = -ENXIO;
 		goto fail;
 	}
 
-	ret = nand_register(0, denali->mtd);
+	ret = nand_register(0, mtd);
 
 fail:
 	return ret;
@@ -1280,13 +1282,6 @@ static int __board_nand_init(void)
 		return -ENOMEM;
 
 	/*
-	 * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
-	 * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
-	 * still provides a "struct mtd_info nand_info" instance.
-	 */
-	denali->mtd = &denali->nand.mtd;
-
-	/*
 	 * In the future, these base addresses should be taken from
 	 * Device Tree or platform data.
 	 */
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index db1457a..0e098bd 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -436,7 +436,6 @@ struct nand_buf {
 #define DT		3
 
 struct denali_nand_info {
-	struct mtd_info *mtd;
 	struct nand_chip nand;
 	int flash_bank; /* currently selected chip */
 	int status;
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
index 1587413..c693032 100644
--- a/drivers/mtd/nand/denali_spl.c
+++ b/drivers/mtd/nand/denali_spl.c
@@ -41,7 +41,7 @@ static int wait_for_irq(uint32_t irq_mask)
 
 		if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
 			debug("Uncorrected ECC detected\n");
-			return -EIO;
+			return -EBADMSG;
 		}
 
 		if (intr_status & irq_mask)
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 362d393..8a8775c 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -100,7 +100,6 @@
 #define NFC_WPC_UNLOCK		(1 << 2)
 
 struct mpc5121_nfc_prv {
-	struct mtd_info mtd;
 	struct nand_chip chip;
 	int irq;
 	void __iomem *regs;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index d4e14b5..7221d0b 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -19,7 +19,6 @@
 #define DRIVER_NAME "mxc_nand"
 
 struct mxc_nand_host {
-	struct mtd_info			mtd;
 	struct nand_chip		*nand;
 
 	struct mxc_nand_regs __iomem	*regs;
@@ -681,7 +680,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				       mtd->writesize / nand_chip->subpagesize
 					    - subpages);
 			}
-			return -1;
+			return -EBADMSG;
 		}
 		ecc_status >>= 4;
 		subpages--;
@@ -713,7 +712,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 	if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 		MTDDEBUG(MTD_DEBUG_LEVEL0,
 		      "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
-		return -1;
+		return -EBADMSG;
 	}
 
 	return 0;
diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c
index 6ac2c96..841fb5b 100644
--- a/drivers/mtd/nand/mxc_nand_spl.c
+++ b/drivers/mtd/nand/mxc_nand_spl.c
@@ -232,7 +232,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf)
 	nfc_nand_read_page(page_address);
 
 	if (nfc_nand_check_ecc())
-		return -1;
+		return -EBADMSG;
 
 	src = (u32 *)&nfc->main_area[0][0];
 	dst = (u32 *)buf;
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 5291330..7be1f86 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -961,7 +961,7 @@ static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
  * Thus, this function is only called when we want *all* blocks to look good,
  * so it *always* return success.
  */
-static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
 {
 	return 0;
 }
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 62e70a7..74c563c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1,6 +1,4 @@
 /*
- *  drivers/mtd/nand.c
- *
  *  Overview:
  *   This is the generic MTD driver for NAND flash devices. It should be
  *   capable of working with almost all NAND chips currently available.
@@ -45,8 +43,6 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
-static bool is_module_text_address(unsigned long addr) {return 0;}
-
 /* Define default oob placement schemes for large and small page devices */
 static struct nand_ecclayout nand_oob_8 = {
 	.eccbytes = 3,
@@ -343,13 +339,12 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  * @mtd: MTD device structure
  * @ofs: offset from device start
- * @getchip: 0, if the chip is already selected
  *
  * Check, if the block is bad.
  */
-static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
 {
-	int page, chipnr, res = 0, i = 0;
+	int page, res = 0, i = 0;
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 bad;
 
@@ -358,15 +353,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 
 	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 
-	if (getchip) {
-		chipnr = (int)(ofs >> chip->chip_shift);
-
-		nand_get_device(mtd, FL_READING);
-
-		/* Select the NAND device */
-		chip->select_chip(mtd, chipnr);
-	}
-
 	do {
 		if (chip->options & NAND_BUSWIDTH_16) {
 			chip->cmdfunc(mtd, NAND_CMD_READOOB,
@@ -391,11 +377,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 		i++;
 	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 
-	if (getchip) {
-		chip->select_chip(mtd, -1);
-		nand_release_device(mtd);
-	}
-
 	return res;
 }
 
@@ -533,14 +514,12 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  * @mtd: MTD device structure
  * @ofs: offset from device start
- * @getchip: 0, if the chip is already selected
  * @allowbbt: 1, if its allowed to access the bbt area
  *
  * Check, if the block is bad. Either by reading the bad block table or
  * calling of the scan function.
  */
-static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
-			       int allowbbt)
+static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 
@@ -551,17 +530,22 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 	}
 
 	if (!chip->bbt)
-		return chip->block_bad(mtd, ofs, getchip);
+		return chip->block_bad(mtd, ofs);
 
 	/* Return info from the table */
 	return nand_isbad_bbt(mtd, ofs, allowbbt);
 }
 
-/* Wait for the ready pin, after a command. The timeout is caught later. */
+/**
+ * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
+ * @mtd: MTD device structure
+ *
+ * Wait for the ready pin after a command, and warn if a timeout occurs.
+ */
 void nand_wait_ready(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
-	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 	u32 time_start;
 
 	time_start = get_timer(0);
@@ -571,6 +555,9 @@ void nand_wait_ready(struct mtd_info *mtd)
 			if (chip->dev_ready(mtd))
 				break;
 	}
+
+	if (!chip->dev_ready(mtd))
+		pr_warn("timeout while waiting for chip to become ready\n");
 }
 EXPORT_SYMBOL_GPL(nand_wait_ready);
 
@@ -871,15 +858,13 @@ static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: MTD device structure
  * @chip: NAND chip structure
  *
- * Wait for command done. This applies to erase and program only. Erase can
- * take up to 400ms and program up to 20ms according to general NAND and
- * SmartMedia specs.
+ * Wait for command done. This applies to erase and program only.
  */
 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 
-	int status, state = chip->state;
-	unsigned long timeo = (state == FL_ERASING ? 400 : 20);
+	int status;
+	unsigned long timeo = 400;
 
 	led_trigger_event(nand_led_trigger, LED_FULL);
 
@@ -912,6 +897,135 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 	return status;
 }
 
+#define BITS_PER_BYTE 8
+
+/**
+ * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
+ * @buf: buffer to test
+ * @len: buffer length
+ * @bitflips_threshold: maximum number of bitflips
+ *
+ * Check if a buffer contains only 0xff, which means the underlying region
+ * has been erased and is ready to be programmed.
+ * The bitflips_threshold specify the maximum number of bitflips before
+ * considering the region is not erased.
+ * Note: The logic of this function has been extracted from the memweight
+ * implementation, except that nand_check_erased_buf function exit before
+ * testing the whole buffer if the number of bitflips exceed the
+ * bitflips_threshold value.
+ *
+ * Returns a positive number of bitflips less than or equal to
+ * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
+ * threshold.
+ */
+static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
+{
+	const unsigned char *bitmap = buf;
+	int bitflips = 0;
+	int weight;
+
+	for (; len && ((uintptr_t)bitmap) % sizeof(long);
+	     len--, bitmap++) {
+		weight = hweight8(*bitmap);
+		bitflips += BITS_PER_BYTE - weight;
+		if (unlikely(bitflips > bitflips_threshold))
+			return -EBADMSG;
+	}
+
+	for (; len >= 4; len -= 4, bitmap += 4) {
+		weight = hweight32(*((u32 *)bitmap));
+		bitflips += 32 - weight;
+		if (unlikely(bitflips > bitflips_threshold))
+			return -EBADMSG;
+	}
+
+	for (; len > 0; len--, bitmap++) {
+		weight = hweight8(*bitmap);
+		bitflips += BITS_PER_BYTE - weight;
+		if (unlikely(bitflips > bitflips_threshold))
+			return -EBADMSG;
+	}
+
+	return bitflips;
+}
+
+/**
+ * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
+ *				 0xff data
+ * @data: data buffer to test
+ * @datalen: data length
+ * @ecc: ECC buffer
+ * @ecclen: ECC length
+ * @extraoob: extra OOB buffer
+ * @extraooblen: extra OOB length
+ * @bitflips_threshold: maximum number of bitflips
+ *
+ * Check if a data buffer and its associated ECC and OOB data contains only
+ * 0xff pattern, which means the underlying region has been erased and is
+ * ready to be programmed.
+ * The bitflips_threshold specify the maximum number of bitflips before
+ * considering the region as not erased.
+ *
+ * Note:
+ * 1/ ECC algorithms are working on pre-defined block sizes which are usually
+ *    different from the NAND page size. When fixing bitflips, ECC engines will
+ *    report the number of errors per chunk, and the NAND core infrastructure
+ *    expect you to return the maximum number of bitflips for the whole page.
+ *    This is why you should always use this function on a single chunk and
+ *    not on the whole page. After checking each chunk you should update your
+ *    max_bitflips value accordingly.
+ * 2/ When checking for bitflips in erased pages you should not only check
+ *    the payload data but also their associated ECC data, because a user might
+ *    have programmed almost all bits to 1 but a few. In this case, we
+ *    shouldn't consider the chunk as erased, and checking ECC bytes prevent
+ *    this case.
+ * 3/ The extraoob argument is optional, and should be used if some of your OOB
+ *    data are protected by the ECC engine.
+ *    It could also be used if you support subpages and want to attach some
+ *    extra OOB data to an ECC chunk.
+ *
+ * Returns a positive number of bitflips less than or equal to
+ * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
+ * threshold. In case of success, the passed buffers are filled with 0xff.
+ */
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+				void *ecc, int ecclen,
+				void *extraoob, int extraooblen,
+				int bitflips_threshold)
+{
+	int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
+
+	data_bitflips = nand_check_erased_buf(data, datalen,
+					      bitflips_threshold);
+	if (data_bitflips < 0)
+		return data_bitflips;
+
+	bitflips_threshold -= data_bitflips;
+
+	ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
+	if (ecc_bitflips < 0)
+		return ecc_bitflips;
+
+	bitflips_threshold -= ecc_bitflips;
+
+	extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
+						  bitflips_threshold);
+	if (extraoob_bitflips < 0)
+		return extraoob_bitflips;
+
+	if (data_bitflips)
+		memset(data, 0xff, datalen);
+
+	if (ecc_bitflips)
+		memset(ecc, 0xff, ecclen);
+
+	if (extraoob_bitflips)
+		memset(extraoob, 0xff, extraooblen);
+
+	return data_bitflips + ecc_bitflips + extraoob_bitflips;
+}
+EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
+
 /**
  * nand_read_page_raw - [INTERN] read raw page data without ecc
  * @mtd: mtd info structure
@@ -1103,6 +1217,16 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 
 		stat = chip->ecc.correct(mtd, p,
 			&chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+						&chip->buffers->ecccode[i],
+						chip->ecc.bytes,
+						NULL, 0,
+						chip->ecc.strength);
+		}
+
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
 		} else {
@@ -1152,6 +1276,15 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 		int stat;
 
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, eccsize,
+						&ecc_code[i], eccbytes,
+						NULL, 0,
+						chip->ecc.strength);
+		}
+
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
 		} else {
@@ -1204,6 +1337,15 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, eccsize,
+						&ecc_code[i], eccbytes,
+						NULL, 0,
+						chip->ecc.strength);
+		}
+
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
 		} else {
@@ -1231,6 +1373,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccsteps = chip->ecc.steps;
+	int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 	uint8_t *p = buf;
 	uint8_t *oob = chip->oob_poi;
 	unsigned int max_bitflips = 0;
@@ -1250,19 +1393,29 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 		chip->read_buf(mtd, oob, eccbytes);
 		stat = chip->ecc.correct(mtd, p, oob, NULL);
 
-		if (stat < 0) {
-			mtd->ecc_stats.failed++;
-		} else {
-			mtd->ecc_stats.corrected += stat;
-			max_bitflips = max_t(unsigned int, max_bitflips, stat);
-		}
-
 		oob += eccbytes;
 
 		if (chip->ecc.postpad) {
 			chip->read_buf(mtd, oob, chip->ecc.postpad);
 			oob += chip->ecc.postpad;
 		}
+
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+							   oob - eccpadbytes,
+							   eccpadbytes,
+							   NULL, 0,
+							   chip->ecc.strength);
+		}
+
+		if (stat < 0) {
+			mtd->ecc_stats.failed++;
+		} else {
+			mtd->ecc_stats.corrected += stat;
+			max_bitflips = max_t(unsigned int, max_bitflips, stat);
+		}
 	}
 
 	/* Calculate remaining oob bytes */
@@ -1361,8 +1514,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 	int ret = 0;
 	uint32_t readlen = ops->len;
 	uint32_t oobreadlen = ops->ooblen;
-	uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
-		mtd->oobavail : mtd->oobsize;
+	uint32_t max_oobsize = mtd_oobavail(mtd, ops);
 
 	uint8_t *bufpoi, *oob, *buf;
 	int use_bufpoi;
@@ -1712,10 +1864,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 
 	stats = mtd->ecc_stats;
 
-	if (ops->mode == MTD_OPS_AUTO_OOB)
-		len = chip->ecc.layout->oobavail;
-	else
-		len = mtd->oobsize;
+	len = mtd_oobavail(mtd, ops);
 
 	if (unlikely(ops->ooboffs >= len)) {
 		pr_debug("%s: attempt to start read outside oob\n",
@@ -1845,8 +1994,7 @@ out:
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required,
-				int page)
+			       const uint8_t *buf, int oob_required, int page)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
 	if (oob_required)
@@ -1861,6 +2009,7 @@ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  *
  * We need a special oob layout and handling even when ECC isn't checked.
  */
@@ -1907,8 +2056,8 @@ static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  * @page: page number to write
  */
 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf, int oob_required,
-				  int page)
+				 const uint8_t *buf, int oob_required,
+				 int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -2029,6 +2178,7 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  *
  * The hw generator calculates the error syndrome automatically. Therefore we
  * need a special oob layout and handling.
@@ -2103,7 +2253,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 						  oob_required, page);
 	else if (subpage)
 		status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
-						  buf, oob_required, page);
+						 buf, oob_required, page);
 	else
 		status = chip->ecc.write_page(mtd, chip, buf, oob_required,
 					      page);
@@ -2145,7 +2295,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * @oob: oob data buffer
  * @len: oob data write length
  * @ops: oob ops structure
- * @page: page number to write
  */
 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
 			      struct mtd_oob_ops *ops)
@@ -2214,8 +2363,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 	uint32_t writelen = ops->len;
 
 	uint32_t oobwritelen = ops->ooblen;
-	uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
-				mtd->oobavail : mtd->oobsize;
+	uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
 
 	uint8_t *oob = ops->oobbuf;
 	uint8_t *buf = ops->datbuf;
@@ -2404,10 +2552,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 	pr_debug("%s: to = 0x%08x, len = %i\n",
 			 __func__, (unsigned int)to, (int)ops->ooblen);
 
-	if (ops->mode == MTD_OPS_AUTO_OOB)
-		len = chip->ecc.layout->oobavail;
-	else
-		len = mtd->oobsize;
+	len = mtd_oobavail(mtd, ops);
 
 	/* Do not allow write past end of page */
 	if ((ops->ooboffs + ops->ooblen) > len) {
@@ -2597,7 +2742,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 
 		/* Check if we have a bad block, we do not erase bad blocks! */
 		if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
-					chip->page_shift, 0, allowbbt)) {
+					chip->page_shift, allowbbt)) {
 			pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
 				    __func__, page);
 			instr->state = MTD_ERASE_FAILED;
@@ -2684,7 +2829,20 @@ static void nand_sync(struct mtd_info *mtd)
  */
 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
 {
-	return nand_block_checkbad(mtd, offs, 1, 0);
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int chipnr = (int)(offs >> chip->chip_shift);
+	int ret;
+
+	/* Select the NAND device */
+	nand_get_device(mtd, FL_READING);
+	chip->select_chip(mtd, chipnr);
+
+	ret = nand_block_checkbad(mtd, offs, 0);
+
+	chip->select_chip(mtd, -1);
+	nand_release_device(mtd);
+
+	return ret;
 }
 
 /**
@@ -2756,9 +2914,6 @@ static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EINVAL;
 #endif
 
-	/* clear the sub feature parameters */
-	memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
-
 	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
 	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
 		*subfeature_param++ = chip->read_byte(mtd);
@@ -3491,7 +3646,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 			if (find_full_id_nand(mtd, chip, type, id_data, &busw))
 				goto ident_done;
 		} else if (*dev_id == type->dev_id) {
-				break;
+			break;
 		}
 	}
 
@@ -3514,10 +3669,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 
 	chip->chipsize = (uint64_t)type->chipsize << 20;
 
-	if (!type->pagesize && chip->init_size) {
-		/* Set the pagesize, oobsize, erasesize by the driver */
-		busw = chip->init_size(mtd, chip, id_data);
-	} else if (!type->pagesize) {
+	if (!type->pagesize) {
 		/* Decode parameters from extended ID */
 		nand_decode_ext_id(mtd, chip, id_data, &busw);
 	} else {
@@ -3621,7 +3773,6 @@ ident_done:
  * This is the first phase of the normal nand_scan() function. It reads the
  * flash ID and sets up MTD fields accordingly.
  *
- * The mtd->owner field must be set to the module of the caller.
  */
 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
 		    struct nand_flash_dev *table)
@@ -3797,7 +3948,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 			ecc->write_oob = nand_write_oob_std;
 		if (!ecc->read_subpage)
 			ecc->read_subpage = nand_read_subpage;
-		if (!ecc->write_subpage)
+		if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
 			ecc->write_subpage = nand_write_subpage_hwecc;
 
 	case NAND_ECC_HW_SYNDROME:
@@ -3875,10 +4026,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 		}
 
 		/* See nand_bch_init() for details. */
-		ecc->bytes = DIV_ROUND_UP(
-				ecc->strength * fls(8 * ecc->size), 8);
-		ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
-					       &ecc->layout);
+		ecc->bytes = 0;
+		ecc->priv = nand_bch_init(mtd);
 		if (!ecc->priv) {
 			pr_warn("BCH ECC initialization failed!\n");
 			BUG();
@@ -3913,11 +4062,11 @@ int nand_scan_tail(struct mtd_info *mtd)
 	 * The number of bytes available for a client to place data into
 	 * the out of band area.
 	 */
-	ecc->layout->oobavail = 0;
-	for (i = 0; ecc->layout->oobfree[i].length
-			&& i < ARRAY_SIZE(ecc->layout->oobfree); i++)
-		ecc->layout->oobavail += ecc->layout->oobfree[i].length;
-	mtd->oobavail = ecc->layout->oobavail;
+	mtd->oobavail = 0;
+	if (ecc->layout) {
+		for (i = 0; ecc->layout->oobfree[i].length; i++)
+			mtd->oobavail += ecc->layout->oobfree[i].length;
+	}
 
 	/* ECC sanity check: warn if it's too weak */
 	if (!nand_ecc_strength_good(mtd))
@@ -4002,18 +4151,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 }
 EXPORT_SYMBOL(nand_scan_tail);
 
-/*
- * is_module_text_address() isn't exported, and it's mostly a pointless
- * test if this is a module _anyway_ -- they'd have to try _really_ hard
- * to call us from in-kernel code if the core NAND support is modular.
- */
-#ifdef MODULE
-#define caller_is_module() (1)
-#else
-#define caller_is_module() \
-	is_module_text_address((unsigned long)__builtin_return_address(0))
-#endif
-
 /**
  * nand_scan - [NAND Interface] Scan for the NAND device
  * @mtd: MTD device structure
@@ -4021,19 +4158,12 @@ EXPORT_SYMBOL(nand_scan_tail);
  *
  * This fills out all the uninitialized function pointers with the defaults.
  * The flash ID is read and the mtd/chip structures are filled with the
- * appropriate values. The mtd->owner field must be set to the module of the
- * caller.
+ * appropriate values.
  */
 int nand_scan(struct mtd_info *mtd, int maxchips)
 {
 	int ret;
 
-	/* Many callers got this wrong, so check for it for a while... */
-	if (!mtd->owner && caller_is_module()) {
-		pr_crit("%s called with NULL mtd->owner!\n", __func__);
-		BUG();
-	}
-
 	ret = nand_scan_ident(mtd, maxchips, NULL);
 	if (!ret)
 		ret = nand_scan_tail(mtd);
@@ -4041,9 +4171,6 @@ int nand_scan(struct mtd_info *mtd, int maxchips)
 }
 EXPORT_SYMBOL(nand_scan);
 
-module_init(nand_base_init);
-module_exit(nand_base_exit);
-
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 152f3bc..74c4c9a 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -1,6 +1,4 @@
 /*
- *  drivers/mtd/nand_bbt.c
- *
  *  Overview:
  *   Bad block table support for the NAND driver
  *
@@ -65,7 +63,6 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/bbm.h>
 #include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
 #include <linux/bitops.h>
 #include <linux/string.h>
 
@@ -718,7 +715,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		/* Must we save the block contents? */
 		if (td->options & NAND_BBT_SAVECONTENT) {
 			/* Make it block aligned */
-			to &= ~((loff_t)((1 << this->bbt_erase_shift) - 1));
+			to &= ~(((loff_t)1 << this->bbt_erase_shift) - 1);
 			len = 1 << this->bbt_erase_shift;
 			res = mtd_read(mtd, to, len, &retlen, buf);
 			if (res < 0) {
@@ -1073,15 +1070,15 @@ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
  * The bad block table memory is allocated here. It must be freed by calling
  * the nand_free_bbt function.
  */
-int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+static int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
 	struct nand_chip *this = mtd_to_nand(mtd);
-	int len, res = 0;
+	int len, res;
 	uint8_t *buf;
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
 
-	len = mtd->size >> (this->bbt_erase_shift + 2);
+	len = (mtd->size >> (this->bbt_erase_shift + 2)) ? : 1;
 	/*
 	 * Allocate memory (2bit per block) and clear the memory bad block
 	 * table.
@@ -1097,10 +1094,9 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	if (!td) {
 		if ((res = nand_memory_bbt(mtd, bd))) {
 			pr_err("nand_bbt: can't scan flash and build the RAM-based BBT\n");
-			kfree(this->bbt);
-			this->bbt = NULL;
+			goto err;
 		}
-		return res;
+		return 0;
 	}
 	verify_bbt_descr(mtd, td);
 	verify_bbt_descr(mtd, md);
@@ -1110,9 +1106,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	len += (len >> this->page_shift) * mtd->oobsize;
 	buf = vmalloc(len);
 	if (!buf) {
-		kfree(this->bbt);
-		this->bbt = NULL;
-		return -ENOMEM;
+		res = -ENOMEM;
+		goto err;
 	}
 
 	/* Is the bbt at a given page? */
@@ -1124,6 +1119,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	}
 
 	res = check_create(mtd, buf, bd);
+	if (res)
+		goto err;
 
 	/* Prevent the bbt regions from erasing / writing */
 	mark_bbt_region(mtd, td);
@@ -1131,6 +1128,11 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 		mark_bbt_region(mtd, md);
 
 	vfree(buf);
+	return 0;
+
+err:
+	kfree(this->bbt);
+	this->bbt = NULL;
 	return res;
 }
 
@@ -1369,5 +1371,3 @@ int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
 
 	return ret;
 }
-
-EXPORT_SYMBOL(nand_scan_bbt);
diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c
index d7f6ce0..c145203 100644
--- a/drivers/mtd/nand/nand_bch.c
+++ b/drivers/mtd/nand/nand_bch.c
@@ -86,7 +86,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 		}
 	} else if (count < 0) {
 		printk(KERN_ERR "ecc unrecoverable error\n");
-		count = -1;
+		count = -EBADMSG;
 	}
 	return count;
 }
@@ -94,9 +94,6 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 /**
  * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction
  * @mtd:	MTD block structure
- * @eccsize:	ecc block size in bytes
- * @eccbytes:	ecc length in bytes
- * @ecclayout:	output default layout
  *
  * Returns:
  *  a pointer to a new NAND BCH control structure, or NULL upon failure
@@ -110,14 +107,21 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
  * @eccsize = 512  (thus, m=13 is the smallest integer such that 2^m-1 > 512*8)
  * @eccbytes = 7   (7 bytes are required to store m*t = 13*4 = 52 bits)
  */
-struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
-	      struct nand_ecclayout **ecclayout)
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
 {
+	struct nand_chip *nand = mtd_to_nand(mtd);
 	unsigned int m, t, eccsteps, i;
-	struct nand_ecclayout *layout;
+	struct nand_ecclayout *layout = nand->ecc.layout;
 	struct nand_bch_control *nbc = NULL;
 	unsigned char *erased_page;
+	unsigned int eccsize = nand->ecc.size;
+	unsigned int eccbytes = nand->ecc.bytes;
+	unsigned int eccstrength = nand->ecc.strength;
+
+	if (!eccbytes && eccstrength) {
+		eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8);
+		nand->ecc.bytes = eccbytes;
+	}
 
 	if (!eccsize || !eccbytes) {
 		printk(KERN_WARNING "ecc parameters not supplied\n");
@@ -145,7 +149,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 	eccsteps = mtd->writesize/eccsize;
 
 	/* if no ecc placement scheme was provided, build one */
-	if (!*ecclayout) {
+	if (!layout) {
 
 		/* handle large page devices only */
 		if (mtd->oobsize < 64) {
@@ -171,7 +175,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 		layout->oobfree[0].offset = 2;
 		layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
 
-		*ecclayout = layout;
+		nand->ecc.layout = layout;
 	}
 
 	/* sanity checks */
@@ -179,7 +183,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 		printk(KERN_WARNING "eccsize %u is too large\n", eccsize);
 		goto fail;
 	}
-	if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) {
+	if (layout->eccbytes != (eccsteps*eccbytes)) {
 		printk(KERN_WARNING "invalid ecc layout\n");
 		goto fail;
 	}
@@ -203,6 +207,9 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 	for (i = 0; i < eccbytes; i++)
 		nbc->eccmask[i] ^= 0xff;
 
+	if (!eccstrength)
+		nand->ecc.strength = (eccbytes * 8) / fls(8 * eccsize);
+
 	return nbc;
 fail:
 	nand_bch_free(nbc);
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index fdd0074..561d2cd 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -1,6 +1,4 @@
 /*
- *  drivers/mtd/nandids.c
- *
  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -41,6 +39,10 @@ struct nand_flash_dev nand_flash_ids[] = {
 	 * listed by full ID. We list them first so that we can easily identify
 	 * the most specific match.
 	 */
+	{"TC58NVG0S3E 1G 3.3V 8-bit",
+		{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
+		  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
+		  2 },
 	{"TC58NVG2S0F 4G 3.3V 8-bit",
 		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
 		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
@@ -58,8 +60,8 @@ struct nand_flash_dev nand_flash_ids[] = {
 		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
 	{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
-		  SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
-		  4 },
+		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+		  NAND_ECC_INFO(40, SZ_1K), 4 },
 
 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index ee353c7..0a9849e 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -1,6 +1,6 @@
 /*
  * Overview:
- *   Platform independend driver for NDFC (NanD Flash Controller)
+ *   Platform independent driver for NDFC (NanD Flash Controller)
  *   integrated into IBM/AMCC PPC4xx cores
  *
  * (C) Copyright 2006-2009
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index cac9eea..37c4341 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -163,7 +163,7 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 				return 0;
 			printf("Error: Bad compare! failed\n");
 			/* detected 2 bit error */
-			return -1;
+			return -EBADMSG;
 		}
 	}
 	return 0;
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index 2a0da6e..dd742a6 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -104,7 +104,7 @@ static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 		return 0;
 
 	printf("s3c24x0_nand_correct_data: not implemented\n");
-	return -1;
+	return -EBADMSG;
 }
 #endif
 
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index dfbefc6..f99bdaf 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -146,7 +146,6 @@ enum vf610_nfc_alt_buf {
 };
 
 struct vf610_nfc {
-	struct mtd_info *mtd;
 	struct nand_chip chip;
 	void __iomem *regs;
 	uint buf_offset;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 9da77ec..cf20674 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -278,6 +278,11 @@ struct mtd_info {
 	int usecount;
 };
 
+static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
+{
+	return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
+}
+
 int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
 #ifndef __UBOOT__
 int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 34945fd..b5a02c3 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -25,6 +25,8 @@
 
 struct mtd_info;
 struct nand_flash_dev;
+struct device_node;
+
 /* Scan and identify a NAND device */
 extern int nand_scan(struct mtd_info *mtd, int max_chips);
 /*
@@ -144,6 +146,14 @@ typedef enum {
 /* Enable Hardware ECC before syndrome is read back from flash */
 #define NAND_ECC_READSYN	2
 
+/*
+ * Enable generic NAND 'page erased' check. This check is only done when
+ * ecc.correct() returns -EBADMSG.
+ * Set this flag if your implementation does not fix bitflips in erased
+ * pages and you want to rely on the default implementation.
+ */
+#define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
+
 /* Bit mask for flags passed to do_nand_read_ecc */
 #define NAND_GET_DEVICE		0x80
 
@@ -179,6 +189,12 @@ typedef enum {
 /* Device supports subpage reads */
 #define NAND_SUBPAGE_READ	0x00001000
 
+/*
+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
+ * patterns.
+ */
+#define NAND_NEED_SCRAMBLING	0x00002000
+
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 
@@ -203,6 +219,11 @@ typedef enum {
  * before calling nand_scan_tail.
  */
 #define NAND_BUSWIDTH_AUTO      0x00080000
+/*
+ * This option could be defined by controller drivers to protect against
+ * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
+ */
+#define NAND_USE_BOUNCE_BUFFER	0x00100000
 
 /* Options set by nand scan */
 /* bbt has already been read */
@@ -292,15 +313,15 @@ struct nand_onfi_params {
 	__le16 t_r;
 	__le16 t_ccs;
 	__le16 src_sync_timing_mode;
-	__le16 src_ssync_features;
+	u8 src_ssync_features;
 	__le16 clk_pin_capacitance_typ;
 	__le16 io_pin_capacitance_typ;
 	__le16 input_pin_capacitance_typ;
 	u8 input_pin_capacitance_max;
 	u8 driver_strength_support;
 	__le16 t_int_r;
-	__le16 t_ald;
-	u8 reserved4[7];
+	__le16 t_adl;
+	u8 reserved4[8];
 
 	/* vendor */
 	__le16 vendor_revision;
@@ -423,7 +444,7 @@ struct nand_jedec_params {
 	__le16 input_pin_capacitance_typ;
 	__le16 clk_pin_capacitance_typ;
 	u8 driver_strength_support;
-	__le16 t_ald;
+	__le16 t_adl;
 	u8 reserved4[36];
 
 	/* ECC and endurance block */
@@ -466,12 +487,19 @@ struct nand_hw_control {
  * @total:	total number of ECC bytes per page
  * @prepad:	padding information for syndrome based ECC generators
  * @postpad:	padding information for syndrome based ECC generators
+ * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
  * @layout:	ECC layout control struct pointer
  * @priv:	pointer to private ECC control data
  * @hwctl:	function to control hardware ECC generator. Must only
  *		be provided if an hardware ECC is available
  * @calculate:	function for ECC calculation or readback from ECC hardware
- * @correct:	function for ECC correction, matching to ECC generator (sw/hw)
+ * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
+ *		Should return a positive number representing the number of
+ *		corrected bitflips, -EBADMSG if the number of bitflips exceed
+ *		ECC strength, or any other error code if the error is not
+ *		directly related to correction.
+ *		If -EBADMSG is returned the input buffers should be left
+ *		untouched.
  * @read_page_raw:	function to read a raw page without ECC. This function
  *			should hide the specific layout used by the ECC
  *			controller and always return contiguous in-band and
@@ -509,6 +537,7 @@ struct nand_ecc_ctrl {
 	int strength;
 	int prepad;
 	int postpad;
+	unsigned int options;
 	struct nand_ecclayout	*layout;
 	void *priv;
 	void (*hwctl)(struct mtd_info *mtd, int mode);
@@ -556,6 +585,7 @@ struct nand_buffers {
 
 /**
  * struct nand_chip - NAND Private Flash Chip Data
+ * @mtd:		MTD device registered to the MTD framework
  * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
  *			flash device
  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
@@ -571,10 +601,6 @@ struct nand_buffers {
  * @block_markbad:	[REPLACEABLE] mark a block bad
  * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
  *			ALE/CLE/nCE. Also used to write command and address
- * @init_size:		[BOARDSPECIFIC] hardwarespecific function for setting
- *			mtd->oobsize, mtd->writesize and so on.
- *			@id_data contains the 8 bytes values of NAND_CMD_READID.
- *			Return with the bus width.
  * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
  *			device ready/busy line. If set to NULL no access to
  *			ready/busy is available and the ready/busy information
@@ -669,11 +695,9 @@ struct nand_chip {
 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 	void (*select_chip)(struct mtd_info *mtd, int chip);
-	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+	int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
 	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
-	int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
-			u8 *id_data);
 	int (*dev_ready)(struct mtd_info *mtd);
 	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 			int page_addr);
@@ -873,7 +897,6 @@ struct nand_manufacturers {
 extern struct nand_flash_dev nand_flash_ids[];
 extern struct nand_manufacturers nand_manuf_ids[];
 
-extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 extern int nand_default_bbt(struct mtd_info *mtd);
 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
@@ -898,7 +921,6 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  * @chip_delay:		R/B delay value in us
  * @options:		Option flags, e.g. 16bit buswidth
  * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
- * @ecclayout:		ECC layout info structure
  * @part_probe_types:	NULL-terminated array of probe types
  */
 struct platform_nand_chip {
@@ -906,7 +928,6 @@ struct platform_nand_chip {
 	int chip_offset;
 	int nr_partitions;
 	struct mtd_partition *partitions;
-	struct nand_ecclayout *ecclayout;
 	int chip_delay;
 	unsigned int options;
 	unsigned int bbt_options;
@@ -955,15 +976,6 @@ struct platform_nand_data {
 	struct platform_nand_ctrl ctrl;
 };
 
-/* Some helpers to access the data structures */
-static inline
-struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
-{
-	struct nand_chip *chip = mtd->priv;
-
-	return chip->priv;
-}
-
 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 /* return the supported features. */
 static inline int onfi_feature(struct nand_chip *chip)
@@ -1081,4 +1093,9 @@ struct nand_sdr_timings {
 
 /* get timing characteristics from ONFI timing mode. */
 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
+
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+				void *ecc, int ecclen,
+				void *extraoob, int extraooblen,
+				int threshold);
 #endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/nand_bch.h b/include/linux/mtd/nand_bch.h
index d8754dd..8ea6b04 100644
--- a/include/linux/mtd/nand_bch.h
+++ b/include/linux/mtd/nand_bch.h
@@ -32,9 +32,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
 /*
  * Initialize BCH encoder/decoder
  */
-struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
-	      unsigned int eccbytes, struct nand_ecclayout **ecclayout);
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd);
 /*
  * Release BCH encoder/decoder resources
  */
@@ -55,12 +53,10 @@ static inline int
 nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 		      unsigned char *read_ecc, unsigned char *calc_ecc)
 {
-	return -1;
+	return -ENOTSUPP;
 }
 
-static inline struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
-	      unsigned int eccbytes, struct nand_ecclayout **ecclayout)
+static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
 {
 	return NULL;
 }
-- 
cgit v0.10.2


From 667067faa18334f1e28c01b47530b5cce1b6182f Mon Sep 17 00:00:00 2001
From: Max Krummenacher <max.oss.09@gmail.com>
Date: Mon, 30 May 2016 16:28:28 +0200
Subject: nand: fix nand torture to use changed mtd api

The mtd subsystem deprecated and renamed the direct use of the mtd_info
struct's functionpointers. Instead the corresponding mtd_xxx function
should be used.

See also:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=3c3c10bba1e4ccb75b41442e45c1a072f6cded19

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 9b61087..5bba66a 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -847,7 +847,7 @@ int nand_torture(struct mtd_info *mtd, loff_t offset)
 	}
 
 	for (i = 0; i < patt_count; i++) {
-		err = mtd->erase(mtd, &instr);
+		err = mtd_erase(mtd, &instr);
 		if (err) {
 			printf("%s: erase() failed for block at 0x%llx: %d\n",
 				mtd->name, instr.addr, err);
@@ -855,7 +855,7 @@ int nand_torture(struct mtd_info *mtd, loff_t offset)
 		}
 
 		/* Make sure the block contains only 0xff bytes */
-		err = mtd->read(mtd, offset, mtd->erasesize, &retlen, buf);
+		err = mtd_read(mtd, offset, mtd->erasesize, &retlen, buf);
 		if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
 			printf("%s: read() failed for block at 0x%llx: %d\n",
 				mtd->name, instr.addr, err);
@@ -872,14 +872,14 @@ int nand_torture(struct mtd_info *mtd, loff_t offset)
 
 		/* Write a pattern and check it */
 		memset(buf, patterns[i], mtd->erasesize);
-		err = mtd->write(mtd, offset, mtd->erasesize, &retlen, buf);
+		err = mtd_write(mtd, offset, mtd->erasesize, &retlen, buf);
 		if (err || retlen != mtd->erasesize) {
 			printf("%s: write() failed for block at 0x%llx: %d\n",
 				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = mtd->read(mtd, offset, mtd->erasesize, &retlen, buf);
+		err = mtd_read(mtd, offset, mtd->erasesize, &retlen, buf);
 		if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
 			printf("%s: read() failed for block at 0x%llx: %d\n",
 				mtd->name, instr.addr, err);
-- 
cgit v0.10.2


From ed4708aaeaf74008d199866bfbd450d91439a9cf Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Wed, 25 May 2016 12:41:48 -0400
Subject: powerpc/board: SPL: Enable malloc flag in global data.

For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT
flag in global data after allocating memory using mem_malloc_init.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index 3f7cc03..fabc783 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -91,6 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 3d31d41..d8d73c7 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -57,6 +57,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 	/* relocate environment function pointers etc. */
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index eb8e567..f858408 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -72,6 +72,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 89ef95a..04db767 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -86,6 +86,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 0142746..76a3cf4 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -83,6 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index 073ff2d..d59d343 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -120,6 +120,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da97c44..bd3cbbf 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -107,6 +107,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 81f48c4..4b35af6 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -98,6 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_initialize(bd);
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 55a0f8f..bb02dab 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -106,6 +106,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index f63366b..2ff05a2 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -76,6 +76,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index d52059a..6ca0f03 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -116,6 +116,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 4c1e0cc..b148a7f 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -80,6 +80,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 	mmc_initialize(bd);
 	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-- 
cgit v0.10.2


From 534992827756c3a1ab49823ca487702a954fe433 Mon Sep 17 00:00:00 2001
From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Tue, 31 May 2016 15:39:06 +0800
Subject: board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl
 boot

We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index eb10a6f..31b186e 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -179,15 +179,13 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }
 
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 2d4d10f..fa1394d 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -172,14 +172,13 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index adf9fd5..b13692b 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -234,12 +234,12 @@ phys_size_t initdram(int board_type)
 	puts("Initializing....using SPD\n");
 #endif
 	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index cf79d2d..22d6a5f 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -124,15 +124,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index f1aff54..f96470f 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -108,13 +108,12 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 	return dram_size;
 }
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 053f128..f6c8ca3 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -101,12 +101,12 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 62d58c5..d533924 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,13 +117,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 27b37b5..230f031 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -110,13 +110,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 	return dram_size;
 }
-- 
cgit v0.10.2


From b7707b043ebbf88fe0fb49442db9316ded3a0740 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Mon, 23 May 2016 06:49:21 -0400
Subject: arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.

Replace a number of array length calculations with the ARRAY_SIZE()
macro, for clarity.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
index 6451ea9..68c5f8a 100644
--- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c
+++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
@@ -70,7 +70,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 		mddrc_config = &default_mddrc_config;
 	if (dram_init_seq == NULL) {
 		dram_init_seq = default_init_seq;
-		seq_sz = sizeof(default_init_seq)/sizeof(u32);
+		seq_sz = ARRAY_SIZE(default_init_seq);
 	}
 
 	/* Initialize IO Control */
diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c
index a9bb5ad..55130f7 100644
--- a/arch/powerpc/cpu/mpc8260/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8260/cpu_init.c
@@ -253,7 +253,7 @@ int prt_8260_rsr (void)
 		RSR_ESRS, "External Soft"}, {
 		RSR_EHRS, "External Hard"}
 	};
-	static int n = sizeof bits / sizeof bits[0];
+	static int n = ARRAY_SIZE(bits);
 	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index 9bb395e..a11ad1e 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -362,7 +362,7 @@ int fec_initialize(bd_t *bis)
 	struct eth_device* dev;
 	int i;
 
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 	{
 		dev = (struct eth_device*) malloc(sizeof *dev);
 		memset(dev, 0, sizeof *dev);
@@ -432,7 +432,7 @@ static elbt_prdesc rxeacc_descs[] = {
 	{ offsetof(elbt_rxeacc, badlen),	"Bad Frame Length"	},
 	{ offsetof(elbt_rxeacc, badbit),	"Data Compare Errors"	},
 };
-static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
+static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs);
 
 typedef
 	struct {
@@ -449,7 +449,7 @@ static elbt_prdesc txeacc_descs[] = {
 	{ offsetof(elbt_txeacc, un),		"Underrun"		},
 	{ offsetof(elbt_txeacc, csl),		"Carrier Sense Lost"	},
 };
-static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
+static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs);
 
 typedef
 	struct {
@@ -500,7 +500,7 @@ static elbt_prdesc epram_descs[] = {
 	{ offsetof(fcc_enet_t, fen_p512c),	"512-1023 Octet Frames"	},
 	{ offsetof(fcc_enet_t, fen_p1024c),	"1024-1518 Octet Frames"},
 };
-static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
+static int epram_ndesc = ARRAY_SIZE(epram_descs);
 
 /*
  * given an elbt_prdesc array and an array of base addresses, print
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 0791043..f911275 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -484,7 +484,7 @@ int prt_83xx_rsr(void)
 		RSR_SRS,  "External/Internal Soft"}, {
 		RSR_HRS,  "External/Internal Hard"}
 	};
-	static int n = sizeof bits / sizeof bits[0];
+	static int n = ARRAY_SIZE(bits);
 	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 2e91f51..5498c19 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -412,7 +412,7 @@ int get_clocks(void)
 #endif
 
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
-	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
+	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
 		/* corecnf_tab_index is too high, possibly wrong value */
 		return -11;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 14358ae..51f1bee 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -424,7 +424,7 @@ int fec_initialize(bd_t *bis)
 	struct eth_device* dev;
 	int i;
 
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 	{
 		dev = (struct eth_device*) malloc(sizeof *dev);
 		memset(dev, 0, sizeof *dev);
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index ea4ab3a..f1ae358 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -137,7 +137,7 @@ int fec_initialize(bd_t *bis)
 	struct ether_fcc_info_s *efis;
 	int             i;
 
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
 
 		dev = malloc(sizeof(*dev));
 		if (dev == NULL)
@@ -879,7 +879,7 @@ void mii_init (void)
 
 	/* Setup the pin configuration of the FEC(s)
 	*/
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 		fec_pin_init(ether_fcc_info[i].ether_index);
 }
 
diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c
index 339d38a..a42327e 100644
--- a/arch/powerpc/cpu/ppc4xx/reginfo.c
+++ b/arch/powerpc/cpu/ppc4xx/reginfo.c
@@ -321,7 +321,7 @@ void ppc4xx_reginfo(void)
 	PRINT_DCR(OPB2PLB40_BCTRL);
 	PRINT_DCR(P4P3BO0_CFG);
 #endif
-	n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]);
+	n = ARRAY_SIZE(ppc4xx_reg);
 	for (i = 0; i < n; i++) {
 		value = 0;
 		type = ppc4xx_reg[i].type;
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index d4ef36d..cd63456 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -33,7 +33,7 @@ sdram_conf_t mb0cf[] = {
 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #endif
 
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
 
 #ifdef CONFIG_SYS_SDRAM_CASL
 static ulong ns2clks(ulong ns)
@@ -266,7 +266,7 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #define CONFIG_SYS_SDRAM0_CFG0		0x82000000 /* DCEN=1, PMUD=0, 64-bit */
 #endif
 
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
 
 #define NUM_TRIES 64
 #define NUM_READS 10
-- 
cgit v0.10.2


From 07d31f8f98fb350776c78a681ef27fd8ee288acd Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 25 May 2016 15:15:20 +0200
Subject: dm: gpio: Add driver for MPC85XX GPIO controller

This patch adds a driver for the built-in GPIO controller of the MPC85XX
SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller@fc00 {
      #gpio-cells = <2>;
      compatible = "fsl,pq3-gpio";
      reg = <0xfc00 0x100>
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index da7352a..41b6677 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARCH_MX85XX_GPIO_H
 #define __ASM_ARCH_MX85XX_GPIO_H
 
+#ifndef CONFIG_MPC85XX_GPIO
 #include <asm/mpc85xx_gpio.h>
+#endif
 
 #endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 07d2adf..c045a24 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -265,6 +265,7 @@ typedef struct ccsr_pcix {
 #define PIWAR_WRITE_SNOOP	0x00005000
 #define PIWAR_MEM_2G		0x0000001e
 
+#ifndef CONFIG_MPC85XX_GPIO
 typedef struct ccsr_gpio {
 	u32	gpdir;
 	u32	gpodr;
@@ -273,6 +274,7 @@ typedef struct ccsr_gpio {
 	u32	gpimr;
 	u32	gpicr;
 } ccsr_gpio_t;
+#endif
 
 /* L2 Cache Registers */
 typedef struct ccsr_l2cache {
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c..b674a47 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -173,4 +173,30 @@ config DM_PCA953X
 
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
+
+config MPC85XX_GPIO
+	bool "Freescale MPC85XX GPIO driver"
+	depends on DM_GPIO
+	help
+	  This driver supports the built-in GPIO controller of MPC85XX CPUs.
+	  Each GPIO bank is identified by its own entry in the device tree,
+	  i.e.
+
+	  gpio-controller@fc00 {
+		#gpio-cells = <2>;
+		compatible = "fsl,pq3-gpio";
+		reg = <0xfc00 0x100>
+	  }
+
+	  By default, each bank is assumed to have 32 GPIOs, but the ngpios
+	  setting is honored, so the number of GPIOs for each bank is
+	  configurable to match the actual GPIO count of the SoC (e.g. the
+	  32/32/23 banks of the P1022 SoC).
+
+	  The standard functions of input/output mode, and output value setting
+	  are supported; the open-drain capability of the controller is not
+	  supported yet.
+
+	  The driver has been tested on MPC85XX, but it is likely that other
+	  PowerQUICC III devices will work as well.
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef..21b2cc2 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
+obj-$(CONFIG_MPC85XX_GPIO)	+= mpc85xx_gpio.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
 obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
new file mode 100644
index 0000000..17755df
--- /dev/null
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ *
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <mapmem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+};
+
+struct mpc85xx_gpio_data {
+	/* The bank's register base in memory */
+	struct ccsr_gpio __iomem *base;
+	/* The address of the registers; used to identify the bank */
+	ulong addr;
+	/* The GPIO count of the bank */
+	uint gpio_count;
+	/* The GPDAT register cannot be used to determine the value of output
+	 * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
+	 * for output pins */
+	u32 dat_shadow;
+};
+
+inline u32 gpio_mask(unsigned gpio) {
+	return (1U << (31 - (gpio)));
+}
+
+static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+{
+	return in_be32(&base->gpdat) & mask;
+}
+
+static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+{
+	return in_be32(&base->gpdir) & mask;
+}
+
+static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
+{
+	clrbits_be32(&base->gpdat, gpios);
+	/* GPDIR register 0 -> input */
+	clrbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
+{
+	clrbits_be32(&base->gpdat, gpios);
+	/* GPDIR register 1 -> output */
+	setbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
+{
+	setbits_be32(&base->gpdat, gpios);
+	/* GPDIR register 1 -> output */
+	setbits_be32(&base->gpdir, gpios);
+}
+
+static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
+	return 0;
+}
+
+static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio,
+				  int value)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	if (value) {
+		data->dat_shadow |= gpio_mask(gpio);
+		mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
+	} else {
+		data->dat_shadow &= ~gpio_mask(gpio);
+		mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
+	}
+	return 0;
+}
+
+static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio,
+					 int value)
+{
+	return mpc85xx_gpio_set_value(dev, gpio, value);
+}
+
+static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+		/* Output -> use shadowed value */
+		return !!(data->dat_shadow & gpio_mask(gpio));
+	} else {
+		/* Input -> read value from GPDAT register */
+		return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
+	}
+}
+
+static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	int dir;
+
+	dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
+	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+
+	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+						  "reg", 0, &size);
+
+	data->addr = addr;
+	data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+	if (!data->base)
+		return -ENOMEM;
+
+	data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					  "ngpios", 32);
+	data->dat_shadow = 0;
+
+	return 0;
+}
+
+static int mpc85xx_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	char name[32], *str;
+
+	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+	str = strdup(name);
+
+	if (!str)
+		return -ENOMEM;
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = data->gpio_count;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_mpc85xx_ops = {
+	.direction_input	= mpc85xx_gpio_direction_input,
+	.direction_output	= mpc85xx_gpio_direction_output,
+	.get_value		= mpc85xx_gpio_get_value,
+	.set_value		= mpc85xx_gpio_set_value,
+	.get_function 		= mpc85xx_gpio_get_function,
+};
+
+static const struct udevice_id mpc85xx_gpio_ids[] = {
+	{ .compatible = "fsl,pq3-gpio" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_mpc85xx) = {
+	.name	= "gpio_mpc85xx",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_mpc85xx_ops,
+	.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
+	.of_match = mpc85xx_gpio_ids,
+	.probe	= mpc85xx_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
+};
-- 
cgit v0.10.2


From 53ecdfb92034ce836ec94ba33ba0d8d27ea3c16c Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 25 May 2016 15:15:21 +0200
Subject: dm: gpio: Add methods for open drain setting

Certain GPIO devices have the capability to switch their GPIOs into
open-drain mode, that is, instead of actively driving the output
(Push-pull output), the pin is connected to the collector (for a NPN
transistor) or the drain (for a MOSFET) of a transistor, respectively.
The pin then either forms an open circuit or a connection to ground,
depending on the state of the transistor.

This patch adds functions to the GPIO uclass to switch GPIOs to
open-drain mode on devices that support it.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 732b6c2..4559739 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -367,6 +367,38 @@ int dm_gpio_set_value(const struct gpio_desc *desc, int value)
 	return 0;
 }
 
+int dm_gpio_get_open_drain(struct gpio_desc *desc)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+	int ret;
+
+	ret = check_reserved(desc, "get_open_drain");
+	if (ret)
+		return ret;
+
+	if (ops->set_open_drain)
+		return ops->get_open_drain(desc->dev, desc->offset);
+	else
+		return -ENOSYS;
+}
+
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+	int ret;
+
+	ret = check_reserved(desc, "set_open_drain");
+	if (ret)
+		return ret;
+
+	if (ops->set_open_drain)
+		ret = ops->set_open_drain(desc->dev, desc->offset, value);
+	else
+		return 0; /* feature not supported -> ignore setting */
+
+	return ret;
+}
+
 int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
 {
 	struct udevice *dev = desc->dev;
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 2500c10..4aa0004 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -251,6 +251,8 @@ struct dm_gpio_ops {
 				int value);
 	int (*get_value)(struct udevice *dev, unsigned offset);
 	int (*set_value)(struct udevice *dev, unsigned offset, int value);
+	int (*get_open_drain)(struct udevice *dev, unsigned offset);
+	int (*set_open_drain)(struct udevice *dev, unsigned offset, int value);
 	/**
 	 * get_function() Get the GPIO function
 	 *
@@ -550,6 +552,38 @@ int dm_gpio_get_value(const struct gpio_desc *desc);
 int dm_gpio_set_value(const struct gpio_desc *desc, int value);
 
 /**
+ * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active
+ *
+ * This checks if open-drain-mode for a GPIO is enabled or not. This method is
+ * optional.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or
+ *	   -ve on error
+ */
+int dm_gpio_get_open_drain(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off
+ *
+ * This enables or disables open-drain mode for a GPIO. This method is
+ * optional; if the driver does not support it, nothing happens when the method
+ * is called.
+ *
+ * In open-drain mode, instead of actively driving the output (Push-pull
+ * output), the GPIO's pin is connected to the collector (for a NPN transistor)
+ * or the drain (for a MOSFET) of a transistor, respectively. The pin then
+ * either forms an open circuit or a connection to ground, depending on the
+ * state of the transistor.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value);
+
+/**
  * dm_gpio_set_dir() - Set the direction for a GPIO
  *
  * This sets up the direction according tot the provided flags. It will do
-- 
cgit v0.10.2


From 51781783c59ad0080621d777579eb8acd14aa0ed Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 25 May 2016 15:15:22 +0200
Subject: dm: gpio: Implement open drain for MPC85XX GPIO

This patch implements the open-drain setting feature for the MPC85XX
GPIO controller.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b674a47..8595e2e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -193,9 +193,9 @@ config MPC85XX_GPIO
 	  configurable to match the actual GPIO count of the SoC (e.g. the
 	  32/32/23 banks of the P1022 SoC).
 
-	  The standard functions of input/output mode, and output value setting
-	  are supported; the open-drain capability of the controller is not
-	  supported yet.
+	  Aside from the standard functions of input/output mode, and output
+	  value setting, the open-drain feature, which can configure individual
+	  GPIOs to work as open-drain outputs, is supported.
 
 	  The driver has been tested on MPC85XX, but it is likely that other
 	  PowerQUICC III devices will work as well.
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
index 17755df..04773e2 100644
--- a/drivers/gpio/mpc85xx_gpio.c
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -73,6 +73,25 @@ static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
 	setbits_be32(&base->gpdir, gpios);
 }
 
+static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+{
+	return in_be32(&base->gpodr) & mask;
+}
+
+static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+					      gpios)
+{
+	/* GPODR register 1 -> open drain on */
+	setbits_be32(&base->gpodr, gpios);
+}
+
+static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
+					       u32 gpios)
+{
+	/* GPODR register 0 -> open drain off (actively driven) */
+	clrbits_be32(&base->gpodr, gpios);
+}
+
 static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
 {
 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
@@ -115,6 +134,26 @@ static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
 	}
 }
 
+static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
+				       int value)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	if (value) {
+		mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+	} else {
+		mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+	}
+	return 0;
+}
+
 static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
 {
 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
@@ -168,6 +207,8 @@ static const struct dm_gpio_ops gpio_mpc85xx_ops = {
 	.direction_output	= mpc85xx_gpio_direction_output,
 	.get_value		= mpc85xx_gpio_get_value,
 	.set_value		= mpc85xx_gpio_set_value,
+	.get_open_drain		= mpc85xx_gpio_get_open_drain,
+	.set_open_drain		= mpc85xx_gpio_set_open_drain,
 	.get_function 		= mpc85xx_gpio_get_function,
 };
 
-- 
cgit v0.10.2


From 743268f5146e3fd93abb8b6142ef6a259a0656c5 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 25 May 2016 15:15:23 +0200
Subject: dm: test: Add GPIO open drain tests

Add some tests for the new open drain setting feature of the GPIO
uclass, and extend the capabilities of the sandbox GPIO driver
accordingly.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
index 8317db1..427af2c 100644
--- a/arch/sandbox/include/asm/gpio.h
+++ b/arch/sandbox/include/asm/gpio.h
@@ -41,6 +41,26 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
 int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
 
 /**
+ * Set or reset the simulated open drain mode of a GPIO (used only in sandbox
+ * test code)
+ *
+ * @param gp	GPIO number
+ * @param value	value to set (0 for enabled open drain mode, non-zero for
+ * 		disabled)
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value);
+
+/**
+ * Return the state of the simulated open drain mode of a GPIO (used only in
+ * sandbox test code)
+ *
+ * @param gp	GPIO number
+ * @return -1 on error, 0 if GPIO is input, >0 if output
+ */
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset);
+
+/**
  * Return the simulated direction of a GPIO (used only in sandbox test code)
  *
  * @param gp	GPIO number
diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c
index a9b1efc..f6435a0 100644
--- a/drivers/gpio/sandbox.c
+++ b/drivers/gpio/sandbox.c
@@ -15,6 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Flags for each GPIO */
 #define GPIOF_OUTPUT	(1 << 0)	/* Currently set as an output */
 #define GPIOF_HIGH	(1 << 1)	/* Currently set high */
+#define GPIOF_ODR	(1 << 2)	/* Currently set to open drain mode */
 
 struct gpio_state {
 	const char *label;	/* label given by requester */
@@ -70,6 +71,16 @@ int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
 }
 
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+	return get_gpio_flag(dev, offset, GPIOF_ODR);
+}
+
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+	return set_gpio_flag(dev, offset, GPIOF_ODR, value);
+}
+
 int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset)
 {
 	return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
@@ -124,6 +135,28 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return sandbox_gpio_set_value(dev, offset, value);
 }
 
+/* read GPIO ODR value of port 'offset' */
+static int sb_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+	debug("%s: offset:%u\n", __func__, offset);
+
+	return sandbox_gpio_get_open_drain(dev, offset);
+}
+
+/* write GPIO ODR value to port 'offset' */
+static int sb_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
+
+	if (!sandbox_gpio_get_direction(dev, offset)) {
+		printf("sandbox_gpio: error: set_open_drain on input gpio %u\n",
+		       offset);
+		return -1;
+	}
+
+	return sandbox_gpio_set_open_drain(dev, offset, value);
+}
+
 static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
 {
 	if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
@@ -154,6 +187,8 @@ static const struct dm_gpio_ops gpio_sandbox_ops = {
 	.direction_output	= sb_gpio_direction_output,
 	.get_value		= sb_gpio_get_value,
 	.set_value		= sb_gpio_set_value,
+	.get_open_drain		= sb_gpio_get_open_drain,
+	.set_open_drain		= sb_gpio_set_open_drain,
 	.get_function		= sb_gpio_get_function,
 	.xlate			= sb_gpio_xlate,
 };
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 727db18..b994523 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -75,6 +75,13 @@ static int dm_test_gpio(struct unit_test_state *uts)
 	ut_assertok(ops->set_value(dev, offset, 1));
 	ut_asserteq(1, ops->get_value(dev, offset));
 
+	/* Make it an open drain output, and reset it */
+	ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+	ut_assertok(ops->set_open_drain(dev, offset, 1));
+	ut_asserteq(1, sandbox_gpio_get_open_drain(dev, offset));
+	ut_assertok(ops->set_open_drain(dev, offset, 0));
+	ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+
 	/* Make it an input */
 	ut_assertok(ops->direction_input(dev, offset));
 	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
-- 
cgit v0.10.2


From 23d4e5ba49b878e01321be2af4e94f73389f4958 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Wed, 13 Apr 2016 17:49:28 -0400
Subject: freescale: Tweak various Makefiles to remove redundancy, fix
 aesthetics

No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index 0acd2a9..673d2ea 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -5,11 +5,11 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
 obj-y	+= b4860qds.o
-obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI)      += pci.o
+obj-$(CONFIG_B4860QDS)	+= eth_b4860qds.o
+obj-$(CONFIG_PCI)	+= pci.o
 endif
 
 obj-y	+= ddr.o
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index b26d3a1..8027750 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -13,15 +13,11 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
-
-obj-y        += bsc9131rdb.o
-obj-y        += ddr.o
-obj-y        += law.o
-obj-y        += tlb.o
-#obj-y		+= bsc9131rdb_mux.o
-
+obj-y	+= bsc9131rdb.o
+obj-y	+= ddr.o
 endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 2e4170f..5419335 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -13,14 +13,11 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
-
 obj-y	+= bsc9132qds.o
 obj-y	+= ddr.o
+endif
+
 obj-y	+= law.o
 obj-y	+= tlb.o
-
-endif
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 818484a..93b3cba 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -11,15 +11,15 @@ endif
 endif
 
 ifdef MINIMAL
-obj-y	+= spl_minimal.o tlb.o law.o
+obj-y	+= spl_minimal.o
 else
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 endif
-
 obj-y	+= c29xpcie.o
 obj-y	+= cpld.o
 obj-y	+= ddr.o
+endif
+
 obj-y	+= law.o
 obj-y	+= tlb.o
-endif
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 660d1bb..86eb694 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -13,18 +13,14 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
-
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 endif
-
 obj-y	+= p1010rdb.o
 obj-y	+= ddr.o
+endif
+
 obj-y	+= law.o
 obj-y	+= tlb.o
-
-endif
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index a582127..9793853 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -13,17 +13,15 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y        += spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 endif
 obj-y	+= p1022ds.o
 obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
-
 obj-$(CONFIG_FSL_DIU_FB) += diu.o
 endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index a2a1f92..045d409 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -13,17 +13,14 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 endif
-
-obj-y        += p1_p2_rdb_pc.o
-obj-y        += ddr.o
-obj-y        += law.o
-obj-y        += tlb.o
-
+obj-y	+= p1_p2_rdb_pc.o
+obj-y	+= ddr.o
 endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index c74f4c6..a335ec6 100644
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -7,6 +7,6 @@
 #
 
 obj-y	+= p2041rdb.o
-obj-y += cpld.o
+obj-y	+= cpld.o
 obj-y	+= ddr.o
 obj-y	+= eth.o
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
index d94f230..afbc914 100644
--- a/board/freescale/t102xqds/Makefile
+++ b/board/freescale/t102xqds/Makefile
@@ -5,7 +5,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
 obj-y	+= t102xqds.o
 obj-y	+= eth_t102xqds.o
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index 0520066..6452865 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -5,7 +5,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
 obj-y   += t102xrdb.o
 obj-$(CONFIG_T1024RDB)   += cpld.o
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index 6cb72c9..ef04a26 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,10 +7,8 @@
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
-obj-$(CONFIG_T2080QDS) += t208xqds.o
-obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o
-obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
 obj-$(CONFIG_PCI)      += pci.o
 endif
 
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 9605f8b..cd8fe09 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -5,11 +5,9 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o
-obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
-obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
 obj-$(CONFIG_PCI)      += pci.o
 endif
 
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index bd2c1f1..731ccb0 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -5,12 +5,12 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
-obj-$(CONFIG_T4240QDS) += t4240qds.o
-obj-$(CONFIG_T4240QDS)+= eth.o
+obj-$(CONFIG_T4240QDS)	+= t4240qds.o eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
+
 obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 83b55ee..4f29eea 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -5,13 +5,14 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
-obj-$(CONFIG_T4240RDB) += t4240rdb.o
-obj-y	+= cpld.o
-obj-y	+= eth.o
+obj-$(CONFIG_T4240RDB)	+= t4240rdb.o
+obj-y			+= cpld.o
+obj-y			+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
+
 obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
-- 
cgit v0.10.2


From 8aa57a95a2efc8174c5482f9b3abc4920b479ff2 Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Fri, 3 Jun 2016 14:05:04 -0500
Subject: spl: fit: Fix non-matching DT names console output

When no DTB can be matched successfully to the board that's being used
a list of available FIT-embedded DTBs will be output to the console for
diagnostic purposes. But rather than the contents of the "description"
FDT property a non-existent property was accessed and as a result "NULL"
was output instead of the actual name(s) of the DTB(s). Fix this issue
by using the correct property which is also the exact same property
that's used earlier during the actual board matching process.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index c9eb020..9874708 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -77,7 +77,7 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 	for (node = fdt_first_subnode(fdt, conf);
 	     node >= 0;
 	     node = fdt_next_subnode(fdt, node)) {
-		name = fdt_getprop(fdt, node, "name", &len);
+		name = fdt_getprop(fdt, node, "description", &len);
 		printf("   %s\n", name);
 	}
 #endif
-- 
cgit v0.10.2


From 756e76f0753fdb6b6ea10482db5ebbaf72c9df66 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sun, 5 Jun 2016 00:46:55 +0200
Subject: arm: lib: Fix fix push/pop-section directives

Repair typos in the previous "arm: lib: fix push/pop-section directives"
patch, which prevented VCMA9 board from building.

Signed-off-by: Marek Vasut <marex@denx.de>
Fixes: b2f1858455e9 ("arm: lib: fix push/pop-section directives")
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 9bf93ce..76968ce 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -367,9 +367,9 @@ UNWIND(.fnend)
 ENDPROC(Ldiv0)
 .popsection
 
-.pushsection .text.__gnu_thumb1_case_sqi, "ax"
 /* Thumb-1 specialities */
 #if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
 ENTRY(__gnu_thumb1_case_sqi)
 	push	{r1}
 	mov	r1, lr
@@ -383,7 +383,7 @@ ENTRY(__gnu_thumb1_case_sqi)
 ENDPROC(__gnu_thumb1_case_sqi)
 .popsection
 
-_.pushsection .text.__gnu_thumb1_case_uqi, "ax"
+.pushsection .text.__gnu_thumb1_case_uqi, "ax"
 ENTRY(__gnu_thumb1_case_uqi)
 	push	{r1}
 	mov	r1, lr
-- 
cgit v0.10.2


From 7530ae087a6b97e789c40070061ab32326c5e394 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Wed, 25 May 2016 15:20:38 +0530
Subject: mtd: nand: arasan_nfc: Correct nand ecc initialization

Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 2d73a05..caa7982 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -1058,20 +1058,20 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	if (found < 0)
 		return 1;
 
-	regval = ecc_matrix[i].eccaddr |
-		 (ecc_matrix[i].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
-		 (ecc_matrix[i].bch << ARASAN_NAND_ECC_BCH_SHIFT);
+	regval = ecc_matrix[found].eccaddr |
+		 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
+		 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
 	writel(regval, &arasan_nand_base->ecc_reg);
 
-	if (ecc_matrix[i].bch) {
+	if (ecc_matrix[found].bch) {
 		regval = readl(&arasan_nand_base->memadr_reg2);
 		regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
-		regval |= (ecc_matrix[i].bchval <<
+		regval |= (ecc_matrix[found].bchval <<
 			   ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
 		writel(regval, &arasan_nand_base->memadr_reg2);
 	}
 
-	nand_oob.eccbytes = ecc_matrix[i].eccsize;
+	nand_oob.eccbytes = ecc_matrix[found].eccsize;
 	eccpos_start = mtd->oobsize - nand_oob.eccbytes;
 
 	for (i = 0; i < nand_oob.eccbytes; i++)
@@ -1080,9 +1080,9 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	nand_oob.oobfree[0].offset = 2;
 	nand_oob.oobfree[0].length = eccpos_start - 2;
 
-	nand_chip->ecc.size = ecc_matrix[i].ecc_codeword_size;
-	nand_chip->ecc.strength = ecc_matrix[i].eccbits;
-	nand_chip->ecc.bytes = ecc_matrix[i].eccsize;
+	nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
+	nand_chip->ecc.strength = ecc_matrix[found].eccbits;
+	nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
 	nand_chip->ecc.layout = &nand_oob;
 
 	return 0;
-- 
cgit v0.10.2


From 1630d5582c2b8be129bcd2d3a0db03bc3349dfab Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 27 May 2016 11:25:49 +0200
Subject: ARM64: zynqmp: Enable CMD_NAND via Kconfig

Simplify board file by enabling CMD_NAND via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index f342ed2..7879b4d 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 77e6180..2edd180 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ffb6b34..c2c6eab 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -105,7 +105,6 @@
 #endif
 
 #ifdef CONFIG_NAND_ARASAN
-# define CONFIG_CMD_NAND
 # define CONFIG_CMD_NAND_LOCK_UNLOCK
 # define CONFIG_SYS_MAX_NAND_DEVICE	1
 # define CONFIG_SYS_NAND_SELF_INIT
-- 
cgit v0.10.2


From 91eeb80ee7cdc7833d752bdaa45ae2a1556c72cf Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 24 May 2016 11:42:26 +0200
Subject: microblaze: Select compilation flags via Kconfig

Remove autogenerated config.mk and select CPU options via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 461d7dc..01c157e 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -9,4 +9,20 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "microblaze-generic"
 
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+	int "USE_PCMP_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_BARREL
+	int "USE_BARREL range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_DIV
+	int "USE_DIV range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+	default 0
+
 endif
diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
index 95ef9c0..4b033f7 100644
--- a/board/xilinx/microblaze-generic/config.mk
+++ b/board/xilinx/microblaze-generic/config.mk
@@ -1,16 +1,16 @@
 #
-# (C) Copyright 2007 Michal Simek
+# (C) Copyright 2007 - 2016 Michal Simek
 #
-# Michal  SIMEK <monstr@monstr.eu>
+# Michal SIMEK <monstr@monstr.eu>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-# CAUTION: This file is a faked configuration !!!
-#          There is no real target for the microblaze-generic
-#          configuration. You have to replace this file with
-#          the generated file from your Xilinx design flow.
-#
 
-PLATFORM_CPPFLAGS += -mno-xl-soft-mul
-PLATFORM_CPPFLAGS += -mno-xl-soft-div
-PLATFORM_CPPFLAGS += -mxl-barrel-shift
+# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+
+PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 8c7e4b7..7e53b5e 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -2,6 +2,9 @@ CONFIG_MICROBLAZE=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
 CONFIG_SYS_TEXT_BASE=0x29000000
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SPL=y
-- 
cgit v0.10.2


From 4ad1096e487f6bd03ec235263259aa97ef9cb2f1 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 24 May 2016 13:23:59 +0200
Subject: microblaze: Add option to pass cpu version number

Toolchain can use some flags by default based on cpu version.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 01c157e..c8b11ca 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -25,4 +25,8 @@ config XILINX_MICROBLAZE0_USE_HW_MUL
 	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
 	default 0
 
+config XILINX_MICROBLAZE0_HW_VER
+	string "Core version number"
+	default 7.10.d
+
 endif
diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
index 4b033f7..1dee2d6 100644
--- a/board/xilinx/microblaze-generic/config.mk
+++ b/board/xilinx/microblaze-generic/config.mk
@@ -6,6 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+
 # USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
 CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
 CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
@@ -13,4 +15,6 @@ CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
 CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
 CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
 
+CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+
 PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
-- 
cgit v0.10.2


From ac551e3492fe7bf9b4e087f8ee454108c5098c6d Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 24 May 2016 11:45:11 +0200
Subject: microblaze: Move MSR instruction selection to Kconfig

Select MSR instructions via Kconfig instead of xparameters.h.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h
index 11f3dd0..94f0562 100644
--- a/arch/microblaze/include/asm/asm.h
+++ b/arch/microblaze/include/asm/asm.h
@@ -50,7 +50,7 @@
 #define NOP	__asm__ __volatile__ ("nop");
 
 /* use machine status registe USE_MSR_REG */
-#if XILINX_USE_MSR_INSTR == 1
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1
 #define MSRSET(val) \
 	__asm__ __volatile__ ("msrset r0," #val );
 
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index c8b11ca..02ac65c 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -9,6 +9,10 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "microblaze-generic"
 
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+	int "USE_MSR_INSTR range (0:1)"
+	default 0
+
 config XILINX_MICROBLAZE0_USE_PCMP_INSTR
 	int "USE_PCMP_INSTR range (0:1)"
 	default 0
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index dc5645b..ee7d087 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -14,7 +14,6 @@
 #define XILINX_BOARD_NAME	microblaze-generic
 
 /* Microblaze is microblaze_0 */
-#define XILINX_USE_MSR_INSTR	1
 #define XILINX_FSL_NUMBER	3
 
 /* GPIO is LEDs_4Bit*/
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 7e53b5e..2ef713f 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -2,6 +2,7 @@ CONFIG_MICROBLAZE=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
-- 
cgit v0.10.2


From a1a6af82e2c7be4ef34e38e2d01dd337e8b32903 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 30 May 2016 10:13:37 +0200
Subject: ARM64: zynqmp: Enable Vitesse and RealTek ethernet phys

Phys are available on zc1751-dc4 that's why enable them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index c2c6eab..455481d 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -189,6 +189,8 @@
 # define CONFIG_PHY_NATSEMI
 # define CONFIG_PHY_TI
 # define CONFIG_PHY_GIGE
+# define CONFIG_PHY_VITESSE
+# define CONFIG_PHY_REALTEK
 # define PHY_ANEG_TIMEOUT       20000
 #endif
 
-- 
cgit v0.10.2


From ead66ab6dfc6fcf8bbd4d056e0a03b915c0e4450 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 20 May 2016 09:55:00 +0200
Subject: ARM64: zynqmp: Add debug uart for zc1751-dc2

Add debug uart for zc1751-dc2.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 2edd180..67d36f3 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -41,6 +41,11 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
-- 
cgit v0.10.2


From 08ac386bb292d3be19f77e7d782574e72646ea1b Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 26 May 2016 08:06:38 +0200
Subject: ARM64: zynqmp: Add support for zc1751-dc4

zc1751-dc4 contains four GEMs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e76f56b..ed897cf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zcu102-revB.dtb			\
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
+	zynqmp-zc1751-xm018-dc4.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
 	am335x-evmsk.dtb \
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 0000000..03f1ad7
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,212 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP zc1751-xm018-dc4";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		can0 = &can0;
+		can1 = &can1;
+		ethernet0 = &gem0;
+		ethernet1 = &gem1;
+		ethernet2 = &gem2;
+		ethernet3 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&lpd_dma_chan1 {
+	status = "okay";
+};
+
+&lpd_dma_chan2 {
+	status = "okay";
+};
+
+&lpd_dma_chan3 {
+	status = "okay";
+};
+
+&lpd_dma_chan4 {
+	status = "okay";
+};
+
+&lpd_dma_chan5 {
+	status = "okay";
+};
+
+&lpd_dma_chan6 {
+	status = "okay";
+};
+
+&lpd_dma_chan7 {
+	status = "okay";
+};
+
+&lpd_dma_chan8 {
+	status = "okay";
+};
+
+&xlnx_dp {
+	status = "okay";
+};
+
+&xlnx_dpdma {
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy0>;
+	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+		reg = <0>;
+	};
+	ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+		reg = <7>;
+	};
+	ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+		reg = <3>;
+	};
+	ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+		reg = <8>;
+	};
+};
+
+&gem1 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 91];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy7>;
+};
+
+&gem2 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 92];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy3>;
+};
+
+&gem3 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 93];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy8>;
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
new file mode 100644
index 0000000..f7f3822
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
new file mode 100644
index 0000000..fd2ec6a
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
@@ -0,0 +1,24 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM018 DC4
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
+#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
+
+#define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm018 dc4"
+
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+	"kernel_offset=0x400000\0" \
+	"fdt_offset=0x2400000\0" \
+	"kernel_size=0x2000000\0" \
+	"fdt_size=0x80000\0" \
+	"board=zc1751-dc4\0"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */
-- 
cgit v0.10.2


From 9c152edd12ba57bb3e3a570652e6493a8264e5af Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 30 May 2016 10:41:26 +0200
Subject: ARM64: zynqmp: Extend page_table_size

0xc000 is not sufficient page table size if dc4 with 4 gems
is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 5dd3cd8..509f0aa 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -63,6 +63,11 @@ static struct mm_region zynqmp_mem_map[] = {
 };
 struct mm_region *mem_map = zynqmp_mem_map;
 
+u64 get_page_table_size(void)
+{
+	return 0x14000;
+}
+
 static unsigned int zynqmp_get_silicon_version_secure(void)
 {
 	u32 ver;
-- 
cgit v0.10.2


From 1a6a6e9a168fefc7b73bbe2619d4a0725cfa344a Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 30 May 2016 14:57:02 +0200
Subject: ARM64: zynq: Fix boot.bin generation for Zynq and ZynqMP

Fix boot.bin generation for Zynq and ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 6d2017d..0997fd9 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -158,11 +158,8 @@ ifeq ($(CONFIG_SYS_SOC),"at91")
 ALL-y	+= boot.bin
 endif
 
-ifdef CONFIG_ARCH_ZYNQ
-ALL-y	+= $(obj)/boot.bin
-endif
-
-ALL-(CONFIG_ARCH_ZYNQMP)	+= $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_ZYNQ)		+= $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_ZYNQMP)	+= $(obj)/boot.bin
 
 all:	$(ALL-y)
 
-- 
cgit v0.10.2


From 340b0e3bb6e8808a7e683e030b3c5b5137715041 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 30 May 2016 16:06:54 +0200
Subject: env: Setup GD_FLG_ENV_DEFAULT flag when default environment are used

Setup flag when default environment are used to be able to
rewrite default distro boot variables based on SoC boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>

diff --git a/common/env_common.c b/common/env_common.c
index af59c72..13db7dc 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -123,6 +123,7 @@ void set_default_env(const char *s)
 		error("Environment import failed: errno = %d\n", errno);
 
 	gd->flags |= GD_FLG_ENV_READY;
+	gd->flags |= GD_FLG_ENV_DEFAULT;
 }
 
 
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index f2810a1..0abcbe4 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -141,5 +141,6 @@ typedef struct global_data {
 #define GD_FLG_SPL_INIT		0x00400	/* spl_init() has been called	   */
 #define GD_FLG_SKIP_RELOC	0x00800	/* Don't relocate */
 #define GD_FLG_RECORD		0x01000	/* Record console */
+#define GD_FLG_ENV_DEFAULT	0x02000 /* Default variable flag */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
-- 
cgit v0.10.2


From 0c1b02a73636f77d8b9733f29c2b324471b9f5a1 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 17 May 2016 08:38:53 +0200
Subject: ARM64: zynqmp: Enable support for SPL FIT images

Enable support for RAM based FIT images read by SPL.
Empty function for now to keep compiler happy.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 7879b4d..facb3b0 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 5d641a5..1941653 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 67d36f3..4f3cd93 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -8,6 +8,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index f7f3822..c7f58ba 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index f7c671b..59c754a 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index b370bc1..d579135 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 9764452..d88035d 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From 0d169b8cd70975f60920b077d6ed96623db97d33 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 1 Jun 2016 14:29:33 +0200
Subject: ARM64: zynqmp: Enable AHCI when CONFIG_SATA_CEVA is defined

Simplify zcu102 board file by moving CONFIG_AHCI enabling to common
file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 455481d..795d586 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -211,7 +211,8 @@
 # define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
 #endif
 
-#ifdef CONFIG_AHCI
+#ifdef CONFIG_SATA_CEVA
+#define CONFIG_AHCI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 81079fe..09c4a51 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -41,7 +41,6 @@
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 
-#define CONFIG_AHCI
 #define CONFIG_SATA_CEVA
 
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-- 
cgit v0.10.2


From a8b6a156c0f7fb99502229e454bc9c3b38645280 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 1 Jun 2016 22:41:54 +0200
Subject: ARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP

When the CONFIG_BOOTP_SERVERIP option is set, we ignore all
dhcp values for the tftp server and use our own serverip and
file name instead.

This is usually not what we want and I doubt it's set for a
good reason on ZynqMP. It definitely hurts if we want to support
uEFI PXE boot on it. So just remove the option for now.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 795d586..ac3de0a 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -76,7 +76,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
-#define CONFIG_BOOTP_SERVERIP
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
-- 
cgit v0.10.2


From b72894f14da79cdcdab8007b079d922bd28e5ce7 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 22 Apr 2016 14:28:54 +0200
Subject: ARM64: zynqmp: Add support for standard distro boot commands

Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.

Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 4623cd4..f15dc5d 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,6 +9,7 @@
 #include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
+#include <malloc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
@@ -214,6 +215,13 @@ int board_late_init(void)
 {
 	u32 reg = 0;
 	u8 bootmode;
+	const char *mode;
+	char *new_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
 
 	reg = readl(&crlapb_base->boot_mode);
 	bootmode = reg & BOOT_MODES_MASK;
@@ -222,37 +230,49 @@ int board_late_init(void)
 	switch (bootmode) {
 	case JTAG_MODE:
 		puts("JTAG_MODE\n");
-		setenv("modeboot", "jtagboot");
+		mode = "pxe dhcp";
 		break;
 	case QSPI_MODE_24BIT:
 	case QSPI_MODE_32BIT:
-		setenv("modeboot", "qspiboot");
+		mode = "qspi0";
 		puts("QSPI_MODE\n");
 		break;
 	case EMMC_MODE:
 		puts("EMMC_MODE\n");
-		setenv("modeboot", "sdboot");
+		mode = "mmc0";
 		break;
 	case SD_MODE:
 		puts("SD_MODE\n");
-		setenv("modeboot", "sdboot");
+		mode = "mmc0";
 		break;
 	case SD_MODE1:
 		puts("SD_MODE1\n");
 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
-		setenv("sdbootdev", "1");
+		mode = "mmc1";
+#else
+		mode = "mmc0";
 #endif
-		setenv("modeboot", "sdboot");
 		break;
 	case NAND_MODE:
 		puts("NAND_MODE\n");
-		setenv("modeboot", "nandboot");
+		mode = "nand0";
 		break;
 	default:
+		mode = "";
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;
 	}
 
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	new_targets = calloc(1, strlen(mode) +
+				strlen(getenv("boot_targets")) + 2);
+
+	sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
+	setenv("boot_targets", new_targets);
+
 	return 0;
 }
 
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ac3de0a..fc2e1f7 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -146,21 +146,6 @@
 # define DFU_ALT_INFO
 #endif
 
-/* Initial environment variables */
-#ifndef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr=0x80000\0" \
-	"fdt_addr=0x7000000\0" \
-	"fdt_high=0x10000000\0" \
-	CONFIG_KERNEL_FDT_OFST_SIZE \
-	"sdbootdev=0\0"\
-	"sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
-		"load mmc $sdbootdev:$partid $kernel_addr Image && " \
-		"booti $kernel_addr - $fdt_addr\0" \
-	DFU_ALT_INFO
-#endif
-
-#define CONFIG_BOOTCOMMAND	"run $modeboot"
 #define CONFIG_BOOTDELAY	3
 
 #define CONFIG_BOARD_LATE_INIT
@@ -230,6 +215,50 @@
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_high=10000000\0" \
+	"initrd_high=10000000\0" \
+	"fdt_addr_r=0x40000000\0" \
+	"pxefile_addr_r=0x10000000\0" \
+	"kernel_addr_r=0x18000000\0" \
+	"scriptaddr=0x02000000\0" \
+	"ramdisk_addr_r=0x02100000\0" \
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if defined(CONFIG_SATA_CEVA)
+# define BOOT_TARGET_DEVICES_SCSI(func)	func(SCSI, scsi, 0)
+#else
+# define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_USB)
+# define BOOT_TARGET_DEVICES_USB(func)	func(USB, usb, 0) func(USB, usb, 1)
+#else
+# define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_SCSI(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV \
+	DFU_ALT_INFO
+#endif
+
 #define CONFIG_SPL_TEXT_BASE		0xfffc0000
 #define CONFIG_SPL_MAX_SIZE		0x20000
 
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 9506355..c5bd5da 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -22,13 +22,6 @@
 
 #define COUNTER_FREQUENCY	4000000
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=ep108\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_EP_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index 3c0ba88..c9f4432 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -17,13 +17,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm015 dc1"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc1\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
index 83ea624..526d0bb 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -14,13 +14,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm016 dc2"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc2\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
index fd2ec6a..65277a6 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
@@ -12,13 +12,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm018 dc4"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc4\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index 4f8f5c1..76350d9 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -15,13 +15,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm019 dc5"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc5\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 09c4a51..7ceab32 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -53,13 +53,6 @@
 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR	0x54
 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET	0x20
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x180000\0" \
-	"fdt_offset=0x100000\0" \
-	"kernel_size=0x1e00000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zcu102\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZCU102_H */
-- 
cgit v0.10.2


From 59e880560f49827458b82345bb5ccfb7cb93af8c Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 3 Jun 2016 11:35:17 +0200
Subject: ARM64: zynqmp: Extend malloc space before relocation

For boards which have more devices it is necessary to extend malloc
space.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index facb3b0..d3f093b 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 1941653..e160f8f 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 4f3cd93..ffbedfa 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index c7f58ba..6570348 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_TEXT_BASE=0x8000000
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 59c754a..e1fc8b0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_TEXT_BASE=0x8000000
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index d579135..7cd54411 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index d88035d..20db671 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
-- 
cgit v0.10.2


From 69c125fe7b7dd057ed3e9013e6786b9f374cf8cd Mon Sep 17 00:00:00 2001
From: Ed Swarthout <Ed.Swarthout@nxp.com>
Date: Wed, 1 Jun 2016 08:11:24 -0500
Subject: dm: scsi: if_typename should be scsi

Fixes:

=> ext2ls scsi 0:1
** Bad device scsi 0:1 **

for boards which use the scsi legacy driver (such as ls1043ardb).

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/common/scsi.c b/common/scsi.c
index 8ac28dd..dbbf404 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -584,7 +584,7 @@ U_BOOT_DRIVER(scsi_blk) = {
 };
 #else
 U_BOOT_LEGACY_BLK(scsi) = {
-	.if_typename	= "sata",
+	.if_typename	= "scsi",
 	.if_type	= IF_TYPE_SCSI,
 	.max_devs	= CONFIG_SYS_SCSI_MAX_DEVICE,
 	.desc		= scsi_dev_desc,
-- 
cgit v0.10.2


From c165994299281957d735f5ec8863dda6243c3456 Mon Sep 17 00:00:00 2001
From: Peter Howard <pjh@northern-ridge.com.au>
Date: Thu, 2 Jun 2016 13:19:26 +1000
Subject: Fix to davinci_nand.h to place CEnCFG registers at correct

Signed-off-by: Peter Howard <phoward@gme.net.au>

diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index 11407be..f343ac2 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -35,10 +35,12 @@ struct davinci_emif_regs {
 	uint32_t	sdrcr;
 	union {
 		uint32_t abncr[4];
-		uint32_t ab1cr;
-		uint32_t ab2cr;
-		uint32_t ab3cr;
-		uint32_t ab4cr;
+		struct {
+			uint32_t ab1cr;
+			uint32_t ab2cr;
+			uint32_t ab3cr;
+			uint32_t ab4cr;
+		};
 	};
 	uint32_t	sdtimr;
 	uint32_t	ddrsr;
-- 
cgit v0.10.2


From 52b13f275e0c1c2e1fb1e367a01614137baf64ce Mon Sep 17 00:00:00 2001
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Date: Thu, 2 Jun 2016 09:05:39 +0200
Subject: ioep-fpga: Support intempo compression

There is a new "intempo" compression type that can
be reported on startup.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
index 96f02d6..f72a01e 100644
--- a/board/gdsys/common/ioep-fpga.c
+++ b/board/gdsys/common/ioep-fpga.c
@@ -25,8 +25,9 @@ enum {
 
 enum {
 	COMPRESSION_NONE = 0,
-	COMPRESSION_TYPE1_DELTA = 1,
-	COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+	COMPRESSION_TYPE_1 = 1,
+	COMPRESSION_TYPE_1_2 = 3,
+	COMPRESSION_TYPE_1_2_3 = 7,
 };
 
 enum {
@@ -158,12 +159,16 @@ void ioep_fpga_print_info(unsigned int fpga)
 		printf(" no compression");
 		break;
 
-	case COMPRESSION_TYPE1_DELTA:
-		printf(" type1-deltacompression");
+	case COMPRESSION_TYPE_1:
+		printf(" compression type1(delta)");
 		break;
 
-	case COMPRESSION_TYPE1_TYPE2_DELTA:
-		printf(" type1-deltacompression, type2-inlinecompression");
+	case COMPRESSION_TYPE_1_2:
+		printf(" compression type1(delta), type2(inline)");
+		break;
+
+	case COMPRESSION_TYPE_1_2_3:
+		printf(" compression type1(delta), type2(inline), type3(intempo)");
 		break;
 
 	default:
-- 
cgit v0.10.2


From df3223f9f78a2d841c10fe5037f11bd28c03b6a5 Mon Sep 17 00:00:00 2001
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Date: Thu, 2 Jun 2016 09:05:40 +0200
Subject: gdsys: osd: Allow osdsize on valid screens only

Limit "osdsize"-command to access valid screens only.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 4e292f5..add9574 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -469,6 +469,9 @@ int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 
 	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
 		OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
 		OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
 		OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
-- 
cgit v0.10.2


From 1d2541ba32c0ab144c9307edd4a76606ad528ce0 Mon Sep 17 00:00:00 2001
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Date: Thu, 2 Jun 2016 09:05:41 +0200
Subject: strider: Support con-dp flavor

There is a new strider console flavor with DisplayPort
video.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index ce23045..d4f0e70 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
 obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
 obj-$(CONFIG_STRIDER) += fanctrl.o
 obj-$(CONFIG_STRIDER_CON) += osd.o
+obj-$(CONFIG_STRIDER_CON_DP) += osd.o
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index eee582b..121977d 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -133,6 +133,9 @@ int last_stage_init(void)
 	unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
 #endif
 	bool hw_type_cat = pca9698_get_value(0x20, 18);
+#ifdef CONFIG_STRIDER_CON_DP
+	bool is_dh = pca9698_get_value(0x20, 25);
+#endif
 	bool ch0_sgmii2_present = false;
 
 	/* Turn on Analog Devices ADV7611 */
@@ -140,6 +143,7 @@ int last_stage_init(void)
 
 	/* Turn on Parade DP501 */
 	pca9698_direction_output(0x20, 10, 1);
+	pca9698_direction_output(0x20, 11, 1);
 
 	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
 
@@ -202,6 +206,14 @@ int last_stage_init(void)
 		osd_probe(0);
 #endif
 
+#ifdef CONFIG_STRIDER_CON_DP
+	if (ioep_fpga_has_osd(0)) {
+		osd_probe(0);
+		if (is_dh)
+			osd_probe(4);
+	}
+#endif
+
 #ifdef CONFIG_STRIDER_CPU
 	ch7301_probe(0, false);
 	dp501_probe(0, false);
@@ -226,6 +238,13 @@ int last_stage_init(void)
 		if (ioep_fpga_has_osd(k))
 			osd_probe(k);
 #endif
+#ifdef CONFIG_STRIDER_CON_DP
+		if (ioep_fpga_has_osd(k)) {
+			osd_probe(k);
+			if (is_dh)
+				osd_probe(k + 4);
+		}
+#endif
 #ifdef CONFIG_STRIDER_CPU
 		if (!adv7611_probe(k))
 			printf("       Advantiv ADV7611 HDMI Receiver\n");
@@ -270,6 +289,24 @@ int fpga_gpio_get(unsigned int bus, int pin)
 	return val & pin;
 }
 
+#ifdef CONFIG_STRIDER_CON_DP
+void fpga_control_set(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, control, &val);
+	FPGA_SET_REG(bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, control, &val);
+	FPGA_SET_REG(bus, control, val & ~pin);
+}
+#endif
+
 void mpc8308_init(void)
 {
 	pca9698_direction_output(0x20, 26, 1);
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
new file mode 100644
index 0000000..b7a16b7
--- /dev/null
+++ b/configs/strider_con_dp_defconfig
@@ -0,0 +1,20 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 5803b66..20ffc0c 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -22,6 +22,8 @@
 
 #ifdef CONFIG_STRIDER_CPU
 #define CONFIG_IDENT_STRING	" strider cpu 0.01"
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_IDENT_STRING	" strider con dp 0.01"
 #else
 #define CONFIG_IDENT_STRING	" strider con 0.01"
 #endif
@@ -225,15 +227,11 @@
 /*
  * FLASH on the Local Bus
  */
-#if 1
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_FLASH_CFI_LEGACY
 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#else
-#define CONFIG_SYS_NO_FLASH
-#endif
 
 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
@@ -341,6 +339,22 @@
 #define CONFIG_SYS_I2C_IHS_SPEED_3		50000
 #define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
 
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
+#endif
+
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -357,7 +371,7 @@
 #define I2C_SOFT_DECLARATIONS4
 #define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
-#ifdef CONFIG_STRIDER_CON
+#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
 #define I2C_SOFT_DECLARATIONS5
 #define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
@@ -371,6 +385,20 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
 #endif
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
+#endif
 
 #ifdef CONFIG_STRIDER_CON
 #define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
@@ -379,6 +407,13 @@
 #define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
 #define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
 						  {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
+#define CONFIG_SYS_CH7301_I2C			{1, 3, 5, 7}
+#define CONFIG_SYS_ADV7611_I2C			{1, 3, 5, 7}
+#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
+						  {12, 0x4c} }
 #else
 #define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
 #define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
@@ -391,6 +426,8 @@
 void fpga_gpio_set(unsigned int bus, int pin);
 void fpga_gpio_clear(unsigned int bus, int pin);
 int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
 #endif
 
 #ifdef CONFIG_STRIDER_CON
@@ -398,12 +435,28 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
 #define I2C_FPGA_IDX	((I2C_ADAP_HWNR > 3) ? \
 			 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)
 #else
 #define I2C_SDA_GPIO	0x0040
 #define I2C_SCL_GPIO	0x0020
 #define I2C_FPGA_IDX	I2C_ADAP_HWNR
 #endif
+
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_ACTIVE \
+	do { \
+		if (I2C_ADAP_HWNR > 7) \
+			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
+		else \
+			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
+	} while (0)
+#else
 #define I2C_ACTIVE	{ }
+#endif
+
 #define I2C_TRISTATE	{ }
 #define I2C_READ \
 	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
@@ -436,6 +489,10 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_DP501_DIFFERENTIAL
 #define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
 
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_OSD_DH
+#endif
+
 /*
  * General PCI
  * Addresses are mapped 1-1.
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 3b8762d..e1b9c64 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -163,7 +163,7 @@ struct ihs_fpga {
 };
 #endif
 
-#ifdef CONFIG_HRCON
+#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
 struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
-- 
cgit v0.10.2


From 145510cc7651fa36f1e6ee2d3d8504b05e965b1a Mon Sep 17 00:00:00 2001
From: Dirk Eibach <dirk.eibach@gdsys.cc>
Date: Thu, 2 Jun 2016 09:05:42 +0200
Subject: strider: Support cpu-dp flavor

There is new strider cpu flavor with DisplayPort video.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
new file mode 100644
index 0000000..db75c0d
--- /dev/null
+++ b/configs/strider_cpu_dp_defconfig
@@ -0,0 +1,20 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 20ffc0c..90492f4 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -20,7 +20,9 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 
-#ifdef CONFIG_STRIDER_CPU
+#ifdef CONFIG_STRIDER_CPU_DP
+#define CONFIG_IDENT_STRING	" strider cpu dp 0.01"
+#elif defined(CONFIG_STRIDER_CPU)
 #define CONFIG_IDENT_STRING	" strider cpu 0.01"
 #elif defined(CONFIG_STRIDER_CON_DP)
 #define CONFIG_IDENT_STRING	" strider con dp 0.01"
@@ -414,6 +416,12 @@
 #define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
 #define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
 						  {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CPU_DP)
+#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS			{ {6, 0x4c}, {7, 0x4c}, \
+						  {8, 0x4c} }
 #else
 #define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
 #define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
-- 
cgit v0.10.2


From 97d44b1f5c328af97d3c381c77858c8dd32c8e20 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 20 May 2016 23:28:22 +0200
Subject: arm: Introduce setjmp/longjmp

To quit an EFI application we will need logic to jump to the caller
of a function without returning from the function we called into,
so we need setjmp/longjmp functionality.

This patch introduces a trivial implementation of these that I
verified works on armv7, thumb2 and aarch64.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
new file mode 100644
index 0000000..b8b85b7
--- /dev/null
+++ b/arch/arm/include/asm/setjmp.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2016
+ * Alexander Graf <agraf@suse.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_	1
+
+struct jmp_buf_data {
+	ulong target;
+	ulong regs[5];
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+static inline int setjmp(jmp_buf jmp)
+{
+	long r = 0;
+
+#ifdef CONFIG_ARM64
+	asm volatile(
+		"adr x1, jmp_target\n"
+		"str x1, %1\n"
+		"stp x26, x27, %2\n"
+		"stp x28, x29, %3\n"
+		"mov x1, sp\n"
+		"str x1, %4\n"
+		"b 2f\n"
+		"jmp_target: "
+		"mov %0, #1\n"
+		"2:\n"
+		: "+r" (r), "=m" (jmp->target),
+		  "=m" (jmp->regs[0]), "=m" (jmp->regs[2]),
+		  "=m" (jmp->regs[4])
+		:
+		: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+		  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+		  "x16", "x17", "x18", "x19", "x20", "x21", "x22",
+		  "x23", "x24", "x25", /* x26, x27, x28, x29, sp */
+		  "x30", "cc", "memory");
+#else
+	asm volatile(
+#ifdef CONFIG_SYS_THUMB_BUILD
+		"adr r0, jmp_target + 1\n"
+#else
+		"adr r0, jmp_target\n"
+#endif
+		"mov r1, %1\n"
+		"mov r2, sp\n"
+		"stm r1, {r0, r2, r4, r5, r6, r7}\n"
+		"b 2f\n"
+		"jmp_target: "
+		"mov %0, #1\n"
+		"2:\n"
+		: "+l" (r)
+		: "l" (&jmp->target)
+		: "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */
+		  "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr",
+		  "cc", "memory");
+#endif
+
+printf("%s:%d target=%#lx\n", __func__, __LINE__, jmp->target);
+
+	return r;
+}
+
+static inline __noreturn void longjmp(jmp_buf jmp)
+{
+#ifdef CONFIG_ARM64
+	asm volatile(
+		"ldr x0, %0\n"
+		"ldr x1, %3\n"
+		"mov sp, x1\n"
+		"ldp x26, x27, %1\n"
+		"ldp x28, x25, %2\n"
+		"mov x29, x25\n"
+		"br x0\n"
+		:
+		: "m" (jmp->target), "m" (jmp->regs[0]), "m" (jmp->regs[2]),
+		  "m" (jmp->regs[4])
+		: "x0", "x1", "x25", "x26", "x27", "x28");
+#else
+	asm volatile(
+		"mov r1, %0\n"
+		"ldm r1, {r0, r2, r4, r5, r6, r7}\n"
+		"mov sp, r2\n"
+		"bx r0\n"
+		:
+		: "l" (&jmp->target)
+		: "r1");
+#endif
+
+	while (1) { }
+}
+
+
+#endif /* _SETJMP_H_ */
-- 
cgit v0.10.2


From a86aeaf228da739bce6bc40927949efc33672050 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 20 May 2016 23:28:23 +0200
Subject: efi_loader: Add exit support

Some times you may want to exit an EFI payload again, for example
to default boot into a PXE installation and decide that you would
rather want to boot from the local disk instead.

This patch adds exit functionality to the EFI implementation, allowing
EFI payloads to exit.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index d3a2331..2a62dce 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -209,6 +209,12 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt)
 #ifdef DEBUG_EFI
 	printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
 #endif
+
+	if (setjmp(&loaded_image_info.exit_jmp)) {
+		efi_status_t status = loaded_image_info.exit_status;
+		return status == EFI_SUCCESS ? 0 : -EINVAL;
+	}
+
 	return entry(&loaded_image_info, &systab);
 }
 
diff --git a/include/efi_api.h b/include/efi_api.h
index 20035d7..f572b88 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -17,6 +17,10 @@
 
 #include <efi.h>
 
+#ifdef CONFIG_EFI_LOADER
+#include <asm/setjmp.h>
+#endif
+
 /* Types and defines for EFI CreateEvent */
 enum efi_event_type {
 	EFI_TIMER_STOP = 0,
@@ -239,6 +243,12 @@ struct efi_loaded_image {
 	unsigned int image_code_type;
 	unsigned int image_data_type;
 	unsigned long unload;
+
+	/* Below are efi loader private fields */
+#ifdef CONFIG_EFI_LOADER
+	efi_status_t exit_status;
+	struct jmp_buf_data exit_jmp;
+#endif
 };
 
 #define DEVICE_PATH_GUID \
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 9daca50..15a1b90 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -458,19 +458,30 @@ static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
 	efi_is_direct_boot = false;
 
 	/* call the image! */
+	if (setjmp(&info->exit_jmp)) {
+		/* We returned from the child image */
+		return EFI_EXIT(info->exit_status);
+	}
+
 	entry(image_handle, &systab);
 
 	/* Should usually never get here */
 	return EFI_EXIT(EFI_SUCCESS);
 }
 
-static efi_status_t EFIAPI efi_exit(void *image_handle, long exit_status,
-				    unsigned long exit_data_size,
-				    uint16_t *exit_data)
+static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle,
+			efi_status_t exit_status, unsigned long exit_data_size,
+			int16_t *exit_data)
 {
+	struct efi_loaded_image *loaded_image_info = (void*)image_handle;
+
 	EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
 		  exit_data_size, exit_data);
-	return EFI_EXIT(efi_unsupported(__func__));
+
+	loaded_image_info->exit_status = exit_status;
+	longjmp(&loaded_image_info->exit_jmp);
+
+	panic("EFI application exited");
 }
 
 static struct efi_object *efi_search_obj(void *handle)
@@ -746,7 +757,7 @@ static const struct efi_boot_services efi_boot_services = {
 	.install_configuration_table = efi_install_configuration_table,
 	.load_image = efi_load_image,
 	.start_image = efi_start_image,
-	.exit = (void*)efi_exit,
+	.exit = efi_exit,
 	.unload_image = efi_unload_image,
 	.exit_boot_services = efi_exit_boot_services,
 	.get_next_monotonic_count = efi_get_next_monotonic_count,
-- 
cgit v0.10.2


From edcef3ba1d2d5beb92fcd7df253e196e77ba174d Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 2 Jun 2016 11:38:27 +0200
Subject: efi_loader: Move to normal debug infrastructure

We introduced special "DEBUG_EFI" defines when the efi loader
support was new. After giving it a bit of thought, turns out
we really didn't have to - the normal #define DEBUG infrastructure
works well enough for efi loader as well.

So this patch switches to the common debug() and #define DEBUG
way of printing debug information.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 2a62dce..2169065 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -206,9 +206,7 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt)
 #endif
 
 	/* Call our payload! */
-#ifdef DEBUG_EFI
-	printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
-#endif
+	debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
 
 	if (setjmp(&loaded_image_info.exit_jmp)) {
 		efi_status_t status = loaded_image_info.exit_status;
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3332d61..9738835 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -15,18 +15,10 @@
 
 #include <linux/list.h>
 
-/* #define DEBUG_EFI */
-
-#ifdef DEBUG_EFI
 #define EFI_ENTRY(format, ...) do { \
 	efi_restore_gd(); \
-	printf("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
+	debug("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
 	} while(0)
-#else
-#define EFI_ENTRY(format, ...) do { \
-	efi_restore_gd(); \
-	} while(0)
-#endif
 
 #define EFI_EXIT(ret) efi_exit_func(ret);
 
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 15a1b90..be6f5e8 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -6,8 +6,6 @@
  *  SPDX-License-Identifier:     GPL-2.0+
  */
 
-/* #define DEBUG_EFI */
-
 #include <common.h>
 #include <efi_loader.h>
 #include <malloc.h>
@@ -76,9 +74,7 @@ efi_status_t efi_exit_func(efi_status_t ret)
 
 static efi_status_t efi_unsupported(const char *funcname)
 {
-#ifdef DEBUG_EFI
-	printf("EFI: App called into unimplemented function %s\n", funcname);
-#endif
+	debug("EFI: App called into unimplemented function %s\n", funcname);
 	return EFI_EXIT(EFI_UNSUPPORTED);
 }
 
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index f9ad615..c434c92 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -84,10 +84,8 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 	blocks = buffer_size / blksz;
 	lba += diskobj->offset;
 
-#ifdef DEBUG_EFI
-	printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
-	       __LINE__, blocks, lba, blksz, direction);
-#endif
+	debug("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
+	      __LINE__, blocks, lba, blksz, direction);
 
 	/* We only support full block access */
 	if (buffer_size & (blksz - 1))
@@ -101,9 +99,8 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 	/* We don't do interrupts, so check for timers cooperatively */
 	efi_timer_check();
 
-#ifdef DEBUG_EFI
-	printf("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
-#endif
+	debug("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
+
 	if (n != blocks)
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 9e669f5..ad713d0 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -6,8 +6,6 @@
  *  SPDX-License-Identifier:     GPL-2.0+
  */
 
-/* #define DEBUG_EFI */
-
 #include <common.h>
 #include <efi_loader.h>
 #include <malloc.h>
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 11d0126..99b5ef1 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -165,9 +165,7 @@ static void efi_runtime_detach(ulong offset)
 		ulong *p = efi_runtime_detach_list[i].ptr;
 		ulong newaddr = patchto ? (patchto + patchoff) : 0;
 
-#ifdef DEBUG_EFI
-		printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
-#endif
+		debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
 		*p = newaddr;
 	}
 }
@@ -182,10 +180,7 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
 	static ulong lastoff = CONFIG_SYS_TEXT_BASE;
 #endif
 
-#ifdef DEBUG_EFI
-	printf("%s: Relocating to offset=%lx\n", __func__, offset);
-#endif
-
+	debug("%s: Relocating to offset=%lx\n", __func__, offset);
 	for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) {
 		ulong base = CONFIG_SYS_TEXT_BASE;
 		ulong *p;
@@ -212,10 +207,7 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
 			continue;
 		}
 
-#ifdef DEBUG_EFI
-		printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
-#endif
-
+		debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
 		*p = newaddr;
 		flush_dcache_range((ulong)p & ~(EFI_CACHELINE_SIZE - 1),
 			ALIGN((ulong)&p[1], EFI_CACHELINE_SIZE));
-- 
cgit v0.10.2


From 74c16acce30bb882ad5951829d8dafef8eea564c Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Fri, 27 May 2016 12:25:03 +0200
Subject: efi_loader: Don't allocate from memory holes

When a payload calls our memory allocator with the exact address hint, we
happily allocate memory from completely unpopulated regions. Payloads however
expect this to only succeed if they would be allocating from free conventional
memory.

This patch makes the logic behind those checks a bit more obvious and ensures
that we always allocate from known good free conventional memory regions if we
want to allocate ram.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index ad713d0..df2381e 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -22,6 +22,10 @@ struct efi_mem_list {
 	struct efi_mem_desc desc;
 };
 
+#define EFI_CARVE_NO_OVERLAP		-1
+#define EFI_CARVE_LOOP_AGAIN		-2
+#define EFI_CARVE_OVERLAPS_NONRAM	-3
+
 /* This list contains all memory map items */
 LIST_HEAD(efi_mem);
 
@@ -76,11 +80,11 @@ static int efi_mem_carve_out(struct efi_mem_list *map,
 
 	/* check whether we're overlapping */
 	if ((carve_end <= map_start) || (carve_start >= map_end))
-		return 0;
+		return EFI_CARVE_NO_OVERLAP;
 
 	/* We're overlapping with non-RAM, warn the caller if desired */
 	if (overlap_only_ram && (map_desc->type != EFI_CONVENTIONAL_MEMORY))
-		return -1;
+		return EFI_CARVE_OVERLAPS_NONRAM;
 
 	/* Sanitize carve_start and carve_end to lie within our bounds */
 	carve_start = max(carve_start, map_start);
@@ -95,7 +99,7 @@ static int efi_mem_carve_out(struct efi_mem_list *map,
 
 		map_desc->physical_start = carve_end;
 		map_desc->num_pages = (map_end - carve_end) >> EFI_PAGE_SHIFT;
-		return 1;
+		return (carve_end - carve_start) >> EFI_PAGE_SHIFT;
 	}
 
 	/*
@@ -115,7 +119,7 @@ static int efi_mem_carve_out(struct efi_mem_list *map,
 	/* Shrink the map to [ map_start ... carve_start ] */
 	map_desc->num_pages = (carve_start - map_start) >> EFI_PAGE_SHIFT;
 
-	return 1;
+	return EFI_CARVE_LOOP_AGAIN;
 }
 
 uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
@@ -123,7 +127,8 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 {
 	struct list_head *lhandle;
 	struct efi_mem_list *newlist;
-	bool do_carving;
+	bool carve_again;
+	uint64_t carved_pages = 0;
 
 	if (!pages)
 		return start;
@@ -150,7 +155,7 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 
 	/* Add our new map */
 	do {
-		do_carving = false;
+		carve_again = false;
 		list_for_each(lhandle, &efi_mem) {
 			struct efi_mem_list *lmem;
 			int r;
@@ -158,14 +163,44 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 			lmem = list_entry(lhandle, struct efi_mem_list, link);
 			r = efi_mem_carve_out(lmem, &newlist->desc,
 					      overlap_only_ram);
-			if (r < 0) {
+			switch (r) {
+			case EFI_CARVE_OVERLAPS_NONRAM:
+				/*
+				 * The user requested to only have RAM overlaps,
+				 * but we hit a non-RAM region. Error out.
+				 */
 				return 0;
-			} else if (r) {
-				do_carving = true;
+			case EFI_CARVE_NO_OVERLAP:
+				/* Just ignore this list entry */
+				break;
+			case EFI_CARVE_LOOP_AGAIN:
+				/*
+				 * We split an entry, but need to loop through
+				 * the list again to actually carve it.
+				 */
+				carve_again = true;
+				break;
+			default:
+				/* We carved a number of pages */
+				carved_pages += r;
+				carve_again = true;
+				break;
+			}
+
+			if (carve_again) {
+				/* The list changed, we need to start over */
 				break;
 			}
 		}
-	} while (do_carving);
+	} while (carve_again);
+
+	if (overlap_only_ram && (carved_pages != pages)) {
+		/*
+		 * The payload wanted to have RAM overlaps, but we overlapped
+		 * with an unallocated region. Error out.
+		 */
+		return 0;
+	}
 
 	/* Add our new map */
         list_add_tail(&newlist->link, &efi_mem);
-- 
cgit v0.10.2


From a812241091cec09c4a214c57776eefb8f19d81a9 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Sun, 5 Jun 2016 22:34:31 +0200
Subject: efi_loader: Add DM_VIDEO support

Some systems are starting to shift to support DM_VIDEO which exposes
the frame buffer through a slightly different interface.

This is a poor man's effort to support the dm video interface instead
of the lcd one. We still only support a single display device.

Signed-off-by: Alexander Graf <agraf@suse.de>
[trini: Remove fb_size / fb_base as they were not used]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index dc6e261..33a3d71 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -7,10 +7,12 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <efi_loader.h>
 #include <inttypes.h>
 #include <lcd.h>
 #include <malloc.h>
+#include <video.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -24,6 +26,8 @@ struct efi_gop_obj {
 	/* The only mode we support */
 	struct efi_gop_mode_info info;
 	struct efi_gop_mode mode;
+	/* Fields we only have acces to during init */
+	u32 bpix;
 };
 
 static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number,
@@ -57,6 +61,7 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 				   unsigned long dy, unsigned long width,
 				   unsigned long height, unsigned long delta)
 {
+	struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops);
 	int i, j, line_len16, line_len32;
 	void *fb;
 
@@ -67,13 +72,17 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 		return EFI_EXIT(EFI_INVALID_PARAMETER);
 
 	fb = (void*)gd->fb_base;
-	line_len16 = panel_info.vl_col * sizeof(u16);
-	line_len32 = panel_info.vl_col * sizeof(u32);
+	line_len16 = gopobj->info.width * sizeof(u16);
+	line_len32 = gopobj->info.width * sizeof(u32);
 
 	/* Copy the contents line by line */
 
-	switch (panel_info.vl_bpix) {
+	switch (gopobj->bpix) {
+#ifdef CONFIG_DM_VIDEO
+	case VIDEO_BPP32:
+#else
 	case LCD_COLOR32:
+#endif
 		for (i = 0; i < height; i++) {
 			u32 *dest = fb + ((i + dy)  * line_len32) +
 					 (dx * sizeof(u32));
@@ -84,7 +93,11 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 			memcpy(dest, src, width * sizeof(u32));
 		}
 		break;
+#ifdef CONFIG_DM_VIDEO
+	case VIDEO_BPP16:
+#else
 	case LCD_COLOR16:
+#endif
 		for (i = 0; i < height; i++) {
 			u16 *dest = fb + ((i + dy)  * line_len16) +
 					 (dx * sizeof(u16));
@@ -102,7 +115,11 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 		break;
 	}
 
+#ifdef CONFIG_DM_VIDEO
+	video_sync_all();
+#else
 	lcd_sync();
+#endif
 
 	return EFI_EXIT(EFI_SUCCESS);
 }
@@ -111,10 +128,34 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 int efi_gop_register(void)
 {
 	struct efi_gop_obj *gopobj;
+	u32 bpix, col, row;
 
-	switch (panel_info.vl_bpix) {
+#ifdef CONFIG_DM_VIDEO
+	struct udevice *vdev;
+
+	/* We only support a single video output device for now */
+	if (uclass_first_device(UCLASS_VIDEO, &vdev))
+		return -1;
+
+	struct video_priv *priv = dev_get_uclass_priv(vdev);
+	bpix = priv->bpix;
+	col = video_get_xsize(vdev);
+	row = video_get_ysize(vdev);
+#else
+
+	bpix = panel_info.vl_bpix;
+	col = panel_info.vl_col;
+	row = panel_info.vl_row;
+#endif
+
+	switch (bpix) {
+#ifdef CONFIG_DM_VIDEO
+	case VIDEO_BPP16:
+	case VIDEO_BPP32:
+#else
 	case LCD_COLOR32:
 	case LCD_COLOR16:
+#endif
 		break;
 	default:
 		/* So far, we only work in 16 or 32 bit mode */
@@ -137,10 +178,12 @@ int efi_gop_register(void)
 	gopobj->mode.info_size = sizeof(gopobj->info);
 
 	gopobj->info.version = 0;
-	gopobj->info.width = panel_info.vl_col;
-	gopobj->info.height = panel_info.vl_row;
+	gopobj->info.width = col;
+	gopobj->info.height = row;
 	gopobj->info.pixel_format = EFI_GOT_RGBA8;
-	gopobj->info.pixels_per_scanline = panel_info.vl_col;
+	gopobj->info.pixels_per_scanline = col;
+
+	gopobj->bpix = bpix;
 
 	/* Hook up to the device list */
 	list_add_tail(&gopobj->parent.link, &efi_obj_list);
-- 
cgit v0.10.2


From e22455f0a6020acc781267cf2f6e926fe8a4cae7 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Thu, 2 Jun 2016 11:43:16 +0200
Subject: armv7: fix order of OMAP die ID printing

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
index 52ea734..2d03ebf 100644
--- a/arch/arm/cpu/armv7/omap-common/utils.c
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -108,6 +108,6 @@ void omap_die_id_display(void)
 
 	omap_die_id(die_id);
 
-	printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1],
-		die_id[2], die_id[3]);
+	printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2],
+		die_id[1], die_id[0]);
 }
-- 
cgit v0.10.2


From ca5599c3fb4551c5a71b627f7552723fb9c74928 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 6 Jun 2016 10:54:57 +0530
Subject: ARM: DRA7xx: Enable FIT for hs platforms

Use a single defconfig for all DRA7xx hs platforms by enabling FIT and delete
the platform specific defconfigs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
index 907cb13..46b6e82 100644
--- a/board/ti/dra7xx/MAINTAINERS
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/ti/dra7xx/
 F:	include/configs/dra7xx_evm.h
 F:	configs/dra7xx_evm_defconfig
+F:	configs/dra7xx_hs_evm_defconfig
diff --git a/configs/dra72_hs_evm_defconfig b/configs/dra72_hs_evm_defconfig
deleted file mode 100644
index 1a4082c..0000000
--- a/configs/dra72_hs_evm_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra74_hs_evm_defconfig b/configs/dra74_hs_evm_defconfig
deleted file mode 100644
index edcdca0..0000000
--- a/configs/dra74_hs_evm_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
new file mode 100644
index 0000000..6933ab5
--- /dev/null
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -0,0 +1,61 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
-- 
cgit v0.10.2


From 5c2728ff0fb6ade135cc15c4849acac7db1d93d0 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 6 Jun 2016 11:18:42 +0530
Subject: configs: k2*_evm: Update fdt file names

Now that all Keystone2 dts file names are changed in Linux kernel, reflect the
same in evn variables inorder to find the right dtb file.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 07f975b..7eaab87 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -21,7 +21,7 @@
 	"addr_mon=0x0c140000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=k2e-evm.dtb\0"					\
+	"name_fdt=keystone-k2e-evm.dtb\0"				\
 	"name_mon=skern-k2e.bin\0"					\
 	"name_ubi=k2e-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2e-evm.gph\0"				\
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 3f98510..f8bba67 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -26,7 +26,7 @@
 	"addr_mon=0x0c040000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=k2g-evm.dtb\0"				\
+	"name_fdt=keystone-k2g-evm.dtb\0"				\
 	"name_mon=skern-k2g.bin\0"					\
 	"name_ubi=k2g-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2g-evm.gph\0"				\
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index a268a86..0256f0e 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -21,7 +21,7 @@
 	"addr_mon=0x0c5f0000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=k2hk-evm.dtb\0"				\
+	"name_fdt=keystone-k2hk-evm.dtb\0"				\
 	"name_mon=skern-k2hk.bin\0"					\
 	"name_ubi=k2hk-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2hk-evm.gph\0"				\
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index f366e67..2322ab2 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -21,7 +21,7 @@
 	"addr_mon=0x0c140000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"	\
-	"name_fdt=k2l-evm.dtb\0"					\
+	"name_fdt=keystone-k2l-evm.dtb\0"				\
 	"name_mon=skern-k2l.bin\0"					\
 	"name_ubi=k2l-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2l-evm.gph\0"				\
-- 
cgit v0.10.2


From 25bab53ab26efdb9e2024477f896be65b6e7191e Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Mon, 30 May 2016 06:55:53 -0400
Subject: Remove unneeded remnants of bcopy().

Since bcopy() is no longer used, delete all remaining references to
it.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h
index 724f5bd..8f67ec7 100644
--- a/arch/microblaze/include/asm/string.h
+++ b/arch/microblaze/include/asm/string.h
@@ -17,13 +17,11 @@
 #define __MICROBLAZE_STRING_H__
 
 #if 0
-#define __HAVE_ARCH_BCOPY
 #define __HAVE_ARCH_MEMCPY
 #define __HAVE_ARCH_MEMSET
 #define __HAVE_ARCH_MEMMOVE
 
 extern void *memcpy (void *, const void *, __kernel_size_t);
-extern void bcopy (const char *, char *, int);
 extern void *memset (void *, int, __kernel_size_t);
 extern void *memmove (void *, const void *, __kernel_size_t);
 #endif
diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S
index 8152ac9..56bb3b8 100644
--- a/arch/powerpc/lib/ppcstring.S
+++ b/arch/powerpc/lib/ppcstring.S
@@ -92,13 +92,6 @@ memset:
 	bdnz	8b
 	blr
 
-	.globl	bcopy
-bcopy:
-	mr	r6,r3
-	mr	r3,r4
-	mr	r4,r6
-	b	memcpy
-
 	.globl	memmove
 memmove:
 	cmplw	0,r3,r4
diff --git a/include/linux/string.h b/include/linux/string.h
index c7047ba..091ccab 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -20,10 +20,6 @@ extern __kernel_size_t strspn(const char *,const char *);
  */
 #include <asm/string.h>
 
-#ifndef __HAVE_ARCH_BCOPY
-char *bcopy(const char *src, char *dest, int count);
-#endif
-
 #ifndef __HAVE_ARCH_STRCPY
 extern char * strcpy(char *,const char *);
 #endif
diff --git a/lib/string.c b/lib/string.c
index 87c9a40..67d5f6a 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -461,30 +461,6 @@ void * memset(void * s,int c,size_t count)
 }
 #endif
 
-#ifndef __HAVE_ARCH_BCOPY
-/**
- * bcopy - Copy one area of memory to another
- * @src: Where to copy from
- * @dest: Where to copy to
- * @count: The size of the area.
- *
- * Note that this is the same as memcpy(), with the arguments reversed.
- * memcpy() is the standard, bcopy() is a legacy BSD function.
- *
- * You should not use this function to access IO space, use memcpy_toio()
- * or memcpy_fromio() instead.
- */
-char * bcopy(const char * src, char * dest, int count)
-{
-	char *tmp = dest;
-
-	while (count--)
-		*tmp++ = *src++;
-
-	return dest;
-}
-#endif
-
 #ifndef __HAVE_ARCH_MEMCPY
 /**
  * memcpy - Copy one area of memory to another
-- 
cgit v0.10.2


From be86492bdaeb8fdfd8d66bba79a9bd899531b8b0 Mon Sep 17 00:00:00 2001
From: Chris Packham <chris.packham@alliedtelesis.co.nz>
Date: Tue, 31 May 2016 20:30:59 +1200
Subject: lib: make strmhz available in SPL

When setting up a DDR controller it is useful to be able to display
frequencies in a readable form. Make the strmhz() function available in
SPL builds provided there is full vsprintf available.

Reviewed-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>

diff --git a/lib/Makefile b/lib/Makefile
index 02dfa29..f77befe 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -42,7 +42,6 @@ obj-y += rc4.o
 obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
 obj-$(CONFIG_SHA256) += sha256.o
-obj-y	+= strmhz.o
 obj-$(CONFIG_TPM) += tpm.o
 obj-$(CONFIG_RBTREE)	+= rbtree.o
 obj-$(CONFIG_BITREVERSE) += bitrev.o
@@ -85,11 +84,11 @@ ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_USE_TINY_PRINTF
 obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
 else
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o strmhz.o
 endif
 else
 # Main U-Boot always uses the full printf support
-obj-y += vsprintf.o panic.o strto.o
+obj-y += vsprintf.o panic.o strto.o strmhz.o
 endif
 
 subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
-- 
cgit v0.10.2


From cdaa633fcf9c2bd54aa3c130ee727708a4e2406a Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Tue, 31 May 2016 10:45:06 -0700
Subject: arm/arm64: implement a boot header capability

Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.

Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
  .space 1000
  .word 0x12345678

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Commit Notes:
Please note that the current code:
  start.S (arm64) and
  vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).

For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.

[1] https://github.com/apritzel/pine64/tree/master/tools
END
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72b0aa7..0805fa4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -91,6 +91,14 @@ config SYS_L2CACHE_OFF
 	  If SoC does not support L2CACHE or one do not want to enable
 	  L2CACHE, choose this option.
 
+config ENABLE_ARM_SOC_BOOT0_HOOK
+	bool "prepare BOOT0 header"
+	help
+	  If the SoC's BOOT0 requires a header area filled with (magic)
+	  values, then choose this option, and create a define called
+	  ARM_SOC_BOOT0_HOOK which contains the required assembler
+	  preprocessor code.
+
 choice
 	prompt "Target select"
 	default TARGET_HIKEY
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e933021..c1a2f45 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -21,6 +21,16 @@
 _start:
 	b	reset
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+ARM_SOC_BOOT0_HOOK
+#endif
+
 	.align 3
 
 .globl	_TEXT_BASE
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h
new file mode 100644
index 0000000..7e72882
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2016 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.word	0xbabeface;	\
+	.word	_end - _start
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
new file mode 100644
index 0000000..ea5675e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -0,0 +1,14 @@
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* reserve space for BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.space	1532
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 49238ed..5cc132b 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -60,6 +60,16 @@ _start:
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+ARM_SOC_BOOT0_HOOK
+#endif
+
 /*
  *************************************************************************
  *
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index bfd519e..4404f32 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -22,3 +22,4 @@ CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
 CONFIG_G_DNL_PRODUCT_NUM=0x0d02
 CONFIG_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 1911122..60eb328 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -22,3 +22,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
 CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 489b75c..0bf79bf 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -9,3 +9,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
cgit v0.10.2


From 65eac4cc54921f9496061b0e0f0a7e159b42a3c6 Mon Sep 17 00:00:00 2001
From: "B, Ravi" <ravibabu@ti.com>
Date: Fri, 3 Jun 2016 20:44:02 +0530
Subject: ti_armv7_common: env: Fix hard coded mmc device for uuid

Avoid use of hard coded mmcdev value, use bootpart
instead, so finduuid works based on bootpart set
for a specific platform.

Signed-off-by: Ravi Babu <ravibabu@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 7db0881..ba7cf15 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -59,7 +59,7 @@
 #define DEFAULT_MMC_TI_ARGS \
 	"mmcdev=0\0" \
 	"mmcrootfstype=ext4 rootwait\0" \
-	"finduuid=part uuid mmc 0:2 uuid\0" \
+	"finduuid=part uuid mmc ${bootpart} uuid\0" \
 	"args_mmc=run finduuid;setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=PARTUUID=${uuid} rw " \
-- 
cgit v0.10.2


From b104b3dc1dd90cdbf67ccf3c51b06e4f1592fe91 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 6 Jun 2016 17:43:54 -0400
Subject: Prepare v2016.07-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 742b165..0f7d6f3 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
 #
 
 VERSION = 2016
-PATCHLEVEL = 05
+PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From 0c344e6e7a05a83556bbd291c39f8456b287abca Mon Sep 17 00:00:00 2001
From: Andrew Shadura <andrew.shadura@collabora.co.uk>
Date: Tue, 24 May 2016 15:56:17 +0200
Subject: board: ge: bx50v3: don't configure the backlight when there's no
 display

Don't try to configure the backlight when CONFIG_VIDEO_IPUV3 isn't set.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index ff8f4d7..d45ed44 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -601,6 +601,8 @@ int board_late_init(void)
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
+
+#ifdef CONFIG_VIDEO_IPUV3
 	/* We need at least 200ms between power on and backlight on
 	 * as per specifications from CHI MEI */
 	mdelay(250);
@@ -615,6 +617,7 @@ int board_late_init(void)
 	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 
 	pwm_enable(0);
+#endif
 
 	return 0;
 }
-- 
cgit v0.10.2


From 07aa030a18552bcb1e9de30e348c6b59f4ffb6a5 Mon Sep 17 00:00:00 2001
From: Andrew Shadura <andrew.shadura@collabora.co.uk>
Date: Tue, 24 May 2016 15:56:18 +0200
Subject: board: ge: bx50v3: make CONFIG_VIDEO optional and disabled by default

The kernel already knows how to initialise the display, and initialising
the display from U-boot is only useful for debugging and isn't necessary
in production, so no need to have it enabled in U-boot by default.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 1304879..53f8689 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -293,13 +293,14 @@
 
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+
 /* Framebuffer */
-#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
@@ -309,6 +310,7 @@
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
+#endif
 
 #define CONFIG_PWM_IMX
 #define CONFIG_IMX6_PWM_PER_CLK	66000000
-- 
cgit v0.10.2


From fc44902a0d447d561a6a30c8d3e3e1ecf535ff9d Mon Sep 17 00:00:00 2001
From: Andrew Shadura <andrew.shadura@collabora.co.uk>
Date: Tue, 24 May 2016 15:56:19 +0200
Subject: board: ge: bx50v3: make USB support optional and disabled by default

The USB support is only useful for development and shouldn't be enabled
in production, so it has to be disabled in U-boot by default.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index ffa0440..98bf52e 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -8,8 +8,6 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index b039c24..b66c98b 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -8,8 +8,6 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index d9c8acd..1cd126a 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -8,8 +8,6 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 53f8689..602763f 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -78,6 +78,7 @@
 #define CONFIG_DOS_PARTITION
 
 /* USB Configs */
+#ifdef CONFIG_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MX6
 #define CONFIG_USB_STORAGE
@@ -99,6 +100,7 @@
 #define CONFIG_G_DNL_VENDOR_NUM   0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM  0xa4a5
 #define CONFIG_G_DNL_MANUFACTURER "Advantech"
+#endif
 
 /* Networking Configs */
 #define CONFIG_FEC_MXC
@@ -221,13 +223,7 @@
 			"bootm; " \
 		"fi;\0" \
 
-#define CONFIG_BOOTCOMMAND \
-	"usb start; " \
-	"setenv dev usb; " \
-	"setenv devnum 0; " \
-	"setenv rootdev sda1; " \
-	"run tryboot; " \
-	\
+#define CONFIG_MMCBOOTCOMMAND \
 	"setenv dev mmc; " \
 	"setenv rootdev mmcblk0p1; " \
 	\
@@ -241,9 +237,23 @@
 	"if mmc dev ${devnum}; then " \
 		"run tryboot; " \
 	"fi; " \
+
+#define CONFIG_USBBOOTCOMMAND \
+	"usb start; " \
+	"setenv dev usb; " \
+	"setenv devnum 0; " \
+	"setenv rootdev sda1; " \
+	"run tryboot; " \
 	\
+	CONFIG_MMCBOOTCOMMAND \
 	"bmode usb; " \
 
+#ifdef CONFIG_CMD_USB
+#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
+#else
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#endif
+
 #define CONFIG_ARP_TIMEOUT     200UL
 
 /* Miscellaneous configurable options */
-- 
cgit v0.10.2


From c26ffd9b3cc20143058bb8917a137f8a25249d9a Mon Sep 17 00:00:00 2001
From: Andrew Shadura <andrew.shadura@collabora.co.uk>
Date: Tue, 24 May 2016 15:56:20 +0200
Subject: board: ge: bx50v3: make network support optional and disabled by
 default

The network support is only useful for development and shouldn't be enabled
in production, so it has to be disabled in U-boot by default.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 98bf52e..a8628d2 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -9,9 +9,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index b66c98b..ce39521 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -9,9 +9,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 1cd126a..d2f6f86 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -9,9 +9,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 602763f..ccaa2b4 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -103,6 +103,7 @@
 #endif
 
 /* Networking Configs */
+#ifdef CONFIG_NET
 #define CONFIG_FEC_MXC
 #define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
@@ -111,6 +112,7 @@
 #define CONFIG_FEC_MXC_PHYADDR		4
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
+#endif
 
 /* Serial Flash */
 #ifdef CONFIG_CMD_SF
-- 
cgit v0.10.2


From aacc10c5be41dabdc7d8ad567b3bfff888ad4037 Mon Sep 17 00:00:00 2001
From: Andrew Shadura <andrew.shadura@collabora.co.uk>
Date: Tue, 24 May 2016 15:56:21 +0200
Subject: board: ge: bx50v3: make SATA optional and disabled by default

The SATA support is only useful for development and shouldn't be enabled
in production, so it has to be disabled in U-boot by default.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index ccaa2b4..98f20c6 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -60,13 +60,14 @@
 #define CONFIG_MXC_OCOTP
 
 /* SATA Configs */
-#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
 #define CONFIG_DWC_AHSATA
 #define CONFIG_SYS_SATA_MAX_DEVICE	1
 #define CONFIG_DWC_AHSATA_PORT_ID	0
 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
 #define CONFIG_LBA48
 #define CONFIG_LIBATA
+#endif
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
-- 
cgit v0.10.2


From f1249119bfc2e11f6c65f21d62e85f70aca46887 Mon Sep 17 00:00:00 2001
From: Andrew Shadura <andrew.shadura@collabora.co.uk>
Date: Tue, 24 May 2016 15:56:22 +0200
Subject: board: ge: bx50v3: disable unused features to improve size and boot
 speed

Disable unused FPGA, NFS, FAT and EFI support to reduce the bootloader
size. Don't clear memory reserved for malloc to improve boot speed.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index a8628d2..0ef418d 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -8,14 +8,18 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGA=n
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index ce39521..2af4b11 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -8,14 +8,18 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGA=n
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index d2f6f86..9e0c5eb 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -8,14 +8,18 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGA=n
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
-- 
cgit v0.10.2


From f6825e4a449f83517742de00c56ef6ce4fda8f5a Mon Sep 17 00:00:00 2001
From: Kimmo Surakka <kimmo.surakka@ge.com>
Date: Tue, 24 May 2016 15:56:23 +0200
Subject: board: ge: bx50v3: add missing partnum variable

Add missing ${partnum} to set rootdev correctly when
booting from USB or MMC.

Signed-off-by: Kimmo Surakka <kimmo.surakka@ge.com>
[Rebased against v2016.05 and adjusted the variable name]
Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>

diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 98f20c6..4033460 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -228,12 +228,12 @@
 
 #define CONFIG_MMCBOOTCOMMAND \
 	"setenv dev mmc; " \
-	"setenv rootdev mmcblk0p1; " \
+	"setenv rootdev mmcblk0p${partnum}; " \
 	\
 	"setenv devnum ${sddev}; " \
 	"if mmc dev ${devnum}; then " \
 		"run tryboot; " \
-		"setenv rootdev mmcblk1p1; " \
+		"setenv rootdev mmcblk1p${partnum}; " \
 	"fi; " \
 	\
 	"setenv devnum ${emmcdev}; " \
@@ -245,7 +245,7 @@
 	"usb start; " \
 	"setenv dev usb; " \
 	"setenv devnum 0; " \
-	"setenv rootdev sda1; " \
+	"setenv rootdev sda${partnum}; " \
 	"run tryboot; " \
 	\
 	CONFIG_MMCBOOTCOMMAND \
-- 
cgit v0.10.2


From d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 Mon Sep 17 00:00:00 2001
From: Michael Heimpold <michael.heimpold@i2se.com>
Date: Mon, 6 Jun 2016 14:26:39 +0200
Subject: arm: mxs: Remove misleading comments

Both comments look like being copy & paste errors.

Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index a6af0fc..2298620 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -167,9 +167,9 @@ const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
 	case MXC_CPU_MX23:
-		return "23";	/* Quad-Plus version of the mx6 */
+		return "23";
 	case MXC_CPU_MX28:
-		return "28";	/* Dual-Plus version of the mx6 */
+		return "28";
 	default:
 		return "??";
 	}
-- 
cgit v0.10.2


From 35546f6f2014282cc4f9772324b5588bd44a2938 Mon Sep 17 00:00:00 2001
From: Pavel Machek <pavel@denx.de>
Date: Tue, 7 Jun 2016 12:37:23 +0200
Subject: ARM: socfpga: add support for IS1 board

This adds support for IS1 board. Pretty usual socfpga board,
256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two
additional ethernet ports connected to the FPGA.

Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a827613..f81bd8b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -105,6 +105,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
new file mode 100644
index 0000000..16a3283
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -0,0 +1,106 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "SoCFPGA Cyclone V IS1";
+	compatible = "anonymous,socfpga-is1", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb1;
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom@51 {
+		compatible = "atmel,24c32";
+		reg = <0x51>;
+		pagesize = <32>;
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&mmc0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	cd-gpios = <&portb 18 0>;
+	vmmc-supply = <&regulator_3_3v>;
+	vqmmc-supply = <&regulator_3_3v>;
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	flash0: n25q00@0 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <100000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 1484607..c4432cf 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -35,6 +35,10 @@ config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_IS1
+	bool "IS1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	bool "samtec VIN|ING FPGA (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -53,6 +57,7 @@ config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "is1" if TARGET_SOCFPGA_IS1
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -75,6 +80,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
diff --git a/board/is1/MAINTAINERS b/board/is1/MAINTAINERS
new file mode 100644
index 0000000..a737e13
--- /dev/null
+++ b/board/is1/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCFPGA IS1 BOARD
+M:	Pavel Machek <pavel@denx.de>
+S:	Maintained
+F:	board/is1/
+F:	include/configs/socfpga_is1.h
+F:	configs/socfpga_is1_defconfig
diff --git a/board/is1/Makefile b/board/is1/Makefile
new file mode 100644
index 0000000..eae7ad0
--- /dev/null
+++ b/board/is1/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h
new file mode 100644
index 0000000..25b2232
--- /dev/null
+++ b/board/is1/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x000C0300,
+	0x300C0000,
+	0x30000000,
+	0x000000C0,
+	0x000300C0,
+	0x80008000,
+	0x0000007F,
+	0x0001FE00,
+	0x07F80000,
+	0xE0000000,
+	0x0000001F,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x00007F80,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00601806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x00100000,
+	0x300C0000,
+	0x0FF00000,
+	0x00000000,
+	0x00040000,
+	0x00008000,
+	0x00080000,
+	0x00000000,
+	0x18000000,
+	0x00000060,
+	0x06018060,
+	0x00004000,
+	0x0C0300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x06000018,
+	0x00006018,
+	0x01806018,
+	0x00001000,
+	0x0300C030,
+	0x0300C000,
+	0x0300000C,
+	0x0000300C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x08024001,
+	0x00100000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x00000000,
+	0x00000010,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x41034030,
+	0x02081A00,
+	0x80A280D0,
+	0x34051406,
+	0x01A02490,
+	0x280D0000,
+	0x30C0680A,
+	0x00000340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680A28,
+	0x49034030,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x30C0680A,
+	0x02490340,
+	0xD012481A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x69A47A05,
+	0xF228A3D5,
+	0xF6D1451E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xD569A47A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00035292,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x0000FF00,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0xF8482000,
+	0x00000007,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x8A28A3D5,
+	0xF4D1451E,
+	0x0352D348,
+	0x821A028A,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x0000FF00,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x08000000,
+	0x00000000,
+	0xF8000020,
+	0x00000007,
+	0x02000000,
+	0x00400000,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x00020080,
+	0x00000400,
+	0x04000000,
+	0xC8800000,
+	0x00003001,
+	0x00004000,
+	0x01000000,
+	0x00200000,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x02000000,
+	0x00000000,
+	0xFE000008,
+	0x00000001,
+	0x00800000,
+	0x00100000,
+	0x00000200,
+	0x08283380,
+	0x00000000,
+	0x00122C80,
+	0x1A000008,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x6800000D,
+	0x03400000,
+	0x001A0000,
+	0x0000D000,
+	0x00000680,
+	0xA0000034,
+	0x0D000001,
+	0x00680000,
+	0x00034000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x0000FF00,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00003FC0,
+	0x00800000,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x00040100,
+	0x00000800,
+	0x08000000,
+	0x00000000,
+	0xF8000020,
+	0x00000007,
+	0x02000000,
+	0x00400000,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x01000000,
+	0x00200000,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x00010040,
+	0x00000200,
+	0x02000000,
+	0x00000004,
+	0x00001008,
+	0x00402000,
+	0x00800000,
+	0x00100001,
+	0x00000200,
+	0x08283380,
+	0x00000000,
+	0x00102C80,
+	0x1A000008,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x6800000D,
+	0x03400000,
+	0x001A0000,
+	0x0000D000,
+	0x00000680,
+	0xA0000034,
+	0x0D000001,
+	0x00680000,
+	0x00034000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x0000FF00,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00003FC0,
+	0x00800000,
+	0x00489800,
+	0x9E1A0000,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0xC0000004,
+	0x0000003F,
+	0x0000FF00,
+	0x03FC0000,
+	0xF0000000,
+	0x0000000F,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0xE0000002,
+	0x0000001F,
+	0x00007F80,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0xF0000001,
+	0x0000000F,
+	0x00003FC0,
+	0x00FF0000,
+	0xFC000000,
+	0x00000003,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x0001FE00,
+	0x07F80000,
+	0xE0000000,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/is1/qts/pinmux_config.h b/board/is1/qts/pinmux_config.h
new file mode 100644
index 0000000..adb913c
--- /dev/null
+++ b/board/is1/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	0, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	0, /* FLASHIO2 */
+	0, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	0, /* FLASHIO9 */
+	0, /* FLASHIO10 */
+	0, /* FLASHIO11 */
+	3, /* GENERALIO0 */
+	3, /* GENERALIO1 */
+	3, /* GENERALIO2 */
+	3, /* GENERALIO3 */
+	3, /* GENERALIO4 */
+	3, /* GENERALIO5 */
+	3, /* GENERALIO6 */
+	3, /* GENERALIO7 */
+	3, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	3, /* GENERALIO13 */
+	3, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	2, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	0, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	0, /* GPLMUX57 */
+	0, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	0, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	0, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	1, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h
new file mode 100644
index 0000000..e775b9f
--- /dev/null
+++ b/board/is1/qts/pll_config.h
@@ -0,0 +1,85 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 375000000
+#define CONFIG_HPS_CLK_SPIM_HZ 12500000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
new file mode 100644
index 0000000..67ea1ec
--- /dev/null
+++ b/board/is1/qts/sdram_config.h
@@ -0,0 +1,341 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			64
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x777
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	2
+#define RW_MGR_MEM_DATA_WIDTH	16
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	2
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	2
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	2
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a00c8,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090130,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/is1/socfpga.c b/board/is1/socfpga.c
new file mode 100644
index 0000000..2a543bf
--- /dev/null
+++ b/board/is1/socfpga.c
@@ -0,0 +1,4 @@
+/*
+ * Currently nothing special is needed on this board, empty file to
+ * make build scripts happy
+ */
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
new file mode 100644
index 0000000..7d43c72
--- /dev/null
+++ b/configs/socfpga_is1_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_IS1=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_MEMTEST is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_MMC is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h
new file mode 100644
index 0000000..6f5dfce
--- /dev/null
+++ b/include/configs/socfpga_is1.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2016 Pavel Machek <pavel@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_IS1_H__
+#define __CONFIG_SOCFPGA_IS1_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x10000000
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ARP_TIMEOUT		500UL
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR       0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#endif	/* __CONFIG_SOCFPGA_IS1_H__ */
-- 
cgit v0.10.2


From cf0a8dab8ee8c1eafbcd9ed081f5cab15e5a58a5 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 8 Jun 2016 02:57:05 +0200
Subject: ARM: socfpga: Sort Kconfig entries

Just sort the board entries, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index c4432cf..1a43c7b 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -27,10 +27,6 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_SR1500
-	bool "SR1500 (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
-
 config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -43,6 +39,10 @@ config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	bool "samtec VIN|ING FPGA (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
-- 
cgit v0.10.2


From adb3928f152796e275f0535759796422d91f4709 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 4 Jun 2016 22:39:08 +0900
Subject: ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20

The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
from an eMMC device.  They are useful to reduce the memory footprint
of SPL, rather than compiling the whole MMC framework.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index d7fefc5..a898021 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -14,4 +14,8 @@ obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= boot-mode-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
 
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE)	+= spl_board.o
+else
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
+endif
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 4b744da..d34b9af 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -51,11 +51,30 @@ u32 spl_boot_device_raw(void)
 
 u32 spl_boot_device(void)
 {
-	u32 ret;
+	u32 mode;
 
-	ret = spl_boot_device_raw();
+	mode = spl_boot_device_raw();
 
-	return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret;
+	switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+	case SOC_UNIPHIER_PXS2:
+	case SOC_UNIPHIER_LD6B:
+		if (mode == BOOT_DEVICE_USB)
+			mode = BOOT_DEVICE_NOR;
+		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD11:
+	case SOC_UNIPHIER_LD20:
+		if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
+			mode = BOOT_DEVICE_BOARD;
+		break;
+#endif
+	default:
+		break;
+	}
+
+	return mode;
 }
 
 u32 spl_boot_mode(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c
new file mode 100644
index 0000000..86292b6
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <asm/processor.h>
+
+#include "../soc-info.h"
+
+void spl_board_announce_boot_device(void)
+{
+	printf("eMMC");
+}
+
+struct uniphier_romfunc_table {
+	void *mmc_send_cmd;
+	void *mmc_card_blockaddr;
+	void *mmc_switch_part;
+	void *mmc_load_image;
+};
+
+static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = {
+	.mmc_send_cmd = (void *)0x20d8,
+	.mmc_card_blockaddr = (void *)0x1b68,
+	.mmc_switch_part = (void *)0x1c38,
+	.mmc_load_image = (void *)0x2e48,
+};
+
+static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = {
+	.mmc_send_cmd = (void *)0x2130,
+	.mmc_card_blockaddr = (void *)0x1ba0,
+	.mmc_switch_part = (void *)0x1c70,
+	.mmc_load_image = (void *)0x2ef0,
+};
+
+int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32),
+				 int (**card_blockaddr)(u32),
+				 int (**switch_part)(int),
+				 int (**load_image)(u32, uintptr_t, u32))
+{
+	const struct uniphier_romfunc_table *table;
+
+	switch (uniphier_get_soc_type()) {
+	case SOC_UNIPHIER_LD11:
+		table = &uniphier_ld11_romfunc_table;
+		break;
+	case SOC_UNIPHIER_LD20:
+		table = &uniphier_ld20_romfunc_table;
+		break;
+	default:
+		printf("unsupported SoC\n");
+		return -EINVAL;
+	}
+
+	*send_cmd = table->mmc_send_cmd;
+	*card_blockaddr = table->mmc_card_blockaddr;
+	*switch_part = table->mmc_switch_part;
+	*load_image = table->mmc_load_image;
+
+	return 0;
+}
+
+int spl_board_load_image(void)
+{
+	int (*send_cmd)(u32 cmd, u32 arg);
+	int (*card_blockaddr)(u32 rca);
+	int (*switch_part)(int part);
+	int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt);
+	u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+	const u32 rca = 0x1000; /* RCA assigned by Boot ROM */
+	int ret;
+
+	ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr,
+					   &switch_part, &load_image);
+	if (ret)
+		return ret;
+
+	/*
+	 * deselect card before SEND_CSD command.
+	 * Do not check the return code.  It fails, but it is OK.
+	 */
+	(*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */
+
+	/* reset CMD Line */
+	writeb(0x6, 0x5a00022f);
+	while (readb(0x5a00022f))
+		cpu_relax();
+
+	ret = (*card_blockaddr)(rca);
+	if (ret) {
+		debug("card is block addressing\n");
+	} else {
+		debug("card is byte addressing\n");
+		dev_addr *= 512;
+	}
+
+	ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */
+	if (ret)
+		printf("failed to select card\n");
+
+	ret = (*switch_part)(1); /* Switch to Boot Partition 1 */
+	if (ret)
+		printf("failed to switch partition\n");
+
+	ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1);
+	if (ret) {
+		printf("failed to load image\n");
+		return ret;
+	}
+
+	ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE);
+	if (ret)
+		return ret;
+
+	ret = (*load_image)(dev_addr, spl_image.load_addr,
+			    spl_image.size / 512);
+	if (ret) {
+		printf("failed to load image\n");
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 10fd8c2..058ccd8 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -288,7 +288,9 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NOR_SUPPORT
-#ifndef CONFIG_ARM64
+#ifdef CONFIG_ARM64
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#else
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #endif
-- 
cgit v0.10.2


From 7760b49fa7fd383094dd7c5566c1382021664e95 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 4 Jun 2016 22:39:09 +0900
Subject: ARM: uniphier: fix boot mode for PH1-LD11

This function is shared between PH1-LD11 and PH1-LD20.  The difference
is the boot-mode latch for the USB boot mode.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
index 96a1270..24255a0 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -9,6 +9,7 @@
 #include <linux/io.h>
 
 #include "../sg-regs.h"
+#include "../soc-info.h"
 #include "boot-device.h"
 
 static struct boot_device_info boot_device_table[] = {
@@ -54,8 +55,24 @@ static int get_boot_mode_sel(void)
 u32 uniphier_ld20_boot_device(void)
 {
 	int boot_mode;
+	u32 usb_boot_mask;
 
-	if (~readl(SG_PINMON0) & 0x00000780)
+	switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	case SOC_UNIPHIER_LD11:
+		usb_boot_mask = 0x00000080;
+		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		usb_boot_mask = 0x00000780;
+		break;
+#endif
+	default:
+		BUG();
+	}
+
+	if (~readl(SG_PINMON0) & usb_boot_mask)
 		return BOOT_DEVICE_USB;
 
 	boot_mode = get_boot_mode_sel();
-- 
cgit v0.10.2


From 80630dad9d95f81a67d4b93e226a79e679393d31 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 7 Jun 2016 21:03:43 +0900
Subject: ARM: uniphier: check return code of setenv()

Because setenv() may fail, it is better to check its return code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 845f047..d9eeacb 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -56,9 +56,7 @@ static int uniphier_set_fdt_file(void)
 
 	strncat(dtb_name, ".dtb", buf_len);
 
-	setenv("fdt_file", dtb_name);
-
-	return 0;
+	return setenv("fdt_file", dtb_name);
 }
 
 int board_late_init(void)
-- 
cgit v0.10.2


From 4565a74d56351c99443f964bf81d49007d2be9c4 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 7 Jun 2016 21:03:44 +0900
Subject: ARM: uniphier: do not overwrite fdt_file environment

This code auto-detects the best-match FDT file name, but it should
respect the user's choice if "fdt_file" environment is found in a
saved set of environments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index d9eeacb..a454126 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -39,6 +39,9 @@ static int uniphier_set_fdt_file(void)
 	int buf_len = 256;
 	int ret;
 
+	if (getenv("fdt_file"))
+		return 0;	/* do nothing if it is already set */
+
 	ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat);
 	if (ret)
 		return -EINVAL;
-- 
cgit v0.10.2


From f7e9402b54db4bed916c9adb2565d9713ca5bbfa Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 7 Jun 2016 21:03:46 +0900
Subject: ARM: uniphier: do not erase when updating U-Boot image in eMMC device

Unlike NAND, eMMC can be re-written without erasing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 058ccd8..c826b20 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -245,7 +245,6 @@
 		"tftpboot $tmp_addr u-boot.bin\0"		\
 	"emmcupdate=mmcsetn &&"					\
 		"mmc partconf $mmc_first_dev 0 1 1 &&"		\
-		"mmc erase 0 800 &&"				\
 		"tftpboot u-boot-spl.bin &&"			\
 		"mmc write $loadaddr 0 80 &&"			\
 		"tftpboot u-boot.bin &&"			\
-- 
cgit v0.10.2


From 9c2f9b2da650907b928995350cc4e29480fb0f80 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 8 Jun 2016 18:02:32 +0900
Subject: ARM: uniphier: insert dsb barrier to ensure visibility of store

I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.

The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 64412e0..5971ad2 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void)
 	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
 
 	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
-	readq(rom_boot_rsv0);	/* relax */
 
 	unmap_sysmem(rom_boot_rsv0);
 
 	uniphier_smp_setup();
 
-	asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+	asm("dsb	ishst\n" /* Ensure the write to ROM_RSV0 is visible */
+	    "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
 }
-- 
cgit v0.10.2


From 3191d8408053674c1b9bb79a82e3973add48830c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 8 Jun 2016 20:55:15 -0600
Subject: tiny-printf: Correct the snprintf() implementation

This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.

This makes firefly-rk3288 boot again.

Fixes: abeb272 ("tiny-printf: Support snprintf()")
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 5ea2555..3c65fc9 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -168,8 +168,10 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
 	int ret;
 
 	va_start(va, fmt);
-	ret = sprintf(buf, fmt, va);
+	outstr = buf;
+	ret = _vprintf(fmt, va, putc_outstr);
 	va_end(va);
+	*outstr = '\0';
 
 	return ret;
 }
-- 
cgit v0.10.2


From bb597c0eeb7ee2f6e983577d993c76a30dd3c2b4 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:14 +0200
Subject: common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig option

move CONFIG_BOOTDELAY into a Kconfig option. Used for this
purpose the moveconfig.py tool in tools.

Signed-off-by: Heiko Schocher <hs@denx.de>

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>

diff --git a/common/Kconfig b/common/Kconfig
index 067545d..4d17b10 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -97,6 +97,15 @@ config BOOTSTAGE_STASH_SIZE
 
 endmenu
 
+config BOOTDELAY
+	int "delay in seconds before automatically booting"
+	default 0
+	help
+	  Delay before automatically running bootcmd;
+	  set to -1 to disable autoboot.
+	  set to -2 to autoboot with no delay and not check for abort
+	  (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
+
 config CONSOLE_RECORD
 	bool "Console recording"
 	help
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 8cb7ac7..378f7a1 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_EMR1=4
 CONFIG_SYS_CLK_FREQ=912000000
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index e4168fa..f121cab 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -14,6 +14,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_USB_EHCI_HCD=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 6430606..57609b3 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -17,6 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
-CONFIG_USB_EHCI_HCD=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index 369afbb..06d89af 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 408e84e..0e2d3f9 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index bab96ca..36986b5 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 10fe1d0..6aea615 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 5e754eb..505e014 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index fca6f5a..4696d6d 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index e833e0c..dfbf2cb 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index cd27638..b6c45ea 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index cdfccbe..85d4a85 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 555e446..2937dc3 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 014916c..fd33d14 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index 941fe75..572de82 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index ae8271b..523b7ad 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index 502ba3c..f15c4a1 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index d60c0c1..6d685b6 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 43fa804..7cdc2b2 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index adc42c5..8fdc698 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index d591a37..c40b6fe 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 034109e..b5fc433 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index c804b4f..c4bbb51 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 49609b7..456fb8d 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index a64db9bb..867e433 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 0850d84..effdd33 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index 7d7ecd2..3d86331 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index a46d8d7..0ac319c 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index 3ef15fc..25e5afa 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 307813c..00fe70b 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index aef5e7b..f20f231 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 3e8c0a1..19ae280 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -13,10 +13,10 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
 CONFIG_G_DNL_VENDOR_NUM=0x1f3a
 CONFIG_G_DNL_PRODUCT_NUM=0x1010
-CONFIG_USB_EHCI_HCD=y
diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig
index ea0775d..99e4ad0 100644
--- a/configs/CPCI2DP_defconfig
+++ b/configs/CPCI2DP_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CPCI2DP=y
+CONFIG_BOOTDELAY=3
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig
index 25818bd..d7c71c1 100644
--- a/configs/CPCI4052_defconfig
+++ b/configs/CPCI4052_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CPCI4052=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 3257aae..4b9abea 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index c884115..97bdcd6 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 725652d..f2c6fe7 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_A83T=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
 CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index 78e94ab..d53c629 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index f03d738..a7c6307 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index fef3685..77e496c 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB09"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 9d8d325..94aab9d 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_USB1_VBUS_PIN=""
 CONFIG_USB2_VBUS_PIN=""
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index 93e39b4..3606700 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index b63386d..af463c3 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_TEXT_BASE=0x43E00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index fc29e30..e758873 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5253DEMO=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig
index 15c22df..17ded58 100644
--- a/configs/M5253EVBE_defconfig
+++ b/configs/M5253EVBE_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5253EVBE=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_CACHE=y
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 585ea17..7638b18 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5272C3=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index cd75118..a7af356 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5275EVB=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index df12b3a..f415f7b 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5282EVB=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig
index 0d0c029..c9913ae 100644
--- a/configs/MIP405T_defconfig
+++ b/configs/MIP405T_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
 CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig
index aa23499..1d8e38e 100644
--- a/configs/MIP405_defconfig
+++ b/configs/MIP405_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 9e6f50b..4e25193 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 978e231..2fdffa9 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 35db541..56538cc 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 63c6d7b..efabb9a 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index a3d5294..be0e274 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index dfb41f0..f2aef33 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8315ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index cf2f655..5e5a2d0 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8323ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index 0c85f40..72aacf3 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index e9cf0c8..3e7390f 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 9272431..c65d3c9 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index d807884..5c95787 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 8900665..4d7c52f 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 60561cf..7ed7923 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index fb7485c..f1afcf8 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 65edb63..5c9f7fc 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 358656e..df08fe3 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 0e09e77..d8b5607 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index f7ad159..c04c256 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 1b2c787..0d6e4b6 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index 40d1a3a..2ffc647 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index c6afe45..5f4d51a 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index eafa11c..0fdc9de 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index 0ae81ef..13e06d6 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
index 401a86d..e3cb0d5 100644
--- a/configs/MPC8540ADS_defconfig
+++ b/configs/MPC8540ADS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8540ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PING=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index ddc3b5b..1ea8800 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index a340c8b..ae529d1 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index 06569e2..ecb05ac 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8544DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index d038267..066eaf2 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index a42d991..ee400a3 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 3a730f9..b733461 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index 86db71c..da42112 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index 485e987..fb14891 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig
index 19407b3..67063c8 100644
--- a/configs/MPC8560ADS_defconfig
+++ b/configs/MPC8560ADS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8560ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PING=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 5ec3712..2e7dceb 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8568MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index daacef7..505a853 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="ATM"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index 26ab184..0f9cc2f 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index 1720d9e..8218ef6 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 63cf745..6c65fbe 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index 6883249..10607e8 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8610HPCD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index c85ddfe..b90e6ea 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index d71369e..d8f74b3 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index cef9794..d230a68 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index f076e30..64f2c74 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 53e023a..198fda9 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -5,7 +5,6 @@ CONFIG_DRAM_CLK=360
 CONFIG_DRAM_ZQ=123
 CONFIG_SYS_CLK_FREQ=1008000000
 CONFIG_MMC0_CD_PIN="PH18"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig
index 57b7db4..129403c 100644
--- a/configs/MigoR_defconfig
+++ b/configs/MigoR_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MIGOR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 53f9bfe..f96757e 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index bad6a39..39fdf6a 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index f7d7f00..3b36d8f 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D300=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index 31e309f..977da33 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index eb65c22..32e475d 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index 67a7757..22e8357 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index 7a29872..a1c2794 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2I=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index 4f35c2e..f33496c 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index 77d1879..04a8fdd 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index 6d91a11..2e4b8ab 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index e135f93..9176431 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index b6bc88e..55054ac 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O3DNT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index af6a4be..5e05795 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 5ed93a1..5e12add 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 2c05f6e..b63475c 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 4dbff83..74168da 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index f421b22..2e34a10 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index f0a74fd..d5bf946 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 6bd7dcb..aa08a59 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index b8968a8..a745bb9 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 551b9db..8ac7c11 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index 7d8ebfe..808851a 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 6fd23ac..ca3ba08 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 1f29b11..dff79c6 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 6da92e4..800e7b9 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index fa7cab8..e1be2eb 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 860bc6a..e8564f9 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 23d938b..425344b 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index 5bc446b..dce2a1a 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 7b83294..883de6f 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 234645e..381caad 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 7adcca8..293a945 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index c455059..0c8ae44 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 45f54f7..880be23 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 7d6de18..d6f4f58 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index 629fbbb..a875553 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 8f44aee..3e96631 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 37ebca3..5adfa49 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 6d6edd1..be7f0e2 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index d21afae..f82850c 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index a0e4471..bb27831 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index d209581..79a4282 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index d07ed43..9b6370d 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 0fe87d1..5c5eb5e 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 735c53f..1c98b55 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 953552d..e5bff61 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index ec94e06..dda50fb 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 044e739..b693705 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 3bd72f0..3d4a746e0 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index a9a659c..121ff79 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index f01dbc3..9dde9c7 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 37e14da..8ee1fa4 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 63faa06..a296fee 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 255b8e2..045216c 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 61a635a..7ff3b74 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index f8e633a..32c5047 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index d6775d9..6dfe195 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 054e9fc..98f9285 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index b0553ef..136e5ac 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 36f7366..42f28cd 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index b24f8ec..eeb232d 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 8f618ae..d2f83fa 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 70e4d44..09ba6ea 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index e119bef..7652d29 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 772a313..a49dfca 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 9206cc7..c2d23b8 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 85c03aa..facbf9e 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index ae78a8e..eebc69b 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index af98b8e..352305d 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 0ea0201..68a6c11 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index 4093449..21300da 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 24e8678..c63abc3 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index cbc3d76..6d90082 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 8c36f58..7643544 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index 1c7b323..2e96cb2 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index b5dee33..679353e 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index bcc0aed..d3731a8 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index dc74708..2a53c57 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index a59ddde..dc93a19 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 9993593..b41e590 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 8f723c6..5541bf9 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index 5285f79..9864486 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index ec6038c..8a3b804 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 6ba76fa..eed1833 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 86b9cd7..89daf1c 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index f7ce9b6..746e150 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 21d98e3..2421a73 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index ce42c82..fce023b 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index c8f86e2..a316264 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index a6a01e8..0bc2d1a 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 0f10e08..cf1ccbf 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 8649e52..e8b6e2a 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 1764f2c..bfbaea1 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index b9610e4..82e7b4b 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index d4b1c55..66f6ec4 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index a36e731..5901458 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 4d40511..b7f3a0d 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index c2dbd98..7f07d2d 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index 3dbf5a3..a767520 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index aea98c6..17e2ad5 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index d5b1c12..c2790b2 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index dfe0e17..1c863de 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index a8e2131..028b9f0 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index 13e2fed..d1b3f70 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 901c373..acce084 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index f9285a8..d20defa 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index d648d97..641f263 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index aaa97f7..deba469 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 437e05a..68c910e 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index a3f0d85..130e2f4 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index 7059c81..b47fc08 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 752a6c6..f9a7ed3 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 2ecb0b8..ae9843c 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index c26e729..3edbee0 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index acc617e..b7a2f1d 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 24d4f17..9523a07 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 3e97ee0..93d92d3 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index f381326..b590651 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index d7145ae..8b8e557 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 0495c4d..e45ed75 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 9be5ff1..73b2216 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 6675164..72923ca 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 552d93a..21a7ba5 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 2caec57..0722667 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 07e67c8..9c3a2ce 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig
index ae95732..53fdfad 100644
--- a/configs/PATI_defconfig
+++ b/configs/PATI_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_5xx=y
 CONFIG_TARGET_PATI=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="pati=> "
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig
index fe88739..dee793b 100644
--- a/configs/PIP405_defconfig
+++ b/configs/PIP405_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PIP405=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig
index c1795a4..a0e8411 100644
--- a/configs/PLU405_defconfig
+++ b/configs/PLU405_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PLU405=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig
index 8f60d87..cdb82d6 100644
--- a/configs/PMC405DE_defconfig
+++ b/configs/PMC405DE_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PMC405DE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig
index 4d060ab..704cd36 100644
--- a/configs/PMC440_defconfig
+++ b/configs/PMC440_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PMC440=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 9a916c9..32df4e5 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 2c41d03..069f5d3 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index e3cf48d..984e60b 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 5ce9ed9..109cade 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index 44c9584..de0d50c 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index 6c4505f..6253b05 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 0af7eab..71ff166 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index efdcbeb..04204fb 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 12a0376..80dd6df 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index 84da583..21f7ed4 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 03d009f..a869853 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index a70963f..c824674 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index a012f3d..ce0ba29 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index d7cce8b..21707f6 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index ceae6cf..5578976 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 1359aad..6a9df48 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 7ffacd4..d54b835 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index a07a59a..9295c61 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index e4c095e..de3aef0 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index a2c1495..fe7b9d1 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 9a78aa9..b762e19 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index f2415d9..4147f38 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index df9e295..11ff5f0 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index 7f889c7..33c6772 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index f93f0b9..fd512db 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 023dc37..8f99f8f 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index bacb060..899339a 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 9d6d9fb..4e5682c 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index b5a050c..a202595 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index a50f177..e2a8321 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index f70d5ce..17b6b83 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 4f21813..097bb8a 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 07bdcf6..fa0e2a6 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index a49d32d..6dd0cdb 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 23f83e6..60fc267 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 1935dad..106b2f0 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index f093e92..3dd11a5 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index f7126e5..5af1987 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index f0aed08..2c72833 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 0057e22..c777714 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 8905b6c..bb1bee7 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 2459eba..e4aec61 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index b937af4..d314307 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 049819e..5e56358 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 8634477..cf15e00 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 40c871e..db6e7fb 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 795a3f0..d5f1de5 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index c6e0710..673655c 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 51caeeb..32c0a57 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index f4190af..af64f23 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 9d4821d..75a56d5 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index 0a15e05..b1cacf7 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 955b394..1161f08 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 0b0e120..1e196a0 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index bffca40..85029cf 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index fc8f1f5..66350d0 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index ed075eb..88702bc 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index 844fe10..d8fadec 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 92b0391..4e7dbe5 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index 2a30e11..d704179 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 37aac2a..560fce8 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 3b13a34..a9cd51c 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 3523fe1..9adcc21 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index c2a16fd..7ce7ff0 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 3ec6c75..9fd17a9 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 18c8e67..2d6b47f 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index c590410..193d54c 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index afb665d..4a24184 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 85fd13b..27093ec 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 21e22be..c14f9b8 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index 7adc71c..6a14703 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index f098954..0d8f096 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index 70eb383..9c310aa 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index 6734495..da88fcc 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index d0adb77..9926fd7 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index 4456361..fe68631 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index 9bf21f5..38f5119 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -3,6 +3,7 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 9f3218b..3bc2934 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index 9a0ba9d..9d40a1f 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 00dd80d..b56d780 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_TQM834X=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 088ed6d..8427f58 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index ab3c44b..1c3f424 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index 6ece068..0234813 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index 9940f96..15541e5 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index 4aec4ff..becd4e1 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index 12b090a..3b27e7f 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index 41737a3..36e2433 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index 642dd02..84d2cb2 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index 3d0bf8c..ddde240 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM866M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index 2238cdd..92b34f6 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM885D=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index df4efa4..e545848 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -3,6 +3,7 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 8d2f2e6..ae8feda 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
index 4c2df57..550e6b8 100644
--- a/configs/VCMA9_defconfig
+++ b/configs/VCMA9_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_VCMA9=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VCMA9 # "
 CONFIG_CMD_I2C=y
diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig
index 8fb023a..800731b 100644
--- a/configs/VOM405_defconfig
+++ b/configs/VOM405_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_VOM405=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index 97e4fc5..c620183 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_A3M071=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index fc344c5..61f7da7 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index 31889fa..24d802e 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ACADIA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 6daefcc..0def407 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -1,5 +1,6 @@
 CONFIG_NDS32=y
 CONFIG_TARGET_ADP_AG101P=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="NDS32 # "
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index bfa243f..661d544 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_ALT=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 696024c..3a1e5a4 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -4,7 +4,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -27,6 +29,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
@@ -42,10 +45,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
 CONFIG_RSA=y
-CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 76a004e..f230671 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 99fc555..3fbc07b 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -35,4 +35,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index d5aa3a2..65d88d8 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index cba5e84..eee5e9b 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 3cd40e9..c227ef4 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -25,4 +25,3 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index a8b8465..6d1dcde 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_AM3517_CRANE=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_CRANE # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index d400c35..b4aa3c6 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AM3517_EVM=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_EVM # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
index 3cd39eb..95b28fb 100644
--- a/configs/am437x_hs_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -2,13 +2,12 @@ CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-# Device tree file can be same on HS evm
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
-CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 3b958d7..9cdae19 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -41,4 +41,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 5264332..7b345ad 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -41,4 +41,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 34c875e..6b53eba 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,14 +1,16 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
-CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -31,6 +33,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -51,9 +54,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
-CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 6743b84..b63ff89 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -7,9 +7,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index c109939..aa459a1 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -8,9 +8,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index 91fa734..fbd63e9 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_ARCH_ATH79=y
 CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="ap121 # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,13 +20,9 @@ CONFIG_SYS_PROMPT="ap121 # "
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_NET=y
-CONFIG_CMD_NFS=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_ETH=y
-CONFIG_AG7XXX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_ATMEL=y
@@ -38,6 +35,8 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_DATAFLASH=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_AR933X_PINCTRL=y
@@ -48,5 +47,3 @@ CONFIG_DEBUG_UART_CLOCK=25000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_AR933X_UART=y
 CONFIG_ATH79_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
index 1aa6e5d..15fe36f 100644
--- a/configs/ap143_defconfig
+++ b/configs/ap143_defconfig
@@ -6,6 +6,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_ARCH_ATH79=y
 CONFIG_TARGET_AP143=y
 CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="ap143 # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -43,5 +44,3 @@ CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
 CONFIG_ATH79_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig
index 5192032..51a48de 100644
--- a/configs/ap325rxa_defconfig
+++ b/configs/ap325rxa_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_AP325RXA=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig
index 77a0aa5..73e6f04 100644
--- a/configs/ap_sh4a_4a_defconfig
+++ b/configs/ap_sh4a_4a_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_AP_SH4A_4A=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 40a65d2..17e8595 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -38,4 +38,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 88912e5..a175274 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_APF27=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="BIOS> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig
index 4c6fcb0..c0c2e4b 100644
--- a/configs/arcangel4-be_defconfig
+++ b/configs/arcangel4-be_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=70000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig
index 2157e0c..efa55d0 100644
--- a/configs/arcangel4_defconfig
+++ b/configs/arcangel4_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=70000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="arcangel4# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index e05a64c..d97715b 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_ARCHES=y
 CONFIG_DEFAULT_DEVICE_TREE="arches"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index fb3257b..14919e5 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_ARIA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 1224da4..9bae3c3 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
index 4f5df35..9ac6657 100644
--- a/configs/aspenite_defconfig
+++ b/configs/aspenite_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ASPENITE=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index bea73a5..f1303b3 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 8012531..8b00ee2 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index d8ec7f1..5a369bb 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index eb17f91..b465395 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index 26ffd97..a30c40b 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 4e8dfa1..4406e58 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index c5684f2..2d59915 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 0fba314..45bc427 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index b09395f..c94e7a4 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index b09395f..c94e7a4 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index dd46a68..05c3f3d 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 25b9a17..eb20eba 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 3cdce9b..aed72da 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 9ff65b5..f829a18 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 76c3b15..a4b9719 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 7438b86..199b5bb 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 0cded82..bb176a0 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index ddfce14..7287860 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 8ce99ee..ffc3a95 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 9ed2b84..9069f30 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index f8f6afb..eaaa6ae 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index c931af2..5452afd 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 4aeca48..011fdad 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 2c4a81a..e61f3b9 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 726d811..62efd6e 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index d0cff22..6a54f03 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index dda3edf..69be1d2 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index c300438..c49bf18 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 6b033fb..142122e 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index 56aa2a0..85ed41c 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index db501c5..cecd416 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 7f0b1a4..002c833 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index f7a4d16..cefe859 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 0ded2ab..77c65b2 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 7995419..9eaf146 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index c859cb6..b17b9a5 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index ba43e35..0e0eadf 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TAURUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 07a6a18..10e802d 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=750000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 01a5143..96a3de6 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=50000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 1cfb380..6da4b69 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=384
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index b0f6bb3..e1f1f3d 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BAMBOO=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 4404f32..71a52a1 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -22,4 +23,3 @@ CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
 CONFIG_G_DNL_PRODUCT_NUM=0x0d02
 CONFIG_OF_LIBFDT=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 60eb328..97fe622 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
 CONFIG_HUSH_PARSER=y
@@ -22,4 +23,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
 CONFIG_G_DNL_PRODUCT_NUM=0x0d02
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index b9323c2..8557c02 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -44,4 +44,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig
index 84f229f..68d2f48 100644
--- a/configs/bf525-ucr2_defconfig
+++ b/configs/bf525-ucr2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF525_UCR2=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
index 7c17cbb..fea8c32 100644
--- a/configs/bf537-minotaur_defconfig
+++ b/configs/bf537-minotaur_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_MINOTAUR=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="minotaur> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
index f8288d9..dc88c44 100644
--- a/configs/bf537-srv1_defconfig
+++ b/configs/bf537-srv1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_SRV1=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="srv1> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 709dfab..b3a13c6 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BG0900=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index bb5db5c..44ed671 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 39cc222..861bdcf 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -38,4 +38,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig
index 679aee1..7aa5a52 100644
--- a/configs/blackstamp_defconfig
+++ b/configs/blackstamp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BLACKSTAMP=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig
index 808cc3d..7c3eb9d 100644
--- a/configs/blackvme_defconfig
+++ b/configs/blackvme_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BLACKVME=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index d570d41..9bfe828 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BUBINGA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 2eefd15..c2e454a 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index 7224588..f2da039 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index 00d8045..d04ac55 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig
index 8d3b476..f1e3265 100644
--- a/configs/canmb_defconfig
+++ b/configs/canmb_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CANMB=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index aac031b..fe9fbd0 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_CANYONLANDS=y
 CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 979b693..ee8e793 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -36,4 +36,3 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index ea50729..ae9b62a 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CHARON=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index d5bc515..6bebcee 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -73,7 +73,6 @@ CONFIG_ROCKCHIP_SPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 75ea200..3bf5388 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -3,8 +3,9 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
-CONFIG_HUSH_PARSER=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
index c7df400..2a67b43 100644
--- a/configs/cm5200_defconfig
+++ b/configs/cm5200_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 72283a6..bbb76a5 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T3517=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3517 # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 9a7b205..110e002 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T35=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3x # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index bcab16b..4f2425b 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP54XX=y
 CONFIG_TARGET_CM_T54=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T54 # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 3cb69ac..400fca0 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_COBRA5272=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="COBRA > "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index a3b2a3c..a0c40fe 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -44,4 +44,3 @@ CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index c920b39..c7f6982 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -36,4 +36,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index 7cc9a6e..aff6328 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index ee7739a..74b67f7 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 37488dd..2efffb5 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_CORVUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 0b77b1b..8282e25 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="d2v2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index 8fd51ad..69839df 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 866d187..0e281a5 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 0bb2d37..9c5428d 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CMD_ASKENV=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 75eaad8..980e153 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -42,4 +42,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index e9ba1ef..f06f27f 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_DB_88F6720=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 7ad3bb6..123e7fc 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_88F6820_GP=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 44f64fd..f2c4a9e 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_DB_MV784MP_GP=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig
index c3fa26f..996e2f7 100644
--- a/configs/dbau1000_defconfig
+++ b/configs/dbau1000_defconfig
@@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig
index 5e2c9bd..2b3ccd8 100644
--- a/configs/dbau1100_defconfig
+++ b/configs/dbau1100_defconfig
@@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig
index 10fe8aa..7459c63 100644
--- a/configs/dbau1500_defconfig
+++ b/configs/dbau1500_defconfig
@@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig
index 7f1bdf4..964d8a8 100644
--- a/configs/dbau1550_defconfig
+++ b/configs/dbau1550_defconfig
@@ -9,4 +9,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig
index 6cd0161..dfe0102 100644
--- a/configs/dbau1550_el_defconfig
+++ b/configs/dbau1550_el_defconfig
@@ -10,4 +10,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index 5449cff..bf7f545 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index 1ebfd23..e22461d 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION_10G=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index 7b28d1d..fba3611 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index a3d053d..e997f6d 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DNS325=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 6ae447c..2d99796 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DOCKSTAR=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="DockStar> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 756af63..1237a73 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -9,9 +9,11 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
@@ -32,6 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -53,7 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 6933ab5..0724916 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_DRA7XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_SPI=y
@@ -11,9 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
@@ -34,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -55,7 +58,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 0a437ed..d17e42f 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DRACO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index d293e30..8f745f8 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DREAMPLUG=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 4d3cb34..a214732 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DS414=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index f8155b2..ba50ce0 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index d6e51f8..57df04f 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_EA20=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ea20 > "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 55d5552..bf9177b 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_EB_CPU5282=y
 CONFIG_SYS_TEXT_BASE=0xFF000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="\nEB+CPU5282> "
 # CONFIG_CMD_LOADB is not set
 CONFIG_CMD_I2C=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index e204ba2..4f6de89 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_EB_CPU5282=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_LOADB is not set
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 467a0a1..b81ad58 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_ECO5PK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ECO5-PK # "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig
index 0066c7d..a23f52a 100644
--- a/configs/ecovec_defconfig
+++ b/configs/ecovec_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_ECOVEC=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index fa7c1b5..e57dfda 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ORION5X=y
 CONFIG_TARGET_EDMINIV2=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="EDMiniV2> "
 CONFIG_CMD_I2C=y
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
index 0fe2759..8d0bace 100644
--- a/configs/espresso7420_defconfig
+++ b/configs/espresso7420_defconfig
@@ -1,9 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS7=y
-CONFIG_TARGET_ESPRESSO7420=y
-CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
 CONFIG_SYS_PROMPT="ESPRESSO7420 # "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 579efd3..a88d37b 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_ETHERNUT5=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 9894fff..3f77981 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -39,6 +39,5 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 4af9120..a64f6de 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -65,7 +65,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 298888c..f6e01c1 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_FLEA3=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="flea3 U-Boot > "
 CONFIG_CMD_SPI=y
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index babfaf4..aad6eaa 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="FO300"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index eacd4bb..ef4c4ed 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_GDPPC440ETX=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 6d0dabe..d8b4227 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index e7e1287..2875492 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index ee02469..cf25116 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_GOFLEXHOME=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="GoFlexHome> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 9f6589a..f2075fe 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_GOSE=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index 2bdd0e7..9fee96a 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_GPLUGD=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
index d3f9c02..b30590e 100644
--- a/configs/gr_cpci_ax2000_defconfig
+++ b/configs/gr_cpci_ax2000_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GR_CPCI_AX2000=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GR_CPCI_AX2000=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
index 29c7f29..302d936 100644
--- a/configs/gr_ep2s60_defconfig
+++ b/configs/gr_ep2s60_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GR_EP2S60=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GR_EP2S60=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
index e4877f2..d6ed305 100644
--- a/configs/gr_xc3s_1500_defconfig
+++ b/configs/gr_xc3s_1500_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GR_XC3S_1500=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GR_XC3S_1500=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig
index d2f709f..f827113 100644
--- a/configs/grsim_defconfig
+++ b/configs/grsim_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GRSIM=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GRSIM=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig
index 9c9c968..f5e7c43 100644
--- a/configs/grsim_leon2_defconfig
+++ b/configs/grsim_leon2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GRSIM_LEON2=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GRSIM_LEON2=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 0baf3a3..31794b9 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_GURUPLUG=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index e04d96b..c4bd2c5 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_A83T=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB0_VBUS_PIN="PL5"
 CONFIG_USB1_VBUS_PIN="PL6"
 CONFIG_AXP_GPIO=y
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index c90eff4..4130e27 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 129a72b..16b0297 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -35,4 +35,3 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index d150dd3..ba0a37e 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
@@ -13,5 +14,3 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_LIBFDT=y
-CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 32d0486..f67eda7 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 657826a..5eff4ac 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 7ec54a7..ebf103a 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_MMC0_CD_PIN="PH1"
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 5e68769..2cadf17 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=127
 CONFIG_DRAM_EMR1=4
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 265114f..3b24256 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_IB62X0=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ib62x0 => "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index d32bbc4..a2a7073 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ICON=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 44a474e..516b239 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_ICONNECT=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="iconnect => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
index e824616..136b9d1 100644
--- a/configs/imx31_phycore_defconfig
+++ b/configs/imx31_phycore_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_IMX31_PHYCORE=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="uboot> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig
index afe3c3c..96252c3 100644
--- a/configs/imx31_phycore_eet_defconfig
+++ b/configs/imx31_phycore_eet_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_IMX31_PHYCORE=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index a8b32cb..e84ed57 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index 0b03e16..2444a38 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 153450f..a2489c4 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 483703a..3cbff46 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index 512d4a8..cd0f234 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="INTIB"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index afc5a83..27ffaea 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_IO64=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/io_defconfig b/configs/io_defconfig
index 1bb9248..2392d9b 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_IO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index 2e66b94..c7b3b27 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_IOCON=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
index e0b4390..19f53df 100644
--- a/configs/ipek01_defconfig
+++ b/configs/ipek01_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_IPEK01=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 9cb8b1d..a9b9084 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=312
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 7b04a0c..f672aa2 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -44,4 +44,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig
index 21c448b..48249b0 100644
--- a/configs/jupiter_defconfig
+++ b/configs/jupiter_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_JUPITER=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index b3e61f8..30c8bf0 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_KATMAI=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index f85cfbb..698de8c 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 5c45f7b..217a868 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_KOELSCH=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 0ff6c6b..bed9df8 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -34,6 +34,5 @@ CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
 CONFIG_RAM=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index e3902ce..00a5441 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_KZM9G=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="KZM-A9-GT# "
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_I2C=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index c262117..19dd1fe 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_LAGER=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 04189de..1aed0c4 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AFRDM=y
 # CONFIG_SYS_MALLOC_F is not set
-CONFIG_SPI_FLASH=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
@@ -10,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
@@ -25,6 +25,7 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
+CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 935f2fd..86ddf71 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AQDS=y
 # CONFIG_SYS_MALLOC_F is not set
-CONFIG_SPI_FLASH=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
@@ -10,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
+CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 5c28bd1..3806412 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012ARDB=y
 # CONFIG_SYS_MALLOC_F is not set
-CONFIG_SPI_FLASH=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
@@ -10,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
+CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index efaa7a9..6012d49 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -2,12 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 9fa5cb9..685f1da 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -2,12 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 24b7a15..eca1cca 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -25,5 +28,3 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 5d2b57d..a39a403 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 # CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -27,5 +30,3 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 426a4be..6748546 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -2,11 +2,11 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 4f5c1e8..81035c9 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -2,12 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 6a791c0..a1504c3 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -2,12 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 33e5c0c..f8bdfe8 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
-CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index 45f0f73..a1ee5b9 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -2,11 +2,11 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
-CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 16243ee..0d406ac 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 # CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -27,5 +30,3 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 3158340..a6be6c6 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -2,11 +2,11 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index bbeb4bf..3b6c5cf 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -2,12 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 6910c4e..0a6cbcd 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -2,12 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index f59ad74..2128c46 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -24,5 +27,3 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 90f810a..8d1f8ed 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -3,12 +3,12 @@ CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_LIBFDT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 1fbfd38..8dfad69 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 6b628d3..56f5efe 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 90f870a..6136887 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 813c269..7c78b6e 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index e665ba4..2b2a714 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 03a263a..f90a6be 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 0062f5c..d85f771 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index bace827..218dd76 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 48a89ab..983e4c2 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 627a90d..c420548 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index c676a91..a5a870b 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index 56922dc..21a0283 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -25,5 +26,4 @@ CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-EMU"
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index f27fbb7..1b670b0 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -28,5 +29,4 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.LS2080A-SIMU"
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 49a4a26..947ac3d 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index c305345..cd8a7bd 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 8a6dd14..8c5b69d 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index a2d88cc..8f98720 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index dc2b872..c0b8a98 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index dbba8ab..26ffe98 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 4af7e5d..002ca44 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 5bcd367..4f63da9 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index e0fa805..90801f4 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_LUAN=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index 64794a1..eaf6c97 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_LWMON5=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index c598c72..b505d29 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_M28EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 62496c3..962e036 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_M53EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index 81a6700..75affaa 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MA5D4EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index 8f7baea..4967e10 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MAKALU=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index 7bef84c..590f9b5 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -13,4 +13,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 47ded9e..ff93931 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -14,4 +14,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index 3c3bb16..3a87586 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -12,4 +12,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index b245d91..11ff259 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -13,4 +13,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 7a5eeba..b67bc51 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MAXBCM=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index ab814cc..2e819e4 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_MCX=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mcx # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index 9597482..98f0068 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MECP5123=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 02eb704..4dd4dce 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -34,4 +34,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 3d295f5..b214a92 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index aac7cc5..727d193 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index d38bc7f..63b6a76 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_USB2_VBUS_PIN="PH12"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index de1b73f..c366411 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index 34935ad..4bc7e43 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 664d949..6c942fc 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 1f28c08..a1fdcf2 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308_P1M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig
index a9bc3d4..026f566 100644
--- a/configs/ms7722se_defconfig
+++ b/configs/ms7722se_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MS7722SE=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index dda0daa..af58328 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_MT_VENTOUX=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mt_ventoux => "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
index eabfe1e..169fc93 100644
--- a/configs/munices_defconfig
+++ b/configs/munices_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_MUNICES=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index e201abb..a028482 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX23_OLINUXINO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig
index 9ccf069..b4c2ad3 100644
--- a/configs/mx31ads_defconfig
+++ b/configs/mx31ads_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX31ADS=y
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index 500b39c..7a62c2b 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 45f5e45..9a05a8b 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index c24aec6..93b20d7 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53SMD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index f904e12..224b5b7 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NAS220=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nas220> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index e306d68..b61b719 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_NEO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index f930e47..fcd4b13 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="2big2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 7917336..a117946 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 55978f2..e4a1149 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index 67b142d..f46b9a1 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 8199bbd..1b76bc2 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 6eb01ea..da10392 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_BOOTDELAY=30
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Nokia RX-51 # "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index 51da5ad..fdec8dc 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NSA310S=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nsa310s => "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 262042d..6cf304f 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -61,6 +61,5 @@ CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
 CONFIG_VIDEO_BRIDGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index c1d0fc3..44b5c16 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS5=y
-CONFIG_TARGET_ODROID_XU3=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 1a9f207..adca570 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 5f0dece..e446586 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TAO3530=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index e7bf385..b8c7621 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_LOGIC=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
@@ -34,4 +33,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="TI"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 4d5e8a0..51dc1db 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_OMAPL138_LCDK=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 7001921..2f40355 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index fd53c78..336104e 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 52b9a5b..11a49fe 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 8b1082c..d5383d4 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -4,9 +4,7 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB1_VBUS_PIN="PG13"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index be8afca..9b6a1af 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -4,8 +4,6 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7eaa795..7f360f5 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 9ff4332..88df360 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,10 +4,8 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PG13"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
index 9f2c418..1136e1f 100644
--- a/configs/p2771-0000_defconfig
+++ b/configs/p2771-0000_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA186=y
-CONFIG_TARGET_P2771_0000=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 0fe43b1..64b956f 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -33,4 +33,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index 6aa2c43..5a7fa80 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -14,4 +14,3 @@ CONFIG_SYS_PROMPT="Pb1x00 # "
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
index dbfaea1..6205aa3 100644
--- a/configs/pcm030_LOWBOOT_defconfig
+++ b/configs/pcm030_LOWBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index 6d25884..994a369 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="uboot> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 27f681f..7f29119 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -30,4 +30,3 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index b277b3a..eff099c 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -30,4 +30,3 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index db8ebdd..5d30f30 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="pcm052"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index c352195..f3de685 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_PDM360NG=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 9547d48..d5e9408 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -6,6 +6,7 @@ CONFIG_MACH_PIC32=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="dask # "
 # CONFIG_CMD_IMLS is not set
@@ -42,6 +43,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_PIC32=y
 CONFIG_USB_STORAGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 723466f..f7069e9 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PICOSAM9G45=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0bf79bf..2d9c4a6 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
 CONFIG_DRAM_CLK=672
@@ -9,4 +10,3 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index ed519a0..6b60335 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -29,4 +29,3 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index cb10fa3..2062dcd 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9261=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="pm9261> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index 37629ba..e6ebd9b 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9263=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="u-boot-pm9263> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 0949e1f..aea412c 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9G45=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 2b3b4c8..bd4db71 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_POGO_E02=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="PogoE02> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 2f819f5..a587ed5 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_PORTER=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 9aa5280..23bd9a9 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 8655665..6f70d68 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_PXM2=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
index 0826a0c..b013a17 100644
--- a/configs/qemu_mips64_defconfig
+++ b/configs/qemu_mips64_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_CPU_MIPS64_R1=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mips64 # "
 # CONFIG_CMD_LOADB is not set
@@ -11,4 +12,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
index f70ebc3..bffa1a3 100644
--- a/configs/qemu_mips64el_defconfig
+++ b/configs/qemu_mips64el_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R1=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mips64el # "
 # CONFIG_CMD_LOADB is not set
@@ -12,4 +13,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
index bb09796..9cab7dd 100644
--- a/configs/qemu_mips_defconfig
+++ b/configs/qemu_mips_defconfig
@@ -1,5 +1,6 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mips # "
 # CONFIG_CMD_LOADB is not set
@@ -9,4 +10,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
index 19e6c7d..b9226a8 100644
--- a/configs/qemu_mipsel_defconfig
+++ b/configs/qemu_mipsel_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mipsel # "
 # CONFIG_CMD_LOADB is not set
@@ -10,4 +11,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig
index 5214923..5f77e05 100644
--- a/configs/r0p7734_defconfig
+++ b/configs/r0p7734_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_R0P7734=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig
index ad6f2f0..fbf2dd5 100644
--- a/configs/r7780mp_defconfig
+++ b/configs/r7780mp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_R7780MP=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index 27998f3..093207c 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 6ebdb38..a7879ae 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index ec89f05..7de5a19 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RASTABAN=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index 89c129f..1cf4832 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_REDWOOD=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 3e16b80..516bee7 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -63,7 +63,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig
index 272bd86..9cc5a20 100644
--- a/configs/rsk7264_defconfig
+++ b/configs/rsk7264_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SH=y
 CONFIG_TARGET_RSK7264=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rsk7269_defconfig b/configs/rsk7269_defconfig
index 41e70a5..58a5644 100644
--- a/configs/rsk7269_defconfig
+++ b/configs/rsk7269_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SH=y
 CONFIG_TARGET_RSK7269=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 406eaf3..14a158f 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_RUT=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig
index 7425184..fce501b 100644
--- a/configs/sama5d2_ptc_nandflash_defconfig
+++ b/configs/sama5d2_ptc_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_PTC=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig
index 27fc394..c090264 100644
--- a/configs/sama5d2_ptc_spiflash_defconfig
+++ b/configs/sama5d2_ptc_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_PTC=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 1880256..9ca2a9c 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -21,4 +23,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index de8f4d9..617d73a 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -21,4 +23,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 1dabc5f..db6592a 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -19,4 +21,3 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 458a486..d70c3b7 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -19,4 +21,3 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 488d950..5738d2a 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -21,4 +23,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 12f28f2..93aef74 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -21,4 +23,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 42fcc1e..a938fe7 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -21,4 +23,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 3110269..74e2087 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -22,4 +24,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 3ea4bd7..3af7ed4 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -22,4 +24,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index dbec4ad..0e037c3 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -22,4 +24,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index f2a5844..9811326 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -22,4 +24,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 58186ce..37b080a 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -22,4 +24,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index ab23e95..ba939b1 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
@@ -22,4 +24,3 @@ CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_OF_LIBFDT=y
-CONFIG_FIT=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 4eb3c22..71f7130 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BLK=y
 CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
@@ -70,7 +71,6 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
-CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -89,6 +89,9 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
+CONFIG_MISC=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_I2C=y
@@ -170,6 +173,3 @@ CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
-CONFIG_MISC=y
-CONFIG_DM_MAILBOX=y
-CONFIG_SANDBOX_MBOX=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 9dd60b7..16f61de 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SANSA_FUZE_PLUS=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 60bb817..7231b60 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 6c0fd99..bf125a5 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index e22c70a..daa2313 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index 6d5b3f6..c5fc4a0 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 8ecb126..1fd17ca 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index bbea0cb..5396e5a 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index f146b2d..ffde056 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index 3dea198..a8a8a93 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index ad38457..a382794 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_SBC8641D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 4b73506..a3bf903 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SC_SPS_1=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 3f8648d..9ffefbd 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -34,4 +34,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index 66d6a1a..8619c57 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index 5c548ff..81cda46 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index 07594d1..f7e055b 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SH=y
 CONFIG_SH_32BIT=y
 CONFIG_TARGET_SH7752EVB=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index 5e7a9c9..fc6c7b1 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_SH7753EVB=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index fafba4c..b0d3f28 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SH=y
 CONFIG_SH_32BIT=y
 CONFIG_TARGET_SH7757LCR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig
index cc31e1c..d98e073 100644
--- a/configs/sh7785lcr_32bit_defconfig
+++ b/configs/sh7785lcr_32bit_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SH=y
 CONFIG_SH_32BIT=y
 CONFIG_TARGET_SH7785LCR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig
index d7724b3..368cb30 100644
--- a/configs/sh7785lcr_defconfig
+++ b/configs/sh7785lcr_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_SH7785LCR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 71ce49c..5cd37a4 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_SHEEVAPLUG=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 0beef09..f5d7afd 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_SILK=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 2ec6e48..1c29a29 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SMARTWEB=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
index 702b36c..4d40a29 100644
--- a/configs/smdk2410_defconfig
+++ b/configs/smdk2410_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SMDK2410=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK2410 # "
 CONFIG_CMD_USB=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index a989e24..0948534 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_TARGET_SMDKC100=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDKC100 # "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 5ba6523..5e3844c 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS4=y
-CONFIG_TARGET_SMDKV310=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 2f8dd50..166fd2f 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Snapper> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index f725693..3cfe694 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index ec40ec7..2478ae5 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 8e5c527..1619b86 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 034a215..43d939b 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -49,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 133a6eb..c5c662b 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -49,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="denx"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 8b1bcfc..1c4a40d 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 56284a1..e34d13e 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="ebv"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index d66f7c6..d1cfbcd 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SR1500=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -44,3 +44,4 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 6ce4def..80552a5 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
@@ -11,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -55,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="samtec"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 86dfd0e..ae9976b 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F4=y
 CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 0048226..e3e6333 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index a8f59ca..9073c17 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_STOUT=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 985aab8..6253615 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index b7a16b7..3d325f4 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 2766104..160df24 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index db75c0d..2a2733d 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 6a3b5b8..40ca293 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_STV0991=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stv0991"
 CONFIG_SYS_EXTRA_OPTIONS="stv0991"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="STV0991> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 6d39dec..5861cff 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index 9fdb2b3..5f7b40d 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index c5562c9..7505996 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_T3CORP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index 6d0877d..4ee5737 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_TAO3530=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="TAO-3530 # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 20f33a8..e566f7f 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TAURUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig
index 83b1b56..2d157b2 100644
--- a/configs/tb100_defconfig
+++ b/configs/tb100_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=500000000
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="[tb100]:~# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index b710229..7dbb4cd 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -35,4 +35,3 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 2055101..742d90d 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -34,4 +34,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 8358757..05368bd 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index 157985f..17bf8cd 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index f9391f2..0b69c07 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_THUBAN=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index cb33f60..4a8655f 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_THUNDERX_88XX=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
 CONFIG_SYS_EXTRA_OPTIONS="ARM64"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ThunderX_88XX> "
 # CONFIG_CMD_IMLS is not set
@@ -22,4 +23,3 @@ CONFIG_DEBUG_UART_BASE=0x87e024000000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_REGEX=y
-CONFIG_BOOTP_VCI_STRING="Diagnostics"
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 4eb7923..c4240e9 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TI816X_EVM=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot/ti816x# "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index 3eec4c2..a69c0b6 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -1,35 +1,24 @@
 CONFIG_MIPS=y
-CONFIG_ARCH_ATH79=y
-CONFIG_BOARD_TPLINK_WDR4300=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_NS16550=y
 CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
 CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_NET=y
-CONFIG_CMD_NFS=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_ETH=y
-CONFIG_AG7XXX=y
 CONFIG_CLK=y
-CONFIG_CMD_USB=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_ATH79_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
@@ -41,4 +30,13 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_DATAFLASH=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
 CONFIG_PINCTRL=y
+CONFIG_SYS_NS16550=y
+CONFIG_ATH79_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 67857a5..72e641d 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -36,4 +36,3 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SFLASH=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index ffbc025..0e57f7c 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TWISTER=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="twister => "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index ffcac79..e7f9b15 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD11=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index cbc65dd..d073e3d 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD20=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 22615a6..04d651d 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index 18f4caf..d5fc138 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index cf6d3e4..285ea98 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 0965019..13f3147 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_UNIPHIER_SLD3=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index fa5561a..916a9c6 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_USB_A9263=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
index 4dd2612..a54999c 100644
--- a/configs/v38b_defconfig
+++ b/configs/v38b_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_V38B=y
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index ed27d85..c65a200 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -10,4 +11,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index 82708f0..23bfe4a 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_VCT_ONENAND=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -13,4 +14,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig
index 7b379be..3306a45 100644
--- a/configs/vct_platinum_onenand_small_defconfig
+++ b/configs/vct_platinum_onenand_small_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_VCT_ONENAND=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig
index 78d215d..0647613 100644
--- a/configs/vct_platinum_small_defconfig
+++ b/configs/vct_platinum_small_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig
index c47f102..1660c66 100644
--- a/configs/vct_platinumavc_defconfig
+++ b/configs/vct_platinumavc_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="VCT# "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
@@ -8,4 +9,3 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig
index e7aef31..55dfd4c 100644
--- a/configs/vct_platinumavc_onenand_defconfig
+++ b/configs/vct_platinumavc_onenand_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_VCT_ONENAND=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,4 +12,3 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig
index be70588..98b5ea2 100644
--- a/configs/vct_platinumavc_onenand_small_defconfig
+++ b/configs/vct_platinumavc_onenand_small_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_VCT_ONENAND=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig
index b7e0a78..f4a9549 100644
--- a/configs/vct_platinumavc_small_defconfig
+++ b/configs/vct_platinumavc_small_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 29d16e3..f85deb3 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -10,4 +11,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index 31b89e3..11879e5 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_VCT_ONENAND=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -13,4 +14,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig
index a3a93b8..ff5e7a6 100644
--- a/configs/vct_premium_onenand_small_defconfig
+++ b/configs/vct_premium_onenand_small_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_VCT_ONENAND=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig
index fddc04d..c601676 100644
--- a/configs/vct_premium_small_defconfig
+++ b/configs/vct_premium_small_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 4ae3550..faeb15c 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_VE8313=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 17a6000..edbb18f 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -42,4 +42,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 97b13a1..aeb9025 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -33,4 +33,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index c0708b2..989f068 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -24,4 +24,3 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 5af9f58..c70851f 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -24,4 +24,3 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index 379dff2..b0a2f67 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -24,4 +24,3 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.armv8.vexpress_aemv8a"
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index c39faaa..2f141dd 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -24,4 +24,3 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2"
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index e71d45e..c495ee5 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -24,4 +24,3 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2"
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 20100a3..fcd6e26 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -24,4 +24,3 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
-CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4"
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index c014294..63a6ab9 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index d50ad90..f66ff4a 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index e79cc4d..0a373a3 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_VINCO=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="vinco => "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 887afdf..b23f235 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index 9fdb2b3..5f7b40d 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index ca753a4..754e5cb 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -29,4 +29,3 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index b4660cd..a2e5957 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
 CONFIG_CMD_MMC=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index bb1ef0a..3b38130 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN_SD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
 CONFIG_CMD_MMC=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 5663b2f..e9fa773 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_DM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 9341087..336d8e4 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -3,6 +3,7 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index 14977dc..b91a711 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_X600=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="X600> "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 59e1014..31a647e 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_XFI3=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index 6c021d7..8e07d40 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="xlx-ppc405:/# "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index ab0ea5a..7f085de 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="board:/# "
 CONFIG_CMD_ASKENV=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index fa380ef..7325f19 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 35226d6..91af8ce 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index cc13179..3e73312 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 6570348..2805219 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index e1fc8b0..32bea4b 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 2829029..d7eb8c2 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 92633d6..80a59ef 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index 4c0e58e..f023c73 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_XPEDITE1000=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index b0e92e0..2839bc6 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index 4a328cd..c3b91f4 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index e0fe947..5ababef 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index e16c8c8..f893abf 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 00992e0..059ff71 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index 3a803f6..df37b90 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index e219fd2..d3ccad7 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_YUCCA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index 9368610..42e38da 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ZMX25=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="zmx25> "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index d0b1ec9..d88c61b 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 3624424..aeb1270 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_picozed"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index e1b1fc9..d68ed0e 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 63d32d9..8bd9230 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 6ccbb8c..81f16ec 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index e6c646b..271fcfd 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index a8cfeb8..a9ea971 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index f2d00ca..56062b1 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7783eeb..c70b860 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 9236c5e..624545e 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index dfc2cbc..9244680 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -27,7 +27,6 @@
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_BOOTDELAY     2
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_MENU
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 5249751..2c3c4ac 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -802,7 +802,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index b092933..0a9d8a6 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -394,7 +394,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10 /* -1 disable auto-boot */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"netdev=eth0\0"						\
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index aaddfca..756beec 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -632,7 +632,6 @@ combinations. this should be removed later
 #define CONFIG_UBOOTPATH	"u-boot.bin"
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10 /* -1 disable auto-boot */
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_DEF_HWCONFIG	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1e5b501..69a9798 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -517,7 +517,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index b60da5e..c5c3a84 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -27,7 +27,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
 #undef	CONFIG_BOOTCOMMAND
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index b66b3ff..db953b9 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
 #undef	CONFIG_BOOTCOMMAND
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 2b2e4e7..b426c18 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -59,7 +59,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 85b1c15..1e052b1 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -82,7 +82,6 @@
 	""
 #endif
 
-#define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
 /* LCD */
 #ifdef CONFIG_CMD_BMP
 #define CONFIG_LCD
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index bacd8e0..0062228 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -76,7 +76,6 @@
 #define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_BOOTFILE		"u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_IPADDR	192.162.1.2
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 7c06fce..6c90700 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -17,7 +17,6 @@
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
-#define CONFIG_BOOTDELAY	5
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index d14f979..faad970 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -18,7 +18,6 @@
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
-#define CONFIG_BOOTDELAY	5
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 0753dc3..a858904 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -57,7 +57,6 @@
  * Command line configuration.
  */
 
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_MII		1
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 1709ccc..1bdacbc 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -104,7 +104,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x800000
 
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTCOMMAND	"bootm ffe40000"
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 8131ea0..62f25e9 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -70,7 +70,6 @@
 #	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
-#define CONFIG_BOOTDELAY	5
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_IPADDR	192.162.1.2
 #	define CONFIG_NETMASK	255.255.255.0
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 81e28f0..03c18da 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -79,7 +79,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 661063c..fabbaf0 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -73,7 +73,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index f0cf715..8fb16bc 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -73,7 +73,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index e10c3e1..63b0a1e 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -75,7 +75,6 @@
 #define CONFIG_SYS_FEC0_PHYADDR	0
 #define CONFIG_SYS_FEC1_PHYADDR	1
 
-#define CONFIG_BOOTDELAY		2	/* autoboot after 5 seconds */
 
 #ifdef	CONFIG_SYS_NAND_BOOT
 #define CONFIG_BOOTARGS	"root=/dev/mtdblock2 rw rootfstype=jffs2 " \
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 00bdbd1..599ffc7 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -56,7 +56,6 @@
 #	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP 50000
 
-#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
 #	define CONFIG_ETHPRIME		"FEC0"
 #	define CONFIG_IPADDR		192.162.1.2
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index f32dd36..8301c46 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -61,7 +61,6 @@
 #	define MCFFEC_TOUT_LOOP 50000
 #	define CONFIG_HAS_ETH1
 
-#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
 #	define CONFIG_ETHPRIME		"FEC0"
 #	define CONFIG_IPADDR		192.162.1.2
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 5fa9683..ccebc30 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -116,7 +116,6 @@
 #define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 9a23e22..7e9f978 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -111,7 +111,6 @@
 #define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #define CONFIG_HOSTNAME		M548xEVB
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 75a26ed..79027e2 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -97,7 +97,6 @@
  * Environment definitions
  **************************************************************/
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
-#define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index e3e3b44..578325c 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -514,7 +514,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index fda894e..5613a4a 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -649,7 +649,6 @@
 
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 41b40cb..7ce5f59 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -602,7 +602,6 @@
 
 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 5c40e5b..13f954d 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -492,7 +492,6 @@
 
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 4a1cebb..fd48260 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -569,7 +569,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 3518b3f..288b126 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -734,7 +734,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	 115200
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 8161903..2721255 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -731,7 +731,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
 #endif
 
-#define CONFIG_BOOTDELAY	6
 
 #define CONFIG_BOOTARGS \
 	"root=/dev/nfs rw" \
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 28ed9c0..921d5f3 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -659,7 +659,6 @@ extern int board_pci_host_broken(void);
 
 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index fa131e2..bb06e89 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -679,7 +679,6 @@
 
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 03f17f9..7c19ff8 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -706,7 +706,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 38bd38c..fae4b0c 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -392,7 +392,6 @@
 
 #define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index d827d2a..0c2afb5 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -414,7 +414,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index f3036c1..b9d97c1 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -441,7 +441,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 5de8b19..e73be48 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -540,7 +540,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index c68e1d8..fcd55c7 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -409,7 +409,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index fb76dd1..4ed06c9 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -434,7 +434,6 @@
 
 #define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 09e32eb..39459de 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -433,7 +433,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 923159b..192cc2c 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -528,7 +528,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index bb7f38e..2e6989f 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -646,7 +646,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f6d45a9..8159493 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -500,7 +500,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 9b2623c..f90f7f2 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -666,7 +666,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index f4c9312..80d8fcd 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -16,7 +16,6 @@
 #define CONFIG_CMD_SDRAM
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 4d08555..5384584 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -850,7 +850,6 @@ extern unsigned long get_sdram_size(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 7457dfc..bdf0323 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -715,7 +715,6 @@
 
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index a10310e..07a594d 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -308,7 +308,6 @@ extern unsigned long get_clock_freq(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY -1	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b3fb38c..24e5431 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -676,7 +676,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 9f3c037..e96fbc5 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -44,11 +44,6 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
 
-#if 0
-#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
-#else
-#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
-#endif
 #define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/
 
 #define CONFIG_BOOTARGS		""		/* */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 4506d86..e7c7a99 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -89,7 +89,6 @@
  **************************************************************/
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
 
-#define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 71a0375..558f3e2 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -118,7 +118,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index a622578..5f17d76 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -21,7 +21,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef  CONFIG_BOOTARGS
 #undef  CONFIG_BOOTCOMMAND
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 005fa2a..868ca84 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -229,7 +229,6 @@
 		"cp.b 200000 fff90000 70000\0"				\
 	""
 
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds     */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index ef2ede4..b151963 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -867,7 +867,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 #define __USB_PHY_TYPE		utmi
 
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 778c64b..06d1d0f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -867,7 +867,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 #define __USB_PHY_TYPE		utmi
 
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index be4ae71..9f5063c 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -749,7 +749,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ed3493b..a8f4f74 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -832,7 +832,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/*-1 disables auto-boot*/
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index f48697c..1f07a83 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -821,7 +821,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define __USB_PHY_TYPE		utmi
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index b6be46e..0ded41e 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -773,7 +773,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define __USB_PHY_TYPE		utmi
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 276428f..f075dfb 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -545,7 +545,6 @@ unsigned long get_board_ddr_clk(void);
 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define __USB_PHY_TYPE	utmi
 
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index ab838a8..9ba69a1 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -738,7 +738,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SHA_HW_ACCEL
 #endif
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define __USB_PHY_TYPE	utmi
 
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 42ebcf0..0e4067a 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -199,7 +199,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 395805c..c557ba1 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -37,7 +37,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index ec36637..814740b 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -35,7 +35,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 2aac682..90e8dd9 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -481,7 +481,6 @@
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		400000
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 00c0cc3..58fd8a4 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index ca26024..3a4f94c 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 39cf02e..134076c 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 30bfb8a..ad6f8f4 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index abe49b9..b935f31 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 48252c4..79248de 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index a73395a..d360644 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -33,7 +33,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 3db6fa1..5c6013b 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -33,7 +33,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 76c8f7a..c098f72 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -44,7 +44,6 @@
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 88b97ab..9d8a607 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -40,7 +40,6 @@
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 4ae61ca..0c9e79f 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -590,7 +590,6 @@
 
 #if defined(CONFIG_DONGLE)
 
-#define CONFIG_BOOTDELAY 1	/* autoboot after 1 seconds */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 "bootcmd=run prog_spi_mbrbootcramfs\0"					\
 "bootfile=uImage\0"							\
@@ -720,7 +719,6 @@
 
 #if defined(CONFIG_UCP1020T1)
 
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0"	\
 "bootfile=uImage\0"							\
@@ -810,7 +808,6 @@
 
 #else /* For Arcturus Modules */
 
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 "bootcmd=run norkernel\0"						\
 "bootfile=uImage\0"							\
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 4e349d5..968e1df 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -115,7 +115,6 @@
 
 #define CONFIG_BAUDRATE			9600
 
-#define CONFIG_BOOTDELAY		5
 #define CONFIG_BOOT_RETRY_TIME		-1
 #define CONFIG_RESET_TO_RETRY
 #define CONFIG_ZERO_BOOTDELAY_CHECK
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index d401d3e..dde98f6 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -27,7 +27,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
 #undef  CONFIG_BOOTCOMMAND
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index e0c92d0..7ec404d 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -321,7 +321,6 @@
  * Environment Configuration
  */
 
-#define CONFIG_BOOTDELAY	3	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index ee1bff8..4e240c6 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -107,7 +107,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
 
 #define CONFIG_SYS_AUTOLOAD	"n"
 
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index f0b5b3e..699ac41 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -462,7 +462,6 @@
 /* default load addr for tftp and bootm */
 #define CONFIG_LOADADDR		400000
 
-#define CONFIG_BOOTDELAY	2	/* -1 disables auto-boot */
 
 /* the builtin environment and standard greeting */
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 7b9470c..c4e0a21 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -97,7 +97,6 @@
  */
 #define CONFIG_FTMAC100
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * SD (MMC) controller
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index e9e971e..8454872 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -10,7 +10,6 @@
 #define __CONFIG_AM335X_EVM_H
 
 #include <configs/ti_am335x_common.h>
-#undef CONFIG_BOOTDELAY
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_TIMESTAMP
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 822e1c8..a65d1a8 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -156,7 +156,6 @@
 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY	10
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 6f83870..4d88aac 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -200,7 +200,6 @@
 #endif /* CONFIG_NAND */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY	10
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 9fa4d16..2666ca6 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -60,7 +60,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index e819185..5667680 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -18,7 +18,6 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_BOOTCOMMAND		"bootm ffc20000"
 
 #undef CONFIG_CMD_AES
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index b01031c..bf5746f 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -34,7 +34,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_BOOTDELAY                3
 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
 					"root=/dev/mtdblock2 " \
 					"rootfstype=squashfs"
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 0fa73a7..5d7e49e 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -38,7 +38,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_BOOTDELAY                3
 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
 					"root=/dev/mtdblock2 " \
 					"rootfstype=squashfs"
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index ae58ec8..7dd2461 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -19,7 +19,6 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_BAUDRATE		38400
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,38400"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index be8feed..37f2d30 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -22,7 +22,6 @@
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC4,115200"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 2291647..f44f71c 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -148,7 +148,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
 #define CONFIG_INITRD_TAG		/* send initrd params	*/
 
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
 #define CONFIG_BOOTARGS		"console=" __stringify(ACFG_CONSOLE_DEV) "," \
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index bb29f3f..50eaf60 100644
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -93,7 +93,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTCOMMAND		"run bootcmd_nand"
 #define CONFIG_LOADADDR			0x41000000
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 8a860ee..d608104 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -54,7 +54,6 @@
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyARC0,115200n8"
 #define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/aria.h b/include/configs/aria.h
index 2d32da1..cb50658 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -510,7 +510,6 @@
 
 #define CONFIG_LOADADDR			400000	/* default load addr */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 681b4e7..522b287 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -22,7 +22,6 @@
 #define BOARD_LATE_INIT
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		""
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index b08276f..e8dca0b 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -149,19 +149,6 @@
 /* AUTOBOOT settings - booting images automatically by u-boot after power on */
 
 /*
- * used for autoboot, delay in seconds u-boot will wait before starting
- * defined (auto-)boot command, setting to -1 disables delay, setting to
- * 0 will too prevent access to u-boot command interface: u-boot then has
- * to be reflashed
- * beware - watchdog is not serviced during autoboot delay time!
- */
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_BOOTDELAY	1
-#else
-#define CONFIG_BOOTDELAY	1
-#endif
-
-/*
  * The following settings will be contained in the environment block ; if you
  * want to use a neutral environment all those settings can be manually set in
  * u-boot: 'set' command
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index dc955b2..9257c5f 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -34,7 +34,6 @@
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
 
-#define CONFIG_BOOTDELAY		3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 2979b25..c92ad85 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -171,7 +171,6 @@
 /*
  * Boot option
  */
-#define CONFIG_BOOTDELAY		3
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 9db8d12..c6d3295 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -61,7 +61,6 @@
 #define	CONFIG_RED_LED		AT91_PIN_PA9	/* this is the power led */
 #define	CONFIG_GREEN_LED	AT91_PIN_PA6	/* this is the user led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index b369624..9c9461b 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -69,7 +69,6 @@
 #define	CONFIG_GREEN_LED	AT91_PIN_PA13	/* this is the user1 led */
 #define	CONFIG_YELLOW_LED	AT91_PIN_PA14	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index f248049..e7bfd49 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -76,7 +76,6 @@
 #define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* the user1 led */
 #define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 18eb01d..290b039 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -59,7 +59,6 @@
 #define	CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
 #define	CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 2f8c377..297938b 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -51,7 +51,6 @@
 #define CONFIG_ATMEL_LCD_RGB565
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_BOOTDELAY		3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index d178d9d..a383de6 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -65,7 +65,6 @@
 #define	CONFIG_GREEN_LED	AT91_PIN_PD15	/* this is the user1 led */
 #define	CONFIG_YELLOW_LED	AT91_PIN_PD16	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * Command line configuration.
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 251094e..743fc39 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -47,7 +47,6 @@
 #define CONFIG_ATMEL_LCD_RGB565
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index e6f6125..a0f451b 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -62,7 +62,6 @@
 #define CONFIG_BOOTCOMMAND						\
 	"fsload; bootm"
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index dfa2d93..4d9282a 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -81,7 +81,6 @@
 #define CONFIG_BOOTCOMMAND						\
 	"fsload 0x10400000 /uImage; bootm"
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 9a647d8..9ddfff2 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -79,7 +79,6 @@
 #define CONFIG_BOOTCOMMAND						\
 	"fsload; bootm $(fileaddr)"
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 05d2d45..c0b68e2 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -119,7 +119,6 @@
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
 #define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index e95deac..de60bb1 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -117,7 +117,6 @@
 /*
  * Misc Settings
  */
-#define CONFIG_BOOTDELAY	1
 #define CONFIG_LOADADDR		0x800000
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h
index 66339ca..f7a45e9 100644
--- a/include/configs/bf525-ucr2.h
+++ b/include/configs/bf525-ucr2.h
@@ -85,7 +85,6 @@
 #define CONFIG_BFIN_SERIAL
 #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw"
 #define CONFIG_BOOTCOMMAND	"run sfboot"
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"sfboot=sf probe 1;" \
 		"sf read 0x1000000 0x20000 0x300000;" \
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 43a9032..2c79720 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -129,12 +129,6 @@
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_LOADS_ECHO		1
 
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY	-1
-#else
-# define CONFIG_BOOTDELAY	5
-#endif
-
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 7055366..6ad5682 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -129,15 +129,6 @@
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_LOADS_ECHO		1
 
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY	-1
-#else
-# define CONFIG_BOOTDELAY	5
-#endif
-
-#ifdef CONFIG_BFIN_MAC
-#endif
-
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 88d2ae9..1307607 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -99,9 +99,7 @@
  */
 #ifndef CONFIG_BOOTDELAY
 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-#  define CONFIG_BOOTDELAY	-1
 # else
-#  define CONFIG_BOOTDELAY	5
 # endif
 #endif
 #ifndef CONFIG_BOOTCOMMAND
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index 6a5bc12..e13f736 100644
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -55,7 +55,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
 #define CONFIG_BOOTCOMMAND	"bootm"
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 6eb83a0..dc596fa 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -106,7 +106,6 @@
 #define CONFIG_CMD_CPLBINFO
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY     5
 #define CONFIG_BOOTCOMMAND   "run ramboot"
 #define CONFIG_BOOTARGS \
 	"root=/dev/mtdblock0 rw " \
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
index ba90830..d3dc216 100644
--- a/include/configs/blackvme.h
+++ b/include/configs/blackvme.h
@@ -155,7 +155,6 @@
  * Default: boot from SPI flash.
  * "sfboot" is a composite command defined in extra settings
  */
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTCOMMAND	"run sfboot"
 
 /*
diff --git a/include/configs/br4.h b/include/configs/br4.h
index 402f352..16e4a1d 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -119,7 +119,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
 
 /*
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 506ad88..3b10360 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -214,7 +214,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS           ""
 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
-#define CONFIG_BOOTDELAY          0
 #define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 #define CONFIG_RESET_TO_RETRY
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 31fe5f6..b416660 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -65,7 +65,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 99182f4..0dd5e99 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -64,7 +64,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
 	"echo"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 0fb8530..de1999d 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -145,7 +145,6 @@
 							/* devices */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 7c087c6..87e41bf 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -152,7 +152,6 @@
 							/* devices */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index ff63d7a..68851ee 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -108,9 +108,7 @@
 #undef CONFIG_SYS_AUTOLOAD
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_BOOTCOMMAND
-#undef CONFIG_BOOTDELAY
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_SYS_AUTOLOAD		"no"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 509c8b42..4396698 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -149,7 +149,6 @@
 
 /*AUTOBOOT settings - booting images automatically by u-boot after power on*/
 
-#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
 seconds u-boot will wait before starting defined (auto-)boot command, setting
 to -1 disables delay, setting to 0 will too prevent access to u-boot command
 interface: u-boot then has to reflashed */
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 5dffc9e..ba8d93c 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -37,7 +37,6 @@
 	"bootm 0xc0000;"
 #define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
 #define	CONFIG_TIMESTAMP
-#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_LZMA			/* LZMA compression support */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 50f7c21..5892595 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -89,7 +89,6 @@
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_SERVERIP		192.168.10.1
 
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_BOARD_LATE_INIT
 
 #define CONFIG_LOADADDR			0x80008000
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index c60c644..30c2831 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -417,7 +417,6 @@
 
 #ifdef CONFIG_TRAILBLAZER
 
-#define CONFIG_BOOTDELAY	0	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
@@ -432,7 +431,6 @@
 
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index a06bfe0..4a770b0 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -682,7 +682,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 8b3c715..686760d 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -54,7 +54,6 @@
 #define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
 #define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 660646e..708d5f7 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -505,7 +505,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index af220fe..3e4bba5 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -278,7 +278,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		\
 	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_EXTRA_ENV_SETTINGS	"hwconfig=dsp:wake=yes"
 
 /*
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 68ff025..dbd2bb3 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -37,7 +37,6 @@
 #endif
 #endif
 
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 913b948..73f53d4 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -179,7 +179,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY		1
 
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 18804d4..1145e37 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -117,7 +117,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	1
 
 #undef	CONFIG_BOOTARGS
 
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 8aee25b..5d866c4 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -82,7 +82,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 "if dfubutton; then " \
@@ -94,7 +93,6 @@
 "reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index d4f3cfa..3f8578f 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -137,7 +137,6 @@
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
 
 /*
  * U-Boot commands
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 521e3cf..6d469a3 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -69,7 +69,6 @@
 
 #define CONFIG_MCFTMR
 
-#define CONFIG_BOOTDELAY	5
 #define	CONFIG_SYS_LONGHELP	1
 
 #define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
index bb5d7e5..c7b0a38 100644
--- a/include/configs/eco5pk.h
+++ b/include/configs/eco5pk.h
@@ -31,7 +31,6 @@
 #define MACH_TYPE_ECO5_PK	4017
 #define CONFIG_MACH_TYPE	MACH_TYPE_ECO5_PK
 
-#define CONFIG_BOOTDELAY	10
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_AUTO_COMPLETE
 
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 2ac7757..706ad1d 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -37,7 +37,6 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 174cdf3..f3f7549 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -26,7 +26,6 @@
 #endif
 
 /* Initial environment and monitor configuration options. */
-#define CONFIG_BOOTDELAY		2
 #define CONFIG_CMDLINE_TAG		1
 #define CONFIG_INITRD_TAG		1
 #define CONFIG_SETUP_MEMORY_TAGS	1
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 99d16b0..f9d4683 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -115,7 +115,6 @@
 #define CONFIG_SYS_FLASH_BASE		0xfff80000
 
 /* auto boot */
-#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 3d67376..86e726c 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -20,7 +20,6 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
 
-#define CONFIG_BOOTDELAY        -1
 #define CONFIG_BOOTARGS         "console=ttySC0,115200 root=1f01"
 #define CONFIG_ENV_OVERWRITE    1
 
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 94fee54..bd32cdb 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -205,7 +205,6 @@
 #define CONFIG_RBTREE
 
 /* Boot command */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 7400870..824aca4 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -81,7 +81,6 @@
 
 #define CONFIG_NET_RETRY_COUNT	100
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 1304879..42771b5 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -36,7 +36,6 @@
 
 #define CONFIG_SUPPORT_EMMC_BOOT
 
-#define CONFIG_BOOTDELAY               1
 
 #include "mx6_common.h"
 #include <linux/sizes.h>
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index e6b7953..8b57354 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -65,7 +65,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 956c0e2..4e78199 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -67,7 +67,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 908d545..36acf01 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -46,7 +46,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 83f1d73..f1afded 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -74,7 +74,6 @@
 
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 6a88901..c2656fb 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -58,7 +58,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 0ebded6..59adbdc 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -53,7 +53,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 3d510d6..3e419c6 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -135,7 +135,6 @@
 #define CONFIG_USB_DEV_PULLUP_GPIO	33
 /* USB VBUS GPIO 3 */
 
-#define CONFIG_BOOTDELAY		2
 #define CONFIG_BOOTCOMMAND		\
 	"setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
 	"if bootp ; then setenv downloaded 1 ; fi ; done ; " \
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 9f02a65..6a8660b 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -621,7 +621,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define CONFIG_HOSTNAME		hrcon
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 04515ba..b750d72 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -25,7 +25,6 @@
 
 #define CONFIG_BOOT_RETRY_TIME		900
 #define CONFIG_BOOT_RETRY_MIN		30
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_RESET_TO_RETRY
 
 #define CONFIG_83XX_CLKIN		66000000	/* in Hz */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index b8ee44d..80628dd 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -175,7 +175,6 @@
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NAND
 
-#define CONFIG_BOOTDELAY	5
 
 #define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 94fc077..50dfc11 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -54,7 +54,6 @@
  ***********************************************************/
 #define CONFIG_CMD_EEPROM
 
-#define CONFIG_BOOTDELAY	3
 
 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
 					"1536k(kernel),-(root)"
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 0d4f292..3420a39 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -92,7 +92,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index a5a8819..e7d058f 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -31,7 +31,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 console=ttyAM0 console=tty"
 #define CONFIG_BOOTCOMMAND	""
 
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index af69ad9..d0b6af8 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -31,7 +31,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS	"root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
 #define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
 #define CONFIG_SERVERIP 192.168.1.100
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index b2a6e7f..b36b75d 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -223,7 +223,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
 		"root=/dev/mtdblock5 rw noinitrd " \
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index 55ed656..eb4e3ae 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -115,7 +115,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 0628203..65f53b7 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -92,7 +92,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 9f76034..6f2773b 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -21,7 +21,6 @@
 
 #undef	CONFIG_WATCHDOG		/* disable platform specific watchdog */
 
-#define CONFIG_BOOTDELAY	2 /* autoboot after 2 seconds */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 /*
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index bcb9e7e..2bddc6b 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -103,7 +103,6 @@ BUR_COMMON_ENV \
 
 #define CONFIG_BOOTCOMMAND \
 	"run usbscript;"
-#define CONFIG_BOOTDELAY		0
 
 /* undefine command which we not need here */
 #undef CONFIG_BOOTM_NETBSD
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 710629b..1b4c7d4 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -31,7 +31,6 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"root=/dev/null console=ttySC4,115200"
-#define CONFIG_BOOTDELAY 3
 
 #define CONFIG_VERSION_VARIABLE
 #undef  CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 1aad97d..f52750e 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -168,7 +168,6 @@
 #define CONFIG_SERIAL_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_SETUP_INITRD_TAG
-#define CONFIG_BOOTDELAY	0
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define CONFIG_BOOTCOMMAND \
 	"if mmc rescan; then " \
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index ccd94ec..fba2fac 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -125,7 +125,6 @@
 #define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
 					"$kernel_start $kernel_size && "\
 					"bootm $kernel_load"
-#define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 1edf798..db684d2 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -567,7 +567,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_FSL_DEVICE_DISABLE
 
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 30f5655..0fb28ef 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -416,7 +416,6 @@
 
 #define CONFIG_FSL_DEVICE_DISABLE
 
-#define CONFIG_BOOTDELAY		3
 
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS       \
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index a7d49ed..b0d4a8d 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -264,7 +264,6 @@
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
 #endif
-#define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c78aeb5..2bf524f 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -255,7 +255,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
 				" cp.b $kernel_start $kernel_load" \
 				" $kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index d5082fa..0abfb00 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -340,7 +340,6 @@
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 428128d..e7fd639 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -130,7 +130,6 @@
 #endif
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define CONFIG_BOOTCOMMAND	"run mmc_mmc"
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 4349357..781a162 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -226,7 +226,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttymxc1,115200"
 #define CONFIG_LOADADDR		0x70800000
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index fb14463..b4bd6b0 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -128,7 +128,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS3,115200"
 #define CONFIG_LOADADDR		0x20800000
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index 8d4a8cd..937febe 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -37,7 +37,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 3dbd920..0c6e111 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -149,7 +149,6 @@
 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 9262f72..4211e72 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -362,7 +362,6 @@
 
 #define CONFIG_LOADADDR		400000	/* def. location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
 
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index f71b662..fbcad4a 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -69,7 +69,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /*
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 801d674..93fb166 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -239,7 +239,6 @@
 /* default load address */
 #define	CONFIG_SYS_LOAD_ADDR	0
 
-#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
 #define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 62919e9..2a83c60 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -63,7 +63,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
 #undef CONFIG_BOOTARGS
 
 #define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index e0c9a98..3cdd0dc 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -516,7 +516,6 @@
 
 #define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 66e1a45..57cb795 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -474,7 +474,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index f983f2d..27e9c0a 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -16,7 +16,6 @@
 #define CONFIG_CMD_SDRAM
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 025a4a6..c0fb16d 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -23,7 +23,6 @@
 #define CONFIG_CONS_SCIF1	1
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	-1
 #define CONFIG_BOOTARGS		"console=ttySC0,38400"
 #define CONFIG_ENV_OVERWRITE	1
 
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index 3073db9..29564d7 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -22,7 +22,6 @@
 #define MACH_TYPE_AM3517_MT_VENTOUX	3832
 #define CONFIG_MACH_TYPE	MACH_TYPE_AM3517_MT_VENTOUX
 
-#define CONFIG_BOOTDELAY	10
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_AUTO_COMPLETE
 
diff --git a/include/configs/munices.h b/include/configs/munices.h
index efbd447..3e4c062 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-#define CONFIG_BOOTDELAY	5   /* autoboot after 5 seconds */
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 6d4bbd1..62f4937 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -57,7 +57,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
 					  115200,230400, 460800, 921600 }
 /* auto boot */
-#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
 #define CONFIG_PREBOOT
 
 /*
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index 1bdbe4b..7747258 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -57,7 +57,6 @@
 #endif
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_LOADADDR		0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 542f1f4..3f9bb0a 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -56,7 +56,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY	1
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_LOADADDR		0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index c63887b..ea0d605 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -117,7 +117,6 @@
 
 /* Ethernet Configs */
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index b3c03b3..068596f 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -137,7 +137,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY	1
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_LOADADDR		0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index b9992de..8de9dec 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -64,7 +64,6 @@
  ***********************************************************/
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 3f63007..a81dd78 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -84,7 +84,6 @@
 
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	1
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index aed0939..1d11787 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -91,7 +91,6 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 23b8b46..93ad048 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -120,7 +120,6 @@
 
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index e697261..0419050 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -70,7 +70,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ETHPRIME		"smc911x"
 
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index feb5580..5e1c597 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -77,7 +77,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 8743ddc..1b580f0 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -87,7 +87,6 @@
 /* Command definition */
 #define CONFIG_SUPPORT_RAW_INITRD
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 9c76678..632ebba 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -64,7 +64,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 17b6c48..27f38f4 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -60,7 +60,6 @@
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
 #ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY	3
 #endif
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 3c9a794..5e5656d 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_TEXT_BASE            0x87800000
 
 #ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY                3
 #endif
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 0fbbce6..cd154a4 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -379,7 +379,6 @@ int rx51_kp_getc(struct stdio_dev *sdev);
 	"run attachboot;" \
 	"echo"
 
-#define CONFIG_BOOTDELAY 30
 #define CONFIG_MENU
 #define CONFIG_MENU_SHOW
 
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 16fa046..8913784 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -90,7 +90,6 @@
 #error "CONFIG_SYS_TEXT_BASE value is invalid"
 #endif
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"run master"
 
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 3f777b6..96c3c4b 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -74,8 +74,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 /* override default CONFIG_BOOTDELAY */
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY	0
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"machid=ffffffff\0" \
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 9dbca1c..1726a3e 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -106,7 +106,6 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index a93a2fa..b7d8765 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -55,7 +55,6 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	0
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"verify=no\0"			\
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
index bb908fa..da5d325 100644
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -45,7 +45,6 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	0
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"verify=no\0"			\
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index f3287e3..1f36d36 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -204,7 +204,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
 #define CONFIG_BOOTCOMMAND	"if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
-#define CONFIG_BOOTDELAY	3
 
 /*
  * U-Boot commands
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 71b2fa9..4f22d12 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -944,7 +944,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR	1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 9b75afe..30bfbf4 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -468,7 +468,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR	1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index b907419..a649991 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -31,7 +31,6 @@
 #endif
 #endif
 
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 0007c50..80d5d6c 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -70,7 +70,6 @@ Serial console configuration
 /*-----------------------------------------------------------------------------
 Autobooting
 -----------------------------------------------------------------------------*/
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
 					/* even with bootdelay=0 */
 #undef	CONFIG_BOOTARGS
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 494524d..74e22db 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -113,7 +113,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_I2C_EEPROM_BUS 2
 
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_LOADADDR			0x82000000
 
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 3b6c7dc..6d03d69 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -448,7 +448,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		400000
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo PDM360NG SAMPLE;" \
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 319e3b5..49c98d8 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -125,7 +125,6 @@
  * Board boot configuration
  */
 #define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-#define CONFIG_BOOTDELAY	5
 
 #define MEM_LAYOUT_ENV_SETTINGS					\
 	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"	\
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 44ffd6d..7d7315e 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -61,7 +61,6 @@
 #define CONFIG_AT91_LED
 #define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 39af5c0..0abd84a 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -168,7 +168,6 @@
 #define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
 #define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 111e0f5..b8ce17e 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -182,7 +182,6 @@
 #define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
 #define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index facba38..0e944d8 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -57,7 +57,6 @@
 #define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
 #define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 9b394dd..6804acb 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -119,7 +119,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
 
 /*
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 7450a1a..794650a 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -92,7 +92,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 	"if dfubutton; then " \
@@ -118,7 +117,6 @@
 	"reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index f58fc4c..546c508 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -17,7 +17,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 2190d16..6cab719 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -17,7 +17,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 73b3771..0b86402 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -179,7 +179,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 
 #define CONFIG_BAUDRATE	115200
 
-#define CONFIG_BOOTDELAY        1
 #define CONFIG_BOOTCOMMAND		\
 	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
 
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index 437ea92..c5e5724 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -22,7 +22,6 @@
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC3,115200"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index bf81d2b..1fc919b 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -22,7 +22,6 @@
 #define CONFIG_CONS_SCIF1	1
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	-1
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 #define CONFIG_ENV_OVERWRITE	1
 
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 6097dc2..c15580c 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -28,7 +28,6 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_CONS_SCIF0	1
 
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 #define CONFIG_ENV_OVERWRITE	1
 
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index 47d2379..6c8681a 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -85,7 +85,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 "if dfubutton; then " \
@@ -97,7 +96,6 @@
 "reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 337ba02..80313fc 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -31,7 +31,6 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_BAUDRATE		38400
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		""
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
index 622b7c7..72fbf10 100644
--- a/include/configs/redwood.h
+++ b/include/configs/redwood.h
@@ -132,7 +132,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define	CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 9ef5eae..dbbb81e 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -214,6 +214,5 @@
 	ENV_MEM_LAYOUT_SETTINGS \
 	BOOTENV
 
-#define CONFIG_BOOTDELAY 2
 
 #endif
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index c60e233..3f9fb7b 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -17,7 +17,6 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"console=ttySC3,115200"
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 #define CONFIG_SYS_LONGHELP	1	/* undef to save memory	*/
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
index b4fbc9c..b7f361b 100644
--- a/include/configs/rsk7269.h
+++ b/include/configs/rsk7269.h
@@ -16,7 +16,6 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"console=ttySC7,115200"
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
diff --git a/include/configs/rut.h b/include/configs/rut.h
index bf2cc2f..b0dcbd8 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -85,7 +85,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 	"if mmc rescan; then " \
@@ -107,7 +106,6 @@
 	"reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index 0c8ecc1..d58b963 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -28,7 +28,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define CONFIG_LOADADDR		0x42000000
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 6c0932a..567c4d5 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -641,7 +641,6 @@
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	 115200
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index bbd1a63..46766a6 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -579,7 +579,6 @@
 
 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index c9970f1..248785d 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -527,7 +527,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 42237d3..b490b62 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -52,7 +52,6 @@
 #endif
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
 #define CONFIG_BOOTCOMMAND	"bootm"
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index 80997a4..fb6e05f 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -24,7 +24,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 248435b..64e9e52 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -24,7 +24,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 547b500..f9a9a03 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -24,7 +24,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 9f1e6d7..538ba98 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -20,7 +20,6 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_JFFS2
 
-#define CONFIG_BOOTDELAY        -1
 #define CONFIG_BOOTARGS         "console=ttySC2,115200 root=1f01"
 #define CONFIG_ENV_OVERWRITE    1
 
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index bd4c6bd..794c48c 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -22,7 +22,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC1,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 40b0cd2..fc4153a 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -178,7 +178,6 @@
 #endif
 
 /* General Boot Parameter */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTCOMMAND		"run flashboot"
 #define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index c5c0c2c..f733c35 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -80,7 +80,6 @@
 #define CONFIG_CMDLINE_EDITING
 
 /* autoboot */
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_RESET_TO_RETRY
 #define CONFIG_ZERO_BOOTDELAY_CHECK
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 0f1a1ec..fe41d17 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -71,7 +71,6 @@
 #define CONFIG_CMD_ONENAND
 #define CONFIG_CMD_MTDPARTS
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 16aefc2..7981a8d 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -117,7 +117,6 @@
 
 /* Boot options */
 #define CONFIG_SYS_LOAD_ADDR		0x23000000
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index ca7f8a2..3b0b416 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index a2da7d4..7ced6a6 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index fdddfa3..6b9546e 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index f0fb43a..d1b31c4 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on MCV */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_PREBOOT		"run try_bootscript"
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 675f5d1..3fceb31 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index 79c16ce..c9473df 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCrates */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index c097f47..286e746 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -20,7 +20,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
index 1ccde1a..1c7d45e 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -21,7 +21,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on VINING_FPGA */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTFILE		"openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run selboot"
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 4ed524b..624cef7 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -346,7 +346,6 @@
 
 #define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
 
-#define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Welcome on the ABB Socrates Board;" \
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 7b2d262..43ba84a 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -104,12 +104,6 @@
 /*
  * Default Environment Varible definitions
  */
-#if defined(CONFIG_SPEAR_USBTTY)
-#define CONFIG_BOOTDELAY			-1
-#else
-#define CONFIG_BOOTDELAY			1
-#endif
-
 #define CONFIG_ENV_OVERWRITE
 
 /*
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index d53f8c1..8bbe580 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -82,7 +82,6 @@
 	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
 	"bootm 0x08044000 - 0x08042000\0"
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_AUTOBOOT
 
 /*
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 9d1f02e..e544a21 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -69,7 +69,6 @@
 	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
 	"bootm 0x08044000 - 0x08042000\0"
 
-#define CONFIG_BOOTDELAY		3
 
 /*
  * Command line configuration.
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 90492f4..36561e0 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -659,7 +659,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define CONFIG_HOSTNAME		hrcon
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index d3704a4..bfd1bd7 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -66,7 +66,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_BOOTDELAY                       3
 #define CONFIG_BOOTCOMMAND                     "go 0x40040000"
 
 /*
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 4d66dd2..6616d73 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -128,7 +128,6 @@
 							/* devices */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 /* Environment information */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 321fb47..0b05289 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -60,7 +60,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * Command line configuration.
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 870406b..39bb5b3 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -79,7 +79,6 @@
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
 #define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index 5fed55d..a03f87c 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -78,7 +78,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 "if dfubutton; then " \
@@ -90,7 +89,6 @@
 "reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index e43a7fd..5c3b3da 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -84,7 +84,6 @@
 					"earlycon=pl011,0x87e024000000 " \
 					"debug maxcpus=48 rootwait rw "\
 					"root=/dev/sda2 coherent_pool=16M"
-#define CONFIG_BOOTDELAY		5
 
 /* Do not preserve environment */
 #define CONFIG_ENV_IS_NOWHERE		1
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 09f8e8f..3c05883 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -39,7 +39,6 @@
 /* commands to include */
 #define CONFIG_VERSION_VARIABLE
 
-#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 2e84dd2..05fd00f 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -34,7 +34,6 @@
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_BOOTDELAY		3 /* set negative for no autoboot */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"loadaddr=0x81000000\0"		\
 
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index abe1da2..74a9a09 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -39,7 +39,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTARGS			\
 	"console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND		\
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 855d789..aed3931 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -162,7 +162,6 @@
 
 /* Environment information (this is the common part) */
 
-#define CONFIG_BOOTDELAY		0
 
 /* hang() the board on panic() */
 #define CONFIG_PANIC_HANG
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index aa0605f..8b4726f 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -90,7 +90,6 @@
 
 /* Environment variables */
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x91000000	/* loadaddr env var */
 
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index b6a1ae0..8ed9eb0 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -195,7 +195,6 @@ MMCARGS
 
 #define CONFIG_BOOTCOMMAND \
 	"run defboot;"
-#define CONFIG_BOOTDELAY		0
 
 #ifdef CONFIG_NAND
 /*
diff --git a/include/configs/twister.h b/include/configs/twister.h
index 4f5560f..66f4680 100644
--- a/include/configs/twister.h
+++ b/include/configs/twister.h
@@ -20,7 +20,6 @@
 #define CONFIG_TAM3517_SW3_SETTINGS
 #define CONFIG_XR16L2751
 
-#define CONFIG_BOOTDELAY	10
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index c826b20..9d14c2d 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -148,7 +148,6 @@
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
 
-#define CONFIG_BOOTDELAY			3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index d118928..ad54192 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -46,7 +46,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY 3
 
 /*
  * BOOTP options
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 9a113f4..28c748d 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -102,7 +102,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/vct.h b/include/configs/vct.h
index cc5e354..2bc98a8 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -240,7 +240,6 @@ int vct_gpio_get(int pin);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 #define CONFIG_BOOTCOMMAND	"run test3"
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 /*
  * UBI configuration
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 2425ebf..83d0004 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -465,7 +465,6 @@
 #define CONFIG_HOSTNAME		ve8313
 #define CONFIG_UBOOTPATH	ve8313/u-boot.bin
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 6a37582..46cf83b 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -216,7 +216,6 @@
 				"fi ; " \
 				"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
 
-#define CONFIG_BOOTDELAY		1
 
 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
 #define CONFIG_EXTRA_ENV_SETTINGS	\
@@ -241,7 +240,6 @@
 				"fdt chosen ${initrd_addr} ${initrd_end}; " \
 				"booti $kernel_addr - $fdt_addr"
 
-#define CONFIG_BOOTDELAY		1
 
 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
 #define CONFIG_EXTRA_ENV_SETTINGS	\
@@ -260,7 +258,6 @@
 
 #define CONFIG_BOOTCOMMAND	"booti $kernel_addr $initrd_addr $fdt_addr"
 
-#define CONFIG_BOOTDELAY		1
 
 #endif
 
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 6dc8f25..51898e6 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -168,7 +168,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
 #define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
-#define CONFIG_BOOTDELAY		2
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		2
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index b240613..c4a1fd0 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -103,7 +103,6 @@
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_SPD_BUS_NUM		0
 
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_SYS_LOAD_ADDR		0x82000000
 
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 732d091..60513df 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -542,7 +542,6 @@
 
 #define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	 9600
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 4dfcd28..f112fa5 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -9,7 +9,6 @@
 #ifndef __WARP7_CONFIG_H
 #define __WARP7_CONFIG_H
 
-#define CONFIG_BOOTDELAY                1
 #include "mx7_common.h"
 
 #define PHYS_SDRAM_SIZE			SZ_512M
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index a4ae304..153466a 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -97,7 +97,6 @@
 
 #define CONFIG_NET_RETRY_COUNT	100
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index b81b6ff..ba222f9 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -175,7 +175,6 @@
 #define CONFIG_INITRD_TAG
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 07c8abe..71c0b45 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -124,7 +124,6 @@
 #define CONFIG_SUPPORT_VFAT
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_BOOTDELAY			3
 
 /*
  * U-Boot Environment placing definitions.
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index b4aad6c..fdefeaf 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -225,6 +225,5 @@
 	"tftpboot $loadaddr $bootfile;"			\
 	"zboot $loadaddr"
 
-#define CONFIG_BOOTDELAY	2
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 4d68c21..69558fd 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -28,7 +28,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define CONFIG_LOADADDR		0x42000000
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index 067cfa6..e97e9d0 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -33,7 +33,6 @@
 #undef CONFIG_CMD_EEPROM
 
 /*Misc*/
-#define CONFIG_BOOTDELAY		5/* autoboot after 5 seconds     */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory         */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size      */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index b848150..e776e32 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -144,7 +144,6 @@
 # define DFU_ALT_INFO
 #endif
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 9838fbf..73c8d5b 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -196,7 +196,6 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 86c9b4c..9f3158d 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -536,7 +536,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index d1847ac..a418fc5 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -319,7 +319,6 @@
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 6a06b0a..36df668 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -391,7 +391,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 5b377e3..1794ba1 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -375,7 +375,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index fcd7772..6e83cc9 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -40,7 +40,6 @@
 #define	CONFIG_BOOTARGS							\
 	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
 #define	CONFIG_TIMESTAMP
-#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_SYS_TEXT_BASE		0x0
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 264bb63..ea1ead2 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -137,7 +137,6 @@
 
 #define CONFIG_PREBOOT  ""
 
-#define CONFIG_BOOTDELAY	5
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 82ece0d..8dbac87 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -236,7 +236,6 @@
 #endif
 
 #define CONFIG_BOOTCOMMAND		"run $modeboot"
-#define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
 
 /* Miscellaneous configurable options */
-- 
cgit v0.10.2


From da37f006e7c58860d03946b6387394b1ab9c13a4 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:15 +0200
Subject: tests: py: disable main_signon check for printenv cmd

if CONFIG_VERSION_VARIABLE is set, the U-Boot environment
contains a "vers" variable with the current U-Boot version
string. If now "printenv" is called, test/py fails as it
detects the main_sign string, which is in this case correct.

So check only the main_sign as an error, if CONFIG_VERSION_VARIABLE
is not set.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index c41aa5a..22a22d1 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -39,7 +39,11 @@ class StateTestEnv(object):
             Nothing.
         """
 
-        response = self.u_boot_console.run_command('printenv')
+        if self.u_boot_console.config.buildconfig['config_version_variable'] == 'y':
+            with self.u_boot_console.disable_check('main_signon'):
+                response = self.u_boot_console.run_command('printenv')
+        else:
+            response = self.u_boot_console.run_command('printenv')
         self.env = {}
         for l in response.splitlines():
             if not '=' in l:
-- 
cgit v0.10.2


From 640ff60af7a36ba9649dc79be6d117c9c12429fe Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:16 +0200
Subject: power, tps65217: add some defines

add the following defines, needed for the upcoming shc board
support:

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 93cbe36..69a49f7 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -65,7 +65,10 @@ enum {
 #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
 
+#define TPS65217_DCDC_VOLT_SEL_950MV		0x02
+#define TPS65217_DCDC_VOLT_SEL_1100MV		0x08
 #define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
+#define TPS65217_DCDC_VOLT_SEL_1200MV		0x0c
 #define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
 #define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
 
-- 
cgit v0.10.2


From 9c410f7cb7d658d93fc38b2e4eeffc438dfea6cc Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:17 +0200
Subject: arm, am335x: add some missing GPIO register definitions

add missing:
OMAP_GPIO_IRQSTATUS_SET_0 and OMAP_GPIO_IRQSTATUS_SET_1
registers.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 112ac5e..e950b96 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -497,6 +497,8 @@ struct ctrl_stat {
 #define OMAP_GPIO_SYSSTATUS		0x0114
 #define OMAP_GPIO_IRQSTATUS1		0x002c
 #define OMAP_GPIO_IRQSTATUS2		0x0030
+#define OMAP_GPIO_IRQSTATUS_SET_0	0x0034
+#define OMAP_GPIO_IRQSTATUS_SET_1	0x0038
 #define OMAP_GPIO_CTRL			0x0130
 #define OMAP_GPIO_OE			0x0134
 #define OMAP_GPIO_DATAIN		0x0138
-- 
cgit v0.10.2


From c01bc75e7d2c8b31fc130762ee596b53f88729e7 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:18 +0200
Subject: am335x: add some missing CM_CLKMODE_DPLL_SSC macros

add missing CM_CLKMODE_DPLL_SSC_ACK_MASK,
CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and
CM_CLKMODE_DPLL_SSC_TYPE_MASK
defines. Used for enabling spread spectrum.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index a6d2419..7c6be4c 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -44,6 +44,9 @@
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
 #define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
+#define CM_CLKMODE_DPLL_SSC_ACK_MASK		(1 << 13)
+#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK	(1 << 14)
+#define CM_CLKMODE_DPLL_SSC_TYPE_MASK		(1 << 15)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
-- 
cgit v0.10.2


From 694607b563df4425b2d50d220048cc3299a6e947 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:19 +0200
Subject: arm, am335x: Enable Spread Spectrum for the MPU

Enable Spread Spectrum for the MPU by calculating the required
values and setting the registers accordingly.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index 92142c8..7b841b2 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -159,3 +159,76 @@ void enable_basic_clocks(void)
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
 }
+
+/*
+ * Enable Spread Spectrum for the MPU by calculating the required
+ * values and setting the registers accordingly.
+ * @param permille The spreading in permille (10th of a percent)
+ */
+void set_mpu_spreadspectrum(int permille)
+{
+	u32 multiplier_m;
+	u32 predivider_n;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_clkmode_dpll_mpu;
+	u32 ref_clock;
+	u32 pll_bandwidth;
+	u32 mod_freq_divider;
+	u32 exponent;
+	u32 mantissa;
+	u32 delta_m_step;
+
+	printf("Enabling Spread Spectrum of %d permille for MPU\n",
+	       permille);
+
+	/* Read PLL parameter m and n */
+	cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu);
+	multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF;
+	predivider_n = cm_clksel_dpll_mpu & 0x7F;
+
+	/*
+	 * Calculate reference clock (clock after pre-divider),
+	 * its max. PLL bandwidth,
+	 * and resulting mod_freq_divider
+	 */
+	ref_clock = V_OSCK / (predivider_n + 1);
+	pll_bandwidth = ref_clock / 70;
+	mod_freq_divider = ref_clock / (4 * pll_bandwidth);
+
+	/* Calculate Mantissa/Exponent */
+	exponent = 0;
+	mantissa = mod_freq_divider;
+	while ((mantissa > 127) && (exponent < 7)) {
+		exponent++;
+		mantissa /= 2;
+	}
+	if (mantissa > 127)
+		mantissa = 127;
+
+	mod_freq_divider = mantissa << exponent;
+
+	/*
+	 * Calculate Modulation steps
+	 * As we use Downspread only, the spread is twice the value of
+	 * permille, so Div2!
+	 * As it takes the value in percent, divide by ten!
+	 */
+	delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18;
+	delta_m_step /= 100;
+	delta_m_step /= mod_freq_divider;
+	if (delta_m_step > 0xFFFFF)
+		delta_m_step = 0xFFFFF;
+
+	/* Setup Spread Spectrum */
+	writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu);
+	writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu);
+	cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu);
+	/* clear all SSC flags */
+	cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT);
+	/* enable SSC with Downspread only */
+	cm_clkmode_dpll_mpu |=  CM_CLKMODE_DPLL_SSC_EN_MASK |
+				CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+	writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu);
+	while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000))
+		;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 7c6be4c..acf3fd5 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -117,4 +117,5 @@ void enable_basic_clocks(void);
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
 void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
+void set_mpu_spreadspectrum(int permille);
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index e950b96..62bca8c 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -99,7 +99,8 @@ struct cm_wkuppll {
 	unsigned int timer0clkctrl;	/* offset 0x10 */
 	unsigned int resv2[3];
 	unsigned int idlestdpllmpu;	/* offset 0x20 */
-	unsigned int resv3[2];
+	unsigned int sscdeltamstepdllmpu; /* off  0x24 */
+	unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
 	unsigned int clkseldpllmpu;	/* offset 0x2c */
 	unsigned int resv4[1];
 	unsigned int idlestdpllddr;	/* offset 0x34 */
-- 
cgit v0.10.2


From 496c5483e9ad80d34ff0d9ee9abb813e51be2237 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:20 +0200
Subject: bootstage: call show_boot_progress also in SPL

show_boot_progress() is now called from SPL also.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/common/init/board_init.c b/common/init/board_init.c
index d17bb29..ef01a9a 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -146,3 +146,8 @@ void board_init_f_init_reserve(ulong base)
 	base += CONFIG_SYS_MALLOC_F_LEN;
 #endif
 }
+
+/*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+__weak void show_boot_progress(int val) {}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index c8dfc14..840910a 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -36,6 +36,11 @@ struct spl_image_info spl_image;
 static bd_t bdata __attribute__ ((section(".data")));
 
 /*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+__weak void show_boot_progress(int val) {}
+
+/*
  * Default function to determine if u-boot or the OS should
  * be started. This implementation always returns 1.
  *
diff --git a/include/bootstage.h b/include/bootstage.h
index 0880a68..a589be6 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -213,7 +213,9 @@ enum bootstage_id {
  */
 ulong timer_get_boot_us(void);
 
-#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC)
+#if defined(USE_HOSTCC)
+#define show_boot_progress(val) do {} while (0)
+#else
 /*
  * Board code can implement show_boot_progress() if needed.
  *
@@ -221,8 +223,6 @@ ulong timer_get_boot_us(void);
  *		has occurred.
  */
 void show_boot_progress(int val);
-#else
-#define show_boot_progress(val) do {} while (0)
 #endif
 
 #if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
-- 
cgit v0.10.2


From a5e27b416fd2068e2e9c01b307f449e29e7abcb5 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:21 +0200
Subject: mmc: revert mmc: Handle switch error status bit in MMC card status

revert patch:
commit: 6b2221b008e0: mmc: Handle switch error status bit in MMC card status

to get eMMC working on shc board

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 94f19ad..7586558 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -155,8 +155,6 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 #endif
 		return TIMEOUT;
 	}
-	if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
-		return SWITCH_ERR;
 
 	return 0;
 }
@@ -516,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc)
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
 
 	if (err)
-		return err == SWITCH_ERR ? 0 : err;
+		return err;
 
 	/* Now check to see that it worked */
 	err = mmc_send_ext_csd(mmc, ext_csd);
-- 
cgit v0.10.2


From 3d4f628d2f6043c3b3ce1fabf2c2286456c02e77 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:22 +0200
Subject: mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xx

Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index be34057..d007b56 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -701,6 +701,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 	defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
+	defined(CONFIG_AM33XX) || \
 	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
 		defined(CONFIG_HSMMC2_8BIT)
 		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
-- 
cgit v0.10.2


From a4475af5b4188b69739dacdc82351ceec71a1bbe Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:23 +0200
Subject: armv7: omap-common: make SPL board_mmc_init() weak

make this function weak, so board code can setup in SPL
MMC init with board special values.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 0456263..8333b20 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -200,7 +200,7 @@ void spl_board_init(void)
 #endif
 }
 
-int board_mmc_init(bd_t *bis)
+__weak int board_mmc_init(bd_t *bis)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
-- 
cgit v0.10.2


From 3e584b94d207deca9663955b78c88d61fdfe8741 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:24 +0200
Subject: doc, spl, am335x: update am335x-network

on the shc board we see when booting in net boot mode,
that the ROM bootloader sends "AM335x ROM" as
vendor-class-identifier. U-Boots doc says "DM814x ROM".

So, add the info to the doc, that there is also
"AM335x ROM" possible.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network
index 9b63791..e3cf93f 100644
--- a/doc/SPL/README.am335x-network
+++ b/doc/SPL/README.am335x-network
@@ -66,6 +66,10 @@ subnet 192.168.8.0 netmask 255.255.255.0 {
   }
 }
 
+  May the ROM bootloader sends another "vendor-class-identifier"
+  on the shc board with an AM335X it is:
+  "AM335x ROM"
+
   2. Setup TFTP server.
      Install TFTP server and put image files to it's root directory
 (likely /tftpboot or /var/lib/tftpboot or /srv/tftp). You will need
-- 
cgit v0.10.2


From d8ccbe93b576696852a7cdb2ac8018bb47ce787e Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:31:25 +0200
Subject: am335x, shc: add support for the am335x based bosch shc board

U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06)
SHC C3-Sample
MPU reference clock runs at 6 MHz
Setting MPU clock to 594 MHz
Enabling Spread Spectrum of 18 permille for MPU
Trying to boot from MMC
reading u-boot.img
reading u-boot.img

U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100)

       Watchdog enabled
I2C:   ready
DRAM:  512 MiB
reloc off 1f783000
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Net:   cpsw
U-Boot#

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 30ed279..26ccf62 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -396,6 +396,14 @@ config TARGET_AM335X_EVM
 	select DM_GPIO
 	select TI_I2C_BOARD_DETECT
 
+config TARGET_AM335X_SHC
+	bool "Support am335x based shc board from bosch"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_AM335X_SL50
 	bool "Support am335x_sl50"
 	select CPU_V7
@@ -875,6 +883,7 @@ source "arch/arm/cpu/armv8/Kconfig"
 
 source "arch/arm/imx-common/Kconfig"
 
+source "board/bosch/shc/Kconfig"
 source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig
new file mode 100644
index 0000000..c71af11
--- /dev/null
+++ b/board/bosch/shc/Kconfig
@@ -0,0 +1,87 @@
+if TARGET_AM335X_SHC
+
+config SYS_BOARD
+	default "shc"
+
+config SYS_VENDOR
+	default "bosch"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_shc"
+
+choice
+	prompt "enable different boot versions for the shc board"
+	default EMMC
+	help
+	  Select the boot version of the shc board.
+
+config SHC_EMMC
+	bool "enable eMMC"
+	help
+	  enable here the eMMC functionality on the bosch shc board.
+
+config SHC_ICT
+	bool "enable ICT"
+	help
+	  enable here the ICT functionality on the bosch shc board
+
+config SHC_NETBOOT
+	bool "enable NETBOOT"
+	help
+	  enable here the NETBOOT functionality on the bosch shc board
+
+config SHC_SDBOOT
+	bool "enable SDBOOT"
+	help
+	  enable here the SDBOOT functionality on the bosch shc board
+
+endchoice
+
+choice
+	prompt "enable different board versions for the shc board"
+	default C3_SAMPLE
+	help
+	  Select the board version of the shc board.
+
+config B_SAMPLE
+	bool "B Sample board version"
+	help
+	  activate, if you want to build for the B sample version
+	  of the bosch shc board
+
+config B2_SAMPLE
+	bool "B2 Sample board version"
+	help
+	  activate, if you want to build for the B2 sample version
+	  of the bosch shc board
+
+config C_SAMPLE
+	bool "C Sample board version"
+	help
+	  activate, if you want to build for the C sample version
+	  of the bosch shc board
+
+config C2_SAMPLE
+	bool "C2 Sample board version"
+	help
+	  activate, if you want to build for the C2 sample version
+	  of the bosch shc board
+
+config C3_SAMPLE
+	bool "C3 Sample board version"
+	help
+	  activate, if you want to build for the C3 sample version
+	  of the bosch shc board
+
+config SERIES
+	bool "Series board version"
+	help
+	  activate, if you want to build for the Series version
+	  of the bosch shc board
+
+endchoice
+
+endif
diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS
new file mode 100644
index 0000000..ae3c035
--- /dev/null
+++ b/board/bosch/shc/MAINTAINERS
@@ -0,0 +1,11 @@
+SHC BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/bosch/shc
+F:	include/configs/am335x_shc.h
+F:	configs/am335x_shc_defconfig
+F:	configs/am335x_shc_ict_defconfig
+F:	configs/am335x_shc_netboot_defconfig
+F:	configs/am335x_shc_prompt_defconfig
+F:	configs/am335x_shc_sdboot_defconfig
+F:	configs/am335x_shc_sdboot_prompt_defconfig
diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile
new file mode 100644
index 0000000..4fec2bf
--- /dev/null
+++ b/board/bosch/shc/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= mux.o
+obj-y	+= board.o
diff --git a/board/bosch/shc/README b/board/bosch/shc/README
new file mode 100644
index 0000000..2f206e0
--- /dev/null
+++ b/board/bosch/shc/README
@@ -0,0 +1,114 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_shc' build.
+
+Hardware
+========
+
+AM335X based board:
+
+I2C:   ready
+DRAM:  512 MiB
+Enabling the D-Cache
+MMC:   OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz
+Net:   cpsw
+
+Following boot options are possible:
+
+2 Jumpers:
+
+Jumper 1 Jumper 2 Bootmode
+off      off    eMMC boot
+on       off    SD boot
+off      on     Net boot
+
+Compiling
+=========
+
+$ make am335x_shc_defconfig
+  HOSTCC  scripts/basic/fixdep
+  HOSTCC  scripts/kconfig/conf.o
+  SHIPPED scripts/kconfig/zconf.tab.c
+  SHIPPED scripts/kconfig/zconf.lex.c
+  SHIPPED scripts/kconfig/zconf.hash.c
+  HOSTCC  scripts/kconfig/zconf.tab.o
+  HOSTLD  scripts/kconfig/conf
+#
+# configuration written to .config
+#
+$ make -s all
+
+-> now you have the MLO and the u-boot.img file, you can put
+on your SD card or eMMC.
+
+Configuring
+===========
+
+There are a lot of board versions and boot configurations, which
+can be selected through "make menuconfig"
+
+ARM architecture  --->
+  enable different boot versions for the shc board (enable eMMC)  --->
+   (X) enable eMMC
+   ( ) enable ICT
+   ( ) enable NETBOOT
+   ( ) enable SDBOOT
+
+  enable different board versions for the shc board (C3 Sample board version)  --->
+   ( ) B Sample board version
+   ( ) B2 Sample board version
+   ( ) C Sample board version
+   ( ) C2 Sample board version
+   (X) C3 Sample board version
+   ( ) Series board version
+
+Netboot
+=======
+- see also doc/SPL/README.am335x-network
+
+- set the jumper into netboot mode
+- compile the U-boot sources with:
+  make am335x_shc_netboot_defconfig
+  make all
+- copy the images into your tftp boot directory
+  cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin
+  cp u-boot.img /tftpboot/.../u-boot-restore.img
+- power on the board, and you should get something like this:
+
+U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18)
+#### NETBOOT ####
+SHC
+MPU reference clock runs at 6 MHz
+Setting MPU clock to 594 MHz
+Enabling Spread Spectrum of 18 permille for MPU
+Trying to boot from net
+Using default environment
+
+<ethaddr> not set. Validating first E-fuse MAC
+cpsw
+cpsw Waiting for PHY auto negotiation to complete... done
+link up on port 0, speed 100, full duplex
+BOOTP broadcast 1
+BOOTP broadcast 2
+DHCP client bound to address 192.168.20.91 (258 ms)
+Using cpsw device
+TFTP from server 192.168.1.1; our IP address is 192.168.20.91
+Filename 'shc/u-boot-restore.img'.
+Load address: 0x807fffc0
+Loading: ##################
+         1.2 MiB/s
+done
+Bytes transferred = 262480 (40150 hex)
+
+
+U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200)
+
+       Watchdog enabled
+I2C:   ready
+DRAM:  512 MiB
+MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
+*** Warning - bad CRC, using default environment
+
+Net:   cpsw
+switch to partitions #0, OK
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
new file mode 100644
index 0000000..e90693f
--- /dev/null
+++ b/board/bosch/shc/board.c
@@ -0,0 +1,648 @@
+/*
+ * board.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "mmc.h"
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+static struct shc_eeprom __attribute__((section(".data"))) header;
+static int shc_eeprom_valid;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+		     sizeof(header))) {
+		puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return -EIO;
+	}
+
+	if (header.magic != HDR_MAGIC) {
+		printf("Incorrect magic number (0x%x) in EEPROM\n",
+		       header.magic);
+		return -EIO;
+	}
+
+	shc_eeprom_valid = 1;
+
+	return 0;
+}
+
+static void shc_request_gpio(void)
+{
+	gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
+	gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
+	gpio_request(RESET_GPIO, "reset");
+	gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
+	gpio_request(WIFI_RST_GPIO, "WIFI rst");
+	gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
+	gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
+	gpio_request(ENOC_RST_GPIO, "ENOC rst");
+#if defined CONFIG_B_SAMPLE
+	gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
+	gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
+	gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
+	gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
+#else
+	gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
+	gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
+	gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
+	gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
+	gpio_request(LED_PWM_GPIO, "LED PWM");
+	gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
+#endif
+	gpio_request(BACK_BUTTON_GPIO, "Back button");
+	gpio_request(FRONT_BUTTON_GPIO, "Front button");
+}
+
+/*
+ * Function which forces all installed modules into running state for ICT
+ * testing. Called by SPL.
+ */
+static void __maybe_unused force_modules_running(void)
+{
+	/* Wi-Fi power regulator enable - high = enabled */
+	gpio_direction_output(WIFI_REGEN_GPIO, 1);
+	/*
+	 * Wait for Wi-Fi power regulator to reach a stable voltage
+	 * (soft-start time, max. 350 µs)
+	 */
+	__udelay(350);
+
+	/* Wi-Fi module reset - high = running */
+	gpio_direction_output(WIFI_RST_GPIO, 1);
+
+	/* ZigBee reset - high = running */
+	gpio_direction_output(ZIGBEE_RST_GPIO, 1);
+
+	/* BidCos reset - high = running */
+	gpio_direction_output(BIDCOS_RST_GPIO, 1);
+
+#if !defined(CONFIG_B_SAMPLE)
+	/* Z-Wave reset - high = running */
+	gpio_direction_output(Z_WAVE_RST_GPIO, 1);
+#endif
+
+	/* EnOcean reset - low = running */
+	gpio_direction_output(ENOC_RST_GPIO, 0);
+}
+
+/*
+ * Function which forces all installed modules into reset - to be released by
+ * the OS, called by SPL
+ */
+static void __maybe_unused force_modules_reset(void)
+{
+	/* Wi-Fi module reset - low = reset */
+	gpio_direction_output(WIFI_RST_GPIO, 0);
+
+	/* Wi-Fi power regulator enable - low = disabled */
+	gpio_direction_output(WIFI_REGEN_GPIO, 0);
+
+	/* ZigBee reset - low = reset */
+	gpio_direction_output(ZIGBEE_RST_GPIO, 0);
+
+	/* BidCos reset - low = reset */
+	/*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
+
+#if !defined(CONFIG_B_SAMPLE)
+	/* Z-Wave reset - low = reset */
+	gpio_direction_output(Z_WAVE_RST_GPIO, 0);
+#endif
+
+	/* EnOcean reset - high = reset*/
+	gpio_direction_output(ENOC_RST_GPIO, 1);
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader booting"
+ */
+static void __maybe_unused leds_set_booting(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+
+	/* Turn all red LEDs on */
+	gpio_direction_output(LED_PWR_RD_GPIO, 1);
+	gpio_direction_output(LED_CONN_RD_GPIO, 1);
+
+#else /* All other SHCs starting with B2-Sample */
+	/* Set the PWM GPIO */
+	gpio_direction_output(LED_PWM_GPIO, 1);
+	/* Turn all red LEDs on */
+	gpio_direction_output(LED_PWR_RD_GPIO, 1);
+	gpio_direction_output(LED_LAN_RD_GPIO, 1);
+	gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
+
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader error"
+ */
+static void leds_set_failure(int state)
+{
+#if defined(CONFIG_B_SAMPLE)
+	/* Turn all blue and green LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_GN_GPIO, 0);
+	gpio_set_value(LED_CONN_BL_GPIO, 0);
+	gpio_set_value(LED_CONN_GN_GPIO, 0);
+
+	/* Turn all red LEDs to 'state' */
+	gpio_set_value(LED_PWR_RD_GPIO, state);
+	gpio_set_value(LED_CONN_RD_GPIO, state);
+
+#else /* All other SHCs starting with B2-Sample */
+	/* Set the PWM GPIO */
+	gpio_direction_output(LED_PWM_GPIO, 1);
+
+	/* Turn all blue LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_LAN_BL_GPIO, 0);
+	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+
+	/* Turn all red LEDs to 'state' */
+	gpio_set_value(LED_PWR_RD_GPIO, state);
+	gpio_set_value(LED_LAN_RD_GPIO, state);
+	gpio_set_value(LED_CLOUD_RD_GPIO, state);
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader finished"
+ */
+static void leds_set_finish(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+	/* Turn all LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_RD_GPIO, 0);
+	gpio_set_value(LED_PWR_GN_GPIO, 0);
+	gpio_set_value(LED_CONN_BL_GPIO, 0);
+	gpio_set_value(LED_CONN_RD_GPIO, 0);
+	gpio_set_value(LED_CONN_GN_GPIO, 0);
+#else /* All other SHCs starting with B2-Sample */
+	/* Turn all LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_RD_GPIO, 0);
+	gpio_set_value(LED_LAN_BL_GPIO, 0);
+	gpio_set_value(LED_LAN_RD_GPIO, 0);
+	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+	gpio_set_value(LED_CLOUD_RD_GPIO, 0);
+
+	/* Turn off the PWM GPIO and mux it to EHRPWM */
+	gpio_set_value(LED_PWM_GPIO, 0);
+	enable_shc_board_pwm_pin_mux();
+#endif
+}
+
+static void check_button_status(void)
+{
+	ulong value;
+	gpio_direction_input(FRONT_BUTTON_GPIO);
+	value = gpio_get_value(FRONT_BUTTON_GPIO);
+
+	if (value == 0) {
+		printf("front button activated !\n");
+		setenv("harakiri", "1");
+	}
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 1;
+}
+#endif
+
+static void shc_board_early_init(void)
+{
+	shc_request_gpio();
+# ifdef CONFIG_SHC_ICT
+	/* Force all modules into enabled state for ICT testing */
+	force_modules_running();
+# else
+	/* Force all modules to enter Reset state until released by the OS */
+	force_modules_reset();
+# endif
+	leds_set_booting();
+}
+
+#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
+#define OSC	(V_OSCK/1000000)
+/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
+#define MPUPLL_N        (4-1)
+/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
+#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
+
+const struct dpll_params dpll_ddr_shc = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr_shc;
+}
+
+/*
+ * As we enabled downspread SSC with 1.8%, the values needed to be corrected
+ * such that the 20% overshoot will not lead to too high frequencies.
+ * In all cases, this is achieved by subtracting one from M (6 MHz less).
+ * Example: 600 MHz CPU
+ *   Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
+ *   600 MHz - 6 MHz (1x Fref) = 594 MHz
+ *   SSC: 594 MHz * 1.8% = 10.7 MHz SSC
+ *   Overshoot: 10.7 MHz * 20 % = 2.2 MHz
+ *   --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
+ */
+const struct dpll_params dpll_mpu_shc_opp100 = {
+		99, MPUPLL_N, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int sil_rev;
+	int mpu_vdd;
+
+	puts(BOARD_ID_STR);
+
+	/*
+	 * Set CORE Frequency to OPP100
+	 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
+	 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	if (sil_rev < 2) {
+		puts("We do not support Silicon Revisions below 2.0!\n");
+		return;
+	}
+
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
+
+	/*
+	 * Retrieve the CPU max frequency by reading the efuse
+	 * SHC-Default: 600 MHz
+	 */
+	switch (dpll_mpu_opp100.m) {
+	case MPUPLL_M_1000:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+		break;
+	case MPUPLL_M_800:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+		break;
+	case MPUPLL_M_720:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+		break;
+	case MPUPLL_M_600:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+		break;
+	case MPUPLL_M_300:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
+		break;
+	default:
+		puts("Cannot determine the frequency, failing!\n");
+		return;
+	}
+
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set MPU Frequency to what we detected */
+	printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
+	printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
+	       dpll_mpu_shc_opp100.m);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
+
+	/* Enable Spread Spectrum for this freq to be clean on EMI side */
+	set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
+
+	/*
+	 * Using the default voltages for the PMIC (TPS65217D)
+	 * LS1 = 1.8V (VDD_1V8)
+	 * LS2 = 3.3V (VDD_3V3A)
+	 * LDO1 = 1.8V (VIO and VRTC)
+	 * LDO2 = 3.3V (VDD_3V3AUX)
+	 */
+	shc_board_early_init();
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_shc_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_shc_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_shc_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+	/* Configure the DDR3 RAM */
+	config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
+		   &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom() < 0)
+		puts("EEPROM Content Invalid.\n");
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+	shc_request_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	check_button_status();
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (shc_eeprom_valid)
+		if (is_valid_ethaddr(header.mac_addr))
+			eth_setenv_enetaddr("ethaddr", header.mac_addr);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
+	defined(CONFIG_SPL_USBETH_SUPPORT)) && \
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if =	PHY_INTERFACE_MODE_MII;
+	cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+static void bosch_check_reset_pin(void)
+{
+	if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
+		printf("Resetting ...\n");
+		writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+		disable_interrupts();
+		reset_cpu(0);
+		/*NOTREACHED*/
+	}
+}
+
+static void hang_bosch(const char *cause, int code)
+{
+	int lv;
+
+	gpio_direction_input(RESET_GPIO);
+
+	/* Enable reset pin interrupt on falling edge */
+	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
+	enable_interrupts();
+
+	puts(cause);
+	for (;;) {
+		for (lv = 0; lv < code; lv++) {
+			bosch_check_reset_pin();
+			leds_set_failure(1);
+			__udelay(150 * 1000);
+			leds_set_failure(0);
+			__udelay(150 * 1000);
+		}
+#if defined(BLINK_CODE)
+		__udelay(300 * 1000);
+#endif
+	}
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case BOOTSTAGE_ID_NEED_RESET:
+		hang_bosch("need reset", 4);
+		break;
+	}
+}
+#endif
+
+void arch_preboot_os(void)
+{
+	leds_set_finish();
+}
+
+#if defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
+	ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
+	if (ret)
+		return ret;
+
+	ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
+	return ret;
+}
+#endif
diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h
new file mode 100644
index 0000000..46167fe
--- /dev/null
+++ b/board/bosch/shc/board.h
@@ -0,0 +1,187 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Definition to control the GPIOs (for LEDs and Reset) */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+static inline int board_is_b_sample(void)
+{
+#if defined CONFIG_B_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_c_sample(void)
+{
+#if defined CONFIG_C_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_c3_sample(void)
+{
+#if defined CONFIG_C3_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_series(void)
+{
+#if defined CONFIG_SERIES
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/*
+ * Definitions for pinmuxing header and Board ID strings
+ */
+#if defined CONFIG_B_SAMPLE
+# define BOARD_ID_STR "SHC B-Sample\n"
+#elif defined CONFIG_B2_SAMPLE
+# define BOARD_ID_STR "SHC B2-Sample\n"
+#elif defined CONFIG_C_SAMPLE
+# if defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C-Sample\n"
+# endif
+#elif defined CONFIG_C2_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C2-Sample\n"
+# endif
+#elif defined CONFIG_C3_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C3-Sample\n"
+# endif
+#elif defined CONFIG_SERIES
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC\n"
+# else
+#  define BOARD_ID_STR "SHC\n"
+# endif
+#else
+# define BOARD_ID_STR "Unknown device!\n"
+#endif
+
+/*
+ * Definitions for GPIO pin assignments
+ */
+#if defined CONFIG_B_SAMPLE
+
+# define LED_PWR_BL_GPIO   GPIO_TO_PIN(1, 17)
+# define LED_PWR_RD_GPIO   GPIO_TO_PIN(1, 18)
+# define LED_PWR_GN_GPIO   GPIO_TO_PIN(1, 19)
+# define LED_CONN_BL_GPIO  GPIO_TO_PIN(0, 26)
+# define LED_CONN_RD_GPIO  GPIO_TO_PIN(0, 22)
+# define LED_CONN_GN_GPIO  GPIO_TO_PIN(0, 23)
+# define RESET_GPIO        GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO   GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO     GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO   GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO   GPIO_TO_PIN(0, 12)
+# define ENOC_RST_GPIO     GPIO_TO_PIN(1, 22)
+
+#else
+
+# define LED_PWR_BL_GPIO   GPIO_TO_PIN(0, 22)
+# define LED_PWR_RD_GPIO   GPIO_TO_PIN(0, 23)
+# define LED_LAN_BL_GPIO   GPIO_TO_PIN(1, 17)
+# define LED_LAN_RD_GPIO   GPIO_TO_PIN(0, 26)
+# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18)
+# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2)
+# define LED_PWM_GPIO      GPIO_TO_PIN(1, 19)
+# define RESET_GPIO        GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO   GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO     GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO   GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO   GPIO_TO_PIN(1, 24)
+# define Z_WAVE_RST_GPIO   GPIO_TO_PIN(1, 21)
+# define ENOC_RST_GPIO     GPIO_TO_PIN(1, 22)
+
+#endif
+
+#define BACK_BUTTON_GPIO    GPIO_TO_PIN(1, 29)
+#define FRONT_BUTTON_GPIO   GPIO_TO_PIN(1, 25)
+
+/* Reset is on GPIO pin 29 of GPIO bank 1 */
+#define RESET_MASK	(0x1 << 29)
+
+#define HDR_MAGIC	0x43485342
+#define HDR_ETH_ALEN	6
+#define HDR_NAME_LEN	8
+#define HDR_REV_LEN	8
+#define HDR_SER_LEN	16
+#define HDR_ROOT_LEN	12
+#define HDR_FATC_LEN	12
+
+/*
+* SHC parameters held in On-Board I²C EEPROM device.
+*
+* Header Format
+*
+*  Name     Size   Contents
+*-------------------------------------------------------------
+*  Magic     4     0x42 0x53 0x48 0x43  [BSHC]
+*
+*  Version   2     0x0100 for v1.0
+*
+*  Lenght    2     The length of the complete structure, not only this header
+*
+*  Eth-MAC   6     Ethernet MAC Address
+*                  SHC Pool: 7C:AC:B2:00:10:01 - TBD
+*
+*  --- Further values follow, not important for Bootloader ---
+*/
+
+struct  shc_eeprom {
+	u32  magic;
+	u16  version;
+	u16  lenght;
+	uint8_t mac_addr[HDR_ETH_ALEN];
+};
+
+void enable_uart0_pin_mux(void);
+void enable_shc_board_pin_mux(void);
+void enable_shc_board_pwm_pin_mux(void);
+
+#endif
diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c
new file mode 100644
index 0000000..e8ada65
--- /dev/null
+++ b/board/bosch/shc/mux.c
@@ -0,0 +1,261 @@
+/*
+ * mux.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)},		/* UART0_TXD */
+	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART0_CTS */
+	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)},		/* UART0_RTS */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)},		/* UART1_TXD */
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART1_CTS */
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)},		/* UART1_RTS */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	{OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */
+	{OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */
+	{OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */
+	{OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{-1},
+};
+
+static struct module_pin_mux mmc2_pin_mux[] = {
+	{OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */
+	{OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */
+	{OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */
+	{OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */
+	{OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */
+	{OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)},  /* MMC2_CLK */
+	{-1},
+};
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)},	/* GPIO0_7 */
+	{-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+	{OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+	{OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+	{OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+	{OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+	{OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)},
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)},	/* gpio0[22] - LED_PWR_BL (external pull-down) */
+	{OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)},	/* gpio0[23] - LED_PWR_RD (external pull-down) */
+	{OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)},	/* gpio0[26] - LED_LAN_RD (external pull-down) */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* gpio0[27] - #WIFI_RST (external pull-down) */
+	{OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)},	/* gpio1[16] - WIFI_REGEN */
+	{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)},	/* gpio1[17] - LED_LAN_BL */
+	{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)},	/* gpio1[18] - LED_Cloud_BL */
+	{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)},	/* gpio1[19] -  LED_PWM as GPIO */
+	{OFFSET(gpmc_a4), (MODE(7))},			/* gpio1[20] -  #eMMC_RST */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},	/* gpio1[21] -  #Z-Wave_RST */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* gpio1[22] -  ENOC_RST */
+	{OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)},	/* gpio1[23] -  WIFI_MODE */
+	{OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[24] -  #BIDCOS_RST */
+	{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[25] -  USR_BUTTON */
+	{OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[26] -  #USB1_OC */
+	{OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[27] -  BIDCOS_PROG */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)},	/* gpio1[28] -  ZIGBEE_PC7 */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[29] -  RESET_BUTTON */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)},	/* gpio2[2] -  LED_Cloud_RD */
+	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] -  #WIFI_POR */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},	/* gpio2[4] -  N/C */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},	/* gpio2[5] -  EEPROM_WP */
+	{OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)},	/* gpio2[6] */
+	{OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)},	/* gpio2[7] */
+	{OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)},	/* gpio2[8] */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)},	/* gpio2[9] */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)},	/* gpio2[10] */
+	{OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)},	/* gpio2[11] */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)},	/* gpio2[12] */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)},	/* gpio2[13] */
+	{OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)},	/* gpio2[14] */
+	{OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)},	/* gpio2[15] */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)},	/* gpio2[16] */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)},	/* gpio2[17] */
+	{OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)},	/* gpio0[8] */
+	{OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)},	/* gpio0[9] */
+	{OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)},	/* gpio0[10] */
+	{OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)},	/* gpio0[11] */
+	{OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)},	/* gpio2[22] */
+	{OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)},	/* gpio2[23] */
+	{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)},	/* gpio2[24] */
+	{OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)},	/* gpio0[4] */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},	/* gpio0[5] */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)},	/* gpio3[18] - #ZIGBEE_RST */
+	{OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS},	/* gpio3[19] - ZIGBEE_BOOT */
+	{OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},	/* gpio3[19] - ZIGBEE_BOOT */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txen), MODE(0)},
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txd3), MODE(0)},
+	{OFFSET(mii1_txd2), MODE(0)},
+	{OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
+	{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
+	{-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+	{OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)},
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_shc_board_pwm_pin_mux(void)
+{
+	configure_module_pin_mux(pwm_pin_mux);
+}
+
+void enable_shc_board_pin_mux(void)
+{
+	/* Do board-specific muxes. */
+	if (board_is_c3_sample() || board_is_series()) {
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(mmc1_pin_mux);
+		configure_module_pin_mux(mmc2_pin_mux);
+		configure_module_pin_mux(i2c0_pin_mux);
+		configure_module_pin_mux(gpio0_7_pin_mux);
+		configure_module_pin_mux(gpio_pin_mux);
+		configure_module_pin_mux(uart1_pin_mux);
+		configure_module_pin_mux(uart2_pin_mux);
+		configure_module_pin_mux(uart4_pin_mux);
+		configure_module_pin_mux(spi1_pin_mux);
+		configure_module_pin_mux(jtag_pin_mux);
+	} else {
+		puts("Unknown board, cannot configure pinmux.");
+		hang();
+	}
+}
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
new file mode 100644
index 0000000..2c7091b
--- /dev/null
+++ b/configs/am335x_shc_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
new file mode 100644
index 0000000..ffda4d2
--- /dev/null
+++ b/configs/am335x_shc_ict_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_ICT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
new file mode 100644
index 0000000..54558b6
--- /dev/null
+++ b/configs/am335x_shc_netboot_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_NETBOOT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
new file mode 100644
index 0000000..a415ab4
--- /dev/null
+++ b/configs/am335x_shc_prompt_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
new file mode 100644
index 0000000..944256f
--- /dev/null
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_SDBOOT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
new file mode 100644
index 0000000..2767012
--- /dev/null
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_SDBOOT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
new file mode 100644
index 0000000..f2484cb
--- /dev/null
+++ b/include/configs/am335x_shc.h
@@ -0,0 +1,340 @@
+/*
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_AM335X_SHC_H
+#define __CONFIG_AM335X_SHC_H
+
+#include <configs/ti_am335x_common.h>
+
+/* settings we don;t want on this board */
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+#undef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_EXT4_WRITE
+#undef CONFIG_CMD_MMC_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_PXE
+
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define MACH_TYPE_BOSCH_SHC_B		9001
+#define MACH_TYPE_BOSCH_SHC_B2		9002
+#define MACH_TYPE_BOSCH_SHC_C		9003
+#define MACH_TYPE_BOSCH_SHC_C2		9004
+#define MACH_TYPE_BOSCH_SHC_C3		9005
+#define MACH_TYPE_BOSCH_SHC		9006
+#ifdef CONFIG_B_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_B
+#elif defined CONFIG_B2_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_B2
+#elif defined CONFIG_C_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_C
+#elif defined CONFIG_C2_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_C2
+#elif defined CONFIG_C3_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_C3
+#elif defined CONFIG_SERIES
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC
+#endif /* #ifdef CONFIG_B_SAMPLE */
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_ENV_IS_IN_MMC		1
+
+/*
+ * in case of SD Card or Network boot we want to have a possibility to
+ * debrick the shc, therefore do not read environment from eMMC
+ */
+#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#else
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#endif
+
+/*
+ * Info when using boot partitions: As environment resides within first
+ * 128 kB, MLO must start at 128 kB == 0x20000
+ * ENV at MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1,
+ * 4..7=general0..3
+ */
+#define CONFIG_ENV_SIZE				0x1000 /* 4 KB */
+#define CONFIG_ENV_OFFSET			0x7000 /* 28 kB */
+
+#define CONFIG_HSMMC2_8BIT
+
+#define CONFIG_ENV_OFFSET_REDUND    0x9000 /* 36 kB */
+#define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_ISO_PARTITION
+#endif
+#ifndef CONFIG_SHC_ICT
+/*
+ * In builds other than ICT, reset to retry after timeout
+ * Define a timeout after which a stopped bootloader continues autoboot
+ * (only works with CONFIG_RESET_TO_RETRY)
+ */
+# define CONFIG_BOOT_RETRY_TIME 30
+# define CONFIG_RESET_TO_RETRY
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"kloadaddr=0x84000000\0" \
+	"fdtaddr=0x85000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=am335x-shc.dtb\0" \
+	"verify=no\0" \
+	"serverip=10.55.152.184\0" \
+	"rootpath=/srv/nfs/shc-rootfs\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=quiet\0" \
+	"mmcdev=1\0" \
+	"harakiri=0\0" \
+	"mmcpart=2\0" \
+	"active_root=root1\0" \
+	"inactive_root=root2\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"ip_method=none\0" \
+	"bootargs_defaults=setenv bootargs " \
+		"console=${console} " \
+		"${optargs}\0" \
+	"mmcargs=run bootargs_defaults;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} ip=${ip_method}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi;\0" \
+	"importbootenv=echo Importing environment variables from uEnv.txt ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \
+	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \
+	"netloaduimage=tftp ${loadaddr} ${bootfile}\0" \
+	"netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting Linux from ${mmcdevice} ...; " \
+		"run mmcargs; " \
+		"if run loadfdt; then " \
+			"echo device tree detected; " \
+			"bootm ${kloadaddr} - ${fdtaddr}; " \
+		"else " \
+			"bootm ${kloadaddr}; " \
+		"fi; \0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"run netloaduimage; " \
+		"run netargs; " \
+		"echo NFS path: ${serverip}:${rootpath};" \
+		"if run netloadfdt; then " \
+			"echo device tree detected; " \
+			"bootm ${loadaddr} - ${fdtaddr}; " \
+		"else " \
+			"bootm ${loadaddr}; " \
+		"fi; \0" \
+	"emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \
+	"mmcpart_gp=mmcpart gp 1 40; \0" \
+	"mmcpart_enhance=mmcpart enhance 0 64; \0" \
+	"mmcpart_rel_write=mmcpart rel_write 1f; \0" \
+	"mmcpart_commit=mmcpart commit 1; \0" \
+	"mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \
+	"led_success=gpio set 22; \0" \
+	"fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \
+	"uenv_exec=if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi;\0" \
+	"sd_setup=echo SD/MMC-Card detected on device 0; " \
+		"setenv mmcdevice SD; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \
+	"emmc_setup=echo eMMC detected on device 1; " \
+		"setenv mmcdevice eMMC; " \
+		"setenv mmcdev 1; " \
+		"run emmc_erase; " \
+		"if test ${active_root} = root2; then " \
+			"echo Active root is partition 6 (root2); " \
+			"setenv mmcpart 6; " \
+		"else " \
+			"echo Active root is partition 5 (root1); " \
+			"setenv mmcpart 5; " \
+		"fi; " \
+		"setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0"
+#endif /* #ifndef CONFIG_SPL_BUILD */
+
+#if defined CONFIG_SHC_NETBOOT
+/* Network Boot */
+# define CONFIG_BOOTCOMMAND \
+	"run fusecmd; " \
+	"if run netboot; then " \
+		"echo Booting from network; " \
+	"else " \
+		"echo ERROR: Cannot boot from network!; " \
+		"panic; " \
+	"fi; "
+
+#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */
+/* SD-Card Boot */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 0; mmc rescan; then " \
+		"run sd_setup; " \
+	"else " \
+		"echo ERROR: SD/MMC-Card not detected!; " \
+		"panic; " \
+	"fi; " \
+	"if run loaduimage; then " \
+		"echo Bootable SD/MMC-Card inserted, booting from it!; " \
+		"run mmcboot; " \
+	"else " \
+		"echo ERROR: Unable to load uImage from SD/MMC-Card!; " \
+		"panic; " \
+	"fi; "
+
+#elif defined CONFIG_SHC_ICT
+/* ICT adapter boots only u-boot and does HW partitioning */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 0; mmc rescan; then " \
+		"run sd_setup; " \
+	"else " \
+		"echo ERROR: SD/MMC-Card not detected!; " \
+		"panic; " \
+	"fi; " \
+	"run fusecmd; "
+
+#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */
+/* Regular Boot from internal eMMC */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 1; mmc rescan; then " \
+		"run emmc_setup; " \
+	"else " \
+		"echo ERROR: eMMC device not detected!; " \
+		"panic; " \
+	"fi; " \
+	"if run loaduimage; then " \
+		"run mmcboot; " \
+	"else " \
+		"echo ERROR Unable to load uImage from eMMC!; " \
+		"echo Performing Rollback!; " \
+		"setenv _active_ ${active_root}; " \
+		"setenv _inactive_ ${inactive_root}; " \
+		"setenv active_root ${_inactive_}; " \
+		"setenv inactive_root ${_active_}; " \
+		"saveenv; " \
+		"reset; " \
+	"fi; "
+
+#endif /* Regular Boot */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_CONS_INDEX               1
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+#endif
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0
+#define CONFIG_PHY_SMSC
+
+/* I2C configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		1
+
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#if defined CONFIG_SHC_NETBOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_MMC
+#endif
+#endif
+#endif	/* ! __CONFIG_AM335X_SHC_H */
-- 
cgit v0.10.2


From 3c5d51fffc92417b38a2c94f4253e9a8a04100b8 Mon Sep 17 00:00:00 2001
From: Samuel Egli <samuel.egli@siemens.com>
Date: Tue, 7 Jun 2016 08:55:39 +0200
Subject: siemens,am33x: add ubi fastmap support

From: Samuel Egli <samuel.egli@siemens.com>

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index dfc928d..ae26dad 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -288,6 +288,8 @@
 #define CONFIG_LZO
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT      1
 #endif
 
 /* Commen environment */
-- 
cgit v0.10.2


From cddfc97d1fc892353d6616cd4287c34c454941e6 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:55:40 +0200
Subject: ubi: add new ubi command "ubi detach"

simple detachs ubi from the mtd partition.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/cmd/ubi.c b/cmd/ubi.c
index 753a4db..4a92d84 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -443,14 +443,8 @@ static int ubi_dev_scan(struct mtd_info *info, char *ubidev,
 	return 0;
 }
 
-int ubi_part(char *part_name, const char *vid_header_offset)
+int ubi_detach(void)
 {
-	int err = 0;
-	char mtd_dev[16];
-	struct mtd_device *dev;
-	struct part_info *part;
-	u8 pnum;
-
 	if (mtdparts_init() != 0) {
 		printf("Error initializing mtdparts!\n");
 		return 1;
@@ -466,17 +460,28 @@ int ubi_part(char *part_name, const char *vid_header_offset)
 		cmd_ubifs_umount();
 #endif
 
-	/* todo: get dev number for NAND... */
-	ubi_dev.nr = 0;
-
 	/*
 	 * Call ubi_exit() before re-initializing the UBI subsystem
 	 */
 	if (ubi_initialized) {
 		ubi_exit();
 		del_mtd_partitions(ubi_dev.mtd_info);
+		ubi_initialized = 0;
 	}
 
+	ubi_dev.selected = 0;
+	return 0;
+}
+
+int ubi_part(char *part_name, const char *vid_header_offset)
+{
+	int err = 0;
+	char mtd_dev[16];
+	struct mtd_device *dev;
+	struct part_info *part;
+	u8 pnum;
+
+	ubi_detach();
 	/*
 	 * Search the mtd device number where this partition
 	 * is located
@@ -517,6 +522,15 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
+
+	if (strcmp(argv[1], "detach") == 0) {
+		if (argc < 2)
+			return CMD_RET_USAGE;
+
+		return ubi_detach();
+	}
+
+
 	if (strcmp(argv[1], "part") == 0) {
 		const char *vid_header_offset = NULL;
 
@@ -661,7 +675,9 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	ubi, 6, 1, do_ubi,
 	"ubi commands",
-	"part [part] [offset]\n"
+	"detach"
+		" - detach ubi from a mtd partition\n"
+	"ubi part [part] [offset]\n"
 		" - Show or set current partition (with optional VID"
 		" header offset)\n"
 	"ubi info [l[ayout]]"
-- 
cgit v0.10.2


From 5d29e27eb93229f27d2c88d5538ad781c144c852 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:55:41 +0200
Subject: nand: add nand mtd concat support

add for nand devices mtd concat support. Generic MTD concat
support is already ported to mainline, and used in the cfi_mtd
driver. This patch adds it similiar for nand devices.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index f449316..0551241 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <nand.h>
 #include <errno.h>
+#include <linux/mtd/concat.h>
 
 #ifndef CONFIG_SYS_NAND_BASE_LIST
 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
@@ -92,6 +93,44 @@ static void nand_init_chip(int i)
 }
 #endif
 
+#ifdef CONFIG_MTD_CONCAT
+static void create_mtd_concat(void)
+{
+	struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE];
+	int nand_devices_found = 0;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
+		if (nand_info[i] != NULL) {
+			nand_info_list[nand_devices_found] = nand_info[i];
+			nand_devices_found++;
+		}
+	}
+	if (nand_devices_found > 1) {
+		struct mtd_info *mtd;
+		char c_mtd_name[16];
+
+		/*
+		 * We detected multiple devices. Concatenate them together.
+		 */
+		sprintf(c_mtd_name, "nand%d", nand_devices_found);
+		mtd = mtd_concat_create(nand_info_list, nand_devices_found,
+					c_mtd_name);
+
+		if (mtd == NULL)
+			return;
+
+		nand_register(nand_devices_found, mtd);
+	}
+
+	return;
+}
+#else
+static void create_mtd_concat(void)
+{
+}
+#endif
+
 void nand_init(void)
 {
 #ifdef CONFIG_SYS_NAND_SELF_INIT
@@ -112,4 +151,6 @@ void nand_init(void)
 	board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]),
 				 nand_curr_device);
 #endif
+
+	create_mtd_concat();
 }
-- 
cgit v0.10.2


From 3a504d9639a2cef276a6e9e31cee11584c885639 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:55:42 +0200
Subject: mtd: nand: omap: allow to switch to BCH16

support in omap_nand_switch_ecc() also an eccstrength
from 16.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 0c44ea5..5f55977 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -280,6 +280,8 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg
 				omap_nand_switch_ecc(1, 1);
 			else if (strncmp(argv[2], "bch8", 4) == 0)
 				omap_nand_switch_ecc(1, 8);
+			else if (strncmp(argv[2], "bch16", 5) == 0)
+				omap_nand_switch_ecc(1, 16);
 			else
 				goto usage;
 		}
@@ -308,8 +310,8 @@ usage:
 U_BOOT_CMD(
 	nandecc, 3, 1,	do_switch_ecc,
 	"switch OMAP3 NAND ECC calculation algorithm",
-	"hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
-	" 8-bit BCH\n"
+	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
+	" and 8-bit/16-bit BCH\n"
 	"                           ecc calculation (second parameter may"
 	" be omitted).\n"
 	"nandecc sw               - Switch to NAND software ecc algorithm."
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 37c4341..67f293d 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -917,6 +917,10 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 			err = omap_select_ecc_scheme(nand,
 					OMAP_ECC_BCH8_CODE_HW,
 					mtd->writesize, mtd->oobsize);
+		} else if (eccstrength == 16) {
+			err = omap_select_ecc_scheme(nand,
+					OMAP_ECC_BCH16_CODE_HW,
+					mtd->writesize, mtd->oobsize);
 		} else {
 			printf("nand: error: unsupported ECC scheme\n");
 			return -EINVAL;
-- 
cgit v0.10.2


From 02b11f11993bc99c0ace4e750ba03f347502ebe9 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:55:43 +0200
Subject: am335x, dxr2: get ECC sType from I2C eeprom

read the ECC Type field from the i2c eeprom, instead
configuring it static in the U-Boot binary.

see RM:
Table 26-17. NAND Geometry Information on I2C EEPROM

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 988c12a..41bdef0 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -105,6 +105,40 @@ static void print_chip_data(void)
 }
 #endif /* CONFIG_SPL_BUILD */
 
+#define AM335X_NAND_ECC_MASK 0x0f
+#define AM335X_NAND_ECC_TYPE_16 0x02
+
+static int ecc_type;
+
+struct am335x_nand_geometry {
+	u32 magic;
+	u8 nand_geo_addr;
+	u8 nand_geo_page;
+	u8 nand_bus;
+};
+
+static int draco_read_nand_geometry(void)
+{
+	struct am335x_nand_geometry geo;
+
+	/* Read NAND geometry */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+		     (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
+		printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
+		return -EIO;
+	}
+	if (geo.magic != 0xa657b310) {
+		printf("%s: bad magic: %x\n", __func__, geo.magic);
+		return -EFAULT;
+	}
+	if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
+		ecc_type = 16;
+	else
+		ecc_type = 8;
+
+	return 0;
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -147,6 +181,8 @@ static int read_eeprom(void)
 		printf("Warning: No chip data in eeprom\n");
 
 	print_ddr3_timings();
+
+	return draco_read_nand_geometry();
 #endif
 	return 0;
 }
@@ -207,7 +243,14 @@ static void spl_siemens_board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-	omap_nand_switch_ecc(1, 8);
+	int ret;
+
+	ret = draco_read_nand_geometry();
+	if (ret != 0)
+		return ret;
+
+	nand_curr_device = 0;
+	omap_nand_switch_ecc(1, ecc_type);
 #ifdef CONFIG_FACTORYSET
 	/* Set ASN in environment*/
 	if (factory_dat.asn[0] != 0) {
-- 
cgit v0.10.2


From 9ae63f46a387573236372b937ada34daa55b893d Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:55:44 +0200
Subject: dfu, nand, ubi: fix erasing after write finish

writting to ubi nand partitions need after write ends an erase
of the remaining sectors. This fail, if dfu write size was not
a multiple of erasesize, example log:

Failure erase: -1

Fix this error.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index ab782be..9fb874c 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -139,6 +139,7 @@ static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf,
 static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 {
 	int ret = 0;
+	u64 off;
 
 	/* in case of ubi partition, erase rest of the partition */
 	if (dfu->data.nand.ubi) {
@@ -155,7 +156,16 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 		mtd = nand_info[nand_curr_device];
 
 		memset(&opts, 0, sizeof(opts));
-		opts.offset = dfu->data.nand.start + dfu->offset +
+		off = dfu->offset;
+		if ((off & (mtd->erasesize - 1)) != 0) {
+			/*
+			 * last write ended with unaligned length
+			 * sector is erased, jump to next
+			 */
+			off = off & ~((mtd->erasesize - 1));
+			off += mtd->erasesize;
+		}
+		opts.offset = dfu->data.nand.start + off +
 				dfu->bad_skip;
 		opts.length = dfu->data.nand.start +
 				dfu->data.nand.size - opts.offset;
-- 
cgit v0.10.2


From 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Tue, 7 Jun 2016 08:55:45 +0200
Subject: siemens,am33x: add draco etamin board

In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.

Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Move BOOTDELAY into defconfig, just always be 3 now]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 26ccf62..e75c4c0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -361,6 +361,11 @@ config TARGET_RASTABAN
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_ETAMIN
+        bool "Support etamin"
+        select CPU_V7
+        select SUPPORT_SPL
+
 config TARGET_PXM2
 	bool "Support pxm2"
 	select CPU_V7
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index c127f6c..9cafcea 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -83,8 +83,12 @@ int board_init(void)
 #ifdef CONFIG_FACTORYSET
 	factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
 #endif
+
 	gpmc_init();
 
+#ifdef CONFIG_NAND_CS_INIT
+	board_nand_cs_init();
+#endif
 #ifdef CONFIG_VIDEO
 	board_video_init();
 #endif
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 819d187..a699c7d 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -45,3 +45,19 @@ config SYS_CONFIG_NAME
 	default "rastaban"
 
 endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+        default "draco"
+
+config SYS_VENDOR
+        default "siemens"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "etamin"
+
+endif
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index 484dd73..e9107f0 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -4,6 +4,7 @@ S:	Maintained
 F:	board/siemens/draco/
 F:	include/configs/draco.h
 F:	configs/draco_defconfig
+F:	configs/etamin_defconfig
 F:	include/configs/thuban.h
 F:	configs/thuban_defconfig
 F:	include/configs/rastaban.h
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 41bdef0..d8869a0 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -24,6 +24,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
@@ -33,6 +34,7 @@
 #include <watchdog.h>
 #include "board.h"
 #include "../common/factoryset.h"
+#include <nand.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
 
 #if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
 /* Default@303MHz-i0 */
 const struct ddr3_data ddr3_default = {
 	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
@@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = {
 	"default name @303MHz           \0",
 	"default marking                \0",
 };
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+	0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
+	0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+	0x0000093B, 0x0000018A,
+	"test-etamin                    \0",
+	"generic-8Gbit                  \0",
+};
+#endif
 #elif DDR_PLL_FREQ == 400
 /* Default@400MHz-i0 */
 const struct ddr3_data ddr3_default = {
@@ -210,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
 	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 		settings.ddr3.emif_ddr_phy_ctlr_1;
 	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+	draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
 	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 
 	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
@@ -251,6 +265,10 @@ int board_late_init(void)
 
 	nand_curr_device = 0;
 	omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+	nand_curr_device = 1;
+	omap_nand_switch_ecc(1, ecc_type);
+#endif
 #ifdef CONFIG_FACTORYSET
 	/* Set ASN in environment*/
 	if (factory_dat.asn[0] != 0) {
@@ -326,7 +344,7 @@ int board_eth_init(bd_t *bis)
 }
 
 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
-			   char *const argv[])
+			  char *const argv[])
 {
 	/* Reset SMSC LAN9303 switch for default configuration */
 	gpio_request(GPIO_LAN9303_NRST, "nRST");
@@ -346,4 +364,23 @@ U_BOOT_CMD(
 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 
+#ifdef CONFIG_NAND_CS_INIT
+/* GPMC definitions for second nand cs1 */
+static const u32 gpmc_nand_config[] = {
+	ETAMIN_NAND_GPMC_CONFIG1,
+	ETAMIN_NAND_GPMC_CONFIG2,
+	ETAMIN_NAND_GPMC_CONFIG3,
+	ETAMIN_NAND_GPMC_CONFIG4,
+	ETAMIN_NAND_GPMC_CONFIG5,
+	ETAMIN_NAND_GPMC_CONFIG6,
+	/*CONFIG7- computed as params */
+};
+
+static void board_nand_cs_init(void)
+{
+	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
+			      0x18000000, GPMC_SIZE_16M);
+}
+#endif
+
 #include "../common/board.c"
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index dbcc80b..38a484e 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
 	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
 	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN},    /* NAND_CS1 */
 	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
 	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
 	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
@@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = {
 	{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y3 GPIO2_28*/
 	{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y7 GPIO2_27*/
 	/* Triacs initial HW Rev */
-	{OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_30 Y0 */
 	{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_28 Y1 */
 	{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_31 Y2 */
 	{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_11 Y3 */
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
new file mode 100644
index 0000000..6c747df
--- /dev/null
+++ b/configs/etamin_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_TARGET_ETAMIN=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 5d866c4..889178c 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -73,6 +73,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=draco\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
new file mode 100644
index 0000000..4919cfe
--- /dev/null
+++ b/include/configs/etamin.h
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ETAMIN_H
+#define __CONFIG_ETAMIN_H
+
+#include "siemens-am33x-common.h"
+/* NAND specific changes for etamin due to different page size */
+#undef CONFIG_SYS_NAND_PAGE_SIZE
+#undef CONFIG_SYS_NAND_OOBSIZE
+#undef CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_SYS_NAND_ECCPOS
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#undef CONFIG_SYS_ENV_SECT_SIZE
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_NAND_OMAP_ECCSCHEME
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+
+#define CONFIG_ENV_OFFSET       0x980000
+#define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
+#define CONFIG_SYS_NAND_PAGE_SIZE       4096
+#define CONFIG_SYS_NAND_OOBSIZE         224
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+
+#undef CONFIG_SYS_NAND_ECCSIZE
+#undef CONFIG_SYS_NAND_ECCBYTES
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 26
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000
+
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+
+#undef CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_MAX_NAND_DEVICE      3
+#define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
+#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
+					CONFIG_SYS_NAND_BASE2}
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_MPUCLK	300
+#define DDR_PLL_FREQ	303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+/* FWD Button = 27
+ * SRV Button = 87 */
+#define BOARD_DFU_BUTTON_GPIO	27
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+/* In dfu mode keep led1 on */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=27\0" \
+	"button_dfu1=87\0" \
+	"led0=3,0,1\0" \
+	"led1=4,0,0\0" \
+	"led2=5,0,1\0" \
+	"led3=87,0,1\0" \
+	"led4=60,0,1\0" \
+	"led5=63,0,1\0"
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* use both define to compile a SPL compliance test  */
+/*
+#define CONFIG_SPL_CMT
+#define CONFIG_SPL_CMT_DEBUG
+*/
+
+/* nedded by compliance test in read mode */
+#if defined(CONFIG_SPL_CMT)
+#define CONFIG_SYS_DCACHE_OFF
+#endif
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND	0xB80000
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE		(4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+
+#define CONFIG_DFU_MTD
+#undef COMMON_ENV_DFU_ARGS
+#define COMMON_ENV_DFU_ARGS	"dfu_args=run bootargs_defaults;" \
+				"setenv bootargs ${bootargs};" \
+				"mtdparts default;" \
+				"draco_led 1;" \
+				"dfu 0 mtd 0;" \
+				"draco_led 0;\0" \
+
+#undef DFU_ALT_INFO_NAND_V2
+#define DFU_ALT_INFO_NAND_V2 \
+	"spl mtddev;" \
+	"spl.backup1 mtddev;" \
+	"spl.backup2 mtddev;" \
+	"spl.backup3 mtddev;" \
+	"u-boot mtddev;" \
+	"u-boot.env0 mtddev;" \
+	"u-boot.env1 mtddev;" \
+	"rootfs mtddevubi" \
+
+#undef MTDIDS_NAME_STR
+#define MTDIDS_NAME_STR		"omap2-nand_concat"
+#undef MTDIDS_DEFAULT
+#define MTDIDS_DEFAULT		"nand2=" MTDIDS_NAME_STR
+
+#undef MTDPARTS_DEFAULT_V2
+#define MTDPARTS_DEFAULT_V2     "mtdparts=" MTDIDS_NAME_STR ":" \
+				"512k(spl)," \
+				"512k(spl.backup1)," \
+				"512k(spl.backup2)," \
+				"512k(spl.backup3)," \
+				"7680k(u-boot)," \
+				"2048k(u-boot.env0)," \
+				"2048k(u-boot.env1)," \
+				"2048k(mtdoops)," \
+				"-(rootfs)"
+
+#undef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT	MTDPARTS_DEFAULT_V2
+
+#undef CONFIG_ENV_SETTINGS_NAND_V2
+#define CONFIG_ENV_SETTINGS_NAND_V2 \
+	"nand_active_ubi_vol=rootfs_a\0" \
+	"rootfs_name=rootfs\0" \
+	"kernel_name=uImage\0"\
+	"nand_root_fs_type=ubifs rootwait=1\0" \
+	"nand_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_a;" \
+		"fi;" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_b;" \
+		"fi;" \
+		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+		"ubi.mtd=rootfs,${ubi_off};" \
+		"setenv bootargs ${bootargs} " \
+		"root=${nand_root} noinitrd ${mtdparts} " \
+		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+		"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+		"=mtdoops\0" \
+	COMMON_ENV_DFU_ARGS \
+		"dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
+	COMMON_ENV_NAND_BOOT \
+		"ubi part rootfs ${ubi_off};" \
+		"ubifsmount ubi0:${nand_active_ubi_vol};" \
+		"ubifsload ${kloadaddr} boot/${kernel_name};" \
+		"ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	"nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	COMMON_ENV_NAND_CMDS
+
+#ifndef CONFIG_SPL_BUILD
+
+#define CONFIG_NAND_CS_INIT
+#define ETAMIN_NAND_GPMC_CONFIG1	0x00000800
+#define ETAMIN_NAND_GPMC_CONFIG2	0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG3	0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG4	0x16051807
+#define ETAMIN_NAND_GPMC_CONFIG5	0x00151e1e
+#define ETAMIN_NAND_GPMC_CONFIG6	0x16000f80
+#define CONFIG_MTD_CONCAT
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=etamin\0" \
+	"ubi_off=4096\0"\
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	CONFIG_ENV_SETTINGS_V2 \
+	CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_ETAMIN_H */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 794650a..990fd84 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -61,6 +61,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=pxm2\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x500000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index 6c8681a..55be46b 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -76,6 +76,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rastaban\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
diff --git a/include/configs/rut.h b/include/configs/rut.h
index b0dcbd8..aea8e21 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -56,6 +56,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rut\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x500000\0" \
 	"splashpos=m,m\0" \
 	"optargs=fixrtc --no-log consoleblank=0 \0" \
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index ae26dad..5969541 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -159,6 +159,7 @@
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)
@@ -421,7 +422,7 @@
 			"setenv nand_src_addr ${nand_src_addr_B};" \
 		"fi;" \
 		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
-		"ubi.mtd=9,2048;" \
+		"ubi.mtd=9,${ubi_off};" \
 		"setenv bootargs ${bootargs} " \
 		"root=${nand_root} noinitrd ${mtdparts} " \
 		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
@@ -513,7 +514,7 @@
 	COMMON_ENV_DFU_ARGS \
 		"dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
 	COMMON_ENV_NAND_BOOT \
-		"ubi part rootfs 2048;" \
+		"ubi part rootfs ${ubi_off};" \
 		"ubifsmount ubi0:${nand_active_ubi_vol};" \
 		"ubifsload ${kloadaddr} boot/${kernel_name};" \
 		"ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index a03f87c..25ac2cb 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -69,6 +69,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=thuban\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
-- 
cgit v0.10.2


From 1903bb91c4dde49a1a44bd6b769527165c8a4d34 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 2 Jun 2016 18:46:09 +0200
Subject: sunxi: Enable ALDO3 and ALDO4 in Wobo_i5_defconfig

These are used for the usb wifi and if we leave the enabling up to the
kernel, we get hit by the axp209 issues with enabling ldo3 or 4 post boot
and the systems hangs as soon as it is enabled.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index fc43cc5..17ed968 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -11,3 +11,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_AXP_ALDO4_VOLT=3300
-- 
cgit v0.10.2


From fd2aa39a619ce011414f6cb6efb0232136e300c7 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 5 Jun 2016 14:40:44 +0200
Subject: sunxi: Add INITIAL_USB_SCAN_DELAY to Mele_A1000G_quad_defconfig

The Mele_A1000G_quad has an onboard usb <-> sata conversion which needs
longer then the usb-spec allows to connect after getting power.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index b3f825e..2ac2596 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=120
+CONFIG_INITIAL_USB_SCAN_DELAY=2000
 CONFIG_USB1_VBUS_PIN="PC27"
 CONFIG_USB2_VBUS_PIN=""
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
-- 
cgit v0.10.2


From bca4c3c5fcb3d170308e621dadcc5555a1aca1b8 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 5 Jun 2016 16:53:04 +0200
Subject: sunxi: musb: Properly turn of musb controller before booting

Turn of the clock and assert the reset when musb_stop gets called, so that
the os gets the musb controller in a pristine state. This fixes a spurious
VBus error interrupt triggering as soon as the Linux musb driver loads.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 3081afc..c016a0b 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev)
 int musb_usb_remove(struct udevice *dev)
 {
 	struct musb_host_data *host = dev_get_priv(dev);
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
 	musb_stop(host->host);
 
+	sunxi_usb_phy_exit(0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From a95800e881a8df837f0c4121a2cd560a4c02bd2f Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 9 Jun 2016 13:09:51 +0100
Subject: MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 5f520c0..db81953 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 	if (start_addr == stop)
 		return;
 
-	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 }
-- 
cgit v0.10.2


From 4b7b0a0f0635c1d1e4a0ae2ed172530b5f78e74b Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 9 Jun 2016 13:09:52 +0100
Subject: MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex

For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 372286217f05 ("MIPS: Split I & D cache line size config")

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5c30ae9..21066f0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -253,7 +253,7 @@ config SYS_DCACHE_SIZE
 	  The total size of the L1 Dcache, if known at compile time.
 
 config SYS_DCACHE_LINE_SIZE
-	hex
+	int
 	default 0
 	help
 	  The size of L1 Dcache lines, if known at compile time.
-- 
cgit v0.10.2


From e19b9004575cacf1f64fff894621adafe0e7ea7f Mon Sep 17 00:00:00 2001
From: Purna Chandra Mandal <purna.mandal@microchip.com>
Date: Thu, 2 Jun 2016 14:26:08 +0530
Subject: spi: pic32_spi: add SPI master driver for PIC32 SoC.

This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controlling respective pin as gpio ('cs-gpios' property in dt node)
and uses PIO mode for SPI transaction. It is configurable based
on driver-model only.

Cc: Jagan Teki <jteki@openedev.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b7fd8e5..aca385d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -75,6 +75,14 @@ config ICH_SPI
 	  access the SPI NOR flash on platforms embedding this Intel
 	  ICH IP core.
 
+config PIC32_SPI
+	bool "Microchip PIC32 SPI driver"
+	depends on MACH_PIC32
+	help
+	  Enable the Microchip PIC32 SPI driver. This driver can be used
+	  to access the SPI NOR flash, MMC-over-SPI on platforms based on
+	  Microchip PIC32 family devices.
+
 config ROCKCHIP_SPI
 	bool "Rockchip SPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7fb2926..b1d9e20 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c
new file mode 100644
index 0000000..25ca1f3
--- /dev/null
+++ b/drivers/spi/pic32_spi.c
@@ -0,0 +1,448 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Copyright (c) 2015, Microchip Technology Inc.
+ *      Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include <mach/pic32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 SPI controller registers */
+struct pic32_reg_spi {
+	struct pic32_reg_atomic ctrl;
+	struct pic32_reg_atomic status;
+	struct pic32_reg_atomic buf;
+	struct pic32_reg_atomic baud;
+	struct pic32_reg_atomic ctrl2;
+};
+
+/* Bit fields in SPI Control Register */
+#define PIC32_SPI_CTRL_MSTEN	BIT(5) /* Enable SPI Master */
+#define PIC32_SPI_CTRL_CKP	BIT(6) /* active low */
+#define PIC32_SPI_CTRL_CKE	BIT(8) /* Tx on falling edge */
+#define PIC32_SPI_CTRL_SMP	BIT(9) /* Rx at middle or end of tx */
+#define PIC32_SPI_CTRL_BPW_MASK	0x03   /* Bits per word */
+#define  PIC32_SPI_CTRL_BPW_8		0x0
+#define  PIC32_SPI_CTRL_BPW_16		0x1
+#define  PIC32_SPI_CTRL_BPW_32		0x2
+#define PIC32_SPI_CTRL_BPW_SHIFT	10
+#define PIC32_SPI_CTRL_ON	BIT(15) /* Macro enable */
+#define PIC32_SPI_CTRL_ENHBUF	BIT(16) /* Enable enhanced buffering */
+#define PIC32_SPI_CTRL_MCLKSEL	BIT(23) /* Select SPI Clock src */
+#define PIC32_SPI_CTRL_MSSEN	BIT(28) /* SPI macro will drive SS */
+#define PIC32_SPI_CTRL_FRMEN	BIT(31) /* Enable framing mode */
+
+/* Bit fields in SPI Status Register */
+#define PIC32_SPI_STAT_RX_OV		BIT(6) /* err, s/w needs to clear */
+#define PIC32_SPI_STAT_TF_LVL_MASK	0x1f
+#define PIC32_SPI_STAT_TF_LVL_SHIFT	16
+#define PIC32_SPI_STAT_RF_LVL_MASK	0x1f
+#define PIC32_SPI_STAT_RF_LVL_SHIFT	24
+
+/* Bit fields in SPI Baud Register */
+#define PIC32_SPI_BAUD_MASK	0x1ff
+
+struct pic32_spi_priv {
+	struct pic32_reg_spi	*regs;
+	u32			fifo_depth; /* FIFO depth in bytes */
+	u32			fifo_n_word; /* FIFO depth in words */
+	struct gpio_desc	cs_gpio;
+
+	/* Current SPI slave specific */
+	ulong			clk_rate;
+	u32			speed_hz; /* spi-clk rate */
+	int			mode;
+
+	/* Current message/transfer state */
+	const void		*tx;
+	const void		*tx_end;
+	const void		*rx;
+	const void		*rx_end;
+	u32			len;
+
+	/* SPI FiFo accessor */
+	void (*rx_fifo)(struct pic32_spi_priv *);
+	void (*tx_fifo)(struct pic32_spi_priv *);
+};
+
+static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
+{
+	writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
+}
+
+static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
+{
+	writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
+}
+
+static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
+{
+	u32 sr = readl(&priv->regs->status.raw);
+
+	return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
+}
+
+static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
+{
+	u32 sr = readl(&priv->regs->status.raw);
+
+	return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
+}
+
+/* Return the max entries we can fill into tx fifo */
+static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+	u32 tx_left, tx_room, rxtx_gap;
+
+	tx_left = (priv->tx_end - priv->tx) / n_bytes;
+	tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
+
+	rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
+	rxtx_gap /= n_bytes;
+	return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
+}
+
+/* Return the max entries we should read out of rx fifo */
+static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+	u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
+
+	return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
+}
+
+#define BUILD_SPI_FIFO_RW(__name, __type, __bwl)		\
+static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv)	\
+{								\
+	__type val;						\
+	u32 mx = pic32_rx_max(priv, sizeof(__type));		\
+								\
+	for (; mx; mx--) {					\
+		val = read##__bwl(&priv->regs->buf.raw);	\
+		if (priv->rx_end - priv->len)			\
+			*(__type *)(priv->rx) = val;		\
+		priv->rx += sizeof(__type);			\
+	}							\
+}								\
+								\
+static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv)	\
+{								\
+	__type val;						\
+	u32 mx = pic32_tx_max(priv, sizeof(__type));		\
+								\
+	for (; mx ; mx--) {					\
+		val = (__type) ~0U;				\
+		if (priv->tx_end - priv->len)			\
+			val =  *(__type *)(priv->tx);		\
+		write##__bwl(val, &priv->regs->buf.raw);	\
+		priv->tx += sizeof(__type);			\
+	}							\
+}
+BUILD_SPI_FIFO_RW(byte, u8, b);
+BUILD_SPI_FIFO_RW(word, u16, w);
+BUILD_SPI_FIFO_RW(dword, u32, l);
+
+static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
+				   unsigned int wordlen)
+{
+	u32 bits_per_word;
+	u32 val;
+
+	switch (wordlen) {
+	case 8:
+		priv->rx_fifo = pic32_spi_rx_byte;
+		priv->tx_fifo = pic32_spi_tx_byte;
+		bits_per_word = PIC32_SPI_CTRL_BPW_8;
+		break;
+	case 16:
+		priv->rx_fifo = pic32_spi_rx_word;
+		priv->tx_fifo = pic32_spi_tx_word;
+		bits_per_word = PIC32_SPI_CTRL_BPW_16;
+		break;
+	case 32:
+		priv->rx_fifo = pic32_spi_rx_dword;
+		priv->tx_fifo = pic32_spi_tx_dword;
+		bits_per_word = PIC32_SPI_CTRL_BPW_32;
+		break;
+	default:
+		printf("pic32-spi: unsupported wordlen\n");
+		return -EINVAL;
+	}
+
+	/* set bits-per-word */
+	val = readl(&priv->regs->ctrl.raw);
+	val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
+	val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
+	writel(val, &priv->regs->ctrl.raw);
+
+	/* calculate maximum number of words fifo can hold */
+	priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
+
+	return 0;
+}
+
+static int pic32_spi_claim_bus(struct udevice *slave)
+{
+	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+	/* enable chip */
+	pic32_spi_enable(priv);
+
+	return 0;
+}
+
+static int pic32_spi_release_bus(struct udevice *slave)
+{
+	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+	/* disable chip */
+	pic32_spi_disable(priv);
+
+	return 0;
+}
+
+static void spi_cs_activate(struct pic32_spi_priv *priv)
+{
+	if (!dm_gpio_is_valid(&priv->cs_gpio))
+		return;
+
+	dm_gpio_set_value(&priv->cs_gpio, 1);
+}
+
+static void spi_cs_deactivate(struct pic32_spi_priv *priv)
+{
+	if (!dm_gpio_is_valid(&priv->cs_gpio))
+		return;
+
+	dm_gpio_set_value(&priv->cs_gpio, 0);
+}
+
+static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
+			  const void *tx_buf, void *rx_buf,
+			  unsigned long flags)
+{
+	struct dm_spi_slave_platdata *slave_plat;
+	struct udevice *bus = slave->parent;
+	struct pic32_spi_priv *priv;
+	int len = bitlen / 8;
+	int ret = 0;
+	ulong tbase;
+
+	priv = dev_get_priv(bus);
+	slave_plat = dev_get_parent_platdata(slave);
+
+	debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
+	      bus->seq, slave_plat->cs, flags);
+	debug("msg tx %p, rx %p submitted of %d byte(s)\n",
+	      tx_buf, rx_buf, len);
+
+	/* assert cs */
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(priv);
+
+	/* set current transfer information */
+	priv->tx = tx_buf;
+	priv->rx = rx_buf;
+	priv->tx_end = priv->tx + len;
+	priv->rx_end = priv->rx + len;
+	priv->len = len;
+
+	/* transact by polling */
+	tbase = get_timer(0);
+	for (;;) {
+		priv->tx_fifo(priv);
+		priv->rx_fifo(priv);
+
+		/* received sufficient data */
+		if (priv->rx >= priv->rx_end) {
+			ret = 0;
+			break;
+		}
+
+		if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
+			printf("pic32_spi: error, xfer timedout.\n");
+			flags |= SPI_XFER_END;
+			ret = -ETIMEDOUT;
+			break;
+		}
+	}
+
+	/* deassert cs */
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(priv);
+
+	return ret;
+}
+
+static int pic32_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct pic32_spi_priv *priv = dev_get_priv(bus);
+	u32 div;
+
+	debug("%s: %s, speed %u\n", __func__, bus->name, speed);
+
+	/* div = [clk_in / (2 * spi_clk)] - 1 */
+	div = (priv->clk_rate / 2 / speed) - 1;
+	div &= PIC32_SPI_BAUD_MASK;
+	writel(div, &priv->regs->baud.raw);
+
+	priv->speed_hz = speed;
+
+	return 0;
+}
+
+static int pic32_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct pic32_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+
+	debug("%s: %s, mode %d\n", __func__, bus->name, mode);
+
+	/* set spi-clk mode */
+	val = readl(&priv->regs->ctrl.raw);
+	/* HIGH when idle */
+	if (mode & SPI_CPOL)
+		val |= PIC32_SPI_CTRL_CKP;
+	else
+		val &= ~PIC32_SPI_CTRL_CKP;
+
+	/* TX at idle-to-active clk transition */
+	if (mode & SPI_CPHA)
+		val &= ~PIC32_SPI_CTRL_CKE;
+	else
+		val |= PIC32_SPI_CTRL_CKE;
+
+	/* RX at end of tx */
+	val |= PIC32_SPI_CTRL_SMP;
+	writel(val, &priv->regs->ctrl.raw);
+
+	priv->mode = mode;
+
+	return 0;
+}
+
+static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
+{
+	struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+	return pic32_spi_set_word_size(priv, wordlen);
+}
+
+static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
+{
+	u32 val;
+
+	/* disable module */
+	pic32_spi_disable(priv);
+
+	val = readl(&priv->regs->ctrl);
+
+	/* enable enhanced fifo of 128bit deep */
+	val |= PIC32_SPI_CTRL_ENHBUF;
+	priv->fifo_depth = 16;
+
+	/* disable framing mode */
+	val &= ~PIC32_SPI_CTRL_FRMEN;
+
+	/* enable master mode */
+	val |= PIC32_SPI_CTRL_MSTEN;
+
+	/* select clk source */
+	val &= ~PIC32_SPI_CTRL_MCLKSEL;
+
+	/* set manual /CS mode */
+	val &= ~PIC32_SPI_CTRL_MSSEN;
+
+	writel(val, &priv->regs->ctrl);
+
+	/* clear rx overflow indicator */
+	writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
+}
+
+static int pic32_spi_probe(struct udevice *bus)
+{
+	struct pic32_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
+	struct udevice *clkdev;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	int ret;
+
+	debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
+	addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = ioremap(addr, size);
+	if (!priv->regs)
+		return -EINVAL;
+
+	dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+					"spi-max-frequency", 250000000);
+	/* get clock rate */
+	ret = clk_get_by_index(bus, 0, &clkdev);
+	if (ret < 0) {
+		printf("pic32-spi: error, clk not found\n");
+		return ret;
+	}
+	priv->clk_rate = clk_get_periph_rate(clkdev, ret);
+
+	/* initialize HW */
+	pic32_spi_hw_init(priv);
+
+	/* set word len */
+	pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
+
+	/* PIC32 SPI controller can automatically drive /CS during transfer
+	 * depending on fifo fill-level. /CS will stay asserted as long as
+	 * TX fifo is non-empty, else will be deasserted confirming completion
+	 * of the ongoing transfer. To avoid this sort of error we will drive
+	 * /CS manually by toggling cs-gpio pins.
+	 */
+	ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
+					 "cs-gpios", 0,
+					 &priv->cs_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		printf("pic32-spi: error, cs-gpios not found\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct dm_spi_ops pic32_spi_ops = {
+	.claim_bus	= pic32_spi_claim_bus,
+	.release_bus	= pic32_spi_release_bus,
+	.xfer		= pic32_spi_xfer,
+	.set_speed	= pic32_spi_set_speed,
+	.set_mode	= pic32_spi_set_mode,
+	.set_wordlen	= pic32_spi_set_wordlen,
+};
+
+static const struct udevice_id pic32_spi_ids[] = {
+	{ .compatible = "microchip,pic32mzda-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(pic32_spi) = {
+	.name		= "pic32_spi",
+	.id		= UCLASS_SPI,
+	.of_match	= pic32_spi_ids,
+	.ops		= &pic32_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
+	.probe		= pic32_spi_probe,
+};
-- 
cgit v0.10.2


From 5bc88cc2be3a962005b6e5768e06ca8f6ffcb88d Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Tue, 31 May 2016 01:48:05 +0300
Subject: sunxi: Downclock AHB1 to 100MHz on Allwinner A64

Currently the AHB1 clock speed is configured as 200MHz by
the SPL, but this causes a subtle and hard to reproduce data
corruption in SRAM C (for example, this can't be easily
detected with a trivial memset/memcmp test).

For what it's worth, the Allwinner's BSP configures AHB1
as 200MHz, as can be verified by running the devmem2 tool
in the system running the Allwinner's kernel 3.10.x:

   0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811
   0x1C20054: AHB1_APB1_CFG_REG    = 0x3180
   0x1C20058: APB2_CFG_REG         = 0x1000000
   0x1C2005C: AHB2_CFG_REG         = 0x1

However the FEL mode uses more conservative settings (100MHz
for AHB1):

   0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811
   0x1C20054: AHB1_APB1_CFG_REG    = 0x3190
   0x1C20058: APB2_CFG_REG         = 0x1000000
   0x1C2005C: AHB2_CFG_REG         = 0x0

It is yet to be confirmed whether faster AHB1/AHB2 clock settings
can be used safely if we initialize the AXP803 PMIC instead of
using reset defaults. But in order to resolve the data corruption
problem right now, it's best to downclock AHB1 to a safe level.

Note that this issue only affects the SPL, which is not fully
supported on Allwinner A64 yet and it should not affect the boot0
usage (unless somebody can confirm SRAM C corruption with the
boot0 too).

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index f2990db..c2e72f5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -222,7 +222,12 @@ struct sunxi_ccm_reg {
 #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
 #define CCM_PLL11_CTRL_EN		(0x1 << 31)
 
+#if defined(CONFIG_MACH_SUN50I)
+/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
+#define AHB1_ABP1_DIV_DEFAULT		0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
+#else
 #define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#endif
 
 #define AXI_GATE_OFFSET_DRAM		0
 
-- 
cgit v0.10.2


From 1a83fb4a17d959d7b037999ab7ed7e62429abe34 Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Tue, 31 May 2016 01:48:06 +0300
Subject: sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80

Since the SRAM C corruption issue is now resolved on Allwinner
A64, it is possible to move the stack top to the address 0x1A000
on both A64 and A80. The boot ROM can load SPL binaries with
up to 32 KiB size on A64 (the 24 KiB SPL size limitation only
affects A10/A20), and this patch also ensures the availability
of 8 KiB stack.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b33cfb8..94275a7 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -100,7 +100,7 @@
  * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x10000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x08000	/* FIXME: 40 KiB ? */
+#define CONFIG_SYS_INIT_RAM_SIZE	0xA000	/* 40 KiB */
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
@@ -213,8 +213,7 @@
 #define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
 
 #if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
-/* FIXME: 40 KiB instead of 32 KiB ? */
-#define LOW_LEVEL_SRAM_STACK		0x00018000
+#define LOW_LEVEL_SRAM_STACK		0x0001A000
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 #else
 /* end of 32 KiB in sram */
-- 
cgit v0.10.2


From a758177f9b9a567df2e8e6e57ac905ada24d8d9c Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Wed, 8 Jun 2016 10:31:42 +0800
Subject: armv8/ls2080a: configure PMU's PCTBENR to enable WDT

The SP805-WDT module on LS2080A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 9a5a6b5..297687d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -636,6 +636,9 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
 	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 
@@ -650,6 +653,15 @@ int timer_init(void)
 	out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+	/*
+	 * In certain Layerscape SoCs, the clock for each core's
+	 * has an enable bit in the PMU Physical Core Time Base Enable
+	 * Register (PCTBENR), which allows the watchdog to operate.
+	 */
+	setbits_le32(pctbenr, 0xff);
+#endif
+
 	/* Enable clock for timer
 	 * This is a global setting.
 	 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..c6b9f13 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-- 
cgit v0.10.2


From 30677deefdf57a8a2d12a766117ea861ca38f52c Mon Sep 17 00:00:00 2001
From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Date: Wed, 20 Jan 2016 12:29:03 +0530
Subject: board: ls2080a: Add "mcinitcmd" env for MC & DPL deployment

Environment variable mcinitcmd is defined to initiate MC and DPL
deployment from the location where it is stored (NOR, NAND, SD, SATA,
USB) during booting. If this variable is not defined then macro
MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will
not be applied during U-boot booting.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index f9323c1..da5e052 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -121,6 +121,35 @@ mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
 mcmemsize:	MC DRAM block size. If this variable is not defined, the value
 		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
+mcinitcmd:	This environment variable is defined to initiate MC and DPL deployment
+		from the location where it is stored(NOR, NAND, SD, SATA, USB)during
+		u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
+		will be null and MC will not be booted and DPL will not be applied
+		during U-boot booting.However the MC, DPC and DPL can be applied from
+		console independently.
+		The variable needs to be set from the console once and then on
+		rebooting the parameters set in the varible will automatically be
+		executed. The commmand is demostrated taking an example of mc boot
+		using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
+
+		cp.b 0xa0000000 0x580300000 $filesize
+		cp.b 0x80000000 0x580800000 $filesize
+		cp.b 0x90000000 0x580700000 $filesize
+
+		setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
+
+		If only linux is to be booted then the mcinitcmd environment should be set as
+
+		setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+
+		Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
+		MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
+		and 0x580700000 are addresses in NOR where these are copied. It is to be
+		noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+		can be replaced with the addresses of DDR to
+		which these will be copied in case of these binaries being stored in other
+		devices like SATA, USB, NAND, SD etc.
+
 Booting from NAND
 -------------------
 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 33ad7dc..95ff68b 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -20,6 +20,7 @@
 
 #include "ls2080aqds_qixis.h"
 
+#define MC_BOOT_ENV_VAR "mcinitcmd"
 
 #ifdef CONFIG_FSL_MC_ENET
  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
@@ -714,6 +715,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 int board_eth_init(bd_t *bis)
 {
 	int error;
+	char *mc_boot_env_var;
 #ifdef CONFIG_FSL_MC_ENET
 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -781,6 +783,9 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+	mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+	if (mc_boot_env_var)
+		run_command_list(mc_boot_env_var, -1, 0);
 	error = cpu_eth_init(bis);
 
 	if (hwconfig_f("xqsgmii", env_hwconfig)) {
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 58ea746..799799c 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -20,9 +20,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MC_BOOT_ENV_VAR "mcinitcmd"
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
+	char *mc_boot_env_var;
 	int i, interface;
 	struct memac_mdio_info mdio_info;
 	struct mii_dev *dev;
@@ -89,6 +91,9 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+	mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+	if (mc_boot_env_var)
+		run_command_list(mc_boot_env_var, -1, 0);
 	cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
 
-- 
cgit v0.10.2


From 9d10c2d3fe6852501a4c43853fe3d2469903a2bb Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:51 +0800
Subject: drivers: i2c: mxc: Add early init

Add early i2c init function with conservative divider when the exact
clock rate is not available.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8..16b1aba 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
 {
 }
 
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
 /*
  * i2c_init_all():
  *
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21..f340208 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX_I2C_REGSHIFT	2
 #define VF610_I2C_REGSHIFT	0
+
+#define I2C_EARLY_INIT_INDEX		0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE	CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE	0x7e
+#endif
+
 /* Register index */
 #define IADR	0
 #define IFDR	1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
 }
 
 /*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+	ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+	bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+					& I2C_QUIRK_FLAG ? true : false;
+	int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+	/* Set I2C divider value */
+	writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+	/* Reset module */
+	writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+	writeb(0, base + (I2SR << reg_shift));
+	/* Enable I2C */
+	writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
  * Init I2C Bus
  */
 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/include/i2c.h b/include/i2c.h
index 1f5ae45..d500445 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -701,6 +701,9 @@ extern struct i2c_bus_hose	i2c_bus[];
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
  */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
 void i2c_init(int speed, int slaveaddr);
 void i2c_init_board(void);
 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-- 
cgit v0.10.2


From 916d9f099edcb2a020ec3f291f0fa0e6fab0f9a5 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:52 +0800
Subject: armv8: ls2080aqds: Select QSPI CLK div via SCFG

QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index c6b9f13..f75bd39 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -140,6 +140,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
 #define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 897793d..b60206b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -26,6 +26,7 @@
 
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
+#define SCFG_QSPICLKCTRL_DIV_20	(5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
 
@@ -219,6 +220,10 @@ int board_init(void)
 int board_early_init_f(void)
 {
 	fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+	/* input clk: 1/2 platform clk, output: input/20 */
+	out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
 	return 0;
 }
 
-- 
cgit v0.10.2


From 82d13340e9d051f193d46596343aa692b0acd92c Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:53 +0800
Subject: configs: ls2080a_common: Remove duplicate NOR configs

The NOR flash related configure options appear in ls2080aqds.h and
ls2080ardb.h, and the two files both includ ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2bf524f..2314b44 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -138,13 +138,6 @@
 #define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
 
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
 #endif
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 7563aaf..7f245b5 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -30,6 +30,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
-- 
cgit v0.10.2


From 8c77ef85405dd319f0469d007630b548afb2d401 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:54 +0800
Subject: armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable

When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux. Enable I2C QIXIS access and I2C
early init to read the sysclk and ddrclk.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index b60206b..a07cd0a 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -219,6 +219,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch3_early_init_f();
 #ifdef CONFIG_FSL_QSPI
 	/* input clk: 1/2 platform clk, output: input/20 */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index b44066c..532a715 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
 #define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
 #define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
-- 
cgit v0.10.2


From b718d371571c0440c21ba0a4241a23b13959800b Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:55 +0800
Subject: configs: ls2080aqds: Enable QSPI flash support

Enable QSPI flash related configure options.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 532a715..b15acf3 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT      0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 #define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM		4
+#endif
+
 #endif
 
 /*
-- 
cgit v0.10.2


From 95ab851de0de317e07a843d23bfaeb89d94575f8 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:56 +0800
Subject: dts: ls2080aqds: Add QSPI dts node

Add QSPI controller and slave dts node for LS2080AQDS board.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts
index 547ec27..0a7f1ff 100644
--- a/arch/arm/dts/fsl-ls2080a-qds.dts
+++ b/arch/arm/dts/fsl-ls2080a-qds.dts
@@ -15,6 +15,7 @@
 	compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
 
 	aliases {
+		spi0 = &qspi;
 		spi1 = &dspi;
 	};
 };
@@ -51,3 +52,16 @@
 		reg = <2>;
 	};
 };
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fs256s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index a5c579c..68ed133 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -126,4 +126,14 @@
 		interrupts = <0 26 0x4>; /* Level high type */
 		num-cs = <6>;
 	};
+
+	qspi: quadspi@1550000 {
+		compatible = "fsl,vf610-qspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x20c0000 0x0 0x10000>,
+			<0x0 0x20000000 0x0 0x10000000>;
+		reg-names = "QuadSPI", "QuadSPI-memory";
+		num-cs = <4>;
+	};
 };
-- 
cgit v0.10.2


From 453418f2d2df33f370754582b7e21d2513e2ee28 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:57 +0800
Subject: armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f75bd39..8d12d6c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -129,6 +129,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
 #define DCFG_RCWSR13			0x130
 #define DCFG_RCWSR13_DSPI		(0 << 8)
+#define DCFG_RCWSR15			0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
 #define DCFG_DCSR_BASE		0X700100000ULL
 #define DCFG_DCSR_PORCR1		0x000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index a07cd0a..694b28b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -208,6 +208,15 @@ int board_init(void)
 	else
 		config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+		QIXIS_WRITE(brdcfg[9],
+			    (QIXIS_READ(brdcfg[9]) & 0xf8) |
+			     FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index b15acf3..9741be1 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -303,6 +303,12 @@ unsigned long get_board_ddr_clk(void);
 #define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM		4
 #endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI		0x1
 
 #endif
 
-- 
cgit v0.10.2


From 74cac00c95efaa06649529adcc3d1b6e9e8cefb7 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:58 +0800
Subject: configs: ls2080a: Increase load image len in NAND boot

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2314b44..cab3ba9 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -282,7 +282,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(640 * 1024)
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 9741be1..e634d25 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SPL_PAD_TO		0x20000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-- 
cgit v0.10.2


From 01de8304028275b2b7650b5f601e87ce63006e19 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:24:59 +0800
Subject: configs: ls2080aqds_nand_defconfig: Enable QSPI

The Freescale QSPI driver has been converted to Driver Model.
This patch enables FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 8c5b69d..dc16492 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -8,6 +8,14 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
@@ -19,6 +27,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-- 
cgit v0.10.2


From a646f6698173ef4ff34c414f91541b4b8f014de1 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@nxp.com>
Date: Wed, 8 Jun 2016 18:25:00 +0800
Subject: armv8: ls2080aqds: Enable QSPI boot support

This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 1cebe2f..df877dd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -122,6 +122,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+	  CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
 	/* For IFC Region #1, only the first 4MB is cache-enabled */
 	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
 	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -176,6 +178,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+	  CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
 	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 694b28b..477f556 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -81,6 +81,8 @@ int checkboard(void)
 		puts("PromJet\n");
 	else if (sw == 0x9)
 		puts("NAND\n");
+	else if (sw == 0xf)
+		puts("QSPI\n");
 	else if (sw == 0x15)
 		printf("IFCCard\n");
 	else
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
new file mode 100644
index 0000000..0850a68
--- /dev/null
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index cab3ba9..ebe1415 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -29,11 +29,13 @@
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE		0x80400000
 #else
 #define CONFIG_SYS_TEXT_BASE		0x30100000
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index e634d25..df1455b 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
 #define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_QSPI		0x0f
 #define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_RCW_SRC_NAND		0x107
+#define QIXIS_RCW_SRC_QSPI		0x62
 #define	QIXIS_RST_FORCE_MEM		0x01
 
 #define CONFIG_SYS_CSPR3_EXT	(0x0)
@@ -267,11 +269,19 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
 
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE		0x20010000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x2000
 #endif
+#endif
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-- 
cgit v0.10.2


From 8a1a7595cfbcb12d01a5c1f486ebfd50af90c34c Mon Sep 17 00:00:00 2001
From: George McCollister <george.mccollister@gmail.com>
Date: Tue, 7 Jun 2016 13:40:18 -0500
Subject: x86: acpi: Fix madt lapic generation

An accumulated length was incorrectly added to current each pass
through the loop. On system with more than 2 cores this caused a
corrupt MADT to be generated.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index ffb4678..bb71286 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -183,20 +183,20 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
 int acpi_create_madt_lapics(u32 current)
 {
 	struct udevice *dev;
-	int length = 0;
+	int total_length = 0;
 
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
 		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
-		length += acpi_create_madt_lapic(
-			(struct acpi_madt_lapic *)current,
-			plat->cpu_id, plat->cpu_id);
+		int length = acpi_create_madt_lapic(
+				(struct acpi_madt_lapic *)current,
+				plat->cpu_id, plat->cpu_id);
 		current += length;
+		total_length += length;
 	}
 
-	return length;
+	return total_length;
 }
 
 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
-- 
cgit v0.10.2


From 8142340ee3847c6422294fad0f1adc01c9d27e2b Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:32 -0700
Subject: x86: ich6_gpio: Output return value of syscon_get_by_driver_data()

The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b7e379a..2d66d04 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -114,9 +114,11 @@ static int ich6_gpio_probe(struct udevice *dev)
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
 	struct udevice *pinctrl;
+	int ret;
 
 	/* Set up pin control if available */
-	syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
+	debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
-- 
cgit v0.10.2


From e264e3cc5be81548c6f102b6b597a474e5bd4f20 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:33 -0700
Subject: x86: baytrail: Add 'reg' property in the pinctrl node

Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.

Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4a50d86..536049b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,6 +65,11 @@
 		};
 	};
 
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
+	};
+
 	pci {
 		compatible = "pci-x86";
 		#address-cells = <3>;
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 1a4ecaa..7e69ba4 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -30,6 +30,7 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
 	};
 
 	chosen {
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 936455b..fda170c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -29,6 +29,7 @@
 
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
 
 		/* GPIO E0 */
 		soc_gpio_s5_0@0 {
-- 
cgit v0.10.2


From 58d1fedb1f7d1a65918dcdc82c53f83b4c813368 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:34 -0700
Subject: x86: baytrail: Change fsp, emmc-boot-mode to "auto"

At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
provides a config option fsp,emmc-boot-mode which tells FSP which
eMMC controller it initializes. Instead of hardcoded to 2, now
we change it to 1 which means "auto".

With this change, MinnowMax board (with a D0 stepping BayTrail SoC)
can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot
'pci' command.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 536049b..1c2f671 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -218,7 +218,7 @@
 		fsp,mrc-init-mmio-size = <0x800>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <1>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 7e69ba4..1e14c8b 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -218,7 +218,7 @@
 		fsp,mrc-init-mmio-size = <0x800>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <1>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index fda170c..ba96e36 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -247,7 +247,7 @@
 		fsp,mrc-init-mmio-size = <0x800>;
 		fsp,mrc-init-spd-addr1 = <0xa0>;
 		fsp,mrc-init-spd-addr2 = <0xa2>;
-		fsp,emmc-boot-mode = <2>;
+		fsp,emmc-boot-mode = <1>;
 		fsp,enable-sdio;
 		fsp,enable-sdcard;
 		fsp,enable-hsuart1;
-- 
cgit v0.10.2


From f7a01e4848a97935985f58e5cd1b133dad298323 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:35 -0700
Subject: x86: baytrail: Configure card detect pin of the SD controller

As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD controller (bit 16 & bit 18 are always zero).

Add a configuration for this pin in the pinctrl node.

Note I've checked the PAD configuration for all the pins in all the
3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get
initialized to correct mode by FSP. With fsp,emmc-boot-mode set to
2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set
fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3
which is correct according to datasheet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 1c2f671..c8907ce 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -68,6 +68,21 @@
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
 		reg = <0 0>;
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
 	};
 
 	pci {
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 1e14c8b..fba089d 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -31,6 +31,21 @@
 	pch_pinctrl {
 		compatible = "intel,x86-pinctrl";
 		reg = <0 0>;
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
 	};
 
 	chosen {
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index ba96e36..1a8a8cc 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -73,6 +73,21 @@
 			output-value = <1>;
 			direction = <PIN_OUTPUT>;
 		};
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
 	};
 
 	chosen {
-- 
cgit v0.10.2


From 2600ba6de07d80407308c632c7bfa3a538b36549 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:36 -0700
Subject: x86: Update x86-pinctrl driver device-tree-bindings doc

This updates the device-tree-bindings doc for x86-pinctrl driver:

 - clarify "gpio-offset" is required only when "mode-gpio" is set
 - correct property name "pull-strength"
 - use tab instead of space at several places

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index 22d3bec..8c3a84c 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -9,7 +9,7 @@ The PINCTRL master node requires the following properties:
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
 - pad-offset	- (required) offset in the IOBASE for the pin to configure
-- gpio-offset	- (required) 2 cells
+- gpio-offset	- (required only when 'mode-gpio' is set) 2 cells
 			- offset in the GPIOBASE for the pin to configure
 			- the bit shift in this register (4 = bit 4)
 - mode-gpio	- (optional) standalone property to force the pin into GPIO mode
@@ -18,16 +18,16 @@ contain the following properties:
 in case of 'mode-gpio' property set:
 - output-value	- (optional) this set the default output value of the GPIO
 - direction	- (optional) this set the direction of the gpio
-- pull-str	- (optional) this set the pull strength of the pin
+- pull-strength	- (optional) this set the pull strength of the pin
 - pull-assign	- (optional) this set the pull assignement (up/down) of the pin
-- invert            - (optional) this input pin is inverted
+- invert	- (optional) this input pin is inverted
 
 Example:
 
 pin_usb_host_en0@0 {
-    gpio-offset = <0x80 8>;
-    pad-offset = <0x260>;
-    mode-gpio;
-    output-value = <1>;
-    direction = <PIN_OUTPUT>;
+	gpio-offset = <0x80 8>;
+	pad-offset = <0x260>;
+	mode-gpio;
+	output-value = <1>;
+	direction = <PIN_OUTPUT>;
 };
-- 
cgit v0.10.2


From 2f29c83eec16b806947c6a224c3a3f70bc31edc9 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:37 -0700
Subject: x86: Enable regmap and syscon for coreboot and qemu-x86

These are generic and should be turned on on coreboot and qemu-x86.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 2fa11fd..b18d80d 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -24,6 +24,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 45bb3ec..a03cff8 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
-- 
cgit v0.10.2


From d8906c1f3fd9e437066a9de7ff2de306696a7598 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:38 -0700
Subject: x86: Probe pinctrl driver in cpu_init_r()

At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

 - Pin's PADs only gets configured when GPIO driver is probed, which
   is not done by default. This leaves the board in a partially
   functional state as we must initialize PADs correctly to get
   perepherals fully working.
 - The probe routine of pinctrl driver is called multiple times, as
   normally there are multiple GPIO controllers. It should really
   be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index e522ff3..269043d 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -24,6 +24,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <syscon.h>
 #include <asm/control_regs.h>
 #include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
@@ -751,6 +752,10 @@ int cpu_init_r(void)
 	uclass_first_device(UCLASS_PCH, &dev);
 	uclass_first_device(UCLASS_LPC, &dev);
 
+	/* Set up pin control if available */
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+	debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
 	return 0;
 }
 
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 2d66d04..fd6181f 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,7 +32,6 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -113,12 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev)
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
-	struct udevice *pinctrl;
-	int ret;
-
-	/* Set up pin control if available */
-	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
-	debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
-- 
cgit v0.10.2


From 9769e05bcf79939bad23a719982dd1f85a110f3c Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 8 Jun 2016 05:07:39 -0700
Subject: x86: broadwell: gpio: Remove the codes to set up pin control

Now that we have set up pin control in cpu_init_r(), remove the
duplicated codes in the broadwell gpio driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 81ce446..8b50900 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -9,7 +9,6 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
-#include <syscon.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev)
 	struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct broadwell_bank_priv *priv = dev_get_priv(dev);
-	struct udevice *pinctrl;
-	int ret;
-
-	/* Set up pin control if available */
-	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
-	debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
-- 
cgit v0.10.2


From 1428d8327006445a861e347e8b1640e8eb9c5edf Mon Sep 17 00:00:00 2001
From: Keerthy <j-keerthy@ti.com>
Date: Tue, 7 Jun 2016 16:05:25 +0530
Subject: arm: dra7xx: Assign omap_vcores based on board type

Currently omap_vcores which holds pmic data is being assigned based
on the SoC type. PMIC is not a part of SoC. It is logical to
to assign omap_vcores based on board type. Hence over ride the
vcores_init function and assign omap_vcores based on the board type.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5b91446a..62dd275 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -364,82 +364,6 @@ struct vcores_data omap5430_volts_es2 = {
 	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
-struct vcores_data dra752_volts = {
-	.mpu.value	= VDD_MPU_DRA7,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
-	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
-	.mpu.pmic	= &tps659038,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-	.eve.value	= VDD_EVE_DRA7,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
-	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
-	.eve.pmic	= &tps659038,
-	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-	.gpu.value	= VDD_GPU_DRA7,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
-	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
-	.gpu.pmic	= &tps659038,
-	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-	.core.value	= VDD_CORE_DRA7,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
-	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.core.addr	= TPS659038_REG_ADDR_SMPS7,
-	.core.pmic	= &tps659038,
-
-	.iva.value	= VDD_IVA_DRA7,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
-	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
-	.iva.pmic	= &tps659038,
-	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
-	.mpu.value	= VDD_MPU_DRA7,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
-	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
-	.mpu.pmic	= &tps659038,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-	.core.value	= VDD_CORE_DRA7,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
-	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.core.addr	= TPS65917_REG_ADDR_SMPS2,
-	.core.pmic	= &tps659038,
-
-	/*
-	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
-	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
-	 */
-	.gpu.value	= VDD_GPU_DRA7,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
-	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
-	.gpu.pmic	= &tps659038,
-	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-	.eve.value	= VDD_EVE_DRA7,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
-	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
-	.eve.pmic	= &tps659038,
-	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-	.iva.value	= VDD_IVA_DRA7,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
-	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
-	.iva.pmic	= &tps659038,
-	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -802,7 +726,6 @@ void __weak hw_data_init(void)
 	case DRA752_ES2_0:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
-	*omap_vcores = &dra752_volts;
 	*ctrl = &dra7xx_ctrl;
 	break;
 
@@ -810,7 +733,6 @@ void __weak hw_data_init(void)
 	case DRA722_ES2_0:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
-	*omap_vcores = &dra722_volts;
 	*ctrl = &dra7xx_ctrl;
 	break;
 
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 3fbbc9b..0394e4e 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -305,6 +305,82 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	}
 }
 
+struct vcores_data dra752_volts = {
+	.mpu.value	= VDD_MPU_DRA7,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value	= VDD_EVE_DRA7,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value	= VDD_GPU_DRA7,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value	= VDD_CORE_DRA7,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic	= &tps659038,
+
+	.iva.value	= VDD_IVA_DRA7,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra722_volts = {
+	.mpu.value	= VDD_MPU_DRA7,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
+	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.core.value	= VDD_CORE_DRA7,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS65917_REG_ADDR_SMPS2,
+	.core.pmic	= &tps659038,
+
+	/*
+	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+	 */
+	.gpu.value	= VDD_GPU_DRA7,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
+	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.eve.value	= VDD_EVE_DRA7,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.iva.value	= VDD_IVA_DRA7,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
+	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
 /**
  * @brief board_init
  *
@@ -390,6 +466,21 @@ void do_board_detect(void)
 }
 #endif	/* CONFIG_SPL_BUILD */
 
+void vcores_init(void)
+{
+	if (board_is_dra74x_evm()) {
+		*omap_vcores = &dra752_volts;
+	} else if (board_is_dra72x_evm()) {
+		*omap_vcores = &dra722_volts;
+	} else {
+		/* If EEPROM is not populated */
+		if (is_dra72x())
+			*omap_vcores = &dra722_volts;
+		else
+			*omap_vcores = &dra752_volts;
+	}
+}
+
 void set_muxconf_regs(void)
 {
 	do_set_mux32((*ctrl)->control_padconf_core_base,
-- 
cgit v0.10.2


From 666362356e1ccc0df91c03b1d3f97939968b9c04 Mon Sep 17 00:00:00 2001
From: Michael Trimarchi <michael@amarulasolutions.com>
Date: Wed, 8 Jun 2016 10:18:16 +0200
Subject: cmd: gpt: add - partition size parsing

This patch try to parse name=userdata,size=-,uuid=${uuid_gpt_userdata};

gpt mmc write 0 $partitions
gpt mmc verify 0 $partitions

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/gpt.c b/cmd/gpt.c
index 8ffaef3..3d9706b 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -181,6 +181,7 @@ static int set_gpt_info(struct blk_desc *dev_desc,
 	disk_partition_t *parts;
 	int errno = 0;
 	uint64_t size_ll, start_ll;
+	lbaint_t offset = 0;
 
 	debug("%s:  lba num: 0x%x %d\n", __func__,
 	      (unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba);
@@ -296,8 +297,14 @@ static int set_gpt_info(struct blk_desc *dev_desc,
 		}
 		if (extract_env(val, &p))
 			p = val;
-		size_ll = ustrtoull(p, &p, 0);
-		parts[i].size = lldiv(size_ll, dev_desc->blksz);
+		if ((strcmp(p, "-") == 0)) {
+			/* remove first usable lba and last block */
+			parts[i].size = dev_desc->lba - 34  - 1 - offset;
+		} else {
+			size_ll = ustrtoull(p, &p, 0);
+			parts[i].size = lldiv(size_ll, dev_desc->blksz);
+		}
+
 		free(val);
 
 		/* start address */
@@ -310,6 +317,8 @@ static int set_gpt_info(struct blk_desc *dev_desc,
 			free(val);
 		}
 
+		offset += parts[i].size + parts[i].start;
+
 		/* bootable */
 		if (found_key(tok, "bootable"))
 			parts[i].bootable = 1;
-- 
cgit v0.10.2


From 7147a7ebd26fd0037b473343f0db2e2a98d19555 Mon Sep 17 00:00:00 2001
From: "Andrew F. Davis" <afd@ti.com>
Date: Wed, 8 Jun 2016 10:19:14 -0500
Subject: ti_armv7_common: env: Remove no longer needed mem_reserve

The kernel can now use DT to reserve memory carveouts and
these areas are now the default for drivers that need reserved
memory, so reserving more here is unneeded and any memory reserved
this way will be wasted.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 707106f..2ee26c4 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -245,7 +245,6 @@
 	"tftp_root=/\0"							\
 	"nfs_root=/export\0"						\
 	"mem_lpae=1\0"							\
-	"mem_reserve=512M\0"						\
 	"addr_ubi=0x82000000\0"						\
 	"addr_secdb_key=0xc000000\0"					\
 	"name_kern=zImage\0"						\
-- 
cgit v0.10.2


From 51c14cd128f4355514397dc3c8647fb14f7d8ff4 Mon Sep 17 00:00:00 2001
From: Teddy Reed <teddy.reed@gmail.com>
Date: Thu, 9 Jun 2016 19:18:44 -0700
Subject: verified-boot: Minimal support for booting U-Boot proper from SPL

This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.

The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256

In this example, SHA256 is the only selected hashing algorithm.

And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y

Signed-off-by: Teddy Reed <teddy.reed@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
Acked-by: Sumit Garg <sumit.garg@nxp.com>

diff --git a/Kconfig b/Kconfig
index 4b46216..817f4f0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -183,6 +183,11 @@ config FIT
 	  verified boot (secure boot using RSA). This option enables that
 	  feature.
 
+config SPL_FIT
+	bool "Support Flattened Image Tree within SPL"
+	depends on FIT
+	depends on SPL
+
 config FIT_VERBOSE
 	bool "Display verbose messages on FIT boot"
 	depends on FIT
@@ -205,6 +210,12 @@ config FIT_SIGNATURE
 	  format support in this case, enable it using
 	  CONFIG_IMAGE_FORMAT_LEGACY.
 
+config SPL_FIT_SIGNATURE
+	bool "Enable signature verification of FIT firmware within SPL"
+	depends on SPL_FIT
+	depends on SPL_DM
+	select SPL_RSA
+
 config FIT_BEST_MATCH
 	bool "Select the best match for the kernel device tree"
 	depends on FIT
diff --git a/common/Makefile b/common/Makefile
index 1557a04..97c59fe 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -93,6 +93,7 @@ obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
 endif # !CONFIG_SPL_BUILD
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
diff --git a/drivers/Makefile b/drivers/Makefile
index f6295d2..db5317c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM)	+= ram/
 
 ifdef CONFIG_SPL_BUILD
 
+obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
index dc6c064..3817fb3 100644
--- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
+++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
@@ -32,6 +32,7 @@ U_BOOT_DRIVER(mod_exp_sw) = {
 	.name	= "mod_exp_sw",
 	.id	= UCLASS_MOD_EXP,
 	.ops	= &mod_exp_ops_sw,
+	.flags	= DM_FLAG_PRE_RELOC,
 };
 
 U_BOOT_DEVICE(mod_exp_sw) = {
diff --git a/lib/Makefile b/lib/Makefile
index f77befe..f48d901 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -9,7 +9,6 @@ ifndef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_EFI) += efi/
 obj-$(CONFIG_EFI_LOADER) += efi_loader/
-obj-$(CONFIG_RSA) += rsa/
 obj-$(CONFIG_LZMA) += lzma/
 obj-$(CONFIG_LZO) += lzo/
 obj-$(CONFIG_ZLIB) += zlib/
@@ -25,8 +24,6 @@ obj-y += crc8.o
 obj-y += crc16.o
 obj-$(CONFIG_ERRNO_STR) += errno_str.o
 obj-$(CONFIG_FIT) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
 obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
 obj-$(CONFIG_GZIP) += gunzip.o
 obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
@@ -39,15 +36,17 @@ obj-y += net_utils.o
 obj-$(CONFIG_PHYSMEM) += physmem.o
 obj-y += qsort.o
 obj-y += rc4.o
-obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
-obj-$(CONFIG_SHA256) += sha256.o
 obj-$(CONFIG_TPM) += tpm.o
 obj-$(CONFIG_RBTREE)	+= rbtree.o
 obj-$(CONFIG_BITREVERSE) += bitrev.o
 obj-y += list_sort.o
 endif
 
+obj-$(CONFIG_$(SPL_)RSA) += rsa/
+obj-$(CONFIG_$(SPL_)SHA1) += sha1.o
+obj-$(CONFIG_$(SPL_)SHA256) += sha256.o
+
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
 ifdef CONFIG_SPL_OF_CONTROL
 obj-$(CONFIG_OF_LIBFDT) += libfdt/
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 86df0a0..09ec358 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -13,6 +13,10 @@ config RSA
 	  option. The software based modular exponentiation is built into
 	  mkimage irrespective of this option.
 
+config SPL_RSA
+	bool "Use RSA Library within SPL"
+	depends on RSA
+
 if RSA
 config RSA_SOFTWARE_EXP
 	bool "Enable driver for RSA Modular Exponentiation in software"
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index 6867e50..4b2c1ba 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -7,5 +7,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
 obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
-- 
cgit v0.10.2


From 152ac5fabf05daf6b0ae28f04d540b1e005c3ea1 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 4 May 2016 23:05:23 +0200
Subject: gpio: at91: Fix pullup/pulldown configuration on PIO3
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On systems with PIO3 (SAMA5D3/D4/..), the pullup and pulldown configuration
is mutualy exclusive. This patch assures that the opposite pull resistor gets
disabled before the requested pull resistor is enabled. This changes behavior
of at91_set_pio_pulldown() such that the pullup is only disabled if pulldown
is to be enabled. This changes behavior of at91_set_pio_pullup() such that
the pulldown is only disabled if pullup is to be enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 75a32ee..8e52e3d 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -59,6 +59,11 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
 {
 	struct at91_port *at91_port = at91_pio_get_port(port);
 
+#if defined(CPU_HAS_PIO3)
+	if (use_pullup)
+		at91_set_pio_pulldown(port, pin, 0);
+#endif
+
 	if (at91_port && (pin < GPIO_PER_BANK))
 		at91_set_port_pullup(at91_port, pin, use_pullup);
 
@@ -305,10 +310,10 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
 
 	if (at91_port && (pin < GPIO_PER_BANK)) {
 		mask = 1 << pin;
-		writel(mask, &at91_port->pudr);
-		if (is_on)
+		if (is_on) {
+			at91_set_pio_pullup(port, pin, 0);
 			writel(mask, &at91_port->ppder);
-		else
+		} else
 			writel(mask, &at91_port->ppddr);
 	}
 
-- 
cgit v0.10.2


From 909584665546ec51c54ac7d362f91fdabaef2cc2 Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Thu, 5 May 2016 07:28:05 -0600
Subject: at91: Add support for the AT91 slow clock controller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is available on AT91SAM9G45. Add the peripheral address and flag
definitions.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/include/mach/at91_sck.h b/arch/arm/mach-at91/include/mach/at91_sck.h
new file mode 100644
index 0000000..ce8e577
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_sck.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_SCK_H
+#define AT91_SCK_H
+
+/*
+ * SCKCR flags
+ */
+#define AT91SAM9G45_SCKCR_RCEN	    (1 << 0)	/* RC Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32EN   (1 << 1)	/* 32kHz Oscillator Enable */
+#define AT91SAM9G45_SCKCR_OSC32BYP  (1 << 2)	/* 32kHz Oscillator Bypass */
+#define AT91SAM9G45_SCKCR_OSCSEL    (1 << 3)	/* Slow Clock Selector */
+#define		AT91SAM9G45_SCKCR_OSCSEL_RC	(0 << 3)
+#define		AT91SAM9G45_SCKCR_OSCSEL_32	(1 << 3)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index cf1c73f..5c32e24 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -109,6 +109,7 @@
 #define ATMEL_BASE_RTT		0xfffffd20
 #define ATMEL_BASE_PIT		0xfffffd30
 #define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_SCKCR	0xfffffd50
 #define ATMEL_BASE_GPBR		0xfffffd60
 #define ATMEL_BASE_RTC		0xfffffdb0
 /* Reserved:	0xfffffdc0 - 0xffffffff */
-- 
cgit v0.10.2


From b5bd09820c79dc92b3e5fb5be4b47ce22c731443 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:06 -0600
Subject: arm: Allow skipping of low-level init with I-cache on
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
lowlevel_init(). This means that the instruction cache is not enabled and
the board runs very slowly.

What is really needed in many cases is to skip the call to lowlevel_init()
but still perform CP15 init. Add an option to handle this.

Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/README b/README
index 1d0b946..03bed18 100644
--- a/README
+++ b/README
@@ -4824,6 +4824,11 @@ Low Level (hardware related) configuration options:
 		other boot loader or by a debugger which performs
 		these initializations itself.
 
+- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+		[ARM926EJ-S only] This allows just the call to lowlevel_init()
+		to be skipped. The normal CPU15 init (such as enabling the
+		instruction cache) is still performed.
+
 - CONFIG_SPL_BUILD
 		Modifies the behaviour of start.S when compiling a loader
 		that is executed before the actual U-Boot. E.g. when
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 3ebdfdd..2f8fd6a 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -82,6 +82,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Jump to board specific initialization... The Mask ROM will have already initialized
 	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
@@ -89,5 +90,6 @@ cpu_init_crit:
 	mov	ip, lr		/* persevere link reg across call */
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
+#endif
 	mov	pc, lr		/* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 69cabeb..3ada6d0 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -135,6 +135,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
@@ -143,7 +144,7 @@ cpu_init_crit:
 	mov	ip, lr
 
 	bl	lowlevel_init
-
 	mov	lr, ip
+#endif
 	mov	pc, lr
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index f05113d..959d1ed 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -101,11 +101,13 @@ flush_dcache:
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	mov	ip, lr		/* perserve link reg across call */
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
+#endif
 	mov	pc, lr		/* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 214cd8c..51053c3 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -90,11 +90,13 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	mov	ip, lr		/* perserve link reg across call */
 	bl	lowlevel_init	/* go setup memory */
 	mov	lr, ip		/* restore link */
+#endif
 	mov	pc, lr		/* back to my caller */
 #endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index b180944..691e5d3 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -66,8 +66,10 @@ save_boot_params_ret:
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_cp15
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	bl	cpu_init_crit
 #endif
+#endif
 
 	bl	_main
 
@@ -250,7 +252,8 @@ skip_errata_621766:
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+	!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 /*************************************************************************
  *
  * CPU_init_critical registers
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 408b70d..f5318c9 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -96,6 +96,7 @@ cpu_init_crit:
 	ldr	r1, cpuspeed
 	str	r1, [r0, #PPCR]
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
@@ -104,6 +105,7 @@ cpu_init_crit:
 	mov	ip,	lr
 	bl	lowlevel_init
 	mov	lr,	ip
+#endif
 
 	/*
 	 * disable MMU stuff and enable I-cache
-- 
cgit v0.10.2


From b4d956f6bc0fe6ff9a5776cbce0fe97a344737a3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:07 -0600
Subject: bootm: Align cache flush end address correctly
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Flushing part of the cache should be done on cache boundaries. Trying to
flush part of a cache line is not supported and the request may be ignored
or print warnings.

Adjust the bootm code to align the end address to prevent this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/common/bootm.c b/common/bootm.c
index 4941414..2431019 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -445,7 +445,7 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
 		bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
 		return err;
 	}
-	flush_cache(load, *load_end - load);
+	flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
 
 	debug("   kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
 	bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
-- 
cgit v0.10.2


From 166c409bc42627d9e19517f6ce121c39d0f52b65 Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Thu, 5 May 2016 07:28:08 -0600
Subject: net: Handle an empty bootp extension section

Avoid generating this section if there is nothing in it.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/net/bootp.c b/net/bootp.c
index aa6cdf0..42e14ed 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -673,6 +673,15 @@ static int bootp_extended(u8 *e)
 
 	*e++ = 255;		/* End of the list */
 
+	/*
+	 * If nothing in list, remove it altogether. Some DHCP servers get
+	 * upset by this minor faux pas and do not respond at all.
+	 */
+	if (e == start + 3) {
+		printf("*** Warning: no DHCP options requested\n");
+		e -= 3;
+	}
+
 	return e - start;
 }
 #endif
-- 
cgit v0.10.2


From d5555b70e6cdbce4e1395f40c19a504015f93668 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:09 -0600
Subject: net: macb: Prepare for driver-model conversion
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Adjust this driver to avoid using struct netdev in functions that driver
model will call. Also refactor the receive function to be compatible with
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 4bf8fa4..8be62af 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -84,6 +84,8 @@ struct macb_device {
 	unsigned int		rx_tail;
 	unsigned int		tx_head;
 	unsigned int		tx_tail;
+	unsigned int		next_rx_tail;
+	bool			wrapped;
 
 	void			*rx_buffer;
 	void			*tx_buffer;
@@ -255,9 +257,9 @@ static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
 
 #if defined(CONFIG_CMD_NET)
 
-static int macb_send(struct eth_device *netdev, void *packet, int length)
+static int _macb_send(struct macb_device *macb, const char *name, void *packet,
+		      int length)
 {
-	struct macb_device *macb = to_macb(netdev);
 	unsigned long paddr, ctrl;
 	unsigned int tx_head = macb->tx_head;
 	int i;
@@ -298,12 +300,11 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
 
 	if (i <= MACB_TX_TIMEOUT) {
 		if (ctrl & TXBUF_UNDERRUN)
-			printf("%s: TX underrun\n", netdev->name);
+			printf("%s: TX underrun\n", name);
 		if (ctrl & TXBUF_EXHAUSTED)
-			printf("%s: TX buffers exhausted in mid frame\n",
-			       netdev->name);
+			printf("%s: TX buffers exhausted in mid frame\n", name);
 	} else {
-		printf("%s: TX timeout\n", netdev->name);
+		printf("%s: TX timeout\n", name);
 	}
 
 	/* No one cares anyway */
@@ -335,26 +336,25 @@ static void reclaim_rx_buffers(struct macb_device *macb,
 	macb->rx_tail = new_tail;
 }
 
-static int macb_recv(struct eth_device *netdev)
+static int _macb_recv(struct macb_device *macb, uchar **packetp)
 {
-	struct macb_device *macb = to_macb(netdev);
-	unsigned int rx_tail = macb->rx_tail;
+	unsigned int next_rx_tail = macb->next_rx_tail;
 	void *buffer;
 	int length;
-	int wrapped = 0;
 	u32 status;
 
+	macb->wrapped = false;
 	for (;;) {
 		macb_invalidate_ring_desc(macb, RX);
 
-		if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
-			return -1;
+		if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+			return -EAGAIN;
 
-		status = macb->rx_ring[rx_tail].ctrl;
+		status = macb->rx_ring[next_rx_tail].ctrl;
 		if (status & RXBUF_FRAME_START) {
-			if (rx_tail != macb->rx_tail)
-				reclaim_rx_buffers(macb, rx_tail);
-			wrapped = 0;
+			if (next_rx_tail != macb->rx_tail)
+				reclaim_rx_buffers(macb, next_rx_tail);
+			macb->wrapped = false;
 		}
 
 		if (status & RXBUF_FRAME_END) {
@@ -362,7 +362,7 @@ static int macb_recv(struct eth_device *netdev)
 			length = status & RXBUF_FRMLEN_MASK;
 
 			macb_invalidate_rx_buffer(macb);
-			if (wrapped) {
+			if (macb->wrapped) {
 				unsigned int headlen, taillen;
 
 				headlen = 128 * (MACB_RX_RING_SIZE
@@ -372,34 +372,33 @@ static int macb_recv(struct eth_device *netdev)
 				       buffer, headlen);
 				memcpy((void *)net_rx_packets[0] + headlen,
 				       macb->rx_buffer, taillen);
-				buffer = (void *)net_rx_packets[0];
+				*packetp = (void *)net_rx_packets[0];
+			} else {
+				*packetp = buffer;
 			}
 
-			net_process_received_packet(buffer, length);
-			if (++rx_tail >= MACB_RX_RING_SIZE)
-				rx_tail = 0;
-			reclaim_rx_buffers(macb, rx_tail);
+			if (++next_rx_tail >= MACB_RX_RING_SIZE)
+				next_rx_tail = 0;
+			macb->next_rx_tail = next_rx_tail;
+			return length;
 		} else {
-			if (++rx_tail >= MACB_RX_RING_SIZE) {
-				wrapped = 1;
-				rx_tail = 0;
+			if (++next_rx_tail >= MACB_RX_RING_SIZE) {
+				macb->wrapped = true;
+				next_rx_tail = 0;
 			}
 		}
 		barrier();
 	}
-
-	return 0;
 }
 
-static void macb_phy_reset(struct macb_device *macb)
+static void macb_phy_reset(struct macb_device *macb, const char *name)
 {
-	struct eth_device *netdev = &macb->netdev;
 	int i;
 	u16 status, adv;
 
 	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
 	macb_mdio_write(macb, MII_ADVERTISE, adv);
-	printf("%s: Starting autonegotiation...\n", netdev->name);
+	printf("%s: Starting autonegotiation...\n", name);
 	macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
 					 | BMCR_ANRESTART));
 
@@ -411,10 +410,10 @@ static void macb_phy_reset(struct macb_device *macb)
 	}
 
 	if (status & BMSR_ANEGCOMPLETE)
-		printf("%s: Autonegotiation complete\n", netdev->name);
+		printf("%s: Autonegotiation complete\n", name);
 	else
 		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
-		       netdev->name, status);
+		       name, status);
 }
 
 #ifdef CONFIG_MACB_SEARCH_PHY
@@ -441,9 +440,8 @@ static int macb_phy_find(struct macb_device *macb)
 #endif /* CONFIG_MACB_SEARCH_PHY */
 
 
-static int macb_phy_init(struct macb_device *macb)
+static int macb_phy_init(struct macb_device *macb, const char *name)
 {
-	struct eth_device *netdev = &macb->netdev;
 #ifdef CONFIG_PHYLIB
 	struct phy_device *phydev;
 #endif
@@ -452,7 +450,7 @@ static int macb_phy_init(struct macb_device *macb)
 	int media, speed, duplex;
 	int i;
 
-	arch_get_mdio_control(netdev->name);
+	arch_get_mdio_control(name);
 #ifdef CONFIG_MACB_SEARCH_PHY
 	/* Auto-detect phy_addr */
 	if (!macb_phy_find(macb))
@@ -462,13 +460,13 @@ static int macb_phy_init(struct macb_device *macb)
 	/* Check if the PHY is up to snuff... */
 	phy_id = macb_mdio_read(macb, MII_PHYSID1);
 	if (phy_id == 0xffff) {
-		printf("%s: No PHY present\n", netdev->name);
+		printf("%s: No PHY present\n", name);
 		return 0;
 	}
 
 #ifdef CONFIG_PHYLIB
 	/* need to consider other phy interface mode */
-	phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
+	phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
 			     PHY_INTERFACE_MODE_RGMII);
 	if (!phydev) {
 		printf("phy_connect failed\n");
@@ -481,7 +479,7 @@ static int macb_phy_init(struct macb_device *macb)
 	status = macb_mdio_read(macb, MII_BMSR);
 	if (!(status & BMSR_LSTATUS)) {
 		/* Try to re-negotiate if we don't have link already. */
-		macb_phy_reset(macb);
+		macb_phy_reset(macb, name);
 
 		for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
 			status = macb_mdio_read(macb, MII_BMSR);
@@ -493,7 +491,7 @@ static int macb_phy_init(struct macb_device *macb)
 
 	if (!(status & BMSR_LSTATUS)) {
 		printf("%s: link down (status: 0x%04x)\n",
-		       netdev->name, status);
+		       name, status);
 		return 0;
 	}
 
@@ -505,7 +503,7 @@ static int macb_phy_init(struct macb_device *macb)
 			duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
 
 			printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
-			       netdev->name,
+			       name,
 			       duplex ? "full" : "half",
 			       lpa);
 
@@ -530,7 +528,7 @@ static int macb_phy_init(struct macb_device *macb)
 		 ? 1 : 0);
 	duplex = (media & ADVERTISE_FULL) ? 1 : 0;
 	printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
-	       netdev->name,
+	       name,
 	       speed ? "100" : "10",
 	       duplex ? "full" : "half",
 	       lpa);
@@ -570,9 +568,8 @@ static int gmac_init_multi_queues(struct macb_device *macb)
 	return 0;
 }
 
-static int macb_init(struct eth_device *netdev, bd_t *bd)
+static int _macb_init(struct macb_device *macb, const char *name)
 {
-	struct macb_device *macb = to_macb(netdev);
 	unsigned long paddr;
 	int i;
 
@@ -605,6 +602,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 	macb->rx_tail = 0;
 	macb->tx_head = 0;
 	macb->tx_tail = 0;
+	macb->next_rx_tail = 0;
 
 	macb_writel(macb, RBQP, macb->rx_ring_dma);
 	macb_writel(macb, TBQP, macb->tx_ring_dma);
@@ -641,7 +639,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 #endif /* CONFIG_RMII */
 	}
 
-	if (!macb_phy_init(macb))
+	if (!macb_phy_init(macb, name))
 		return -1;
 
 	/* Enable TX and RX */
@@ -650,9 +648,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 	return 0;
 }
 
-static void macb_halt(struct eth_device *netdev)
+static void _macb_halt(struct macb_device *macb)
 {
-	struct macb_device *macb = to_macb(netdev);
 	u32 ncr, tsr;
 
 	/* Halt the controller and wait for any ongoing transmission to end. */
@@ -668,17 +665,16 @@ static void macb_halt(struct eth_device *netdev)
 	macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
 }
 
-static int macb_write_hwaddr(struct eth_device *dev)
+static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
 {
-	struct macb_device *macb = to_macb(dev);
 	u32 hwaddr_bottom;
 	u16 hwaddr_top;
 
 	/* set hardware address */
-	hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
-			dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
+	hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
+			enetaddr[2] << 16 | enetaddr[3] << 24;
 	macb_writel(macb, SA1B, hwaddr_bottom);
-	hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
+	hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
 	macb_writel(macb, SA1T, hwaddr_top);
 	return 0;
 }
@@ -739,11 +735,86 @@ static u32 macb_dbw(struct macb_device *macb)
 	}
 }
 
+static void _macb_eth_initialize(struct macb_device *macb)
+{
+	int id = 0;	/* This is not used by functions we call */
+	u32 ncfgr;
+
+	/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
+	macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
+					     &macb->rx_buffer_dma);
+	macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
+					   &macb->rx_ring_dma);
+	macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
+					   &macb->tx_ring_dma);
+	macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
+					   &macb->dummy_desc_dma);
+
+	/*
+	 * Do some basic initialization so that we at least can talk
+	 * to the PHY
+	 */
+	if (macb_is_gem(macb)) {
+		ncfgr = gem_mdc_clk_div(id, macb);
+		ncfgr |= macb_dbw(macb);
+	} else {
+		ncfgr = macb_mdc_clk_div(id, macb);
+	}
+
+	macb_writel(macb, NCFGR, ncfgr);
+}
+
+static int macb_send(struct eth_device *netdev, void *packet, int length)
+{
+	struct macb_device *macb = to_macb(netdev);
+
+	return _macb_send(macb, netdev->name, packet, length);
+}
+
+static int macb_recv(struct eth_device *netdev)
+{
+	struct macb_device *macb = to_macb(netdev);
+	uchar *packet;
+	int length;
+
+	macb->wrapped = false;
+	for (;;) {
+		macb->next_rx_tail = macb->rx_tail;
+		length = _macb_recv(macb, &packet);
+		if (length >= 0) {
+			net_process_received_packet(packet, length);
+			reclaim_rx_buffers(macb, macb->next_rx_tail);
+		} else if (length < 0) {
+			return length;
+		}
+	}
+}
+
+static int macb_init(struct eth_device *netdev, bd_t *bd)
+{
+	struct macb_device *macb = to_macb(netdev);
+
+	return _macb_init(macb, netdev->name);
+}
+
+static void macb_halt(struct eth_device *netdev)
+{
+	struct macb_device *macb = to_macb(netdev);
+
+	return _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct eth_device *netdev)
+{
+	struct macb_device *macb = to_macb(netdev);
+
+	return _macb_write_hwaddr(macb, netdev->enetaddr);
+}
+
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 {
 	struct macb_device *macb;
 	struct eth_device *netdev;
-	u32 ncfgr;
 
 	macb = malloc(sizeof(struct macb_device));
 	if (!macb) {
@@ -754,17 +825,6 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 
 	netdev = &macb->netdev;
 
-	macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
-					     &macb->rx_buffer_dma);
-	macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
-					   &macb->rx_ring_dma);
-	macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
-					   &macb->tx_ring_dma);
-	macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
-					   &macb->dummy_desc_dma);
-
-	/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
-
 	macb->regs = regs;
 	macb->phy_addr = phy_addr;
 
@@ -779,18 +839,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 	netdev->recv = macb_recv;
 	netdev->write_hwaddr = macb_write_hwaddr;
 
-	/*
-	 * Do some basic initialization so that we at least can talk
-	 * to the PHY
-	 */
-	if (macb_is_gem(macb)) {
-		ncfgr = gem_mdc_clk_div(id, macb);
-		ncfgr |= macb_dbw(macb);
-	} else {
-		ncfgr = macb_mdc_clk_div(id, macb);
-	}
-
-	macb_writel(macb, NCFGR, ncfgr);
+	_macb_eth_initialize(macb);
 
 	eth_register(netdev);
 
-- 
cgit v0.10.2


From f589f8cca64bddb59fe2409c10ab14529ab47a40 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:10 -0600
Subject: net: macb: Flush correct cache portion when sending
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8be62af..84bae37 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
 	barrier();
 	macb_flush_ring_desc(macb, TX);
 	/* Do we need check paddr and length is dcache line aligned? */
-	flush_dcache_range(paddr, paddr + length);
+	flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
 	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
 
 	/*
-- 
cgit v0.10.2


From f1dcc19b213df97127df9c6f4bec296ae2f91f38 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:11 -0600
Subject: net: macb: Convert to driver model
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add driver-model support to this driver. The old code remains for now so
that we can convert boards one at a time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 84bae37..0835fdc 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
 
 /*
  * The u-boot networking stack is a little weird.  It seems like the
@@ -28,7 +29,9 @@
  */
 
 #include <net.h>
+#ifndef CONFIG_DM_ETH
 #include <netdev.h>
+#endif
 #include <malloc.h>
 #include <miiphy.h>
 
@@ -100,11 +103,15 @@ struct macb_device {
 	unsigned long		dummy_desc_dma;
 
 	const struct device	*dev;
+#ifndef CONFIG_DM_ETH
 	struct eth_device	netdev;
+#endif
 	unsigned short		phy_addr;
 	struct mii_dev		*bus;
 };
+#ifndef CONFIG_DM_ETH
 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
+#endif
 
 static int macb_is_gem(struct macb_device *macb)
 {
@@ -194,8 +201,13 @@ void __weak arch_get_mdio_control(const char *name)
 
 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
 {
+#ifdef CONFIG_DM_ETH
+	struct udevice *dev = eth_get_dev_by_name(devname);
+	struct macb_device *macb = dev_get_priv(dev);
+#else
 	struct eth_device *dev = eth_get_dev_by_name(devname);
 	struct macb_device *macb = to_macb(dev);
+#endif
 
 	if (macb->phy_addr != phy_adr)
 		return -1;
@@ -208,8 +220,13 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
 
 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
 {
+#ifdef CONFIG_DM_ETH
+	struct udevice *dev = eth_get_dev_by_name(devname);
+	struct macb_device *macb = dev_get_priv(dev);
+#else
 	struct eth_device *dev = eth_get_dev_by_name(devname);
 	struct macb_device *macb = to_macb(dev);
+#endif
 
 	if (macb->phy_addr != phy_adr)
 		return -1;
@@ -764,6 +781,7 @@ static void _macb_eth_initialize(struct macb_device *macb)
 	macb_writel(macb, NCFGR, ncfgr);
 }
 
+#ifndef CONFIG_DM_ETH
 static int macb_send(struct eth_device *netdev, void *packet, int length)
 {
 	struct macb_device *macb = to_macb(netdev);
@@ -849,5 +867,106 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 #endif
 	return 0;
 }
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_DM_ETH
+
+static int macb_start(struct udevice *dev)
+{
+	struct macb_device *macb = dev_get_priv(dev);
+
+	return _macb_init(macb, dev->name);
+}
+
+static int macb_send(struct udevice *dev, void *packet, int length)
+{
+	struct macb_device *macb = dev_get_priv(dev);
+
+	return _macb_send(macb, dev->name, packet, length);
+}
+
+static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct macb_device *macb = dev_get_priv(dev);
+
+	macb->next_rx_tail = macb->rx_tail;
+	macb->wrapped = false;
+
+	return _macb_recv(macb, packetp);
+}
+
+static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	struct macb_device *macb = dev_get_priv(dev);
+
+	reclaim_rx_buffers(macb, macb->next_rx_tail);
+
+	return 0;
+}
+
+static void macb_stop(struct udevice *dev)
+{
+	struct macb_device *macb = dev_get_priv(dev);
+
+	_macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct udevice *dev)
+{
+	struct eth_pdata *plat = dev_get_platdata(dev);
+	struct macb_device *macb = dev_get_priv(dev);
+
+	return _macb_write_hwaddr(macb, plat->enetaddr);
+}
+
+static const struct eth_ops macb_eth_ops = {
+	.start	= macb_start,
+	.send	= macb_send,
+	.recv	= macb_recv,
+	.stop	= macb_stop,
+	.free_pkt	= macb_free_pkt,
+	.write_hwaddr	= macb_write_hwaddr,
+};
+
+static int macb_eth_probe(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct macb_device *macb = dev_get_priv(dev);
+
+	macb->regs = (void *)pdata->iobase;
+
+	_macb_eth_initialize(macb);
+#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
+	miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write);
+	macb->bus = miiphy_get_dev_by_name(dev->name);
+#endif
+
+	return 0;
+}
+
+static int macb_eth_ofdata_to_platdata(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+
+	pdata->iobase = dev_get_addr(dev);
+	return 0;
+}
+
+static const struct udevice_id macb_eth_ids[] = {
+	{ .compatible = "cdns,macb" },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_macb) = {
+	.name	= "eth_macb",
+	.id	= UCLASS_ETH,
+	.of_match = macb_eth_ids,
+	.ofdata_to_platdata = macb_eth_ofdata_to_platdata,
+	.probe	= macb_eth_probe,
+	.ops	= &macb_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct macb_device),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif
 
 #endif
-- 
cgit v0.10.2


From 6f9678567a57c5c82620c35a05a2f89c32cdd34d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:12 -0600
Subject: arm: at91: dts: Bring in device tree file for AT91SAM9G45
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add this file from Linux v4.5.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a827613..602fab1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-gurnard.dtb
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi
new file mode 100644
index 0000000..af8b708
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45.dtsi
@@ -0,0 +1,1335 @@
+/*
+ * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
+ *                    applies to AT91SAM9G45, AT91SAM9M10,
+ *                    AT91SAM9G46, AT91SAM9M11 SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+	model = "Atmel AT91SAM9G45 family SoC";
+	compatible = "atmel,at91sam9g45";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		serial1 = &usart0;
+		serial2 = &usart1;
+		serial3 = &usart2;
+		serial4 = &usart3;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		gpio4 = &pioE;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		ssc0 = &ssc0;
+		ssc1 = &ssc1;
+		pwm0 = &pwm0;
+	};
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		reg = <0x70000000 0x10000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		adc_op_clk: adc_op_clk{
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <300000>;
+		};
+	};
+
+	sram: sram@00300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x10000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			aic: interrupt-controller@fffff000 {
+				#interrupt-cells = <3>;
+				compatible = "atmel,at91rm9200-aic";
+				interrupt-controller;
+				reg = <0xfffff000 0x200>;
+				atmel,external-irqs = <31>;
+			};
+
+			ramc0: ramc@ffffe400 {
+				compatible = "atmel,at91sam9g45-ddramc";
+				reg = <0xffffe400 0x200>;
+				clocks = <&ddrck>;
+				clock-names = "ddrck";
+			};
+
+			ramc1: ramc@ffffe600 {
+				compatible = "atmel,at91sam9g45-ddramc";
+				reg = <0xffffe600 0x200>;
+				clocks = <&ddrck>;
+				clock-names = "ddrck";
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91sam9g45-pmc", "syscon";
+				reg = <0xfffffc00 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				interrupt-controller;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#interrupt-cells = <1>;
+
+				main_osc: main_osc {
+					compatible = "atmel,at91rm9200-clk-main-osc";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+					clocks = <&main_xtal>;
+				};
+
+				main: mainck {
+					compatible = "atmel,at91rm9200-clk-main";
+					#clock-cells = <0>;
+					clocks = <&main_osc>;
+				};
+
+				plla: pllack {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+					clocks = <&main>;
+					reg = <0>;
+					atmel,clk-input-range = <2000000 32000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <745000000 800000000 0 0
+								       695000000 750000000 1 0
+								       645000000 700000000 2 0
+								       595000000 650000000 3 0
+								       545000000 600000000 0 1
+								       495000000 555000000 1 1
+								       445000000 500000000 2 1
+								       400000000 450000000 3 1>;
+				};
+
+				plladiv: plladivck {
+					compatible = "atmel,at91sam9x5-clk-plldiv";
+					#clock-cells = <0>;
+					clocks = <&plla>;
+				};
+
+				utmi: utmick {
+					compatible = "atmel,at91sam9x5-clk-utmi";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKU>;
+					clocks = <&main>;
+				};
+
+				mck: masterck {
+					compatible = "atmel,at91rm9200-clk-master";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+					atmel,clk-output-range = <0 133333333>;
+					atmel,clk-divisors = <1 2 4 3>;
+				};
+
+				usb: usbck {
+					compatible = "atmel,at91sam9x5-clk-usb";
+					#clock-cells = <0>;
+					clocks = <&plladiv>, <&utmi>;
+				};
+
+				prog: progck {
+					compatible = "atmel,at91sam9g45-clk-programmable";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					interrupt-parent = <&pmc>;
+					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+					prog0: prog0 {
+						#clock-cells = <0>;
+						reg = <0>;
+						interrupts = <AT91_PMC_PCKRDY(0)>;
+					};
+
+					prog1: prog1 {
+						#clock-cells = <0>;
+						reg = <1>;
+						interrupts = <AT91_PMC_PCKRDY(1)>;
+					};
+				};
+
+				systemck {
+					compatible = "atmel,at91rm9200-clk-system";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					ddrck: ddrck {
+						#clock-cells = <0>;
+						reg = <2>;
+						clocks = <&mck>;
+					};
+
+					uhpck: uhpck {
+						#clock-cells = <0>;
+						reg = <6>;
+						clocks = <&usb>;
+					};
+
+					pck0: pck0 {
+						#clock-cells = <0>;
+						reg = <8>;
+						clocks = <&prog0>;
+					};
+
+					pck1: pck1 {
+						#clock-cells = <0>;
+						reg = <9>;
+						clocks = <&prog1>;
+					};
+				};
+
+				periphck {
+					compatible = "atmel,at91rm9200-clk-peripheral";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					clocks = <&mck>;
+
+					pioA_clk: pioA_clk {
+						#clock-cells = <0>;
+						reg = <2>;
+					};
+
+					pioB_clk: pioB_clk {
+						#clock-cells = <0>;
+						reg = <3>;
+					};
+
+					pioC_clk: pioC_clk {
+						#clock-cells = <0>;
+						reg = <4>;
+					};
+
+					pioDE_clk: pioDE_clk {
+						#clock-cells = <0>;
+						reg = <5>;
+					};
+
+					trng_clk: trng_clk {
+						#clock-cells = <0>;
+						reg = <6>;
+					};
+
+					usart0_clk: usart0_clk {
+						#clock-cells = <0>;
+						reg = <7>;
+					};
+
+					usart1_clk: usart1_clk {
+						#clock-cells = <0>;
+						reg = <8>;
+					};
+
+					usart2_clk: usart2_clk {
+						#clock-cells = <0>;
+						reg = <9>;
+					};
+
+					usart3_clk: usart3_clk {
+						#clock-cells = <0>;
+						reg = <10>;
+					};
+
+					mci0_clk: mci0_clk {
+						#clock-cells = <0>;
+						reg = <11>;
+					};
+
+					twi0_clk: twi0_clk {
+						#clock-cells = <0>;
+						reg = <12>;
+					};
+
+					twi1_clk: twi1_clk {
+						#clock-cells = <0>;
+						reg = <13>;
+					};
+
+					spi0_clk: spi0_clk {
+						#clock-cells = <0>;
+						reg = <14>;
+					};
+
+					spi1_clk: spi1_clk {
+						#clock-cells = <0>;
+						reg = <15>;
+					};
+
+					ssc0_clk: ssc0_clk {
+						#clock-cells = <0>;
+						reg = <16>;
+					};
+
+					ssc1_clk: ssc1_clk {
+						#clock-cells = <0>;
+						reg = <17>;
+					};
+
+					tcb0_clk: tcb0_clk {
+						#clock-cells = <0>;
+						reg = <18>;
+					};
+
+					pwm_clk: pwm_clk {
+						#clock-cells = <0>;
+						reg = <19>;
+					};
+
+					adc_clk: adc_clk {
+						#clock-cells = <0>;
+						reg = <20>;
+					};
+
+					dma0_clk: dma0_clk {
+						#clock-cells = <0>;
+						reg = <21>;
+					};
+
+					uhphs_clk: uhphs_clk {
+						#clock-cells = <0>;
+						reg = <22>;
+					};
+
+					lcd_clk: lcd_clk {
+						#clock-cells = <0>;
+						reg = <23>;
+					};
+
+					ac97_clk: ac97_clk {
+						#clock-cells = <0>;
+						reg = <24>;
+					};
+
+					macb0_clk: macb0_clk {
+						#clock-cells = <0>;
+						reg = <25>;
+					};
+
+					isi_clk: isi_clk {
+						#clock-cells = <0>;
+						reg = <26>;
+					};
+
+					udphs_clk: udphs_clk {
+						#clock-cells = <0>;
+						reg = <27>;
+					};
+
+					aestdessha_clk: aestdessha_clk {
+						#clock-cells = <0>;
+						reg = <28>;
+					};
+
+					mci1_clk: mci1_clk {
+						#clock-cells = <0>;
+						reg = <29>;
+					};
+
+					vdec_clk: vdec_clk {
+						#clock-cells = <0>;
+						reg = <30>;
+					};
+				};
+			};
+
+			rstc@fffffd00 {
+				compatible = "atmel,at91sam9g45-rstc";
+				reg = <0xfffffd00 0x10>;
+				clocks = <&clk32k>;
+			};
+
+			pit: timer@fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&mck>;
+			};
+
+
+			shdwc@fffffd10 {
+				compatible = "atmel,at91sam9rl-shdwc";
+				reg = <0xfffffd10 0x10>;
+				clocks = <&clk32k>;
+			};
+
+			tcb0: timer@fff7c000 {
+				compatible = "atmel,at91rm9200-tcb";
+				reg = <0xfff7c000 0x100>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+			};
+
+			tcb1: timer@fffd4000 {
+				compatible = "atmel,at91rm9200-tcb";
+				reg = <0xfffd4000 0x100>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+			};
+
+			dma: dma-controller@ffffec00 {
+				compatible = "atmel,at91sam9g45-dma";
+				reg = <0xffffec00 0x200>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
+				#dma-cells = <2>;
+				clocks = <&dma0_clk>;
+				clock-names = "dma_clk";
+			};
+
+			pinctrl@fffff200 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff200 0xfffff200 0xa00>;
+
+				atmel,mux-mask = <
+				      /*    A         B     */
+				       0xffffffff 0xffc003ff  /* pioA */
+				       0xffffffff 0x800f8f00  /* pioB */
+				       0xffffffff 0x00000e00  /* pioC */
+				       0xffffffff 0xff0c1381  /* pioD */
+				       0xffffffff 0x81ffff81  /* pioE */
+				      >;
+
+				/* shared pinctrl settings */
+				adc0 {
+					pinctrl_adc0_adtrg: adc0_adtrg {
+						atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad0: adc0_ad0 {
+						atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad1: adc0_ad1 {
+						atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad2: adc0_ad2 {
+						atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad3: adc0_ad3 {
+						atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad4: adc0_ad4 {
+						atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad5: adc0_ad5 {
+						atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad6: adc0_ad6 {
+						atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_adc0_ad7: adc0_ad7 {
+						atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+				};
+
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
+							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB13 periph A */
+					};
+				};
+
+				i2c0 {
+					pinctrl_i2c0: i2c0-0 {
+						atmel,pins =
+							<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA21 periph A TWCK0 */
+							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA20 periph A TWD0 */
+					};
+				};
+
+				i2c1 {
+					pinctrl_i2c1: i2c1-0 {
+						atmel,pins =
+							<AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A TWCK1 */
+							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A TWD1 */
+					};
+				};
+
+				isi {
+					pinctrl_isi_data_0_7: isi-0-data-0-7 {
+						atmel,pins =
+							<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
+							AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
+							AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
+							AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
+							AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
+							AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
+							AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
+							AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
+							AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
+							AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
+							AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
+					};
+
+					pinctrl_isi_data_8_9: isi-0-data-8-9 {
+						atmel,pins =
+							<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
+							AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
+					};
+
+					pinctrl_isi_data_10_11: isi-0-data-10-11 {
+						atmel,pins =
+							<AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
+							AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
+					};
+				};
+
+				usart0 {
+					pinctrl_usart0: usart0-0 {
+						atmel,pins =
+							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB19 periph A with pullup */
+							 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB18 periph A */
+					};
+
+					pinctrl_usart0_rts: usart0_rts-0 {
+						atmel,pins =
+							<AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB17 periph B */
+					};
+
+					pinctrl_usart0_cts: usart0_cts-0 {
+						atmel,pins =
+							<AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB15 periph B */
+					};
+				};
+
+				uart1 {
+					pinctrl_usart1: usart1-0 {
+						atmel,pins =
+							<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB4 periph A with pullup */
+							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB5 periph A */
+					};
+
+					pinctrl_usart1_rts: usart1_rts-0 {
+						atmel,pins =
+							<AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD16 periph A */
+					};
+
+					pinctrl_usart1_cts: usart1_cts-0 {
+						atmel,pins =
+							<AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD17 periph A */
+					};
+				};
+
+				usart2 {
+					pinctrl_usart2: usart2-0 {
+						atmel,pins =
+							<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB6 periph A with pullup */
+							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB7 periph A */
+					};
+
+					pinctrl_usart2_rts: usart2_rts-0 {
+						atmel,pins =
+							<AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC9 periph B */
+					};
+
+					pinctrl_usart2_cts: usart2_cts-0 {
+						atmel,pins =
+							<AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC11 periph B */
+					};
+				};
+
+				usart3 {
+					pinctrl_usart3: usart3-0 {
+						atmel,pins =
+							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB9 periph A with pullup */
+							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB8 periph A */
+					};
+
+					pinctrl_usart3_rts: usart3_rts-0 {
+						atmel,pins =
+							<AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA23 periph B */
+					};
+
+					pinctrl_usart3_cts: usart3_cts-0 {
+						atmel,pins =
+							<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA24 periph B */
+					};
+				};
+
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PC8 gpio RDY pin pull_up*/
+							 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PC14 gpio enable pin pull_up */
+					};
+				};
+
+				macb {
+					pinctrl_macb_rmii: macb_rmii-0 {
+						atmel,pins =
+							<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA10 periph A */
+							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A */
+							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A */
+							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA13 periph A */
+							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA14 periph A */
+							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA15 periph A */
+							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA16 periph A */
+							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
+							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA18 periph A */
+							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA19 periph A */
+					};
+
+					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+						atmel,pins =
+							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA6 periph B */
+							 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA7 periph B */
+							 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA8 periph B */
+							 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA9 periph B */
+							 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
+							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
+							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA29 periph B */
+							 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA30 periph B */
+					};
+				};
+
+				mmc0 {
+					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA0 periph A */
+							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA1 periph A with pullup */
+							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA2 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA3 periph A with pullup */
+							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA4 periph A with pullup */
+							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA5 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
+						atmel,pins =
+							<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA6 periph A with pullup */
+							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
+							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA8 periph A with pullup */
+							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA9 periph A with pullup */
+					};
+				};
+
+				mmc1 {
+					pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA31 periph A */
+							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA22 periph A with pullup */
+							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA23 periph A with pullup */
+					};
+
+					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA24 periph A with pullup */
+							 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA25 periph A with pullup */
+							 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA26 periph A with pullup */
+					};
+
+					pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
+						atmel,pins =
+							<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA27 periph A with pullup */
+							 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA28 periph A with pullup */
+							 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA29 periph A with pullup */
+							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA30 periph A with pullup */
+					};
+				};
+
+				ssc0 {
+					pinctrl_ssc0_tx: ssc0_tx-0 {
+						atmel,pins =
+							<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD0 periph A */
+							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD1 periph A */
+							 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD2 periph A */
+					};
+
+					pinctrl_ssc0_rx: ssc0_rx-0 {
+						atmel,pins =
+							<AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD3 periph A */
+							 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD4 periph A */
+							 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD5 periph A */
+					};
+				};
+
+				ssc1 {
+					pinctrl_ssc1_tx: ssc1_tx-0 {
+						atmel,pins =
+							<AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD10 periph A */
+							 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD11 periph A */
+							 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD12 periph A */
+					};
+
+					pinctrl_ssc1_rx: ssc1_rx-0 {
+						atmel,pins =
+							<AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD13 periph A */
+							 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD14 periph A */
+							 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD15 periph A */
+					};
+				};
+
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A SPI0_MISO pin */
+							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A SPI0_MOSI pin */
+							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB2 periph A SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A SPI1_MISO pin */
+							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A SPI1_MOSI pin */
+							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB16 periph A SPI1_SPCK pin */
+					};
+				};
+
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				fb {
+					pinctrl_fb: fb-0 {
+						atmel,pins =
+							<AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE0 periph A */
+							 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE2 periph A */
+							 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE3 periph A */
+							 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE4 periph A */
+							 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE5 periph A */
+							 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE6 periph A */
+							 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE7 periph A */
+							 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE8 periph A */
+							 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE9 periph A */
+							 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE10 periph A */
+							 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE11 periph A */
+							 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE12 periph A */
+							 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE13 periph A */
+							 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE14 periph A */
+							 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE15 periph A */
+							 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE16 periph A */
+							 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE17 periph A */
+							 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE18 periph A */
+							 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE19 periph A */
+							 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE20 periph A */
+							 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE21 periph A */
+							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE22 periph A */
+							 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE23 periph A */
+							 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE24 periph A */
+							 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE25 periph A */
+							 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE26 periph A */
+							 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE27 periph A */
+							 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE28 periph A */
+							 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE29 periph A */
+							 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PE30 periph A */
+					};
+				};
+
+				pioA: gpio@fffff200 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+				};
+
+				pioB: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+				};
+
+				pioC: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+				};
+
+				pioD: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioDE_clk>;
+				};
+
+				pioE: gpio@fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioDE_clk>;
+				};
+			};
+
+			dbgu: serial@ffffee00 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xffffee00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
+				clocks = <&mck>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart0: serial@fff8c000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff8c000 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart0>;
+				clocks = <&usart0_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart1: serial@fff90000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff90000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart1>;
+				clocks = <&usart1_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart2: serial@fff94000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff94000 0x200>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart2>;
+				clocks = <&usart2_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart3: serial@fff98000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff98000 0x200>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart3>;
+				clocks = <&usart3_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			macb0: ethernet@fffbc000 {
+				compatible = "cdns,at91sam9260-macb", "cdns,macb";
+				reg = <0xfffbc000 0x100>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb_rmii>;
+				clocks = <&macb0_clk>, <&macb0_clk>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			trng@fffcc000 {
+				compatible = "atmel,at91sam9g45-trng";
+				reg = <0xfffcc000 0x4000>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&trng_clk>;
+			};
+
+			i2c0: i2c@fff84000 {
+				compatible = "atmel,at91sam9g10-i2c";
+				reg = <0xfff84000 0x100>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&twi0_clk>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@fff88000 {
+				compatible = "atmel,at91sam9g10-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&twi1_clk>;
+				status = "disabled";
+			};
+
+			ssc0: ssc@fff9c000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xfff9c000 0x4000>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+				clocks = <&ssc0_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			ssc1: ssc@fffa0000 {
+				compatible = "atmel,at91sam9g45-ssc";
+				reg = <0xfffa0000 0x4000>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+				clocks = <&ssc1_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			adc0: adc@fffb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9g45-adc";
+				reg = <0xfffb0000 0x100>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&adc_clk>, <&adc_op_clk>;
+				clock-names = "adc_clk", "adc_op_clk";
+				atmel,adc-channels-used = <0xff>;
+				atmel,adc-vref = <3300>;
+				atmel,adc-startup-time = <40>;
+				atmel,adc-res = <8 10>;
+				atmel,adc-res-names = "lowres", "highres";
+				atmel,adc-use-res = "highres";
+
+				trigger@0 {
+					reg = <0>;
+					trigger-name = "external-rising";
+					trigger-value = <0x1>;
+					trigger-external;
+				};
+				trigger@1 {
+					reg = <1>;
+					trigger-name = "external-falling";
+					trigger-value = <0x2>;
+					trigger-external;
+				};
+
+				trigger@2 {
+					reg = <2>;
+					trigger-name = "external-any";
+					trigger-value = <0x3>;
+					trigger-external;
+				};
+
+				trigger@3 {
+					reg = <3>;
+					trigger-name = "continuous";
+					trigger-value = <0x6>;
+				};
+			};
+
+			isi@fffb4000 {
+				compatible = "atmel,at91sam9g45-isi";
+				reg = <0xfffb4000 0x4000>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
+				clocks = <&isi_clk>;
+				clock-names = "isi_clk";
+				status = "disabled";
+				port {
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+
+			pwm0: pwm@fffb8000 {
+				compatible = "atmel,at91sam9rl-pwm";
+				reg = <0xfffb8000 0x300>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				clocks = <&pwm_clk>;
+				status = "disabled";
+			};
+
+			mmc0: mmc@fff80000 {
+				compatible = "atmel,hsmci";
+				reg = <0xfff80000 0x600>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
+				dma-names = "rxtx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&mci0_clk>;
+				clock-names = "mci_clk";
+				status = "disabled";
+			};
+
+			mmc1: mmc@fffd0000 {
+				compatible = "atmel,hsmci";
+				reg = <0xfffd0000 0x600>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
+				dma-names = "rxtx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&mci1_clk>;
+				clock-names = "mci_clk";
+				status = "disabled";
+			};
+
+			watchdog@fffffd40 {
+				compatible = "atmel,at91sam9260-wdt";
+				reg = <0xfffffd40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				atmel,watchdog-type = "hardware";
+				atmel,reset-type = "all";
+				atmel,dbg-halt;
+				status = "disabled";
+			};
+
+			spi0: spi@fffa4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa4000 0x200>;
+				interrupts = <14 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
+				clocks = <&spi0_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			spi1: spi@fffa8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa8000 0x200>;
+				interrupts = <15 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
+				clocks = <&spi1_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			usb2: gadget@fff78000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9g45-udc";
+				reg = <0x00600000 0x80000
+				       0xfff78000 0x400>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&udphs_clk>, <&utmi>;
+				clock-names = "pclk", "hclk";
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma;
+					atmel,can-isoc;
+				};
+			};
+
+			sckc@fffffd50 {
+				compatible = "atmel,at91sam9x5-sckc";
+				reg = <0xfffffd50 0x4>;
+
+				slow_osc: slow_osc {
+					compatible = "atmel,at91sam9x5-clk-slow-osc";
+					#clock-cells = <0>;
+					atmel,startup-time-usec = <1200000>;
+					clocks = <&slow_xtal>;
+				};
+
+				slow_rc_osc: slow_rc_osc {
+					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+					#clock-cells = <0>;
+					atmel,startup-time-usec = <75>;
+					clock-frequency = <32768>;
+					clock-accuracy = <50000000>;
+				};
+
+				clk32k: slck {
+					compatible = "atmel,at91sam9x5-clk-slow";
+					#clock-cells = <0>;
+					clocks = <&slow_rc_osc &slow_osc>;
+				};
+			};
+
+			rtc@fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				status = "disabled";
+			};
+
+			rtc@fffffdb0 {
+				compatible = "atmel,at91rm9200-rtc";
+				reg = <0xfffffdb0 0x30>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				status = "disabled";
+			};
+
+			gpbr: syscon@fffffd60 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd60 0x10>;
+				status = "disabled";
+			};
+		};
+
+		fb0: fb@0x00500000 {
+			compatible = "atmel,at91sam9g45-lcdc";
+			reg = <0x00500000 0x1000>;
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_fb>;
+			clocks = <&lcd_clk>, <&lcd_clk>;
+			clock-names = "hclk", "lcdc_clk";
+			status = "disabled";
+		};
+
+		nand0: nand@40000000 {
+			compatible = "atmel,at91rm9200-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40000000 0x10000000
+			       0xffffe200 0x200
+			      >;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			atmel,nand-has-dma;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			gpios = <&pioC 8 GPIO_ACTIVE_HIGH
+				 &pioC 14 GPIO_ACTIVE_HIGH
+				 0
+				>;
+			status = "disabled";
+		};
+
+		usb0: ohci@00700000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb1: ehci@00800000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00800000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&utmi>, <&uhphs_clk>;
+			clock-names = "usb_clk", "ehci_clk";
+			status = "disabled";
+		};
+	};
+
+	i2c@0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
new file mode 100644
index 0000000..ab3ee24
--- /dev/null
+++ b/include/dt-bindings/clock/at91.h
@@ -0,0 +1,23 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+#define AT91_PMC_LOCKA		1		/* PLLA Lock */
+#define AT91_PMC_LOCKB		2		/* PLLB Lock */
+#define AT91_PMC_MCKRDY		3		/* Master Clock */
+#define AT91_PMC_LOCKU		6		/* UPLL Lock */
+#define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
+#define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
+#define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY		24		/* Generated Clocks */
+
+#endif
diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
new file mode 100644
index 0000000..ab6cbba
--- /dev/null
+++ b/include/dt-bindings/dma/at91.h
@@ -0,0 +1,52 @@
+/*
+ * This header provides macros for at91 dma bindings.
+ *
+ * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_DMA_H__
+#define __DT_BINDINGS_AT91_DMA_H__
+
+/* ---------- HDMAC ---------- */
+
+/*
+ * Source and/or destination peripheral ID
+ */
+#define AT91_DMA_CFG_PER_ID_MASK	(0xff)
+#define AT91_DMA_CFG_PER_ID(id)		(id & AT91_DMA_CFG_PER_ID_MASK)
+
+/*
+ * FIFO configuration: it defines when a request is serviced.
+ */
+#define AT91_DMA_CFG_FIFOCFG_OFFSET	(8)
+#define AT91_DMA_CFG_FIFOCFG_MASK	(0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
+#define AT91_DMA_CFG_FIFOCFG_HALF	(0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* half FIFO (default behavior) */
+#define AT91_DMA_CFG_FIFOCFG_ALAP	(0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* largest defined AHB burst */
+#define AT91_DMA_CFG_FIFOCFG_ASAP	(0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* single AHB access */
+
+
+/* ---------- XDMAC ---------- */
+#define AT91_XDMAC_DT_MEM_IF_MASK	(0x1)
+#define AT91_XDMAC_DT_MEM_IF_OFFSET	(13)
+#define AT91_XDMAC_DT_MEM_IF(mem_if)	(((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
+					<< AT91_XDMAC_DT_MEM_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_MEM_IF(cfg)	(((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
+					& AT91_XDMAC_DT_MEM_IF_MASK)
+
+#define AT91_XDMAC_DT_PER_IF_MASK	(0x1)
+#define AT91_XDMAC_DT_PER_IF_OFFSET	(14)
+#define AT91_XDMAC_DT_PER_IF(per_if)	(((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
+					<< AT91_XDMAC_DT_PER_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_PER_IF(cfg)	(((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
+					& AT91_XDMAC_DT_PER_IF_MASK)
+
+#define AT91_XDMAC_DT_PERID_MASK	(0x7f)
+#define AT91_XDMAC_DT_PERID_OFFSET	(24)
+#define AT91_XDMAC_DT_PERID(perid)	(((perid) & AT91_XDMAC_DT_PERID_MASK) \
+					<< AT91_XDMAC_DT_PERID_OFFSET)
+#define AT91_XDMAC_DT_GET_PERID(cfg)	(((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
+					& AT91_XDMAC_DT_PERID_MASK)
+
+#endif /* __DT_BINDINGS_AT91_DMA_H__ */
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
new file mode 100644
index 0000000..bbca3d0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for most at91 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
+#define __DT_BINDINGS_AT91_PINCTRL_H__
+
+#define AT91_PINCTRL_NONE		(0 << 0)
+#define AT91_PINCTRL_PULL_UP		(1 << 0)
+#define AT91_PINCTRL_MULTI_DRIVE	(1 << 1)
+#define AT91_PINCTRL_DEGLITCH		(1 << 2)
+#define AT91_PINCTRL_PULL_DOWN		(1 << 3)
+#define AT91_PINCTRL_DIS_SCHMIT		(1 << 4)
+#define AT91_PINCTRL_DEBOUNCE		(1 << 16)
+#define AT91_PINCTRL_DEBOUNCE_VAL(x)	(x << 17)
+
+#define AT91_PINCTRL_PULL_UP_DEGLITCH	(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT		(0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW			(0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED			(0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI			(0x3 << 5)
+
+#define AT91_PIOA	0
+#define AT91_PIOB	1
+#define AT91_PIOC	2
+#define AT91_PIOD	3
+#define AT91_PIOE	4
+
+#define AT91_PERIPH_GPIO	0
+#define AT91_PERIPH_A		1
+#define AT91_PERIPH_B		2
+#define AT91_PERIPH_C		3
+#define AT91_PERIPH_D		4
+
+#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
-- 
cgit v0.10.2


From 01648f324df32aa2ec152b220bbd74a8511174d3 Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Thu, 5 May 2016 07:28:13 -0600
Subject: arm: at91: Add a header file for the real-time clock
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add register definitions for the AT91 RTC so that this can potentially be
used in U-Boot.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
new file mode 100644
index 0000000..73070e3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Real Time Clock (RTC) - System peripheral registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_RTC_H
+#define AT91_RTC_H
+
+/* Control Register */
+#define AT91_RTC_CR		(ATMEL_BASE_RTC + 0x00)
+#define AT91_RTC_UPDTIM		(1 <<  0)	/* Update Request Time */
+#define AT91_RTC_UPDCAL		(1 <<  1)	/* Update Request Calendar */
+#define AT91_RTC_TIMEVSEL	(3 <<  8)	/* Time Event Selection */
+#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
+#define AT91_RTC_TIMEVSEL_HOUR	(1 << 8)
+#define AT91_RTC_TIMEVSEL_DAY24	(2 << 8)
+#define AT91_RTC_TIMEVSEL_DAY12	(3 << 8)
+#define AT91_RTC_CALEVSEL	(3 << 16)	/* Calendar Event Selection */
+#define AT91_RTC_CALEVSEL_WEEK	(0 << 16)
+#define AT91_RTC_CALEVSEL_MONTH	(1 << 16)
+#define AT91_RTC_CALEVSEL_YEAR	(2 << 16)
+
+#define AT91_RTC_MR		(ATMEL_BASE_RTC + 0x04)	/* Mode Register */
+#define AT91_RTC_HRMOD		(1 <<  0)		/* 12/24 Hour Mode */
+
+#define AT91_RTC_TIMR		(ATMEL_BASE_RTC + 0x08)	/* Time Register */
+#define AT91_RTC_SEC		(0x7f <<  0)		/* Current Second */
+#define AT91_RTC_MIN		(0x7f <<  8)		/* Current Minute */
+#define AT91_RTC_HOUR		(0x3f << 16)		/* Current Hour */
+#define AT91_RTC_AMPM		(1    << 22)		/* AM/PM */
+
+#define AT91_RTC_CALR		(ATMEL_BASE_RTC + 0x0c)	/* Calendar Register */
+#define AT91_RTC_CENT		(0x7f <<  0)		/* Current Century */
+#define AT91_RTC_YEAR		(0xff <<  8)		/* Current Year */
+#define AT91_RTC_MONTH		(0x1f << 16)		/* Current Month */
+#define AT91_RTC_DAY		(7    << 21)		/* Current Day */
+#define AT91_RTC_DATE		(0x3f << 24)		/* Current Date */
+
+#define AT91_RTC_TIMALR		(ATMEL_BASE_RTC + 0x10)	/* Time Alarm */
+#define AT91_RTC_SECEN		(1 <<  7)		/* Second Alarm Enab */
+#define AT91_RTC_MINEN		(1 << 15)		/* Minute Alarm Enab */
+#define AT91_RTC_HOUREN		(1 << 23)		/* Hour Alarm Enable */
+
+#define AT91_RTC_CALALR		(ATMEL_BASE_RTC + 0x14)	/* Calendar Alarm */
+#define AT91_RTC_MTHEN		(1 << 23)		/* Month Alarm Enable */
+#define AT91_RTC_DATEEN		(1 << 31)		/* Date Alarm Enable */
+
+#define AT91_RTC_SR		(ATMEL_BASE_RTC + 0x18)	/* Status Register */
+#define AT91_RTC_ACKUPD		(1 <<  0)		/* Ack for Update */
+#define AT91_RTC_ALARM		(1 <<  1)		/* Alarm Flag */
+#define AT91_RTC_SECEV		(1 <<  2)		/* Second Event */
+#define AT91_RTC_TIMEV		(1 <<  3)		/* Time Event */
+#define AT91_RTC_CALEV		(1 <<  4)		/* Calendar Event */
+
+#define AT91_RTC_SCCR		(ATMEL_BASE_RTC + 0x1c)	/* Status Clear Cmd */
+#define AT91_RTC_IER		(ATMEL_BASE_RTC + 0x20)	/* Interrupt Enable */
+#define AT91_RTC_IDR		(ATMEL_BASE_RTC + 0x24)	/* Interrupt Disable */
+#define AT91_RTC_IMR		(ATMEL_BASE_RTC + 0x28)	/* Interrupt Mask */
+
+#define AT91_RTC_VER		(ATMEL_BASE_RTC + 0x2c)	/* Valid Entry */
+#define AT91_RTC_NVTIM		(1 <<  0)		/* Non-valid Time */
+#define AT91_RTC_NVCAL		(1 <<  1)		/* Non-valid Calendar */
+#define AT91_RTC_NVTIMALR	(1 <<  2)		/* .. Time Alarm */
+#define AT91_RTC_NVCALALR	(1 <<  3)		/* .. Calendar Alarm */
+
+#endif
-- 
cgit v0.10.2


From 5a9ae333161902475b14c7722208082c1ac28cff Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Thu, 5 May 2016 07:28:14 -0600
Subject: at91: Correct NAND ECC register access
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This uses the wrote base register value. Fix it.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 75e8307..debf933 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -24,9 +24,9 @@
 
 /* Register access macros */
 #define ecc_readl(add, reg)				\
-	readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+	readl(add + ATMEL_ECC_##reg)
 #define ecc_writel(add, reg, value)			\
-	writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+	writel((value), add + ATMEL_ECC_##reg)
 
 #include "atmel_nand_ecc.h"	/* Hardware ECC registers */
 
-- 
cgit v0.10.2


From 65319f15ca6ed1be6ca12576fe96a338352d45b7 Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Thu, 5 May 2016 07:28:15 -0600
Subject: at91: nand: Set up the ECC strength correctly
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This needs to be set to avoid a fatal error when ECC is used.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index debf933..ad5ded3 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1156,6 +1156,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
 	nand->ecc.hwctl = atmel_nand_hwctl;
 	nand->ecc.read_page = atmel_nand_read_page;
 	nand->ecc.bytes = 4;
+	nand->ecc.strength = 4;
 
 	if (nand->ecc.mode == NAND_ECC_HW) {
 		/* ECC is calculated for the whole page (1 step) */
-- 
cgit v0.10.2


From b3ab0fc7dda96d1bb5e7315edef3741fce0140b8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:17 -0600
Subject: at91: Add driver-model GPIO devices for AT91SAM9G45
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add these definitions so that GPIOs can be used with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
index 0d83426..eddfdb0 100644
--- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
@@ -165,3 +166,20 @@ void at91_mci_hw_init(void)
 	at91_periph_clk_enable(ATMEL_ID_MCI0);
 }
 #endif
+
+/* Platform data for the GPIOs */
+static const struct at91_port_platdata at91sam9260_plat[] = {
+	{ ATMEL_BASE_PIOA, "PA" },
+	{ ATMEL_BASE_PIOB, "PB" },
+	{ ATMEL_BASE_PIOC, "PC" },
+	{ ATMEL_BASE_PIOD, "PD" },
+	{ ATMEL_BASE_PIOE, "PE" },
+};
+
+U_BOOT_DEVICES(at91sam9260_gpios) = {
+	{ "gpio_at91", &at91sam9260_plat[0] },
+	{ "gpio_at91", &at91sam9260_plat[1] },
+	{ "gpio_at91", &at91sam9260_plat[2] },
+	{ "gpio_at91", &at91sam9260_plat[3] },
+	{ "gpio_at91", &at91sam9260_plat[4] },
+};
-- 
cgit v0.10.2


From 88a7fffe382b9640099db4d655a36a3a0c68692d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= <andreas@biessmann.org>
Date: Sat, 4 Jun 2016 22:27:22 +0200
Subject: linux/compat.h: add dev_warn()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In order to prevent build errors for copied code from linux introduce
dev_warn().

Suggested-by: Scott Wood <oss@buserror.net>
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/include/linux/compat.h b/include/linux/compat.h
index e561ee3..7236b8d 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -25,6 +25,8 @@ extern struct p_current *current;
 	printf(fmt, ##args)
 #define dev_err(dev, fmt, args...)		\
 	printf(fmt, ##args)
+#define dev_warn(dev, fmt, args...)		\
+	printf(fmt, ##args)
 #define printk	printf
 #define printk_once	printf
 
-- 
cgit v0.10.2


From d63ec26a49a1ae8c0fd65c24e8c0b6c67b79cd01 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:19 -0600
Subject: at91: video: Prepare for driver-model conversion
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Adjust the driver to use struct display_timing for its display timing.
This is what is used by driver-model and allows the LCD init code to be
common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index d43d8a5..37838a8 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -91,39 +92,41 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
 	}
 }
 
-void lcd_ctrl_init(void *lcdbase)
+static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
+			  bool tft, bool cont_pol_low, ulong lcdbase)
 {
 	unsigned long value;
+	void *reg = (void *)addr;
 
 	/* Turn off the LCD controller and the DMA controller */
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+	lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 		    ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 
 	/* Wait for the LCDC core to become idle */
-	while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+	while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
 		udelay(10);
 
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
+	lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 
 	/* Reset LCDC DMA */
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
+	lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 
 	/* ...set frame size and burst length = 8 words (?) */
-	value = (panel_info.vl_col * panel_info.vl_row *
-		 NBITS(panel_info.vl_bpix)) / 32;
+	value = (timing->hactive.typ * timing->vactive.typ *
+		 (1 << bpix)) / 32;
 	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
+	lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 
 	/* Set pixel clock */
-	value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
-	if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
+	value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
+	if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
 		value++;
 	value = (value / 2) - 1;
 
 	if (!value) {
-		lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+		lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 	} else
-		lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
+		lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
 			    value << ATMEL_LCDC_CLKVAL_OFFSET);
 
 	/* Initialize control register 2 */
@@ -132,56 +135,87 @@ void lcd_ctrl_init(void *lcdbase)
 #else
 	value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 #endif
-	if (panel_info.vl_tft)
+	if (tft)
 		value |= ATMEL_LCDC_DISTYPE_TFT;
 
-	value |= panel_info.vl_sync;
-	value |= (panel_info.vl_bpix << 5);
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
+	if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
+		value |= ATMEL_LCDC_INVLINE_INVERTED;
+	if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
+		value |= ATMEL_LCDC_INVFRAME_INVERTED;
+	value |= bpix << 5;
+	lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 
 	/* Vertical timing */
-	value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
-	value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
-	value |= panel_info.vl_lower_margin;
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
+	value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
+	value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
+	value |= timing->vfront_porch.typ;
+	/* Magic! (Datasheet says "Bit 31 must be written to 1") */
+	value |= 1U << 31;
+	lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 
 	/* Horizontal timing */
-	value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
-	value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
-	value |= (panel_info.vl_left_margin - 1);
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
+	value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
+	value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
+	value |= (timing->hback_porch.typ - 1);
+	lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 
 	/* Display size */
-	value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
-	value |= panel_info.vl_row - 1;
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
+	value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+	value |= timing->vactive.typ - 1;
+	lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 
 	/* FIFO Threshold: Use formula from data sheet */
 	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
+	lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 
 	/* Toggle LCD_MODE every frame */
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
+	lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 
 	/* Disable all interrupts */
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
+	lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 
 	/* Set contrast */
 	value = ATMEL_LCDC_PS_DIV8 |
 		ATMEL_LCDC_ENA_PWMENABLE;
-	if (!panel_info.vl_cont_pol_low)
+	if (!cont_pol_low)
 		value |= ATMEL_LCDC_POL_POSITIVE;
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+	lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
+	lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 
 	/* Set framebuffer DMA base address and pixel offset */
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
+	lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
-	lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+	lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
+	lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 		    (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 }
 
+void lcd_ctrl_init(void *lcdbase)
+{
+	struct display_timing timing;
+
+	timing.flags = 0;
+	if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
+		timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+	if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
+		timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
+	timing.pixelclock.typ = panel_info.vl_clk;
+
+	timing.hactive.typ = panel_info.vl_col;
+	timing.hfront_porch.typ = panel_info.vl_right_margin;
+	timing.hback_porch.typ = panel_info.vl_left_margin;
+	timing.hsync_len.typ = panel_info.vl_hsync_len;
+
+	timing.vactive.typ = panel_info.vl_row;
+	timing.vfront_porch.typ = panel_info.vl_clk;
+	timing.vback_porch.typ = panel_info.vl_clk;
+	timing.vsync_len.typ = panel_info.vl_clk;
+
+	atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
+		      panel_info.vl_tft, panel_info.vl_cont_pol_low,
+		      (ulong)lcdbase);
+}
+
 ulong calc_fbsize(void)
 {
 	return ((panel_info.vl_col * panel_info.vl_row *
-- 
cgit v0.10.2


From 9dc89a053d29deea73c39ef49c9f1c6cb4c38820 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:20 -0600
Subject: at91: video: Support driver-model for the LCD driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add driver-model support to this driver. Most features can be controlled
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 37838a8..39cd7ca 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -7,7 +7,10 @@
  */
 
 #include <common.h>
+#include <atmel_lcd.h>
+#include <dm.h>
 #include <fdtdec.h>
+#include <video.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -15,6 +18,21 @@
 #include <bmp_layout.h>
 #include <atmel_lcdc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_VIDEO
+enum {
+	/* Maximum LCD size we support */
+	LCD_MAX_WIDTH		= 1366,
+	LCD_MAX_HEIGHT		= 768,
+	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
+};
+#endif
+
+struct atmel_fb_priv {
+	struct display_timing timing;
+};
+
 /* configurable parameters */
 #define ATMEL_LCDC_CVAL_DEFAULT		0xc8
 #define ATMEL_LCDC_DMA_BURST_LEN	8
@@ -31,6 +49,7 @@
 #define lcdc_readl(mmio, reg)		__raw_readl((mmio)+(reg))
 #define lcdc_writel(mmio, reg, val)	__raw_writel((val), (mmio)+(reg))
 
+#ifndef CONFIG_DM_VIDEO
 ushort *configuration_get_cmap(void)
 {
 	return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
@@ -91,6 +110,7 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
 		lcd_setcolreg(i, cte.red, cte.green, cte.blue);
 	}
 }
+#endif
 
 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
 			  bool tft, bool cont_pol_low, ulong lcdbase)
@@ -190,6 +210,7 @@ static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
 		    (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 }
 
+#ifndef CONFIG_DM_VIDEO
 void lcd_ctrl_init(void *lcdbase)
 {
 	struct display_timing timing;
@@ -221,3 +242,73 @@ ulong calc_fbsize(void)
 	return ((panel_info.vl_col * panel_info.vl_row *
 		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 }
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static int atmel_fb_lcd_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct atmel_fb_priv *priv = dev_get_priv(dev);
+	struct display_timing *timing = &priv->timing;
+
+	/*
+	 * For now some values are hard-coded. We could use the device tree
+	 * bindings in simple-framebuffer.txt to specify the format/bpp and
+	 * some Atmel-specific binding for tft and cont_pol_low.
+	 */
+	atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
+		      uc_plat->base);
+	uc_priv->xsize = timing->hactive.typ;
+	uc_priv->ysize = timing->vactive.typ;
+	uc_priv->bpix = VIDEO_BPP16;
+	video_set_flush_dcache(dev, true);
+	debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
+	      uc_plat->size, uc_priv->xsize, uc_priv->ysize);
+
+	return 0;
+}
+
+static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
+{
+	struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+	struct atmel_fb_priv *priv = dev_get_priv(dev);
+	struct display_timing *timing = &priv->timing;
+	const void *blob = gd->fdt_blob;
+
+	if (fdtdec_decode_display_timing(blob, dev->of_offset,
+					 plat->timing_index, timing)) {
+		debug("%s: Failed to decode display timing\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int atmel_fb_lcd_bind(struct udevice *dev)
+{
+	struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+
+	uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+			(1 << VIDEO_BPP16) / 8;
+	debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+	return 0;
+}
+
+static const struct udevice_id atmel_fb_lcd_ids[] = {
+	{ .compatible = "atmel,at91sam9g45-lcdc" },
+	{ }
+};
+
+U_BOOT_DRIVER(atmel_fb) = {
+	.name	= "atmel_fb",
+	.id	= UCLASS_VIDEO,
+	.of_match = atmel_fb_lcd_ids,
+	.bind	= atmel_fb_lcd_bind,
+	.ofdata_to_platdata	= atmel_fb_ofdata_to_platdata,
+	.probe	= atmel_fb_lcd_probe,
+	.platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
+	.priv_auto_alloc_size	= sizeof(struct atmel_fb_priv),
+};
+#endif
diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h
index 6993128..8a2f46f 100644
--- a/include/atmel_lcd.h
+++ b/include/atmel_lcd.h
@@ -10,6 +10,15 @@
 #ifndef _ATMEL_LCD_H_
 #define _ATMEL_LCD_H_
 
+/**
+ * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ *
+ * @timing_index:	Index of LCD timing to use in device tree node
+ */
+struct atmel_lcd_platdata {
+	int timing_index;
+};
+
 typedef struct vidinfo {
 	ushort vl_col;		/* Number of columns (i.e. 640) */
 	ushort vl_row;		/* Number of rows (i.e. 480) */
-- 
cgit v0.10.2


From 04b9dd10cc11e4f603a2bae9cf4cc21af1229534 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 5 May 2016 07:28:21 -0600
Subject: fdt: Correct return value in fdtdec_decode_display_timing()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This should return a non-zero value if there is a missing property. Update
the return value accordingly. The only expected error is -FDT_ERR_NOTFOUND.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index ab002e9..686b89d 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1170,7 +1170,7 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
 	if (fdtdec_get_bool(blob, node, "doubleclk"))
 		dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
 
-	return 0;
+	return ret;
 }
 
 int fdtdec_setup(void)
-- 
cgit v0.10.2


From 885fc03aab946d3c0a842aaf32f9513e3a7c8c20 Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Thu, 5 May 2016 07:28:22 -0600
Subject: arm: at91: Add support for gurnard
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and
128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and
two UARTs.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[apply CONFIG_BOOTDELAY transition]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/dts/at91sam9g45-gurnard.dts b/arch/arm/dts/at91sam9g45-gurnard.dts
new file mode 100644
index 0000000..75c1e99
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45-gurnard.dts
@@ -0,0 +1,157 @@
+/*
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9g45.dtsi"
+
+/ {
+	model = "Bluewater Systems Gurnard";
+	compatible = "atmel,at91sam9g45", "atmel,at91sam9";
+
+	chosen {
+		bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x20000000 0x8000000>;
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <18432000>;
+		};
+	};
+
+	ahb {
+		u-boot,dm-pre-reloc;
+
+		fb@0x00500000 {
+			u-boot,dm-pre-reloc;
+			status = "okay";
+			display-timings {
+				rev1 {
+					clock-frequency = <4166666>;
+					hactive = <480>;
+					vactive = <272>;
+					hfront-porch = <1>;
+					hback-porch = <1>;
+					hsync-len = <1>;
+					vback-porch = <4>;
+					vfront-porch = <2>;
+					vsync-len = <1>;
+					hsync-active = <0>;
+					vsync-active = <0>;
+				};
+
+				rev2 {
+					clock-frequency = <4166666>;
+					hactive = <480>;
+					vactive = <272>;
+					hfront-porch = <2>;
+					hback-porch = <2>;
+					hsync-len = <10>;
+					vback-porch = <2>;
+					vfront-porch = <2>;
+					vsync-len = <10>;
+					hsync-active = <0>;
+					vsync-active = <0>;
+				};
+			};
+		};
+
+		apb {
+			pinctrl@fffff400 {
+				board {
+					pinctrl_pck0_as_mck: pck0_as_mck {
+						atmel,pins =
+							<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC1 periph B */
+					};
+
+				};
+
+				mmc0_slot1 {
+					pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+						atmel,pins =
+							<AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;	/* PC9 gpio CD pin pull up and deglitch */
+					};
+				};
+			};
+
+			dbgu: serial@ffffee00 {
+				status = "okay";
+			};
+
+			macb0: ethernet@fffbc000 {
+				phy-mode = "rmii";
+				status = "okay";
+			};
+
+			mmc0: mmc@fff80000 {
+				pinctrl-0 = <
+					&pinctrl_board_mmc0_slot1
+					&pinctrl_mmc0_slot0_clk_cmd_dat0
+					&pinctrl_mmc0_slot0_dat1_3>;
+				status = "okay";
+				slot@1 {
+					reg = <1>;
+					bus-width = <4>;
+					cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
+				};
+			};
+
+			ssc0: ssc@fff9c000 {
+				status = "okay";
+				pinctrl-0 = <&pinctrl_ssc0_tx>;
+			};
+
+			spi0: spi@fffa4000 {
+				cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+				mtd_dataflash@0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					spi-max-frequency = <50000000>;
+					reg = <1>;
+				};
+			};
+
+			shdwc@fffffd10 {
+				atmel,wakeup-counter = <10>;
+				atmel,wakeup-rtt-timer;
+			};
+
+			rtc@fffffd20 {
+				atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+				status = "okay";
+			};
+
+			watchdog@fffffd40 {
+				status = "okay";
+			};
+
+			gpbr: syscon@fffffd60 {
+				status = "okay";
+			};
+		};
+
+		nand0: nand@40000000 {
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hardware";
+			nand-on-flash-bbt;
+			status = "okay";
+		};
+
+		usb1: ehci@00800000 {
+			atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+			status = "okay";
+		};
+	};
+
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 73a9c74..6180699 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -23,6 +23,14 @@ config TARGET_SNAPPER9260
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_GURNARD
+	bool "Support gurnard"
+	select CPU_ARM926EJS
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select DM_ETH
+
 config TARGET_AT91SAM9261EK
 	bool "Atmel at91sam9261 reference board"
 	select CPU_ARM926EJS
@@ -149,6 +157,7 @@ source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
 source "board/atmel/sama5d4_xplained/Kconfig"
 source "board/atmel/sama5d4ek/Kconfig"
+source "board/bluewater/gurnard/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
 source "board/denx/ma5d4evk/Kconfig"
diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig
new file mode 100644
index 0000000..e2cd9f0
--- /dev/null
+++ b/board/bluewater/gurnard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GURNARD
+
+config SYS_BOARD
+	default "gurnard"
+
+config SYS_VENDOR
+	default "bluewater"
+
+config SYS_CONFIG_NAME
+	default "snapper9g45"
+
+endif
diff --git a/board/bluewater/gurnard/MAINTAINERS b/board/bluewater/gurnard/MAINTAINERS
new file mode 100644
index 0000000..5e546d4
--- /dev/null
+++ b/board/bluewater/gurnard/MAINTAINERS
@@ -0,0 +1,6 @@
+GURNARD BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/bluewater/gurnard/
+F:	include/configs/snapper9g45.h
+F:	configs/gurnard_defconfig
diff --git a/board/bluewater/gurnard/Makefile b/board/bluewater/gurnard/Makefile
new file mode 100644
index 0000000..f646d35
--- /dev/null
+++ b/board/bluewater/gurnard/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= gurnard.o
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
new file mode 100644
index 0000000..2a36d29
--- /dev/null
+++ b/board/bluewater/gurnard/gurnard.c
@@ -0,0 +1,449 @@
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#include <dm.h>
+#include <lcd.h>
+#include <net.h>
+#ifndef CONFIG_DM_ETH
+#include <netdev.h>
+#endif
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_emac.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_rtc.h>
+#include <asm/arch/at91_sck.h>
+#include <asm/arch/atmel_serial.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <dm/uclass-internal.h>
+
+#ifdef CONFIG_GURNARD_SPLASH
+#include "splash_logo.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET	(0 << 1)
+#define IO_EXP_ETH_POWER	(1 << 1)
+
+#ifdef CONFIG_MACB
+static void gurnard_macb_hw_init(void)
+{
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+	/*
+	 * Enable pull-up on:
+	 *	RXDV (PA12) => MODE0 - PHY also has pull-up
+	 *	ERX0 (PA13) => MODE1 - PHY also has pull-up
+	 *	ERX1 (PA15) => MODE2 - PHY also has pull-up
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->puer);
+
+	at91_phy_reset();
+
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static int gurnard_nand_hw_init(void)
+{
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	ulong flags;
+	int ret;
+
+	/* Enable CS3 as NAND/SmartMedia */
+	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+#ifdef CONFIG_SYS_NAND_DBW_16
+	flags = AT91_SMC_MODE_DBW_16;
+#else
+	flags = AT91_SMC_MODE_DBW_8;
+#endif
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       flags |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+	if (ret)
+		return ret;
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+	if (ret)
+		return ret;
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GURNARD_SPLASH
+static void lcd_splash(int width, int height)
+{
+	u16 colour;
+	int x, y;
+	u16 *base_addr = (u16 *)gd->video_bottom;
+
+	memset(base_addr, 0xff, width * height * 2);
+	/*
+	 * Blit the logo to the center of the screen
+	 */
+	for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
+		for (x = 0; x < BMP_LOGO_WIDTH; x++) {
+			int posx, posy;
+			colour = bmp_logo_palette[bmp_logo_bitmap[
+			    y * BMP_LOGO_WIDTH + x]];
+			posx = x + (width - BMP_LOGO_WIDTH) / 2;
+			posy = y;
+			base_addr[posy * width + posx] = colour;
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static void at91sam9g45_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+/**
+ * Initialise the memory bus settings so that we can talk to the
+ * memory mapped FPGA
+ */
+static int fpga_hw_init(void)
+{
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	int i;
+
+	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
+
+	at91_set_a_periph(2, 4, 0); /* EBIA21 */
+	at91_set_a_periph(2, 5, 0); /* EBIA22 */
+	at91_set_a_periph(2, 6, 0); /* EBIA23 */
+	at91_set_a_periph(2, 7, 0); /* EBIA24 */
+	at91_set_a_periph(2, 12, 0); /* EBIA25 */
+	for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
+		at91_set_a_periph(2, i, 0);
+
+	/* configure SMC cs0 for FPGA access timing */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
+	       AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
+	       &smc->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+	       &smc->cs[0].cycle);
+	writel(AT91_SMC_MODE_BAT |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_32 |
+	       AT91_SMC_MODE_TDF |
+	       AT91_SMC_MODE_TDF_CYCLE(2),
+	       &smc->cs[0].mode);
+
+	/* Do a write to within EBI_CS1 to enable the SDCK */
+	writel(0, ATMEL_BASE_CS1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+
+#define USB0_ENABLE_PIN		AT91_PIN_PB22
+#define USB1_ENABLE_PIN		AT91_PIN_PB23
+
+void gurnard_usb_init(void)
+{
+	at91_set_gpio_output(USB0_ENABLE_PIN, 1);
+	at91_set_gpio_value(USB0_ENABLE_PIN, 0);
+	at91_set_gpio_output(USB1_ENABLE_PIN, 1);
+	at91_set_gpio_value(USB1_ENABLE_PIN, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int cpu_mmc_init(bd_t *bis)
+{
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+static void gurnard_enable_console(int enable)
+{
+	at91_set_gpio_output(AT91_PIN_PB14, 1);
+	at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
+}
+
+void at91sam9g45_slowclock_init(void)
+{
+	/*
+	 * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
+	 * internal impreciseRC oscillator or an external 32kHz oscillator.
+	 * Switch to the latter.
+	 */
+	unsigned i, tmp;
+	ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
+
+	tmp = readl(reg);
+	if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
+		timer_init();
+		tmp |= AT91SAM9G45_SCKCR_OSC32EN;
+		writel(tmp, reg);
+		for (i = 0; i < 1200; i++)
+			udelay(1000);
+		tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
+		writel(tmp, reg);
+		udelay(200);
+		tmp &= ~AT91SAM9G45_SCKCR_RCEN;
+		writel(tmp, reg);
+	}
+}
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	gurnard_enable_console(1);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	const char *rev_str;
+#ifdef CONFIG_CMD_NAND
+	int ret;
+#endif
+
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+	at91sam9g45_slowclock_init();
+
+	/*
+	 * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
+	 * boots with spurious IRQs.
+	 */
+	writel(0xffffffff, AT91_RTC_IDR);
+
+	/* Make sure that the reset signal is attached properly */
+	setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
+
+	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	ret = gurnard_nand_hw_init();
+	if (ret)
+		return ret;
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+	gurnard_macb_hw_init();
+#endif
+
+#ifdef CONFIG_GURNARD_FPGA
+	fpga_hw_init();
+#endif
+
+#ifdef CONFIG_CMD_USB
+	gurnard_usb_init();
+#endif
+
+#ifdef CONFIG_CMD_MMC
+	at91_set_A_periph(AT91_PIN_PA12, 0);
+	at91_set_gpio_output(AT91_PIN_PA8, 1);
+	at91_set_gpio_value(AT91_PIN_PA8, 0);
+	at91_mci_hw_init();
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+	at91sam9g45_lcd_hw_init();
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+
+	/* Select the second timing index for board rev 2 */
+	rev_str = getenv("board_rev");
+	if (rev_str && !strncmp(rev_str, "2", 1)) {
+		struct udevice *dev;
+
+		uclass_find_first_device(UCLASS_VIDEO, &dev);
+		if (dev) {
+			struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+
+			plat->timing_index = 1;
+		}
+	}
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u_int8_t env_enetaddr[8];
+	char *env_str;
+	char *end;
+	int i;
+
+	/*
+	 * Set MAC address so we do not need to init Ethernet before Linux
+	 * boot
+	 */
+	env_str = getenv("ethaddr");
+	if (env_str) {
+		struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
+		/* Parse MAC address */
+		for (i = 0; i < 6; i++) {
+			env_enetaddr[i] = env_str ?
+				simple_strtoul(env_str, &end, 16) : 0;
+			if (env_str)
+				env_str = (*end) ? end+1 : end;
+		}
+
+		/* Set hardware address */
+		writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
+		       env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
+		       &emac->sa2l);
+		writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
+
+		printf("MAC:   %s\n", getenv("ethaddr"));
+	} else {
+		/* Not set in environment */
+		printf("MAC:   not set\n");
+	}
+#ifdef CONFIG_GURNARD_SPLASH
+	lcd_splash(480, 272);
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+int board_eth_init(bd_t *bis)
+{
+	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+void reset_phy(void)
+{
+}
+
+/* This breaks the Ethernet MAC at present */
+void enable_caches(void)
+{
+	dcache_enable();
+}
+
+/* SPI chip select control - only used for FPGA programming */
+#ifdef CONFIG_ATMEL_SPI
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* We don't use chipselects for FPGA programming */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	/* We don't use chipselects for FPGA programming */
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.platdata = &at91sam9260_serial_plat,
+};
diff --git a/board/bluewater/gurnard/splash_logo.h b/board/bluewater/gurnard/splash_logo.h
new file mode 100644
index 0000000..fb87dea
--- /dev/null
+++ b/board/bluewater/gurnard/splash_logo.h
@@ -0,0 +1,2619 @@
+/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/
+#ifndef __BMP_LOGO_H__
+#define __BMP_LOGO_H__
+#define BMP_LOGO_WIDTH 187
+#define BMP_LOGO_HEIGHT 139
+#define BMP_LOGO_COLORS 255
+#define BMP_LOGO_OFFSET 50
+
+unsigned short bmp_logo_palette[] = {
+	0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e,
+	0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7,
+	0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf,
+	0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d,
+	0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410,
+	0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe,
+	0xffff, 0xef3c, };
+
+unsigned char bmp_logo_bitmap[] = {
+	0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
+	0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005,
+	0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+	0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005,
+	0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0006, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
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+	0x002d, 0x0022, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x001f,
+	0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
+	0x000e, 0x000e, 0x0009, };
+#endif
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
new file mode 100644
index 0000000..80f0013
--- /dev/null
+++ b/configs/gurnard_defconfig
@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_GURNARD=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_BOOTDELAY=3
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
new file mode 100644
index 0000000..ddfbcec
--- /dev/null
+++ b/include/configs/snapper9g45.h
@@ -0,0 +1,155 @@
+/*
+ * Bluewater Systems Snapper 9G45 module
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x73f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+/* CPU */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM + 0x1000 - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_SYS_NAND_ECC_BASE	ATMEL_BASE_ECC
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC8
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#define CONFIG_PARTITION_UUIDS
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+
+/* LCD */
+#define CONFIG_ATMEL_LCD
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_GURNARD_SPLASH
+
+#define CONFIG_ATMEL_SPI
+
+/* GPIOs and IO expander */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP		1
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_BAUDRATE			115200
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR		0x23000000
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Environment settings */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SIZE			(256 << 10)
+#define CONFIG_ENV_OVERWRITE
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:00:00:00:00:00\0" \
+	"serial=0\0" \
+	"stdout=serial_atmel\0" \
+	"stderr=serial_atmel\0" \
+	"stdin=serial_atmel\0" \
+	"bootlimit=3\0" \
+	"loadaddr=0x71000000\0" \
+	"board_rev=2\0" \
+	"bootfile=/tftpboot/uImage\0" \
+	"bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
+	"nfsroot=/export/root\0" \
+	"boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
+	"boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
+	"boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
+	"boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+	"boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+	"bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
+	"altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
+
+/* Console settings */
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+
+/* Command line configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PART
+
+#endif /* __CONFIG_H */
-- 
cgit v0.10.2


From 1c24f13f694e94650211607dc0365d654577e259 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 14 May 2016 23:43:01 +0200
Subject: ARM: at91: sama5: Extend boot device autodetection
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Extend the boot device autodetection from SAMA5D2 only to the entire
SAMA5Dx family of microcontrollers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[minor compile fix for SAMA5D2]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d2abf31..a908004 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,8 +10,8 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
-obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
+obj-$(CONFIG_SAMA5D3) += bootparams_atmel.o mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
 endif
 
diff --git a/arch/arm/mach-at91/include/mach/sama5_boot.h b/arch/arm/mach-at91/include/mach/sama5_boot.h
new file mode 100644
index 0000000..8911a44
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5_boot.h
@@ -0,0 +1,25 @@
+/*
+ * Boot mode definitions for the SAMA5Dx SoC
+ *
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SAMA5_BOOT_H
+#define __SAMA5_BOOT_H
+
+/* Boot modes stored by BootROM in r4 */
+#define ATMEL_SAMA5_BOOT_FROM_OFF	0
+#define ATMEL_SAMA5_BOOT_FROM_MASK	0xf
+#define ATMEL_SAMA5_BOOT_FROM_SPI	(0 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_MCI	(1 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_SMC	(2 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_TWI	(3 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_QSPI	(4 << 0)
+#define ATMEL_SAMA5_BOOT_FROM_SAMBA	(7 << 0)
+
+#define ATMEL_SAMA5_BOOT_DEV_ID_OFF	4
+#define ATMEL_SAMA5_BOOT_DEV_ID_MASK	0xf
+
+#endif /* __SAMA5_BOOT_H */
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index ee841da..25c8541 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -230,18 +230,6 @@
 /* No PMECC Galois table in ROM */
 #define NO_GALOIS_TABLE_IN_ROM
 
-/* Boot modes stored by BootROM in r4 */
-#define ATMEL_SAMA5D2_BOOT_FROM_OFF	0
-#define ATMEL_SAMA5D2_BOOT_FROM_MASK	0xf
-#define ATMEL_SAMA5D2_BOOT_FROM_SPI	(0 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_MCI	(1 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_SMC	(2 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_TWI	(3 << 0)
-#define ATMEL_SAMA5D2_BOOT_FROM_QSPI	(4 << 0)
-
-#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF	4
-#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK	0xf
-
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
 unsigned int get_extension_chip_id(void);
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index c4ed224..f255b59 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -23,20 +23,22 @@ void at91_disable_wdt(void)
 }
 #endif
 
-#if defined(CONFIG_SAMA5D2)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+    defined(CONFIG_SAMA5D4)
+#include <asm/arch/sama5_boot.h>
 struct {
 	u32	r4;
 } bootrom_stash __attribute__((section(".data")));
 
 u32 spl_boot_device(void)
 {
-	u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) &
-		  ATMEL_SAMA5D2_BOOT_FROM_MASK;
-	u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) &
-		  ATMEL_SAMA5D2_BOOT_DEV_ID_MASK;
+	u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5_BOOT_FROM_OFF) &
+		  ATMEL_SAMA5_BOOT_FROM_MASK;
+	u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5_BOOT_DEV_ID_OFF) &
+		  ATMEL_SAMA5_BOOT_DEV_ID_MASK;
 
 #if defined(CONFIG_SYS_USE_MMC)
-	if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) {
+	if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) {
 		if (off == 0)
 			return BOOT_DEVICE_MMC1;
 		if (off == 1)
@@ -47,10 +49,13 @@ u32 spl_boot_device(void)
 #endif
 
 #if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
-	if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI)
+	if (dev == ATMEL_SAMA5_BOOT_FROM_SPI)
 		return BOOT_DEVICE_SPI;
 #endif
 
+	if (dev == ATMEL_SAMA5_BOOT_FROM_SAMBA)
+		return BOOT_DEVICE_USB;
+
 	printf("ERROR: SMC/TWI/QSPI boot device not supported!\n"
 	       "       Boot device %i, controller number %i\n", dev, off);
 
-- 
cgit v0.10.2


From d3b6662086de317e0495edf9c4670772bff98211 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 14 May 2016 23:43:19 +0200
Subject: ARM: at91: Fix PMC bit definitions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add missing parenthesis around the variable into the macro.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 7684f09..680ceb0 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -67,18 +67,18 @@ typedef struct at91_pmc {
 #define AT91_PMC_MOR_MOSCEN		0x01
 #define AT91_PMC_MOR_OSCBYPASS		0x02
 #define AT91_PMC_MOR_MOSCRCEN		0x08
-#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
-#define AT91_PMC_MOR_KEY(x)		((x & 0xff) << 16)
+#define AT91_PMC_MOR_OSCOUNT(x)		(((x) & 0xff) << 8)
+#define AT91_PMC_MOR_KEY(x)		(((x) & 0xff) << 16)
 #define AT91_PMC_MOR_MOSCSEL		(1 << 24)
 
-#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
-#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
-#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
+#define AT91_PMC_PLLXR_DIV(x)		((x) & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x)	(((x) & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x)		(((x) & 0x03) << 14)
 #if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
 	defined(CONFIG_SAMA5D4)
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
+#define AT91_PMC_PLLXR_MUL(x)		(((x) & 0x7F) << 18)
 #else
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#define AT91_PMC_PLLXR_MUL(x)		(((x) & 0x7FF) << 16)
 #endif
 #define AT91_PMC_PLLAR_29		0x20000000
 #define AT91_PMC_PLLBR_USBDIV_1		0x00000000
@@ -158,7 +158,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_PCR_CMD_WRITE		(0x1 << 12)
 #define AT91_PMC_PCR_DIV		(0x3 << 16)
 #define AT91_PMC_PCR_GCKDIV		(0xff << 20)
-#define		AT91_PMC_PCR_GCKDIV_(x)		((x & 0xff) << 20)
+#define		AT91_PMC_PCR_GCKDIV_(x)		(((x) & 0xff) << 20)
 #define		AT91_PMC_PCR_GCKDIV_OFFSET	20
 #define AT91_PMC_PCR_EN			(0x1 << 28)
 #define AT91_PMC_PCR_GCKEN		(0x1 << 29)
-- 
cgit v0.10.2


From c1631c8a04f53e694dd73bbb987b97eed5188517 Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Wed, 1 Jun 2016 08:36:56 +0800
Subject: serial: atmel_usart: Add device tree support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add device tree support.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 4fe992b..e450135 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -191,16 +191,35 @@ static int atmel_serial_probe(struct udevice *dev)
 {
 	struct atmel_serial_platdata *plat = dev->platdata;
 	struct atmel_serial_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	fdt_addr_t addr_base;
 
+	addr_base = dev_get_addr(dev);
+	if (addr_base == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	plat->base_addr = (uint32_t)addr_base;
+#endif
 	priv->usart = (atmel_usart3_t *)plat->base_addr;
 	atmel_serial_init_internal(priv->usart);
 
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id atmel_serial_ids[] = {
+	{ .compatible = "atmel,at91sam9260-usart" },
+	{ }
+};
+#endif
+
 U_BOOT_DRIVER(serial_atmel) = {
 	.name	= "serial_atmel",
 	.id	= UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	.of_match = atmel_serial_ids,
+	.platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
+#endif
 	.probe = atmel_serial_probe,
 	.ops	= &atmel_serial_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v0.10.2


From e423d17fccd8a8bd6f46aa69fe910e7cac77cd3b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:49 +0900
Subject: tools: moveconfig: fix --dry-run option

Since commit 96464badc794 ("moveconfig: Always run savedefconfig on
the moved config"), --dry-run option is broken.

The --dry-run option prevents the .config from being modified,
but defconfig files might be updated by "make savedefconfig"
regardless of the --dry-run option.

Move the "if not self.options.dry_run" conditional to the correct
place.

Fixes 96464badc794 ("moveconfig: Always run savedefconfig on the moved config")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 68631b7..fd98e41 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -511,11 +511,10 @@ class KconfigParser:
         # Print log in one shot to not mix up logs from different threads.
         print log,
 
-        if not self.options.dry_run:
-            with open(dotconfig_path, 'a') as f:
-                for (action, value) in results:
-                    if action == ACTION_MOVE:
-                        f.write(value + '\n')
+        with open(dotconfig_path, 'a') as f:
+            for (action, value) in results:
+                if action == ACTION_MOVE:
+                    f.write(value + '\n')
 
         os.remove(os.path.join(self.build_dir, 'include', 'config', 'auto.conf'))
         os.remove(autoconf_path)
@@ -647,9 +646,9 @@ class Slot:
             return False
 
         if self.state == STATE_SAVEDEFCONFIG:
-            defconfig_path = os.path.join(self.build_dir, 'defconfig')
-            shutil.move(defconfig_path,
-                        os.path.join('configs', self.defconfig))
+            if not self.options.dry_run:
+                shutil.move(os.path.join(self.build_dir, 'defconfig'),
+                            os.path.join('configs', self.defconfig))
             self.state = STATE_IDLE
             return True
 
-- 
cgit v0.10.2


From 6ff36d21746d61d7a2af08ea0bd973059d91d306 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:50 +0900
Subject: tools: moveconfig: rename update_defconfig() to update_dotconfig()

Commit 96464badc794 ("moveconfig: Always run savedefconfig on the
moved config") changed how defconfig files were updated.

Since then, the function update_defconfig() does not modify defconfig
files at all (instead, they are updated by "make savedefconfig"), so
update_dotconfig() is a better fit for this function.  Also, update
the comment block to match the actual behavior.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index fd98e41..9029287 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -459,13 +459,13 @@ class KconfigParser:
 
         return (action, value)
 
-    def update_defconfig(self, defconfig):
-        """Parse files for the config options and update the defconfig.
+    def update_dotconfig(self, defconfig):
+        """Parse files for the config options and update the .config.
 
         This function parses the given defconfig, the generated .config
         and include/autoconf.mk searching the target options.
-        Move the config option(s) to the defconfig or do nothing if unneeded.
-        Also, display the log to show what happened to this defconfig.
+        Move the config option(s) to the .config as needed.
+        Also, display the log to show what happened to the .config.
 
         Arguments:
           defconfig: defconfig name.
@@ -632,7 +632,7 @@ class Slot:
                 return True
 
         if self.state == STATE_AUTOCONF:
-            self.parser.update_defconfig(self.defconfig)
+            self.parser.update_dotconfig(self.defconfig)
 
             print ' %d defconfigs out of %d\r' % (self.num + 1, self.total),
             sys.stdout.flush()
-- 
cgit v0.10.2


From ff8725bbe06b3b890beb2044c02ef332c8d028b4 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:51 +0900
Subject: tools: moveconfig: remove redundant else: after sys.exit()

Nesting by "else:" is not generally useful after such statements
as return, break, sys.exit(), etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 9029287..1332bd2 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -623,13 +623,11 @@ class Slot:
                                                 COLOR_LIGHT_CYAN, errout)
             if self.options.exit_on_error:
                 sys.exit("Exit on error.")
-            else:
-                # If --exit-on-error flag is not set,
-                # skip this board and continue.
-                # Record the failed board.
-                self.failed_boards.append(self.defconfig)
-                self.state = STATE_IDLE
-                return True
+            # If --exit-on-error flag is not set, skip this board and continue.
+            # Record the failed board.
+            self.failed_boards.append(self.defconfig)
+            self.state = STATE_IDLE
+            return True
 
         if self.state == STATE_AUTOCONF:
             self.parser.update_dotconfig(self.defconfig)
-- 
cgit v0.10.2


From 4b430c983a57146633f1b9a9ca5ed7289215763f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:52 +0900
Subject: tools: moveconfig: check directory location before compilers

We must ensure this tool is run from the top of source directory
before calling update_cross_compile().  Otherwise, the following
exception is thrown:

Traceback (most recent call last):
  File "./moveconfig.py", line 918, in <module>
    main()
  File "./moveconfig.py", line 908, in main
    update_cross_compile()
  File "./moveconfig.py", line 292, in update_cross_compile
    for arch in os.listdir('arch'):
OSError: [Errno 2] No such file or directory: 'arch'

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 1332bd2..ce8245a 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -905,10 +905,10 @@ def main():
 
     config_attrs = parse_recipe(args[0])
 
-    update_cross_compile()
-
     check_top_directory()
 
+    update_cross_compile()
+
     if not options.cleanup_headers_only:
         move_config(config_attrs, options)
 
-- 
cgit v0.10.2


From 90ed6cba51446f0e623ce076d6e565fad8909b46 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:53 +0900
Subject: tools: moveconfig: check compilers before starting defconfig walk

Since commit 25400090b1e2 ("moveconfig: Print a message for
missing compiler"), this tool parses an error message every time an
error occurs during the process in order to detect missing compiler.

Instead of that, we can look for compilers in the PATH environment
only once before starting the defconfig walk.  If a desired compiler
is missing, "make include/config/auto.conf" will apparently fail for
that architecture.  So, the tool can just skip those board, showing
"Compiler is missing.  Do nothing.".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index ce8245a..7e916c2 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -82,7 +82,12 @@ It looks like one of the followings:
    This config option was not found in the config header.
    Nothing to do.
 
- - Failed to process.  Skip.
+ - Compiler is missing.  Do nothing.
+   The compiler specified for this architecture was not found
+   in your PATH environment.
+   (If -e option is passed, the tool exits immediately.)
+
+ - Failed to process.
    An error occurred during processing this defconfig.  Skipped.
    (If -e option is passed, the tool exits immediately on error.)
 
@@ -272,7 +277,7 @@ def log_msg(color_enabled, color, defconfig, msg):
     return defconfig[:-len('_defconfig')].ljust(37) + ': ' + \
         color_text(color_enabled, color, msg) + '\n'
 
-def update_cross_compile():
+def update_cross_compile(color_enabled):
     """Update per-arch CROSS_COMPILE via environment variables
 
     The default CROSS_COMPILE values are available
@@ -286,6 +291,9 @@ def update_cross_compile():
 
     export CROSS_COMPILE_ARM=...
     export CROSS_COMPILE_POWERPC=...
+
+    Then, this function checks if specified compilers really exist in your
+    PATH environment.
     """
     archs = []
 
@@ -299,8 +307,20 @@ def update_cross_compile():
     for arch in archs:
         env = 'CROSS_COMPILE_' + arch.upper()
         cross_compile = os.environ.get(env)
-        if cross_compile:
-            CROSS_COMPILE[arch] = cross_compile
+        if not cross_compile:
+            cross_compile = CROSS_COMPILE.get(arch, '')
+
+        for path in os.environ["PATH"].split(os.pathsep):
+            gcc_path = os.path.join(path, cross_compile + 'gcc')
+            if os.path.isfile(gcc_path) and os.access(gcc_path, os.X_OK):
+                break
+        else:
+            print >> sys.stderr, color_text(color_enabled, COLOR_YELLOW,
+                 'warning: %sgcc: not found in PATH.  %s architecture boards will be skipped'
+                                            % (cross_compile, arch))
+            cross_compile = None
+
+        CROSS_COMPILE[arch] = cross_compile
 
 def cleanup_one_header(header_path, patterns, dry_run):
     """Clean regex-matched lines away from a file.
@@ -387,6 +407,10 @@ class KconfigParser:
 
         Returns:
           A string storing the compiler prefix for the architecture.
+          Return a NULL string for architectures that do not require
+          compiler prefix (Sandbox and native build is the case).
+          Return None if the specified compiler is missing in your PATH.
+          Caller should distinguish '' and None.
         """
         arch = ''
         cpu = ''
@@ -400,13 +424,14 @@ class KconfigParser:
             if m:
                 cpu = m.group(1)
 
-        assert arch, 'Error: arch is not defined in %s' % defconfig
+        if not arch:
+            return None
 
         # fix-up for aarch64
         if arch == 'arm' and cpu == 'armv8':
             arch = 'aarch64'
 
-        return CROSS_COMPILE.get(arch, '')
+        return CROSS_COMPILE.get(arch, None)
 
     def parse_one_config(self, config_attr, defconfig_lines, autoconf_lines):
         """Parse .config, defconfig, include/autoconf.mk for one config.
@@ -606,21 +631,12 @@ class Slot:
             return False
 
         if self.ps.poll() != 0:
-            errmsg = 'Failed to process.'
-            errout = self.ps.stderr.read()
-            if errout.find('gcc: command not found') != -1:
-                errmsg = 'Compiler not found ('
-                errmsg += color_text(self.options.color, COLOR_YELLOW,
-                                     self.cross_compile)
-                errmsg += color_text(self.options.color, COLOR_LIGHT_RED,
-                                     ')')
-            print >> sys.stderr, log_msg(self.options.color,
-                                         COLOR_LIGHT_RED,
-                                         self.defconfig,
-                                         errmsg),
+            print >> sys.stderr, log_msg(self.options.color, COLOR_LIGHT_RED,
+                                         self.defconfig, "Failed to process."),
             if self.options.verbose:
                 print >> sys.stderr, color_text(self.options.color,
-                                                COLOR_LIGHT_CYAN, errout)
+                                                COLOR_LIGHT_CYAN,
+                                                self.ps.stderr.read())
             if self.options.exit_on_error:
                 sys.exit("Exit on error.")
             # If --exit-on-error flag is not set, skip this board and continue.
@@ -651,15 +667,24 @@ class Slot:
             return True
 
         self.cross_compile = self.parser.get_cross_compile()
+        if self.cross_compile is None:
+            print >> sys.stderr, log_msg(self.options.color, COLOR_YELLOW,
+                                         self.defconfig,
+                                         "Compiler is missing.  Do nothing."),
+            if self.options.exit_on_error:
+                sys.exit("Exit on error.")
+            # If --exit-on-error flag is not set, skip this board and continue.
+            # Record the failed board.
+            self.failed_boards.append(self.defconfig)
+            self.state = STATE_IDLE
+            return True
+
         cmd = list(self.make_cmd)
         if self.cross_compile:
             cmd.append('CROSS_COMPILE=%s' % self.cross_compile)
         cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
         cmd.append('include/config/auto.conf')
-        """This will be screen-scraped, so be sure the expected text will be
-        returned consistently on every machine by setting LANG=C"""
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   env=dict(os.environ, LANG='C'),
                                    stderr=subprocess.PIPE)
         self.state = STATE_AUTOCONF
         return False
@@ -907,7 +932,7 @@ def main():
 
     check_top_directory()
 
-    update_cross_compile()
+    update_cross_compile(options.color)
 
     if not options.cleanup_headers_only:
         move_config(config_attrs, options)
-- 
cgit v0.10.2


From bd63e5baf9c1ec724374c6b6a5d88408479d34ca Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:54 +0900
Subject: tools: moveconfig: exit with error message for not clean directory

When the source tree is not clean, this tool raises an exception
with a message like follows:

Traceback (most recent call last):
  File "tools/moveconfig.py", line 939, in <module>
    main()
  File "tools/moveconfig.py", line 934, in main
    move_config(config_attrs, options)
  File "tools/moveconfig.py", line 808, in move_config
    while not slots.available():
  File "tools/moveconfig.py", line 733, in available
    if slot.poll():
  File "tools/moveconfig.py", line 645, in poll
    self.parser.update_dotconfig(self.defconfig)
  File "tools/moveconfig.py", line 503, in update_dotconfig
    with open(autoconf_path) as f:
IOError: [Errno 2] No such file or directory: '/tmp/tmpDtzCgl/include/autoconf.mk'

This does not explain what is wrong.  Show an appropriate error
message "source tree is not clean, please run 'make mrproper'"
in such a situation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 7e916c2..0d64998 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -252,6 +252,12 @@ def check_top_directory():
         if not os.path.exists(f):
             sys.exit('Please run at the top of source directory.')
 
+def check_clean_directory():
+    """Exit if the source tree is not clean."""
+    for f in ('.config', 'include/config'):
+        if os.path.exists(f):
+            sys.exit("source tree is not clean, please run 'make mrproper'")
+
 def get_make_cmd():
     """Get the command name of GNU Make.
 
@@ -932,6 +938,8 @@ def main():
 
     check_top_directory()
 
+    check_clean_directory()
+
     update_cross_compile(options.color)
 
     if not options.cleanup_headers_only:
-- 
cgit v0.10.2


From c5e60fd4954ccbeee4d7cd783b338c4783604547 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:55 +0900
Subject: tools: moveconfig: increment number of processed files monotonically

Currently, the progress " * defconfigs out of 1133" does not increase
monotonically.

Moreover, the number of processed defconfigs does not match the total
number of defconfigs when this tool finishes, like:

 1132 defconfigs out of 1133
Clean up headers? [y/n]:

It looks like the task was not completed, and some users might feel
upset about it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 0d64998..caf2a82 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -388,6 +388,29 @@ def cleanup_headers(config_attrs, dry_run):
                                        patterns, dry_run)
 
 ### classes ###
+class Progress:
+
+    """Progress Indicator"""
+
+    def __init__(self, total):
+        """Create a new progress indicator.
+
+        Arguments:
+          total: A number of defconfig files to process.
+        """
+        self.current = 0
+        self.total = total
+
+    def inc(self):
+        """Increment the number of processed defconfig files."""
+
+        self.current += 1
+
+    def show(self):
+        """Display the progress."""
+        print ' %d defconfigs out of %d\r' % (self.current, self.total),
+        sys.stdout.flush()
+
 class KconfigParser:
 
     """A parser of .config and include/autoconf.mk."""
@@ -395,17 +418,19 @@ class KconfigParser:
     re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
     re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
 
-    def __init__(self, config_attrs, options, build_dir):
+    def __init__(self, config_attrs, options, progress, build_dir):
         """Create a new parser.
 
         Arguments:
           config_attrs: A list of dictionaris, each of them includes the name,
                         the type, and the default value of the target config.
           options: option flags.
+          progress: A progress indicator
           build_dir: Build directory.
         """
         self.config_attrs = config_attrs
         self.options = options
+        self.progress = progress
         self.build_dir = build_dir
 
     def get_cross_compile(self):
@@ -541,6 +566,7 @@ class KconfigParser:
         # Some threads are running in parallel.
         # Print log in one shot to not mix up logs from different threads.
         print log,
+        self.progress.show()
 
         with open(dotconfig_path, 'a') as f:
             for (action, value) in results:
@@ -559,21 +585,24 @@ class Slot:
     for faster processing.
     """
 
-    def __init__(self, config_attrs, options, devnull, make_cmd):
+    def __init__(self, config_attrs, options, progress, devnull, make_cmd):
         """Create a new process slot.
 
         Arguments:
           config_attrs: A list of dictionaris, each of them includes the name,
                         the type, and the default value of the target config.
           options: option flags.
+          progress: A progress indicator.
           devnull: A file object of '/dev/null'.
           make_cmd: command name of GNU Make.
         """
         self.options = options
+        self.progress = progress
         self.build_dir = tempfile.mkdtemp()
         self.devnull = devnull
         self.make_cmd = (make_cmd, 'O=' + self.build_dir)
-        self.parser = KconfigParser(config_attrs, options, self.build_dir)
+        self.parser = KconfigParser(config_attrs, options, progress,
+                                    self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = []
 
@@ -592,7 +621,7 @@ class Slot:
                 pass
         shutil.rmtree(self.build_dir)
 
-    def add(self, defconfig, num, total):
+    def add(self, defconfig):
         """Assign a new subprocess for defconfig and add it to the slot.
 
         If the slot is vacant, create a new subprocess for processing the
@@ -613,8 +642,6 @@ class Slot:
                                    stderr=subprocess.PIPE)
         self.defconfig = defconfig
         self.state = STATE_DEFCONFIG
-        self.num = num
-        self.total = total
         return True
 
     def poll(self):
@@ -643,6 +670,8 @@ class Slot:
                 print >> sys.stderr, color_text(self.options.color,
                                                 COLOR_LIGHT_CYAN,
                                                 self.ps.stderr.read())
+            self.progress.inc()
+            self.progress.show()
             if self.options.exit_on_error:
                 sys.exit("Exit on error.")
             # If --exit-on-error flag is not set, skip this board and continue.
@@ -654,9 +683,6 @@ class Slot:
         if self.state == STATE_AUTOCONF:
             self.parser.update_dotconfig(self.defconfig)
 
-            print ' %d defconfigs out of %d\r' % (self.num + 1, self.total),
-            sys.stdout.flush()
-
             """Save off the defconfig in a consistent way"""
             cmd = list(self.make_cmd)
             cmd.append('savedefconfig')
@@ -669,6 +695,7 @@ class Slot:
             if not self.options.dry_run:
                 shutil.move(os.path.join(self.build_dir, 'defconfig'),
                             os.path.join('configs', self.defconfig))
+            self.progress.inc()
             self.state = STATE_IDLE
             return True
 
@@ -677,6 +704,8 @@ class Slot:
             print >> sys.stderr, log_msg(self.options.color, COLOR_YELLOW,
                                          self.defconfig,
                                          "Compiler is missing.  Do nothing."),
+            self.progress.inc()
+            self.progress.show()
             if self.options.exit_on_error:
                 sys.exit("Exit on error.")
             # If --exit-on-error flag is not set, skip this board and continue.
@@ -704,22 +733,24 @@ class Slots:
 
     """Controller of the array of subprocess slots."""
 
-    def __init__(self, config_attrs, options):
+    def __init__(self, config_attrs, options, progress):
         """Create a new slots controller.
 
         Arguments:
           config_attrs: A list of dictionaris containing the name, the type,
                         and the default value of the target CONFIG.
           options: option flags.
+          progress: A progress indicator.
         """
         self.options = options
         self.slots = []
         devnull = get_devnull()
         make_cmd = get_make_cmd()
         for i in range(options.jobs):
-            self.slots.append(Slot(config_attrs, options, devnull, make_cmd))
+            self.slots.append(Slot(config_attrs, options, progress, devnull,
+                                   make_cmd))
 
-    def add(self, defconfig, num, total):
+    def add(self, defconfig):
         """Add a new subprocess if a vacant slot is found.
 
         Arguments:
@@ -729,7 +760,7 @@ class Slots:
           Return True on success or False on failure
         """
         for slot in self.slots:
-            if slot.add(defconfig, num, total):
+            if slot.add(defconfig):
                 return True
         return False
 
@@ -808,13 +839,14 @@ def move_config(config_attrs, options):
             for filename in fnmatch.filter(filenames, '*_defconfig'):
                 defconfigs.append(os.path.join(dirpath, filename))
 
-    slots = Slots(config_attrs, options)
+    progress = Progress(len(defconfigs))
+    slots = Slots(config_attrs, options, progress)
 
     # Main loop to process defconfig files:
     #  Add a new subprocess into a vacant slot.
     #  Sleep if there is no available slot.
-    for i, defconfig in enumerate(defconfigs):
-        while not slots.add(defconfig, i, len(defconfigs)):
+    for defconfig in defconfigs:
+        while not slots.add(defconfig):
             while not slots.available():
                 # No available slot: sleep for a while
                 time.sleep(SLEEP_TIME)
@@ -823,6 +855,7 @@ def move_config(config_attrs, options):
     while not slots.empty():
         time.sleep(SLEEP_TIME)
 
+    progress.show()
     print ''
     slots.show_failed_boards()
 
-- 
cgit v0.10.2


From cc008299f8526dbbd2cb9485799218a67757c4e2 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:56 +0900
Subject: tools: moveconfig: do not rely on type and default value given by
 users

Commit 96464badc794 ("moveconfig: Always run savedefconfig on the
moved config") changed the work flow of this tool a lot from the
original intention when this tool was designed first.

Since then, before running this tool, users must edit the Kconfig to
add the menu entries for the configs they are moving.  It means users
had already specified the type and the default value for each CONFIG
via its Kconfig entry.  Nevertheless, users are still required to
dictate the same type and the default value in the input file.  This
is tedious to use.  So, my idea here is to deprecate the latter.

Before moving forward with it, there is one issue worth mentioning;
since the savedefconfig re-sync was introduced, this tool has not
been able to move bool options with "default y".  Joe sent a patch
to solve this problem about a year ago, but it was not applied for
some reasons.  Now, he came back with an updated patch, so this
problem will be fixed soon.

For other use cases, I see no reason to require redundant dictation
in the input file.  Instead, the tool can know the types and default
values by parsing the .config file.

This commit changes the tool to use the CONFIG names, but ignore the
types and default values given by the input file.

This commit also fixes one bug.  Prior to this commit, it could not
move an integer-typed CONFIG with value 1.

For example, assume we are moving CONFIG_CONS_INDEX.  Please note
this is an integer type option.

Many board headers define this CONFIG as 1.

  #define CONFIG_CONS_INDEX    1

It will be converted to

  CONFIG_CONS_INDEX=y

and moved to include/autoconf.mk, by the tools/scripts/define2mk.sed.
It will cause "make savedefconfig" to fail due to the type conflict.

This commit takes care of it by detecting the type and converting the
CONFIG value correctly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index caf2a82..96834c4 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -70,13 +70,17 @@ It looks like one of the followings:
  - Move 'CONFIG_... '
    This config option was moved to the defconfig
 
- - Default value 'CONFIG_...'.  Do nothing.
-   The value of this option is the same as default.
-   We do not have to add it to the defconfig.
-
- - 'CONFIG_...' already exists in Kconfig.  Do nothing.
-   This config option is already defined in Kconfig.
-   We do not need/want to touch it.
+ - CONFIG_... is not defined in Kconfig.  Do nothing.
+   The entry for this CONFIG was not found in Kconfig.
+   There are two common cases:
+     - You forgot to create an entry for the CONFIG before running
+       this tool, or made a typo in a CONFIG passed to this tool.
+     - The entry was hidden due to unmet 'depends on'.
+       This is correct behavior.
+
+ - 'CONFIG_...' is the same as the define in Kconfig.  Do nothing.
+   The define in the config header matched the one in Kconfig.
+   We do not need to touch it.
 
  - Undefined.  Do nothing.
    This config option was not found in the config header.
@@ -216,9 +220,8 @@ STATE_AUTOCONF = 2
 STATE_SAVEDEFCONFIG = 3
 
 ACTION_MOVE = 0
-ACTION_DEFAULT_VALUE = 1
-ACTION_ALREADY_EXIST = 2
-ACTION_UNDEFINED = 3
+ACTION_NO_ENTRY = 1
+ACTION_NO_CHANGE = 2
 
 COLOR_BLACK        = '0;30'
 COLOR_RED          = '0;31'
@@ -464,7 +467,7 @@ class KconfigParser:
 
         return CROSS_COMPILE.get(arch, None)
 
-    def parse_one_config(self, config_attr, defconfig_lines, autoconf_lines):
+    def parse_one_config(self, config_attr, dotconfig_lines, autoconf_lines):
         """Parse .config, defconfig, include/autoconf.mk for one config.
 
         This function looks for the config options in the lines from
@@ -474,7 +477,7 @@ class KconfigParser:
         Arguments:
           config_attr: A dictionary including the name, the type,
                        and the default value of the target config.
-          defconfig_lines: lines from the original defconfig file.
+          dotconfig_lines: lines from the .config file.
           autoconf_lines: lines from the include/autoconf.mk file.
 
         Returns:
@@ -484,42 +487,40 @@ class KconfigParser:
         config = config_attr['config']
         not_set = '# %s is not set' % config
 
-        if config_attr['type'] in ('bool', 'tristate') and \
-           config_attr['default'] == 'n':
-            default = not_set
-        else:
-            default = config + '=' + config_attr['default']
-
-        for line in defconfig_lines:
+        for line in dotconfig_lines:
             line = line.rstrip()
             if line.startswith(config + '=') or line == not_set:
-                return (ACTION_ALREADY_EXIST, line)
-
-        if config_attr['type'] in ('bool', 'tristate'):
-            value = not_set
+                old_val = line
+                break
         else:
-            value = '(undefined)'
+            return (ACTION_NO_ENTRY, config)
 
         for line in autoconf_lines:
             line = line.rstrip()
             if line.startswith(config + '='):
-                value = line
+                new_val = line
                 break
-
-        if value == default:
-            action = ACTION_DEFAULT_VALUE
-        elif value == '(undefined)':
-            action = ACTION_UNDEFINED
         else:
-            action = ACTION_MOVE
+            new_val = not_set
+
+        if old_val == new_val:
+            return (ACTION_NO_CHANGE, new_val)
+
+        # If this CONFIG is neither bool nor trisate
+        if old_val[-2:] != '=y' and old_val[-2:] != '=m' and old_val != not_set:
+            # tools/scripts/define2mk.sed changes '1' to 'y'.
+            # This is a problem if the CONFIG is int type.
+            # Check the type in Kconfig and handle it correctly.
+            if new_val[-2:] == '=y':
+                new_val = new_val[:-1] + '1'
 
-        return (action, value)
+        return (ACTION_MOVE, new_val)
 
     def update_dotconfig(self, defconfig):
         """Parse files for the config options and update the .config.
 
-        This function parses the given defconfig, the generated .config
-        and include/autoconf.mk searching the target options.
+        This function parses the generated .config and include/autoconf.mk
+        searching the target options.
         Move the config option(s) to the .config as needed.
         Also, display the log to show what happened to the .config.
 
@@ -527,19 +528,18 @@ class KconfigParser:
           defconfig: defconfig name.
         """
 
-        defconfig_path = os.path.join('configs', defconfig)
         dotconfig_path = os.path.join(self.build_dir, '.config')
         autoconf_path = os.path.join(self.build_dir, 'include', 'autoconf.mk')
         results = []
 
-        with open(defconfig_path) as f:
-            defconfig_lines = f.readlines()
+        with open(dotconfig_path) as f:
+            dotconfig_lines = f.readlines()
 
         with open(autoconf_path) as f:
             autoconf_lines = f.readlines()
 
         for config_attr in self.config_attrs:
-            result = self.parse_one_config(config_attr, defconfig_lines,
+            result = self.parse_one_config(config_attr, dotconfig_lines,
                                            autoconf_lines)
             results.append(result)
 
@@ -549,15 +549,13 @@ class KconfigParser:
             if action == ACTION_MOVE:
                 actlog = "Move '%s'" % value
                 log_color = COLOR_LIGHT_GREEN
-            elif action == ACTION_DEFAULT_VALUE:
-                actlog = "Default value '%s'.  Do nothing." % value
+            elif action == ACTION_NO_ENTRY:
+                actlog = "%s is not defined in Kconfig.  Do nothing." % value
                 log_color = COLOR_LIGHT_BLUE
-            elif action == ACTION_ALREADY_EXIST:
-                actlog = "'%s' already defined in Kconfig.  Do nothing." % value
+            elif action == ACTION_NO_CHANGE:
+                actlog = "'%s' is the same as the define in Kconfig.  Do nothing." \
+                         % value
                 log_color = COLOR_LIGHT_PURPLE
-            elif action == ACTION_UNDEFINED:
-                actlog = "Undefined.  Do nothing."
-                log_color = COLOR_DARK_GRAY
             else:
                 sys.exit("Internal Error. This should not happen.")
 
-- 
cgit v0.10.2


From b134bc13543f2627d3044310151459eeb904216c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:57 +0900
Subject: tools: moveconfig: drop code for handling type and default value

Now types and defalut values given by the input file are just
ignored.  Delete unnecessary code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 96834c4..d54dd4e 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -360,12 +360,11 @@ def cleanup_one_header(header_path, patterns, dry_run):
             if not i in matched:
                 f.write(line)
 
-def cleanup_headers(config_attrs, dry_run):
+def cleanup_headers(configs, dry_run):
     """Delete config defines from board headers.
 
     Arguments:
-      config_attrs: A list of dictionaris, each of them includes the name,
-                    the type, and the default value of the target config.
+      configs: A list of CONFIGs to remove.
       dry_run: make no changes, but still display log.
     """
     while True:
@@ -378,8 +377,7 @@ def cleanup_headers(config_attrs, dry_run):
         return
 
     patterns = []
-    for config_attr in config_attrs:
-        config = config_attr['config']
+    for config in configs:
         patterns.append(re.compile(r'#\s*define\s+%s\W' % config))
         patterns.append(re.compile(r'#\s*undef\s+%s\W' % config))
 
@@ -421,17 +419,16 @@ class KconfigParser:
     re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
     re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
 
-    def __init__(self, config_attrs, options, progress, build_dir):
+    def __init__(self, configs, options, progress, build_dir):
         """Create a new parser.
 
         Arguments:
-          config_attrs: A list of dictionaris, each of them includes the name,
-                        the type, and the default value of the target config.
+          configs: A list of CONFIGs to move.
           options: option flags.
           progress: A progress indicator
           build_dir: Build directory.
         """
-        self.config_attrs = config_attrs
+        self.configs = configs
         self.options = options
         self.progress = progress
         self.build_dir = build_dir
@@ -467,7 +464,7 @@ class KconfigParser:
 
         return CROSS_COMPILE.get(arch, None)
 
-    def parse_one_config(self, config_attr, dotconfig_lines, autoconf_lines):
+    def parse_one_config(self, config, dotconfig_lines, autoconf_lines):
         """Parse .config, defconfig, include/autoconf.mk for one config.
 
         This function looks for the config options in the lines from
@@ -475,8 +472,7 @@ class KconfigParser:
         which action should be taken for this defconfig.
 
         Arguments:
-          config_attr: A dictionary including the name, the type,
-                       and the default value of the target config.
+          config: CONFIG name to parse.
           dotconfig_lines: lines from the .config file.
           autoconf_lines: lines from the include/autoconf.mk file.
 
@@ -484,7 +480,6 @@ class KconfigParser:
           A tupple of the action for this defconfig and the line
           matched for the config.
         """
-        config = config_attr['config']
         not_set = '# %s is not set' % config
 
         for line in dotconfig_lines:
@@ -538,8 +533,8 @@ class KconfigParser:
         with open(autoconf_path) as f:
             autoconf_lines = f.readlines()
 
-        for config_attr in self.config_attrs:
-            result = self.parse_one_config(config_attr, dotconfig_lines,
+        for config in self.configs:
+            result = self.parse_one_config(config, dotconfig_lines,
                                            autoconf_lines)
             results.append(result)
 
@@ -583,12 +578,11 @@ class Slot:
     for faster processing.
     """
 
-    def __init__(self, config_attrs, options, progress, devnull, make_cmd):
+    def __init__(self, configs, options, progress, devnull, make_cmd):
         """Create a new process slot.
 
         Arguments:
-          config_attrs: A list of dictionaris, each of them includes the name,
-                        the type, and the default value of the target config.
+          configs: A list of CONFIGs to move.
           options: option flags.
           progress: A progress indicator.
           devnull: A file object of '/dev/null'.
@@ -599,8 +593,7 @@ class Slot:
         self.build_dir = tempfile.mkdtemp()
         self.devnull = devnull
         self.make_cmd = (make_cmd, 'O=' + self.build_dir)
-        self.parser = KconfigParser(config_attrs, options, progress,
-                                    self.build_dir)
+        self.parser = KconfigParser(configs, options, progress, self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = []
 
@@ -731,12 +724,11 @@ class Slots:
 
     """Controller of the array of subprocess slots."""
 
-    def __init__(self, config_attrs, options, progress):
+    def __init__(self, configs, options, progress):
         """Create a new slots controller.
 
         Arguments:
-          config_attrs: A list of dictionaris containing the name, the type,
-                        and the default value of the target CONFIG.
+          configs: A list of CONFIGs to move.
           options: option flags.
           progress: A progress indicator.
         """
@@ -745,7 +737,7 @@ class Slots:
         devnull = get_devnull()
         make_cmd = get_make_cmd()
         for i in range(options.jobs):
-            self.slots.append(Slot(config_attrs, options, progress, devnull,
+            self.slots.append(Slot(configs, options, progress, devnull,
                                    make_cmd))
 
     def add(self, defconfig):
@@ -803,23 +795,18 @@ class Slots:
                 for board in failed_boards:
                     f.write(board + '\n')
 
-def move_config(config_attrs, options):
+def move_config(configs, options):
     """Move config options to defconfig files.
 
     Arguments:
-      config_attrs: A list of dictionaris, each of them includes the name,
-                    the type, and the default value of the target config.
+      configs: A list of CONFIGs to move.
       options: option flags
     """
-    if len(config_attrs) == 0:
+    if len(configs) == 0:
         print 'Nothing to do. exit.'
         sys.exit(0)
 
-    print 'Move the following CONFIG options (jobs: %d)' % options.jobs
-    for config_attr in config_attrs:
-        print '  %s (type: %s, default: %s)' % (config_attr['config'],
-                                                config_attr['type'],
-                                                config_attr['default'])
+    print 'Move %s (jobs: %d)' % (', '.join(configs), options.jobs)
 
     if options.defconfigs:
         defconfigs = [line.strip() for line in open(options.defconfigs)]
@@ -838,7 +825,7 @@ def move_config(config_attrs, options):
                 defconfigs.append(os.path.join(dirpath, filename))
 
     progress = Progress(len(defconfigs))
-    slots = Slots(config_attrs, options, progress)
+    slots = Slots(configs, options, progress)
 
     # Main loop to process defconfig files:
     #  Add a new subprocess into a vacant slot.
@@ -862,7 +849,7 @@ def bad_recipe(filename, linenum, msg):
     sys.exit("%s: line %d: error : " % (filename, linenum) + msg)
 
 def parse_recipe(filename):
-    """Parse the recipe file and retrieve the config attributes.
+    """Parse the recipe file and retrieve CONFIGs to move.
 
     This function parses the given recipe file and gets the name,
     the type, and the default value of the target config options.
@@ -870,10 +857,9 @@ def parse_recipe(filename):
     Arguments:
       filename: path to file to be parsed.
     Returns:
-      A list of dictionaris, each of them includes the name,
-      the type, and the default value of the target config.
+      A list of CONFIGs to move.
     """
-    config_attrs = []
+    configs = []
     linenum = 1
 
     for line in open(filename):
@@ -889,43 +875,10 @@ def parse_recipe(filename):
         if not config.startswith('CONFIG_'):
             config = 'CONFIG_' + config
 
-        # sanity check of default values
-        if type == 'bool':
-            if not default in ('y', 'n'):
-                bad_recipe(filename, linenum,
-                           "default for bool type must be either y or n")
-        elif type == 'tristate':
-            if not default in ('y', 'm', 'n'):
-                bad_recipe(filename, linenum,
-                           "default for tristate type must be y, m, or n")
-        elif type == 'string':
-            if default[0] != '"' or default[-1] != '"':
-                bad_recipe(filename, linenum,
-                           "default for string type must be surrounded by double-quotations")
-        elif type == 'int':
-            try:
-                int(default)
-            except:
-                bad_recipe(filename, linenum,
-                           "type is int, but default value is not decimal")
-        elif type == 'hex':
-            if len(default) < 2 or default[:2] != '0x':
-                bad_recipe(filename, linenum,
-                           "default for hex type must be prefixed with 0x")
-            try:
-                int(default, 16)
-            except:
-                bad_recipe(filename, linenum,
-                           "type is hex, but default value is not hexadecimal")
-        else:
-            bad_recipe(filename, linenum,
-                       "unsupported type '%s'. type must be one of bool, tristate, string, int, hex"
-                       % type)
-
-        config_attrs.append({'config': config, 'type': type, 'default': default})
+        configs.append(config)
         linenum += 1
 
-    return config_attrs
+    return configs
 
 def main():
     try:
@@ -965,7 +918,7 @@ def main():
         parser.print_usage()
         sys.exit(1)
 
-    config_attrs = parse_recipe(args[0])
+    configs = parse_recipe(args[0])
 
     check_top_directory()
 
@@ -974,9 +927,9 @@ def main():
     update_cross_compile(options.color)
 
     if not options.cleanup_headers_only:
-        move_config(config_attrs, options)
+        move_config(configs, options)
 
-    cleanup_headers(config_attrs, options.dry_run)
+    cleanup_headers(configs, options.dry_run)
 
 if __name__ == '__main__':
     main()
-- 
cgit v0.10.2


From b6ef393ad78706398c0d7ec3358172af7fc8a66b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:51:58 +0900
Subject: tools: moveconfig: allow to give CONFIG names as argument directly

We still pass the input file with CONFIG name, type, default value
in each line, but the last two fields are just ignored by the tool.
So, let's deprecate the input file and allow users to give CONFIG
names directly from the command line.  The types and default values
are automatically detected and handled nicely by the tool.

Going forward, we can use this tool more easily like:

  tools/moveconfig.py CONFIG_FOO CONFIG_BAR

Update the documentation and fix some typos I noticed while I was
working on.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index d54dd4e..07136f5 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -17,44 +17,16 @@ This tool intends to help this tremendous work.
 Usage
 -----
 
-This tool takes one input file.  (let's say 'recipe' file here.)
-The recipe describes the list of config options you want to move.
-Each line takes the form:
-<config_name> <type> <default>
-(the fields must be separated with whitespaces.)
-
-<config_name> is the name of config option.
-
-<type> is the type of the option.  It must be one of bool, tristate,
-string, int, and hex.
-
-<default> is the default value of the option.  It must be appropriate
-value corresponding to the option type.  It must be either y or n for
-the bool type.  Tristate options can also take m (although U-Boot has
-not supported the module feature).
-
-You can add two or more lines in the recipe file, so you can move
-multiple options at once.
-
-Let's say, for example, you want to move CONFIG_CMD_USB and
-CONFIG_SYS_TEXT_BASE.
-
-The type should be bool, hex, respectively.  So, the recipe file
-should look like this:
-
-  $ cat recipe
-  CONFIG_CMD_USB bool n
-  CONFIG_SYS_TEXT_BASE hex 0x00000000
-
-Next you must edit the Kconfig to add the menu entries for the configs
+First, you must edit the Kconfig to add the menu entries for the configs
 you are moving.
 
-And then run this tool giving the file name of the recipe
+And then run this tool giving CONFIG names you want to move.
+For example, if you want to move CONFIG_CMD_USB and CONFIG_SYS_TEXT_BASE,
+simply type as follows:
 
-  $ tools/moveconfig.py recipe
+  $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_SYS_TEXT_BASE
 
-The tool walks through all the defconfig files to move the config
-options specified by the recipe file.
+The tool walks through all the defconfig files and move the given CONFIGs.
 
 The log is also displayed on the terminal.
 
@@ -103,19 +75,19 @@ It just uses the regex method, so you should not rely on it.
 Just in case, please do 'git diff' to see what happened.
 
 
-How does it works?
-------------------
+How does it work?
+-----------------
 
 This tool runs configuration and builds include/autoconf.mk for every
 defconfig.  The config options defined in Kconfig appear in the .config
 file (unless they are hidden because of unmet dependency.)
 On the other hand, the config options defined by board headers are seen
 in include/autoconf.mk.  The tool looks for the specified options in both
-of them to decide the appropriate action for the options.  If the option
-is found in the .config or the value is the same as the specified default,
-the option does not need to be touched.  If the option is found in
-include/autoconf.mk, but not in the .config, and the value is different
-from the default, the tools adds the option to the defconfig.
+of them to decide the appropriate action for the options.  If the given
+config option is found in the .config, but its value does not match the
+one from the board header, the config option in the .config is replaced
+with the define in the board header.  Then, the .config is synced by
+"make savedefconfig" and the defconfig is updated with it.
 
 For faster processing, this tool handles multi-threading.  It creates
 separate build directories where the out-of-tree build is run.  The
@@ -148,7 +120,7 @@ Available options
   Specify a file containing a list of defconfigs to move
 
  -n, --dry-run
-   Peform a trial run that does not make any changes.  It is useful to
+   Perform a trial run that does not make any changes.  It is useful to
    see what is going to happen before one actually runs it.
 
  -e, --exit-on-error
@@ -844,42 +816,6 @@ def move_config(configs, options):
     print ''
     slots.show_failed_boards()
 
-def bad_recipe(filename, linenum, msg):
-    """Print error message with the file name and the line number and exit."""
-    sys.exit("%s: line %d: error : " % (filename, linenum) + msg)
-
-def parse_recipe(filename):
-    """Parse the recipe file and retrieve CONFIGs to move.
-
-    This function parses the given recipe file and gets the name,
-    the type, and the default value of the target config options.
-
-    Arguments:
-      filename: path to file to be parsed.
-    Returns:
-      A list of CONFIGs to move.
-    """
-    configs = []
-    linenum = 1
-
-    for line in open(filename):
-        tokens = line.split()
-        if len(tokens) != 3:
-            bad_recipe(filename, linenum,
-                       "%d fields in this line.  Each line must contain 3 fields"
-                       % len(tokens))
-
-        (config, type, default) = tokens
-
-        # prefix the option name with CONFIG_ if missing
-        if not config.startswith('CONFIG_'):
-            config = 'CONFIG_' + config
-
-        configs.append(config)
-        linenum += 1
-
-    return configs
-
 def main():
     try:
         cpu_count = multiprocessing.cpu_count()
@@ -904,21 +840,17 @@ def main():
                       help='the number of jobs to run simultaneously')
     parser.add_option('-v', '--verbose', action='store_true', default=False,
                       help='show any build errors as boards are built')
-    parser.usage += ' recipe_file\n\n' + \
-                    'The recipe_file should describe config options you want to move.\n' + \
-                    'Each line should contain config_name, type, default_value\n\n' + \
-                    'Example:\n' + \
-                    'CONFIG_FOO bool n\n' + \
-                    'CONFIG_BAR int 100\n' + \
-                    'CONFIG_BAZ string "hello"\n'
+    parser.usage += ' CONFIG ...'
 
-    (options, args) = parser.parse_args()
+    (options, configs) = parser.parse_args()
 
-    if len(args) != 1:
+    if len(configs) == 0:
         parser.print_usage()
         sys.exit(1)
 
-    configs = parse_recipe(args[0])
+    # prefix the option name with CONFIG_ if missing
+    configs = [ config if config.startswith('CONFIG_') else 'CONFIG_' + config
+                for config in configs ]
 
     check_top_directory()
 
-- 
cgit v0.10.2


From 1f16992ee93595fa840aff55bdb722185cc31ca5 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:00 +0900
Subject: tools: moveconfig: compute file paths just once

The paths to .config, include/autoconf.mk, include/config/auto.conf
are not changed during the defconfig walk.  Compute them only once
when a new class instance is created.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 07136f5..7dd9d8c 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -403,7 +403,10 @@ class KconfigParser:
         self.configs = configs
         self.options = options
         self.progress = progress
-        self.build_dir = build_dir
+        self.dotconfig = os.path.join(build_dir, '.config')
+        self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
+        self.config_autoconf = os.path.join(build_dir, 'include', 'config',
+                                            'auto.conf')
 
     def get_cross_compile(self):
         """Parse .config file and return CROSS_COMPILE.
@@ -417,8 +420,7 @@ class KconfigParser:
         """
         arch = ''
         cpu = ''
-        dotconfig = os.path.join(self.build_dir, '.config')
-        for line in open(dotconfig):
+        for line in open(self.dotconfig):
             m = self.re_arch.match(line)
             if m:
                 arch = m.group(1)
@@ -495,14 +497,12 @@ class KconfigParser:
           defconfig: defconfig name.
         """
 
-        dotconfig_path = os.path.join(self.build_dir, '.config')
-        autoconf_path = os.path.join(self.build_dir, 'include', 'autoconf.mk')
         results = []
 
-        with open(dotconfig_path) as f:
+        with open(self.dotconfig) as f:
             dotconfig_lines = f.readlines()
 
-        with open(autoconf_path) as f:
+        with open(self.autoconf) as f:
             autoconf_lines = f.readlines()
 
         for config in self.configs:
@@ -533,13 +533,13 @@ class KconfigParser:
         print log,
         self.progress.show()
 
-        with open(dotconfig_path, 'a') as f:
+        with open(self.dotconfig, 'a') as f:
             for (action, value) in results:
                 if action == ACTION_MOVE:
                     f.write(value + '\n')
 
-        os.remove(os.path.join(self.build_dir, 'include', 'config', 'auto.conf'))
-        os.remove(autoconf_path)
+        os.remove(self.config_autoconf)
+        os.remove(self.autoconf)
 
 class Slot:
 
-- 
cgit v0.10.2


From 522e8dcb4c1d7a64fc19d1545d71b5ee356640bf Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:01 +0900
Subject: tools: moveconfig: move log output code out of Kconfig Parser class

This will help further improvement/clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 7dd9d8c..97d2faf 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -391,18 +391,16 @@ class KconfigParser:
     re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
     re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
 
-    def __init__(self, configs, options, progress, build_dir):
+    def __init__(self, configs, options, build_dir):
         """Create a new parser.
 
         Arguments:
           configs: A list of CONFIGs to move.
           options: option flags.
-          progress: A progress indicator
           build_dir: Build directory.
         """
         self.configs = configs
         self.options = options
-        self.progress = progress
         self.dotconfig = os.path.join(build_dir, '.config')
         self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
         self.config_autoconf = os.path.join(build_dir, 'include', 'config',
@@ -491,10 +489,12 @@ class KconfigParser:
         This function parses the generated .config and include/autoconf.mk
         searching the target options.
         Move the config option(s) to the .config as needed.
-        Also, display the log to show what happened to the .config.
 
         Arguments:
           defconfig: defconfig name.
+
+        Returns:
+          Return log string
         """
 
         results = []
@@ -528,11 +528,6 @@ class KconfigParser:
 
             log += log_msg(self.options.color, log_color, defconfig, actlog)
 
-        # Some threads are running in parallel.
-        # Print log in one shot to not mix up logs from different threads.
-        print log,
-        self.progress.show()
-
         with open(self.dotconfig, 'a') as f:
             for (action, value) in results:
                 if action == ACTION_MOVE:
@@ -541,6 +536,8 @@ class KconfigParser:
         os.remove(self.config_autoconf)
         os.remove(self.autoconf)
 
+        return log
+
 class Slot:
 
     """A slot to store a subprocess.
@@ -565,7 +562,7 @@ class Slot:
         self.build_dir = tempfile.mkdtemp()
         self.devnull = devnull
         self.make_cmd = (make_cmd, 'O=' + self.build_dir)
-        self.parser = KconfigParser(configs, options, progress, self.build_dir)
+        self.parser = KconfigParser(configs, options, self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = []
 
@@ -644,7 +641,7 @@ class Slot:
             return True
 
         if self.state == STATE_AUTOCONF:
-            self.parser.update_dotconfig(self.defconfig)
+            self.log = self.parser.update_dotconfig(self.defconfig)
 
             """Save off the defconfig in a consistent way"""
             cmd = list(self.make_cmd)
@@ -658,7 +655,11 @@ class Slot:
             if not self.options.dry_run:
                 shutil.move(os.path.join(self.build_dir, 'defconfig'),
                             os.path.join('configs', self.defconfig))
+            # Some threads are running in parallel.
+            # Print log in one shot to not mix up logs from different threads.
+            print self.log,
             self.progress.inc()
+            self.progress.show()
             self.state = STATE_IDLE
             return True
 
@@ -812,7 +813,6 @@ def move_config(configs, options):
     while not slots.empty():
         time.sleep(SLEEP_TIME)
 
-    progress.show()
     print ''
     slots.show_failed_boards()
 
-- 
cgit v0.10.2


From 1d085568b3def83b541ab0d7ee550c52f638eab5 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:02 +0900
Subject: tools: moveconfig: display log atomically in more readable format

Before this commit, the log was displayed in the format:

<defconfig_name>   : <action1>
<defconfig_name>   : <action2>
<defconfig_name>   : <action3>

When we move multiple CONFIGs at the same time, we see as many
<defconfig_name> strings as actions for every defconfig, which is
redundant information.

Moreover, since normal log and error log are displayed separately,
Messages from different threads could be mixed, like this:

<foo>              : <action1>
<foo>              : <action2>
<bar>              : <action1>
<bar>              : <action2>
<foo>              : <error_log>

This commit makes sure to call "print" once a defconfig, which
enables atomic logging for each defconfig.  It also makes it
possible to refactor the log format as follows:

<foo_defconfig>
    <action1>
    <action2>
    <error_log>

<bar_defconfig>
    <action1>
    <action2>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 97d2faf..5906bd0 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -30,13 +30,17 @@ The tool walks through all the defconfig files and move the given CONFIGs.
 
 The log is also displayed on the terminal.
 
-Each line is printed in the format
-<defconfig_name>   :  <action>
+The log is printed for each defconfig as follows:
 
-<defconfig_name> is the name of the defconfig
-(without the suffix _defconfig).
+<defconfig_name>
+    <action1>
+    <action2>
+    <action3>
+    ...
 
-<action> shows what the tool did for that defconfig.
+<defconfig_name> is the name of the defconfig.
+
+<action*> shows what the tool did for that defconfig.
 It looks like one of the followings:
 
  - Move 'CONFIG_... '
@@ -249,15 +253,13 @@ def get_make_cmd():
 def color_text(color_enabled, color, string):
     """Return colored string."""
     if color_enabled:
-        return '\033[' + color + 'm' + string + '\033[0m'
+        # LF should not be surrounded by the escape sequence.
+        # Otherwise, additional whitespace or line-feed might be printed.
+        return '\n'.join([ '\033[' + color + 'm' + s + '\033[0m' if s else ''
+                           for s in string.split('\n') ])
     else:
         return string
 
-def log_msg(color_enabled, color, defconfig, msg):
-    """Return the formated line for the log."""
-    return defconfig[:-len('_defconfig')].ljust(37) + ': ' + \
-        color_text(color_enabled, color, msg) + '\n'
-
 def update_cross_compile(color_enabled):
     """Update per-arch CROSS_COMPILE via environment variables
 
@@ -483,7 +485,7 @@ class KconfigParser:
 
         return (ACTION_MOVE, new_val)
 
-    def update_dotconfig(self, defconfig):
+    def update_dotconfig(self):
         """Parse files for the config options and update the .config.
 
         This function parses the generated .config and include/autoconf.mk
@@ -526,7 +528,7 @@ class KconfigParser:
             else:
                 sys.exit("Internal Error. This should not happen.")
 
-            log += log_msg(self.options.color, log_color, defconfig, actlog)
+            log += color_text(self.options.color, log_color, actlog) + '\n'
 
         with open(self.dotconfig, 'a') as f:
             for (action, value) in results:
@@ -602,6 +604,7 @@ class Slot:
                                    stderr=subprocess.PIPE)
         self.defconfig = defconfig
         self.state = STATE_DEFCONFIG
+        self.log = ''
         return True
 
     def poll(self):
@@ -624,14 +627,12 @@ class Slot:
             return False
 
         if self.ps.poll() != 0:
-            print >> sys.stderr, log_msg(self.options.color, COLOR_LIGHT_RED,
-                                         self.defconfig, "Failed to process."),
+            self.log += color_text(self.options.color, COLOR_LIGHT_RED,
+                                   "Failed to process.\n")
             if self.options.verbose:
-                print >> sys.stderr, color_text(self.options.color,
-                                                COLOR_LIGHT_CYAN,
-                                                self.ps.stderr.read())
-            self.progress.inc()
-            self.progress.show()
+                self.log += color_text(self.options.color, COLOR_LIGHT_CYAN,
+                                       self.ps.stderr.read())
+            self.show_log(sys.stderr)
             if self.options.exit_on_error:
                 sys.exit("Exit on error.")
             # If --exit-on-error flag is not set, skip this board and continue.
@@ -641,7 +642,7 @@ class Slot:
             return True
 
         if self.state == STATE_AUTOCONF:
-            self.log = self.parser.update_dotconfig(self.defconfig)
+            self.log += self.parser.update_dotconfig()
 
             """Save off the defconfig in a consistent way"""
             cmd = list(self.make_cmd)
@@ -655,21 +656,15 @@ class Slot:
             if not self.options.dry_run:
                 shutil.move(os.path.join(self.build_dir, 'defconfig'),
                             os.path.join('configs', self.defconfig))
-            # Some threads are running in parallel.
-            # Print log in one shot to not mix up logs from different threads.
-            print self.log,
-            self.progress.inc()
-            self.progress.show()
+            self.show_log()
             self.state = STATE_IDLE
             return True
 
         self.cross_compile = self.parser.get_cross_compile()
         if self.cross_compile is None:
-            print >> sys.stderr, log_msg(self.options.color, COLOR_YELLOW,
-                                         self.defconfig,
-                                         "Compiler is missing.  Do nothing."),
-            self.progress.inc()
-            self.progress.show()
+            self.log += color_text(self.options.color, COLOR_YELLOW,
+                                   "Compiler is missing.  Do nothing.\n")
+            self.show_log(sys.stderr)
             if self.options.exit_on_error:
                 sys.exit("Exit on error.")
             # If --exit-on-error flag is not set, skip this board and continue.
@@ -688,6 +683,22 @@ class Slot:
         self.state = STATE_AUTOCONF
         return False
 
+    def show_log(self, file=sys.stdout):
+        """Display log along with progress.
+
+        Arguments:
+          file: A file object to which the log string is sent.
+        """
+        # output at least 30 characters to hide the "* defconfigs out of *".
+        log = self.defconfig.ljust(30) + '\n'
+
+        log += '\n'.join([ '    ' + s for s in self.log.split('\n') ])
+        # Some threads are running in parallel.
+        # Print log atomically to not mix up logs from different threads.
+        print >> file, log
+        self.progress.inc()
+        self.progress.show()
+
     def get_failed_boards(self):
         """Returns a list of failed boards (defconfigs) in this slot.
         """
-- 
cgit v0.10.2


From 4efef998cda69edb162ea61e4a14f564133457d1 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:03 +0900
Subject: tools: moveconfig: refactor code to go back to idle state

Move similar code to finish() function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 5906bd0..84ad16d 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -632,13 +632,7 @@ class Slot:
             if self.options.verbose:
                 self.log += color_text(self.options.color, COLOR_LIGHT_CYAN,
                                        self.ps.stderr.read())
-            self.show_log(sys.stderr)
-            if self.options.exit_on_error:
-                sys.exit("Exit on error.")
-            # If --exit-on-error flag is not set, skip this board and continue.
-            # Record the failed board.
-            self.failed_boards.append(self.defconfig)
-            self.state = STATE_IDLE
+            self.finish(False)
             return True
 
         if self.state == STATE_AUTOCONF:
@@ -656,21 +650,14 @@ class Slot:
             if not self.options.dry_run:
                 shutil.move(os.path.join(self.build_dir, 'defconfig'),
                             os.path.join('configs', self.defconfig))
-            self.show_log()
-            self.state = STATE_IDLE
+            self.finish(True)
             return True
 
         self.cross_compile = self.parser.get_cross_compile()
         if self.cross_compile is None:
             self.log += color_text(self.options.color, COLOR_YELLOW,
                                    "Compiler is missing.  Do nothing.\n")
-            self.show_log(sys.stderr)
-            if self.options.exit_on_error:
-                sys.exit("Exit on error.")
-            # If --exit-on-error flag is not set, skip this board and continue.
-            # Record the failed board.
-            self.failed_boards.append(self.defconfig)
-            self.state = STATE_IDLE
+            self.finish(False)
             return True
 
         cmd = list(self.make_cmd)
@@ -683,11 +670,12 @@ class Slot:
         self.state = STATE_AUTOCONF
         return False
 
-    def show_log(self, file=sys.stdout):
-        """Display log along with progress.
+    def finish(self, success):
+        """Display log along with progress and go to the idle state.
 
         Arguments:
-          file: A file object to which the log string is sent.
+          success: Should be True when the defconfig was processed
+                   successfully, or False when it fails.
         """
         # output at least 30 characters to hide the "* defconfigs out of *".
         log = self.defconfig.ljust(30) + '\n'
@@ -695,9 +683,18 @@ class Slot:
         log += '\n'.join([ '    ' + s for s in self.log.split('\n') ])
         # Some threads are running in parallel.
         # Print log atomically to not mix up logs from different threads.
-        print >> file, log
+        print >> (sys.stdout if success else sys.stderr), log
+
+        if not success:
+            if self.options.exit_on_error:
+                sys.exit("Exit on error.")
+            # If --exit-on-error flag is not set, skip this board and continue.
+            # Record the failed board.
+            self.failed_boards.append(self.defconfig)
+
         self.progress.inc()
         self.progress.show()
+        self.state = STATE_IDLE
 
     def get_failed_boards(self):
         """Returns a list of failed boards (defconfigs) in this slot.
-- 
cgit v0.10.2


From 7fb0bacd389b9b041164965d31a8c50e8616f7a0 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:04 +0900
Subject: tools: moveconfig: skip savedefconfig if .config was not updated

If no CONFIG option is moved to the .config, no need to sync the
defconfig file.  This accelerates the processing by skipping
needless "make savedefconfig".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 84ad16d..e321044 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -496,10 +496,13 @@ class KconfigParser:
           defconfig: defconfig name.
 
         Returns:
-          Return log string
+          Return a tuple of (updated flag, log string).
+          The "updated flag" is True if the .config was updated, False
+          otherwise.  The "log string" shows what happend to the .config.
         """
 
         results = []
+        updated = False
 
         with open(self.dotconfig) as f:
             dotconfig_lines = f.readlines()
@@ -534,11 +537,12 @@ class KconfigParser:
             for (action, value) in results:
                 if action == ACTION_MOVE:
                     f.write(value + '\n')
+                    updated = True
 
         os.remove(self.config_autoconf)
         os.remove(self.autoconf)
 
-        return log
+        return (updated, log)
 
 class Slot:
 
@@ -614,8 +618,11 @@ class Slot:
         If the configuration is successfully finished, assign a new
         subprocess to build include/autoconf.mk.
         If include/autoconf.mk is generated, invoke the parser to
-        parse the .config and the include/autoconf.mk, and then set the
-        slot back to the idle state.
+        parse the .config and the include/autoconf.mk, moving
+        config options to the .config as needed.
+        If the .config was updated, run "make savedefconfig" to sync
+        it, update the original defconfig, and then set the slot back
+        to the idle state.
 
         Returns:
           Return True if the subprocess is terminated, False otherwise
@@ -636,8 +643,12 @@ class Slot:
             return True
 
         if self.state == STATE_AUTOCONF:
-            self.log += self.parser.update_dotconfig()
+            (updated, log) = self.parser.update_dotconfig()
+            self.log += log
 
+            if not updated:
+                self.finish(True)
+                return True
             """Save off the defconfig in a consistent way"""
             cmd = list(self.make_cmd)
             cmd.append('savedefconfig')
-- 
cgit v0.10.2


From c1c4d0f056f0c0fc8ad6397ad3ad870948d8951e Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:05 +0900
Subject: tools: moveconfig: display log when savedefconfig occurs

Now, "make savedefconfig" does not always happen.  Display the log
when it happens.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index e321044..9c8ab19 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -649,7 +649,8 @@ class Slot:
             if not updated:
                 self.finish(True)
                 return True
-            """Save off the defconfig in a consistent way"""
+            self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+                                   "Syncing by savedefconfig...\n")
             cmd = list(self.make_cmd)
             cmd.append('savedefconfig')
             self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-- 
cgit v0.10.2


From 5da4f857beac1cf859aefac3cf2ae980115ec1ae Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:06 +0900
Subject: tools: moveconfig: report when CONFIGs are removed by savedefconfig

This is a rare case, but there is still possibility that some CONFIG
is moved to the .config, but it is removed by "make savedefconfig".
(For example, it happens when the specified CONFIG has no prompt in
the Kconfig entry, i.e. it is not user-configurable.)

It might be an unexpected case.  So, display the log in this case
(in yellow color to gain user's attention if --color option is given).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 9c8ab19..4881ec5 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -407,6 +407,7 @@ class KconfigParser:
         self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
         self.config_autoconf = os.path.join(build_dir, 'include', 'config',
                                             'auto.conf')
+        self.defconfig = os.path.join(build_dir, 'defconfig')
 
     def get_cross_compile(self):
         """Parse .config file and return CROSS_COMPILE.
@@ -539,11 +540,35 @@ class KconfigParser:
                     f.write(value + '\n')
                     updated = True
 
+        self.results = results
         os.remove(self.config_autoconf)
         os.remove(self.autoconf)
 
         return (updated, log)
 
+    def check_defconfig(self):
+        """Check the defconfig after savedefconfig
+
+        Returns:
+          Return additional log if moved CONFIGs were removed again by
+          'make savedefconfig'.
+        """
+
+        log = ''
+
+        with open(self.defconfig) as f:
+            defconfig_lines = f.readlines()
+
+        for (action, value) in self.results:
+            if action != ACTION_MOVE:
+                continue
+            if not value + '\n' in defconfig_lines:
+                log += color_text(self.options.color, COLOR_YELLOW,
+                                  "'%s' was removed by savedefconfig.\n" %
+                                  value)
+
+        return log
+
 class Slot:
 
     """A slot to store a subprocess.
@@ -659,6 +684,7 @@ class Slot:
             return False
 
         if self.state == STATE_SAVEDEFCONFIG:
+            self.log += self.parser.check_defconfig()
             if not self.options.dry_run:
                 shutil.move(os.path.join(self.build_dir, 'defconfig'),
                             os.path.join('configs', self.defconfig))
-- 
cgit v0.10.2


From c8e1b10d07b1dbbf3cbf882ac270476b964d05ff Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:07 +0900
Subject: tools: moveconfig: report when defconfig is updated

There are various factors that determine if the given defconfig is
updated, and it is probably what users are more interested in.

Show the log when the defconfig is updated.  Also, copy the file
only when the file content was really updated to avoid changing
the time stamp needlessly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 4881ec5..a8531f1 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -147,6 +147,7 @@ To see the complete list of supported options, run
 
 """
 
+import filecmp
 import fnmatch
 import multiprocessing
 import optparse
@@ -685,9 +686,16 @@ class Slot:
 
         if self.state == STATE_SAVEDEFCONFIG:
             self.log += self.parser.check_defconfig()
-            if not self.options.dry_run:
-                shutil.move(os.path.join(self.build_dir, 'defconfig'),
-                            os.path.join('configs', self.defconfig))
+            orig_defconfig = os.path.join('configs', self.defconfig)
+            new_defconfig = os.path.join(self.build_dir, 'defconfig')
+            updated = not filecmp.cmp(orig_defconfig, new_defconfig)
+
+            if updated:
+                self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+                                       "defconfig was updated.\n")
+
+            if not self.options.dry_run and updated:
+                shutil.move(new_defconfig, orig_defconfig)
             self.finish(True)
             return True
 
-- 
cgit v0.10.2


From 8513dc048598bba15f75ab3fbe257159cb27007a Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:08 +0900
Subject: tools: moveconfig: add --force-sync option

Now, this tools invokes "make savedefconfig" only when it needs to
do so, but there might be cases where a user wants the tool to do
savedefconfig forcibly, for example, some defconfigs were already
out of sync and the user wants to fix it as well.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index a8531f1..95a7356 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -131,6 +131,11 @@ Available options
    Exit immediately if Make exits with a non-zero status while processing
    a defconfig file.
 
+ -s, --force-sync
+   Do "make savedefconfig" forcibly for all the defconfig files.
+   If not specified, "make savedefconfig" only occurs for cases
+   where at least one CONFIG was moved.
+
  -H, --headers-only
    Only cleanup the headers; skip the defconfig processing
 
@@ -672,11 +677,15 @@ class Slot:
             (updated, log) = self.parser.update_dotconfig()
             self.log += log
 
-            if not updated:
+            if not self.options.force_sync and not updated:
                 self.finish(True)
                 return True
-            self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
-                                   "Syncing by savedefconfig...\n")
+            if updated:
+                self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+                                       "Syncing by savedefconfig...\n")
+            else:
+                self.log += "Syncing by savedefconfig (forced by option)...\n"
+
             cmd = list(self.make_cmd)
             cmd.append('savedefconfig')
             self.ps = subprocess.Popen(cmd, stdout=self.devnull,
@@ -887,6 +896,8 @@ def main():
     parser.add_option('-e', '--exit-on-error', action='store_true',
                       default=False,
                       help='exit immediately on any error')
+    parser.add_option('-s', '--force-sync', action='store_true', default=False,
+                      help='force sync by savedefconfig')
     parser.add_option('-H', '--headers-only', dest='cleanup_headers_only',
                       action='store_true', default=False,
                       help='only cleanup the headers')
-- 
cgit v0.10.2


From 6a9f79f712dfce7c451c26120ffc112d3e1a88e7 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 19 May 2016 15:52:09 +0900
Subject: tools: moveconfig: allow to run without any CONFIG specified

I found "tools/moveconfig -s" might be useful for defconfig re-sync.
I could optimize it for re-sync if I wanted, but I do not want to
make the code complex for this feature.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 95a7356..eee28b3 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -839,10 +839,13 @@ def move_config(configs, options):
       options: option flags
     """
     if len(configs) == 0:
-        print 'Nothing to do. exit.'
-        sys.exit(0)
-
-    print 'Move %s (jobs: %d)' % (', '.join(configs), options.jobs)
+        if options.force_sync:
+            print 'No CONFIG is specified. You are probably syncing defconfigs.',
+        else:
+            print 'Neither CONFIG nor --force-sync is specified. Nothing will happen.',
+    else:
+        print 'Move ' + ', '.join(configs),
+    print '(jobs: %d)\n' % options.jobs
 
     if options.defconfigs:
         defconfigs = [line.strip() for line in open(options.defconfigs)]
@@ -909,7 +912,7 @@ def main():
 
     (options, configs) = parser.parse_args()
 
-    if len(configs) == 0:
+    if len(configs) == 0 and not options.force_sync:
         parser.print_usage()
         sys.exit(1)
 
@@ -926,7 +929,8 @@ def main():
     if not options.cleanup_headers_only:
         move_config(configs, options)
 
-    cleanup_headers(configs, options.dry_run)
+    if configs:
+        cleanup_headers(configs, options.dry_run)
 
 if __name__ == '__main__':
     main()
-- 
cgit v0.10.2


From e307fa9d89e0f12e900c0fe80c76453fc1c7c2b6 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 8 Jun 2016 11:47:37 +0900
Subject: tools: moveconfig: make Slot.poll() more readable with helper methods

The Slot.poll() method is already complicated and a new feature
we are going to add will make it more difficult to understand
the execution flow.

Refactor it with helper methods, .handle_error(), .do_defconfig(),
.do_autoconf(), .do_savedefconfig, and .update_defconfig().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index eee28b3..9bbcead 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -633,13 +633,10 @@ class Slot:
         """
         if self.state != STATE_IDLE:
             return False
-        cmd = list(self.make_cmd)
-        cmd.append(defconfig)
-        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   stderr=subprocess.PIPE)
+
         self.defconfig = defconfig
-        self.state = STATE_DEFCONFIG
         self.log = ''
+        self.do_defconfig()
         return True
 
     def poll(self):
@@ -665,55 +662,46 @@ class Slot:
             return False
 
         if self.ps.poll() != 0:
-            self.log += color_text(self.options.color, COLOR_LIGHT_RED,
-                                   "Failed to process.\n")
-            if self.options.verbose:
-                self.log += color_text(self.options.color, COLOR_LIGHT_CYAN,
-                                       self.ps.stderr.read())
-            self.finish(False)
-            return True
+            self.handle_error()
+        elif self.state == STATE_DEFCONFIG:
+            self.do_autoconf()
+        elif self.state == STATE_AUTOCONF:
+            self.do_savedefconfig()
+        elif self.state == STATE_SAVEDEFCONFIG:
+            self.update_defconfig()
+        else:
+            sys.exit("Internal Error. This should not happen.")
 
-        if self.state == STATE_AUTOCONF:
-            (updated, log) = self.parser.update_dotconfig()
-            self.log += log
+        return True if self.state == STATE_IDLE else False
 
-            if not self.options.force_sync and not updated:
-                self.finish(True)
-                return True
-            if updated:
-                self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
-                                       "Syncing by savedefconfig...\n")
-            else:
-                self.log += "Syncing by savedefconfig (forced by option)...\n"
+    def handle_error(self):
+        """Handle error cases."""
 
-            cmd = list(self.make_cmd)
-            cmd.append('savedefconfig')
-            self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                       stderr=subprocess.PIPE)
-            self.state = STATE_SAVEDEFCONFIG
-            return False
+        self.log += color_text(self.options.color, COLOR_LIGHT_RED,
+                               "Failed to process.\n")
+        if self.options.verbose:
+            self.log += color_text(self.options.color, COLOR_LIGHT_CYAN,
+                                   self.ps.stderr.read())
+        self.finish(False)
 
-        if self.state == STATE_SAVEDEFCONFIG:
-            self.log += self.parser.check_defconfig()
-            orig_defconfig = os.path.join('configs', self.defconfig)
-            new_defconfig = os.path.join(self.build_dir, 'defconfig')
-            updated = not filecmp.cmp(orig_defconfig, new_defconfig)
+    def do_defconfig(self):
+        """Run 'make <board>_defconfig' to create the .config file."""
 
-            if updated:
-                self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
-                                       "defconfig was updated.\n")
+        cmd = list(self.make_cmd)
+        cmd.append(self.defconfig)
+        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+                                   stderr=subprocess.PIPE)
+        self.state = STATE_DEFCONFIG
 
-            if not self.options.dry_run and updated:
-                shutil.move(new_defconfig, orig_defconfig)
-            self.finish(True)
-            return True
+    def do_autoconf(self):
+        """Run 'make include/config/auto.conf'."""
 
         self.cross_compile = self.parser.get_cross_compile()
         if self.cross_compile is None:
             self.log += color_text(self.options.color, COLOR_YELLOW,
                                    "Compiler is missing.  Do nothing.\n")
             self.finish(False)
-            return True
+            return
 
         cmd = list(self.make_cmd)
         if self.cross_compile:
@@ -723,7 +711,43 @@ class Slot:
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
                                    stderr=subprocess.PIPE)
         self.state = STATE_AUTOCONF
-        return False
+
+    def do_savedefconfig(self):
+        """Update the .config and run 'make savedefconfig'."""
+
+        (updated, log) = self.parser.update_dotconfig()
+        self.log += log
+
+        if not self.options.force_sync and not updated:
+            self.finish(True)
+            return
+        if updated:
+            self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+                                   "Syncing by savedefconfig...\n")
+        else:
+            self.log += "Syncing by savedefconfig (forced by option)...\n"
+
+        cmd = list(self.make_cmd)
+        cmd.append('savedefconfig')
+        self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+                                   stderr=subprocess.PIPE)
+        self.state = STATE_SAVEDEFCONFIG
+
+    def update_defconfig(self):
+        """Update the input defconfig and go back to the idle state."""
+
+        self.log += self.parser.check_defconfig()
+        orig_defconfig = os.path.join('configs', self.defconfig)
+        new_defconfig = os.path.join(self.build_dir, 'defconfig')
+        updated = not filecmp.cmp(orig_defconfig, new_defconfig)
+
+        if updated:
+            self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+                                   "defconfig was updated.\n")
+
+        if not self.options.dry_run and updated:
+            shutil.move(new_defconfig, orig_defconfig)
+        self.finish(True)
 
     def finish(self, success):
         """Display log along with progress and go to the idle state.
-- 
cgit v0.10.2


From f2dae751fbaa029cd3b1fe13cb4710f5c52cbc8e Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Fri, 10 Jun 2016 14:53:29 -0500
Subject: tools: moveconfig: Fix another typo

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 9bbcead..d2744c1 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -608,7 +608,7 @@ class Slot:
 
         This function makes sure the temporary directory is cleaned away
         even if Python suddenly dies due to error.  It should be done in here
-        because it is guranteed the destructor is always invoked when the
+        because it is guaranteed the destructor is always invoked when the
         instance of the class gets unreferenced.
 
         If the subprocess is still running, wait until it finishes.
-- 
cgit v0.10.2


From 06cc1d36d0e5ae4954f60bce78f6ac2117c3b357 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Fri, 10 Jun 2016 14:53:30 -0500
Subject: tools: moveconfig: New color used for changed defconfig

The old color blends in with similar messages and makes them not stand
out.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index d2744c1..12a145c 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -742,7 +742,7 @@ class Slot:
         updated = not filecmp.cmp(orig_defconfig, new_defconfig)
 
         if updated:
-            self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+            self.log += color_text(self.options.color, COLOR_LIGHT_BLUE,
                                    "defconfig was updated.\n")
 
         if not self.options.dry_run and updated:
-- 
cgit v0.10.2


From 6b96c1a1ca9e86e0f377f18dc470d054c4509c8a Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Fri, 10 Jun 2016 14:53:32 -0500
Subject: tools: moveconfig: Add a new --git-ref option

This option allows the 'make autoconf.mk' step to run against a former
repo state, while the savedefconfig step runs against the current repo
state. This is convenient for the case where something in the Kconfig
has changed such that the defconfig is no longer complete with the new
Kconfigs. This feature allows the .config to be built assuming those old
Kconfigs, but then savedefconfig based on the new state of the Kconfigs.

If in doubt, always specify this switch. It will always do the right
thing even if not required, but if it was required and you don't use it,
the moved configs will be incorrect. When not using this switch, you
must very carefully evaluate that all moved configs are correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 12a145c..5e5ca06 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -143,6 +143,14 @@ Available options
    Specify the number of threads to run simultaneously.  If not specified,
    the number of threads is the same as the number of CPU cores.
 
+ -r, --git-ref
+   Specify the git ref to clone for building the autoconf.mk. If unspecified
+   use the CWD. This is useful for when changes to the Kconfig affect the
+   default values and you want to capture the state of the defconfig from
+   before that change was in effect. If in doubt, specify a ref pre-Kconfig
+   changes (use HEAD if Kconfig changes are not committed). Worst case it will
+   take a bit longer to run, but will always do the right thing.
+
  -v, --verbose
    Show any build errors as boards are built
 
@@ -584,7 +592,7 @@ class Slot:
     for faster processing.
     """
 
-    def __init__(self, configs, options, progress, devnull, make_cmd):
+    def __init__(self, configs, options, progress, devnull, make_cmd, reference_src_dir):
         """Create a new process slot.
 
         Arguments:
@@ -593,12 +601,15 @@ class Slot:
           progress: A progress indicator.
           devnull: A file object of '/dev/null'.
           make_cmd: command name of GNU Make.
+          reference_src_dir: Determine the true starting config state from this
+                             source tree.
         """
         self.options = options
         self.progress = progress
         self.build_dir = tempfile.mkdtemp()
         self.devnull = devnull
         self.make_cmd = (make_cmd, 'O=' + self.build_dir)
+        self.reference_src_dir = reference_src_dir
         self.parser = KconfigParser(configs, options, self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = []
@@ -636,6 +647,7 @@ class Slot:
 
         self.defconfig = defconfig
         self.log = ''
+        self.use_git_ref = True if self.options.git_ref else False
         self.do_defconfig()
         return True
 
@@ -664,9 +676,16 @@ class Slot:
         if self.ps.poll() != 0:
             self.handle_error()
         elif self.state == STATE_DEFCONFIG:
-            self.do_autoconf()
+            if self.options.git_ref and not self.use_git_ref:
+                self.do_savedefconfig()
+            else:
+                self.do_autoconf()
         elif self.state == STATE_AUTOCONF:
-            self.do_savedefconfig()
+            if self.use_git_ref:
+                self.use_git_ref = False
+                self.do_defconfig()
+            else:
+                self.do_savedefconfig()
         elif self.state == STATE_SAVEDEFCONFIG:
             self.update_defconfig()
         else:
@@ -689,6 +708,9 @@ class Slot:
 
         cmd = list(self.make_cmd)
         cmd.append(self.defconfig)
+        if self.use_git_ref:
+            cmd.append('-C')
+            cmd.append(self.reference_src_dir)
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
                                    stderr=subprocess.PIPE)
         self.state = STATE_DEFCONFIG
@@ -708,6 +730,9 @@ class Slot:
             cmd.append('CROSS_COMPILE=%s' % self.cross_compile)
         cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
         cmd.append('include/config/auto.conf')
+        if self.use_git_ref:
+            cmd.append('-C')
+            cmd.append(self.reference_src_dir)
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
                                    stderr=subprocess.PIPE)
         self.state = STATE_AUTOCONF
@@ -784,13 +809,15 @@ class Slots:
 
     """Controller of the array of subprocess slots."""
 
-    def __init__(self, configs, options, progress):
+    def __init__(self, configs, options, progress, reference_src_dir):
         """Create a new slots controller.
 
         Arguments:
           configs: A list of CONFIGs to move.
           options: option flags.
           progress: A progress indicator.
+          reference_src_dir: Determine the true starting config state from this
+                             source tree.
         """
         self.options = options
         self.slots = []
@@ -798,7 +825,7 @@ class Slots:
         make_cmd = get_make_cmd()
         for i in range(options.jobs):
             self.slots.append(Slot(configs, options, progress, devnull,
-                                   make_cmd))
+                                   make_cmd, reference_src_dir))
 
     def add(self, defconfig):
         """Add a new subprocess if a vacant slot is found.
@@ -855,6 +882,24 @@ class Slots:
                 for board in failed_boards:
                     f.write(board + '\n')
 
+class WorkDir:
+    def __init__(self):
+        """Create a new working directory."""
+        self.work_dir = tempfile.mkdtemp()
+
+    def __del__(self):
+        """Delete the working directory
+
+        This function makes sure the temporary directory is cleaned away
+        even if Python suddenly dies due to error.  It should be done in here
+        because it is guaranteed the destructor is always invoked when the
+        instance of the class gets unreferenced.
+        """
+        shutil.rmtree(self.work_dir)
+
+    def get(self):
+        return self.work_dir
+
 def move_config(configs, options):
     """Move config options to defconfig files.
 
@@ -871,6 +916,21 @@ def move_config(configs, options):
         print 'Move ' + ', '.join(configs),
     print '(jobs: %d)\n' % options.jobs
 
+    reference_src_dir = ''
+
+    if options.git_ref:
+        work_dir = WorkDir()
+        reference_src_dir = work_dir.get()
+        print "Cloning git repo to a separate work directory..."
+        subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
+                                cwd=reference_src_dir)
+        print "Checkout '%s' to build the original autoconf.mk." % \
+            subprocess.check_output(['git', 'rev-parse', '--short',
+                                    options.git_ref]).strip()
+        subprocess.check_output(['git', 'checkout', options.git_ref],
+                                stderr=subprocess.STDOUT,
+                                cwd=reference_src_dir)
+
     if options.defconfigs:
         defconfigs = [line.strip() for line in open(options.defconfigs)]
         for i, defconfig in enumerate(defconfigs):
@@ -888,7 +948,7 @@ def move_config(configs, options):
                 defconfigs.append(os.path.join(dirpath, filename))
 
     progress = Progress(len(defconfigs))
-    slots = Slots(configs, options, progress)
+    slots = Slots(configs, options, progress, reference_src_dir)
 
     # Main loop to process defconfig files:
     #  Add a new subprocess into a vacant slot.
@@ -930,6 +990,8 @@ def main():
                       help='only cleanup the headers')
     parser.add_option('-j', '--jobs', type='int', default=cpu_count,
                       help='the number of jobs to run simultaneously')
+    parser.add_option('-r', '--git-ref', type='string',
+                      help='the git ref to clone for building the autoconf.mk')
     parser.add_option('-v', '--verbose', action='store_true', default=False,
                       help='show any build errors as boards are built')
     parser.usage += ' CONFIG ...'
-- 
cgit v0.10.2


From cd51878e34f6beef8ec7b66886e5a23a64b88653 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 11 Jun 2016 18:44:10 +0900
Subject: tools: fix define2mk.sed to not add quotes around negative integers

The sed script, tools/scripts/define2mk.sed, converts config defines
from C headers into include/autoconf.mk for the use in Makefiles.

I found the tool adds quotes around negative integer values.

For example, at the point of the v2016.07-rc1 tag,
include/configs/microblaze-generic.h defines
  #define CONFIG_BOOTDELAY         -1     /* -1 disables auto-boot */

Because it is an integer option, it should be converted to:
  CONFIG_BOOTDELAY=-1

But, the script actually converts it to:
  CONFIG_BOOTDELAY="-1"

This is a fatal problem for the tools/moveconfig.py because it parses
include/autoconf.mk for the config defines from the board headers.
CONFIG_BOOTDELAY="-1" is considered as a string type option and it
is dropped due to the type mismatch from the entry in Kconfig.

This commit fixes the script so that the tools/moveconfig.py can
correctly convert integer options with a negative value.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/scripts/define2mk.sed b/tools/scripts/define2mk.sed
index c641edf..0f00285 100644
--- a/tools/scripts/define2mk.sed
+++ b/tools/scripts/define2mk.sed
@@ -22,6 +22,8 @@
 	s/=\(..*\)/="\1"/;
 	# but remove again from decimal numbers
 	s/="\([0-9][0-9]*\)"/=\1/;
+	# ... and from negative decimal numbers
+	s/="\(-[1-9][0-9]*\)"/=\1/;
 	# ... and from hex numbers
 	s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
 	# ... and from configs defined from other configs
-- 
cgit v0.10.2


From 2c15534f6b5b2157b7c93b6d7c59e26989afb069 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 11 Jun 2016 18:44:08 +0900
Subject: ARM: stm32: remove unused CONFIG_AUTOBOOT

At this point, this is not referenced from anywhere, so remove it
(but it will be re-added later for a different meaning).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 8bbe580..f05c1aa 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -82,8 +82,6 @@
 	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
 	"bootm 0x08044000 - 0x08042000\0"
 
-#define CONFIG_AUTOBOOT
-
 /*
  * Command line configuration.
  */
-- 
cgit v0.10.2


From 3865b9ebe73eb6246ff2ab6ae7957f507eb539f7 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sat, 11 Jun 2016 18:44:09 +0900
Subject: autoboot: follow-up cleanup after CONFIG_BOOTDELAY moves

Tidy up garbage left by commit bb597c0eeb7e ("common: bootdelay: move
CONFIG_BOOTDELAY into a Kconfig option").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 1307607..502ddad 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -97,11 +97,6 @@
 /*
  * Env Settings
  */
-#ifndef CONFIG_BOOTDELAY
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# else
-# endif
-#endif
 #ifndef CONFIG_BOOTCOMMAND
 # define CONFIG_BOOTCOMMAND	"run ramboot"
 #endif
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 27f38f4..fb49322 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -59,9 +59,6 @@
 #endif
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
-#ifndef CONFIG_BOOTDELAY
-#endif
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX       1
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 5e5656d..fbc6de6 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -34,9 +34,6 @@
 #define CONFIG_LOADADDR                 0x80800000
 #define CONFIG_SYS_TEXT_BASE            0x87800000
 
-#ifndef CONFIG_BOOTDELAY
-#endif
-
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX               1
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 96c3c4b..82e0d50 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -73,8 +73,6 @@
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-/* override default CONFIG_BOOTDELAY */
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"machid=ffffffff\0" \
 	"fdt_high=0x87000000\0" \
-- 
cgit v0.10.2


From c1f51e0f3edca57273ff524714b69345ce627996 Mon Sep 17 00:00:00 2001
From: Marcin Niestroj <m.niestroj@grinn-global.com>
Date: Tue, 24 May 2016 14:59:55 +0200
Subject: common: env_ubi: Clear environment buffer before reading

In case we have restarted u-boot there is a chance that environment
buffer contains old environment (from the previous boot). If UBI volume
is zero size, ubi_volume_read() doesn't modify the buffer and exits
successfully.

We need to clear buffer manually before reading it from UBI, so the
invalid CRC will cause setting default environment in case that the UBI
volume is zero size.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>

diff --git a/common/env_ubi.c b/common/env_ubi.c
index e611199..0ac2f65 100644
--- a/common/env_ubi.c
+++ b/common/env_ubi.c
@@ -115,6 +115,17 @@ void env_relocate_spec(void)
 	int crc1_ok = 0, crc2_ok = 0;
 	env_t *ep, *tmp_env1, *tmp_env2;
 
+	/*
+	 * In case we have restarted u-boot there is a chance that buffer
+	 * contains old environment (from the previous boot).
+	 * If UBI volume is zero size, ubi_volume_read() doesn't modify the
+	 * buffer.
+	 * We need to clear buffer manually here, so the invalid CRC will
+	 * cause setting default environment as expected.
+	 */
+	memset(env1_buf, 0x0, CONFIG_ENV_SIZE);
+	memset(env2_buf, 0x0, CONFIG_ENV_SIZE);
+
 	tmp_env1 = (env_t *)env1_buf;
 	tmp_env2 = (env_t *)env2_buf;
 
@@ -174,6 +185,16 @@ void env_relocate_spec(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
 
+	/*
+	 * In case we have restarted u-boot there is a chance that buffer
+	 * contains old environment (from the previous boot).
+	 * If UBI volume is zero size, ubi_volume_read() doesn't modify the
+	 * buffer.
+	 * We need to clear buffer manually here, so the invalid CRC will
+	 * cause setting default environment as expected.
+	 */
+	memset(buf, 0x0, CONFIG_ENV_SIZE);
+
 	if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
 		printf("\n** Cannot find mtd partition \"%s\"\n",
 		       CONFIG_ENV_UBI_PART);
-- 
cgit v0.10.2


From bd91508b50ade5c73b3749bf4e5ede31d2da7ef8 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Wed, 8 Jun 2016 07:57:19 +0300
Subject: arc/cache: really do invalidate_dcache_all() even if IOC exists

invalidate_dcache_all() could be used in different use-cases
and what is especially important most of those cases won't be
related to DMAed data to or from peripherals, i.e. we'll be doing
invalidation of data used purely by CPU cores.

Given that IOC engine only snoops data that goes through DMA
we need to care ourselves about data used only by CPU cores
and so remove dependency on IOC from invalidate_dcache_all()
and always do real invalidation.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index d1fb661..a27499e 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -417,13 +417,10 @@ void flush_cache(unsigned long start, unsigned long size)
 
 void invalidate_dcache_all(void)
 {
-#ifdef CONFIG_ISA_ARCV2
-	if (!ioc_exists)
-#endif
-		__dc_entire_op(OP_INV);
+	__dc_entire_op(OP_INV);
 
 #ifdef CONFIG_ISA_ARCV2
-	if (slc_exists && !ioc_exists)
+	if (slc_exists)
 		__slc_entire_op(OP_INV);
 #endif
 }
-- 
cgit v0.10.2


From a4a43fcf9cca1ebd3d26f9a01b923b7393d69c54 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Wed, 8 Jun 2016 08:04:03 +0300
Subject: arc/cache: Flush & invalidate all caches right before enabling IOC

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index a27499e..b6ec831 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -209,6 +209,9 @@ void cache_init(void)
 	read_decode_cache_bcr_arcv2();
 
 	if (ioc_exists) {
+		flush_dcache_all();
+		invalidate_dcache_all();
+
 		/* IO coherency base - 0x8z */
 		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
 		/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
-- 
cgit v0.10.2


From c7d8db66ffd1c20b6a27445af892c28305e64e8a Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Wed, 8 Jun 2016 08:19:33 +0300
Subject: board: axs10x: Flush entire cache after programming reset vector

Now when we have support of IOC (IO-Coherency block) cahce operations
on regions are tuned to not be dummy stubs if IOC was found and enabled
in the core. That makes flush_dcache_range() useless for our purposes
here. And since we do need to flush modified reset vector to at least L2
cache (AKA SLC) so other cores will see it via its L1 instruction cache
we're using always functional flush_dcache_all() here.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>

diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 84ee2bf..a5e774b 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -54,7 +54,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
 	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
 
 	/* Make sure other cores see written value in memory */
-	flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+	flush_dcache_all();
 }
 
 void smp_kick_all_cpus(void)
-- 
cgit v0.10.2


From 5bea2becf3b6897315fa01d8318df75526855745 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Wed, 8 Jun 2016 08:24:54 +0300
Subject: arc: Update data accessors with use of memory barriers

Memory barriers are proven to be a requirement for both compiler and
real hardware to properly serialize access to critical data.

For example if CPU or data bus it uses may do reordering of data
accesses absence of memory barriers might easily lead to very subtle and
hard to debug data corruptions.

This implementation was heavily borrowed from up to date Linux kernel.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index b6f7724..42e7f22 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -10,6 +10,46 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
+#ifdef CONFIG_ISA_ARCV2
+
+/*
+ * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
+ * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
+ *
+ * Explicit barrier provided by DMB instruction
+ *  - Operand supports fine grained load/store/load+store semantics
+ *  - Ensures that selected memory operation issued before it will complete
+ *    before any subsequent memory operation of same type
+ *  - DMB guarantees SMP as well as local barrier semantics
+ *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
+ *    UP: barrier(), SMP: smp_*mb == *mb)
+ *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
+ *    in the general case. Plus it only provides full barrier.
+ */
+
+#define mb()	asm volatile("dmb 3\n" : : : "memory")
+#define rmb()	asm volatile("dmb 1\n" : : : "memory")
+#define wmb()	asm volatile("dmb 2\n" : : : "memory")
+
+#else
+
+/*
+ * ARCompact based cores (ARC700) only have SYNC instruction which is super
+ * heavy weight as it flushes the pipeline as well.
+ * There are no real SMP implementations of such cores.
+ */
+
+#define mb()	asm volatile("sync\n" : : : "memory")
+#endif
+
+#ifdef CONFIG_ISA_ARCV2
+#define __iormb()		rmb()
+#define __iowmb()		wmb()
+#else
+#define __iormb()		do { } while (0)
+#define __iowmb()		do { } while (0)
+#endif
+
 /*
  * Given a physical address and a length, return a virtual address
  * that can be used to access the memory range with the caching
@@ -72,18 +112,6 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
 	return w;
 }
 
-#define readb __raw_readb
-
-static inline u16 readw(const volatile void __iomem *addr)
-{
-	return __le16_to_cpu(__raw_readw(addr));
-}
-
-static inline u32 readl(const volatile void __iomem *addr)
-{
-	return __le32_to_cpu(__raw_readl(addr));
-}
-
 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
 {
 	__asm__ __volatile__("stb%U1	%0, %1\n"
@@ -108,10 +136,6 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr)
 			     : "memory");
 }
 
-#define writeb __raw_writeb
-#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
-#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
-
 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
 {
 	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
@@ -184,6 +208,45 @@ static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
 	return longlen;
 }
 
+/*
+ * MMIO can also get buffered/optimized in micro-arch, so barriers needed
+ * Based on ARM model for the typical use case
+ *
+ *	<ST [DMA buffer]>
+ *	<writel MMIO "go" reg>
+ *  or:
+ *	<readl MMIO "status" reg>
+ *	<LD [DMA buffer]>
+ *
+ * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
+ */
+#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })
+
+/*
+ * Relaxed API for drivers which can handle barrier ordering themselves
+ *
+ * Also these are defined to perform little endian accesses.
+ * To provide the typical device register semantics of fixed endian,
+ * swap the byte order for Big Endian
+ *
+ * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
+ */
+#define readb_relaxed(c)	__raw_readb(c)
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+					__raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+					__raw_readl(c)); __r; })
+
+#define writeb_relaxed(v,c)	__raw_writeb(v,c)
+#define writew_relaxed(v,c)	__raw_writew((__force u16) cpu_to_le16(v),c)
+#define writel_relaxed(v,c)	__raw_writel((__force u32) cpu_to_le32(v),c)
+
 #define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
 #define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
 
-- 
cgit v0.10.2


From fc1e8fbbb2ea73139c2eadf2f174d6c3fc4ee03f Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Fri, 10 Jun 2016 18:19:25 +0300
Subject: axs103: Bump CPU frequency from 50MHz to 100MHz

In the upcoming release of axs103 v1.1 CPU will
run @100MHz which we support with that change.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 96a3de6..c8474de 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARC=y
 CONFIG_ISA_ARCV2=y
 CONFIG_DM_SERIAL=y
-CONFIG_SYS_CLK_FREQ=50000000
+CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="axs10x"
 CONFIG_BOOTDELAY=3
-- 
cgit v0.10.2


From 43486e4cd094eabdd514ed7a2376ca55655e506f Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Thu, 2 Jun 2016 15:10:56 -0700
Subject: board: arm:: Add support for Broadcom BCM23550

Add support for the Broadcom BCM23550 board.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e75c4c0..9f78fb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -441,6 +441,10 @@ config TARGET_TI816X_EVM
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_BCM23550_W1D
+	bool "Support bcm23550_w1d"
+	select CPU_V7
+
 config TARGET_BCM28155_AP
 	bool "Support bcm28155_ap"
 	select CPU_V7
@@ -898,6 +902,7 @@ source "board/armadeus/apf27/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
+source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 328c4b1..0a5ac97 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -38,6 +38,7 @@ obj-y += s5p-common/
 endif
 
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
+obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
diff --git a/arch/arm/cpu/armv7/bcm235xx/Makefile b/arch/arm/cpu/armv7/bcm235xx/Makefile
new file mode 100644
index 0000000..7fdb263
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= clk-core.o
+obj-y	+= clk-bcm235xx.o
+obj-y	+= clk-sdio.o
+obj-y	+= clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
new file mode 100644
index 0000000..ce3d019
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
@@ -0,0 +1,573 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * bcm235xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K		1000
+#define CLOCK_1M		(CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+	.clk	=	{ \
+		.name	=	#clk_name, \
+		.parent =	clk_parent, \
+		.rate	=	clk_rate, \
+		.div	=	clk_div, \
+		.ops	=	&ref_clk_ops, \
+	}, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal,	0,		26  * CLOCK_1M,	1);
+DECLARE_REF_CLK(var_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(ref_104m,	&ref_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(ref_52m,	&ref_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(ref_13m,	&ref_52m.clk,	13  * CLOCK_1M,	4);
+DECLARE_REF_CLK(var_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(var_104m,	&var_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(var_52m,	&var_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(var_13m,	&var_52m.clk,	13  * CLOCK_1M,	4);
+
+struct refclk_lkup {
+	struct refclk *procclk;
+	const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+	MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+	MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+	MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+	MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+	int i;
+	struct refclk_lkup *tblp = refclk_str_tbl;
+	for (i = 0; i < refclk_entries; i++, tblp++) {
+		if (!(strcmp(name, tblp->name)))
+			return tblp->procclk;
+	}
+	return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	312 * CLOCK_1M,
+	312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	26 * CLOCK_1M,
+	39 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M
+};
+
+unsigned long esub_freq_tbl[8] = {
+	78 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	208 * CLOCK_1M,
+	208 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a28, 0, 3),
+	.div		= DIVIDER(0x0a28, 4, 14),
+	.trig		= TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a2c, 0, 3),
+	.div		= DIVIDER(0x0a2c, 4, 14),
+	.trig		= TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a34, 0, 3),
+	.div		= DIVIDER(0x0a34, 4, 14),
+	.trig		= TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a30, 0, 3),
+	.div		= DIVIDER(0x0a30, 4, 14),
+	.trig		= TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a64, 0, 3),
+	.trig		= TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a68, 0, 3),
+	.trig		= TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a84, 0, 3),
+	.trig		= TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+	.clk = {
+		.name = "kpm_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+	.clk = {
+		.name = "kps_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 2,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.policy0_mask2_offset = 0x00000048,
+	.policy1_mask2_offset = 0x0000004c,
+	.policy2_mask2_offset = 0x00000050,
+	.policy3_mask2_offset = 0x00000054,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = slave_axi_freq_tbl,
+};
+
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+	.clk = {
+		.name = "esub_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = esub_freq_tbl,
+};
+#endif
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
+static struct bus_clock sdio1_ahb_clk = {
+	.clk = {
+		.name = "sdio1_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+	.clk = {
+		.name = "sdio2_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+	.clk = {
+		.name = "sdio3_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+	.clk = {
+		.name = "sdio4_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+	.clk = {
+		.name = "bsc1_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+	.clk = {
+		.name = "bsc2_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+	.clk = {
+		.name = "bsc3_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+	.clk = {
+		.name = "sdio1_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+	.clk = {
+		.name = "sdio2_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+	.clk = {
+		.name = "sdio3_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+	.clk = {
+		.name = "sdio4_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+	.clk = {
+		.name = "sdio1_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+	.clk = {
+		.name = "sdio2_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+	.clk = {
+		.name = "sdio3_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+	.clk = {
+		.name = "sdio4_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+	.clk = {
+		.name = "bsc1_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+	.clk = {
+		.name = "bsc2_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+	.clk = {
+		.name = "bsc3_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+	/* Peripheral clocks */
+	CLK_LK(sdio1),
+	CLK_LK(sdio2),
+	CLK_LK(sdio3),
+	CLK_LK(sdio4),
+	CLK_LK(sdio1_sleep),
+	CLK_LK(sdio2_sleep),
+	CLK_LK(sdio3_sleep),
+	CLK_LK(sdio4_sleep),
+	CLK_LK(bsc1),
+	CLK_LK(bsc2),
+	CLK_LK(bsc3),
+	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
+	CLK_LK(sdio1_ahb),
+	CLK_LK(sdio2_ahb),
+	CLK_LK(sdio3_ahb),
+	CLK_LK(sdio4_ahb),
+	CLK_LK(bsc1_apb),
+	CLK_LK(bsc2_apb),
+	CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+	CLK_LK(esub_ccu),
+#endif
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
new file mode 100644
index 0000000..d263068
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+	int ret;
+	char *bscstr, *apbstr;
+
+	switch ((u32) base) {
+	case PMU_BSC_BASE_ADDR:
+		/* PMU clock is always enabled */
+		return 0;
+	case BSC1_BASE_ADDR:
+		bscstr = "bsc1_clk";
+		apbstr = "bsc1_apb_clk";
+		break;
+	case BSC2_BASE_ADDR:
+		bscstr = "bsc2_clk";
+		apbstr = "bsc2_apb_clk";
+		break;
+	case BSC3_BASE_ADDR:
+		bscstr = "bsc3_clk";
+		apbstr = "bsc3_apb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	/* Note that the bus clock must be enabled first */
+
+	ret = clk_get_and_enable(apbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(bscstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
new file mode 100644
index 0000000..2b5da6b
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * bcm235xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD	0x00a5a501
+#define WR_ACCESS_OFFSET	0	/* common to all clock blocks */
+#define POLICY_CTL_GO		1	/* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL	4	/* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+	int ret = 0;
+	struct clk *c;
+
+	debug("%s: %s\n", __func__, clkstr);
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear). Delay
+ * a microsecond after each read of the register. Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+	unsigned int tries;
+	u32 bit_mask = 1 << bit;
+
+	for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+		u32 val;
+		bool bit_val;
+
+		val = readl(base + offset);
+		bit_val = (val & bit_mask) ? 1 : 0;
+		if (bit_val == want)
+			return 0;	/* success */
+		udelay(1);
+	}
+
+	debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+	      __func__, base + offset, bit, want);
+
+	return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+	int ret = 0;
+	u32 reg;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	struct bcm_clk_gate *gate = &cd->gate;
+	void *base = (void *)c->ccu_clk_mgr_base;
+
+
+	debug("%s: %s\n", __func__, c->name);
+
+	clk_get_rate(c);	/* Make sure rate and sel are filled in */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	if (enable) {
+		debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+		      __func__, c->name, c->rate, c->div, c->sel,
+		      c->parent->rate);
+
+		/*
+		 * clkgate - only software controllable gates are
+		 * supported by u-boot which includes all clocks
+		 * that matter. This avoids bringing in a lot of extra
+		 * complexity as done in the kernel framework.
+		 */
+		if (gate_exists(gate)) {
+			reg = readl(base + cd->gate.offset);
+			reg |= (1 << cd->gate.en_bit);
+			writel(reg, base + cd->gate.offset);
+		}
+
+		/* div and pll select */
+		if (divider_exists(&cd->div)) {
+			reg = readl(base + cd->div.offset);
+			bitfield_replace(reg, cd->div.shift, cd->div.width,
+					 c->div - 1);
+			writel(reg, base + cd->div.offset);
+		}
+
+		/* frequency selector */
+		if (selector_exists(&cd->sel)) {
+			reg = readl(base + cd->sel.offset);
+			bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+					 c->sel);
+			writel(reg, base + cd->sel.offset);
+		}
+
+		/* trigger */
+		if (trigger_exists(&cd->trig)) {
+			writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+			/* wait for trigger status bit to go to 0 */
+			ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+			if (ret)
+				return ret;
+		}
+
+		/* wait for running (status_bit = 1) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+		if (ret)
+			return ret;
+	} else {
+		debug("%s disable clock %s\n", __func__, c->name);
+
+		/* clkgate */
+		reg = readl(base + cd->gate.offset);
+		reg &= ~(1 << cd->gate.en_bit);
+		writel(reg, base + cd->gate.offset);
+
+		/* wait for stop (status_bit = 0) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	int i;
+	unsigned long diff;
+	unsigned long new_rate = 0, div = 1;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	const char **clock;
+
+	debug("%s: %s\n", __func__, c->name);
+	diff = rate;
+
+	i = 0;
+	for (clock = cd->clocks; *clock; clock++, i++) {
+		struct refclk *ref = refclk_str_to_clk(*clock);
+		if (!ref) {
+			printf("%s: Lookup of %s failed\n", __func__, *clock);
+			return -EINVAL;
+		}
+
+		/* round to the new rate */
+		div = ref->clk.rate / rate;
+		if (div == 0)
+			div = 1;
+
+		new_rate = ref->clk.rate / div;
+
+		/* get the min diff */
+		if (abs(new_rate - rate) < diff) {
+			diff = abs(new_rate - rate);
+			c->sel = i;
+			c->parent = &ref->clk;
+			c->rate = new_rate;
+			c->div = div;
+		}
+	}
+
+	debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+	      c->name, c->rate, c->div, c->sel, c->parent->rate);
+	return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int div = 1;
+	const char **clock;
+	struct refclk *ref;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (selector_exists(&cd->sel)) {
+		reg = readl(base + cd->sel.offset);
+		c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+	} else {
+		/*
+		 * For peri clocks that don't have a selector, the single
+		 * reference clock will always exist at index 0.
+		 */
+		c->sel = 0;
+	}
+
+	if (divider_exists(&cd->div)) {
+		reg = readl(base + cd->div.offset);
+		div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+		div += 1;
+	}
+
+	clock = cd->clocks;
+	ref = refclk_str_to_clk(clock[c->sel]);
+	if (!ref) {
+		printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+		return 0;
+	}
+
+	c->parent = &ref->clk;
+	c->div = div;
+	c->rate = c->parent->rate / c->div;
+	debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+	      c->parent->rate, div, c->sel, c->rate);
+
+	return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+	.enable = peri_clk_enable,
+	.set_rate = peri_clk_set_rate,
+	.get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!enable)
+		return -EINVAL;	/* CCU clock cannot shutdown */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* config enable for policy engine */
+	writel(1, base + ccu_clk->lvm_en_offset);
+
+	/* wait for bit to go to 0 */
+	ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* freq ID */
+	if (!ccu_clk->freq_bit_shift)
+		ccu_clk->freq_bit_shift = 8;
+
+	/* Set frequency id for each of the 4 policies */
+	reg = ccu_clk->freq_id |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+	writel(reg, base + ccu_clk->policy_freq_offset);
+
+	/* enable all clock mask */
+	writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+	if (ccu_clk->num_policy_masks == 2) {
+		writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+	}
+
+	/* start policy engine */
+	reg = readl(base + ccu_clk->policy_ctl_offset);
+	reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+	writel(reg, base + ccu_clk->policy_ctl_offset);
+
+	/* wait till started */
+	ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	debug("%s: %s\n", __func__, c->name);
+	c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+	return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+	.enable = ccu_clk_enable,
+	.get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct bus_clk_data *cd = bus_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* enable gating */
+	reg = readl(base + cd->gate.offset);
+	if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+		debug("%s already %s\n", c->name,
+		      enable ? "enabled" : "disabled");
+	else {
+		int want = (enable) ? 1 : 0;
+		reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+		if (enable)
+			reg |= (1 << cd->gate.en_bit);
+		else
+			reg &= ~(1 << cd->gate.en_bit);
+
+		writel(reg, base + cd->gate.offset);
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+			       want);
+		if (ret)
+			return ret;
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct ccu_clock *ccu_clk;
+
+	debug("%s: %s\n", __func__, c->name);
+	ccu_clk = to_ccu_clk(c->parent);
+
+	c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+	c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+	return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+	.enable = bus_clk_enable,
+	.get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+	debug("%s: %s\n", __func__, c->name);
+	return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+	.enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+	debug("%s:\n", __func__);
+	return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+	int i;
+	struct clk_lookup *clk_tblp;
+
+	debug("%s: %s\n", __func__, con_id);
+
+	clk_tblp = arch_clk_tbl;
+	for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+		if (clk_tblp->con_id) {
+			if (!con_id || strcmp(clk_tblp->con_id, con_id))
+				continue;
+			return clk_tblp->clk;
+		}
+	}
+	return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+	int ret = 0;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return -1;
+
+	/* enable parent clock first */
+	if (c->parent)
+		ret = clk_enable(c->parent);
+
+	if (ret)
+		return ret;
+
+	if (!c->use_cnt) {
+		c->use_cnt++;
+		ret = c->ops->enable(c, 1);
+	}
+
+	return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return;
+
+	if (c->use_cnt) {
+		c->use_cnt--;
+		c->ops->enable(c, 0);
+	}
+
+	/* disable parent */
+	if (c->parent)
+		clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long rate;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c || !c->ops || !c->ops->get_rate)
+		return 0;
+
+	rate = c->ops->get_rate(c);
+	debug("%s: rate = %ld\n", __func__, rate);
+	return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret;
+
+	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+	if (!c || !c->ops || !c->ops->set_rate)
+		return -EINVAL;
+
+	if (c->use_cnt)
+		return -EINVAL;
+
+	ret = c->ops->set_rate(c, rate);
+
+	return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.h b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
new file mode 100644
index 0000000..de9a1ef
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.h
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+	printf("Write [0x%p] = 0x%08x\n", addr, val);
+	*(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+	u32 val = *(u32 *)addr;
+	printf("Read  [0x%p] = 0x%08x\n", addr, val);
+	return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+	const char *dev_id;
+	const char *con_id;
+	struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+	int (*enable)(struct clk *c, int enable);
+	int (*set_rate)(struct clk *c, unsigned long rate);
+	unsigned long (*get_rate)(struct clk *c);
+	unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+	int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+struct clk {
+	struct clk *parent;
+	const char *name;
+	int use_cnt;
+	unsigned long rate;	/* in HZ */
+
+	/* programmable divider. 0 means fixed ratio to parent clock */
+	unsigned long div;
+
+	struct clk_src *src;
+	struct clk_ops *ops;
+
+	unsigned long ccu_clk_mgr_base;
+	int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX	((u32)U8_MAX)
+
+#define BAD_CLK_INDEX		U8_MAX	/* Can't ever be valid */
+#define BAD_CLK_NAME		((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE	U64_MAX
+
+/*
+ * Utility macros for object flag management. If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag)		BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div)		FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div)		FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div)	(!divider_is_fixed(div) && \
+						(div)->frac_width > 0)
+
+#define selector_exists(sel)		((sel)->width != 0)
+#define trigger_exists(trig)		FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+	bcm_clk_none,		/* undefined clock type */
+	bcm_clk_bus,
+	bcm_clk_core,
+	bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ *     A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ *     Enabling or disabling clocks with this type of gate is
+ *     managed automatically by the hardware. Such clocks can be
+ *     considered by the software to be enabled. The current status
+ *     of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ *     Auto-gating is not available for this type of clock.
+ *     Instead, software manages whether it's enabled by setting or
+ *     clearing the enable bit. The current gate status of a gate
+ *     under software control can be read from the gate status bit.
+ *     To ensure a change to the gating status is complete, the
+ *     status bit can be polled to verify that the gate has entered
+ *     the desired state.
+ * - selectable hardware or software gating
+ *     Gating for this type of clock can be configured to be either
+ *     under software or hardware control. Which type is in use is
+ *     determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+	u32 offset;		/* gate register offset */
+	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
+	u32 en_bit;		/* 0: disable; 1: enable */
+	u32 hw_sw_sel_bit;	/* 0: hardware gating; 1: software gating */
+	u32 flags;		/* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ *   HW         means this gate can be auto-gated
+ *   SW         means the state of this gate can be software controlled
+ *   NO_DISABLE means this gate is (only) enabled if under software control
+ *   SW_MANAGED means the status of this gate is under software control
+ *   ENABLED    means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE	((u32)1 << 3)	/* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED	((u32)1 << 5)	/* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
+	}
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)			\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
+			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
+	}
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit)				\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
+	}
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock. Each divider can be either fixed or
+ * variable. If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider. If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register. The position of the field in the
+ * register is defined by its offset and width. The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider. Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point. Most variable dividers have zero
+ * fractional bits. Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only. (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values. A scaled value is one that's
+ * been left-shifted by the fractional width of a divider. Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified. To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate). In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+	union {
+		struct {	/* variable divider */
+			u32 offset;	/* divider register offset */
+			u32 shift;	/* field shift */
+			u32 width;	/* field width */
+			u32 frac_width;	/* field fraction width */
+
+			u64 scaled_div;	/* scaled divider value */
+		};
+		u32 fixed;	/* non-zero fixed divider value */
+	};
+	u32 flags;		/* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ *   EXISTS means this divider exists
+ *   FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value)						\
+	{								\
+		.fixed = (_value),					\
+		.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),		\
+	}
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)		\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.frac_width = (_frac_width),				\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/*
+ * Clocks may have multiple "parent" clocks. If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use. The selected clock is indicated in a
+ * sub-field of a 32-bit selector register. The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks. Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+	u32 offset;		/* selector register offset */
+	u32 shift;		/* field shift */
+	u32 width;		/* field width */
+
+	u32 parent_count;	/* number of entries in parent_sel[] */
+	u32 *parent_sel;	/* array of parent selector values */
+	u8 clk_index;		/* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.clk_index = BAD_CLK_INDEX,				\
+	}
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger. A trigger is defined by a single
+ * bit within a register. To signal a change, a 1 is written into
+ * that bit. To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger. In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+	u32 offset;		/* trigger register offset */
+	u32 bit;		/* trigger bit */
+	u32 flags;		/* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ *   EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS	((u32)1 << 0)	/* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit)						\
+	{								\
+		.offset = (_offset),					\
+		.bit = (_bit),						\
+		.flags = FLAG(TRIG, EXISTS),				\
+	}
+
+struct bus_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+	struct bcm_clk_gate gate;
+	struct bcm_clk_trig pre_trig;
+	struct bcm_clk_div pre_div;
+	struct bcm_clk_trig trig;
+	struct bcm_clk_div div;
+	struct bcm_clk_sel sel;
+	const char *clocks[];	/* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...)	{ __VA_ARGS__, NULL, }
+#define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
+
+struct refclk {
+	struct clk clk;
+};
+
+struct peri_clock {
+	struct clk clk;
+	struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+	struct clk clk;
+
+	int num_policy_masks;
+	unsigned long policy_freq_offset;
+	int freq_bit_shift;	/* 8 for most CCUs */
+	unsigned long policy_ctl_offset;
+	unsigned long policy0_mask_offset;
+	unsigned long policy1_mask_offset;
+	unsigned long policy2_mask_offset;
+	unsigned long policy3_mask_offset;
+	unsigned long policy0_mask2_offset;
+	unsigned long policy1_mask2_offset;
+	unsigned long policy2_mask2_offset;
+	unsigned long policy3_mask2_offset;
+	unsigned long lvm_en_offset;
+
+	int freq_id;
+	unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+	struct clk clk;
+	struct bus_clk_data *data;
+	unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+	struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+	return a == b;
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+	return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+	return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+	return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+	return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+	return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+int clk_get_and_enable(char *clkstr);
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
new file mode 100644
index 0000000..b0b92b9
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR			ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD				0xA5A500
+
+#define PLLE_POST_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK		0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK	0x00000001
+
+#define PLL_LOCK_ADDR			(ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK			0x00000001
+
+#define ESW_SYS_DIV_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK			0x00000300
+#define ESW_SYS_DIV_DIV_MASK				0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT		0x00000100
+#define ESW_SYS_DIV_DIV_SELECT				0x4
+#define ESW_SYS_DIV_TRIGGER_MASK			0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK		0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK	0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT	0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK			0x00000001
+
+#define PLL_MAX_RETRY	100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+	int rc = -1;
+	int retry_count = 0;
+	rc = clk_get_and_enable("esub_ccu_clk");
+
+	/* Enable Access to CCU registers */
+	writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+	writel(readl(PLLE_POST_RESETB_ADDR) &
+	       ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Take PLL out of reset and put into normal mode */
+	writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+	       PLLE_RESETB_ADDR);
+
+	/* Wait for PLL lock */
+	rc = -1;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	writel(readl(PLLE_POST_RESETB_ADDR) |
+	       PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+	writel((readl(ESW_SYS_DIV_ADDR) &
+		~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+	       ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+	       ESW_SYS_DIV_ADDR);
+
+	writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+	       ESW_SYS_DIV_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* switch Esub AXI clock to 208MHz */
+	writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+		  ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+		  ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+	       ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+	       ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+	       ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		      ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* Disable Access to CCU registers */
+	writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+	return rc;
+}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
new file mode 100644
index 0000000..b2ce6d6
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	int ret;
+	struct clk *c;
+
+	char *clkstr;
+	char *slpstr;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case CONFIG_SYS_SDIO_BASE0:
+		clkstr = CONFIG_SYS_SDIO0 "_clk";
+		ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE1:
+		clkstr = CONFIG_SYS_SDIO1 "_clk";
+		ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE2:
+		clkstr = CONFIG_SYS_SDIO2 "_clk";
+		ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE3:
+		clkstr = CONFIG_SYS_SDIO3 "_clk";
+		ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(slpstr);
+	if (ret)
+		return ret;
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_set_rate(c, rate);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	*actual_ratep = rate;
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
new file mode 100644
index 0000000..1d7c5af
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	return clk_get_and_enable(ahbstr);
+}
diff --git a/arch/arm/cpu/armv7/kona-common/Makefile b/arch/arm/cpu/armv7/kona-common/Makefile
index da225cb..5167ebb 100644
--- a/arch/arm/cpu/armv7/kona-common/Makefile
+++ b/arch/arm/cpu/armv7/kona-common/Makefile
@@ -7,3 +7,4 @@
 obj-y	+= s_init.o
 obj-y	+= hwinit-common.o
 obj-y	+= clk-stubs.o
+obj-${CONFIG_KONA_RESET_S} += reset.o
diff --git a/arch/arm/cpu/armv7/kona-common/reset.S b/arch/arm/cpu/armv7/kona-common/reset.S
new file mode 100644
index 0000000..220a1ec
--- /dev/null
+++ b/arch/arm/cpu/armv7/kona-common/reset.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =0x35001f00
+	ldr	r2, [r1]
+	ldr	r4, =0x80000000
+	and	r4, r2, r4
+	ldr	r3, =0xA5A500
+	orr	r4, r4, r3
+	orr	r4, r4, #0x1
+
+	str	r4, [r1]
+
+	ldr	r1, =0x35001f04
+	ldr	r2, [r1]
+	ldr	r4, =0x80000000
+	and	r4, r2, r4
+	str	r4, [r1]
+
+_loop_forever:
+	b	_loop_forever
diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h
new file mode 100644
index 0000000..da31f98
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM235XX_GPIO_H
+#define __ARCH_BCM235XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
new file mode 100644
index 0000000..90eb2ff
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM235XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR		0x3e016000
+#define BSC2_BASE_ADDR		0x3e017000
+#define BSC3_BASE_ADDR		0x3e018000
+#define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
+#define KONA_MST_CLK_BASE_ADDR	0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
+#define PMU_BSC_BASE_ADDR	0x3500d000
+#define SDIO1_BASE_ADDR		0x3f180000
+#define SDIO2_BASE_ADDR		0x3f190000
+#define SDIO3_BASE_ADDR		0x3f1a0000
+#define SDIO4_BASE_ADDR		0x3f1b0000
+#define TIMER_BASE_ADDR		0x3e00d000
+
+#define HSOTG_DCTL_OFFSET					0x00000804
+#define    HSOTG_DCTL_SFTDISCON_MASK				0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET				0x00000008
+#define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK			0x00000002
+#define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK		0x00000001
+
+#endif
diff --git a/board/broadcom/bcm23550_w1d/Kconfig b/board/broadcom/bcm23550_w1d/Kconfig
new file mode 100644
index 0000000..007a127
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCM23550_W1D
+
+config SYS_BOARD
+	default "bcm23550_w1d"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "bcm235xx"
+
+config SYS_CONFIG_NAME
+	default "bcm23550_w1d"
+
+endif
diff --git a/board/broadcom/bcm23550_w1d/MAINTAINERS b/board/broadcom/bcm23550_w1d/MAINTAINERS
new file mode 100644
index 0000000..fdaa539
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM23550_W1D BOARD
+M:	Steve Rae <srae@broadcom.com>
+S:	Maintained
+F:	board/broadcom/bcm23550_w1d/
+F:	include/configs/bcm23550_w1d.h
+F:	configs/bcm23550_w1d_defconfig
diff --git a/board/broadcom/bcm23550_w1d/Makefile b/board/broadcom/bcm23550_w1d/Makefile
new file mode 100644
index 0000000..76bd032
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= bcm23550_w1d.o
diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
new file mode 100644
index 0000000..0cb059f
--- /dev/null
+++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <g_dnl.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET	0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT	27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT	26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT	20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT	0
+
+#ifndef CONFIG_USB_SERIALNO
+#define CONFIG_USB_SERIALNO "1234567890"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+	printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	clk_init();
+
+	return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+	return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+	int ret = 0;
+
+	/* Register eMMC - SDIO2 */
+	ret = kona_sdhci_init(1, 400000, 0);
+	if (ret)
+		return ret;
+
+	/* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+	ret = kona_sdhci_init(3, 400000, 0);
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+static struct dwc2_plat_otg_data bcm_otg_data = {
+	.regs_otg	= HSOTG_BASE_ADDR
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("%s: performing dwc2_udc_probe\n", __func__);
+	return dwc2_udc_probe(&bcm_otg_data);
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	debug("%s\n", __func__);
+	if (!getenv("serial#"))
+		g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
+	return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	debug("%s\n", __func__);
+	return 1;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	debug("%s\n", __func__);
+	return 0;
+}
+#endif
diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
new file mode 100644
index 0000000..3328e51
--- /dev/null
+++ b/configs/bcm23550_w1d_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCM23550_W1D=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
new file mode 100644
index 0000000..bd3c711
--- /dev/null
+++ b/include/configs/bcm23550_w1d.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BCM23550_W1D_H
+#define __BCM23550_W1D_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* CPU, chip, mach, etc */
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_KONA_RESET_S
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x9f000000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
+#define CONFIG_STACKSIZE		SZ_256K
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_KONA_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM	3	/* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS	4
+#define CONFIG_SYS_I2C_BASE0	BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1	BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2	BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3	PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE		32000
+#define CONFIG_SYS_TIMER_COUNTER	(TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+#define CONFIG_MISC_INIT_R	/* board's misc_init_r function */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		0x3e000000
+
+#define CONFIG_BAUDRATE			115200
+
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(0x00011a00 * 512)
+#define CONFIG_ENV_SIZE			(8 * 512)
+
+#define CONFIG_SYS_NO_FLASH	/* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+			sizeof(CONFIG_SYS_PROMPT) + 16)	/* Printbuffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND		""
+
+/* Commands */
+#define CONFIG_FAT_WRITE
+
+/* Fastboot and USB OTG */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	0
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_FASTBOOT_BUF_SIZE	0x1d000000
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+#define CONFIG_USB_GADGET_DWC2_PHY_8_BIT
+#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
+#define CONFIG_USBID_ADDR		0x34052c46
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_L2CACHE_OFF
+
+#endif /* __BCM23550_W1D_H */
-- 
cgit v0.10.2


From 1f68dbc881d3169f2cd6093564b8e90e000cc034 Mon Sep 17 00:00:00 2001
From: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Date: Sun, 5 Jun 2016 03:42:59 +0300
Subject: serial: Introduce linflex uart support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The Linflex module is integrated on some NXP automotive SoCs part of the former
Freescale portfolio, like S32V234, an SoC for Advanced Driver Assistance
Systems.

Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Chircu Bogdan <Bogdan.Chircu@freescale.com>
Original-signed-off-by: Depons Eric <eric.depons@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>

Signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e1e28de..92cbea5 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
+obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c
new file mode 100644
index 0000000..fbb3959
--- /dev/null
+++ b/drivers/serial/serial_linflexuart.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define US1_TDRE            (1 << 7)
+#define US1_RDRF            (1 << 5)
+#define UC2_TE              (1 << 3)
+#define LINCR1_INIT         (1 << 0)
+#define LINCR1_MME          (1 << 4)
+#define LINCR1_BF           (1 << 7)
+#define LINSR_LINS_INITMODE (0x00001000)
+#define LINSR_LINS_MASK     (0x0000F000)
+#define UARTCR_UART         (1 << 0)
+#define UARTCR_WL0          (1 << 1)
+#define UARTCR_PCE          (1 << 2)
+#define UARTCR_PC0          (1 << 3)
+#define UARTCR_TXEN         (1 << 4)
+#define UARTCR_RXEN         (1 << 5)
+#define UARTCR_PC1          (1 << 6)
+#define UARTSR_DTF          (1 << 1)
+#define UARTSR_DRF          (1 << 2)
+#define UARTSR_RMB          (1 << 9)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_SERIAL
+#error "The linflex serial driver does not have non-DM support."
+#endif
+
+static void _linflex_serial_setbrg(struct linflex_fsl *base, int baudrate)
+{
+	u32 clk = mxc_get_clock(MXC_UART_CLK);
+	u32 ibr, fbr;
+
+	if (!baudrate)
+		baudrate = CONFIG_BAUDRATE;
+
+	ibr = (u32) (clk / (16 * gd->baudrate));
+	fbr = (u32) (clk % (16 * gd->baudrate)) * 16;
+
+	__raw_writel(ibr, &base->linibrr);
+	__raw_writel(fbr, &base->linfbrr);
+}
+
+static int _linflex_serial_getc(struct linflex_fsl *base)
+{
+	char c;
+
+	if (!(__raw_readb(&base->uartsr) & UARTSR_DRF))
+		return -EAGAIN;
+
+	if (!(__raw_readl(&base->uartsr) & UARTSR_RMB))
+		return -EAGAIN;
+
+	c = __raw_readl(&base->bdrm);
+	__raw_writeb((__raw_readb(&base->uartsr) | (UARTSR_DRF | UARTSR_RMB)),
+		     &base->uartsr);
+	return c;
+}
+
+static int _linflex_serial_putc(struct linflex_fsl *base, const char c)
+{
+	__raw_writeb(c, &base->bdrl);
+
+
+	if (!(__raw_readb(&base->uartsr) & UARTSR_DTF))
+		return -EAGAIN;
+
+	__raw_writeb((__raw_readb(&base->uartsr) | UARTSR_DTF), &base->uartsr);
+
+	return 0;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int _linflex_serial_init(struct linflex_fsl *base)
+{
+	volatile u32 ctrl;
+
+	/* set the Linflex in master mode amd activate by-pass filter */
+	ctrl = LINCR1_BF | LINCR1_MME;
+	__raw_writel(ctrl, &base->lincr1);
+
+	/* init mode */
+	ctrl |= LINCR1_INIT;
+	__raw_writel(ctrl, &base->lincr1);
+
+	/* waiting for init mode entry - TODO: add a timeout */
+	while ((__raw_readl(&base->linsr) & LINSR_LINS_MASK) !=
+	       LINSR_LINS_INITMODE);
+
+	/* set UART bit to allow writing other bits */
+	__raw_writel(UARTCR_UART, &base->uartcr);
+
+	/* provide data bits, parity, stop bit, etc */
+	serial_setbrg();
+
+	/* 8 bit data, no parity, Tx and Rx enabled, UART mode */
+	__raw_writel(UARTCR_PC1 | UARTCR_RXEN | UARTCR_TXEN | UARTCR_PC0
+		     | UARTCR_WL0 | UARTCR_UART, &base->uartcr);
+
+	ctrl = __raw_readl(&base->lincr1);
+	ctrl &= ~LINCR1_INIT;
+	__raw_writel(ctrl, &base->lincr1);	/* end init mode */
+
+	return 0;
+}
+
+struct linflex_serial_platdata {
+	struct linflex_fsl *base_addr;
+	u8 port_id; /* do we need this? */
+};
+
+struct linflex_serial_priv {
+	struct linflex_fsl *lfuart;
+};
+
+int linflex_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+	_linflex_serial_setbrg(priv->lfuart, baudrate);
+
+	return 0;
+}
+
+static int linflex_serial_getc(struct udevice *dev)
+{
+	struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+	return _linflex_serial_getc(priv->lfuart);
+}
+
+static int linflex_serial_putc(struct udevice *dev, const char ch)
+{
+
+	struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+	return _linflex_serial_putc(priv->lfuart, ch);
+}
+
+static int linflex_serial_pending(struct udevice *dev, bool input)
+{
+	struct linflex_serial_priv *priv = dev_get_priv(dev);
+	uint32_t uartsr = __raw_readl(&priv->lfuart->uartsr);
+
+	if (input)
+		return ((uartsr & UARTSR_DRF) && (uartsr & UARTSR_RMB)) ? 1 : 0;
+	else
+		return uartsr & UARTSR_DTF ? 0 : 1;
+}
+
+static void linflex_serial_init_internal(struct linflex_fsl *lfuart)
+{
+	_linflex_serial_init(lfuart);
+	_linflex_serial_setbrg(lfuart, CONFIG_BAUDRATE);
+	return;
+}
+
+static int linflex_serial_probe(struct udevice *dev)
+{
+	struct linflex_serial_platdata *plat = dev->platdata;
+	struct linflex_serial_priv *priv = dev_get_priv(dev);
+
+	priv->lfuart = (struct linflex_fsl *)plat->base_addr;
+	linflex_serial_init_internal(priv->lfuart);
+
+	return 0;
+}
+
+static const struct dm_serial_ops linflex_serial_ops = {
+	.putc = linflex_serial_putc,
+	.pending = linflex_serial_pending,
+	.getc = linflex_serial_getc,
+	.setbrg = linflex_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_linflex) = {
+	.name	= "serial_linflex",
+	.id	= UCLASS_SERIAL,
+	.probe = linflex_serial_probe,
+	.ops	= &linflex_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+	.priv_auto_alloc_size	= sizeof(struct linflex_serial_priv),
+};
+
+#ifdef CONFIG_DEBUG_UART_LINFLEXUART
+
+#include <debug_uart.h>
+
+
+static inline void _debug_uart_init(void)
+{
+	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+
+	linflex_serial_init_internal(base);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+
+	/* XXX: Is this OK? Should this use the non-DM version? */
+	_linflex_serial_putc(base, ch);
+}
+
+DEBUG_UART_FUNCS
+
+#endif /* CONFIG_DEBUG_UART_LINFLEXUART */
-- 
cgit v0.10.2


From 9702ec00e95dbc1fd66ef8e9624c649e1ee818e5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eddy=20Petri=C8=99or?= <eddy.petrisor@gmail.com>
Date: Sun, 5 Jun 2016 03:43:00 +0300
Subject: armv8: s32v234: Introduce basic support for s32v234evb
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add initial support for NXP's S32V234 SoC and S32V234EVB board.

The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.

Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>

Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f78fb0..80a3f93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,6 +561,10 @@ config RMOBILE
 	bool "Renesas ARM SoCs"
 	select CPU_V7
 
+config TARGET_S32V234EVB
+	bool "Support s32v234evb"
+	select ARM64
+
 config ARCH_SNAPDRAGON
 	bool "Qualcomm Snapdragon SoCs"
 	select ARM64
@@ -934,6 +938,7 @@ source "board/freescale/mx53ard/Kconfig"
 source "board/freescale/mx53evk/Kconfig"
 source "board/freescale/mx53loco/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
+source "board/freescale/s32v234evb/Kconfig"
 source "board/freescale/vf610twr/Kconfig"
 source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 1c85aa9..bf8644c 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -17,5 +17,6 @@ obj-y	+= transition.o
 obj-y	+= fwcall.o
 
 obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
+obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/s32v234/Makefile b/arch/arm/cpu/armv8/s32v234/Makefile
new file mode 100644
index 0000000..49774f6
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += generic.o
+obj-y += cpu.o
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
new file mode 100644
index 0000000..dac12a2
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/mc_me_regs.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 cpu_mask(void)
+{
+	return readl(MC_ME_CS);
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#define S32V234_IRAM_BASE        0x3e800000UL
+#define S32V234_IRAM_SIZE        0x800000UL
+#define S32V234_DRAM_BASE1       0x80000000UL
+#define S32V234_DRAM_SIZE1       0x40000000UL
+#define S32V234_DRAM_BASE2       0xC0000000UL
+#define S32V234_DRAM_SIZE2       0x20000000UL
+#define S32V234_PERIPH_BASE      0x40000000UL
+#define S32V234_PERIPH_SIZE      0x40000000UL
+
+static struct mm_region s32v234_mem_map[] = {
+	{
+		.base = S32V234_IRAM_BASE,
+		.size = S32V234_IRAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.base = S32V234_DRAM_BASE1,
+		.size = S32V234_DRAM_SIZE1,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.base = S32V234_PERIPH_BASE,
+		.size = S32V234_PERIPH_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE
+			 /* TODO: Do we need these? */
+			 /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
+	}, {
+		.base = S32V234_DRAM_BASE2,
+		.size = S32V234_DRAM_SIZE2,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = s32v234_mem_map;
+
+#endif
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+	int numcores;
+	u32 mask;
+
+	mask = cpu_mask();
+	numcores = hweight32(cpu_mask());
+
+	/* Verify if M4 is deactivated */
+	if (mask & 0x1)
+		numcores--;
+
+	return numcores;
+}
+
+#if defined(CONFIG_ARCH_EARLY_INIT_R)
+int arch_early_init_r(void)
+{
+	int rv;
+	asm volatile ("dsb sy");
+	rv = fsl_s32v234_wake_seconday_cores();
+
+	if (rv)
+		printf("Did not wake secondary cores\n");
+
+	asm volatile ("sev");
+	return 0;
+}
+#endif /* CONFIG_ARCH_EARLY_INIT_R */
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.h b/arch/arm/cpu/armv8/s32v234/cpu.h
new file mode 100644
index 0000000..402ac29
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/cpu.h
@@ -0,0 +1,8 @@
+/*
+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+u32 cpu_mask(void);
+int cpu_numcores(void);
diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c
new file mode 100644
index 0000000..7bb894e
--- /dev/null
+++ b/arch/arm/cpu/armv8/s32v234/generic.c
@@ -0,0 +1,350 @@
+/*
+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc_cgm_regs.h>
+#include <asm/arch/mc_me_regs.h>
+#include <asm/arch/mc_rgm_regs.h>
+#include <netdev.h>
+#include <div64.h>
+#include <errno.h>
+
+u32 get_cpu_rev(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
+	u32 cpu = readl(&mscmir->cpxtype);
+
+	return cpu;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
+			     u32 pllfd, u32 selected_output)
+{
+	u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
+	u32 plldv_rfdphi_div = 0, fout = 0;
+	u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
+
+	if (selected_output > DFS_MAXNUMBER) {
+		return -1;
+	}
+
+	plldv_prediv =
+	    (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
+	plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
+
+	pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
+
+	plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
+
+	/* The formula for VCO is from TR manual, rev. D */
+	vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
+
+	if (selected_output != 0) {
+		/* Determine the RFDPHI for PHI1 */
+		plldv_rfdphi_div =
+		    (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
+		    PLLDIG_PLLDV_RFDPHI1_OFFSET;
+		plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
+		if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
+			dfs_portn =
+			    readl(DFS_DVPORTn(pll, selected_output - 1));
+			dfs_mfi =
+			    (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
+			    DFS_DVPORTn_MFI_OFFSET;
+			dfs_mfn =
+			    (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
+			    DFS_DVPORTn_MFI_OFFSET;
+			fout = vco / (dfs_mfi + (dfs_mfn / 256));
+		} else {
+			fout = vco / plldv_rfdphi_div;
+		}
+
+	} else {
+		/* Determine the RFDPHI for PHI0 */
+		plldv_rfdphi_div =
+		    (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
+		    PLLDIG_PLLDV_RFDPHI_OFFSET;
+		fout = vco / plldv_rfdphi_div;
+	}
+
+	return fout;
+
+}
+
+/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
+static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
+			    u32 selected_output)
+{
+	u32 plldv, pllfd;
+
+	plldv = readl(PLLDIG_PLLDV(pll));
+	pllfd = readl(PLLDIG_PLLFD(pll));
+
+	return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 coreclk_div;
+	u32 sysclk_sel;
+	u32 freq = 0;
+
+	sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
+	sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
+
+	coreclk_div =
+	    readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
+	coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
+	coreclk_div += 1;
+
+	switch (sysclk_sel) {
+	case MC_CGM_SC_SEL_FIRC:
+		freq = FIRC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_XOSC:
+		freq = XOSC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_ARMPLL:
+		/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
+		freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
+		break;
+	case MC_CGM_SC_SEL_CLKDISABLE:
+		printf("Sysclk is disabled\n");
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / coreclk_div;
+}
+
+static u32 get_sys_clk(u32 number)
+{
+	u32 sysclk_div, sysclk_div_number;
+	u32 sysclk_sel;
+	u32 freq = 0;
+
+	switch (number) {
+	case 3:
+		sysclk_div_number = 0;
+		break;
+	case 6:
+		sysclk_div_number = 1;
+		break;
+	default:
+		printf("unsupported system clock \n");
+		return -1;
+	}
+	sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
+	sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
+
+	sysclk_div =
+	    readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
+	    MC_CGM_SC_DCn_PREDIV_MASK;
+	sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
+	sysclk_div += 1;
+
+	switch (sysclk_sel) {
+	case MC_CGM_SC_SEL_FIRC:
+		freq = FIRC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_XOSC:
+		freq = XOSC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_ARMPLL:
+		/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
+		freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
+		break;
+	case MC_CGM_SC_SEL_CLKDISABLE:
+		printf("Sysclk is disabled\n");
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / sysclk_div;
+}
+
+static u32 get_peripherals_clk(void)
+{
+	u32 aux5clk_div;
+	u32 freq = 0;
+
+	aux5clk_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	aux5clk_div += 1;
+
+	freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
+
+	return freq / aux5clk_div;
+
+}
+
+static u32 get_uart_clk(void)
+{
+	u32 auxclk3_div, auxclk3_sel, freq = 0;
+
+	auxclk3_sel =
+	    readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
+	auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
+
+	auxclk3_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	auxclk3_div += 1;
+
+	switch (auxclk3_sel) {
+	case MC_CGM_ACn_SEL_FIRC:
+		freq = FIRC_CLK_FREQ;
+		break;
+	case MC_CGM_ACn_SEL_XOSC:
+		freq = XOSC_CLK_FREQ;
+		break;
+	case MC_CGM_ACn_SEL_PERPLLDIVX:
+		freq = get_peripherals_clk() / 3;
+		break;
+	case MC_CGM_ACn_SEL_SYSCLK:
+		freq = get_sys_clk(6);
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / auxclk3_div;
+}
+
+static u32 get_fec_clk(void)
+{
+	u32 aux2clk_div;
+	u32 freq = 0;
+
+	aux2clk_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	aux2clk_div += 1;
+
+	freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
+
+	return freq / aux2clk_div;
+}
+
+static u32 get_usdhc_clk(void)
+{
+	u32 aux15clk_div;
+	u32 freq = 0;
+
+	aux15clk_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	aux15clk_div += 1;
+
+	freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
+
+	return freq / aux15clk_div;
+}
+
+static u32 get_i2c_clk(void)
+{
+	return get_peripherals_clk();
+}
+
+/* return clocks in Hz */
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_PERIPHERALS_CLK:
+		return get_peripherals_clk();
+	case MXC_UART_CLK:
+		return get_uart_clk();
+	case MXC_FEC_CLK:
+		return get_fec_clk();
+	case MXC_I2C_CLK:
+		return get_i2c_clk();
+	case MXC_USDHC_CLK:
+		return get_usdhc_clk();
+	default:
+		break;
+	}
+	printf("Error: Unsupported function to read the frequency! \
+			Please define it correctly!");
+	return -1;
+}
+
+/* Not yet implemented - int soc_clk_dump(); */
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
+
+	switch (cause) {
+	case F_SWT4:
+		return "WDOG";
+	case F_JTAG:
+		return "JTAG";
+	case F_FCCU_SOFT:
+		return "FCCU soft reaction";
+	case F_FCCU_HARD:
+		return "FCCU hard reaction";
+	case F_SOFT_FUNC:
+		return "Software Functional reset";
+	case F_ST_DONE:
+		return "Self Test done reset";
+	case F_EXT_RST:
+		return "External reset";
+	default:
+		return "unknown reset";
+	}
+
+}
+
+#define SRC_SCR_SW_RST					(1<<12)
+
+void reset_cpu(ulong addr)
+{
+	printf("Feature not supported.\n");
+};
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   Freescale Treerunner S32V234 at %d MHz\n",
+	       mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+
+	return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t * bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
+#endif
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h
new file mode 100644
index 0000000..df92fb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/clock.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_PERIPHERALS_CLK,
+	MXC_UART_CLK,
+	MXC_USDHC_CLK,
+	MXC_FEC_CLK,
+	MXC_I2C_CLK,
+};
+enum pll_type {
+	ARM_PLL = 0,
+	PERIPH_PLL,
+	ENET_PLL,
+	DDR_PLL,
+	VIDEO_PLL,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void clock_init(void);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h
new file mode 100644
index 0000000..10a9a79
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/ddr.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
+#define __ARCH_ARM_MACH_S32V234_DDR_H__
+
+#define DDR0	0
+#define DDR1	1
+
+/* DDR offset in MSCR register */
+#define _DDR0_RESET	168
+#define _DDR0_CLK0	169
+#define _DDR0_CAS	170
+#define _DDR0_RAS	171
+#define _DDR0_WE_B	172
+#define _DDR0_CKE0	173
+#define _DDR0_CKE1	174
+#define _DDR0_CS_B0	175
+#define _DDR0_CS_B1	176
+#define _DDR0_BA0	177
+#define _DDR0_BA1	178
+#define _DDR0_BA2	179
+#define _DDR0_A0	180
+#define _DDR0_A1	181
+#define _DDR0_A2	182
+#define _DDR0_A3	183
+#define _DDR0_A4	184
+#define _DDR0_A5	185
+#define _DDR0_A6	186
+#define _DDR0_A7	187
+#define _DDR0_A8	188
+#define _DDR0_A9	189
+#define _DDR0_A10	190
+#define _DDR0_A11	191
+#define _DDR0_A12	192
+#define _DDR0_A13	193
+#define _DDR0_A14	194
+#define _DDR0_A15	195
+#define _DDR0_DM0	196
+#define _DDR0_DM1	197
+#define _DDR0_DM2	198
+#define _DDR0_DM3	199
+#define _DDR0_DQS0	200
+#define _DDR0_DQS1	201
+#define _DDR0_DQS2	202
+#define _DDR0_DQS3	203
+#define _DDR0_D0	204
+#define _DDR0_D1	205
+#define _DDR0_D2	206
+#define _DDR0_D3	207
+#define _DDR0_D4	208
+#define _DDR0_D5	209
+#define _DDR0_D6	210
+#define _DDR0_D7	211
+#define _DDR0_D8	212
+#define _DDR0_D9	213
+#define _DDR0_D10	214
+#define _DDR0_D11	215
+#define _DDR0_D12	216
+#define _DDR0_D13	217
+#define _DDR0_D14	218
+#define _DDR0_D15	219
+#define _DDR0_D16	220
+#define _DDR0_D17	221
+#define _DDR0_D18	222
+#define _DDR0_D19	223
+#define _DDR0_D20	224
+#define _DDR0_D21	225
+#define _DDR0_D22	226
+#define _DDR0_D23	227
+#define _DDR0_D24	228
+#define _DDR0_D25	229
+#define _DDR0_D26	230
+#define _DDR0_D27	231
+#define _DDR0_D28	232
+#define _DDR0_D29	233
+#define _DDR0_D30	234
+#define _DDR0_D31	235
+#define _DDR0_ODT0	236
+#define _DDR0_ODT1	237
+#define _DDR0_ZQ	238
+#define _DDR1_RESET	239
+#define _DDR1_CLK0	240
+#define _DDR1_CAS	241
+#define _DDR1_RAS	242
+#define _DDR1_WE_B	243
+#define _DDR1_CKE0	244
+#define _DDR1_CKE1	245
+#define _DDR1_CS_B0	246
+#define _DDR1_CS_B1	247
+#define _DDR1_BA0	248
+#define _DDR1_BA1	249
+#define _DDR1_BA2	250
+#define _DDR1_A0	251
+#define _DDR1_A1	252
+#define _DDR1_A2	253
+#define _DDR1_A3	254
+#define _DDR1_A4	255
+#define _DDR1_A5	256
+#define _DDR1_A6	257
+#define _DDR1_A7	258
+#define _DDR1_A8	259
+#define _DDR1_A9	260
+#define _DDR1_A10	261
+#define _DDR1_A11	262
+#define _DDR1_A12	263
+#define _DDR1_A13	264
+#define _DDR1_A14	265
+#define _DDR1_A15	266
+#define _DDR1_DM0	267
+#define _DDR1_DM1	268
+#define _DDR1_DM2	269
+#define _DDR1_DM3	270
+#define _DDR1_DQS0	271
+#define _DDR1_DQS1	272
+#define _DDR1_DQS2	273
+#define _DDR1_DQS3	274
+#define _DDR1_D0	275
+#define _DDR1_D1	276
+#define _DDR1_D2	277
+#define _DDR1_D3	278
+#define _DDR1_D4	279
+#define _DDR1_D5	280
+#define _DDR1_D6	281
+#define _DDR1_D7	282
+#define _DDR1_D8	283
+#define _DDR1_D9	284
+#define _DDR1_D10	285
+#define _DDR1_D11	286
+#define _DDR1_D12	287
+#define _DDR1_D13	288
+#define _DDR1_D14	289
+#define _DDR1_D15	290
+#define _DDR1_D16	291
+#define _DDR1_D17	292
+#define _DDR1_D18	293
+#define _DDR1_D19	294
+#define _DDR1_D20	295
+#define _DDR1_D21	296
+#define _DDR1_D22	297
+#define _DDR1_D23	298
+#define _DDR1_D24	299
+#define _DDR1_D25	300
+#define _DDR1_D26	301
+#define _DDR1_D27	302
+#define _DDR1_D28	303
+#define _DDR1_D29	304
+#define _DDR1_D30	305
+#define _DDR1_D31	306
+#define _DDR1_ODT0	307
+#define _DDR1_ODT1	308
+#define _DDR1_ZQ	309
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h
new file mode 100644
index 0000000..a42f6cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/imx-regs.h
@@ -0,0 +1,329 @@
+/*
+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR      0x3E800000	/* internal ram */
+#define IRAM_SIZE           0x00400000	/* 4MB */
+
+#define AIPS0_BASE_ADDR     (0x40000000UL)
+#define AIPS1_BASE_ADDR     (0x40080000UL)
+
+/* AIPS 0 */
+#define AXBS_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00000000)
+#define CSE3_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00001000)
+#define EDMA_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00002000)
+#define XRDC_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00004000)
+#define SWT0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000A000)
+#define SWT1_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000B000)
+#define STM0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC301_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00010000)
+#define GC3000_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00020000)
+#define DEC200_DECODER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00026000)
+#define DEC200_ENCODER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00027000)
+#define TWOD_ACE_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00028000)
+#define MIPI_CSI0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00030000)
+#define DMAMUX0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00031000)
+#define ENET_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00032000)
+#define FLEXRAY_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00034000)
+#define MMDC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00036000)
+#define MEW0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00037000)
+#define MONITOR_DDR0_BASE_ADDR			(AIPS0_BASE_ADDR + 0x00038000)
+#define MONITOR_CCI0_BASE_ADDR			(AIPS0_BASE_ADDR + 0x00039000)
+#define PIT0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0003A000)
+#define MC_CGM0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0003C000)
+#define MC_CGM1_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0003F000)
+#define MC_CGM2_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00042000)
+#define MC_CGM3_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00045000)
+#define MC_RGM_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00048000)
+#define MC_ME_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0004A000)
+#define MC_PCU_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0004B000)
+#define ADC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0004D000)
+#define FLEXTIMER_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0004F000)
+#define I2C0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00051000)
+#define LINFLEXD0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00053000)
+#define FLEXCAN0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00055000)
+#define SPI0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00057000)
+#define SPI2_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00059000)
+#define CRC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0005B000)
+#define USDHC_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0005D000)
+#define OCOTP_CONTROLLER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0005F000)
+#define WKPU_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00063000)
+#define VIU0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00064000)
+#define HPSMI_SRAM_CONTROLLER_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00068000)
+#define SIUL2_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0006C000)
+#define SIPI_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00074000)
+#define LFAST_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00078000)
+#define SSE_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00079000)
+#define SRC_SOC_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0007C000)
+
+/* AIPS 1 */
+#define ERM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000000000)
+#define MSCM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000001000)
+#define SEMA42_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000002000)
+#define INTC_MON_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000003000)
+#define SWT2_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000004000)
+#define SWT3_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000005000)
+#define SWT4_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000006000)
+#define STM1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000007000)
+#define EIM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000008000)
+#define APB_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000009000)
+#define XBIC_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000012000)
+#define MIPI_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000020000)
+#define DMAMUX1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000021000)
+#define MMDC1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000022000)
+#define MEW1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000023000)
+#define DDR1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000024000)
+#define CCI1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000025000)
+#define QUADSPI0_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000026000)
+#define PIT1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00002A000)
+#define FCCU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000030000)
+#define FLEXTIMER_FTM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0X000036000)
+#define I2C1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000038000)
+#define I2C2_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00003A000)
+#define LINFLEXD1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00003C000)
+#define FLEXCAN1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00003E000)
+#define SPI1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000040000)
+#define SPI3_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000042000)
+#define IPL_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000043000)
+#define CGM_CMU_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000044000)
+#define PMC_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000048000)
+#define CRC1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00004C000)
+#define TMU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00004E000)
+#define VIU1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000050000)
+#define JPEG_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000054000)
+#define H264_DEC_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000058000)
+#define H264_ENC_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00005C000)
+#define MEMU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000060000)
+#define STCU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000064000)
+#define SLFTST_CTRL_BASE_ADDR			(AIPS1_BASE_ADDR + 0X000066000)
+#define MCT_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000068000)
+#define REP_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00006A000)
+#define MBIST_CONTROLLER_BASE_ADDR		(AIPS1_BASE_ADDR + 0X00006C000)
+#define BOOT_LOADER_BASE_ADDR			(AIPS1_BASE_ADDR + 0X00006F000)
+
+/* TODO Remove this after the IOMUX framework is implemented */
+#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
+
+/* MSCM interrupt router */
+#define MSCM_IRSPRC_CPn_EN		3
+#define MSCM_IRSPRC_NUM			176
+#define MSCM_CPXTYPE_RYPZ_MASK		0xFF
+#define MSCM_CPXTYPE_RYPZ_OFFSET	0
+#define MSCM_CPXTYPE_PERS_MASK		0xFFFFFF00
+#define MSCM_CPXTYPE_PERS_OFFSET	8
+#define MSCM_CPXTYPE_PERS_A53		0x413533
+#define MSCM_CPXTYPE_PERS_CM4		0x434d34
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 bmr1;
+	u32 bmr2;
+	u32 gpr1_boot;
+	u32 reserved_0x00C[61];
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 gpr5;
+	u32 gpr6;
+	u32 gpr7;
+	u32 reserved_0x11C[1];
+	u32 gpr9;
+	u32 gpr10;
+	u32 gpr11;
+	u32 gpr12;
+	u32 gpr13;
+	u32 gpr14;
+	u32 gpr15;
+	u32 gpr16;
+	u32 reserved_0x140[1];
+	u32 gpr17;
+	u32 gpr18;
+	u32 gpr19;
+	u32 gpr20;
+	u32 gpr21;
+	u32 gpr22;
+	u32 gpr23;
+	u32 gpr24;
+	u32 gpr25;
+	u32 gpr26;
+	u32 gpr27;
+	u32 reserved_0x16C[5];
+	u32 pcie_config1;
+	u32 ddr_self_ref_ctrl;
+	u32 pcie_config0;
+	u32 reserved_0x18C[4];
+	u32 soc_misc_config2;
+};
+
+/* SRC registers definitions */
+
+/* SRC_GPR1 */
+#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
+										(SRC_GPR1_PLL_OFFSET + (pll)) )
+#define SRC_GPR1_PLL_SOURCE_MASK	(0x1)
+
+#define SRC_GPR1_PLL_OFFSET			(27)
+#define SRC_GPR1_FIRC_CLK_SOURCE	(0x0)
+#define SRC_GPR1_XOSC_CLK_SOURCE	(0x1)
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+	u32 mcr;
+	u32 recv0[55];
+	u32 ltmr64h;
+	u32 ltmr64l;
+	u32 recv1[6];
+	u32 ldval0;
+	u32 cval0;
+	u32 tctrl0;
+	u32 tflg0;
+	u32 ldval1;
+	u32 cval1;
+	u32 tctrl1;
+	u32 tflg1;
+	u32 ldval2;
+	u32 cval2;
+	u32 tctrl2;
+	u32 tflg2;
+	u32 ldval3;
+	u32 cval3;
+	u32 tctrl3;
+	u32 tflg3;
+	u32 ldval4;
+	u32 cval4;
+	u32 tctrl4;
+	u32 tflg4;
+	u32 ldval5;
+	u32 cval5;
+	u32 tctrl5;
+	u32 tflg5;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+	u32 cr;
+	u32 ir;
+	u32 to;
+	u32 wn;
+	u32 sr;
+	u32 co;
+	u32 sk;
+};
+
+/* UART */
+struct linflex_fsl {
+	u32 lincr1;
+	u32 linier;
+	u32 linsr;
+	u32 linesr;
+	u32 uartcr;
+	u32 uartsr;
+	u32 lintcsr;
+	u32 linocr;
+	u32 lintocr;
+	u32 linfbrr;
+	u32 linibrr;
+	u32 lincfr;
+	u32 lincr2;
+	u32 bidr;
+	u32 bdrl;
+	u32 bdrm;
+	u32 ifer;
+	u32 ifmi;
+	u32 ifmr;
+	u32 ifcr0;
+	u32 ifcr1;
+	u32 ifcr2;
+	u32 ifcr3;
+	u32 ifcr4;
+	u32 ifcr5;
+	u32 ifcr6;
+	u32 ifcr7;
+	u32 ifcr8;
+	u32 ifcr9;
+	u32 ifcr10;
+	u32 ifcr11;
+	u32 ifcr12;
+	u32 ifcr13;
+	u32 ifcr14;
+	u32 ifcr15;
+	u32 gcr;
+	u32 uartpto;
+	u32 uartcto;
+	u32 dmatxe;
+	u32 dmarxe;
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+	u32 cpxtype;		/* Processor x Type Register                    */
+	u32 cpxnum;		/* Processor x Number Register                  */
+	u32 cpxmaster;		/* Processor x Master Number Register   */
+	u32 cpxcount;		/* Processor x Count Register                   */
+	u32 cpxcfg0;		/* Processor x Configuration 0 Register */
+	u32 cpxcfg1;		/* Processor x Configuration 1 Register */
+	u32 cpxcfg2;		/* Processor x Configuration 2 Register */
+	u32 cpxcfg3;		/* Processor x Configuration 3 Register */
+	u32 cp0type;		/* Processor 0 Type Register                    */
+	u32 cp0num;		/* Processor 0 Number Register                  */
+	u32 cp0master;		/* Processor 0 Master Number Register   */
+	u32 cp0count;		/* Processor 0 Count Register                   */
+	u32 cp0cfg0;		/* Processor 0 Configuration 0 Register */
+	u32 cp0cfg1;		/* Processor 0 Configuration 1 Register */
+	u32 cp0cfg2;		/* Processor 0 Configuration 2 Register */
+	u32 cp0cfg3;		/* Processor 0 Configuration 3 Register */
+	u32 cp1type;		/* Processor 1 Type Register                    */
+	u32 cp1num;		/* Processor 1 Number Register                  */
+	u32 cp1master;		/* Processor 1 Master Number Register   */
+	u32 cp1count;		/* Processor 1 Count Register                   */
+	u32 cp1cfg0;		/* Processor 1 Configuration 0 Register */
+	u32 cp1cfg1;		/* Processor 1 Configuration 1 Register */
+	u32 cp1cfg2;		/* Processor 1 Configuration 2 Register */
+	u32 cp1cfg3;		/* Processor 1 Configuration 3 Register */
+	u32 reserved_0x060[232];
+	u32 ocmdr0;		/* On-Chip Memory Descriptor Register   */
+	u32 reserved_0x404[2];
+	u32 ocmdr3;		/* On-Chip Memory Descriptor Register   */
+	u32 reserved_0x410[28];
+	u32 tcmdr[4];		/* Generic Tightly Coupled Memory Descriptor Register   */
+	u32 reserved_0x490[28];
+	u32 cpce0;		/* Core Parity Checking Enable Register 0                               */
+	u32 reserved_0x504[191];
+	u32 ircp0ir;		/* Interrupt Router CP0 Interrupt Register                              */
+	u32 ircp1ir;		/* Interrupt Router CP1 Interrupt Register                              */
+	u32 reserved_0x808[6];
+	u32 ircpgir;		/* Interrupt Router CPU Generate Interrupt Register             */
+	u32 reserved_0x824[23];
+	u16 irsprc[176];	/* Interrupt Router Shared Peripheral Routing Control Register  */
+	u32 reserved_0x9e0[136];
+	u32 iahbbe0;		/* Gasket Burst Enable Register                                                 */
+	u32 reserved_0xc04[63];
+	u32 ipcge;		/* Interconnect Parity Checking Global Enable Register  */
+	u32 reserved_0xd04[3];
+	u32 ipce[4];		/* Interconnect Parity Checking Enable Register                 */
+	u32 reserved_0xd20[8];
+	u32 ipcgie;		/* Interconnect Parity Checking Global Injection Enable Register        */
+	u32 reserved_0xd44[3];
+	u32 ipcie[4];		/* Interconnect Parity Checking Injection Enable Register       */
+};
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h
new file mode 100644
index 0000000..5a05965
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/lpddr2.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
+#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
+
+/* definitions for LPDDR2 PAD values */
+#define LPDDR2_CLK0_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 |			\
+	 SIUL2_MSCR_DCYCLE_TRIM_NONE)
+#define LPDDR2_CKEn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_CS_Bn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_DMn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_DQSn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN |						\
+	 SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
+#define LPDDR2_An_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT		|	\
+	 SIUL2_MSCR_PUS_100K_UP)
+#define LPDDR2_Dn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT		|	\
+	 SIUL2_MSCR_PUS_100K_UP)
+
+#define _MDCTL							0x03010000
+
+#define MMDC_MDSCR_CFG_VALUE			0x00008000	/* Set MDSCR[CON_REQ] (configuration request) */
+#define MMDC_MDCFG0_VALUE				0x464F61A5	/* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
+#define MMDC_MDCFG1_VALUE				0x00180E63	/* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
+#define MMDC_MDCFG2_VALUE				0x000000DD	/* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
+#define MMDC_MDCFG3LP_VALUE				0x001F099B	/* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
+#define MMDC_MDOTC_VALUE				0x00000000	/* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
+#define MMDC_MDMISC_VALUE				0x00001688	/* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
+#define MMDC_MDOR_VALUE					0x00000010	/* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
+#define MMDC_MPMUR0_VALUE				0x00000800	/* Force delay line initialisation */
+#define MMDC_MDSCR_RST_VALUE			0x003F8030	/* Reset command CS0 */
+#define MMDC_MPZQLP2CTL_VALUE			0x1B5F0109	/* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
+#define MMDC_MPZQHWCTRL_VALUE			0xA0010003	/* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
+#define MMDC_MDSCR_MR1_VALUE			0xC2018030	/* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
+#define MMDC_MDSCR_MR2_VALUE			0x06028030	/* Configure MR2: RL=8, WL=4 */
+#define MMDC_MDSCR_MR3_VALUE			0x01038030	/* Configure MR3: DS=34R */
+#define MMDC_MDSCR_MR10_VALUE			0xFF0A8030	/* Configure MR10: Calibration at init */
+#define MMDC_MDASP_MODULE0_VALUE		0x0000007F	/* 2Gb, 256 MB memory so CS0 is 256 MB  (0x90000000) */
+#define MMDC_MPRDDLCTL_MODULE0_VALUE	0x4D4B4F4B	/* Read delay line offsets */
+#define MMDC_MPWRDLCTL_MODULE0_VALUE	0x38383737	/* Write delay line offsets */
+#define MMDC_MPDGCTRL0_MODULE0_VALUE	0x20000000	/* Read DQS gating control 0 (disabled) */
+#define MMDC_MPDGCTRL1_MODULE0_VALUE	0x00000000	/* Read DQS gating control 1 */
+#define MMDC_MDASP_MODULE1_VALUE		0x0000007F	/* 2Gb, 256 MB memory so CS0 is 256 MB  (0xD0000000) */
+#define MMDC_MPRDDLCTL_MODULE1_VALUE	0x4D4B4F4B	/* Read delay line offsets */
+#define MMDC_MPWRDLCTL_MODULE1_VALUE	0x38383737	/* Write delay line offsets */
+#define MMDC_MPDGCTRL0_MODULE1_VALUE	0x20000000	/* Read DQS gating control 0 (disabled) */
+#define MMDC_MPDGCTRL1_MODULE1_VALUE	0x00000000	/* Read DQS gating control 1 */
+#define MMDC_MDRWD_VALUE				0x0F9F26D2	/* Read/write command delay - default used */
+#define MMDC_MDPDC_VALUE				0x00020024	/* Power down control */
+#define MMDC_MDREF_VALUE				0x30B01800	/* Refresh control */
+#define MMDC_MPODTCTRL_VALUE			0x00000000	/* No ODT */
+#define MMDC_MDSCR_DEASSERT_VALUE				0x00000000	/* Deassert the configuration request */
+
+/* set I/O pads for DDR */
+void lpddr2_config_iomux(uint8_t module);
+void config_mmdc(uint8_t module);
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
new file mode 100644
index 0000000..eb50475
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* MC_CGM registers definitions */
+/* MC_CGM_SC_SS */
+#define CGM_SC_SS(cgm_addr)			( ((cgm_addr) + 0x000007E4) )
+#define MC_CGM_SC_SEL_FIRC			(0x0)
+#define MC_CGM_SC_SEL_XOSC			(0x1)
+#define MC_CGM_SC_SEL_ARMPLL		(0x2)
+#define MC_CGM_SC_SEL_CLKDISABLE	(0xF)
+
+/* MC_CGM_SC_DCn */
+#define CGM_SC_DCn(cgm_addr,dc)		( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
+#define MC_CGM_SC_DCn_PREDIV(val)	(MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
+#define MC_CGM_SC_DCn_PREDIV_MASK	(0x00070000)
+#define MC_CGM_SC_DCn_PREDIV_OFFSET	(16)
+#define MC_CGM_SC_DCn_DE			(1 << 31)
+#define MC_CGM_SC_SEL_MASK			(0x0F000000)
+#define MC_CGM_SC_SEL_OFFSET		(24)
+
+/* MC_CGM_ACn_DCm */
+#define CGM_ACn_DCm(cgm_addr,ac,dc)		( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
+#define MC_CGM_ACn_DCm_PREDIV(val)		(MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
+
+/*
+ * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
+ * that the 5th bit is always ignored during writes if the current
+ * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
+ *
+ * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
+ *
+ * This should be changed if any problems occur.
+ */
+#define MC_CGM_ACn_DCm_PREDIV_MASK		(0x001F0000)
+#define MC_CGM_ACn_DCm_PREDIV_OFFSET	(16)
+#define MC_CGM_ACn_DCm_DE				(1 << 31)
+
+/*
+ * MC_CGM_ACn_SC/MC_CGM_ACn_SS
+ */
+#define CGM_ACn_SC(cgm_addr,ac)			((cgm_addr + 0x00000800) + ((ac) * 0x20))
+#define CGM_ACn_SS(cgm_addr,ac)			((cgm_addr + 0x00000804) + ((ac) * 0x20))
+#define MC_CGM_ACn_SEL_MASK				(0x07000000)
+#define MC_CGM_ACn_SEL_SET(source)		(MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
+#define MC_CGM_ACn_SEL_OFFSET			(24)
+
+#define MC_CGM_ACn_SEL_FIRC				(0x0)
+#define MC_CGM_ACn_SEL_XOSC				(0x1)
+#define MC_CGM_ACn_SEL_ARMPLL			(0x2)
+/*
+ * According to the manual some PLL can be divided by X (X={1,3,5}):
+ * PERPLLDIVX, VIDEOPLLDIVX.
+ */
+#define MC_CGM_ACn_SEL_PERPLLDIVX		(0x3)
+#define MC_CGM_ACn_SEL_ENETPLL			(0x4)
+#define MC_CGM_ACn_SEL_DDRPLL			(0x5)
+#define MC_CGM_ACn_SEL_EXTSRCPAD		(0x7)
+#define MC_CGM_ACn_SEL_SYSCLK			(0x8)
+#define MC_CGM_ACn_SEL_VIDEOPLLDIVX		(0x9)
+#define MC_CGM_ACn_SEL_PERCLK			(0xA)
+
+/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
+#define PLLDIG_PLLDV(pll)				((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
+#define PLLDIG_PLLDV_MFD(div)			(PLLDIG_PLLDV_MFD_MASK & (div))
+#define PLLDIG_PLLDV_MFD_MASK			(0x000000FF)
+
+/*
+ * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
+ * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
+ */
+#define PLLDIG_PLLDV_RFDPHI_SET(val)	(PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
+#define PLLDIG_PLLDV_RFDPHI_MASK		(0x003F0000)
+#define PLLDIG_PLLDV_RFDPHI_MAXVALUE	(0x3F)
+#define PLLDIG_PLLDV_RFDPHI_OFFSET		(16)
+
+#define PLLDIG_PLLDV_RFDPHI1_SET(val)	(PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
+#define PLLDIG_PLLDV_RFDPHI1_MASK		(0x7E000000)
+#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE	(0x3F)
+#define PLLDIG_PLLDV_RFDPHI1_OFFSET		(25)
+
+#define PLLDIG_PLLDV_PREDIV_SET(val)	(PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
+#define PLLDIG_PLLDV_PREDIV_MASK		(0x00007000)
+#define PLLDIG_PLLDV_PREDIV_MAXVALUE	(0x7)
+#define PLLDIG_PLLDV_PREDIV_OFFSET		(12)
+
+/* PLLDIG PLL Fractional  Divide Register (PLLDIG_PLLFD) */
+#define PLLDIG_PLLFD(pll)				((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
+#define PLLDIG_PLLFD_MFN_SET(val)		(PLLDIG_PLLFD_MFN_MASK & (val))
+#define PLLDIG_PLLFD_MFN_MASK			(0x00007FFF)
+#define PLLDIG_PLLFD_SMDEN				(1 << 30)
+
+/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
+#define PLLDIG_PLLCAL1(pll)				((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
+#define PLLDIG_PLLCAL1_NDAC1_SET(val)	(PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
+#define PLLDIG_PLLCAL1_NDAC1_OFFSET		(24)
+#define PLLDIG_PLLCAL1_NDAC1_MASK		(0x7F000000)
+
+/* Digital Frequency Synthesizer (DFS) */
+/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
+#define DFS0_BASE_ADDR				(MC_CGM0_BASE_ADDR + 0x00000040)
+
+/* DFS DLL Program Register 1 */
+#define DFS_DLLPRG1(pll)			(DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
+
+#define DFS_DLLPRG1_V2IGC_SET(val)	(DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
+#define DFS_DLLPRG1_V2IGC_OFFSET	(0)
+#define DFS_DLLPRG1_V2IGC_MASK		(0x00000007)
+
+#define DFS_DLLPRG1_LCKWT_SET(val)		(DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
+#define DFS_DLLPRG1_LCKWT_OFFSET		(4)
+#define DFS_DLLPRG1_LCKWT_MASK			(0x00000030)
+
+#define DFS_DLLPRG1_DACIN_SET(val)		(DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
+#define DFS_DLLPRG1_DACIN_OFFSET		(6)
+#define DFS_DLLPRG1_DACIN_MASK			(0x000001C0)
+
+#define DFS_DLLPRG1_CALBYPEN_SET(val)	(DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
+#define DFS_DLLPRG1_CALBYPEN_OFFSET		(9)
+#define DFS_DLLPRG1_CALBYPEN_MASK		(0x00000200)
+
+#define DFS_DLLPRG1_VSETTLCTRL_SET(val)	(DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
+#define DFS_DLLPRG1_VSETTLCTRL_OFFSET	(10)
+#define DFS_DLLPRG1_VSETTLCTRL_MASK		(0x00000C00)
+
+#define DFS_DLLPRG1_CPICTRL_SET(val)	(DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
+#define DFS_DLLPRG1_CPICTRL_OFFSET		(12)
+#define DFS_DLLPRG1_CPICTRL_MASK		(0x00007000)
+
+/* DFS Control Register (DFS_CTRL) */
+#define DFS_CTRL(pll)					(DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
+#define DFS_CTRL_DLL_LOLIE				(1 << 0)
+#define DFS_CTRL_DLL_RESET				(1 << 1)
+
+/* DFS Port Status Register (DFS_PORTSR) */
+#define DFS_PORTSR(pll)						(DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
+/* DFS Port Reset Register (DFS_PORTRESET) */
+#define DFS_PORTRESET(pll)					(DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
+#define DFS_PORTRESET_PORTRESET_SET(val)	(DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
+#define DFS_PORTRESET_PORTRESET_MAXVAL		(0xF)
+#define DFS_PORTRESET_PORTRESET_MASK		(0x0000000F)
+#define DFS_PORTRESET_PORTRESET_OFFSET		(0)
+
+/* DFS Divide Register Portn (DFS_DVPORTn) */
+#define DFS_DVPORTn(pll,n)			(DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
+
+/*
+ * The mathematical formula for fdfs_clockout is the following:
+ * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
+ */
+#define DFS_DVPORTn_MFI_SET(val)	(DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
+#define DFS_DVPORTn_MFN_SET(val)	(DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
+#define DFS_DVPORTn_MFI_MASK		(0x0000FF00)
+#define DFS_DVPORTn_MFN_MASK		(0x000000FF)
+#define DFS_DVPORTn_MFI_MAXVAL		(0xFF)
+#define DFS_DVPORTn_MFN_MAXVAL		(0xFF)
+#define DFS_DVPORTn_MFI_OFFSET		(8)
+#define DFS_DVPORTn_MFN_OFFSET		(0)
+#define DFS_MAXNUMBER				(4)
+
+#define DFS_PARAMS_Nr				(3)
+
+/* Frequencies are in Hz */
+#define FIRC_CLK_FREQ				(48000000)
+#define XOSC_CLK_FREQ				(40000000)
+
+#define PLL_MIN_FREQ				(650000000)
+#define PLL_MAX_FREQ				(1300000000)
+
+#define ARM_PLL_PHI0_FREQ			(1000000000)
+#define ARM_PLL_PHI1_FREQ			(1000000000)
+/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
+#define ARM_PLL_PHI1_DFS1_EN		(1)
+#define ARM_PLL_PHI1_DFS1_MFI		(3)
+#define ARM_PLL_PHI1_DFS1_MFN		(194)
+/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
+#define ARM_PLL_PHI1_DFS2_EN		(1)
+#define ARM_PLL_PHI1_DFS2_MFI		(1)
+#define ARM_PLL_PHI1_DFS2_MFN		(170)
+/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
+#define ARM_PLL_PHI1_DFS3_EN		(1)
+#define ARM_PLL_PHI1_DFS3_MFI		(1)
+#define ARM_PLL_PHI1_DFS3_MFN		(170)
+#define ARM_PLL_PHI1_DFS_Nr			(3)
+#define ARM_PLL_PLLDV_PREDIV		(2)
+#define ARM_PLL_PLLDV_MFD			(50)
+#define ARM_PLL_PLLDV_MFN			(0)
+
+#define PERIPH_PLL_PHI0_FREQ		(400000000)
+#define PERIPH_PLL_PHI1_FREQ		(100000000)
+#define PERIPH_PLL_PHI1_DFS_Nr		(0)
+#define PERIPH_PLL_PLLDV_PREDIV		(1)
+#define PERIPH_PLL_PLLDV_MFD		(30)
+#define PERIPH_PLL_PLLDV_MFN		(0)
+
+#define ENET_PLL_PHI0_FREQ			(500000000)
+#define ENET_PLL_PHI1_FREQ			(1000000000)
+/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
+#define ENET_PLL_PHI1_DFS1_EN		(1)
+#define ENET_PLL_PHI1_DFS1_MFI		(2)
+#define ENET_PLL_PHI1_DFS1_MFN		(219)
+/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
+#define ENET_PLL_PHI1_DFS2_EN		(1)
+#define ENET_PLL_PHI1_DFS2_MFI		(2)
+#define ENET_PLL_PHI1_DFS2_MFN		(219)
+/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
+#define ENET_PLL_PHI1_DFS3_EN		(1)
+#define ENET_PLL_PHI1_DFS3_MFI		(3)
+#define ENET_PLL_PHI1_DFS3_MFN		(32)
+/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
+#define ENET_PLL_PHI1_DFS4_EN		(1)
+#define ENET_PLL_PHI1_DFS4_MFI		(2)
+#define ENET_PLL_PHI1_DFS4_MFN		(0)
+#define ENET_PLL_PHI1_DFS_Nr		(4)
+#define ENET_PLL_PLLDV_PREDIV		(2)
+#define ENET_PLL_PLLDV_MFD			(50)
+#define ENET_PLL_PLLDV_MFN			(0)
+
+#define DDR_PLL_PHI0_FREQ			(533000000)
+#define DDR_PLL_PHI1_FREQ			(1066000000)
+/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
+#define DDR_PLL_PHI1_DFS1_EN		(1)
+#define DDR_PLL_PHI1_DFS1_MFI		(2)
+#define DDR_PLL_PHI1_DFS1_MFN		(33)
+/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
+#define DDR_PLL_PHI1_DFS2_EN		(1)
+#define DDR_PLL_PHI1_DFS2_MFI		(2)
+#define DDR_PLL_PHI1_DFS2_MFN		(33)
+/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
+#define DDR_PLL_PHI1_DFS3_EN		(1)
+#define DDR_PLL_PHI1_DFS3_MFI		(3)
+#define DDR_PLL_PHI1_DFS3_MFN		(11)
+#define DDR_PLL_PHI1_DFS_Nr			(3)
+#define DDR_PLL_PLLDV_PREDIV		(2)
+#define DDR_PLL_PLLDV_MFD			(53)
+#define DDR_PLL_PLLDV_MFN			(6144)
+
+#define VIDEO_PLL_PHI0_FREQ			(600000000)
+#define VIDEO_PLL_PHI1_FREQ			(0)
+#define VIDEO_PLL_PHI1_DFS_Nr		(0)
+#define VIDEO_PLL_PLLDV_PREDIV		(1)
+#define VIDEO_PLL_PLLDV_MFD			(30)
+#define VIDEO_PLL_PLLDV_MFN			(0)
+
+#endif
+
+#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
new file mode 100644
index 0000000..a1172e0
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* MC_ME registers definitions */
+
+/* MC_ME_GS */
+#define MC_ME_GS						(MC_ME_BASE_ADDR + 0x00000000)
+
+#define MC_ME_GS_S_SYSCLK_FIRC			(0x0 << 0)
+#define MC_ME_GS_S_SYSCLK_FXOSC			(0x1 << 0)
+#define MC_ME_GS_S_SYSCLK_ARMPLL		(0x2 << 0)
+#define MC_ME_GS_S_STSCLK_DISABLE		(0xF << 0)
+#define MC_ME_GS_S_FIRC					(1 << 4)
+#define MC_ME_GS_S_XOSC					(1 << 5)
+#define MC_ME_GS_S_ARMPLL				(1 << 6)
+#define MC_ME_GS_S_PERPLL				(1 << 7)
+#define MC_ME_GS_S_ENETPLL				(1 << 8)
+#define MC_ME_GS_S_DDRPLL				(1 << 9)
+#define MC_ME_GS_S_VIDEOPLL				(1 << 10)
+#define MC_ME_GS_S_MVR					(1 << 20)
+#define MC_ME_GS_S_PDO					(1 << 23)
+#define MC_ME_GS_S_MTRANS				(1 << 27)
+#define MC_ME_GS_S_CRT_MODE_RESET		(0x0 << 28)
+#define MC_ME_GS_S_CRT_MODE_TEST		(0x1 << 28)
+#define MC_ME_GS_S_CRT_MODE_DRUN		(0x3 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN0		(0x4 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN1		(0x5 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN2		(0x6 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN3		(0x7 << 28)
+
+/* MC_ME_MCTL */
+#define MC_ME_MCTL						(MC_ME_BASE_ADDR + 0x00000004)
+
+#define MC_ME_MCTL_KEY					(0x00005AF0)
+#define MC_ME_MCTL_INVERTEDKEY			(0x0000A50F)
+#define MC_ME_MCTL_RESET				(0x0 << 28)
+#define MC_ME_MCTL_TEST					(0x1 << 28)
+#define MC_ME_MCTL_DRUN					(0x3 << 28)
+#define MC_ME_MCTL_RUN0					(0x4 << 28)
+#define MC_ME_MCTL_RUN1					(0x5 << 28)
+#define MC_ME_MCTL_RUN2					(0x6 << 28)
+#define MC_ME_MCTL_RUN3					(0x7 << 28)
+
+/* MC_ME_ME */
+#define MC_ME_ME						(MC_ME_BASE_ADDR + 0x00000008)
+
+#define MC_ME_ME_RESET_FUNC				(1 << 0)
+#define MC_ME_ME_TEST					(1 << 1)
+#define MC_ME_ME_DRUN					(1 << 3)
+#define MC_ME_ME_RUN0					(1 << 4)
+#define MC_ME_ME_RUN1					(1 << 5)
+#define MC_ME_ME_RUN2					(1 << 6)
+#define MC_ME_ME_RUN3					(1 << 7)
+
+/* MC_ME_RUN_PCn */
+#define MC_ME_RUN_PCn(n)				(MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
+
+#define MC_ME_RUN_PCn_RESET				(1 << 0)
+#define MC_ME_RUN_PCn_TEST				(1 << 1)
+#define MC_ME_RUN_PCn_DRUN				(1 << 3)
+#define MC_ME_RUN_PCn_RUN0				(1 << 4)
+#define MC_ME_RUN_PCn_RUN1				(1 << 5)
+#define MC_ME_RUN_PCn_RUN2				(1 << 6)
+#define MC_ME_RUN_PCn_RUN3				(1 << 7)
+
+/*
+ * MC_ME_RESET_MC/MC_ME_TEST_MC
+ * MC_ME_DRUN_MC
+ * MC_ME_RUNn_MC
+ */
+#define MC_ME_RESET_MC						(MC_ME_BASE_ADDR + 0x00000020)
+#define MC_ME_TEST_MC						(MC_ME_BASE_ADDR + 0x00000024)
+#define MC_ME_DRUN_MC						(MC_ME_BASE_ADDR + 0x0000002C)
+#define MC_ME_RUNn_MC(n)					(MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
+
+#define MC_ME_RUNMODE_MC_SYSCLK(val)	(MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
+#define MC_ME_RUNMODE_MC_SYSCLK_MASK	(0x0000000F)
+#define MC_ME_RUNMODE_MC_FIRCON			(1 << 4)
+#define MC_ME_RUNMODE_MC_XOSCON			(1 << 5)
+#define MC_ME_RUNMODE_MC_PLL(pll)		(1 << (6 + (pll)))
+#define MC_ME_RUNMODE_MC_MVRON			(1 << 20)
+#define MC_ME_RUNMODE_MC_PDO			(1 << 23)
+#define MC_ME_RUNMODE_MC_PWRLVL0		(1 << 28)
+#define MC_ME_RUNMODE_MC_PWRLVL1		(1 << 29)
+#define MC_ME_RUNMODE_MC_PWRLVL2		(1 << 30)
+
+/* MC_ME_DRUN_SEC_CC_I */
+#define MC_ME_DRUN_SEC_CC_I					(MC_ME_BASE_ADDR + 0x260)
+/* MC_ME_RUNn_SEC_CC_I */
+#define MC_ME_RUNn_SEC_CC_I(n)				(MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)	((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET	(4)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET	(8)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET	(12)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK		(0x3)
+
+/*
+ * ME_PCTLn
+ * Please note that these registers are 8 bits width, so
+ * the operations over them should be done using 8 bits operations.
+ */
+#define MC_ME_PCTLn_RUNPCm(n)			( (n) & MC_ME_PCTLn_RUNPCm_MASK )
+#define MC_ME_PCTLn_RUNPCm_MASK			(0x7)
+
+/* DEC200 Peripheral Control Register		*/
+#define MC_ME_PCTL39	(MC_ME_BASE_ADDR + 0x000000E4)
+/* 2D-ACE Peripheral Control Register		*/
+#define MC_ME_PCTL40	(MC_ME_BASE_ADDR + 0x000000EB)
+/* ENET Peripheral Control Register		*/
+#define MC_ME_PCTL50	(MC_ME_BASE_ADDR + 0x000000F1)
+/* DMACHMUX0 Peripheral Control Register	*/
+#define MC_ME_PCTL49	(MC_ME_BASE_ADDR + 0x000000F2)
+/* CSI0 Peripheral Control Register			*/
+#define MC_ME_PCTL48	(MC_ME_BASE_ADDR + 0x000000F3)
+/* MMDC0 Peripheral Control Register		*/
+#define MC_ME_PCTL54	(MC_ME_BASE_ADDR + 0x000000F5)
+/* FRAY Peripheral Control Register			*/
+#define MC_ME_PCTL52	(MC_ME_BASE_ADDR + 0x000000F7)
+/* PIT0 Peripheral Control Register			*/
+#define MC_ME_PCTL58	(MC_ME_BASE_ADDR + 0x000000F9)
+/* FlexTIMER0 Peripheral Control Register	*/
+#define MC_ME_PCTL79	(MC_ME_BASE_ADDR + 0x0000010C)
+/* SARADC0 Peripheral Control Register		*/
+#define MC_ME_PCTL77	(MC_ME_BASE_ADDR + 0x0000010E)
+/* LINFLEX0 Peripheral Control Register		*/
+#define MC_ME_PCTL83	(MC_ME_BASE_ADDR + 0x00000110)
+/* IIC0 Peripheral Control Register			*/
+#define MC_ME_PCTL81	(MC_ME_BASE_ADDR + 0x00000112)
+/* DSPI0 Peripheral Control Register		*/
+#define MC_ME_PCTL87	(MC_ME_BASE_ADDR + 0x00000114)
+/* CANFD0 Peripheral Control Register		*/
+#define MC_ME_PCTL85	(MC_ME_BASE_ADDR + 0x00000116)
+/* CRC0 Peripheral Control Register			*/
+#define MC_ME_PCTL91	(MC_ME_BASE_ADDR + 0x00000118)
+/* DSPI2 Peripheral Control Register		*/
+#define MC_ME_PCTL89	(MC_ME_BASE_ADDR + 0x0000011A)
+/* SDHC Peripheral Control Register			*/
+#define MC_ME_PCTL93	(MC_ME_BASE_ADDR + 0x0000011E)
+/* VIU0 Peripheral Control Register			*/
+#define MC_ME_PCTL100	(MC_ME_BASE_ADDR + 0x00000127)
+/* HPSMI Peripheral Control Register		*/
+#define MC_ME_PCTL104	(MC_ME_BASE_ADDR + 0x0000012B)
+/* SIPI Peripheral Control Register			*/
+#define MC_ME_PCTL116	(MC_ME_BASE_ADDR + 0x00000137)
+/* LFAST Peripheral Control Register		*/
+#define MC_ME_PCTL120	(MC_ME_BASE_ADDR + 0x0000013B)
+/* MMDC1 Peripheral Control Register		*/
+#define MC_ME_PCTL162	(MC_ME_BASE_ADDR + 0x00000161)
+/* DMACHMUX1 Peripheral Control Register	*/
+#define MC_ME_PCTL161	(MC_ME_BASE_ADDR + 0x00000162)
+/* CSI1 Peripheral Control Register			*/
+#define MC_ME_PCTL160	(MC_ME_BASE_ADDR + 0x00000163)
+/* QUADSPI0 Peripheral Control Register		*/
+#define MC_ME_PCTL166	(MC_ME_BASE_ADDR + 0x00000165)
+/* PIT1 Peripheral Control Register			*/
+#define MC_ME_PCTL170	(MC_ME_BASE_ADDR + 0x00000169)
+/* FlexTIMER1 Peripheral Control Register	*/
+#define MC_ME_PCTL182	(MC_ME_BASE_ADDR + 0x00000175)
+/* IIC2 Peripheral Control Register			*/
+#define MC_ME_PCTL186	(MC_ME_BASE_ADDR + 0x00000179)
+/* IIC1 Peripheral Control Register			*/
+#define MC_ME_PCTL184	(MC_ME_BASE_ADDR + 0x0000017B)
+/* CANFD1 Peripheral Control Register		*/
+#define MC_ME_PCTL190	(MC_ME_BASE_ADDR + 0x0000017D)
+/* LINFLEX1 Peripheral Control Register		*/
+#define MC_ME_PCTL188	(MC_ME_BASE_ADDR + 0x0000017F)
+/* DSPI3 Peripheral Control Register		*/
+#define MC_ME_PCTL194	(MC_ME_BASE_ADDR + 0x00000181)
+/* DSPI1 Peripheral Control Register		*/
+#define MC_ME_PCTL192	(MC_ME_BASE_ADDR + 0x00000183)
+/* TSENS Peripheral Control Register		*/
+#define MC_ME_PCTL206	(MC_ME_BASE_ADDR + 0x0000018D)
+/* CRC1 Peripheral Control Register			*/
+#define MC_ME_PCTL204	(MC_ME_BASE_ADDR + 0x0000018F)
+/* VIU1 Peripheral Control Register		*/
+#define MC_ME_PCTL208	(MC_ME_BASE_ADDR + 0x00000193)
+/* JPEG Peripheral Control Register		*/
+#define MC_ME_PCTL212	(MC_ME_BASE_ADDR + 0x00000197)
+/* H264_DEC Peripheral Control Register	*/
+#define MC_ME_PCTL216	(MC_ME_BASE_ADDR + 0x0000019B)
+/* H264_ENC Peripheral Control Register	*/
+#define MC_ME_PCTL220	(MC_ME_BASE_ADDR + 0x0000019F)
+/* MBIST Peripheral Control Register	*/
+#define MC_ME_PCTL236	(MC_ME_BASE_ADDR + 0x000001A9)
+
+/* Core status register */
+#define MC_ME_CS               (MC_ME_BASE_ADDR + 0x000001C0)
+
+#endif
+
+#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
new file mode 100644
index 0000000..f39e81b
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
+
+#define MC_RGM_DES			(MC_RGM_BASE_ADDR)
+#define MC_RGM_FES			(MC_RGM_BASE_ADDR + 0x300)
+#define MC_RGM_FERD			(MC_RGM_BASE_ADDR + 0x310)
+#define MC_RGM_FBRE			(MC_RGM_BASE_ADDR + 0x330)
+#define MC_RGM_FESS			(MC_RGM_BASE_ADDR + 0x340)
+#define MC_RGM_DDR_HE			(MC_RGM_BASE_ADDR + 0x350)
+#define MC_RGM_DDR_HS			(MC_RGM_BASE_ADDR + 0x354)
+#define MC_RGM_FRHE			(MC_RGM_BASE_ADDR + 0x358)
+#define MC_RGM_FREC			(MC_RGM_BASE_ADDR + 0x600)
+#define MC_RGM_FRET			(MC_RGM_BASE_ADDR + 0x607)
+#define MC_RGM_DRET			(MC_RGM_BASE_ADDR + 0x60B)
+
+/* function reset sources mask */
+#define F_SWT4				0x8000
+#define F_JTAG				0x400
+#define F_FCCU_SOFT			0x40
+#define F_FCCU_HARD			0x20
+#define F_SOFT_FUNC			0x8
+#define F_ST_DONE			0x4
+#define F_EXT_RST			0x1
+
+#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h
new file mode 100644
index 0000000..504aa68
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mmdc.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
+#define __ARCH_ARM_MACH_S32V234_MMDC_H__
+
+#define MMDC0				0
+#define MMDC1				1
+
+#define MMDC_MDCTL			0x0
+#define MMDC_MDPDC			0x4
+#define MMDC_MDOTC			0x8
+#define MMDC_MDCFG0			0xC
+#define MMDC_MDCFG1			0x10
+#define MMDC_MDCFG2			0x14
+#define MMDC_MDMISC			0x18
+#define MMDC_MDSCR			0x1C
+#define MMDC_MDREF			0x20
+#define MMDC_MDRWD			0x2C
+#define MMDC_MDOR			0x30
+#define MMDC_MDMRR			0x34
+#define MMDC_MDCFG3LP		0x38
+#define MMDC_MDMR4			0x3C
+#define MMDC_MDASP			0x40
+#define MMDC_MAARCR			0x400
+#define MMDC_MAPSR			0x404
+#define MMDC_MAEXIDR0		0x408
+#define MMDC_MAEXIDR1		0x40C
+#define MMDC_MADPCR0		0x410
+#define MMDC_MADPCR1		0x414
+#define MMDC_MADPSR0		0x418
+#define MMDC_MADPSR1		0x41C
+#define MMDC_MADPSR2		0x420
+#define MMDC_MADPSR3		0x424
+#define MMDC_MADPSR4		0x428
+#define MMDC_MADPSR5		0x42C
+#define MMDC_MASBS0			0x430
+#define MMDC_MASBS1			0x434
+#define MMDC_MAGENP			0x440
+#define MMDC_MPZQHWCTRL		0x800
+#define MMDC_MPWLGCR		0x808
+#define MMDC_MPWLDECTRL0	0x80C
+#define MMDC_MPWLDECTRL1	0x810
+#define MMDC_MPWLDLST		0x814
+#define MMDC_MPODTCTRL		0x818
+#define MMDC_MPRDDQBY0DL	0x81C
+#define MMDC_MPRDDQBY1DL	0x820
+#define MMDC_MPRDDQBY2DL	0x824
+#define MMDC_MPRDDQBY3DL	0x828
+#define MMDC_MPDGCTRL0		0x83C
+#define MMDC_MPDGCTRL1		0x840
+#define MMDC_MPDGDLST0		0x844
+#define MMDC_MPRDDLCTL		0x848
+#define MMDC_MPRDDLST		0x84C
+#define MMDC_MPWRDLCTL		0x850
+#define MMDC_MPWRDLST		0x854
+#define MMDC_MPZQLP2CTL		0x85C
+#define MMDC_MPRDDLHWCTL	0x860
+#define MMDC_MPWRDLHWCTL	0x864
+#define MMDC_MPRDDLHWST0	0x868
+#define MMDC_MPRDDLHWST1	0x86C
+#define MMDC_MPWRDLHWST1	0x870
+#define MMDC_MPWRDLHWST2	0x874
+#define MMDC_MPWLHWERR		0x878
+#define MMDC_MPDGHWST0		0x87C
+#define MMDC_MPDGHWST1		0x880
+#define MMDC_MPDGHWST2		0x884
+#define MMDC_MPDGHWST3		0x888
+#define MMDC_MPPDCMPR1		0x88C
+#define MMDC_MPPDCMPR2		0x890
+#define MMDC_MPSWDAR0		0x894
+#define MMDC_MPSWDRDR0		0x898
+#define MMDC_MPSWDRDR1		0x89C
+#define MMDC_MPSWDRDR2		0x8A0
+#define MMDC_MPSWDRDR3		0x8A4
+#define MMDC_MPSWDRDR4		0x8A8
+#define MMDC_MPSWDRDR5		0x8AC
+#define MMDC_MPSWDRDR6		0x8B0
+#define MMDC_MPSWDRDR7		0x8B4
+#define MMDC_MPMUR0			0x8B8
+#define MMDC_MPDCCR			0x8C0
+
+#define MMDC_MPMUR0_FRC_MSR			(1 << 11)
+#define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(1 << 16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h
new file mode 100644
index 0000000..2e8c211
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/siul.h
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
+#define __ARCH_ARM_MACH_S32V234_SIUL_H__
+
+#include "ddr.h"
+
+#define SIUL2_MIDR1				(SIUL2_BASE_ADDR + 0x00000004)
+#define SIUL2_MIDR2				(SIUL2_BASE_ADDR + 0x00000008)
+#define SIUL2_DISR0				(SIUL2_BASE_ADDR + 0x00000010)
+#define SIUL2_DIRER0				(SIUL2_BASE_ADDR + 0x00000018)
+#define SIUL2_DIRSR0				(SIUL2_BASE_ADDR + 0x00000020)
+#define SIUL2_IREER0				(SIUL2_BASE_ADDR + 0x00000028)
+#define SIUL2_IFEER0				(SIUL2_BASE_ADDR + 0x00000030)
+#define SIUL2_IFER0				(SIUL2_BASE_ADDR + 0x00000038)
+
+#define SIUL2_IFMCR_BASE			(SIUL2_BASE_ADDR + 0x00000040)
+#define SIUL2_IFMCRn(i)				(SIUL2_IFMCR_BASE + 4 * (i))
+
+#define SIUL2_IFCPR				(SIUL2_BASE_ADDR + 0x000000C0)
+
+/* SIUL2_MSCR specifications as stated in Reference Manual:
+ * 0 - 359 Output Multiplexed Signal Configuration Registers
+ * 512- 1023 Input Multiplexed Signal Configuration Registers */
+#define SIUL2_MSCR_BASE				(SIUL2_BASE_ADDR + 0x00000240)
+#define SIUL2_MSCRn(i)				(SIUL2_MSCR_BASE + 4 * (i))
+
+#define SIUL2_IMCR_BASE				(SIUL2_BASE_ADDR + 0x00000A40)
+#define SIUL2_IMCRn(i)				(SIUL2_IMCR_BASE +  4 * (i))
+
+#define SIUL2_GPDO_BASE				(SIUL2_BASE_ADDR + 0x00001300)
+#define SIUL2_GPDOn(i)				(SIUL2_GPDO_BASE + 4 * (i))
+
+#define SIUL2_GPDI_BASE				(SIUL2_BASE_ADDR + 0x00001500)
+#define SIUL2_GPDIn(i)				(SIUL2_GPDI_BASE + 4 * (i))
+
+#define SIUL2_PGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001700)
+#define SIUL2_PGPDOn(i)				(SIUL2_PGPDO_BASE +  2 * (i))
+
+#define SIUL2_PGPDI_BASE			(SIUL2_BASE_ADDR + 0x00001740)
+#define SIUL2_PGPDIn(i)				(SIUL2_PGPDI_BASE + 2 * (i))
+
+#define SIUL2_MPGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001780)
+#define SIUL2_MPGPDOn(i)			(SIUL2_MPGPDO_BASE + 4 * (i))
+
+/* SIUL2_MSCR masks */
+#define SIUL2_MSCR_DDR_DO_TRIM(v)	((v) & 0xC0000000)
+#define SIUL2_MSCR_DDR_DO_TRIM_MIN	(0 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_50PS	(1 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_100PS	(2 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_150PS	(3 << 30)
+
+#define SIUL2_MSCR_DDR_INPUT(v)		((v) & 0x20000000)
+#define SIUL2_MSCR_DDR_INPUT_CMOS	(0 << 29)
+#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR	(1 << 29)
+
+#define SIUL2_MSCR_DDR_SEL(v)		((v) & 0x18000000)
+#define SIUL2_MSCR_DDR_SEL_DDR3		(0 << 27)
+#define SIUL2_MSCR_DDR_SEL_LPDDR2	(2 << 27)
+
+#define SIUL2_MSCR_DDR_ODT(v)		((v) & 0x07000000)
+#define SIUL2_MSCR_DDR_ODT_120ohm	(1 << 24)
+#define SIUL2_MSCR_DDR_ODT_60ohm	(2 << 24)
+#define SIUL2_MSCR_DDR_ODT_40ohm	(3 << 24)
+#define SIUL2_MSCR_DDR_ODT_30ohm	(4 << 24)
+#define SIUL2_MSCR_DDR_ODT_24ohm	(5 << 24)
+#define SIUL2_MSCR_DDR_ODT_20ohm	(6 << 24)
+#define SIUL2_MSCR_DDR_ODT_17ohm	(7 << 24)
+
+#define SIUL2_MSCR_DCYCLE_TRIM(v)	((v) & 0x00C00000)
+#define SIUL2_MSCR_DCYCLE_TRIM_NONE	(0 << 22)
+#define SIUL2_MSCR_DCYCLE_TRIM_LEFT	(1 << 22)
+#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT	(2 << 22)
+
+#define SIUL2_MSCR_OBE(v)		((v) & 0x00200000)
+#define SIUL2_MSCR_OBE_EN		(1 << 21)
+
+#define SIUL2_MSCR_ODE(v)		((v) & 0x00100000)
+#define SIUL2_MSCR_ODE_EN		(1 << 20)
+
+#define SIUL2_MSCR_IBE(v)		((v) & 0x00010000)
+#define SIUL2_MSCR_IBE_EN		(1 << 19)
+
+#define SIUL2_MSCR_HYS(v)		((v) & 0x00400000)
+#define SIUL2_MSCR_HYS_EN		(1 << 18)
+
+#define SIUL2_MSCR_INV(v)		((v) & 0x00020000)
+#define SIUL2_MSCR_INV_EN		(1 << 17)
+
+#define SIUL2_MSCR_PKE(v)		((v) & 0x00010000)
+#define SIUL2_MSCR_PKE_EN		(1 << 16)
+
+#define SIUL2_MSCR_SRE(v)		((v) & 0x0000C000)
+#define SIUL2_MSCR_SRE_SPEED_LOW_50	(0 << 14)
+#define SIUL2_MSCR_SRE_SPEED_LOW_100	(1 << 14)
+#define SIUL2_MSCR_SRE_SPEED_HIGH_100	(2 << 14)
+#define SIUL2_MSCR_SRE_SPEED_HIGH_200	(3 << 14)
+
+#define SIUL2_MSCR_PUE(v)		((v) & 0x00002000)
+#define SIUL2_MSCR_PUE_EN		(1 << 13)
+
+#define SIUL2_MSCR_PUS(v)		((v) & 0x00001800)
+#define SIUL2_MSCR_PUS_100K_DOWN	(0 << 11)
+#define SIUL2_MSCR_PUS_50K_DOWN		(1 << 11)
+#define SIUL2_MSCR_PUS_100K_UP		(2 << 11)
+#define SIUL2_MSCR_PUS_33K_UP		(3 << 11)
+
+#define SIUL2_MSCR_DSE(v)		((v) & 0x00000700)
+#define SIUL2_MSCR_DSE_240ohm		(1 << 8)
+#define SIUL2_MSCR_DSE_120ohm		(2 << 8)
+#define SIUL2_MSCR_DSE_80ohm		(3 << 8)
+#define SIUL2_MSCR_DSE_60ohm		(4 << 8)
+#define SIUL2_MSCR_DSE_48ohm		(5 << 8)
+#define SIUL2_MSCR_DSE_40ohm		(6 << 8)
+#define SIUL2_MSCR_DSE_34ohm		(7 << 8)
+
+#define SIUL2_MSCR_CRPOINT_TRIM(v)	((v) & 0x000000C0)
+#define SIUL2_MSCR_CRPOINT_TRIM_1	(1 << 6)
+
+#define SIUL2_MSCR_SMC(v)		((v) & 0x00000020)
+#define SIUL2_MSCR_MUX_MODE(v)		((v) & 0x0000000f)
+#define SIUL2_MSCR_MUX_MODE_ALT1	(0x1)
+#define SIUL2_MSCR_MUX_MODE_ALT2	(0x2)
+#define SIUL2_MSCR_MUX_MODE_ALT3	(0x3)
+
+/* UART settings */
+#define SIUL2_UART0_TXD_PAD	12
+#define SIUL2_UART_TXD		(SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm |	\
+				SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
+
+#define SIUL2_UART0_MSCR_RXD_PAD	11
+#define SIUL2_UART0_IMCR_RXD_PAD	200
+
+#define SIUL2_UART_MSCR_RXD	(SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
+#define SIUL2_UART_IMCR_RXD	(SIUL2_MSCR_MUX_MODE_ALT2)
+
+/* uSDHC settings */
+#define SIUL2_USDHC_PAD_CTRL_BASE	(SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN |	\
+						SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN |		\
+						SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
+#define SIUL2_USDHC_PAD_CTRL_CMD	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
+#define SIUL2_USDHC_PAD_CTRL_CLK	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
+#define SIUL2_USDHC_PAD_CTRL_DAT0_3	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
+#define SIUL2_USDHC_PAD_CTRL_DAT4_7	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
+
+#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */
diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig
new file mode 100644
index 0000000..e71dfc4
--- /dev/null
+++ b/board/freescale/s32v234evb/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_S32V234EVB
+
+config SYS_CPU
+	string
+	default "armv8"
+
+config SYS_BOARD
+	string
+	default "s32v234evb"
+
+config SYS_VENDOR
+	string
+	default "freescale"
+
+config SYS_SOC
+	string
+	default "s32v234"
+
+config SYS_CONFIG_NAME
+	string
+	default "s32v234evb"
+
+endif
diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS
new file mode 100644
index 0000000..62b2e1b
--- /dev/null
+++ b/board/freescale/s32v234evb/MAINTAINERS
@@ -0,0 +1,8 @@
+S32V234 Evaluation BOARD
+M:	Eddy Petrișor <eddy.petrisor@gmail.com>
+S:	Maintained
+F:	arch/arm/cpu/armv8/s32v234/
+F:	arch/arm/include/asm/arch-s32v234/
+F:	board/freescale/s32v234evb/
+F:	include/configs/s32v234evb.h
+F:	configs/s32v234evb_defconfig
diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile
new file mode 100644
index 0000000..69e6d3e
--- /dev/null
+++ b/board/freescale/s32v234evb/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y   := clock.o
+obj-y   += lpddr2.o
+obj-y   += s32v234evb.o
+
+#########################################################################
diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c
new file mode 100644
index 0000000..d218c21
--- /dev/null
+++ b/board/freescale/s32v234evb/clock.c
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mc_cgm_regs.h>
+#include <asm/arch/mc_me_regs.h>
+#include <asm/arch/clock.h>
+
+/*
+ * Select the clock reference for required pll.
+ * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
+ * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
+ */
+static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)
+{
+	u32 clk_src;
+	u32 pll_idx;
+	volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR;
+
+	/* select the pll clock source */
+	switch (refclk_freq) {
+	case FIRC_CLK_FREQ:
+		clk_src = SRC_GPR1_FIRC_CLK_SOURCE;
+		break;
+	case XOSC_CLK_FREQ:
+		clk_src = SRC_GPR1_XOSC_CLK_SOURCE;
+		break;
+	default:
+		/* The clock frequency for the source clock is unknown */
+		return -1;
+	}
+	/*
+	 * The hardware definition is not uniform, it has to calculate again
+	 * the recurrence formula.
+	 */
+	switch (pll) {
+	case PERIPH_PLL:
+		pll_idx = 3;
+		break;
+	case ENET_PLL:
+		pll_idx = 1;
+		break;
+	case DDR_PLL:
+		pll_idx = 2;;
+		break;
+	default:
+		pll_idx = pll;
+	}
+
+	writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src),
+	       &src->gpr1);
+
+	return 0;
+}
+
+static void entry_to_target_mode(u32 mode)
+{
+	writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL);
+	writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL);
+	while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ;
+}
+
+/*
+ * Program the pll according to the input parameters.
+ * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL.
+ * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
+ * freq - expected output frequency for PHY0
+ * freq1 - expected output frequency for PHY1
+ * dfs_nr - number of DFS modules for current PLL
+ * dfs - array with the activation dfs field, mfn and mfi
+ * plldv_prediv - divider of clkfreq_ref
+ * plldv_mfd - loop multiplication factor divider
+ * pllfd_mfn - numerator loop multiplication factor divider
+ * Please consult the PLLDIG chapter of platform manual
+ * before to use this function.
+ *)
+ */
+static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1,
+		       u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv,
+		       u32 plldv_mfd, u32 pllfd_mfn)
+{
+	u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco;
+
+	/*
+	 * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter.
+	 */
+	fvco =
+	    (refclk_freq / plldv_prediv) * (plldv_mfd +
+					    pllfd_mfn / (float)20480);
+
+	/*
+	 * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult
+	 * the platform DataSheet in order to determine the allowed values.
+	 */
+
+	if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) {
+		return -1;
+	}
+
+	if (select_pll_source_clk(pll, refclk_freq) < 0) {
+		return -1;
+	}
+
+	rfdphi = fvco / freq0;
+
+	rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1;
+
+	writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) |
+	       PLLDIG_PLLDV_RFDPHI_SET(rfdphi) |
+	       PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) |
+	       PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll));
+
+	writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) |
+	       PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll));
+
+	/* switch on the pll in current mode */
+	writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll),
+	       MC_ME_RUNn_MC(0));
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+	/* Only ARM_PLL, ENET_PLL and DDR_PLL */
+	if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) {
+		/* DFS clk enable programming */
+		writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll));
+
+		writel(DFS_DLLPRG1_CPICTRL_SET(0x5) |
+		       DFS_DLLPRG1_VSETTLCTRL_SET(0x1) |
+		       DFS_DLLPRG1_CALBYPEN_SET(0x0) |
+		       DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) |
+		       DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll));
+
+		for (i = 0; i < dfs_nr; i++) {
+			if (dfs[i][0]) {
+				writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) |
+				       DFS_DVPORTn_MFN_SET(dfs[i][1]),
+				       DFS_DVPORTn(pll, i));
+				dfs_on |= (dfs[i][0] << i);
+			}
+		}
+
+		writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET,
+		       DFS_CTRL(pll));
+		writel(readl(DFS_PORTRESET(pll)) &
+		       ~DFS_PORTRESET_PORTRESET_SET(dfs_on),
+		       DFS_PORTRESET(pll));
+		while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ;
+	}
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+	return 0;
+
+}
+
+static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source)
+{
+	/* select the clock source */
+	writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac));
+}
+
+static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider)
+{
+	/* set the divider */
+	writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider),
+	       CGM_ACn_DCm(cgm_addr, ac, dc));
+}
+
+static void setup_sys_clocks(void)
+{
+
+	/* set ARM PLL DFS 1 as SYSCLK */
+	writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) |
+	       MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0));
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+	/* select sysclks  ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */
+	writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK
+	       (0x2,
+		MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) |
+	       MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
+					     MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET)
+	       | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2,
+					       MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET),
+	       MC_ME_RUNn_SEC_CC_I(0));
+
+	/* setup the sys clock divider for CORE_CLK (1000MHz) */
+	writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
+	       CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0));
+
+	/* setup the sys clock divider for CORE2_CLK (500MHz) */
+	writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
+	       CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1));
+	/* setup the sys clock divider for SYS3_CLK (266 MHz) */
+	writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0),
+	       CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0));
+
+	/* setup the sys clock divider for SYS6_CLK (133 Mhz) */
+	writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1),
+	       CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1));
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+}
+
+static void setup_aux_clocks(void)
+{
+	/*
+	 * setup the aux clock divider for PERI_CLK
+	 * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)
+	 */
+	aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX);
+	aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4);
+
+	/* setup the aux clock divider for LIN_CLK (40MHz) */
+	aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX);
+	aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1);
+
+	/* setup the aux clock divider for ENET_TIME_CLK (50MHz) */
+	aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL);
+	aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9);
+
+	/* setup the aux clock divider for ENET_CLK (50MHz) */
+	aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL);
+	aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9);
+
+	/* setup the aux clock divider for SDHC_CLK (50 MHz). */
+	aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL);
+	aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9);
+
+	/* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */
+	aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL);
+	aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0);
+	/* setup the aux clock divider for DDR4_CLK (133,25MHz) */
+	aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3);
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+}
+
+static void enable_modules_clock(void)
+{
+	/* PIT0 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58);
+	/* PIT1 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170);
+	/* LINFLEX0 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83);
+	/* LINFLEX1 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188);
+	/* ENET */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50);
+	/* SDHC */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93);
+	/* IIC0 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81);
+	/* IIC1 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184);
+	/* IIC2 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186);
+	/* MMDC0 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54);
+	/* MMDC1 */
+	writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162);
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+}
+
+void clock_init(void)
+{
+	unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
+		{ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN,
+		 ARM_PLL_PHI1_DFS1_MFI},
+		{ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN,
+		 ARM_PLL_PHI1_DFS2_MFI},
+		{ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN,
+		 ARM_PLL_PHI1_DFS3_MFI}
+	};
+
+	unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
+		{ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN,
+		 ENET_PLL_PHI1_DFS1_MFI},
+		{ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN,
+		 ENET_PLL_PHI1_DFS2_MFI},
+		{ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN,
+		 ENET_PLL_PHI1_DFS3_MFI},
+		{ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN,
+		 ENET_PLL_PHI1_DFS4_MFI}
+	};
+
+	unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = {
+		{DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN,
+		 DDR_PLL_PHI1_DFS1_MFI},
+		{DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN,
+		 DDR_PLL_PHI1_DFS2_MFI},
+		{DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN,
+		 DDR_PLL_PHI1_DFS3_MFI}
+	};
+
+	writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 |
+	       MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0));
+
+	/* turn on FXOSC */
+	writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON |
+	       MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1),
+	       MC_ME_RUNn_MC(0));
+
+	entry_to_target_mode(MC_ME_MCTL_RUN0);
+
+	program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ,
+		    ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs,
+		    ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN);
+
+	setup_sys_clocks();
+
+	program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ,
+		    PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL,
+		    PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD,
+		    PERIPH_PLL_PLLDV_MFN);
+
+	program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ,
+		    ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs,
+		    ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD,
+		    ENET_PLL_PLLDV_MFN);
+
+	program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ,
+		    DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs,
+		    DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN);
+
+	program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ,
+		    VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL,
+		    VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD,
+		    VIDEO_PLL_PLLDV_MFN);
+
+	setup_aux_clocks();
+
+	enable_modules_clock();
+
+}
diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c
new file mode 100644
index 0000000..ecc0842
--- /dev/null
+++ b/board/freescale/s32v234evb/lpddr2.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/siul.h>
+#include <asm/arch/lpddr2.h>
+#include <asm/arch/mmdc.h>
+
+volatile int mscr_offset_ck0;
+
+void lpddr2_config_iomux(uint8_t module)
+{
+	int i;
+
+	switch (module) {
+	case DDR0:
+		mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
+		writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
+
+		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
+		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
+
+		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
+		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
+
+		for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
+			writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
+
+		for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
+			writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
+
+		for (i = _DDR0_A0; i <= _DDR0_A9; i++)
+			writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
+
+		for (i = _DDR0_D0; i <= _DDR0_D31; i++)
+			writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
+		break;
+	case DDR1:
+		writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
+
+		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
+		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
+
+		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
+		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
+
+		for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
+			writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
+
+		for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
+			writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
+
+		for (i = _DDR1_A0; i <= _DDR1_A9; i++)
+			writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
+
+		for (i = _DDR1_D0; i <= _DDR1_D31; i++)
+			writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
+		break;
+	}
+}
+
+void config_mmdc(uint8_t module)
+{
+	unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
+
+	writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
+
+	writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
+	writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
+	writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
+	writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
+	writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
+	writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
+	writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
+	writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
+
+	writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
+
+	while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
+	}
+
+	writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
+
+	/* Perform ZQ calibration */
+	writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
+	writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
+	while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
+	}
+
+	/* Enable MMDC with CS0 */
+	writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
+
+	/* Complete the initialization sequence as defined by JEDEC */
+	writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
+	writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
+	writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
+	writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
+
+	/* Set the amount of DRAM */
+	/* Set DQS settings based on board type */
+
+	switch (module) {
+	case MMDC0:
+		writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
+		writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
+		       mmdc_addr + MMDC_MPRDDLCTL);
+		writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
+		       mmdc_addr + MMDC_MPWRDLCTL);
+		writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
+		       mmdc_addr + MMDC_MPDGCTRL0);
+		writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
+		       mmdc_addr + MMDC_MPDGCTRL1);
+		break;
+	case MMDC1:
+		writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
+		writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
+		       mmdc_addr + MMDC_MPRDDLCTL);
+		writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
+		       mmdc_addr + MMDC_MPWRDLCTL);
+		writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
+		       mmdc_addr + MMDC_MPDGCTRL0);
+		writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
+		       mmdc_addr + MMDC_MPDGCTRL1);
+		break;
+	}
+
+	writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
+	writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
+	writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
+	writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
+	writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
+
+}
diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c
new file mode 100644
index 0000000..3100f09
--- /dev/null
+++ b/board/freescale/s32v234evb/s32v234evb.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/siul.h>
+#include <asm/arch/lpddr2.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void setup_iomux_ddr(void)
+{
+	lpddr2_config_iomux(DDR0);
+	lpddr2_config_iomux(DDR1);
+
+}
+
+void ddr_phy_init(void)
+{
+}
+
+void ddr_ctrl_init(void)
+{
+	config_mmdc(0);
+	config_mmdc(1);
+}
+
+int dram_init(void)
+{
+	setup_iomux_ddr();
+
+	ddr_ctrl_init();
+
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* Muxing for linflex */
+	/* Replace the magic values after bringup */
+
+	/* set TXD - MSCR[12] PA12 */
+	writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
+
+	/* set RXD - MSCR[11] - PA11 */
+	writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
+
+	/* set RXD - IMCR[200] - 200 */
+	writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
+}
+
+static void setup_iomux_enet(void)
+{
+}
+
+static void setup_iomux_i2c(void)
+{
+}
+
+#ifdef CONFIG_SYS_USE_NAND
+void setup_iomux_nfc(void)
+{
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{USDHC_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t * bis)
+{
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
+
+	/* Set iomux PADS for USDHC */
+
+	/* PK6 pad: uSDHC clk */
+	writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
+	writel(0x3, SIUL2_MSCRn(902));
+
+	/* PK7 pad: uSDHC CMD */
+	writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
+	writel(0x3, SIUL2_MSCRn(901));
+
+	/* PK8 pad: uSDHC DAT0 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
+	writel(0x3, SIUL2_MSCRn(903));
+
+	/* PK9 pad: uSDHC DAT1 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
+	writel(0x3, SIUL2_MSCRn(904));
+
+	/* PK10 pad: uSDHC DAT2 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
+	writel(0x3, SIUL2_MSCRn(905));
+
+	/* PK11 pad: uSDHC DAT3 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
+	writel(0x3, SIUL2_MSCRn(906));
+
+	/* PK15 pad: uSDHC DAT4 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
+	writel(0x3, SIUL2_MSCRn(907));
+
+	/* PL0 pad: uSDHC DAT5 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
+	writel(0x3, SIUL2_MSCRn(908));
+
+	/* PL1 pad: uSDHC DAT6 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
+	writel(0x3, SIUL2_MSCRn(909));
+
+	/* PL2 pad: uSDHC DAT7 */
+	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
+	writel(0x3, SIUL2_MSCRn(910));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+	setup_iomux_i2c();
+#ifdef CONFIG_SYS_USE_NAND
+	setup_iomux_nfc();
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: s32v234evb\n");
+
+	return 0;
+}
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg
new file mode 100644
index 0000000..6017a40
--- /dev/null
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+BOOT_FROM sd
+
+
+/*
+ * Boot Device : one of qspi, sd:
+ * qspi:   flash_offset: 0x1000
+ * sd/mmc: flash_offset: 0x1000
+ */
+
+
+#ifdef CONFIG_SECURE_BOOT
+SECURE_BOOT
+#endif
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
new file mode 100644
index 0000000..847de63
--- /dev/null
+++ b/configs/s32v234evb_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_S32V234EVB=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
+CONFIG_CMD_BOOTZ=y
+CONFIG_OF_LIBFDT=y
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 57ad975..b7b4f14 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -208,7 +208,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	int timeout;
 	struct fsl_esdhc_priv *priv = mmc->priv;
 	struct fsl_esdhc *regs = priv->esdhc_regs;
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 	dma_addr_t addr;
 #endif
 	uint wml_value;
@@ -221,7 +221,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 		addr = virt_to_phys((void *)(data->dest));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -247,7 +247,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 					wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 		addr = virt_to_phys((void *)(data->src));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -312,7 +312,7 @@ static void check_and_invalidate_dcache_range
 	unsigned end = 0;
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
-#ifdef CONFIG_FSL_LAYERSCAPE
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 	dma_addr_t addr;
 
 	addr = virt_to_phys((void *)(data->dest));
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
new file mode 100644
index 0000000..9723bab
--- /dev/null
+++ b/include/configs/s32v234evb.h
@@ -0,0 +1,260 @@
+/*
+ * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ * Configuration settings for the Freescale S32V234 EVB board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_S32V234
+#define CONFIG_DM
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Config GIC */
+#define CONFIG_GICV2
+#define GICD_BASE 0x7D001000
+#define GICC_BASE 0x7D002000
+
+#define CONFIG_REMAKE_ELF
+#undef CONFIG_RUN_FROM_IRAM_ONLY
+
+#define CONFIG_RUN_FROM_DDR1
+#undef CONFIG_RUN_FROM_DDR0
+
+/* Run by default from DDR1  */
+#ifdef CONFIG_RUN_FROM_DDR0
+#define DDR_BASE_ADDR		0x80000000
+#else
+#define DDR_BASE_ADDR		0xC0000000
+#endif
+
+#define CONFIG_MACH_TYPE		4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Config CACHE */
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_FULL_VA
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY               (1000000000)	/* 1000MHz */
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+
+/* Size of malloc() pool */
+#ifdef CONFIG_RUN_FROM_IRAM_ONLY
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#endif
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_DM_SERIAL
+#define CONFIG_FSL_LINFLEXUART
+#define LINFLEXUART_BASE		LINFLEXD0_BASE_ADDR
+
+#define CONFIG_DEBUG_UART_LINFLEXUART
+#define CONFIG_DEBUG_UART_BASE		LINFLEXUART_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT		(1)
+#define CONFIG_BAUDRATE				115200
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+/* #define CONFIG_CMD_EXT2 EXT2 Support */
+#define CONFIG_CMD_FAT		/* FAT support */
+#define CONFIG_DOS_PARTITION
+
+#if 0
+
+/* Ethernet config */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE            ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE     RMII
+#define CONFIG_FEC_MXC_PHYADDR  0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#endif
+
+#if 0				/* Disable until the I2C driver will be updated */
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE		I2C0_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#if 0				/* Disable until the FLASH will be implemented */
+#define CONFIG_SYS_USE_NAND
+#endif
+
+#ifdef CONFIG_SYS_USE_NAND
+/* Nand Flash Configs */
+#define	CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define MTD_NAND_FSL_NFC_SWECC 1
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE		0x400E0000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+#endif
+
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_LOADADDR			0xC307FFC0
+#define CONFIG_BOOTARGS			"console=ttyLF0 root=/dev/ram rw"
+
+#define CONFIG_CMD_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"boot_scripts=boot.scr.uimg boot.scr\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"console=ttyLF0,115200\0" \
+	"fdt_file=s32v234-evb.dtb\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0xC2000000\0" \
+	"kernel_addr_r=0xC307FFC0\0" \
+	"ramdisk_addr_r=0xC4000000\0" \
+	"ramdisk=rootfs.uimg\0"\
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
+	"jtagboot=echo Booting using jtag...; " \
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+	"jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
+		"run loaduimage; run loadramdisk; run loadfdt;"\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+	"boot_net_usb_start=true\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+	"run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"=> "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	(DDR_BASE_ADDR)
+#define CONFIG_SYS_MEMTEST_END		(DDR_BASE_ADDR + 0x7C00000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ				1000
+
+#define CONFIG_SYS_TEXT_BASE		0x3E800000	/* SDRAM */
+
+#ifdef CONFIG_RUN_FROM_IRAM_ONLY
+#define CONFIG_SYS_MALLOC_BASE		(DDR_BASE_ADDR)
+#endif
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+
+#if 0
+/* Configure PXE */
+#define CONFIG_CMD_PXE
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
+#endif
+
+/* Physical memory map */
+/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			(DDR_BASE_ADDR)
+#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#endif
-- 
cgit v0.10.2


From 165bd7a1cc1624750376eb291bcd3c46597b4148 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 10 Jun 2016 09:35:42 +0530
Subject: board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVM

board/am57xx supports all boards based on am57xx. Rename the taget
as TARGET_AM57XX_EVM.

Fixes: 74cc8b097d9af ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms")
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
index 026bf24..4fb5ef9 100644
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ b/arch/arm/cpu/armv7/omap5/Kconfig
@@ -14,8 +14,8 @@ config TARGET_DRA7XX_EVM
 	bool "TI DRA7XX"
 	select TI_I2C_BOARD_DETECT
 
-config TARGET_BEAGLE_X15
-	bool "BeagleBoard X15"
+config TARGET_AM57XX_EVM
+	bool "AM57XX"
 	select TI_I2C_BOARD_DETECT
 
 endchoice
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 602fab1..daddb8f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -115,7 +115,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_vining_fpga.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
-dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
+dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
 dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig
index 87654f9..cead0f4 100644
--- a/board/ti/am57xx/Kconfig
+++ b/board/ti/am57xx/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_BEAGLE_X15
+if TARGET_AM57XX_EVM
 
 config SYS_BOARD
 	default "am57xx"
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index b63ff89..4d8fbcd 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 1cf82d2..4c5a0de 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index aa459a1..ce377cb 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-- 
cgit v0.10.2


From 7a0ea589ba8344eb39f864cb277b5056e37b50a7 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 10 Jun 2016 09:35:43 +0530
Subject: board: am57xx: fit: add support for selecting dtb dynamically

FIT allows for a multiple dtb in a single image. SPL needs away to
detect the right dtb to be used. Adding support for the same for am57xx
platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index ccf97b2..ac5b794 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -736,3 +736,15 @@ int ft_board_setup(void *blob, bd_t *bd)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
+		return 0;
+	else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
+		return 0;
+	else
+		return -1;
+}
+#endif
-- 
cgit v0.10.2


From 5e8f29a08225016311d190363c68eeab5b8b4b7c Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 10 Jun 2016 09:35:44 +0530
Subject: ARM: AM57xx: Enable FIT

Enable FIT support for AM57xx platforms

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 4d8fbcd..249a287 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -36,3 +36,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am57xx-beagle-x15"
-- 
cgit v0.10.2


From 332dddc6a1290665963be3b74d3ec7a80d7bf1ae Mon Sep 17 00:00:00 2001
From: Schuyler Patton <spatton@ti.com>
Date: Fri, 10 Jun 2016 09:35:45 +0530
Subject: ARM: dts: AM572x-IDK Initial Support

Add initial DTS support for AM572-IDK evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index daddb8f..0b2b269 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -115,7 +115,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_vining_fpga.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
-dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb
+dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
+	am572x-idk.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
 
 dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts
new file mode 100644
index 0000000..b340551
--- /dev/null
+++ b/arch/arm/dts/am572x-idk.dts
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+	model = "TI AM5728 IDK";
+	compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
+		     "ti,dra7";
+
+	chosen {
+		stdout-path = &uart3;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	extcon_usb2: extcon_usb2 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+	};
+
+	status-leds {
+		compatible = "gpio-leds";
+		cpu0-led {
+			label = "status0:red:cpu0";
+			gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu0";
+		};
+
+		usr0-led {
+			label = "status0:green:usr";
+			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		heartbeat-led {
+			label = "status0:blue:heartbeat";
+			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+
+		cpu1-led {
+			label = "status1:red:cpu1";
+			gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu1";
+		};
+
+		usr1-led {
+			label = "status1:green:usr";
+			gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		mmc0-led {
+			label = "status1:blue:mmc0";
+			gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+	};
+};
+
+&omap_dwc3_2 {
+	extcon = <&extcon_usb2>;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&v3_3d>;
+	vmmc_aux-supply = <&ldo1_reg>;
+	bus-width = <4>;
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
new file mode 100644
index 0000000..2805b68
--- /dev/null
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	aliases {
+		rtc0 = &tps659038_rtc;
+		rtc1 = &rtc;
+	};
+
+	vmain: fixedregulator-vmain {
+		compatible = "regulator-fixed";
+		regulator-name = "VMAIN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	v3_3d: fixedregulator-v3_3d {
+		compatible = "regulator-fixed";
+		regulator-name = "V3_3D";
+		vin-supply = <&smps9_reg>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vtt_fixed: fixedregulator-vtt {
+		/* TPS51200 */
+		compatible = "regulator-fixed";
+		regulator-name = "vtt_fixed";
+		vin-supply = <&v3_3d>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps659038: tps659038@58 {
+		compatible = "ti,tps659038";
+		reg = <0x58>;
+		interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
+			       &dra7_pmx_core 0x418>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		ti,system-power-controller;
+
+		tps659038_pmic {
+			compatible = "ti,tps659038-pmic";
+			regulators {
+				smps12_reg: smps12 {
+					/* VDD_MPU */
+					vin-supply = <&vmain>;
+					regulator-name = "smps12";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps3_reg: smps3 {
+					/* VDD_DDR EMIF1 EMIF2 */
+					vin-supply = <&vmain>;
+					regulator-name = "smps3";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps45_reg: smps45 {
+					/* VDD_DSPEVE on AM572 */
+					/* VDD_IVA + VDD_DSP on AM571 */
+					vin-supply = <&vmain>;
+					regulator-name = "smps45";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps6_reg: smps6 {
+					/* VDD_GPU */
+					vin-supply = <&vmain>;
+					regulator-name = "smps6";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps7_reg: smps7 {
+					/* VDD_CORE */
+					vin-supply = <&vmain>;
+					regulator-name = "smps7";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps8_reg: smps8 {
+					/* 5728 - VDD_IVAHD */
+					/* 5718 - N.C. test point */
+					vin-supply = <&vmain>;
+					regulator-name = "smps8";
+				};
+
+				smps9_reg: smps9 {
+					/* VDD_3_3D */
+					vin-supply = <&vmain>;
+					regulator-name = "smps9";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo1_reg: ldo1 {
+					/* VDDSHV8 - VSDMMC  */
+					/* NOTE: on rev 1.3a, data supply */
+					vin-supply = <&vmain>;
+					regulator-name = "ldo1";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo2_reg: ldo2 {
+					/* VDDSH18V */
+					vin-supply = <&vmain>;
+					regulator-name = "ldo2";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo3_reg: ldo3 {
+					/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
+					vin-supply = <&vmain>;
+					regulator-name = "ldo3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo4_reg: ldo4 {
+					/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
+					vin-supply = <&vmain>;
+					regulator-name = "ldo4";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				/* LDO5-8 unused */
+
+				ldo9_reg: ldo9 {
+					/* VDD_RTC  */
+					vin-supply = <&vmain>;
+					regulator-name = "ldo9";
+					regulator-min-microvolt = <840000>;
+					regulator-max-microvolt = <1160000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldoln_reg: ldoln {
+					/* VDDA_1V8_PLL */
+					vin-supply = <&vmain>;
+					regulator-name = "ldoln";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldousb_reg: ldousb {
+					/* VDDA_3V_USB: VDDA_USBHS33 */
+					vin-supply = <&vmain>;
+					regulator-name = "ldousb";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldortc_reg: ldortc {
+					/* VDDA_RTC  */
+					vin-supply = <&vmain>;
+					regulator-name = "ldortc";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				regen1: regen1 {
+					/* VDD_3V3_ON */
+					regulator-name = "regen1";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				regen2: regen2 {
+					/* Needed for PMIC internal resource */
+					regulator-name = "regen2";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+			};
+		};
+
+		tps659038_rtc: tps659038_rtc {
+			compatible = "ti,palmas-rtc";
+			interrupt-parent = <&tps659038>;
+			interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+			wakeup-source;
+		};
+
+		tps659038_pwr_button: tps659038_pwr_button {
+			compatible = "ti,palmas-pwrbutton";
+			interrupt-parent = <&tps659038>;
+			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+			wakeup-source;
+			ti,palmas-long-press-seconds = <12>;
+		};
+
+		tps659038_gpio: tps659038_gpio {
+			compatible = "ti,palmas-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
+
+&uart3 {
+	status = "okay";
+	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
+			       &dra7_pmx_core 0x248>;
+};
+
+&rtc {
+	status = "okay";
+	ext-clk-src;
+};
+
+&mac {
+	status = "okay";
+	dual_emac;
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rgmii";
+	dual_emac_res_vlan = <2>;
+};
+
+&usb2_phy1 {
+	phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+	phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+	dr_mode = "host";
+};
+
+&usb2 {
+	dr_mode = "otg";
+};
+
+&mmc2 {
+	status = "okay";
+	vmmc-supply = <&v3_3d>;
+	bus-width = <8>;
+	ti,non-removable;
+	max-frequency = <96000000>;
+};
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index ac5b794..08cf14d 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -744,6 +744,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
 		return 0;
+	else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
+		return 0;
 	else
 		return -1;
 }
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 249a287..8526526 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -39,4 +39,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_LIST="am57xx-beagle-x15"
+CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
-- 
cgit v0.10.2


From cc5cdaad42dc6672ca41c2a2848003a051350d02 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 10 Jun 2016 09:35:46 +0530
Subject: ti_omap5_common: Add right dtb file for AM572x-IDK

Add proper dtb file name for AM572x-IDK in env.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 5c5a12d..2e4c8e9 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -104,6 +104,8 @@
 			"setenv fdtfile dra72-evm.dtb; fi;" \
 		"if test $board_name = beagle_x15; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+		"if test $board_name = am572x_idk; then " \
+			"setenv fdtfile am572x-idk.dtb; fi;" \
 		"if test $board_name = am57xx_evm; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
 		"if test $fdtfile = undefined; then " \
-- 
cgit v0.10.2


From 1736121b24f0cf05b08bac03035b9d34d52a5d99 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Fri, 10 Jun 2016 10:44:47 +0530
Subject: board: am437x-hs: spl: Select right dtb from fit

Select a right dtb from FIT for am437x-hs platform.

Reported-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index bde5ac7..f005762 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -850,7 +850,7 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+	if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 		return 0;
 	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 		return 0;
-- 
cgit v0.10.2


From f221db0ed5b4c6580abb4ab6fde5cbabaa348350 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 15:35:21 -0700
Subject: usb: dwc2_udc_otg: support 8-bit interface

Define CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 to allow the
physical interface to be 8-bit (rather than 16-bit).

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index a35a1c7..ae62476 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -52,6 +52,16 @@ config USB_GADGET_DWC2_OTG
 	  driver to operate in Peripheral mode. This option requires
 	  USB_GADGET to be enabled.
 
+if USB_GADGET_DWC2_OTG
+
+config USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
+	bool "DesignWare USB2.0 HS OTG controller 8-bit PHY bus width"
+	help
+	  Set the Designware USB2.0 high-speed OTG controller
+	  PHY interface width to 8 bits, rather than the default (16 bits).
+
+endif # USB_GADGET_DWC2_OTG
+
 config CI_UDC
 	bool "ChipIdea device controller"
 	select USB_GADGET_DUALSPEED
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index cb20b00..a23278d 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -415,7 +415,11 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 		|0<<7		/* Ulpi DDR sel*/
 		|0<<6		/* 0: high speed utmi+, 1: full speed serial*/
 		|0<<4		/* 0: utmi+, 1:ulpi*/
+#ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
+		|0<<3		/* phy i/f  0:8bit, 1:16bit*/
+#else
 		|1<<3		/* phy i/f  0:8bit, 1:16bit*/
+#endif
 		|0x7<<0;	/* HS/FS Timeout**/
 
 	if (dev->pdata->usb_gusbcfg)
-- 
cgit v0.10.2


From 1653cd18eee1555e1fd4a8c2fd88048d53bdc619 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 15:35:22 -0700
Subject: arm: bcm281xx: choose 8-bit phy bus width

The Kona PHY supports an 8-bit wide UTMI interface,
therefore, choose this Kconfig setting.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index b8ec8ac..2716868 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 6021fd2..8e01c52 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 71a52a1..4c0f3b3 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 97fe622..e9d13b9 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
-- 
cgit v0.10.2


From 6fb522dc774db981e1c8463e71898287e039c5f4 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 13 Jun 2016 09:58:32 +0530
Subject: arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper

Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 9a5a6b5..9c575c1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -528,6 +528,13 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 	return -1;      /* cannot identify the cluster */
 }
 
+uint get_svr(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	return gur_in32(&gur->svr);
+}
+
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index e98e055..8b8a7c1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -596,4 +596,6 @@ struct ccsr_cci400 {
 #define SCR0_CLIENTPD_MASK		0x00000001
 #define SCR0_USFCFG_MASK		0x00000400
 
+uint get_svr(void);
+
 #endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357..e48bbaf 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -319,4 +319,7 @@ struct ccsr_reset {
 	u32 ip_rev1;			/* 0xbf8 */
 	u32 ip_rev2;			/* 0xbfc */
 };
+
+uint get_svr(void);
+
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 02ecc62..2cb6c54 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -53,6 +53,8 @@ struct cpu_type {
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
+#define IS_SVR_REV(svr, maj, min) \
+		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
-- 
cgit v0.10.2


From bf655775f5f97122605c96c0ecd41158c1147785 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 13 Jun 2016 09:58:33 +0530
Subject: usb: xhci: fsl: code cleanup for device tree fixup for fsl usb
 controllers

Performs code cleanup for device tree fixup for fsl usb controllers by
making functions to handle these similar errata checking code.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>

diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 6f31932..1523f98 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -19,10 +19,16 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 #endif
 
+/* USB Controllers */
+#define FSL_USB2_MPH	"fsl-usb2-mph"
+#define FSL_USB2_DR	"fsl-usb2-dr"
+#define CHIPIDEA_USB2	"chipidea,usb2"
+#define SNPS_DWC3	"snps,dwc3"
+
 static const char * const compat_usb_fsl[] = {
-	"fsl-usb2-mph",
-	"fsl-usb2-dr",
-	"snps,dwc3",
+	FSL_USB2_MPH,
+	FSL_USB2_DR,
+	SNPS_DWC3,
 	NULL
 };
 
@@ -80,16 +86,24 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 }
 
 static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
-				 int start_offset)
+				 const char *controller_type, int start_offset)
 {
 	int node_offset, err;
 	const char *node_type = NULL;
+	const char *node_name = NULL;
 
 	err = fdt_usb_get_node_type(blob, start_offset,
 				    &node_offset, &node_type);
 	if (err < 0)
 		return err;
 
+	if (!strcmp(node_type, FSL_USB2_MPH) || !strcmp(node_type, FSL_USB2_DR))
+		node_name = CHIPIDEA_USB2;
+	else
+		node_name = node_type;
+	if (strcmp(node_name, controller_type))
+		return err;
+
 	err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
 	if (err < 0) {
 		printf("ERROR: could not set %s for %s: %s.\n",
@@ -99,6 +113,23 @@ static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
 	return node_offset;
 }
 
+static int fdt_fixup_erratum(int *usb_erratum_off, void *blob,
+			     const char *controller_type, char *str,
+			     bool (*has_erratum)(void))
+{
+	char buf[32] = {0};
+
+	snprintf(buf, sizeof(buf), "fsl,usb-erratum-%s", str);
+	if (!has_erratum())
+		return -EINVAL;
+	*usb_erratum_off = fdt_fixup_usb_erratum(blob, buf, controller_type,
+						 *usb_erratum_off);
+	if (*usb_erratum_off < 0)
+		return -ENOSPC;
+	debug("Adding USB erratum %s\n", str);
+	return 0;
+}
+
 void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
 	static const char * const modes[] = { "host", "peripheral", "otg" };
@@ -111,6 +142,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	int usb_phy_off = -1;
 	char str[5];
 	int i, j;
+	int ret;
 
 	for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
 		const char *dr_mode_type = NULL;
@@ -164,39 +196,25 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 		if (usb_phy_off < 0)
 			return;
 
-		if (has_erratum_a006261()) {
-			usb_erratum_a006261_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a006261",
-						    usb_erratum_a006261_off);
-			if (usb_erratum_a006261_off < 0)
-				return;
-		}
-
-		if (has_erratum_a007075()) {
-			usb_erratum_a007075_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a007075",
-						    usb_erratum_a007075_off);
-			if (usb_erratum_a007075_off < 0)
-				return;
-		}
-
-		if (has_erratum_a007792()) {
-			usb_erratum_a007792_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a007792",
-						    usb_erratum_a007792_off);
-			if (usb_erratum_a007792_off < 0)
-				return;
-		}
-		if (has_erratum_a005697()) {
-			usb_erratum_a005697_off =  fdt_fixup_usb_erratum
-						   (blob,
-						    "fsl,usb-erratum-a005697",
-						    usb_erratum_a005697_off);
-			if (usb_erratum_a005697_off < 0)
-				return;
-		}
+		ret = fdt_fixup_erratum(&usb_erratum_a006261_off, blob,
+					CHIPIDEA_USB2, "a006261",
+					has_erratum_a006261);
+		if (ret == -ENOSPC)
+			return;
+		ret = fdt_fixup_erratum(&usb_erratum_a007075_off, blob,
+					CHIPIDEA_USB2, "a007075",
+					has_erratum_a007075);
+		if (ret == -ENOSPC)
+			return;
+		ret = fdt_fixup_erratum(&usb_erratum_a007792_off, blob,
+					CHIPIDEA_USB2, "a007792",
+					has_erratum_a007792);
+		if (ret == -ENOSPC)
+			return;
+		ret = fdt_fixup_erratum(&usb_erratum_a005697_off, blob,
+					CHIPIDEA_USB2, "a005697",
+					has_erratum_a005697);
+		if (ret == -ENOSPC)
+			return;
 	}
 }
-- 
cgit v0.10.2


From 92623672f9d3f1b4ea12ae1e2bcc0ad9fde5d2cb Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 13 Jun 2016 09:58:34 +0530
Subject: fsl: usb: make errata function common for PPC and ARM

This patch does the following things:
1. Makes the errata checking code common for PPC and ARM
2. Moves all these static inline functions into a dedicated C file

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index 2f46d38..aee7e32 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -4,5 +4,5 @@
 #
 
 obj-$(CONFIG_DM_USB) += common.o
-obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
-obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
+obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o
+obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o fsl-errata.o
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 1523f98..930ca1d 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -12,6 +12,7 @@
 #include <usb.h>
 #include <asm/io.h>
 #include <hwconfig.h>
+#include <fsl_errata.h>
 #include <fsl_usb.h>
 #include <fdt_support.h>
 
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
new file mode 100644
index 0000000..95918fc
--- /dev/null
+++ b/drivers/usb/common/fsl-errata.c
@@ -0,0 +1,178 @@
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_errata.h>
+#include<fsl_usb.h>
+
+/* USB Erratum Checking code */
+#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
+bool has_dual_phy(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_PPC
+	case SVR_T1023:
+	case SVR_T1024:
+	case SVR_T1013:
+	case SVR_T1014:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T1040:
+	case SVR_T1042:
+	case SVR_T1020:
+	case SVR_T1022:
+	case SVR_T2080:
+	case SVR_T2081:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+	case SVR_T4240:
+	case SVR_T4160:
+	case SVR_T4080:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+#endif
+	}
+
+	return false;
+}
+
+bool has_erratum_a006261(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_PPC
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P2041:
+	case SVR_P2040:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P3041:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) ||
+			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P5010:
+	case SVR_P5020:
+	case SVR_P5021:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T4240:
+	case SVR_T4160:
+	case SVR_T4080:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T1040:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T2080:
+	case SVR_T2081:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P5040:
+		return IS_SVR_REV(svr, 1, 0);
+#endif
+	}
+
+	return false;
+}
+
+bool has_erratum_a007075(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_PPC
+	case SVR_B4860:
+	case SVR_B4420:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P4080:
+		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+#endif
+	}
+	return false;
+}
+
+bool has_erratum_a007798(void)
+{
+#ifdef CONFIG_PPC
+	return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+		IS_SVR_REV(get_svr(), 2, 0);
+#endif
+	return false;
+}
+
+bool has_erratum_a007792(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_PPC
+	case SVR_T4240:
+	case SVR_T4160:
+	case SVR_T4080:
+		return IS_SVR_REV(svr, 2, 0);
+	case SVR_T1024:
+	case SVR_T1023:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T1040:
+	case SVR_T1042:
+	case SVR_T1020:
+	case SVR_T1022:
+	case SVR_T2080:
+	case SVR_T2081:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+	}
+	return false;
+}
+
+bool has_erratum_a005697(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_PPC
+	case SVR_9131:
+	case SVR_9132:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+	}
+	return false;
+}
+
+bool has_erratum_a004477(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_PPC
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P1022:
+	case SVR_9131:
+	case SVR_9132:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+	case SVR_P2020:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
+			IS_SVR_REV(svr, 2, 1);
+	case SVR_B4860:
+	case SVR_B4420:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P4080:
+		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+#endif
+	}
+
+	return false;
+}
+
+#endif
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 187e384..d183349 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -86,188 +86,13 @@ struct ccsr_usb_phy {
 #endif
 
 /* USB Erratum Checking code */
-#ifdef CONFIG_PPC
-static inline bool has_dual_phy(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_T1023:
-	case SVR_T1024:
-	case SVR_T1013:
-	case SVR_T1014:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_T1040:
-	case SVR_T1042:
-	case SVR_T1020:
-	case SVR_T1022:
-	case SVR_T2080:
-	case SVR_T2081:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
-	case SVR_T4240:
-	case SVR_T4160:
-	case SVR_T4080:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	}
-
-	return false;
-}
-
-static inline bool has_erratum_a006261(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P2041:
-	case SVR_P2040:
-		return IS_SVR_REV(svr, 1, 0) ||
-			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
-	case SVR_P3041:
-		return IS_SVR_REV(svr, 1, 0) ||
-			IS_SVR_REV(svr, 1, 1) ||
-			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
-	case SVR_P5010:
-	case SVR_P5020:
-	case SVR_P5021:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_T4240:
-	case SVR_T4160:
-	case SVR_T4080:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_T1040:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_T2080:
-	case SVR_T2081:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_P5040:
-		return IS_SVR_REV(svr, 1, 0);
-	}
-
-	return false;
-}
-
-static inline bool has_erratum_a007075(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_B4860:
-	case SVR_B4420:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_P4080:
-		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
-	}
-	return false;
-}
-
-static inline bool has_erratum_a007798(void)
-{
-	return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
-		IS_SVR_REV(get_svr(), 2, 0);
-}
-
-static inline bool has_erratum_a007792(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_T4240:
-	case SVR_T4160:
-	case SVR_T4080:
-		return IS_SVR_REV(svr, 2, 0);
-	case SVR_T1024:
-	case SVR_T1023:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_T1040:
-	case SVR_T1042:
-	case SVR_T1020:
-	case SVR_T1022:
-	case SVR_T2080:
-	case SVR_T2081:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
-	}
-	return false;
-}
-
-static inline bool has_erratum_a005697(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_9131:
-	case SVR_9132:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
-	}
-	return false;
-}
-
-static inline bool has_erratum_a004477(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P1022:
-	case SVR_9131:
-	case SVR_9132:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
-	case SVR_P2020:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
-			IS_SVR_REV(svr, 2, 1);
-	case SVR_B4860:
-	case SVR_B4420:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P4080:
-		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
-	}
-
-	return false;
-}
-#else
-static inline bool has_dual_phy(void)
-{
-	return false;
-}
-
-static inline bool has_erratum_a006261(void)
-{
-	return false;
-}
-
-static inline bool has_erratum_a007075(void)
-{
-	return false;
-}
-
-static inline bool has_erratum_a007798(void)
-{
-	return false;
-}
-
-static inline bool has_erratum_a007792(void)
-{
-	return false;
-}
-
-static inline bool has_erratum_a005697(void)
-{
-	return false;
-}
-
-static inline bool has_erratum_a004477(void)
-{
-	return false;
-}
+#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
+bool has_dual_phy(void);
+bool has_erratum_a006261(void);
+bool has_erratum_a007075(void);
+bool has_erratum_a007798(void);
+bool has_erratum_a007792(void);
+bool has_erratum_a005697(void);
+bool has_erratum_a004477(void);
 #endif
 #endif /*_ASM_FSL_USB_H_ */
-- 
cgit v0.10.2


From 32fbd46f38ed183ae92aabc0a2abd7847bc3363e Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 13 Jun 2016 09:58:35 +0530
Subject: armv8/ls2080: Remove workaround for erratum A008751

This errata a008751 is applied on Soc specific file currently.This will be
moved to a file where all the errata implementation will take place for usb
for fsl. This patch removes the errata workaround from soc specific file
for LS2080.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index dd633f3..d8ec426 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -124,15 +124,6 @@ void erratum_a009635(void)
 }
 #endif	/* CONFIG_SYS_FSL_ERRATUM_A009635 */
 
-static void erratum_a008751(void)
-{
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
-	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
-
-	writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
-#endif
-}
-
 static void erratum_rcw_src(void)
 {
 #if defined(CONFIG_SPL)
@@ -189,7 +180,6 @@ void bypass_smmu(void)
 }
 void fsl_lsch3_early_init_f(void)
 {
-	erratum_a008751();
 	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
 	erratum_a009203();
-- 
cgit v0.10.2


From ef53b8c4ce2919d6685d2dc0c51a91a180433ff0 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 13 Jun 2016 09:58:36 +0530
Subject: usb: xhci: fsl: Add workaround for USB erratum A008751

This patch is doing the following:
1. Implementing the errata for LS2080.
2. Adding fixup for fdt for LS2080.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e48bbaf..9b60bd3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,6 +139,7 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM1CR_INIT		0x27672b2a
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
 #define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 897793d..479f689 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -298,6 +298,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
+	fdt_fixup_dr_usb(blob, bd);
+
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
 	err = fsl_mc_ldpaa_exit(bd);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 52e5e3f..a65cd4a 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -281,6 +281,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
+	fdt_fixup_dr_usb(blob, bd);
+
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
 	err = fsl_mc_ldpaa_exit(bd);
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 930ca1d..9c48852 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -139,6 +139,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	int usb_erratum_a007075_off = -1;
 	int usb_erratum_a007792_off = -1;
 	int usb_erratum_a005697_off = -1;
+	int usb_erratum_a008751_off = -1;
 	int usb_mode_off = -1;
 	int usb_phy_off = -1;
 	char str[5];
@@ -217,5 +218,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 					has_erratum_a005697);
 		if (ret == -ENOSPC)
 			return;
+		ret = fdt_fixup_erratum(&usb_erratum_a008751_off, blob,
+					SNPS_DWC3, "a008751",
+					has_erratum_a008751);
+		if (ret == -ENOSPC)
+			return;
+
 	}
 }
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index 95918fc..ebe60a8 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -175,4 +175,19 @@ bool has_erratum_a004477(void)
 	return false;
 }
 
+bool has_erratum_a008751(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+#ifdef CONFIG_ARM64
+	case SVR_LS2080:
+	case SVR_LS2085:
+		return IS_SVR_REV(svr, 1, 0);
+#endif
+	}
+	return false;
+}
+
 #endif
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 05f09d7..c12a189 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -15,6 +15,8 @@
 #include <linux/usb/xhci-fsl.h>
 #include <linux/usb/dwc3.h>
 #include "xhci.h"
+#include <fsl_errata.h>
+#include <fsl_usb.h>
 
 /* Declare global data pointer */
 DECLARE_GLOBAL_DATA_PTR;
@@ -27,6 +29,26 @@ __weak int __board_usb_init(int index, enum usb_init_type init)
 	return 0;
 }
 
+static int erratum_a008751(void)
+{
+#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
+	return 0;
+#endif
+	return 1;
+}
+
+static void fsl_apply_xhci_errata(void)
+{
+	int ret;
+	if (has_erratum_a008751()) {
+		ret = erratum_a008751();
+		if (ret != 0)
+			puts("Failed to apply erratum a008751\n");
+	}
+}
+
 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 {
 	int ret = 0;
@@ -69,6 +91,8 @@ int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
 		return ret;
 	}
 
+	fsl_apply_xhci_errata();
+
 	ret = fsl_xhci_core_init(ctx);
 	if (ret < 0) {
 		puts("Failed to initialize xhci\n");
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index d183349..fc72fb9 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -94,5 +94,6 @@ bool has_erratum_a007798(void);
 bool has_erratum_a007792(void);
 bool has_erratum_a005697(void);
 bool has_erratum_a004477(void);
+bool has_erratum_a008751(void);
 #endif
 #endif /*_ASM_FSL_USB_H_ */
-- 
cgit v0.10.2


From 1cb075c6c6ce1a46c3423e63013686e74457275c Mon Sep 17 00:00:00 2001
From: Eran Matityahu <eran.m@variscite.com>
Date: Tue, 7 Jun 2016 10:38:37 +0300
Subject: splash_source: add support for ubifs formatted nand

Add support for loading splash image from NAND Flash formatted with a (UBI) filesystem.

Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/common/splash_source.c b/common/splash_source.c
index f86a78a..914f12f 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -120,6 +120,12 @@ static int splash_select_fs_dev(struct splash_location *location)
 	case SPLASH_STORAGE_SATA:
 		res = fs_set_blk_dev("sata", location->devpart, FS_TYPE_ANY);
 		break;
+	case SPLASH_STORAGE_NAND:
+		if (location->ubivol != NULL)
+			res = fs_set_blk_dev("ubi", NULL, FS_TYPE_UBIFS);
+		else
+			res = -ENODEV;
+		break;
 	default:
 		printf("Error: unsupported location storage.\n");
 		return -ENODEV;
@@ -163,6 +169,41 @@ static inline int splash_init_sata(void)
 }
 #endif
 
+#ifdef CONFIG_CMD_UBIFS
+static int splash_mount_ubifs(struct splash_location *location)
+{
+	int res;
+	char cmd[32];
+
+	sprintf(cmd, "ubi part %s", location->mtdpart);
+	res = run_command(cmd, 0);
+	if (res)
+		return res;
+
+	sprintf(cmd, "ubifsmount %s", location->ubivol);
+	res = run_command(cmd, 0);
+
+	return res;
+}
+
+static inline int splash_umount_ubifs(void)
+{
+	return run_command("ubifsumount", 0);
+}
+#else
+static inline int splash_mount_ubifs(struct splash_location *location)
+{
+	printf("Cannot load splash image: no UBIFS support\n");
+	return -ENOSYS;
+}
+
+static inline int splash_umount_ubifs(void)
+{
+	printf("Cannot unmount UBIFS: no UBIFS support\n");
+	return -ENOSYS;
+}
+#endif
+
 #define SPLASH_SOURCE_DEFAULT_FILE_NAME		"splash.bmp"
 
 static int splash_load_fs(struct splash_location *location, u32 bmp_load_addr)
@@ -181,26 +222,36 @@ static int splash_load_fs(struct splash_location *location, u32 bmp_load_addr)
 	if (location->storage == SPLASH_STORAGE_SATA)
 		res = splash_init_sata();
 
+	if (location->ubivol != NULL)
+		res = splash_mount_ubifs(location);
+
 	if (res)
 		return res;
 
 	res = splash_select_fs_dev(location);
 	if (res)
-		return res;
+		goto out;
 
 	res = fs_size(splash_file, &bmp_size);
 	if (res) {
 		printf("Error (%d): cannot determine file size\n", res);
-		return res;
+		goto out;
 	}
 
 	if (bmp_load_addr + bmp_size >= gd->start_addr_sp) {
 		printf("Error: splashimage address too high. Data overwrites U-Boot and/or placed beyond DRAM boundaries.\n");
-		return -EFAULT;
+		res = -EFAULT;
+		goto out;
 	}
 
 	splash_select_fs_dev(location);
-	return fs_read(splash_file, bmp_load_addr, 0, 0, NULL);
+	res = fs_read(splash_file, bmp_load_addr, 0, 0, NULL);
+
+out:
+	if (location->ubivol != NULL)
+		splash_umount_ubifs();
+
+	return res;
 }
 
 /**
diff --git a/include/splash.h b/include/splash.h
index f0755ca..25df1cf 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -43,6 +43,8 @@ struct splash_location {
 	enum splash_flags flags;
 	u32 offset;	/* offset from start of storage */
 	char *devpart;  /* Use the load command dev:part conventions */
+	char *mtdpart;	/* MTD partition for ubi part */
+	char *ubivol;	/* UBI volume-name for ubifsmount */
 };
 
 int splash_source_load(struct splash_location *locations, uint size);
-- 
cgit v0.10.2


From 5e4e87418e0f0e62854fe6c38736e2ee771ec3a7 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 13 Jun 2016 09:00:30 -0400
Subject: common/Kconfig: Change the default BOOTDELAY to 2

The value of 0 is fairly uncommon while 2 is one of the more common ones
so switch.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/common/Kconfig b/common/Kconfig
index 4d17b10..e691145 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -99,7 +99,7 @@ endmenu
 
 config BOOTDELAY
 	int "delay in seconds before automatically booting"
-	default 0
+	default 2
 	help
 	  Delay before automatically running bootcmd;
 	  set to -1 to disable autoboot.
-- 
cgit v0.10.2


From 7802ce910ba17a962d90b60b5e998e40d5a08067 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 13 Jun 2016 09:45:14 -0400
Subject: configs: Re-sync BOOTDELAY changes

With updated moveconfig.py and an better default, re-generate
the migration of BOOTDELAY to the defconfig.

Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 378f7a1..8cb7ac7 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_EMR1=4
 CONFIG_SYS_CLK_FREQ=912000000
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index f121cab..e4168fa 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -14,6 +14,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
-CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 57609b3..6430606 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -17,6 +17,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
 # CONFIG_CMD_FPGA is not set
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
-CONFIG_USB_EHCI_HCD=y
diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig
index 726e08e..bc2ddca 100644
--- a/configs/C29XPCIE_NAND_defconfig
+++ b/configs/C29XPCIE_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
index 032be47..99b437a 100644
--- a/configs/C29XPCIE_NOR_SECBOOT_defconfig
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
index a450c60..491fba2 100644
--- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig
index c50234c..f2d9772 100644
--- a/configs/C29XPCIE_SPIFLASH_defconfig
+++ b/configs/C29XPCIE_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig
index c16559d..9ccf0e8 100644
--- a/configs/C29XPCIE_defconfig
+++ b/configs/C29XPCIE_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 19ae280..3e8c0a1 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -13,10 +13,10 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
-CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
 CONFIG_G_DNL_VENDOR_NUM=0x1f3a
 CONFIG_G_DNL_PRODUCT_NUM=0x1010
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 4b9abea..3257aae 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 97bdcd6..c884115 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index f2c6fe7..725652d 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_A83T=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
 CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 77e496c..fef3685 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB09"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 94aab9d..9d8d325 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_USB1_VBUS_PIN=""
 CONFIG_USB2_VBUS_PIN=""
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 8cee863..5b0c65a 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5208EVBE=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index ffb709c..eff91ec 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5235EVB=y
 CONFIG_SYS_TEXT_BASE=0xFFC00000
 CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
+CONFIG_BOOTDELAY=1
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_I2C=y
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 0885727..28c7f20 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5235EVB=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index b9a4fde..9a5d36a 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M53017EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index dc90334..f09af5e 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5329EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index 2850e3a..9954afa 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5329EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 9b63e54..6f89dd2 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5373EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
index 5f354a8..25ee121 100644
--- a/configs/M54451EVB_defconfig
+++ b/configs/M54451EVB_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54451EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
index c43c49d..af0de25 100644
--- a/configs/M54451EVB_stmicro_defconfig
+++ b/configs/M54451EVB_stmicro_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54451EVB=y
 CONFIG_SYS_TEXT_BASE=0x47e00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
+CONFIG_BOOTDELAY=1
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
index 8e1bcbf..a59421f 100644
--- a/configs/M54455EVB_a66_defconfig
+++ b/configs/M54455EVB_a66_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54455EVB=y
 CONFIG_SYS_TEXT_BASE=0x04000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
+CONFIG_BOOTDELAY=1
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
index 705b5ae..89150a7 100644
--- a/configs/M54455EVB_defconfig
+++ b/configs/M54455EVB_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54455EVB=y
 CONFIG_SYS_TEXT_BASE=0x04000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
index a1dd018..862003d 100644
--- a/configs/M54455EVB_i66_defconfig
+++ b/configs/M54455EVB_i66_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54455EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
+CONFIG_BOOTDELAY=1
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
index 3a17303..b568e2a 100644
--- a/configs/M54455EVB_intel_defconfig
+++ b/configs/M54455EVB_intel_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54455EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
+CONFIG_BOOTDELAY=1
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
index 52441d4..a1ce1b2 100644
--- a/configs/M54455EVB_stm33_defconfig
+++ b/configs/M54455EVB_stm33_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M54455EVB=y
 CONFIG_SYS_TEXT_BASE=0x4FE00000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
+CONFIG_BOOTDELAY=1
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_SF=y
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
index 3bad5d0..0e3e180 100644
--- a/configs/M5475AFE_defconfig
+++ b/configs/M5475AFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
index d3ff58b..5c2d31b 100644
--- a/configs/M5475BFE_defconfig
+++ b/configs/M5475BFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
index 670bda5..58d354b 100644
--- a/configs/M5475CFE_defconfig
+++ b/configs/M5475CFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
index 4a49e90..13cbd24 100644
--- a/configs/M5475DFE_defconfig
+++ b/configs/M5475DFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
index 8e90823..f82ef5c 100644
--- a/configs/M5475EFE_defconfig
+++ b/configs/M5475EFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
index e26b1fe..08d5ff3 100644
--- a/configs/M5475FFE_defconfig
+++ b/configs/M5475FFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
index e79d991..6fb7f63 100644
--- a/configs/M5475GFE_defconfig
+++ b/configs/M5475GFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5475EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
index abdf504..36e95e8 100644
--- a/configs/M5485AFE_defconfig
+++ b/configs/M5485AFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
index 0708f18..2dccf22 100644
--- a/configs/M5485BFE_defconfig
+++ b/configs/M5485BFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
index de2c9f1..e40efb0 100644
--- a/configs/M5485CFE_defconfig
+++ b/configs/M5485CFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
index cc93f81..692cd40 100644
--- a/configs/M5485DFE_defconfig
+++ b/configs/M5485DFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
index d084d58..ebd1a55 100644
--- a/configs/M5485EFE_defconfig
+++ b/configs/M5485EFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
index 0e1b285..18f26f1 100644
--- a/configs/M5485FFE_defconfig
+++ b/configs/M5485FFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
index 66e5316..87fe150 100644
--- a/configs/M5485GFE_defconfig
+++ b/configs/M5485GFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
index 9ec6c45..d67c01f 100644
--- a/configs/M5485HFE_defconfig
+++ b/configs/M5485HFE_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M5485EVB=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index d230a68..cef9794 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 64f2c74..f076e30 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 198fda9..53e023a 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=360
 CONFIG_DRAM_ZQ=123
 CONFIG_SYS_CLK_FREQ=1008000000
 CONFIG_MMC0_CD_PIN="PH18"
+# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index f96757e..53f9bfe 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig
index bdf91d2..3505e7d 100644
--- a/configs/P1023RDB_defconfig
+++ b/configs/P1023RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 3a1e5a4..696024c 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -4,9 +4,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -29,7 +27,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
@@ -45,5 +42,10 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
 CONFIG_RSA=y
+CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index f230671..76a004e 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig
index 3fbc07b..99fc555 100644
--- a/configs/am335x_evm_norboot_defconfig
+++ b/configs/am335x_evm_norboot_defconfig
@@ -35,3 +35,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 65d88d8..d5aa3a2 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index eee5e9b..cba5e84 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 2c7091b..c83311f 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index ffda4d2..bfb56b2 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 54558b6..d16c5f0 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
index a415ab4..b9bc355 100644
--- a/configs/am335x_shc_prompt_defconfig
+++ b/configs/am335x_shc_prompt_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=5
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
 CONFIG_AUTOBOOT_DELAY_STR="shc"
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 944256f..b0e8eff 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
index 2767012..b0e8eff 100644
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
index 95b28fb..3cd39eb 100644
--- a/configs/am437x_hs_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -2,12 +2,13 @@ CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+# Device tree file can be same on HS evm
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 9cdae19..3b958d7 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -41,3 +41,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 7b345ad..5264332 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -41,3 +41,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 6b53eba..34c875e 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,16 +1,14 @@
 CONFIG_ARM=y
 CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -33,7 +31,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -54,4 +51,9 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
+CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 8526526..c29a05a 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -7,9 +7,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index ce377cb..a100079 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -8,9 +8,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index f169fd3..0361418 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_AMCORE=y
 CONFIG_SYS_TEXT_BASE=0xffc00000
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="amcore $ "
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 17e8595..40a65d2 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -38,3 +38,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index 0df8ac0..a6bac0e 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_APX4DEVKIT=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 0f68eba..18d6a25 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS2=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 2457513..aeea87f 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS2B=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index ad2bf08..a55ce6a 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_ARISTAINETOS=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index 9888c7e..1e41628 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -1,5 +1,6 @@
 CONFIG_M68K=y
 CONFIG_TARGET_ASTRO_MCF5373L=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="URMEL > "
 CONFIG_CMD_I2C=y
diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig
index 685d5ac..52dbefd 100644
--- a/configs/atngw100_defconfig
+++ b/configs/atngw100_defconfig
@@ -1,5 +1,6 @@
 CONFIG_AVR32=y
 CONFIG_TARGET_ATNGW100=y
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig
index c392df7..bfceedb 100644
--- a/configs/atngw100mkii_defconfig
+++ b/configs/atngw100mkii_defconfig
@@ -1,5 +1,6 @@
 CONFIG_AVR32=y
 CONFIG_TARGET_ATNGW100MKII=y
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig
index bd37d2e..df57568 100644
--- a/configs/atstk1002_defconfig
+++ b/configs/atstk1002_defconfig
@@ -1,5 +1,6 @@
 CONFIG_AVR32=y
 CONFIG_TARGET_ATSTK1002=y
+CONFIG_BOOTDELAY=1
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 6da4b69..1cfb380 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=384
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
index 3e61a3f..ad894a2 100644
--- a/configs/bct-brettl2_defconfig
+++ b/configs/bct-brettl2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BCT_BRETTL2=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 8557c02..b9323c2 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -44,3 +44,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
index 0b6f517..e17c969 100644
--- a/configs/bf518f-ezbrd_defconfig
+++ b/configs/bf518f-ezbrd_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF518F_EZBRD=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index ea4f8e4..8e9fc1a 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF526_EZBRD=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
index b5f5f5d..45f4149 100644
--- a/configs/bf527-ad7160-eval_defconfig
+++ b/configs/bf527-ad7160-eval_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_AD7160_EVAL=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index faac28d..d980392 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_EZKIT=y
 CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index d69b146..4be8ed7 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_EZKIT=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
index 5137293..fec1307 100644
--- a/configs/bf527-sdp_defconfig
+++ b/configs/bf527-sdp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF527_SDP=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
index 6b2395a..853a5d4 100644
--- a/configs/bf533-ezkit_defconfig
+++ b/configs/bf533-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_EZKIT=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
index ef23ea7..e0f5de9 100644
--- a/configs/bf533-stamp_defconfig
+++ b/configs/bf533-stamp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF533_STAMP=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig
index cb01bc1..bbc171d 100644
--- a/configs/bf537-pnav_defconfig
+++ b/configs/bf537-pnav_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_PNAV=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
index 15e5254..d189ad4 100644
--- a/configs/bf537-stamp_defconfig
+++ b/configs/bf537-stamp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_STAMP=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
index 2c71498..8507b40 100644
--- a/configs/bf538f-ezkit_defconfig
+++ b/configs/bf538f-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF538F_EZKIT=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index e4fa136..42f1211 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF548_EZKIT=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
index 3ecdd9f..6428d18 100644
--- a/configs/bf561-acvilon_defconfig
+++ b/configs/bf561-acvilon_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_ACVILON=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="Acvilon> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
index 1e99b4b..f8206b8 100644
--- a/configs/bf561-ezkit_defconfig
+++ b/configs/bf561-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF561_EZKIT=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index 44ed671..bb5db5c 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 861bdcf..39cc222 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -38,3 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="BAV335x U-Boot SPL"
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index a8775f3..5257312 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_CAIRO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Cairo # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig
index 5f6bc5c..505ab37 100644
--- a/configs/calimain_defconfig
+++ b/configs/calimain_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_CALIMAIN=y
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Calimain > "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index ee8e793..979b693 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -36,3 +36,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 68cf2ac..f263165 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_CGTQMX6EVAL=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 6bebcee..d5bc515 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -73,6 +73,7 @@ CONFIG_ROCKCHIP_SPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
index 072483a..773edfb 100644
--- a/configs/cm-bf527_defconfig
+++ b/configs/cm-bf527_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF527=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
index 1fb91b2..6fa231d 100644
--- a/configs/cm-bf533_defconfig
+++ b/configs/cm-bf533_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF533=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
index c65a703..16f129b 100644
--- a/configs/cm-bf537e_defconfig
+++ b/configs/cm-bf537e_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537E=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
index b030a27..68e8659 100644
--- a/configs/cm-bf537u_defconfig
+++ b/configs/cm-bf537u_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF537U=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
index 1355dd4..0589803 100644
--- a/configs/cm-bf548_defconfig
+++ b/configs/cm-bf548_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF548=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
index b6e711e..5a32f56 100644
--- a/configs/cm-bf561_defconfig
+++ b/configs/cm-bf561_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_CM_BF561=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 4193764..f01a6dd 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CM_FX6=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-FX6 # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index a0c40fe..a3b2a3c 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -44,3 +44,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index c7f6982..c920b39 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -36,3 +36,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index df17f2e..986cec4 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SPI=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Colibri VFxx # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
index be8174b..b6f14db 100644
--- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
 CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
+CONFIG_BOOTDELAY=0
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig
index 74b5266..2c45aff 100644
--- a/configs/controlcenterd_TRAILBLAZER_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
 CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
+CONFIG_BOOTDELAY=0
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 980e153..75eaad8 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -42,3 +42,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig
index 996e2f7..c3fa26f 100644
--- a/configs/dbau1000_defconfig
+++ b/configs/dbau1000_defconfig
@@ -12,3 +12,4 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig
index 2b3ccd8..5e2c9bd 100644
--- a/configs/dbau1100_defconfig
+++ b/configs/dbau1100_defconfig
@@ -12,3 +12,4 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig
index 7459c63..10fe8aa 100644
--- a/configs/dbau1500_defconfig
+++ b/configs/dbau1500_defconfig
@@ -12,3 +12,4 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig
index 964d8a8..7f1bdf4 100644
--- a/configs/dbau1550_defconfig
+++ b/configs/dbau1550_defconfig
@@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig
index dfe0102..6cd0161 100644
--- a/configs/dbau1550_el_defconfig
+++ b/configs/dbau1550_el_defconfig
@@ -10,3 +10,4 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index eca6e86..0795458 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_DM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig
index 67fda76..0e708cd 100644
--- a/configs/digsy_mtc_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig
index e05583f..977d3b2 100644
--- a/configs/digsy_mtc_defconfig
+++ b/configs/digsy_mtc_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
index 424c214..9c8470d 100644
--- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig
+++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig
index 4579ab6..c1dca2e 100644
--- a/configs/digsy_mtc_rev5_defconfig
+++ b/configs/digsy_mtc_rev5_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_DIGSY_MTC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 1237a73..756af63 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -9,11 +9,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
@@ -34,7 +32,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -56,4 +53,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 0724916..6933ab5 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DRA7XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_SPI=y
@@ -11,11 +11,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
@@ -36,7 +34,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -58,4 +55,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index ba50ce0..f8155b2 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/espt_defconfig b/configs/espt_defconfig
index 78e319c..81425bd 100644
--- a/configs/espt_defconfig
+++ b/configs/espt_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_ESPT=y
+CONFIG_BOOTDELAY=-1
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 3f77981..9894fff 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -39,5 +39,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index a64f6de..4af9120 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -65,6 +65,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig
index 0ef418d..8577167 100644
--- a/configs/ge_b450v3_defconfig
+++ b/configs/ge_b450v3_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B450V3=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -8,18 +10,16 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_FPGA=n
+# CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_NET=n
-CONFIG_CMD_NFS=n
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
-CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
-CONFIG_EFI_LOADER=n
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig
index 2af4b11..c5f391e 100644
--- a/configs/ge_b650v3_defconfig
+++ b/configs/ge_b650v3_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B650V3=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -8,18 +10,16 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_FPGA=n
+# CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_NET=n
-CONFIG_CMD_NFS=n
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
-CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
-CONFIG_EFI_LOADER=n
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig
index 9e0c5eb..2c5aa05 100644
--- a/configs/ge_b850v3_defconfig
+++ b/configs/ge_b850v3_defconfig
@@ -1,6 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_GE_B850V3=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -8,18 +10,16 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_FPGA=n
+# CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_NET=n
-CONFIG_CMD_NFS=n
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=n
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_OF_LIBFDT=y
-CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
-CONFIG_EFI_LOADER=n
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig
index 25b9c4e..26b8a1f 100644
--- a/configs/grasshopper_defconfig
+++ b/configs/grasshopper_defconfig
@@ -1,5 +1,6 @@
 CONFIG_AVR32=y
 CONFIG_TARGET_GRASSHOPPER=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index 9959ef4..e9449fa 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Ventana > "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index c4bd2c5..e04d96b 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_A83T=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB0_VBUS_PIN="PL5"
 CONFIG_USB1_VBUS_PIN="PL6"
 CONFIG_AXP_GPIO=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 16b0297..129a72b 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -35,3 +35,4 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index ba0a37e..d150dd3 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
@@ -14,3 +13,5 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index ebf103a..7ec54a7 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_MMC0_CD_PIN="PH1"
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 2cadf17..5e68769 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=127
 CONFIG_DRAM_EMR1=4
diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig
index 5ce6abc..036a92f 100644
--- a/configs/ibf-dsp561_defconfig
+++ b/configs/ibf-dsp561_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_IBF_DSP561=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 794b85e..b0487ef 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index e84ed57..a8b32cb 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index 2444a38..0b03e16 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index a2489c4..153450f 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig
index 506a8f8..d8586a4 100644
--- a/configs/inka4x0_defconfig
+++ b/configs/inka4x0_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_INKA4X0=y
+CONFIG_BOOTDELAY=1
 CONFIG_LOOPW=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
index b944b07..277988c 100644
--- a/configs/ip04_defconfig
+++ b/configs/ip04_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_IP04=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index a9b9084..9cb8b1d 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=312
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index f672aa2..7b04a0c 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -44,3 +44,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
index 30558e7..790292e 100644
--- a/configs/kwb_defconfig
+++ b/configs/kwb_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_KWB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index bed9df8..0ff6c6b 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -34,5 +34,6 @@ CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
 CONFIG_RAM=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index d080f05..8161f73 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_LEGOEV3=y
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index dc16492..ea3fd1e 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -8,16 +11,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_DM=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
@@ -27,13 +23,15 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
-CONFIG_CMD_SF=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
-CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 4dd4dce..02eb704 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -34,3 +34,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 2ef713f..a66cd3b 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=-1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
 CONFIG_CMD_ASKENV=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 63b6a76..d38bc7f 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_USB2_VBUS_PIN="PH12"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index c366411..de1b73f 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/ms7750se_defconfig b/configs/ms7750se_defconfig
index fb7932a..6a53642 100644
--- a/configs/ms7750se_defconfig
+++ b/configs/ms7750se_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MS7750SE=y
+CONFIG_BOOTDELAY=-1
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index b1bd634..5638c52 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX23EVK=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index 1c1afd8..b4afb05 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX25PDK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index 8738f59..d43bb53 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index de8a297..0a7564a 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 83ff3a3..65d4a6b 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index 906d3da..d5b001c 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_MX28EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index e1bb561..901f992 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX31PDK=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_SPI=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index e6cc065..8addf85 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX35PDK=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 0b3b232..2b9acf5 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX51EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index da9aa4f..71b9ce4 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53LOCO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index eb30bf6..cd79341 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index dc52b9b..d4374f6 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
index de925d9..4e94603 100644
--- a/configs/mx6dlsabreauto_defconfig
+++ b/configs/mx6dlsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 2fcc088..f7b3e13 100644
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 391da69..79fa471 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index af3b9b0..467b006 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QARM2=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
index 6212540..8ef6809 100644
--- a/configs/mx6qpsabreauto_defconfig
+++ b/configs/mx6qpsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
index 250411d..0890257 100644
--- a/configs/mx6qsabreauto_defconfig
+++ b/configs/mx6qsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6QSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 66575b8..fa6139a 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index 7456cf3..d6fa6a2 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index 8d5e289..e803069 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SABRESD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 9f29b15..2d7e230 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index a43de4a..d3c6fb0 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 2efd833..100103e 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SLEVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 8a4c7d5..83a1a34 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABREAUTO=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 55093c9..54ddca8 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index f01fd3b..9ad038a 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6SXSABRESD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index dee1ef0..c65bdbf 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 644fd20..caf2477 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 3bde39f..09716a7 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MX7DSABRESD=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index cc86e3f..02b2462 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 05dcea2..52553f6 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 2de93a4..11188b7 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index a5f57f6..05bf140 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index fdd444e..bb081a2 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index daace52..08e91c9 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 6cf304f..262042d 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -61,5 +61,6 @@ CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
 CONFIG_VIDEO_BRIDGE=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 44b5c16..c1d0fc3 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS5=y
+CONFIG_TARGET_ODROID_XU3=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
index 3385d67..801c959 100644
--- a/configs/omap3_evm_quick_mmc_defconfig
+++ b/configs/omap3_evm_quick_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig
index b53a9c2..8815fca 100644
--- a/configs/omap3_evm_quick_nand_defconfig
+++ b/configs/omap3_evm_quick_nand_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=0
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index b8c7621..e7bf385 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
@@ -33,5 +34,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="TI"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index d5383d4..8b1082c 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -4,7 +4,9 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB1_VBUS_PIN="PG13"
+# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 9b6a1af..be8afca 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -4,6 +4,8 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7f360f5..7eaa795 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 88df360..9ff4332 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,8 +4,10 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PG13"
+# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index c604340..0af6a0b 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_OT1200=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index b5791ad..28bc9ba 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_OT1200=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
index 1136e1f..9f2c418 100644
--- a/configs/p2771-0000_defconfig
+++ b/configs/p2771-0000_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TEGRA=y
 CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 64b956f..0fe43b1 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -33,3 +33,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index 5a7fa80..6aa2c43 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -14,3 +14,4 @@ CONFIG_SYS_PROMPT="Pb1x00 # "
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 7f29119..27f681f 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -30,3 +30,4 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index eff099c..b277b3a 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -30,3 +30,4 @@ CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index d46cd3b..ab9c9f1 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PICO_IMX6UL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 2d9c4a6..0bf79bf 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,5 +1,4 @@
 CONFIG_ARM=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
 CONFIG_DRAM_CLK=672
@@ -10,3 +9,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 9676a99..08efb3a 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PLATINUM_PICON=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="picon > "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index f3de3fc..00e227f 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_PLATINUM_TITANIUM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="titanium > "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 6b60335..ed519a0 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -29,3 +29,4 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index 23bd9a9..9aa5280 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index f7f3fb0..038eb39 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index bd553be..1c1e304 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_R2DPLUS=y
+CONFIG_BOOTDELAY=-1
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 516bee7..3e16b80 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -63,6 +63,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 71f7130..4eb3c22 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,5 +1,4 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_BLK=y
 CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
@@ -71,6 +70,7 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -89,9 +89,6 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_DM_MAILBOX=y
-CONFIG_SANDBOX_MBOX=y
-CONFIG_MISC=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_I2C=y
@@ -173,3 +170,6 @@ CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
+CONFIG_MISC=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 9ffefbd..3f8648d 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -34,3 +34,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 2c57714..3e9e329 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -5,6 +5,7 @@ CONFIG_SECOMX6_UQ7=y
 CONFIG_SECOMX6Q=y
 CONFIG_SECOMX6_2GB=y
 CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig
index cc20fbd..41d2b55 100644
--- a/configs/sh7763rdp_defconfig
+++ b/configs/sh7763rdp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_SH7763RDP=y
+CONFIG_BOOTDELAY=-1
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 5e3844c..5ba6523 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS4=y
+CONFIG_TARGET_SMDKV310=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index aa4bbb6..aaf5873 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SOCRATES=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig
index db3b6ea..2ef309c 100644
--- a/configs/spear300_defconfig
+++ b/configs/spear300_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig
index ea4e8d7..611631e 100644
--- a/configs/spear300_nand_defconfig
+++ b/configs/spear300_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300,nand"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig
index a2b56f3..5338418 100644
--- a/configs/spear300_usbtty_defconfig
+++ b/configs/spear300_usbtty_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig
index 1738489..d525edf 100644
--- a/configs/spear300_usbtty_nand_defconfig
+++ b/configs/spear300_usbtty_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR300=y
 CONFIG_SYS_EXTRA_OPTIONS="spear300,usbtty,nand"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig
index a6064a5..3f20387 100644
--- a/configs/spear310_defconfig
+++ b/configs/spear310_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig
index 85944c6..2feb9cc 100644
--- a/configs/spear310_nand_defconfig
+++ b/configs/spear310_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,nand"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig
index 48efe3d..4ab49d9 100644
--- a/configs/spear310_pnor_defconfig
+++ b/configs/spear310_pnor_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,FLASH_PNOR"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig
index 8edbe0c..299cf6d 100644
--- a/configs/spear310_usbtty_defconfig
+++ b/configs/spear310_usbtty_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig
index b622f74..9ac10f2 100644
--- a/configs/spear310_usbtty_nand_defconfig
+++ b/configs/spear310_usbtty_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,nand"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig
index 241a72a..f582b46 100644
--- a/configs/spear310_usbtty_pnor_defconfig
+++ b/configs/spear310_usbtty_pnor_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR310=y
 CONFIG_SYS_EXTRA_OPTIONS="spear310,usbtty,FLASH_PNOR"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig
index 49d7c04..4b4f2f6 100644
--- a/configs/spear320_defconfig
+++ b/configs/spear320_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig
index 70b3025..7308879 100644
--- a/configs/spear320_nand_defconfig
+++ b/configs/spear320_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,nand"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig
index 5ced0e1..fdffa97 100644
--- a/configs/spear320_pnor_defconfig
+++ b/configs/spear320_pnor_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,FLASH_PNOR"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig
index de75b17..ee873e9 100644
--- a/configs/spear320_usbtty_defconfig
+++ b/configs/spear320_usbtty_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig
index 2202d2e..a587470 100644
--- a/configs/spear320_usbtty_nand_defconfig
+++ b/configs/spear320_usbtty_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,nand"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig
index 35bb036..a65dc11 100644
--- a/configs/spear320_usbtty_pnor_defconfig
+++ b/configs/spear320_usbtty_pnor_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR320=y
 CONFIG_SYS_EXTRA_OPTIONS="spear320,usbtty,FLASH_PNOR"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig
index f540839..623800c 100644
--- a/configs/spear600_defconfig
+++ b/configs/spear600_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600"
+CONFIG_BOOTDELAY=1
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig
index de416d9..8da9b34 100644
--- a/configs/spear600_nand_defconfig
+++ b/configs/spear600_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600,nand"
+CONFIG_BOOTDELAY=1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig
index 8b6e0d0..68b11cc 100644
--- a/configs/spear600_usbtty_defconfig
+++ b/configs/spear600_usbtty_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig
index e8b4b0a..776c611 100644
--- a/configs/spear600_usbtty_nand_defconfig
+++ b/configs/spear600_usbtty_nand_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SPEAR600=y
 CONFIG_SYS_EXTRA_OPTIONS="spear600,usbtty,nand"
+CONFIG_BOOTDELAY=-1
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 5861cff..6d39dec 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index dc69b39..3fb04b7 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TBS2910=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Matrix U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
index cc46a52..fd31cfc 100644
--- a/configs/tcm-bf518_defconfig
+++ b/configs/tcm-bf518_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF518=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
index 576dc6a..d66e499 100644
--- a/configs/tcm-bf537_defconfig
+++ b/configs/tcm-bf537_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_TCM_BF537=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 7dbb4cd..b710229 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -35,3 +35,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 742d90d..2055101 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -34,3 +34,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index e41e2a4..ef9c074 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TI814X_EVM=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index 4d16ef6..57cf670 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_TITANIUM=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Titanium > "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index 22b16a1..aa1ecd8 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_TQMA6=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index 715db21..f40b1dd 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -5,6 +5,7 @@ CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index 824cd2b..eaea483 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -5,6 +5,7 @@ CONFIG_TQMA6S=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index 058bb89..213dada 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -6,6 +6,7 @@ CONFIG_TQMA6X_SPI_BOOT=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index e348960..b44522b 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -6,6 +6,7 @@ CONFIG_WRU4=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 25c499a..2482888 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_TRICORDER=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 200fbe1..b285a81 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TRICORDER=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 72e641d..67857a5 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -36,3 +36,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SFLASH=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 7d8953d..bd05405 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TS4800=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
index 4b4cfd2..337404b 100644
--- a/configs/tseries_mmc_defconfig
+++ b/configs/tseries_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
index 1485aaa..4dc0296 100644
--- a/configs/tseries_nand_defconfig
+++ b/configs/tseries_nand_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
index a68cfac..5b52bf6 100644
--- a/configs/tseries_spi_defconfig
+++ b/configs/tseries_spi_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_TSERIES=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 81c32cd..3c75706 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_UDOO=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index edbb18f..17a6000 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -42,3 +42,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index aeb9025..97b13a1 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -33,3 +33,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig
index 989f068..5dd6e75 100644
--- a/configs/vexpress_aemv8a_dram_defconfig
+++ b/configs/vexpress_aemv8a_dram_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM_SERIAL=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index c70851f..26cbc85 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS64_JUNO=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM_SERIAL=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index b0a2f67..27c04ba 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DM_SERIAL=y
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VExpress64# "
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig
index 2f141dd..c39faaa 100644
--- a/configs/vexpress_ca15_tc2_defconfig
+++ b/configs/vexpress_ca15_tc2_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca15x2_tc2"
diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig
index c495ee5..e71d45e 100644
--- a/configs/vexpress_ca5x2_defconfig
+++ b/configs/vexpress_ca5x2_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca5x2"
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index fcd6e26..20100a3 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -24,3 +24,4 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7.vexpress_ca9x4"
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index ad4fbbf..102b5b1 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_WARP7=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
+CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index 3f9bb25..389bb7f 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_WARP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index 754e5cb..ca753a4 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -29,3 +29,4 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 59a3138..d06df39 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_TARGET_XPRESS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index ad0cddb..b82a5ed 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_TARGET_XPRESS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 4396698..0e8d4ac 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -149,10 +149,6 @@
 
 /*AUTOBOOT settings - booting images automatically by u-boot after power on*/
 
-seconds u-boot will wait before starting defined (auto-)boot command, setting
-to -1 disables delay, setting to 0 will too prevent access to u-boot command
-interface: u-boot then has to reflashed */
-
 /* The following settings will be contained in the environment block ; if you
 want to use a neutral environment all those settings can be manually set in
 u-boot: 'set' command */
-- 
cgit v0.10.2


From 8311b3b4406ead0f5d54712f1c0cef1e564b23ab Mon Sep 17 00:00:00 2001
From: "Srinivas, Madan" <madans@ti.com>
Date: Thu, 16 Jun 2016 15:42:31 -0400
Subject: ARM: AM437x: Sync defconfig between GP and HS EVM

Adds missing NAND option to CONFIG_SYS_EXTRA_OPTIONS for
AM437x HS EVMs. This syncs up the config options between
GP and HS EVMs.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
index 3cd39eb..e82085b 100644
--- a/configs/am437x_hs_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -10,7 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
 CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From 030cada824730df4b601d8e1503baf8eea29b1ce Mon Sep 17 00:00:00 2001
From: "Srinivas, Madan" <madans@ti.com>
Date: Thu, 16 Jun 2016 15:42:32 -0400
Subject: ARM: AM437x: Enable FIT for hs platforms

Adds FIT support to the SPL and u-boot for AM437x HS devices.

Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
index e82085b..4856a19 100644
--- a/configs/am437x_hs_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -10,7 +10,9 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
 CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -33,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -53,3 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_SPL_OF_LIBFDT=y
-- 
cgit v0.10.2


From e17adbb3507fc022fe6ed38b150ce9044101d9b0 Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Wed, 15 Jun 2016 17:00:19 -0500
Subject: common: image-fit: Cleanup spelling mistakes

The comments in the source file are riddled with spelling mistakes. Be
a good citizen and take a stab at cleaning up some of the more obvious
ones.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/image-fit.c b/common/image-fit.c
index 9873957..6f920da 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -147,7 +147,7 @@ int fit_get_subimage_count(const void *fit, int images_noffset)
  * @p: pointer to prefix string
  *
  * fit_print_contents() formats a multi line FIT image contents description.
- * The routine prints out FIT image properties (root node level) follwed by
+ * The routine prints out FIT image properties (root node level) followed by
  * the details of each component image.
  *
  * returns:
@@ -249,7 +249,7 @@ void fit_print_contents(const void *fit)
  * @p: pointer to prefix string
  * @type: Type of information to print ("hash" or "sign")
  *
- * fit_image_print_data() lists properies for the processed hash node
+ * fit_image_print_data() lists properties for the processed hash node
  *
  * This function avoid using puts() since it prints a newline on the host
  * but does not in U-Boot.
@@ -314,7 +314,7 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p,
  * @noffset: offset of the hash or signature node
  * @p: pointer to prefix string
  *
- * This lists properies for the processed hash node
+ * This lists properties for the processed hash node
  *
  * returns:
  *     no returned results
@@ -344,7 +344,7 @@ static void fit_image_print_verification_data(const void *fit, int noffset,
  * @image_noffset: offset of the component image node
  * @p: pointer to prefix string
  *
- * fit_image_print() lists all mandatory properies for the processed component
+ * fit_image_print() lists all mandatory properties for the processed component
  * image. If present, hash nodes are printed out as well. Load
  * address for images of type firmware is also printed out. Since the load
  * address is not mandatory for firmware images, it will be output as
@@ -459,10 +459,10 @@ void fit_image_print(const void *fit, int image_noffset, const char *p)
  * fit_get_desc - get node description property
  * @fit: pointer to the FIT format image header
  * @noffset: node offset
- * @desc: double pointer to the char, will hold pointer to the descrption
+ * @desc: double pointer to the char, will hold pointer to the description
  *
  * fit_get_desc() reads description property from a given node, if
- * description is found pointer to it is returened in third call argument.
+ * description is found pointer to it is returned in third call argument.
  *
  * returns:
  *     0, on success
@@ -487,8 +487,8 @@ int fit_get_desc(const void *fit, int noffset, char **desc)
  * @noffset: node offset
  * @timestamp: pointer to the time_t, will hold read timestamp
  *
- * fit_get_timestamp() reads timestamp poperty from given node, if timestamp
- * is found and has a correct size its value is retured in third call
+ * fit_get_timestamp() reads timestamp property from given node, if timestamp
+ * is found and has a correct size its value is returned in third call
  * argument.
  *
  * returns:
@@ -520,7 +520,7 @@ int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp)
  * @fit: pointer to the FIT format image header
  * @image_uname: component image node unit name
  *
- * fit_image_get_node() finds a component image (withing the '/images'
+ * fit_image_get_node() finds a component image (within the '/images'
  * node) of a provided unit name. If image is found its node offset is
  * returned to the caller.
  *
@@ -989,7 +989,7 @@ static int fit_image_check_hash(const void *fit, int noffset, const void *data,
 }
 
 /**
- * fit_image_verify - verify data intergity
+ * fit_image_verify - verify data integrity
  * @fit: pointer to the FIT format image header
  * @image_noffset: component image node offset
  *
@@ -1073,7 +1073,7 @@ error:
 }
 
 /**
- * fit_all_image_verify - verify data intergity for all images
+ * fit_all_image_verify - verify data integrity for all images
  * @fit: pointer to the FIT format image header
  *
  * fit_all_image_verify() goes over all images in the FIT and
@@ -1380,8 +1380,8 @@ int fit_conf_find_compat(const void *fit, const void *fdt)
  * @fit: pointer to the FIT format image header
  * @conf_uname: configuration node unit name
  *
- * fit_conf_get_node() finds a configuration (withing the '/configurations'
- * parant node) of a provided unit name. If configuration is found its node
+ * fit_conf_get_node() finds a configuration (within the '/configurations'
+ * parent node) of a provided unit name. If configuration is found its node
  * offset is returned to the caller.
  *
  * When NULL is provided in second argument fit_conf_get_node() will search
@@ -1447,7 +1447,7 @@ int fit_conf_get_prop_node(const void *fit, int noffset,
  * @noffset: offset of the configuration node
  * @p: pointer to prefix string
  *
- * fit_conf_print() lists all mandatory properies for the processed
+ * fit_conf_print() lists all mandatory properties for the processed
  * configuration node.
  *
  * returns:
@@ -1558,7 +1558,7 @@ static const char *fit_get_image_type_property(int type)
 {
 	/*
 	 * This is sort-of available in the uimage_type[] table in image.c
-	 * but we don't have access to the sohrt name, and "fdt" is different
+	 * but we don't have access to the short name, and "fdt" is different
 	 * anyway. So let's just keep it here.
 	 */
 	switch (type) {
-- 
cgit v0.10.2


From 58c95d5356f4a4c711523dbca0e989cfc8d2cf21 Mon Sep 17 00:00:00 2001
From: Petr Kulhavy <brain@jikos.cz>
Date: Tue, 14 Jun 2016 12:06:36 +0200
Subject: SPL: ext: remove redundant ifdef statement

Remove redundant #if defined(CONFIG_SPL_OS_BOOT) statement around
getenv() calls in spl_load_image_ext_os().

The whole function is surrounded by #ifdef CONFIG_SPL_OS_BOOT.

No functional change.

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
CC: Guillaume GARDET <guillaume.gardet@free.fr>
Acked-by:  Guillaume GARDET <guillaume.gardet@free.fr>

diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index ade5496..89ac4f4 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -88,8 +88,7 @@ int spl_load_image_ext_os(struct blk_desc *block_dev, int partition)
 #endif
 		return -1;
 	}
-
-#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
+#if defined(CONFIG_SPL_ENV_SUPPORT)
 	file = getenv("falcon_args_file");
 	if (file) {
 		err = ext4fs_open(file, &filelen);
-- 
cgit v0.10.2


From 1e2a1fb70284d217cfa5679f75fe69122057b975 Mon Sep 17 00:00:00 2001
From: Thomas Lange <thomas@corelatus.se>
Date: Tue, 14 Jun 2016 11:04:37 +0200
Subject: Orphan dbau1x00 boards

I no longer have access to such a board

Signed-off-by: Thomas Lange <thomas@corelatus.se>

diff --git a/board/dbau1x00/MAINTAINERS b/board/dbau1x00/MAINTAINERS
index b94ed81..21853ed 100644
--- a/board/dbau1x00/MAINTAINERS
+++ b/board/dbau1x00/MAINTAINERS
@@ -1,6 +1,6 @@
 DBAU1X00 BOARD
-M:	Thomas Lange <thomas@corelatus.se>
-S:	Maintained
+#M:	-
+S:	Orphan (since 2016-06)
 F:	board/dbau1x00/
 F:	include/configs/dbau1x00.h
 F:	configs/dbau1000_defconfig
-- 
cgit v0.10.2


From f51c8a99e330dbd6a8db5d45a431390a339cfc41 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Tue, 14 Jun 2016 09:13:37 +0200
Subject: OMAP3: fix twister board

twister board was not updated after changing
SPL defines, resulting in a broken board.

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index efdc706..73ff416 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -207,6 +207,8 @@
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
@@ -219,12 +221,26 @@
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
 #define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+/* FAT */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
 /* NAND boot config */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
-- 
cgit v0.10.2


From ae094f8d55a1cab50b1aa17c924feeb1818a57ef Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Mon, 13 Jun 2016 18:25:16 -0500
Subject: ARM: AM57xx: Enable FIT for HS Devices

Enable FIT support for AM57xx platforms using the high-security (HS)
device variant.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index a100079..e01e504 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -37,3 +37,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_FIT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="am57xx-beagle-x15"
-- 
cgit v0.10.2


From e7b35eb2e0f209e26eb30c4e5b3da50a50d19af1 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 13 Jun 2016 15:16:00 +0200
Subject: arm, am335x: siemens: update etamin defconfig

add missing USB_MUSB_* and CONFIG_G_DNL_*
board configuration.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 6c747df..f86f4a3 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -14,5 +14,11 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
-- 
cgit v0.10.2


From 71423435fb02c2ed9e7aa14c1208d3cccbff2519 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Mon, 13 Jun 2016 15:16:01 +0200
Subject: arm, am335x: siemens: enable DM/DTS support

enable basic DM/DTS support for the siemens am335x based boards.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80a3f93..84cabb8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,31 +350,49 @@ config TARGET_DRACO
 	bool "Support draco"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_THUBAN
 	bool "Support thuban"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_RASTABAN
 	bool "Support rastaban"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_ETAMIN
         bool "Support etamin"
         select CPU_V7
         select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_PXM2
 	bool "Support pxm2"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_RUT
 	bool "Support rut"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_PENGWYN
 	bool "Support pengwyn"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0b2b269..7fe10c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -95,10 +95,14 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm018-dc4.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
+	am335x-draco.dtb \
+	am335x-evm.dtb \
 	am335x-evmsk.dtb \
 	am335x-bonegreen.dtb \
-	am335x-icev2.dtb
+	am335x-icev2.dtb \
+	am335x-pxm50.dtb \
+	am335x-rut.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb
diff --git a/arch/arm/dts/am335x-draco.dts b/arch/arm/dts/am335x-draco.dts
new file mode 100644
index 0000000..25d0480
--- /dev/null
+++ b/arch/arm/dts/am335x-draco.dts
@@ -0,0 +1,152 @@
+/*
+ * Support for Siemens DRACO board
+ *
+ * Copyright (C) 2014 - Lukas Stockmann <lukas.stockmann@siemens.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-draco.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Siemens DRACO";
+	compatible = "siemens,draco", "ti,am33xx";
+
+	/* ethernet alias is needed for the MAC address passing from U-Boot */
+	aliases {
+		ethernet0 = &cpsw_emac0;
+		mdio-gpio0 = &mdio0;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		button0 {
+			label = "button0";
+			gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_F1>; /* button0 */
+		};
+		button1 {
+			label = "button1";
+			gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_F2>; /* button1 */
+		};
+	};
+
+	ocp {
+		debugss: debugss@4b000000 {
+			compatible = "ti,debugss";
+			ti,hwmods = "debugss";
+			reg = <0x4b000000 1000000>;
+			status = "disabled";
+		};
+	};
+};
+
+&am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio_mux_pins>;
+
+	gpio_mux_pins: gpio_mux_pins {
+		pinctrl-single,pins = <
+			0x1d0 (PIN_INPUT | MUX_MODE0)	/* tms jtag */
+			0x1d4 (PIN_INPUT | MUX_MODE0)	/* tdi jtag */
+			0x1d8 (PIN_OUTPUT | MUX_MODE0)	/* tdo jtag */
+			0x1dc (PIN_INPUT | MUX_MODE0)	/* tck jtag */
+			0x1e0 (PIN_INPUT | MUX_MODE0)	/* trstn jtag */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7)	/* lcd_plck FIX STO should be a OUTPUT driven high*/
+			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
+			0x114 (PIN_OUTPUT | MUX_MODE1)		/* mii1_txen.mii1_txen */
+			0x124 (PIN_OUTPUT | MUX_MODE1)		/* mii1_txd1.mii1_txd1 */
+			0x128 (PIN_OUTPUT | MUX_MODE1)		/* mii1_txd0.mii1_txd0 */
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.mii1_rxd1 */
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.mii1_rxd0 */
+			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			0x14c (PIN_OUTPUT | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	gpio_mdio_default: gpio_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO via GPIO */
+			0x148 (PIN_INPUT | MUX_MODE7)	/* mdio_data.mdio_data GPIO0_0 */
+			0x14c (PIN_OUTPUT | MUX_MODE7)	/* mdio_clk.mdio_clk GPIO0_1 */
+		>;
+	};
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	slaves = <1>;			/* use only one emac if */
+
+	mdio0: gpio {
+		compatible = "virtual,mdio-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_mdio_default>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpio0 1 GPIO_ACTIVE_HIGH	/* MDIO-CLK */
+			 &gpio0 0 GPIO_ACTIVE_HIGH>;	/* MDIO-DATA */
+
+		phy0: ethernet-phy@1 {
+			reg = <0>;
+		};
+	};
+};
+
+/* Disable davinci/am335x mdio interface on this platform */
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "disabled";
+};
+
+&cpsw_emac0 {
+	phy_id = <&mdio0>, <0>;
+	phy-mode = "rmii";
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
diff --git a/arch/arm/dts/am335x-draco.dtsi b/arch/arm/dts/am335x-draco.dtsi
new file mode 100644
index 0000000..b38ff55
--- /dev/null
+++ b/arch/arm/dts/am335x-draco.dtsi
@@ -0,0 +1,169 @@
+/*
+ * Common support for Siemens Draco SOM (AM335x based)
+ *
+ * Copyright (C) 2013,2014 - Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x08000000>; /* 128 MB */
+	};
+
+	ocp {
+		uart0: serial@44e09000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins>;
+			status = "okay";
+		};
+
+		i2c0: i2c@44e0b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
+
+			status = "okay";
+			clock-frequency = <400000>;
+
+			eeprom: eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+				pagesize = <64>;
+			};
+		};
+
+		musb: usb@47400000 {
+			status = "okay";
+
+			control@44e10620 {
+				status = "okay";
+			};
+
+			usb-phy@47401300 {
+				status = "okay";
+			};
+
+			usb-phy@47401b00 {
+				status = "okay";
+			};
+
+			usb@47401000 {
+				status = "okay";
+			};
+
+			usb@47401800 {
+				status = "okay";
+				dr_mode = "host";
+			};
+
+			dma-controller@47402000  {
+				status = "okay";
+			};
+		};
+	};
+};
+
+&am33xx_pinmux {
+		i2c0_pins: pinmux_i2c0_pins {
+			pinctrl-single,pins = <
+				0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			>;
+		};
+
+		uart0_pins: pinmux_uart0_pins {
+			pinctrl-single,pins = <
+				0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+				0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			>;
+		};
+
+		nandflash_pins: nandflash_pins {
+			pinctrl-single,pins = <
+				0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+				0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+				0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+				0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+				0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+				0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+				0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+				0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+				0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+				0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
+				0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+				0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+				0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+				0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+				0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			>;
+		};
+	};
+
+
+&timer3 {
+	status = "disabled";
+};
+
+&uart4 {
+	status = "disabled";
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins>;
+
+	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+
+	nand@0,0 {
+		reg = <0 0 0>; /* CS0, offset 0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		elm_id = <&elm>;
+	};
+};
+
+/* disable the RTC node as its not accessible on the draco/dxr2 board */
+&rtc {
+	status = "disabled";
+	ti,hwmods = "disabled";
+};
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
new file mode 100644
index 0000000..8d58cd4
--- /dev/null
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -0,0 +1,539 @@
+/*
+ * Copyright (C) 2014 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * Based on:
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
+	backlight0: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap0 0 50000 0>;
+		brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35
+				     38 40 43 45 48 51 53 56 58 61 63 66 68 71
+				     73 76 79 81 84 86 89 91 94 96 99 102 104
+				     107 109 112 114 117 119 122 124 127 130
+				     132 135 137 140 142 145 147 150 153 155
+				     158 160 163 165 168 170 173 175 178 181
+				     183 186 188 191 193 196 198 201 204 206
+				     209 211 214 216 219 221 224 226 229 232
+				     234 237 239 242 244 247 249 252 255>;
+		default-brightness-level = <80>;
+		power-supply = <&backlight_reg>;
+		enable-gpios = <&gpio3 16 0>;
+	};
+
+	backlight_reg: fixedregulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "backlight_reg";
+		regulator-boot-on;
+	};
+
+	gpio_keys: restart-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		restart0 {
+			label = "restart";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+			gpio-key,wakeup;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_blue {
+			label = "blue";
+			gpios = <&gpio3 20 0>;
+		};
+		led_green {
+			label = "green";
+			gpios = <&gpio1 31 0>;
+		};
+		led_red {
+			label = "red";
+			gpios = <&gpio3 21 0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	reg_lcd_3v3: fixedregulator1 {
+		compatible = "regulator-gpio";
+                regulator-name = "lcd-3v3";
+		regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+		regulator-type = "voltage";
+		startup-delay-us = <100>;
+		states = <1800000 0x1
+			  2900000 0x0>;
+		enable-at-boot;
+                gpios = <&gpio3 19 0>;
+                enable-active-high;
+        };
+
+	vbat: fixedregulator2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	vmmc: fixedregulator3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&cppi41dma  {
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii-txid";
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rgmii-txid";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&elm {
+	status = "okay";
+};
+
+&epwmss0 {
+	status = "okay";
+
+	ecap0: ecap@48300100 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap0_pins>;
+	};
+};
+
+&gpmc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins>;
+	status = "okay";
+
+	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+
+	nand@0,0 {
+		reg = <0 0 0>; /* CS0, offset 0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		elm_id = <&elm>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	tps: tps@2d {
+		reg = <0x2d>;
+	};
+	eeprom: eeprom@50 {
+		compatible = "atmel,24c128";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	tsl2563: tsl2563@49 {
+		compatible = "amstaos,tsl2563";
+		reg = <0x49>;
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	egalax_ts@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <24 2>;
+		wakeup-gpios = <&gpio1 25 0>;
+	};
+};
+
+&lcdc {
+	status = "okay";
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmc>;
+	bus-width = <4>;
+	cd-gpios = <&gpio0 6 0>;
+	wp-gpios = <&gpio3 18 0>;
+	status = "okay";
+};
+
+&phy_sel {
+	rgmii-no-delay;
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1312500>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb1_phy {
+	status = "okay";
+};
+
+&am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&clkout2_pin &gpio_pin>;
+
+	clkout2_pin: pinmux_clkout2_pin {
+		pinctrl-single,pins = <
+			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
+			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
+			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
+			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
+			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	ecap0_pins: ecap_pins {
+		pinctrl-single,pins = <
+			0x198 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* mcasp0_axr0.gpio3_16 Backlight enable */
+			0x164 (MUX_MODE0)	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+		>;
+	};
+
+
+	gpio_pin: gpio_pin {
+		pinctrl-single,pins = <
+			0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a6.gpio1_22 touch reset */
+			0x60 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a8.gpio1_24 touch irq */
+			0x64 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a9.gpio1_25 touch power */
+			0x6c (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a11.gpio1_27 pad14 to DFU */
+			0x21c (MUX_MODE0)	/* usb0_drvvbus */
+			0x234 (MUX_MODE0)	/* usb1_drvvbus */
+			0x1a0 (PIN_INPUT_PULLUP | MUX_MODE4)	/* mcasp0_aclkr.mmc0_sdwp */
+			0x160 (PIN_INPUT_PULLUP | MUX_MODE5)	/* spi0_cs1.mmc0_sdcd */
+		>;
+	};
+
+	i2c0_pins: pinmux_i2c0_pins {
+		pinctrl-single,pins = <
+			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x158 (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
+			0x15c (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
+		>;
+	};
+
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			0x150 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)	/* spi0_sclk.i2c2_sda */
+			0x154 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)	/* spi0_cs0.i2c2_scl */
+		>;
+	};
+
+	lcd_pins_s0: lcd_pins_s0 {
+		pinctrl-single,pins = <
+			0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
+			0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
+			0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
+			0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
+			0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
+			0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
+			0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
+			0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
+			0xa0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
+			0xa4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
+			0xa8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
+			0xac (PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
+			0xb0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
+			0xb4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
+			0xb8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
+			0xbc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
+			0xc0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
+			0xc4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
+			0xc8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
+			0xcc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
+			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
+			0xd4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
+			0xd8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
+			0xdc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
+			0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
+			0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
+			0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
+			0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+			0x194 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* mcasp0_fsx.gpio3_15 LCD enable */
+		>;
+	};
+
+	nandflash_pins: pinmux_nandflash_pins {
+		pinctrl-single,pins = <
+			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
+			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
+			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+		>;
+	};
+};
+
+&wdt2 {
+	wdt-keep-enabled;
+};
diff --git a/arch/arm/dts/am335x-pxm50.dts b/arch/arm/dts/am335x-pxm50.dts
new file mode 100644
index 0000000..f4e66d2
--- /dev/null
+++ b/arch/arm/dts/am335x-pxm50.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2014 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am335x-pxm2.dtsi"
+
+/ {
+	model = "PXM2/PXM50";
+	compatible = "ti,am335x-evm", "ti,am33xx";
+
+		panel {
+			compatible = "ti,tilcdc,panel";
+			backlight = <&backlight0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&lcd_pins_s0>;
+			enable-gpios = <&gpio3 15 0>;
+			status = "okay";
+
+			panel-info {
+				ac-bias           = <255>;
+				ac-bias-intrpt    = <0>;
+				dma-burst-sz      = <16>;
+				bpp               = <32>;
+				fdd               = <0x80>;
+				sync-edge         = <0>;
+				sync-ctrl         = <1>;
+				raster-order      = <0>;
+				fifo-th           = <0>;
+				tft-alt-mode      = <0>;
+				invert-pxl-clk    = <0>;
+			};
+
+			display-timings {
+				native-mode = <&timing1>;
+
+				timing1: 1376x768p50 {
+					clock-frequency = <60000000>;
+					hactive = <1376>;
+					vactive = <768>;
+					hfront-porch = <14>;
+					hback-porch = <64>;
+					hsync-len = <56>;
+					vback-porch = <28>;
+					vfront-porch = <1>;
+					vsync-len = <6>;
+					hsync-active = <1>;
+					vsync-active = <1>;
+				};
+			};
+		};
+};
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
new file mode 100644
index 0000000..c6cfbb8
--- /dev/null
+++ b/arch/arm/dts/am335x-rut.dts
@@ -0,0 +1,611 @@
+/*
+ * Copyright (C) 2014 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * Based on:
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "RUT";
+	compatible = "ti,am335x-evm", "ti,am33xx";
+
+	buzzer {
+		compatible = "pwm-beeper";
+		pwms = <&ecap0 0 16000 0>;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&dcdc2_reg>;
+		};
+	};
+
+	gpio_keys: powerfail-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pwr-fail0 {
+			label = "power-fail";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+			gpio-key,wakeup;
+		};
+
+		pwr-fail1 {
+			label = "power-fail-redundant";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+			gpio-key,wakeup;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_green {
+			label = "rut:green:debug:run_mode";
+			gpios = <&gpio3 20 1>;
+			/* activelow = 1, default trigger heartbeat */
+		};
+		led_yellow {
+			label = "rut:debug:yellow:osc_ch1";
+			gpios = <&gpio0 17 1>;
+			/* activelow = 1, default trigger mmc0 */
+		};
+		led_red {
+			label = "rut:debug:red:osc_ch2";
+			gpios = <&gpio0 16 1>;
+			/* activelow = 1, default trigger debug_osc_ch2 */
+		};
+		/* optional */
+		led_alive {
+			label = "rut:alive";
+			gpios = <&gpio0 15 1>;
+			linux,default-trigger = "heartbeat";
+			/* activelow = 1, default trigger heartbeat */
+		};
+
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	panel {
+		compatible = "ti,tilcdc,panel";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_pins_s0>;
+		status = "okay";
+
+		/* FORMIKE_KWH043ST20_F01 */
+		panel-info {
+			ac-bias           = <255>;
+			ac-bias-intrpt    = <0>;
+			dma-burst-sz      = <16>;
+			bpp               = <16>;
+			fdd               = <0x80>;
+			sync-edge         = <0>;
+			sync-ctrl         = <1>;
+			raster-order      = <0>;
+			fifo-th           = <0>;
+			tft-alt-mode      = <0>;
+			invert-pxl-clk    = <1>;
+		};
+
+		display-timings {
+			native-mode = <&timing1>;
+			timing1: 480x800p60 {
+				clock-frequency = <29925000>;
+				hactive = <480>;
+				vactive = <800>;
+				hfront-porch = <50>;
+				hback-porch = <50>;
+				hsync-len = <50>;
+				vback-porch = <50>;
+				vfront-porch = <50>;
+				vsync-len = <50>;
+				hsync-active = <1>;
+				vsync-active = <1>;
+			};
+		};
+	};
+
+	vmmc: fixedregulator3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	watchdog {
+		compatible = "linux,wdt-gpio";
+		gpios = <&gpio0 14 0>;
+		hw_algo = "level";
+		hw_margin_ms = <30000>;
+	};
+};
+
+&aes {
+	status = "okay";
+};
+
+&cppi41dma  {
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rmii";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+	gpios = <&gpio2 18 0>;
+
+        ethernet_phy: ethernet-phy@1 {
+                compatible = "ethernet-phy-id2000.5ce1";
+                reg = <1>;
+		natsemi,master_mode_fixup;
+        };
+};
+
+&elm {
+	status = "okay";
+};
+
+&epwmss0 {
+	status = "okay";
+
+	ecap0: ecap@48300100 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap0_pins>;
+	};
+};
+
+&epwmss1 {
+	status = "okay";
+
+	ehrpwm1: ehrpwm@48302200 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&epwmss1_pins>;
+	};
+};
+
+&gpmc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins>;
+	status = "okay";
+
+	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+
+	nand@0,0 {
+		reg = <0 0 0>; /* CS0, offset 0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <57>;
+		gpmc,cs-wr-off-ns = <57>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <57>;
+		gpmc,adv-wr-off-ns = <57>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <48>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <57>;
+		gpmc,access-ns = <38>;
+		gpmc,rd-cycle-ns = <67>;
+		gpmc,wr-cycle-ns = <67>;
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <96>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		elm_id = <&elm>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom: eeprom@50 {
+		compatible = "atmel,24c128";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	tps: tps@24 {
+		reg = <0x24>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	atmel: atmel_mxt_ts@4a {
+		compatible = "atmel,maxtouch";
+		reg = <0x4a>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <28 8>;
+		gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+	};
+
+	temp@48 {
+		compatible = "st,ds75";
+		reg = <0x4c>;
+	};
+};
+
+&lcdc {
+	status = "okay";
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmc>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	status = "okay";
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
+
+&sham {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mx25l25635e";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <24000000>;
+
+		partition@0 {
+			label = "dummy";
+			reg = <0x0000000 0x8000>;
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+	status = "okay";
+
+	lcd_init: lcd@0 {
+		compatible = "formike,kwh043st20";
+		reg = <0>;
+		reset-gpios = <&gpio3 19 0>;
+		spi-max-frequency = <1200000>;
+		spi-cpol;
+		spi-cpha;
+		power-on-delay = <10>;
+		reset-delay = <10>;
+	};
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+	backlight0: backlight {
+		isel = <1>;  /* 1 - ISET1, 2 ISET2 */
+		fdim = <1000>; /* TPS65217_BL_FDIM_100HZ */
+		default-brightness = <80>;
+	};
+
+	regulators {
+		dcdc1_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		dcdc2_reg: regulator@1 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1325000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3_reg: regulator@2 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo1_reg: regulator@3 {
+			regulator-always-on;
+		};
+
+		ldo2_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		ldo3_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		ldo4_reg: regulator@6 {
+			regulator-always-on;
+		};
+	};
+};
+
+&tscadc {
+	status = "okay";
+	adc {
+		ti,adc-channels = <4 5 6 7>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "device";
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&clkout2_pin &gpio_pin>;
+
+	clkout2_pin: pinmux_clkout2_pin {
+		pinctrl-single,pins = <
+			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
+			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.mii1_rxerr */
+			0x114 (MUX_MODE1)	/* mii1_txen.mii1_txen */
+			0x124 (MUX_MODE1)	/* mii1_txd1.mii1_txd1 */
+			0x128 (MUX_MODE1)	/* mii1_txd0.mii1_txd0 */
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.mii1_rxd1 */
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.mii1_rxd0 */
+			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	ecap0_pins: ecap_pins {
+		pinctrl-single,pins = <
+			0x164 (MUX_MODE0)	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 buzzer frequency: ecap.0 */
+		>;
+	};
+
+	epwmss1_pins: epwmss_pins {
+		pinctrl-single,pins = <
+			0x48 (PIN_INPUT | MUX_MODE7)	/* gpmc_a2.gpio1_18 buzzer frequency: ehrpwm1A high-Z due to connected to ecap0 by R0469 */
+			0x4c (MUX_MODE6)	/* gpmc_a3.ehrpwm1B buzzer volume pwm */
+		>;
+	};
+
+	gpio_pin: gpio_pin {
+		pinctrl-single,pins = <
+			0x6c (PIN_INPUT | MUX_MODE7)		/* gpmc_a11.gpio1_27 PWR_FAIL_GPIO_SPARE */
+			0x78 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7)	/* gpmc_be1n.gpio1_28 TOUCH_CHANGE_N */
+			0x88 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7)		/* gpmc_csn3.gpio2_0 RUT_GPIO0_GPIO */
+			0x118 (PIN_INPUT | MUX_MODE7)		/* gmii1_rxdv.gpio3_4 PWR_FAIL_GPIO */
+			0x11c (MUX_MODE7)			/* mii1_txd3.gpio0_16 DEBUG_OSC_CH2_GPIO */
+			0x120 (MUX_MODE7)			/* mii1_txd2.gpio0_17 DEBUG_OSC_CH1_GPIO */
+			0x134 (MUX_MODE7)			/* gmii1_rxd3.gpio2_18 PHY_RSTn_GPIO */
+			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gmii1_rxd2.gpio2_19 PHY_INT_GPIO */
+			0x180 (MUX_MODE7)			/* uart1_rxd.gpio0_14 WATCHDOG_TRIGGER_GPIO */
+			0x184 (MUX_MODE7)			/* uart1_txd.gpio0_15 ALIVE_LED_N_GPIO */
+			0x1a0 (MUX_MODE7)			/* mcasp0_aclkr.gpio3_18 MAXTOUCH_RESET_GPIO */
+			0x1a4 (MUX_MODE7)			/* mcasp0_fsr.gpio3_19 DISPLAY_RESET_GPIO */
+			0x1a8 (MUX_MODE7)			/* mcasp0_axr1.gpio3_20 DEBUG_RUN_MODE_GPIO */
+			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_ahclkx.gpio3_21 NORFLASH_WP_GPIO */
+			0x1b0 (PIN_OUTPUT | MUX_MODE3)		/* xdma_event_intr0.clkout1 */
+		>;
+	};
+
+	i2c0_pins: pinmux_i2c0_pins {
+		pinctrl-single,pins = <
+			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x168 (PIN_INPUT | MUX_MODE3)	/* uart0_ctsn.i2c1_sda */
+			0x16c (PIN_INPUT | MUX_MODE3)	/* uart0.rtsn.i2c1_scl */
+		>;
+	};
+
+	lcd_pins_s0: lcd_pins_s0 {
+		pinctrl-single,pins = <
+			0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
+			0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
+			0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
+			0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
+			0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
+			0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
+			0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
+			0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
+			0xa0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
+			0xa4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
+			0xa8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
+			0xac (PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
+			0xb0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
+			0xb4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
+			0xb8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
+			0xbc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
+			0xc0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
+			0xc4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
+			0xc8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
+			0xcc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
+			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
+			0xd4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
+			0xd8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
+			0xdc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
+			0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
+			0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
+			0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
+			0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+		>;
+	};
+
+	mmc1_pins: mmc1_pins {
+		pinctrl-single,pins = <
+			0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0.mmc0_dat0 */
+			0xf4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1.mmc0_dat1 */
+			0xf8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2.mmc0_dat2 */
+			0xfc (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
+			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk.mmc0_clk */
+			0x104 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd.mmc0_cmd */
+		>;
+	};
+
+	nandflash_pins: pinmux_nandflash_pins {
+		pinctrl-single,pins = <
+			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
+			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
+			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+
+	spi0_pins: pinmux_spi0_pins {
+		pinctrl-single,pins = <
+			0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_sclk.spi0_sclk */
+			0x154 (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d0.spi0_d0 */
+			0x158 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d1.spi0_d1 */
+			0x15c (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_CS0.spi0_CS0 */
+		>;
+	};
+
+	spi1_pins: pinmux_spi1_pins {
+		pinctrl-single,pins = <
+			0x190 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcasp0_aclkx.spi1_sclk */
+			0x194 (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcasp0_fsx.spi1_d0 */
+			0x198 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcasp0_axr0.spi1_d1 */
+			0x19c (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcasp0_ahclkr.spi1_cs0 */
+		>;
+	};
+
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			0x170 (PIN_INPUT | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			0x174 (PIN_OUTPUT | MUX_MODE0)	/* uart0_txd.uart0_txd */
+		>;
+	};
+};
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index d17e42f..6347b4c 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DRACO=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
@@ -23,6 +26,9 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index f86f4a3..326df8f 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -1,15 +1,34 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ETAMIN=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
 CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 # CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 6f70d68..f34af43 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_PXM2=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -25,6 +28,9 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 7de5a19..901547b 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RASTABAN=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
@@ -23,6 +26,9 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 14a158f..1d04f76 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RUT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
@@ -25,6 +28,9 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 0b69c07..5fcffa2 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_THUBAN=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
@@ -23,6 +26,9 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 5969541..eab665c 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -102,8 +102,10 @@
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 
 /* NS16550 Configuration */
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
 #define CONFIG_SYS_NS16550_CLK		(48000000)
 #define CONFIG_SYS_NS16550_COM1		0x44e09000
 #define CONFIG_SYS_NS16550_COM4		0x481a6000
-- 
cgit v0.10.2


From e677724884c175e978b463cf941ecb9310d3b900 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 13 Jun 2016 14:01:07 +0200
Subject: arm: Fix setjmp

The setjmp/longjmp implementation did not work on thumb1 implementations
because it used instruction encodings that don't exist on thumb1 yet.

This patch limits itself to thumb1 instruction set for 32bit arm and
removes a superfluous printf along the way.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
index b8b85b7..ae738b2 100644
--- a/arch/arm/include/asm/setjmp.h
+++ b/arch/arm/include/asm/setjmp.h
@@ -43,13 +43,14 @@ static inline int setjmp(jmp_buf jmp)
 #else
 	asm volatile(
 #ifdef CONFIG_SYS_THUMB_BUILD
-		"adr r0, jmp_target + 1\n"
+		"adr r0, jmp_target\n"
+		"add r0, r0, $1\n"
 #else
 		"adr r0, jmp_target\n"
 #endif
 		"mov r1, %1\n"
 		"mov r2, sp\n"
-		"stm r1, {r0, r2, r4, r5, r6, r7}\n"
+		"stm r1!, {r0, r2, r4, r5, r6, r7}\n"
 		"b 2f\n"
 		"jmp_target: "
 		"mov %0, #1\n"
@@ -61,8 +62,6 @@ static inline int setjmp(jmp_buf jmp)
 		  "cc", "memory");
 #endif
 
-printf("%s:%d target=%#lx\n", __func__, __LINE__, jmp->target);
-
 	return r;
 }
 
@@ -84,7 +83,7 @@ static inline __noreturn void longjmp(jmp_buf jmp)
 #else
 	asm volatile(
 		"mov r1, %0\n"
-		"ldm r1, {r0, r2, r4, r5, r6, r7}\n"
+		"ldm r1!, {r0, r2, r4, r5, r6, r7}\n"
 		"mov sp, r2\n"
 		"bx r0\n"
 		:
-- 
cgit v0.10.2


From 7839f5f8092762f048076c6c7b010c10f2ee8a0b Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Fri, 17 Jun 2016 14:18:11 +0800
Subject: cmd: usb: check if_type before using this device

For legacy usb storage driver, USB_MAX_STOR_DEV is defined as 7.
If we only have one usb disk on board, `usb dev 0` is ok.
But if `usb dev 1`, still ok, then `usb read xxx` will trigger
system fault and reboot.

So check if_type before using this device.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/cmd/usb.c b/cmd/usb.c
index b83d323..58d9db2 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -800,7 +800,8 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			int dev = (int)simple_strtoul(argv[2], NULL, 10);
 			printf("\nUSB device %d: ", dev);
 			stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, dev);
-			if (stor_dev == NULL) {
+			if ((stor_dev == NULL) ||
+			    (stor_dev->if_type == IF_TYPE_UNKNOWN)) {
 				printf("unknown device\n");
 				return 1;
 			}
-- 
cgit v0.10.2


From 1e6fb0e367564d427d7c57fa7b3b972ecb7147a3 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 15 Jun 2016 13:15:46 +0800
Subject: usb: ehci: only shutdown opened controller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If the usb controller is not running, no need to shutdown it,
otherwise `usb stop` complains about:
"EHCI failed to shut down host controller".

To i.MX7D SDB, there are two usb ports, one Host, one OTG.
If we only plug one udisk to the Host port and then `usb start`,
the OTG controller for OTG port does not run actually. Then,
if `usb stop`, the OTG controller for OTG port will also be
shutdown, but it is not running.

This patch adds a check to only shutdown the running controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: "Stefan Brüns" <stefan.bruens@rwth-aachen.de>
Cc: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index fa5d584..13aa70d 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -210,6 +210,9 @@ static int ehci_shutdown(struct ehci_ctrl *ctrl)
 		return -EINVAL;
 
 	cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
+	/* If not run, directly return */
+	if (!(cmd & CMD_RUN))
+		return 0;
 	cmd &= ~(CMD_PSE | CMD_ASE);
 	ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
 	ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
-- 
cgit v0.10.2


From 6c51a3644e233bce171c19cec9cec77a77beada7 Mon Sep 17 00:00:00 2001
From: Marco Franchi <marco.franchi@nxp.com>
Date: Wed, 8 Jun 2016 15:05:31 -0300
Subject: mx6sabresd: Allow LVDS backlight to be functional after a kernel
 reboot
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
in the kernel.

This problem occurs because the kernel uses this pin in PWM mode and U-Boot
does not configure the backlight pin as GPIO functionality.

So fix the problem by explicitly configuring the backlight pin as GPIO in
U-Boot.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 54ba36b..0cf6809 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -177,13 +177,27 @@ static iomux_v3_cfg_t const rgb_pads[] = {
 	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const bl_pads[] = {
 	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+static void enable_backlight(void)
+{
+	imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
+	gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
 static void enable_rgb(struct display_info_t const *dev)
 {
 	imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
-	gpio_direction_output(DISP0_PWR_EN, 1);
+	enable_backlight();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	enable_backlight();
 }
 
 static struct i2c_pads_info i2c_pad_info1 = {
@@ -370,7 +384,7 @@ struct display_info_t const displays[] = {{
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB666,
 	.detect	= NULL,
-	.enable	= NULL,
+	.enable	= enable_lvds,
 	.mode	= {
 		.name           = "Hannstar-XGA",
 		.refresh        = 60,
-- 
cgit v0.10.2


From 0fcb85cc0cdf898019680a09200677a0beef27d9 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Wed, 15 Jun 2016 14:18:36 +0800
Subject: mx7dsabresd: Fix LCD_PWR_EN output setting

LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index c3062f1..1f4fc03 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -171,7 +171,7 @@ static enum qn_level seq[3][2] = {
 
 static enum qn_func qn_output[8] = {
 	qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
-	qn_enable
+	qn_disable
 };
 
 static void iox74lv_init(void)
-- 
cgit v0.10.2


From 85801579e10208b7466f4a7f8329b4f5d2056fff Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 15 Jun 2016 14:18:37 +0800
Subject: imx6ulevk: fix 74LV OE usage

Fix 74LV OE gpio index. gpio index is wrong,
so gpio output will not have effect, since we
use wrong GPIO5_IO18, but not correct GPIO5_IO8.

And at the end of the initialization of 74lv init, should
keep OE voltage level at LOW to make 74lv output the correct
voltage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 88d3fbd..b861122 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -66,7 +66,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IOX_SDI IMX_GPIO_NR(5, 10)
 #define IOX_STCP IMX_GPIO_NR(5, 7)
 #define IOX_SHCP IMX_GPIO_NR(5, 11)
-#define IOX_OE IMX_GPIO_NR(5, 18)
+#define IOX_OE IMX_GPIO_NR(5, 8)
 
 static iomux_v3_cfg_t const iox_pads[] = {
 	/* IOX_SDI */
@@ -154,8 +154,6 @@ static void iox74lv_init(void)
 	 * shift register will be output to pins
 	 */
 	gpio_direction_output(IOX_STCP, 1);
-
-	gpio_direction_output(IOX_OE, 1);
 };
 
 #ifdef CONFIG_SYS_I2C_MXC
-- 
cgit v0.10.2


From 288683280f18b267615d9afa86e1378727fe3405 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 15 Jun 2016 14:18:38 +0800
Subject: imx6ulevk: fix LCD_nPWREN setting

Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index b861122..112e6ab 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -117,7 +117,7 @@ static enum qn_level seq[3][2] = {
 
 static enum qn_func qn_output[8] = {
 	qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
-	qn_disable, qn_enable
+	qn_disable, qn_disable
 };
 
 static void iox74lv_init(void)
-- 
cgit v0.10.2


From 0d7cdc2abfc34125f0bc85f864d285f06675290a Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 15 Jun 2016 14:18:39 +0800
Subject: imx: mx6ulevk: change QSPI PAD DSE to 120ohm

The current pad DSE for QSPI is 60ohm. This setting cause
too strong drive to clock and data signals. Need to change
the DSE to 120ohm for better signal quality.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 112e6ab..92c9211 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -303,7 +303,7 @@ static void setup_iomux_uart(void)
 
 #define QSPI_PAD_CTRL1	\
 	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
-	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
 
 static iomux_v3_cfg_t const quadspi_pads[] = {
 	MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
-- 
cgit v0.10.2


From 0a35cc9395b7e4e5bc2b1370016f7c3156f945a4 Mon Sep 17 00:00:00 2001
From: Marco Franchi <marco.franchi@nxp.com>
Date: Fri, 10 Jun 2016 14:45:28 -0300
Subject: warp7: Fix watchdog reset

The latest version of warp7 board provides the connection of the
WDOG1_B pin to the PMIC.

Program the watchdog to enable the WDOG1_B output which causes
a POR reset.

Based on the imx7dsabresd code.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index 8c5bf9a..27e31f3 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -32,6 +32,10 @@ int dram_init(void)
 	return 0;
 }
 
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -100,3 +104,20 @@ int board_usb_phy_mode(int port)
 {
 	return USB_INIT_DEVICE;
 }
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+	return 0;
+}
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index f112fa5..8b9ed2b 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
-- 
cgit v0.10.2


From 72a868f16eeffd880b2ed77ab4bc9e072446f5a7 Mon Sep 17 00:00:00 2001
From: Marco Franchi <marco.franchi@nxp.com>
Date: Fri, 10 Jun 2016 14:56:23 -0300
Subject: warp7: Add README file

Add a README file for helping users to install U-Boot into the eMMC.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/warp7/README b/board/warp7/README
new file mode 100644
index 0000000..60339da
--- /dev/null
+++ b/board/warp7/README
@@ -0,0 +1,63 @@
+How to Update U-Boot on Warp7 board
+----------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+- dfu-util: http://dfu-util.sourceforge.net/releases/ (if you are in a
+Debian distribution then you can get it via libdfu-dev package)
+
+- libusb: http://libusb.org/ (if you are in a Debian distribution
+then you can get it via libusb-dev and libusb-1.0-0-dev)
+
+In U-Boot folder, build U-Boot for Warp7:
+
+$ make mrproper
+$ make warp7_config
+$ make
+
+This will generate the U-Boot binary called u-boot.imx.
+
+Put warp7 board in USB download mode: 
+
+Remove the CPU board from the base board then put switch 2 in the upper
+position
+
+Connect a USB to serial adapter between the host PC and warp7
+
+Connect a USB cable between the OTG warp7 port and the host PC
+
+Copy u-boot.imx to the imx_usb_loader folder.
+
+Load u-boot.imx via USB:
+
+$ sudo ./imx_usb u-boot.imx
+
+Then U-Boot should start and its messages will appear in the console program.
+
+Open a terminal program such as minicom
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+Run the DFU command:
+=> dfu 0 mmc 0
+
+Transfer u-boot.imx that will be flashed into the eMMC:
+
+$ sudo dfu-util -D u-boot.imx -a boot
+
+Then on the U-Boot prompt the following message should be seen after a
+successful upgrade:
+
+#DOWNLOAD ... OK
+Ctrl+C to exit ...
+
+Remove power from the warp7 board.
+
+Put warp7 board into normal boot mode (put the switch 2 in the lower position)
+
+Power up the board and the new updated U-Boot should boot from eMMC
-- 
cgit v0.10.2


From 67ef2c133f099d3d719058eb73aeec8f1574655c Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Thu, 9 Jun 2016 14:54:30 -0300
Subject: warp7: Fix DFU support

Currently DFU is not working.

Adjust CONFIG_SYS_MALLOC_LEN and dfu_alt_info so that we are
able to flash u-boot.imx into the eMMC via dfu using the
following method:

=> dfu 0 mmc 0

In the host PC:

dfu-util -D u-boot.imx -a boot

This is the same approach done in the mx6sl warp board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 8b9ed2b..fc0e51a 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -16,7 +16,7 @@
 #define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
@@ -28,10 +28,7 @@
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
 
 #define CONFIG_DFU_ENV_SETTINGS \
-	"dfu_alt_info=image raw 0 0x800000;"\
-		"u-boot raw 0 0x4000;"\
-		"bootimg part 0 1;"\
-		"rootfs part 0 2\0" \
+	"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_DFU_ENV_SETTINGS \
-- 
cgit v0.10.2


From 7a8f8865582583314c884e77a607f5b9dc9cf8b6 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 16 Jun 2016 12:59:34 -0600
Subject: test/py: fix printenv signon message disable code

CONFIG_VERSION_VARIABLE isn't always defined, so we can't simply look up
its value directly, or an exception will occur if it isn't defined.
Instead, we must use .get() to supply a default value if the variable
isn't defined.

Fixes: da37f006e7c5 ("tests: py: disable main_signon check for printenv cmd")
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index 22a22d1..035dbf5 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -39,7 +39,8 @@ class StateTestEnv(object):
             Nothing.
         """
 
-        if self.u_boot_console.config.buildconfig['config_version_variable'] == 'y':
+        if self.u_boot_console.config.buildconfig.get(
+                'config_version_variable', 'n') == 'y':
             with self.u_boot_console.disable_check('main_signon'):
                 response = self.u_boot_console.run_command('printenv')
         else:
-- 
cgit v0.10.2


From 7a77e909a22848f5d5820fae58c087b83e90bdbc Mon Sep 17 00:00:00 2001
From: Guillaume GARDET <guillaume.gardet@free.fr>
Date: Fri, 17 Jun 2016 11:45:37 +0200
Subject: fs: cbfs: Fix build of fs/cbfs/cbfs.c when building u-boot sandbox on
 x86 32-bit

Fix the following build errors when building sandbox on x86 32-bit:

	In file included from fs/cbfs/cbfs.c:8:0:
	include/malloc.h:364:7: error: conflicting types for 'memset'
	void* memset(void*, int, size_t);
	^
	In file included from include/compiler.h:123:0,
			from include/cbfs.h:10,
			from fs/cbfs/cbfs.c:7:
	include/linux/string.h:78:15: note: previous declaration of 'memset' was here
	extern void * memset(void *,int,__kernel_size_t);
		^
	In file included from fs/cbfs/cbfs.c:8:0:
	include/malloc.h:365:7: error: conflicting types for 'memcpy'
	void* memcpy(void*, const void*, size_t);
	^
	In file included from include/compiler.h:123:0,
			from include/cbfs.h:10,
			from fs/cbfs/cbfs.c:7:
	include/linux/string.h:81:15: note: previous declaration of 'memcpy' was here
	extern void * memcpy(void *,const void *,__kernel_size_t);
		^
	scripts/Makefile.build:280: recipe for target 'fs/cbfs/cbfs.o' failed

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index c81b611..95a48a4 100644
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
 #include <cbfs.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
-- 
cgit v0.10.2


From 9ab165d8b05706284de0ee9bd402346c54ae6b15 Mon Sep 17 00:00:00 2001
From: Petr Kulhavy <brain@jikos.cz>
Date: Sat, 18 Jun 2016 12:21:17 +0200
Subject: SPL ext: cosmetic: correct error message in spl_load_image_ext()

Correct the error message in spl_load_image_ext() when image parsing
fails. Instead of "ext4fs_read failed" print "failed to parse image
header".

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
CC: Guillaume GARDET <guillaume.gardet@free.fr>
CC: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 89ac4f4..a85dc85 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -50,7 +50,7 @@ int spl_load_image_ext(struct blk_desc *block_dev,
 
 	err = spl_parse_image_header(header);
 	if (err < 0) {
-		puts("spl: ext4fs_read failed\n");
+		puts("spl: ext: failed to parse image header\n");
 		goto end;
 	}
 
-- 
cgit v0.10.2


From 50862a5196dc3d30a939f106e296121f7a680711 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 15 Jun 2016 14:46:09 +0900
Subject: ARM: uniphier: change CPU_RELEASE_ADDR to the head of DRAM space

At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 9d14c2d..68f6c9f 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -100,7 +100,7 @@
 
 #ifdef CONFIG_ARM64
 #define CONFIG_ARMV8_MULTIENTRY
-#define CPU_RELEASE_ADDR			0x80000100
+#define CPU_RELEASE_ADDR			0x80000000
 #define COUNTER_FREQUENCY			50000000
 #define CONFIG_GICV3
 #define GICD_BASE				0x5fe00000
-- 
cgit v0.10.2


From 48efc8a25bcf859a5ba58e3025b65641adaed3cb Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 19:24:27 +0900
Subject: ARM: uniphier: introduce CONFIG_ARM_UNIPHIER_{32, 64}BIT

This will make it easier to select config options specific to
particular ARM processor generation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index ae763ad..175c9f7 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -3,35 +3,42 @@ if ARCH_UNIPHIER
 config SYS_CONFIG_NAME
 	default "uniphier"
 
+config ARCH_UNIPHIER_32BIT
+	bool
+	select CPU_V7
+
+config ARCH_UNIPHIER_64BIT
+	bool
+	select ARM64
+	select SPL_SEPARATE_BSS
+
 choice
         prompt "UniPhier SoC select"
         default ARCH_UNIPHIER_PRO4
 
 config ARCH_UNIPHIER_SLD3
 	bool "UniPhier PH1-sLD3 SoC"
-	select CPU_V7
+	select ARCH_UNIPHIER_32BIT
 
 config ARCH_UNIPHIER_LD4_SLD8
 	bool "UniPhier PH1-LD4/PH1-sLD8 SoC"
-	select CPU_V7
+	select ARCH_UNIPHIER_32BIT
 
 config ARCH_UNIPHIER_PRO4
 	bool "UniPhier PH1-Pro4 SoC"
-	select CPU_V7
+	select ARCH_UNIPHIER_32BIT
 
 config ARCH_UNIPHIER_PRO5_PXS2_LD6B
 	bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
-	select CPU_V7
+	select ARCH_UNIPHIER_32BIT
 
 config ARCH_UNIPHIER_LD11
 	bool "UniPhier PH1-LD11 SoC"
-	select ARM64
-	select SPL_SEPARATE_BSS
+	select ARCH_UNIPHIER_64BIT
 
 config ARCH_UNIPHIER_LD20
 	bool "UniPhier PH1-LD20 SoC"
-	select ARM64
-	select SPL_SEPARATE_BSS
+	select ARCH_UNIPHIER_64BIT
 
 endchoice
 
-- 
cgit v0.10.2


From 18c11986674ae917aad2465ef88cbb2c4e92b170 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 19:24:28 +0900
Subject: ARM: uniphier: move CONFIG_ARMV8_MULTIENTRY to Kconfig

I just did not notice this option had an entry in Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 175c9f7..89be0b3 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -11,6 +11,7 @@ config ARCH_UNIPHIER_64BIT
 	bool
 	select ARM64
 	select SPL_SEPARATE_BSS
+	select ARMV8_MULTIENTRY
 
 choice
         prompt "UniPhier SoC select"
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 68f6c9f..77057d0 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -99,7 +99,6 @@
 #define CONFIG_SYS_MMC_ENV_PART		1
 
 #ifdef CONFIG_ARM64
-#define CONFIG_ARMV8_MULTIENTRY
 #define CPU_RELEASE_ADDR			0x80000000
 #define COUNTER_FREQUENCY			50000000
 #define CONFIG_GICV3
-- 
cgit v0.10.2


From 51ea5a060d7bb187d344c9d24b9bfdc7570681df Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 19:24:29 +0900
Subject: ARM: uniphier: reserve memory for DRAM PHY training on PH1-LD20

The DRAM PHY layer on PH1-LD20 is able to calibrate PHY parameters
periodically.  This compensates for the voltage and temperature
deviation and improves the PHY parameter adjustment.  Instead, it
requires 64 byte scratch memory in each DRAM channel for the dynamic
training.  The memory regions must be reserved in DT before jumping
to the kernel.

The scratch area can be anywhere in each DRAM channel, but the DRAM
init code in SPL currently assigns it at the end of each channel.
So, it makes sense to reserve the regions on run-time by U-Boot
instead of statically embedding it in the DT in Linux.  Anyway,
a boot-loader should know much more about memory initialization
than the kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84cabb8..8a9cfcc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -827,6 +827,7 @@ config ARCH_UNIPHIER
 	select SPL
 	select OF_CONTROL
 	select SPL_OF_CONTROL
+	select OF_LIBFDT
 	select DM
 	select SPL_DM
 	select DM_GPIO
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 89be0b3..e256eeb 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -40,6 +40,7 @@ config ARCH_UNIPHIER_LD11
 config ARCH_UNIPHIER_LD20
 	bool "UniPhier PH1-LD20 SoC"
 	select ARCH_UNIPHIER_64BIT
+	select OF_BOARD_SETUP
 
 endchoice
 
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index ef0e2e8..489366c 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -9,6 +9,9 @@
 #include <fdtdec.h>
 #include <linux/err.h>
 
+#include "init.h"
+#include "soc-info.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static const void *get_memory_reg_prop(const void *fdt, int *lenp)
@@ -81,3 +84,40 @@ void dram_init_banksize(void)
 		      (unsigned long)gd->bd->bi_dram[i].size);
 	}
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+/*
+ * The DRAM PHY requires 64 byte scratch area in each DRAM channel
+ * for its dynamic PHY training feature.
+ */
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+	const struct uniphier_board_data *param;
+	unsigned long rsv_addr;
+	const unsigned long rsv_size = 64;
+	int ch, ret;
+
+	if (uniphier_get_soc_type() != SOC_UNIPHIER_LD20)
+		return 0;
+
+	param = uniphier_get_board_param();
+	if (!param) {
+		printf("failed to get board parameter\n");
+		return -ENODEV;
+	}
+
+	for (ch = 0; ch < param->dram_nr_ch; ch++) {
+		rsv_addr = param->dram_ch[ch].base + param->dram_ch[ch].size;
+		rsv_addr -= rsv_size;
+
+		ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
+		if (ret)
+			return -ENOSPC;
+
+		printf("   Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",
+		       rsv_addr, rsv_size);
+	}
+
+	return 0;
+}
+#endif
-- 
cgit v0.10.2


From 7c8ef0feb97586d35b0296b48903daef8c06ab21 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 19:24:30 +0900
Subject: ARM: uniphier: use the default CONFIG_BOOTDELAY=2

I do not insist on CONFIG_BOOTDELAY=3. The default value in Kconfig,
CONFIG_BOOTDELAY=2, is just fine for these boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index e7f9b15..ffcac79 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_UNIPHIER_LD11=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index d073e3d..cbc65dd 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_UNIPHIER_LD20=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 04d651d..22615a6 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index d5fc138..18f4caf 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index 285ea98..cf6d3e4 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 13f3147..0965019 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -4,7 +4,6 @@ CONFIG_ARCH_UNIPHIER_SLD3=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
-- 
cgit v0.10.2


From 5aeedebc33849efbbee2d422a4c7da8194e1b670 Mon Sep 17 00:00:00 2001
From: Angelo Dureghello <angelo@sysam.it>
Date: Sat, 21 May 2016 12:05:49 +0200
Subject: dm: add manual relocation for devices

Some architectures as m68k still need to use CONFIG_NEEDS_MANUAL_RELOC,
and are not still using the device tree.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 13c2713..95886ad 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -122,6 +122,20 @@ void fix_uclass(void)
 			entry->ops += gd->reloc_off;
 	}
 }
+
+void fix_devices(void)
+{
+	struct driver_info *dev =
+		ll_entry_start(struct driver_info, driver_info);
+	const int n_ents = ll_entry_count(struct driver_info, driver_info);
+	struct driver_info *entry;
+
+	for (entry = dev; entry != dev + n_ents; entry++) {
+		if (entry->platdata)
+			entry->platdata += gd->reloc_off;
+	}
+}
+
 #endif
 
 int dm_init(void)
@@ -137,6 +151,7 @@ int dm_init(void)
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	fix_drivers();
 	fix_uclass();
+	fix_devices();
 #endif
 
 	ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST);
-- 
cgit v0.10.2


From fc76b698736efa9d52e06aa09c03dc8ef10fd581 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 23 May 2016 09:54:56 +0200
Subject: gpio: pca953x: Fix register reading past 8th GPIO

A bug in the pca953x driver prevents correct reading of GPIO input
values beyond the 8th GPIO; all values are reported as zero. Setting of
GPIO output values is not affected.

This patch fixes the reading behavior.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 065b181..0410add 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -148,11 +148,13 @@ static int pca953x_get_value(struct udevice *dev, unsigned offset)
 	int ret;
 	u8 val = 0;
 
+	int off = offset % BANK_SZ;
+
 	ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
 	if (ret)
 		return ret;
 
-	return (val >> offset) & 0x1;
+	return (val >> off) & 0x1;
 }
 
 static int pca953x_set_value(struct udevice *dev, unsigned offset,
-- 
cgit v0.10.2


From 6feed2a5aefb7fd0ac443a50bfe00625000bdd34 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Mon, 23 May 2016 05:40:55 -0400
Subject: lib/libfdt/: General aesthetic/style fixes.

A number of style fixes across the files in this directory, including:

 * Correct invalid kernel-doc content.
 * Tidy up massive comment in fdt_region.c.
 * Use correct spelling of "U-Boot".
 * Replace tests of "! <var>" with "!<var>".
 * Replace "libfdt_env.h" with <libfdt_env.h>.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile
index 934d614..8b86c15 100644
--- a/lib/libfdt/Makefile
+++ b/lib/libfdt/Makefile
@@ -5,5 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o \
-	fdt_empty_tree.o fdt_addresses.o fdt_region.o
+obj-y += \
+	fdt.o \
+	fdt_ro.o \
+	fdt_rw.o \
+	fdt_strerror.o \
+	fdt_sw.o \
+	fdt_wip.o \
+	fdt_empty_tree.o \
+	fdt_addresses.o \
+	fdt_region.o
diff --git a/lib/libfdt/README b/lib/libfdt/README
index e059876..db40ab2 100644
--- a/lib/libfdt/README
+++ b/lib/libfdt/README
@@ -1,5 +1,5 @@
 The libfdt functionality was written by David Gibson.  The original
-source came from the git repository:
+source came from the Git repository:
 
 URL:		git://ozlabs.org/home/dgibson/git/libfdt.git
 
@@ -11,13 +11,15 @@ commit		857f54e79f74429af20c2b5ecc00ee98af6a3b8b
 tree		2f648f0f88225a51ded452968d28b4402df8ade0
 parent		07a12a08005f3b5cd9337900a6551e450c07b515
 
-To adapt for u-boot usage, only the applicable files were copied and
-imported into the u-boot git repository.
+To adapt for U-Boot usage, only the applicable files were copied and
+imported into the U-Boot Git repository.
+
 Omitted:
-* GPL - u-boot comes with a copy of the GPL license
-* test subdirectory - not directly useful for u-boot
 
-After importing, other customizations were performed.  See the git log
-for details.
+  * GPL - U-Boot comes with a copy of the GPL license
+  * test subdirectory - not directly useful for U-Boot
+
+After importing, other customizations were performed.  See the
+"git log" for details.
 
 Jerry Van Baren
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index e146aba..96017a1 100644
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2006 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c
index 76054d9..b6bc66e 100644
--- a/lib/libfdt/fdt_addresses.c
+++ b/lib/libfdt/fdt_addresses.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2014 David Gibson <david@gibson.dropbear.id.au>
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
diff --git a/lib/libfdt/fdt_empty_tree.c b/lib/libfdt/fdt_empty_tree.c
index 34f1c84..6fde1eb 100644
--- a/lib/libfdt/fdt_empty_tree.c
+++ b/lib/libfdt/fdt_empty_tree.c
@@ -3,8 +3,7 @@
  * Copyright (C) 2012 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
-
+#include <libfdt_env.h>
 #include <fdt.h>
 #include <libfdt.h>
 
diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c
index 747d8bb..d2ce4c1 100644
--- a/lib/libfdt/fdt_region.c
+++ b/lib/libfdt/fdt_region.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
 
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
@@ -18,14 +18,13 @@
 
 /**
  * fdt_add_region() - Add a new region to our list
+ * @info:	State information
+ * @offset:	Start offset of region
+ * @size:	Size of region
  *
  * The region is added if there is space, but in any case we increment the
  * count. If permitted, and the new region overlaps the last one, we merge
  * them.
- *
- * @info: State information
- * @offset: Start offset of region
- * @size: Size of region
  */
 static int fdt_add_region(struct fdt_region_state *info, int offset, int size)
 {
@@ -119,6 +118,8 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
 
 /**
  * fdt_include_supernodes() - Include supernodes required by this node
+ * @info:	State information
+ * @depth:	Current stack depth
  *
  * When we decided to include a node or property which is not at the top
  * level, this function forces the inclusion of higher level nodes. For
@@ -131,9 +132,6 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
  *
  * If we decide to include testing then we need the root node to have a valid
  * tree. This function adds those regions.
- *
- * @info: State information
- * @depth: Current stack depth
  */
 static int fdt_include_supernodes(struct fdt_region_state *info, int depth)
 {
@@ -203,72 +201,78 @@ int fdt_first_region(const void *fdt,
 			       path, path_len, flags, info);
 }
 
-/*
- * Theory of operation
+/***********************************************************************
+ *
+ *	Theory of operation
+ *
+ * Note: in this description 'included' means that a node (or other part
+ * of the tree) should be included in the region list, i.e. it will have
+ * a region which covers its part of the tree.
+ *
+ * This function maintains some state from the last time it is called.
+ * It checks the next part of the tree that it is supposed to look at
+ * (p.nextoffset) to see if that should be included or not. When it
+ * finds something to include, it sets info->start to its offset. This
+ * marks the start of the region we want to include.
+ *
+ * Once info->start is set to the start (i.e. not -1), we continue
+ * scanning until we find something that we don't want included. This
+ * will be the end of a region. At this point we can close off the
+ * region and add it to the list. So we do so, and reset info->start
+ * to -1.
+ *
+ * One complication here is that we want to merge regions. So when we
+ * come to add another region later, we may in fact merge it with the
+ * previous one if one ends where the other starts.
+ *
+ * The function fdt_add_region() will return -1 if it fails to add the
+ * region, because we already have a region ready to be returned, and
+ * the new one cannot be merged in with it. In this case, we must return
+ * the region we found, and wait for another call to this function.
+ * When it comes, we will repeat the processing of the tag and again
+ * try to add a region. This time it will succeed.
+ *
+ * The current state of the pointers (stack, offset, etc.) is maintained
+ * in a ptrs member. At the start of every loop iteration we make a copy
+ * of it.  The copy is then updated as the tag is processed. Only if we
+ * get to the end of the loop iteration (and successfully call
+ * fdt_add_region() if we need to) can we commit the changes we have
+ * made to these pointers. For example, if we see an FDT_END_NODE tag,
+ * we will decrement the depth value. But if we need to add a region
+ * for this tag (let's say because the previous tag is included and this
+ * FDT_END_NODE tag is not included) then we will only commit the result
+ * if we were able to add the region. That allows us to retry again next
+ * time.
+ *
+ * We keep track of a variable called 'want' which tells us what we want
+ * to include when there is no specific information provided by the
+ * h_include function for a particular property. This basically handles
+ * the inclusion of properties which are pulled in by virtue of the node
+ * they are in. So if you include a node, its properties are also
+ * included.  In this case 'want' will be WANT_NODES_AND_PROPS. The
+ * FDT_REG_DIRECT_SUBNODES feature also makes use of 'want'. While we
+ * are inside the subnode, 'want' will be set to WANT_NODES_ONLY, so
+ * that only the subnode's FDT_BEGIN_NODE and FDT_END_NODE tags will be
+ * included, and properties will be skipped. If WANT_NOTHING is
+ * selected, then we will just rely on what the h_include() function
+ * tells us.
  *
+ * Using 'want' we work out 'include', which tells us whether this
+ * current tag should be included or not. As you can imagine, if the
+ * value of 'include' changes, that means we are on a boundary between
+ * nodes to include and nodes to exclude. At this point we either close
+ * off a previous region and add it to the list, or mark the start of a
+ * new region.
  *
+ * Apart from the nodes, we have mem_rsvmap, the FDT_END tag and the
+ * string list. Each of these dealt with as a whole (i.e. we create a
+ * region for each if it is to be included). For mem_rsvmap we don't
+ * allow it to merge with the first struct region. For the stringlist,
+ * we don't allow it to merge with the last struct region (which
+ * contains at minimum the FDT_END tag).
  *
+ *********************************************************************/
 
-Note: in this description 'included' means that a node (or other part of
-the tree) should be included in the region list, i.e. it will have a region
-which covers its part of the tree.
-
-This function maintains some state from the last time it is called. It
-checks the next part of the tree that it is supposed to look at
-(p.nextoffset) to see if that should be included or not. When it finds
-something to include, it sets info->start to its offset. This marks the
-start of the region we want to include.
-
-Once info->start is set to the start (i.e. not -1), we continue scanning
-until we find something that we don't want included. This will be the end
-of a region. At this point we can close off the region and add it to the
-list. So we do so, and reset info->start to -1.
-
-One complication here is that we want to merge regions. So when we come to
-add another region later, we may in fact merge it with the previous one if
-one ends where the other starts.
-
-The function fdt_add_region() will return -1 if it fails to add the region,
-because we already have a region ready to be returned, and the new one
-cannot be merged in with it. In this case, we must return the region we
-found, and wait for another call to this function. When it comes, we will
-repeat the processing of the tag and again try to add a region. This time it
-will succeed.
-
-The current state of the pointers (stack, offset, etc.) is maintained in
-a ptrs member. At the start of every loop iteration we make a copy of it.
-The copy is then updated as the tag is processed. Only if we get to the end
-of the loop iteration (and successfully call fdt_add_region() if we need
-to) can we commit the changes we have made to these pointers. For example,
-if we see an FDT_END_NODE tag we will decrement the depth value. But if we
-need to add a region for this tag (let's say because the previous tag is
-included and this FDT_END_NODE tag is not included) then we will only commit
-the result if we were able to add the region. That allows us to retry again
-next time.
-
-We keep track of a variable called 'want' which tells us what we want to
-include when there is no specific information provided by the h_include
-function for a particular property. This basically handles the inclusion of
-properties which are pulled in by virtue of the node they are in. So if you
-include a node, its properties are also included. In this case 'want' will
-be WANT_NODES_AND_PROPS. The FDT_REG_DIRECT_SUBNODES feature also makes use
-of 'want'. While we are inside the subnode, 'want' will be set to
-WANT_NODES_ONLY, so that only the subnode's FDT_BEGIN_NODE and FDT_END_NODE
-tags will be included, and properties will be skipped. If WANT_NOTHING is
-selected, then we will just rely on what the h_include() function tells us.
-
-Using 'want' we work out 'include', which tells us whether this current tag
-should be included or not. As you can imagine, if the value of 'include'
-changes, that means we are on a boundary between nodes to include and nodes
-to exclude. At this point we either close off a previous region and add it
-to the list, or mark the start of a new region.
-
-Apart from the nodes, we have mem_rsvmap, the FDT_END tag and the string
-list. Each of these dealt with as a whole (i.e. we create a region for each
-if it is to be included). For mem_rsvmap we don't allow it to merge with
-the first struct region. For the stringlist we don't allow it to merge with
-the last struct region (which contains at minimum the FDT_END tag).
-*/
 int fdt_next_region(const void *fdt,
 		int (*h_include)(void *priv, const void *fdt, int offset,
 				 int type, const char *data, int size),
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 7b0777b..12214c2 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2006 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
@@ -19,7 +19,7 @@ static int _fdt_nodename_eq(const void *fdt, int offset,
 {
 	const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1);
 
-	if (! p)
+	if (!p)
 		/* short match */
 		return 0;
 
@@ -115,7 +115,7 @@ int fdt_subnode_offset(const void *fdt, int parentoffset,
 
 /*
  * Find the next of path seperator, note we need to search for both '/' and ':'
- * and then take the first one so that we do the rigth thing for e.g.
+ * and then take the first one so that we do the right thing for e.g.
  * "foo/bar:option" and "bar:option/otheroption", both of which happen, so
  * first searching for either ':' or '/' does not work.
  */
@@ -163,7 +163,7 @@ int fdt_path_offset(const void *fdt, const char *path)
 		if (*p == '\0' || *p == ':')
 			return offset;
 		q = fdt_path_next_seperator(p);
-		if (! q)
+		if (!q)
 			q = end;
 
 		offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
@@ -273,7 +273,7 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
 	const struct fdt_property *prop;
 
 	prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp);
-	if (! prop)
+	if (!prop)
 		return NULL;
 
 	return prop->data;
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 1a358a8..e7321cc 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2006 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
@@ -168,7 +168,7 @@ static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
 	int err;
 
 	*prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
-	if (! (*prop))
+	if (!(*prop))
 		return oldlen;
 
 	if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
@@ -283,7 +283,7 @@ int fdt_delprop(void *fdt, int nodeoffset, const char *name)
 	FDT_RW_CHECK_HEADER(fdt);
 
 	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
-	if (! prop)
+	if (!prop)
 		return len;
 
 	proplen = sizeof(*prop) + FDT_TAGALIGN(len);
diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c
index 2f3cc24..3b7e168 100644
--- a/lib/libfdt/fdt_strerror.c
+++ b/lib/libfdt/fdt_strerror.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2006 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c
index 345a3ac..70fd026 100644
--- a/lib/libfdt/fdt_sw.c
+++ b/lib/libfdt/fdt_sw.c
@@ -3,8 +3,7 @@
  * Copyright (C) 2006 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
-
+#include <libfdt_env.h>
 #include <fdt.h>
 #include <libfdt.h>
 
diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c
index 3f2dfa5..9fe9886 100644
--- a/lib/libfdt/fdt_wip.c
+++ b/lib/libfdt/fdt_wip.c
@@ -3,7 +3,7 @@
  * Copyright (C) 2006 David Gibson, IBM Corporation.
  * SPDX-License-Identifier:	GPL-2.0+ BSD-2-Clause
  */
-#include "libfdt_env.h"
+#include <libfdt_env.h>
 
 #ifndef USE_HOSTCC
 #include <fdt.h>
@@ -21,7 +21,7 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
 	int proplen;
 
 	propval = fdt_getprop_w(fdt, nodeoffset, name, &proplen);
-	if (! propval)
+	if (!propval)
 		return proplen;
 
 	if (proplen != len)
@@ -45,7 +45,7 @@ int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
 	int len;
 
 	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
-	if (! prop)
+	if (!prop)
 		return len;
 
 	_fdt_nop_region(prop, len + sizeof(*prop));
-- 
cgit v0.10.2


From 21047b31f1d7db585bbb58ae2b733e3987b23e61 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 25 May 2016 15:18:10 +0200
Subject: sandbox: gpio: doc: Fix parameter documentation

The documentation of parameters in arch/sandbox/include/asm/gpio.h is
either missing or faulty.

This patch corrects the documentation.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
index 427af2c..73b42f0 100644
--- a/arch/sandbox/include/asm/gpio.h
+++ b/arch/sandbox/include/asm/gpio.h
@@ -26,7 +26,8 @@
 /**
  * Return the simulated value of a GPIO (used only in sandbox test code)
  *
- * @param gp	GPIO number
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
  * @return -1 on error, 0 if GPIO is low, >0 if high
  */
 int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
@@ -34,8 +35,9 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
 /**
  * Set the simulated value of a GPIO (used only in sandbox test code)
  *
- * @param gp	GPIO number
- * @param value	value to set (0 for low, non-zero for high)
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
+ * @param value		value to set (0 for low, non-zero for high)
  * @return -1 on error, 0 if ok
  */
 int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
@@ -63,7 +65,8 @@ int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset);
 /**
  * Return the simulated direction of a GPIO (used only in sandbox test code)
  *
- * @param gp	GPIO number
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
  * @return -1 on error, 0 if GPIO is input, >0 if output
  */
 int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
@@ -71,8 +74,9 @@ int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
 /**
  * Set the simulated direction of a GPIO (used only in sandbox test code)
  *
- * @param gp	GPIO number
- * @param output 0 to set as input, 1 to set as output
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
+ * @param output 	0 to set as input, 1 to set as output
  * @return -1 on error, 0 if ok
  */
 int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,
-- 
cgit v0.10.2


From 769d52ef0f04812fd65ef2f3ab921ad2e8562ab1 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 17 Jun 2016 09:43:56 -0600
Subject: mailbox: rename headers

Rename mailbox*.h to match the naming convention requested during review
of the new reset subsystem.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
index 73fa328..40f851d 100644
--- a/drivers/mailbox/mailbox-uclass.c
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <fdtdec.h>
-#include <mailbox_client.h>
-#include <mailbox_uclass.h>
+#include <mailbox.h>
+#include <mailbox-uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/drivers/mailbox/sandbox-mbox-test.c b/drivers/mailbox/sandbox-mbox-test.c
index 02d161a..8351522 100644
--- a/drivers/mailbox/sandbox-mbox-test.c
+++ b/drivers/mailbox/sandbox-mbox-test.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <dm.h>
-#include <mailbox_client.h>
+#include <mailbox.h>
 #include <asm/io.h>
 
 struct sandbox_mbox_test {
diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c
index 1b7ac23..530c62c 100644
--- a/drivers/mailbox/sandbox-mbox.c
+++ b/drivers/mailbox/sandbox-mbox.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <dm.h>
-#include <mailbox_uclass.h>
+#include <mailbox-uclass.h>
 #include <asm/io.h>
 #include <asm/mbox.h>
 
diff --git a/include/mailbox-uclass.h b/include/mailbox-uclass.h
new file mode 100644
index 0000000..6ec62e5
--- /dev/null
+++ b/include/mailbox-uclass.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_UCLASS_H
+#define _MAILBOX_UCLASS_H
+
+/* See mailbox.h for background documentation. */
+
+#include <mailbox.h>
+
+struct udevice;
+
+/**
+ * struct mbox_ops - The functions that a mailbox driver must implement.
+ */
+struct mbox_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
+	 *
+	 * The mailbox core calls this function as the first step in
+	 * implementing a client's mbox_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the mailbox core will use
+	 * a default implementation, which assumes #mbox-cells = <1>, and that
+	 * the DT cell contains a simple integer channel ID.
+	 *
+	 * At present, the mailbox API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @chan:	The channel to hold the translation result.
+	 * @args:	The mailbox specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct mbox_chan *chan,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated channel.
+	 *
+	 * The mailbox core calls this function as the second step in
+	 * implementing a client's mbox_get_by_*() call, following a successful
+	 * xxx_xlate() call.
+	 *
+	 * @chan:	The channel to request; this has been filled in by a
+	 *		previoux xxx_xlate() function call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct mbox_chan *chan);
+	/**
+	 * free - Free a previously requested channel.
+	 *
+	 * This is the implementation of the client mbox_free() API.
+	 *
+	 * @chan:	The channel to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct mbox_chan *chan);
+	/**
+	* send - Send a message over a mailbox channel
+	*
+	* @chan:	The channel to send to the message to.
+	* @data:	A pointer to the message to send.
+	* @return 0 if OK, or a negative error code.
+	*/
+	int (*send)(struct mbox_chan *chan, const void *data);
+	/**
+	* recv - Receive any available message from the channel.
+	*
+	* This function does not block. If not message is immediately
+	* available, the function should return an error.
+	*
+	* @chan:	The channel to receive to the message from.
+	* @data:	A pointer to the buffer to hold the received message.
+	* @return 0 if OK, -ENODATA if no message was available, or a negative
+	* error code.
+	*/
+	int (*recv)(struct mbox_chan *chan, void *data);
+};
+
+#endif
diff --git a/include/mailbox.h b/include/mailbox.h
new file mode 100644
index 0000000..a92a1a5
--- /dev/null
+++ b/include/mailbox.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_H
+#define _MAILBOX_H
+
+/**
+ * A mailbox is a hardware mechanism for transferring small fixed-size messages
+ * and/or notifications between the CPU on which U-Boot runs and some other
+ * device such as an auxiliary CPU running firmware or a hardware module.
+ *
+ * Data transfer is optional; a mailbox may consist solely of a notification
+ * mechanism. When data transfer is implemented, it is via HW registers or
+ * FIFOs, rather than via RAM-based buffers. The mailbox API generally
+ * implements any communication protocol enforced solely by hardware, and
+ * leaves any higher-level protocols to other layers.
+ *
+ * A mailbox channel is a bi-directional mechanism that can send a message or
+ * notification to a single specific remote entity, and receive messages or
+ * notifications from that entity. The size, content, and format of such
+ * messages is defined by the mailbox implementation, or the remote entity with
+ * which it communicates; there is no general standard at this API level.
+ *
+ * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
+ * will often implement multiple separate mailbox channels, since the hardware
+ * it manages often has this capability. mailbox-uclass.h describes the
+ * interface which mailbox providers must implement.
+ *
+ * Mailbox consumers/clients generate and send, or receive and process,
+ * messages. This header file describes the API used by clients.
+ */
+
+struct udevice;
+
+/**
+ * struct mbox_chan - A handle to a single mailbox channel.
+ *
+ * Clients provide storage for channels. The content of the channel structure
+ * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
+ * is initialized by "get"ing the mailbox. The channel struct is passed to all
+ * other mailbox APIs to identify which mailbox to operate upon.
+ *
+ * @dev: The device which implements the mailbox.
+ * @id: The mailbox channel ID within the provider.
+ *
+ * Currently, the mailbox API assumes that a single integer ID is enough to
+ * identify and configure any mailbox channel for any mailbox provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow mailbox providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct mbox_chan {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+/**
+ * mbox_get_by_index - Get/request a mailbox by integer index
+ *
+ * This looks up and requests a mailbox channel. The index is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel indices to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the mailbox channel to request, within the
+ *		client's list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
+
+/**
+ * mbox_get_by_name - Get/request a mailbox by name
+ *
+ * This looks up and requests a mailbox channel. The name is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel names to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the mailbox channel to request, within the client's
+ *		list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan);
+
+/**
+ * mbox_free - Free a previously requested mailbox channel.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_free(struct mbox_chan *chan);
+
+/**
+ * mbox_send - Send a message over a mailbox channel
+ *
+ * This function will send a message to the remote entity. It may return before
+ * the remote entity has received and/or processed the message.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the message to transfer. The format and size of
+ *		the memory region pointed at by @data is determined by the
+ *		mailbox provider. Providers that solely transfer notifications
+ *		will ignore this parameter.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_send(struct mbox_chan *chan, const void *data);
+
+/**
+ * mbox_recv - Receive any available message from a mailbox channel
+ *
+ * This function will wait (up to the specified @timeout_us) for a message to
+ * be sent by the remote entity, and write the content of any such message
+ * into a caller-provided buffer.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the buffer to receive the message. The format and
+ *		size of the memory region pointed at by @data is determined by
+ *		the mailbox provider. Providers that solely transfer
+ *		notifications will ignore this parameter.
+ * @timeout_us:	The maximum time to wait for a message to be available, in
+ *		micro-seconds. A value of 0 does not wait at all.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative error
+ * code.
+ */
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
+
+#endif
diff --git a/include/mailbox_client.h b/include/mailbox_client.h
deleted file mode 100644
index 8345ea0..0000000
--- a/include/mailbox_client.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _MAILBOX_CLIENT_H
-#define _MAILBOX_CLIENT_H
-
-/**
- * A mailbox is a hardware mechanism for transferring small fixed-size messages
- * and/or notifications between the CPU on which U-Boot runs and some other
- * device such as an auxiliary CPU running firmware or a hardware module.
- *
- * Data transfer is optional; a mailbox may consist solely of a notification
- * mechanism. When data transfer is implemented, it is via HW registers or
- * FIFOs, rather than via RAM-based buffers. The mailbox API generally
- * implements any communication protocol enforced solely by hardware, and
- * leaves any higher-level protocols to other layers.
- *
- * A mailbox channel is a bi-directional mechanism that can send a message or
- * notification to a single specific remote entity, and receive messages or
- * notifications from that entity. The size, content, and format of such
- * messages is defined by the mailbox implementation, or the remote entity with
- * which it communicates; there is no general standard at this API level.
- *
- * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
- * will often implement multiple separate mailbox channels, since the hardware
- * it manages often has this capability. mailbox_uclass.h describes the
- * interface which mailbox providers must implement.
- *
- * Mailbox consumers/clients generate and send, or receive and process,
- * messages. This header file describes the API used by clients.
- */
-
-struct udevice;
-
-/**
- * struct mbox_chan - A handle to a single mailbox channel.
- *
- * Clients provide storage for channels. The content of the channel structure
- * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
- * is initialized by "get"ing the mailbox. The channel struct is passed to all
- * other mailbox APIs to identify which mailbox to operate upon.
- *
- * @dev: The device which implements the mailbox.
- * @id: The mailbox channel ID within the provider.
- *
- * Currently, the mailbox API assumes that a single integer ID is enough to
- * identify and configure any mailbox channel for any mailbox provider. If this
- * assumption becomes invalid in the future, the struct could be expanded to
- * either (a) add more fields to allow mailbox providers to store additional
- * information, or (b) replace the id field with an opaque pointer, which the
- * provider would dynamically allocated during its .of_xlate op, and process
- * during is .request op. This may require the addition of an extra op to clean
- * up the allocation.
- */
-struct mbox_chan {
-	struct udevice *dev;
-	/*
-	 * Written by of_xlate. We assume a single id is enough for now. In the
-	 * future, we might add more fields here.
-	 */
-	unsigned long id;
-};
-
-/**
- * mbox_get_by_index - Get/request a mailbox by integer index
- *
- * This looks up and requests a mailbox channel. The index is relative to the
- * client device; each device is assumed to have n mailbox channels associated
- * with it somehow, and this function finds and requests one of them. The
- * mapping of client device channel indices to provider channels may be via
- * device-tree properties, board-provided mapping tables, or some other
- * mechanism.
- *
- * @dev:	The client device.
- * @index:	The index of the mailbox channel to request, within the
- *		client's list of channels.
- * @chan	A pointer to a channel object to initialize.
- * @return 0 if OK, or a negative error code.
- */
-int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
-
-/**
- * mbox_get_by_name - Get/request a mailbox by name
- *
- * This looks up and requests a mailbox channel. The name is relative to the
- * client device; each device is assumed to have n mailbox channels associated
- * with it somehow, and this function finds and requests one of them. The
- * mapping of client device channel names to provider channels may be via
- * device-tree properties, board-provided mapping tables, or some other
- * mechanism.
- *
- * @dev:	The client device.
- * @name:	The name of the mailbox channel to request, within the client's
- *		list of channels.
- * @chan	A pointer to a channel object to initialize.
- * @return 0 if OK, or a negative error code.
- */
-int mbox_get_by_name(struct udevice *dev, const char *name,
-		     struct mbox_chan *chan);
-
-/**
- * mbox_free - Free a previously requested mailbox channel.
- *
- * @chan:	A channel object that was previously successfully requested by
- *		calling mbox_get_by_*().
- * @return 0 if OK, or a negative error code.
- */
-int mbox_free(struct mbox_chan *chan);
-
-/**
- * mbox_send - Send a message over a mailbox channel
- *
- * This function will send a message to the remote entity. It may return before
- * the remote entity has received and/or processed the message.
- *
- * @chan:	A channel object that was previously successfully requested by
- *		calling mbox_get_by_*().
- * @data:	A pointer to the message to transfer. The format and size of
- *		the memory region pointed at by @data is determined by the
- *		mailbox provider. Providers that solely transfer notifications
- *		will ignore this parameter.
- * @return 0 if OK, or a negative error code.
- */
-int mbox_send(struct mbox_chan *chan, const void *data);
-
-/**
- * mbox_recv - Receive any available message from a mailbox channel
- *
- * This function will wait (up to the specified @timeout_us) for a message to
- * be sent by the remote entity, and write the content of any such message
- * into a caller-provided buffer.
- *
- * @chan:	A channel object that was previously successfully requested by
- *		calling mbox_get_by_*().
- * @data:	A pointer to the buffer to receive the message. The format and
- *		size of the memory region pointed at by @data is determined by
- *		the mailbox provider. Providers that solely transfer
- *		notifications will ignore this parameter.
- * @timeout_us:	The maximum time to wait for a message to be available, in
- *		micro-seconds. A value of 0 does not wait at all.
- * @return 0 if OK, -ENODATA if no message was available, or a negative error
- * code.
- */
-int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
-
-#endif
diff --git a/include/mailbox_uclass.h b/include/mailbox_uclass.h
deleted file mode 100644
index 6a2994c..0000000
--- a/include/mailbox_uclass.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _MAILBOX_UCLASS_H
-#define _MAILBOX_UCLASS_H
-
-/* See mailbox_client.h for background documentation. */
-
-#include <mailbox_client.h>
-
-struct udevice;
-
-/**
- * struct mbox_ops - The functions that a mailbox driver must implement.
- */
-struct mbox_ops {
-	/**
-	 * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
-	 *
-	 * The mailbox core calls this function as the first step in
-	 * implementing a client's mbox_get_by_*() call.
-	 *
-	 * If this function pointer is set to NULL, the mailbox core will use
-	 * a default implementation, which assumes #mbox-cells = <1>, and that
-	 * the DT cell contains a simple integer channel ID.
-	 *
-	 * At present, the mailbox API solely supports device-tree. If this
-	 * changes, other xxx_xlate() functions may be added to support those
-	 * other mechanisms.
-	 *
-	 * @chan:	The channel to hold the translation result.
-	 * @args:	The mailbox specifier values from device tree.
-	 * @return 0 if OK, or a negative error code.
-	 */
-	int (*of_xlate)(struct mbox_chan *chan,
-			struct fdtdec_phandle_args *args);
-	/**
-	 * request - Request a translated channel.
-	 *
-	 * The mailbox core calls this function as the second step in
-	 * implementing a client's mbox_get_by_*() call, following a successful
-	 * xxx_xlate() call.
-	 *
-	 * @chan:	The channel to request; this has been filled in by a
-	 *		previoux xxx_xlate() function call.
-	 * @return 0 if OK, or a negative error code.
-	 */
-	int (*request)(struct mbox_chan *chan);
-	/**
-	 * free - Free a previously requested channel.
-	 *
-	 * This is the implementation of the client mbox_free() API.
-	 *
-	 * @chan:	The channel to free.
-	 * @return 0 if OK, or a negative error code.
-	 */
-	int (*free)(struct mbox_chan *chan);
-	/**
-	* send - Send a message over a mailbox channel
-	*
-	* @chan:	The channel to send to the message to.
-	* @data:	A pointer to the message to send.
-	* @return 0 if OK, or a negative error code.
-	*/
-	int (*send)(struct mbox_chan *chan, const void *data);
-	/**
-	* recv - Receive any available message from the channel.
-	*
-	* This function does not block. If not message is immediately
-	* available, the function should return an error.
-	*
-	* @chan:	The channel to receive to the message from.
-	* @data:	A pointer to the buffer to hold the received message.
-	* @return 0 if OK, -ENODATA if no message was available, or a negative
-	* error code.
-	*/
-	int (*recv)(struct mbox_chan *chan, void *data);
-};
-
-#endif
-- 
cgit v0.10.2


From 0f67e2395be44db2c1bef17b6ada2e46221908ed Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 17 Jun 2016 09:43:57 -0600
Subject: mailbox: add Tegra186 HSP driver

Tegra186's HSP module implements doorbells, mailboxes, semaphores, and
shared interrupts. This patch provides a driver for HSP, and hooks it
into the mailbox API. Currently, only doorbells are supported.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index 18b6a26..fce34fa6 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -1,6 +1,7 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/tegra-hsp.h>
 
 / {
 	compatible = "nvidia,tegra186";
@@ -40,6 +41,18 @@
 		status = "disabled";
 	};
 
+	hsp: hsp@3c00000 {
+		compatible = "nvidia,tegra186-hsp";
+		reg = <0x0 0x03c00000 0x0 0xa0000>;
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+		nvidia,num-SM = <0x8>;
+		nvidia,num-AS = <0x2>;
+		nvidia,num-SS = <0x2>;
+		nvidia,num-DB = <0x7>;
+		nvidia,num-SI = <0x8>;
+		#mbox-cells = <1>;
+	};
+
 	gpio@c2f0000 {
 		compatible = "nvidia,tegra186-gpio-aon";
 		reg-names = "security", "gpio";
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b18a12e..f4affa5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -56,8 +56,10 @@ config TEGRA210
 
 config TEGRA186
 	bool "Tegra186 family"
+	select DM_MAILBOX
 	select TEGRA186_GPIO
 	select TEGRA_ARMV8_COMMON
+	select TEGRA_HSP
 
 endchoice
 
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 9087512..9649b70 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -17,4 +17,11 @@ config SANDBOX_MBOX
 	  Enable support for a test mailbox implementation, which simply echos
 	  back a modified version of any message that is sent.
 
+config TEGRA_HSP
+	bool "Enable Tegra HSP controller support"
+	depends on DM_MAILBOX && TEGRA
+	help
+	  This enables support for the NVIDIA Tegra HSP Hw module, which
+	  implements doorbells, mailboxes, semaphores, and shared interrupts.
+
 endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index bbae4de..155dbeb 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
+obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
new file mode 100644
index 0000000..5c781a5
--- /dev/null
+++ b/drivers/mailbox/tegra-hsp.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <dt-bindings/mailbox/tegra-hsp.h>
+
+#define TEGRA_HSP_DB_REG_TRIGGER	0x0
+#define TEGRA_HSP_DB_REG_ENABLE		0x4
+#define TEGRA_HSP_DB_REG_RAW		0x8
+#define TEGRA_HSP_DB_REG_PENDING	0xc
+
+#define TEGRA_HSP_DB_ID_CCPLEX		1
+#define TEGRA_HSP_DB_ID_BPMP		3
+#define TEGRA_HSP_DB_ID_NUM		7
+
+struct tegra_hsp {
+	fdt_addr_t regs;
+	uint32_t db_base;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
+			       uint32_t reg)
+{
+	return (uint32_t *)(thsp->regs + thsp->db_base + (db_id * 0x100) + reg);
+}
+
+static uint32_t tegra_hsp_readl(struct tegra_hsp *thsp, uint32_t db_id,
+				uint32_t reg)
+{
+	uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
+	return readl(r);
+}
+
+static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
+			     uint32_t db_id, uint32_t reg)
+{
+	uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
+
+	writel(val, r);
+	readl(r);
+}
+
+static int tegra_hsp_db_id(ulong chan_id)
+{
+	switch (chan_id) {
+	case TEGRA_HSP_MASTER_BPMP:
+		return TEGRA_HSP_DB_ID_BPMP;
+	default:
+		debug("Invalid channel ID\n");
+		return -EINVAL;
+	}
+}
+
+static int tegra_hsp_request(struct mbox_chan *chan)
+{
+	int db_id;
+
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	db_id = tegra_hsp_db_id(chan->id);
+	if (db_id < 0) {
+		debug("tegra_hsp_db_id() failed: %d\n", db_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tegra_hsp_free(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return 0;
+}
+
+static int tegra_hsp_send(struct mbox_chan *chan, const void *data)
+{
+	struct tegra_hsp *thsp = dev_get_priv(chan->dev);
+	int db_id;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	db_id = tegra_hsp_db_id(chan->id);
+	tegra_hsp_writel(thsp, 1, db_id, TEGRA_HSP_DB_REG_TRIGGER);
+
+	return 0;
+}
+
+static int tegra_hsp_recv(struct mbox_chan *chan, void *data)
+{
+	struct tegra_hsp *thsp = dev_get_priv(chan->dev);
+	uint32_t db_id = TEGRA_HSP_DB_ID_CCPLEX;
+	uint32_t val;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	val = tegra_hsp_readl(thsp, db_id, TEGRA_HSP_DB_REG_RAW);
+	if (!(val & BIT(chan->id)))
+		return -ENODATA;
+
+	tegra_hsp_writel(thsp, BIT(chan->id), db_id, TEGRA_HSP_DB_REG_RAW);
+
+	return 0;
+}
+
+static int tegra_hsp_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int tegra_hsp_probe(struct udevice *dev)
+{
+	struct tegra_hsp *thsp = dev_get_priv(dev);
+	int nr_sm, nr_ss, nr_as;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	thsp->regs = dev_get_addr(dev);
+	if (thsp->regs == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM",
+			       0);
+	nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS",
+			       0);
+	nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS",
+			       0);
+	thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
+
+	return 0;
+}
+
+static const struct udevice_id tegra_hsp_ids[] = {
+	{ .compatible = "nvidia,tegra186-hsp" },
+	{ }
+};
+
+struct mbox_ops tegra_hsp_mbox_ops = {
+	.request = tegra_hsp_request,
+	.free = tegra_hsp_free,
+	.send = tegra_hsp_send,
+	.recv = tegra_hsp_recv,
+};
+
+U_BOOT_DRIVER(tegra_hsp) = {
+	.name = "tegra-hsp",
+	.id = UCLASS_MAILBOX,
+	.of_match = tegra_hsp_ids,
+	.bind = tegra_hsp_bind,
+	.probe = tegra_hsp_probe,
+	.priv_auto_alloc_size = sizeof(struct tegra_hsp),
+	.ops = &tegra_hsp_mbox_ops,
+};
diff --git a/include/dt-bindings/mailbox/tegra-hsp.h b/include/dt-bindings/mailbox/tegra-hsp.h
new file mode 100644
index 0000000..e8c23fa
--- /dev/null
+++ b/include/dt-bindings/mailbox/tegra-hsp.h
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for binding nvidia,tegra186-hsp.
+ *
+ * The number with TEGRA_HSP_MASTER prefix indicates the bit that is
+ * associated with a master ID in the doorbell registers.
+ */
+
+#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
+#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
+
+#define TEGRA_HSP_MASTER_CCPLEX		17
+#define TEGRA_HSP_MASTER_BPMP		19
+
+#endif
-- 
cgit v0.10.2


From 89c1e2da78f82a09685006291ce8bb44f635fa25 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 17 Jun 2016 09:43:58 -0600
Subject: Add a reset driver framework/uclass

A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.

This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.

The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/device-tree-bindings/reset/reset.txt b/doc/device-tree-bindings/reset/reset.txt
new file mode 100644
index 0000000..31db6ff
--- /dev/null
+++ b/doc/device-tree-bindings/reset/reset.txt
@@ -0,0 +1,75 @@
+= Reset Signal Device Tree Bindings =
+
+This binding is intended to represent the hardware reset signals present
+internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
+standalone chips are most likely better represented as GPIOs, although there
+are likely to be exceptions to this rule.
+
+Hardware blocks typically receive a reset signal. This signal is generated by
+a reset provider (e.g. power management or clock module) and received by a
+reset consumer (the module being reset, or a module managing when a sub-
+ordinate module is reset). This binding exists to represent the provider and
+consumer, and provide a way to couple the two together.
+
+A reset signal is represented by the phandle of the provider, plus a reset
+specifier - a list of DT cells that represents the reset signal within the
+provider. The length (number of cells) and semantics of the reset specifier
+are dictated by the binding of the reset provider, although common schemes
+are described below.
+
+A word on where to place reset signal consumers in device tree: It is possible
+in hardware for a reset signal to affect multiple logically separate HW blocks
+at once. In this case, it would be unwise to represent this reset signal in
+the DT node of each affected HW block, since if activated, an unrelated block
+may be reset. Instead, reset signals should be represented in the DT node
+where it makes most sense to control it; this may be a bus node if all
+children of the bus are affected by the reset signal, or an individual HW
+block node for dedicated reset signals. The intent of this binding is to give
+appropriate software access to the reset signals in order to manage the HW,
+rather than to slavishly enumerate the reset signal that affects each HW
+block.
+
+= Reset providers =
+
+Required properties:
+#reset-cells:	Number of cells in a reset specifier; Typically 0 for nodes
+		with a single reset output and 1 for nodes with multiple
+		reset outputs.
+
+For example:
+
+	rst: reset-controller {
+		#reset-cells = <1>;
+	};
+
+= Reset consumers =
+
+Required properties:
+resets:		List of phandle and reset specifier pairs, one pair
+		for each reset signal that affects the device, or that the
+		device manages. Note: if the reset provider specifies '0' for
+		#reset-cells, then only the phandle portion of the pair will
+		appear.
+
+Optional properties:
+reset-names:	List of reset signal name strings sorted in the same order as
+		the resets property. Consumers drivers will use reset-names to
+		match reset signal names with reset specifiers.
+
+For example:
+
+	device {
+		resets = <&rst 20>;
+		reset-names = "reset";
+	};
+
+This represents a device with a single reset signal named "reset".
+
+	bus {
+		resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
+		reset-names = "i2s1", "i2s2", "dma", "mixer";
+	};
+
+This represents a bus that controls the reset signal of each of four sub-
+ordinate devices. Consider for example a bus that fails to operate unless no
+child device has reset asserted.
diff --git a/drivers/Kconfig b/drivers/Kconfig
index f2a137a..f6003a0 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -56,6 +56,8 @@ source "drivers/ram/Kconfig"
 
 source "drivers/remoteproc/Kconfig"
 
+source "drivers/reset/Kconfig"
+
 source "drivers/rtc/Kconfig"
 
 source "drivers/serial/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index db5317c..1723958 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_U_QE) += qe/
 obj-y += mailbox/
 obj-y += memory/
 obj-y += pwm/
+obj-y += reset/
 obj-y += input/
 # SOC specific infrastructure drivers.
 obj-y += soc/
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
new file mode 100644
index 0000000..5c449a9
--- /dev/null
+++ b/drivers/reset/Kconfig
@@ -0,0 +1,15 @@
+menu "Reset Controller Support"
+
+config DM_RESET
+	bool "Enable reset controllers using Driver Model"
+	depends on DM && OF_CONTROL
+	help
+	  Enable support for the reset controller driver class. Many hardware
+	  modules are equipped with a reset signal, typically driven by some
+	  reset controller hardware module within the chip. In U-Boot, reset
+	  controller drivers allow control over these reset signals. In some
+	  cases this API is applicable to chips outside the CPU as well,
+	  although driving such reset isgnals using GPIOs may be more
+	  appropriate in this case.
+
+endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
new file mode 100644
index 0000000..508608e
--- /dev/null
+++ b/drivers/reset/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DM_RESET) += reset-uclass.o
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
new file mode 100644
index 0000000..edaecfb
--- /dev/null
+++ b/drivers/reset/reset-uclass.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <reset.h>
+#include <reset-uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
+{
+	return (struct reset_ops *)dev->driver->ops;
+}
+
+static int reset_of_xlate_default(struct reset_ctl *reset_ctl,
+				  struct fdtdec_phandle_args *args)
+{
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	if (args->args_count != 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	reset_ctl->id = args->args[0];
+
+	return 0;
+}
+
+int reset_get_by_index(struct udevice *dev, int index,
+		       struct reset_ctl *reset_ctl)
+{
+	struct fdtdec_phandle_args args;
+	int ret;
+	struct udevice *dev_reset;
+	struct reset_ops *ops;
+
+	debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
+	      reset_ctl);
+
+	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+					     "resets", "#reset-cells", 0,
+					     index, &args);
+	if (ret) {
+		debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node,
+					     &dev_reset);
+	if (ret) {
+		debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+	ops = reset_dev_ops(dev_reset);
+
+	reset_ctl->dev = dev_reset;
+	if (ops->of_xlate)
+		ret = ops->of_xlate(reset_ctl, &args);
+	else
+		ret = reset_of_xlate_default(reset_ctl, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ops->request(reset_ctl);
+	if (ret) {
+		debug("ops->request() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int reset_get_by_name(struct udevice *dev, const char *name,
+		     struct reset_ctl *reset_ctl)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
+	      reset_ctl);
+
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reset-names",
+				name);
+	if (index < 0) {
+		debug("fdt_find_string() failed: %d\n", index);
+		return index;
+	}
+
+	return reset_get_by_index(dev, index, reset_ctl);
+}
+
+int reset_free(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->free(reset_ctl);
+}
+
+int reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->rst_assert(reset_ctl);
+}
+
+int reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->rst_deassert(reset_ctl);
+}
+
+UCLASS_DRIVER(reset) = {
+	.id		= UCLASS_RESET,
+	.name		= "reset",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0777cbe..b768660 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -63,6 +63,7 @@ enum uclass_id {
 	UCLASS_PWRSEQ,		/* Power sequence device */
 	UCLASS_REGULATOR,	/* Regulator device */
 	UCLASS_REMOTEPROC,	/* Remote Processor device */
+	UCLASS_RESET,		/* Reset controller device */
 	UCLASS_RTC,		/* Real time clock device */
 	UCLASS_SERIAL,		/* Serial UART */
 	UCLASS_SPI,		/* SPI bus */
diff --git a/include/reset-uclass.h b/include/reset-uclass.h
new file mode 100644
index 0000000..50adeca
--- /dev/null
+++ b/include/reset-uclass.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _RESET_UCLASS_H
+#define _RESET_UCLASS_H
+
+/* See reset.h for background documentation. */
+
+#include <reset.h>
+
+struct udevice;
+
+/**
+ * struct reset_ops - The functions that a reset controller driver must
+ * implement.
+ */
+struct reset_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) reset specifier.
+	 *
+	 * The reset core calls this function as the first step in implementing
+	 * a client's reset_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the reset core will use a
+	 * default implementation, which assumes #reset-cells = <1>, and that
+	 * the DT cell contains a simple integer reset signal ID.
+	 *
+	 * At present, the reset API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @reset_ctl:	The reset control struct to hold the translation result.
+	 * @args:	The reset specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct reset_ctl *reset_ctl,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated reset control.
+	 *
+	 * The reset core calls this function as the second step in
+	 * implementing a client's reset_get_by_*() call, following a
+	 * successful xxx_xlate() call.
+	 *
+	 * @reset_ctl:	The reset control struct to request; this has been
+	 *		filled in by a previoux xxx_xlate() function call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct reset_ctl *reset_ctl);
+	/**
+	 * free - Free a previously requested reset control.
+	 *
+	 * This is the implementation of the client reset_free() API.
+	 *
+	 * @reset_ctl:	The reset control to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct reset_ctl *reset_ctl);
+	/**
+	 * rst_assert - Assert a reset signal.
+	 *
+	 * Note: This function is named rst_assert not assert to avoid
+	 * conflicting with global macro assert().
+	 *
+	 * @reset_ctl:	The reset signal to assert.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*rst_assert)(struct reset_ctl *reset_ctl);
+	/**
+	 * rst_deassert - Deassert a reset signal.
+	 *
+	 * @reset_ctl:	The reset signal to deassert.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*rst_deassert)(struct reset_ctl *reset_ctl);
+};
+
+#endif
diff --git a/include/reset.h b/include/reset.h
new file mode 100644
index 0000000..dc0900f
--- /dev/null
+++ b/include/reset.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _RESET_H
+#define _RESET_H
+
+/**
+ * A reset is a hardware signal indicating that a HW module (or IP block, or
+ * sometimes an entire off-CPU chip) reset all of its internal state to some
+ * known-good initial state. Drivers will often reset HW modules when they
+ * begin execution to ensure that hardware correctly responds to all requests,
+ * or in response to some error condition. Reset signals are often controlled
+ * externally to the HW module being reset, by an entity this API calls a reset
+ * controller. This API provides a standard means for drivers to request that
+ * reset controllers set or clear reset signals.
+ *
+ * A driver that implements UCLASS_RESET is a reset controller or provider. A
+ * controller will often implement multiple separate reset signals, since the
+ * hardware it manages often has this capability. reset-uclass.h describes the
+ * interface which reset controllers must implement.
+ *
+ * Reset consumers/clients are the HW modules affected by reset signals. This
+ * header file describes the API used by drivers for those HW modules.
+ */
+
+struct udevice;
+
+/**
+ * struct reset_ctl - A handle to (allowing control of) a single reset signal.
+ *
+ * Clients provide storage for reset control handles. The content of the
+ * structure is managed solely by the reset API and reset drivers. A reset
+ * control struct is initialized by "get"ing the reset control struct. The
+ * reset control struct is passed to all other reset APIs to identify which
+ * reset signal to operate upon.
+ *
+ * @dev: The device which implements the reset signal.
+ * @id: The reset signal ID within the provider.
+ *
+ * Currently, the reset API assumes that a single integer ID is enough to
+ * identify and configure any reset signal for any reset provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow reset providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct reset_ctl {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+/**
+ * reset_get_by_index - Get/request a reset signal by integer index.
+ *
+ * This looks up and requests a reset signal. The index is relative to the
+ * client device; each device is assumed to have n reset signals associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device reset signal indices to provider reset signals may
+ * be via device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl	A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_index(struct udevice *dev, int index,
+		       struct reset_ctl *reset_ctl);
+
+/**
+ * reset_get_by_name - Get/request a reset signal by name.
+ *
+ * This looks up and requests a reset signal. The name is relative to the
+ * client device; each device is assumed to have n reset signals associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device reset signal names to provider reset signal may be
+ * via device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl:	A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_name(struct udevice *dev, const char *name,
+		      struct reset_ctl *reset_ctl);
+
+/**
+ * reset_free - Free a previously requested reset signal.
+ *
+ * @reset_ctl:	A reset control struct that was previously successfully
+ *		requested by reset_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_free(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_assert - Assert a reset signal.
+ *
+ * This function will assert the specified reset signal, thus resetting the
+ * affected HW module(s). Depending on the reset controller hardware, the reset
+ * signal will either stay asserted until reset_deassert() is called, or the
+ * hardware may autonomously clear the reset signal itself.
+ *
+ * @reset_ctl:	A reset control struct that was previously successfully
+ *		requested by reset_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_assert(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_deassert - Deassert a reset signal.
+ *
+ * This function will deassert the specified reset signal, thus releasing the
+ * affected HW modules() from reset, and allowing them to continue normal
+ * operation.
+ *
+ * @reset_ctl:	A reset control struct that was previously successfully
+ *		requested by reset_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_deassert(struct reset_ctl *reset_ctl);
+
+#endif
-- 
cgit v0.10.2


From 4581b717b1bf0fb04e7d9fcaf3d4c23d357154ac Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 17 Jun 2016 09:43:59 -0600
Subject: reset: implement a reset test

This adds a sandbox reset implementation (provider), a test client
device, instantiates them both from Sandbox's DT, and adds a DM test
that excercises everything.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 686c215..879b30e 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -259,6 +259,17 @@
 		compatible = "sandbox,reset";
 	};
 
+	resetc: reset-ctl {
+		compatible = "sandbox,reset-ctl";
+		#reset-cells = <1>;
+	};
+
+	reset-ctl-test {
+		compatible = "sandbox,reset-ctl-test";
+		resets = <&resetc 100>, <&resetc 2>;
+		reset-names = "other", "test";
+	};
+
 	rproc_1: rproc@1 {
 		compatible = "sandbox,test-processor";
 		remoteproc-name = "remoteproc-test-dev1";
diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h
new file mode 100644
index 0000000..7146aa5
--- /dev/null
+++ b/arch/sandbox/include/asm/reset.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_RESET_H
+#define __SANDBOX_RESET_H
+
+#include <common.h>
+
+struct udevice;
+
+int sandbox_reset_query(struct udevice *dev, unsigned long id);
+
+int sandbox_reset_test_get(struct udevice *dev);
+int sandbox_reset_test_assert(struct udevice *dev);
+int sandbox_reset_test_deassert(struct udevice *dev);
+int sandbox_reset_test_free(struct udevice *dev);
+
+#endif
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 4eb3c22..94253a6 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BLK=y
 CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
@@ -70,7 +71,6 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
-CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -89,6 +89,9 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
+CONFIG_MISC=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_I2C=y
@@ -140,6 +143,8 @@ CONFIG_DM_REGULATOR_SANDBOX=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_RAM=y
 CONFIG_REMOTEPROC_SANDBOX=y
+CONFIG_DM_RESET=y
+CONFIG_SANDBOX_RESET=y
 CONFIG_DM_RTC=y
 CONFIG_SANDBOX_SERIAL=y
 CONFIG_SOUND=y
@@ -170,6 +175,3 @@ CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
-CONFIG_MISC=y
-CONFIG_DM_MAILBOX=y
-CONFIG_SANDBOX_MBOX=y
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5c449a9..0fe8cc3 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -12,4 +12,12 @@ config DM_RESET
 	  although driving such reset isgnals using GPIOs may be more
 	  appropriate in this case.
 
+config SANDBOX_RESET
+	bool "Enable the sandbox reset test driver"
+	depends on DM_MAILBOX && SANDBOX
+	help
+	  Enable support for a test reset controller implementation, which
+	  simply accepts requests to reset various HW modules without actually
+	  doing anything beyond a little error checking.
+
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 508608e..71f3b21 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_DM_RESET) += reset-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c
new file mode 100644
index 0000000..e37d6c9
--- /dev/null
+++ b/drivers/reset/sandbox-reset-test.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/reset.h>
+
+struct sandbox_reset_test {
+	struct reset_ctl ctl;
+};
+
+int sandbox_reset_test_get(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_get_by_name(dev, "test", &sbrt->ctl);
+}
+
+int sandbox_reset_test_assert(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_assert(&sbrt->ctl);
+}
+
+int sandbox_reset_test_deassert(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_deassert(&sbrt->ctl);
+}
+
+int sandbox_reset_test_free(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_free(&sbrt->ctl);
+}
+
+static const struct udevice_id sandbox_reset_test_ids[] = {
+	{ .compatible = "sandbox,reset-ctl-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_reset_test) = {
+	.name = "sandbox_reset_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_reset_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_reset_test),
+};
diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c
new file mode 100644
index 0000000..4258af5
--- /dev/null
+++ b/drivers/reset/sandbox-reset.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <asm/reset.h>
+
+#define SANDBOX_RESET_SIGNALS 3
+
+struct sandbox_reset_signal {
+	bool asserted;
+};
+
+struct sandbox_reset {
+	struct sandbox_reset_signal signals[SANDBOX_RESET_SIGNALS];
+};
+
+static int sandbox_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	if (reset_ctl->id >= SANDBOX_RESET_SIGNALS)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sandbox_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return 0;
+}
+
+static int sandbox_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	sbr->signals[reset_ctl->id].asserted = true;
+
+	return 0;
+}
+
+static int sandbox_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	sbr->signals[reset_ctl->id].asserted = false;
+
+	return 0;
+}
+
+static int sandbox_reset_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int sandbox_reset_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_reset_ids[] = {
+	{ .compatible = "sandbox,reset-ctl" },
+	{ }
+};
+
+struct reset_ops sandbox_reset_reset_ops = {
+	.request = sandbox_reset_request,
+	.free = sandbox_reset_free,
+	.rst_assert = sandbox_reset_assert,
+	.rst_deassert = sandbox_reset_deassert,
+};
+
+U_BOOT_DRIVER(sandbox_reset) = {
+	.name = "sandbox_reset",
+	.id = UCLASS_RESET,
+	.of_match = sandbox_reset_ids,
+	.bind = sandbox_reset_bind,
+	.probe = sandbox_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_reset),
+	.ops = &sandbox_reset_reset_ops,
+};
+
+int sandbox_reset_query(struct udevice *dev, unsigned long id)
+{
+	struct sandbox_reset *sbr = dev_get_priv(dev);
+
+	debug("%s(dev=%p, id=%ld)\n", __func__, dev, id);
+
+	if (id >= SANDBOX_RESET_SIGNALS)
+		return -EINVAL;
+
+	return sbr->signals[id].asserted;
+}
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 9eaf04b..cad3374 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
 obj-$(CONFIG_REMOTEPROC) += remoteproc.o
+obj-$(CONFIG_DM_RESET) += reset.o
 obj-$(CONFIG_SYSRESET) += sysreset.o
 obj-$(CONFIG_DM_RTC) += rtc.o
 obj-$(CONFIG_DM_SPI_FLASH) += sf.o
diff --git a/test/dm/reset.c b/test/dm/reset.c
new file mode 100644
index 0000000..0ae8031
--- /dev/null
+++ b/test/dm/reset.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <asm/reset.h>
+#include <test/ut.h>
+
+/* This must match the specifier for mbox-names="test" in the DT node */
+#define TEST_RESET_ID 2
+
+static int dm_test_reset(struct unit_test_state *uts)
+{
+	struct udevice *dev_reset;
+	struct udevice *dev_test;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
+					      &dev_reset));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+					      &dev_test));
+	ut_assertok(sandbox_reset_test_get(dev_test));
+
+	ut_assertok(sandbox_reset_test_assert(dev_test));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+
+	ut_assertok(sandbox_reset_test_deassert(dev_test));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+
+	ut_assertok(sandbox_reset_test_free(dev_test));
+
+	return 0;
+}
+DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
-- 
cgit v0.10.2


From 135aa95002646c46e89de93fa36adad1b010548f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 17 Jun 2016 09:44:00 -0600
Subject: clk: convert API to match reset/mailbox style

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index d66b26f..317e512 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -62,18 +62,6 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  */
 void *rockchip_get_cru(void);
 
-/**
- * rkclk_get_clk() - get a pointer to a given clock
- *
- * This is an internal function - use outside the clock subsystem indicates
- * that work is needed!
- *
- * @clk_id:	Clock requested
- * @devp:	Returns a pointer to that clock
- * @return 0 if OK, -ve on error
- */
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
-
 struct rk3288_cru;
 struct rk3288_grf;
 
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 133d663..816540e 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -9,6 +9,7 @@
 #include <dm.h>
 #include <ram.h>
 #include <asm/io.h>
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,15 +55,43 @@ void lowlevel_init(void)
 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
+	static const struct {
+		char *name;
+		int id;
+	} clks[] = {
+		{ "osc", CLK_OSC },
+		{ "apll", CLK_ARM },
+		{ "dpll", CLK_DDR },
+		{ "cpll", CLK_CODEC },
+		{ "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+		{ "mpll", CLK_NEW },
+#else
+		{ "npll", CLK_NEW },
+#endif
+	};
+	int ret, i;
 	struct udevice *dev;
 
-	for (uclass_first_device(UCLASS_CLK, &dev);
-	     dev;
-	     uclass_next_device(&dev)) {
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret) {
+		printf("clk-uclass not found\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		struct clk clk;
 		ulong rate;
 
-		rate = clk_get_rate(dev);
-		printf("%s: %lu\n", dev->name, rate);
+		clk.id = clks[i].id;
+		ret = clk_request(dev, &clk);
+		if (ret < 0)
+			continue;
+
+		rate = clk_get_rate(&clk);
+		printf("%s: %lu\n", clks[i].name, rate);
+
+		clk_free(&clk);
 	}
 
 	return 0;
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 2e21282..55ac73e 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -36,7 +36,7 @@ struct chan_info {
 struct dram_info {
 	struct chan_info chan[2];
 	struct ram_info info;
-	struct udevice *ddr_clk;
+	struct clk ddr_clk;
 	struct rk3288_cru *cru;
 	struct rk3288_grf *grf;
 	struct rk3288_sgrf *sgrf;
@@ -576,7 +576,7 @@ static void dram_all_config(const struct dram_info *dram,
 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
 
-static int sdram_init(const struct dram_info *dram,
+static int sdram_init(struct dram_info *dram,
 		      const struct rk3288_sdram_params *sdram_params)
 {
 	int channel;
@@ -592,8 +592,8 @@ static int sdram_init(const struct dram_info *dram,
 		return -E2BIG;
 	}
 
-	debug("ddr clk %s\n", dram->ddr_clk->name);
-	ret = clk_set_rate(dram->ddr_clk, sdram_params->base.ddr_freq);
+	debug("ddr clk dpll\n");
+	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
 	debug("ret=%d\n", ret);
 	if (ret) {
 		debug("Could not set DDR clock\n");
@@ -836,6 +836,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	struct dram_info *priv = dev_get_priv(dev);
 	struct regmap *map;
 	int ret;
+	struct udevice *dev_clk;
 
 	map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 	if (IS_ERR(map))
@@ -856,7 +857,11 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	priv->chan[1].pctl = regmap_get_range(map, 2);
 	priv->chan[1].publ = regmap_get_range(map, 3);
 
-	ret = uclass_get_device(UCLASS_CLK, CLK_DDR, &priv->ddr_clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
+	if (ret)
+		return ret;
+	priv->ddr_clk.id = CLK_DDR;
+	ret = clk_request(dev_clk, &priv->ddr_clk);
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c
index d548d75..c2cf924 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -9,7 +9,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
 #include <asm/io.h>
@@ -212,11 +212,11 @@ static int clk_init_uart(struct msm_clk_priv *priv)
 	return 0;
 }
 
-ulong msm_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+ulong msm_set_rate(struct clk *clk, ulong rate)
 {
-	struct msm_clk_priv *priv = dev_get_priv(dev);
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	switch (periph) {
+	switch (clk->id) {
 	case 0: /* SDC1 */
 		return clk_init_sdc(priv, 0, rate);
 		break;
@@ -243,7 +243,7 @@ static int msm_clk_probe(struct udevice *dev)
 }
 
 static struct clk_ops msm_clk_ops = {
-	.set_periph_rate = msm_set_periph_rate,
+	.set_rate = msm_set_rate,
 };
 
 static const struct udevice_id msm_clk_ids[] = {
diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c
index 6444be8..40383c1 100644
--- a/arch/arm/mach-zynq/clk.c
+++ b/arch/arm/mach-zynq/clk.c
@@ -6,7 +6,6 @@
  */
 #include <common.h>
 #include <errno.h>
-#include <clk.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clk.h>
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index f2ee911..ac33391 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -23,18 +23,34 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static ulong clk_get_cpu_rate(void)
+static ulong rate(int id)
 {
 	int ret;
 	struct udevice *dev;
+	struct clk clk;
+	ulong rate;
 
 	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
 	if (ret) {
-		panic("uclass-clk: device not found\n");
+		printf("clk-uclass not found\n");
 		return 0;
 	}
 
-	return clk_get_rate(dev);
+	clk.id = id;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	return rate;
+}
+
+static ulong clk_get_cpu_rate(void)
+{
+	return rate(PB7CLK);
 }
 
 /* initialize prefetch module related to cpu_clk */
@@ -127,30 +143,25 @@ const char *get_core_name(void)
 }
 #endif
 #ifdef CONFIG_CMD_CLK
+
 int soc_clk_dump(void)
 {
-	int i, ret;
-	struct udevice *dev;
-
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
-	if (ret) {
-		printf("clk-uclass not found\n");
-		return ret;
-	}
+	int i;
 
 	printf("PLL Speed: %lu MHz\n",
-	       CLK_MHZ(clk_get_periph_rate(dev, PLLCLK)));
-	printf("CPU Speed: %lu MHz\n", CLK_MHZ(clk_get_rate(dev)));
-	printf("MPLL Speed: %lu MHz\n",
-	       CLK_MHZ(clk_get_periph_rate(dev, MPLL)));
+	       CLK_MHZ(rate(PLLCLK)));
+
+	printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
+
+	printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
 
 	for (i = PB1CLK; i <= PB7CLK; i++)
 		printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
-		       CLK_MHZ(clk_get_periph_rate(dev, i)));
+		       CLK_MHZ(rate(i)));
 
 	for (i = REF1CLK; i <= REF5CLK; i++)
 		printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
-		       CLK_MHZ(clk_get_periph_rate(dev, i)));
+		       CLK_MHZ(rate(i)));
 	return 0;
 }
 #endif
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 879b30e..9e46f9e 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -108,8 +108,23 @@
 		compatible = "denx,u-boot-fdt-test";
 	};
 
-	clk@0 {
+	clk_fixed: clk-fixed {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1234>;
+	};
+
+	clk_sandbox: clk-sbox {
 		compatible = "sandbox,clk";
+		#clock-cells = <1>;
+	};
+
+	clk-test {
+		compatible = "sandbox,clk-test";
+		clocks = <&clk_fixed>,
+			 <&clk_sandbox 1>,
+			 <&clk_sandbox 0>;
+		clock-names = "fixed", "i2c", "spi";
 	};
 
 	eth@10002000 {
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
new file mode 100644
index 0000000..9dc6c81
--- /dev/null
+++ b/arch/sandbox/include/asm/clk.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_CLK_H
+#define __SANDBOX_CLK_H
+
+#include <common.h>
+
+struct udevice;
+
+/**
+ * enum sandbox_clk_id - Identity of clocks implemented by the sandbox clock
+ * provider.
+ *
+ * These IDs are within/relative-to the clock provider.
+ */
+enum sandbox_clk_id {
+	SANDBOX_CLK_ID_SPI,
+	SANDBOX_CLK_ID_I2C,
+
+	SANDBOX_CLK_ID_COUNT,
+};
+
+/**
+ * enum sandbox_clk_test_id - Identity of the clocks consumed by the sandbox
+ * clock test device.
+ *
+ * These are the IDs the clock consumer knows the clocks as.
+ */
+enum sandbox_clk_test_id {
+	SANDBOX_CLK_TEST_ID_FIXED,
+	SANDBOX_CLK_TEST_ID_SPI,
+	SANDBOX_CLK_TEST_ID_I2C,
+
+	SANDBOX_CLK_TEST_ID_COUNT,
+};
+
+/**
+ * sandbox_clk_query_rate - Query the current rate of a sandbox clock.
+ *
+ * @dev:	The sandbox clock provider device.
+ * @id:		The clock to query.
+ * @return:	The rate of the clock.
+ */
+ulong sandbox_clk_query_rate(struct udevice *dev, int id);
+/**
+ * sandbox_clk_query_enable - Query the enable state of a sandbox clock.
+ *
+ * @dev:	The sandbox clock provider device.
+ * @id:		The clock to query.
+ * @return:	The rate of the clock.
+ */
+int sandbox_clk_query_enable(struct udevice *dev, int id);
+
+/**
+ * sandbox_clk_test_get - Ask the sandbox clock test device to request its
+ * clocks.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_get(struct udevice *dev);
+/**
+ * sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a
+ * clock's rate.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to query.
+ * @return:	The rate of the clock.
+ */
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_set_rate - Ask the sandbox clock test device to set a
+ * clock's rate.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to configure.
+ * @return:	The new rate of the clock.
+ */
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
+/**
+ * sandbox_clk_test_enable - Ask the sandbox clock test device to enable a
+ * clock.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to configure.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_enable(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_disable - Ask the sandbox clock test device to disable a
+ * clock.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to configure.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_disable(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_free - Ask the sandbox clock test device to free its
+ * clocks.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_free(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 224b0eb..451a78e 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -19,15 +19,6 @@
 
 #define SANDBOX_CLK_RATE		32768
 
-enum {
-	PERIPH_ID_FIRST = 0,
-	PERIPH_ID_SPI = PERIPH_ID_FIRST,
-	PERIPH_ID_I2C,
-	PERIPH_ID_PCI,
-
-	PERIPH_ID_COUNT,
-};
-
 /* System controller driver data */
 enum {
 	SYSCON0		= 32,
diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c
index afe2ab8..3d31d3d 100644
--- a/board/microchip/pic32mzda/pic32mzda.c
+++ b/board/microchip/pic32mzda/pic32mzda.c
@@ -11,20 +11,31 @@
 #include <common.h>
 #include <dm.h>
 #include <clk.h>
+#include <dt-bindings/clock/microchip,clock.h>
 #include <mach/pic32.h>
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
-	ulong rate = 0;
+	ulong rate;
 	struct udevice *dev;
+	struct clk clk;
+	int ret;
 
 	printf("Core: %s\n", get_core_name());
 
-	if (!uclass_get_device(UCLASS_CLK, 0, &dev)) {
-		rate = clk_get_rate(dev);
-		printf("CPU Speed: %lu MHz\n", rate / 1000000);
-	}
+	if (uclass_get_device(UCLASS_CLK, 0, &dev))
+		return 0;
+
+	clk.id = PB7CLK;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+	printf("CPU Speed: %lu MHz\n", rate / 1000000);
+
+	clk_free(&clk);
 
 	return 0;
 }
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 81fe600..f7a8891 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index b483c1e..6e4d672 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -1,91 +1,78 @@
 /*
  * Copyright (C) 2015 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <dm/lists.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-ulong clk_get_rate(struct udevice *dev)
+static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
 {
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->get_rate)
-		return -ENOSYS;
-
-	return ops->get_rate(dev);
+	return (struct clk_ops *)dev->driver->ops;
 }
 
-ulong clk_set_rate(struct udevice *dev, ulong rate)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+#ifdef CONFIG_SPL_BUILD
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 {
-	struct clk_ops *ops = clk_get_ops(dev);
+	int ret;
+	u32 cell[2];
 
-	if (!ops->set_rate)
+	if (index != 0)
 		return -ENOSYS;
-
-	return ops->set_rate(dev, rate);
+	assert(clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
+	if (ret)
+		return ret;
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
+				   cell, 2);
+	if (ret)
+		return ret;
+	clk->id = cell[1];
+	return 0;
 }
 
-int clk_enable(struct udevice *dev, int periph)
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
 {
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->enable)
-		return -ENOSYS;
-
-	return ops->enable(dev, periph);
+	return -ENOSYS;
 }
-
-ulong clk_get_periph_rate(struct udevice *dev, int periph)
+#else
+static int clk_of_xlate_default(struct clk *clk,
+				struct fdtdec_phandle_args *args)
 {
-	struct clk_ops *ops = clk_get_ops(dev);
+	debug("%s(clk=%p)\n", __func__, clk);
 
-	if (!ops->get_periph_rate)
-		return -ENOSYS;
-
-	return ops->get_periph_rate(dev, periph);
-}
-
-ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
-{
-	struct clk_ops *ops = clk_get_ops(dev);
+	if (args->args_count > 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
 
-	if (!ops->set_periph_rate)
-		return -ENOSYS;
+	if (args->args_count)
+		clk->id = args->args[0];
+	else
+		clk->id = 0;
 
-	return ops->set_periph_rate(dev, periph, rate);
+	return 0;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 {
 	int ret;
-#ifdef CONFIG_SPL_BUILD
-	u32 cell[2];
-
-	if (index != 0)
-		return -ENOSYS;
-	assert(*clk_devp);
-	ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
-	if (ret)
-		return ret;
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
-				   cell, 2);
-	if (ret)
-		return ret;
-	return cell[1];
-#else
 	struct fdtdec_phandle_args args;
+	struct udevice *dev_clk;
+	struct clk_ops *ops;
+
+	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
 
-	assert(*clk_devp);
+	assert(clk);
 	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
 					     "clocks", "#clock-cells", 0, index,
 					     &args);
@@ -95,16 +82,117 @@ int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
 		return ret;
 	}
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, clk_devp);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev_clk);
 	if (ret) {
 		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
 		      __func__, ret);
 		return ret;
 	}
-	return args.args_count > 0 ? args.args[0] : 0;
-#endif
+	ops = clk_dev_ops(dev_clk);
+
+	if (ops->of_xlate)
+		ret = ops->of_xlate(clk, &args);
+	else
+		ret = clk_of_xlate_default(clk, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	return clk_request(dev_clk, clk);
+}
+
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
+
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "clock-names",
+				name);
+	if (index < 0) {
+		debug("fdt_find_string() failed: %d\n", index);
+		return index;
+	}
+
+	return clk_get_by_index(dev, index, clk);
 }
 #endif
+#endif
+
+int clk_request(struct udevice *dev, struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(dev);
+
+	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
+
+	clk->dev = dev;
+
+	if (!ops->request)
+		return 0;
+
+	return ops->request(clk);
+}
+
+int clk_free(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->free)
+		return 0;
+
+	return ops->free(clk);
+}
+
+ulong clk_get_rate(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->get_rate)
+		return -ENOSYS;
+
+	return ops->get_rate(clk);
+}
+
+ulong clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+
+	if (!ops->set_rate)
+		return -ENOSYS;
+
+	return ops->set_rate(clk, rate);
+}
+
+int clk_enable(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->enable)
+		return -ENOSYS;
+
+	return ops->enable(clk);
+}
+
+int clk_disable(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->disable)
+		return -ENOSYS;
+
+	return ops->disable(clk);
+}
 
 UCLASS_DRIVER(clk) = {
 	.id		= UCLASS_CLK,
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 8beda9c..797e537 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm/device.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -16,19 +16,16 @@ struct clk_fixed_rate {
 
 #define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
 
-static ulong clk_fixed_rate_get_rate(struct udevice *dev)
+static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
-	return to_clk_fixed_rate(dev)->fixed_rate;
-}
+	if (clk->id != 0)
+		return -EINVAL;
 
-static ulong clk_fixed_rate_get_periph_rate(struct udevice *dev, int periph)
-{
-	return clk_fixed_rate_get_rate(dev);
+	return to_clk_fixed_rate(clk->dev)->fixed_rate;
 }
 
 const struct clk_ops clk_fixed_rate_ops = {
 	.get_rate = clk_fixed_rate_get_rate,
-	.get_periph_rate = clk_fixed_rate_get_periph_rate,
 };
 
 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
index 5d88354..70ec354 100644
--- a/drivers/clk/clk_pic32.c
+++ b/drivers/clk/clk_pic32.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <div64.h>
 #include <wait_bit.h>
@@ -339,24 +339,17 @@ static void pic32_clk_init(struct udevice *dev)
 	pic32_mpll_init(priv);
 }
 
-static ulong pic32_clk_get_rate(struct udevice *dev)
+static ulong pic32_get_rate(struct clk *clk)
 {
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
-
-	return pic32_get_cpuclk(priv);
-}
-
-static ulong pic32_get_periph_rate(struct udevice *dev, int periph)
-{
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
+	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong rate;
 
-	switch (periph) {
+	switch (clk->id) {
 	case PB1CLK ... PB7CLK:
-		rate = pic32_get_pbclk(priv, periph);
+		rate = pic32_get_pbclk(priv, clk->id);
 		break;
 	case REF1CLK ... REF5CLK:
-		rate = pic32_get_refclk(priv, periph);
+		rate = pic32_get_refclk(priv, clk->id);
 		break;
 	case PLLCLK:
 		rate = pic32_get_pll_rate(priv);
@@ -372,15 +365,15 @@ static ulong pic32_get_periph_rate(struct udevice *dev, int periph)
 	return rate;
 }
 
-static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong pic32_set_rate(struct clk *clk, ulong rate)
 {
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
+	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong pll_hz;
 
-	switch (periph) {
+	switch (clk->id) {
 	case REF1CLK ... REF5CLK:
 		pll_hz = pic32_get_pll_rate(priv);
-		pic32_set_refclk(priv, periph, pll_hz, rate, ROCLK_SRC_SPLL);
+		pic32_set_refclk(priv, clk->id, pll_hz, rate, ROCLK_SRC_SPLL);
 		break;
 	default:
 		break;
@@ -390,9 +383,8 @@ static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 }
 
 static struct clk_ops pic32_pic32_clk_ops = {
-	.get_rate = pic32_clk_get_rate,
-	.set_periph_rate = pic32_set_periph_rate,
-	.get_periph_rate = pic32_get_periph_rate,
+	.set_rate = pic32_set_rate,
+	.get_rate = pic32_get_rate,
 };
 
 static int pic32_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index 7ec65bd..6202c9d 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
 #include <syscon.h>
@@ -18,10 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct rk3036_clk_plat {
-	enum rk_clk_id clk_id;
-};
-
 struct rk3036_clk_priv {
 	struct rk3036_cru *cru;
 	ulong rate;
@@ -315,31 +311,30 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
 	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
 }
 
-static ulong rk3036_clk_get_rate(struct udevice *dev)
-{
-	struct rk3036_clk_plat *plat = dev_get_platdata(dev);
-	struct rk3036_clk_priv *priv = dev_get_priv(dev);
-
-	debug("%s\n", dev->name);
-	return rkclk_pll_get_rate(priv->cru, plat->clk_id);
-}
-
-static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate)
+static ulong rk3036_clk_get_rate(struct clk *clk)
 {
-	debug("%s\n", dev->name);
+	struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
 
-	return 0;
+	switch (clk->id) {
+	case 0 ... 63:
+		return rkclk_pll_get_rate(priv->cru, clk->id);
+	default:
+		return -ENOENT;
+	}
 }
 
-static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct rk3036_clk_priv *priv = dev_get_priv(dev);
-	ulong new_rate;
+	struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong new_rate, gclk_rate;
 
-	switch (periph) {
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 0 ... 63:
+		return 0;
 	case HCLK_EMMC:
-		new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
-						periph, rate);
+		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
+						clk->id, rate);
 		break;
 	default:
 		return -ENOENT;
@@ -351,60 +346,21 @@ static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 static struct clk_ops rk3036_clk_ops = {
 	.get_rate	= rk3036_clk_get_rate,
 	.set_rate	= rk3036_clk_set_rate,
-	.set_periph_rate = rk3036_set_periph_rate,
 };
 
 static int rk3036_clk_probe(struct udevice *dev)
 {
-	struct rk3036_clk_plat *plat = dev_get_platdata(dev);
 	struct rk3036_clk_priv *priv = dev_get_priv(dev);
 
-	if (plat->clk_id != CLK_OSC) {
-		struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent);
-
-		priv->cru = parent_priv->cru;
-		return 0;
-	}
 	priv->cru = (struct rk3036_cru *)dev_get_addr(dev);
 	rkclk_init(priv->cru);
 
 	return 0;
 }
 
-static const char *const clk_name[] = {
-	"osc",
-	"apll",
-	"dpll",
-	"cpll",
-	"gpll",
-	"mpll",
-};
-
 static int rk3036_clk_bind(struct udevice *dev)
 {
-	struct rk3036_clk_plat *plat = dev_get_platdata(dev);
-	int pll, ret;
-
-	/* We only need to set up the root clock */
-	if (dev->of_offset == -1) {
-		plat->clk_id = CLK_OSC;
-		return 0;
-	}
-
-	/* Create devices for P main clocks */
-	for (pll = 1; pll < CLK_COUNT; pll++) {
-		struct udevice *child;
-		struct rk3036_clk_plat *cplat;
-
-		debug("%s %s\n", __func__, clk_name[pll]);
-		ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll],
-					 &child);
-		if (ret)
-			return ret;
-
-		cplat = dev_get_platdata(child);
-		cplat->clk_id = pll;
-	}
+	int ret;
 
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
@@ -424,7 +380,6 @@ U_BOOT_DRIVER(clk_rk3036) = {
 	.id		= UCLASS_CLK,
 	.of_match	= rk3036_clk_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
-	.platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat),
 	.ops		= &rk3036_clk_ops,
 	.bind		= rk3036_clk_bind,
 	.probe		= rk3036_clk_probe,
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index d88893c..2285453 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
 #include <syscon.h>
@@ -21,10 +21,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct rk3288_clk_plat {
-	enum rk_clk_id clk_id;
-};
-
 struct rk3288_clk_priv {
 	struct rk3288_grf *grf;
 	struct rk3288_cru *cru;
@@ -135,34 +131,18 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
-{
-	struct udevice *dev;
-
-	for (uclass_find_first_device(UCLASS_CLK, &dev);
-	     dev;
-	     uclass_find_next_device(&dev)) {
-		struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-
-		if (plat->clk_id == clk_id) {
-			*devp = dev;
-			return device_probe(dev);
-		}
-	}
-
-	return -ENODEV;
-}
-
 void *rockchip_get_cru(void)
 {
 	struct rk3288_clk_priv *priv;
 	struct udevice *dev;
 	int ret;
 
-	ret = rkclk_get_clk(CLK_GENERAL, &dev);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
 	if (ret)
 		return ERR_PTR(ret);
+
 	priv = dev_get_priv(dev);
+
 	return priv->cru;
 }
 
@@ -539,32 +519,6 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 	}
 }
 
-static ulong rk3288_clk_get_rate(struct udevice *dev)
-{
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
-
-	debug("%s\n", dev->name);
-	return rkclk_pll_get_rate(priv->cru, plat->clk_id);
-}
-
-static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
-{
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
-
-	debug("%s\n", dev->name);
-	switch (plat->clk_id) {
-	case CLK_DDR:
-		rkclk_configure_ddr(priv->cru, priv->grf, rate);
-		break;
-	default:
-		return -ENOENT;
-	}
-
-	return 0;
-}
-
 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 				  int periph)
 {
@@ -710,27 +664,25 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
-static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
+static ulong rk3288_clk_get_rate(struct clk *clk)
 {
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
-	struct udevice *gclk;
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong new_rate, gclk_rate;
-	int ret;
 
-	ret = rkclk_get_clk(CLK_GENERAL, &gclk);
-	if (ret)
-		return ret;
-	gclk_rate = clk_get_rate(gclk);
-	switch (periph) {
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 0 ... 63:
+		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
+		break;
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO0:
-		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
+		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 		break;
 	case SCLK_SPI0:
 	case SCLK_SPI1:
 	case SCLK_SPI2:
-		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
+		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 		break;
 	case PCLK_I2C0:
 	case PCLK_I2C1:
@@ -746,36 +698,34 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 	return new_rate;
 }
 
-static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 	struct rk3288_cru *cru = priv->cru;
-	struct udevice *gclk;
 	ulong new_rate, gclk_rate;
-	int ret;
 
-	ret = rkclk_get_clk(CLK_GENERAL, &gclk);
-	if (ret)
-		return ret;
-	gclk_rate = clk_get_rate(gclk);
-	switch (periph) {
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case CLK_DDR:
+		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
+		break;
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO0:
-		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
+		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 		break;
 	case SCLK_SPI0:
 	case SCLK_SPI1:
 	case SCLK_SPI2:
-		new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
+		new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 		break;
 #ifndef CONFIG_SPL_BUILD
 	case SCLK_MAC:
-		new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
+		new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
 		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
-		new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
+		new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 		break;
 	case SCLK_EDP_24M:
 		/* clk_edp_24M source: 24M */
@@ -795,7 +745,7 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 		div = CPLL_HZ / rate;
 		assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 
-		switch (periph) {
+		switch (clk->id) {
 		case ACLK_VOP0:
 			rk_clrsetreg(&cru->cru_clksel_con[31],
 				     3 << 6 | 0x1f << 0,
@@ -831,22 +781,12 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 static struct clk_ops rk3288_clk_ops = {
 	.get_rate	= rk3288_clk_get_rate,
 	.set_rate	= rk3288_clk_set_rate,
-	.set_periph_rate = rk3288_set_periph_rate,
-	.get_periph_rate = rk3288_get_periph_rate,
 };
 
 static int rk3288_clk_probe(struct udevice *dev)
 {
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 	struct rk3288_clk_priv *priv = dev_get_priv(dev);
 
-	if (plat->clk_id != CLK_OSC) {
-		struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
-
-		priv->cru = parent_priv->cru;
-		priv->grf = parent_priv->grf;
-		return 0;
-	}
 	priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 #ifdef CONFIG_SPL_BUILD
@@ -856,39 +796,9 @@ static int rk3288_clk_probe(struct udevice *dev)
 	return 0;
 }
 
-static const char *const clk_name[CLK_COUNT] = {
-	"osc",
-	"apll",
-	"dpll",
-	"cpll",
-	"gpll",
-	"npll",
-};
-
 static int rk3288_clk_bind(struct udevice *dev)
 {
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-	int pll, ret;
-
-	/* We only need to set up the root clock */
-	if (dev->of_offset == -1) {
-		plat->clk_id = CLK_OSC;
-		return 0;
-	}
-
-	/* Create devices for P main clocks */
-	for (pll = 1; pll < CLK_COUNT; pll++) {
-		struct udevice *child;
-		struct rk3288_clk_plat *cplat;
-
-		debug("%s %s\n", __func__, clk_name[pll]);
-		ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
-					 &child);
-		if (ret)
-			return ret;
-		cplat = dev_get_platdata(child);
-		cplat->clk_id = pll;
-	}
+	int ret;
 
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
@@ -908,7 +818,6 @@ U_BOOT_DRIVER(clk_rk3288) = {
 	.id		= UCLASS_CLK,
 	.of_match	= rk3288_clk_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
-	.platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 	.ops		= &rk3288_clk_ops,
 	.bind		= rk3288_clk_bind,
 	.probe		= rk3288_clk_probe,
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 367130f..c6bd7c6 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -5,61 +5,63 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/test.h>
+#include <asm/clk.h>
 
 struct sandbox_clk_priv {
-	ulong rate;
-	ulong periph_rate[PERIPH_ID_COUNT];
+	ulong rate[SANDBOX_CLK_ID_COUNT];
+	bool enabled[SANDBOX_CLK_ID_COUNT];
 };
 
-static ulong sandbox_clk_get_rate(struct udevice *dev)
+static ulong sandbox_clk_get_rate(struct clk *clk)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
 
-	return priv->rate;
+	return priv->rate[clk->id];
 }
 
-static ulong sandbox_clk_set_rate(struct udevice *dev, ulong rate)
+static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong old_rate;
+
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
 
 	if (!rate)
 		return -EINVAL;
-	priv->rate = rate;
-	return 0;
-}
 
-static ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
-{
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	old_rate = priv->rate[clk->id];
+	priv->rate[clk->id] = rate;
 
-	if (periph < PERIPH_ID_FIRST || periph >= PERIPH_ID_COUNT)
-		return -EINVAL;
-	return priv->periph_rate[periph];
+	return old_rate;
 }
 
-static ulong sandbox_set_periph_rate(struct udevice *dev, int periph,
-				     ulong rate)
+static int sandbox_clk_enable(struct clk *clk)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
-	ulong old_rate;
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (periph < PERIPH_ID_FIRST || periph >= PERIPH_ID_COUNT)
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
 		return -EINVAL;
-	old_rate = priv->periph_rate[periph];
-	priv->periph_rate[periph] = rate;
 
-	return old_rate;
+	priv->enabled[clk->id] = true;
+
+	return 0;
 }
 
-static int sandbox_clk_probe(struct udevice *dev)
+static int sandbox_clk_disable(struct clk *clk)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
 
-	priv->rate = SANDBOX_CLK_RATE;
+	priv->enabled[clk->id] = false;
 
 	return 0;
 }
@@ -67,8 +69,8 @@ static int sandbox_clk_probe(struct udevice *dev)
 static struct clk_ops sandbox_clk_ops = {
 	.get_rate	= sandbox_clk_get_rate,
 	.set_rate	= sandbox_clk_set_rate,
-	.get_periph_rate = sandbox_get_periph_rate,
-	.set_periph_rate = sandbox_set_periph_rate,
+	.enable		= sandbox_clk_enable,
+	.disable	= sandbox_clk_disable,
 };
 
 static const struct udevice_id sandbox_clk_ids[] = {
@@ -82,5 +84,24 @@ U_BOOT_DRIVER(clk_sandbox) = {
 	.of_match	= sandbox_clk_ids,
 	.ops		= &sandbox_clk_ops,
 	.priv_auto_alloc_size = sizeof(struct sandbox_clk_priv),
-	.probe		= sandbox_clk_probe,
 };
+
+ulong sandbox_clk_query_rate(struct udevice *dev, int id)
+{
+	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	return priv->rate[id];
+}
+
+int sandbox_clk_query_enable(struct udevice *dev, int id)
+{
+	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	return priv->enabled[id];
+}
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
new file mode 100644
index 0000000..999100d
--- /dev/null
+++ b/drivers/clk/clk_sandbox_test.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <asm/clk.h>
+
+struct sandbox_clk_test {
+	struct clk clks[SANDBOX_CLK_TEST_ID_COUNT];
+};
+
+static const char * const sandbox_clk_test_names[] = {
+	[SANDBOX_CLK_TEST_ID_FIXED] = "fixed",
+	[SANDBOX_CLK_TEST_ID_SPI] = "spi",
+	[SANDBOX_CLK_TEST_ID_I2C] = "i2c",
+};
+
+int sandbox_clk_test_get(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+	int i, ret;
+
+	for (i = 0; i < SANDBOX_CLK_TEST_ID_COUNT; i++) {
+		ret = clk_get_by_name(dev, sandbox_clk_test_names[i],
+				      &sbct->clks[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_get_rate(&sbct->clks[id]);
+}
+
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_set_rate(&sbct->clks[id], rate);
+}
+
+int sandbox_clk_test_enable(struct udevice *dev, int id)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_enable(&sbct->clks[id]);
+}
+
+int sandbox_clk_test_disable(struct udevice *dev, int id)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_disable(&sbct->clks[id]);
+}
+
+int sandbox_clk_test_free(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+	int i, ret;
+
+	for (i = 0; i < SANDBOX_CLK_TEST_ID_COUNT; i++) {
+		ret = clk_free(&sbct->clks[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_clk_test_ids[] = {
+	{ .compatible = "sandbox,clk-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_clk_test) = {
+	.name = "sandbox_clk_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_clk_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_clk_test),
+};
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index bf5d0e6..1f017a3 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <asm/io.h>
 #include <dt-bindings/clock/exynos7420-clk.h>
 #include "clk-pll.h"
@@ -67,11 +67,11 @@ struct exynos7420_clk_top0_priv {
 	unsigned long sclk_uart2;
 };
 
-static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_topc_get_rate(struct clk *clk)
 {
-	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
 
-	switch (periph) {
+	switch (clk->id) {
 	case DOUT_SCLK_BUS0_PLL:
 	case SCLK_BUS0_PLL_A:
 	case SCLK_BUS0_PLL_B:
@@ -86,14 +86,14 @@ static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
 }
 
 static struct clk_ops exynos7420_clk_topc_ops = {
-	.get_periph_rate	= exynos7420_topc_get_periph_rate,
+	.get_rate	= exynos7420_topc_get_rate,
 };
 
 static int exynos7420_clk_topc_probe(struct udevice *dev)
 {
 	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
 	struct exynos7420_clk_cmu_topc *topc;
-	struct udevice *clk_dev;
+	struct clk in_clk;
 	unsigned long rate;
 	fdt_addr_t base;
 	int ret;
@@ -105,9 +105,9 @@ static int exynos7420_clk_topc_probe(struct udevice *dev)
 	topc = (struct exynos7420_clk_cmu_topc *)base;
 	priv->topc = topc;
 
-	ret = clk_get_by_index(dev, 0, &clk_dev);
+	ret = clk_get_by_index(dev, 0, &in_clk);
 	if (ret >= 0)
-		priv->fin_freq = clk_get_rate(clk_dev);
+		priv->fin_freq = clk_get_rate(&in_clk);
 
 	rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
 	if (readl(&topc->mux_sel[1]) & (1 << 16))
@@ -122,12 +122,12 @@ static int exynos7420_clk_topc_probe(struct udevice *dev)
 	return 0;
 }
 
-static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_top0_get_rate(struct clk *clk)
 {
-	struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_top0_priv *priv = dev_get_priv(clk->dev);
 	struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
 
-	switch (periph) {
+	switch (clk->id) {
 	case CLK_SCLK_UART2:
 		return priv->mout_top0_bus0_pll_half /
 			DIVIDER(&top0->div_peric[3], 8, 0xf);
@@ -137,14 +137,14 @@ static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
 }
 
 static struct clk_ops exynos7420_clk_top0_ops = {
-	.get_periph_rate	= exynos7420_top0_get_periph_rate,
+	.get_rate	= exynos7420_top0_get_rate,
 };
 
 static int exynos7420_clk_top0_probe(struct udevice *dev)
 {
 	struct exynos7420_clk_top0_priv *priv;
 	struct exynos7420_clk_cmu_top0 *top0;
-	struct udevice *clk_dev;
+	struct clk in_clk;
 	fdt_addr_t base;
 	int ret;
 
@@ -159,10 +159,10 @@ static int exynos7420_clk_top0_probe(struct udevice *dev)
 	top0 = (struct exynos7420_clk_cmu_top0 *)base;
 	priv->top0 = top0;
 
-	ret = clk_get_by_index(dev, 1, &clk_dev);
+	ret = clk_get_by_index(dev, 1, &in_clk);
 	if (ret >= 0) {
 		priv->mout_top0_bus0_pll_half =
-			clk_get_periph_rate(clk_dev, ret);
+			clk_get_rate(&in_clk);
 		if (readl(&top0->mux_sel[1]) & (1 << 16))
 			priv->mout_top0_bus0_pll_half >>= 1;
 	}
@@ -170,18 +170,18 @@ static int exynos7420_clk_top0_probe(struct udevice *dev)
 	return 0;
 }
 
-static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_peric1_get_rate(struct clk *clk)
 {
-	struct udevice *clk_dev;
+	struct clk in_clk;
 	unsigned int ret;
 	unsigned long freq = 0;
 
-	switch (periph) {
+	switch (clk->id) {
 	case SCLK_UART2:
-		ret = clk_get_by_index(dev, 3, &clk_dev);
+		ret = clk_get_by_index(clk->dev, 3, &in_clk);
 		if (ret < 0)
 			return ret;
-		freq = clk_get_periph_rate(clk_dev, ret);
+		freq = clk_get_rate(&in_clk);
 		break;
 	}
 
@@ -189,7 +189,7 @@ static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
 }
 
 static struct clk_ops exynos7420_clk_peric1_ops = {
-	.get_periph_rate	= exynos7420_peric1_get_periph_rate,
+	.get_rate	= exynos7420_peric1_get_rate,
 };
 
 static const struct udevice_id exynos7420_clk_topc_compat[] = {
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 25c163b..2f5d4d8 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -9,14 +9,14 @@
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm/device.h>
 
 #include "clk-uniphier.h"
 
-static int uniphier_clk_enable(struct udevice *dev, int index)
+static int uniphier_clk_enable(struct clk *clk)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_gate_data *gate = priv->socdata->gate;
 	unsigned int nr_gate = priv->socdata->nr_gate;
 	void __iomem *reg;
@@ -24,7 +24,7 @@ static int uniphier_clk_enable(struct udevice *dev, int index)
 	int i;
 
 	for (i = 0; i < nr_gate; i++) {
-		if (gate[i].index != index)
+		if (gate[i].index != clk->id)
 			continue;
 
 		reg = priv->base + gate[i].reg;
@@ -41,9 +41,9 @@ static int uniphier_clk_enable(struct udevice *dev, int index)
 	return 0;
 }
 
-static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
+static ulong uniphier_clk_get_rate(struct clk *clk)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;
@@ -52,7 +52,7 @@ static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
 	int i;
 
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index)
+		if (rdata[i].index != clk->id)
 			continue;
 
 		if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
@@ -75,9 +75,9 @@ static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
 	return matched_rate;
 }
 
-static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
+static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;
@@ -87,7 +87,7 @@ static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
 
 	/* first, decide the best match rate */
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index)
+		if (rdata[i].index != clk->id)
 			continue;
 
 		if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
@@ -105,7 +105,7 @@ static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
 
 	/* second, really set registers */
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index || rdata[i].rate != best_rate)
+		if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
 			continue;
 
 		reg = priv->base + rdata[i].reg;
@@ -124,8 +124,8 @@ static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
 
 const struct clk_ops uniphier_clk_ops = {
 	.enable = uniphier_clk_enable,
-	.get_periph_rate = uniphier_clk_get_rate,
-	.set_periph_rate = uniphier_clk_set_rate,
+	.get_rate = uniphier_clk_get_rate,
+	.set_rate = uniphier_clk_set_rate,
 };
 
 int uniphier_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index c6ecd11..2dd3fc0 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <clk.h>
 #include <dm/device.h>
 
 #include "clk-uniphier.h"
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index 3fceade..63b1418 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -29,10 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RK_I2C_FIFO_SIZE	32
 
 struct rk_i2c {
-	struct udevice *clk;
+	struct clk clk;
 	struct i2c_regs *regs;
 	unsigned int speed;
-	int clk_id;
 };
 
 static inline void rk_i2c_get_div(int div, int *divh, int *divl)
@@ -55,7 +54,7 @@ static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
 	int div, divl, divh;
 
 	/* First get i2c rate from pclk */
-	i2c_rate = clk_get_periph_rate(i2c->clk, i2c->clk_id);
+	i2c_rate = clk_get_rate(&i2c->clk);
 
 	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
 	divh = 0;
@@ -362,7 +361,6 @@ static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
 		      bus->name, ret);
 		return ret;
 	}
-	priv->clk_id = ret;
 
 	return 0;
 }
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 1e2a29b..64bbf0c 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -49,7 +49,8 @@ static int msm_sdc_clk_init(struct udevice *dev)
 					"clock-frequency", 400000);
 	uint clkd[2]; /* clk_id and clk_no */
 	int clk_offset;
-	struct udevice *clk;
+	struct udevice *clk_dev;
+	struct clk clk;
 	int ret;
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
@@ -61,11 +62,17 @@ static int msm_sdc_clk_init(struct udevice *dev)
 	if (clk_offset < 0)
 		return clk_offset;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 	if (ret)
 		return ret;
 
-	ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+	clk.id = clkd[1];
+	ret = clk_request(clk_dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, clk_rate);
+	clk_free(&clk);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 750ab9f..d41d60c 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -24,8 +24,7 @@ struct rockchip_mmc_plat {
 };
 
 struct rockchip_dwmmc_priv {
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	struct dwmci_host host;
 };
 
@@ -35,7 +34,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = clk_set_periph_rate(priv->clk, priv->periph, freq);
+	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
 		debug("%s: err=%d\n", __func__, ret);
 		return ret;
@@ -81,7 +80,6 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
 		return ret;
-	priv->periph = ret;
 
 	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
 				 "clock-freq-min-max", minmax, 2))
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 4978cca..152e987 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -651,8 +651,7 @@ int uniphier_sd_probe(struct udevice *dev)
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	fdt_addr_t base;
-	struct udevice *clk_dev;
-	int clk_id;
+	struct clk clk;
 	int ret;
 
 	priv->dev = dev;
@@ -665,20 +664,22 @@ int uniphier_sd_probe(struct udevice *dev)
 	if (!priv->regbase)
 		return -ENOMEM;
 
-	clk_id = clk_get_by_index(dev, 0, &clk_dev);
-	if (clk_id < 0) {
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0) {
 		dev_err(dev, "failed to get host clock\n");
-		return clk_id;
+		return ret;
 	}
 
 	/* set to max rate */
-	priv->mclk = clk_set_periph_rate(clk_dev, clk_id, ULONG_MAX);
+	priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 	if (IS_ERR_VALUE(priv->mclk)) {
 		dev_err(dev, "failed to set rate for host clock\n");
+		clk_free(&clk);
 		return priv->mclk;
 	}
 
-	ret = clk_enable(clk_dev, clk_id);
+	ret = clk_enable(&clk);
+	clk_free(&clk);
 	if (ret) {
 		dev_err(dev, "failed to enable host clock\n");
 		return ret;
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 80fb89e..a7cab13 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -150,7 +150,8 @@ static int msm_uart_clk_init(struct udevice *dev)
 					"clock-frequency", 115200);
 	uint clkd[2]; /* clk_id and clk_no */
 	int clk_offset;
-	struct udevice *clk;
+	struct udevice *clk_dev;
+	struct clk clk;
 	int ret;
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
@@ -162,11 +163,17 @@ static int msm_uart_clk_init(struct udevice *dev)
 	if (clk_offset < 0)
 		return clk_offset;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 	if (ret)
 		return ret;
 
-	ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+	clk.id = clkd[1];
+	ret = clk_request(clk_dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, clk_rate);
+	clk_free(&clk);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
index af9fbbf..c2141f0 100644
--- a/drivers/serial/serial_pic32.c
+++ b/drivers/serial/serial_pic32.c
@@ -135,7 +135,7 @@ static int pic32_uart_getc(struct udevice *dev)
 static int pic32_uart_probe(struct udevice *dev)
 {
 	struct pic32_uart_priv *priv = dev_get_priv(dev);
-	struct udevice *clkdev;
+	struct clk clk;
 	fdt_addr_t addr;
 	fdt_size_t size;
 	int ret;
@@ -148,10 +148,11 @@ static int pic32_uart_probe(struct udevice *dev)
 	priv->base = ioremap(addr, size);
 
 	/* get clock rate */
-	ret = clk_get_by_index(dev, 0, &clkdev);
+	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
 		return ret;
-	priv->uartclk = clk_get_periph_rate(clkdev, ret);
+	priv->uartclk = clk_get_rate(&clk);
+	clk_free(&clk);
 
 	/* initialize serial */
 	return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index cb55c5a..6225479 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -94,13 +94,13 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
 	u32 uclk;
 
 #ifdef CONFIG_CLK_EXYNOS
-	struct udevice *clk_dev;
+	struct clk clk;
 	u32 ret;
 
-	ret = clk_get_by_index(dev, 1, &clk_dev);
+	ret = clk_get_by_index(dev, 1, &clk);
 	if (ret < 0)
 		return ret;
-	uclk = clk_get_periph_rate(clk_dev, ret);
+	uclk = clk_get_rate(&clk);
 #else
 	uclk = get_uart_clk(plat->port_id);
 #endif
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 9eff423..bc6dfd8 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -35,8 +35,7 @@ struct rockchip_spi_platdata {
 
 struct rockchip_spi_priv {
 	struct rockchip_spi *regs;
-	struct udevice *clk;
-	int clk_id;
+	struct clk clk;
 	unsigned int max_freq;
 	unsigned int mode;
 	ulong last_transaction_us;	/* Time of last transaction end */
@@ -144,7 +143,6 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 		      bus->name, ret);
 		return ret;
 	}
-	priv->clk_id = ret;
 
 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 					 50000000);
@@ -175,7 +173,7 @@ static int rockchip_spi_probe(struct udevice *bus)
 	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
 	 * is the assumed speed for CLK_GENERAL.
 	 */
-	ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
+	ret = clk_set_rate(&priv->clk, 99000000);
 	if (ret < 0) {
 		debug("%s: Failed to set clock: %d\n", __func__, ret);
 		return ret;
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 4444988..e0377ca 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -26,15 +26,15 @@ static int ehci_usb_probe(struct udevice *dev)
 	int i;
 
 	for (i = 0; ; i++) {
-		struct udevice *clk_dev;
-		int clk_id;
+		struct clk clk;
+		int ret;
 
-		clk_id = clk_get_by_index(dev, i, &clk_dev);
-		if (clk_id < 0)
+		ret = clk_get_by_index(dev, i, &clk);
+		if (ret < 0)
 			break;
-		if (clk_enable(clk_dev, clk_id))
-			printf("failed to enable clock (dev=%s, id=%d)\n",
-			       clk_dev->name, clk_id);
+		if (clk_enable(&clk))
+			printf("failed to enable clock %d\n", i);
+		clk_free(&clk);
 	}
 
 	hccr = map_physmem(dev_get_addr(dev), 0x100, MAP_NOCACHE);
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 124ddf6..7ece038 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1009,8 +1009,7 @@ int rk_edp_probe(struct udevice *dev)
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_edp_priv *priv = dev_get_priv(dev);
 	struct rk3288_edp *regs = priv->regs;
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	int ret;
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
@@ -1026,8 +1025,8 @@ int rk_edp_probe(struct udevice *dev)
 
 	ret = clk_get_by_index(dev, 1, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
@@ -1036,8 +1035,8 @@ int rk_edp_probe(struct udevice *dev)
 
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 192000000);
+		ret = clk_set_rate(&clk, 192000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 5fcb61a..8dd2c87 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -859,15 +859,15 @@ static int rk_hdmi_probe(struct udevice *dev)
 {
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	struct udevice *reg, *clk;
-	int periph;
+	struct udevice *reg;
+	struct clk clk;
 	int ret;
 	int vop_id = uc_plat->source_id;
 
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
@@ -880,8 +880,8 @@ static int rk_hdmi_probe(struct udevice *dev)
 	 */
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 384000000);
+		ret = clk_set_rate(&clk, 384000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
index dc10b86..fcbb4d6 100644
--- a/drivers/video/rockchip/rk_lvds.c
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <display.h>
 #include <dm.h>
 #include <edid.h>
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index db09d9a..cc26f19 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -195,7 +195,8 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 	struct udevice *disp;
 	int ret, remote, i, offset;
 	struct display_plat *disp_uc_plat;
-	struct udevice *clk;
+	struct udevice *dev_clk;
+	struct clk clk;
 
 	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
 	debug("vop_id=%d\n", vop_id);
@@ -237,11 +238,13 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 		return ret;
 	}
 
-	ret = rkclk_get_clk(CLK_NEW, &clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
 	if (!ret) {
-		ret = clk_set_periph_rate(clk, DCLK_VOP0 + remote_vop_id,
-					  timing.pixelclock.typ);
+		clk.id = DCLK_VOP0 + remote_vop_id;
+		ret = clk_request(dev_clk, &clk);
 	}
+	if (!ret)
+		ret = clk_set_rate(&clk, timing.pixelclock.typ);
 	if (ret) {
 		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
 		return ret;
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
new file mode 100644
index 0000000..07c1065
--- /dev/null
+++ b/include/clk-uclass.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLK_UCLASS_H
+#define _CLK_UCLASS_H
+
+/* See clk.h for background documentation. */
+
+#include <clk.h>
+#include <fdtdec.h>
+
+/**
+ * struct clk_ops - The functions that a clock driver must implement.
+ */
+struct clk_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) clock specifier.
+	 *
+	 * The clock core calls this function as the first step in implementing
+	 * a client's clk_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the clock core will use a
+	 * default implementation, which assumes #clock-cells = <1>, and that
+	 * the DT cell contains a simple integer clock ID.
+	 *
+	 * At present, the clock API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @clock:	The clock struct to hold the translation result.
+	 * @args:	The clock specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct clk *clock,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated clock.
+	 *
+	 * The clock core calls this function as the second step in
+	 * implementing a client's clk_get_by_*() call, following a successful
+	 * xxx_xlate() call, or as the only step in implementing a client's
+	 * clk_request() call.
+	 *
+	 * @clock:	The clock struct to request; this has been fille in by
+	 *		a previoux xxx_xlate() function call, or by the caller
+	 *		of clk_request().
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct clk *clock);
+	/**
+	 * free - Free a previously requested clock.
+	 *
+	 * This is the implementation of the client clk_free() API.
+	 *
+	 * @clock:	The clock to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct clk *clock);
+	/**
+	 * get_rate() - Get current clock rate.
+	 *
+	 * @clk:	The clock to query.
+	 * @return clock rate in Hz, or -ve error code
+	 */
+	ulong (*get_rate)(struct clk *clk);
+	/**
+	 * set_rate() - Set current clock rate.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @rate:	New clock rate in Hz.
+	 * @return new rate, or -ve error code.
+	 */
+	ulong (*set_rate)(struct clk *clk, ulong rate);
+	/**
+	 * enable() - Enable a clock.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*enable)(struct clk *clk);
+	/**
+	 * disable() - Disable a clock.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*disable)(struct clk *clk);
+};
+
+#endif
diff --git a/include/clk.h b/include/clk.h
index ca20c3d..2f31cf7 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2015 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -8,125 +9,166 @@
 #ifndef _CLK_H_
 #define _CLK_H_
 
-#include <errno.h>
 #include <linux/types.h>
 
-struct udevice;
+/**
+ * A clock is a hardware signal that oscillates autonomously at a specific
+ * frequency and duty cycle. Most hardware modules require one or more clock
+ * signal to drive their operation. Clock signals are typically generated
+ * externally to the HW module consuming them, by an entity this API calls a
+ * clock provider. This API provides a standard means for drivers to enable and
+ * disable clocks, and to set the rate at which they oscillate.
+ *
+ * A driver that implements UCLASS_CLOCK is a clock provider. A provider will
+ * often implement multiple separate clocks, since the hardware it manages
+ * often has this capability. clock_uclass.h describes the interface which
+ * clock providers must implement.
+ *
+ * Clock consumers/clients are the HW modules driven by the clock signals. This
+ * header file describes the API used by drivers for those HW modules.
+ */
 
-int soc_clk_dump(void);
+struct udevice;
 
-struct clk_ops {
-	/**
-	 * get_rate() - Get current clock rate
-	 *
-	 * @dev:	Device to check (UCLASS_CLK)
-	 * @return clock rate in Hz, or -ve error code
-	 */
-	ulong (*get_rate)(struct udevice *dev);
-
-	/**
-	 * set_rate() - Set current clock rate
-	 *
-	 * @dev:	Device to adjust
-	 * @rate:	New clock rate in Hz
-	 * @return new rate, or -ve error code
-	 */
-	ulong (*set_rate)(struct udevice *dev, ulong rate);
-
-	/**
-	 * enable() - Enable the clock for a peripheral
-	 *
-	 * @dev:	clock provider
-	 * @periph:	Peripheral ID to enable
-	 * @return zero on success, or -ve error code
-	 */
-	int (*enable)(struct udevice *dev, int periph);
-
-	/**
-	 * get_periph_rate() - Get clock rate for a peripheral
-	 *
-	 * @dev:	Device to check (UCLASS_CLK)
-	 * @periph:	Peripheral ID to check
-	 * @return clock rate in Hz, or -ve error code
-	 */
-	ulong (*get_periph_rate)(struct udevice *dev, int periph);
-
-	/**
-	 * set_periph_rate() - Set current clock rate for a peripheral
-	 *
-	 * @dev:	Device to update (UCLASS_CLK)
-	 * @periph:	Peripheral ID to update
-	 * @return new clock rate in Hz, or -ve error code
+/**
+ * struct clk - A handle to (allowing control of) a single clock.
+ *
+ * Clients provide storage for clock handles. The content of the structure is
+ * managed solely by the clock API and clock drivers. A clock struct is
+ * initialized by "get"ing the clock struct. The clock struct is passed to all
+ * other clock APIs to identify which clock signal to operate upon.
+ *
+ * @dev: The device which implements the clock signal.
+ * @id: The clock signal ID within the provider.
+ *
+ * Currently, the clock API assumes that a single integer ID is enough to
+ * identify and configure any clock signal for any clock provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow clock providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct clk {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
 	 */
-	ulong (*set_periph_rate)(struct udevice *dev, int periph, ulong rate);
+	unsigned long id;
 };
 
-#define clk_get_ops(dev)	((struct clk_ops *)(dev)->driver->ops)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * clock_get_by_index - Get/request a clock by integer index.
+ *
+ * This looks up and requests a clock. The index is relative to the client
+ * device; each device is assumed to have n clocks associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device clock indices to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the clock to request, within the client's list of
+ *		clocks.
+ * @clock	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
 
 /**
- * clk_get_rate() - Get current clock rate
+ * clock_get_by_name - Get/request a clock by name.
  *
- * @dev:	Device to check (UCLASS_CLK)
- * @return clock rate in Hz, or -ve error code
+ * This looks up and requests a clock. The name is relative to the client
+ * device; each device is assumed to have n clocks associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device clock names to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the clock to request, within the client's list of
+ *		clocks.
+ * @clock:	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
  */
-ulong clk_get_rate(struct udevice *dev);
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
+#else
+static inline int clk_get_by_index(struct udevice *dev, int index,
+				   struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static int clk_get_by_name(struct udevice *dev, const char *name,
+			   struct clk *clk)
+{
+	return -ENOSYS;
+}
+#endif
 
 /**
- * clk_set_rate() - Set current clock rate
+ * clk_request - Request a clock by provider-specific ID.
  *
- * @dev:	Device to adjust
- * @rate:	New clock rate in Hz
- * @return new rate, or -ve error code
+ * This requests a clock using a provider-specific ID. Generally, this function
+ * should not be used, since clk_get_by_index/name() provide an interface that
+ * better separates clients from intimate knowledge of clock providers.
+ * However, this function may be useful in core SoC-specific code.
+ *
+ * @dev:	The clock provider device.
+ * @clock:	A pointer to a clock struct to initialize. The caller must
+ *		have already initialized any field in this struct which the
+ *		clock provider uses to identify the clock.
+ * @return 0 if OK, or a negative error code.
  */
-ulong clk_set_rate(struct udevice *dev, ulong rate);
+int clk_request(struct udevice *dev, struct clk *clk);
 
 /**
- * clk_enable() - Enable the clock for a peripheral
+ * clock_free - Free a previously requested clock.
  *
- * @dev:	clock provider
- * @periph:	Peripheral ID to enable
- * @return zero on success, or -ve error code
+ * @clock:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return 0 if OK, or a negative error code.
  */
-int clk_enable(struct udevice *dev, int periph);
+int clk_free(struct clk *clk);
 
 /**
- * clk_get_periph_rate() - Get current clock rate for a peripheral
+ * clk_get_rate() - Get current clock rate.
  *
- * @dev:	Device to check (UCLASS_CLK)
- * @return clock rate in Hz, -ve error code
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return clock rate in Hz, or -ve error code.
  */
-ulong clk_get_periph_rate(struct udevice *dev, int periph);
+ulong clk_get_rate(struct clk *clk);
 
 /**
- * clk_set_periph_rate() - Set current clock rate for a peripheral
+ * clk_set_rate() - Set current clock rate.
  *
- * @dev:	Device to update (UCLASS_CLK)
- * @periph:	Peripheral ID to update
- * @return new clock rate in Hz, or -ve error code
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @rate:	New clock rate in Hz.
+ * @return new rate, or -ve error code.
  */
-ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate);
+ulong clk_set_rate(struct clk *clk, ulong rate);
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 /**
- * clk_get_by_index() - look up a clock referenced by a device
+ * clk_enable() - Enable (turn on) a clock.
  *
- * Parse a device's 'clocks' list, returning information on the indexed clock,
- * ensuring that it is activated.
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int clk_enable(struct clk *clk);
+
+/**
+ * clk_disable() - Disable (turn off) a clock.
  *
- * @dev:	Device containing the clock reference
- * @index:	Clock index to return (0 = first)
- * @clk_devp:	Returns clock device
- * @return:	Peripheral ID for the device to control. This is the first
- *		argument after the clock node phandle. If there is no arguemnt,
- *		returns 0. Return -ve error code on any error
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return zero on success, or -ve error code.
  */
-int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp);
-#else
-static inline int clk_get_by_index(struct udevice *dev, int index,
-				   struct udevice **clk_devp)
-{
-	return -ENOSYS;
-}
-#endif
+int clk_disable(struct clk *clk);
 
-#endif /* _CLK_H_ */
+int soc_clk_dump(void);
+
+#endif
diff --git a/test/dm/clk.c b/test/dm/clk.c
index 9ff6d95..712a1e6 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -5,55 +5,99 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
-#include <asm/test.h>
+#include <asm/clk.h>
 #include <dm/test.h>
 #include <linux/err.h>
 #include <test/ut.h>
 
-/* Test that we can find and adjust clocks */
-static int dm_test_clk_base(struct unit_test_state *uts)
+static int dm_test_clk(struct unit_test_state *uts)
 {
-	struct udevice *clk;
+	struct udevice *dev_fixed, *dev_clk, *dev_test;
 	ulong rate;
 
-	ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
-	rate = clk_get_rate(clk);
-	ut_asserteq(SANDBOX_CLK_RATE, rate);
-	ut_asserteq(-EINVAL, clk_set_rate(clk, 0));
-	ut_assertok(clk_set_rate(clk, rate * 2));
-	ut_asserteq(SANDBOX_CLK_RATE * 2, clk_get_rate(clk));
+	ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
+					      &dev_fixed));
 
-	return 0;
-}
-DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+	ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
+					      &dev_clk));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+	ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
 
-/* Test that peripheral clocks work as expected */
-static int dm_test_clk_periph(struct unit_test_state *uts)
-{
-	struct udevice *clk;
-	ulong rate;
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
+					      &dev_test));
+	ut_assertok(sandbox_clk_test_get(dev_test));
 
-	ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
-	rate = clk_set_periph_rate(clk, PERIPH_ID_COUNT, 123);
-	ut_asserteq(-EINVAL, rate);
-	ut_asserteq(1, IS_ERR_VALUE(rate));
+	ut_asserteq(1234,
+		    sandbox_clk_test_get_rate(dev_test,
+					      SANDBOX_CLK_TEST_ID_FIXED));
+	ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
+						 SANDBOX_CLK_TEST_ID_SPI));
+	ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
+						 SANDBOX_CLK_TEST_ID_I2C));
 
-	rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 123);
-	ut_asserteq(0, rate);
-	ut_asserteq(123, clk_get_periph_rate(clk, PERIPH_ID_SPI));
+	rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED,
+					 12345);
+	ut_assert(IS_ERR_VALUE(rate));
+	rate = sandbox_clk_test_get_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED);
+	ut_asserteq(1234, rate);
 
-	rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
-	ut_asserteq(123, rate);
+	ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
+						 SANDBOX_CLK_TEST_ID_SPI,
+						 1000));
+	ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
+						 SANDBOX_CLK_TEST_ID_I2C,
+						 2000));
 
-	rate = clk_set_periph_rate(clk, PERIPH_ID_I2C, 567);
+	ut_asserteq(1000, sandbox_clk_test_get_rate(dev_test,
+						    SANDBOX_CLK_TEST_ID_SPI));
+	ut_asserteq(2000, sandbox_clk_test_get_rate(dev_test,
+						    SANDBOX_CLK_TEST_ID_I2C));
 
-	rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
-	ut_asserteq(1234, rate);
+	ut_asserteq(1000, sandbox_clk_test_set_rate(dev_test,
+						    SANDBOX_CLK_TEST_ID_SPI,
+						    10000));
+	ut_asserteq(2000, sandbox_clk_test_set_rate(dev_test,
+						    SANDBOX_CLK_TEST_ID_I2C,
+						    20000));
+
+	rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
+	ut_assert(IS_ERR_VALUE(rate));
+	rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
+	ut_assert(IS_ERR_VALUE(rate));
+
+	ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
+						     SANDBOX_CLK_TEST_ID_SPI));
+	ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
+						     SANDBOX_CLK_TEST_ID_I2C));
+
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+	ut_asserteq(10000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(20000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_SPI));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_I2C));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	ut_assertok(sandbox_clk_test_disable(dev_test,
+					     SANDBOX_CLK_TEST_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	ut_assertok(sandbox_clk_test_disable(dev_test,
+					     SANDBOX_CLK_TEST_ID_I2C));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
 
-	ut_asserteq(567, clk_get_periph_rate(clk, PERIPH_ID_I2C));
+	ut_assertok(sandbox_clk_test_free(dev_test));
 
 	return 0;
 }
-DM_TEST(dm_test_clk_periph, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk, DM_TESTF_SCAN_FDT);
-- 
cgit v0.10.2


From c4adf9db5d382be6d13a19585f28de6f3e4e3d61 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:16:56 +0200
Subject: spl: nand: sunxi: remove support for so-called 'syndrome' mode

The sunxi SPL NAND controller driver supports use 'BootROM'-like configs,
that is, configs where the ECC bytes and real data are interleaved in the
page instead of putting ECC bytes in the OOB area.

Doing that has several drawbacks:
- since you're interleaving data and ECC bytes you can't use the whole page
  otherwise you might override the bad block marker with non-FF bytes.
- to solve the bad block marker problem, the ROM code supports partially
  using the page, but this introduces a huge penalty both in term of read
  speed and NAND memory usage. While this is fine for rather small
  binaries(like the SPL one which is at maximum 24KB large), it becomes
  non-negligible for the bootloader image (several hundred of KB).
- auto-detection of the page size is not reliable (this is in my opinion
  the biggest problem). If you get the page size wrong, you'll end up
  reading data at a different offset than what was specified by the caller
  and the reading may succeed (if valid data were written at this address).

For all those reasons I think it's wiser to completely remove support for
'syndrome' configs. If we ever need to support it again, then I'd recommend
specifying all the config parameters through Kconfig options.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index b0e07aa..1739da2 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -119,9 +119,6 @@ const uint16_t random_seed[128] = {
 	0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 };
 
-/* random seed used for syndrome calls */
-const uint16_t random_seed_syndrome = 0x4a80;
-
 #define MAX_RETRIES 10
 
 static int check_value_inner(int offset, int expected_bits,
@@ -183,7 +180,7 @@ void nand_init(void)
 }
 
 static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
-	int addr_cycles, uint32_t real_addr, dma_addr_t dst, int syndrome)
+	int addr_cycles, uint32_t real_addr, dma_addr_t dst)
 {
 	uint32_t val;
 	int i, ecc_off = 0;
@@ -209,17 +206,11 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 	page = real_addr / page_size;
 	column = real_addr % page_size;
 
-	if (syndrome)
-		column += (column / ecc_page_size) * ecc_off;
-
 	/* clear ecc status */
 	writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 
 	/* Choose correct seed */
-	if (syndrome)
-		rand_seed = random_seed_syndrome;
-	else
-		rand_seed = random_seed[page % 128];
+	rand_seed = random_seed[page % 128];
 
 	writel((rand_seed << 16) | NFC_ECC_RANDOM_EN | NFC_ECC_EN
 		| NFC_ECC_PIPELINE | (ecc_mode << 12),
@@ -228,9 +219,8 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 	val = readl(SUNXI_NFC_BASE + NFC_CTL);
 	writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
 
-	if (!syndrome)
-		writel(page_size + (column / ecc_page_size) * ecc_off,
-		       SUNXI_NFC_BASE + NFC_SPARE_AREA);
+	writel(page_size + (column / ecc_page_size) * ecc_off,
+	       SUNXI_NFC_BASE + NFC_SPARE_AREA);
 
 	flush_dcache_range(dst, ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
 
@@ -266,7 +256,7 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 	writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
 		NFC_PAGE_CMD | NFC_WAIT_FLAG |
 		((addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) |
-		NFC_SEND_ADR | NFC_DATA_SWAP_METHOD | (syndrome ? NFC_SEQ : 0),
+		NFC_SEND_ADR | NFC_DATA_SWAP_METHOD,
 		SUNXI_NFC_BASE + NFC_CMD);
 
 	if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
@@ -292,7 +282,7 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 }
 
 static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
-	int addr_cycles, uint32_t offs, uint32_t size, void *dest, int syndrome)
+	int addr_cycles, uint32_t offs, uint32_t size, void *dest)
 {
 	void *end = dest + size;
 
@@ -301,16 +291,14 @@ static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
 
 	for ( ;dest < end; dest += ecc_page_size, offs += ecc_page_size) {
 		if (nand_read_page(page_size, ecc_strength, ecc_page_size,
-				   addr_cycles, offs, (dma_addr_t)dest,
-				   syndrome))
+				   addr_cycles, offs, (dma_addr_t)dest))
 			return -1;
 	}
 
 	return 0;
 }
 
-static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest,
-			    int syndrome)
+static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest)
 {
 	const struct {
 		int page_size;
@@ -337,7 +325,7 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest,
 					  nand_configs[i].ecc_strength,
 					  nand_configs[i].ecc_page_size,
 					  nand_configs[i].addr_cycles,
-					  offs, size, dest, syndrome) == 0) {
+					  offs, size, dest) == 0) {
 				debug("success\n");
 				nand_config = i;
 				return 0;
@@ -351,48 +339,32 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest,
 			     nand_configs[nand_config].ecc_strength,
 			     nand_configs[nand_config].ecc_page_size,
 			     nand_configs[nand_config].addr_cycles,
-			     offs, size, dest, syndrome);
+			     offs, size, dest);
 }
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 {
-#if CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO
-	/*
-	 * u-boot-dtb.bin appended to SPL, use syndrome (like the BROM does)
-	 * and try different erase block sizes to find the backup.
-	 */
-	const uint32_t boot_offsets[] = {
-		0 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
-		1 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
-		2 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
-		4 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
-	};
-	const int syndrome = 1;
-#else
 	/*
-	 * u-boot-dtb.bin on its own partition, do not use syndrome, u-boot
-	 * partition sits after 2 eraseblocks (spl, spl-backup), look for
-	 * backup u-boot 1 erase block further.
+	 * u-boot partition sits after 2 eraseblocks (spl, spl-backup), look
+	 * for backup u-boot 1 erase block further.
 	 */
 	const uint32_t eraseblock_size = CONFIG_SYS_NAND_U_BOOT_OFFS / 2;
 	const uint32_t boot_offsets[] = {
 		CONFIG_SYS_NAND_U_BOOT_OFFS,
 		CONFIG_SYS_NAND_U_BOOT_OFFS + eraseblock_size,
 	};
-	const int syndrome = 0;
-#endif
 	int i;
 
 	if (offs == CONFIG_SYS_NAND_U_BOOT_OFFS) {
 		for (i = 0; i < ARRAY_SIZE(boot_offsets); i++) {
 			if (nand_read_buffer(boot_offsets[i], size,
-					     dest, syndrome) == 0)
+					     dest) == 0)
 				return 0;
 		}
 		return -1;
 	}
 
-	return nand_read_buffer(offs, size, dest, syndrome);
+	return nand_read_buffer(offs, size, dest);
 }
 
 void nand_deselect(void)
-- 
cgit v0.10.2


From 494e108651a3c55b85d060202e941e4d8d68ce5e Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:16:57 +0200
Subject: spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependency

The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced
to explicitly depend on platforms that are not already defining it in their
include/configs/<board>.h header.

Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS
depends on it, remove the dependency on NAND_SUNXI and make it dependent
on SPL selection.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 2fc73ef..5fe169f 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -99,17 +99,24 @@ config SYS_NAND_BUSWIDTH_16BIT
 	    not available while configuring controller. So a static CONFIG_NAND_xx
 	    is needed to know the device's bus-width in advance.
 
-# Enhance depends when converting drivers to Kconfig which use this config
+if SPL
+
+config SYS_NAND_U_BOOT_LOCATIONS
+	bool "Define U-boot binaries locations in NAND"
+	help
+	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
+	This option should not be enabled when compiling U-boot for boards
+	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
+	file.
+
 config SYS_NAND_U_BOOT_OFFS
 	hex "Location in NAND to read U-Boot from"
 	default 0x8000 if NAND_SUNXI
-	depends on NAND_SUNXI
+	depends on SYS_NAND_U_BOOT_LOCATIONS
 	help
 	Set the offset from the start of the nand where u-boot should be
 	loaded from.
 
-if SPL
-
 config SPL_NAND_DENALI
 	bool "Support Denali NAND controller for SPL"
 	help
-- 
cgit v0.10.2


From 80ef700f8df1f85dd3b0880584e2e2a998a9b3dd Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:16:58 +0200
Subject: spl: nand: support redundant u-boot image

On modern NAND it's more than recommended to have a backup copy of the
u-boot binary to recover from corruption: bitflips are quite common on
MLC NANDs, and the read-disturbance will corrupt your u-boot partitition
more quickly than what you would see on an SLC NAND.

Add an extra Kconfig option to specify the offset of the redundant u-boot
image.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
[scottwood: added ifdef to fix build break]
Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 7cf0d1b..0e35e0f 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -134,6 +134,13 @@ int spl_nand_load_image(void)
 #endif
 	/* Load u-boot */
 	err = spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS, header);
+#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
+#if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
+	if (err)
+		err = spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND,
+					    header);
+#endif
+#endif
 	nand_deselect();
 	return err;
 }
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5fe169f..8c46a2f 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -117,6 +117,14 @@ config SYS_NAND_U_BOOT_OFFS
 	Set the offset from the start of the nand where u-boot should be
 	loaded from.
 
+config SYS_NAND_U_BOOT_OFFS_REDUND
+	hex "Location in NAND to read U-Boot from"
+	default SYS_NAND_U_BOOT_OFFS
+	depends on SYS_NAND_U_BOOT_LOCATIONS
+	help
+	Set the offset from the start of the nand where the redundant u-boot
+	should be loaded from.
+
 config SPL_NAND_DENALI
 	bool "Support Denali NAND controller for SPL"
 	help
-- 
cgit v0.10.2


From fa3011587887ba222bc9337d9ac17f3000db63b2 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:16:59 +0200
Subject: spl: nand: sunxi: stop guessing the redundant u-boot offset

Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess
where the redundant u-boot image is based on simple (and most of the time
erroneous) heuristics.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

# Conflicts:
#	drivers/mtd/nand/sunxi_nand_spl.c

diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index 1739da2..13e6eab 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -344,26 +344,6 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest)
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 {
-	/*
-	 * u-boot partition sits after 2 eraseblocks (spl, spl-backup), look
-	 * for backup u-boot 1 erase block further.
-	 */
-	const uint32_t eraseblock_size = CONFIG_SYS_NAND_U_BOOT_OFFS / 2;
-	const uint32_t boot_offsets[] = {
-		CONFIG_SYS_NAND_U_BOOT_OFFS,
-		CONFIG_SYS_NAND_U_BOOT_OFFS + eraseblock_size,
-	};
-	int i;
-
-	if (offs == CONFIG_SYS_NAND_U_BOOT_OFFS) {
-		for (i = 0; i < ARRAY_SIZE(boot_offsets); i++) {
-			if (nand_read_buffer(boot_offsets[i], size,
-					     dest) == 0)
-				return 0;
-		}
-		return -1;
-	}
-
 	return nand_read_buffer(offs, size, dest);
 }
 
-- 
cgit v0.10.2


From bb9783b66bf56a27b4db8dc444dda6c380816e99 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:17:00 +0200
Subject: spl: nand: sunxi: rework status polling loop

check_value_xxx() helpers are using a 1ms delay between each test, which
can be quite long for some operations (like a page read on an SLC NAND).
Since we don't have anything to do but to poll this register, reduce the
delay between each test to 1us.

While we're at it, rename the max_number_of_retries parameters and the
MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that
we're actually waiting a given amount of time and not only a number of
retries.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index 13e6eab..55b3c8a 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -119,35 +119,31 @@ const uint16_t random_seed[128] = {
 	0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 };
 
-#define MAX_RETRIES 10
+#define DEFAULT_TIMEOUT_US	100000
 
 static int check_value_inner(int offset, int expected_bits,
-				int max_number_of_retries, int negation)
+			     int timeout_us, int negation)
 {
-	int retries = 0;
 	do {
 		int val = readl(offset) & expected_bits;
 		if (negation ? !val : val)
 			return 1;
-		mdelay(1);
-		retries++;
-	} while (retries < max_number_of_retries);
+		udelay(1);
+	} while (--timeout_us);
 
 	return 0;
 }
 
 static inline int check_value(int offset, int expected_bits,
-				int max_number_of_retries)
+			      int timeout_us)
 {
-	return check_value_inner(offset, expected_bits,
-					max_number_of_retries, 0);
+	return check_value_inner(offset, expected_bits, timeout_us, 0);
 }
 
 static inline int check_value_negated(int offset, int unexpected_bits,
-					int max_number_of_retries)
+				      int timeout_us)
 {
-	return check_value_inner(offset, unexpected_bits,
-					max_number_of_retries, 1);
+	return check_value_inner(offset, unexpected_bits, timeout_us, 1);
 }
 
 void nand_init(void)
@@ -162,7 +158,7 @@ void nand_init(void)
 	       SUNXI_NFC_BASE + NFC_CTL);
 
 	if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
-				 NFC_CTL_RESET, MAX_RETRIES)) {
+				 NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
 		printf("Couldn't initialize nand\n");
 	}
 
@@ -172,7 +168,7 @@ void nand_init(void)
 	       SUNXI_NFC_BASE + NFC_CMD);
 
 	if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
-			 MAX_RETRIES)) {
+			 DEFAULT_TIMEOUT_US)) {
 		printf("Error timeout waiting for nand reset\n");
 		return;
 	}
@@ -260,14 +256,15 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 		SUNXI_NFC_BASE + NFC_CMD);
 
 	if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
-			 MAX_RETRIES)) {
+			 DEFAULT_TIMEOUT_US)) {
 		printf("Error while initializing dma interrupt\n");
 		return -1;
 	}
 	writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 
 	if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
-				 SUNXI_DMA_DDMA_CFG_REG_LOADING, MAX_RETRIES)) {
+				 SUNXI_DMA_DDMA_CFG_REG_LOADING,
+				 DEFAULT_TIMEOUT_US)) {
 		printf("Error while waiting for dma transfer to finish\n");
 		return -1;
 	}
-- 
cgit v0.10.2


From 4e7d1b3bebc5bf5176d35ac32378bcf0ff6e5914 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:17:01 +0200
Subject: spl: nand: sunxi: split 'load page' and 'read page' logic

Split the 'load page' and 'read page' logic in 2 different functions so
we can later load the page and test different ECC configs without the
penalty of reloading the same page in the NAND cache.

We also move common setup to a dedicated function (nand_apply_config()) to
avoid rewriting the same values in NFC registers each time we read a page.

These new functions are passed a pointer to an nfc_config struct to limit
the number of parameters.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index 55b3c8a..b43f2af 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -66,6 +66,8 @@
 #define NFC_ROW_AUTO_INC           (1 << 27)
 #define NFC_SEND_CMD3              (1 << 28)
 #define NFC_SEND_CMD4              (1 << 29)
+#define NFC_RAW_CMD                (0 << 30)
+#define NFC_PAGE_CMD               (2 << 30)
 
 #define NFC_ST_CMD_INT_FLAG        (1 << 1)
 #define NFC_ST_DMA_INT_FLAG        (1 << 2)
@@ -78,9 +80,6 @@
 #define NFC_CMD_RNDOUT             0x05
 #define NFC_CMD_READSTART          0x30
 
-
-#define NFC_PAGE_CMD               (2 << 30)
-
 #define SUNXI_DMA_CFG_REG0              0x300
 #define SUNXI_DMA_SRC_START_ADDR_REG0   0x304
 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
@@ -97,6 +96,15 @@
 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
 
+struct nfc_config {
+	int page_size;
+	int ecc_strength;
+	int ecc_size;
+	int addr_cycles;
+	int nseeds;
+	bool randomize;
+};
+
 /* minimal "boot0" style NAND support for Allwinner A20 */
 
 /* random seed used by linux */
@@ -175,50 +183,70 @@ void nand_init(void)
 	writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 }
 
-static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
-	int addr_cycles, uint32_t real_addr, dma_addr_t dst)
+static void nand_apply_config(const struct nfc_config *conf)
 {
-	uint32_t val;
-	int i, ecc_off = 0;
-	uint16_t ecc_mode = 0;
-	uint16_t rand_seed;
-	uint32_t page;
-	uint16_t column;
-	static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
+	u32 val;
 
-	for (i = 0; i < ARRAY_SIZE(strengths); i++) {
-		if (ecc_strength == strengths[i]) {
-			ecc_mode = i;
-			break;
-		}
+	val = readl(SUNXI_NFC_BASE + NFC_CTL);
+	val &= ~NFC_CTL_PAGE_SIZE_MASK;
+	writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
+	       SUNXI_NFC_BASE + NFC_CTL);
+	writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
+	writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
+}
+
+static int nand_load_page(const struct nfc_config *conf, u32 offs)
+{
+	int page = offs / conf->page_size;
+
+	writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
+	       (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
+	       (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
+	       SUNXI_NFC_BASE + NFC_RCMD_SET);
+	writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
+	writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
+	writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
+	writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG |
+	       ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR,
+	       SUNXI_NFC_BASE + NFC_CMD);
+
+	if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
+			 DEFAULT_TIMEOUT_US)) {
+		printf("Error while initializing dma interrupt\n");
+		return -EIO;
 	}
 
-	/* HW ECC always request ECC bytes for 1024 bytes blocks */
-	ecc_off = DIV_ROUND_UP(ecc_strength * fls(8 * 1024), 8);
-	/* HW ECC always work with even numbers of ECC bytes */
-	ecc_off += (ecc_off & 1);
-	ecc_off += 4; /* prepad */
+	return 0;
+}
+
+static int nand_read_page(const struct nfc_config *conf, u32 offs,
+			  void *dest, int len)
+{
+	dma_addr_t dst = (dma_addr_t)dest;
+	int nsectors = len / conf->ecc_size;
+	u16 rand_seed;
+	u32 val;
+	int page;
+
+	page = offs / conf->page_size;
 
-	page = real_addr / page_size;
-	column = real_addr % page_size;
+	if (offs % conf->page_size || len % conf->ecc_size ||
+	    len > conf->page_size || len < 0)
+		return -EINVAL;
 
 	/* clear ecc status */
 	writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 
 	/* Choose correct seed */
-	rand_seed = random_seed[page % 128];
+	rand_seed = random_seed[page % conf->nseeds];
 
-	writel((rand_seed << 16) | NFC_ECC_RANDOM_EN | NFC_ECC_EN
-		| NFC_ECC_PIPELINE | (ecc_mode << 12),
+	writel((rand_seed << 16) | (conf->ecc_strength << 12) |
+		(conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
+		(conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
+		NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION,
 		SUNXI_NFC_BASE + NFC_ECC_CTL);
 
-	val = readl(SUNXI_NFC_BASE + NFC_CTL);
-	writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
-
-	writel(page_size + (column / ecc_page_size) * ecc_off,
-	       SUNXI_NFC_BASE + NFC_SPARE_AREA);
-
-	flush_dcache_range(dst, ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
+	flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
 
 	/* SUNXI_DMA */
 	writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
@@ -227,38 +255,27 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 	       SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
 	/* read to RAM */
 	writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
-	writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
-			| SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
-			SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
-	writel(ecc_page_size,
-	       SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
-	writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
-		| SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
-		| SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM
-		| SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32
-		| SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO
-		| SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
-		SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
-
-	writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET)
-		| (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET)
-		| (NFC_CMD_READSTART | NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE
-			+ NFC_RCMD_SET);
-	writel(1, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
-	writel(((page & 0xFFFF) << 16) | column,
-	       SUNXI_NFC_BASE + NFC_ADDR_LOW);
-	writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
+	writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC |
+	       SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
+	       SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
+	writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0);
+	writel(SUNXI_DMA_DDMA_CFG_REG_LOADING |
+	       SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 |
+	       SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM |
+	       SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 |
+	       SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO |
+	       SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
+	       SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
+
+	writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
 	writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
-	writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
-		NFC_PAGE_CMD | NFC_WAIT_FLAG |
-		((addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) |
-		NFC_SEND_ADR | NFC_DATA_SWAP_METHOD,
-		SUNXI_NFC_BASE + NFC_CMD);
+	writel(NFC_DATA_TRANS |	NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD,
+	       SUNXI_NFC_BASE + NFC_CMD);
 
 	if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
 			 DEFAULT_TIMEOUT_US)) {
 		printf("Error while initializing dma interrupt\n");
-		return -1;
+		return -EIO;
 	}
 	writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 
@@ -266,29 +283,55 @@ static int nand_read_page(int page_size, int ecc_strength, int ecc_page_size,
 				 SUNXI_DMA_DDMA_CFG_REG_LOADING,
 				 DEFAULT_TIMEOUT_US)) {
 		printf("Error while waiting for dma transfer to finish\n");
-		return -1;
+		return -EIO;
 	}
 
 	invalidate_dcache_range(dst,
-			        ALIGN(dst + ecc_page_size, ARCH_DMA_MINALIGN));
+				ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
 
-	if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
-		return -1;
+	val = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
 
-	return 0;
+	/* ECC error detected. */
+	if (val & 0xffff)
+		return -EIO;
+
+	/*
+	 * Return 1 if the page is empty.
+	 * We consider the page as empty if the first ECC block is marked
+	 * empty.
+	 */
+	return (val & 0x10000) ? 1 : 0;
 }
 
 static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
 	int addr_cycles, uint32_t offs, uint32_t size, void *dest)
 {
 	void *end = dest + size;
+	static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
+	struct nfc_config conf = {
+		.page_size = page_size,
+		.ecc_size = ecc_page_size,
+		.addr_cycles = addr_cycles,
+		.nseeds = ARRAY_SIZE(random_seed),
+		.randomize = true,
+	};
+	int i;
 
-	clrsetbits_le32(SUNXI_NFC_BASE + NFC_CTL, NFC_CTL_PAGE_SIZE_MASK,
-			NFC_CTL_PAGE_SIZE(page_size));
+	for (i = 0; i < ARRAY_SIZE(strengths); i++) {
+		if (ecc_strength == strengths[i]) {
+			conf.ecc_strength = i;
+			break;
+		}
+	}
+
+
+	nand_apply_config(&conf);
+
+	for ( ;dest < end; dest += ecc_page_size, offs += page_size) {
+		if (nand_load_page(&conf, offs))
+			return -1;
 
-	for ( ;dest < end; dest += ecc_page_size, offs += ecc_page_size) {
-		if (nand_read_page(page_size, ecc_strength, ecc_page_size,
-				   addr_cycles, offs, (dma_addr_t)dest))
+		if (nand_read_page(&conf, offs, dest, page_size))
 			return -1;
 	}
 
-- 
cgit v0.10.2


From 7748b4148207d6e0dca8c0b5b95975e8e64179db Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Mon, 6 Jun 2016 10:17:02 +0200
Subject: spl: nand: sunxi: add support for NAND config auto-detection

NAND chips are supposed to expose their capabilities through advanced
mechanisms like READID, ONFI or JEDEC parameter tables. While those
methods are appropriate for the bootloader itself, it's way to
complicated and takes too much space to fit in the SPL.

Replace those mechanisms by a dumb 'trial and error' mechanism.

With this new approach we can get rid of the fixed config list that was
used in the sunxi NAND SPL driver.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
index b43f2af..1ef7366 100644
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -103,6 +103,7 @@ struct nfc_config {
 	int addr_cycles;
 	int nseeds;
 	bool randomize;
+	bool valid;
 };
 
 /* minimal "boot0" style NAND support for Allwinner A20 */
@@ -219,6 +220,26 @@ static int nand_load_page(const struct nfc_config *conf, u32 offs)
 	return 0;
 }
 
+static int nand_reset_column(void)
+{
+	writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
+	       (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
+	       (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
+	       SUNXI_NFC_BASE + NFC_RCMD_SET);
+	writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW);
+	writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
+	       (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR | NFC_CMD_RNDOUT,
+	       SUNXI_NFC_BASE + NFC_CMD);
+
+	if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
+			 DEFAULT_TIMEOUT_US)) {
+		printf("Error while initializing dma interrupt\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 static int nand_read_page(const struct nfc_config *conf, u32 offs,
 			  void *dest, int len)
 {
@@ -303,88 +324,213 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs,
 	return (val & 0x10000) ? 1 : 0;
 }
 
-static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
-	int addr_cycles, uint32_t offs, uint32_t size, void *dest)
+static int nand_max_ecc_strength(struct nfc_config *conf)
 {
-	void *end = dest + size;
-	static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
-	struct nfc_config conf = {
-		.page_size = page_size,
-		.ecc_size = ecc_page_size,
-		.addr_cycles = addr_cycles,
-		.nseeds = ARRAY_SIZE(random_seed),
-		.randomize = true,
-	};
+	static const int ecc_bytes[] = { 32, 46, 54, 60, 74, 88, 102, 110, 116 };
+	int max_oobsize, max_ecc_bytes;
+	int nsectors = conf->page_size / conf->ecc_size;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(strengths); i++) {
-		if (ecc_strength == strengths[i]) {
-			conf.ecc_strength = i;
+	/*
+	 * ECC strength is limited by the size of the OOB area which is
+	 * correlated with the page size.
+	 */
+	switch (conf->page_size) {
+	case 2048:
+		max_oobsize = 64;
+		break;
+	case 4096:
+		max_oobsize = 256;
+		break;
+	case 8192:
+		max_oobsize = 640;
+		break;
+	case 16384:
+		max_oobsize = 1664;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	max_ecc_bytes = max_oobsize / nsectors;
+
+	for (i = 0; i < ARRAY_SIZE(ecc_bytes); i++) {
+		if (ecc_bytes[i] > max_ecc_bytes)
 			break;
-		}
 	}
 
+	if (!i)
+		return -EINVAL;
 
-	nand_apply_config(&conf);
+	return i - 1;
+}
 
-	for ( ;dest < end; dest += ecc_page_size, offs += page_size) {
-		if (nand_load_page(&conf, offs))
-			return -1;
+static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs,
+				  void *dest)
+{
+	/* NAND with pages > 4k will likely require 1k sector size. */
+	int min_ecc_size = conf->page_size > 4096 ? 1024 : 512;
+	int page = offs / conf->page_size;
+	int ret;
 
-		if (nand_read_page(&conf, offs, dest, page_size))
-			return -1;
+	/*
+	 * In most cases, 1k sectors are preferred over 512b ones, start
+	 * testing this config first.
+	 */
+	for (conf->ecc_size = 1024; conf->ecc_size >= min_ecc_size;
+	     conf->ecc_size >>= 1) {
+		int max_ecc_strength = nand_max_ecc_strength(conf);
+
+		nand_apply_config(conf);
+
+		/*
+		 * We are starting from the maximum ECC strength because
+		 * most of the time NAND vendors provide an OOB area that
+		 * barely meets the ECC requirements.
+		 */
+		for (conf->ecc_strength = max_ecc_strength;
+		     conf->ecc_strength >= 0;
+		     conf->ecc_strength--) {
+			conf->randomize = false;
+			if (nand_reset_column())
+				return -EIO;
+
+			/*
+			 * Only read the first sector to speedup detection.
+			 */
+			ret = nand_read_page(conf, offs, dest, conf->ecc_size);
+			if (!ret) {
+				return 0;
+			} else if (ret > 0) {
+				/*
+				 * If page is empty we can't deduce anything
+				 * about the ECC config => stop the detection.
+				 */
+				return -EINVAL;
+			}
+
+			conf->randomize = true;
+			conf->nseeds = ARRAY_SIZE(random_seed);
+			do {
+				if (nand_reset_column())
+					return -EIO;
+
+				if (!nand_read_page(conf, offs, dest,
+						    conf->ecc_size))
+					return 0;
+
+				/*
+				 * Find the next ->nseeds value that would
+				 * change the randomizer seed for the page
+				 * we're trying to read.
+				 */
+				while (conf->nseeds >= 16) {
+					int seed = page % conf->nseeds;
+
+					conf->nseeds >>= 1;
+					if (seed != page % conf->nseeds)
+						break;
+				}
+			} while (conf->nseeds >= 16);
+		}
 	}
 
-	return 0;
+	return -EINVAL;
 }
 
-static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest)
+static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest)
 {
-	const struct {
-		int page_size;
-		int ecc_strength;
-		int ecc_page_size;
-		int addr_cycles;
-	} nand_configs[] = {
-		{  8192, 40, 1024, 5 },
-		{ 16384, 56, 1024, 5 },
-		{  8192, 24, 1024, 5 },
-		{  4096, 24, 1024, 5 },
-	};
-	static int nand_config = -1;
-	int i;
+	if (conf->valid)
+		return 0;
 
-	if (nand_config == -1) {
-		for (i = 0; i < ARRAY_SIZE(nand_configs); i++) {
-			debug("nand: trying page %d ecc %d / %d addr %d: ",
-			      nand_configs[i].page_size,
-			      nand_configs[i].ecc_strength,
-			      nand_configs[i].ecc_page_size,
-			      nand_configs[i].addr_cycles);
-			if (nand_read_ecc(nand_configs[i].page_size,
-					  nand_configs[i].ecc_strength,
-					  nand_configs[i].ecc_page_size,
-					  nand_configs[i].addr_cycles,
-					  offs, size, dest) == 0) {
-				debug("success\n");
-				nand_config = i;
+	/*
+	 * Modern NANDs are more likely than legacy ones, so we start testing
+	 * with 5 address cycles.
+	 */
+	for (conf->addr_cycles = 5;
+	     conf->addr_cycles >= 4;
+	     conf->addr_cycles--) {
+		int max_page_size = conf->addr_cycles == 4 ? 2048 : 16384;
+
+		/*
+		 * Ignoring 1k pages cause I'm not even sure this case exist
+		 * in the real world.
+		 */
+		for (conf->page_size = 2048; conf->page_size <= max_page_size;
+		     conf->page_size <<= 1) {
+			if (nand_load_page(conf, offs))
+				return -1;
+
+			if (!nand_detect_ecc_config(conf, offs, dest)) {
+				conf->valid = true;
 				return 0;
 			}
-			debug("failed\n");
 		}
-		return -1;
 	}
 
-	return nand_read_ecc(nand_configs[nand_config].page_size,
-			     nand_configs[nand_config].ecc_strength,
-			     nand_configs[nand_config].ecc_page_size,
-			     nand_configs[nand_config].addr_cycles,
-			     offs, size, dest);
+	return -EINVAL;
+}
+
+static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
+			    unsigned int size, void *dest)
+{
+	int first_seed, page, ret;
+
+	size = ALIGN(size, conf->page_size);
+	page = offs / conf->page_size;
+	first_seed = page % conf->nseeds;
+
+	for (; size; size -= conf->page_size) {
+		if (nand_load_page(conf, offs))
+			return -1;
+
+		ret = nand_read_page(conf, offs, dest, conf->page_size);
+		/*
+		 * The ->nseeds value should be equal to the number of pages
+		 * in an eraseblock. Since we don't know this information in
+		 * advance we might have picked a wrong value.
+		 */
+		if (ret < 0 && conf->randomize) {
+			int cur_seed = page % conf->nseeds;
+
+			/*
+			 * We already tried all the seed values => we are
+			 * facing a real corruption.
+			 */
+			if (cur_seed < first_seed)
+				return -EIO;
+
+			/* Try to adjust ->nseeds and read the page again... */
+			conf->nseeds = cur_seed;
+
+			if (nand_reset_column())
+				return -EIO;
+
+			/* ... it still fails => it's a real corruption. */
+			if (nand_read_page(conf, offs, dest, conf->page_size))
+				return -EIO;
+		} else if (ret && conf->randomize) {
+			memset(dest, 0xff, conf->page_size);
+		}
+
+		page++;
+		offs += conf->page_size;
+		dest += conf->page_size;
+	}
+
+	return 0;
 }
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 {
-	return nand_read_buffer(offs, size, dest);
+	static struct nfc_config conf = { };
+	int ret;
+
+	ret = nand_detect_config(&conf, offs, dest);
+	if (ret)
+		return ret;
+
+	return nand_read_buffer(&conf, offs, size, dest);
 }
 
 void nand_deselect(void)
-- 
cgit v0.10.2


From 61717571f2b55747e394f217b2fd519213433f88 Mon Sep 17 00:00:00 2001
From: Sergey Kubushyn <ksi@koi8.net>
Date: Tue, 7 Jun 2016 14:22:59 -0700
Subject: common: fb_nand: won't compile

Somehow this got overlooked when getting rid of nand_info.

Small patch, won't affect anything else, no reason to wait for the
next cycle.

Signed-off-by: Sergey Kubushyn <ksi@koi8.net>

diff --git a/common/fb_nand.c b/common/fb_nand.c
index e55ea38..ae34f48 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -34,7 +34,7 @@ __weak int board_fastboot_write_partition_setup(char *name)
 }
 
 static int fb_nand_lookup(const char *partname, char *response,
-			  struct mtd_info **nand,
+			  struct mtd_info **mtd,
 			  struct part_info **part)
 {
 	struct mtd_device *dev;
-- 
cgit v0.10.2


From e1c29086d58f619423f0648748d0678af28f9871 Mon Sep 17 00:00:00 2001
From: Max Krummenacher <max.oss.09@gmail.com>
Date: Mon, 13 Jun 2016 10:15:47 +0200
Subject: nand: nand torture: follow sync with linux v4.6

follow parameter name change (nand to mtd) to fix compiler error.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 5bba66a..e8bcc34 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -820,7 +820,7 @@ int nand_torture(struct mtd_info *mtd, loff_t offset)
 {
 	u_char patterns[] = {0xa5, 0x5a, 0x00};
 	struct erase_info instr = {
-		.mtd = nand,
+		.mtd = mtd,
 		.addr = offset,
 		.len = mtd->erasesize,
 	};
-- 
cgit v0.10.2


From 1866be7d28ce807397e4aedd93f70564ac8bebc0 Mon Sep 17 00:00:00 2001
From: Max Krummenacher <max.oss.09@gmail.com>
Date: Mon, 13 Jun 2016 10:15:48 +0200
Subject: nand: extend nand torture
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

nand torture currently works on exactly one nand block which is specified
by giving the byteoffset to the beginning of the block.

Extend this by allowing for a second parameter specifying the byte size
to be tested.

e.g.
==> nand torture 1000000

NAND torture: device 0 offset 0x1000000 size 0x20000 (block size 0x20000)
 Passed: 1, failed: 0

==> nand torture 1000000 40000

NAND torture: device 0 offset 0x1000000 size 0x40000 (block size 0x20000)
 Passed: 2, failed: 0

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
[scottwood: fix usage to show size as optional, and add misssing braces]
Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/cmd/nand.c b/cmd/nand.c
index 583a18f..ffdeea4 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -647,6 +647,9 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #ifdef CONFIG_CMD_NAND_TORTURE
 	if (strcmp(cmd, "torture") == 0) {
+		loff_t endoff;
+		unsigned int failed = 0, passed = 0;
+
 		if (argc < 3)
 			goto usage;
 
@@ -655,12 +658,37 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 1;
 		}
 
-		printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
-			dev, off, mtd->erasesize);
-		ret = nand_torture(mtd, off);
-		printf(" %s\n", ret ? "Failed" : "Passed");
+		size = mtd->erasesize;
+		if (argc > 3) {
+			if (!str2off(argv[3], &size)) {
+				puts("Size is not a valid number\n");
+				return 1;
+			}
+		}
 
-		return ret == 0 ? 0 : 1;
+		endoff = off + size;
+		if (endoff > mtd->size) {
+			puts("Arguments beyond end of NAND\n");
+			return 1;
+		}
+
+		off = round_down(off, mtd->erasesize);
+		endoff = round_up(endoff, mtd->erasesize);
+		size = endoff - off;
+		printf("\nNAND torture: device %d offset 0x%llx size 0x%llx (block size 0x%x)\n",
+		       dev, off, size, mtd->erasesize);
+		while (off < endoff) {
+			ret = nand_torture(mtd, off);
+			if (ret) {
+				failed++;
+				printf("  block at 0x%llx failed\n", off);
+			} else {
+				passed++;
+			}
+			off += mtd->erasesize;
+		}
+		printf(" Passed: %u, failed: %u\n", passed, failed);
+		return failed != 0;
 	}
 #endif
 
@@ -775,7 +803,8 @@ static char nand_help_text[] =
 	"nand bad - show bad blocks\n"
 	"nand dump[.oob] off - dump page\n"
 #ifdef CONFIG_CMD_NAND_TORTURE
-	"nand torture off - torture block at offset\n"
+	"nand torture off - torture one block at offset\n"
+	"nand torture off [size] - torture blocks from off to off+size\n"
 #endif
 	"nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
 	"    really clean NAND erasing bad blocks (UNSAFE)\n"
diff --git a/doc/README.nand b/doc/README.nand
index 96ffc48..4ecf9de 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -307,7 +307,7 @@ Miscellaneous and testing commands:
   DANGEROUS!!! Factory set bad blocks will be lost. Use only
   to remove artificial bad blocks created with the "markbad" command.
 
-  "torture offset"
+  "torture offset [size]"
   Torture block to determine if it is still reliable.
   Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
   This command returns 0 if the block is still reliable, else 1.
@@ -324,6 +324,10 @@ Miscellaneous and testing commands:
   automate actions following a nand->write() error. This would e.g. be required
   in order to program or update safely firmware to NAND, especially for the UBI
   part of such firmware.
+  Optionally, a second parameter size can be given to test multiple blocks with
+  one call. If size is not a multiple of the NAND's erase size, then the block
+  that contains offset + size will be tested in full. If used with size, this
+  command returns 0 if all tested blocks have been found reliable, else 1.
 
 
 NAND locking command (for chips with active LOCKPRE pin)
-- 
cgit v0.10.2


From caad0d00a8bc3d44ca6581030b95dce97386689c Mon Sep 17 00:00:00 2001
From: Fabian Mewes <architekt@coding4coffee.org>
Date: Tue, 14 Jun 2016 02:46:14 +0200
Subject: nand: doc: fix example ecc scheme calculation

Signed-off-by: Fabian Mewes <architekt@coding4coffee.org>

diff --git a/doc/README.nand b/doc/README.nand
index 4ecf9de..edb45eb 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -271,7 +271,7 @@ Platform specific options
 
 		However, for 4K pagesize NAND
 		NAND_PAGESIZE = 4096
-		NAND_OOBSIZE = 64
+		NAND_OOBSIZE = 224
 		ECC_BYTES = 26
 		2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
 		Thus BCH16 can be supported on 4K page NAND.
-- 
cgit v0.10.2


From 30780f948346436f9974fd6eae89aa2eb841b436 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 20:56:10 +0200
Subject: mtd: nand: Patch remaining places where nand_to_mtd() should be used

Some drivers are still directly accessing the chip->mtd field. Patch
them to use nand_to_mtd() instead.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/doc/README.nand b/doc/README.nand
index edb45eb..f1c20ff 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -137,7 +137,7 @@ Configuration Options:
       init:
 
 	/* chip is struct nand_chip, and is now provided by the driver. */
-	mtd = &chip.mtd;
+	mtd = nand_to_mtd(&chip);
 
 	/*
 	 * Fill in appropriate values if this driver uses these fields,
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index f8770e0..a8a7a66 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -223,7 +223,7 @@ void nand_init(void)
 	/*
 	 * Init board specific nand support
 	 */
-	mtd = &nand_chip.mtd;
+	mtd = nand_to_mtd(&nand_chip);
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 75e8307..a66cfc1 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1448,7 +1448,7 @@ int board_nand_init(struct nand_chip *nand)
 
 void nand_init(void)
 {
-	mtd = &nand_chip.mtd;
+	mtd = nand_to_mtd(&nand_chip);
 	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
 	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
 	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index 4262029..a793115 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -541,7 +541,7 @@ static struct nand_chip lpc32xx_chip;
 
 void board_nand_init(void)
 {
-	struct mtd_info *mtd = &lpc32xx_chip.mtd;
+	struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
 	int ret;
 
 	/* Set all BOARDSPECIFIC (actually core-specific) fields  */
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index a8a3084..ff28df4 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -147,7 +147,7 @@ static int mxs_nand_init(void)
 
 	/* init mxs nand driver */
 	board_nand_init(&nand_chip);
-	mtd = &nand_chip.mtd;
+	mtd = nand_to_mtd(&nand_chip);
 	/* set mtd functions */
 	nand_chip.cmdfunc = mxs_nand_command;
 	nand_chip.numchips = 1;
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index b023e00..60a7607 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -249,7 +249,7 @@ void nand_init(void)
 	/*
 	 * Init board specific nand support
 	 */
-	mtd = &nand_chip.mtd;
+	mtd = nand_to_mtd(&nand_chip);
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
-- 
cgit v0.10.2


From 333463d6698b9e7b8a36c7fd3bd5887c34e5cd71 Mon Sep 17 00:00:00 2001
From: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Date: Sun, 19 Jun 2016 23:05:32 +0200
Subject: dragonboard410c: Increase default environment size.

Due to changes in distro environment, ENV_SIZE limit was reached on Dragonboard.
This patch increases environment size to 8KiB.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>

diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index d32889d..4b00922 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -129,7 +129,7 @@ REFLASH(dragonboard/u-boot.img, 8)\
 	BOOTENV
 
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_SYS_NO_FLASH
 
-- 
cgit v0.10.2


From 1a3619cf825fcef15ebe0fac6d65a9af1bc0588c Mon Sep 17 00:00:00 2001
From: Stefan Wahren <stefan.wahren@i2se.com>
Date: Thu, 16 Jun 2016 17:54:06 +0000
Subject: mmc: add MMC_VERSION_5_1

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 7586558..aabfc71 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1227,6 +1227,9 @@ static int mmc_startup(struct mmc *mmc)
 		case 7:
 			mmc->version = MMC_VERSION_5_0;
 			break;
+		case 8:
+			mmc->version = MMC_VERSION_5_1;
+			break;
 		}
 
 		/* The partition data may be non-zero but it is only
diff --git a/include/mmc.h b/include/mmc.h
index 7fdfc32..f383925 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -49,6 +49,7 @@
 #define MMC_VERSION_4_41	MAKE_MMC_VERSION(4, 4, 1)
 #define MMC_VERSION_4_5		MAKE_MMC_VERSION(4, 5, 0)
 #define MMC_VERSION_5_0		MAKE_MMC_VERSION(5, 0, 0)
+#define MMC_VERSION_5_1		MAKE_MMC_VERSION(5, 1, 0)
 
 #define MMC_MODE_HS		(1 << 0)
 #define MMC_MODE_HS_52MHz	(1 << 1)
-- 
cgit v0.10.2


From 41598c82513672b1052c88ce816d98467345141f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 20 Jun 2016 17:33:39 +0900
Subject: autoboot: add CONFIG_AUTOBOOT to allow to not compile autoboot.c

Since commit bb597c0eeb7e ("common: bootdelay: move CONFIG_BOOTDELAY
into a Kconfig option"), CONFIG_BOOTDELAY is defined for all boards.

Prior to that commit, it was allowed to unset CONFIG_BOOTDELAY to
not compile common/autoboot.c, as described in common/Makefile:

  # This option is not just y/n - it can have a numeric value
  ifdef CONFIG_BOOTDELAY
  obj-y += autoboot.o
  endif

It was a bit odd to enable/disable code with an integer type option,
but it was how this option worked before that commit, and several
boards actually unset it to opt out of the autoboot feature.

This commit adds a new bool option, CONFIG_AUTOBOOT, and makes
CONFIG_BOOTDELAY depend on it.

I chose "default y" for this option because most boards use the
autoboot.  I added "# CONFIG_AUTOBOOT is not set" for the boards that
had not set CONFIG_BOOTDELAY prior to the bad commit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/cmd/Kconfig b/cmd/Kconfig
index d51645c..42e0e39 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -38,6 +38,12 @@ config SYS_PROMPT
 
 menu "Autoboot options"
 
+config AUTOBOOT
+	bool "Autoboot"
+	default y
+	help
+	  This enables the autoboot.  See doc/README.autoboot for detail.
+
 config AUTOBOOT_KEYED
 	bool "Stop autobooting via specific input key / string"
 	default n
diff --git a/common/Kconfig b/common/Kconfig
index e691145..ada4ddb 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -100,6 +100,7 @@ endmenu
 config BOOTDELAY
 	int "delay in seconds before automatically booting"
 	default 2
+	depends on AUTOBOOT
 	help
 	  Delay before automatically running bootcmd;
 	  set to -1 to disable autoboot.
diff --git a/common/Makefile b/common/Makefile
index 97c59fe..34cb898 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -15,10 +15,7 @@ ifdef CONFIG_SYS_HUSH_PARSER
 obj-y += cli_hush.o
 endif
 
-# This option is not just y/n - it can have a numeric value
-ifdef CONFIG_BOOTDELAY
-obj-y += autoboot.o
-endif
+obj-$(CONFIG_AUTOBOOT) += autoboot.o
 
 # This option is not just y/n - it can have a numeric value
 ifdef CONFIG_BOOT_RETRY_TIME
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index 4f85c22..15952af 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index c145caf..b19c956 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index f06379f..1588c52 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5249EVB=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+# CONFIG_AUTOBOOT is not set
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index c227ef4..01c1eeb 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
index 2716868..d2a3b73 100644
--- a/configs/bcm11130_defconfig
+++ b/configs/bcm11130_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
index 8e01c52..5fc501f 100644
--- a/configs/bcm11130_nand_defconfig
+++ b/configs/bcm11130_nand_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index 4c0f3b3..70eb44a 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index e9d13b9..b849074 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -3,6 +3,7 @@ CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
index d8a30d1..a9403a8 100644
--- a/configs/bcm911360_entphn-ns_defconfig
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
index 205db1e..aee2e2e 100644
--- a/configs/bcm911360_entphn_defconfig
+++ b/configs/bcm911360_entphn_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
index bcb24b4..df76dac 100644
--- a/configs/bcm911360k_defconfig
+++ b/configs/bcm911360k_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
index 527f4a5..0b00ce3 100644
--- a/configs/bcm958300k-ns_defconfig
+++ b/configs/bcm958300k-ns_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index bcb24b4..df76dac 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
index bcb24b4..df76dac 100644
--- a/configs/bcm958305k_defconfig
+++ b/configs/bcm958305k_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMCYGNUS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index 6d06b4e..99e5452 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BCMNSP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
 CONFIG_HUSH_PARSER=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/bf506f-ezkit_defconfig b/configs/bf506f-ezkit_defconfig
index 0decb53..c36fc5f 100644
--- a/configs/bf506f-ezkit_defconfig
+++ b/configs/bf506f-ezkit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF506F_EZKIT=y
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/dnp5370_defconfig b/configs/dnp5370_defconfig
index b6d3b74..782cc88 100644
--- a/configs/dnp5370_defconfig
+++ b/configs/dnp5370_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_DNP5370=y
+# CONFIG_AUTOBOOT is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
index 8d0bace..c50da0c 100644
--- a/configs/espresso7420_defconfig
+++ b/configs/espresso7420_defconfig
@@ -4,5 +4,6 @@ CONFIG_ARCH_EXYNOS7=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
 CONFIG_SYS_PROMPT="ESPRESSO7420 # "
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index 590f9b5..fcce6c7 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -4,6 +4,7 @@ CONFIG_CPU_MIPS64_R2=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="malta # "
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index ff93931..002633b 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -5,6 +5,7 @@ CONFIG_CPU_MIPS64_R2=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="maltael # "
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index 3a87586..e74f23d 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_MALTA=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="malta # "
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 11ff259..3c4c1fe 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="maltael # "
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/configs/mpr2_defconfig b/configs/mpr2_defconfig
index a8dbfc5..606b942 100644
--- a/configs/mpr2_defconfig
+++ b/configs/mpr2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MPR2=y
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig
index 2ef3105..537ea7c 100644
--- a/configs/ms7720se_defconfig
+++ b/configs/ms7720se_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MS7720SE=y
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig
index a476ba7..14923c0 100644
--- a/configs/openrisc-generic_defconfig
+++ b/configs/openrisc-generic_defconfig
@@ -7,3 +7,4 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_SYS_NS16550=y
+# CONFIG_AUTOBOOT is not set
diff --git a/configs/rsk7203_defconfig b/configs/rsk7203_defconfig
index b63ad4e..f2e9deb 100644
--- a/configs/rsk7203_defconfig
+++ b/configs/rsk7203_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_RSK7203=y
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index c35287d..b381e21 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_S5P_GONI=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Goni # "
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/shmin_defconfig b/configs/shmin_defconfig
index 1749f13..65b4525 100644
--- a/configs/shmin_defconfig
+++ b/configs/shmin_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_SHMIN=y
+# CONFIG_AUTOBOOT is not set
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/include/autoboot.h b/include/autoboot.h
index 3a9059a..c175f91c 100644
--- a/include/autoboot.h
+++ b/include/autoboot.h
@@ -12,7 +12,7 @@
 #ifndef __AUTOBOOT_H
 #define __AUTOBOOT_H
 
-#ifdef CONFIG_BOOTDELAY
+#ifdef CONFIG_AUTOBOOT
 /**
  * bootdelay_process() - process the bootd delay
  *
-- 
cgit v0.10.2


From 46fd625dfee9ef69cd183f0cd11e09309a71a4e2 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 20 Jun 2016 11:14:12 -0400
Subject: Prepare v2016.07-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 0f7d6f3..d0e7a8a 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From da70b4d14116d2b3d63840cd2ea01d0badf39e41 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 10 Jun 2016 21:03:34 +0200
Subject: tinyprintf: Add vprintf implementation

vprintf is used by panic() which is used in various SPL paths on some
boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 3c65fc9..451f4f7 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -130,6 +130,11 @@ abort:
 	return 0;
 }
 
+int vprintf(const char *fmt, va_list va)
+{
+	return _vprintf(fmt, va, putc);
+}
+
 int printf(const char *fmt, ...)
 {
 	va_list va;
-- 
cgit v0.10.2


From 8c7d22965dc7bf3abcd3bdcc28164c378525f445 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 10 Jun 2016 12:19:40 +0200
Subject: sunxi: Select USE_TINY_PRINTF

This gives us a bit more breathing room wrt our SPL size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8a9cfcc..f48be96 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -637,6 +637,7 @@ config ARCH_SUNXI
 	select USB
 	select USB_STORAGE
 	select USB_KEYBOARD
+	select USE_TINY_PRINTF
 
 config TARGET_TS4800
 	bool "Support TS4800"
-- 
cgit v0.10.2


From cd38e3d1b485bbc5e5481318c70445a60c609d19 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 11 Jun 2016 15:19:38 +0200
Subject: sunxi: Add defconfig and dts file for Polaroid MID2407PXE03 tablet

The Polaroid MID2407PXE03 is an a23 based 7" tablet based on a M86_MB V2.0
PCB, featuring a 800x480 LCD, 512MB RAM, 4G NAND, esp8089 wifi, gsl1680
touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg
connector which doubles as charging port.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0a41eb2..5172a7e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -223,6 +223,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
 dtb-$(CONFIG_MACH_SUN8I_A23) += \
 	sun8i-a23-evb.dtb \
 	sun8i-a23-gt90h-v4.dtb \
+	sun8i-a23-polaroid-mid2407pxe03.dtb \
 	sun8i-a23-polaroid-mid2809pxe04.dtb \
 	sun8i-a23-q8-tablet.dtb
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi
index 0cfec50..458b668 100644
--- a/arch/arm/dts/axp22x.dtsi
+++ b/arch/arm/dts/axp22x.dtsi
@@ -141,5 +141,15 @@
 			regulator-max-microvolt = <3000000>;
 			regulator-name = "rtc_ldo";
 		};
+
+		reg_drivevbus: drivevbus {
+			regulator-name = "drivevbus";
+			status = "disabled";
+		};
+	};
+
+	usb_power_supply: usb_power_supply {
+		compatible = "x-powers,axp221-usb-power-supply";
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts
new file mode 100644
index 0000000..bb2f073
--- /dev/null
+++ b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Polaroid MID2407PXE03 tablet";
+	compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23";
+
+	aliases {
+		serial0 = &r_uart;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bl_en_pin_mid2407>;
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+		enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+	/*
+	 * The gsl1680 is rated at 400KHz and it will not work reliable at
+	 * 100KHz, this has been confirmed on multiple different tablets.
+	 * The gsl1680 is the only device on this bus.
+	 */
+	clock-frequency = <400000>;
+
+	gsl1680: touchscreen@40 {
+		compatible = "silead,gsl1680";
+		reg = <0x40>;
+		interrupt-parent = <&pio>;
+		interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
+		pinctrl-names = "default";
+		pinctrl-0 = <&ts_power_pin_mid2407>;
+		power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+		touchscreen-size-x = <960>;
+		touchscreen-size-y = <640>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		touchscreen-max-fingers = <5>;
+		touchscreen-fw-name = "silead/gsl1680-polaroid-mid2407pxe03.fw";
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+};
+
+&lradc {
+	vref-supply = <&reg_vcc3v0>;
+	status = "okay";
+
+	button@200 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <200000>;
+	};
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <400000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mid2407>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&pio {
+	bl_en_pin_mid2407: bl_en_pin@0 {
+		allwinner,pins = "PH6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	mmc0_cd_pin_mid2407: mmc0_cd_pin@0 {
+		allwinner,pins = "PB4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	ts_power_pin_mid2407: ts_power_pin@0 {
+		allwinner,pins = "PH1";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH8";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins>;
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+		x-powers,drive-vbus-en;
+	};
+};
+
+&r_uart {
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_uart_pins_a>;
+	status = "okay";
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_drivevbus {
+	regulator-name = "usb0-vbus";
+	status = "okay";
+};
+
+&reg_ldo_io1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-touchscreen";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_lcd {
+	vcc-lcd-supply = <&reg_dc1sw>;
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb0_vbus-supply = <&reg_drivevbus>;
+	status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2cb8a75..4f8d950 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -58,6 +58,7 @@ F:	configs/orangepi_2_defconfig
 F:	configs/orangepi_one_defconfig
 F:	configs/orangepi_pc_defconfig
 F:	configs/orangepi_plus_defconfig
+F:	configs/polaroid_mid2407pxe03_defconfig
 F:	configs/polaroid_mid2809pxe04_defconfig
 F:	configs/q8_a23_tablet_800x480_defconfig
 F:	configs/q8_a33_tablet_800x480_defconfig
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
new file mode 100644
index 0000000..9bf6fbf
--- /dev/null
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A23=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=63351
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_MUSB_HOST=y
-- 
cgit v0.10.2


From 3551b24f5354fc47bb4ddf99d2f095ccc6b03f2d Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 12 Jun 2016 19:44:42 +0200
Subject: sunxi: Add defconfig and dts file for inet86dz board

The inet86dz board is a board used in 7" tablets from various oems.

These tablets are a23 based 7" tablets featuring a 1024x600 LCD,
512MB RAM, 4G NAND, rtl8188etv usb wifi, gsl1680 touchschreen,
micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector
which doubles as charging port.

The dts file this commit adds is identical to the one submitted to
the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5172a7e..de75e24 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -223,6 +223,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
 dtb-$(CONFIG_MACH_SUN8I_A23) += \
 	sun8i-a23-evb.dtb \
 	sun8i-a23-gt90h-v4.dtb \
+	sun8i-a23-inet86dz.dtb \
 	sun8i-a23-polaroid-mid2407pxe03.dtb \
 	sun8i-a23-polaroid-mid2809pxe04.dtb \
 	sun8i-a23-q8-tablet.dtb
diff --git a/arch/arm/dts/sun8i-a23-inet86dz.dts b/arch/arm/dts/sun8i-a23-inet86dz.dts
new file mode 100644
index 0000000..0405258
--- /dev/null
+++ b/arch/arm/dts/sun8i-a23-inet86dz.dts
@@ -0,0 +1,293 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "INet-86DZ Rev 01";
+	compatible = "primux,inet86dz", "allwinner,sun8i-a23";
+
+	aliases {
+		serial0 = &r_uart;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bl_en_pin_inet86dz>;
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+		enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+	/*
+	 * The gsl1680 is rated at 400KHz and it will not work reliable at
+	 * 100KHz, this has been confirmed on multiple different tablets.
+	 * The gsl1680 is the only device on this bus.
+	 */
+	clock-frequency = <400000>;
+
+	gsl1680: touchscreen@40 {
+		compatible = "silead,gsl1680";
+		reg = <0x40>;
+		interrupt-parent = <&pio>;
+		interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
+		pinctrl-names = "default";
+		pinctrl-0 = <&ts_power_pin_inet86dz>;
+		power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+		touchscreen-size-x = <960>;
+		touchscreen-size-y = <640>;
+		touchscreen-max-fingers = <5>;
+		touchscreen-fw-name = "silead/gsl1680-inet86dz.fw";
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+};
+
+&lradc {
+	vref-supply = <&reg_vcc3v0>;
+	status = "okay";
+
+	button@200 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <200000>;
+	};
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <400000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet86dz>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&pio {
+	bl_en_pin_inet86dz: bl_en_pin@0 {
+		allwinner,pins = "PH6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	mmc0_cd_pin_inet86dz: mmc0_cd_pin@0 {
+		allwinner,pins = "PB4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	ts_power_pin_inet86dz: ts_power_pin@0 {
+		allwinner,pins = "PH1";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH8";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins>;
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+		x-powers,drive-vbus-en;
+	};
+};
+
+&r_uart {
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_uart_pins_a>;
+	status = "okay";
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_drivevbus {
+	regulator-name = "usb0-vbus";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_lcd {
+	vcc-lcd-supply = <&reg_dc1sw>;
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb1_vbus-supply = <&reg_dldo1>;
+	status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 4f8d950..de5207e 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -54,6 +54,7 @@ F:	configs/Wits_Pro_A20_DKT_defconfig
 F:	include/configs/sun8i.h
 F:	configs/ga10h_v1_1_defconfig
 F:	configs/gt90h_v4_defconfig
+F:	configs/inet86dz_defconfig
 F:	configs/orangepi_2_defconfig
 F:	configs/orangepi_one_defconfig
 F:	configs/orangepi_pc_defconfig
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
new file mode 100644
index 0000000..55768ba
--- /dev/null
+++ b/configs/inet86dz_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A23=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=63351
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_MUSB_HOST=y
-- 
cgit v0.10.2


From 3da9536e8f377d8ec63df930bfd27c700475b68e Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 12 Jun 2016 11:57:07 +0200
Subject: sunxi: Revert "sunxi: make SoC variant choice mandatory"

This reverts commit 1a5f0de08e86("sunxi: make SoC variant choice
mandatory").

With the optional marking in the Kconfig "make savedefconfig"
will drop CONFIG_MACH_SUN4I=y from all the A10 boards, making it
hard to see at a glance which family of sunxi chips the defconfig
is for.

This commit therefore restores the optional, and restores
CONFIG_MACH_SUN4I=y to all defconfig's which had it dropped
because of this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c1ae6f5..323e972 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -18,6 +18,7 @@ config SUNXI_GEN_SUN6I
 
 choice
 	prompt "Sunxi SoC Variant"
+	optional
 
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
-- 
cgit v0.10.2


From dae08d228122e4ad296077106520a4db3ca17872 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:24 +0800
Subject: ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()

For psci_get_cpu_stack_top() to be usable in C code, it must adhere to
the ARM calling conventions. Since it could be called when the stack
is still unavailable, and the entry code to linux also expects r1 and
r2 to remain unchanged, stick to r0 and r3.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b..cdd001f 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,15 +196,15 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-	mov	r5, #0x400			@ 1kB of stack per CPU
-	mul	r0, r0, r5
-
-	ldr	r5, =psci_text_end		@ end of monitor text
-	add	r5, r5, #0x2000			@ Skip two pages
-	lsr	r5, r5, #12			@ Align to start of page
-	lsl	r5, r5, #12
-	sub	r5, r5, #4			@ reserve 1 word for target PC
-	sub	r0, r5, r0			@ here's our stack!
+	mov	r3, #0x400			@ 1kB of stack per CPU
+	mul	r0, r0, r3
+
+	ldr	r3, =psci_text_end		@ end of monitor text
+	add	r3, r3, #0x2000			@ Skip two pages
+	lsr	r3, r3, #12			@ Align to start of page
+	lsl	r3, r3, #12
+	sub	r3, r3, #4			@ reserve 1 word for target PC
+	sub	r0, r3, r0			@ here's our stack!
 
 	bx	lr
 ENDPROC(psci_get_cpu_stack_top)
-- 
cgit v0.10.2


From 778dc5f43e92d8736a81e15fb0bbb6cb5a78c1ab Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:25 +0800
Subject: ARM: PSCI: save and restore clobbered registers in
 v7_flush_dcache_all

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index cdd001f..ab40837 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -110,6 +110,7 @@ ENDPROC(psci_get_cpu_id)
 
 /* Imported from Linux kernel */
 LENTRY(v7_flush_dcache_all)
+	stmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	dmb					@ ensure ordering with previous memory accesses
 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
 	ands	r3, r0, #0x7000000		@ extract loc from clidr
@@ -153,6 +154,7 @@ finished:
 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
 	dsb	st
 	isb
+	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	bx	lr
 ENDPROC(v7_flush_dcache_all)
 
-- 
cgit v0.10.2


From cbeeb2aebfebcacfe11a88104c6ee923baa50144 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:26 +0800
Subject: ARM: PSCI: export common PSCI function declarations for C code

Some common PSCI functions are written in assembly, but it should be
possible to use them from C code.

Add function declarations for C code to consume.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 3704f07..bc5edda 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -48,6 +48,13 @@
 #define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
 
 #ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+void psci_cpu_entry(void);
+u32 psci_get_cpu_id(void);
+u32 psci_get_cpu_stack_top(int cpu);
+void psci_cpu_off_common(void);
+
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
 #endif /* ! __ASSEMBLY__ */
-- 
cgit v0.10.2


From b56e06d343ba4f9af3063d023032fdc00ba17944 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:27 +0800
Subject: ARM: allocate extra space for PSCI stack in secure section during
 link phase

The PSCI implementation expects at most 2 pages worth of space reserved
at the end of the secure section for its stacks. If PSCI is relocated to
secure SRAM, then everything is fine. If no secure SRAM is available,
and PSCI remains in main memory, the reserved memory space doesn't cover
the space used by the stack.

If one accesses PSCI after Linux has fully booted, the memory that should
have been reserved for the PSCI stacks may have been used by the kernel
or userspace, and would be corrupted. Observed after effects include the
system hanging or telinit core dumping when trying to reboot. It seems
the init process gets hit the most on my test bed.

This fix allocates the space used by the PSCI stacks in the secure
section by skipping pages in the linker script, but only when there is
no secure SRAM, to avoid bloating the binary.

This fix is only a stop gap. It would be better to rework the stack
allocation mechanism, maybe with proper usage of CONFIG_ macros and an
explicit symbol.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index cfab8b0..1769b6e 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -50,6 +50,7 @@ SECTIONS
 
 #ifndef CONFIG_ARMV7_SECURE_BASE
 #define CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_PSCI_STACK_IN_RAM
 #endif
 
 	.__secure_start : {
@@ -67,6 +68,12 @@ SECTIONS
 		SIZEOF(.__secure_start) +
 		SIZEOF(.secure_text);
 
+#ifdef __ARMV7_PSCI_STACK_IN_RAM
+	/* Align to page boundary and skip 2 pages */
+	. = (. & ~ 0xfff) + 0x2000;
+#undef __ARMV7_PSCI_STACK_IN_RAM
+#endif
+
 	__secure_end_lma = .;
 	.__secure_end : AT(__secure_end_lma) {
 		*(.__secure_end)
-- 
cgit v0.10.2


From 0f3b8944269034bab18760053346ae1cdcf82d51 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:28 +0800
Subject: sunxi: Make CPUCFG_BASE macro names the same across families

Use SUNXI_CPUCFG_BASE across all families. This makes writing common
PSCI code easier.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd..9752550 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
 	lsr	r9, r9, #10
 	and	r9, r9, #0xf
 
-	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Wait for the core to enter WFI
 	lsl	r11, r9, #6		@ x64
@@ -114,8 +114,8 @@ psci_fiq_enter:
 	str	r10, [r12, #0x140]
 #endif
 
-	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Unlock CPU
 	ldr	r10, [r8, #0x1e4]
@@ -139,8 +139,8 @@ psci_cpu_on:
 	str	r2, [r0]		@ store target PC at stack top
 	dsb
 
-	movw	r0, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ CPU mask
 	and	r1, r1, #3	@ only care about first cluster
@@ -189,8 +189,8 @@ psci_cpu_on:
 	str	r6, [r0, #0x100]
 
 	@ re-calculate CPU control register address
-	movw	r0, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Deassert reset on target CPU
 	mov	r6, #3
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587..ac8ebf8 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
 	lsr	r9, r9, #10
 	and	r9, r9, #0xf
 
-	movw	r8, #(SUN7I_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUN7I_CPUCFG_BASE >> 16)
+	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Wait for the core to enter WFI
 	lsl	r11, r9, #6		@ x64
@@ -128,8 +128,8 @@ psci_cpu_on:
 	str	r2, [r0]		@ store target PC at stack top
 	dsb
 
-	movw	r0, #(SUN7I_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUN7I_CPUCFG_BASE >> 16)
+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ CPU mask
 	and	r1, r1, #3	@ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 65c0441..47e327e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,10 @@
 #define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
 #define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
 
+#ifdef CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE		0x01700000
+#endif
+
 #define SUNXI_SRAMC_BASE		0x01c00000
 #define SUNXI_DRAMC_BASE		0x01c01000
 #define SUNXI_DMA_BASE			0x01c02000
@@ -94,7 +98,10 @@
 
 #define SUNXI_TP_BASE			0x01c25000
 #define SUNXI_PMU_BASE			0x01c25400
-#define SUN7I_CPUCFG_BASE              0x01c25c00
+
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_CPUCFG_BASE		0x01c25c00
+#endif
 
 #define SUNXI_UART0_BASE		0x01c28000
 #define SUNXI_UART1_BASE		0x01c28400
@@ -148,7 +155,11 @@
 
 #define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
-#define SUN6I_CPUCFG_BASE		0x01f01c00
+
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE		0x01f01c00
+#endif
+
 #define SUNXI_R_TWI_BASE		0x01f02400
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
-- 
cgit v0.10.2


From d7d4e5ccd646538a735ea97b446a9453ab49cc17 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:29 +0800
Subject: sunxi: Add packed attribute to struct sunxi_prcm_reg

struct sunxi_prcm_reg is a representation of the PRCM registers. Add
the packed attribute to prevent the compiler from doing funny things.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 556c1af..34e01e8 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -197,7 +197,9 @@
 #define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
 
 #ifndef __ASSEMBLY__
-struct sunxi_prcm_reg {
+#include <linux/compiler.h>
+
+struct __packed sunxi_prcm_reg {
 	u32 cpus_cfg;		/* 0x000 */
 	u8 res0[0x8];		/* 0x004 */
 	u32 apb0_ratio;		/* 0x00c */
-- 
cgit v0.10.2


From 57c2a255725a033407835cc596158a153c255bc1 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:30 +0800
Subject: sunxi: Add missing linux/types.h header for cpucfg_sun6i.h

cpucfg_sun6i.h includes a register definition for the CPUCFG register
block. The types used are u32 and u8, which are defined in linux/types.h.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
index e2a29cb..6885a97 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
@@ -9,6 +9,8 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
+#include <linux/types.h>
+
 #ifndef __ASSEMBLY__
 
 struct sunxi_cpucfg_reg {
-- 
cgit v0.10.2


From 20e3d05370b75bc71b74765adc80de35ad2d2ec7 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:31 +0800
Subject: sunxi: Group cpu core related controls together

Instead of listing individual registers for controls to each processor
core, list them as an array of registers. This makes accessing controls
by core index easier.

Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic
"cpucfg.h", and add packed attribute to struct sunxi_cpucfg.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
new file mode 100644
index 0000000..f6d2f21
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -0,0 +1,63 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#ifndef __ASSEMBLY__
+
+struct __packed sunxi_cpucfg_cpu {
+	u32 rst;		/* base + 0x0 */
+	u32 ctrl;		/* base + 0x4 */
+	u32 status;		/* base + 0x8 */
+	u8 res[0x34];		/* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
+	u8 res0[0x40];		/* 0x000 */
+	struct sunxi_cpucfg_cpu cpu[4];		/* 0x040 */
+	u8 res1[0x44];		/* 0x140 */
+	u32 gen_ctrl;		/* 0x184 */
+	u32 l2_status;		/* 0x188 */
+	u8 res2[0x4];		/* 0x18c */
+	u32 event_in;		/* 0x190 */
+	u8 res3[0xc];		/* 0x194 */
+	u32 super_standy_flag;	/* 0x1a0 */
+	u32 priv0;		/* 0x1a4 */
+	u32 priv1;		/* 0x1a8 */
+	u8 res4[0x54];		/* 0x1ac */
+	u32 idle_cnt0_low;	/* 0x200 */
+	u32 idle_cnt0_high;	/* 0x204 */
+	u32 idle_cnt0_ctrl;	/* 0x208 */
+	u8 res8[0x4];		/* 0x20c */
+	u32 idle_cnt1_low;	/* 0x210 */
+	u32 idle_cnt1_high;	/* 0x214 */
+	u32 idle_cnt1_ctrl;	/* 0x218 */
+	u8 res9[0x4];		/* 0x21c */
+	u32 idle_cnt2_low;	/* 0x220 */
+	u32 idle_cnt2_high;	/* 0x224 */
+	u32 idle_cnt2_ctrl;	/* 0x228 */
+	u8 res10[0x4];		/* 0x22c */
+	u32 idle_cnt3_low;	/* 0x230 */
+	u32 idle_cnt3_high;	/* 0x234 */
+	u32 idle_cnt3_ctrl;	/* 0x238 */
+	u8 res11[0x4];		/* 0x23c */
+	u32 idle_cnt4_low;	/* 0x240 */
+	u32 idle_cnt4_high;	/* 0x244 */
+	u32 idle_cnt4_ctrl;	/* 0x248 */
+	u8 res12[0x34];		/* 0x24c */
+	u32 cnt64_ctrl;		/* 0x280 */
+	u32 cnt64_low;		/* 0x284 */
+	u32 cnt64_high;		/* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
deleted file mode 100644
index 6885a97..0000000
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Sunxi A31 CPUCFG register definition.
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SUNXI_CPUCFG_H
-#define _SUNXI_CPUCFG_H
-
-#include <linux/types.h>
-
-#ifndef __ASSEMBLY__
-
-struct sunxi_cpucfg_reg {
-	u8 res0[0x40];		/* 0x000 */
-	u32 cpu0_rst;		/* 0x040 */
-	u32 cpu0_ctrl;		/* 0x044 */
-	u32 cpu0_status;	/* 0x048 */
-	u8 res1[0x34];		/* 0x04c */
-	u32 cpu1_rst;		/* 0x080 */
-	u32 cpu1_ctrl;		/* 0x084 */
-	u32 cpu1_status;	/* 0x088 */
-	u8 res2[0x34];		/* 0x08c */
-	u32 cpu2_rst;		/* 0x0c0 */
-	u32 cpu2_ctrl;		/* 0x0c4 */
-	u32 cpu2_status;	/* 0x0c8 */
-	u8 res3[0x34];		/* 0x0cc */
-	u32 cpu3_rst;		/* 0x100 */
-	u32 cpu3_ctrl;		/* 0x104 */
-	u32 cpu3_status;	/* 0x108 */
-	u8 res4[0x78];		/* 0x10c */
-	u32 gen_ctrl;		/* 0x184 */
-	u32 l2_status;		/* 0x188 */
-	u8 res5[0x4];		/* 0x18c */
-	u32 event_in;		/* 0x190 */
-	u8 res6[0xc];		/* 0x194 */
-	u32 super_standy_flag;	/* 0x1a0 */
-	u32 priv0;		/* 0x1a4 */
-	u32 priv1;		/* 0x1a8 */
-	u8 res7[0x54];		/* 0x1ac */
-	u32 idle_cnt0_low;	/* 0x200 */
-	u32 idle_cnt0_high;	/* 0x204 */
-	u32 idle_cnt0_ctrl;	/* 0x208 */
-	u8 res8[0x4];		/* 0x20c */
-	u32 idle_cnt1_low;	/* 0x210 */
-	u32 idle_cnt1_high;	/* 0x214 */
-	u32 idle_cnt1_ctrl;	/* 0x218 */
-	u8 res9[0x4];		/* 0x21c */
-	u32 idle_cnt2_low;	/* 0x220 */
-	u32 idle_cnt2_high;	/* 0x224 */
-	u32 idle_cnt2_ctrl;	/* 0x228 */
-	u8 res10[0x4];		/* 0x22c */
-	u32 idle_cnt3_low;	/* 0x230 */
-	u32 idle_cnt3_high;	/* 0x234 */
-	u32 idle_cnt3_ctrl;	/* 0x238 */
-	u8 res11[0x4];		/* 0x23c */
-	u32 idle_cnt4_low;	/* 0x240 */
-	u32 idle_cnt4_high;	/* 0x244 */
-	u32 idle_cnt4_ctrl;	/* 0x248 */
-	u8 res12[0x34];		/* 0x24c */
-	u32 cnt64_ctrl;		/* 0x280 */
-	u32 cnt64_low;		/* 0x284 */
-	u32 cnt64_high;		/* 0x288 */
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* _SUNXI_CPUCFG_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 34e01e8..ae3880b 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -227,10 +227,8 @@ struct __packed sunxi_prcm_reg {
 	u32 gpu_pwroff;		/* 0x118 */
 	u8 res9[0x4];		/* 0x11c */
 	u32 vdd_pwr_reset;	/* 0x120 */
-	u8 res10[0x20];		/* 0x124 */
-	u32 cpu1_pwr_clamp;	/* 0x144 */
-	u32 cpu2_pwr_clamp;	/* 0x148 */
-	u32 cpu3_pwr_clamp;	/* 0x14c */
+	u8 res10[0x1c];		/* 0x124 */
+	u32 cpu_pwr_clamp[4];	/* 0x140 but first one is actually unused */
 	u8 res11[0x30];		/* 0x150 */
 	u32 dram_pwr;		/* 0x180 */
 	u8 res12[0xc];		/* 0x184 */
-- 
cgit v0.10.2


From 7579a3ec8c655b57f072c44c92f281fdc5401450 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:32 +0800
Subject: sunxi: Add CPUCFG debug lock and sun7i cpu power controls

CPUCFG has an unlisted debug control register, which is used to disable
external debug access.

Also, sun7i secondary core power controls are in CPUCFG, as there's no
separate PRCM block.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
index f6d2f21..297cdd2 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -33,7 +33,12 @@ struct __packed sunxi_cpucfg_reg {
 	u32 super_standy_flag;	/* 0x1a0 */
 	u32 priv0;		/* 0x1a4 */
 	u32 priv1;		/* 0x1a8 */
-	u8 res4[0x54];		/* 0x1ac */
+	u8 res4[0x4];		/* 0x1ac */
+	u32 cpu1_pwr_clamp;	/* 0x1b0 sun7i only */
+	u32 cpu1_pwroff;	/* 0x1b4 sun7i only */
+	u8 res5[0x2c];		/* 0x1b8 */
+	u32 dbg_ctrl1;		/* 0x1e4 */
+	u8 res6[0x18];		/* 0x1e8 */
 	u32 idle_cnt0_low;	/* 0x200 */
 	u32 idle_cnt0_high;	/* 0x204 */
 	u32 idle_cnt0_ctrl;	/* 0x208 */
-- 
cgit v0.10.2


From 3424c3f29970beaa3810acbc6ba3b8062a71ef09 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:33 +0800
Subject: sunxi: Add base address for GIC

Instead of hardcoding the GIC addresses in the PSCI implementation,
provide a base address in the cpu header.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 9752550..95fdb0e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -42,8 +42,8 @@
 
 #define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
 #define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		0x1c81000
-#define	GICC_BASE		0x1c82000
+#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
+#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
 
 .globl	psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index ac8ebf8..87bbd72 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -42,8 +42,8 @@
 
 #define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
 #define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		0x1c81000
-#define	GICC_BASE		0x1c82000
+#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
+#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
 
 .globl	psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 47e327e..c5e9d88 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -143,6 +143,8 @@
 #define SUNXI_DRAM_PHY0_BASE		0x01c65000
 #define SUNXI_DRAM_PHY1_BASE		0x01c66000
 
+#define SUNXI_GIC400_BASE		0x01c80000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
 
-- 
cgit v0.10.2


From 4257f5f8f631147803cdc6693b5046deb1a57be6 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 7 Jun 2016 10:54:34 +0800
Subject: sunxi: Add PSCI implementation in C

To make the PSCI backend more maintainable and easier to port to newer
SoCs, rewrite the current PSCI implementation in C.

Some inline assembly bits are required to access coprocessor registers.
PSCI stack setup is the only part left completely in assembly. In theory
this part could be split out of psci_arch_init into a separate common
function, and psci_arch_init could be completely in C.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 4d2274a..c208510 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
 
 ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_ARMV7_PSCI
-obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
-obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
-obj-$(CONFIG_MACH_SUN8I)	+= psci_sun6i.o
-endif
+obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
+obj-$(CONFIG_ARMV7_PSCI)	+= psci_head.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
new file mode 100644
index 0000000..a118e9d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
+ * which was based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#include <config.h>
+#include <common.h>
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/cpucfg.h>
+#include <asm/arch/prcm.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/system.h>
+
+#include <linux/bitops.h>
+
+#define __secure	__attribute__ ((section ("._secure.text")))
+#define __irq		__attribute__ ((interrupt ("IRQ")))
+
+#define	GICD_BASE	(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#define	GICC_BASE	(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+static void __secure cp15_write_cntp_tval(u32 tval)
+{
+	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+}
+
+static void __secure cp15_write_cntp_ctl(u32 val)
+{
+	asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+}
+
+static u32 __secure cp15_read_cntp_ctl(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+
+	return val;
+}
+
+#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
+
+static void __secure __mdelay(u32 ms)
+{
+	u32 reg = ONE_MS * ms;
+
+	cp15_write_cntp_tval(reg);
+	ISB;
+	cp15_write_cntp_ctl(3);
+
+	do {
+		ISB;
+		reg = cp15_read_cntp_ctl();
+	} while (!(reg & BIT(2)));
+
+	cp15_write_cntp_ctl(0);
+	ISB;
+}
+
+static void __secure clamp_release(u32 __maybe_unused *clamp)
+{
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
+	defined(CONFIG_MACH_SUN8I_H3)
+	u32 tmp = 0x1ff;
+	do {
+		tmp >>= 1;
+		writel(tmp, clamp);
+	} while (tmp);
+
+	__mdelay(10);
+#endif
+}
+
+static void __secure clamp_set(u32 __maybe_unused *clamp)
+{
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
+	defined(CONFIG_MACH_SUN8I_H3)
+	writel(0xff, clamp);
+#endif
+}
+
+static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
+					int cpu)
+{
+	if (on) {
+		/* Release power clamp */
+		clamp_release(clamp);
+
+		/* Clear power gating */
+		clrbits_le32(pwroff, BIT(cpu));
+	} else {
+		/* Set power gating */
+		setbits_le32(pwroff, BIT(cpu));
+
+		/* Activate power clamp */
+		clamp_set(clamp);
+	}
+}
+
+#ifdef CONFIG_MACH_SUN7I
+/* sun7i (A20) is different from other single cluster SoCs */
+static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
+			   on, 0);
+}
+#else /* ! CONFIG_MACH_SUN7I */
+static void __secure sunxi_cpu_set_power(int cpu, bool on)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
+			   on, cpu);
+}
+#endif /* CONFIG_MACH_SUN7I */
+
+void __secure sunxi_cpu_power_off(u32 cpuid)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+	u32 cpu = cpuid & 0x3;
+
+	/* Wait for the core to enter WFI */
+	while (1) {
+		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
+			break;
+		__mdelay(1);
+	}
+
+	/* Assert reset on target CPU */
+	writel(0, &cpucfg->cpu[cpu].rst);
+
+	/* Lock CPU (Disable external debug access) */
+	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+
+	/* Power down CPU */
+	sunxi_cpu_set_power(cpuid, false);
+
+	/* Unlock CPU (Disable external debug access) */
+	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+}
+
+static u32 __secure cp15_read_scr(void)
+{
+	u32 scr;
+
+	asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
+
+	return scr;
+}
+
+static void __secure cp15_write_scr(u32 scr)
+{
+	asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
+	ISB;
+}
+
+/*
+ * Although this is an FIQ handler, the FIQ is processed in monitor mode,
+ * which means there's no FIQ banked registers. This is the same as IRQ
+ * mode, so use the IRQ attribute to ask the compiler to handler entry
+ * and return.
+ */
+void __secure __irq psci_fiq_enter(void)
+{
+	u32 scr, reg, cpu;
+
+	/* Switch to secure mode */
+	scr = cp15_read_scr();
+	cp15_write_scr(scr & ~BIT(0));
+
+	/* Validate reason based on IAR and acknowledge */
+	reg = readl(GICC_BASE + GICC_IAR);
+
+	/* Skip spurious interrupts 1022 and 1023 */
+	if (reg == 1023 || reg == 1022)
+		goto out;
+
+	/* End of interrupt */
+	writel(reg, GICC_BASE + GICC_EOIR);
+	DSB;
+
+	/* Get CPU number */
+	cpu = (reg >> 10) & 0x7;
+
+	/* Power off the CPU */
+	sunxi_cpu_power_off(cpu);
+
+out:
+	/* Restore security level */
+	cp15_write_scr(scr);
+}
+
+int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+	u32 cpu = (mpidr & 0x3);
+
+	/* store target PC at target CPU stack top */
+	writel(pc, psci_get_cpu_stack_top(cpu));
+	DSB;
+
+	/* Set secondary core power on PC */
+	writel((u32)&psci_cpu_entry, &cpucfg->priv0);
+
+	/* Assert reset on target CPU */
+	writel(0, &cpucfg->cpu[cpu].rst);
+
+	/* Invalidate L1 cache */
+	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
+
+	/* Lock CPU (Disable external debug access) */
+	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+
+	/* Power up target CPU */
+	sunxi_cpu_set_power(cpu, true);
+
+	/* De-assert reset on target CPU */
+	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
+
+	/* Unlock CPU (Disable external debug access) */
+	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+void __secure psci_cpu_off(void)
+{
+	psci_cpu_off_common();
+
+	/* Ask CPU0 via SGI15 to pull the rug... */
+	writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+	DSB;
+
+	/* Wait to be turned off */
+	while (1)
+		wfi();
+}
+
+void __secure sunxi_gic_init(void)
+{
+	u32 reg;
+
+	/* SGI15 as Group-0 */
+	clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
+
+	/* Set SGI15 priority to 0 */
+	writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
+
+	/* Be cool with non-secure */
+	writel(0xff, GICC_BASE + GICC_PMR);
+
+	/* Switch FIQEn on */
+	setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
+
+	reg = cp15_read_scr();
+	reg |= BIT(2);  /* Enable FIQ in monitor mode */
+	reg &= ~BIT(0); /* Secure mode */
+	cp15_write_scr(reg);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/psci_head.S b/arch/arm/cpu/armv7/sunxi/psci_head.S
new file mode 100644
index 0000000..8fa823d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci_head.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/arch-armv7/generictimer.h>
+#include <asm/gic.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Memory layout:
+ *
+ * SECURE_RAM to text_end :
+ *	._secure_text section
+ * text_end to ALIGN_PAGE(text_end):
+ *	nothing
+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
+ *	1kB of stack per CPU (4 CPUs max).
+ */
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
+#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
+
+@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
+@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
+@ this function.
+ENTRY(psci_arch_init)
+	mov	r6, lr
+	mov	r7, r0
+	bl	psci_get_cpu_id		@ CPU ID => r0
+	bl	psci_get_cpu_stack_top	@ stack top => r0
+	sub	r0, r0, #4		@ Save space for target PC
+	mov	sp, r0
+	mov	r0, r7
+	mov	lr, r6
+
+	push	{r0, r1, r2, ip, lr}
+	bl	sunxi_gic_init
+	pop	{r0, r1, r2, ip, pc}
+ENDPROC(psci_arch_init)
+
+ENTRY(psci_text_end)
+	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
deleted file mode 100644
index 95fdb0e..0000000
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * Copyright (C) 2015 - Chen-Yu Tsai
- * Author: Chen-Yu Tsai <wens@csie.org>
- *
- * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <config.h>
-
-#include <asm/arch-armv7/generictimer.h>
-#include <asm/gic.h>
-#include <asm/macro.h>
-#include <asm/psci.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Memory layout:
- *
- * SECURE_RAM to text_end :
- *	._secure_text section
- * text_end to ALIGN_PAGE(text_end):
- *	nothing
- * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
- *	1kB of stack per CPU (4 CPUs max).
- */
-
-	.pushsection ._secure.text, "ax"
-
-	.arch_extension sec
-
-#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
-#define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
-#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
-
-.globl	psci_fiq_enter
-psci_fiq_enter:
-	push	{r0-r12}
-
-	@ Switch to secure
-	mrc	p15, 0, r7, c1, c1, 0
-	bic	r8, r7, #1
-	mcr	p15, 0, r8, c1, c1, 0
-	isb
-
-	@ Validate reason based on IAR and acknowledge
-	movw	r8, #(GICC_BASE & 0xffff)
-	movt	r8, #(GICC_BASE >> 16)
-	ldr	r9, [r8, #GICC_IAR]
-	movw	r10, #0x3ff
-	movt	r10, #0
-	cmp	r9, r10			@ skip spurious interrupt 1023
-	beq	out
-	movw	r10, #0x3fe		@ ...and 1022
-	cmp	r9, r10
-	beq	out
-	str	r9, [r8, #GICC_EOIR]	@ acknowledge the interrupt
-	dsb
-
-	@ Compute CPU number
-	lsr	r9, r9, #10
-	and	r9, r9, #0xf
-
-	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Wait for the core to enter WFI
-	lsl	r11, r9, #6		@ x64
-	add	r11, r11, r8
-
-1:	ldr	r10, [r11, #0x48]
-	tst	r10, #(1 << 2)
-	bne	2f
-	timer_wait r10, ONE_MS
-	b	1b
-
-	@ Reset CPU
-2:	mov	r10, #0
-	str	r10, [r11, #0x40]
-
-	@ Lock CPU
-	mov	r10, #1
-	lsl	r11, r10, r9		@ r11 is now CPU mask
-	ldr	r10, [r8, #0x1e4]
-	bic	r10, r10, r11
-	str	r10, [r8, #0x1e4]
-
-	movw	r8, #(SUNXI_PRCM_BASE & 0xffff)
-	movt	r8, #(SUNXI_PRCM_BASE >> 16)
-
-	@ Set power gating
-	ldr	r10, [r8, #0x100]
-	orr	r10, r10, r11
-	str	r10, [r8, #0x100]
-	timer_wait r10, ONE_MS
-
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
-	@ Activate power clamp
-	lsl	r12, r9, #2		@ x4
-	add	r12, r12, r8
-	mov	r10, #0xff
-	str	r10, [r12, #0x140]
-#endif
-
-	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Unlock CPU
-	ldr	r10, [r8, #0x1e4]
-	orr	r10, r10, r11
-	str	r10, [r8, #0x1e4]
-
-	@ Restore security level
-out:	mcr	p15, 0, r7, c1, c1, 0
-
-	pop	{r0-r12}
-	subs    pc, lr, #4
-
-	@ r1 = target CPU
-	@ r2 = target PC
-.globl	psci_cpu_on
-psci_cpu_on:
-	push	{lr}
-
-	mov	r0, r1
-	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
-	str	r2, [r0]		@ store target PC at stack top
-	dsb
-
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ CPU mask
-	and	r1, r1, #3	@ only care about first cluster
-	mov	r4, #1
-	lsl	r4, r4, r1
-
-	ldr	r6, =psci_cpu_entry
-	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
-
-	@ Assert reset on target CPU
-	mov	r6, #0
-	lsl	r5, r1, #6	@ 64 bytes per CPU
-	add	r5, r5, #0x40	@ Offset from base
-	add	r5, r5, r0	@ CPU control block
-	str	r6, [r5]	@ Reset CPU
-
-	@ l1 invalidate
-	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x184]
-
-	@ Lock CPU (Disable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	movw	r0, #(SUNXI_PRCM_BASE & 0xffff)
-	movt	r0, #(SUNXI_PRCM_BASE >> 16)
-
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
-	@ Release power clamp
-	lsl	r5, r1, #2	@ 1 register per CPU
-	add	r5, r5, r0	@ PRCM
-	movw	r6, #0x1ff
-	movt	r6, #0
-1:	lsrs	r6, r6, #1
-	str	r6, [r5, #0x140] @ CPUx_PWR_CLAMP
-	bne	1b
-#endif
-
-	timer_wait r6, TEN_MS
-
-	@ Clear power gating
-	ldr	r6, [r0, #0x100] @ CPU_PWROFF_GATING
-	bic	r6, r6, r4
-	str	r6, [r0, #0x100]
-
-	@ re-calculate CPU control register address
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Deassert reset on target CPU
-	mov	r6, #3
-	lsl	r5, r1, #6	@ 64 bytes per CPU
-	add	r5, r5, #0x40	@ Offset from base
-	add	r5, r5, r0	@ CPU control block
-	str	r6, [r5]
-
-	@ Unlock CPU (Enable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	orr	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-	pop	{pc}
-
-.globl	psci_cpu_off
-psci_cpu_off:
-	bl	psci_cpu_off_common
-
-	@ Ask CPU0 to pull the rug...
-	movw	r0, #(GICD_BASE & 0xffff)
-	movt	r0, #(GICD_BASE >> 16)
-	movw	r1, #15				@ SGI15
-	movt	r1, #1				@ Target is CPU0
-	str	r1, [r0, #GICD_SGIR]
-	dsb
-
-1:	wfi
-	b	1b
-
-.globl	psci_arch_init
-psci_arch_init:
-	mov	r6, lr
-
-	movw	r4, #(GICD_BASE & 0xffff)
-	movt	r4, #(GICD_BASE >> 16)
-
-	ldr	r5, [r4, #GICD_IGROUPRn]
-	bic	r5, r5, #(1 << 15) 	@ SGI15 as Group-0
-	str	r5, [r4, #GICD_IGROUPRn]
-
-	mov	r5, #0			@ Set SGI15 priority to 0
-	strb	r5, [r4, #(GICD_IPRIORITYRn + 15)]
-
-	add	r4, r4, #0x1000		@ GICC address
-
-	mov	r5, #0xff
-	str	r5, [r4, #GICC_PMR]	@ Be cool with non-secure
-
-	ldr	r5, [r4, #GICC_CTLR]
-	orr	r5, r5, #(1 << 3)	@ Switch FIQEn on
-	str	r5, [r4, #GICC_CTLR]
-
-	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
-	orr	r5, r5, #4		@ Enable FIQ in monitor mode
-	bic	r5, r5, #1		@ Secure mode
-	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
-	isb
-
-	bl	psci_get_cpu_id		@ CPU ID => r0
-	bl	psci_get_cpu_stack_top	@ stack top => r0
-	mov	sp, r0
-
-	bx	r6
-
-	.globl psci_text_end
-psci_text_end:
-	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
deleted file mode 100644
index 87bbd72..0000000
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright (C) 2013 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * Based on code by Carl van Schaik <carl@ok-labs.com>.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <config.h>
-
-#include <asm/arch-armv7/generictimer.h>
-#include <asm/gic.h>
-#include <asm/macro.h>
-#include <asm/psci.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Memory layout:
- *
- * SECURE_RAM to text_end :
- *	._secure_text section
- * text_end to ALIGN_PAGE(text_end):
- *	nothing
- * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
- *	1kB of stack per CPU (4 CPUs max).
- */
-
-	.pushsection ._secure.text, "ax"
-
-	.arch_extension sec
-
-#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
-#define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
-#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
-
-.globl	psci_fiq_enter
-psci_fiq_enter:
-	push	{r0-r12}
-
-	@ Switch to secure
-	mrc	p15, 0, r7, c1, c1, 0
-	bic	r8, r7, #1
-	mcr	p15, 0, r8, c1, c1, 0
-	isb
-
-	@ Validate reason based on IAR and acknowledge
-	movw	r8, #(GICC_BASE & 0xffff)
-	movt	r8, #(GICC_BASE >> 16)
-	ldr	r9, [r8, #GICC_IAR]
-	movw	r10, #0x3ff
-	movt	r10, #0
-	cmp	r9, r10			@ skip spurious interrupt 1023
-	beq	out
-	movw	r10, #0x3fe		@ ...and 1022
-	cmp	r9, r10
-	beq	out
-	str	r9, [r8, #GICC_EOIR]	@ acknowledge the interrupt
-	dsb
-
-	@ Compute CPU number
-	lsr	r9, r9, #10
-	and	r9, r9, #0xf
-
-	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Wait for the core to enter WFI
-	lsl	r11, r9, #6		@ x64
-	add	r11, r11, r8
-
-1:	ldr	r10, [r11, #0x48]
-	tst	r10, #(1 << 2)
-	bne	2f
-	timer_wait r10, ONE_MS
-	b	1b
-
-	@ Reset CPU
-2:	mov	r10, #0
-	str	r10, [r11, #0x40]
-
-	@ Lock CPU
-	mov	r10, #1
-	lsl	r9, r10, r9		@ r9 is now CPU mask
-	ldr	r10, [r8, #0x1e4]
-	bic	r10, r10, r9
-	str	r10, [r8, #0x1e4]
-
-	@ Set power gating
-	ldr	r10, [r8, #0x1b4]
-	orr	r10, r10, #1
-	str	r10, [r8, #0x1b4]
-	timer_wait r10, ONE_MS
-
-	@ Activate power clamp
-	mov	r10, #1
-1:	str	r10, [r8, #0x1b0]
-	lsl	r10, r10, #1
-	orr	r10, r10, #1
-	tst	r10, #0x100
-	beq	1b
-
-	@ Restore security level
-out:	mcr	p15, 0, r7, c1, c1, 0
-
-	pop	{r0-r12}
-	subs    pc, lr, #4
-
-	@ r1 = target CPU
-	@ r2 = target PC
-.globl	psci_cpu_on
-psci_cpu_on:
-	push	{lr}
-
-	mov	r0, r1
-	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
-	str	r2, [r0]		@ store target PC at stack top
-	dsb
-
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ CPU mask
-	and	r1, r1, #3	@ only care about first cluster
-	mov	r4, #1
-	lsl	r4, r4, r1
-
-	ldr	r6, =psci_cpu_entry
-	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
-
-	@ Assert reset on target CPU
-	mov	r6, #0
-	lsl	r5, r1, #6	@ 64 bytes per CPU
-	add	r5, r5, #0x40	@ Offset from base
-	add	r5, r5, r0	@ CPU control block
-	str	r6, [r5]	@ Reset CPU
-
-	@ l1 invalidate
-	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x184]
-
-	@ Lock CPU (Disable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	@ Release power clamp
-	movw	r6, #0x1ff
-	movt	r6, #0
-1:	lsrs	r6, r6, #1
-	str	r6, [r0, #0x1b0] @ CPU1_PWR_CLAMP
-	bne	1b
-
-	timer_wait r1, TEN_MS
-
-	@ Clear power gating
-	ldr	r6, [r0, #0x1b4] @ CPU1_PWROFF_REG
-	bic	r6, r6, #1
-	str	r6, [r0, #0x1b4]
-
-	@ Deassert reset on target CPU
-	mov	r6, #3
-	str	r6, [r5]
-
-	@ Unlock CPU (Enable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	orr	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-	pop	{pc}
-
-.globl	psci_cpu_off
-psci_cpu_off:
-	bl	psci_cpu_off_common
-
-	@ Ask CPU0 to pull the rug...
-	movw	r0, #(GICD_BASE & 0xffff)
-	movt	r0, #(GICD_BASE >> 16)
-	movw	r1, #15				@ SGI15
-	movt	r1, #1				@ Target is CPU0
-	str	r1, [r0, #GICD_SGIR]
-	dsb
-
-1:	wfi
-	b	1b
-
-.globl	psci_arch_init
-psci_arch_init:
-	mov	r6, lr
-
-	movw	r4, #(GICD_BASE & 0xffff)
-	movt	r4, #(GICD_BASE >> 16)
-
-	ldr	r5, [r4, #GICD_IGROUPRn]
-	bic	r5, r5, #(1 << 15) 	@ SGI15 as Group-0
-	str	r5, [r4, #GICD_IGROUPRn]
-
-	mov	r5, #0			@ Set SGI15 priority to 0
-	strb	r5, [r4, #(GICD_IPRIORITYRn + 15)]
-
-	add	r4, r4, #0x1000		@ GICC address
-
-	mov	r5, #0xff
-	str	r5, [r4, #GICC_PMR]	@ Be cool with non-secure
-
-	ldr	r5, [r4, #GICC_CTLR]
-	orr	r5, r5, #(1 << 3)	@ Switch FIQEn on
-	str	r5, [r4, #GICC_CTLR]
-
-	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
-	orr	r5, r5, #4		@ Enable FIQ in monitor mode
-	bic	r5, r5, #1		@ Secure mode
-	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
-	isb
-
-	bl	psci_get_cpu_id		@ CPU ID => r0
-	bl	psci_get_cpu_stack_top	@ stack top => r0
-	mov	sp, r0
-
-	bx	r6
-
-	.globl psci_text_end
-psci_text_end:
-	.popsection
-- 
cgit v0.10.2


From 9f823615af919c6b89f0b80197f009f78299dcde Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Mon, 20 Jun 2016 23:16:28 +0200
Subject: Kconfig: Add a new DISTRO_DEFAULTS Kconfig option

DISTRO_DEFAULTS is intended to mirror / replace
include/config_distro_defaults.h.

The intend is for boards which include this file to select this from
their Kconfig files and when moving setting to Kconfig which are #define-ed
in config_distro_defaults.h to select this from DISTRO_DEFAULTS so that
boards which have selected DISTRO_DEFAULTS will keep the same configuration
as before without needing any defconfig file changes.

The initial list of selected things matches all settings recently removed
from config_distro_defaults.h because they have been converted to Kconfig,
with the exception of CMD_ELF and CMD_NET, which have a default of y, if
the default of these ever changes they should be selected by DISTRO_DEFAULTS
too.

For testing and example purposes this commit also converts ARCH_SUNXI
to use DISTRO_DEFAULT instead of selecting everything it needs itself.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/Kconfig b/Kconfig
index 817f4f0..3ceff25 100644
--- a/Kconfig
+++ b/Kconfig
@@ -53,6 +53,23 @@ config CC_OPTIMIZE_FOR_SIZE
 
 	  This option is enabled by default for U-Boot.
 
+config DISTRO_DEFAULTS
+	bool "Select defaults suitable for booting general purpose Linux distributions"
+	default y if ARCH_SUNXI
+	default n
+	select CMD_BOOTZ
+	select CMD_DHCP
+	select CMD_EXT2
+	select CMD_EXT4
+	select CMD_FAT
+	select CMD_FS_GENERIC
+	select CMD_MII
+	select CMD_PING
+	select HUSH_PARSER
+	help
+	  Select this to enable various options and commands which are suitable
+	  for building u-boot for booting general purpose Linux distributions.
+
 config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
 	default y if DM
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f48be96..e9d2fc9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -610,16 +610,8 @@ config TARGET_CM_T43
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
-	select CMD_BOOTZ
-	select CMD_DHCP
-	select CMD_EXT2
-	select CMD_EXT4
-	select CMD_FAT
-	select CMD_FS_GENERIC
 	select CMD_GPIO
-	select CMD_MII
 	select CMD_MMC if MMC
-	select CMD_PING
 	select CMD_USB
 	select DM
 	select DM_ETH
@@ -627,7 +619,6 @@ config ARCH_SUNXI
 	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_USB
-	select HUSH_PARSER
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
diff --git a/doc/README.distro b/doc/README.distro
index e1b7216..77d5c6d 100644
--- a/doc/README.distro
+++ b/doc/README.distro
@@ -162,6 +162,12 @@ U-Boot Implementation
 Enabling the distro options
 ---------------------------
 
+In your board's defconfig, enable the DISTRO_DEFAULTS option by adding
+a line with "CONFIG_DISTRO_DEFAULTS=y". If you want to enable this
+from Kconfig itself, for e.g. all boards using a specific SoC then
+add a "default y if ARCH_FOO" to the DISTRO_DEFAULTS section of
+the Kconfig file in the root of the u-boot sources.
+
 In your board configuration file, include the following:
 
 ------------------------------------------------------------
-- 
cgit v0.10.2


From dad7b74045929ff10d93ec1dd60d0fd36fd9a527 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 26 Apr 2016 15:29:00 -0600
Subject: net: rtl8169: fix switching between adapters

The rtl8169 driver uses a global variable to store the register address
of the adapter being operated upon. This is updated to point at the
correct adapter when sending or receiving a packet, or shutting down the
adapter, but not when initializing the adapter. Consequently, switching
between different adapters within the same U-Boot runtime does not work
correctly since the driver programs the wrong registers during
rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start().

Note that since rtl8169_eth_stop() does set the global variable, the
second consecutive attempt to use the "new" adapter did work even before
this patch, because each time network usage is shut down, the network
core calls stop, which sets the variable so that the next start does
actually initialize the hardware, and the adapter works.

Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so
if using only a single device, or if picking the "right" device (based on
probe order) when multiple devices are present, ioaddr will already be set
correctly from the get-go, so the issue does not occur.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 163b9df..843b083 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -850,9 +850,11 @@ static void rtl8169_init_ring(pci_dev_t dev)
 }
 
 #ifdef CONFIG_DM_ETH
-static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr)
+static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
+				 unsigned long dev_iobase)
 #else
-static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
+static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
+				 unsigned long dev_iobase)
 #endif
 {
 	int i;
@@ -862,6 +864,8 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
 	printf ("%s\n", __FUNCTION__);
 #endif
 
+	ioaddr = dev_iobase;
+
 	rtl8169_init_ring(dev);
 	rtl8169_hw_start(dev);
 	/* Construct a perfect filter frame with the mac address as first match
@@ -885,8 +889,9 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
 static int rtl8169_eth_start(struct udevice *dev)
 {
 	struct eth_pdata *plat = dev_get_platdata(dev);
+	struct rtl8169_private *priv = dev_get_priv(dev);
 
-	rtl8169_common_start(dev, plat->enetaddr);
+	rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
 
 	return 0;
 }
@@ -897,7 +902,7 @@ RESET - Finish setting up the ethernet interface
 static int rtl_reset(struct eth_device *dev, bd_t *bis)
 {
 	rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
-			     dev->enetaddr);
+			     dev->enetaddr, dev->iobase);
 
 	return 0;
 }
-- 
cgit v0.10.2


From 79887749f802af5c30ef019bd13f299f79a1530a Mon Sep 17 00:00:00 2001
From: Alexey Firago <alexey_firago@mentor.com>
Date: Thu, 26 May 2016 16:28:44 +0300
Subject: net: phy: micrel: add support for KSZ886x switches in MIIM mode

This patch adds a phy driver for the Micrel KSZ886x switches.

Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.

KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)

This patch supports only unmanaged and MIIM modes.

Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.

Verified with the KSZ8863MLL.

Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index b08788a..6b313a9 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -487,6 +487,31 @@ static struct phy_driver ksz9031_driver = {
 	.readext = &ksz9031_phy_extread,
 };
 
+int ksz886x_config(struct phy_device *phydev)
+{
+	/* we are connected directly to the switch without
+	 * dedicated PHY. */
+	phydev->link = 1;
+	phydev->duplex = DUPLEX_FULL;
+	phydev->speed = SPEED_100;
+	return 0;
+}
+
+static int ksz886x_startup(struct phy_device *phydev)
+{
+	return 0;
+}
+
+static struct phy_driver ksz886x_driver = {
+	.name = "Micrel KSZ886x Switch",
+	.uid  = 0x00221430,
+	.mask = 0xfffff0,
+	.features = PHY_BASIC_FEATURES,
+	.config = &ksz886x_config,
+	.startup = &ksz886x_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 int phy_micrel_init(void)
 {
 	phy_register(&KSZ804_driver);
@@ -500,5 +525,6 @@ int phy_micrel_init(void)
 #endif
 	phy_register(&ksz9031_driver);
 	phy_register(&ksz8895_driver);
+	phy_register(&ksz886x_driver);
 	return 0;
 }
-- 
cgit v0.10.2


From 08e64cece2f8e793b5c085ebf27c27dfc5ed730d Mon Sep 17 00:00:00 2001
From: Nathan Rossi <nathan@nathanrossi.com>
Date: Fri, 3 Jun 2016 23:16:17 +1000
Subject: net: phy: marvell: Do not reset 88e1310 after autoneg

Commit a058052c "net: phy: do not read configuration register on reset",
changes the behaviour of the phy_reset function such that the state of
the BMCR register is not preserved during reset.

Change the config function for the m88e1310 so that it does not do a
reset after configuring auto-negotiation.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index d2e68d4..58d287b 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -476,10 +476,7 @@ static int m88e1310_config(struct phy_device *phydev)
 	/* Ensure to return to page 0 */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
 
-	genphy_config_aneg(phydev);
-	phy_reset(phydev);
-
-	return 0;
+	return genphy_config_aneg(phydev);
 }
 
 static struct phy_driver M88E1011S_driver = {
-- 
cgit v0.10.2


From 69fd0d4131c73a3b8a199a8d88fb4e5c688b58d5 Mon Sep 17 00:00:00 2001
From: Guillaume GARDET <guillaume.gardet@free.fr>
Date: Mon, 6 Jun 2016 15:11:45 +0200
Subject: NFS: Add error message when U-Boot NFS version (V2) is not supported
 by NFS server

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: joe.hershberger@ni.com
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/net/nfs.c b/net/nfs.c
index 78968d8..f60a037 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -481,8 +481,23 @@ static int nfs_lookup_reply(uchar *pkt, unsigned len)
 	if (rpc_pkt.u.reply.rstatus  ||
 	    rpc_pkt.u.reply.verifier ||
 	    rpc_pkt.u.reply.astatus  ||
-	    rpc_pkt.u.reply.data[0])
+	    rpc_pkt.u.reply.data[0]) {
+		switch (ntohl(rpc_pkt.u.reply.astatus)) {
+		case 0: /* Not an error */
+			break;
+		case 2: /* Remote can't support NFS version */
+			printf("*** ERROR: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n",
+			       2,
+			       ntohl(rpc_pkt.u.reply.data[0]),
+			       ntohl(rpc_pkt.u.reply.data[1]));
+			break;
+		default: /* Unknown error on 'accept state' flag */
+			printf("*** ERROR: accept state error (%d)\n",
+			       ntohl(rpc_pkt.u.reply.astatus));
+			break;
+		}
 		return -1;
+	}
 
 	memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
 
-- 
cgit v0.10.2


From 5030159e27a1d6293f0f064807d4eef5dd6de714 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 15 Jun 2016 14:33:50 +0900
Subject: tools: moveconfig: fix needless move for config with default 1

When moving an integer type option with default value 1, the tool
moves configs with the same value as the default (, and then removed
by the later savedefconfig).  This is a needless operation.

The KconfigParser.parse_one_config() should compare the config after
the "=y -> =1" fixup.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 5e5ca06..03acbea 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -487,9 +487,6 @@ class KconfigParser:
         else:
             new_val = not_set
 
-        if old_val == new_val:
-            return (ACTION_NO_CHANGE, new_val)
-
         # If this CONFIG is neither bool nor trisate
         if old_val[-2:] != '=y' and old_val[-2:] != '=m' and old_val != not_set:
             # tools/scripts/define2mk.sed changes '1' to 'y'.
@@ -498,7 +495,8 @@ class KconfigParser:
             if new_val[-2:] == '=y':
                 new_val = new_val[:-1] + '1'
 
-        return (ACTION_MOVE, new_val)
+        return (ACTION_NO_CHANGE if old_val == new_val else ACTION_MOVE,
+                new_val)
 
     def update_dotconfig(self):
         """Parse files for the config options and update the .config.
-- 
cgit v0.10.2


From 5cc42a51846cd69596081a9cd9d2bd0495815525 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 15 Jun 2016 14:33:51 +0900
Subject: tools: moveconfig: change class WorkDir to class ReferenceSource

The class WorkDir can be used in a very generic way, but currently
it is only used for containing a reference source directory.

This commit changes it for a more dedicated use.  The move_config
function can be more readable by enclosing the git-clone and git-
checkout in the class constructor.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 03acbea..44be51f 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -880,23 +880,39 @@ class Slots:
                 for board in failed_boards:
                     f.write(board + '\n')
 
-class WorkDir:
-    def __init__(self):
-        """Create a new working directory."""
-        self.work_dir = tempfile.mkdtemp()
+class ReferenceSource:
+
+    """Reference source against which original configs should be parsed."""
+
+    def __init__(self, commit):
+        """Create a reference source directory based on a specified commit.
+
+        Arguments:
+          commit: commit to git-clone
+        """
+        self.src_dir = tempfile.mkdtemp()
+        print "Cloning git repo to a separate work directory..."
+        subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
+                                cwd=self.src_dir)
+        print "Checkout '%s' to build the original autoconf.mk." % \
+            subprocess.check_output(['git', 'rev-parse', '--short', commit]).strip()
+        subprocess.check_output(['git', 'checkout', commit],
+                                stderr=subprocess.STDOUT, cwd=self.src_dir)
 
     def __del__(self):
-        """Delete the working directory
+        """Delete the reference source directory
 
         This function makes sure the temporary directory is cleaned away
         even if Python suddenly dies due to error.  It should be done in here
         because it is guaranteed the destructor is always invoked when the
         instance of the class gets unreferenced.
         """
-        shutil.rmtree(self.work_dir)
+        shutil.rmtree(self.src_dir)
+
+    def get_dir(self):
+        """Return the absolute path to the reference source directory."""
 
-    def get(self):
-        return self.work_dir
+        return self.src_dir
 
 def move_config(configs, options):
     """Move config options to defconfig files.
@@ -914,20 +930,11 @@ def move_config(configs, options):
         print 'Move ' + ', '.join(configs),
     print '(jobs: %d)\n' % options.jobs
 
-    reference_src_dir = ''
-
     if options.git_ref:
-        work_dir = WorkDir()
-        reference_src_dir = work_dir.get()
-        print "Cloning git repo to a separate work directory..."
-        subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
-                                cwd=reference_src_dir)
-        print "Checkout '%s' to build the original autoconf.mk." % \
-            subprocess.check_output(['git', 'rev-parse', '--short',
-                                    options.git_ref]).strip()
-        subprocess.check_output(['git', 'checkout', options.git_ref],
-                                stderr=subprocess.STDOUT,
-                                cwd=reference_src_dir)
+        reference_src = ReferenceSource(options.git_ref)
+        reference_src_dir = reference_src.get_dir()
+    else:
+        reference_src_dir = ''
 
     if options.defconfigs:
         defconfigs = [line.strip() for line in open(options.defconfigs)]
-- 
cgit v0.10.2


From f432c33f27898070718dd568feb104fc1870ca15 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 15 Jun 2016 14:33:52 +0900
Subject: tools: moveconfig: simplify source tree switching

The subprocess.Popen() does not change the child process's working
directory if cwd=None is given.  Let's exploit this fact to refactor
the source directory handling.

We no longer have to pass "-C <reference_src_dir>" to the sub-process
because self.current_src_dir tracks the source tree against which we
want to run defconfig/autoconf.

The flag self.use_git_ref is not necessary either because we can know
the current state by checking whether the self.current_src_dir is a
valid string or None.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 44be51f..c0ac5f4 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -645,7 +645,7 @@ class Slot:
 
         self.defconfig = defconfig
         self.log = ''
-        self.use_git_ref = True if self.options.git_ref else False
+        self.current_src_dir = self.reference_src_dir
         self.do_defconfig()
         return True
 
@@ -674,13 +674,13 @@ class Slot:
         if self.ps.poll() != 0:
             self.handle_error()
         elif self.state == STATE_DEFCONFIG:
-            if self.options.git_ref and not self.use_git_ref:
+            if self.reference_src_dir and not self.current_src_dir:
                 self.do_savedefconfig()
             else:
                 self.do_autoconf()
         elif self.state == STATE_AUTOCONF:
-            if self.use_git_ref:
-                self.use_git_ref = False
+            if self.current_src_dir:
+                self.current_src_dir = None
                 self.do_defconfig()
             else:
                 self.do_savedefconfig()
@@ -706,11 +706,9 @@ class Slot:
 
         cmd = list(self.make_cmd)
         cmd.append(self.defconfig)
-        if self.use_git_ref:
-            cmd.append('-C')
-            cmd.append(self.reference_src_dir)
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   stderr=subprocess.PIPE)
+                                   stderr=subprocess.PIPE,
+                                   cwd=self.current_src_dir)
         self.state = STATE_DEFCONFIG
 
     def do_autoconf(self):
@@ -728,11 +726,9 @@ class Slot:
             cmd.append('CROSS_COMPILE=%s' % self.cross_compile)
         cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
         cmd.append('include/config/auto.conf')
-        if self.use_git_ref:
-            cmd.append('-C')
-            cmd.append(self.reference_src_dir)
         self.ps = subprocess.Popen(cmd, stdout=self.devnull,
-                                   stderr=subprocess.PIPE)
+                                   stderr=subprocess.PIPE,
+                                   cwd=self.current_src_dir)
         self.state = STATE_AUTOCONF
 
     def do_savedefconfig(self):
@@ -934,7 +930,7 @@ def move_config(configs, options):
         reference_src = ReferenceSource(options.git_ref)
         reference_src_dir = reference_src.get_dir()
     else:
-        reference_src_dir = ''
+        reference_src_dir = None
 
     if options.defconfigs:
         defconfigs = [line.strip() for line in open(options.defconfigs)]
-- 
cgit v0.10.2


From 96dccd9767311f4b8e585fd9e33fcb2a09e36951 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 15 Jun 2016 14:33:53 +0900
Subject: tools: moveconfig: simplify show_failed_boards() and show more info

Since commit 1d085568b3de ("tools: moveconfig: display log atomically
in more readable format"), the function color_text() is clever enough
to exclude LF from escape sequences.  Exploit it for removing the
"for" loops from Slots.show_failed_boards().

Also, display "(the list has been saved in moveconfig.failed)" if
there are failed boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index c0ac5f4..7a4136d 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -860,21 +860,22 @@ class Slots:
 
     def show_failed_boards(self):
         """Display all of the failed boards (defconfigs)."""
-        failed_boards = []
+        boards = []
+        output_file = 'moveconfig.failed'
 
         for slot in self.slots:
-            failed_boards += slot.get_failed_boards()
-
-        if len(failed_boards) > 0:
-            msg = [ "The following boards were not processed due to error:" ]
-            msg += failed_boards
-            for line in msg:
-                print >> sys.stderr, color_text(self.options.color,
-                                                COLOR_LIGHT_RED, line)
-
-            with open('moveconfig.failed', 'w') as f:
-                for board in failed_boards:
-                    f.write(board + '\n')
+            boards += slot.get_failed_boards()
+
+        if boards:
+            boards = '\n'.join(boards) + '\n'
+            msg = "The following boards were not processed due to error:\n"
+            msg += boards
+            msg += "(the list has been saved in %s)\n" % output_file
+            print >> sys.stderr, color_text(self.options.color, COLOR_LIGHT_RED,
+                                            msg)
+
+            with open(output_file, 'w') as f:
+                f.write(boards)
 
 class ReferenceSource:
 
-- 
cgit v0.10.2


From fc2661eebe9e788aee61dcb0c9c8337cda1ae93b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 15 Jun 2016 14:33:54 +0900
Subject: tools: moveconfig: show suspicious boards with possible misconversion

There are some cases where config options are moved, but they are
ripped off at the final savedefconfig stage:

  - The moved option is not user-configurable, for example, due to
    a missing prompt in the Kconfig entry

  - The config was not defined in the original config header despite
    the Kconfig specifies it as non-bool type

  - The config define in the header contains reference to another
    macro, for example:
        #define CONFIG_CONS_INDEX     (CONFIG_SYS_LPC32XX_UART - 2)
    The current moveconfig does not support recursive macro expansion.

In these cases, the conversion is very likely to be an unexpected
result.  That is why I decided to display the log in yellow color
in commit 5da4f857beac ("tools: moveconfig: report when CONFIGs are
removed by savedefconfig").

It would be nice to display the list of suspicious boards when the
tool finishes processing.  It is highly recommended to check the
defconfigs once again when this message is displayed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 7a4136d..d362923 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -611,6 +611,7 @@ class Slot:
         self.parser = KconfigParser(configs, options, self.build_dir)
         self.state = STATE_IDLE
         self.failed_boards = []
+        self.suspicious_boards = []
 
     def __del__(self):
         """Delete the working directory
@@ -755,7 +756,10 @@ class Slot:
     def update_defconfig(self):
         """Update the input defconfig and go back to the idle state."""
 
-        self.log += self.parser.check_defconfig()
+        log = self.parser.check_defconfig()
+        if log:
+            self.suspicious_boards.append(self.defconfig)
+            self.log += log
         orig_defconfig = os.path.join('configs', self.defconfig)
         new_defconfig = os.path.join(self.build_dir, 'defconfig')
         updated = not filecmp.cmp(orig_defconfig, new_defconfig)
@@ -799,6 +803,11 @@ class Slot:
         """
         return self.failed_boards
 
+    def get_suspicious_boards(self):
+        """Returns a list of boards (defconfigs) with possible misconversion.
+        """
+        return self.suspicious_boards
+
 class Slots:
 
     """Controller of the array of subprocess slots."""
@@ -877,6 +886,26 @@ class Slots:
             with open(output_file, 'w') as f:
                 f.write(boards)
 
+    def show_suspicious_boards(self):
+        """Display all boards (defconfigs) with possible misconversion."""
+        boards = []
+        output_file = 'moveconfig.suspicious'
+
+        for slot in self.slots:
+            boards += slot.get_suspicious_boards()
+
+        if boards:
+            boards = '\n'.join(boards) + '\n'
+            msg = "The following boards might have been converted incorrectly.\n"
+            msg += "It is highly recommended to check them manually:\n"
+            msg += boards
+            msg += "(the list has been saved in %s)\n" % output_file
+            print >> sys.stderr, color_text(self.options.color, COLOR_YELLOW,
+                                            msg)
+
+            with open(output_file, 'w') as f:
+                f.write(boards)
+
 class ReferenceSource:
 
     """Reference source against which original configs should be parsed."""
@@ -967,6 +996,7 @@ def move_config(configs, options):
 
     print ''
     slots.show_failed_boards()
+    slots.show_suspicious_boards()
 
 def main():
     try:
-- 
cgit v0.10.2


From 61520ac4d5545cc8d2e1792092e46ab8043d5f36 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 23 Jun 2016 18:14:50 +0200
Subject: arm: socfpga: Fix "improve raw MMC SPL boot"

This fixes commit d31e9c575f24f4b7f5f382ccae70d7a86bbc379d ,
which broke booting from SD card on all SoCFPGA boards. The
patch assumes the bootloader partition to be partition 3, at
the end of the SD card, which doesn't make any sense. U-Boot
assumes the bootloader partition is partition 1 or that the
bootloader image is at offset +1 MiB from the start of SD card.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Sylvain Lesne <lesne@alse-fr.com>

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 1f8b7b3..f654f94 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -346,7 +346,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200 /* offset 512 sect (256k) */
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
-- 
cgit v0.10.2


From f3acaf438de74a0b278abc71fb2aca7e7aa86ffa Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Sun, 12 Jun 2016 14:42:04 +0800
Subject: armv8/fsl_lsch2: Correct the cores frequency initialization

The register CLKCNCSR controls the frequency of all cores in the same
cluster.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 3a77b21..d0dc58d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/soc.h>
 #include <fsl_ifc.h>
+#include "cpu.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -47,7 +48,7 @@ void get_sys_info(struct sys_info *sys_info)
 		[5] = 2,	/* CC2 PPL / 2 */
 	};
 
-	uint i;
+	uint i, cluster;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
@@ -80,8 +81,9 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
 
-	for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
-		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		cluster = fsl_qoriq_core_to_cluster(cpu);
+		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_pll[c_pll_sel];
 
-- 
cgit v0.10.2


From a2fd238e4923d0b0e10d4ca24ad6410244d8ea6c Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Mon, 13 Jun 2016 11:20:30 +0800
Subject: armv8: ls1043aqds: fix to get boot device info from FPGA

The LBMAP switches on the board will tell which boot device is used.
Only QSPI boot is supported if the boot device is IFCCard.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 7e47ef0..9447c93 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -47,7 +47,7 @@ enum {
 int checkboard(void)
 {
 	char buf[64];
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
+#ifndef CONFIG_SD_BOOT
 	u8 sw;
 #endif
 
@@ -55,8 +55,6 @@ int checkboard(void)
 
 #ifdef CONFIG_SD_BOOT
 	puts("SD\n");
-#elif defined(CONFIG_QSPI_BOOT)
-	puts("QSPI\n");
 #else
 	sw = QIXIS_READ(brdcfg[0]);
 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -67,8 +65,8 @@ int checkboard(void)
 		puts("PromJet\n");
 	else if (sw == 0x9)
 		puts("NAND\n");
-	else if (sw == 0x15)
-		printf("IFCCard\n");
+	else if (sw == 0xF)
+		printf("QSPI\n");
 	else
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
-- 
cgit v0.10.2


From 85a2f772c256af9d8f0570548d2c2041a7b461e9 Mon Sep 17 00:00:00 2001
From: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
Date: Mon, 6 Jun 2016 09:40:11 +0200
Subject: omap3: bugfix in timer on rollover

Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>

diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 032bd2c..49e3a97 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -77,7 +77,7 @@ ulong get_timer_masked(void)
 		/* move stamp fordward with absoulte diff ticks */
 		gd->arch.tbl += (now - gd->arch.lastinc);
 	} else {	/* we have rollover of incrementer */
-		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+		gd->arch.tbl += ((TIMER_OVERFLOW_VAL / (TIMER_CLOCK /
 				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
 	}
 	gd->arch.lastinc = now;
-- 
cgit v0.10.2


From 92dfd9221c97265ff303bf9437481b9767bd72ea Mon Sep 17 00:00:00 2001
From: Sergey Kubushyn <ksi@koi8.net>
Date: Tue, 7 Jun 2016 11:14:31 -0700
Subject: cmd: bootefi: cosmetic

Short help (description) in bootefi command has a trailing "\n" that
breaks the "help" command output (empty line after "bootefi").

Nothing important, doesn't affect anything but better be fixed in the
upcoming release.

Still working on i.MX6 and their siblings NAND U-Boot update -- it
works here but not ready for a submission yet. Anyway it is for the
next cycle, not going to go into this release because it is too big
and may affect something else.

Also have some thoughts about fastboot (using multiple devices) but
this will go into separate email with RFC.

Signed-off-by: Sergey Kubushyn <ksi@koi8.net>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 2169065..011f62c 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -255,7 +255,7 @@ static char bootefi_help_text[] =
 
 U_BOOT_CMD(
 	bootefi, 3, 0, do_bootefi,
-	"Boots an EFI payload from memory\n",
+	"Boots an EFI payload from memory",
 	bootefi_help_text
 );
 
-- 
cgit v0.10.2


From f8f9107d97b849afe69ca86e7abd8d1748ea7acd Mon Sep 17 00:00:00 2001
From: Teddy Reed <teddy.reed@gmail.com>
Date: Thu, 9 Jun 2016 19:38:02 -0700
Subject: mkimage: fit: spl: Add an optional static offset for external data

When building a FIT with external data (-E), U-Boot proper may require
absolute positioning for executing the external firmware. To acheive this
use the (-p) switch, which will replace the amended 'data-offset' with
'data-position' indicating the absolute position of external data.

It is considered an error if the requested absolute position overlaps with the
initial data required for the compact FIT.

Signed-off-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/doc/mkimage.1 b/doc/mkimage.1
index 4b3a255..ffa7d60 100644
--- a/doc/mkimage.1
+++ b/doc/mkimage.1
@@ -152,6 +152,12 @@ verification. Typically the file here is the device tree binary used by
 CONFIG_OF_CONTROL in U-Boot.
 
 .TP
+.BI "\-p [" "external position" "]"
+Place external data at a static external position. See \-E. Instead of writing
+a 'data-offset' property defining the offset from the end of the FIT, \-p will
+use 'data-position' as the absolute position from the base of the FIT.
+
+.TP
 .BI "\-r
 Specifies that keys used to sign the FIT are required. This means that they
 must be verified for the image to boot. Without this option, the verification
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 3f54180..91aa89a 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -282,6 +282,9 @@ In this case the 'data' property is omitted. Instead you can use:
     aligned to a 4-byte boundary.
   - data-size : size of the data in bytes
 
+The 'data-offset' property can be substituted with 'data-position', which
+defines an absolute position or address as the offset. This is helpful when
+booting U-Boot proper before performing relocation.
 
 9) Examples
 -----------
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 0551572..76a6de4 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -416,7 +416,13 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname)
 			ret = -EPERM;
 			goto err_munmap;
 		}
-		fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
+		if (params->external_offset > 0) {
+			/* An external offset positions the data absolutely. */
+			fdt_setprop_u32(fdt, node, "data-position",
+					params->external_offset + buf_ptr);
+		} else {
+			fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
+		}
 		fdt_setprop_u32(fdt, node, "data-size", len);
 
 		buf_ptr += (len + 3) & ~3;
@@ -437,6 +443,17 @@ static int fit_extract_data(struct image_tool_params *params, const char *fname)
 		ret = -EIO;
 		goto err;
 	}
+
+	/* Check if an offset for the external data was set. */
+	if (params->external_offset > 0) {
+		if (params->external_offset < new_size) {
+			debug("External offset %x overlaps FIT length %x",
+			      params->external_offset, new_size);
+			ret = -EINVAL;
+			goto err;
+		}
+		new_size = params->external_offset;
+	}
 	if (lseek(fd, new_size, SEEK_SET) < 0) {
 		debug("%s: Failed to seek to end of file: %s\n", __func__,
 		      strerror(errno));
diff --git a/tools/imagetool.h b/tools/imagetool.h
index a3ed0f4..1f2161c 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -74,6 +74,7 @@ struct image_tool_params {
 	struct content_info *content_tail;
 	bool external_data;	/* Store data outside the FIT */
 	bool quiet;		/* Don't output text in normal operation */
+	unsigned int external_offset;	/* Add padding to external data */
 };
 
 /*
diff --git a/tools/mkimage.c b/tools/mkimage.c
index aefe22f..ff3024a 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -93,11 +93,13 @@ static void usage(const char *msg)
 		"          -f => input filename for FIT source\n");
 #ifdef CONFIG_FIT_SIGNATURE
 	fprintf(stderr,
-		"Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-r]\n"
+		"Signing / verified boot options: [-E] [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r]\n"
+		"          -E => place data outside of the FIT structure\n"
 		"          -k => set directory containing private keys\n"
 		"          -K => write public keys to this .dtb file\n"
 		"          -c => add comment in signature node\n"
 		"          -F => re-sign existing FIT image\n"
+		"          -p => place external data at a static position\n"
 		"          -r => mark keys used as 'required' in dtb\n");
 #else
 	fprintf(stderr,
@@ -136,7 +138,7 @@ static void process_args(int argc, char **argv)
 	int opt;
 
 	while ((opt = getopt(argc, argv,
-			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:qsT:vVx")) != -1) {
+			     "a:A:b:cC:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != -1) {
 		switch (opt) {
 		case 'a':
 			params.addr = strtoull(optarg, &ptr, 16);
@@ -216,6 +218,13 @@ static void process_args(int argc, char **argv)
 			if (params.os < 0)
 				usage("Invalid operating system");
 			break;
+		case 'p':
+			params.external_offset = strtoull(optarg, &ptr, 16);
+			if (*ptr) {
+				fprintf(stderr, "%s: invalid offset size %s\n",
+					params.cmdname, optarg);
+				exit(EXIT_FAILURE);
+			}
 		case 'q':
 			params.quiet = 1;
 			break;
-- 
cgit v0.10.2


From 4f1318b29c7a20a694d02247917a6000f08dec9a Mon Sep 17 00:00:00 2001
From: Michael Trimarchi <michael@amarulasolutions.com>
Date: Fri, 10 Jun 2016 19:54:37 +0200
Subject: common: image: minimal android image iminfo support

We already support iminfo for other images. The idea
of this patch is start to have a minimal support for
android image format. We still need to print id[] array

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/bootm.c b/cmd/bootm.c
index f5e91f4..16fdea5 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -275,6 +275,12 @@ static int image_info(ulong addr)
 		puts("OK\n");
 		return 0;
 #endif
+#if defined(CONFIG_ANDROID_BOOT_IMAGE)
+	case IMAGE_FORMAT_ANDROID:
+		puts("   Android image found\n");
+		android_print_contents(hdr);
+		return 0;
+#endif
 #if defined(CONFIG_FIT)
 	case IMAGE_FORMAT_FIT:
 		puts("   FIT image found\n");
diff --git a/common/image-android.c b/common/image-android.c
index b6a94b3..ee03b96 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -145,3 +145,32 @@ int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
 	*rd_len = hdr->ramdisk_size;
 	return 0;
 }
+
+#if !defined(CONFIG_SPL_BUILD)
+/**
+ * android_print_contents - prints out the contents of the Android format image
+ * @hdr: pointer to the Android format image header
+ *
+ * android_print_contents() formats a multi line Android image contents
+ * description.
+ * The routine prints out Android image properties
+ *
+ * returns:
+ *     no returned results
+ */
+void android_print_contents(const struct andr_img_hdr *hdr)
+{
+	const char * const p = IMAGE_INDENT_STRING;
+
+	printf("%skernel size:      %x\n", p, hdr->kernel_size);
+	printf("%skernel address:   %x\n", p, hdr->kernel_addr);
+	printf("%sramdisk size:     %x\n", p, hdr->ramdisk_size);
+	printf("%sramdisk addrress: %x\n", p, hdr->ramdisk_addr);
+	printf("%ssecond size:      %x\n", p, hdr->second_size);
+	printf("%ssecond address:   %x\n", p, hdr->second_addr);
+	printf("%stags address:     %x\n", p, hdr->tags_addr);
+	printf("%spage size:        %x\n", p, hdr->page_size);
+	printf("%sname:             %s\n", p, hdr->name);
+	printf("%scmdline:          %s\n", p, hdr->cmdline);
+}
+#endif
diff --git a/include/image.h b/include/image.h
index a8f6bd1..d788c26 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1156,6 +1156,7 @@ int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
 			      ulong *rd_data, ulong *rd_len);
 ulong android_image_get_end(const struct andr_img_hdr *hdr);
 ulong android_image_get_kload(const struct andr_img_hdr *hdr);
+void android_print_contents(const struct andr_img_hdr *hdr);
 
 #endif /* CONFIG_ANDROID_BOOT_IMAGE */
 
-- 
cgit v0.10.2


From 4b3ab59d21efc2bcc76628a54f9c368dee23d5fe Mon Sep 17 00:00:00 2001
From: Carlo Caione <carlo@endlessm.com>
Date: Fri, 10 Jun 2016 20:18:22 +0200
Subject: configs: gxbb: Introduce a common config header file

Introduce a meson-gxbb-common.h header file and derive the
configuration for Hardkernel Odroid-C2 board from that.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>

diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h
new file mode 100644
index 0000000..d1c0050
--- /dev/null
+++ b/include/configs/meson-gxbb-common.h
@@ -0,0 +1,45 @@
+/*
+ * Configuration for Amlogic Meson GXBB SoCs
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MESON_GXBB_COMMON_CONFIG_H
+#define __MESON_GXBB_COMMON_CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
+
+#define CONFIG_CMD_ENV
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#include <config_distro_defaults.h>
+
+#endif /* __MESON_GXBB_COMMON_CONFIG_H */
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index 37a5671..bf5df9c 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -8,44 +8,12 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_CPU_ARMV8
-#define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE	64
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_ENV_IS_NOWHERE		1
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_SYS_MAXARGS		32
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_TEXT_BASE		0x01000000
-#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE			0xc4301000
-#define GICC_BASE			0xc4302000
-
 #define CONFIG_IDENT_STRING		" odroid-c2"
 
 /* Serial setup */
 #define CONFIG_CONS_INDEX		0
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_CMD_ENV
-
-/* Monitor Command Prompt */
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-#include <config_distro_defaults.h>
+#include <configs/meson-gxbb-common.h>
 
 #endif /* __CONFIG_H */
-- 
cgit v0.10.2


From 1e23737df8c3887afd45b3c9842827df168d915b Mon Sep 17 00:00:00 2001
From: Carlo Caione <carlo@endlessm.com>
Date: Fri, 10 Jun 2016 20:18:23 +0200
Subject: board: amlogic: Rename folder for Amlogic boards

s/hardkernel/amlogic/ to have a single place for all the amlogic-based
boards.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 77d3cfe..af3be59 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -26,6 +26,6 @@ config SYS_SOC
 config SYS_MALLOC_F_LEN
 	default 0x1000
 
-source "board/hardkernel/odroid-c2/Kconfig"
+source "board/amlogic/odroid-c2/Kconfig"
 
 endif
diff --git a/board/amlogic/odroid-c2/Kconfig b/board/amlogic/odroid-c2/Kconfig
new file mode 100644
index 0000000..2b16889
--- /dev/null
+++ b/board/amlogic/odroid-c2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_C2
+
+config SYS_BOARD
+	default "odroid-c2"
+
+config SYS_VENDOR
+	default "amlogic"
+
+config SYS_CONFIG_NAME
+	default "odroid-c2"
+
+endif
diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/odroid-c2/MAINTAINERS
new file mode 100644
index 0000000..699850f
--- /dev/null
+++ b/board/amlogic/odroid-c2/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID-C2
+M:	Beniamino Galvani <b.galvani@gmail.com>
+S:	Maintained
+F:	board/amlogic/odroid-c2/
+F:	include/configs/odroid-c2.h
+F:	configs/odroid-c2_defconfig
diff --git a/board/amlogic/odroid-c2/Makefile b/board/amlogic/odroid-c2/Makefile
new file mode 100644
index 0000000..571044b
--- /dev/null
+++ b/board/amlogic/odroid-c2/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= odroid-c2.o
diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README
new file mode 100644
index 0000000..d6d266a
--- /dev/null
+++ b/board/amlogic/odroid-c2/README
@@ -0,0 +1,60 @@
+U-Boot for ODROID-C2
+====================
+
+ODROID-C2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-c2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > DIR=odroid-c2
+ > git clone --depth 1 \
+       https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
+       $DIR
+ > $DIR/fip/fip_create --bl30  $DIR/fip/gxb/bl30.bin \
+                       --bl301 $DIR/fip/gxb/bl301.bin \
+                       --bl31  $DIR/fip/gxb/bl31.bin \
+                       --bl33  u-boot.bin \
+                       $DIR/fip.bin
+ > $DIR/fip/fip_create --dump $DIR/fip.bin
+ > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
+ > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
+                                --input $DIR/boot_new.bin \
+                                --output $DIR/u-boot.img
+ > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > BL1=$DIR/sd_fuse/bl1.bin.hardkernel
+ > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
+ > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
+ > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
new file mode 100644
index 0000000..bd72100
--- /dev/null
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <dm/platdata.h>
+#include <phy.h>
+
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
+int board_init(void)
+{
+	return 0;
+}
+
+static const struct eth_pdata gxbb_eth_pdata = {
+	.iobase = GXBB_ETH_BASE,
+	.phy_interface = PHY_INTERFACE_MODE_RGMII,
+};
+
+U_BOOT_DEVICE(meson_eth) = {
+	.name = "eth_designware",
+	.platdata = &gxbb_eth_pdata,
+};
+
+int misc_init_r(void)
+{
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	ssize_t len;
+
+	/* Select Ethernet function */
+	setbits_le32(GXBB_PINMUX(6), 0x3fff);
+
+	/* Set RGMII mode */
+	setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
+				     GXBB_ETH_REG_0_TX_PHASE(1) |
+				     GXBB_ETH_REG_0_TX_RATIO(4) |
+				     GXBB_ETH_REG_0_PHY_CLK_EN |
+				     GXBB_ETH_REG_0_CLK_EN);
+
+	/* Enable power and clock gate */
+	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+	/* Reset PHY on GPIOZ_14 */
+	clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
+	clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+	mdelay(10);
+	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	return 0;
+}
diff --git a/board/hardkernel/odroid-c2/Kconfig b/board/hardkernel/odroid-c2/Kconfig
deleted file mode 100644
index 687d9c6..0000000
--- a/board/hardkernel/odroid-c2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ODROID_C2
-
-config SYS_BOARD
-	default "odroid-c2"
-
-config SYS_VENDOR
-	default "hardkernel"
-
-config SYS_CONFIG_NAME
-	default "odroid-c2"
-
-endif
diff --git a/board/hardkernel/odroid-c2/MAINTAINERS b/board/hardkernel/odroid-c2/MAINTAINERS
deleted file mode 100644
index 23ae1e7..0000000
--- a/board/hardkernel/odroid-c2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ODROID-C2
-M:	Beniamino Galvani <b.galvani@gmail.com>
-S:	Maintained
-F:	board/hardkernel/odroid-c2/
-F:	include/configs/odroid-c2.h
-F:	configs/odroid-c2_defconfig
diff --git a/board/hardkernel/odroid-c2/Makefile b/board/hardkernel/odroid-c2/Makefile
deleted file mode 100644
index 571044b..0000000
--- a/board/hardkernel/odroid-c2/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= odroid-c2.o
diff --git a/board/hardkernel/odroid-c2/README b/board/hardkernel/odroid-c2/README
deleted file mode 100644
index d6d266a..0000000
--- a/board/hardkernel/odroid-c2/README
+++ /dev/null
@@ -1,60 +0,0 @@
-U-Boot for ODROID-C2
-====================
-
-ODROID-C2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
-
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - Gigabit Ethernet
- - HDMI 2.0 4K/60Hz display
- - 40-pin GPIO header
- - 4 x USB 2.0 Host, 1 x USB OTG
- - eMMC, microSD
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the u-boot port supports the following devices:
- - serial
- - Ethernet
-
-u-boot compilation
-==================
-
- > export ARCH=arm
- > export CROSS_COMPILE=aarch64-none-elf-
- > make odroid-c2_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > DIR=odroid-c2
- > git clone --depth 1 \
-       https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
-       $DIR
- > $DIR/fip/fip_create --bl30  $DIR/fip/gxb/bl30.bin \
-                       --bl301 $DIR/fip/gxb/bl301.bin \
-                       --bl31  $DIR/fip/gxb/bl31.bin \
-                       --bl33  u-boot.bin \
-                       $DIR/fip.bin
- > $DIR/fip/fip_create --dump $DIR/fip.bin
- > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
- > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
-                                --input $DIR/boot_new.bin \
-                                --output $DIR/u-boot.img
- > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > BL1=$DIR/sd_fuse/bl1.bin.hardkernel
- > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
- > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
- > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
deleted file mode 100644
index bd72100..0000000
--- a/board/hardkernel/odroid-c2/odroid-c2.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gxbb.h>
-#include <asm/arch/sm.h>
-#include <dm/platdata.h>
-#include <phy.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-static const struct eth_pdata gxbb_eth_pdata = {
-	.iobase = GXBB_ETH_BASE,
-	.phy_interface = PHY_INTERFACE_MODE_RGMII,
-};
-
-U_BOOT_DEVICE(meson_eth) = {
-	.name = "eth_designware",
-	.platdata = &gxbb_eth_pdata,
-};
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	ssize_t len;
-
-	/* Select Ethernet function */
-	setbits_le32(GXBB_PINMUX(6), 0x3fff);
-
-	/* Set RGMII mode */
-	setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
-				     GXBB_ETH_REG_0_TX_PHASE(1) |
-				     GXBB_ETH_REG_0_TX_RATIO(4) |
-				     GXBB_ETH_REG_0_PHY_CLK_EN |
-				     GXBB_ETH_REG_0_CLK_EN);
-
-	/* Enable power and clock gate */
-	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
-	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
-
-	/* Reset PHY on GPIOZ_14 */
-	clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
-	clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
-	mdelay(10);
-	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
-
-	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-
-	return 0;
-}
-- 
cgit v0.10.2


From 42ffa51fd46bc6fd4bf2c244f00a80df31d01596 Mon Sep 17 00:00:00 2001
From: Vagrant Cascadian <vagrant@debian.org>
Date: Sun, 12 Jun 2016 06:07:07 -0700
Subject: Use C locale when setting CC_VERSION_STRING and LD_VERSION_STRING.

The output reported may be locale-dependent, which results in
unreproducible builds.

  $ LANG=C ld --version | head -n 1
    GNU ld (GNU Binutils for Debian) 2.26

  $ LANG=it_CH.UTF-8 ld --version | head -n 1
    ld di GNU (GNU Binutils for Debian) 2.26

Forcing LC_ALL=C ensures the output is consistant regardless of the
build environment.

Thanks to HW42 for debugging the issue:

  https://lists.alioth.debian.org/pipermail/reproducible-builds/Week-of-Mon-20160606/005722.html

For more information about reproducible builds:

  https://reproducible-builds.org/

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index d0e7a8a..256d4ff 100644
--- a/Makefile
+++ b/Makefile
@@ -1269,8 +1269,8 @@ prepare: prepare0
 define filechk_version.h
 	(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
 	echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
-	echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \
-	echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; )
+	echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
+	echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
 endef
 
 # The SOURCE_DATE_EPOCH mechanism requires a date that behaves like GNU date.
-- 
cgit v0.10.2


From 5847084f6bbd0778afb29f0574085d4210ea8cff Mon Sep 17 00:00:00 2001
From: Vagrant Cascadian <vagrant@debian.org>
Date: Thu, 16 Jun 2016 12:28:40 -0700
Subject: Respect SOURCE_DATE_EPOCH when building FIT images.

Embedding timestamps in FIT images results in unreproducible builds
for targets that generate a fit image, such as dra7xx_evm.

This patch uses the SOURCE_DATE_EPOCH environment variable, when set,
to use specified value for the date.

Thanks to HW42 for debugging the issue and providing the patch:

  https://lists.alioth.debian.org/pipermail/reproducible-builds/Week-of-Mon-20160606/005722.html

For more information about reproducible builds and the
SOURCE_DATE_EPOCH specification:

  https://reproducible-builds.org/specs/source-date-epoch/
  https://reproducible-builds.org/

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/default_image.c b/tools/default_image.c
index 3ed7014..6e4ae14 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -88,7 +88,6 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd,
 				struct image_tool_params *params)
 {
 	uint32_t checksum;
-	char *source_date_epoch;
 	time_t time;
 
 	image_header_t * hdr = (image_header_t *)ptr;
@@ -98,18 +97,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd,
 				sizeof(image_header_t)),
 			sbuf->st_size - sizeof(image_header_t));
 
-	source_date_epoch = getenv("SOURCE_DATE_EPOCH");
-	if (source_date_epoch != NULL) {
-		time = (time_t) strtol(source_date_epoch, NULL, 10);
-
-		if (gmtime(&time) == NULL) {
-			fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
-				__func__);
-			time = 0;
-		}
-	} else {
-		time = sbuf->st_mtime;
-	}
+	time = imagetool_get_source_date(params, sbuf->st_mtime);
 
 	/* Build new header */
 	image_set_magic(hdr, IH_MAGIC);
diff --git a/tools/fit_image.c b/tools/fit_image.c
index 76a6de4..58aa8e2 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -51,8 +51,10 @@ static int fit_add_file_data(struct image_tool_params *params, size_t size_inc,
 	}
 
 	/* for first image creation, add a timestamp at offset 0 i.e., root  */
-	if (params->datafile)
-		ret = fit_set_timestamp(ptr, 0, sbuf.st_mtime);
+	if (params->datafile) {
+		time_t time = imagetool_get_source_date(params, sbuf.st_mtime);
+		ret = fit_set_timestamp(ptr, 0, time);
+	}
 
 	if (!ret) {
 		ret = fit_add_verification_data(params->keydir, dest_blob, ptr,
diff --git a/tools/imagetool.c b/tools/imagetool.c
index 08d191d..855a096 100644
--- a/tools/imagetool.c
+++ b/tools/imagetool.c
@@ -115,3 +115,23 @@ int imagetool_get_filesize(struct image_tool_params *params, const char *fname)
 
 	return sbuf.st_size;
 }
+
+time_t imagetool_get_source_date(
+	 struct image_tool_params *params,
+	 time_t fallback)
+{
+	char *source_date_epoch = getenv("SOURCE_DATE_EPOCH");
+
+	if (source_date_epoch == NULL)
+		return fallback;
+
+	time_t time = (time_t) strtol(source_date_epoch, NULL, 10);
+
+	if (gmtime(&time) == NULL) {
+		fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
+			params->cmdname);
+		time = 0;
+	}
+
+	return time;
+}
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 1f2161c..6c1a9d3 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -206,6 +206,22 @@ int imagetool_save_subimage(
  */
 int imagetool_get_filesize(struct image_tool_params *params, const char *fname);
 
+/**
+ * imagetool_get_source_date() - Get timestamp for build output.
+ *
+ * Gets a timestamp for embedding it in a build output. If set
+ * SOURCE_DATE_EPOCH is used. Else the given fallback value is returned. Prints
+ * an error message if SOURCE_DATE_EPOCH contains an invalid value and returns
+ * 0.
+ *
+ * @params:	mkimage parameters
+ * @fallback:	timestamp to use if SOURCE_DATE_EPOCH isn't set
+ * @return timestamp based on SOURCE_DATE_EPOCH
+ */
+time_t imagetool_get_source_date(
+	struct image_tool_params *params,
+	time_t fallback);
+
 /*
  * There is a c file associated with supported image type low level code
  * for ex. default_image.c, fit_image.c
-- 
cgit v0.10.2


From 96044745cb8c086d47215f4aa7b4defb1d1fec57 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 14:24:07 +0900
Subject: env: avoid build error for boards without CONFIG_SYS_{CPU, BOARD}

If CONFIG_ENV_VARS_UBOOT_CONFIG is enabled (it is by distro), this
code causes build error for boards without CONFIG_SYS_{CPU,_BOARD}.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/env_default.h b/include/env_default.h
index 3096576..ea6704a 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -90,9 +90,13 @@ const uchar default_environment[] = {
 #endif
 #ifdef	CONFIG_ENV_VARS_UBOOT_CONFIG
 	"arch="		CONFIG_SYS_ARCH			"\0"
+#ifdef CONFIG_SYS_CPU
 	"cpu="		CONFIG_SYS_CPU			"\0"
+#endif
+#ifdef CONFIG_SYS_BOARD
 	"board="	CONFIG_SYS_BOARD		"\0"
 	"board_name="	CONFIG_SYS_BOARD		"\0"
+#endif
 #ifdef CONFIG_SYS_VENDOR
 	"vendor="	CONFIG_SYS_VENDOR		"\0"
 #endif
-- 
cgit v0.10.2


From a2cfc8d5935efd445d9f9b258383e2a42f83ef6e Mon Sep 17 00:00:00 2001
From: Joris Lijssens <joris.lijssens@gmail.com>
Date: Fri, 17 Jun 2016 10:46:58 +0200
Subject: lib/lzo: bugfix when input data is not compressed

When the input data is not compressed at all,
lzo1x_decompress_safe will fail, so call memcpy()
instead.

Signed-off-by: Joris Lijssens <joris.lijssens@gmail.com>

diff --git a/lib/lzo/lzo1x_decompress.c b/lib/lzo/lzo1x_decompress.c
index ebdf10b..ccc90b8 100644
--- a/lib/lzo/lzo1x_decompress.c
+++ b/lib/lzo/lzo1x_decompress.c
@@ -98,18 +98,25 @@ int lzop_decompress(const unsigned char *src, size_t src_len,
 		if (dlen > remaining)
 			return LZO_E_OUTPUT_OVERRUN;
 
-		/* decompress */
-		tmp = dlen;
-		r = lzo1x_decompress_safe((u8 *) src, slen, dst, &tmp);
+		/* When the input data is not compressed at all,
+		 * lzo1x_decompress_safe will fail, so call memcpy()
+		 * instead */
+		if (dlen == slen) {
+			memcpy(dst, src, slen);
+		} else {
+			/* decompress */
+			tmp = dlen;
+			r = lzo1x_decompress_safe((u8 *)src, slen, dst, &tmp);
+
+			if (r != LZO_E_OK) {
+				*dst_len = dst - start;
+				return r;
+			}
 
-		if (r != LZO_E_OK) {
-			*dst_len = dst - start;
-			return r;
+			if (dlen != tmp)
+				return LZO_E_ERROR;
 		}
 
-		if (dlen != tmp)
-			return LZO_E_ERROR;
-
 		src += slen;
 		dst += dlen;
 		remaining -= dlen;
-- 
cgit v0.10.2


From afedf5488de99925f00ead847e40d7ba0d508f0e Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 18:32:47 +0900
Subject: arm64: optimize smp_kick_all_cpus

gic_kick_secondary_cpus can directly return to the caller of
smp_kick_all_cpus.  We do not have to use x29 register here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index c1a2f45..670e323 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -258,12 +258,10 @@ ENDPROC(lowlevel_init)
 
 WEAK(smp_kick_all_cpus)
 	/* Kick secondary cpus up by SGI 0 interrupt */
-	mov	x29, lr			/* Save LR */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	ldr	x0, =GICD_BASE
-	bl	gic_kick_secondary_cpus
+	b	gic_kick_secondary_cpus
 #endif
-	mov	lr, x29			/* Restore LR */
 	ret
 ENDPROC(smp_kick_all_cpus)
 
-- 
cgit v0.10.2


From 6441e3deb429f218c05e6a71fbbb89e7519e2e52 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 17 Jun 2016 21:51:48 +0900
Subject: ARM: move #ifdef to match the error handling code

Match the #ifdef ... #endif and the code,

   ret = do_something();
   if (ret)
           return ret;

This will make it easier to add more #ifdef'ed code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 7677358..76b75d8 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -42,11 +42,14 @@ int arch_fixup_fdt(void *blob)
 	}
 
 	ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-#ifdef CONFIG_ARMV7_NONSEC
 	if (ret)
 		return ret;
 
+#ifdef CONFIG_ARMV7_NONSEC
 	ret = psci_update_dt(blob);
+	if (ret)
+		return ret;
 #endif
-	return ret;
+
+	return 0;
 }
-- 
cgit v0.10.2


From 62f8183f6adee9df47d6d3c02bf19809117dcbad Mon Sep 17 00:00:00 2001
From: Andre Renaud <andre@designa-electronics.com>
Date: Sun, 19 Jun 2016 19:25:25 -0600
Subject: mtd: nand: Drop a blank line in nand_wait()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This empty line should not be there. Remove it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 74c563c..6897167 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -862,7 +862,6 @@ static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  */
 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
-
 	int status;
 	unsigned long timeo = 400;
 
-- 
cgit v0.10.2


From b88d6f761445df5fd9d2dfe8eb5e32891a3843f0 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 21 Jun 2016 02:11:18 +0900
Subject: Move CONFIG_SYS_HUSH_PARSER to Kconfig for last 4 boards

I still see some defines of this config in board headers.  Move them
to defconfigs (+ renaming to CONFIG_HUSH_PARSER) to complete this
migration.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
index 80f0013..d74757c 100644
--- a/configs/gurnard_defconfig
+++ b/configs/gurnard_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
 CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 483d490..808bbc2 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MESON=y
 CONFIG_MESON_GXBB=y
 CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
index 847de63..dfedf82 100644
--- a/configs/s32v234evb_defconfig
+++ b/configs/s32v234evb_defconfig
@@ -2,5 +2,6 @@ CONFIG_ARM=y
 CONFIG_TARGET_S32V234EVB=y
 CONFIG_SYS_MALLOC_F=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index a69c0b6..ed6239b 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -7,6 +7,7 @@ CONFIG_ARCH_ATH79=y
 CONFIG_BOARD_TPLINK_WDR4300=y
 CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
 CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h
index d1c0050..eaf6a9c 100644
--- a/include/configs/meson-gxbb-common.h
+++ b/include/configs/meson-gxbb-common.h
@@ -35,7 +35,6 @@
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
index 9723bab..13eac75 100644
--- a/include/configs/s32v234evb.h
+++ b/include/configs/s32v234evb.h
@@ -190,7 +190,6 @@
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"=> "
 #undef CONFIG_AUTO_COMPLETE
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index ddfbcec..8344f15 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -136,7 +136,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
 /* U-Boot memory settings */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 74a9a09..b2ccb70 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -60,7 +60,6 @@
 #define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
 #define CONFIG_AUTO_COMPLETE			/* Command auto complete */
 #define CONFIG_CMDLINE_EDITING			/* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /* USB, USB storage, USB ethernet */
-- 
cgit v0.10.2


From f1f9d4fac5274d9b5ae1b0087fb0fcfa00687bac Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 21 Jun 2016 02:11:19 +0900
Subject: hush: complete renaming CONFIG_SYS_HUSH_PARSER to CONFIG_HUSH_PARSER

There is no more define of CONFIG_SYS_HUSH_PARSER.  Rename some
remaining references and drop the backward compatible Kconfig entry.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c
index c8b1013..3d7438e 100644
--- a/board/work-microwave/work_92105/work_92105_display.c
+++ b/board/work-microwave/work_92105/work_92105_display.c
@@ -311,8 +311,8 @@ U_BOOT_CMD(
  * only HUSH can understand them.
  */
 
-#if !defined(CONFIG_SYS_HUSH_PARSER)
-#error CONFIG_CMD_HD44760 requires CONFIG_SYS_HUSH_PARSER
+#if !defined(CONFIG_HUSH_PARSER)
+#error CONFIG_CMD_HD44760 requires CONFIG_HUSH_PARSER
 #endif
 
 static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 42e0e39..d69b817 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -13,7 +13,6 @@ config CMDLINE
 
 config HUSH_PARSER
 	bool "Use hush shell"
-	select SYS_HUSH_PARSER
 	depends on CMDLINE
 	help
 	  This option enables the "hush" shell (from Busybox) as command line
@@ -24,11 +23,6 @@ config HUSH_PARSER
 	  If disabled, you get the old, much simpler behaviour with a somewhat
 	  smaller memory footprint.
 
-config SYS_HUSH_PARSER
-	bool
-	help
-	  Backward compatibility.
-
 config SYS_PROMPT
 	string "Shell prompt"
 	default "=> "
diff --git a/cmd/Makefile b/cmd/Makefile
index 9ce7861..a1731be 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -49,7 +49,7 @@ obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
 obj-$(CONFIG_CMD_EEPROM) += eeprom.o
 obj-$(CONFIG_EFI_STUB) += efi.o
 obj-$(CONFIG_CMD_ELF) += elf.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += exit.o
+obj-$(CONFIG_HUSH_PARSER) += exit.o
 obj-$(CONFIG_CMD_EXT4) += ext4.o
 obj-$(CONFIG_CMD_EXT2) += ext2.o
 obj-$(CONFIG_CMD_FAT) += fat.o
@@ -123,7 +123,7 @@ obj-$(CONFIG_CMD_STRINGS) += strings.o
 obj-$(CONFIG_CMD_TERMINAL) += terminal.o
 obj-$(CONFIG_CMD_TIME) += time.o
 obj-$(CONFIG_CMD_TRACE) += trace.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += test.o
+obj-$(CONFIG_HUSH_PARSER) += test.o
 obj-$(CONFIG_CMD_TPM) += tpm.o
 obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
 obj-$(CONFIG_CMD_TSI148) += tsi148.o
diff --git a/common/Makefile b/common/Makefile
index 34cb898..e08cd3e 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -11,10 +11,7 @@ obj-y += init/
 obj-y += main.o
 obj-y += exports.o
 obj-y += hash.o
-ifdef CONFIG_SYS_HUSH_PARSER
-obj-y += cli_hush.o
-endif
-
+obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
 obj-$(CONFIG_AUTOBOOT) += autoboot.o
 
 # This option is not just y/n - it can have a numeric value
diff --git a/common/cli.c b/common/cli.c
index 18d7e19..a433ef2 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int run_command(const char *cmd, int flag)
 {
-#ifndef CONFIG_SYS_HUSH_PARSER
+#ifndef CONFIG_HUSH_PARSER
 	/*
 	 * cli_run_command can return 0 or 1 for success, so clean up
 	 * its result.
@@ -55,7 +55,7 @@ int run_command(const char *cmd, int flag)
  */
 int run_command_repeatable(const char *cmd, int flag)
 {
-#ifndef CONFIG_SYS_HUSH_PARSER
+#ifndef CONFIG_HUSH_PARSER
 	return cli_simple_run_command(cmd, flag);
 #else
 	/*
@@ -79,7 +79,7 @@ int run_command_list(const char *cmd, int len, int flag)
 
 	if (len == -1) {
 		len = strlen(cmd);
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
 		/* hush will never change our string */
 		need_buff = 0;
 #else
@@ -94,7 +94,7 @@ int run_command_list(const char *cmd, int len, int flag)
 		memcpy(buff, cmd, len);
 		buff[len] = '\0';
 	}
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
 	rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
 #else
 	/*
@@ -214,7 +214,7 @@ err:
 
 void cli_loop(void)
 {
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
 	parse_file_outer();
 	/* This point is never reached */
 	for (;;);
@@ -222,12 +222,12 @@ void cli_loop(void)
 	cli_simple_loop();
 #else
 	printf("## U-Boot command line is disabled. Please enable CONFIG_CMDLINE\n");
-#endif /*CONFIG_SYS_HUSH_PARSER*/
+#endif /*CONFIG_HUSH_PARSER*/
 }
 
 void cli_init(void)
 {
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
 	u_boot_hush_start();
 #endif
 
diff --git a/test/command_ut.c b/test/command_ut.c
index 54bf62b..21283eb 100644
--- a/test/command_ut.c
+++ b/test/command_ut.c
@@ -43,7 +43,7 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	assert(run_command_list("false", -1, 0) == 1);
 	assert(run_command_list("echo", -1, 0) == 0);
 
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
 	run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
 	run_command("run foo", 0);
 	assert(getenv("black") != NULL);
-- 
cgit v0.10.2


From ec048369e2d68d60fdb4e0e6b5def08fff0a0be4 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 21 Jun 2016 21:30:09 +0900
Subject: ARM: armv7: refactor Makefile slightly

Use Kbuild standard style where possible.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0a5ac97..ddd8d12 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -18,15 +18,8 @@ obj-y	+= lowlevel_init.o
 endif
 endif
 
-ifneq ($(CONFIG_ARMV7_NONSEC),)
-obj-y	+= nonsec_virt.o
-obj-y	+= virt-v7.o
-obj-y	+= virt-dt.o
-endif
-
-ifneq ($(CONFIG_ARMV7_PSCI),)
-obj-y	+= psci.o
-endif
+obj-$(CONFIG_ARMV7_NONSEC)	+= nonsec_virt.o virt-v7.o virt-dt.o
+obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
 
 obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
-- 
cgit v0.10.2


From bd62e2419b9528292882e3b0008c507db6ae20a8 Mon Sep 17 00:00:00 2001
From: Andrej Rosano <andrej@inversepath.com>
Date: Tue, 21 Jun 2016 17:54:25 +0200
Subject: common: Fix support for environment file in EXT4

Signed-off-by: Andrej Rosano <andrej@inversepath.com>

diff --git a/common/env_ext4.c b/common/env_ext4.c
index ce748ed..adefa7d 100644
--- a/common/env_ext4.c
+++ b/common/env_ext4.c
@@ -25,6 +25,7 @@
 #include <environment.h>
 #include <linux/stddef.h>
 #include <malloc.h>
+#include <memalign.h>
 #include <search.h>
 #include <errno.h>
 #include <ext4fs.h>
@@ -49,7 +50,7 @@ int env_init(void)
 int saveenv(void)
 {
 	env_t	env_new;
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	disk_partition_t info;
 	int dev, part;
 	int err;
@@ -58,13 +59,13 @@ int saveenv(void)
 	if (err)
 		return err;
 
-	part = get_device_and_partition(EXT4_ENV_INTERFACE,
+	part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
 					EXT4_ENV_DEVICE_AND_PART,
 					&dev_desc, &info, 1);
 	if (part < 0)
 		return 1;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	ext4fs_set_blk_dev(dev_desc, &info);
 
 	if (!ext4fs_mount(info.size)) {
@@ -90,18 +91,19 @@ int saveenv(void)
 void env_relocate_spec(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
-	block_dev_desc_t *dev_desc = NULL;
+	struct blk_desc *dev_desc = NULL;
 	disk_partition_t info;
 	int dev, part;
 	int err;
+	loff_t off;
 
-	part = get_device_and_partition(EXT4_ENV_INTERFACE,
+	part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
 					EXT4_ENV_DEVICE_AND_PART,
 					&dev_desc, &info, 1);
 	if (part < 0)
 		goto err_env_relocate;
 
-	dev = dev_desc->dev;
+	dev = dev_desc->devnum;
 	ext4fs_set_blk_dev(dev_desc, &info);
 
 	if (!ext4fs_mount(info.size)) {
@@ -110,7 +112,7 @@ void env_relocate_spec(void)
 		goto err_env_relocate;
 	}
 
-	err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE);
+	err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE, &off);
 	ext4fs_close();
 
 	if (err == -1) {
-- 
cgit v0.10.2


From df8b0a037394246fd591b7fac4de4541810ab1e8 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 21 Jun 2016 13:32:07 -0600
Subject: clk: sandbox: don't check clk ID against 0

clk->id is unsigned, so it can't be < 0. Remove the check for that.

FWIW, this issue was introduced when the clock API converted e.g.
clk_get_rate()'s clock ID parameter from an int to an unsigned long
(with a struct clk), without removing this check.

Fixes: 135aa9500264 ("clk: convert API to match reset/mailbox style")
Reported-by: Coverity Scan
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index c6bd7c6..ef58503 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -19,7 +19,7 @@ static ulong sandbox_clk_get_rate(struct clk *clk)
 {
 	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+	if (clk->id >= SANDBOX_CLK_ID_COUNT)
 		return -EINVAL;
 
 	return priv->rate[clk->id];
@@ -30,7 +30,7 @@ static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)
 	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong old_rate;
 
-	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+	if (clk->id >= SANDBOX_CLK_ID_COUNT)
 		return -EINVAL;
 
 	if (!rate)
@@ -46,7 +46,7 @@ static int sandbox_clk_enable(struct clk *clk)
 {
 	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+	if (clk->id >= SANDBOX_CLK_ID_COUNT)
 		return -EINVAL;
 
 	priv->enabled[clk->id] = true;
@@ -58,7 +58,7 @@ static int sandbox_clk_disable(struct clk *clk)
 {
 	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+	if (clk->id >= SANDBOX_CLK_ID_COUNT)
 		return -EINVAL;
 
 	priv->enabled[clk->id] = false;
-- 
cgit v0.10.2


From 202b84ae59d1bc356813b81b9611dcb8af610d97 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 21 Jun 2016 16:43:04 -0700
Subject: arm: bcm235xx: choose 8-bit phy bus width

The Kona PHY supports an 8-bit wide UTMI interface,
therefore, choose this Kconfig setting.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
index 3328e51..cd47cd0 100644
--- a/configs/bcm23550_w1d_defconfig
+++ b/configs/bcm23550_w1d_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
 CONFIG_G_DNL_VENDOR_NUM=0x18d1
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
index bd3c711..8d041ed 100644
--- a/include/configs/bcm23550_w1d.h
+++ b/include/configs/bcm23550_w1d.h
@@ -137,7 +137,6 @@
 #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
 #undef CONFIG_USB_GADGET_VBUS_DRAW
 #define CONFIG_USB_GADGET_VBUS_DRAW	0
-#define CONFIG_USB_GADGET_DWC2_PHY_8_BIT
 #define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
 #define CONFIG_USBID_ADDR		0x34052c46
 
-- 
cgit v0.10.2


From 9d7f416cedb5e9d7a809952e9483e05de5d30eda Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 21 Jun 2016 16:43:05 -0700
Subject: arm: bcm235xx: implement the boot0 hook code

Choose the Kconfig boot0 hook option and implement the required code.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h
new file mode 100644
index 0000000..7e72882
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2016 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.word	0xbabeface;	\
+	.word	_end - _start
+
+#endif /* __BOOT0_H */
diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig
index cd47cd0..0ef4a37 100644
--- a/configs/bcm23550_w1d_defconfig
+++ b/configs/bcm23550_w1d_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM23550_W1D=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
-- 
cgit v0.10.2


From 77a1a677a6db02377921cda1a146d18efb1f31ec Mon Sep 17 00:00:00 2001
From: Chris Brand <chris.brand@broadcom.com>
Date: Tue, 21 Jun 2016 16:43:06 -0700
Subject: arm: bcm235xx: fix kps ccu

The Kona Peripheral Slave CCU has 4 policy mask registers, not 8.

Signed-off-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
index ce3d019..80187e3 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
@@ -292,7 +292,7 @@ static struct ccu_clock kps_ccu_clk = {
 		.ops = &ccu_clk_ops,
 		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
 	},
-	.num_policy_masks = 2,
+	.num_policy_masks = 1,
 	.policy_freq_offset = 0x00000008,
 	.freq_bit_shift = 8,
 	.policy_ctl_offset = 0x0000000c,
@@ -300,10 +300,6 @@ static struct ccu_clock kps_ccu_clk = {
 	.policy1_mask_offset = 0x00000014,
 	.policy2_mask_offset = 0x00000018,
 	.policy3_mask_offset = 0x0000001c,
-	.policy0_mask2_offset = 0x00000048,
-	.policy1_mask2_offset = 0x0000004c,
-	.policy2_mask2_offset = 0x00000050,
-	.policy3_mask2_offset = 0x00000054,
 	.lvm_en_offset = 0x00000034,
 	.freq_id = 2,
 	.freq_tbl = slave_axi_freq_tbl,
-- 
cgit v0.10.2


From 8ada4e0ee652d2108c640a4daaf63865ad8dedb1 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 21 Jun 2016 16:43:07 -0700
Subject: arm: bcm235xx: update clock framework

The handling of the "usage counter" is incorrect, and the clock should
only be disabled when transitioning from 1 to 0.

Reported-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
index 2b5da6b..a326dfe 100644
--- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c
+++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c
@@ -449,10 +449,9 @@ int clk_enable(struct clk *c)
 	if (ret)
 		return ret;
 
-	if (!c->use_cnt) {
-		c->use_cnt++;
+	if (!c->use_cnt)
 		ret = c->ops->enable(c, 1);
-	}
+	c->use_cnt++;
 
 	return ret;
 }
@@ -464,9 +463,10 @@ void clk_disable(struct clk *c)
 	if (!c->ops || !c->ops->enable)
 		return;
 
-	if (c->use_cnt) {
+	if (c->use_cnt > 0) {
 		c->use_cnt--;
-		c->ops->enable(c, 0);
+		if (c->use_cnt == 0)
+			c->ops->enable(c, 0);
 	}
 
 	/* disable parent */
-- 
cgit v0.10.2


From 2290fe06421720d1c54523a9acf1052181bc6e87 Mon Sep 17 00:00:00 2001
From: Hannes Schmelzer <oe5hpm@oevsv.at>
Date: Wed, 22 Jun 2016 12:36:13 +0200
Subject: board/BuR: rename tseries board to brppt1

Rename B&R tseries board to brppt1

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e9d2fc9..3c2c755 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -309,8 +309,8 @@ config TARGET_KWB
 	select CPU_V7
 	select SUPPORT_SPL
 
-config TARGET_TSERIES
-	bool "Support tseries"
+config TARGET_BRPPT1
+	bool "Support BRPPT1"
 	select CPU_V7
 	select SUPPORT_SPL
 
@@ -909,7 +909,7 @@ source "arch/arm/imx-common/Kconfig"
 
 source "board/bosch/shc/Kconfig"
 source "board/BuR/kwb/Kconfig"
-source "board/BuR/tseries/Kconfig"
+source "board/BuR/brppt1/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
diff --git a/board/BuR/brppt1/Kconfig b/board/BuR/brppt1/Kconfig
new file mode 100644
index 0000000..e006c80
--- /dev/null
+++ b/board/BuR/brppt1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BRPPT1
+
+config SYS_BOARD
+	default "brppt1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brppt1"
+
+endif
diff --git a/board/BuR/brppt1/MAINTAINERS b/board/BuR/brppt1/MAINTAINERS
new file mode 100644
index 0000000..9eddab4
--- /dev/null
+++ b/board/BuR/brppt1/MAINTAINERS
@@ -0,0 +1,8 @@
+BRPPT1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brppt1/
+F:	include/configs/brppt1.h
+F:	configs/brppt1_mmc_defconfig
+F:	configs/brppt1_nand_defconfig
+F:	configs/brppt1_spi_defconfig
diff --git a/board/BuR/brppt1/Makefile b/board/BuR/brppt1/Makefile
new file mode 100644
index 0000000..43945d2
--- /dev/null
+++ b/board/BuR/brppt1/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y	:= mux.o
+endif
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
new file mode 100644
index 0000000..a227221
--- /dev/null
+++ b/board/BuR/brppt1/board.c
@@ -0,0 +1,174 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R BRPPT1
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include <lcd.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define	REPSWITCH	(0+20)	/* GPIO0_20 */
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * called from spl_nand.c
+ * return 0 for loading linux, return 1 for loading u-boot
+ */
+int spl_start_uboot(void)
+{
+	if (0 == gpio_get_value(REPSWITCH)) {
+		mdelay(1000);
+		printf("SPL: entering u-boot instead kernel image.\n");
+		return 1;
+	}
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define OSC	(V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
+	struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+	/*
+	 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
+	 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
+	 * the source of timer6 clk to CLK_M_OSC
+	 */
+	writel(0x01, &cmdpll->clktimer6clk);
+
+	/* enable additional clocks of modules which are accessed later */
+	u32 *const clk_domains[] = {
+		&cmper->lcdcclkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_tsspecific[] = {
+		&cmper->lcdclkctrl,
+		&cmper->timer5clkctrl,
+		&cmper->timer6clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
+
+	/* setup LCD-Pixel Clock */
+	writel(0x2, &cmdpll->clklcdcpixelclk);	/* clock comes from perPLL M2 */
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+	i2c_set_bus_num(0);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	pmicsetup(0);
+
+	gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */
+	gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup.  Pinmux has been handled already. */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_NAND
+	gpmc_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	if (0 == gpio_get_value(REPSWITCH)) {
+		lcd_position_cursor(1, 8);
+		lcd_puts(
+		"switching to network-console ...       ");
+		setenv("bootcmd", "run netconsole");
+	}
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c
new file mode 100644
index 0000000..ab3788f
--- /dev/null
+++ b/board/BuR/brppt1/mux.c
@@ -0,0 +1,254 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R BRPPT1 Board(s)
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_RTS */
+	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+static struct module_pin_mux uart1_pin_mux[] = {
+	/* UART1_RTS as I2C2-SCL */
+	{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_CTS as I2C2-SDA */
+	{OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_RXD */
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART1_TXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+	{-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI0_SCLK */
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_D0 */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
+	/* SPI0_D1 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	/* SPI0_CS0 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
+	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
+	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
+	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
+	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
+	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
+	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
+	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
+	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
+	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
+	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
+	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
+	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+	{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
+						/*
+						 * MII2_CRS is shared with
+						 * NAND_WAIT0
+						 */
+	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+	{-1},
+};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
+	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3 */
+	{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_28 (MMC0_DAT1)	 - MII_nNAND */
+	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
+	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO2_0  (GPMC_nCS3) - DCOK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/*
+	 * GPIO0_7 (PWW0 OUT)
+	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+	 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
+	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+#ifndef CONFIG_NAND
+	/* GPIO2_3 - NAND_OE */
+	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+	/* GPIO2_4 - NAND_WEN */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+	/* GPIO2_5 - NAND_BE_CLE */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
+#endif
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+	configure_module_pin_mux(mmc1_pin_mux);
+#endif
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+	configure_module_pin_mux(gpIOs);
+}
diff --git a/board/BuR/tseries/Kconfig b/board/BuR/tseries/Kconfig
deleted file mode 100644
index ed48300..0000000
--- a/board/BuR/tseries/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TSERIES
-
-config SYS_BOARD
-	default "tseries"
-
-config SYS_VENDOR
-	default "BuR"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "tseries"
-
-endif
diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS
deleted file mode 100644
index e2e67e6..0000000
--- a/board/BuR/tseries/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-TSERIES BOARD
-M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
-S:	Maintained
-F:	board/BuR/tseries/
-F:	include/configs/tseries.h
-F:	configs/tseries_mmc_defconfig
-F:	configs/tseries_nand_defconfig
-F:	configs/tseries_spi_defconfig
diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile
deleted file mode 100644
index 43945d2..0000000
--- a/board/BuR/tseries/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
-# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CONFIG_SPL_BUILD),y)
-obj-y	:= mux.o
-endif
-obj-y	+= ../common/common.o
-obj-y	+= board.o
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
deleted file mode 100644
index bc119e6..0000000
--- a/board/BuR/tseries/board.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * board.c
- *
- * Board functions for B&R LEIT Board
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <power/tps65217.h>
-#include "../common/bur_common.h"
-#include <lcd.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* --------------------------------------------------------------------------*/
-/* -- defines for GPIO -- */
-#define	REPSWITCH	(0+20)	/* GPIO0_20 */
-
-#if defined(CONFIG_SPL_BUILD)
-/* TODO: check ram-timing ! */
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
-	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
-	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
-	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = MT41K256M16HA125E_RATIO,
-	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41K256M16HA125E_RATIO,
-	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41K256M16HA125E_RATIO,
-	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
-	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
-	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
-	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
-	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
-	.zq_config = MT41K256M16HA125E_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-static const struct ctrl_ioregs ddr3_ioregs = {
-	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * called from spl_nand.c
- * return 0 for loading linux, return 1 for loading u-boot
- */
-int spl_start_uboot(void)
-{
-	if (0 == gpio_get_value(REPSWITCH)) {
-		mdelay(1000);
-		printf("SPL: entering u-boot instead kernel image.\n");
-		return 1;
-	}
-	return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
-
-#define OSC	(V_OSCK/1000000)
-static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
-	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
-	/*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
-	struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
-
-	/*
-	 * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
-	 * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
-	 * the source of timer6 clk to CLK_M_OSC
-	 */
-	writel(0x01, &cmdpll->clktimer6clk);
-
-	/* enable additional clocks of modules which are accessed later */
-	u32 *const clk_domains[] = {
-		&cmper->lcdcclkstctrl,
-		0
-	};
-
-	u32 *const clk_modules_tsspecific[] = {
-		&cmper->lcdclkctrl,
-		&cmper->timer5clkctrl,
-		&cmper->timer6clkctrl,
-		0
-	};
-	do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
-
-	/* setup LCD-Pixel Clock */
-	writel(0x2, &cmdpll->clklcdcpixelclk);	/* clock comes from perPLL M2 */
-
-	/* setup I2C */
-	enable_i2c_pin_mux();
-	i2c_set_bus_num(0);
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	pmicsetup(0);
-
-	gpio_direction_output(64+29, 1); /* switch NAND_RnB to GPMC_WAIT1 */
-	gpio_direction_output(64+28, 1); /* switch MII2_CRS to GPMC_WAIT0 */
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr3;
-}
-
-void sdram_init(void)
-{
-	config_ddr(400, &ddr3_ioregs,
-		   &ddr3_data,
-		   &ddr3_cmd_ctrl_data,
-		   &ddr3_emif_reg_data, 0);
-}
-#endif /* CONFIG_SPL_BUILD */
-
-/* Basic board specific setup.  Pinmux has been handled already. */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
-	hw_watchdog_init();
-#endif
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#ifdef CONFIG_NAND
-	gpmc_init();
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	if (0 == gpio_get_value(REPSWITCH)) {
-		lcd_position_cursor(1, 8);
-		lcd_puts(
-		"switching to network-console ...       ");
-		setenv("bootcmd", "run netconsole");
-	}
-	return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
deleted file mode 100644
index 349788a..0000000
--- a/board/BuR/tseries/mux.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * mux.c
- *
- * Pinmux Setting for B&R LEIT Board(s)
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	/* UART0_RTS */
-	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
-	/* UART0_CTS */
-	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART0_RXD */
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART0_TXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
-	{-1},
-};
-static struct module_pin_mux uart1_pin_mux[] = {
-	/* UART1_RTS as I2C2-SCL */
-	{OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART1_CTS as I2C2-SDA */
-	{OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART1_RXD */
-	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART1_TXD */
-	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
-	{-1},
-};
-#ifdef CONFIG_MMC
-static struct module_pin_mux mmc1_pin_mux[] = {
-	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
-	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
-	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
-	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
-
-	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
-	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
-	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
-	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
-	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
-	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
-	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
-	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
-	{-1},
-};
-#endif
-static struct module_pin_mux i2c0_pin_mux[] = {
-	/* I2C_DATA */
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	/* I2C_SCLK */
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	{-1},
-};
-
-static struct module_pin_mux spi0_pin_mux[] = {
-	/* SPI0_SCLK */
-	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
-	/* SPI0_D0 */
-	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
-	/* SPI0_D1 */
-	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
-	/* SPI0_CS0 */
-	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
-	{-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
-	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
-	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
-	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
-	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
-	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
-	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
-	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
-	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
-	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
-	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
-	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
-	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
-	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
-	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
-	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-static struct module_pin_mux mii2_pin_mux[] = {
-	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
-	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
-	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
-	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
-	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
-	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
-	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
-	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
-	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
-	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
-	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
-	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
-	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
-	{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
-						/*
-						 * MII2_CRS is shared with
-						 * NAND_WAIT0
-						 */
-	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
-	{-1},
-};
-#ifdef CONFIG_NAND
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-#endif
-static struct module_pin_mux gpIOs[] = {
-	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
-	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
-	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
-	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3 */
-	{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
-	/* GPIO2_28 (MMC0_DAT1)	 - MII_nNAND */
-	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
-	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
-	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
-	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
-	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
-	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
-	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
-	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
-	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
-	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* GPIO2_0  (GPMC_nCS3) - DCOK */
-	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
-	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
-	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
-	/*
-	 * GPIO0_7 (PWW0 OUT)
-	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
-	 */
-	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
-	/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
-	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
-	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
-	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
-	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
-	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
-	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
-	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
-	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
-	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
-	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
-#ifndef CONFIG_NAND
-	/* GPIO2_3 - NAND_OE */
-	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-	/* GPIO2_4 - NAND_WEN */
-	{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-	/* GPIO2_5 - NAND_BE_CLE */
-	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
-#endif
-	{-1},
-};
-
-static struct module_pin_mux lcd_pin_mux[] = {
-	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
-	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
-	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
-	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
-	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
-	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
-	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
-	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
-	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
-	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
-	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
-	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
-	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
-	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
-	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
-	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
-
-	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
-	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
-	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
-	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
-	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
-	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
-	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
-	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
-
-	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
-	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
-	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
-	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
-
-	{-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-	configure_module_pin_mux(mii1_pin_mux);
-	configure_module_pin_mux(mii2_pin_mux);
-#ifdef CONFIG_NAND
-	configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_MMC)
-	configure_module_pin_mux(mmc1_pin_mux);
-#endif
-	configure_module_pin_mux(spi0_pin_mux);
-	configure_module_pin_mux(lcd_pin_mux);
-	configure_module_pin_mux(uart1_pin_mux);
-	configure_module_pin_mux(gpIOs);
-}
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
new file mode 100644
index 0000000..f8d9de5
--- /dev/null
+++ b/configs/brppt1_mmc_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BRPPT1=y
+CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NETCONSOLE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
new file mode 100644
index 0000000..85ddbe7
--- /dev/null
+++ b/configs/brppt1_nand_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BRPPT1=y
+CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NETCONSOLE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
new file mode 100644
index 0000000..37b8bc9
--- /dev/null
+++ b/configs/brppt1_spi_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BRPPT1=y
+CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NETCONSOLE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig
deleted file mode 100644
index 337404b..0000000
--- a/configs/tseries_mmc_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TSERIES=y
-CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
-CONFIG_BOOTDELAY=0
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NETCONSOLE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig
deleted file mode 100644
index 4dc0296..0000000
--- a/configs/tseries_nand_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TSERIES=y
-CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
-CONFIG_BOOTDELAY=0
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NETCONSOLE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig
deleted file mode 100644
index 5b52bf6..0000000
--- a/configs/tseries_spi_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_TSERIES=y
-CONFIG_SPL=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
-CONFIG_BOOTDELAY=0
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NETCONSOLE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
new file mode 100644
index 0000000..6a239b5
--- /dev/null
+++ b/include/configs/brppt1.h
@@ -0,0 +1,304 @@
+/*
+ * brtpp1.h
+ *
+ * specific parts for B&R T-Series Motherboard
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __CONFIG_BRPPT1_H__
+#define __CONFIG_BRPPT1_H__
+
+#include <configs/bur_cfg_common.h>
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_ROTATION
+#define CONFIG_LCD_DT_SIMPLEFB
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP				LCD_COLOR32
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
+#define CONFIG_SPL_GPIO_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_USE_FDT			/* use fdt within board code */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/*#define CONFIG_MACH_TYPE		3589*/
+#define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/
+
+/* MMC/SD IP block */
+#if defined(CONFIG_EMMC_BOOT)
+ #define CONFIG_MMC
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_OMAP_HSMMC
+ #define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
+ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
+ #define CONFIG_SPL_MMC_SUPPORT
+#endif /* CONFIG_EMMC_BOOT */
+
+/*
+ * When we have SPI or NAND flash we expect to be making use of mtdparts,
+ * both for ease of use in U-Boot and for passing information on to
+ * the Linux kernel.
+ */
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#endif /* CONFIG_SPI_BOOT, ... */
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_SPL_NAND_OFS			0x080000 /* end of u-boot */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x140000
+#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
+#endif /* CONFIG_NAND */
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* OMAP4 and later ELM support */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#endif /* CONFIG_NAND */
+
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE			(64 << 10)
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"${optargs_rot} " \
+		"root=mtd6 " \
+		"rootfstype=jffs2\0" \
+	"kernelsize=0x400000\0" \
+	"nandboot=echo booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} kernel ${kernelsize}; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+	"defboot=run nandboot\0" \
+	"bootlimit=1\0" \
+	"simplefb=1\0 " \
+	"altbootcmd=run usbscript\0"
+#else
+#define NANDARGS ""
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#define MMCARGS \
+"dtbdev=mmc\0" \
+"dtbpart=0:1\0" \
+"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \
+"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
+	"root=/dev/mmcblk0p2 rootfstype=ext4\0" \
+"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
+	"setenv simplefb 1; " \
+	"ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
+	"ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
+	"run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
+"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
+	"setenv simplefb 0; " \
+	"ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
+	"run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
+"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
+	"ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
+	"run ramboot; run usbscript;\0" \
+"bootlimit=1\0" \
+"altbootcmd=run mmcboot0;\0" \
+"upduboot=dhcp; " \
+	"tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
+	"tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
+#else
+#define MMCARGS ""
+#endif /* CONFIG_MMC */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+BUR_COMMON_ENV \
+"verify=no\0" \
+"autoload=0\0" \
+"dtb=bur-ppt-ts30.dtb\0" \
+"dtbaddr=0x80100000\0" \
+"loadaddr=0x80200000\0" \
+"ramaddr=0x80A00000\0" \
+"kernel=zImage\0" \
+"ramdisk=rootfs.cpio.uboot\0" \
+"console=ttyO0,115200n8\0" \
+"optargs=consoleblank=0 quiet panic=2\0" \
+"nfsroot=/tftpboot/tseries/rootfs-small\0" \
+"nfsopts=nolock\0" \
+"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
+"netargs=setenv bootargs console=${console} " \
+	"${optargs} " \
+	"root=/dev/nfs " \
+	"nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
+	"ip=dhcp\0" \
+"netboot=echo Booting from network ...; " \
+	"dhcp; " \
+	"tftp ${loadaddr} ${kernel}; " \
+	"tftp ${dtbaddr} ${dtb}; " \
+	"run netargs; " \
+	"bootz ${loadaddr} - ${dtbaddr}\0" \
+"ramboot=echo Booting from network into RAM ...; "\
+	"if dhcp; then; " \
+	"tftp ${loadaddr} ${kernel}; " \
+	"tftp ${ramaddr} ${ramdisk}; " \
+	"if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
+	"then; else tftp ${dtbaddr} ${dtb}; fi;" \
+	"run mmcroot0; " \
+	"bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
+"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+	"setenv autoload 0; " \
+	"dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
+NANDARGS \
+MMCARGS
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+	"run defboot;"
+
+#ifdef CONFIG_NAND
+/*
+ * GPMC  block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#define CONFIG_NAND_OMAP_GPMC
+/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, \
+					10, 11, 12, 13, 14, 15, 16, 17, \
+					18, 19, 20, 21, 22, 23, 24, 25, \
+					26, 27, 28, 29, 30, 31, 32, 33, \
+					34, 35, 36, 37, 38, 39, 40, 41, \
+					42, 43, 44, 45, 46, 47, 48, 49, \
+					50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
+					"128k(MLO)," \
+					"128k(MLO.backup)," \
+					"128k(dtb)," \
+					"128k(u-boot-env)," \
+					"512k(u-boot)," \
+					"4m(kernel),"\
+					"128m(rootfs),"\
+					"-(user)"
+#define CONFIG_NAND_OMAP_GPMC_WSCFG	1
+#endif /* CONFIG_NAND */
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#if defined(CONFIG_SPI_BOOT)
+/* McSPI IP block */
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
+
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#elif defined(CONFIG_NAND)
+/* No NAND env support in SPL */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#else
+#error "no storage for Environment defined!"
+#endif
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#endif /* CONFIG_MMC, ... */
+
+#endif	/* ! __CONFIG_BRPPT1_H__ */
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
deleted file mode 100644
index 8ed9eb0..0000000
--- a/include/configs/tseries.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * tseries.h
- *
- * specific parts for B&R T-Series Motherboard
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:        GPL-2.0+
- */
-
-#ifndef __CONFIG_TSERIES_H__
-#define __CONFIG_TSERIES_H__
-
-#include <configs/bur_cfg_common.h>
-#include <configs/bur_am335x_common.h>
-/* ------------------------------------------------------------------------- */
-#define CONFIG_AM335X_LCD
-#define CONFIG_LCD
-#define CONFIG_LCD_ROTATION
-#define CONFIG_LCD_DT_SIMPLEFB
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define LCD_BPP				LCD_COLOR32
-
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_OMAP_WATCHDOG
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-
-#define CONFIG_SPL_GPIO_SUPPORT
-/* Bootcount using the RTC block */
-#define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_BOOTCOUNT_AM33XX
-
-/* memory */
-#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
-
-/* Clock Defines */
-#define V_OSCK				26000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK)
-
-#define CONFIG_POWER_TPS65217
-
-/* Support both device trees and ATAGs. */
-#define CONFIG_USE_FDT			/* use fdt within board code */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-/*#define CONFIG_MACH_TYPE		3589*/
-#define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/
-
-/* MMC/SD IP block */
-#if defined(CONFIG_EMMC_BOOT)
- #define CONFIG_MMC
- #define CONFIG_GENERIC_MMC
- #define CONFIG_OMAP_HSMMC
- #define CONFIG_SUPPORT_EMMC_BOOT
-/* RAW SD card / eMMC locations. */
- #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
- #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
- #define CONFIG_SPL_MMC_SUPPORT
-#endif /* CONFIG_EMMC_BOOT */
-
-/*
- * When we have SPI or NAND flash we expect to be making use of mtdparts,
- * both for ease of use in U-Boot and for passing information on to
- * the Linux kernel.
- */
-#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
-#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
-#define CONFIG_CMD_MTDPARTS
-#endif /* CONFIG_SPI_BOOT, ... */
-
-#undef CONFIG_SPL_OS_BOOT
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
-
-/* NAND */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_SPL_NAND_OFS			0x080000 /* end of u-boot */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x140000
-#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
-#endif /* CONFIG_NAND */
-#endif /* CONFIG_SPL_OS_BOOT */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_AM33XX_BCH	/* OMAP4 and later ELM support */
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-#endif /* CONFIG_NAND */
-
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE			(64 << 10)
-
-#ifdef CONFIG_NAND
-#define NANDARGS \
-	"mtdids=" MTDIDS_DEFAULT "\0" \
-	"mtdparts=" MTDPARTS_DEFAULT "\0" \
-	"nandargs=setenv bootargs console=${console} " \
-		"${optargs} " \
-		"${optargs_rot} " \
-		"root=mtd6 " \
-		"rootfstype=jffs2\0" \
-	"kernelsize=0x400000\0" \
-	"nandboot=echo booting from nand ...; " \
-		"run nandargs; " \
-		"nand read ${loadaddr} kernel ${kernelsize}; " \
-		"bootz ${loadaddr} - ${dtbaddr}\0" \
-	"defboot=run nandboot\0" \
-	"bootlimit=1\0" \
-	"simplefb=1\0 " \
-	"altbootcmd=run usbscript\0"
-#else
-#define NANDARGS ""
-#endif /* CONFIG_NAND */
-
-#ifdef CONFIG_MMC
-#define MMCARGS \
-"dtbdev=mmc\0" \
-"dtbpart=0:1\0" \
-"mmcroot0=setenv bootargs ${optargs_rot} ${optargs} console=${console}\0" \
-"mmcroot1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
-	"root=/dev/mmcblk0p2 rootfstype=ext4\0" \
-"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
-	"setenv simplefb 1; " \
-	"ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
-	"ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
-	"run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
-"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
-	"setenv simplefb 0; " \
-	"ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
-	"run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
-"defboot=ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
-	"ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
-	"run ramboot; run usbscript;\0" \
-"bootlimit=1\0" \
-"altbootcmd=run mmcboot0;\0" \
-"upduboot=dhcp; " \
-	"tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
-	"tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
-#else
-#define MMCARGS ""
-#endif /* CONFIG_MMC */
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
-BUR_COMMON_ENV \
-"verify=no\0" \
-"autoload=0\0" \
-"dtb=bur-ppt-ts30.dtb\0" \
-"dtbaddr=0x80100000\0" \
-"loadaddr=0x80200000\0" \
-"ramaddr=0x80A00000\0" \
-"kernel=zImage\0" \
-"ramdisk=rootfs.cpio.uboot\0" \
-"console=ttyO0,115200n8\0" \
-"optargs=consoleblank=0 quiet panic=2\0" \
-"nfsroot=/tftpboot/tseries/rootfs-small\0" \
-"nfsopts=nolock\0" \
-"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
-"netargs=setenv bootargs console=${console} " \
-	"${optargs} " \
-	"root=/dev/nfs " \
-	"nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
-	"ip=dhcp\0" \
-"netboot=echo Booting from network ...; " \
-	"dhcp; " \
-	"tftp ${loadaddr} ${kernel}; " \
-	"tftp ${dtbaddr} ${dtb}; " \
-	"run netargs; " \
-	"bootz ${loadaddr} - ${dtbaddr}\0" \
-"ramboot=echo Booting from network into RAM ...; "\
-	"if dhcp; then; " \
-	"tftp ${loadaddr} ${kernel}; " \
-	"tftp ${ramaddr} ${ramdisk}; " \
-	"if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
-	"then; else tftp ${dtbaddr} ${dtb}; fi;" \
-	"run mmcroot0; " \
-	"bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
-"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
-	"setenv autoload 0; " \
-	"dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
-NANDARGS \
-MMCARGS
-#endif /* !CONFIG_SPL_BUILD*/
-
-#define CONFIG_BOOTCOMMAND \
-	"run defboot;"
-
-#ifdef CONFIG_NAND
-/*
- * GPMC  block.  We support 1 device and the physical address to
- * access CS0 at is 0x8000000.
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0x8000000
-#define CONFIG_NAND_OMAP_GPMC
-/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
-#define CONFIG_NAND_OMAP_ELM
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
-					CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, \
-					10, 11, 12, 13, 14, 15, 16, 17, \
-					18, 19, 20, 21, 22, 23, 24, 25, \
-					26, 27, 28, 29, 30, 31, 32, 33, \
-					34, 35, 36, 37, 38, 39, 40, 41, \
-					42, 43, 44, 45, 46, 47, 48, 49, \
-					50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-
-#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
-					"128k(MLO)," \
-					"128k(MLO.backup)," \
-					"128k(dtb)," \
-					"128k(u-boot-env)," \
-					"512k(u-boot)," \
-					"4m(kernel),"\
-					"128m(rootfs),"\
-					"-(user)"
-#define CONFIG_NAND_OMAP_GPMC_WSCFG	1
-#endif /* CONFIG_NAND */
-
-/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-#if defined(CONFIG_SPI_BOOT)
-/* McSPI IP block */
-#define CONFIG_SPI
-#define CONFIG_OMAP3_SPI
-#define CONFIG_SF_DEFAULT_SPEED		24000000
-
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
-#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
-#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
-
-#elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_SYS_MMC_ENV_PART		2
-#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#elif defined(CONFIG_NAND)
-/* No NAND env support in SPL */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_ENV_IS_NOWHERE
-#else
-#define CONFIG_ENV_IS_IN_NAND
-#endif
-#define CONFIG_ENV_OFFSET		0x60000
-#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
-#else
-#error "no storage for Environment defined!"
-#endif
-/*
- * Common filesystems support.  When we have removable storage we
- * enabled a number of useful commands and support.
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FAT_WRITE
-#define CONFIG_FS_EXT4
-#define CONFIG_EXT4_WRITE
-#endif /* CONFIG_MMC, ... */
-
-#endif	/* ! __CONFIG_TSERIES_H__ */
-- 
cgit v0.10.2


From a4d799939fdb08ce4d7464578734316cdd0bf452 Mon Sep 17 00:00:00 2001
From: Hannes Schmelzer <oe5hpm@oevsv.at>
Date: Wed, 22 Jun 2016 12:36:14 +0200
Subject: board/BuR: rename kwb board to brxre1

Rename B&R kwb board to brxre1

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3c2c755..3237a74 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -304,8 +304,8 @@ config TARGET_VEXPRESS_CA9X4
 	bool "Support vexpress_ca9x4"
 	select CPU_V7
 
-config TARGET_KWB
-	bool "Support kwb"
+config TARGET_BRXRE1
+	bool "Support BRXRE1"
 	select CPU_V7
 	select SUPPORT_SPL
 
@@ -908,7 +908,7 @@ source "arch/arm/cpu/armv8/Kconfig"
 source "arch/arm/imx-common/Kconfig"
 
 source "board/bosch/shc/Kconfig"
-source "board/BuR/kwb/Kconfig"
+source "board/BuR/brxre1/Kconfig"
 source "board/BuR/brppt1/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
diff --git a/board/BuR/brxre1/Kconfig b/board/BuR/brxre1/Kconfig
new file mode 100644
index 0000000..389e523
--- /dev/null
+++ b/board/BuR/brxre1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BRXRE1
+
+config SYS_BOARD
+	default "brxre1"
+
+config SYS_VENDOR
+	default "BuR"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "brxre1"
+
+endif
diff --git a/board/BuR/brxre1/MAINTAINERS b/board/BuR/brxre1/MAINTAINERS
new file mode 100644
index 0000000..a10d9c1
--- /dev/null
+++ b/board/BuR/brxre1/MAINTAINERS
@@ -0,0 +1,6 @@
+BRXRE1 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/brxre1/
+F:	include/configs/brxre1.h
+F:	configs/brxre1_defconfig
diff --git a/board/BuR/brxre1/Makefile b/board/BuR/brxre1/Makefile
new file mode 100644
index 0000000..782664c
--- /dev/null
+++ b/board/BuR/brxre1/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y	+= ../common/common.o
+obj-y	+= board.o
diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c
new file mode 100644
index 0000000..f4bfa41
--- /dev/null
+++ b/board/BuR/brxre1/board.c
@@ -0,0 +1,298 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R BRXRE1 Board
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+#include <lcd.h>
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define ESC_KEY					(0+19)
+#define LCD_PWR					(0+5)
+#define PUSH_KEY				(0+31)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define	RSTCTRL_ADDR				0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG				0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG			0x04
+
+/* -- defines for RSTCTRL_CTRLREG  -- */
+#define	RSTCTRL_FORCE_PWR_NEN			0x0404
+#define	RSTCTRL_CAN_STB				0x4040
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC	(V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	unsigned int oldspeed;
+	unsigned short buf;
+
+	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+	/*
+	 * enable additional clocks of modules which are accessed later from
+	 * VxWorks OS
+	 */
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_xre1specific[] = {
+		&cmwkup->wkup_adctscctrl,
+		&cmper->spi1clkctrl,
+		&cmper->dcan0clkctrl,
+		&cmper->dcan1clkctrl,
+		&cmper->epwmss0clkctrl,
+		&cmper->epwmss1clkctrl,
+		&cmper->epwmss2clkctrl,
+		&cmper->lcdclkctrl,
+		&cmper->lcdcclkstctrl,
+		0
+	};
+	do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
+	/* setup LCD-Pixel Clock */
+	writel(0x2, CM_DPLL + 0x34);
+	/* power-OFF LCD-Display */
+	gpio_direction_output(LCD_PWR, 0);
+
+	/* setup I2C */
+	enable_i2c_pin_mux();
+	i2c_set_bus_num(0);
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	/* power-ON  3V3 via Resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+		buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
+		i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+			  (uint8_t *)&buf, sizeof(buf));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+	}
+
+	pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+	config_ddr(400, &ddr3_ioregs,
+		   &ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gpmc_init();
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	const unsigned int toff = 1000;
+	unsigned int cnt  = 3;
+	unsigned short buf = 0xAAAA;
+	unsigned char scratchreg = 0;
+	unsigned int oldspeed;
+
+	/* try to read out some boot-instruction from resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+		i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+			 &scratchreg, sizeof(scratchreg));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+	}
+
+	if (gpio_get_value(ESC_KEY)) {
+		do {
+			lcd_position_cursor(1, 8);
+			switch (cnt) {
+			case 3:
+				lcd_puts(
+				"release ESC-KEY to enter SERVICE-mode.");
+				break;
+			case 2:
+				lcd_puts(
+				"release ESC-KEY to enter DIAGNOSE-mode.");
+				break;
+			case 1:
+				lcd_puts(
+				"release ESC-KEY to enter BOOT-mode.    ");
+				break;
+			}
+			mdelay(toff);
+			cnt--;
+			if (!gpio_get_value(ESC_KEY) &&
+			    gpio_get_value(PUSH_KEY) && 2 == cnt) {
+				lcd_position_cursor(1, 8);
+				lcd_puts(
+				"switching to network-console ...       ");
+				setenv("bootcmd", "run netconsole");
+				cnt = 4;
+				break;
+			} else if (!gpio_get_value(ESC_KEY) &&
+			    gpio_get_value(PUSH_KEY) && 1 == cnt) {
+				lcd_position_cursor(1, 8);
+				lcd_puts(
+				"starting u-boot script from USB ...    ");
+				setenv("bootcmd", "run usbscript");
+				cnt = 4;
+				break;
+			} else if ((!gpio_get_value(ESC_KEY) &&
+				    gpio_get_value(PUSH_KEY) && cnt == 0) ||
+				    (gpio_get_value(ESC_KEY) &&
+				    gpio_get_value(PUSH_KEY) && cnt == 0)) {
+				lcd_position_cursor(1, 8);
+				lcd_puts(
+				"starting script from network ...      ");
+				setenv("bootcmd", "run netscript");
+				cnt = 4;
+				break;
+			} else if (!gpio_get_value(ESC_KEY)) {
+				break;
+			}
+		} while (cnt);
+	} else if (scratchreg == 0xCC) {
+		lcd_position_cursor(1, 8);
+		lcd_puts(
+		"starting vxworks from network ...      ");
+		setenv("bootcmd", "run netboot");
+		cnt = 4;
+	} else if (scratchreg == 0xCD) {
+		lcd_position_cursor(1, 8);
+		lcd_puts(
+		"starting script from network ...      ");
+		setenv("bootcmd", "run netscript");
+		cnt = 4;
+	} else if (scratchreg == 0xCE) {
+		lcd_position_cursor(1, 8);
+		lcd_puts(
+		"starting AR from eMMC ...             ");
+		setenv("bootcmd", "run mmcboot");
+		cnt = 4;
+	}
+
+	lcd_position_cursor(1, 8);
+	switch (cnt) {
+	case 0:
+		lcd_puts("entering BOOT-mode.                    ");
+		setenv("bootcmd", "run defaultAR");
+		buf = 0x0000;
+		break;
+	case 1:
+		lcd_puts("entering DIAGNOSE-mode.                ");
+		buf = 0x0F0F;
+		break;
+	case 2:
+		lcd_puts("entering SERVICE mode.                 ");
+		buf = 0xB4B4;
+		break;
+	case 3:
+		lcd_puts("loading OS...                          ");
+		buf = 0x0404;
+		break;
+	}
+	/* write bootinfo into scratchregister of resetcontroller */
+	oldspeed = i2c_get_bus_speed();
+	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+		i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+			  (uint8_t *)&buf, sizeof(buf));
+		i2c_set_bus_speed(oldspeed);
+	} else {
+		puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+	}
+	/* setup othbootargs for bootvx-command (vxWorks bootline) */
+	char othbootargs[128];
+	snprintf(othbootargs, sizeof(othbootargs),
+		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
+		 (unsigned int) gd->fb_base-0x20,
+		 (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
+		 (u32)getenv_ulong("vx_romfsbase", 16, 0),
+		 (u32)getenv_ulong("vx_romfssize", 16, 0));
+	setenv("othbootargs", othbootargs);
+	/*
+	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+	 * expect that vectors are there, original u-boot moves them to _start
+	 */
+	__asm__("ldr r0,=0x20000");
+	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/brxre1/mux.c b/board/BuR/brxre1/mux.c
new file mode 100644
index 0000000..40224f7
--- /dev/null
+++ b/board/BuR/brxre1/mux.c
@@ -0,0 +1,198 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux spi0_pin_mux[] = {
+	/* SPI1_SCLK */
+	{OFFSET(spi0_sclk),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_D0 */
+	{OFFSET(spi0_d0),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_D1 */
+	{OFFSET(spi0_d1),	MODE(0) | PULLUDEN | RXACTIVE},
+	/* SPI1_CS0 */
+	{OFFSET(spi0_cs0),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	/* SPI1_CS1 */
+	{OFFSET(spi0_cs1),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+	/* DCAN0 TX */
+	{OFFSET(uart1_ctsn),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN0 RX */
+	{OFFSET(uart1_rtsn),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+	/* DCAN1 TX */
+	{OFFSET(uart1_rxd),   MODE(2) | PULLUDEN | PULLUP_EN},
+	/* DCAN1 RX */
+	{OFFSET(uart1_txd),   MODE(2) | RXACTIVE},
+	{-1},
+};
+
+static struct module_pin_mux gpios[] = {
+	/* GPIO0_7  (PWW0 OUT) - CAN TERM */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_19 (DMA_INTR0) - TA602 */
+	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
+	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+	/* GPIO0_30 (GPMC_WAIT0) - TA601 */
+	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+	/* GPIO1_29 (gpmc_csn0) - MMC nRST */
+	{OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_0  (GPMC_nCS3)	- VBAT_OK */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+	/* GPIO2_2  (GPMC_nADV_ALE) - DCOK */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO2_4  (GPMC_nWE) - TST_BAST */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+	/* GPIO2_5  (gpmc_be0n_cle) - DISPLAY_ON_OFF */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
+	/* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
+	{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+	{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+	{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+	{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+	{-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	/* UART0_CTS */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_RXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+	/* UART0_TXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+	{-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
+	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
+	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
+	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
+	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
+	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
+	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
+	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
+	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
+	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
+	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
+	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
+	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
+	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
+	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
+	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
+
+	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
+	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
+	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
+	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
+	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
+	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
+	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
+	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
+
+	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
+	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
+	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
+
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(mii1_pin_mux);
+	configure_module_pin_mux(spi0_pin_mux);
+	configure_module_pin_mux(dcan0_pin_mux);
+	configure_module_pin_mux(dcan1_pin_mux);
+	configure_module_pin_mux(mmc1_pin_mux);
+	configure_module_pin_mux(lcd_pin_mux);
+	configure_module_pin_mux(gpios);
+}
diff --git a/board/BuR/kwb/Kconfig b/board/BuR/kwb/Kconfig
deleted file mode 100644
index 4beefbf..0000000
--- a/board/BuR/kwb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_KWB
-
-config SYS_BOARD
-	default "kwb"
-
-config SYS_VENDOR
-	default "BuR"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "kwb"
-
-endif
diff --git a/board/BuR/kwb/MAINTAINERS b/board/BuR/kwb/MAINTAINERS
deleted file mode 100644
index ca7d329..0000000
--- a/board/BuR/kwb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KWB BOARD
-M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
-S:	Maintained
-F:	board/BuR/kwb/
-F:	include/configs/kwb.h
-F:	configs/kwb_defconfig
diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile
deleted file mode 100644
index 782664c..0000000
--- a/board/BuR/kwb/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
-# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_SPL_BUILD) += mux.o
-obj-y	+= ../common/common.o
-obj-y	+= board.o
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
deleted file mode 100644
index ad74ff2..0000000
--- a/board/BuR/kwb/board.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * board.c
- *
- * Board functions for B&R KWB Board
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- */
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <power/tps65217.h>
-#include "../common/bur_common.h"
-#include <lcd.h>
-
-/* -------------------------------------------------------------------------*/
-/* -- defines for used GPIO Hardware -- */
-#define ESC_KEY					(0+19)
-#define LCD_PWR					(0+5)
-#define PUSH_KEY				(0+31)
-/* -------------------------------------------------------------------------*/
-/* -- PSOC Resetcontroller Register defines -- */
-
-/* I2C Address of controller */
-#define	RSTCTRL_ADDR				0x75
-/* Register for CTRL-word */
-#define RSTCTRL_CTRLREG				0x01
-/* Register for giving some information to VxWorks OS */
-#define RSTCTRL_SCRATCHREG			0x04
-
-/* -- defines for RSTCTRL_CTRLREG  -- */
-#define	RSTCTRL_FORCE_PWR_NEN			0x0404
-#define	RSTCTRL_CAN_STB				0x4040
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_SPL_BUILD)
-/* TODO: check ram-timing ! */
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
-	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
-	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
-	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = MT41K256M16HA125E_RATIO,
-	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41K256M16HA125E_RATIO,
-	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41K256M16HA125E_RATIO,
-	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
-	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
-	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
-	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
-	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
-	.zq_config = MT41K256M16HA125E_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-static const struct ctrl_ioregs ddr3_ioregs = {
-	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-#define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
-	unsigned int oldspeed;
-	unsigned short buf;
-
-	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
-	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
-	/*
-	 * enable additional clocks of modules which are accessed later from
-	 * VxWorks OS
-	 */
-	u32 *const clk_domains[] = { 0 };
-
-	u32 *const clk_modules_kwbspecific[] = {
-		&cmwkup->wkup_adctscctrl,
-		&cmper->spi1clkctrl,
-		&cmper->dcan0clkctrl,
-		&cmper->dcan1clkctrl,
-		&cmper->epwmss0clkctrl,
-		&cmper->epwmss1clkctrl,
-		&cmper->epwmss2clkctrl,
-		&cmper->lcdclkctrl,
-		&cmper->lcdcclkstctrl,
-		0
-	};
-	do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
-	/* setup LCD-Pixel Clock */
-	writel(0x2, CM_DPLL + 0x34);
-	/* power-OFF LCD-Display */
-	gpio_direction_output(LCD_PWR, 0);
-
-	/* setup I2C */
-	enable_i2c_pin_mux();
-	i2c_set_bus_num(0);
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
-	/* power-ON  3V3 via Resetcontroller */
-	oldspeed = i2c_get_bus_speed();
-	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
-		buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
-		i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
-			  (uint8_t *)&buf, sizeof(buf));
-		i2c_set_bus_speed(oldspeed);
-	} else {
-		puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
-	}
-
-	pmicsetup(0);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr3;
-}
-
-void sdram_init(void)
-{
-	config_ddr(400, &ddr3_ioregs,
-		   &ddr3_data,
-		   &ddr3_cmd_ctrl_data,
-		   &ddr3_emif_reg_data, 0);
-}
-#endif /* CONFIG_SPL_BUILD */
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	gpmc_init();
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	const unsigned int toff = 1000;
-	unsigned int cnt  = 3;
-	unsigned short buf = 0xAAAA;
-	unsigned char scratchreg = 0;
-	unsigned int oldspeed;
-
-	/* try to read out some boot-instruction from resetcontroller */
-	oldspeed = i2c_get_bus_speed();
-	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
-		i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
-			 &scratchreg, sizeof(scratchreg));
-		i2c_set_bus_speed(oldspeed);
-	} else {
-		puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
-	}
-
-	if (gpio_get_value(ESC_KEY)) {
-		do {
-			lcd_position_cursor(1, 8);
-			switch (cnt) {
-			case 3:
-				lcd_puts(
-				"release ESC-KEY to enter SERVICE-mode.");
-				break;
-			case 2:
-				lcd_puts(
-				"release ESC-KEY to enter DIAGNOSE-mode.");
-				break;
-			case 1:
-				lcd_puts(
-				"release ESC-KEY to enter BOOT-mode.    ");
-				break;
-			}
-			mdelay(toff);
-			cnt--;
-			if (!gpio_get_value(ESC_KEY) &&
-			    gpio_get_value(PUSH_KEY) && 2 == cnt) {
-				lcd_position_cursor(1, 8);
-				lcd_puts(
-				"switching to network-console ...       ");
-				setenv("bootcmd", "run netconsole");
-				cnt = 4;
-				break;
-			} else if (!gpio_get_value(ESC_KEY) &&
-			    gpio_get_value(PUSH_KEY) && 1 == cnt) {
-				lcd_position_cursor(1, 8);
-				lcd_puts(
-				"starting u-boot script from USB ...    ");
-				setenv("bootcmd", "run usbscript");
-				cnt = 4;
-				break;
-			} else if ((!gpio_get_value(ESC_KEY) &&
-				    gpio_get_value(PUSH_KEY) && cnt == 0) ||
-				    (gpio_get_value(ESC_KEY) &&
-				    gpio_get_value(PUSH_KEY) && cnt == 0)) {
-				lcd_position_cursor(1, 8);
-				lcd_puts(
-				"starting script from network ...      ");
-				setenv("bootcmd", "run netscript");
-				cnt = 4;
-				break;
-			} else if (!gpio_get_value(ESC_KEY)) {
-				break;
-			}
-		} while (cnt);
-	} else if (scratchreg == 0xCC) {
-		lcd_position_cursor(1, 8);
-		lcd_puts(
-		"starting vxworks from network ...      ");
-		setenv("bootcmd", "run netboot");
-		cnt = 4;
-	} else if (scratchreg == 0xCD) {
-		lcd_position_cursor(1, 8);
-		lcd_puts(
-		"starting script from network ...      ");
-		setenv("bootcmd", "run netscript");
-		cnt = 4;
-	} else if (scratchreg == 0xCE) {
-		lcd_position_cursor(1, 8);
-		lcd_puts(
-		"starting AR from eMMC ...             ");
-		setenv("bootcmd", "run mmcboot");
-		cnt = 4;
-	}
-
-	lcd_position_cursor(1, 8);
-	switch (cnt) {
-	case 0:
-		lcd_puts("entering BOOT-mode.                    ");
-		setenv("bootcmd", "run defaultAR");
-		buf = 0x0000;
-		break;
-	case 1:
-		lcd_puts("entering DIAGNOSE-mode.                ");
-		buf = 0x0F0F;
-		break;
-	case 2:
-		lcd_puts("entering SERVICE mode.                 ");
-		buf = 0xB4B4;
-		break;
-	case 3:
-		lcd_puts("loading OS...                          ");
-		buf = 0x0404;
-		break;
-	}
-	/* write bootinfo into scratchregister of resetcontroller */
-	oldspeed = i2c_get_bus_speed();
-	if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
-		i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
-			  (uint8_t *)&buf, sizeof(buf));
-		i2c_set_bus_speed(oldspeed);
-	} else {
-		puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
-	}
-	/* setup othbootargs for bootvx-command (vxWorks bootline) */
-	char othbootargs[128];
-	snprintf(othbootargs, sizeof(othbootargs),
-		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
-		 (unsigned int) gd->fb_base-0x20,
-		 (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
-		 (u32)getenv_ulong("vx_romfsbase", 16, 0),
-		 (u32)getenv_ulong("vx_romfssize", 16, 0));
-	setenv("othbootargs", othbootargs);
-	/*
-	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
-	 * expect that vectors are there, original u-boot moves them to _start
-	 */
-	__asm__("ldr r0,=0x20000");
-	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
-
-	return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
deleted file mode 100644
index 40224f7..0000000
--- a/board/BuR/kwb/mux.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * mux.c
- *
- * Pinmux Setting for B&R LEIT Board(s)
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-static struct module_pin_mux spi0_pin_mux[] = {
-	/* SPI1_SCLK */
-	{OFFSET(spi0_sclk),	MODE(0) | PULLUDEN | RXACTIVE},
-	/* SPI1_D0 */
-	{OFFSET(spi0_d0),	MODE(0) | PULLUDEN | RXACTIVE},
-	/* SPI1_D1 */
-	{OFFSET(spi0_d1),	MODE(0) | PULLUDEN | RXACTIVE},
-	/* SPI1_CS0 */
-	{OFFSET(spi0_cs0),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
-	/* SPI1_CS1 */
-	{OFFSET(spi0_cs1),	MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
-	{-1},
-};
-
-static struct module_pin_mux dcan0_pin_mux[] = {
-	/* DCAN0 TX */
-	{OFFSET(uart1_ctsn),   MODE(2) | PULLUDEN | PULLUP_EN},
-	/* DCAN0 RX */
-	{OFFSET(uart1_rtsn),   MODE(2) | RXACTIVE},
-	{-1},
-};
-
-static struct module_pin_mux dcan1_pin_mux[] = {
-	/* DCAN1 TX */
-	{OFFSET(uart1_rxd),   MODE(2) | PULLUDEN | PULLUP_EN},
-	/* DCAN1 RX */
-	{OFFSET(uart1_txd),   MODE(2) | RXACTIVE},
-	{-1},
-};
-
-static struct module_pin_mux gpios[] = {
-	/* GPIO0_7  (PWW0 OUT) - CAN TERM */
-	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO0_19 (DMA_INTR0) - TA602 */
-	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
-	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
-	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
-	/* GPIO0_30 (GPMC_WAIT0) - TA601 */
-	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
-	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
-	/* GPIO1_29 (gpmc_csn0) - MMC nRST */
-	{OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
-	/* GPIO2_0  (GPMC_nCS3)	- VBAT_OK */
-	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
-	/* GPIO2_2  (GPMC_nADV_ALE) - DCOK */
-	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO2_4  (GPMC_nWE) - TST_BAST */
-	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
-	/* GPIO2_5  (gpmc_be0n_cle) - DISPLAY_ON_OFF */
-	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
-	/* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
-	{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
-	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
-	/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
-	{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
-	/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
-	{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
-	/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
-	{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
-	{-1},
-};
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	/* UART0_CTS */
-	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART0_RXD */
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
-	/* UART0_TXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
-	{-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
-	/* I2C_DATA */
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	/* I2C_SCLK */
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
-	{-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
-	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
-	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
-	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
-	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
-	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
-	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
-	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
-	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
-	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
-	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
-	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
-	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
-	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
-	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
-	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
-	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
-	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
-	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
-	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
-	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
-	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
-	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
-	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
-	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
-	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
-	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
-	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
-
-	{-1},
-};
-
-static struct module_pin_mux lcd_pin_mux[] = {
-	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
-	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
-	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
-	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
-	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
-	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
-	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
-	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
-	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
-	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
-	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
-	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
-	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
-	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
-	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
-	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */
-
-	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
-	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
-	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
-	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
-	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
-	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
-	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
-	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */
-
-	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
-	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
-	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
-	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */
-
-	{-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-	configure_module_pin_mux(mii1_pin_mux);
-	configure_module_pin_mux(spi0_pin_mux);
-	configure_module_pin_mux(dcan0_pin_mux);
-	configure_module_pin_mux(dcan1_pin_mux);
-	configure_module_pin_mux(mmc1_pin_mux);
-	configure_module_pin_mux(lcd_pin_mux);
-	configure_module_pin_mux(gpios);
-}
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
new file mode 100644
index 0000000..13617d3
--- /dev/null
+++ b/configs/brxre1_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BRXRE1=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NETCONSOLE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig
deleted file mode 100644
index 790292e..0000000
--- a/configs/kwb_defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_KWB=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-CONFIG_BOOTDELAY=0
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_GO is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NETCONSOLE=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h
new file mode 100644
index 0000000..11f56bf
--- /dev/null
+++ b/include/configs/brxre1.h
@@ -0,0 +1,143 @@
+/*
+ * brxre1.h
+ *
+ * specific parts for B&R KWB Motherboard
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __CONFIG_BRXRE1_H__
+#define __CONFIG_BRXRE1_H__
+
+#include <configs/bur_cfg_common.h>
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP				LCD_COLOR32
+
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(1366*767*4)
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_24BMP
+#define CONFIG_BMP_32BPP
+
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_MACH_TYPE		3589
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC	20000
+
+/* GPIO */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
+#define CONFIG_SPL_MMC_SUPPORT
+
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE			(64 << 10)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+BUR_COMMON_ENV \
+"bootaddr=0x80001100\0" \
+"bootdev=cpsw(0,0)\0" \
+"vx_romfsbase=0x800E0000\0" \
+"vx_romfssize=0x20000\0" \
+"vx_memtop=0x8FBEF000\0" \
+"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
+"autoload=0\0" \
+"loadaddr=0x80100000\0" \
+"logoaddr=0x82000000\0" \
+"defaultARlen=0x8000\0" \
+"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
+"defaultAR=run loadromfs; run loaddefaultAR; bootvx ${loadaddr}\0" \
+"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
+	"bmp display ${logoaddr} 0 0\0" \
+"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
+	"bmp display ${logoaddr} 0 0\0" \
+"mmcboot=echo booting AR from eMMC-flash ...; "\
+	"run logo0 || run logo1; " \
+	"run loadromfs; " \
+	"fatload mmc 0:1 ${loadaddr} arimg && bootvx ${loadaddr}; " \
+	"run defaultAR;\0" \
+"netboot=echo booting AR from network ...; " \
+	"run loadromfs; " \
+	"tftp ${loadaddr} arimg && bootvx ${loadaddr}; " \
+	"puts 'networkboot failed!';\0" \
+"netscript=echo running script from network (tftp) ...; " \
+	"tftp 0x80000000 netscript.img && source; " \
+	"puts 'netscript load failed!'\0" \
+"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \
+	"tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \
+"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \
+	"if tftp 0x80100000 arimg.bin; " \
+	"then mmc write 0x80100000 800 ${defaultARlen}; " \
+	"else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \
+"netupdateROMFS=echo updating romfs from network (tftp) ...; " \
+	"if tftp 0x80100000 romfs.bin; " \
+	"then mmc write 0x80100000 700 100; " \
+	"else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0"
+
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+	"run usbscript;"
+
+/* undefine command which we not need here */
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE	MUSB_HOST
+
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#endif /* CONFIG_MMC, ... */
+
+#endif	/* __CONFIG_BRXRE1_H__ */
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
deleted file mode 100644
index 2bddc6b..0000000
--- a/include/configs/kwb.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * kwb.h
- *
- * specific parts for B&R KWB Motherboard
- *
- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:        GPL-2.0+
- */
-
-#ifndef __CONFIG_KWB_H__
-#define __CONFIG_KWB_H__
-
-#include <configs/bur_cfg_common.h>
-#include <configs/bur_am335x_common.h>
-/* ------------------------------------------------------------------------- */
-#define CONFIG_AM335X_LCD
-#define CONFIG_LCD
-#define CONFIG_LCD_NOSTDOUT
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define LCD_BPP				LCD_COLOR32
-
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(1366*767*4)
-#define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_24BMP
-#define CONFIG_BMP_32BPP
-
-/* memory */
-#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
-
-/* Clock Defines */
-#define V_OSCK				26000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK)
-
-#define CONFIG_POWER_TPS65217
-
-#define CONFIG_MACH_TYPE		3589
-/* I2C IP block */
-#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC	20000
-
-/* GPIO */
-#define CONFIG_SPL_GPIO_SUPPORT
-
-/* MMC/SD IP block */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
-#define CONFIG_SPL_MMC_SUPPORT
-
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE			(64 << 10)
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
-BUR_COMMON_ENV \
-"bootaddr=0x80001100\0" \
-"bootdev=cpsw(0,0)\0" \
-"vx_romfsbase=0x800E0000\0" \
-"vx_romfssize=0x20000\0" \
-"vx_memtop=0x8FBEF000\0" \
-"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
-"autoload=0\0" \
-"loadaddr=0x80100000\0" \
-"logoaddr=0x82000000\0" \
-"defaultARlen=0x8000\0" \
-"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
-"defaultAR=run loadromfs; run loaddefaultAR; bootvx ${loadaddr}\0" \
-"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
-	"bmp display ${logoaddr} 0 0\0" \
-"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
-	"bmp display ${logoaddr} 0 0\0" \
-"mmcboot=echo booting AR from eMMC-flash ...; "\
-	"run logo0 || run logo1; " \
-	"run loadromfs; " \
-	"fatload mmc 0:1 ${loadaddr} arimg && bootvx ${loadaddr}; " \
-	"run defaultAR;\0" \
-"netboot=echo booting AR from network ...; " \
-	"run loadromfs; " \
-	"tftp ${loadaddr} arimg && bootvx ${loadaddr}; " \
-	"puts 'networkboot failed!';\0" \
-"netscript=echo running script from network (tftp) ...; " \
-	"tftp 0x80000000 netscript.img && source; " \
-	"puts 'netscript load failed!'\0" \
-"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \
-	"tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \
-"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \
-	"if tftp 0x80100000 arimg.bin; " \
-	"then mmc write 0x80100000 800 ${defaultARlen}; " \
-	"else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \
-"netupdateROMFS=echo updating romfs from network (tftp) ...; " \
-	"if tftp 0x80100000 romfs.bin; " \
-	"then mmc write 0x80100000 700 100; " \
-	"else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0"
-
-#endif /* !CONFIG_SPL_BUILD*/
-
-#define CONFIG_BOOTCOMMAND \
-	"run usbscript;"
-
-/* undefine command which we not need here */
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
-/* Support both device trees and ATAGs. */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/* USB configuration */
-#define CONFIG_USB_MUSB_DSPS
-#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE	MUSB_HOST
-
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_SYS_MMC_ENV_PART		2
-#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-/*
- * Common filesystems support.  When we have removable storage we
- * enabled a number of useful commands and support.
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FAT_WRITE
-#endif /* CONFIG_MMC, ... */
-
-#endif	/* __CONFIG_KWB_H__ */
-- 
cgit v0.10.2


From fba5f93c71902079f096549e886e4774334bc7ca Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 23 Jun 2016 01:15:38 +0200
Subject: efi_loader: Fix typo in distro script

The distro script is supposed to use the internal fdt as fallback if we
find no viable other option. However, we're missing a space key to actually
make that work.

Add the space, so we can successfully load an EFI blob even when there is
no device tree provided on the target device.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 4db6faa..9ecaf38 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -120,7 +120,7 @@
 			"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "      \
 		"if fdt addr ${fdt_addr_r}; then "                        \
 			"bootefi ${kernel_addr_r} ${fdt_addr_r};"         \
-		"else"                                                    \
+		"else "                                                    \
 			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
 		"fi\0"                                                    \
 	\
-- 
cgit v0.10.2


From 4141e85bcd79c0b9b16def710e527f165107b7af Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 23 Jun 2016 13:53:46 +0900
Subject: kbuild: avoid race between dtbs and dt/dt.dtb targets

If the final targets depend on both "dtbs" and "dts/dt.dtb",
and -j option is given to the command line, multiple threads
descend into the dts/ directory, which causes build error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>

diff --git a/Makefile b/Makefile
index 256d4ff..0c47bb6 100644
--- a/Makefile
+++ b/Makefile
@@ -810,7 +810,9 @@ ifeq ($(CONFIG_DM_I2C_COMPAT),y)
 endif
 
 PHONY += dtbs
-dtbs dts/dt.dtb: checkdtc u-boot
+dtbs: dts/dt.dtb
+	@:
+dts/dt.dtb: checkdtc u-boot
 	$(Q)$(MAKE) $(build)=dts dtbs
 
 quiet_cmd_copy = COPY    $@
-- 
cgit v0.10.2


From 217d16973db6239c88ca77c7ffe3e4abdaf58d57 Mon Sep 17 00:00:00 2001
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Date: Sat, 18 Jun 2016 10:47:10 +0530
Subject: usb: fsl: Fix NULL terminating issue for usb controller name string

Fixes NULL terminating issue for usb controller name string by using
sizeof operator.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index a43d37d..fa916ed 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -65,7 +65,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		mdelay(5);
 	}
 	memset(current_usb_controller, '\0', 5);
-	snprintf(current_usb_controller, 4, "usb%d", index+1);
+	snprintf(current_usb_controller, sizeof(current_usb_controller),
+		 "usb%d", index+1);
 
 	switch (index) {
 	case 0:
-- 
cgit v0.10.2


From 429ff4473b8b1a98c528608a127de833ece0496a Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 20 Jun 2016 09:43:08 +0800
Subject: ehci: mx7: fix usbnc_regs

There is a 4 bytes hole between phy_cfg2 and phy_status, fix the
usbnc_regs structure to include the hole.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index bb48d0d..cc3b11c 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -194,8 +194,9 @@ struct usbnc_regs {
 	u32 reserve1[10];
 	u32 phy_cfg1;
 	u32 phy_cfg2;
+	u32 reserve2;
 	u32 phy_status;
-	u32 reserve2[4];
+	u32 reserve3[4];
 	u32 adp_cfg1;
 	u32 adp_cfg2;
 	u32 adp_status;
-- 
cgit v0.10.2


From 57de41e9c944af8d2c7bfcc2358414c5dd8c39df Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Mon, 20 Jun 2016 09:43:09 +0800
Subject: ehci: mx7: fix otg id detection

The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the
OTG ID detection, not set it. When the bit is set, the ACA
Resistance Detection is enabled, which disables the OTG ID
detection, because the internal pull up is off.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index cc3b11c..069f116 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -208,8 +208,11 @@ static void usb_power_config(int index)
 			(0x10000 * index) + USBNC_OFFSET);
 	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
 
-	/* Enable usb_otg_id detection */
-	setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+	/*
+	 * Clear the ACAENB to enable usb_otg_id detection,
+	 * otherwise it is the ACA detection enabled.
+	 */
+	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
 }
 
 int usb_phy_mode(int port)
-- 
cgit v0.10.2


From 2b1cdafa9fdd0c88eb1bc96e9330e252c9795689 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 14 May 2016 23:42:07 +0200
Subject: common: Pass the boot device into spl_boot_mode()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.

The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index bc98edd..068d93e 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -526,7 +526,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 0289058..1246eed 100644
--- a/arch/arm/cpu/armv7/ls102xa/spl.c
+++ b/arch/arm/cpu/armv7/ls102xa/spl.c
@@ -15,7 +15,7 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NAND;
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 8333b20..60c367a 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -166,7 +166,7 @@ u32 spl_boot_device(void)
 	return gd->arch.omap_boot_device;
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	return gd->arch.omap_boot_mode;
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 5883c00..19e34fa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -24,7 +24,7 @@ u32 spl_boot_device(void)
 	return 0;
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index e3e2a4f..867d2b2 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -68,7 +68,7 @@ u32 spl_boot_device(void)
 	return 0;
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_RAM:
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index caa45cf..bdcda7d 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -70,7 +70,7 @@ u32 spl_boot_device(void)
 
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 	/* for MMC return either RAW or FAT mode */
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index f255b59..ad6a597 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -75,7 +75,7 @@ u32 spl_boot_device(void)
 }
 #endif
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 #ifdef CONFIG_SYS_USE_MMC
diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c
index 49349da..0aeaa7d 100644
--- a/arch/arm/mach-davinci/spl.c
+++ b/arch/arm/mach-davinci/spl.c
@@ -45,7 +45,7 @@ void spl_board_init(void)
 	preloader_console_init();
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	return MMCSD_MODE_RAW;
 }
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index ac5bb2c..e1c9cdb 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -57,7 +57,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	return MMCSD_MODE_RAW;
 }
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index e133cca..15f1266 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -66,7 +66,7 @@ fallback:
 	return BOOT_DEVICE_MMC1;
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	return MMCSD_MODE_RAW;
 }
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 98c16a0..fec4c7a 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -58,7 +58,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 	return MMCSD_MODE_FS;
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index bd15b9b..66e028e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -257,7 +257,7 @@ void spl_board_announce_boot_device(void)
 }
 
 /* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	return MMCSD_MODE_RAW;
 }
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index d34b9af..1d53140 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -77,7 +77,7 @@ u32 spl_boot_device(void)
 	return mode;
 }
 
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	struct mmc *mmc;
 
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 6c5415a..e8added 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -69,7 +69,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	return MMCSD_MODE_FS;
 }
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ef8583a..c44f1b5 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -286,7 +286,7 @@ int spl_mmc_load_image(u32 boot_device)
 		return err;
 	}
 
-	boot_mode = spl_boot_mode();
+	boot_mode = spl_boot_mode(boot_device);
 	err = -EINVAL;
 	switch (boot_mode) {
 	case MMCSD_MODE_EMMCBOOT:
diff --git a/include/spl.h b/include/spl.h
index 0ae1605..2360466 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -66,7 +66,7 @@ extern struct spl_image_info spl_image;
 /* SPL common functions */
 void preloader_console_init(void);
 u32 spl_boot_device(void);
-u32 spl_boot_mode(void);
+u32 spl_boot_mode(const u32 boot_device);
 void spl_set_header_raw_uboot(void);
 int spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
-- 
cgit v0.10.2


From 968ebdf1ef1493a9095cbc00934d608c624bcad4 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 14 May 2016 23:42:28 +0200
Subject: ARM: at91: Don't invoke spl_boot_device() twice
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since the spl_boot_mode() is now passed the boot device to boot from,
make use of it instead of inquiring for the boot device again. This
allows board_boot_order() to function correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index ad6a597..98f280c 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -77,7 +77,7 @@ u32 spl_boot_device(void)
 
 u32 spl_boot_mode(const u32 boot_device)
 {
-	switch (spl_boot_device()) {
+	switch (boot_device) {
 #ifdef CONFIG_SYS_USE_MMC
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
-- 
cgit v0.10.2


From ce9844ce17e8f8d8b97d0962751265247a51cb01 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Wed, 25 May 2016 07:23:44 +0200
Subject: arm: at91: add CONFIG_AT91SAM9M10G45
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

add support for CONFIG_AT91SAM9M10G45.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
index 2379dd4..61e36c4 100644
--- a/arch/arm/mach-at91/include/mach/at91_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -15,7 +15,7 @@
 #define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x30)
 #elif defined(CONFIG_AT91SAM9263)
 #define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x120)
-#elif defined(CONFIG_AT91SAM9G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x128)
 #else
 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
@@ -33,7 +33,7 @@
 #elif defined(CONFIG_AT91SAM9263)
 #define AT91_MATRIX_MASTERS	9
 #define AT91_MATRIX_SLAVES	7
-#elif defined(CONFIG_AT91SAM9G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #define AT91_MATRIX_MASTERS	11
 #define AT91_MATRIX_SLAVES	8
 #else
@@ -63,7 +63,7 @@ typedef struct at91_matrix {
 	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
 	u32		mrcr;		/* 0x100 Master Remap Control */
 	u32		reserve4[3];
-#if	defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 	u32		ccr[52];	/* 0x110 - 0x1E0 Chip Configuration */
 	u32		womr;		/* 0x1E4 Write Protect Mode  */
 	u32		wpsr;		/* 0x1E8 Write Protect Status */
@@ -106,14 +106,14 @@ typedef struct at91_matrix {
 
 /* Undefined Length Burst Type */
 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
+	defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #define AT91_MATRIX_MCFG_ULBT_INFINITE	0x00000000
 #define AT91_MATRIX_MCFG_ULBT_SINGLE	0x00000001
 #define AT91_MATRIX_MCFG_ULBT_FOUR	0x00000002
 #define AT91_MATRIX_MCFG_ULBT_EIGHT	0x00000003
 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN	0x00000004
 #endif
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO	0x00000005
 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR	0x00000006
 #define AT91_MATRIX_MCFG_ULBT_128	0x00000007
@@ -125,14 +125,15 @@ typedef struct at91_matrix {
 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	0x00020000
 
 /* Fixed Index of Default Master */
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \
+	defined(CONFIG_AT91SAM9M10G45)
 #define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 0xf) << 18)
 #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
 #define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 7) << 18)
 #endif
 
 /* Maximum Number of Allowed Cycles for a Burst */
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0x1ff) << 0)
 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
 	defined(CONFIG_AT91SAM9263)
@@ -147,13 +148,14 @@ typedef struct at91_matrix {
 
 /* Master Remap Control Register */
 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
+	defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define	AT91_MATRIX_MRCR_RCB0	(1 << 0)
 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define	AT91_MATRIX_MRCR_RCB1	(1 << 1)
 #endif
-#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
+	defined(CONFIG_AT91SAM9M10G45)
 #define	AT91_MATRIX_MRCR_RCB2	0x00000004
 #define	AT91_MATRIX_MRCR_RCB3	0x00000008
 #define	AT91_MATRIX_MRCR_RCB4	0x00000010
@@ -162,14 +164,14 @@ typedef struct at91_matrix {
 #define	AT91_MATRIX_MRCR_RCB7	0x00000080
 #define	AT91_MATRIX_MRCR_RCB8	0x00000100
 #endif
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 #define	AT91_MATRIX_MRCR_RCB9	0x00000200
 #define	AT91_MATRIX_MRCR_RCB10	0x00000400
 #define	AT91_MATRIX_MRCR_RCB11	0x00000800
 #endif
 
 /* TCM Configuration Register */
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 /* Size of ITCM enabled memory block */
 #define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
 #define	AT91_MATRIX_TCMR_ITCM_32	0x00000040
@@ -204,7 +206,7 @@ typedef struct at91_matrix {
 #define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
 #endif
 
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
 /* Video Mode Configuration Register */
 #define	AT91C_MATRIX_VDEC_SEL_OFF	0x00000000
 #define	AT91C_MATRIX_VDEC_SEL_ON	0x00000001
-- 
cgit v0.10.2


From 289f979cc9585b68ff74971d90512847f9b3c868 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Wed, 25 May 2016 07:23:45 +0200
Subject: corvus DTS / DM support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebase on current ToT, don't delete gurnard DTB creation]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index de75e24..5338a39 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,7 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-gurnard.dtb
+dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-corvus.dtb \
+	at91sam9g45-gurnard.dtb
+
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
diff --git a/arch/arm/dts/at91sam9g45-corvus.dts b/arch/arm/dts/at91sam9g45-corvus.dts
new file mode 100644
index 0000000..c207c02
--- /dev/null
+++ b/arch/arm/dts/at91sam9g45-corvus.dts
@@ -0,0 +1,108 @@
+/*
+ * at91sam9g45-corvus.dts Device Tree file fir Siemens corvus board
+ * (C) Copyright 2016 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "at91sam9g45.dtsi"
+
+/ {
+	model = "Siemens corvus";
+	compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
+
+	chosen {
+		stdout-path = &dbgu;
+	};
+
+	memory {
+		reg = <0x70000000 0x8000000>;
+	};
+
+	clocks {
+		slow_xtal {
+		      clock-frequency = <32768>;
+		};
+
+		main_xtal {
+		      clock-frequency = <12000000>;
+		};
+	};
+
+	ahb {
+		apb {
+			dbgu: serial@ffffee00 {
+				status = "okay";
+			};
+
+			usart1: serial@fff90000 {
+				pinctrl-0 =
+					<&pinctrl_usart1
+					 &pinctrl_usart1_rts
+					 &pinctrl_usart1_cts>;
+				status = "okay";
+			};
+
+			macb0: ethernet@fffbc000 {
+				phy-mode = "rmii";
+				status = "okay";
+			};
+
+			watchdog@fffffd40 {
+				status = "okay";
+			};
+
+			spi0: spi@fffa4000{
+				status = "okay";
+				cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
+				mtd_dataflash@0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					spi-max-frequency = <13000000>;
+					reg = <0>;
+				};
+			};
+
+			usb2: gadget@fff78000 {
+				atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
+
+			rtc@fffffd20 {
+				atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+				status = "okay";
+			};
+
+			gpbr: syscon@fffffd60 {
+				status = "okay";
+			};
+
+			rtc@fffffdb0 {
+				status = "okay";
+			};
+		};
+
+		nand0: nand@40000000 {
+			nand-bus-width = <8>;
+			nand-ecc-mode = "soft";
+			nand-on-flash-bbt;
+			status = "okay";
+		};
+
+		usb0: ohci@00700000 {
+			status = "okay";
+			num-ports = <2>;
+			atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
+					   &pioD 3 GPIO_ACTIVE_LOW>;
+		};
+
+		usb1: ehci@00800000 {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6180699..0ff0d1d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -122,6 +122,10 @@ config TARGET_CORVUS
 	bool "Support corvus"
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select DM_ETH
 
 config TARGET_TAURUS
 	bool "Support taurus"
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 9d52661..d4416e6 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -11,21 +11,23 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_serial.h>
 #include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/arch/clk.h>
-#include <lcd.h>
-#include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
+#ifndef CONFIG_DM_ETH
 #include <netdev.h>
+#endif
 #include <spi.h>
 
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
@@ -34,6 +36,24 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void corvus_request_gpio(void)
+{
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(AT91_PIN_PD7, "d0");
+	gpio_request(AT91_PIN_PD8, "d1");
+	gpio_request(AT91_PIN_PA12, "d2");
+	gpio_request(AT91_PIN_PA13, "d3");
+	gpio_request(AT91_PIN_PA15, "d4");
+	gpio_request(AT91_PIN_PB7, "recovery button");
+	gpio_request(AT91_PIN_PD1, "USB0");
+	gpio_request(AT91_PIN_PD3, "USB1");
+	gpio_request(AT91_PIN_PB18, "SPICS1");
+	gpio_request(AT91_PIN_PB3, "SPICS0");
+	gpio_request(CONFIG_RED_LED, "red led");
+	gpio_request(CONFIG_GREEN_LED, "green led");
+}
+
 static void corvus_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -78,6 +98,7 @@ static void corvus_nand_hw_init(void)
 
 void spl_board_init(void)
 {
+	corvus_request_gpio();
 	/*
 	 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
 	 * mode, so it need do some action to exit mode.
@@ -200,6 +221,7 @@ static void corvus_macb_hw_init(void)
 int board_early_init_f(void)
 {
 	at91_seriald_hw_init();
+	corvus_request_gpio();
 	return 0;
 }
 
@@ -220,6 +242,8 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+	/* we have to request the gpios again after relocation */
+	corvus_request_gpio();
 #ifdef CONFIG_CMD_NAND
 	corvus_nand_hw_init();
 #endif
@@ -249,6 +273,7 @@ int dram_init(void)
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
@@ -257,6 +282,7 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+#endif
 
 /* SPI chip select control */
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -289,3 +315,12 @@ void spi_cs_deactivate(struct spi_slave *slave)
 			break;
 	}
 }
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.platdata = &at91sam9260_serial_plat,
+};
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 2efffb5..51d1516 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_CORVUS=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -14,6 +15,8 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SOURCE is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
@@ -25,3 +28,8 @@ CONFIG_G_DNL_MANUFACTURER="Siemens AG"
 CONFIG_G_DNL_VENDOR_NUM=0x0908
 CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_OF_LIBFDT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 686760d..e6a811a 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -35,7 +35,7 @@
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-- 
cgit v0.10.2


From ae21e964d831e9544f1398a63d6f082570bd17fe Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Wed, 25 May 2016 07:23:46 +0200
Subject: arm: at91: dts: Bring in dts files for AT91SAM9G20 and SAM9260
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add this files from Linux v4.6-rc5

66b8a424d: [workqueue: fix ghost PENDING flag while doing MQ IO]

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi
new file mode 100644
index 0000000..d4884dd
--- /dev/null
+++ b/arch/arm/dts/at91sam9260.dtsi
@@ -0,0 +1,1034 @@
+/*
+ * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+	model = "Atmel AT91SAM9260 family SoC";
+	compatible = "atmel,at91sam9260";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		serial1 = &usart0;
+		serial2 = &usart1;
+		serial3 = &usart2;
+		serial4 = &usart3;
+		serial5 = &uart0;
+		serial6 = &uart1;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		tcb0 = &tcb0;
+		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		ssc0 = &ssc0;
+	};
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		reg = <0x20000000 0x04000000>;
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		adc_op_clk: adc_op_clk{
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <5000000>;
+		};
+	};
+
+	sram0: sram@002ff000 {
+		compatible = "mmio-sram";
+		reg = <0x002ff000 0x2000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			aic: interrupt-controller@fffff000 {
+				#interrupt-cells = <3>;
+				compatible = "atmel,at91rm9200-aic";
+				interrupt-controller;
+				reg = <0xfffff000 0x200>;
+				atmel,external-irqs = <29 30 31>;
+			};
+
+			ramc0: ramc@ffffea00 {
+				compatible = "atmel,at91sam9260-sdramc";
+				reg = <0xffffea00 0x200>;
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91sam9260-pmc", "syscon";
+				reg = <0xfffffc00 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				interrupt-controller;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#interrupt-cells = <1>;
+
+				main_osc: main_osc {
+					compatible = "atmel,at91rm9200-clk-main-osc";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+					clocks = <&main_xtal>;
+				};
+
+				main: mainck {
+					compatible = "atmel,at91rm9200-clk-main";
+					#clock-cells = <0>;
+					clocks = <&main_osc>;
+				};
+
+				slow_rc_osc: slow_rc_osc {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <32768>;
+					clock-accuracy = <50000000>;
+				};
+
+				clk32k: slck {
+					compatible = "atmel,at91sam9260-clk-slow";
+					#clock-cells = <0>;
+					clocks = <&slow_rc_osc>, <&slow_xtal>;
+				};
+
+				plla: pllack {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+					clocks = <&main>;
+					reg = <0>;
+					atmel,clk-input-range = <1000000 32000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
+								<150000000 240000000 2 1>;
+				};
+
+				pllb: pllbck {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+					clocks = <&main>;
+					reg = <1>;
+					atmel,clk-input-range = <1000000 5000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+				};
+
+				mck: masterck {
+					compatible = "atmel,at91rm9200-clk-master";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+					clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+					atmel,clk-output-range = <0 105000000>;
+					atmel,clk-divisors = <1 2 4 0>;
+				};
+
+				usb: usbck {
+					compatible = "atmel,at91rm9200-clk-usb";
+					#clock-cells = <0>;
+					atmel,clk-divisors = <1 2 4 0>;
+					clocks = <&pllb>;
+				};
+
+				prog: progck {
+					compatible = "atmel,at91rm9200-clk-programmable";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					interrupt-parent = <&pmc>;
+					clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+					prog0: prog0 {
+						#clock-cells = <0>;
+						reg = <0>;
+						interrupts = <AT91_PMC_PCKRDY(0)>;
+					};
+
+					prog1: prog1 {
+						#clock-cells = <0>;
+						reg = <1>;
+						interrupts = <AT91_PMC_PCKRDY(1)>;
+					};
+				};
+
+				systemck {
+					compatible = "atmel,at91rm9200-clk-system";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					uhpck: uhpck {
+						#clock-cells = <0>;
+						reg = <6>;
+						clocks = <&usb>;
+					};
+
+					udpck: udpck {
+						#clock-cells = <0>;
+						reg = <7>;
+						clocks = <&usb>;
+					};
+
+					pck0: pck0 {
+						#clock-cells = <0>;
+						reg = <8>;
+						clocks = <&prog0>;
+					};
+
+					pck1: pck1 {
+						#clock-cells = <0>;
+						reg = <9>;
+						clocks = <&prog1>;
+					};
+				};
+
+				periphck {
+					compatible = "atmel,at91rm9200-clk-peripheral";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					clocks = <&mck>;
+
+					pioA_clk: pioA_clk {
+						#clock-cells = <0>;
+						reg = <2>;
+					};
+
+					pioB_clk: pioB_clk {
+						#clock-cells = <0>;
+						reg = <3>;
+					};
+
+					pioC_clk: pioC_clk {
+						#clock-cells = <0>;
+						reg = <4>;
+					};
+
+					adc_clk: adc_clk {
+						#clock-cells = <0>;
+						reg = <5>;
+					};
+
+					usart0_clk: usart0_clk {
+						#clock-cells = <0>;
+						reg = <6>;
+					};
+
+					usart1_clk: usart1_clk {
+						#clock-cells = <0>;
+						reg = <7>;
+					};
+
+					usart2_clk: usart2_clk {
+						#clock-cells = <0>;
+						reg = <8>;
+					};
+
+					mci0_clk: mci0_clk {
+						#clock-cells = <0>;
+						reg = <9>;
+					};
+
+					udc_clk: udc_clk {
+						#clock-cells = <0>;
+						reg = <10>;
+					};
+
+					twi0_clk: twi0_clk {
+						reg = <11>;
+						#clock-cells = <0>;
+					};
+
+					spi0_clk: spi0_clk {
+						#clock-cells = <0>;
+						reg = <12>;
+					};
+
+					spi1_clk: spi1_clk {
+						#clock-cells = <0>;
+						reg = <13>;
+					};
+
+					ssc0_clk: ssc0_clk {
+						#clock-cells = <0>;
+						reg = <14>;
+					};
+
+					tc0_clk: tc0_clk {
+						#clock-cells = <0>;
+						reg = <17>;
+					};
+
+					tc1_clk: tc1_clk {
+						#clock-cells = <0>;
+						reg = <18>;
+					};
+
+					tc2_clk: tc2_clk {
+						#clock-cells = <0>;
+						reg = <19>;
+					};
+
+					ohci_clk: ohci_clk {
+						#clock-cells = <0>;
+						reg = <20>;
+					};
+
+					macb0_clk: macb0_clk {
+						#clock-cells = <0>;
+						reg = <21>;
+					};
+
+					isi_clk: isi_clk {
+						#clock-cells = <0>;
+						reg = <22>;
+					};
+
+					usart3_clk: usart3_clk {
+						#clock-cells = <0>;
+						reg = <23>;
+					};
+
+					uart0_clk: uart0_clk {
+						#clock-cells = <0>;
+						reg = <24>;
+					};
+
+					uart1_clk: uart1_clk {
+						#clock-cells = <0>;
+						reg = <25>;
+					};
+
+					tc3_clk: tc3_clk {
+						#clock-cells = <0>;
+						reg = <26>;
+					};
+
+					tc4_clk: tc4_clk {
+						#clock-cells = <0>;
+						reg = <27>;
+					};
+
+					tc5_clk: tc5_clk {
+						#clock-cells = <0>;
+						reg = <28>;
+					};
+				};
+			};
+
+			rstc@fffffd00 {
+				compatible = "atmel,at91sam9260-rstc";
+				reg = <0xfffffd00 0x10>;
+				clocks = <&clk32k>;
+			};
+
+			shdwc@fffffd10 {
+				compatible = "atmel,at91sam9260-shdwc";
+				reg = <0xfffffd10 0x10>;
+				clocks = <&clk32k>;
+			};
+
+			pit: timer@fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&mck>;
+			};
+
+			tcb0: timer@fffa0000 {
+				compatible = "atmel,at91rm9200-tcb";
+				reg = <0xfffa0000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+					      18 IRQ_TYPE_LEVEL_HIGH 0
+					      19 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+			};
+
+			tcb1: timer@fffdc000 {
+				compatible = "atmel,at91rm9200-tcb";
+				reg = <0xfffdc000 0x100>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+					      27 IRQ_TYPE_LEVEL_HIGH 0
+					      28 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
+				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+			};
+
+			pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x600>;
+
+				atmel,mux-mask = <
+				      /*    A         B     */
+				       0xffffffff 0xffc00c3b  /* pioA */
+				       0xffffffff 0x7fff3ccf  /* pioB */
+				       0xffffffff 0x007fffff  /* pioC */
+				      >;
+
+				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
+							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PB15 periph with pullup */
+					};
+				};
+
+				usart0 {
+					pinctrl_usart0: usart0-0 {
+						atmel,pins =
+							<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB5 periph A */
+					};
+
+					pinctrl_usart0_rts: usart0_rts-0 {
+						atmel,pins =
+							<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB26 periph A */
+					};
+
+					pinctrl_usart0_cts: usart0_cts-0 {
+						atmel,pins =
+							<AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB27 periph A */
+					};
+
+					pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
+						atmel,pins =
+							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB24 periph A */
+							 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB22 periph A */
+					};
+
+					pinctrl_usart0_dcd: usart0_dcd-0 {
+						atmel,pins =
+							<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB23 periph A */
+					};
+
+					pinctrl_usart0_ri: usart0_ri-0 {
+						atmel,pins =
+							<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB25 periph A */
+					};
+				};
+
+				usart1 {
+					pinctrl_usart1: usart1-0 {
+						atmel,pins =
+							<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB6 periph A with pullup */
+							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB7 periph A */
+					};
+
+					pinctrl_usart1_rts: usart1_rts-0 {
+						atmel,pins =
+							<AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB28 periph A */
+					};
+
+					pinctrl_usart1_cts: usart1_cts-0 {
+						atmel,pins =
+							<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB29 periph A */
+					};
+				};
+
+				usart2 {
+					pinctrl_usart2: usart2-0 {
+						atmel,pins =
+							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB8 periph A with pullup */
+							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB9 periph A */
+					};
+
+					pinctrl_usart2_rts: usart2_rts-0 {
+						atmel,pins =
+							<AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA4 periph A */
+					};
+
+					pinctrl_usart2_cts: usart2_cts-0 {
+						atmel,pins =
+							<AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA5 periph A */
+					};
+				};
+
+				usart3 {
+					pinctrl_usart3: usart3-0 {
+						atmel,pins =
+							<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB10 periph A with pullup */
+							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB11 periph A */
+					};
+
+					pinctrl_usart3_rts: usart3_rts-0 {
+						atmel,pins =
+							<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart3_cts: usart3_cts-0 {
+						atmel,pins =
+							<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				uart0 {
+					pinctrl_uart0: uart0-0 {
+						atmel,pins =
+							<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA31 periph B with pullup */
+							 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA30 periph B */
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1: uart1-0 {
+						atmel,pins =
+							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB12 periph A with pullup */
+							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB13 periph A */
+					};
+				};
+
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PC13 gpio RDY pin pull_up */
+							 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PC14 gpio enable pin pull_up */
+					};
+				};
+
+				macb {
+					pinctrl_macb_rmii: macb_rmii-0 {
+						atmel,pins =
+							<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A */
+							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA13 periph A */
+							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA14 periph A */
+							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA15 periph A */
+							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA16 periph A */
+							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
+							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA18 periph A */
+							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA19 periph A */
+							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA20 periph A */
+							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA21 periph A */
+					};
+
+					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+						atmel,pins =
+							<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B */
+							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA23 periph B */
+							 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA24 periph B */
+							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
+							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA26 periph B */
+							 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
+							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
+							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
+					};
+
+					pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
+						atmel,pins =
+							<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA10 periph B */
+							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA11 periph B */
+							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B */
+							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
+							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA26 periph B */
+							 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
+							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
+							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
+					};
+				};
+
+				mmc0 {
+					pinctrl_mmc0_clk: mmc0_clk-0 {
+						atmel,pins =
+							<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA8 periph A */
+					};
+
+					pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
+							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA6 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA9 periph A with pullup */
+							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA10 periph A with pullup */
+							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA11 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA1 periph B with pullup */
+							 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA0 periph B with pullup */
+					};
+
+					pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA5 periph B with pullup */
+							 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA4 periph B with pullup */
+							 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA3 periph B with pullup */
+					};
+				};
+
+				ssc0 {
+					pinctrl_ssc0_tx: ssc0_tx-0 {
+						atmel,pins =
+							<AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
+							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB17 periph A */
+							 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB18 periph A */
+					};
+
+					pinctrl_ssc0_rx: ssc0_rx-0 {
+						atmel,pins =
+							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB19 periph A */
+							 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB20 periph A */
+							 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB21 periph A */
+					};
+				};
+
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA0 periph A SPI0_MISO pin */
+							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA1 periph A SPI0_MOSI pin */
+							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A SPI1_MISO pin */
+							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A SPI1_MOSI pin */
+							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB2 periph A SPI1_SPCK pin */
+					};
+				};
+
+				i2c_gpio0 {
+					pinctrl_i2c_gpio0: i2c_gpio0-0 {
+						atmel,pins =
+							<AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
+							 AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+					};
+				};
+
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb1 {
+					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+						atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+						atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+						atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+						atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+						atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+						atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+						atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+						atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+						atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+				};
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
+				clocks = <&mck>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart0: serial@fffb0000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb0000 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart0>;
+				clocks = <&usart0_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart1: serial@fffb4000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb4000 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart1>;
+				clocks = <&usart1_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart2: serial@fffb8000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb8000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart2>;
+				clocks = <&usart2_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart3: serial@fffd0000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffd0000 0x200>;
+				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart3>;
+				clocks = <&usart3_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			uart0: serial@fffd4000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffd4000 0x200>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart0>;
+				clocks = <&uart0_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			uart1: serial@fffd8000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffd8000 0x200>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1>;
+				clocks = <&uart1_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			macb0: ethernet@fffc4000 {
+				compatible = "cdns,at91sam9260-macb", "cdns,macb";
+				reg = <0xfffc4000 0x100>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb_rmii>;
+				clocks = <&macb0_clk>, <&macb0_clk>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			usb1: gadget@fffa4000 {
+				compatible = "atmel,at91sam9260-udc";
+				reg = <0xfffa4000 0x4000>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+				clocks = <&udc_clk>, <&udpck>;
+				clock-names = "pclk", "hclk";
+				status = "disabled";
+			};
+
+			i2c0: i2c@fffac000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfffac000 0x100>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&twi0_clk>;
+				status = "disabled";
+			};
+
+			mmc0: mmc@fffa8000 {
+				compatible = "atmel,hsmci";
+				reg = <0xfffa8000 0x600>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				pinctrl-names = "default";
+				clocks = <&mci0_clk>;
+				clock-names = "mci_clk";
+				status = "disabled";
+			};
+
+			ssc0: ssc@fffbc000 {
+				compatible = "atmel,at91rm9200-ssc";
+				reg = <0xfffbc000 0x4000>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+				clocks = <&ssc0_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			spi0: spi@fffc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffc8000 0x200>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
+				clocks = <&spi0_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			spi1: spi@fffcc000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffcc000 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
+				clocks = <&spi1_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			adc0: adc@fffe0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9260-adc";
+				reg = <0xfffe0000 0x100>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&adc_clk>, <&adc_op_clk>;
+				clock-names = "adc_clk", "adc_op_clk";
+				atmel,adc-use-external-triggers;
+				atmel,adc-channels-used = <0xf>;
+				atmel,adc-vref = <3300>;
+				atmel,adc-startup-time = <15>;
+				atmel,adc-res = <8 10>;
+				atmel,adc-res-names = "lowres", "highres";
+				atmel,adc-use-res = "highres";
+
+				trigger@0 {
+					reg = <0>;
+					trigger-name = "timer-counter-0";
+					trigger-value = <0x1>;
+				};
+				trigger@1 {
+					reg = <1>;
+					trigger-name = "timer-counter-1";
+					trigger-value = <0x3>;
+				};
+
+				trigger@2 {
+					reg = <2>;
+					trigger-name = "timer-counter-2";
+					trigger-value = <0x5>;
+				};
+
+				trigger@3 {
+					reg = <3>;
+					trigger-name = "external";
+					trigger-value = <0xd>;
+					trigger-external;
+				};
+			};
+
+			rtc@fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				status = "disabled";
+			};
+
+			watchdog@fffffd40 {
+				compatible = "atmel,at91sam9260-wdt";
+				reg = <0xfffffd40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
+				atmel,watchdog-type = "hardware";
+				atmel,reset-type = "all";
+				atmel,dbg-halt;
+				status = "disabled";
+			};
+
+			gpbr: syscon@fffffd50 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd50 0x10>;
+				status = "disabled";
+			};
+		};
+
+		nand0: nand@40000000 {
+			compatible = "atmel,at91rm9200-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40000000 0x10000000
+			       0xffffe800 0x200
+			      >;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			gpios = <&pioC 13 GPIO_ACTIVE_HIGH
+				 &pioC 14 GPIO_ACTIVE_HIGH
+				 0
+				>;
+			status = "disabled";
+		};
+
+		usb0: ohci@00500000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00500000 0x100000>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+	};
+
+	i2c@0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
+			 &pioA 24 GPIO_ACTIVE_HIGH /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c_gpio0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi
new file mode 100644
index 0000000..5e09de4
--- /dev/null
+++ b/arch/arm/dts/at91sam9261.dtsi
@@ -0,0 +1,876 @@
+/*
+ * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
+ *
+ *  Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+	model = "Atmel AT91SAM9261 family SoC";
+	compatible = "atmel,at91sam9261";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		serial1 = &usart0;
+		serial2 = &usart1;
+		serial3 = &usart2;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		tcb0 = &tcb0;
+		i2c0 = &i2c0;
+		ssc0 = &ssc0;
+		ssc1 = &ssc1;
+		ssc2 = &ssc2;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		reg = <0x20000000 0x08000000>;
+	};
+
+	clocks {
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	sram: sram@00300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x28000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb0: ohci@00500000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00500000 0x100000>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		fb0: fb@0x00600000 {
+			compatible = "atmel,at91sam9261-lcdc";
+			reg = <0x00600000 0x1000>;
+			interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_fb>;
+			clocks = <&lcd_clk>, <&hclk1>;
+			clock-names = "lcdc_clk", "hclk";
+			status = "disabled";
+		};
+
+		nand0: nand@40000000 {
+			compatible = "atmel,at91rm9200-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40000000 0x10000000>;
+			atmel,nand-addr-offset = <22>;
+			atmel,nand-cmd-offset = <21>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+
+			gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
+				<&pioC 14 GPIO_ACTIVE_HIGH>,
+				<0>;
+			status = "disabled";
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			tcb0: timer@fffa0000 {
+				compatible = "atmel,at91rm9200-tcb";
+				reg = <0xfffa0000 0x100>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+					     <18 IRQ_TYPE_LEVEL_HIGH 0>,
+					     <19 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+			};
+
+			usb1: gadget@fffa4000 {
+				compatible = "atmel,at91sam9261-udc";
+				reg = <0xfffa4000 0x4000>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+				clocks = <&udc_clk>, <&udpck>;
+				clock-names = "pclk", "hclk";
+				atmel,matrix = <&matrix>;
+				status = "disabled";
+			};
+
+			mmc0: mmc@fffa8000 {
+				compatible = "atmel,hsmci";
+				reg = <0xfffa8000 0x600>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&mci0_clk>;
+				clock-names = "mci_clk";
+				status = "disabled";
+			};
+
+			i2c0: i2c@fffac000 {
+				compatible = "atmel,at91sam9261-i2c";
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c_twi>;
+				reg = <0xfffac000 0x100>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&twi0_clk>;
+				status = "disabled";
+			};
+
+			usart0: serial@fffb0000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb0000 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart0>;
+				clocks = <&usart0_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart1: serial@fffb4000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb4000 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart1>;
+				clocks = <&usart1_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart2: serial@fffb8000{
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfffb8000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart2>;
+				clocks = <&usart2_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			ssc0: ssc@fffbc000 {
+				compatible = "atmel,at91rm9200-ssc";
+				reg = <0xfffbc000 0x4000>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+				clocks = <&ssc0_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			ssc1: ssc@fffc0000 {
+				compatible = "atmel,at91rm9200-ssc";
+				reg = <0xfffc0000 0x4000>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+				clocks = <&ssc1_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			ssc2: ssc@fffc4000 {
+				compatible = "atmel,at91rm9200-ssc";
+				reg = <0xfffc4000 0x4000>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+				clocks = <&ssc2_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			spi0: spi@fffc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffc8000 0x200>;
+				cs-gpios = <0>, <0>, <0>, <0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
+				clocks = <&spi0_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			spi1: spi@fffcc000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffcc000 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
+				clocks = <&spi1_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			ramc: ramc@ffffea00 {
+				compatible = "atmel,at91sam9260-sdramc";
+				reg = <0xffffea00 0x200>;
+			};
+
+			matrix: matrix@ffffee00 {
+				compatible = "atmel,at91sam9260-bus-matrix", "syscon";
+				reg = <0xffffee00 0x200>;
+			};
+
+			aic: interrupt-controller@fffff000 {
+				#interrupt-cells = <3>;
+				compatible = "atmel,at91rm9200-aic";
+				interrupt-controller;
+				reg = <0xfffff000 0x200>;
+				atmel,external-irqs = <29 30 31>;
+			};
+
+			dbgu: serial@fffff200 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xfffff200 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
+				clocks = <&mck>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			pinctrl@fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff400 0xfffff400 0x600>;
+
+				atmel,mux-mask =
+				      /*    A         B     */
+				      <0xffffffff 0xfffffff7>,  /* pioA */
+				      <0xffffffff 0xfffffff4>,  /* pioB */
+				      <0xffffffff 0xffffff07>;  /* pioC */
+
+				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<AT91_PIOA 9  AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+					};
+				};
+
+				usart0 {
+					pinctrl_usart0: usart0-0 {
+						atmel,pins =
+							<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart0_rts: usart0_rts-0 {
+						atmel,pins =
+							<AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart0_cts: usart0_cts-0 {
+						atmel,pins =
+							<AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				usart1 {
+					pinctrl_usart1: usart1-0 {
+						atmel,pins =
+							<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart1_rts: usart1_rts-0 {
+						atmel,pins =
+							<AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart1_cts: usart1_cts-0 {
+						atmel,pins =
+							<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				usart2 {
+					pinctrl_usart2: usart2-0 {
+						atmel,pins =
+							<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart2_rts: usart2_rts-0 {
+						atmel,pins =
+							<AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_usart2_cts: usart2_cts-0 {
+						atmel,pins =
+							<AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+					};
+				};
+
+				mmc0 {
+					pinctrl_mmc0_clk: mmc0_clk-0 {
+						atmel,pins =
+							<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+					};
+
+					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+					};
+					};
+
+				ssc0 {
+					pinctrl_ssc0_tx: ssc0_tx-0 {
+						atmel,pins =
+							<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_ssc0_rx: ssc0_rx-0 {
+						atmel,pins =
+							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				ssc1 {
+					pinctrl_ssc1_tx: ssc1_tx-0 {
+						atmel,pins =
+							<AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_ssc1_rx: ssc1_rx-0 {
+						atmel,pins =
+							<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				ssc2 {
+					pinctrl_ssc2_tx: ssc2_tx-0 {
+						atmel,pins =
+							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_ssc2_rx: ssc2_rx-0 {
+						atmel,pins =
+							<AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+					};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				i2c0 {
+					pinctrl_i2c_bitbang: i2c-0-bitbang {
+						atmel,pins =
+							<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
+							<AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+					pinctrl_i2c_twi: i2c-0-twi {
+						atmel,pins =
+							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+				};
+
+				fb {
+					pinctrl_fb: fb-0 {
+						atmel,pins =
+							<AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+							<AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+							<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+				};
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91rm9200-pmc", "syscon";
+				reg = <0xfffffc00 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				interrupt-controller;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#interrupt-cells = <1>;
+
+				main_osc: main_osc {
+					compatible = "atmel,at91rm9200-clk-main-osc";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+					clocks = <&main_xtal>;
+				};
+
+				main: mainck {
+					compatible = "atmel,at91rm9200-clk-main";
+					#clock-cells = <0>;
+					clocks = <&main_osc>;
+				};
+
+				plla: pllack {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+					clocks = <&main>;
+					reg = <0>;
+					atmel,clk-input-range = <1000000 32000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+								<190000000 240000000 2 1>;
+				};
+
+				pllb: pllbck {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+					clocks = <&main>;
+					reg = <1>;
+					atmel,clk-input-range = <1000000 5000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+				};
+
+				mck: masterck {
+					compatible = "atmel,at91rm9200-clk-master";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+					clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+					atmel,clk-output-range = <0 94000000>;
+					atmel,clk-divisors = <1 2 4 0>;
+				};
+
+				usb: usbck {
+					compatible = "atmel,at91rm9200-clk-usb";
+					#clock-cells = <0>;
+					atmel,clk-divisors = <1 2 4 0>;
+					clocks = <&pllb>;
+				};
+
+				prog: progck {
+					compatible = "atmel,at91rm9200-clk-programmable";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					interrupt-parent = <&pmc>;
+					clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+
+					prog0: prog0 {
+						#clock-cells = <0>;
+						reg = <0>;
+						interrupts = <AT91_PMC_PCKRDY(0)>;
+					};
+
+					prog1: prog1 {
+						#clock-cells = <0>;
+						reg = <1>;
+						interrupts = <AT91_PMC_PCKRDY(1)>;
+					};
+
+					prog2: prog2 {
+						#clock-cells = <0>;
+						reg = <2>;
+						interrupts = <AT91_PMC_PCKRDY(2)>;
+					};
+
+					prog3: prog3 {
+						#clock-cells = <0>;
+						reg = <3>;
+						interrupts = <AT91_PMC_PCKRDY(3)>;
+					};
+				};
+
+				systemck {
+					compatible = "atmel,at91rm9200-clk-system";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					uhpck: uhpck {
+						#clock-cells = <0>;
+						reg = <6>;
+						clocks = <&usb>;
+					};
+
+					udpck: udpck {
+						#clock-cells = <0>;
+						reg = <7>;
+						clocks = <&usb>;
+					};
+
+					pck0: pck0 {
+						#clock-cells = <0>;
+						reg = <8>;
+						clocks = <&prog0>;
+					};
+
+					pck1: pck1 {
+						#clock-cells = <0>;
+						reg = <9>;
+						clocks = <&prog1>;
+					};
+
+					pck2: pck2 {
+						#clock-cells = <0>;
+						reg = <10>;
+						clocks = <&prog2>;
+					};
+
+					pck3: pck3 {
+						#clock-cells = <0>;
+						reg = <11>;
+						clocks = <&prog3>;
+					};
+
+					hclk0: hclk0 {
+						#clock-cells = <0>;
+						reg = <16>;
+						clocks = <&mck>;
+					};
+
+					hclk1: hclk1 {
+						#clock-cells = <0>;
+						reg = <17>;
+						clocks = <&mck>;
+					};
+				};
+
+				periphck {
+					compatible = "atmel,at91rm9200-clk-peripheral";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					clocks = <&mck>;
+
+					pioA_clk: pioA_clk {
+						#clock-cells = <0>;
+						reg = <2>;
+					};
+
+					pioB_clk: pioB_clk {
+						#clock-cells = <0>;
+						reg = <3>;
+					};
+
+					pioC_clk: pioC_clk {
+						#clock-cells = <0>;
+						reg = <4>;
+					};
+
+					usart0_clk: usart0_clk {
+						#clock-cells = <0>;
+						reg = <6>;
+					};
+
+					usart1_clk: usart1_clk {
+						#clock-cells = <0>;
+						reg = <7>;
+					};
+
+					usart2_clk: usart2_clk {
+						#clock-cells = <0>;
+						reg = <8>;
+					};
+
+					mci0_clk: mci0_clk {
+						#clock-cells = <0>;
+						reg = <9>;
+					};
+
+					udc_clk: udc_clk {
+						#clock-cells = <0>;
+						reg = <10>;
+					};
+
+					twi0_clk: twi0_clk {
+						reg = <11>;
+						#clock-cells = <0>;
+					};
+
+					spi0_clk: spi0_clk {
+						#clock-cells = <0>;
+						reg = <12>;
+					};
+
+					spi1_clk: spi1_clk {
+						#clock-cells = <0>;
+						reg = <13>;
+					};
+
+					ssc0_clk: ssc0_clk {
+						#clock-cells = <0>;
+						reg = <14>;
+					};
+
+					ssc1_clk: ssc1_clk {
+						#clock-cells = <0>;
+						reg = <15>;
+					};
+
+					ssc2_clk: ssc2_clk {
+						#clock-cells = <0>;
+						reg = <16>;
+					};
+
+					tc0_clk: tc0_clk {
+						#clock-cells = <0>;
+						reg = <17>;
+					};
+
+					tc1_clk: tc1_clk {
+						#clock-cells = <0>;
+						reg = <18>;
+					};
+
+					tc2_clk: tc2_clk {
+						#clock-cells = <0>;
+						reg = <19>;
+					};
+
+					ohci_clk: ohci_clk {
+						#clock-cells = <0>;
+						reg = <20>;
+					};
+
+					lcd_clk: lcd_clk {
+						#clock-cells = <0>;
+						reg = <21>;
+					};
+				};
+			};
+
+			rstc@fffffd00 {
+				compatible = "atmel,at91sam9260-rstc";
+				reg = <0xfffffd00 0x10>;
+				clocks = <&slow_xtal>;
+			};
+
+			shdwc@fffffd10 {
+				compatible = "atmel,at91sam9260-shdwc";
+				reg = <0xfffffd10 0x10>;
+				clocks = <&slow_xtal>;
+			};
+
+			pit: timer@fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&mck>;
+			};
+
+			rtc@fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				status = "disabled";
+			};
+
+			watchdog@fffffd40 {
+				compatible = "atmel,at91sam9260-wdt";
+				reg = <0xfffffd40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				status = "disabled";
+			};
+
+			gpbr: syscon@fffffd50 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd50 0x10>;
+				status = "disabled";
+			};
+		};
+	};
+
+	i2c@0 {
+		compatible = "i2c-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c_bitbang>;
+		gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
+			<&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi
new file mode 100644
index 0000000..9344642
--- /dev/null
+++ b/arch/arm/dts/at91sam9263.dtsi
@@ -0,0 +1,1034 @@
+/*
+ * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+	model = "Atmel AT91SAM9263 family SoC";
+	compatible = "atmel,at91sam9263";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		serial1 = &usart0;
+		serial2 = &usart1;
+		serial3 = &usart2;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+		gpio4 = &pioE;
+		tcb0 = &tcb0;
+		i2c0 = &i2c0;
+		ssc0 = &ssc0;
+		ssc1 = &ssc1;
+		pwm0 = &pwm0;
+	};
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	memory {
+		reg = <0x20000000 0x08000000>;
+	};
+
+	clocks {
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	sram0: sram@00300000 {
+		compatible = "mmio-sram";
+		reg = <0x00300000 0x14000>;
+	};
+
+	sram1: sram@00500000 {
+		compatible = "mmio-sram";
+		reg = <0x00500000 0x4000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			aic: interrupt-controller@fffff000 {
+				#interrupt-cells = <3>;
+				compatible = "atmel,at91rm9200-aic";
+				interrupt-controller;
+				reg = <0xfffff000 0x200>;
+				atmel,external-irqs = <30 31>;
+			};
+
+			pmc: pmc@fffffc00 {
+				compatible = "atmel,at91rm9200-pmc", "syscon";
+				reg = <0xfffffc00 0x100>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				interrupt-controller;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#interrupt-cells = <1>;
+
+				main_osc: main_osc {
+					compatible = "atmel,at91rm9200-clk-main-osc";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+					clocks = <&main_xtal>;
+				};
+
+				main: mainck {
+					compatible = "atmel,at91rm9200-clk-main";
+					#clock-cells = <0>;
+					clocks = <&main_osc>;
+				};
+
+				plla: pllack {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+					clocks = <&main>;
+					reg = <0>;
+					atmel,clk-input-range = <1000000 32000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+								<190000000 240000000 2 1>;
+				};
+
+				pllb: pllbck {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+					clocks = <&main>;
+					reg = <1>;
+					atmel,clk-input-range = <1000000 32000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+								<190000000 240000000 2 1>;
+				};
+
+				mck: masterck {
+					compatible = "atmel,at91rm9200-clk-master";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+					clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+					atmel,clk-output-range = <0 120000000>;
+					atmel,clk-divisors = <1 2 4 0>;
+				};
+
+				usb: usbck {
+					compatible = "atmel,at91rm9200-clk-usb";
+					#clock-cells = <0>;
+					atmel,clk-divisors = <1 2 4 0>;
+					clocks = <&pllb>;
+				};
+
+				prog: progck {
+					compatible = "atmel,at91rm9200-clk-programmable";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					interrupt-parent = <&pmc>;
+					clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+
+					prog0: prog0 {
+						#clock-cells = <0>;
+						reg = <0>;
+						interrupts = <AT91_PMC_PCKRDY(0)>;
+					};
+
+					prog1: prog1 {
+						#clock-cells = <0>;
+						reg = <1>;
+						interrupts = <AT91_PMC_PCKRDY(1)>;
+					};
+
+					prog2: prog2 {
+						#clock-cells = <0>;
+						reg = <2>;
+						interrupts = <AT91_PMC_PCKRDY(2)>;
+					};
+
+					prog3: prog3 {
+						#clock-cells = <0>;
+						reg = <3>;
+						interrupts = <AT91_PMC_PCKRDY(3)>;
+					};
+				};
+
+				systemck {
+					compatible = "atmel,at91rm9200-clk-system";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					uhpck: uhpck {
+						#clock-cells = <0>;
+						reg = <6>;
+						clocks = <&usb>;
+					};
+
+					udpck: udpck {
+						#clock-cells = <0>;
+						reg = <7>;
+						clocks = <&usb>;
+					};
+
+					pck0: pck0 {
+						#clock-cells = <0>;
+						reg = <8>;
+						clocks = <&prog0>;
+					};
+
+					pck1: pck1 {
+						#clock-cells = <0>;
+						reg = <9>;
+						clocks = <&prog1>;
+					};
+
+					pck2: pck2 {
+						#clock-cells = <0>;
+						reg = <10>;
+						clocks = <&prog2>;
+					};
+
+					pck3: pck3 {
+						#clock-cells = <0>;
+						reg = <11>;
+						clocks = <&prog3>;
+					};
+				};
+
+				periphck {
+					compatible = "atmel,at91rm9200-clk-peripheral";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					clocks = <&mck>;
+
+					pioA_clk: pioA_clk {
+						#clock-cells = <0>;
+						reg = <2>;
+					};
+
+					pioB_clk: pioB_clk {
+						#clock-cells = <0>;
+						reg = <3>;
+					};
+
+					pioCDE_clk: pioCDE_clk {
+						#clock-cells = <0>;
+						reg = <4>;
+					};
+
+					usart0_clk: usart0_clk {
+						#clock-cells = <0>;
+						reg = <7>;
+					};
+
+					usart1_clk: usart1_clk {
+						#clock-cells = <0>;
+						reg = <8>;
+					};
+
+					usart2_clk: usart2_clk {
+						#clock-cells = <0>;
+						reg = <9>;
+					};
+
+					mci0_clk: mci0_clk {
+						#clock-cells = <0>;
+						reg = <10>;
+					};
+
+					mci1_clk: mci1_clk {
+						#clock-cells = <0>;
+						reg = <11>;
+					};
+
+					can_clk: can_clk {
+						#clock-cells = <0>;
+						reg = <12>;
+					};
+
+					twi0_clk: twi0_clk {
+						#clock-cells = <0>;
+						reg = <13>;
+					};
+
+					spi0_clk: spi0_clk {
+						#clock-cells = <0>;
+						reg = <14>;
+					};
+
+					spi1_clk: spi1_clk {
+						#clock-cells = <0>;
+						reg = <15>;
+					};
+
+					ssc0_clk: ssc0_clk {
+						#clock-cells = <0>;
+						reg = <16>;
+					};
+
+					ssc1_clk: ssc1_clk {
+						#clock-cells = <0>;
+						reg = <17>;
+					};
+
+					ac97_clk: ac97_clk {
+						#clock-cells = <0>;
+						reg = <18>;
+					};
+
+					tcb_clk: tcb_clk {
+						#clock-cells = <0>;
+						reg = <19>;
+					};
+
+					pwm_clk: pwm_clk {
+						#clock-cells = <0>;
+						reg = <20>;
+					};
+
+					macb0_clk: macb0_clk {
+						#clock-cells = <0>;
+						reg = <21>;
+					};
+
+					g2de_clk: g2de_clk {
+						#clock-cells = <0>;
+						reg = <23>;
+					};
+
+					udc_clk: udc_clk {
+						#clock-cells = <0>;
+						reg = <24>;
+					};
+
+					isi_clk: isi_clk {
+						#clock-cells = <0>;
+						reg = <25>;
+					};
+
+					lcd_clk: lcd_clk {
+						#clock-cells = <0>;
+						reg = <26>;
+					};
+
+					dma_clk: dma_clk {
+						#clock-cells = <0>;
+						reg = <27>;
+					};
+
+					ohci_clk: ohci_clk {
+						#clock-cells = <0>;
+						reg = <29>;
+					};
+				};
+			};
+
+			ramc0: ramc@ffffe200 {
+				compatible = "atmel,at91sam9260-sdramc";
+				reg = <0xffffe200 0x200>;
+			};
+
+			ramc1: ramc@ffffe800 {
+				compatible = "atmel,at91sam9260-sdramc";
+				reg = <0xffffe800 0x200>;
+			};
+
+			pit: timer@fffffd30 {
+				compatible = "atmel,at91sam9260-pit";
+				reg = <0xfffffd30 0xf>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&mck>;
+			};
+
+			tcb0: timer@fff7c000 {
+				compatible = "atmel,at91rm9200-tcb";
+				reg = <0xfff7c000 0x100>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&tcb_clk>, <&slow_xtal>;
+				clock-names = "t0_clk", "slow_clk";
+			};
+
+			rstc@fffffd00 {
+				compatible = "atmel,at91sam9260-rstc";
+				reg = <0xfffffd00 0x10>;
+				clocks = <&slow_xtal>;
+			};
+
+			shdwc@fffffd10 {
+				compatible = "atmel,at91sam9260-shdwc";
+				reg = <0xfffffd10 0x10>;
+				clocks = <&slow_xtal>;
+			};
+
+			pinctrl@fffff200 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				ranges = <0xfffff200 0xfffff200 0xa00>;
+
+				atmel,mux-mask = <
+				      /*    A         B     */
+				       0xfffffffb 0xffffe07f  /* pioA */
+				       0x0007ffff 0x39072fff  /* pioB */
+				       0xffffffff 0x3ffffff8  /* pioC */
+				       0xfffffbff 0xffffffff  /* pioD */
+				       0xffe00fff 0xfbfcff00  /* pioE */
+				      >;
+
+				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC30 periph A */
+							 AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PC31 periph with pullup */
+					};
+				};
+
+				usart0 {
+					pinctrl_usart0: usart0-0 {
+						atmel,pins =
+							<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA26 periph A with pullup */
+							 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA27 periph A */
+					};
+
+					pinctrl_usart0_rts: usart0_rts-0 {
+						atmel,pins =
+							<AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA28 periph A */
+					};
+
+					pinctrl_usart0_cts: usart0_cts-0 {
+						atmel,pins =
+							<AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA29 periph A */
+					};
+				};
+
+				usart1 {
+					pinctrl_usart1: usart1-0 {
+						atmel,pins =
+							<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD0 periph A with pullup */
+							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD1 periph A */
+					};
+
+					pinctrl_usart1_rts: usart1_rts-0 {
+						atmel,pins =
+							<AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PD7 periph B */
+					};
+
+					pinctrl_usart1_cts: usart1_cts-0 {
+						atmel,pins =
+							<AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PD8 periph B */
+					};
+				};
+
+				usart2 {
+					pinctrl_usart2: usart2-0 {
+						atmel,pins =
+							<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD2 periph A with pullup */
+							 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD3 periph A */
+					};
+
+					pinctrl_usart2_rts: usart2_rts-0 {
+						atmel,pins =
+							<AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PD5 periph B */
+					};
+
+					pinctrl_usart2_cts: usart2_cts-0 {
+						atmel,pins =
+							<AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PD6 periph B */
+					};
+				};
+
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PA22 gpio RDY pin pull_up*/
+							 AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PD15 gpio enable pin pull_up */
+					};
+				};
+
+				macb {
+					pinctrl_macb_rmii: macb_rmii-0 {
+						atmel,pins =
+							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC25 periph B */
+							 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE21 periph A */
+							 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE23 periph A */
+							 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE24 periph A */
+							 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE25 periph A */
+							 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE26 periph A */
+							 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE27 periph A */
+							 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE28 periph A */
+							 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE29 periph A */
+							 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PE30 periph A */
+					};
+
+					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+						atmel,pins =
+							<AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
+							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
+							 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC22 periph B */
+							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC23 periph B */
+							 AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC24 periph B */
+							 AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC25 periph B */
+							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
+							 AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PE22 periph B */
+					};
+				};
+
+				mmc0 {
+					pinctrl_mmc0_clk: mmc0_clk-0 {
+						atmel,pins =
+							<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA12 periph A */
+					};
+
+					pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA1 periph A with pullup */
+							 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA0 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA3 periph A with pullup */
+							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA4 periph A with pullup */
+							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA5 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA16 periph A with pullup */
+							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA17 periph A with pullup */
+					};
+
+					pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA18 periph A with pullup */
+							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA19 periph A with pullup */
+							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA20 periph A with pullup */
+					};
+				};
+
+				mmc1 {
+					pinctrl_mmc1_clk: mmc1_clk-0 {
+						atmel,pins =
+							<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA6 periph A */
+					};
+
+					pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
+							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA8 periph A with pullup */
+					};
+
+					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA9 periph A with pullup */
+							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA10 periph A with pullup */
+							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA11 periph A with pullup */
+					};
+
+					pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
+						atmel,pins =
+							<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA21 periph A with pullup */
+							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA22 periph A with pullup */
+					};
+
+					pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
+						atmel,pins =
+							<AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA23 periph A with pullup */
+							 AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA24 periph A with pullup */
+							 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA25 periph A with pullup */
+					};
+				};
+
+				ssc0 {
+					pinctrl_ssc0_tx: ssc0_tx-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB0 periph B */
+							 AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB1 periph B */
+							 AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB2 periph B */
+					};
+
+					pinctrl_ssc0_rx: ssc0_rx-0 {
+						atmel,pins =
+							<AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB3 periph B */
+							 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB4 periph B */
+							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB5 periph B */
+					};
+				};
+
+				ssc1 {
+					pinctrl_ssc1_tx: ssc1_tx-0 {
+						atmel,pins =
+							<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+							 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB8 periph A */
+					};
+
+					pinctrl_ssc1_rx: ssc1_rx-0 {
+						atmel,pins =
+							<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB10 periph A */
+							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB11 periph A */
+					};
+				};
+
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA0 periph B SPI0_MISO pin */
+							 AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA1 periph B SPI0_MOSI pin */
+							 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA2 periph B SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A SPI1_MISO pin */
+							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A SPI1_MOSI pin */
+							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB14 periph A SPI1_SPCK pin */
+					};
+				};
+
+				tcb0 {
+					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+						atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+						atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+						atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+						atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+						atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+						atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+						atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+						atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+
+					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+						atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+					};
+				};
+
+				fb {
+					pinctrl_fb: fb-0 {
+						atmel,pins =
+							<AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC1 periph A */
+							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC2 periph A */
+							 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC3 periph A */
+							 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB9 periph B */
+							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC6 periph A */
+							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC7 periph A */
+							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC8 periph A */
+							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC9 periph A */
+							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC10 periph A */
+							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC11 periph A */
+							 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC14 periph A */
+							 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC15 periph A */
+							 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC16 periph A */
+							 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC12 periph B */
+							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC18 periph A */
+							 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC19 periph A */
+							 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC22 periph A */
+							 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC23 periph A */
+							 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC24 periph A */
+							 AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC17 periph B */
+							 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC26 periph A */
+							 AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PC27 periph A */
+					};
+				};
+
+				can {
+					pinctrl_can_rx_tx: can_rx_tx {
+						atmel,pins =
+							<AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* CANRX, conflicts with IRQ0 */
+							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* CANTX, conflicts with PCK0 */
+					};
+				};
+
+				ac97 {
+					pinctrl_ac97: ac97-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A AC97FS pin */
+							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A AC97CK pin */
+							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A AC97TX pin */
+							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB14 periph A AC97RX pin */
+					};
+				};
+
+				pioA: gpio@fffff200 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+				};
+
+				pioB: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+				};
+
+				pioC: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCDE_clk>;
+				};
+
+				pioD: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCDE_clk>;
+				};
+
+				pioE: gpio@fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCDE_clk>;
+				};
+			};
+
+			dbgu: serial@ffffee00 {
+				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+				reg = <0xffffee00 0x200>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
+				clocks = <&mck>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart0: serial@fff8c000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff8c000 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart0>;
+				clocks = <&usart0_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart1: serial@fff90000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff90000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart1>;
+				clocks = <&usart1_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			usart2: serial@fff94000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xfff94000 0x200>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart2>;
+				clocks = <&usart2_clk>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			ssc0: ssc@fff98000 {
+				compatible = "atmel,at91rm9200-ssc";
+				reg = <0xfff98000 0x4000>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+				clocks = <&ssc0_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			ssc1: ssc@fff9c000 {
+				compatible = "atmel,at91rm9200-ssc";
+				reg = <0xfff9c000 0x4000>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+				clocks = <&ssc1_clk>;
+				clock-names = "pclk";
+				status = "disabled";
+			};
+
+			ac97: sound@fffa0000 {
+				compatible = "atmel,at91sam9263-ac97c";
+				reg = <0xfffa0000 0x4000>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ac97>;
+				clocks = <&ac97_clk>;
+				clock-names = "ac97_clk";
+				status = "disabled";
+			};
+
+			macb0: ethernet@fffbc000 {
+				compatible = "cdns,at91sam9260-macb", "cdns,macb";
+				reg = <0xfffbc000 0x100>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb_rmii>;
+				clocks = <&macb0_clk>, <&macb0_clk>;
+				clock-names = "hclk", "pclk";
+				status = "disabled";
+			};
+
+			usb1: gadget@fff78000 {
+				compatible = "atmel,at91sam9263-udc";
+				reg = <0xfff78000 0x4000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
+				clocks = <&udc_clk>, <&udpck>;
+				clock-names = "pclk", "hclk";
+				status = "disabled";
+			};
+
+			i2c0: i2c@fff88000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&twi0_clk>;
+				status = "disabled";
+			};
+
+			mmc0: mmc@fff80000 {
+				compatible = "atmel,hsmci";
+				reg = <0xfff80000 0x600>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&mci0_clk>;
+				clock-names = "mci_clk";
+				status = "disabled";
+			};
+
+			mmc1: mmc@fff84000 {
+				compatible = "atmel,hsmci";
+				reg = <0xfff84000 0x600>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&mci1_clk>;
+				clock-names = "mci_clk";
+				status = "disabled";
+			};
+
+			watchdog@fffffd40 {
+				compatible = "atmel,at91sam9260-wdt";
+				reg = <0xfffffd40 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				atmel,watchdog-type = "hardware";
+				atmel,reset-type = "all";
+				atmel,dbg-halt;
+				status = "disabled";
+			};
+
+			spi0: spi@fffa4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa4000 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
+				clocks = <&spi0_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			spi1: spi@fffa8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa8000 0x200>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
+				clocks = <&spi1_clk>;
+				clock-names = "spi_clk";
+				status = "disabled";
+			};
+
+			pwm0: pwm@fffb8000 {
+				compatible = "atmel,at91sam9rl-pwm";
+				reg = <0xfffb8000 0x300>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				clocks = <&pwm_clk>;
+				clock-names = "pwm_clk";
+				status = "disabled";
+			};
+
+			can: can@fffac000 {
+				compatible = "atmel,at91sam9263-can";
+				reg = <0xfffac000 0x300>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_can_rx_tx>;
+				clocks = <&can_clk>;
+				clock-names = "can_clk";
+			};
+
+			rtc@fffffd20 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd20 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				status = "disabled";
+			};
+
+			rtc@fffffd50 {
+				compatible = "atmel,at91sam9260-rtt";
+				reg = <0xfffffd50 0x10>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&slow_xtal>;
+				status = "disabled";
+			};
+
+			gpbr: syscon@fffffd60 {
+				compatible = "atmel,at91sam9260-gpbr", "syscon";
+				reg = <0xfffffd60 0x50>;
+				status = "disabled";
+			};
+		};
+
+		fb0: fb@0x00700000 {
+			compatible = "atmel,at91sam9263-lcdc";
+			reg = <0x00700000 0x1000>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_fb>;
+			clocks = <&lcd_clk>, <&lcd_clk>;
+			clock-names = "lcdc_clk", "hclk";
+			status = "disabled";
+		};
+
+		nand0: nand@40000000 {
+			compatible = "atmel,at91rm9200-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40000000 0x10000000
+			       0xffffe000 0x200
+			      >;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
+			gpios = <&pioA 22 GPIO_ACTIVE_HIGH
+				 &pioD 15 GPIO_ACTIVE_HIGH
+				 0
+				>;
+			status = "disabled";
+		};
+
+		usb0: ohci@00a00000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00a00000 0x100000>;
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+	};
+
+	i2c@0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
+			 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/dts/at91sam9g20.dtsi b/arch/arm/dts/at91sam9g20.dtsi
new file mode 100644
index 0000000..f593016
--- /dev/null
+++ b/arch/arm/dts/at91sam9g20.dtsi
@@ -0,0 +1,68 @@
+/*
+ * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include "at91sam9260.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G20 family SoC";
+	compatible = "atmel,at91sam9g20";
+
+	memory {
+		reg = <0x20000000 0x08000000>;
+	};
+
+	sram0: sram@002ff000 {
+		status = "disabled";
+	};
+
+	sram1: sram@002fc000 {
+		compatible = "mmio-sram";
+		reg = <0x002fc000 0x8000>;
+	};
+
+	ahb {
+		apb {
+			i2c0: i2c@fffac000 {
+				compatible = "atmel,at91sam9g20-i2c";
+			};
+
+			ssc0: ssc@fffbc000 {
+				compatible = "atmel,at91sam9rl-ssc";
+			};
+
+			adc0: adc@fffe0000 {
+				atmel,adc-startup-time = <40>;
+			};
+
+			pmc: pmc@fffffc00 {
+				plla: pllack {
+					atmel,clk-input-range = <2000000 32000000>;
+					atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
+								<695000000 750000000 1 0>,
+								<645000000 700000000 2 0>,
+								<595000000 650000000 3 0>,
+								<545000000 600000000 0 1>,
+								<495000000 550000000 1 1>,
+								<445000000 500000000 2 1>,
+								<400000000 450000000 3 1>;
+				};
+
+				pllb: pllbck {
+					compatible = "atmel,at91sam9g20-clk-pllb";
+					atmel,clk-input-range = <2000000 32000000>;
+					atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
+				};
+
+				mck: masterck {
+					atmel,clk-output-range = <0 133000000>;
+					atmel,clk-divisors = <1 2 4 6>;
+				};
+			};
+		};
+	};
+};
-- 
cgit v0.10.2


From 13ee78907418872cc2c7943e3a82183af8229e8a Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Wed, 25 May 2016 07:23:47 +0200
Subject: arm: at91: smartweb: add DM and DTS support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebased on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5338a39..63b86f1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-corvus.dtb \
+dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \
+	at91sam9g45-corvus.dtb \
 	at91sam9g45-gurnard.dtb
 
 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
diff --git a/arch/arm/dts/at91sam9260-smartweb.dts b/arch/arm/dts/at91sam9260-smartweb.dts
new file mode 100644
index 0000000..faed763
--- /dev/null
+++ b/arch/arm/dts/at91sam9260-smartweb.dts
@@ -0,0 +1,110 @@
+/*
+ * at91sam9260-smartweb.dts
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9260.dtsi"
+
+/ {
+	model = "Siemens smartweb";
+	compatible = "atmel,at91sam9260", "atmel,at91sam9";
+
+	chosen {
+		stdout-path = &dbgu;
+	};
+
+	memory {
+		reg = <0x20000000 0x4000000>;
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <18432000>;
+		};
+	};
+
+	ahb {
+		apb {
+			pinctrl@fffff400 {
+				board {
+					pinctrl_pck0_as_mck: pck0_as_mck {
+						atmel,pins =
+							<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC1 periph B */
+					};
+
+				};
+			};
+
+			dbgu: serial@fffff200 {
+				status = "okay";
+			};
+
+			usart0: serial@fffb0000 {
+				pinctrl-0 =
+					<&pinctrl_usart0
+					 &pinctrl_usart0_rts
+					 &pinctrl_usart0_cts
+					 &pinctrl_usart0_dtr_dsr
+					 &pinctrl_usart0_dcd
+					 &pinctrl_usart0_ri>;
+				status = "okay";
+			};
+
+			usart1: serial@fffb4000 {
+				status = "okay";
+			};
+
+			macb0: ethernet@fffc4000 {
+				phy-mode = "rmii";
+				status = "okay";
+			};
+
+			usb1: gadget@fffa4000 {
+				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
+
+			ssc0: ssc@fffbc000 {
+				status = "okay";
+				pinctrl-0 = <&pinctrl_ssc0_tx>;
+			};
+
+			rtc@fffffd20 {
+				atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+				status = "okay";
+			};
+
+			watchdog@fffffd40 {
+				status = "okay";
+			};
+
+			gpbr: syscon@fffffd50 {
+				status = "okay";
+			};
+		};
+
+		nand0: nand@40000000 {
+			nand-bus-width = <8>;
+			nand-ecc-mode = "soft";
+			nand-on-flash-bbt;
+			status = "okay";
+		};
+
+		usb0: ohci@00500000 {
+			num-ports = <2>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0ff0d1d..3adfe7e 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -136,6 +136,10 @@ config TARGET_SMARTWEB
 	bool "Support smartweb"
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select DM_ETH
 
 config TARGET_VINCO
 	bool "Support VINCO"
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index 47a60a7..78a7946 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -17,23 +17,33 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_serial.h>
 #include <asm/arch/at91_spi.h>
 #include <spi.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <watchdog.h>
-#ifdef CONFIG_MACB
 # include <net.h>
+#ifndef CONFIG_DM_ETH
 # include <netdev.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void smartweb_request_gpio(void)
+{
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(AT91_PIN_PA26, "ena PHY");
+}
+
 static void smartweb_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -65,7 +75,6 @@ static void smartweb_nand_hw_init(void)
 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 
-#ifdef CONFIG_MACB
 static void smartweb_macb_hw_init(void)
 {
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
@@ -108,7 +117,6 @@ static void smartweb_macb_hw_init(void)
 	/* Initialize EMAC=MACB hardware */
 	at91_macb_hw_init();
 }
-#endif /* CONFIG_MACB */
 
 #ifdef CONFIG_USB_GADGET_AT91
 #include <linux/usb/at91_udc.h>
@@ -133,11 +141,13 @@ int board_early_init_f(void)
 {
 	/* enable this here, as we have SPL without serial support */
 	at91_seriald_hw_init();
+	smartweb_request_gpio();
 	return 0;
 }
 
 int board_init(void)
 {
+	smartweb_request_gpio();
 	/* power LED red */
 	at91_set_gpio_output(AT91_PIN_PC6, 0);
 	at91_set_gpio_output(AT91_PIN_PC7, 1);
@@ -157,9 +167,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	smartweb_nand_hw_init();
-#ifdef CONFIG_MACB
 	smartweb_macb_hw_init();
-#endif
 	return 0;
 }
 
@@ -171,12 +179,14 @@ int dram_init(void)
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 #ifdef CONFIG_MACB
 int board_eth_init(bd_t *bis)
 {
 	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 }
 #endif /* CONFIG_MACB */
+#endif
 
 #if defined(CONFIG_SPL_BUILD)
 #include <spl.h>
@@ -192,8 +202,9 @@ void matrix_init(void)
 			&mat->scfg[3]);
 }
 
-void spl_board_init(void)
+void at91_spl_board_init(void)
 {
+	smartweb_request_gpio();
 	/* power LED orange */
 	at91_set_gpio_output(AT91_PIN_PC6, 1);
 	at91_set_gpio_output(AT91_PIN_PC7, 1);
@@ -245,3 +256,12 @@ void mem_init(void)
 	sdramc_initialize(ATMEL_BASE_CS1, &setting);
 }
 #endif
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.platdata = &at91sam9260_serial_plat,
+};
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 1c29a29..cf8bff6 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SMARTWEB=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
@@ -16,13 +17,17 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Siemens AG"
 CONFIG_G_DNL_VENDOR_NUM=0x0908
 CONFIG_G_DNL_PRODUCT_NUM=0x02d2
-CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index fc4153a..6add391 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -45,7 +45,7 @@
 #define CONFIG_CMDLINE_TAG		/* pass commandline to Kernel */
 #define CONFIG_SETUP_MEMORY_TAGS	/* pass memory defs to kernel */
 #define CONFIG_INITRD_TAG		/* pass initrd param to kernel */
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY	/* U-Boot is loaded by a bootloader */
 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f() */
 #define CONFIG_DISPLAY_CPUINFO		/* display CPU Info at startup */
 
@@ -157,10 +157,6 @@
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-
 /* USB DFU support */
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE
-- 
cgit v0.10.2


From 8e6e8221c78ed283a45f8598c65ffe4d287dcf42 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Wed, 25 May 2016 07:23:48 +0200
Subject: arm: at91: taurus/axm: add DM and DTS support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

add DM and DTS support for the at91 based siemens
boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebased on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 63b86f1..5d463ce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -3,6 +3,7 @@
 #
 
 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \
+	at91sam9g20-taurus.dtb \
 	at91sam9g45-corvus.dtb \
 	at91sam9g45-gurnard.dtb
 
diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts
new file mode 100644
index 0000000..f27d772
--- /dev/null
+++ b/arch/arm/dts/at91sam9g20-taurus.dts
@@ -0,0 +1,119 @@
+/*
+ * at91sam9g20-taurus.dts
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+	model = "Siemens taurus";
+	compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
+
+	chosen {
+		stdout-path = &dbgu;
+	};
+
+	memory {
+		reg = <0x20000000 0x4000000>;
+	};
+
+	clocks {
+		slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal {
+			clock-frequency = <18432000>;
+		};
+	};
+
+	ahb {
+		apb {
+			pinctrl@fffff400 {
+				board {
+					pinctrl_pck0_as_mck: pck0_as_mck {
+						atmel,pins =
+							<AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC1 periph B */
+					};
+
+				};
+			};
+
+			dbgu: serial@fffff200 {
+				status = "okay";
+			};
+
+			usart0: serial@fffb0000 {
+				pinctrl-0 =
+					<&pinctrl_usart0
+					 &pinctrl_usart0_rts
+					 &pinctrl_usart0_cts
+					 &pinctrl_usart0_dtr_dsr
+					 &pinctrl_usart0_dcd
+					 &pinctrl_usart0_ri>;
+				status = "okay";
+			};
+
+			usart1: serial@fffb4000 {
+				status = "okay";
+			};
+
+			macb0: ethernet@fffc4000 {
+				phy-mode = "rmii";
+				status = "okay";
+			};
+
+			usb1: gadget@fffa4000 {
+				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+				status = "okay";
+			};
+
+			ssc0: ssc@fffbc000 {
+				status = "okay";
+				pinctrl-0 = <&pinctrl_ssc0_tx>;
+			};
+
+			spi0: spi@fffc8000 {
+				cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+				mtd_dataflash@0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					spi-max-frequency = <50000000>;
+					reg = <1>;
+				};
+			};
+
+			rtc@fffffd20 {
+				atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+				status = "okay";
+			};
+
+			watchdog@fffffd40 {
+				status = "okay";
+			};
+
+			gpbr: syscon@fffffd50 {
+				status = "okay";
+			};
+		};
+
+		nand0: nand@40000000 {
+			nand-bus-width = <8>;
+			nand-ecc-mode = "soft";
+			nand-on-flash-bbt;
+			status = "okay";
+		};
+
+		usb0: ohci@00500000 {
+			num-ports = <2>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3adfe7e..13e19ba 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -131,6 +131,10 @@ config TARGET_TAURUS
 	bool "Support taurus"
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select DM_ETH
 
 config TARGET_SMARTWEB
 	bool "Support smartweb"
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index b0385d8..8da24be 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -14,6 +14,7 @@
 
 #include <command.h>
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -21,17 +22,28 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/atmel_serial.h>
 #include <asm/arch/clk.h>
+#include <asm/gpio.h>
 #include <linux/mtd/nand.h>
 #include <atmel_mci.h>
 #include <asm/arch/at91_spi.h>
 #include <spi.h>
 
 #include <net.h>
+#ifndef CONFIG_DM_ETH
 #include <netdev.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void taurus_request_gpio(void)
+{
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+	gpio_request(AT91_PIN_PA25, "ena PHY");
+}
+
 static void taurus_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -265,6 +277,7 @@ int board_early_init_f(void)
 	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	at91_seriald_hw_init();
+	taurus_request_gpio();
 
 	return 0;
 }
@@ -308,6 +321,7 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+	taurus_request_gpio();
 #ifdef CONFIG_CMD_NAND
 	taurus_nand_hw_init();
 #endif
@@ -330,6 +344,7 @@ int dram_init(void)
 	return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
@@ -338,6 +353,7 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+#endif
 
 #if !defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_BOARD_AXM)
@@ -432,3 +448,12 @@ U_BOOT_CMD(
 );
 #endif
 #endif
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+	.name   = "serial_atmel",
+	.platdata = &at91sam9260_serial_plat,
+};
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 0e0eadf..d1f0c75 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -1,8 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TAURUS=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
+CONFIG_HUSH_PARSER=y
 CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
@@ -16,7 +18,8 @@ CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USE_TINY_PRINTF=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index e566f7f..f451515 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -1,8 +1,10 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TAURUS=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_HUSH_PARSER=y
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
@@ -19,6 +21,8 @@ CONFIG_CMD_DFU=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_USB=y
@@ -28,4 +32,3 @@ CONFIG_G_DNL_MANUFACTURER="Siemens AG"
 CONFIG_G_DNL_VENDOR_NUM=0x0908
 CONFIG_G_DNL_PRODUCT_NUM=0x02d2
 CONFIG_USE_TINY_PRINTF=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 0b05289..882a4e5 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -45,7 +45,7 @@
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
-- 
cgit v0.10.2


From ca2ec9adc951cc3798e9b0c3773cdcc613232a22 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Fri, 13 May 2016 23:37:44 +0900
Subject: mmc: dw_mmc: fix the wrong AND operation

These condition checking are wrong.
Original Author's intention might be "&" instead of "&&".
It can know whether receive or transmit data request with
BIT[4]/BIT[5] of RINTSTS register.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 74a2663..af6e04a 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -121,7 +121,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
 
 		if (host->fifo_mode && size) {
 			if (data->flags == MMC_DATA_READ) {
-				if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+				if ((dwmci_readl(host, DWMCI_RINTSTS) &
 				     DWMCI_INTMSK_RXDR)) {
 					len = dwmci_readl(host, DWMCI_STATUS);
 					len = (len >> DWMCI_FIFO_SHIFT) &
@@ -133,7 +133,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
 						     DWMCI_INTMSK_RXDR);
 				}
 			} else {
-				if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+				if ((dwmci_readl(host, DWMCI_RINTSTS) &
 				     DWMCI_INTMSK_TXDR)) {
 					len = dwmci_readl(host, DWMCI_STATUS);
 					len = fifo_depth - ((len >>
-- 
cgit v0.10.2


From 64ece84854ae49f40e9b9d4d88502247774f9d2f Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 11:19:35 -0700
Subject: fastboot: sparse: remove session-id logic

This "session-id" alogrithm is not required, and currently corrupts
the stored image whenever more the one "session" is required.

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index e3abcc8..9e53adb 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -97,9 +97,8 @@ static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
 	fastboot_okay(response_str, "");
 }
 
-void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
-			void *download_buffer, unsigned int download_bytes,
-			char *response)
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response)
 {
 	struct blk_desc *dev_desc;
 	disk_partition_t info;
@@ -153,8 +152,7 @@ void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
 		printf("Flashing sparse image at offset " LBAFU "\n",
 		       info.start);
 
-		store_sparse_image(&sparse, &sparse_priv, session_id,
-				   download_buffer);
+		store_sparse_image(&sparse, &sparse_priv, download_buffer);
 	} else {
 		write_raw_image(dev_desc, &info, cmd, download_buffer,
 				download_bytes);
diff --git a/common/fb_nand.c b/common/fb_nand.c
index ae34f48..a0a9839 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -126,7 +126,7 @@ static int fb_nand_sparse_write(struct sparse_storage *storage,
 	return written / storage->block_sz;
 }
 
-void fb_nand_flash_write(const char *partname, unsigned int session_id,
+void fb_nand_flash_write(const char *partname,
 			 void *download_buffer, unsigned int download_bytes,
 			 char *response)
 {
@@ -161,7 +161,7 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 		sparse.name = part->name;
 		sparse.write = fb_nand_sparse_write;
 
-		ret = store_sparse_image(&sparse, &sparse_priv, session_id,
+		ret = store_sparse_image(&sparse, &sparse_priv,
 					 download_buffer);
 	} else {
 		printf("Flashing raw image at offset 0x%llx\n",
diff --git a/common/image-sparse.c b/common/image-sparse.c
index 2bf737b..893c68b 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -52,8 +52,6 @@ typedef struct sparse_buffer {
 	u16	type;
 } sparse_buffer_t;
 
-static uint32_t last_offset;
-
 static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse,
 					       chunk_header_t *chunk)
 {
@@ -267,8 +265,8 @@ static void sparse_put_data_buffer(sparse_buffer_t *buffer)
 	free(buffer);
 }
 
-int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
-		       unsigned int session_id, void *data)
+int store_sparse_image(sparse_storage_t *storage,
+		       void *storage_priv, void *data)
 {
 	unsigned int chunk, offset;
 	sparse_header_t *sparse_header;
@@ -303,19 +301,10 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 		return -EINVAL;
 	}
 
-	/*
-	 * If it's a new flashing session, start at the beginning of
-	 * the partition. If not, then simply resume where we were.
-	 */
-	if (session_id > 0)
-		start = last_offset;
-	else
-		start = storage->start;
-
-	printf("Flashing sparse image on partition %s at offset 0x%x (ID: %d)\n",
-	       storage->name, start * storage->block_sz, session_id);
+	puts("Flashing Sparse Image\n");
 
 	/* Start processing chunks */
+	start = storage->start;
 	for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
 		uint32_t blkcnt;
 
@@ -390,7 +379,5 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 		return -EIO;
 	}
 
-	last_offset = start + total_blocks;
-
 	return 0;
 }
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 28b244a..ddf989c 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -59,7 +59,6 @@ static inline struct f_fastboot *func_to_fastboot(struct usb_function *f)
 }
 
 static struct f_fastboot *fastboot_func;
-static unsigned int fastboot_flash_session_id;
 static unsigned int download_size;
 static unsigned int download_bytes;
 
@@ -424,15 +423,6 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 
 		sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE);
 		strncat(response, str_num, chars_left);
-
-		/*
-		 * This also indicates the start of a new flashing
-		 * "session", in which we could have 1-N buffers to
-		 * write to a partition.
-		 *
-		 * Reset our session counter.
-		 */
-		fastboot_flash_session_id = 0;
 	} else if (!strcmp_l1("serialno", cmd)) {
 		s = getenv("serial#");
 		if (s)
@@ -600,16 +590,14 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
 
 	strcpy(response, "FAILno flash device defined");
 #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
-	fb_mmc_flash_write(cmd, fastboot_flash_session_id,
-			   (void *)CONFIG_FASTBOOT_BUF_ADDR,
+	fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR,
 			   download_bytes, response);
 #endif
 #ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
-	fb_nand_flash_write(cmd, fastboot_flash_session_id,
+	fb_nand_flash_write(cmd,
 			    (void *)CONFIG_FASTBOOT_BUF_ADDR,
 			    download_bytes, response);
 #endif
-	fastboot_flash_session_id++;
 	fastboot_tx_write_str(response);
 }
 #endif
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
index 978a139..402ba9b 100644
--- a/include/fb_mmc.h
+++ b/include/fb_mmc.h
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
-			void *download_buffer, unsigned int download_bytes,
-			char *response);
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response);
 void fb_mmc_erase(const char *cmd, char *response);
diff --git a/include/fb_nand.h b/include/fb_nand.h
index 80ddef5..88bdf36 100644
--- a/include/fb_nand.h
+++ b/include/fb_nand.h
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-void fb_nand_flash_write(const char *cmd, unsigned int session_id,
-			 void *download_buffer, unsigned int download_bytes,
-			 char *response);
+void fb_nand_flash_write(const char *cmd, void *download_buffer,
+			 unsigned int download_bytes, char *response);
 void fb_nand_erase(const char *cmd, char *response);
diff --git a/include/image-sparse.h b/include/image-sparse.h
index 0382f5b..a2b0694 100644
--- a/include/image-sparse.h
+++ b/include/image-sparse.h
@@ -32,4 +32,4 @@ static inline int is_sparse_image(void *buf)
 }
 
 int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
-		       unsigned int session_id, void *data);
+		       void *data);
-- 
cgit v0.10.2


From cc0f08cd347ea9741375a70c490c6bee684f7bac Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 11:19:36 -0700
Subject: fastboot: sparse: resync common/image-sparse.c (part 1)

This file originally came from upstream code.

While retaining the storage abstraction feature, this is the first
set of the changes required to resync with the
  cmd_flash_mmc_sparse_img()
in the file
  aboot.c
from
  https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 9e53adb..3dad0ea 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -7,12 +7,10 @@
 #include <config.h>
 #include <common.h>
 #include <blk.h>
-#include <errno.h>
 #include <fastboot.h>
 #include <fb_mmc.h>
 #include <image-sparse.h>
 #include <part.h>
-#include <sparse_format.h>
 #include <mmc.h>
 #include <div64.h>
 
@@ -48,22 +46,13 @@ static int part_get_info_efi_by_name_or_alias(struct blk_desc *dev_desc,
 	return ret;
 }
 
-
-static int fb_mmc_sparse_write(struct sparse_storage *storage,
-			       void *priv,
-			       unsigned int offset,
-			       unsigned int size,
-			       char *data)
+static lbaint_t fb_mmc_sparse_write(struct sparse_storage *info,
+		lbaint_t blk, lbaint_t blkcnt, const void *buffer)
 {
-	struct fb_mmc_sparse *sparse = priv;
+	struct fb_mmc_sparse *sparse = info->priv;
 	struct blk_desc *dev_desc = sparse->dev_desc;
-	int ret;
-
-	ret = blk_dwrite(dev_desc, offset, size, data);
-	if (!ret)
-		return -EIO;
 
-	return ret;
+	return blk_dwrite(dev_desc, blk, blkcnt, buffer);
 }
 
 static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
@@ -139,26 +128,25 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer,
 
 	if (is_sparse_image(download_buffer)) {
 		struct fb_mmc_sparse sparse_priv;
-		sparse_storage_t sparse;
+		struct sparse_storage sparse;
 
 		sparse_priv.dev_desc = dev_desc;
 
-		sparse.block_sz = info.blksz;
+		sparse.blksz = info.blksz;
 		sparse.start = info.start;
 		sparse.size = info.size;
-		sparse.name = cmd;
 		sparse.write = fb_mmc_sparse_write;
 
 		printf("Flashing sparse image at offset " LBAFU "\n",
-		       info.start);
+		       sparse.start);
 
-		store_sparse_image(&sparse, &sparse_priv, download_buffer);
+		sparse.priv = &sparse_priv;
+		write_sparse_image(&sparse, cmd, download_buffer,
+				   download_bytes, response_str);
 	} else {
 		write_raw_image(dev_desc, &info, cmd, download_buffer,
 				download_bytes);
 	}
-
-	fastboot_okay(response_str, "");
 }
 
 void fb_mmc_erase(const char *cmd, char *response)
diff --git a/common/fb_nand.c b/common/fb_nand.c
index a0a9839..bdfad17 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -10,7 +10,6 @@
 
 #include <fastboot.h>
 #include <image-sparse.h>
-#include <sparse_format.h>
 
 #include <linux/mtd/mtd.h>
 #include <jffs2/jffs2.h>
@@ -19,7 +18,7 @@
 static char *response_str;
 
 struct fb_nand_sparse {
-	struct mtd_info		*nand;
+	struct mtd_info		*mtd;
 	struct part_info	*part;
 };
 
@@ -105,30 +104,32 @@ static int _fb_nand_write(struct mtd_info *mtd, struct part_info *part,
 				   buffer, flags);
 }
 
-static int fb_nand_sparse_write(struct sparse_storage *storage,
-				void *priv,
-				unsigned int offset,
-				unsigned int size,
-				char *data)
+static lbaint_t fb_nand_sparse_write(struct sparse_storage *info,
+		lbaint_t blk, lbaint_t blkcnt, const void *buffer)
 {
-	struct fb_nand_sparse *sparse = priv;
+	struct fb_nand_sparse *sparse = info->priv;
 	size_t written;
 	int ret;
 
-	ret = _fb_nand_write(sparse->nand, sparse->part, data,
-			     offset * storage->block_sz,
-			     size * storage->block_sz, &written);
+	ret = _fb_nand_write(sparse->mtd, sparse->part, (void *)buffer,
+			     blk * info->blksz,
+			     blkcnt * info->blksz, &written);
 	if (ret < 0) {
 		printf("Failed to write sparse chunk\n");
 		return ret;
 	}
 
-	return written / storage->block_sz;
+/* TODO - verify that the value "written" includes the "bad-blocks" ... */
+
+	/*
+	 * the return value must be 'blkcnt' ("good-blocks") plus the
+	 * number of "bad-blocks" encountered within this space...
+	 */
+	return written / info->blksz;
 }
 
-void fb_nand_flash_write(const char *partname,
-			 void *download_buffer, unsigned int download_bytes,
-			 char *response)
+void fb_nand_flash_write(const char *cmd, void *download_buffer,
+			 unsigned int download_bytes, char *response)
 {
 	struct part_info *part;
 	struct mtd_info *mtd = NULL;
@@ -137,7 +138,7 @@ void fb_nand_flash_write(const char *partname,
 	/* initialize the response buffer */
 	response_str = response;
 
-	ret = fb_nand_lookup(partname, response, &mtd, &part);
+	ret = fb_nand_lookup(cmd, response, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
 		fastboot_fail(response_str, "invalid NAND device");
@@ -150,19 +151,22 @@ void fb_nand_flash_write(const char *partname,
 
 	if (is_sparse_image(download_buffer)) {
 		struct fb_nand_sparse sparse_priv;
-		sparse_storage_t sparse;
+		struct sparse_storage sparse;
 
-		sparse_priv.nand = mtd;
+		sparse_priv.mtd = mtd;
 		sparse_priv.part = part;
 
-		sparse.block_sz = mtd->writesize;
-		sparse.start = part->offset / sparse.block_sz;
-		sparse.size = part->size  / sparse.block_sz;
-		sparse.name = part->name;
+		sparse.blksz = mtd->writesize;
+		sparse.start = part->offset / sparse.blksz;
+		sparse.size = part->size / sparse.blksz;
 		sparse.write = fb_nand_sparse_write;
 
-		ret = store_sparse_image(&sparse, &sparse_priv,
-					 download_buffer);
+		printf("Flashing sparse image at offset " LBAFU "\n",
+		       sparse.start);
+
+		sparse.priv = &sparse_priv;
+		write_sparse_image(&sparse, cmd, download_buffer,
+				   download_bytes, response_str);
 	} else {
 		printf("Flashing raw image at offset 0x%llx\n",
 		       part->offset);
@@ -182,7 +186,7 @@ void fb_nand_flash_write(const char *partname,
 	fastboot_okay(response_str, "");
 }
 
-void fb_nand_erase(const char *partname, char *response)
+void fb_nand_erase(const char *cmd, char *response)
 {
 	struct part_info *part;
 	struct mtd_info *mtd = NULL;
@@ -191,7 +195,7 @@ void fb_nand_erase(const char *partname, char *response)
 	/* initialize the response buffer */
 	response_str = response;
 
-	ret = fb_nand_lookup(partname, response, &mtd, &part);
+	ret = fb_nand_lookup(cmd, response, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
 		fastboot_fail(response_str, "invalid NAND device");
diff --git a/common/image-sparse.c b/common/image-sparse.c
index 893c68b..924cc63 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -36,54 +36,44 @@
 
 #include <config.h>
 #include <common.h>
-#include <div64.h>
-#include <errno.h>
 #include <image-sparse.h>
+#include <div64.h>
 #include <malloc.h>
 #include <part.h>
 #include <sparse_format.h>
+#include <fastboot.h>
 
 #include <linux/math64.h>
 
-typedef struct sparse_buffer {
-	void	*data;
-	u32	length;
-	u32	repeat;
-	u16	type;
-} sparse_buffer_t;
-
-static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse,
-					       chunk_header_t *chunk)
+void write_sparse_image(
+		struct sparse_storage *info, const char *part_name,
+		void *data, unsigned sz, char *response_str)
 {
-	return chunk->total_sz - sparse->chunk_hdr_sz;
-}
-
-static unsigned int sparse_block_size_to_storage(unsigned int size,
-						 sparse_storage_t *storage,
-						 sparse_header_t *sparse)
-{
-	return (unsigned int)lldiv((uint64_t)size * sparse->blk_sz,
-				   storage->block_sz);
-}
-
-static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
-{
-	switch (chunk->chunk_type) {
-	case CHUNK_TYPE_RAW:
-	case CHUNK_TYPE_FILL:
-		return true;
-
-	default:
-		return false;
-	}
-}
+	lbaint_t blk;
+	lbaint_t blkcnt;
+	lbaint_t blks;
+	uint32_t bytes_written = 0;
+	unsigned int chunk;
+	unsigned int offset;
+	unsigned int chunk_data_sz;
+	uint32_t *fill_buf = NULL;
+	uint32_t fill_val;
+	sparse_header_t *sparse_header;
+	chunk_header_t *chunk_header;
+	uint32_t total_blocks = 0;
+	int i;
 
-static sparse_header_t *sparse_parse_header(void **data)
-{
 	/* Read and skip over sparse image header */
-	sparse_header_t *sparse_header = (sparse_header_t *) *data;
+	sparse_header = (sparse_header_t *)data;
 
-	*data += sparse_header->file_hdr_sz;
+	data += sparse_header->file_hdr_sz;
+	if (sparse_header->file_hdr_sz > sizeof(sparse_header_t)) {
+		/*
+		 * Skip the remaining bytes in a header that is longer than
+		 * we expected.
+		 */
+		data += (sparse_header->file_hdr_sz - sizeof(sparse_header_t));
+	}
 
 	debug("=== Sparse Image Header ===\n");
 	debug("magic: 0x%x\n", sparse_header->magic);
@@ -95,289 +85,164 @@ static sparse_header_t *sparse_parse_header(void **data)
 	debug("total_blks: %d\n", sparse_header->total_blks);
 	debug("total_chunks: %d\n", sparse_header->total_chunks);
 
-	return sparse_header;
-}
-
-static int sparse_parse_fill_chunk(sparse_header_t *sparse,
-				   chunk_header_t *chunk)
-{
-	unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-
-	if (chunk_data_sz != sizeof(uint32_t))
-		return -EINVAL;
-
-	return 0;
-}
-
-static int sparse_parse_raw_chunk(sparse_header_t *sparse,
-				  chunk_header_t *chunk)
-{
-	unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-
-	/* Check if the data size is a multiple of the main block size */
-	if (chunk_data_sz % sparse->blk_sz)
-		return -EINVAL;
-
-	/* Check that the chunk size is consistent */
-	if ((chunk_data_sz / sparse->blk_sz) != chunk->chunk_sz)
-		return -EINVAL;
-
-	return 0;
-}
-
-static chunk_header_t *sparse_parse_chunk(sparse_header_t *sparse,
-					  void **image)
-{
-	chunk_header_t *chunk = (chunk_header_t *) *image;
-	int ret;
-
-	debug("=== Chunk Header ===\n");
-	debug("chunk_type: 0x%x\n", chunk->chunk_type);
-	debug("chunk_data_sz: 0x%x\n", chunk->chunk_sz);
-	debug("total_size: 0x%x\n", chunk->total_sz);
-
-	switch (chunk->chunk_type) {
-	case CHUNK_TYPE_RAW:
-		ret = sparse_parse_raw_chunk(sparse, chunk);
-		if (ret)
-			return NULL;
-		break;
-
-	case CHUNK_TYPE_FILL:
-		ret = sparse_parse_fill_chunk(sparse, chunk);
-		if (ret)
-			return NULL;
-		break;
-
-	case CHUNK_TYPE_DONT_CARE:
-	case CHUNK_TYPE_CRC32:
-		debug("Ignoring chunk\n");
-		break;
-
-	default:
-		printf("%s: Unknown chunk type: %x\n", __func__,
-		       chunk->chunk_type);
-		return NULL;
-	}
-
-	*image += sparse->chunk_hdr_sz;
-
-	return chunk;
-}
-
-static int sparse_get_fill_buffer(sparse_header_t *sparse,
-				  chunk_header_t *chunk,
-				  sparse_buffer_t *buffer,
-				  unsigned int blk_sz,
-				  void *data)
-{
-	int i;
-
-	buffer->type = CHUNK_TYPE_FILL;
-
-	/*
-	 * We create a buffer of one block, and ask it to be
-	 * repeated as many times as needed.
-	 */
-	buffer->length = blk_sz;
-	buffer->repeat = (chunk->chunk_sz * sparse->blk_sz) / blk_sz;
-
-	buffer->data = memalign(ARCH_DMA_MINALIGN,
-				ROUNDUP(blk_sz,
-					ARCH_DMA_MINALIGN));
-	if (!buffer->data)
-		return -ENOMEM;
-
-	for (i = 0; i < (buffer->length / sizeof(uint32_t)); i++)
-		((uint32_t *)buffer->data)[i] = *(uint32_t *)(data);
-
-	return 0;
-}
-
-static int sparse_get_raw_buffer(sparse_header_t *sparse,
-				 chunk_header_t *chunk,
-				 sparse_buffer_t *buffer,
-				 unsigned int blk_sz,
-				 void *data)
-{
-	unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-
-	buffer->type = CHUNK_TYPE_RAW;
-	buffer->length = chunk_data_sz;
-	buffer->data = data;
-	buffer->repeat = 1;
-
-	return 0;
-}
-
-static sparse_buffer_t *sparse_get_data_buffer(sparse_header_t *sparse,
-					       chunk_header_t *chunk,
-					       unsigned int blk_sz,
-					       void **image)
-{
-	unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-	sparse_buffer_t *buffer;
-	void *data = *image;
-	int ret;
-
-	*image += chunk_data_sz;
-
-	if (!sparse_chunk_has_buffer(chunk))
-		return NULL;
-
-	buffer = calloc(sizeof(sparse_buffer_t), 1);
-	if (!buffer)
-		return NULL;
-
-	switch (chunk->chunk_type) {
-	case CHUNK_TYPE_RAW:
-		ret = sparse_get_raw_buffer(sparse, chunk, buffer, blk_sz,
-					    data);
-		if (ret)
-			return NULL;
-		break;
-
-	case CHUNK_TYPE_FILL:
-		ret = sparse_get_fill_buffer(sparse, chunk, buffer, blk_sz,
-					     data);
-		if (ret)
-			return NULL;
-		break;
-
-	default:
-		return NULL;
-	}
-
-	debug("=== Buffer ===\n");
-	debug("length: 0x%x\n", buffer->length);
-	debug("repeat: 0x%x\n", buffer->repeat);
-	debug("type: 0x%x\n", buffer->type);
-	debug("data: 0x%p\n", buffer->data);
-
-	return buffer;
-}
-
-static void sparse_put_data_buffer(sparse_buffer_t *buffer)
-{
-	if (buffer->type == CHUNK_TYPE_FILL)
-		free(buffer->data);
-
-	free(buffer);
-}
-
-int store_sparse_image(sparse_storage_t *storage,
-		       void *storage_priv, void *data)
-{
-	unsigned int chunk, offset;
-	sparse_header_t *sparse_header;
-	chunk_header_t *chunk_header;
-	sparse_buffer_t *buffer;
-	uint32_t start;
-	uint32_t total_blocks = 0;
-	int i;
-
-	debug("=== Storage ===\n");
-	debug("name: %s\n", storage->name);
-	debug("block_size: 0x%x\n", storage->block_sz);
-	debug("start: 0x%x\n", storage->start);
-	debug("size: 0x%x\n", storage->size);
-	debug("write: 0x%p\n", storage->write);
-	debug("priv: 0x%p\n", storage_priv);
-
-	sparse_header = sparse_parse_header(&data);
-	if (!sparse_header) {
-		printf("sparse header issue\n");
-		return -EINVAL;
-	}
-
 	/*
 	 * Verify that the sparse block size is a multiple of our
 	 * storage backend block size
 	 */
-	div_u64_rem(sparse_header->blk_sz, storage->block_sz, &offset);
+	div_u64_rem(sparse_header->blk_sz, info->blksz, &offset);
 	if (offset) {
 		printf("%s: Sparse image block size issue [%u]\n",
 		       __func__, sparse_header->blk_sz);
-		return -EINVAL;
+		fastboot_fail(response_str, "sparse image block size issue");
+		return;
 	}
 
 	puts("Flashing Sparse Image\n");
 
 	/* Start processing chunks */
-	start = storage->start;
+	blk = info->start;
 	for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
-		uint32_t blkcnt;
-
-		chunk_header = sparse_parse_chunk(sparse_header, &data);
-		if (!chunk_header) {
-			printf("Unknown chunk type");
-			return -EINVAL;
+		/* Read and skip over chunk header */
+		chunk_header = (chunk_header_t *)data;
+		data += sizeof(chunk_header_t);
+
+		if (chunk_header->chunk_type != CHUNK_TYPE_RAW) {
+			debug("=== Chunk Header ===\n");
+			debug("chunk_type: 0x%x\n", chunk_header->chunk_type);
+			debug("chunk_data_sz: 0x%x\n", chunk_header->chunk_sz);
+			debug("total_size: 0x%x\n", chunk_header->total_sz);
 		}
 
-		/*
-		 * If we have a DONT_CARE type, just skip the blocks
-		 * and go on parsing the rest of the chunks
-		 */
-		if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) {
-			blkcnt = sparse_block_size_to_storage(chunk_header->chunk_sz,
-							      storage,
-							      sparse_header);
-#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
-			total_blocks += blkcnt;
-#endif
-			continue;
+		if (sparse_header->chunk_hdr_sz > sizeof(chunk_header_t)) {
+			/*
+			 * Skip the remaining bytes in a header that is longer
+			 * than we expected.
+			 */
+			data += (sparse_header->chunk_hdr_sz -
+				 sizeof(chunk_header_t));
 		}
 
-		/* Retrieve the buffer we're going to write */
-		buffer = sparse_get_data_buffer(sparse_header, chunk_header,
-						storage->block_sz, &data);
-		if (!buffer)
-			continue;
+		chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
+		blkcnt = chunk_data_sz / info->blksz;
+		switch (chunk_header->chunk_type) {
+		case CHUNK_TYPE_RAW:
+			if (chunk_header->total_sz !=
+			    (sparse_header->chunk_hdr_sz + chunk_data_sz)) {
+				fastboot_fail(response_str,
+					"Bogus chunk size for chunk type Raw");
+				return;
+			}
+
+			if (blk + blkcnt > info->start + info->size) {
+				printf(
+				    "%s: Request would exceed partition size!\n",
+				    __func__);
+				fastboot_fail(response_str,
+				    "Request would exceed partition size!");
+				return;
+			}
 
-		blkcnt = (buffer->length / storage->block_sz) * buffer->repeat;
+			blks = info->write(info, blk, blkcnt, data);
+			/* blks might be > blkcnt (eg. NAND bad-blocks) */
+			if (blks < blkcnt) {
+				printf("%s: %s" LBAFU " [" LBAFU "]\n",
+				       __func__, "Write failed, block #",
+				       blk, blks);
+				fastboot_fail(response_str,
+					      "flash write failure");
+				return;
+			}
+			blk += blks;
+			bytes_written += blkcnt * info->blksz;
+			total_blocks += chunk_header->chunk_sz;
+			data += chunk_data_sz;
+			break;
+
+		case CHUNK_TYPE_FILL:
+			if (chunk_header->total_sz !=
+			    (sparse_header->chunk_hdr_sz + sizeof(uint32_t))) {
+				fastboot_fail(response_str,
+					"Bogus chunk size for chunk type FILL");
+				return;
+			}
 
-		if ((start + total_blocks + blkcnt) >
-		    (storage->start + storage->size)) {
-			printf("%s: Request would exceed partition size!\n",
-			       __func__);
-			return -EINVAL;
-		}
+			fill_buf = (uint32_t *)
+				   memalign(ARCH_DMA_MINALIGN,
+					    ROUNDUP(info->blksz,
+						    ARCH_DMA_MINALIGN));
+			if (!fill_buf) {
+				fastboot_fail(response_str,
+					"Malloc failed for: CHUNK_TYPE_FILL");
+				return;
+			}
 
-		for (i = 0; i < buffer->repeat; i++) {
-			unsigned long buffer_blk_cnt;
-			int ret;
+			fill_val = *(uint32_t *)data;
+			data = (char *)data + sizeof(uint32_t);
 
-			buffer_blk_cnt = buffer->length / storage->block_sz;
+			for (i = 0; i < (info->blksz / sizeof(fill_val)); i++)
+				fill_buf[i] = fill_val;
 
-			ret = storage->write(storage, storage_priv,
-					     start + total_blocks,
-					     buffer_blk_cnt,
-					     buffer->data);
-			if (ret < 0) {
-				printf("%s: Write %d failed %d\n",
-				       __func__, i, ret);
-				return ret;
+			if (blk + blkcnt > info->start + info->size) {
+				printf(
+				    "%s: Request would exceed partition size!\n",
+				    __func__);
+				fastboot_fail(response_str,
+				    "Request would exceed partition size!");
+				return;
 			}
 
-			total_blocks += ret;
-		}
+			for (i = 0; i < blkcnt; i++) {
+				blks = info->write(info, blk, 1, fill_buf);
+				/* blks might be > 1 (eg. NAND bad-blocks) */
+				if (blks < 1) {
+					printf("%s: %s, block # " LBAFU "\n",
+					       __func__, "Write failed", blk);
+					fastboot_fail(response_str,
+						      "flash write failure");
+					free(fill_buf);
+					return;
+				}
+				blk += blks;
+			}
+			bytes_written += blkcnt * info->blksz;
+			total_blocks += chunk_data_sz / sparse_header->blk_sz;
+			free(fill_buf);
+			break;
 
-		sparse_put_data_buffer(buffer);
+		case CHUNK_TYPE_DONT_CARE:
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+			blk += blkcnt;
+			total_blocks += chunk_header->chunk_sz;
+#endif
+			break;
+
+		case CHUNK_TYPE_CRC32:
+			if (chunk_header->total_sz !=
+			    sparse_header->chunk_hdr_sz) {
+				fastboot_fail(response_str,
+					"Bogus chunk size for chunk type Dont Care");
+				return;
+			}
+			total_blocks += chunk_header->chunk_sz;
+			data += chunk_data_sz;
+			break;
+
+		default:
+			printf("%s: Unknown chunk type: %x\n", __func__,
+			       chunk_header->chunk_type);
+			fastboot_fail(response_str, "Unknown chunk type");
+			return;
+		}
 	}
 
 	debug("Wrote %d blocks, expected to write %d blocks\n",
-	      total_blocks,
-	      sparse_block_size_to_storage(sparse_header->total_blks,
-					   storage, sparse_header));
-	printf("........ wrote %d blocks to '%s'\n", total_blocks,
-	       storage->name);
+	      total_blocks, sparse_header->total_blks);
+	printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
 
-	if (total_blocks !=
-	    sparse_block_size_to_storage(sparse_header->total_blks,
-					 storage, sparse_header)) {
-		printf("sparse image write failure\n");
-		return -EIO;
-	}
+	if (total_blocks != sparse_header->total_blks)
+		fastboot_fail(response_str, "sparse image write failure");
+	else
+		fastboot_okay(response_str, "");
 
-	return 0;
+	return;
 }
diff --git a/include/image-sparse.h b/include/image-sparse.h
index a2b0694..4e9e784 100644
--- a/include/image-sparse.h
+++ b/include/image-sparse.h
@@ -9,16 +9,17 @@
 
 #define ROUNDUP(x, y)	(((x) + ((y) - 1)) & ~((y) - 1))
 
-typedef struct sparse_storage {
-	unsigned int	block_sz;
-	unsigned int	start;
-	unsigned int	size;
-	const char	*name;
-
-	int	(*write)(struct sparse_storage *storage, void *priv,
-			 unsigned int offset, unsigned int size,
-			 char *data);
-} sparse_storage_t;
+struct sparse_storage {
+	lbaint_t	blksz;
+	lbaint_t	start;
+	lbaint_t	size;
+	void		*priv;
+
+	lbaint_t	(*write)(struct sparse_storage *info,
+				 lbaint_t blk,
+				 lbaint_t blkcnt,
+				 const void *buffer);
+};
 
 static inline int is_sparse_image(void *buf)
 {
@@ -31,5 +32,5 @@ static inline int is_sparse_image(void *buf)
 	return 0;
 }
 
-int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
-		       void *data);
+void write_sparse_image(struct sparse_storage *info, const char *part_name,
+			void *data, unsigned sz, char *response_str);
-- 
cgit v0.10.2


From 9bc34799c8e6d8907b18e02c405576aa6bf9ce15 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 11:19:37 -0700
Subject: fastboot: sparse: resync common/image-sparse.c (part 2)

- update fastboot_okay() and fastboot_fail()

This file originally came from upstream code.

While retaining the storage abstraction feature, this is the second
set of the changes required to resync with the
  cmd_flash_mmc_sparse_img()
in the file
  aboot.c
from
  https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 3dad0ea..6bafbc6 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -18,8 +18,6 @@
 #define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
 #endif
 
-static char *response_str;
-
 struct fb_mmc_sparse {
 	struct blk_desc	*dev_desc;
 };
@@ -68,7 +66,7 @@ static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
 
 	if (blkcnt > info->size) {
 		error("too large for partition: '%s'\n", part_name);
-		fastboot_fail(response_str, "too large for partition");
+		fastboot_fail("too large for partition");
 		return;
 	}
 
@@ -77,28 +75,25 @@ static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
 	blks = blk_dwrite(dev_desc, info->start, blkcnt, buffer);
 	if (blks != blkcnt) {
 		error("failed writing to device %d\n", dev_desc->devnum);
-		fastboot_fail(response_str, "failed writing to device");
+		fastboot_fail("failed writing to device");
 		return;
 	}
 
 	printf("........ wrote " LBAFU " bytes to '%s'\n", blkcnt * info->blksz,
 	       part_name);
-	fastboot_okay(response_str, "");
+	fastboot_okay("");
 }
 
 void fb_mmc_flash_write(const char *cmd, void *download_buffer,
-			unsigned int download_bytes, char *response)
+			unsigned int download_bytes)
 {
 	struct blk_desc *dev_desc;
 	disk_partition_t info;
 
-	/* initialize the response buffer */
-	response_str = response;
-
 	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
 	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
 		error("invalid mmc device\n");
-		fastboot_fail(response_str, "invalid mmc device");
+		fastboot_fail("invalid mmc device");
 		return;
 	}
 
@@ -108,21 +103,21 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer,
 		if (is_valid_gpt_buf(dev_desc, download_buffer)) {
 			printf("%s: invalid GPT - refusing to write to flash\n",
 			       __func__);
-			fastboot_fail(response_str, "invalid GPT partition");
+			fastboot_fail("invalid GPT partition");
 			return;
 		}
 		if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) {
 			printf("%s: writing GPT partitions failed\n", __func__);
-			fastboot_fail(response_str,
+			fastboot_fail(
 				      "writing GPT partitions failed");
 			return;
 		}
 		printf("........ success\n");
-		fastboot_okay(response_str, "");
+		fastboot_okay("");
 		return;
 	} else if (part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info)) {
 		error("cannot find partition: '%s'\n", cmd);
-		fastboot_fail(response_str, "cannot find partition");
+		fastboot_fail("cannot find partition");
 		return;
 	}
 
@@ -142,14 +137,14 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer,
 
 		sparse.priv = &sparse_priv;
 		write_sparse_image(&sparse, cmd, download_buffer,
-				   download_bytes, response_str);
+				   download_bytes);
 	} else {
 		write_raw_image(dev_desc, &info, cmd, download_buffer,
 				download_bytes);
 	}
 }
 
-void fb_mmc_erase(const char *cmd, char *response)
+void fb_mmc_erase(const char *cmd)
 {
 	int ret;
 	struct blk_desc *dev_desc;
@@ -159,24 +154,21 @@ void fb_mmc_erase(const char *cmd, char *response)
 
 	if (mmc == NULL) {
 		error("invalid mmc device");
-		fastboot_fail(response_str, "invalid mmc device");
+		fastboot_fail("invalid mmc device");
 		return;
 	}
 
-	/* initialize the response buffer */
-	response_str = response;
-
 	dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
 	if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
 		error("invalid mmc device");
-		fastboot_fail(response_str, "invalid mmc device");
+		fastboot_fail("invalid mmc device");
 		return;
 	}
 
 	ret = part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info);
 	if (ret) {
 		error("cannot find partition: '%s'", cmd);
-		fastboot_fail(response_str, "cannot find partition");
+		fastboot_fail("cannot find partition");
 		return;
 	}
 
@@ -195,11 +187,11 @@ void fb_mmc_erase(const char *cmd, char *response)
 	blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
 	if (blks != blks_size) {
 		error("failed erasing from device %d", dev_desc->devnum);
-		fastboot_fail(response_str, "failed erasing from device");
+		fastboot_fail("failed erasing from device");
 		return;
 	}
 
 	printf("........ erased " LBAFU " bytes from '%s'\n",
 	       blks_size * info.blksz, cmd);
-	fastboot_okay(response_str, "");
+	fastboot_okay("");
 }
diff --git a/common/fb_nand.c b/common/fb_nand.c
index bdfad17..77ca55d 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -15,8 +15,6 @@
 #include <jffs2/jffs2.h>
 #include <nand.h>
 
-static char *response_str;
-
 struct fb_nand_sparse {
 	struct mtd_info		*mtd;
 	struct part_info	*part;
@@ -32,7 +30,7 @@ __weak int board_fastboot_write_partition_setup(char *name)
 	return 0;
 }
 
-static int fb_nand_lookup(const char *partname, char *response,
+static int fb_nand_lookup(const char *partname,
 			  struct mtd_info **mtd,
 			  struct part_info **part)
 {
@@ -43,21 +41,21 @@ static int fb_nand_lookup(const char *partname, char *response,
 	ret = mtdparts_init();
 	if (ret) {
 		error("Cannot initialize MTD partitions\n");
-		fastboot_fail(response_str, "cannot init mtdparts");
+		fastboot_fail("cannot init mtdparts");
 		return ret;
 	}
 
 	ret = find_dev_and_part(partname, &dev, &pnum, part);
 	if (ret) {
 		error("cannot find partition: '%s'", partname);
-		fastboot_fail(response_str, "cannot find partition");
+		fastboot_fail("cannot find partition");
 		return ret;
 	}
 
 	if (dev->id->type != MTD_DEV_TYPE_NAND) {
 		error("partition '%s' is not stored on a NAND device",
 		      partname);
-		fastboot_fail(response_str, "not a NAND device");
+		fastboot_fail("not a NAND device");
 		return -EINVAL;
 	}
 
@@ -129,19 +127,16 @@ static lbaint_t fb_nand_sparse_write(struct sparse_storage *info,
 }
 
 void fb_nand_flash_write(const char *cmd, void *download_buffer,
-			 unsigned int download_bytes, char *response)
+			 unsigned int download_bytes)
 {
 	struct part_info *part;
 	struct mtd_info *mtd = NULL;
 	int ret;
 
-	/* initialize the response buffer */
-	response_str = response;
-
-	ret = fb_nand_lookup(cmd, response, &mtd, &part);
+	ret = fb_nand_lookup(cmd, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
-		fastboot_fail(response_str, "invalid NAND device");
+		fastboot_fail("invalid NAND device");
 		return;
 	}
 
@@ -166,7 +161,7 @@ void fb_nand_flash_write(const char *cmd, void *download_buffer,
 
 		sparse.priv = &sparse_priv;
 		write_sparse_image(&sparse, cmd, download_buffer,
-				   download_bytes, response_str);
+				   download_bytes);
 	} else {
 		printf("Flashing raw image at offset 0x%llx\n",
 		       part->offset);
@@ -179,26 +174,23 @@ void fb_nand_flash_write(const char *cmd, void *download_buffer,
 	}
 
 	if (ret) {
-		fastboot_fail(response_str, "error writing the image");
+		fastboot_fail("error writing the image");
 		return;
 	}
 
-	fastboot_okay(response_str, "");
+	fastboot_okay("");
 }
 
-void fb_nand_erase(const char *cmd, char *response)
+void fb_nand_erase(const char *cmd)
 {
 	struct part_info *part;
 	struct mtd_info *mtd = NULL;
 	int ret;
 
-	/* initialize the response buffer */
-	response_str = response;
-
-	ret = fb_nand_lookup(cmd, response, &mtd, &part);
+	ret = fb_nand_lookup(cmd, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
-		fastboot_fail(response_str, "invalid NAND device");
+		fastboot_fail("invalid NAND device");
 		return;
 	}
 
@@ -209,9 +201,9 @@ void fb_nand_erase(const char *cmd, char *response)
 	ret = _fb_nand_erase(mtd, part);
 	if (ret) {
 		error("failed erasing from device %s", mtd->name);
-		fastboot_fail(response_str, "failed erasing from device");
+		fastboot_fail("failed erasing from device");
 		return;
 	}
 
-	fastboot_okay(response_str, "");
+	fastboot_okay("");
 }
diff --git a/common/image-sparse.c b/common/image-sparse.c
index 924cc63..b36703b 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -47,7 +47,7 @@
 
 void write_sparse_image(
 		struct sparse_storage *info, const char *part_name,
-		void *data, unsigned sz, char *response_str)
+		void *data, unsigned sz)
 {
 	lbaint_t blk;
 	lbaint_t blkcnt;
@@ -93,7 +93,7 @@ void write_sparse_image(
 	if (offset) {
 		printf("%s: Sparse image block size issue [%u]\n",
 		       __func__, sparse_header->blk_sz);
-		fastboot_fail(response_str, "sparse image block size issue");
+		fastboot_fail("sparse image block size issue");
 		return;
 	}
 
@@ -128,7 +128,7 @@ void write_sparse_image(
 		case CHUNK_TYPE_RAW:
 			if (chunk_header->total_sz !=
 			    (sparse_header->chunk_hdr_sz + chunk_data_sz)) {
-				fastboot_fail(response_str,
+				fastboot_fail(
 					"Bogus chunk size for chunk type Raw");
 				return;
 			}
@@ -137,7 +137,7 @@ void write_sparse_image(
 				printf(
 				    "%s: Request would exceed partition size!\n",
 				    __func__);
-				fastboot_fail(response_str,
+				fastboot_fail(
 				    "Request would exceed partition size!");
 				return;
 			}
@@ -148,7 +148,7 @@ void write_sparse_image(
 				printf("%s: %s" LBAFU " [" LBAFU "]\n",
 				       __func__, "Write failed, block #",
 				       blk, blks);
-				fastboot_fail(response_str,
+				fastboot_fail(
 					      "flash write failure");
 				return;
 			}
@@ -161,7 +161,7 @@ void write_sparse_image(
 		case CHUNK_TYPE_FILL:
 			if (chunk_header->total_sz !=
 			    (sparse_header->chunk_hdr_sz + sizeof(uint32_t))) {
-				fastboot_fail(response_str,
+				fastboot_fail(
 					"Bogus chunk size for chunk type FILL");
 				return;
 			}
@@ -171,7 +171,7 @@ void write_sparse_image(
 					    ROUNDUP(info->blksz,
 						    ARCH_DMA_MINALIGN));
 			if (!fill_buf) {
-				fastboot_fail(response_str,
+				fastboot_fail(
 					"Malloc failed for: CHUNK_TYPE_FILL");
 				return;
 			}
@@ -186,7 +186,7 @@ void write_sparse_image(
 				printf(
 				    "%s: Request would exceed partition size!\n",
 				    __func__);
-				fastboot_fail(response_str,
+				fastboot_fail(
 				    "Request would exceed partition size!");
 				return;
 			}
@@ -197,7 +197,7 @@ void write_sparse_image(
 				if (blks < 1) {
 					printf("%s: %s, block # " LBAFU "\n",
 					       __func__, "Write failed", blk);
-					fastboot_fail(response_str,
+					fastboot_fail(
 						      "flash write failure");
 					free(fill_buf);
 					return;
@@ -219,7 +219,7 @@ void write_sparse_image(
 		case CHUNK_TYPE_CRC32:
 			if (chunk_header->total_sz !=
 			    sparse_header->chunk_hdr_sz) {
-				fastboot_fail(response_str,
+				fastboot_fail(
 					"Bogus chunk size for chunk type Dont Care");
 				return;
 			}
@@ -230,7 +230,7 @@ void write_sparse_image(
 		default:
 			printf("%s: Unknown chunk type: %x\n", __func__,
 			       chunk_header->chunk_type);
-			fastboot_fail(response_str, "Unknown chunk type");
+			fastboot_fail("Unknown chunk type");
 			return;
 		}
 	}
@@ -240,9 +240,9 @@ void write_sparse_image(
 	printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
 
 	if (total_blocks != sparse_header->total_blks)
-		fastboot_fail(response_str, "sparse image write failure");
+		fastboot_fail("sparse image write failure");
 	else
-		fastboot_okay(response_str, "");
+		fastboot_okay("");
 
 	return;
 }
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index ddf989c..2160b1c 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -151,16 +151,18 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
 static int strcmp_l1(const char *s1, const char *s2);
 
 
-void fastboot_fail(char *response, const char *reason)
+static char *fb_response_str;
+
+void fastboot_fail(const char *reason)
 {
-	strncpy(response, "FAIL\0", 5);
-	strncat(response, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
+	strncpy(fb_response_str, "FAIL\0", 5);
+	strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
 }
 
-void fastboot_okay(char *response, const char *reason)
+void fastboot_okay(const char *reason)
 {
-	strncpy(response, "OKAY\0", 5);
-	strncat(response, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
+	strncpy(fb_response_str, "OKAY\0", 5);
+	strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
 }
 
 static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
@@ -588,15 +590,18 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
 		return;
 	}
 
-	strcpy(response, "FAILno flash device defined");
+	/* initialize the response buffer */
+	fb_response_str = response;
+
+	fastboot_fail("no flash device defined");
 #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
 	fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR,
-			   download_bytes, response);
+			   download_bytes);
 #endif
 #ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
 	fb_nand_flash_write(cmd,
 			    (void *)CONFIG_FASTBOOT_BUF_ADDR,
-			    download_bytes, response);
+			    download_bytes);
 #endif
 	fastboot_tx_write_str(response);
 }
@@ -637,13 +642,15 @@ static void cb_erase(struct usb_ep *ep, struct usb_request *req)
 		return;
 	}
 
-	strcpy(response, "FAILno flash device defined");
+	/* initialize the response buffer */
+	fb_response_str = response;
 
+	fastboot_fail("no flash device defined");
 #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
-	fb_mmc_erase(cmd, response);
+	fb_mmc_erase(cmd);
 #endif
 #ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
-	fb_nand_erase(cmd, response);
+	fb_nand_erase(cmd);
 #endif
 	fastboot_tx_write_str(response);
 }
diff --git a/include/fastboot.h b/include/fastboot.h
index db826d2..616631e 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -16,7 +16,7 @@
 /* The 64 defined bytes plus \0 */
 #define FASTBOOT_RESPONSE_LEN	(64 + 1)
 
-void fastboot_fail(char *response, const char *reason);
-void fastboot_okay(char *response, const char *reason);
+void fastboot_fail(const char *reason);
+void fastboot_okay(const char *reason);
 
 #endif /* _FASTBOOT_H_ */
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
index 402ba9b..12b99cb 100644
--- a/include/fb_mmc.h
+++ b/include/fb_mmc.h
@@ -5,5 +5,5 @@
  */
 
 void fb_mmc_flash_write(const char *cmd, void *download_buffer,
-			unsigned int download_bytes, char *response);
-void fb_mmc_erase(const char *cmd, char *response);
+			unsigned int download_bytes);
+void fb_mmc_erase(const char *cmd);
diff --git a/include/fb_nand.h b/include/fb_nand.h
index 88bdf36..aaf7cf7 100644
--- a/include/fb_nand.h
+++ b/include/fb_nand.h
@@ -6,5 +6,5 @@
  */
 
 void fb_nand_flash_write(const char *cmd, void *download_buffer,
-			 unsigned int download_bytes, char *response);
-void fb_nand_erase(const char *cmd, char *response);
+			 unsigned int download_bytes);
+void fb_nand_erase(const char *cmd);
diff --git a/include/image-sparse.h b/include/image-sparse.h
index 4e9e784..f6869d6 100644
--- a/include/image-sparse.h
+++ b/include/image-sparse.h
@@ -33,4 +33,4 @@ static inline int is_sparse_image(void *buf)
 }
 
 void write_sparse_image(struct sparse_storage *info, const char *part_name,
-			void *data, unsigned sz, char *response_str);
+			void *data, unsigned sz);
-- 
cgit v0.10.2


From 2c72404687f1061d042769cc65ef90e6c3da3f96 Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 11:19:38 -0700
Subject: fastboot: sparse: implement reserve()

In order to process the CHUNK_TYPE_DONT_CARE properly, there is
a requirement to be able to 'reserve' a specified number of blocks
in the storage media. Because of the special handling of "bad blocks"
in NAND devices, this is implemented in a storage abstraction function.

Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 6bafbc6..c739651 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -53,6 +53,12 @@ static lbaint_t fb_mmc_sparse_write(struct sparse_storage *info,
 	return blk_dwrite(dev_desc, blk, blkcnt, buffer);
 }
 
+static lbaint_t fb_mmc_sparse_reserve(struct sparse_storage *info,
+		lbaint_t blk, lbaint_t blkcnt)
+{
+	return blkcnt;
+}
+
 static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
 		const char *part_name, void *buffer,
 		unsigned int download_bytes)
@@ -131,6 +137,7 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer,
 		sparse.start = info.start;
 		sparse.size = info.size;
 		sparse.write = fb_mmc_sparse_write;
+		sparse.reserve = fb_mmc_sparse_reserve;
 
 		printf("Flashing sparse image at offset " LBAFU "\n",
 		       sparse.start);
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 77ca55d..c8c79e9 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -126,6 +126,25 @@ static lbaint_t fb_nand_sparse_write(struct sparse_storage *info,
 	return written / info->blksz;
 }
 
+static lbaint_t fb_nand_sparse_reserve(struct sparse_storage *info,
+		lbaint_t blk, lbaint_t blkcnt)
+{
+	int bad_blocks = 0;
+
+/*
+ * TODO - implement a function to determine the total number
+ * of blocks which must be used in order to reserve the specified
+ * number ("blkcnt") of "good-blocks", starting at "blk"...
+ * ( possibly something like the "check_skip_len()" function )
+ */
+
+	/*
+	 * the return value must be 'blkcnt' ("good-blocks") plus the
+	 * number of "bad-blocks" encountered within this space...
+	 */
+	return blkcnt + bad_blocks;
+}
+
 void fb_nand_flash_write(const char *cmd, void *download_buffer,
 			 unsigned int download_bytes)
 {
@@ -155,6 +174,7 @@ void fb_nand_flash_write(const char *cmd, void *download_buffer,
 		sparse.start = part->offset / sparse.blksz;
 		sparse.size = part->size / sparse.blksz;
 		sparse.write = fb_nand_sparse_write;
+		sparse.reserve = fb_nand_sparse_reserve;
 
 		printf("Flashing sparse image at offset " LBAFU "\n",
 		       sparse.start);
diff --git a/common/image-sparse.c b/common/image-sparse.c
index b36703b..9632c6f 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -1,3 +1,4 @@
+
 /*
  * Copyright (c) 2009, Google Inc.
  * All rights reserved.
@@ -210,10 +211,8 @@ void write_sparse_image(
 			break;
 
 		case CHUNK_TYPE_DONT_CARE:
-#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
-			blk += blkcnt;
+			blk += info->reserve(info, blk, blkcnt);
 			total_blocks += chunk_header->chunk_sz;
-#endif
 			break;
 
 		case CHUNK_TYPE_CRC32:
diff --git a/include/image-sparse.h b/include/image-sparse.h
index f6869d6..b0cc500 100644
--- a/include/image-sparse.h
+++ b/include/image-sparse.h
@@ -19,6 +19,10 @@ struct sparse_storage {
 				 lbaint_t blk,
 				 lbaint_t blkcnt,
 				 const void *buffer);
+
+	lbaint_t	(*reserve)(struct sparse_storage *info,
+				 lbaint_t blk,
+				 lbaint_t blkcnt);
 };
 
 static inline int is_sparse_image(void *buf)
-- 
cgit v0.10.2


From 0abd63b26de890dc3ea8d70f2022fd587cdc686b Mon Sep 17 00:00:00 2001
From: Steve Rae <srae@broadcom.com>
Date: Tue, 7 Jun 2016 11:19:39 -0700
Subject: fastboot: sparse: improve CHUNK_TYPE_FILL write performance

- increase the size of the fill buffer
- testing has shown a 10x improvement when the sparse image
  has large CHUNK_TYPE_FILL chunks

Signed-off-by: Steve Rae <srae@broadcom.com>

diff --git a/common/image-sparse.c b/common/image-sparse.c
index 9632c6f..ddf5772 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -1,4 +1,3 @@
-
 /*
  * Copyright (c) 2009, Google Inc.
  * All rights reserved.
@@ -46,6 +45,10 @@
 
 #include <linux/math64.h>
 
+#ifndef CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE
+#define CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE (1024 * 512)
+#endif
+
 void write_sparse_image(
 		struct sparse_storage *info, const char *part_name,
 		void *data, unsigned sz)
@@ -62,7 +65,11 @@ void write_sparse_image(
 	sparse_header_t *sparse_header;
 	chunk_header_t *chunk_header;
 	uint32_t total_blocks = 0;
+	int fill_buf_num_blks;
 	int i;
+	int j;
+
+	fill_buf_num_blks = CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE / info->blksz;
 
 	/* Read and skip over sparse image header */
 	sparse_header = (sparse_header_t *)data;
@@ -169,8 +176,9 @@ void write_sparse_image(
 
 			fill_buf = (uint32_t *)
 				   memalign(ARCH_DMA_MINALIGN,
-					    ROUNDUP(info->blksz,
-						    ARCH_DMA_MINALIGN));
+					    ROUNDUP(
+						info->blksz * fill_buf_num_blks,
+						ARCH_DMA_MINALIGN));
 			if (!fill_buf) {
 				fastboot_fail(
 					"Malloc failed for: CHUNK_TYPE_FILL");
@@ -180,7 +188,10 @@ void write_sparse_image(
 			fill_val = *(uint32_t *)data;
 			data = (char *)data + sizeof(uint32_t);
 
-			for (i = 0; i < (info->blksz / sizeof(fill_val)); i++)
+			for (i = 0;
+			     i < (info->blksz * fill_buf_num_blks /
+				  sizeof(fill_val));
+			     i++)
 				fill_buf[i] = fill_val;
 
 			if (blk + blkcnt > info->start + info->size) {
@@ -192,18 +203,24 @@ void write_sparse_image(
 				return;
 			}
 
-			for (i = 0; i < blkcnt; i++) {
-				blks = info->write(info, blk, 1, fill_buf);
-				/* blks might be > 1 (eg. NAND bad-blocks) */
-				if (blks < 1) {
-					printf("%s: %s, block # " LBAFU "\n",
-					       __func__, "Write failed", blk);
+			for (i = 0; i < blkcnt;) {
+				j = blkcnt - i;
+				if (j > fill_buf_num_blks)
+					j = fill_buf_num_blks;
+				blks = info->write(info, blk, j, fill_buf);
+				/* blks might be > j (eg. NAND bad-blocks) */
+				if (blks < j) {
+					printf("%s: %s " LBAFU " [%d]\n",
+					       __func__,
+					       "Write failed, block #",
+					       blk, j);
 					fastboot_fail(
 						      "flash write failure");
 					free(fill_buf);
 					return;
 				}
 				blk += blks;
+				i += j;
 			}
 			bytes_written += blkcnt * info->blksz;
 			total_blocks += chunk_data_sz / sparse_header->blk_sz;
-- 
cgit v0.10.2


From 4a9a3292771e80a9be37af147f4efcd2fd99e8d7 Mon Sep 17 00:00:00 2001
From: Steve Rae <steve.rae@raedomain.com>
Date: Mon, 27 Jun 2016 16:11:32 -0700
Subject: maintainers: new email address

Update the email address for the boards that I maintain.

Signed-off-by: Steve Rae <steve.rae@raedomain.com>

diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS
index b22e86f..5478350 100644
--- a/board/broadcom/bcm11130/MAINTAINERS
+++ b/board/broadcom/bcm11130/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM11130 BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcm28155_ap/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS
index 881db5b..4cf66b7 100644
--- a/board/broadcom/bcm11130_nand/MAINTAINERS
+++ b/board/broadcom/bcm11130_nand/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM11130_NAND BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcm28155_ap/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm23550_w1d/MAINTAINERS b/board/broadcom/bcm23550_w1d/MAINTAINERS
index fdaa539..bde6337 100644
--- a/board/broadcom/bcm23550_w1d/MAINTAINERS
+++ b/board/broadcom/bcm23550_w1d/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM23550_W1D BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcm23550_w1d/
 F:	include/configs/bcm23550_w1d.h
diff --git a/board/broadcom/bcm28155_ap/MAINTAINERS b/board/broadcom/bcm28155_ap/MAINTAINERS
index a74c394..e1e99d0 100644
--- a/board/broadcom/bcm28155_ap/MAINTAINERS
+++ b/board/broadcom/bcm28155_ap/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM28155_AP BOARD
-M:	Tim Kryger <tim.kryger@linaro.org>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcm28155_ap/
 F:	include/configs/bcm28155_ap.h
diff --git a/board/broadcom/bcm28155_w1d/MAINTAINERS b/board/broadcom/bcm28155_w1d/MAINTAINERS
index a436490..c0558e7 100644
--- a/board/broadcom/bcm28155_w1d/MAINTAINERS
+++ b/board/broadcom/bcm28155_w1d/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM28155_W1D BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcm28155_ap/
 F:	include/configs/bcm28155_ap.h
diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
index b5f0207..8b831d8 100644
--- a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
+++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM911360_ENTPHN-NS BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmcygnus/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS b/board/broadcom/bcm911360_entphn/MAINTAINERS
index fb7ee2b..d4f6aef 100644
--- a/board/broadcom/bcm911360_entphn/MAINTAINERS
+++ b/board/broadcom/bcm911360_entphn/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM911360_ENTPHN BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmcygnus/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm911360k/MAINTAINERS b/board/broadcom/bcm911360k/MAINTAINERS
index 754a15f..32e6032 100644
--- a/board/broadcom/bcm911360k/MAINTAINERS
+++ b/board/broadcom/bcm911360k/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM911360K BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmcygnus/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS b/board/broadcom/bcm958300k-ns/MAINTAINERS
index 763401a..237d344 100644
--- a/board/broadcom/bcm958300k-ns/MAINTAINERS
+++ b/board/broadcom/bcm958300k-ns/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM958300K-NS BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmcygnus/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS
index 8afc728..bbb6d64 100644
--- a/board/broadcom/bcm958300k/MAINTAINERS
+++ b/board/broadcom/bcm958300k/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM958300K BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmcygnus/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm958305k/MAINTAINERS b/board/broadcom/bcm958305k/MAINTAINERS
index 179fd4e..5ca0eff 100644
--- a/board/broadcom/bcm958305k/MAINTAINERS
+++ b/board/broadcom/bcm958305k/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM958305K BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmcygnus/
 F:	include/configs/bcm_ep_board.h
diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS
index d08aded..de44dd1 100644
--- a/board/broadcom/bcm958622hr/MAINTAINERS
+++ b/board/broadcom/bcm958622hr/MAINTAINERS
@@ -1,5 +1,5 @@
 BCM958622HR BOARD
-M:	Steve Rae <srae@broadcom.com>
+M:	Steve Rae <steve.rae@raedomain.com>
 S:	Maintained
 F:	board/broadcom/bcmnsp/
 F:	include/configs/bcm_ep_board.h
-- 
cgit v0.10.2


From d14739ffe16092323f838b8d3f61796afe083810 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Fri, 17 Jun 2016 17:39:50 +0800
Subject: Kconfig: make NOR_BOOT a common option

Not only am335x supports booting from NOR, i.MX6 SoCs also
supports booting from NOR. Make NOR_BOOT a common
option to let different SoCs share it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 11ef3ca..97374bd 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -29,15 +29,6 @@ config NOR
 	  In practice this is seen as a NOR flash module connected to the
 	  "memory cape" for the BeagleBone family.
 
-config NOR_BOOT
-	bool "Support for booting from NOR flash"
-	depends on NOR
-	help
-	  Enabling this will make a U-Boot binary that is capable of being
-	  booted via NOR.  In this case we will enable certain pinmux early
-	  as the ROM only partially sets up pinmux.  We also default to using
-	  NOR for environment.
-
 source "board/ti/common/Kconfig"
 
 endif
diff --git a/common/Kconfig b/common/Kconfig
index ada4ddb..6f301e7 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -97,6 +97,19 @@ config BOOTSTAGE_STASH_SIZE
 
 endmenu
 
+menu "Boot media"
+
+config NOR_BOOT
+	bool "Support for booting from NOR flash"
+	depends on NOR
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via NOR.  In this case we will enable certain pinmux early
+	  as the ROM only partially sets up pinmux.  We also default to using
+	  NOR for environment.
+
+endmenu
+
 config BOOTDELAY
 	int "delay in seconds before automatically booting"
 	default 2
-- 
cgit v0.10.2


From faaef73f7eedaaeed12ffbc95dd7b4b7411a3af5 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Fri, 17 Jun 2016 17:39:51 +0800
Subject: common: add new boot media kconfig entry

Add CONFIG_{SD|NAND|ONENAND|SPI|QSPI|SATA}_BOOT kconfig entries.

SoCs supports loading U-Boot from different medias to DRAM, such as
i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
and etc. For i.MX, imximage will generate different IVT headers according
to boot medias.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>

diff --git a/common/Kconfig b/common/Kconfig
index 6f301e7..af7ead8 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -108,6 +108,54 @@ config NOR_BOOT
 	  as the ROM only partially sets up pinmux.  We also default to using
 	  NOR for environment.
 
+config NAND_BOOT
+	bool "Support for booting from NAND flash"
+	default n
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via NAND flash. This is not a must, some SoCs need this,
+	  somes not.
+
+config ONENAND_BOOT
+	bool "Support for booting from ONENAND"
+	default n
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via ONENAND. This is not a must, some SoCs need this,
+	  somes not.
+
+config QSPI_BOOT
+	bool "Support for booting from QSPI flash"
+	default n
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via QSPI flash. This is not a must, some SoCs need this,
+	  somes not.
+
+config SATA_BOOT
+	bool "Support for booting from SATA"
+	default n
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via SATA. This is not a must, some SoCs need this,
+	  somes not.
+
+config SD_BOOT
+	bool "Support for booting from SD/EMMC"
+	default n
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via SD/EMMC. This is not a must, some SoCs need this,
+	  somes not.
+
+config SPI_BOOT
+	bool "Support for booting from SPI flash"
+	default n
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via SPI flash. This is not a must, some SoCs need this,
+	  somes not.
+
 endmenu
 
 config BOOTDELAY
-- 
cgit v0.10.2


From 581ff00bf7d276dadaa793aa1fc20b54d7b89e6a Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Mon, 13 Jun 2016 11:20:31 +0800
Subject: armv8: ls1043aqds: use configurable clock

Get the clocks from FPGA through I2C, if IFC is disabled.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 9447c93..b7e9c21 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -230,6 +230,10 @@ int board_early_init_f(void)
 #ifdef CONFIG_LPUART
 	u8 uart;
 #endif
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch2_early_init_f();
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index a19eaee..520b28c 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -29,8 +29,8 @@ unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 
-#define CONFIG_SYS_CLK_FREQ		100000000
-#define CONFIG_DDR_CLK_FREQ		100000000
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -225,6 +225,7 @@ unsigned long get_board_ddr_clk(void);
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
 #define CONFIG_SYS_NO_FLASH
 #endif
 
-- 
cgit v0.10.2


From 68aaa980c488696fa6f71109e53e819b02455e33 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Mon, 13 Jun 2016 11:20:32 +0800
Subject: armv8: ls1043aqds: print FPGA info early for QSPI boot

Now I2C is initialized early enough to access FPGA so it supports to
show board info as early as other boot methods.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 520b28c..ee8cb23 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -10,11 +10,7 @@
 #include "ls1043a_common.h"
 
 #define CONFIG_DISPLAY_CPUINFO
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#else
 #define CONFIG_DISPLAY_BOARDINFO
-#endif
 
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE		0x82000000
-- 
cgit v0.10.2


From f53225cce406058c09cf81456d9dc4956fef1b73 Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 15 Jun 2016 10:53:00 +0800
Subject: mmc: fsl: reset to normal boot mode when eMMC fast boot

When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index b7b4f14..bfbef66 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -56,21 +56,27 @@ struct fsl_esdhc {
 	uint    fevt;		/* Force event register */
 	uint    admaes;		/* ADMA error status register */
 	uint    adsaddr;	/* ADMA system address register */
-	char    reserved2[100];	/* reserved */
-	uint    vendorspec;	/* Vendor Specific register */
-	char    reserved3[56];	/* reserved */
+	char    reserved2[4];
+	uint    dllctrl;
+	uint    dllstat;
+	uint    clktunectrlstatus;
+	char    reserved3[84];
+	uint    vendorspec;
+	uint    mmcboot;
+	uint    vendorspec2;
+	char	reserved4[48];
 	uint    hostver;	/* Host controller version register */
-	char    reserved4[4];	/* reserved */
-	uint    dmaerraddr;	/* DMA error address register */
 	char    reserved5[4];	/* reserved */
-	uint    dmaerrattr;	/* DMA error attribute register */
+	uint    dmaerraddr;	/* DMA error address register */
 	char    reserved6[4];	/* reserved */
+	uint    dmaerrattr;	/* DMA error attribute register */
+	char    reserved7[4];	/* reserved */
 	uint    hostcapblt2;	/* Host controller capabilities register 2 */
-	char    reserved7[8];	/* reserved */
+	char    reserved8[8];	/* reserved */
 	uint    tcr;		/* Tuning control register */
-	char    reserved8[28];	/* reserved */
+	char    reserved9[28];	/* reserved */
 	uint    sddirctl;	/* SD direction control register */
-	char    reserved9[712];	/* reserved */
+	char    reserved10[712];/* reserved */
 	uint    scr;		/* eSDHC control register */
 };
 
@@ -616,6 +622,20 @@ static int esdhc_init(struct mmc *mmc)
 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 		udelay(1000);
 
+#if defined(CONFIG_FSL_USDHC)
+	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+	esdhc_write32(&regs->mmcboot, 0x0);
+	/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
+	esdhc_write32(&regs->mixctrl, 0x0);
+	esdhc_write32(&regs->clktunectrlstatus, 0x0);
+
+	/* Put VEND_SPEC to default value */
+	esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+
+	/* Disable DLL_CTRL delay line */
+	esdhc_write32(&regs->dllctrl, 0x0);
+#endif
+
 #ifndef ARCH_MXC
 	/* Enable cache snooping */
 	esdhc_write32(&regs->scr, 0x00000040);
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index fa760a5..78c67c8 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -35,6 +35,12 @@
 #define SYSCTL_RSTC		0x02000000
 #define SYSCTL_RSTD		0x04000000
 
+#define VENDORSPEC_CKEN		0x00004000
+#define VENDORSPEC_PEREN	0x00002000
+#define VENDORSPEC_HCKEN	0x00001000
+#define VENDORSPEC_IPGEN	0x00000800
+#define VENDORSPEC_INIT		0x20007809
+
 #define IRQSTAT			0x0002e030
 #define IRQSTAT_DMAE		(0x10000000)
 #define IRQSTAT_AC12E		(0x01000000)
-- 
cgit v0.10.2


From 84ecdf6da9eb102b2de87d5912d1554f44d33237 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Wed, 15 Jun 2016 10:53:01 +0800
Subject: fsl_esdhc: Update clock enable bits for USDHC

The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
   implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
   external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits
operation.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index bfbef66..c5f08ea 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -538,7 +538,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 	clk = (pre_div << 8) | (div << 4);
 
 #ifdef CONFIG_FSL_USDHC
-	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+	esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
 #else
 	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 #endif
@@ -548,7 +548,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 	udelay(10000);
 
 #ifdef CONFIG_FSL_USDHC
-	esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA);
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
 #else
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
 #endif
@@ -643,6 +643,8 @@ static int esdhc_init(struct mmc *mmc)
 
 #ifndef CONFIG_FSL_USDHC
 	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#else
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
 #endif
 
 	/* Set the initial clock speed */
@@ -740,6 +742,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
 #ifndef CONFIG_FSL_USDHC
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 				| SYSCTL_IPGEN | SYSCTL_CKEN);
+#else
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
+			VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
 #endif
 
 	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
-- 
cgit v0.10.2


From 1483151e84161449c3f652a751a04e06b0723bff Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Wed, 15 Jun 2016 10:53:02 +0800
Subject: mmc: fsl: introduce wp_enable

Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.

Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.

If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5f08ea..a865c7b 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -91,7 +91,9 @@ struct fsl_esdhc {
  * Following is used when Driver Model is enabled for MMC
  * @dev: pointer for the device
  * @non_removable: 0: removable; 1: non-removable
+ * @wp_enable: 1: enable checking wp; 0: no check
  * @cd_gpio: gpio for card detection
+ * @wp_gpio: gpio for write protection
  */
 struct fsl_esdhc_priv {
 	struct fsl_esdhc *esdhc_regs;
@@ -101,7 +103,9 @@ struct fsl_esdhc_priv {
 	struct mmc *mmc;
 	struct udevice *dev;
 	int non_removable;
+	int wp_enable;
 	struct gpio_desc cd_gpio;
+	struct gpio_desc wp_gpio;
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
@@ -245,9 +249,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 #endif
 		if (wml_value > WML_WR_WML_MAX)
 			wml_value = WML_WR_WML_MAX_VAL;
-		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
-			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
-			return TIMEOUT;
+		if (priv->wp_enable) {
+			if ((esdhc_read32(&regs->prsstat) &
+			    PRSSTAT_WPSPL) == 0) {
+				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+				return TIMEOUT;
+			}
 		}
 
 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
@@ -721,6 +728,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
 	priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
 	priv->bus_width = cfg->max_bus_width;
 	priv->sdhc_clk = cfg->sdhc_clk;
+	priv->wp_enable  = cfg->wp_enable;
 
 	return 0;
 };
@@ -963,6 +971,13 @@ static int fsl_esdhc_probe(struct udevice *dev)
 					   &priv->cd_gpio, GPIOD_IS_IN);
 	}
 
+	priv->wp_enable = 1;
+
+	ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
+					 &priv->wp_gpio, GPIOD_IS_IN);
+	if (ret)
+		priv->wp_enable = 0;
+
 	/*
 	 * TODO:
 	 * Because lack of clk driver, if SDHC clk is not enabled,
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 78c67c8..c6f4666 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -177,6 +177,7 @@ struct fsl_esdhc_cfg {
 	phys_addr_t esdhc_base;
 	u32	sdhc_clk;
 	u8	max_bus_width;
+	u8	wp_enable;
 	struct mmc_config cfg;
 };
 
-- 
cgit v0.10.2


From 49cdce163519ad760ca7769be64dd2a6133a5c11 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Fri, 24 Jun 2016 13:48:13 +0530
Subject: armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs

Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.

So append "A" to SoC names.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d8ec426..f62b78d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,7 +28,7 @@ bool soc_has_dp_ddr(void)
 	u32 svr = gur_in32(&gur->svr);
 
 	/* LS2085A has DP_DDR */
-	if (SVR_SOC_VER(svr) == SVR_LS2085)
+	if (SVR_SOC_VER(svr) == SVR_LS2085A)
 		return true;
 
 	return false;
@@ -40,7 +40,7 @@ bool soc_has_aiop(void)
 	u32 svr = gur_in32(&gur->svr);
 
 	/* LS2085A has AIOP */
-	if (SVR_SOC_VER(svr) == SVR_LS2085)
+	if (SVR_SOC_VER(svr) == SVR_LS2085A)
 		return true;
 
 	return false;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index df877dd..197b0eb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -8,13 +8,13 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
 static struct cpu_type cpu_type_list[] = {
-	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
-	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
-	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
-	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
-	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
-	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
-	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
+	CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+	CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+	CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 2cb6c54..39e8c7a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -41,13 +41,13 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
-#define SVR_LS1012		0x870400
-#define SVR_LS1043		0x879200
-#define SVR_LS1023		0x879208
-#define SVR_LS2045		0x870120
-#define SVR_LS2080		0x870110
-#define SVR_LS2085		0x870100
-#define SVR_LS2040		0x870130
+#define SVR_LS1012A		0x870400
+#define SVR_LS1043A		0x879200
+#define SVR_LS1023A		0x879208
+#define SVR_LS2045A		0x870120
+#define SVR_LS2080A		0x870110
+#define SVR_LS2085A		0x870100
+#define SVR_LS2040A		0x870130
 
 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c
index ebe60a8..183bf2b 100644
--- a/drivers/usb/common/fsl-errata.c
+++ b/drivers/usb/common/fsl-errata.c
@@ -182,8 +182,8 @@ bool has_erratum_a008751(void)
 
 	switch (soc) {
 #ifdef CONFIG_ARM64
-	case SVR_LS2080:
-	case SVR_LS2085:
+	case SVR_LS2080A:
+	case SVR_LS2085A:
 		return IS_SVR_REV(svr, 1, 0);
 #endif
 	}
-- 
cgit v0.10.2


From dee01e426b39eac974364c0658fca431894987c3 Mon Sep 17 00:00:00 2001
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Date: Tue, 14 Jun 2016 13:18:31 +0530
Subject: armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs

Currently layescape SoCs are not using cpu nodes. So removing
them in favour of compatibly with  similar SoCs that
have different cores like LS2080A and LS2088A.

This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 546a87a..024527e 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -9,18 +9,6 @@
 / {
 	compatible = "fsl,ls1012a";
 	interrupt-parent = <&gic>;
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			reg = <0x0 0x0>;
-			clocks = <&clockgen 1 0>;
-		};
-
-	};
 
 	sysclk: sysclk {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index bf1dfe6..a8bffba 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -15,38 +15,6 @@
 / {
 	compatible = "fsl,ls1043a";
 	interrupt-parent = <&gic>;
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			reg = <0x0 0x0>;
-			clocks = <&clockgen 1 0>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			reg = <0x0 0x1>;
-			clocks = <&clockgen 1 0>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			reg = <0x0 0x2>;
-			clocks = <&clockgen 1 0>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a53";
-			reg = <0x0 0x3>;
-			clocks = <&clockgen 1 0>;
-		};
-	};
 
 	sysclk: sysclk {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 68ed133..b308c8b 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -12,67 +12,6 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		/*
-		 * We expect the enable-method for cpu's to be "psci", but this
-		 * is dependent on the SoC FW, which will fill this in.
-		 *
-		 * Currently supported enable-method is psci v0.2
-		 */
-
-		/* We have 4 clusters having 2 Cortex-A57 cores each */
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x1>;
-		};
-
-		cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x100>;
-		};
-
-		cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x101>;
-		};
-
-		cpu@200 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x200>;
-		};
-
-		cpu@201 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x201>;
-		};
-
-		cpu@300 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x300>;
-		};
-
-		cpu@301 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a57";
-			reg = <0x0 0x301>;
-		};
-	};
-
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x00000000 0x80000000 0 0x80000000>;
-- 
cgit v0.10.2


From 6f0aea39aeb093a404a7dc21a0f79fa75ca851db Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 27 Jun 2016 22:40:17 -0400
Subject: configs: Re-sync after boot menu changes

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index d5aa3a2..2fe1a25 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
+CONFIG_SPI_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -38,4 +39,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 5264332..c6bc8e4 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -3,6 +3,7 @@ CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_ISW_ENTRY_ADDR=0x30000000
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -41,4 +42,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 37b8bc9..f023ebf 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_BRPPT1=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+CONFIG_SPI_BOOT=y
 CONFIG_BOOTDELAY=0
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 1aed0c4..1d8e28b 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 86ddf71..bbfb118 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 3806412..b418d5c 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index eca1cca..b79fc58 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_NAND_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index a1504c3..284cc07 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index f8bdfe8..b6f8d74 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index a1ee5b9..e3abe36 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 0a6cbcd..7e440b2 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 2128c46..e735fa0 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 8d1f8ed..6cf4dbc 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 6136887..3a95124 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_NAND_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 2b2a714..cfc7310 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index f90a6be..f4f464e 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index d85f771..0a077a3 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index c420548..dcf5de2 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_NAND_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index a5a870b..9fd0679 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 0850a68..7826bbc 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -1,21 +1,19 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS2080AQDS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_DM=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
@@ -25,13 +23,15 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
-CONFIG_CMD_SF=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
-CONFIG_OF_LIBFDT=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
cgit v0.10.2


From ff6e1569663eccaf9e582c57cc44568915c2f54b Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 22 Jun 2016 02:30:03 -0700
Subject: x86: coreboot: Remove the dummy pch driver

There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index b6e870a..d663656 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -18,4 +18,3 @@ obj-y += coreboot.o
 obj-y += tables.o
 obj-y += sdram.o
 obj-y += timestamp.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
deleted file mode 100644
index 7f5087a..0000000
--- a/arch/x86/cpu/coreboot/pci.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <pci.h>
-
-static const struct udevice_id generic_pch_ids[] = {
-	{ .compatible = "intel,pch7" },
-	{ .compatible = "intel,pch9" },
-	{ }
-};
-
-U_BOOT_DRIVER(generic_pch_drv) = {
-	.name		= "pch",
-	.id		= UCLASS_PCH,
-	.of_match	= generic_pch_ids,
-};
-- 
cgit v0.10.2


From 4cb9399e9baa0a05fe2c0376c391b9aac18edc04 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 24 Jun 2016 11:51:38 +0900
Subject: ARM: uniphier: fix typo "talbe"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index e2bb1fc..cc34116 100644
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -29,7 +29,7 @@ ENTRY(lowlevel_init)
 	bl	debug_ll_init
 #endif
 
-	bl	setup_init_ram		@ RAM area for stack and page talbe
+	bl	setup_init_ram		@ RAM area for stack and page table
 
 	/*
 	 * Now we are using the page table embedded in the Boot ROM.
-- 
cgit v0.10.2


From 4d1065c8d8d9a6b238cbf7151fc11d0bc1e5cd1b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:53 +0900
Subject: pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2

These are pin group names, not function names.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index cfec877..0dbfdc7 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -96,11 +96,9 @@ static const char * const uniphier_pxs2_functions[] = {
 	"nand",
 	"sd",
 	"uart0",
-	"uart0b",
 	"uart1",
 	"uart2",
 	"uart3",
-	"uart3b",
 	"usb0",
 	"usb1",
 	"usb2",
-- 
cgit v0.10.2


From 69da34c073ec7cda928e6cc09fe9cb6abdb3eccd Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:54 +0900
Subject: pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20

My mistake in the initial support patch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index fe154b7..4ddaddc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -23,8 +23,8 @@ static const unsigned i2c4_pins[] = {61, 62};
 static const unsigned i2c4_muxvals[] = {1, 1};
 static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 				     15, 16, 17};
-static const unsigned nand_muxvals[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-					2, 2, 2};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					0, 0, 0};
 static const unsigned nand_cs1_pins[] = {};
 static const unsigned nand_cs1_muxvals[] = {};
 static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
-- 
cgit v0.10.2


From aac641bcf43207feeca5335f5b98d955fe84c257 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:55 +0900
Subject: pinctrl: uniphier: remove unneeded pin group nand_cs1

This SoC does not support NAND CS1.  This place-holder is no longer
necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 4ddaddc..7bc0b28 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -25,8 +25,6 @@ static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 				     15, 16, 17};
 static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 					0, 0, 0};
-static const unsigned nand_cs1_pins[] = {};
-static const unsigned nand_cs1_muxvals[] = {};
 static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
 static const unsigned sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3};  /* No SDVOLC */
 static const unsigned uart0_pins[] = {54, 55};
@@ -54,7 +52,6 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(i2c3),
 	UNIPHIER_PINCTRL_GROUP(i2c4),
 	UNIPHIER_PINCTRL_GROUP(nand),
-	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),	/* SD does not exist for LD11 */
 	UNIPHIER_PINCTRL_GROUP(uart0),
 	UNIPHIER_PINCTRL_GROUP(uart1),
-- 
cgit v0.10.2


From c4adc50ea66436438f10d7eedb00d2c441ec9dbe Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:56 +0900
Subject: ARM: dts: uniphier: sync Device Trees with upstream Linux

I periodically sync Device Trees for better maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index 7d59112..b0b2b57 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -22,6 +22,7 @@
 		#size-cells = <1>;
 		ranges;
 		interrupt-parent = <&intc>;
+		u-boot,dm-pre-reloc;
 
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -65,9 +66,12 @@
 
 		system_bus: system-bus@58c00000 {
 			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
 			reg = <0x58c00000 0x400>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
 		};
 
 		smpctrl@59800000 {
@@ -109,9 +113,15 @@
 			interrupt-controller;
 		};
 
-		pinctrl: pinctrl@5f801000 {
-			/* specify compatible in each SoC DTSI */
-			reg = <0x5f801000 0xe00>;
+		soc-glue@5f800000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				/* specify compatible in each SoC DTSI */
+				u-boot,dm-pre-reloc;
+			};
 		};
 
 		sysctrl: sysctrl@61840000 {
@@ -124,8 +134,12 @@
 
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
-			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			interrupts = <0 65 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index b148e9f..4eb7664 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -1,7 +1,8 @@
 /*
  * Device Tree Source for UniPhier PH1-LD11 Reference Board
  *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
@@ -62,20 +63,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index e485f90..8901a79 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -1,11 +1,14 @@
 /*
  * Device Tree Source for UniPhier PH1-LD11 SoC
  *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
+/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+
 / {
 	compatible = "socionext,ph1-ld11";
 	#address-cells = <2>;
@@ -16,24 +19,41 @@
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x000>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x001>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 	};
 
 	clocks {
+		refclk: ref {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
 		uart_clk: uart_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -60,6 +80,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
+		u-boot,dm-pre-reloc;
 
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -183,6 +204,8 @@
 			reg = <0x58c00000 0x400>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
 		};
 
 		smpctrl@59800000 {
@@ -226,9 +249,15 @@
 			#clock-cells = <1>;
 		};
 
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-ld11-pinctrl", "syscon";
-			reg = <0x5f801000 0xe00>;
+		soc-glue@5f800000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-ld11-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
 		};
 
 		gic: interrupt-controller@5fe00000 {
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
index 3049016..90c8705 100644
--- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts
@@ -51,20 +51,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index f9cc3c4..f5cced5 100644
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier:	GPL-2.0+	X11
  */
 
+/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+
 / {
 	compatible = "socionext,ph1-ld20";
 	#address-cells = <2>;
@@ -41,7 +43,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
 		cpu1: cpu@1 {
@@ -49,7 +51,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
 		cpu2: cpu@100 {
@@ -57,7 +59,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 
 		cpu3: cpu@101 {
@@ -65,11 +67,17 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x80000000>;
 		};
 	};
 
 	clocks {
+		refclk: ref {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
 		uart_clk: uart_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -96,6 +104,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
+		u-boot,dm-pre-reloc;
 
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
@@ -219,6 +228,8 @@
 			reg = <0x58c00000 0x400>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_system_bus>;
 		};
 
 		smpctrl@59800000 {
@@ -243,9 +254,15 @@
 			bus-width = <4>;
 		};
 
-		pinctrl: pinctrl@5f801000 {
-			compatible = "socionext,ph1-ld20-pinctrl", "syscon";
-			reg = <0x5f801000 0xe00>;
+		soc-glue@5f800000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-ld20-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
 		};
 
 		gic: interrupt-controller@5fe00000 {
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 6cae452..36de7e3 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -69,20 +69,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 5ae029e..5629b7d 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -310,7 +310,7 @@
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-ld4-pinctrl", "syscon";
+	compatible = "socionext,uniphier-ld4-pinctrl";
 };
 
 &sysctrl {
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index e2a2a8c..e29a6ea 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -71,20 +71,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/dts/uniphier-ph1-ld6b.dtsi
index cf02e62..e8110ee 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld6b.dtsi
@@ -17,7 +17,7 @@
 	compatible = "socionext,ph1-ld6b";
 };
 
-/* UART3 unavilable: the pads are not wired to the package balls */
+/* UART3 unavailable: the pads are not wired to the package balls */
 &serial3 {
 	status = "disabled";
 };
@@ -27,5 +27,5 @@
  * which makes the pinctrl driver unshareable.
  */
 &pinctrl {
-	compatible = "socionext,ph1-ld6b-pinctrl", "syscon";
+	compatible = "socionext,uniphier-ld6b-pinctrl";
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts
index 37e0853..d8740cc 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ace.dts
@@ -90,20 +90,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index 5be76e2..4a2de08 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -80,20 +80,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
index 82e2bd0..965fe08 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
@@ -85,12 +85,6 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
@@ -103,10 +97,6 @@
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index d5767b6..080fced 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -452,7 +452,7 @@
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pro4-pinctrl";
 };
 
 &sysctrl {
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
index cbdc3eb..682b795 100644
--- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
+++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
@@ -56,20 +56,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial1 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart1 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index bd1b4b1..5b7f6e8 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -431,7 +431,7 @@
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pro5-pinctrl";
 };
 
 &sysctrl {
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index 8ceb93e..9af012c 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -73,20 +73,10 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial0 {
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart0 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 61e0b45..f07a1d1 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -310,7 +310,7 @@
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
+	compatible = "socionext,uniphier-sld8-pinctrl";
 };
 
 &sysctrl {
diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi
index 2d36f98..2810f3b 100644
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -47,6 +47,11 @@
 		function = "nand";
 	};
 
+	pinctrl_nand2cs: nand2cs_grp {
+		groups = "nand", "nand_cs1";
+		function = "nand";
+	};
+
 	pinctrl_sd: sd_grp {
 		groups = "sd";
 		function = "sd";
@@ -67,6 +72,11 @@
 		function = "sd1";
 	};
 
+	pinctrl_system_bus: system_bus_grp {
+		groups = "system_bus", "system_bus_cs1";
+		function = "system_bus";
+	};
+
 	pinctrl_uart0: uart0_grp {
 		groups = "uart0";
 		function = "uart0";
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index eb1d2bc..61f6164 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -65,12 +65,6 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial2 {
 	u-boot,dm-pre-reloc;
 };
@@ -83,10 +77,6 @@
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart2 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
index e7d5db8..3d5b300 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -50,12 +50,6 @@
 };
 
 /* for U-Boot only */
-/ {
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
 &serial2 {
 	u-boot,dm-pre-reloc;
 };
@@ -68,10 +62,6 @@
 	u-boot,dm-pre-reloc;
 };
 
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
 &pinctrl_uart2 {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 12968bd..0a8c049 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -435,7 +435,7 @@
 };
 
 &pinctrl {
-	compatible = "socionext,proxstream2-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pxs2-pinctrl";
 };
 
 &sysctrl {
diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi
index b8960fd..6d25104 100644
--- a/arch/arm/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/dts/uniphier-ref-daughter.dtsi
@@ -7,7 +7,7 @@
  */
 
 &i2c0 {
-	eeprom {
+	eeprom@50 {
 		compatible = "microchip,24lc128", "i2c-eeprom";
 		reg = <0x50>;
 		u-boot,i2c-offset-len = <2>;
-- 
cgit v0.10.2


From 186c133444152005473955f1feea2e3184740dd6 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:57 +0900
Subject: pinctrl: uniphier: allow to have pinctrl node under syscon node

Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node.  This commit allows to migrate to
the new DT structure.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index b8e26d9..fc8bbd2 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -173,7 +173,7 @@ int uniphier_pinctrl_probe(struct udevice *dev,
 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
 	fdt_addr_t addr;
 
-	addr = dev_get_addr(dev);
+	addr = dev_get_addr(dev->parent);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 7bc0b28..a394081 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -95,8 +95,8 @@ static int uniphier_ld20_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_ld20_pinctrl_match[] = {
-	{ .compatible = "socionext,ph1-ld11-pinctrl" },
-	{ .compatible = "socionext,ph1-ld20-pinctrl" },
+	{ .compatible = "socionext,uniphier-ld11-pinctrl" },
+	{ .compatible = "socionext,uniphier-ld20-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index ca66dee..79bc540 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -115,7 +115,7 @@ static int uniphier_ld4_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_ld4_pinctrl_match[] = {
-	{ .compatible = "socionext,ph1-ld4-pinctrl" },
+	{ .compatible = "socionext,uniphier-ld4-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 0fd4dc4..861e741 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -115,7 +115,7 @@ static int uniphier_ld6b_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_ld6b_pinctrl_match[] = {
-	{ .compatible = "socionext,ph1-ld6b-pinctrl" },
+	{ .compatible = "socionext,uniphier-ld6b-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index 9ed7c74..f5194b6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -112,7 +112,7 @@ static int uniphier_pro4_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_pro4_pinctrl_match[] = {
-	{ .compatible = "socionext,ph1-pro4-pinctrl" },
+	{ .compatible = "socionext,uniphier-pro4-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 6597f1c..72b9b39 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -126,7 +126,7 @@ static int uniphier_pro5_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_pro5_pinctrl_match[] = {
-	{ .compatible = "socionext,ph1-pro5-pinctrl" },
+	{ .compatible = "socionext,uniphier-pro5-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 0dbfdc7..a1c4240 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -120,7 +120,7 @@ static int uniphier_pxs2_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_pxs2_pinctrl_match[] = {
-	{ .compatible = "socionext,proxstream2-pinctrl" },
+	{ .compatible = "socionext,uniphier-pxs2-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index 5a733b3..6f4847a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -123,7 +123,7 @@ static int uniphier_sld8_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_sld8_pinctrl_match[] = {
-	{ .compatible = "socionext,ph1-sld8-pinctrl" },
+	{ .compatible = "socionext,uniphier-sld8-pinctrl" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 2b43848..200d743 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -12,9 +12,9 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 
-#define UNIPHIER_PINCTRL_PINMUX_BASE	0x0
-#define UNIPHIER_PINCTRL_LOAD_PINMUX	0x700
-#define UNIPHIER_PINCTRL_IECTRL		0xd00
+#define UNIPHIER_PINCTRL_PINMUX_BASE	0x1000
+#define UNIPHIER_PINCTRL_LOAD_PINMUX	0x1700
+#define UNIPHIER_PINCTRL_IECTRL		0x1d00
 
 #define UNIPHIER_PIN_ATTR_PACKED(iectrl)	(iectrl)
 
-- 
cgit v0.10.2


From 3379987e26956d9eab668a0811a0f0a9a056754f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:58 +0900
Subject: pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20

PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.

However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development.  Split it into two dedicated drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 1856ff0..7febea2 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -39,9 +39,15 @@ config PINCTRL_UNIPHIER_LD6B
 	default y
 	select PINCTRL_UNIPHIER
 
+config PINCTRL_UNIPHIER_LD11
+	bool "UniPhier PH1-LD11 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_LD11
+	default y
+	select PINCTRL_UNIPHIER
+
 config PINCTRL_UNIPHIER_LD20
-	bool "UniPhier PH1-LD11/PH1-LD20 SoC pinctrl driver"
-	depends on ARCH_UNIPHIER_LD11 || ARCH_UNIPHIER_LD20
+	bool "UniPhier PH1-LD20 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_LD20
 	default y
 	select PINCTRL_UNIPHIER
 
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index bea4dd8..4de251b 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8)	+= pinctrl-uniphier-sld8.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5)	+= pinctrl-uniphier-pro5.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2)	+= pinctrl-uniphier-pxs2.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B)	+= pinctrl-uniphier-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD11)	+= pinctrl-uniphier-ld11.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD20)	+= pinctrl-uniphier-ld20.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
new file mode 100644
index 0000000..bf8c693
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {63, 64};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const unsigned i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+				     15, 16, 17};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					0, 0, 0};
+static const unsigned uart0_pins[] = {54, 55};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const unsigned uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const unsigned usb2_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
+	UNIPHIER_PINCTRL_GROUP(emmc),
+	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(i2c4),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(uart0),
+	UNIPHIER_PINCTRL_GROUP(uart1),
+	UNIPHIER_PINCTRL_GROUP(uart2),
+	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const uniphier_ld11_functions[] = {
+	"emmc",
+	"i2c0",
+	"i2c1",
+	"i2c3",
+	"i2c4",
+	"nand",
+	"uart0",
+	"uart1",
+	"uart2",
+	"uart3",
+	"usb0",
+	"usb1",
+	"usb2",
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld11_pinctrl_socdata = {
+	.groups = uniphier_ld11_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld11_groups),
+	.functions = uniphier_ld11_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld11_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_ld11_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_ld11_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_ld11_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-ld11-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_ld11_pinctrl) = {
+	.name = "uniphier-ld11-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_ld11_pinctrl_match),
+	.probe = uniphier_ld11_pinctrl_probe,
+	.remove = uniphier_pinctrl_remove,
+	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index a394081..c84f7b1 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -52,7 +53,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(i2c3),
 	UNIPHIER_PINCTRL_GROUP(i2c4),
 	UNIPHIER_PINCTRL_GROUP(nand),
-	UNIPHIER_PINCTRL_GROUP(sd),	/* SD does not exist for LD11 */
+	UNIPHIER_PINCTRL_GROUP(sd),
 	UNIPHIER_PINCTRL_GROUP(uart0),
 	UNIPHIER_PINCTRL_GROUP(uart1),
 	UNIPHIER_PINCTRL_GROUP(uart2),
@@ -60,7 +61,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
-	UNIPHIER_PINCTRL_GROUP(usb3),	/* USB3 does not exist for LD11 */
+	UNIPHIER_PINCTRL_GROUP(usb3),
 };
 
 static const char * const uniphier_ld20_functions[] = {
@@ -70,7 +71,7 @@ static const char * const uniphier_ld20_functions[] = {
 	"i2c3",
 	"i2c4",
 	"nand",
-	"sd",		/* SD does not exist for LD11 */
+	"sd",
 	"uart0",
 	"uart1",
 	"uart2",
@@ -78,7 +79,7 @@ static const char * const uniphier_ld20_functions[] = {
 	"usb0",
 	"usb1",
 	"usb2",
-	"usb3",		/* USB3 does not exist for LD11 */
+	"usb3",
 };
 
 static struct uniphier_pinctrl_socdata uniphier_ld20_pinctrl_socdata = {
@@ -95,7 +96,6 @@ static int uniphier_ld20_pinctrl_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_ld20_pinctrl_match[] = {
-	{ .compatible = "socionext,uniphier-ld11-pinctrl" },
 	{ .compatible = "socionext,uniphier-ld20-pinctrl" },
 	{ /* sentinel */ }
 };
-- 
cgit v0.10.2


From 5e25b9d5d90205ce9531677e362e9dd9359963b3 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:38:59 +0900
Subject: pinctrl: uniphier: support pin configuration for dedicated pins

PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.

Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function.  The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.

[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index fc8bbd2..0ad15ab 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -91,7 +91,7 @@ static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
 }
 
 static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
-				    unsigned muxval)
+				    int muxval)
 {
 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
 	unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
@@ -101,6 +101,9 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
 	/* some pins need input-enabling */
 	uniphier_pinconf_input_enable(dev, pin);
 
+	if (muxval < 0)
+		return;		/* dedicated pin; nothing to do for pin-mux */
+
 	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
 		/*
 		 *  Mode       offset        bit
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index bf8c693..e7147fc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -11,35 +11,34 @@
 #include "pinctrl-uniphier.h"
 
 static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
 static const unsigned i2c0_pins[] = {63, 64};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c3_pins[] = {67, 68};
-static const unsigned i2c3_muxvals[] = {1, 1};
+static const int i2c3_muxvals[] = {1, 1};
 static const unsigned i2c4_pins[] = {61, 62};
-static const unsigned i2c4_muxvals[] = {1, 1};
+static const int i2c4_muxvals[] = {1, 1};
 static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 				     15, 16, 17};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned uart0_pins[] = {54, 55};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
 static const unsigned uart1_pins[] = {58, 59};
-static const unsigned uart1_muxvals[] = {1, 1};
+static const int uart1_muxvals[] = {1, 1};
 static const unsigned uart2_pins[] = {90, 91};
-static const unsigned uart2_muxvals[] = {1, 1};
+static const int uart2_muxvals[] = {1, 1};
 static const unsigned uart3_pins[] = {94, 95};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
 static const unsigned usb0_pins[] = {46, 47};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {48, 49};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {50, 51};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index c84f7b1..b662ae7 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -11,39 +11,38 @@
 #include "pinctrl-uniphier.h"
 
 static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
 static const unsigned i2c0_pins[] = {63, 64};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c3_pins[] = {67, 68};
-static const unsigned i2c3_muxvals[] = {1, 1};
+static const int i2c3_muxvals[] = {1, 1};
 static const unsigned i2c4_pins[] = {61, 62};
-static const unsigned i2c4_muxvals[] = {1, 1};
+static const int i2c4_muxvals[] = {1, 1};
 static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 				     15, 16, 17};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
-static const unsigned sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3};  /* No SDVOLC */
+static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3};  /* No SDVOLC */
 static const unsigned uart0_pins[] = {54, 55};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
 static const unsigned uart1_pins[] = {58, 59};
-static const unsigned uart1_muxvals[] = {1, 1};
+static const int uart1_muxvals[] = {1, 1};
 static const unsigned uart2_pins[] = {90, 91};
-static const unsigned uart2_muxvals[] = {1, 1};
+static const int uart2_muxvals[] = {1, 1};
 static const unsigned uart3_pins[] = {94, 95};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
 static const unsigned usb0_pins[] = {46, 47};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {48, 49};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {50, 51};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
 static const unsigned usb3_pins[] = {52, 53};
-static const unsigned usb3_muxvals[] = {0, 0};
+static const int usb3_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 79bc540..f3849b4 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -24,43 +24,42 @@ static const struct uniphier_pinctrl_pin uniphier_ld4_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
+static const int i2c2_muxvals[] = {2, 2};
 static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
+static const int i2c3_muxvals[] = {3, 3};
 static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
 				     160, 161, 162, 163, 164};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
 static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned uart0_pins[] = {85, 88};
-static const unsigned uart0_muxvals[] = {1, 1};
+static const int uart0_muxvals[] = {1, 1};
 static const unsigned uart1_pins[] = {155, 156};
-static const unsigned uart1_muxvals[] = {13, 13};
+static const int uart1_muxvals[] = {13, 13};
 static const unsigned uart1b_pins[] = {69, 70};
-static const unsigned uart1b_muxvals[] = {23, 23};
+static const int uart1b_muxvals[] = {23, 23};
 static const unsigned uart2_pins[] = {128, 129};
-static const unsigned uart2_muxvals[] = {13, 13};
+static const int uart2_muxvals[] = {13, 13};
 static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
 static const unsigned usb0_pins[] = {53, 54};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {55, 56};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {155, 156};
-static const unsigned usb2_muxvals[] = {4, 4};
+static const int usb2_muxvals[] = {4, 4};
 static const unsigned usb2b_pins[] = {67, 68};
-static const unsigned usb2b_muxvals[] = {23, 23};
+static const int usb2b_muxvals[] = {23, 23};
 
 static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 861e741..4627f2c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -21,45 +21,44 @@ static const struct uniphier_pinctrl_pin uniphier_ld6b_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c2_pins[] = {115, 116};
-static const unsigned i2c2_muxvals[] = {1, 1};
+static const int i2c2_muxvals[] = {1, 1};
 static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {1, 1};
+static const int i2c3_muxvals[] = {1, 1};
 static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
 				     42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
 static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned uart0_pins[] = {135, 136};
-static const unsigned uart0_muxvals[] = {3, 3};
+static const int uart0_muxvals[] = {3, 3};
 static const unsigned uart0b_pins[] = {11, 12};
-static const unsigned uart0b_muxvals[] = {2, 2};
+static const int uart0b_muxvals[] = {2, 2};
 static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
 static const unsigned uart1b_pins[] = {113, 114};
-static const unsigned uart1b_muxvals[] = {1, 1};
+static const int uart1b_muxvals[] = {1, 1};
 static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {2, 2};
+static const int uart2_muxvals[] = {2, 2};
 static const unsigned uart2b_pins[] = {86, 87};
-static const unsigned uart2b_muxvals[] = {1, 1};
+static const int uart2b_muxvals[] = {1, 1};
 static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
 static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {0, 0};
+static const int usb3_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index f5194b6..7e465b6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -13,46 +13,45 @@ static const struct uniphier_pinctrl_pin uniphier_pro4_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {142, 143};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {144, 145};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c2_pins[] = {146, 147};
-static const unsigned i2c2_muxvals[] = {0, 0};
+static const int i2c2_muxvals[] = {0, 0};
 static const unsigned i2c3_pins[] = {148, 149};
-static const unsigned i2c3_muxvals[] = {0, 0};
+static const int i2c3_muxvals[] = {0, 0};
 static const unsigned i2c6_pins[] = {308, 309};
-static const unsigned i2c6_muxvals[] = {6, 6};
+static const int i2c6_muxvals[] = {6, 6};
 static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
 				     50, 51, 52, 53, 54};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned nand_cs1_pins[] = {131, 132};
-static const unsigned nand_cs1_muxvals[] = {1, 1};
+static const int nand_cs1_muxvals[] = {1, 1};
 static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
 				    327};
-static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned uart0_pins[] = {127, 128};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
 static const unsigned uart1_pins[] = {129, 130};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
 static const unsigned uart2_pins[] = {131, 132};
-static const unsigned uart2_muxvals[] = {0, 0};
+static const int uart2_muxvals[] = {0, 0};
 static const unsigned uart3_pins[] = {88, 89};
-static const unsigned uart3_muxvals[] = {2, 2};
+static const int uart3_muxvals[] = {2, 2};
 static const unsigned usb0_pins[] = {180, 181};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {182, 183};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {184, 185};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
 static const unsigned usb3_pins[] = {186, 187};
-static const unsigned usb3_muxvals[] = {0, 0};
+static const int usb3_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 72b9b39..2c6b4f9 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -23,49 +23,48 @@ static const struct uniphier_pinctrl_pin uniphier_pro5_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
 static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
 static const unsigned i2c0_pins[] = {112, 113};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {114, 115};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c2_pins[] = {116, 117};
-static const unsigned i2c2_muxvals[] = {0, 0};
+static const int i2c2_muxvals[] = {0, 0};
 static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {0, 0};
+static const int i2c3_muxvals[] = {0, 0};
 static const unsigned i2c5_pins[] = {87, 88};
-static const unsigned i2c5_muxvals[] = {2, 2};
+static const int i2c5_muxvals[] = {2, 2};
 static const unsigned i2c5b_pins[] = {196, 197};
-static const unsigned i2c5b_muxvals[] = {2, 2};
+static const int i2c5b_muxvals[] = {2, 2};
 static const unsigned i2c5c_pins[] = {215, 216};
-static const unsigned i2c5c_muxvals[] = {2, 2};
+static const int i2c5c_muxvals[] = {2, 2};
 static const unsigned i2c6_pins[] = {101, 102};
-static const unsigned i2c6_muxvals[] = {2, 2};
+static const int i2c6_muxvals[] = {2, 2};
 static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
 				     31, 32, 33, 34, 35};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned nand_cs1_pins[] = {26, 27};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
 static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned uart0_pins[] = {47, 48};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
 static const unsigned uart0b_pins[] = {227, 228};
-static const unsigned uart0b_muxvals[] = {3, 3};
+static const int uart0b_muxvals[] = {3, 3};
 static const unsigned uart1_pins[] = {49, 50};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
 static const unsigned uart2_pins[] = {51, 52};
-static const unsigned uart2_muxvals[] = {0, 0};
+static const int uart2_muxvals[] = {0, 0};
 static const unsigned uart3_pins[] = {53, 54};
-static const unsigned uart3_muxvals[] = {0, 0};
+static const int uart3_muxvals[] = {0, 0};
 static const unsigned usb0_pins[] = {124, 125};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {126, 127};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {128, 129};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index a1c4240..9eddd14 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -17,49 +17,48 @@ static const struct uniphier_pinctrl_pin uniphier_pxs2_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
 static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const int emmc_dat8_muxvals[] = {9, 9, 9, 9};
 static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {8, 8};
+static const int i2c0_muxvals[] = {8, 8};
 static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {8, 8};
+static const int i2c1_muxvals[] = {8, 8};
 static const unsigned i2c2_pins[] = {171, 172};
-static const unsigned i2c2_muxvals[] = {8, 8};
+static const int i2c2_muxvals[] = {8, 8};
 static const unsigned i2c3_pins[] = {159, 160};
-static const unsigned i2c3_muxvals[] = {8, 8};
+static const int i2c3_muxvals[] = {8, 8};
 static const unsigned i2c5_pins[] = {183, 184};
-static const unsigned i2c5_muxvals[] = {11, 11};
+static const int i2c5_muxvals[] = {11, 11};
 static const unsigned i2c6_pins[] = {185, 186};
-static const unsigned i2c6_muxvals[] = {11, 11};
+static const int i2c6_muxvals[] = {11, 11};
 static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
 				     42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
-					8, 8};
+static const int nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8};
 static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {8, 8};
+static const int nand_cs1_muxvals[] = {8, 8};
 static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
 static const unsigned uart0_pins[] = {217, 218};
-static const unsigned uart0_muxvals[] = {8, 8};
+static const int uart0_muxvals[] = {8, 8};
 static const unsigned uart0b_pins[] = {179, 180};
-static const unsigned uart0b_muxvals[] = {10, 10};
+static const int uart0b_muxvals[] = {10, 10};
 static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {8, 8};
+static const int uart1_muxvals[] = {8, 8};
 static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {8, 8};
+static const int uart2_muxvals[] = {8, 8};
 static const unsigned uart3_pins[] = {219, 220};
-static const unsigned uart3_muxvals[] = {8, 8};
+static const int uart3_muxvals[] = {8, 8};
 static const unsigned uart3b_pins[] = {181, 182};
-static const unsigned uart3b_muxvals[] = {10, 10};
+static const int uart3b_muxvals[] = {10, 10};
 static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {8, 8};
+static const int usb0_muxvals[] = {8, 8};
 static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {8, 8};
+static const int usb1_muxvals[] = {8, 8};
 static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {8, 8};
+static const int usb2_muxvals[] = {8, 8};
 static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {8, 8};
+static const int usb3_muxvals[] = {8, 8};
 
 static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index 6f4847a..82fe33d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -38,39 +38,38 @@ static const struct uniphier_pinctrl_pin uniphier_sld8_pins[] = {
 };
 
 static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
 static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
+static const int i2c2_muxvals[] = {2, 2};
 static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
+static const int i2c3_muxvals[] = {3, 3};
 static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
 				     27, 28, 29, 30, 31};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-					0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
 static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned uart0_pins[] = {70, 71};
-static const unsigned uart0_muxvals[] = {3, 3};
+static const int uart0_muxvals[] = {3, 3};
 static const unsigned uart1_pins[] = {114, 115};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
 static const unsigned uart2_pins[] = {112, 113};
-static const unsigned uart2_muxvals[] = {1, 1};
+static const int uart2_muxvals[] = {1, 1};
 static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
 static const unsigned usb0_pins[] = {41, 42};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
 static const unsigned usb1_pins[] = {43, 44};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
 static const unsigned usb2_pins[] = {114, 115};
-static const unsigned usb2_muxvals[] = {1, 1};
+static const int usb2_muxvals[] = {1, 1};
 
 static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 200d743..ff0a368 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -46,7 +46,7 @@ struct uniphier_pinctrl_group {
 	const char *name;
 	const unsigned *pins;
 	unsigned num_pins;
-	const unsigned *muxvals;
+	const int *muxvals;
 };
 
 /**
-- 
cgit v0.10.2


From 64c1cc4cc5f72f480787bf493a5ebb0696d68bc0 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:39:00 +0900
Subject: pinctrl: uniphier: avoid building unneeded pin-mux tables for SPL

SPL does not use all of the devices, so we can save some memory
footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 0ad15ab..225a05c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -14,6 +14,8 @@
 
 #include "pinctrl-uniphier.h"
 
+static const char *uniphier_pinctrl_dummy_name = "_dummy";
+
 static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
 {
 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
@@ -26,6 +28,9 @@ static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
 {
 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
 
+	if (!priv->socdata->groups[selector].name)
+		return uniphier_pinctrl_dummy_name;
+
 	return priv->socdata->groups[selector].name;
 }
 
@@ -41,6 +46,9 @@ static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
 {
 	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
 
+	if (!priv->socdata->functions[selector])
+		return uniphier_pinctrl_dummy_name;
+
 	return priv->socdata->functions[selector];
 }
 
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e7147fc..e2bd9ae 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -48,29 +48,29 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(i2c3),
 	UNIPHIER_PINCTRL_GROUP(i2c4),
 	UNIPHIER_PINCTRL_GROUP(nand),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
 };
 
 static const char * const uniphier_ld11_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c3",
-	"i2c4",
-	"nand",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
+	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c4),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_ld11_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index b662ae7..15ee469 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -53,10 +53,10 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(i2c4),
 	UNIPHIER_PINCTRL_GROUP(nand),
 	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
@@ -64,21 +64,21 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 };
 
 static const char * const uniphier_ld20_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c3",
-	"i2c4",
-	"nand",
-	"sd",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
-	"usb3",
+	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c4),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_ld20_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index f3849b4..56d9d5b 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -62,8 +62,8 @@ static const unsigned usb2b_pins[] = {67, 68};
 static const int usb2b_muxvals[] = {23, 23};
 
 static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
-	UNIPHIER_PINCTRL_GROUP(emmc),
-	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -71,11 +71,11 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(nand),
 	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart1b),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
@@ -83,20 +83,20 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
 };
 
 static const char * const uniphier_ld4_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c2",
-	"i2c3",
-	"nand",
-	"sd",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_ld4_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 4627f2c..dd4a28c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -61,8 +61,8 @@ static const unsigned usb3_pins[] = {62, 63};
 static const int usb3_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
-	UNIPHIER_PINCTRL_GROUP(emmc),
-	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -70,12 +70,12 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(nand),
 	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart0b),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart1b),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart2b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2b),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
@@ -83,20 +83,20 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
 };
 
 static const char * const uniphier_ld6b_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c2",
-	"i2c3",
-	"nand",
-	"sd",
-	"uart0",
-	"uart1",
-	"uart2",
-	"usb0",
-	"usb1",
-	"usb2",
-	"usb3",
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_ld6b_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index 7e465b6..f87a2c6 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -54,8 +54,8 @@ static const unsigned usb3_pins[] = {186, 187};
 static const int usb3_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
-	UNIPHIER_PINCTRL_GROUP(emmc),
-	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -65,10 +65,10 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),
 	UNIPHIER_PINCTRL_GROUP(sd1),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
@@ -76,23 +76,23 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
 };
 
 static const char * const uniphier_pro4_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c2",
-	"i2c3",
-	"i2c6",
-	"nand",
-	"sd",
-	"sd1",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
-	"usb3",
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c6),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(sd1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_pro4_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 2c6b4f9..50b41cc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -67,8 +67,8 @@ static const unsigned usb2_pins[] = {128, 129};
 static const int usb2_muxvals[] = {0, 0};
 
 static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
-	UNIPHIER_PINCTRL_GROUP(emmc),
-	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -80,33 +80,33 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(nand),
 	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart0b),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
 };
 
 static const char * const uniphier_pro5_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c2",
-	"i2c3",
-	"i2c5",
-	"i2c6",
-	"nand",
-	"sd",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c5),
+	UNIPHIER_PINMUX_FUNCTION(i2c6),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_pro5_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 9eddd14..70fb168 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -61,8 +61,8 @@ static const unsigned usb3_pins[] = {62, 63};
 static const int usb3_muxvals[] = {8, 8};
 
 static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
-	UNIPHIER_PINCTRL_GROUP(emmc),
-	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -72,12 +72,12 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(nand),
 	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart0b),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
-	UNIPHIER_PINCTRL_GROUP(uart3b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3b),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
@@ -85,23 +85,23 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
 };
 
 static const char * const uniphier_pxs2_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c2",
-	"i2c3",
-	"i2c5",
-	"i2c6",
-	"nand",
-	"sd",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
-	"usb3",
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c5),
+	UNIPHIER_PINMUX_FUNCTION(i2c6),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_pxs2_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index 82fe33d..fe4d70d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -72,8 +72,8 @@ static const unsigned usb2_pins[] = {114, 115};
 static const int usb2_muxvals[] = {1, 1};
 
 static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
-	UNIPHIER_PINCTRL_GROUP(emmc),
-	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -81,30 +81,30 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(nand),
 	UNIPHIER_PINCTRL_GROUP(nand_cs1),
 	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(uart0),
-	UNIPHIER_PINCTRL_GROUP(uart1),
-	UNIPHIER_PINCTRL_GROUP(uart2),
-	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
 	UNIPHIER_PINCTRL_GROUP(usb0),
 	UNIPHIER_PINCTRL_GROUP(usb1),
 	UNIPHIER_PINCTRL_GROUP(usb2),
 };
 
 static const char * const uniphier_sld8_functions[] = {
-	"emmc",
-	"i2c0",
-	"i2c1",
-	"i2c2",
-	"i2c3",
-	"nand",
-	"sd",
-	"uart0",
-	"uart1",
-	"uart2",
-	"uart3",
-	"usb0",
-	"usb1",
-	"usb2",
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
 };
 
 static struct uniphier_pinctrl_socdata uniphier_sld8_pinctrl_socdata = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index ff0a368..4bb8932 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -80,7 +80,7 @@ struct uniphier_pinctrl_socdata {
 	.data = UNIPHIER_PIN_ATTR_PACKED(b),				\
 }
 
-#define UNIPHIER_PINCTRL_GROUP(grp)					\
+#define __UNIPHIER_PINCTRL_GROUP(grp)					\
 	{								\
 		.name = #grp,						\
 		.pins = grp##_pins,					\
@@ -90,6 +90,19 @@ struct uniphier_pinctrl_socdata {
 					  ARRAY_SIZE(grp##_muxvals)),	\
 	}
 
+#define __UNIPHIER_PINMUX_FUNCTION(func)	#func
+
+#ifdef CONFIG_SPL_BUILD
+#define UNIPHIER_PINCTRL_GROUP(grp)		{ .name = NULL }
+#define UNIPHIER_PINMUX_FUNCTION(func)		NULL
+#else
+#define UNIPHIER_PINCTRL_GROUP(grp)		__UNIPHIER_PINCTRL_GROUP(grp)
+#define UNIPHIER_PINMUX_FUNCTION(func)		__UNIPHIER_PINMUX_FUNCTION(func)
+#endif
+
+#define UNIPHIER_PINCTRL_GROUP_SPL(grp)		__UNIPHIER_PINCTRL_GROUP(grp)
+#define UNIPHIER_PINMUX_FUNCTION_SPL(func)	__UNIPHIER_PINMUX_FUNCTION(func)
+
 /**
  * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
  *
-- 
cgit v0.10.2


From fc9da85c6059fa204498c55c61b7dfa2ebf7fff8 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:39:01 +0900
Subject: pinctrl: uniphier: add Ethernet pin-mux settings

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e2bd9ae..e95870f 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -14,6 +14,9 @@ static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
 static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
 static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+					   16, 17};
+static const int ether_rmii_muxvals[] = {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4};
 static const unsigned i2c0_pins[] = {63, 64};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};
@@ -43,6 +46,7 @@ static const int usb2_muxvals[] = {0, 0};
 static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c3),
@@ -59,6 +63,7 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
 
 static const char * const uniphier_ld11_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c3),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 15ee469..e903196 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -14,6 +14,13 @@ static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
 static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
 static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38,
+					    39, 40, 41, 42, 43, 44, 45};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
+					   41, 42, 45};
+static const int ether_rmii_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {63, 64};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};
@@ -47,6 +54,8 @@ static const int usb3_muxvals[] = {0, 0};
 static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 	UNIPHIER_PINCTRL_GROUP(emmc),
 	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c3),
@@ -65,6 +74,8 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
 
 static const char * const uniphier_ld20_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c3),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 56d9d5b..dbb9499 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -27,6 +27,14 @@ static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
 static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
 static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+					  41, 42, 43, 136, 137, 138, 139, 140,
+					  141, 142};
+static const int ether_mii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					4, 4, 4, 4, 4, 4, 4};
+static const unsigned ether_rmii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+					   41, 42, 43};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned i2c0_pins[] = {102, 103};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {104, 105};
@@ -64,6 +72,8 @@ static const int usb2b_muxvals[] = {23, 23};
 static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -84,6 +94,8 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
 
 static const char * const uniphier_ld4_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index dd4a28c..8b40801 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -24,6 +24,14 @@ static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
 static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
 static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_rgmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					    150, 151, 152, 153, 154, 155, 156,
+					    157, 158};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					   150, 152, 154, 155, 158};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {109, 110};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {111, 112};
@@ -63,6 +71,8 @@ static const int usb3_muxvals[] = {0, 0};
 static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -84,6 +94,8 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
 
 static const char * const uniphier_ld6b_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index f87a2c6..dace726 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -16,6 +16,22 @@ static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
 static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
 static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {160, 161, 162, 163, 164, 165, 166,
+					  167, 168, 169, 170, 171, 172, 173,
+					  174, 175, 176, 177, 178, 179};
+static const int ether_mii_muxvals[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					0, 0, 0, 0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {160, 161, 162, 163, 164, 165, 167,
+					    168, 169, 170, 171, 172, 176, 177,
+					    178, 179};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {160, 161, 162, 165, 168, 169, 172,
+					   173, 176, 177, 178, 179};
+static const int ether_rmii_muxvals[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned ether_rmiib_pins[] = {161, 162, 165, 167, 168, 169, 172,
+					    173, 176, 177, 178, 179};
+static const int ether_rmiib_muxvals[] = {0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0};
 static const unsigned i2c0_pins[] = {142, 143};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {144, 145};
@@ -56,6 +72,10 @@ static const int usb3_muxvals[] = {0, 0};
 static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmiib),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -77,6 +97,9 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
 
 static const char * const uniphier_pro4_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 70fb168..9223eeb 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -20,6 +20,19 @@ static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
 static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
 static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
 static const int emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned ether_mii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					  150, 151, 152, 153, 154, 155, 156,
+					  158, 159, 199, 200, 201, 202};
+static const int ether_mii_muxvals[] = {8, 8, 8, 8, 10, 10, 10, 10, 10, 10, 10,
+					10, 10, 10, 10, 10, 12, 12, 12, 12};
+static const unsigned ether_rgmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					    150, 151, 152, 153, 154, 155, 156,
+					    157, 158};
+static const int ether_rgmii_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+					  8, 8, 8, 8};
+static const unsigned ether_rmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					   150, 152, 154, 155, 158};
+static const int ether_rmii_muxvals[] = {8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9};
 static const unsigned i2c0_pins[] = {109, 110};
 static const int i2c0_muxvals[] = {8, 8};
 static const unsigned i2c1_pins[] = {111, 112};
@@ -63,6 +76,9 @@ static const int usb3_muxvals[] = {8, 8};
 static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -86,6 +102,9 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
 
 static const char * const uniphier_pxs2_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index fe4d70d..cee0eb1 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -41,6 +41,14 @@ static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
 static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
 static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
 static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14,
+					  61, 63, 64, 65, 66, 67, 68};
+static const int ether_mii_muxvals[] = {13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+					13, 13, 27, 27, 27, 27, 27, 27, 27};
+static const unsigned ether_rmii_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13,
+					   14};
+static const int ether_rmii_muxvals[] = {13, 13, 13, 13, 13, 13, 13, 13, 13,
+					 13, 13, 13};
 static const unsigned i2c0_pins[] = {102, 103};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {104, 105};
@@ -74,6 +82,8 @@ static const int usb2_muxvals[] = {1, 1};
 static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
 	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
 	UNIPHIER_PINCTRL_GROUP(i2c0),
 	UNIPHIER_PINCTRL_GROUP(i2c1),
 	UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -92,6 +102,8 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
 
 static const char * const uniphier_sld8_functions[] = {
 	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
 	UNIPHIER_PINMUX_FUNCTION(i2c0),
 	UNIPHIER_PINMUX_FUNCTION(i2c1),
 	UNIPHIER_PINMUX_FUNCTION(i2c2),
-- 
cgit v0.10.2


From 1013aef3307e6cc3e1b654314aa9f48dc5cf62c7 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:39:02 +0900
Subject: ARM: dts: uniphier: add AIDET nodes

The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of
syscon block related with the interrupt controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index 8901a79..ffe04f5 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -260,6 +260,11 @@
 			};
 		};
 
+		aidet@5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
+
 		gic: interrupt-controller@5fe00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x5fe00000 0x10000>,	/* GICD */
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi
index f5cced5..7497539 100644
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi
@@ -265,6 +265,11 @@
 			};
 		};
 
+		aidet@5fc20000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5fc20000 0x200>;
+		};
+
 		gic: interrupt-controller@5fe00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x5fe00000 0x10000>,	/* GICD */
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 5629b7d..07f315a 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -274,6 +274,11 @@
 		pinctrl-0 = <&pinctrl_usb2>;
 		clocks = <&mio 5>, <&mio 6>;
 	};
+
+	aidet@61830000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x61830000 0x200>;
+	};
 };
 
 &refclk {
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 080fced..e0b28b8 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -400,6 +400,11 @@
 		clocks = <&mio 4>, <&mio 6>;
 	};
 
+	aidet@5fc20000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x5fc20000 0x200>;
+	};
+
 	usb0: usb@65a00000 {
 		compatible = "socionext,uniphier-xhci", "generic-xhci";
 		status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 5b7f6e8..05f961f 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -355,6 +355,11 @@
 		clock-frequency = <400000>;
 	};
 
+	aidet@5fc20000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x5fc20000 0x200>;
+	};
+
 	emmc: sdhc@68400000 {
 		compatible = "socionext,uniphier-sdhc";
 		status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 789713d..c3adaf1 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -349,6 +349,11 @@
 			clocks = <&mio 7>, <&mio 6>;
 		};
 
+		aidet@f1830000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0xf1830000 0x200>;
+		};
+
 		sysctrl: sysctrl@f1840000 {
 			compatible = "socionext,ph1-sld3-sysctrl";
 			reg = <0xf1840000 0x4000>;
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index f07a1d1..e0376a1 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -274,6 +274,11 @@
 		pinctrl-0 = <&pinctrl_usb2>;
 		clocks = <&mio 5>, <&mio 6>;
 	};
+
+	aidet@61830000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x61830000 0x200>;
+	};
 };
 
 &refclk {
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 0a8c049..23a6bfa 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -383,6 +383,11 @@
 		bus-width = <4>;
 	};
 
+	aidet@5fc20000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x5fc20000 0x200>;
+	};
+
 	usb0: usb@65a00000 {
 		compatible = "socionext,uniphier-xhci", "generic-xhci";
 		status = "disabled";
-- 
cgit v0.10.2


From e64a6b11411befbaf166443d02d8b10e06852f6a Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 29 Jun 2016 19:39:03 +0900
Subject: ARM: uniphier: add external IRQ setup code

I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index f853701..d35d38d 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -4,10 +4,47 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
+#include <libfdt.h>
+#include <linux/io.h>
+
 #include "init.h"
 #include "micro-support-card.h"
 #include "soc-info.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_setup_xirq(void)
+{
+	const void *fdt = gd->fdt_blob;
+	int soc_node, aidet_node;
+	const u32 *val;
+	unsigned long aidet_base;
+	u32 tmp;
+
+	soc_node = fdt_path_offset(fdt, "/soc");
+	if (soc_node < 0)
+		return;
+
+	aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
+	if (aidet_node < 0)
+		return;
+
+	val = fdt_getprop(fdt, aidet_node, "reg", NULL);
+	if (!val)
+		return;
+
+	aidet_base = fdt32_to_cpu(*val);
+
+	tmp = readl(aidet_base + 8);	/* AIDET DETCONFR2 */
+	tmp |= 0x00ff0000;		/* Set XIRQ0-7 low active */
+	writel(tmp, aidet_base + 8);
+
+	tmp = readl(0x55000090);	/* IRQCTL */
+	tmp |= 0x000000ff;
+	writel(tmp, 0x55000090);
+}
+
 int board_early_init_f(void)
 {
 	led_puts("U0");
@@ -81,6 +118,8 @@ int board_early_init_f(void)
 		break;
 	}
 
+	uniphier_setup_xirq();
+
 	led_puts("U2");
 
 	return 0;
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
index 6066b16..645b901 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
@@ -43,4 +43,9 @@ void uniphier_ld20_pin_init(void)
 	sg_set_pinsel(53, 0, 8, 4);	/* USB3OD   -> USB3OD */
 	sg_set_iectrl_range(46, 53);
 #endif
+
+	sg_set_pinsel(149, 14, 8, 4);	/* XIRQ0    -> XIRQ0 */
+	sg_set_iectrl(149);
+	sg_set_pinsel(153, 14, 8, 4);	/* XIRQ4    -> XIRQ4 */
+	sg_set_iectrl(153);
 }
-- 
cgit v0.10.2


From 8dfd6e2129e7eaba8f7fe20b14fda635241bd11b Mon Sep 17 00:00:00 2001
From: Praneeth Bajjuri <praneeth@ti.com>
Date: Tue, 21 Jun 2016 14:05:36 +0530
Subject: driver: qspi: correct QSPI disable CS reset value

Correcting QSPI disable/unselect CS reset value.
CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]

This is not causing any issue, but its better
to untouch the reserved bits.

Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index e69ec0d..9a372ad 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01
 #define MEM_CS(cs)                      ((cs + 1) << 8)
-#define MEM_CS_UNSELECT                 0xfffff0ff
+#define MEM_CS_UNSELECT                 0xfffff8ff
 #define MMAP_START_ADDR_DRA		0x5c000000
 #define MMAP_START_ADDR_AM43x		0x30000000
 #define CORE_CTRL_IO                    0x4a002558
-- 
cgit v0.10.2


From 4aae64c22abbe3a3003322654ae6cd08d5d4c889 Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Wed, 22 Jun 2016 17:10:26 -0500
Subject: ARM: AM437x: Align HS device variant defconfig filename

Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.

Furthermore, update and cleanup associated MAINTAINERS file.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Madan Srinivas <madans@ti.com>

diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
index 3d40b17..83645ac 100644
--- a/board/ti/am43xx/MAINTAINERS
+++ b/board/ti/am43xx/MAINTAINERS
@@ -4,6 +4,7 @@ S:	Maintained
 F:	board/ti/am43xx/
 F:	include/configs/am43xx_evm.h
 F:	configs/am43xx_evm_defconfig
-F:	configs/am43xx_evm_qspiboot_defconfig
 F:	configs/am43xx_evm_ethboot_defconfig
+F:	configs/am43xx_evm_qspiboot_defconfig
 F:	configs/am43xx_evm_usbhost_boot_defconfig
+F:	configs/am43xx_hs_evm_defconfig
diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig
deleted file mode 100644
index 4856a19..0000000
--- a/configs/am437x_hs_evm_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_ARM=y
-CONFIG_AM43XX=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-# Device tree file can be same on HS evm
-CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL=y
-CONFIG_ISW_ENTRY_ADDR=0x40302ae0
-CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am437x-gp-evm"
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0403
-CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
new file mode 100644
index 0000000..4856a19
--- /dev/null
+++ b/configs/am43xx_hs_evm_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+# Device tree file can be same on HS evm
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_SPL=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_SPL_OF_LIBFDT=y
-- 
cgit v0.10.2


From ea72ee72f2e6dbce1125f0b37559ad547b7ee802 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 16:22:59 +0900
Subject: ARM: socfpga: move CONFIG_BOOTDELAY to Kconfig for IS1 board

This recently added board missed the tree-wide migration of
CONFIG_BOOTDELAY.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 7d43c72..658770b 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -9,14 +9,13 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_MEMTEST is not set
 # CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_MMC is not set
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
@@ -36,7 +35,6 @@ CONFIG_SYS_I2C_DW=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_USE_4K_SECTORS=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h
index 6f5dfce..cc07253 100644
--- a/include/configs/socfpga_is1.h
+++ b/include/configs/socfpga_is1.h
@@ -19,7 +19,6 @@
 #define PHYS_SDRAM_1_SIZE		0x10000000
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_LOADADDR		0x01000000
-- 
cgit v0.10.2


From 9060970f4d89c79212982afbf9148dcbc94dcf75 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 16:23:00 +0900
Subject: doc: bootdelay: drop explanation about CONFIG_BOOTDELAY from README

The same information now exists in common/Kconfig.  Do not duplicate
documentation from the point of view of maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/README b/README
index 03bed18..26d5ad2 100644
--- a/README
+++ b/README
@@ -890,23 +890,6 @@ The following options need to be configured:
 		'Sane' compilers will generate smaller code if
 		CONFIG_PRE_CON_BUF_SZ is a power of 2
 
-- Boot Delay:	CONFIG_BOOTDELAY - in seconds
-		Delay before automatically booting the default image;
-		set to -1 to disable autoboot.
-		set to -2 to autoboot with no delay and not check for abort
-		(even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
-
-		See doc/README.autoboot for these options that
-		work with CONFIG_BOOTDELAY. None are required.
-		CONFIG_BOOT_RETRY_TIME
-		CONFIG_BOOT_RETRY_MIN
-		CONFIG_AUTOBOOT_KEYED
-		CONFIG_AUTOBOOT_PROMPT
-		CONFIG_AUTOBOOT_DELAY_STR
-		CONFIG_AUTOBOOT_STOP_STR
-		CONFIG_ZERO_BOOTDELAY_CHECK
-		CONFIG_RESET_TO_RETRY
-
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
diff --git a/common/Kconfig b/common/Kconfig
index af7ead8..e08541b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -168,6 +168,8 @@ config BOOTDELAY
 	  set to -2 to autoboot with no delay and not check for abort
 	  (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
 
+	  See doc/README.autoboot for details.
+
 config CONSOLE_RECORD
 	bool "Console recording"
 	help
-- 
cgit v0.10.2


From 2fbb8462b0e18893b4b739705db047ffda82d4fc Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 16:23:01 +0900
Subject: autoboot: remove CONFIG_ZERO_BOOTDELAY_CHECK

As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.

To sum up, the autoboot behaves as follows:

 [1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    autoboot with no delay, with no check for abort

 [3] CONFIG_BOOTDELAY=-1
    disable autoboot

 [4] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK.  We can control all the
cases only by CONFIG_BOOTDELAY, like this:

 [1] CONFIG_BOOTDELAY=0
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=-1
    disable autoboot

 [3] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

This commit converts the logic as follow:
  CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    --> CONFIG_BOOTDELAY=-2

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicronenergy.com>
Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

diff --git a/common/Kconfig b/common/Kconfig
index e08541b..8adc821 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -164,9 +164,9 @@ config BOOTDELAY
 	depends on AUTOBOOT
 	help
 	  Delay before automatically running bootcmd;
+	  set to 0 to autoboot with no delay, but you can stop it by key input.
 	  set to -1 to disable autoboot.
 	  set to -2 to autoboot with no delay and not check for abort
-	  (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
 
 	  See doc/README.autoboot for details.
 
diff --git a/common/autoboot.c b/common/autoboot.c
index 223e062..35deece 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -187,10 +187,8 @@ static int abortboot_keyed(int bootdelay)
 	int abort;
 	uint64_t etime = endtick(bootdelay);
 
-#ifndef CONFIG_ZERO_BOOTDELAY_CHECK
-	if (bootdelay == 0)
+	if (bootdelay < 0)
 		return 0;
-#endif
 
 #  ifdef CONFIG_AUTOBOOT_PROMPT
 	/*
@@ -230,7 +228,6 @@ static int abortboot_normal(int bootdelay)
 		printf("Hit any key to stop autoboot: %2d ", bootdelay);
 #endif
 
-#if defined CONFIG_ZERO_BOOTDELAY_CHECK
 	/*
 	 * Check if key already pressed
 	 * Don't check if bootdelay < 0
@@ -242,7 +239,6 @@ static int abortboot_normal(int bootdelay)
 			abort = 1;	/* don't auto boot	*/
 		}
 	}
-#endif
 
 	while ((bootdelay > 0) && (!abort)) {
 		--bootdelay;
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index f8d9de5..cf2800b 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -3,7 +3,7 @@ CONFIG_TARGET_BRPPT1=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index 85ddbe7..a14a130 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -3,7 +3,7 @@ CONFIG_TARGET_BRPPT1=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index f023ebf..fee9973 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -4,7 +4,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
 CONFIG_SPI_BOOT=y
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 13617d3..2567a40 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_BRXRE1=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_BOOTM is not set
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 5257312..c529c7c 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_CAIRO=y
 CONFIG_SPL=y
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Cairo # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
index b6f14db..efb8ad6 100644
--- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
 CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig
index 2c45aff..45e8b8f 100644
--- a/configs/controlcenterd_TRAILBLAZER_defconfig
+++ b/configs/controlcenterd_TRAILBLAZER_defconfig
@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_CONTROLCENTERD=y
 CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig
index 801c959..ebdc105 100644
--- a/configs/omap3_evm_quick_mmc_defconfig
+++ b/configs/omap3_evm_quick_mmc_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
 CONFIG_SPL=y
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig
index 8815fca..52b08b8 100644
--- a/configs/omap3_evm_quick_nand_defconfig
+++ b/configs/omap3_evm_quick_nand_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
 CONFIG_SPL=y
-CONFIG_BOOTDELAY=0
+CONFIG_BOOTDELAY=-2
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
diff --git a/doc/README.autoboot b/doc/README.autoboot
index 227e3b5..30fd0b0 100644
--- a/doc/README.autoboot
+++ b/doc/README.autoboot
@@ -132,14 +132,6 @@ What they do
 	provides an escape sequence from the limited "password"
 	strings.
 
-
-  CONFIG_ZERO_BOOTDELAY_CHECK
-
-	If this option is defined, you can stop the autoboot process
-	by hitting a key even in that case when "bootdelay" has been
-	set to 0. You can set "bootdelay" to a negative value to
-	prevent the check for console input.
-
   CONFIG_RESET_TO_RETRY
 
 	(Only effective when CONFIG_BOOT_RETRY_TIME is also set)
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index c5c3a84..8010f28 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -98,8 +98,6 @@
 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index db953b9..ffae107 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -121,8 +121,6 @@
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 79027e2..6ef39db 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -99,7 +99,6 @@
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
 
 #define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
 #define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index e7c7a99..9203f85 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -91,7 +91,6 @@
 
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
 
 #define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
 #define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 558f3e2..c2e067a 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -117,7 +117,6 @@
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 5f17d76..619222f 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -92,7 +92,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 868ca84..d3183ff 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -312,7 +312,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
 #define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 968e1df..a60c7c1 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -117,7 +117,6 @@
 
 #define CONFIG_BOOT_RETRY_TIME		-1
 #define CONFIG_RESET_TO_RETRY
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_NETMASK			255.255.255.0
 #define CONFIG_IPADDR			10.0.0.110
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index dde98f6..e87cea8 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -105,7 +105,6 @@
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 7ec404d..8f17dd1 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -322,7 +322,6 @@
  */
 
 #undef  CONFIG_BOOTARGS
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_SYS_AUTOLOAD	"n"
 
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 2666ca6..9bda7fa 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -78,7 +78,6 @@
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 	/* include version env variable */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
 
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index f44f71c..51a16eb 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -148,7 +148,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
 #define CONFIG_INITRD_TAG		/* send initrd params	*/
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 #define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
 #define CONFIG_BOOTARGS		"console=" __stringify(ACFG_CONSOLE_DEV) "," \
 			__stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 3b10360..9c2b9e8 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -214,7 +214,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS           ""
 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
-#define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 #define CONFIG_RESET_TO_RETRY
 
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index de1999d..03dc3cc 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -145,8 +145,6 @@
 							/* devices */
 
 /* Environment information */
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"usbtty=cdc_acm\0" \
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 87e41bf..ea9983b 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -152,8 +152,6 @@
 							/* devices */
 
 /* Environment information */
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"baudrate=115200\0" \
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 5076540..9bb975a 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -98,7 +98,6 @@
 #undef CONFIG_SPL_NAND_SUPPORT
 #undef CONFIG_SYS_MONITOR_LEN
 #undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_ENV_SIZE			(16 * 1024)
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 73f53d4..22f4322 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -178,7 +178,6 @@
  */
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 1145e37..c6d6d41 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -379,7 +379,6 @@
 #define CONFIG_CMDLINE_EDITING	1
 
 #define CONFIG_MX_CYCLIC	1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 445a346..521604e 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -27,8 +27,6 @@
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
-
 /*
  * Configure PLL
  */
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 98474d3..38298a2 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -51,8 +51,6 @@
 #define CONFIG_EXYNOS_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 /* PWM */
 #define CONFIG_PWM
 
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 8d79ea8..2845a80 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -33,8 +33,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* call board_early_init_f*/
 #define CONFIG_MISC_INIT_R		1	/* call misc_init_r()     */
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
-
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 6a8660b..c5e6828 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -543,8 +543,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
 #define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
-
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/intip.h b/include/configs/intip.h
index f3db077..4984dc1 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -48,8 +48,6 @@
 #define CONFIG_BOARD_TYPES		1	/* support board types */
 #define CFG_ALT_MEMTEST
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
-
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
diff --git a/include/configs/io.h b/include/configs/io.h
index 0dd7f00..544d044 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -33,8 +33,6 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
-
 /* new uImage format support */
 #define CONFIG_FIT_DISABLE_SHA256
 
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 1a6275e..14ffb33 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -44,8 +44,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
-
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 43688c7..d85a76c 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -35,8 +35,6 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
-
 /* new uImage format support */
 #define CONFIG_FIT_DISABLE_SHA256
 
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index f52750e..04f593e 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -168,7 +168,6 @@
 #define CONFIG_SERIAL_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_SETUP_INITRD_TAG
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 #define CONFIG_BOOTCOMMAND \
 	"if mmc rescan; then " \
 		"if run loadbootscr; then " \
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index fbcad4a..df76a20 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -69,8 +69,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 /*
  * BOOTP options
  */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 3c11e2a..49a8b3f 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -47,7 +47,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_CMDLINE_EDITING		/* cmd line edit/history */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress w/no delay */
 
 /* Hardware drivers */
 
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 80d5d6c..32f059d 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -67,11 +67,6 @@ Serial console configuration
 #define MTDPARTS_DEFAULT   	"mtdparts=physmap-flash.0:256k(ubootl)," \
 	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
 
-/*-----------------------------------------------------------------------------
-Autobooting
------------------------------------------------------------------------------*/
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
-					/* even with bootdelay=0 */
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index c15580c..bc01ae9 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -31,9 +31,6 @@
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 #define CONFIG_ENV_OVERWRITE	1
 
-/* check for keypress on bootdelay==0 */
-/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
-
 #define CONFIG_SYS_TEXT_BASE		0x0FFC0000
 #define CONFIG_SYS_SDRAM_BASE		(0x08000000)
 #define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index afea884..87e51d0 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -94,8 +94,6 @@
 				",12m(modem)"\
 				",60m(qboot)\0"
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 /* partitions definitions */
 #define PARTS_CSA			"csa-mmc"
 #define PARTS_BOOTLOADER	"u-boot"
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index f733c35..e328842 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -82,7 +82,6 @@
 /* autoboot */
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_RESET_TO_RETRY
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_IPADDR		10.0.0.110
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index fe41d17..84a188a 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -71,9 +71,6 @@
 #define CONFIG_CMD_ONENAND
 #define CONFIG_CMD_MTDPARTS
 
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 7981a8d..b33bec9 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -117,7 +117,6 @@
 
 /* Boot options */
 #define CONFIG_SYS_LOAD_ADDR		0x23000000
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 8344f15..fd6c70e 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -95,7 +95,6 @@
 
 /* Boot options */
 #define CONFIG_SYS_LOAD_ADDR		0x23000000
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 43ba84a..7f6cb93 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -178,7 +178,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_MISC_INIT_R
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_SYS_MEMTEST_START		0x00800000
 #define CONFIG_SYS_MEMTEST_END			0x04000000
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 36561e0..5fabbad 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -581,8 +581,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
 #define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
-
 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index dda70c5..1caa858 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -64,7 +64,6 @@
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PREBOOT
 
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index aed3931..127a968 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -46,7 +46,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_SILENT_CONSOLE
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /* Clock Defines */
 #define V_OSCK				26000000 /* Clock output from T2 */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 77057d0..4ebaf84 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -147,8 +147,6 @@
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
 /*
  * Network Configuration
  */
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index 35fe9de..4ae179c 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -150,6 +150,5 @@
 	"bootdelay=0\0"
 
 #endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #endif
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index ba222f9..eae7eba 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -174,8 +174,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
 #define CONFIG_LOADADDR			0x80008000
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 71c0b45..748e331 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -145,7 +145,6 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_SYS_MEMTEST_START		0x00800000
 #define CONFIG_SYS_MEMTEST_END			0x04000000
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index e97e9d0..39c1bd8 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -57,7 +57,6 @@
 #define CONFIG_CMDLINE_EDITING		/* add command line history     */
 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE		/* include version env variable */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download  */
-- 
cgit v0.10.2


From d8da8298ad9b5a379d6fb7f079a3a1a591147a5e Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 16:23:02 +0900
Subject: autoboot: rename abortboot_{keyed, normal} to __abortboot

Because abortboot_keyed() and abortboot_normal() are not compiled
at the same time, we can rename both of them to __abortboot().
This allows to drop #ifdef from the caller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/common/autoboot.c b/common/autoboot.c
index 35deece..eb31c88 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -182,7 +182,7 @@ static int passwd_abort(uint64_t etime)
  * Watch for 'delay' seconds for autoboot stop or autoboot delay string.
  * returns: 0 -  no key string, allow autoboot 1 - got key string, abort
  */
-static int abortboot_keyed(int bootdelay)
+static int __abortboot(int bootdelay)
 {
 	int abort;
 	uint64_t etime = endtick(bootdelay);
@@ -216,7 +216,7 @@ static int abortboot_keyed(int bootdelay)
 static int menukey;
 #endif
 
-static int abortboot_normal(int bootdelay)
+static int __abortboot(int bootdelay)
 {
 	int abort = 0;
 	unsigned long ts;
@@ -274,11 +274,7 @@ static int abortboot_normal(int bootdelay)
 
 static int abortboot(int bootdelay)
 {
-#ifdef CONFIG_AUTOBOOT_KEYED
-	return abortboot_keyed(bootdelay);
-#else
-	return abortboot_normal(bootdelay);
-#endif
+	return __abortboot(bootdelay);
 }
 
 static void process_fdt_options(const void *blob)
-- 
cgit v0.10.2


From 09b9d9e55f64259763c20217f7743dbeec9bb055 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 16:23:03 +0900
Subject: autoboot: move CONFIG_SILENT_CONSOLE handling

Factor out the same code from the callees to the caller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/common/autoboot.c b/common/autoboot.c
index eb31c88..fb13139 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -202,11 +202,6 @@ static int __abortboot(int bootdelay)
 	if (!abort)
 		debug_bootkeys("key timeout\n");
 
-#ifdef CONFIG_SILENT_CONSOLE
-	if (abort)
-		gd->flags &= ~GD_FLG_SILENT;
-#endif
-
 	return abort;
 }
 
@@ -263,18 +258,22 @@ static int __abortboot(int bootdelay)
 
 	putc('\n');
 
-#ifdef CONFIG_SILENT_CONSOLE
-	if (abort)
-		gd->flags &= ~GD_FLG_SILENT;
-#endif
-
 	return abort;
 }
 # endif	/* CONFIG_AUTOBOOT_KEYED */
 
 static int abortboot(int bootdelay)
 {
-	return __abortboot(bootdelay);
+	int abort;
+
+	abort = __abortboot(bootdelay);
+
+#ifdef CONFIG_SILENT_CONSOLE
+	if (abort)
+		gd->flags &= ~GD_FLG_SILENT;
+#endif
+
+	return abort;
 }
 
 static void process_fdt_options(const void *blob)
-- 
cgit v0.10.2


From 4632739202ae4d1f67c5591551598be0a80d501d Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 16:23:04 +0900
Subject: autoboot: move bootdelay >= 0 check to abortboot()

Move the bootdelay >= 0 check to the caller, which simplifies
the callees.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/common/autoboot.c b/common/autoboot.c
index fb13139..c52bad8 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -187,9 +187,6 @@ static int __abortboot(int bootdelay)
 	int abort;
 	uint64_t etime = endtick(bootdelay);
 
-	if (bootdelay < 0)
-		return 0;
-
 #  ifdef CONFIG_AUTOBOOT_PROMPT
 	/*
 	 * CONFIG_AUTOBOOT_PROMPT includes the %d for all boards.
@@ -219,20 +216,16 @@ static int __abortboot(int bootdelay)
 #ifdef CONFIG_MENUPROMPT
 	printf(CONFIG_MENUPROMPT);
 #else
-	if (bootdelay >= 0)
-		printf("Hit any key to stop autoboot: %2d ", bootdelay);
+	printf("Hit any key to stop autoboot: %2d ", bootdelay);
 #endif
 
 	/*
 	 * Check if key already pressed
-	 * Don't check if bootdelay < 0
 	 */
-	if (bootdelay >= 0) {
-		if (tstc()) {	/* we got a key press	*/
-			(void) getc();  /* consume input	*/
-			puts("\b\b\b 0");
-			abort = 1;	/* don't auto boot	*/
-		}
+	if (tstc()) {	/* we got a key press	*/
+		(void) getc();  /* consume input	*/
+		puts("\b\b\b 0");
+		abort = 1;	/* don't auto boot	*/
 	}
 
 	while ((bootdelay > 0) && (!abort)) {
@@ -264,9 +257,10 @@ static int __abortboot(int bootdelay)
 
 static int abortboot(int bootdelay)
 {
-	int abort;
+	int abort = 0;
 
-	abort = __abortboot(bootdelay);
+	if (bootdelay >= 0)
+		abort = __abortboot(bootdelay);
 
 #ifdef CONFIG_SILENT_CONSOLE
 	if (abort)
-- 
cgit v0.10.2


From df6b506f16d2666ebac5b9d61b67bb6bbfaea6de Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Wed, 29 Jun 2016 14:50:41 +0530
Subject: ti_omap5_common: Find right dtb file for DRA72-RevC Evm

DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 0394e4e..6a4d027 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -413,10 +413,14 @@ int board_late_init(void)
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	char *name = "unknown";
 
-	if (is_dra72x())
-		name = "dra72x";
-	else
+	if (is_dra72x()) {
+		if (board_is_dra72x_revc_or_later())
+			name = "dra72x-revc";
+		else
+			name = "dra72x";
+	} else {
 		name = "dra7xx";
+	}
 
 	set_board_info_env(name);
 
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 2e4c8e9..3589cdc 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -100,6 +100,8 @@
 			"setenv fdtfile omap5-uevm.dtb; fi; " \
 		"if test $board_name = dra7xx; then " \
 			"setenv fdtfile dra7-evm.dtb; fi;" \
+		"if test $board_name = dra72x-revc; then " \
+			"setenv fdtfile dra72-evm-revc.dtb; fi;" \
 		"if test $board_name = dra72x; then " \
 			"setenv fdtfile dra72-evm.dtb; fi;" \
 		"if test $board_name = beagle_x15; then " \
-- 
cgit v0.10.2


From d90bb439335386b3ae6ada89b89720cc66ec9352 Mon Sep 17 00:00:00 2001
From: Steve Rae <steve.rae@raedomain.com>
Date: Wed, 29 Jun 2016 13:42:01 -0700
Subject: mmc: increase MMC SDHCI read status timeout

Otherwise,  ocassionally see errors like this:
  Flashing sparse image at offset 2078720
  Flashing Sparse Image
  sdhci_send_command: Timeout for status update!
  mmc fail to send stop cmd
  write_sparse_image: Write failed, block #2181088 [0]

This does not affect the actual writing speed, which is controlled by
the default value:
  CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT

It only increases the retries when reading:
  SDHCI_INT_STATUS
to avoid the timeout error.

Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 5c71ab8..604f18d 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -127,6 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 #define CONFIG_SDHCI_CMD_MAX_TIMEOUT		3200
 #endif
 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
+#define SDHCI_READ_STATUS_TIMEOUT		1000
 
 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		       struct mmc_data *data)
@@ -243,9 +244,9 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		if (stat & SDHCI_INT_ERROR)
 			break;
 	} while (((stat & mask) != mask) &&
-		 (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT));
+		 (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT));
 
-	if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) {
+	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
 			return 0;
 		else {
-- 
cgit v0.10.2


From 0e1e587ff4fc2d81ad4f6313f02c5ca4c8ceea01 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 1 Jul 2016 17:37:17 -0400
Subject: Prepare v2016.07-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 0c47bb6..09a18e1 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From cd8b35d2e14f598ab0e5c8a211495b675b978915 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 26 Jun 2016 13:56:01 +0200
Subject: sunxi: spl: Fix DRAM info printing

The switch to simple_printf was causing the SPL dram info to show as:

DRAM: u MiB

This fixes this by switching from %lu to %d for printing the DRAM size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index d09cf6d..c8bf316 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -529,7 +529,7 @@ void sunxi_board_init(void)
 #endif
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
-	printf(" %lu MiB\n", ramsize >> 20);
+	printf(" %d MiB\n", (int)(ramsize >> 20));
 	if (!ramsize)
 		hang();
 
-- 
cgit v0.10.2


From 9acebe8a18788c5a0d7b154e812cf2d9dfbab68f Mon Sep 17 00:00:00 2001
From: Olliver Schinagl <oliver@schinagl.nl>
Date: Mon, 13 Jun 2016 18:13:07 +0200
Subject: sunxi: Add missing boot_media fields in the SPL header

Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index a0f33b0..ec73379 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -20,6 +20,8 @@
 
 /* The low 8-bits of the 'boot_media' field in the SPL header */
 #define SUNXI_BOOTED_FROM_MMC0	0
+#define SUNXI_BOOTED_FROM_NAND	1
+#define SUNXI_BOOTED_FROM_MMC2	2
 #define SUNXI_BOOTED_FROM_SPI	3
 
 /* boot head definition from sun4i boot code */
-- 
cgit v0.10.2


From d2a6af052845f671204ff978bc70bcfba8767cc9 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Fri, 24 Jun 2016 14:33:35 +0200
Subject: sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)

The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.

The DTS file is identical to the one submitted to the upstream kernel.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5d463ce..ef573ec 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -234,7 +234,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
 dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-q8-tablet.dtb \
-	sun8i-a33-sinlinx-sina33.dtb
+	sun8i-a33-sinlinx-sina33.dtb \
+	sun8i-r16-parrot.dtb
 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-allwinner-h8homlet-v2.dtb \
 	sun8i-a83t-cubietruck-plus.dtb \
diff --git a/arch/arm/dts/sun8i-r16-parrot.dts b/arch/arm/dts/sun8i-r16-parrot.dts
new file mode 100644
index 0000000..39c40be
--- /dev/null
+++ b/arch/arm/dts/sun8i-r16-parrot.dts
@@ -0,0 +1,348 @@
+/*
+ * Copyright 2016 Quentin Schulz
+ *
+ * Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Allwinner R16 EVB (Parrot)";
+	compatible = "allwinner,parrot", "allwinner,sun8i-a33";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_parrot>;
+
+		led1 {
+			label = "parrot:led1:usr";
+			gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+		};
+
+		led2 {
+			label = "parrot:led2:usr";
+			gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+		};
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+	};
+
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+
+	/* FIXME: An as-yet-unknown accelerometer is connected to this i2c bus. */
+};
+
+&lradc {
+	vref-supply = <&reg_aldo3>;
+	status = "okay";
+
+	button@0 {
+		label = "V+";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <190000>;
+	};
+
+	button@1 {
+		label = "V-";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <390000>;
+	};
+
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>;
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>;
+	vmmc-supply = <&reg_aldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&mmc2_8bit_pins {
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&pio {
+	mmc0_cd_pin_parrot: mmc0_cd_pin@0 {
+		allwinner,pins = "PD14";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	led_pins_parrot: led_pins@0 {
+		allwinner,pins = "PE16", "PE17";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_id_det: usb0_id_detect_pin@0 {
+		allwinner,pins = "PD10";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	usb1_vbus_pin_parrot: usb1_vbus_pin@0 {
+		allwinner,pins = "PD12";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	wifi_reset_pin_parrot: wifi_reset_pin@0 {
+		allwinner,pins = "PL6";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		drivevbus-supply = <&reg_vcc5v0>;
+		x-powers,drive-vbus-en;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	/*
+	 * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
+	 * Remove next line once it is possible to sync two regulators.
+	 */
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+	/*
+	 * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
+	 * Remove next line once it is possible to sync two regulators.
+	 */
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi1";
+};
+
+&reg_dldo3 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0-csi";
+};
+
+&reg_drivevbus {
+	regulator-name = "usb0-vbus";
+	status = "okay";
+};
+
+&reg_eldo1 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_eldo2 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-dsp";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "eldo3";
+};
+
+&reg_usb1_vbus {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_vbus_pin_parrot>;
+	gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_det>;
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index de5207e..d2dfebe 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -202,6 +202,11 @@ M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
 S:	Maintained
 F:	configs/MSI_Primo81_defconfig
 
+R16 EVB PARROT BOARD
+M:	Quentin Schulz <quentin.schulz@free-electrons.com>
+S:	Maintained
+F:	configs/parrot_r16_defconfig
+
 SINLINX SINA31s BOARD
 M:	Chen-Yu Tsai <wens@csie.org>
 S:	Maintained
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
new file mode 100644
index 0000000..211a41e
--- /dev/null
+++ b/configs/parrot_r16_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_MACH_SUN8I=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+
+CONFIG_CMD_MMC=y
+CONFIG_MMC0_CD_PIN="PD14"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC2_PINS="PC"
+
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=15291
+CONFIG_ODT_EN=y
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PD12"
+
+CONFIG_AXP_GPIO=y
+CONFIG_USB0_ID_DET="PD10"
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
-- 
cgit v0.10.2


From 7a54f5177ac3d8d972622dd9f85964c23a6df68d Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Thu, 16 Jun 2016 10:55:00 +0200
Subject: arc: Use "-mcpu=archs" instead of deprecated "-marchs" for ARC HS

Newer ARC toolchains don't support "-marchs" option any longer.
Instead "-mcpu=archs" should be used. What's also important older
toiolchains that support ARC HS cores will also happily accept
"-mcpu=archs" so that's a very safe move.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 74943d9..7c974f0 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -43,11 +43,11 @@ PLATFORM_CPPFLAGS += -marcem
 endif
 
 ifdef CONFIG_CPU_ARCHS34
-PLATFORM_CPPFLAGS += -marchs
+PLATFORM_CPPFLAGS += -mcpu=archs
 endif
 
 ifdef CONFIG_CPU_ARCHS38
-PLATFORM_CPPFLAGS += -marchs
+PLATFORM_CPPFLAGS += -mcpu=archs
 endif
 
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
-- 
cgit v0.10.2


From c7dea6e259d68cc0645daf3fe2188e077748ef9e Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Mon, 4 Jul 2016 11:37:55 +0300
Subject: arc: make global_data.h usable in assembly files

Currently on attempt to use global_data.h in an assembly file following
will happen:
-------------------->8-----------------
./arch/arc/include/asm/global_data.h: Assembler messages:
./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{'
./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}'
scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed
-------------------->8-----------------

In this change we disable struct arch_global_data in ASM which fixes
the issue above.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
index e25b966..f0242f1 100644
--- a/arch/arc/include/asm/global_data.h
+++ b/arch/arc/include/asm/global_data.h
@@ -7,9 +7,11 @@
 #ifndef	__ASM_ARC_GLOBAL_DATA_H
 #define __ASM_ARC_GLOBAL_DATA_H
 
+#ifndef __ASSEMBLY__
 /* Architecture-specific global data */
 struct arch_global_data {
 };
+#endif /* __ASSEMBLY__ */
 
 #include <asm-generic/global_data.h>
 
-- 
cgit v0.10.2


From 2138fd6d5d358bcfef6631300763c16a70f2af3d Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 3 Jul 2016 20:22:04 +0200
Subject: usb: dm: Add a usb_for_each_root_dev() helper function

Iterating over usb-root devs and doing something for all of them is
a bit tricky with dm, factor out the proven usb_show_tree() for this
into a helper function.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/cmd/usb.c b/cmd/usb.c
index 58d9db2..5453c0d 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -438,9 +438,11 @@ static void usb_show_subtree(struct usb_device *dev)
 	usb_show_tree_graph(dev, &preamble[0]);
 }
 
-void usb_show_tree(void)
-{
 #ifdef CONFIG_DM_USB
+typedef void (*usb_dev_func_t)(struct usb_device *udev);
+
+static void usb_for_each_root_dev(usb_dev_func_t func)
+{
 	struct udevice *bus;
 
 	for (uclass_find_first_device(UCLASS_USB, &bus);
@@ -455,9 +457,16 @@ void usb_show_tree(void)
 		device_find_first_child(bus, &dev);
 		if (dev && device_active(dev)) {
 			udev = dev_get_parent_priv(dev);
-			usb_show_subtree(udev);
+			func(udev);
 		}
 	}
+}
+#endif
+
+void usb_show_tree(void)
+{
+#ifdef CONFIG_DM_USB
+	usb_for_each_root_dev(usb_show_subtree);
 #else
 	struct usb_device *udev;
 	int i;
-- 
cgit v0.10.2


From e6e188f5623e3db7fcba785f4246d16425dd2104 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 3 Jul 2016 20:22:05 +0200
Subject: usb: dm: Make "usb info" use usb_for_each_root_dev()

The old dm "usb info" implementation has several issues:

1) NULL pointer deref when a bus has no children
2) Not showing usb devices on busses without an emulated root-hub (otg host)
3) Attempting to show devices on inactive busses
4) "usb info" Would cause some hosts to get re-probed something which only
   "usb reset" should do

TL;DR: proper iterating over usb bus root devs is hard, use the helper
for it.

Reported-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/cmd/usb.c b/cmd/usb.c
index 5453c0d..455127c 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -593,39 +593,20 @@ static void do_usb_start(void)
 }
 
 #ifdef CONFIG_DM_USB
-static void show_info(struct udevice *dev)
+static void usb_show_info(struct usb_device *udev)
 {
 	struct udevice *child;
-	struct usb_device *udev;
 
-	udev = dev_get_parent_priv(dev);
 	usb_display_desc(udev);
 	usb_display_config(udev);
-	for (device_find_first_child(dev, &child);
+	for (device_find_first_child(udev->dev, &child);
 	     child;
 	     device_find_next_child(&child)) {
-		if (device_active(child))
-			show_info(child);
-	}
-}
-
-static int usb_device_info(void)
-{
-	struct udevice *bus;
-
-	for (uclass_first_device(UCLASS_USB, &bus);
-	     bus;
-	     uclass_next_device(&bus)) {
-		struct udevice *hub;
-
-		device_find_first_child(bus, &hub);
-		if (device_get_uclass_id(hub) == UCLASS_USB_HUB &&
-		    device_active(hub)) {
-			show_info(hub);
+		if (device_active(child)) {
+			udev = dev_get_parent_priv(child);
+			usb_show_info(udev);
 		}
 	}
-
-	return 0;
 }
 #endif
 
@@ -681,7 +662,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (strncmp(argv[1], "inf", 3) == 0) {
 		if (argc == 2) {
 #ifdef CONFIG_DM_USB
-			usb_device_info();
+			usb_for_each_root_dev(usb_show_info);
 #else
 			int d;
 			for (d = 0; d < USB_MAX_DEVICE; d++) {
-- 
cgit v0.10.2


From 12c67d7522d77c5aa5ee1e5ec4147b569ccb7666 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 5 Jul 2016 17:40:27 +0200
Subject: powerpc: mpc85xx: Do not build errata command in SPL

The errata command is useless in SPL, so don't build it. This fixes
multiple build failures on PowerPC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: York Sun <york.sun@nxp.com>
Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 65c26c0..f4c4fe2 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -26,7 +26,9 @@ else
 
 obj-$(CONFIG_MP)	+= release.o
 
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
+endif
 obj-$(CONFIG_CPM2)	+= commproc.o
 
 obj-$(CONFIG_CPM2)	+= ether_fcc.o
-- 
cgit v0.10.2


From 70c440e5bdca097915b71170f9532ae4faad735a Mon Sep 17 00:00:00 2001
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Date: Sun, 28 Feb 2016 22:40:02 +0100
Subject: rockchip: video: Lower hpd wait time

Waiting 30 seconds for the hpd to go high seems a bit much, especially
on headless boots. Lowering the timeout to 300ms.

Sending as RFC because frankly i don't know what a sensible timeout is
here, but 30 seconds is clearly not it :)

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dropped RFC tag:
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 8dd2c87..7976c5e 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -666,7 +666,7 @@ static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
 		if (hdmi_get_plug_in_status(regs))
 			return 0;
 		udelay(100);
-	} while (get_timer(start) < 30000);
+	} while (get_timer(start) < 300);
 
 	return -1;
 }
-- 
cgit v0.10.2


From 3cfc6be4a85c722e9e0a657c7696f5fa1ac2ed48 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 21 Jun 2016 12:47:51 -0600
Subject: pci: tegra: correctly program PADS_REFCLK registers

The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index c5b04da..1aa56fc 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -154,15 +154,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PADS_REFCLK_CFG_PREDI_SHIFT		8  /* 11:8 */
 #define PADS_REFCLK_CFG_DRVI_SHIFT		12 /* 15:12 */
 
-/* Default value provided by HW engineering is 0xfa5c */
-#define PADS_REFCLK_CFG_VALUE \
-	( \
-		(0x17 << PADS_REFCLK_CFG_TERM_SHIFT)   | \
-		(0    << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
-		(0xa  << PADS_REFCLK_CFG_PREDI_SHIFT)  | \
-		(0xf  << PADS_REFCLK_CFG_DRVI_SHIFT)     \
-	)
-
 #define RP_VEND_XP	0x00000F00
 #define  RP_VEND_XP_DL_UP	(1 << 30)
 
@@ -198,6 +189,8 @@ struct tegra_pcie_soc {
 	unsigned int num_ports;
 	unsigned long pads_pll_ctl;
 	unsigned long tx_ref_sel;
+	u32 pads_refclk_cfg0;
+	u32 pads_refclk_cfg1;
 	bool has_pex_clkreq_en;
 	bool has_pex_bias_ctrl;
 	bool has_cml_clk;
@@ -628,11 +621,9 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
 	pads_writel(pcie, value, soc->pads_pll_ctl);
 
 	/* configure the reference clock driver */
-	value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
-	pads_writel(pcie, value, PADS_REFCLK_CFG0);
-
+	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
 	if (soc->num_ports > 2)
-		pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
+		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
 
 	/* wait for the PLL to lock */
 	err = tegra_pcie_pll_wait(pcie, 500);
@@ -943,6 +934,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 2,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+		.pads_refclk_cfg0 = 0xfa5cfa5c,
 		.has_pex_clkreq_en = false,
 		.has_pex_bias_ctrl = false,
 		.has_cml_clk = false,
@@ -952,6 +944,8 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 3,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+		.pads_refclk_cfg0 = 0xfa5cfa5c,
+		.pads_refclk_cfg1 = 0xfa5cfa5c,
 		.has_pex_clkreq_en = true,
 		.has_pex_bias_ctrl = true,
 		.has_cml_clk = true,
@@ -961,6 +955,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 2,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+		.pads_refclk_cfg0 = 0x44ac44ac,
 		.has_pex_clkreq_en = true,
 		.has_pex_bias_ctrl = true,
 		.has_cml_clk = true,
@@ -970,6 +965,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
 		.num_ports = 2,
 		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+		.pads_refclk_cfg0 = 0x90b890b8,
 		.has_pex_clkreq_en = true,
 		.has_pex_bias_ctrl = true,
 		.has_cml_clk = true,
-- 
cgit v0.10.2


From f39a6a327721285aa68f7e4d57b887c165ed3f14 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 24 Jun 2016 08:36:04 -0600
Subject: pci: tegra: actually program REFCLK_CFG* on recent SoCs

On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.

For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index 1aa56fc..352cdef 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -620,11 +620,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
 	value |= PADS_PLL_CTL_RST_B4SM;
 	pads_writel(pcie, value, soc->pads_pll_ctl);
 
-	/* configure the reference clock driver */
-	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
-	if (soc->num_ports > 2)
-		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
-
 	/* wait for the PLL to lock */
 	err = tegra_pcie_pll_wait(pcie, 500);
 	if (err < 0) {
@@ -818,20 +813,21 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
 
 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 {
-	const struct tegra_pcie_soc *soc = port->pcie->soc;
+	struct tegra_pcie *pcie = port->pcie;
+	const struct tegra_pcie_soc *soc = pcie->soc;
 	unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
 	unsigned long value;
 
 	/* enable reference clock */
-	value = afi_readl(port->pcie, ctrl);
+	value = afi_readl(pcie, ctrl);
 	value |= AFI_PEX_CTRL_REFCLK_EN;
 
-	if (port->pcie->soc->has_pex_clkreq_en)
+	if (pcie->soc->has_pex_clkreq_en)
 		value |= AFI_PEX_CTRL_CLKREQ_EN;
 
 	value |= AFI_PEX_CTRL_OVERRIDE_EN;
 
-	afi_writel(port->pcie, value, ctrl);
+	afi_writel(pcie, value, ctrl);
 
 	tegra_pcie_port_reset(port);
 
@@ -840,6 +836,11 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 		value |= RP_VEND_CTL2_PCA_ENABLE;
 		rp_writel(port, value, RP_VEND_CTL2);
 	}
+
+	/* configure the reference clock driver */
+	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
+	if (soc->num_ports > 2)
+		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
 }
 
 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
-- 
cgit v0.10.2


From 00e9e6d1ffb9786a7ca42cc41f5320303c1ab84f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 8 May 2016 16:55:17 -0600
Subject: errno: Add copyright header and header guard

Bring in a copyright for this file from cmd/pmic.c since this file was
submitted by the same author at around the same time. Also fix the missing
header guard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/include/errno.h b/include/errno.h
index 14ac3cb..3942681 100644
--- a/include/errno.h
+++ b/include/errno.h
@@ -1,4 +1,11 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
 #ifndef _ERRNO_H
+#define _ERRNO_H
 
 #include <asm-generic/errno.h>
 
-- 
cgit v0.10.2


From 862887d8836643e316cd019b93b1732971c8aaf8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 8 May 2016 16:55:18 -0600
Subject: errno: Allow errno_str() to be used without CONFIG_ERRNO_STR

The pmic framework uses errno_str() and this requires board that use it to
enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide
a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build
error.

This will show as "(null)" when U-Boot prints it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/include/errno.h b/include/errno.h
index 3942681..15ece2f 100644
--- a/include/errno.h
+++ b/include/errno.h
@@ -15,5 +15,10 @@ extern int errno;
 
 #ifdef CONFIG_ERRNO_STR
 const char *errno_str(int errno);
+#else
+static inline const char *errno_str(int errno)
+{
+	return 0;
+}
 #endif
 #endif /* _ERRNO_H */
-- 
cgit v0.10.2


From ce02a71c23749f2334ee84a3a88f5da30774edfa Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 8 May 2016 16:55:19 -0600
Subject: tegra: dts: Sync tegra20 device tree files with Linux

Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts
index 623eb90..a8540d4 100644
--- a/arch/arm/dts/tegra20-harmony.dts
+++ b/arch/arm/dts/tegra20-harmony.dts
@@ -1,5 +1,6 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
@@ -11,6 +12,9 @@
 	};
 
 	aliases {
+		rtc0 = "/i2c@7000d000/tps6586x@34";
+		rtc1 = "/rtc@7000e000";
+		serial0 = &uartd;
 		usb0 = "/usb@c5008000";
 		usb1 = "/usb@c5004000";
 		sdhci0 = "/sdhci@c8000600";
@@ -30,12 +34,276 @@
 				nvidia,panel = <&lcd_panel>;
 			};
 		};
+
+		hdmi@54280000 {
+			status = "okay";
+
+			hdmi-supply = <&vdd_5v0_hdmi>;
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+					"spia", "spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtd";
+				nvidia,function = "sdio2";
+			};
+			dtb {
+				nvidia,pins = "dtb", "dtc", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "cdev2", "dap1", "dtb", "gma",
+					"gmb", "gmc", "gmd", "gme", "gpu7",
+					"gpv", "i2cp", "pta", "rm", "slxa",
+					"slxk", "spia", "spib", "uac";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			};
+			conf_csus {
+				nvidia,pins = "csus", "spid", "spif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+					"dtc", "dte", "dtf", "gpu", "sdio1",
+					"slxc", "slxd", "spdi", "spdo", "spig",
+					"uda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dta", "dtd", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"sdc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "owc", "sdb";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "sdd", "spic",
+					"spie", "spih", "uaa", "uab", "uad",
+					"uca", "ucb";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc";
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+			};
+		};
+	};
+
+	i2s@70002800 {
+		status = "okay";
 	};
 
 	serial@70006300 {
+		status = "okay";
 		clock-frequency = < 216000000 >;
 	};
 
+	pwm: pwm@7000a000 {
+		status = "okay";
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+		};
+	};
+
 	nand-controller@70008000 {
 		nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
 		nvidia,width = <8>;
@@ -46,15 +314,319 @@
 		};
 	};
 
+	hdmi_ddc: i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				pci_clk_reg: ldo0 {
+					regulator-name = "vdd_ldo0,vddio_pex_clk";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "adi,adt7461";
+			reg = <0x4c>;
+		};
+	};
+
+	kbc@7000e200 {
+		status = "okay";
+		nvidia,debounce-delay-ms = <2>;
+		nvidia,repeat-delay-ms = <160>;
+		nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+		nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+				MATRIX_KEY(0x00, 0x03, KEY_S)
+				MATRIX_KEY(0x00, 0x04, KEY_A)
+				MATRIX_KEY(0x00, 0x05, KEY_Z)
+				MATRIX_KEY(0x00, 0x07, KEY_FN)
+				MATRIX_KEY(0x01, 0x07, KEY_MENU)
+				MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
+				MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
+				MATRIX_KEY(0x03, 0x00, KEY_5)
+				MATRIX_KEY(0x03, 0x01, KEY_4)
+				MATRIX_KEY(0x03, 0x02, KEY_R)
+				MATRIX_KEY(0x03, 0x03, KEY_E)
+				MATRIX_KEY(0x03, 0x04, KEY_F)
+				MATRIX_KEY(0x03, 0x05, KEY_D)
+				MATRIX_KEY(0x03, 0x06, KEY_X)
+				MATRIX_KEY(0x04, 0x00, KEY_7)
+				MATRIX_KEY(0x04, 0x01, KEY_6)
+				MATRIX_KEY(0x04, 0x02, KEY_T)
+				MATRIX_KEY(0x04, 0x03, KEY_H)
+				MATRIX_KEY(0x04, 0x04, KEY_G)
+				MATRIX_KEY(0x04, 0x05, KEY_V)
+				MATRIX_KEY(0x04, 0x06, KEY_C)
+				MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+				MATRIX_KEY(0x05, 0x00, KEY_9)
+				MATRIX_KEY(0x05, 0x01, KEY_8)
+				MATRIX_KEY(0x05, 0x02, KEY_U)
+				MATRIX_KEY(0x05, 0x03, KEY_Y)
+				MATRIX_KEY(0x05, 0x04, KEY_J)
+				MATRIX_KEY(0x05, 0x05, KEY_N)
+				MATRIX_KEY(0x05, 0x06, KEY_B)
+				MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+				MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+				MATRIX_KEY(0x06, 0x01, KEY_0)
+				MATRIX_KEY(0x06, 0x02, KEY_O)
+				MATRIX_KEY(0x06, 0x03, KEY_I)
+				MATRIX_KEY(0x06, 0x04, KEY_L)
+				MATRIX_KEY(0x06, 0x05, KEY_K)
+				MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+				MATRIX_KEY(0x06, 0x07, KEY_M)
+				MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+				MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+				MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+				MATRIX_KEY(0x07, 0x07, KEY_MENU)
+				MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
+				MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
+				MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
+				MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
+				MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+				MATRIX_KEY(0x0B, 0x01, KEY_P)
+				MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+				MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+				MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+				MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+				MATRIX_KEY(0x0C, 0x00, KEY_F10)
+				MATRIX_KEY(0x0C, 0x01, KEY_F9)
+				MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+				MATRIX_KEY(0x0C, 0x03, KEY_3)
+				MATRIX_KEY(0x0C, 0x04, KEY_2)
+				MATRIX_KEY(0x0C, 0x05, KEY_UP)
+				MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+				MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+				MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+				MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+				MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+				MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+				MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+				MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+				MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+				MATRIX_KEY(0x0E, 0x00, KEY_F11)
+				MATRIX_KEY(0x0E, 0x01, KEY_F12)
+				MATRIX_KEY(0x0E, 0x02, KEY_F8)
+				MATRIX_KEY(0x0E, 0x03, KEY_Q)
+				MATRIX_KEY(0x0E, 0x04, KEY_F4)
+				MATRIX_KEY(0x0E, 0x05, KEY_F3)
+				MATRIX_KEY(0x0E, 0x06, KEY_1)
+				MATRIX_KEY(0x0E, 0x07, KEY_F7)
+				MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+				MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+				MATRIX_KEY(0x0F, 0x02, KEY_F5)
+				MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+				MATRIX_KEY(0x0F, 0x04, KEY_F1)
+				MATRIX_KEY(0x0F, 0x05, KEY_F2)
+				MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+				MATRIX_KEY(0x0F, 0x07, KEY_F6)
+				MATRIX_KEY(0x14, 0x00, KEY_KP7)
+				MATRIX_KEY(0x15, 0x00, KEY_KP9)
+				MATRIX_KEY(0x15, 0x01, KEY_KP8)
+				MATRIX_KEY(0x15, 0x02, KEY_KP4)
+				MATRIX_KEY(0x15, 0x04, KEY_KP1)
+				MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+				MATRIX_KEY(0x16, 0x02, KEY_KP6)
+				MATRIX_KEY(0x16, 0x03, KEY_KP5)
+				MATRIX_KEY(0x16, 0x04, KEY_KP3)
+				MATRIX_KEY(0x16, 0x05, KEY_KP2)
+				MATRIX_KEY(0x16, 0x07, KEY_KP0)
+				MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+				MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+				MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+				MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+				MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+				MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+				MATRIX_KEY(0x1D, 0x04, KEY_END)
+				MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
+				MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+				MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
+				MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+				MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+				MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+				MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <3875>;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	pcie-controller@80003000 {
+		status = "okay";
+
+		avdd-pex-supply = <&pci_vdd_reg>;
+		vdd-pex-supply = <&pci_vdd_reg>;
+		avdd-pex-pll-supply = <&pci_vdd_reg>;
+		avdd-plle-supply = <&pci_vdd_reg>;
+		vddio-pex-clk-supply = <&pci_clk_reg>;
+
+		pci@1,0 {
+			status = "okay";
+		};
+
+		pci@2,0 {
+			status = "okay";
+		};
+	};
+
+	usb@c5000000 {
+		status = "okay";
+	};
+
+	usb-phy@c5000000 {
+		status = "okay";
+	};
+
 	usb@c5004000 {
-		statuc = "okay";
+		status = "okay";
 		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
 	};
 
+	usb-phy@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
+	};
+
 	usb@c5008000 {
 		status = "okay";
 	};
 
+	usb-phy@c5008000 {
+		status = "okay";
+	};
+
 	sdhci@c8000200 {
 		status = "okay";
 		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -71,6 +643,17 @@
 		bus-width = <8>;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+		power-supply = <&vdd_bl_reg>;
+		pwms = <&pwm 0 5000000>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
+
 	clocks {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -84,8 +667,15 @@
 		};
 	};
 
-	pwm: pwm@7000a000 {
-		status = "okay";
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			gpio-key,wakeup;
+		};
 	};
 
 	lcd_panel: panel {
@@ -112,4 +702,111 @@
 							GPIO_ACTIVE_HIGH>;
 		nvidia,panel-timings = <0 0 200 0 0>;
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		pci_vdd_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_1v05";
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_pnl_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_bl_reg: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_5v0_hdmi: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "VDDIO_HDMI";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_reg>;
+		};
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm8903-harmony",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "NVIDIA Tegra Harmony";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
+
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+	};
 };
diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index 5893d2a..6169094 100644
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -1,19 +1,12 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
 	model = "NVIDIA Seaboard";
 	compatible = "nvidia,seaboard", "nvidia,tegra20";
 
-	chosen {
-		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
-	};
-
-	chosen {
-		stdout-path = &uartd;
-	};
-
 	aliases {
 		/* This defines the order of our ports */
 		usb0 = "/usb@c5008000";
@@ -22,13 +15,23 @@
 		i2c1 = "/i2c@7000c000";
 		i2c2 = "/i2c@7000c400";
 		i2c3 = "/i2c@7000c500";
+		rtc0 = "/i2c@7000d000/tps6586x@34";
+		rtc1 = "/rtc@7000e000";
+		serial0 = &uartd;
 		sdhci0 = "/sdhci@c8000600";
 		sdhci1 = "/sdhci@c8000400";
 	};
 
+	chosen {
+		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+	};
+
+	chosen {
+		stdout-path = &uartd;
+	};
+
 	memory {
-		device_type = "memory";
-		reg = < 0x00000000 0x40000000 >;
+		reg = <0x00000000 0x40000000>;
 	};
 
 	host1x@50000000 {
@@ -37,31 +40,305 @@
 			status = "okay";
 			rgb {
 				status = "okay";
-				nvidia,panel = <&lcd_panel>;
+
+				nvidia,panel = <&panel>;
 			};
 		};
+
+		hdmi@54280000 {
+			status = "okay";
+
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+			hdmi-supply = <&vdd_hdmi>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
+		};
 	};
 
-	/* This is not used in U-Boot, but is expected to be in kernel .dts */
-	i2c@7000d000 {
-		status = "okay";
-		clock-frequency = <100000>;
-		pmic@34 {
-			compatible = "ti,tps6586x";
-			reg = <0x34>;
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "spia",
+					"spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp", "lm1";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gmd {
+				nvidia,pins = "gmd";
+				nvidia,function = "sflash";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "pwm";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
+					"lsck", "lsda";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uartb";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+					"lsdi", "lvp0";
+				nvidia,function = "rsvd4";
+			};
+			ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
+					"lspi", "lvp1", "lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "sdio3";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd",
+					"cdev1", "cdev2", "dap1", "dap2",
+					"dap4", "ddc", "dtf", "gma", "gmc", "gmd",
+					"gme", "gpu", "gpu7", "i2cp", "irrx",
+					"irtx", "pta", "rm", "sdc", "sdd",
+					"slxd", "slxk", "spdi", "spdo", "uac",
+					"uad", "uca", "ucb", "uda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ate {
+				nvidia,pins = "ate", "csus", "dap3",
+					"gpv", "owc", "slxc", "spib", "spid",
+					"spie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "gmb", "slxa", "spia",
+					"spig", "spih";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_dte {
+				nvidia,pins = "dte", "spif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf", "sdio1", "spic", "uaa",
+					"uab";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc", "sdb";
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+			};
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+			};
+		};
+
+		state_i2cmux_ddc: pinmux_i2cmux_ddc {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
 
-			clk_32k: clock {
-				compatible = "fixed-clock";
-				/*
-				 * leave out for now due to CPP:
-				 * #clock-cells = <0>;
-				 */
-				clock-frequency = <32768>;
+		state_i2cmux_pta: pinmux_i2cmux_pta {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "i2c2";
+			};
+		};
+
+		state_i2cmux_idle: pinmux_i2cmux_idle {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
 			};
 		};
 	};
 
+	i2s@70002800 {
+		status = "okay";
+	};
+
 	serial@70006300 {
+		status = "okay";
 		clock-frequency = < 216000000 >;
 	};
 
@@ -75,56 +352,376 @@
 		};
 	};
 
+	pwm: pwm@7000a000 {
+		status = "okay";
+	};
+
 	i2c@7000c000 {
 		status = "okay";
-		clock-frequency = <100000>;
+		clock-frequency = <400000>;
+
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+		};
+
+		/* ALS and proximity sensor */
+		isl29018@44 {
+			compatible = "isil,isl29018";
+			reg = <0x44>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		gyrometer@68 {
+			compatible = "invn,mpu3050";
+			reg = <0x68>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};
 
 	i2c@7000c400 {
 		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c-parent = <&{/i2c@7000c400}>;
+
+		pinctrl-names = "ddc", "pta", "idle";
+		pinctrl-0 = <&state_i2cmux_ddc>;
+		pinctrl-1 = <&state_i2cmux_pta>;
+		pinctrl-2 = <&state_i2cmux_idle>;
+
+		hdmi_ddc: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		lvds_ddc: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smart-battery@b {
+				compatible = "ti,bq20z75", "smart-battery-1.1";
+				reg = <0xb>;
+				ti,i2c-retry-count = <2>;
+				ti,poll-retry-count = <10>;
+			};
+		};
 	};
 
 	i2c@7000c500 {
 		status = "okay";
-		clock-frequency = <100000>;
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		magnetometer@c {
+			compatible = "asahi-kasei,ak8975";
+			reg = <0xc>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1300000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1125000>;
+					regulator-max-microvolt = <1125000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "onnn,nct1008";
+			reg = <0x4c>;
+		};
 	};
 
 	kbc@7000e200 {
 		status = "okay";
-		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
-			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
-			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
-			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
-			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
-			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
-			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
-			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
-			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
-			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
-			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
-			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
-			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
-			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
-			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
-			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
-			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
-			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
-			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
-			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
-			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
-			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
-			0x1f04008a>;
-		linux,fn-keymap = <0x05040002>;
-	};
-
-	emc@7000f400 {
-		#address-cells = <1>;
-		#size-cells = <0>;
+		nvidia,debounce-delay-ms = <32>;
+		nvidia,repeat-delay-ms = <160>;
+		nvidia,ghost-filter;
+		nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+		nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
+				MATRIX_KEY(0x00, 0x03, KEY_S)
+				MATRIX_KEY(0x00, 0x04, KEY_A)
+				MATRIX_KEY(0x00, 0x05, KEY_Z)
+				MATRIX_KEY(0x00, 0x07, KEY_FN)
+
+				MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
+				MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
+				MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
+
+				MATRIX_KEY(0x03, 0x00, KEY_5)
+				MATRIX_KEY(0x03, 0x01, KEY_4)
+				MATRIX_KEY(0x03, 0x02, KEY_R)
+				MATRIX_KEY(0x03, 0x03, KEY_E)
+				MATRIX_KEY(0x03, 0x04, KEY_F)
+				MATRIX_KEY(0x03, 0x05, KEY_D)
+				MATRIX_KEY(0x03, 0x06, KEY_X)
+
+				MATRIX_KEY(0x04, 0x00, KEY_7)
+				MATRIX_KEY(0x04, 0x01, KEY_6)
+				MATRIX_KEY(0x04, 0x02, KEY_T)
+				MATRIX_KEY(0x04, 0x03, KEY_H)
+				MATRIX_KEY(0x04, 0x04, KEY_G)
+				MATRIX_KEY(0x04, 0x05, KEY_V)
+				MATRIX_KEY(0x04, 0x06, KEY_C)
+				MATRIX_KEY(0x04, 0x07, KEY_SPACE)
+
+				MATRIX_KEY(0x05, 0x00, KEY_9)
+				MATRIX_KEY(0x05, 0x01, KEY_8)
+				MATRIX_KEY(0x05, 0x02, KEY_U)
+				MATRIX_KEY(0x05, 0x03, KEY_Y)
+				MATRIX_KEY(0x05, 0x04, KEY_J)
+				MATRIX_KEY(0x05, 0x05, KEY_N)
+				MATRIX_KEY(0x05, 0x06, KEY_B)
+				MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
+
+				MATRIX_KEY(0x06, 0x00, KEY_MINUS)
+				MATRIX_KEY(0x06, 0x01, KEY_0)
+				MATRIX_KEY(0x06, 0x02, KEY_O)
+				MATRIX_KEY(0x06, 0x03, KEY_I)
+				MATRIX_KEY(0x06, 0x04, KEY_L)
+				MATRIX_KEY(0x06, 0x05, KEY_K)
+				MATRIX_KEY(0x06, 0x06, KEY_COMMA)
+				MATRIX_KEY(0x06, 0x07, KEY_M)
+
+				MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
+				MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
+				MATRIX_KEY(0x07, 0x03, KEY_ENTER)
+				MATRIX_KEY(0x07, 0x07, KEY_MENU)
+
+				MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
+				MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
+
+				MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
+				MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
+
+				MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
+				MATRIX_KEY(0x0B, 0x01, KEY_P)
+				MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
+				MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
+				MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
+				MATRIX_KEY(0x0B, 0x05, KEY_DOT)
+
+				MATRIX_KEY(0x0C, 0x00, KEY_F10)
+				MATRIX_KEY(0x0C, 0x01, KEY_F9)
+				MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
+				MATRIX_KEY(0x0C, 0x03, KEY_3)
+				MATRIX_KEY(0x0C, 0x04, KEY_2)
+				MATRIX_KEY(0x0C, 0x05, KEY_UP)
+				MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
+				MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
+
+				MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
+				MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
+				MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
+				MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
+				MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
+				MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
+				MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
+
+				MATRIX_KEY(0x0E, 0x00, KEY_F11)
+				MATRIX_KEY(0x0E, 0x01, KEY_F12)
+				MATRIX_KEY(0x0E, 0x02, KEY_F8)
+				MATRIX_KEY(0x0E, 0x03, KEY_Q)
+				MATRIX_KEY(0x0E, 0x04, KEY_F4)
+				MATRIX_KEY(0x0E, 0x05, KEY_F3)
+				MATRIX_KEY(0x0E, 0x06, KEY_1)
+				MATRIX_KEY(0x0E, 0x07, KEY_F7)
+
+				MATRIX_KEY(0x0F, 0x00, KEY_ESC)
+				MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
+				MATRIX_KEY(0x0F, 0x02, KEY_F5)
+				MATRIX_KEY(0x0F, 0x03, KEY_TAB)
+				MATRIX_KEY(0x0F, 0x04, KEY_F1)
+				MATRIX_KEY(0x0F, 0x05, KEY_F2)
+				MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
+				MATRIX_KEY(0x0F, 0x07, KEY_F6)
+
+				/* Software Handled Function Keys */
+				MATRIX_KEY(0x14, 0x00, KEY_KP7)
+
+				MATRIX_KEY(0x15, 0x00, KEY_KP9)
+				MATRIX_KEY(0x15, 0x01, KEY_KP8)
+				MATRIX_KEY(0x15, 0x02, KEY_KP4)
+				MATRIX_KEY(0x15, 0x04, KEY_KP1)
+
+				MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
+				MATRIX_KEY(0x16, 0x02, KEY_KP6)
+				MATRIX_KEY(0x16, 0x03, KEY_KP5)
+				MATRIX_KEY(0x16, 0x04, KEY_KP3)
+				MATRIX_KEY(0x16, 0x05, KEY_KP2)
+				MATRIX_KEY(0x16, 0x07, KEY_KP0)
+
+				MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
+				MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
+				MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
+				MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
+
+				MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
+
+				MATRIX_KEY(0x1D, 0x03, KEY_HOME)
+				MATRIX_KEY(0x1D, 0x04, KEY_END)
+				MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
+				MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
+				MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
+
+				MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
+				MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
+				MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
+
+				MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <5000>;
+		nvidia,cpu-pwr-off-time = <5000>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <3875>;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	memory-controller@7000f400 {
 		emc-table@190000 {
-			reg = < 190000 >;
+			reg = <190000>;
 			compatible = "nvidia,tegra20-emc-table";
-			clock-frequency = < 190000 >;
-			nvidia,emc-registers = < 0x0000000c 0x00000026
+			clock-frequency = <190000>;
+			nvidia,emc-registers = <0x0000000c 0x00000026
 				0x00000009 0x00000003 0x00000004 0x00000004
 				0x00000002 0x0000000c 0x00000003 0x00000003
 				0x00000002 0x00000001 0x00000004 0x00000005
@@ -135,13 +732,14 @@
 				0x00000002 0x00000000 0x00000000 0x00000002
 				0x00000000 0x00000000 0x00000083 0xa06204ae
 				0x007dc010 0x00000000 0x00000000 0x00000000
-				0x00000000 0x00000000 0x00000000 0x00000000 >;
+				0x00000000 0x00000000 0x00000000 0x00000000>;
 		};
+
 		emc-table@380000 {
-			reg = < 380000 >;
+			reg = <380000>;
 			compatible = "nvidia,tegra20-emc-table";
-			clock-frequency = < 380000 >;
-			nvidia,emc-registers = < 0x00000017 0x0000004b
+			clock-frequency = <380000>;
+			nvidia,emc-registers = <0x00000017 0x0000004b
 				0x00000012 0x00000006 0x00000004 0x00000005
 				0x00000003 0x0000000c 0x00000006 0x00000006
 				0x00000003 0x00000001 0x00000004 0x00000005
@@ -152,7 +750,7 @@
 				0x00000002 0x00000000 0x00000000 0x00000002
 				0x00000000 0x00000000 0x00000083 0xe044048b
 				0x007d8010 0x00000000 0x00000000 0x00000000
-				0x00000000 0x00000000 0x00000000 0x00000000 >;
+				0x00000000 0x00000000 0x00000000 0x00000000>;
 		};
 	};
 
@@ -162,14 +760,39 @@
 		dr_mode = "otg";
 	};
 
+	usb-phy@c5000000 {
+		status = "okay";
+		vbus-supply = <&vbus_reg>;
+		dr_mode = "otg";
+	};
+
 	usb@c5004000 {
 		status = "disabled";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
+	};
+
+	usb-phy@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb@c5008000 {
 		status = "okay";
 	};
 
+	usb-phy@c5008000 {
+		status = "okay";
+	};
+
+	sdhci@c8000000 {
+		status = "okay";
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+		keep-power-in-suspend;
+	};
+
 	sdhci@c8000400 {
 		status = "okay";
 		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -181,6 +804,18 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+		power-supply = <&vdd_bl_reg>;
+		pwms = <&pwm 2 5000000>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
 	};
 
 	clocks {
@@ -196,11 +831,27 @@
 		};
 	};
 
-	pwm: pwm@7000a000 {
-		status = "okay";
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			gpio-key,wakeup;
+		};
+
+		lid {
+			label = "Lid";
+			gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
+			linux,input-type = <5>; /* EV_SW */
+			linux,code = <0>; /* SW_LID */
+			debounce-interval = <1>;
+			gpio-key,wakeup;
+		};
 	};
 
-	lcd_panel: panel {
+	panel: panel {
 		/* Seaboard has 1366x768 */
 		clock = <70600000>;
 		xres = <1366>;
@@ -224,4 +875,108 @@
 							GPIO_ACTIVE_HIGH>;
 		nvidia,panel-timings = <400 4 203 17 15>;
 	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vbus_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_vbus_wup1";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vdd_pnl_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_bl_reg: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_hdmi: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "VDDIO_HDMI";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&vdd_5v0_reg>;
+		};
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm8903-seaboard",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "NVIDIA Tegra Seaboard";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1R", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+	};
 };
diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts
index 851e0ed..0ce46ae 100644
--- a/arch/arm/dts/tegra20-ventana.dts
+++ b/arch/arm/dts/tegra20-ventana.dts
@@ -1,5 +1,6 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
@@ -11,6 +12,9 @@
 	};
 
 	aliases {
+		rtc0 = "/i2c@7000d000/tps6586x@34";
+		rtc1 = "/rtc@7000e000";
+		serial0 = &uartd;
 		usb0 = "/usb@c5008000";
 		sdhci0 = "/sdhci@c8000600";
 		sdhci1 = "/sdhci@c8000400";
@@ -29,16 +33,537 @@
 				nvidia,panel = <&lcd_panel>;
 			};
 		};
+
+		hdmi@54280000 {
+			status = "okay";
+
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+				GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "spia",
+					"spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp", "lm1";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gmd {
+				nvidia,pins = "gmd";
+				nvidia,function = "sflash";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "pwm";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uartb";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+					"lsdi", "lvp0";
+				nvidia,function = "rsvd4";
+			};
+			ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
+					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
+					"lspi", "lvp1", "lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
+				nvidia,function = "sdio3";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxd {
+				nvidia,pins = "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd",
+					"cdev1", "cdev2", "dap1", "dap2",
+					"dap4", "ddc", "dtf", "gma", "gmc",
+					"gme", "gpu", "gpu7", "i2cp", "irrx",
+					"irtx", "pta", "rm", "sdc", "sdd",
+					"slxc", "slxd", "slxk", "spdi", "spdo",
+					"uac", "uad", "uca", "ucb", "uda";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ate {
+				nvidia,pins = "ate", "csus", "dap3", "gmd",
+					"gpv", "owc", "spia", "spib", "spic",
+					"spid", "spie", "spig";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "gmb", "slxa", "spih";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_dte {
+				nvidia,pins = "dte", "spif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+			conf_kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf", "sdio1", "uaa", "uab";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+					"lvp1", "lvs", "pmc", "sdb";
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+			};
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+			};
+		};
+
+		state_i2cmux_ddc: pinmux_i2cmux_ddc {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+
+		state_i2cmux_pta: pinmux_i2cmux_pta {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "i2c2";
+			};
+		};
+
+		state_i2cmux_idle: pinmux_i2cmux_idle {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+	};
+
+	i2s@70002800 {
+		status = "okay";
 	};
 
 	serial@70006300 {
-		clock-frequency = < 216000000 >;
+		status = "okay";
+		clock-frequency = < 216000000 >;	};
+
+	pwm: pwm@7000a000 {
+		status = "okay";
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		wm8903: wm8903@1a {
+			compatible = "wlf,wm8903";
+			reg = <0x1a>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			micdet-cfg = <0>;
+			micdet-delay = <100>;
+			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+		};
+
+		/* ALS and proximity sensor */
+		isl29018@44 {
+			compatible = "isil,isl29018";
+			reg = <0x44>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c-parent = <&{/i2c@7000c400}>;
+
+		pinctrl-names = "ddc", "pta", "idle";
+		pinctrl-0 = <&state_i2cmux_ddc>;
+		pinctrl-1 = <&state_i2cmux_pta>;
+		pinctrl-2 = <&state_i2cmux_idle>;
+
+		hdmi_ddc: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		lvds_ddc: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "onnn,nct1008";
+			reg = <0x4c>;
+		};
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <100>;
+		nvidia,core-pwr-good-time = <3845 3845>;
+		nvidia,core-pwr-off-time = <458>;
+		nvidia,sys-clock-req-active-high;
+	};
+
+	usb@c5000000 {
+		status = "okay";
+	};
+
+	usb-phy@c5000000 {
+		status = "okay";
+	};
+
+	usb@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
+	};
+
+	usb-phy@c5004000 {
+		status = "okay";
+		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+			GPIO_ACTIVE_LOW>;
 	};
 
 	usb@c5008000 {
 		status = "okay";
 	};
 
+	usb-phy@c5008000 {
+		status = "okay";
+	};
+
+	sdhci@c8000000 {
+		status = "okay";
+		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+		keep-power-in-suspend;
+	};
+
 	sdhci@c8000400 {
 		status = "okay";
 		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -50,6 +575,18 @@
 	sdhci@c8000600 {
 		status = "okay";
 		bus-width = <8>;
+		non-removable;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+
+		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+		power-supply = <&vdd_bl_reg>;
+		pwms = <&pwm 2 5000000>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
 	};
 
 	clocks {
@@ -65,8 +602,69 @@
 		};
 	};
 
-	pwm: pwm@7000a000 {
-		status = "okay";
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			gpio-key,wakeup;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_pnl_reg: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		vdd_bl_reg: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
 	};
 
 	lcd_panel: panel {
@@ -93,4 +691,35 @@
 							GPIO_ACTIVE_HIGH>;
 		nvidia,panel-timings = <0 0 200 0 0>;
 	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm8903-ventana",
+			     "nvidia,tegra-audio-wm8903";
+		nvidia,model = "NVIDIA Tegra Ventana";
+
+		nvidia,audio-routing =
+			"Headphone Jack", "HPOUTR",
+			"Headphone Jack", "HPOUTL",
+			"Int Spk", "ROP",
+			"Int Spk", "RON",
+			"Int Spk", "LOP",
+			"Int Spk", "LON",
+			"Mic Jack", "MICBIAS",
+			"IN1L", "Mic Jack";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8903>;
+
+		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+			GPIO_ACTIVE_HIGH>;
+		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+			GPIO_ACTIVE_HIGH>;
+
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+	};
 };
-- 
cgit v0.10.2


From ec5507707a1d1e84056a6c864338f95f6118d3ca Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 8 May 2016 16:55:20 -0600
Subject: video: tegra: Move to using simple-panel and pwm-backlight

We have standard drivers for panels and backlights which can do most of the
work for us. Move the tegra20 LCD driver over to use those instead of custom
code.

This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use display-timings:

   - colibri
   - medcom-wide
   - paz00
   - tec

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts
index a8540d4..8e9fe5a 100644
--- a/arch/arm/dts/tegra20-harmony.dts
+++ b/arch/arm/dts/tegra20-harmony.dts
@@ -31,7 +31,23 @@
 			status = "okay";
 			rgb {
 				status = "okay";
-				nvidia,panel = <&lcd_panel>;
+
+				nvidia,panel = <&panel>;
+
+				display-timings {
+					timing@0 {
+						/* Seaboard has 1366x768 */
+						clock-frequency = <42430000>;
+						hactive = <1024>;
+						vactive = <600>;
+						hback-porch = <138>;
+						hfront-porch = <34>;
+						hsync-len = <136>;
+						vback-porch = <21>;
+						vfront-porch = <4>;
+						vsync-len = <4>;
+					};
+				};
 			};
 		};
 
@@ -678,29 +694,13 @@
 		};
 	};
 
-	lcd_panel: panel {
-		clock = <42430000>;
-		xres = <1024>;
-		yres = <600>;
-		left-margin = <138>;
-		right-margin = <34>;
-		hsync-len = <136>;
-		lower-margin = <4>;
-		upper-margin = <21>;
-		vsync-len = <4>;
-		hsync-active-high;
-		vsyncx-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 0 0>;
-		nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-timings = <0 0 200 0 0>;
+	panel: panel {
+		compatible = "auo,b101aw03", "simple-panel";
+
+		power-supply = <&vdd_pnl_reg>;
+		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+		backlight = <&backlight>;
 	};
 
 	regulators {
diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index 6169094..0a454f9 100644
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -42,6 +42,22 @@
 				status = "okay";
 
 				nvidia,panel = <&panel>;
+
+				display-timings {
+					timing@0 {
+						/* Seaboard has 1366x768 */
+						clock-frequency = <70600000>;
+						hactive = <1366>;
+						vactive = <768>;
+						hback-porch = <58>;
+						hfront-porch = <58>;
+						hsync-len = <58>;
+						vback-porch = <4>;
+						vfront-porch = <4>;
+						vsync-len = <4>;
+						hsync-active = <1>;
+					};
+				};
 			};
 		};
 
@@ -852,28 +868,13 @@
 	};
 
 	panel: panel {
-		/* Seaboard has 1366x768 */
-		clock = <70600000>;
-		xres = <1366>;
-		yres = <768>;
-		left-margin = <58>;
-		right-margin = <58>;
-		hsync-len = <58>;
-		lower-margin = <4>;
-		upper-margin = <4>;
-		vsync-len = <4>;
-		hsync-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 2 0>;
-		nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-timings = <400 4 203 17 15>;
+		compatible = "chunghwa,claa101wa01a", "simple-panel";
+
+		power-supply = <&vdd_pnl_reg>;
+		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+		backlight = <&backlight>;
+		ddc-i2c-bus = <&lvds_ddc>;
 	};
 
 	regulators {
diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts
index 0ce46ae..143e964 100644
--- a/arch/arm/dts/tegra20-ventana.dts
+++ b/arch/arm/dts/tegra20-ventana.dts
@@ -30,7 +30,24 @@
 			status = "okay";
 			rgb {
 				status = "okay";
-				nvidia,panel = <&lcd_panel>;
+
+				nvidia,panel = <&panel>;
+
+				display-timings {
+					timing@0 {
+						/* Seaboard has 1366x768 */
+						clock-frequency = <70600000>;
+						hactive = <1366>;
+						vactive = <768>;
+						hback-porch = <58>;
+						hfront-porch = <58>;
+						hsync-len = <58>;
+						vback-porch = <4>;
+						vfront-porch = <4>;
+						vsync-len = <4>;
+						hsync-active = <1>;
+					};
+				};
 			};
 		};
 
@@ -613,6 +630,16 @@
 		};
 	};
 
+	panel: panel {
+		compatible = "chunghwa,claa101wa01a", "simple-panel";
+
+		power-supply = <&vdd_pnl_reg>;
+		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+		backlight = <&backlight>;
+		ddc-i2c-bus = <&lvds_ddc>;
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -667,31 +694,6 @@
 		};
 	};
 
-	lcd_panel: panel {
-		clock = <72072000>;
-		xres = <1366>;
-		yres = <768>;
-		left-margin = <58>;
-		right-margin = <58>;
-		hsync-len = <58>;
-		lower-margin = <4>;
-		upper-margin = <4>;
-		vsync-len = <4>;
-		hsync-active-high;
-		vsync-active-high;
-		nvidia,bits-per-pixel = <16>;
-		nvidia,pwm = <&pwm 2 0>;
-		nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
-							GPIO_ACTIVE_HIGH>;
-		nvidia,panel-timings = <0 0 200 0 0>;
-	};
-
 	sound {
 		compatible = "nvidia,tegra-audio-wm8903-ventana",
 			     "nvidia,tegra-audio-wm8903";
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index a3b2a3c..5907a33 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -23,6 +23,8 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -30,6 +32,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 129a72b..e0b9559 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 02eb704..14cb53a 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 0fe43b1..000bbfb 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 3f8648d..3c5c413 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 2055101..dc7169b 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 97b13a1..07a4afe 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index c01809e..5c48c3b 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <fdtdec.h>
+#include <panel.h>
 #include <pwm.h>
 #include <video.h>
 #include <asm/system.h>
@@ -21,28 +22,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* These are the stages we go throuh in enabling the LCD */
-enum stage_t {
-	STAGE_START,
-	STAGE_PANEL_VDD,
-	STAGE_LVDS,
-	STAGE_BACKLIGHT_VDD,
-	STAGE_PWM,
-	STAGE_BACKLIGHT_EN,
-	STAGE_DONE,
-};
-
-#define FDT_LCD_TIMINGS	4
-
-enum {
-	FDT_LCD_TIMING_REF_TO_SYNC,
-	FDT_LCD_TIMING_SYNC_WIDTH,
-	FDT_LCD_TIMING_BACK_PORCH,
-	FDT_LCD_TIMING_FRONT_PORCH,
-
-	FDT_LCD_TIMING_COUNT,
-};
-
 enum lcd_cache_t {
 	FDT_LCD_CACHE_OFF		= 0,
 	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
@@ -54,37 +33,15 @@ enum lcd_cache_t {
 
 /* Information about the display controller */
 struct tegra_lcd_priv {
-	enum stage_t stage;	/* Current stage we are at */
-	unsigned long timer_next; /* Time we can move onto next stage */
 	int width;			/* width in pixels */
 	int height;			/* height in pixels */
-
-	/*
-	 * log2 of number of bpp, in general, unless it bpp is 24 in which
-	 * case this field holds 24 also! This is a U-Boot thing.
-	 */
-	int log2_bpp;
+	enum video_log2_bpp log2_bpp;	/* colour depth */
+	struct display_timing timing;
+	struct udevice *panel;
 	struct disp_ctlr *disp;		/* Display controller to use */
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
 	unsigned pixel_clock;		/* Pixel clock in Hz */
-	uint horiz_timing[FDT_LCD_TIMING_COUNT];	/* Horizontal timing */
-	uint vert_timing[FDT_LCD_TIMING_COUNT];		/* Vertical timing */
-	struct udevice *pwm;
-	int pwm_channel;		/* PWM channel to use for backlight */
 	enum lcd_cache_t cache_type;
-
-	struct gpio_desc backlight_en;	/* GPIO for backlight enable */
-	struct gpio_desc lvds_shutdown;	/* GPIO for lvds shutdown */
-	struct gpio_desc backlight_vdd;	/* GPIO for backlight vdd */
-	struct gpio_desc panel_vdd;	/* GPIO for panel vdd */
-	/*
-	 * Panel required timings
-	 * Timing 1: delay between panel_vdd-rise and data-rise
-	 * Timing 2: delay between data-rise and backlight_vdd-rise
-	 * Timing 3: delay between backlight_vdd and pwm-rise
-	 * Timing 4: delay between pwm-rise and backlight_en-rise
-	 */
-	uint panel_timings[FDT_LCD_TIMINGS];
 };
 
 enum {
@@ -150,26 +107,23 @@ static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
 	writel(val, &dc->cmd.state_ctrl);
 }
 
-static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg)
-{
-	writel(priv->horiz_timing[item] |
-			(priv->vert_timing[item] << 16), reg);
-}
-
 static int update_display_mode(struct dc_disp_reg *disp,
 			       struct tegra_lcd_priv *priv)
 {
+	struct display_timing *dt = &priv->timing;
 	unsigned long val;
 	unsigned long rate;
 	unsigned long div;
 
 	writel(0x0, &disp->disp_timing_opt);
-	write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
-	write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
-	write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
-	write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
 
-	writel(priv->width | (priv->height << 16), &disp->disp_active);
+	writel(1 | 1 << 16, &disp->ref_to_sync);
+	writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
+	writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
+	       &disp->back_porch);
+	writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
+	       &disp->front_porch);
+	writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
 
 	val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
 	val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
@@ -287,12 +241,11 @@ static int setup_window(struct disp_ctl_win *win,
 	win->stride = priv->width * (1 << priv->log2_bpp) / 8;
 	debug("%s: depth = %d\n", __func__, priv->log2_bpp);
 	switch (priv->log2_bpp) {
-	case 5:
-	case 24:
+	case VIDEO_BPP32:
 		win->fmt = COLOR_DEPTH_R8G8B8A8;
 		win->bpp = 32;
 		break;
-	case 4:
+	case VIDEO_BPP16:
 		win->fmt = COLOR_DEPTH_B5G6R5;
 		win->bpp = 16;
 		break;
@@ -305,18 +258,6 @@ static int setup_window(struct disp_ctl_win *win,
 	return 0;
 }
 
-static void debug_timing(const char *name, unsigned int timing[])
-{
-#ifdef DEBUG
-	int i;
-
-	debug("%s timing: ", name);
-	for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
-		debug("%d ", timing[i]);
-	debug("\n");
-#endif
-}
-
 /**
  * Register a new display based on device tree configuration.
  *
@@ -363,112 +304,6 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
 	return 0;
 }
 
-/**
- * Handle the next stage of device init
- */
-static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
-{
-	debug("%s: stage %d\n", __func__, priv->stage);
-
-	/* do the things for this stage */
-	switch (priv->stage) {
-	case STAGE_START:
-		/*
-		 * It is possible that the FDT has requested that the LCD be
-		 * disabled. We currently don't support this. It would require
-		 * changes to U-Boot LCD subsystem to have LCD support
-		 * compiled in but not used. An easier option might be to
-		 * still have a frame buffer, but leave the backlight off and
-		 * remove all mention of lcd in the stdout environment
-		 * variable.
-		 */
-
-		funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
-		break;
-	case STAGE_PANEL_VDD:
-		if (dm_gpio_is_valid(&priv->panel_vdd))
-			dm_gpio_set_value(&priv->panel_vdd, 1);
-		break;
-	case STAGE_LVDS:
-		if (dm_gpio_is_valid(&priv->lvds_shutdown))
-			dm_gpio_set_value(&priv->lvds_shutdown, 1);
-		break;
-	case STAGE_BACKLIGHT_VDD:
-		if (dm_gpio_is_valid(&priv->backlight_vdd))
-			dm_gpio_set_value(&priv->backlight_vdd, 1);
-		break;
-	case STAGE_PWM:
-		/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
-		pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
-		pinmux_tristate_disable(PMUX_PINGRP_GPU);
-
-		pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff);
-		pwm_set_enable(priv->pwm, priv->pwm_channel, true);
-		break;
-	case STAGE_BACKLIGHT_EN:
-		if (dm_gpio_is_valid(&priv->backlight_en))
-			dm_gpio_set_value(&priv->backlight_en, 1);
-		break;
-	case STAGE_DONE:
-		break;
-	}
-
-	/* set up timer for next stage */
-	priv->timer_next = timer_get_us();
-	if (priv->stage < FDT_LCD_TIMINGS)
-		priv->timer_next += priv->panel_timings[priv->stage] * 1000;
-
-	/* move to next stage */
-	priv->stage++;
-	return 0;
-}
-
-/**
- * Perform the next stage of the LCD init if it is time to do so.
- *
- * LCD init can be time-consuming because of the number of delays we need
- * while waiting for the backlight power supply, etc. This function can
- * be called at various times during U-Boot operation to advance the
- * initialization of the LCD to the next stage if sufficient time has
- * passed since the last stage. It keeps track of what stage it is up to
- * and the time that it is permitted to move to the next stage.
- *
- * The final call should have wait=1 to complete the init.
- *
- * @param blob	fdt blob containing LCD information
- * @param wait	1 to wait until all init is complete, and then return
- *		0 to return immediately, potentially doing nothing if it is
- *		not yet time for the next init.
- */
-static int tegra_lcd_check_next_stage(const void *blob,
-				      struct tegra_lcd_priv *priv, int wait)
-{
-	if (priv->stage == STAGE_DONE)
-		return 0;
-
-	do {
-		/* wait if we need to */
-		debug("%s: stage %d\n", __func__, priv->stage);
-		if (priv->stage != STAGE_START) {
-			int delay = priv->timer_next - timer_get_us();
-
-			if (delay > 0) {
-				if (wait)
-					udelay(delay);
-				else
-					return 0;
-			}
-		}
-
-		if (handle_stage(blob, priv))
-			return -1;
-	} while (wait && priv->stage != STAGE_DONE);
-	if (priv->stage == STAGE_DONE)
-		debug("%s: LCD init complete\n", __func__);
-
-	return 0;
-}
-
 static int tegra_lcd_probe(struct udevice *dev)
 {
 	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
@@ -476,14 +311,23 @@ static int tegra_lcd_probe(struct udevice *dev)
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
 	const void *blob = gd->fdt_blob;
 	int type = DCACHE_OFF;
+	int ret;
 
 	/* Initialize the Tegra display controller */
+	funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
 	if (tegra_display_probe(blob, priv, (void *)plat->base)) {
 		printf("%s: Failed to probe display driver\n", __func__);
 		return -1;
 	}
 
-	tegra_lcd_check_next_stage(blob, priv, 1);
+	pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PMUX_PINGRP_GPU);
+
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
+		return ret;
+	}
 
 	/* Set up the LCD caching as requested */
 	if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
@@ -507,13 +351,11 @@ static int tegra_lcd_probe(struct udevice *dev)
 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 {
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
-	struct fdtdec_phandle_args args;
 	const void *blob = gd->fdt_blob;
+	struct display_timing *timing;
 	int node = dev->of_offset;
-	int front, back, ref;
 	int panel_node;
 	int rgb;
-	int bpp, bit;
 	int ret;
 
 	priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
@@ -523,96 +365,40 @@ static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	rgb = fdt_subnode_offset(blob, node, "rgb");
-
-	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
-	if (panel_node < 0) {
-		debug("%s: Cannot find panel information\n", __func__);
+	if (rgb < 0) {
+		debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
+		      __func__, dev->name, rgb);
 		return -EINVAL;
 	}
 
-	priv->width = fdtdec_get_int(blob, panel_node, "xres", -1);
-	priv->height = fdtdec_get_int(blob, panel_node, "yres", -1);
-	priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0);
-	if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) {
-		debug("%s: Pixel parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	back = fdtdec_get_int(blob, panel_node, "left-margin", -1);
-	front = fdtdec_get_int(blob, panel_node, "right-margin", -1);
-	ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1);
-	if ((back | front | ref) == -1) {
-		debug("%s: Horizontal parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	/* Use a ref-to-sync of 1 always, and take this from the front porch */
-	priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
-	priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
-	priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
-	priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
-		priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
-	debug_timing("horiz", priv->horiz_timing);
-
-	back = fdtdec_get_int(blob, panel_node, "upper-margin", -1);
-	front = fdtdec_get_int(blob, panel_node, "lower-margin", -1);
-	ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1);
-	if ((back | front | ref) == -1) {
-		debug("%s: Vertical parameters missing\n", __func__);
-		return -EINVAL;
-	}
-
-	priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
-	priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
-	priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
-	priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
-		priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
-	debug_timing("vert", priv->vert_timing);
-
-	bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1);
-	bit = ffs(bpp) - 1;
-	if (bpp == (1 << bit))
-		priv->log2_bpp = bit;
-	else
-		priv->log2_bpp = bpp;
-	if (bpp == -1) {
-		debug("%s: Pixel bpp parameters missing\n", __func__);
+	ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+	if (ret) {
+		debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+		      __func__, dev->name, ret);
 		return -EINVAL;
 	}
+	timing = &priv->timing;
+	priv->width = timing->hactive.typ;
+	priv->height = timing->vactive.typ;
+	priv->pixel_clock = timing->pixelclock.typ;
+	priv->log2_bpp = VIDEO_BPP16;
 
-	if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm",
-					   "#pwm-cells", 0, 0, &args)) {
-		debug("%s: Unable to decode PWM\n", __func__);
+	/*
+	 * Sadly the panel phandle is in an rgb subnode so we cannot use
+	 * uclass_get_device_by_phandle().
+	 */
+	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
+	if (panel_node < 0) {
+		debug("%s: Cannot find panel information\n", __func__);
 		return -EINVAL;
 	}
-
-	ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
+	ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
+					     &priv->panel);
 	if (ret) {
-		debug("%s: Unable to find PWM\n", __func__);
-		return -EINVAL;
+		debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
+		      dev->name, ret);
+		return ret;
 	}
-	priv->pwm_channel = args.args[0];
-
-	priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
-					  FDT_LCD_CACHE_WRITE_BACK_FLUSH);
-
-	/* These GPIOs are all optional */
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,backlight-enable-gpios", 0,
-				   &priv->backlight_en, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,lvds-shutdown-gpios", 0,
-				   &priv->lvds_shutdown, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,backlight-vdd-gpios", 0,
-				   &priv->backlight_vdd, GPIOD_IS_OUT);
-	gpio_request_by_name_nodev(blob, panel_node,
-				   "nvidia,panel-vdd-gpios", 0,
-				   &priv->panel_vdd, GPIOD_IS_OUT);
-
-	if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings",
-				 priv->panel_timings, FDT_LCD_TIMINGS))
-		return -EINVAL;
 
 	return 0;
 }
-- 
cgit v0.10.2


From 8d37483e7cfff9e36a928379d7ab6c4fc11bd4c1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 8 May 2016 16:55:21 -0600
Subject: tegra: video: Always use write-through cache on LCD

This seems to give the best performance, so let's use it always.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 5c48c3b..217f05f 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -22,15 +22,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-enum lcd_cache_t {
-	FDT_LCD_CACHE_OFF		= 0,
-	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
-	FDT_LCD_CACHE_WRITE_BACK	= 1 << 1,
-	FDT_LCD_CACHE_FLUSH		= 1 << 2,
-	FDT_LCD_CACHE_WRITE_BACK_FLUSH	= FDT_LCD_CACHE_WRITE_BACK |
-						FDT_LCD_CACHE_FLUSH,
-};
-
 /* Information about the display controller */
 struct tegra_lcd_priv {
 	int width;			/* width in pixels */
@@ -41,7 +32,6 @@ struct tegra_lcd_priv {
 	struct disp_ctlr *disp;		/* Display controller to use */
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
 	unsigned pixel_clock;		/* Pixel clock in Hz */
-	enum lcd_cache_t cache_type;
 };
 
 enum {
@@ -310,7 +300,6 @@ static int tegra_lcd_probe(struct udevice *dev)
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
 	const void *blob = gd->fdt_blob;
-	int type = DCACHE_OFF;
 	int ret;
 
 	/* Initialize the Tegra display controller */
@@ -329,15 +318,11 @@ static int tegra_lcd_probe(struct udevice *dev)
 		return ret;
 	}
 
-	/* Set up the LCD caching as requested */
-	if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
-		type = DCACHE_WRITETHROUGH;
-	else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
-		type = DCACHE_WRITEBACK;
-	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
+	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
+					DCACHE_WRITETHROUGH);
 
 	/* Enable flushing after LCD writes if requested */
-	video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
+	video_set_flush_dcache(dev, true);
 
 	uc_priv->xsize = priv->width;
 	uc_priv->ysize = priv->height;
-- 
cgit v0.10.2


From 703aaf76c2c06109fc36266767b2d1dcfce6f3ba Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 8 May 2016 16:55:22 -0600
Subject: fdt: Drop some unused compatible strings

We have driver-model drivers for some of these now, so drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 54e3d81..05d70c4 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -119,10 +119,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
 	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
 	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
-	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
-	COMPAT_NVIDIA_TEGRA124_SOR,	/* Tegra 124 Serial Output Resource */
 	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
-	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
 	COMPAT_NVIDIA_TEGRA186_SDMMC,	/* Tegra186 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
@@ -146,7 +143,6 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
 	COMPAT_SAMSUNG_EXYNOS_DWMMC,	/* Exynos DWMMC controller */
 	COMPAT_SAMSUNG_EXYNOS_MMC,	/* Exynos MMC controller */
-	COMPAT_SAMSUNG_EXYNOS_SERIAL,	/* Exynos UART */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
 	COMPAT_MAXIM_98095_CODEC,	/* MAX98095 Codec */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 686b89d..0534c0b 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -26,10 +26,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
 	COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
 	COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
-	COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
-	COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
 	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
-	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
 	COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
 	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
@@ -51,7 +48,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
 	COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
 	COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
-	COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"),
 	COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
 	COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
-- 
cgit v0.10.2


From c8864d720926c6b136aa9aa97fd1d4410250d271 Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Thu, 21 Apr 2016 09:28:02 +0200
Subject: spi: spi-uclass: fix typo in debug output

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 84b6786..80aff7b 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -333,7 +333,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
 	return 0;
 
 err:
-	debug("%s: Error path, credted=%d, device '%s'\n", __func__,
+	debug("%s: Error path, created=%d, device '%s'\n", __func__,
 	      created, dev->name);
 	if (created) {
 		device_remove(dev);
-- 
cgit v0.10.2


From 2307ea4053cdf45174f842312d07f538bf5be5f6 Mon Sep 17 00:00:00 2001
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Mon, 4 Apr 2016 04:07:33 -0500
Subject: common: Always include errno.h in common.h

We want people using errnos for errors instead of -1, so make it easy
by always including the definition of all the errnos.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/include/common.h b/include/common.h
index f9f4605..3feaae6 100644
--- a/include/common.h
+++ b/include/common.h
@@ -16,6 +16,7 @@ typedef volatile unsigned short vu_short;
 typedef volatile unsigned char	vu_char;
 
 #include <config.h>
+#include <errno.h>
 #include <asm-offsets.h>
 #include <linux/bitops.h>
 #include <linux/types.h>
-- 
cgit v0.10.2


From 66d027e22c55534135a43da794d31fcc98509913 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Date: Mon, 27 Jun 2016 13:17:51 +0300
Subject: net: designware: Make driver independent from DM_GPIO again

Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
 * dm_gpio_XXX()
 * gpio_request_by_name()

But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8858f07..8ba72e3 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -80,7 +80,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	return ret;
 }
 
-#if CONFIG_DM_ETH
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
 static int dw_mdio_reset(struct mii_dev *bus)
 {
 	struct udevice *dev = bus->priv;
@@ -126,7 +126,7 @@ static int dw_mdio_init(const char *name, void *priv)
 	bus->read = dw_mdio_read;
 	bus->write = dw_mdio_write;
 	snprintf(bus->name, sizeof(bus->name), "%s", name);
-#ifdef CONFIG_DM_ETH
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
 	bus->reset = dw_mdio_reset;
 #endif
 
@@ -690,11 +690,15 @@ static const struct eth_ops designware_eth_ops = {
 static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+#ifdef CONFIG_DM_GPIO
 	struct dw_eth_dev *priv = dev_get_priv(dev);
+#endif
 	struct eth_pdata *pdata = &dw_pdata->eth_pdata;
 	const char *phy_mode;
 	const fdt32_t *cell;
+#ifdef CONFIG_DM_GPIO
 	int reset_flags = GPIOD_IS_OUT;
+#endif
 	int ret = 0;
 
 	pdata->iobase = dev_get_addr(dev);
@@ -712,6 +716,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	if (cell)
 		pdata->max_speed = fdt32_to_cpu(*cell);
 
+#ifdef CONFIG_DM_GPIO
 	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
 			    "snps,reset-active-low"))
 		reset_flags |= GPIOD_ACTIVE_LOW;
@@ -724,6 +729,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	} else if (ret == -ENOENT) {
 		ret = 0;
 	}
+#endif
 
 	return ret;
 }
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 51ba769..d345c5b 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -8,7 +8,9 @@
 #ifndef _DW_ETH_H
 #define _DW_ETH_H
 
-#include <asm/gpio.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
 
 #define CONFIG_TX_DESCR_NUM	16
 #define CONFIG_RX_DESCR_NUM	16
@@ -234,7 +236,10 @@ struct dw_eth_dev {
 #ifndef CONFIG_DM_ETH
 	struct eth_device *dev;
 #endif
+#ifdef CONFIG_DM_GPIO
 	struct gpio_desc reset_gpio;
+#endif
+
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 };
-- 
cgit v0.10.2


From 19c9ddaa4f41f6f0bc5cf2991f24fc178c6e56ed Mon Sep 17 00:00:00 2001
From: Mingkai Hu <mingkai.hu@nxp.com>
Date: Fri, 1 Jul 2016 19:03:23 +0800
Subject: driver: net: phylib: add support for aquantia AQR106/107 PHY

This patch adds support for aquantia AQR106/107 PHY.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index f90c2ae..ad12f6d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -147,6 +147,32 @@ struct phy_driver aqr105_driver = {
 	.shutdown = &gen10g_shutdown,
 };
 
+struct phy_driver aqr106_driver = {
+	.name = "Aquantia AQR106",
+	.uid = 0x3a1b4d0,
+	.mask = 0xfffffff0,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+			MDIO_MMD_PHYXS | MDIO_MMD_AN |
+			MDIO_MMD_VEND1),
+	.config = &aquantia_config,
+	.startup = &aquantia_startup,
+	.shutdown = &gen10g_shutdown,
+};
+
+struct phy_driver aqr107_driver = {
+	.name = "Aquantia AQR107",
+	.uid = 0x3a1b4e0,
+	.mask = 0xfffffff0,
+	.features = PHY_10G_FEATURES,
+	.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+			MDIO_MMD_PHYXS | MDIO_MMD_AN |
+			MDIO_MMD_VEND1),
+	.config = &aquantia_config,
+	.startup = &aquantia_startup,
+	.shutdown = &gen10g_shutdown,
+};
+
 struct phy_driver aqr405_driver = {
 	.name = "Aquantia AQR405",
 	.uid = 0x3a1b4b2,
@@ -165,6 +191,8 @@ int phy_aquantia_init(void)
 	phy_register(&aq1202_driver);
 	phy_register(&aq2104_driver);
 	phy_register(&aqr105_driver);
+	phy_register(&aqr106_driver);
+	phy_register(&aqr107_driver);
 	phy_register(&aqr405_driver);
 
 	return 0;
-- 
cgit v0.10.2


From e4ead4a21db266c84051279ed4ceeab72981df8c Mon Sep 17 00:00:00 2001
From: Ralf Hubert <r.hubert@technisat.de>
Date: Fri, 1 Jul 2016 13:19:51 +0200
Subject: net: Fix incorrect RPC packets on 64-bit systems

This patch fixes incorrect RPC packet layout caused by
'long' type size difference on 64 and 32-bit architectures.

Signed-off-by: Ralf Hubert <r.hubert@technisat.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/net/nfs.c b/net/nfs.c
index f60a037..4a5a1ab 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -132,7 +132,7 @@ static char *dirname(char *path)
 /**************************************************************************
 RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries
 **************************************************************************/
-static long *rpc_add_credentials(long *p)
+static uint32_t *rpc_add_credentials(uint32_t *p)
 {
 	int hl;
 	int hostnamelen;
@@ -241,7 +241,7 @@ static void nfs_mount_req(char *path)
 	pathlen = strlen(path);
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	*p++ = htonl(pathlen);
 	if (pathlen & 3)
@@ -268,7 +268,7 @@ static void nfs_umountall_req(void)
 		return;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
@@ -289,7 +289,7 @@ static void nfs_readlink_req(void)
 	int len;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	memcpy(p, filefh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
@@ -312,7 +312,7 @@ static void nfs_lookup_req(char *fname)
 	fnamelen = strlen(fname);
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	memcpy(p, dirfh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
@@ -337,7 +337,7 @@ static void nfs_read_req(int offset, int readlen)
 	int len;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials((long *)p);
+	p = rpc_add_credentials(p);
 
 	memcpy(p, filefh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
-- 
cgit v0.10.2


From 4c64c4db3b87818318ed8b4cd6907c508aaf04ce Mon Sep 17 00:00:00 2001
From: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Date: Fri, 1 Jul 2016 13:22:00 -0700
Subject: net: rtl8169: Fix return value for rtl_send_common

Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.

Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.

Cc: Stephen Warren <swarren@nvidia.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 843b083..1cc0b40 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -666,12 +666,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
 		puts("tx timeout/error\n");
 		printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 #endif
-		ret = 0;
+		ret = -ETIMEDOUT;
 	} else {
 #ifdef DEBUG_RTL8169_TX
 		puts("tx done\n");
 #endif
-		ret = length;
+		ret = 0;
 	}
 	/* Delay to make net console (nc) work properly */
 	udelay(20);
-- 
cgit v0.10.2


From eb364c3dc28d59d33e823470d07746b22a8e6fee Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Wed, 6 Jul 2016 16:39:51 -0700
Subject: powerpc: mpc85xx: kmp204x: Fix compiling error for usb errata

Commit 9262367 moves USB errata workaround into a C file. This
causes compiling error for kmcoge4 and kmlion1. To enable the
errata workaround, define CONFIG_USB_EHCI_FSL in common header.

Signed-off-by: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Ed Swarthout <Ed.Swarthout@nxp.com>
Cc: Sriram Dash <sriram.dash@nxp.com>
Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")

diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 028623d..5bdda22 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -406,6 +406,7 @@ int get_scl(void);
 #endif
 
 #define __USB_PHY_TYPE	utmi
+#define CONFIG_USB_EHCI_FSL
 
 /*
  * Environment Configuration
-- 
cgit v0.10.2


From eb9d3ca3560d9348f2db83beb2f51a85806519dd Mon Sep 17 00:00:00 2001
From: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Date: Sun, 26 Jun 2016 22:43:55 +0200
Subject: mmc: msm_sdhci: Set mmc->dev pointer in msm_sdc_probe()

MMC core expects (now) valid mmc->dev pointer.
During conversion in commit cffe5d86 not every driver was updated.

This patch fixes crash while accessing MMC on
boards using Qualcomm SDHCI controller.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 64bbf0c..96dcdbe 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -136,7 +136,12 @@ static int msm_sdc_probe(struct udevice *dev)
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
 	/* automatically detect max and min speed */
-	return add_sdhci(host, 0, 0);
+	ret =  add_sdhci(host, 0, 0);
+	if (ret)
+		return ret;
+	host->mmc->dev = dev;
+
+	return 0;
 }
 
 static int msm_sdc_remove(struct udevice *dev)
-- 
cgit v0.10.2


From a82642f39856c0b9edb2545570b599a157b73f63 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 6 Jul 2016 09:04:08 -0600
Subject: test/py: fix CONFIG_ tests

Some CONFIG_ variables were recently renamed, but test/py wasn't updated
to match. This causes some tests to be skipped. Fix test/py so the tests
are run.

Fixes: 11636258981a ("Rename reset to sysreset")
Fixes: f1f9d4fac527 ("hush: complete renaming CONFIG_SYS_HUSH_PARSER to CONFIG_HUSH_PARSER")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py
index 1eeaa5b..b572538 100644
--- a/test/py/tests/test_hush_if_test.py
+++ b/test/py/tests/test_hush_if_test.py
@@ -109,27 +109,27 @@ def exec_hush_if(u_boot_console, expr, result):
     response = u_boot_console.run_command(cmd)
     assert response.strip() == str(result).lower()
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 def test_hush_if_test_setup(u_boot_console):
     """Set up environment variables used during the "if" tests."""
 
     u_boot_console.run_command('setenv ut_var_nonexistent')
     u_boot_console.run_command('setenv ut_var_exists 1')
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 @pytest.mark.parametrize('expr,result', subtests)
 def test_hush_if_test(u_boot_console, expr, result):
     """Test a single "if test" condition."""
 
     exec_hush_if(u_boot_console, expr, result)
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 def test_hush_if_test_teardown(u_boot_console):
     """Clean up environment variables used during the "if" tests."""
 
     u_boot_console.run_command('setenv ut_var_exists')
 
-@pytest.mark.buildconfigspec('sys_hush_parser')
+@pytest.mark.buildconfigspec('hush_parser')
 # We might test this on real filesystems via UMS, DFU, 'save', etc.
 # Of those, only UMS currently allows file removal though.
 @pytest.mark.boardspec('sandbox')
diff --git a/test/py/tests/test_sandbox_exit.py b/test/py/tests/test_sandbox_exit.py
index d1aa308..4e333ec 100644
--- a/test/py/tests/test_sandbox_exit.py
+++ b/test/py/tests/test_sandbox_exit.py
@@ -7,7 +7,7 @@ import pytest
 import signal
 
 @pytest.mark.boardspec('sandbox')
-@pytest.mark.buildconfigspec('reset')
+@pytest.mark.buildconfigspec('sysreset')
 def test_reset(u_boot_console):
     """Test that the "reset" command exits sandbox process."""
 
-- 
cgit v0.10.2


From 59d07ee08e858bf2c121d0cdc6c8ddd3b26ee5b1 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Fri, 8 Jul 2016 15:18:35 +0100
Subject: SPL: tiny-printf: avoid any BSS usage

As printf calls may be executed quite early, we should avoid using any
BSS stored variables, since some boards put BSS in DRAM, which may not
have been initialised yet.
Explicitly mark those "static global" variables as belonging to the
.data section, to keep tiny-printf clear of any BSS usage.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 451f4f7..b334f05 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -13,11 +13,16 @@
 #include <stdarg.h>
 #include <serial.h>
 
-static char *bf;
-static char zs;
+/*
+ * This code in here may execute before the DRAM is initialised, so
+ * we should make sure that it doesn't touch BSS, which some boards
+ * put in DRAM.
+ */
+static char *bf __attribute__ ((section(".data")));
+static char zs __attribute__ ((section(".data")));
 
 /* Current position in sprintf() output string */
-static char *outstr;
+static char *outstr __attribute__ ((section(".data")));
 
 static void out(char c)
 {
-- 
cgit v0.10.2


From 359787cfe48b066ba96b1062a1a85772464939d6 Mon Sep 17 00:00:00 2001
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Date: Mon, 18 Apr 2016 16:51:04 +0900
Subject: serial_sh: Device Tree support

Add Device Tree bindings.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/doc/device-tree-bindings/serial/sh.txt b/doc/device-tree-bindings/serial/sh.txt
new file mode 100644
index 0000000..b23b135
--- /dev/null
+++ b/doc/device-tree-bindings/serial/sh.txt
@@ -0,0 +1,6 @@
+* Renesas SCI serial interface
+
+Required properties:
+- compatible: must be "renesas,scif" or "renesas,scifa"
+- reg: exactly one register range with length
+- clock: input clock frequency for the SCI unit
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 8693c1e..32b2bf0 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -17,6 +17,8 @@
 #include <dm/platform_data/serial_sh.h>
 #include "serial_sh.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CPU_SH7760) || \
 	defined(CONFIG_CPU_SH7780) || \
 	defined(CONFIG_CPU_SH7785) || \
@@ -201,9 +203,35 @@ static const struct dm_serial_ops sh_serial_ops = {
 	.setbrg = sh_serial_setbrg,
 };
 
+#ifdef CONFIG_OF_CONTROL
+static const struct udevice_id sh_serial_id[] ={
+	{.compatible = "renesas,scif", .data = PORT_SCIF},
+	{.compatible = "renesas,scifa", .data = PORT_SCIFA},
+	{}
+};
+
+static int sh_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sh_serial_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->base = addr;
+	plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+	plat->type = dev_get_driver_data(dev);
+	return 0;
+}
+#endif
+
 U_BOOT_DRIVER(serial_sh) = {
 	.name	= "serial_sh",
 	.id	= UCLASS_SERIAL,
+	.of_match = of_match_ptr(sh_serial_id),
+	.ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
+	.platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
 	.probe	= sh_serial_probe,
 	.ops	= &sh_serial_ops,
 	.flags	= DM_FLAG_PRE_RELOC,
-- 
cgit v0.10.2


From 747431b9d54d3ebdef87352006218ed948011612 Mon Sep 17 00:00:00 2001
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Date: Mon, 18 Apr 2016 16:51:05 +0900
Subject: serial_sh: Add standrad SCI (w/o FIFO) support

Add support for standard type SCI (without FIFO) port.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/doc/device-tree-bindings/serial/sh.txt b/doc/device-tree-bindings/serial/sh.txt
index b23b135..99634a5 100644
--- a/doc/device-tree-bindings/serial/sh.txt
+++ b/doc/device-tree-bindings/serial/sh.txt
@@ -1,6 +1,6 @@
 * Renesas SCI serial interface
 
 Required properties:
-- compatible: must be "renesas,scif" or "renesas,scifa"
+- compatible: must be "renesas,scif", "renesas,scifa" or "renesas,sci"
 - reg: exactly one register range with length
 - clock: input clock frequency for the SCI unit
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 32b2bf0..ef7cf0f 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -205,6 +205,7 @@ static const struct dm_serial_ops sh_serial_ops = {
 
 #ifdef CONFIG_OF_CONTROL
 static const struct udevice_id sh_serial_id[] ={
+	{.compatible = "renesas,sci", .data = PORT_SCI},
 	{.compatible = "renesas,scif", .data = PORT_SCIF},
 	{.compatible = "renesas,scifa", .data = PORT_SCIFA},
 	{}
@@ -262,6 +263,8 @@ U_BOOT_DRIVER(serial_sh) = {
 
 #if defined(CONFIG_SCIF_A)
 	#define SCIF_BASE_PORT	PORT_SCIFA
+#elif defined(CONFIG_SCI)
+	#define SCIF_BASE_PORT  PORT_SCI
 #else
 	#define SCIF_BASE_PORT	PORT_SCIF
 #endif
-- 
cgit v0.10.2


From 0de02de76833cf3adcc0ba2e43cff52e6e18b63f Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Tue, 5 Jul 2016 20:37:17 +0200
Subject: arm: Fix setjmp (again)

Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp
code path with thumv1. Unfortunately it missed a constraint that the adr
instruction can only refer to 4 byte aligned offsets.

So this patch adds the required alignment hooks to make compilation
work again even when setjmp doesn't happen to be 4 byte aligned.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
index ae738b2..f7b97ef 100644
--- a/arch/arm/include/asm/setjmp.h
+++ b/arch/arm/include/asm/setjmp.h
@@ -43,6 +43,7 @@ static inline int setjmp(jmp_buf jmp)
 #else
 	asm volatile(
 #ifdef CONFIG_SYS_THUMB_BUILD
+		".align 2\n"
 		"adr r0, jmp_target\n"
 		"add r0, r0, $1\n"
 #else
@@ -52,7 +53,8 @@ static inline int setjmp(jmp_buf jmp)
 		"mov r2, sp\n"
 		"stm r1!, {r0, r2, r4, r5, r6, r7}\n"
 		"b 2f\n"
-		"jmp_target: "
+		".align 2\n"
+		"jmp_target: \n"
 		"mov %0, #1\n"
 		"2:\n"
 		: "+l" (r)
-- 
cgit v0.10.2


From 085e64dd421caeff6ebcdef867e67b99b0942659 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 6 Jul 2016 10:34:30 -0600
Subject: test/py: strip VT100 codes from match buffer

Prior to this patch, any VT100 codes emitted by U-Boot are considered part
of a command's output, which often causes tests to fail. For example,
test_env_echo_exists executes printenv, and then considers any text on a
line before an = sign as a valid U-Boot environment variable name. This
includes any VT100 codes emitted. When the test later attempts to use that
variable, the name would be invalid since it includes the VT100 codes.
Solve this by stripping VT100 codes from the match buffer, so they are
never seen by higher level test code.

The codes are still logged unmodified, so that users can expect U-Boot's
exact output without interference. This does clutter the log file a bit.
However, it allows users to see exactly what U-Boot emitted rather than a
modified version, which hopefully is better for debugging. It's also much
simpler to implement, since logging happens as soon as text is received,
and so stripping the VT100 codes from the log would require handling
reception and stripping of partial VT100 codes.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py
index a5f4a8e..d155173 100644
--- a/test/py/u_boot_spawn.py
+++ b/test/py/u_boot_spawn.py
@@ -38,6 +38,11 @@ class Spawn(object):
         self.before = ''
         self.after = ''
         self.timeout = None
+        # http://stackoverflow.com/questions/7857352/python-regex-to-match-vt100-escape-sequences
+        # Note that re.I doesn't seem to work with this regex (or perhaps the
+        # version of Python in Ubuntu 14.04), hence the inclusion of a-z inside
+        # [] instead.
+        self.re_vt100 = re.compile('(\x1b\[|\x9b)[^@-_a-z]*[@-_a-z]|\x1b[@-_a-z]')
 
         (self.pid, self.fd) = pty.fork()
         if self.pid == 0:
@@ -168,6 +173,10 @@ class Spawn(object):
                 if self.logfile_read:
                     self.logfile_read.write(c)
                 self.buf += c
+                # count=0 is supposed to be the default, which indicates
+                # unlimited substitutions, but in practice the version of
+                # Python in Ubuntu 14.04 appears to default to count=2!
+                self.buf = self.re_vt100.sub('', self.buf, count=1000000)
         finally:
             if self.logfile_read:
                 self.logfile_read.flush()
-- 
cgit v0.10.2


From d56dd0b1f8eb1dc13d4e6227a485fca5b9e94c1e Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Wed, 6 Jul 2016 12:44:22 +0200
Subject: test/py: support 'memstart =' in u_boot_utils.find_ram_base()

Some archs like MIPS or PPC have a different 'bdinfo' output
than ARM regarding the memory configuration. Also support
'memstart = 0x*' in u_boot_utils.find_ram_base() to make
all tests requiring the RAM base working on those archs.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 6a6b2ec..e4765e3 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -201,7 +201,7 @@ def find_ram_base(u_boot_console):
     with u_boot_console.log.section('find_ram_base'):
         response = u_boot_console.run_command('bdinfo')
         for l in response.split('\n'):
-            if '-> start' in l:
+            if '-> start' in l or 'memstart    =' in l:
                 ram_base = int(l.split('=')[1].strip(), 16)
                 break
         if ram_base is None:
-- 
cgit v0.10.2


From d73718f3236c520a92efa401084c658e6cc067f3 Mon Sep 17 00:00:00 2001
From: Mingkai Hu <mingkai.hu@nxp.com>
Date: Thu, 7 Jul 2016 12:22:12 +0800
Subject: armv8: Enable CPUECTLR.SMPEN for coherency

For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..dfce469 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,6 +81,14 @@ reset:
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
 
+	/* Enalbe SMPEN bit for coherency.
+	 * This register is not architectural but at the moment
+	 * this bit should be set for A53/A57/A72.
+	 */
+	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
+	orr     x0, x0, #0x40
+	msr     S3_1_c15_c2_1, x0
+
 	/* Apply ARM core specific erratas */
 	bl	apply_core_errata
 
-- 
cgit v0.10.2


From 7c616862553e37c89ea5db399961018a7367ca33 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:58:55 +0530
Subject: dm: core: implement dev_map_physmem()

This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index eb75b17..f7fb0cc 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <fdtdec.h>
 #include <fdt_support.h>
 #include <malloc.h>
@@ -697,6 +698,16 @@ void *dev_get_addr_ptr(struct udevice *dev)
 	return (void *)(uintptr_t)dev_get_addr_index(dev, 0);
 }
 
+void *dev_map_physmem(struct udevice *dev, unsigned long size)
+{
+	fdt_addr_t addr = dev_get_addr(dev);
+
+	if (addr == FDT_ADDR_T_NONE)
+		return NULL;
+
+	return map_physmem(addr, size, MAP_NOCACHE);
+}
+
 bool device_has_children(struct udevice *dev)
 {
 	return !list_empty(&dev->child_head);
diff --git a/include/dm/device.h b/include/dm/device.h
index f03bcd3..1bfcf3b 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -467,6 +467,19 @@ fdt_addr_t dev_get_addr(struct udevice *dev);
 void *dev_get_addr_ptr(struct udevice *dev);
 
 /**
+ * dev_map_physmem() - Read device address from reg property of the
+ *                     device node and map the address into CPU address
+ *                     space.
+ *
+ * @dev: Pointer to device
+ * @size: size of the memory to map
+ *
+ * @return  mapped address, or NULL if the device does not have reg
+ *          property.
+ */
+void *dev_map_physmem(struct udevice *dev, unsigned long size);
+
+/**
  * dev_get_addr_index() - Get the indexed reg property of a device
  *
  * @dev: Pointer to a device
-- 
cgit v0.10.2


From 192bb756dca3d6285a685c6b645b59190b28f4b5 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:58:56 +0530
Subject: spi: davinci_spi: Convert to driver to adapt to DM

Convert davinci_spi driver so that it complies with SPI DM framework.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0bd4f88..20aa99a 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -14,6 +14,7 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <dm.h>
 
 /* SPIGCR0 */
 #define SPIGCR0_SPIENA_MASK	0x1
@@ -51,6 +52,7 @@
 /* SPIDEF */
 #define SPIDEF_CSDEF0_MASK	BIT(0)
 
+#ifndef CONFIG_DM_SPI
 #define SPI0_BUS		0
 #define SPI0_BASE		CONFIG_SYS_SPI_BASE
 /*
@@ -83,6 +85,9 @@
 #define SPI2_NUM_CS		CONFIG_SYS_SPI2_NUM_CS
 #define SPI2_BASE		CONFIG_SYS_SPI2_BASE
 #endif
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* davinci spi register set */
 struct davinci_spi_regs {
@@ -114,16 +119,17 @@ struct davinci_spi_regs {
 
 /* davinci spi slave */
 struct davinci_spi_slave {
+#ifndef CONFIG_DM_SPI
 	struct spi_slave slave;
+#endif
 	struct davinci_spi_regs *regs;
-	unsigned int freq;
+	unsigned int freq; /* current SPI bus frequency */
+	unsigned int mode; /* current SPI mode used */
+	u8 num_cs;	   /* total no. of CS available */
+	u8 cur_cs;	   /* CS of current slave */
+	bool half_duplex;  /* true, if master is half-duplex only */
 };
 
-static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
-{
-	return container_of(slave, struct davinci_spi_slave, slave);
-}
-
 /*
  * This functions needs to act like a macro to avoid pipeline reloads in the
  * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
@@ -144,15 +150,14 @@ static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
 	return buf_reg_val;
 }
 
-static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
+static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
 			    u8 *rxp, unsigned long flags)
 {
-	struct davinci_spi_slave *ds = to_davinci_spi(slave);
 	unsigned int data1_reg_val;
 
 	/* enable CS hold, CS[n] and clear the data bits */
 	data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
-			 (slave->cs << SPIDAT1_CSNR_SHIFT));
+			 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 
 	/* wait till TXFULL is deasserted */
 	while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
@@ -175,15 +180,14 @@ static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
 	return 0;
 }
 
-static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
+static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
 			     const u8 *txp, unsigned long flags)
 {
-	struct davinci_spi_slave *ds = to_davinci_spi(slave);
 	unsigned int data1_reg_val;
 
 	/* enable CS hold and clear the data bits */
 	data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
-			 (slave->cs << SPIDAT1_CSNR_SHIFT));
+			 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 
 	/* wait till TXFULL is deasserted */
 	while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
@@ -209,16 +213,15 @@ static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
 	return 0;
 }
 
-#ifndef CONFIG_SPI_HALF_DUPLEX
-static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
-				  u8 *rxp, const u8 *txp, unsigned long flags)
+static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
+				  int len, u8 *rxp, const u8 *txp,
+				  unsigned long flags)
 {
-	struct davinci_spi_slave *ds = to_davinci_spi(slave);
 	unsigned int data1_reg_val;
 
 	/* enable CS hold and clear the data bits */
 	data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
-			 (slave->cs << SPIDAT1_CSNR_SHIFT));
+			 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
 
 	/* wait till TXFULL is deasserted */
 	while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
@@ -237,7 +240,115 @@ static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
 
 	return 0;
 }
-#endif
+
+
+static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
+{
+	unsigned int mode = 0, scalar;
+
+	/* Enable the SPI hardware */
+	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+	udelay(1000);
+	writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
+
+	/* Set master mode, powered up and not activated */
+	writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
+
+	/* CS, CLK, SIMO and SOMI are functional pins */
+	writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
+		SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
+
+	/* setup format */
+	scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+
+	/*
+	 * Use following format:
+	 *   character length = 8,
+	 *   MSB shifted out first
+	 */
+	if (ds->mode & SPI_CPOL)
+		mode |= SPI_CPOL;
+	if (!(ds->mode & SPI_CPHA))
+		mode |= SPI_CPHA;
+	writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
+		(mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
+
+	/*
+	 * Including a minor delay. No science here. Should be good even with
+	 * no delay
+	 */
+	writel((50 << SPI_C2TDELAY_SHIFT) |
+		(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
+
+	/* default chip select register */
+	writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
+
+	/* no interrupts */
+	writel(0, &ds->regs->int0);
+	writel(0, &ds->regs->lvl);
+
+	/* enable SPI */
+	writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+
+	return 0;
+}
+
+static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
+{
+	/* Disable the SPI hardware */
+	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+
+	return 0;
+}
+
+static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
+		unsigned int bitlen,  const void *dout, void *din,
+		unsigned long flags)
+{
+	unsigned int len;
+
+	if (bitlen == 0)
+		/* Finish any previously submitted transfers */
+		goto out;
+
+	/*
+	 * It's not clear how non-8-bit-aligned transfers are supposed to be
+	 * represented as a stream of bytes...this is a limitation of
+	 * the current SPI interface - here we terminate on receiving such a
+	 * transfer request.
+	 */
+	if (bitlen % 8) {
+		/* Errors always terminate an ongoing transfer */
+		flags |= SPI_XFER_END;
+		goto out;
+	}
+
+	len = bitlen / 8;
+
+	if (!dout)
+		return davinci_spi_read(ds, len, din, flags);
+	if (!din)
+		return davinci_spi_write(ds, len, dout, flags);
+	if (!ds->half_duplex)
+		return davinci_spi_read_write(ds, len, din, dout, flags);
+
+	printf("SPI full duplex not supported\n");
+	flags |= SPI_XFER_END;
+
+out:
+	if (flags & SPI_XFER_END) {
+		u8 dummy = 0;
+		davinci_spi_write(ds, 1, &dummy, flags);
+	}
+	return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct davinci_spi_slave, slave);
+}
 
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
@@ -313,6 +424,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	}
 
 	ds->freq = max_hz;
+	ds->mode = mode;
 
 	return &ds->slave;
 }
@@ -324,104 +436,143 @@ void spi_free_slave(struct spi_slave *slave)
 	free(ds);
 }
 
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *dout, void *din, unsigned long flags)
+{
+	struct davinci_spi_slave *ds = to_davinci_spi(slave);
+
+	ds->cur_cs = slave->cs;
+
+	return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
+}
+
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
-	unsigned int scalar;
 
-	/* Enable the SPI hardware */
-	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
-	udelay(1000);
-	writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
+#ifdef CONFIG_SPI_HALF_DUPLEX
+	ds->half_duplex = true;
+#else
+	ds->half_duplex = false;
+#endif
+	return __davinci_spi_claim_bus(ds, ds->slave.cs);
+}
 
-	/* Set master mode, powered up and not activated */
-	writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct davinci_spi_slave *ds = to_davinci_spi(slave);
 
-	/* CS, CLK, SIMO and SOMI are functional pins */
-	writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
-		SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
+	__davinci_spi_release_bus(ds);
+}
 
-	/* setup format */
-	scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+#else
+static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
+{
+	struct davinci_spi_slave *ds = dev_get_priv(bus);
 
-	/*
-	 * Use following format:
-	 *   character length = 8,
-	 *   clock signal delayed by half clk cycle,
-	 *   clock low in idle state - Mode 0,
-	 *   MSB shifted out first
-	 */
-	writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
-		(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
+	debug("%s speed %u\n", __func__, max_hz);
+	if (max_hz > CONFIG_SYS_SPI_CLK / 2)
+		return -EINVAL;
 
-	/*
-	 * Including a minor delay. No science here. Should be good even with
-	 * no delay
-	 */
-	writel((50 << SPI_C2TDELAY_SHIFT) |
-		(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
+	ds->freq = max_hz;
 
-	/* default chip select register */
-	writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
+	return 0;
+}
 
-	/* no interrupts */
-	writel(0, &ds->regs->int0);
-	writel(0, &ds->regs->lvl);
+static int davinci_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct davinci_spi_slave *ds = dev_get_priv(bus);
 
-	/* enable SPI */
-	writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+	debug("%s mode %u\n", __func__, mode);
+	ds->mode = mode;
 
 	return 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
+static int davinci_spi_claim_bus(struct udevice *dev)
 {
-	struct davinci_spi_slave *ds = to_davinci_spi(slave);
+	struct dm_spi_slave_platdata *slave_plat =
+		dev_get_parent_platdata(dev);
+	struct udevice *bus = dev->parent;
+	struct davinci_spi_slave *ds = dev_get_priv(bus);
+
+	if (slave_plat->cs >= ds->num_cs) {
+		printf("Invalid SPI chipselect\n");
+		return -EINVAL;
+	}
+	ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
 
-	/* Disable the SPI hardware */
-	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
+	return __davinci_spi_claim_bus(ds, slave_plat->cs);
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-	     const void *dout, void *din, unsigned long flags)
+static int davinci_spi_release_bus(struct udevice *dev)
 {
-	unsigned int len;
+	struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
 
-	if (bitlen == 0)
-		/* Finish any previously submitted transfers */
-		goto out;
+	return __davinci_spi_release_bus(ds);
+}
 
-	/*
-	 * It's not clear how non-8-bit-aligned transfers are supposed to be
-	 * represented as a stream of bytes...this is a limitation of
-	 * the current SPI interface - here we terminate on receiving such a
-	 * transfer request.
-	 */
-	if (bitlen % 8) {
-		/* Errors always terminate an ongoing transfer */
-		flags |= SPI_XFER_END;
-		goto out;
+static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			    const void *dout, void *din,
+			    unsigned long flags)
+{
+	struct dm_spi_slave_platdata *slave =
+		dev_get_parent_platdata(dev);
+	struct udevice *bus = dev->parent;
+	struct davinci_spi_slave *ds = dev_get_priv(bus);
+
+	if (slave->cs >= ds->num_cs) {
+		printf("Invalid SPI chipselect\n");
+		return -EINVAL;
 	}
+	ds->cur_cs = slave->cs;
 
-	len = bitlen / 8;
+	return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
+}
 
-	if (!dout)
-		return davinci_spi_read(slave, len, din, flags);
-	else if (!din)
-		return davinci_spi_write(slave, len, dout, flags);
-#ifndef CONFIG_SPI_HALF_DUPLEX
-	else
-		return davinci_spi_read_write(slave, len, din, dout, flags);
-#else
-	printf("SPI full duplex transaction requested with "
-	       "CONFIG_SPI_HALF_DUPLEX defined.\n");
-	flags |= SPI_XFER_END;
-#endif
+static int davinci_spi_probe(struct udevice *bus)
+{
+	/* Nothing to do */
+	return 0;
+}
 
-out:
-	if (flags & SPI_XFER_END) {
-		u8 dummy = 0;
-		davinci_spi_write(slave, 1, &dummy, flags);
+static int davinci_ofdata_to_platadata(struct udevice *bus)
+{
+	struct davinci_spi_slave *ds = dev_get_priv(bus);
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+
+	ds->regs = dev_map_physmem(bus, sizeof(struct davinci_spi_regs));
+	if (!ds->regs) {
+		printf("%s: could not map device address\n", __func__);
+		return -EINVAL;
 	}
+	ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
 	return 0;
 }
+
+static const struct dm_spi_ops davinci_spi_ops = {
+	.claim_bus	= davinci_spi_claim_bus,
+	.release_bus	= davinci_spi_release_bus,
+	.xfer		= davinci_spi_xfer,
+	.set_speed	= davinci_spi_set_speed,
+	.set_mode	= davinci_spi_set_mode,
+};
+
+static const struct udevice_id davinci_spi_ids[] = {
+	{ .compatible = "ti,keystone-spi" },
+	{ .compatible = "ti,dm6441-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(davinci_spi) = {
+	.name = "davinci_spi",
+	.id = UCLASS_SPI,
+	.of_match = davinci_spi_ids,
+	.ops = &davinci_spi_ops,
+	.ofdata_to_platdata = davinci_ofdata_to_platadata,
+	.priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
+	.probe = davinci_spi_probe,
+};
+#endif
-- 
cgit v0.10.2


From 39832244231eab3629f412f1a679779316c6e3e8 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:58:57 +0530
Subject: keystone2: spi: do not define DM_SPI and DM_SPI_FLASH for SPL build

Since Keystone2 devices do not have support DM in SPL, do not define
DM_SPI and DM_SPI_FLASH for SPL build.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 2ee26c4..4aa262e 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -89,6 +89,10 @@
 #define CONFIG_SYS_SPI2
 #define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
 #define CONFIG_SYS_SPI2_NUM_CS		4
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
 
 /* Network Configuration */
 #define CONFIG_PHYLIB
-- 
cgit v0.10.2


From e5fcf0372b4b59cc2b83da683177c5904edc4e93 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:58:58 +0530
Subject: ARM: dts: keystone2: add SPI aliases for davinci SPI nodes

Add aliases for SPI nodes in order for it to be probed by the DM
framework.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
index f39b969..be97f3f 100644
--- a/arch/arm/dts/keystone.dtsi
+++ b/arch/arm/dts/keystone.dtsi
@@ -19,6 +19,9 @@
 
 	aliases {
 		serial0	= &uart0;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
 	};
 
 	chosen {
-- 
cgit v0.10.2


From 96368e6e389e6be64b9f4dfa654d5fdcf2d32653 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:58:59 +0530
Subject: ARM: dts: k2hk: Enable Davinci SPI controller

Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/k2hk-evm.dts b/arch/arm/dts/k2hk-evm.dts
index 660ebf5..c5cad2c 100644
--- a/arch/arm/dts/k2hk-evm.dts
+++ b/arch/arm/dts/k2hk-evm.dts
@@ -147,10 +147,11 @@
 };
 
 &spi0 {
+	status = "okay";
 	nor_flash: n25q128a11@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "Micron,n25q128a11";
+		compatible = "Micron,n25q128a11", "spi-flash";
 		spi-max-frequency = <54000000>;
 		m25p,fast-read;
 		reg = <0>;
-- 
cgit v0.10.2


From 376c533b8997a929f6c52313ad5f480c620b0d09 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:00 +0530
Subject: defconfig: k2hk_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2HK SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 278eaf3..8623e1c 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From 2655f1625a97742e1de7db947811115e112d8fb5 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:01 +0530
Subject: ARM: dts: k2e: Enable Davinci SPI controller

Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/k2e-evm.dts b/arch/arm/dts/k2e-evm.dts
index 50c83c2..e2c3fb4 100644
--- a/arch/arm/dts/k2e-evm.dts
+++ b/arch/arm/dts/k2e-evm.dts
@@ -119,10 +119,11 @@
 };
 
 &spi0 {
+	status = "okay";
 	nor_flash: n25q128a11@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "Micron,n25q128a11";
+		compatible = "Micron,n25q128a11", "spi-flash";
 		spi-max-frequency = <54000000>;
 		m25p,fast-read;
 		reg = <0>;
-- 
cgit v0.10.2


From cf4f0a9afc2ca1e6a8abb6dd777dd0e5a02cbd94 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:02 +0530
Subject: defconfig: k2e_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2E SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 9fcdfe9..65561b1 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From 188179481d4ce286fd7f4f59777272e4c65b789b Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:03 +0530
Subject: ARM: dts: k2l: Enable Davinci SPI controller

Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/k2l-evm.dts b/arch/arm/dts/k2l-evm.dts
index 9a69a6b..da0661b 100644
--- a/arch/arm/dts/k2l-evm.dts
+++ b/arch/arm/dts/k2l-evm.dts
@@ -96,10 +96,11 @@
 };
 
 &spi0 {
+	status ="okay";
 	nor_flash: n25q128a11@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "Micron,n25q128a11";
+		compatible = "Micron,n25q128a11", "spi-flash";
 		spi-max-frequency = <54000000>;
 		m25p,fast-read;
 		reg = <0>;
-- 
cgit v0.10.2


From c48f879c38afdfe746c2a39de6214d8c80a9ba4c Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:04 +0530
Subject: defconfig: k2l_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2L SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 8417e0a..9aa429c 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -28,6 +28,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_TI_AEMIF=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From c8e750473a8b81f38e1ece0a2a99572d36ebda53 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:05 +0530
Subject: ARM: dts: k2g: add support for Davinci SPI controller

K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts
index 0ca36ef..38ca7ae 100644
--- a/arch/arm/dts/k2g-evm.dts
+++ b/arch/arm/dts/k2g-evm.dts
@@ -31,3 +31,27 @@
 &gbe0 {
 	phy-handle = <&ethphy0>;
 };
+
+&spi1 {
+	status = "okay";
+
+	spi_nor: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		reg = <0>;
+
+		partition@0 {
+			label = "u-boot-spl";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@1 {
+			label = "misc";
+			reg = <0x80000 0xf80000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi
index a3ed444..88b1a8e 100644
--- a/arch/arm/dts/k2g.dtsi
+++ b/arch/arm/dts/k2g.dtsi
@@ -19,6 +19,10 @@
 
 	aliases {
 		serial0	= &uart0;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
 	};
 
 	memory {
@@ -88,5 +92,48 @@
 			ti,lpsc_module = <1>;
 		};
 
+		spi0: spi@21805400 {
+			compatible = "ti,keystone-spi", "ti,dm6441-spi";
+			reg = <0x21805400 0x200>;
+			num-cs = <4>;
+			ti,davinci-spi-intr-line = <0>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@21805800 {
+			compatible = "ti,keystone-spi", "ti,dm6441-spi";
+			reg = <0x21805800 0x200>;
+			num-cs = <4>;
+			ti,davinci-spi-intr-line = <0>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@21805c00 {
+			compatible = "ti,keystone-spi", "ti,dm6441-spi";
+			reg = <0x21805C00 0x200>;
+			num-cs = <4>;
+			ti,davinci-spi-intr-line = <0>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi3: spi@21806000 {
+			compatible = "ti,keystone-spi", "ti,dm6441-spi";
+			reg = <0x21806000 0x200>;
+			num-cs = <4>;
+			ti,davinci-spi-intr-line = <0>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };
-- 
cgit v0.10.2


From fdf02a36c52cb96717b64113775c4251ecd49596 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 09:59:06 +0530
Subject: defconfig: k2g_evm_defconfig: enable SPI driver model

Enable SPI and SPI Flash driver model as K2G SPI controller driver
supports driver model.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 8efa58c..802eeee 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -27,6 +27,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
-- 
cgit v0.10.2


From dac3bf20fb2c9b03476be0d73db620f62ab3cee1 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 10:20:55 +0530
Subject: spi: cadence_qspi_apb: Support 32 bit AHB address

AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a71531d..a8cc23f 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -45,7 +45,6 @@
 #define CQSPI_INST_TYPE_QUAD			(2)
 
 #define CQSPI_STIG_DATA_LEN_MAX			(8)
-#define CQSPI_INDIRECTTRIGGER_ADDR_MASK		(0xFFFFF)
 
 #define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
 #define CQSPI_DUMMY_BYTES_MAX			(4)
@@ -573,7 +572,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 		addr_bytes = cmdlen - 1;
 
 	/* Setup the indirect trigger address */
-	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+	writel((u32)plat->ahbbase,
 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
 	/* Configure the opcode */
@@ -714,7 +713,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 		return -EINVAL;
 	}
 	/* Setup the indirect trigger address */
-	writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
+	writel((u32)plat->ahbbase,
 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
 	/* Configure the opcode */
-- 
cgit v0.10.2


From 2372e14f1937fceea54d698342e5a4240b58a893 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 10:20:56 +0530
Subject: spi: cadence_quadspi: Enable QUAD mode based on DT data

Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 4f7fd52..a5244ff 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -191,6 +191,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	struct udevice *bus = dev->parent;
 	struct cadence_spi_platdata *plat = bus->platdata;
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
 	void *base = priv->regbase;
 	u8 *cmd_buf = priv->cmd_buf;
 	size_t data_bytes;
@@ -250,7 +251,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		break;
 		case CQSPI_INDIRECT_READ:
 			err = cadence_qspi_apb_indirect_read_setup(plat,
-				priv->cmd_len, cmd_buf);
+				priv->cmd_len, dm_plat->mode_rx, cmd_buf);
 			if (!err) {
 				err = cadence_qspi_apb_indirect_read_execute
 				(plat, data_bytes, din);
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 2912e36..a849f7b 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -53,7 +53,7 @@ int cadence_qspi_apb_command_write(void *reg_base_addr,
 	unsigned int txlen,  const u8 *txbuf);
 
 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
-	unsigned int cmdlen, const u8 *cmdbuf);
+	unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 	unsigned int rxlen, u8 *rxbuf);
 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a8cc23f..1a35d55 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -29,6 +29,7 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <wait_bit.h>
+#include <spi.h>
 #include "cadence_qspi.h"
 
 #define CQSPI_REG_POLL_US			(1) /* 1us */
@@ -548,7 +549,7 @@ int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 
 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
-	unsigned int cmdlen, const u8 *cmdbuf)
+	unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
 {
 	unsigned int reg;
 	unsigned int rd_reg;
@@ -578,10 +579,9 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 	/* Configure the opcode */
 	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
-#if (CONFIG_SPI_FLASH_QUAD == 1)
-	/* Instruction and address at DQ0, data at DQ0-3. */
-	rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
-#endif
+	if (rx_width & SPI_RX_QUAD)
+		/* Instruction and address at DQ0, data at DQ0-3. */
+		rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 
 	/* Get address */
 	addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
-- 
cgit v0.10.2


From b60774fff1d2098c79cf1efb1e242f5f662ce317 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 10:20:57 +0530
Subject: ARM: dts: K2G: Add support for QSPI controller

K2G SoC has a Cadence QSPI controller to communicate with NOR flash
devices. Add DT nodes to support the same.
Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor
flash slave node for the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts
index 38ca7ae..e95efd4 100644
--- a/arch/arm/dts/k2g-evm.dts
+++ b/arch/arm/dts/k2g-evm.dts
@@ -55,3 +55,48 @@
 		};
 	};
 };
+
+&qspi {
+	status = "okay";
+
+        flash0: m25p80@0 {
+                compatible = "s25fl512s","spi-flash";
+                reg = <0>;
+                spi-tx-bus-width = <1>;
+                spi-rx-bus-width = <4>;
+                spi-max-frequency = <96000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                tshsl-ns = <392>;
+                tsd2d-ns = <392>;
+                tchsh-ns = <100>;
+                tslch-ns = <100>;
+		block-size = <18>;
+
+
+                partition@0 {
+                        label = "QSPI.u-boot-spl-os";
+                        reg = <0x00000000 0x00100000>;
+                };
+                partition@1 {
+                        label = "QSPI.u-boot-env";
+                        reg = <0x00100000 0x00040000>;
+                };
+                partition@2 {
+                        label = "QSPI.skern";
+                        reg = <0x00140000 0x0040000>;
+                };
+                partition@3 {
+                        label = "QSPI.pmmc-firmware";
+                        reg = <0x00180000 0x0040000>;
+                };
+                partition@4 {
+                        label = "QSPI.kernel";
+                        reg = <0x001C0000 0x0800000>;
+                };
+                partition@5 {
+                        label = "QSPI.file-system";
+                        reg = <0x009C0000 0x3640000>;
+                };
+        };
+};
diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi
index 88b1a8e..00cd492 100644
--- a/arch/arm/dts/k2g.dtsi
+++ b/arch/arm/dts/k2g.dtsi
@@ -23,6 +23,7 @@
 		spi1 = &spi1;
 		spi2 = &spi2;
 		spi3 = &spi3;
+		spi4 = &qspi;
 	};
 
 	memory {
@@ -84,6 +85,19 @@
 			bus_freq = <2500000>;
 		};
 
+		qspi: qspi@2940000 {
+			compatible =  "cadence,qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x02940000 0x1000>,
+			      <0x24000000 0x4000000>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+			num-cs = <4>;
+			fifo-depth = <256>;
+			sram-size = <256>;
+			status = "disabled";
+		};
+
 		#include "k2g-netcp.dtsi"
 
 		pmmc: pmmc@2900000 {
-- 
cgit v0.10.2


From 988fb5ce610bbd2cc5a839cce737bba307e94db7 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 10:20:58 +0530
Subject: defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller

Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also
enable Spansion flash support to access s25fl512s flash present on K2G
QSPI bus.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 802eeee..5d44e8d 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -37,3 +37,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_BAR=y
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index f8bba67..71b0037 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -73,4 +73,10 @@
 #define CONFIG_SF_DEFAULT_BUS		1
 #define CONFIG_SF_DEFAULT_CS		0
 
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CADENCE_QSPI
+#define CONFIG_CQSPI_REF_CLK 384000000
+#define CONFIG_CQSPI_DECODER 0x0
+#endif
+
 #endif /* __CONFIG_K2G_EVM_H */
-- 
cgit v0.10.2


From e835a74159798723592e3c45d06793cd6acaf7ff Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 10:26:03 +0530
Subject: ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 08ef04e..429b9ed 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -491,15 +491,13 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <48000000>;
+	spi-max-frequency = <64000000>;
 	m25p80@0 {
 		compatible = "s25fl256s1","spi-flash";
-		spi-max-frequency = <48000000>;
+		spi-max-frequency = <64000000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index 205103e..ced2f11 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -603,15 +603,13 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <48000000>;
+	spi-max-frequency = <64000000>;
 	m25p80@0 {
 		compatible = "s25fl256s1","spi-flash";
-		spi-max-frequency = <48000000>;
+		spi-max-frequency = <64000000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-- 
cgit v0.10.2


From 96907c0fe50a856f66f60ade68864a2d7949bf15 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Wed, 6 Jul 2016 10:04:28 +0530
Subject: dm: spi: Read default speed and mode values from DT

In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/cmd/sf.c b/cmd/sf.c
index 42862d9..286906c 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -88,6 +88,8 @@ static int do_spi_flash_probe(int argc, char * const argv[])
 #ifdef CONFIG_DM_SPI_FLASH
 	struct udevice *new, *bus_dev;
 	int ret;
+	/* In DM mode defaults will be taken from DT */
+	speed = 0, mode = 0;
 #else
 	struct spi_flash *new;
 #endif
diff --git a/common/env_sf.c b/common/env_sf.c
index 273098c..c53200f 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -55,9 +55,9 @@ int saveenv(void)
 #ifdef CONFIG_DM_SPI_FLASH
 	struct udevice *new;
 
+	/* speed and mode will be read from DT */
 	ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
-				     CONFIG_ENV_SPI_MAX_HZ,
-				     CONFIG_ENV_SPI_MODE, &new);
+				     0, 0, &new);
 	if (ret) {
 		set_default_env("!spi_flash_probe_bus_cs() failed");
 		return 1;
@@ -245,9 +245,9 @@ int saveenv(void)
 #ifdef CONFIG_DM_SPI_FLASH
 	struct udevice *new;
 
+	/* speed and mode will be read from DT */
 	ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
-				     CONFIG_ENV_SPI_MAX_HZ,
-				     CONFIG_ENV_SPI_MODE, &new);
+				     0, 0, &new);
 	if (ret) {
 		set_default_env("!spi_flash_probe_bus_cs() failed");
 		return 1;
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 80aff7b..8003f9b 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -278,6 +278,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
 		       struct udevice **busp, struct spi_slave **devp)
 {
 	struct udevice *bus, *dev;
+	struct dm_spi_slave_platdata *plat;
 	bool created = false;
 	int ret;
 
@@ -294,8 +295,6 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
 	 * SPI flash chip - we will bind to the correct driver.
 	 */
 	if (ret == -ENODEV && drv_name) {
-		struct dm_spi_slave_platdata *plat;
-
 		debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
 		      __func__, dev_name, busnum, cs, drv_name);
 		ret = device_bind_driver(bus, drv_name, dev_name, &dev);
@@ -322,6 +321,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
 		slave->dev = dev;
 	}
 
+	plat = dev_get_parent_platdata(dev);
+	if (!speed) {
+		speed = plat->max_hz;
+		mode = plat->mode;
+	}
 	ret = spi_set_speed_mode(bus, speed, mode);
 	if (ret)
 		goto err;
-- 
cgit v0.10.2


From 5fb0001a6729d2d5132b87f7123dc3f357ac74f8 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Sat, 9 Jul 2016 21:12:04 +0800
Subject: git-mailrc: add rockchip alias

It's easier to Cc rockchip maintainers on rockchip-releated patches.

Signed-off-by: jk <jk.kernel@gmail.com>

diff --git a/doc/git-mailrc b/doc/git-mailrc
index 1d6f4fc..8f0724f 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -76,7 +76,7 @@ alias tegra2         tegra
 alias ti             uboot, trini
 alias uniphier       uboot, masahiro
 alias zynq           uboot, monstr
-
+alias rockchip       uboot, sjg, Lin huang <hl@rock-chips.com>
 alias avr32          uboot, abiessmann
 
 alias bfin           uboot, vapier, sonic
-- 
cgit v0.10.2


From 969cd1fa6df4d13615e26afbf03864670af6c098 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Mon, 11 Jul 2016 16:09:48 +0200
Subject: mkimage -l is broken for images after gpimage

Because a gpimage cannot be detected, a false
GP header is printed instead of checking
for further image types.

Move gpimage as last to be linked, letting check
all other image types and printing a GP header just
in case no image is detected.

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/tools/Makefile b/tools/Makefile
index 63355aa..f72294a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -76,8 +76,6 @@ dumpimage-mkimage-objs := aisimage.o \
 			lib/fdtdec.o \
 			fit_common.o \
 			fit_image.o \
-			gpimage.o \
-			gpimage-common.o \
 			common/image-fit.o \
 			image-host.o \
 			common/image.o \
@@ -100,6 +98,8 @@ dumpimage-mkimage-objs := aisimage.o \
 			zynqimage.o \
 			zynqmpimage.o \
 			$(LIBFDT_OBJS) \
+			gpimage.o \
+			gpimage-common.o \
 			$(RSA_OBJS-y)
 
 dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
-- 
cgit v0.10.2


From a868598a4844adf231c0e094b75219327237f262 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Fri, 8 Jul 2016 15:25:23 +0100
Subject: doc: ARMv8: add README.pine64

Since we lack information about the DRAM initialization for the
Allwinner A64 SoC, booting any A64 based board like the Pine64 is a bit
involved at the moment.
Add a README file to explain the process.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to board/sunxi/ from doc/]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/board/sunxi/README.pine64 b/board/sunxi/README.pine64
new file mode 100644
index 0000000..5553415
--- /dev/null
+++ b/board/sunxi/README.pine64
@@ -0,0 +1,98 @@
+Pine64 board README
+====================
+
+The Pine64(+) is a single board computer equipped with an AArch64 capable ARMv8
+compliant Allwinner A64 SoC.
+This chip has ARM Cortex A-53 cores and thus can run both in AArch32
+(compatible to 32-bit ARMv7) and AArch64 modes. Upon reset the SoC starts
+in AArch32 mode and executes 32-bit code from the Boot ROM (BROM).
+This has some implications on U-Boot.
+
+Quick start
+============
+- Get hold of a boot0.img file (see below for more details).
+- Get the boot0img tool source from the tools directory in [1] and compile
+  that on your host.
+- Build U-Boot:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make pine64_plus_defconfig
+$ make
+- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the
+  "allwinner" branch from the github repository [2] and build it:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make PLAT=sun50iw1p1 DEBUG=1 bl31
+  The resulting binary is build/sun50iw1p1/debug/bl31.bin.
+
+Now put an empty (or disposable) micro SD card in your card reader and learn
+its device file name, replacing /dev/sd<x> below with the result (that could
+be /dev/mmcblk<x> as well):
+
+$ ./boot0img --device /dev/sd<x> -e -u u-boot.bin -B boot0.img \
+	-d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100
+(either copying the respective files to the working directory or specifying
+the paths directly)
+
+This will create a new partition table (with a 100 MB FAT boot partition),
+copies boot0.img, ATF and U-Boot to the proper locations on the SD card and
+will fill in the magic Allwinner header to be recognized by boot0.
+Prefix the above call with "sudo" if you don't have write access to the
+uSD card. You can also use "-o output.img" instead of "--device /dev/sd<x>"
+to create an image file and "dd" that to the uSD card.
+Omitting the "-p" option will skip the partition table.
+
+Now put this uSD card in the board and power it on. You should be greeted by
+the U-Boot prompt.
+
+
+Main U-Boot
+============
+The main U-Boot proper is a real 64-bit ARMv8 port and runs entirely in the
+64-bit AArch64 mode. It can load any AArch64 code, EFI applications or arm64
+Linux kernel images (often named "Image") using the booti command.
+Launching 32-bit code and kernels is technically possible, though not without
+drawbacks (or hacks to avoid them) and currently not implemented.
+
+SPL support
+============
+The main task of the SPL support is to bring up the DRAM controller and make
+DRAM actually accessible. At the moment there is no documentation or source
+code available which would do this.
+There are currently two ways to overcome this situation: using a tainted 32-bit
+SPL (involving some hacks and resulting in a non-redistributable binary, thus
+not described here) or using the Allwinner boot0 blob.
+
+boot0 method
+-------------
+boot0 is Allwiner's secondary program loader and it can be used as some kind
+of SPL replacement to get U-Boot up and running.
+The binary is a 32 KByte blob and contained on every Pine64 image distributed
+so far. It can be easily extracted from a micro SD card or an image file:
+# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
+where /dev/sd<x> is the device name of the uSD card or the name of the image
+file. Apparently Allwinner allows re-distribution of this proprietary code
+as-is.
+For the time being this boot0 blob is the only redistributable way of making
+U-Boot work on the Pine64. Beside loading the various parts of the (original)
+firmware it also switches the core into AArch64 mode.
+The original boot0 code looks for U-Boot at a certain place on an uSD card
+(at 19096 KB), also it expects a header with magic bytes and a checksum.
+There is a tool called boot0img[1] which takes a boot0.bin image and a compiled
+U-Boot binary (plus other binaries) and will populate that header accordingly.
+To make space for the magic header, the pine64_plus_defconfig will make sure
+there is sufficient space at the beginning of the U-Boot binary.
+boot0img will also take care of putting the different binaries at the right
+places on the uSD card and works around unused, but mandatory parts by using
+trampoline code. See the output of "boot0img -h" for more information.
+boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
+fetching it from just behind the boot0 binary (-B option).
+
+FEL boot
+=========
+FEL is the name of the Allwinner defined USB boot protocol built-in the
+mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
+by using the USB-OTG interface and a host port on another computer.
+Since FEL boot does not work with boot0, it requires the libdram hack, which
+is not described here.
+
+[1] https://github.com/apritzel/pine64/
+[2] https://github.com/apritzel/arm-trusted-firmware.git
-- 
cgit v0.10.2


From 19ce924ff914f315dc2fdf79f357825c513aed6e Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 11 Jul 2016 15:01:01 -0400
Subject: Prepare v2016.07

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 09a18e1..88128ec 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From e7a773a0bcceb130e441398d8bc97febacb0d499 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:13 -0600
Subject: dm: mmc: dwmmc: Add comments to the dwmmc setup functions

These comments were missed when the original code was written. Add them to
help people port their drivers over.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/dwmmc.h b/include/dwmmc.h
index 335af51..0199def 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -224,9 +224,73 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
 	return readb(host->ioaddr + reg);
 }
 
+#ifdef CONFIG_BLK
+/**
+ * dwmci_setup_cfg() - Set up the configuration for DWMMC
+ *
+ * This is used to set up a DWMMC device when you are using CONFIG_BLK.
+ *
+ * This should be called from your MMC driver's probe() method once you have
+ * the information required.
+ *
+ * Generally your driver will have a platform data structure which holds both
+ * the configuration (struct mmc_config) and the MMC device info (struct mmc).
+ * For example:
+ *
+ * struct rockchip_mmc_plat {
+ *	struct mmc_config cfg;
+ *	struct mmc mmc;
+ * };
+ *
+ * ...
+ *
+ * Inside U_BOOT_DRIVER():
+ *	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
+ *
+ * To access platform data:
+ *	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ *
+ * See rockchip_dw_mmc.c for an example.
+ *
+ * @cfg:	Configuration structure to fill in (generally &plat->mmc)
+ * @name:	Device name (normally dev->name)
+ * @buswidth:	Bus width (in bits, such as 4 or 8)
+ * @caps:	Host capabilities (MMC_MODE_...)
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 400000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 150000000)
+ */
 void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 		     uint caps, u32 max_clk, u32 min_clk);
+
+/**
+ * dwmci_bind() - Set up a new MMC block device
+ *
+ * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
+ * It should be called from your driver's bind() method.
+ *
+ * See rockchip_dw_mmc.c for an example.
+ *
+ * @dev:	Device to set up
+ * @mmc:	Pointer to mmc structure (normally &plat->mmc)
+ * @cfg:	Empty configuration structure (generally &plat->cfg). This is
+ *		normally all zeroes at this point. The only purpose of passing
+ *		this in is to set mmc->cfg to it.
+ * @return 0 if OK, -ve if the block device could not be created
+ */
 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 
+#else
+/**
+ * add_dwmci() - Add a new DWMMC interface
+ *
+ * This is used when you are not using CONFIG_BLK. Convert your driver over!
+ *
+ * @host:	DWMMC host structure
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 400000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 150000000)
+ * @return 0 if OK, -ve on error
+ */
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
+#endif /* !CONFIG_BLK */
+
 #endif	/* __DWMMC_HW_H */
-- 
cgit v0.10.2


From aa15038cdf4a00898bac05be8af63e6d1006aa1f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:14 -0600
Subject: rockchip: Use 'select' instead of defaults in Kconfig

Rockchip uses driver model for all subsystems. Specify this in the arm
Kconfig rather than as defaults in the Rockchip Kconfig. This means that
boards cannot turn these options off, which seems correct.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3237a74..8004c17 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -842,7 +842,17 @@ config ARCH_ROCKCHIP
 	select SPL
 	select OF_CONTROL
 	select CPU_V7
+	select BLK
 	select DM
+	select SPL_DM
+	select SYS_MALLOC_F
+	select SPL_SYS_MALLOC_SIMPLE
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select DM_SERIAL
+	select DM_SPI
+	select DM_SPI_FLASH
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 2a8afac..c49cc19 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -17,33 +17,6 @@ config ROCKCHIP_RK3036
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
-config SYS_MALLOC_F
-	default y
-
-config SPL_SYS_MALLOC_SIMPLE
-	default y
-
-config SPL_DM
-	default y
-
-config DM_SERIAL
-	default y
-
-config DM_SPI
-	default y
-
-config DM_SPI_FLASH
-	default y
-
-config DM_I2C
-	default y
-
-config DM_GPIO
-	default y
-
-config BLK
-	default y
-
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 endif
-- 
cgit v0.10.2


From 7dba0b93672adf94285bfd072eed543d3b68d4c9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:15 -0600
Subject: mmc: Add function declarations for mmc_bread() and mmc_switch_part()

These private functions are used both in the driver-model implementation and
in the legacy code. Add them to the header.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index aabfc71..a27fcb4 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -215,11 +215,10 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 }
 
 #ifdef CONFIG_BLK
-static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
-		       void *dst)
+ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
 #else
-static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
-		       lbaint_t blkcnt, void *dst)
+ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
+		void *dst)
 #endif
 {
 #ifdef CONFIG_BLK
@@ -566,7 +565,7 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
 	return 0;
 }
 
-static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 {
 	int ret;
 
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 9f0d5c2..cfc4aca 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -20,6 +20,14 @@ extern int mmc_set_blocklen(struct mmc *mmc, int len);
 void mmc_adapter_card_type_ident(void);
 #endif
 
+#ifdef CONFIG_BLK
+ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+		void *dst);
+#else
+ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
+		void *dst);
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 
 unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
@@ -89,4 +97,13 @@ void mmc_list_init(void);
  */
 void mmc_list_add(struct mmc *mmc);
 
+/**
+ * mmc_switch_part() - Switch to a new MMC hardware partition
+ *
+ * @mmc:	MMC device
+ * @part_num:	Hardware partition number
+ * @return 0 if OK, -ve on error
+ */
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
+
 #endif /* _MMC_PRIVATE_H_ */
-- 
cgit v0.10.2


From eede897e2782a90efc8190ff8424e216730ced7d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:16 -0600
Subject: dm: mmc: Move CONFIG_BLK code into the mmc uclass

Rather than having #ifdef in mmc.c, move this code into the uclass file.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 1b967d9..530276a 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -8,8 +8,10 @@
 #include <common.h>
 #include <mmc.h>
 #include <dm.h>
+#include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/root.h>
+#include "mmc_private.h"
 
 struct mmc *mmc_get_mmc_dev(struct udevice *dev)
 {
@@ -125,6 +127,84 @@ void print_mmc_devices(char separator)
 #else
 void print_mmc_devices(char separator) { }
 #endif
+
+int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
+{
+	struct blk_desc *bdesc;
+	struct udevice *bdev;
+	int ret;
+
+	ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512,
+				 0, &bdev);
+	if (ret) {
+		debug("Cannot create block device\n");
+		return ret;
+	}
+	bdesc = dev_get_uclass_platdata(bdev);
+	mmc->cfg = cfg;
+	mmc->priv = dev;
+
+	/* the following chunk was from mmc_register() */
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = 0xffffffff;
+	/* Setup the universal parts of the block interface just once */
+	bdesc->removable = 1;
+
+	/* setup initial part type */
+	bdesc->part_type = cfg->part_type;
+	mmc->dev = dev;
+
+	return 0;
+}
+
+int mmc_unbind(struct udevice *dev)
+{
+	struct udevice *bdev;
+
+	device_find_first_child(dev, &bdev);
+	if (bdev) {
+		device_remove(bdev);
+		device_unbind(bdev);
+	}
+
+	return 0;
+}
+
+static int mmc_select_hwpart(struct udevice *bdev, int hwpart)
+{
+	struct udevice *mmc_dev = dev_get_parent(bdev);
+	struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
+	struct blk_desc *desc = dev_get_uclass_platdata(bdev);
+	int ret;
+
+	if (desc->hwpart == hwpart)
+		return 0;
+
+	if (mmc->part_config == MMCPART_NOAVAILABLE)
+		return -EMEDIUMTYPE;
+
+	ret = mmc_switch_part(mmc, hwpart);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct blk_ops mmc_blk_ops = {
+	.read	= mmc_bread,
+#ifndef CONFIG_SPL_BUILD
+	.write	= mmc_bwrite,
+#endif
+	.select_hwpart	= mmc_select_hwpart,
+};
+
+U_BOOT_DRIVER(mmc_blk) = {
+	.name		= "mmc_blk",
+	.id		= UCLASS_BLK,
+	.ops		= &mmc_blk_ops,
+};
 #endif /* CONFIG_BLK */
 
 U_BOOT_DRIVER(mmc) = {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a27fcb4..9ca60f7b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -585,27 +585,7 @@ int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 	return ret;
 }
 
-#ifdef CONFIG_BLK
-static int mmc_select_hwpart(struct udevice *bdev, int hwpart)
-{
-	struct udevice *mmc_dev = dev_get_parent(bdev);
-	struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
-	struct blk_desc *desc = dev_get_uclass_platdata(bdev);
-	int ret;
-
-	if (desc->hwpart == hwpart)
-		return 0;
-
-	if (mmc->part_config == MMCPART_NOAVAILABLE)
-		return -EMEDIUMTYPE;
-
-	ret = mmc_switch_part(mmc, hwpart);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-#else
+#ifndef CONFIG_BLK
 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
 {
 	struct mmc *mmc = find_mmc_device(desc->devnum);
@@ -1531,52 +1511,7 @@ static int mmc_send_if_cond(struct mmc *mmc)
 	return 0;
 }
 
-#ifdef CONFIG_BLK
-int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
-{
-	struct blk_desc *bdesc;
-	struct udevice *bdev;
-	int ret;
-
-	ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512,
-				 0, &bdev);
-	if (ret) {
-		debug("Cannot create block device\n");
-		return ret;
-	}
-	bdesc = dev_get_uclass_platdata(bdev);
-	mmc->cfg = cfg;
-	mmc->priv = dev;
-
-	/* the following chunk was from mmc_register() */
-
-	/* Setup dsr related values */
-	mmc->dsr_imp = 0;
-	mmc->dsr = 0xffffffff;
-	/* Setup the universal parts of the block interface just once */
-	bdesc->removable = 1;
-
-	/* setup initial part type */
-	bdesc->part_type = cfg->part_type;
-	mmc->dev = dev;
-
-	return 0;
-}
-
-int mmc_unbind(struct udevice *dev)
-{
-	struct udevice *bdev;
-
-	device_find_first_child(dev, &bdev);
-	if (bdev) {
-		device_remove(bdev);
-		device_unbind(bdev);
-	}
-
-	return 0;
-}
-
-#else
+#ifndef CONFIG_BLK
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
 	struct blk_desc *bdesc;
@@ -1620,9 +1555,7 @@ void mmc_destroy(struct mmc *mmc)
 	/* only freeing memory for now */
 	free(mmc);
 }
-#endif
 
-#ifndef CONFIG_BLK
 static int mmc_get_dev(int dev, struct blk_desc **descp)
 {
 	struct mmc *mmc = find_mmc_device(dev);
@@ -1962,19 +1895,7 @@ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
 }
 #endif
 
-#ifdef CONFIG_BLK
-static const struct blk_ops mmc_blk_ops = {
-	.read	= mmc_bread,
-	.write	= mmc_bwrite,
-	.select_hwpart	= mmc_select_hwpart,
-};
-
-U_BOOT_DRIVER(mmc_blk) = {
-	.name		= "mmc_blk",
-	.id		= UCLASS_BLK,
-	.ops		= &mmc_blk_ops,
-};
-#else
+#ifndef CONFIG_BLK
 U_BOOT_LEGACY_BLK(mmc) = {
 	.if_typename	= "mmc",
 	.if_type	= IF_TYPE_MMC,
-- 
cgit v0.10.2


From 5aed4cbba07526d1a575f07f45b4d10d8cdca11e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:17 -0600
Subject: dm: mmc: Move non-CONFIG_BLK code into mmc_legacy.c

Rather than having #ifdef in mmc.c, move this code into the legacy file.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 9ca60f7b..8085dbb 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -585,29 +585,6 @@ int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 	return ret;
 }
 
-#ifndef CONFIG_BLK
-static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
-{
-	struct mmc *mmc = find_mmc_device(desc->devnum);
-	int ret;
-
-	if (!mmc)
-		return -ENODEV;
-
-	if (mmc->block_dev.hwpart == hwpart)
-		return 0;
-
-	if (mmc->part_config == MMCPART_NOAVAILABLE)
-		return -EMEDIUMTYPE;
-
-	ret = mmc_switch_part(mmc, hwpart);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-#endif
-
 int mmc_hwpart_config(struct mmc *mmc,
 		      const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode)
@@ -1511,68 +1488,6 @@ static int mmc_send_if_cond(struct mmc *mmc)
 	return 0;
 }
 
-#ifndef CONFIG_BLK
-struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
-{
-	struct blk_desc *bdesc;
-	struct mmc *mmc;
-
-	/* quick validation */
-	if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
-			cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
-		return NULL;
-
-	mmc = calloc(1, sizeof(*mmc));
-	if (mmc == NULL)
-		return NULL;
-
-	mmc->cfg = cfg;
-	mmc->priv = priv;
-
-	/* the following chunk was mmc_register() */
-
-	/* Setup dsr related values */
-	mmc->dsr_imp = 0;
-	mmc->dsr = 0xffffffff;
-	/* Setup the universal parts of the block interface just once */
-	bdesc = mmc_get_blk_desc(mmc);
-	bdesc->if_type = IF_TYPE_MMC;
-	bdesc->removable = 1;
-	bdesc->devnum = mmc_get_next_devnum();
-	bdesc->block_read = mmc_bread;
-	bdesc->block_write = mmc_bwrite;
-	bdesc->block_erase = mmc_berase;
-
-	/* setup initial part type */
-	bdesc->part_type = mmc->cfg->part_type;
-	mmc_list_add(mmc);
-
-	return mmc;
-}
-
-void mmc_destroy(struct mmc *mmc)
-{
-	/* only freeing memory for now */
-	free(mmc);
-}
-
-static int mmc_get_dev(int dev, struct blk_desc **descp)
-{
-	struct mmc *mmc = find_mmc_device(dev);
-	int ret;
-
-	if (!mmc)
-		return -ENODEV;
-	ret = mmc_init(mmc);
-	if (ret)
-		return ret;
-
-	*descp = &mmc->block_dev;
-
-	return 0;
-}
-#endif
-
 /* board-specific MMC power initializations. */
 __weak void board_mmc_power_init(void)
 {
@@ -1894,13 +1809,3 @@ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
 			  enable);
 }
 #endif
-
-#ifndef CONFIG_BLK
-U_BOOT_LEGACY_BLK(mmc) = {
-	.if_typename	= "mmc",
-	.if_type	= IF_TYPE_MMC,
-	.max_devs	= -1,
-	.get_dev	= mmc_get_dev,
-	.select_hwpart	= mmc_select_hwpartp,
-};
-#endif
diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c
index 3ec649f..040728b 100644
--- a/drivers/mmc/mmc_legacy.c
+++ b/drivers/mmc/mmc_legacy.c
@@ -6,7 +6,9 @@
  */
 
 #include <common.h>
+#include <malloc.h>
 #include <mmc.h>
+#include "mmc_private.h"
 
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
@@ -106,3 +108,92 @@ void print_mmc_devices(char separator)
 #else
 void print_mmc_devices(char separator) { }
 #endif
+
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
+{
+	struct blk_desc *bdesc;
+	struct mmc *mmc;
+
+	/* quick validation */
+	if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
+	    cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
+		return NULL;
+
+	mmc = calloc(1, sizeof(*mmc));
+	if (mmc == NULL)
+		return NULL;
+
+	mmc->cfg = cfg;
+	mmc->priv = priv;
+
+	/* the following chunk was mmc_register() */
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = 0xffffffff;
+	/* Setup the universal parts of the block interface just once */
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->if_type = IF_TYPE_MMC;
+	bdesc->removable = 1;
+	bdesc->devnum = mmc_get_next_devnum();
+	bdesc->block_read = mmc_bread;
+	bdesc->block_write = mmc_bwrite;
+	bdesc->block_erase = mmc_berase;
+
+	/* setup initial part type */
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc_list_add(mmc);
+
+	return mmc;
+}
+
+void mmc_destroy(struct mmc *mmc)
+{
+	/* only freeing memory for now */
+	free(mmc);
+}
+
+static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
+{
+	struct mmc *mmc = find_mmc_device(desc->devnum);
+	int ret;
+
+	if (!mmc)
+		return -ENODEV;
+
+	if (mmc->block_dev.hwpart == hwpart)
+		return 0;
+
+	if (mmc->part_config == MMCPART_NOAVAILABLE)
+		return -EMEDIUMTYPE;
+
+	ret = mmc_switch_part(mmc, hwpart);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int mmc_get_dev(int dev, struct blk_desc **descp)
+{
+	struct mmc *mmc = find_mmc_device(dev);
+	int ret;
+
+	if (!mmc)
+		return -ENODEV;
+	ret = mmc_init(mmc);
+	if (ret)
+		return ret;
+
+	*descp = &mmc->block_dev;
+
+	return 0;
+}
+
+U_BOOT_LEGACY_BLK(mmc) = {
+	.if_typename	= "mmc",
+	.if_type	= IF_TYPE_MMC,
+	.max_devs	= -1,
+	.get_dev	= mmc_get_dev,
+	.select_hwpart	= mmc_select_hwpartp,
+};
-- 
cgit v0.10.2


From c40704f4b13a19a95aa13965c0f1f6a93b5574c0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:18 -0600
Subject: mmc: Move MMC boot code into its own file

Rather than having an #ifdef in the main mmc.c file, control this feature
from the Makefile by moving the code into its own file.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 3da4817..b44a12e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,6 +25,9 @@ obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
 obj-$(CONFIG_GENERIC_MMC) += mmc.o
+ifdef CONFIG_SUPPORT_EMMC_BOOT
+obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o
+endif
 obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8085dbb..c850285 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -463,8 +463,7 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 	return err;
 }
 
-
-static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
+int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 {
 	struct mmc_cmd cmd;
 	int timeout = 1000;
@@ -1686,126 +1685,3 @@ int mmc_initialize(bd_t *bis)
 	mmc_do_preinit();
 	return 0;
 }
-
-#ifdef CONFIG_SUPPORT_EMMC_BOOT
-/*
- * This function changes the size of boot partition and the size of rpmb
- * partition present on EMMC devices.
- *
- * Input Parameters:
- * struct *mmc: pointer for the mmc device strcuture
- * bootsize: size of boot partition
- * rpmbsize: size of rpmb partition
- *
- * Returns 0 on success.
- */
-
-int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
-				unsigned long rpmbsize)
-{
-	int err;
-	struct mmc_cmd cmd;
-
-	/* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
-	cmd.cmdidx = MMC_CMD_RES_MAN;
-	cmd.resp_type = MMC_RSP_R1b;
-	cmd.cmdarg = MMC_CMD62_ARG1;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err) {
-		debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
-		return err;
-	}
-
-	/* Boot partition changing mode */
-	cmd.cmdidx = MMC_CMD_RES_MAN;
-	cmd.resp_type = MMC_RSP_R1b;
-	cmd.cmdarg = MMC_CMD62_ARG2;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err) {
-		debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
-		return err;
-	}
-	/* boot partition size is multiple of 128KB */
-	bootsize = (bootsize * 1024) / 128;
-
-	/* Arg: boot partition size */
-	cmd.cmdidx = MMC_CMD_RES_MAN;
-	cmd.resp_type = MMC_RSP_R1b;
-	cmd.cmdarg = bootsize;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err) {
-		debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
-		return err;
-	}
-	/* RPMB partition size is multiple of 128KB */
-	rpmbsize = (rpmbsize * 1024) / 128;
-	/* Arg: RPMB partition size */
-	cmd.cmdidx = MMC_CMD_RES_MAN;
-	cmd.resp_type = MMC_RSP_R1b;
-	cmd.cmdarg = rpmbsize;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err) {
-		debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
-		return err;
-	}
-	return 0;
-}
-
-/*
- * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
- * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
- * and BOOT_MODE.
- *
- * Returns 0 on success.
- */
-int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
-{
-	int err;
-
-	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
-			 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
-			 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
-			 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
-
-	if (err)
-		return err;
-	return 0;
-}
-
-/*
- * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
- * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
- * PARTITION_ACCESS.
- *
- * Returns 0 on success.
- */
-int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
-{
-	int err;
-
-	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
-			 EXT_CSD_BOOT_ACK(ack) |
-			 EXT_CSD_BOOT_PART_NUM(part_num) |
-			 EXT_CSD_PARTITION_ACCESS(access));
-
-	if (err)
-		return err;
-	return 0;
-}
-
-/*
- * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
- * for enable.  Note that this is a write-once field for non-zero values.
- *
- * Returns 0 on success.
- */
-int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
-{
-	return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
-			  enable);
-}
-#endif
diff --git a/drivers/mmc/mmc_boot.c b/drivers/mmc/mmc_boot.c
new file mode 100644
index 0000000..756a982
--- /dev/null
+++ b/drivers/mmc/mmc_boot.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Amar <amarendra.xt@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include "mmc_private.h"
+
+/*
+ * This function changes the size of boot partition and the size of rpmb
+ * partition present on EMMC devices.
+ *
+ * Input Parameters:
+ * struct *mmc: pointer for the mmc device strcuture
+ * bootsize: size of boot partition
+ * rpmbsize: size of rpmb partition
+ *
+ * Returns 0 on success.
+ */
+
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+				unsigned long rpmbsize)
+{
+	int err;
+	struct mmc_cmd cmd;
+
+	/* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = MMC_CMD62_ARG1;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
+		return err;
+	}
+
+	/* Boot partition changing mode */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = MMC_CMD62_ARG2;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
+		return err;
+	}
+	/* boot partition size is multiple of 128KB */
+	bootsize = (bootsize * 1024) / 128;
+
+	/* Arg: boot partition size */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = bootsize;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
+		return err;
+	}
+	/* RPMB partition size is multiple of 128KB */
+	rpmbsize = (rpmbsize * 1024) / 128;
+	/* Arg: RPMB partition size */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = rpmbsize;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
+		return err;
+	}
+	return 0;
+}
+
+/*
+ * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
+ * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
+ * and BOOT_MODE.
+ *
+ * Returns 0 on success.
+ */
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
+{
+	int err;
+
+	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
+			 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
+			 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
+			 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
+
+	if (err)
+		return err;
+	return 0;
+}
+
+/*
+ * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
+ * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
+ * PARTITION_ACCESS.
+ *
+ * Returns 0 on success.
+ */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+	int err;
+
+	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+			 EXT_CSD_BOOT_ACK(ack) |
+			 EXT_CSD_BOOT_PART_NUM(part_num) |
+			 EXT_CSD_PARTITION_ACCESS(access));
+
+	if (err)
+		return err;
+	return 0;
+}
+
+/*
+ * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
+ * for enable.  Note that this is a write-once field for non-zero values.
+ *
+ * Returns 0 on success.
+ */
+int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
+{
+	return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
+			  enable);
+}
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index cfc4aca..3d189ba 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -106,4 +106,15 @@ void mmc_list_add(struct mmc *mmc);
  */
 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 
+/**
+ * mmc_switch() - Issue and MMC switch mode command
+ *
+ * @mmc:	MMC device
+ * @set:	Unused
+ * @index:	Cmdarg index
+ * @value:	Cmdarg value
+ * @return 0 if OK, -ve on error
+ */
+int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value);
+
 #endif /* _MMC_PRIVATE_H_ */
-- 
cgit v0.10.2


From 6775e013c9b68d110e4d6f0489a8b79876081590 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:19 -0600
Subject: dm: mmc: rockchip: Support only CONFIG_BLK

Since all Rockchip boards use CONFIG_BLK, we can remove this old code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index d41d60c..7bd850a 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -66,9 +66,7 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 
 static int rockchip_dwmmc_probe(struct udevice *dev)
 {
-#ifdef CONFIG_BLK
 	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
-#endif
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
@@ -106,16 +104,9 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 			return ret;
 	}
 #endif
-#ifdef CONFIG_BLK
 	dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
 			minmax[1], minmax[0]);
 	host->mmc = &plat->mmc;
-#else
-	ret = add_dwmci(host, minmax[1], minmax[0]);
-	if (ret)
-		return ret;
-
-#endif
 	host->mmc->priv = &priv->host;
 	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
@@ -125,14 +116,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 
 static int rockchip_dwmmc_bind(struct udevice *dev)
 {
-#ifdef CONFIG_BLK
 	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
 	int ret;
 
 	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 	if (ret)
 		return ret;
-#endif
 
 	return 0;
 }
-- 
cgit v0.10.2


From c0c76ebae3d088867e38fb7a61e290ed9676e516 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:20 -0600
Subject: mmc: Move tracing code into separate functions

Move this code into separate functions so that it can be used from the uclass
also. Add static inline versions for when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c850285..afb11b9 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -47,17 +47,18 @@ __weak int board_mmc_getcd(struct mmc *mmc)
 	return -1;
 }
 
-int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+#ifdef CONFIG_MMC_TRACE
+void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
 {
-	int ret;
+	printf("CMD_SEND:%d\n", cmd->cmdidx);
+	printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
+}
 
-#ifdef CONFIG_MMC_TRACE
+void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
+{
 	int i;
 	u8 *ptr;
 
-	printf("CMD_SEND:%d\n", cmd->cmdidx);
-	printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
-	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
 	if (ret) {
 		printf("\t\tRET\t\t\t %d\n", ret);
 	} else {
@@ -103,9 +104,25 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			break;
 		}
 	}
-#else
-	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
+}
+
+void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
+{
+	int status;
+
+	status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
+	printf("CURR STATE:%d\n", status);
+}
 #endif
+
+int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	int ret;
+
+	mmmc_trace_before_send(mmc, cmd);
+	ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
+	mmmc_trace_after_send(mmc, cmd, ret);
+
 	return ret;
 }
 
@@ -113,9 +130,6 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 {
 	struct mmc_cmd cmd;
 	int err, retries = 5;
-#ifdef CONFIG_MMC_TRACE
-	int status;
-#endif
 
 	cmd.cmdidx = MMC_CMD_SEND_STATUS;
 	cmd.resp_type = MMC_RSP_R1;
@@ -145,10 +159,7 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 		udelay(1000);
 	}
 
-#ifdef CONFIG_MMC_TRACE
-	status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
-	printf("CURR STATE:%d\n", status);
-#endif
+	mmc_trace_state(mmc, &cmd);
 	if (timeout <= 0) {
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("Timeout waiting card ready\n");
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 3d189ba..49ec022 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -73,6 +73,25 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
 
 #endif /* CONFIG_SPL_BUILD */
 
+#ifdef CONFIG_MMC_TRACE
+void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd);
+void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret);
+void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd);
+#else
+static inline void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
+{
+}
+
+static inline void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd,
+					 int ret)
+{
+}
+
+static inline void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
+{
+}
+#endif
+
 /**
  * mmc_get_next_devnum() - Get the next available MMC device number
  *
-- 
cgit v0.10.2


From 7d1c8d99fd12ad1e879533075b87c908462c1fd3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:21 -0600
Subject: rockchip: Disable CONFIG_SDHCI

This option is not actually needed for rockchip boards. Drop it, since it
will not support driver-model MMC operation support.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 1bdcf9d..ae4b101 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -45,7 +45,6 @@
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_SDHCI
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 9d50d83..8adc26f 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -51,7 +51,6 @@
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-#define CONFIG_SDHCI
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
-- 
cgit v0.10.2


From 8ca51e51c182699ebc64b10660db3e03cb43cb54 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:22 -0600
Subject: dm: mmc: Add a way to use driver model for MMC operations

The driver model conversion for MMC has moved in small steps. The first step
was to have an MMC device (CONFIG_DM_MMC). The second was to use a child
block device (CONFIG_BLK). The final one is to use driver model for MMC
operations (CONFIG_DM_MMC_OP). Add support for this.

The immediate priority is to make all boards that use DM_MMC also use those
other two options. This will allow them to be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c80efc3..b9662f9 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -16,6 +16,15 @@ config DM_MMC
 	  appear as block devices in U-Boot and can support filesystems such
 	  as EXT4 and FAT.
 
+config DM_MMC_OPS
+	bool "Support MMC controller operations using Driver Model"
+	depends on DM_MMC
+	help
+	  Driver model provides a means of supporting device operations. This
+	  option moves MMC operations under the control of driver model. The
+	  option will be removed as soon as all DM_MMC drivers use it, as it
+	  will the only supported behaviour.
+
 config MSM_SDHCI
 	bool "Qualcomm SDHCI controller"
 	depends on DM_MMC
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 530276a..38ced41 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -13,6 +13,72 @@
 #include <dm/root.h>
 #include "mmc_private.h"
 
+#ifdef CONFIG_DM_MMC_OPS
+int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+		    struct mmc_data *data)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+	struct dm_mmc_ops *ops = mmc_get_ops(dev);
+	int ret;
+
+	mmmc_trace_before_send(mmc, cmd);
+	if (ops->send_cmd)
+		ret = ops->send_cmd(dev, cmd, data);
+	else
+		ret = -ENOSYS;
+	mmmc_trace_after_send(mmc, cmd, ret);
+
+	return ret;
+}
+
+int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	return dm_mmc_send_cmd(mmc->dev, cmd, data);
+}
+
+int dm_mmc_set_ios(struct udevice *dev)
+{
+	struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+	if (!ops->set_ios)
+		return -ENOSYS;
+	return ops->set_ios(dev);
+}
+
+int mmc_set_ios(struct mmc *mmc)
+{
+	return dm_mmc_set_ios(mmc->dev);
+}
+
+int dm_mmc_get_wp(struct udevice *dev)
+{
+	struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+	if (!ops->get_wp)
+		return -ENOSYS;
+	return ops->get_wp(dev);
+}
+
+int mmc_getwp(struct mmc *mmc)
+{
+	return dm_mmc_get_wp(mmc->dev);
+}
+
+int dm_mmc_get_cd(struct udevice *dev)
+{
+	struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+	if (!ops->get_cd)
+		return -ENOSYS;
+	return ops->get_cd(dev);
+}
+
+int mmc_getcd(struct mmc *mmc)
+{
+	return dm_mmc_get_cd(mmc->dev);
+}
+#endif
+
 struct mmc *mmc_get_mmc_dev(struct udevice *dev)
 {
 	struct mmc_uclass_priv *upriv;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index afb11b9..f8e5f7a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,6 +21,7 @@
 #include <div64.h>
 #include "mmc_private.h"
 
+#ifndef CONFIG_DM_MMC_OPS
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
@@ -46,6 +47,7 @@ __weak int board_mmc_getcd(struct mmc *mmc)
 {
 	return -1;
 }
+#endif
 
 #ifdef CONFIG_MMC_TRACE
 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
@@ -115,6 +117,7 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
 }
 #endif
 
+#ifndef CONFIG_DM_MMC_OPS
 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
 	int ret;
@@ -125,6 +128,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	return ret;
 }
+#endif
 
 int mmc_send_status(struct mmc *mmc, int timeout)
 {
@@ -789,6 +793,7 @@ int mmc_hwpart_config(struct mmc *mmc,
 	return 0;
 }
 
+#ifndef CONFIG_DM_MMC_OPS
 int mmc_getcd(struct mmc *mmc)
 {
 	int cd;
@@ -804,6 +809,7 @@ int mmc_getcd(struct mmc *mmc)
 
 	return cd;
 }
+#endif
 
 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
 {
@@ -967,11 +973,13 @@ static const u8 multipliers[] = {
 	80,
 };
 
+#ifndef CONFIG_DM_MMC_OPS
 static void mmc_set_ios(struct mmc *mmc)
 {
 	if (mmc->cfg->ops->set_ios)
 		mmc->cfg->ops->set_ios(mmc);
 }
+#endif
 
 void mmc_set_clock(struct mmc *mmc, uint clock)
 {
@@ -1505,10 +1513,15 @@ __weak void board_mmc_power_init(void)
 
 int mmc_start_init(struct mmc *mmc)
 {
+	bool no_card;
 	int err;
 
 	/* we pretend there's no card when init is NULL */
-	if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
+	no_card = mmc_getcd(mmc) == 0;
+#ifndef CONFIG_DM_MMC_OPS
+	no_card = no_card || (mmc->cfg->ops->init == NULL);
+#endif
+	if (no_card) {
 		mmc->has_init = 0;
 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: no card present\n");
@@ -1524,12 +1537,14 @@ int mmc_start_init(struct mmc *mmc)
 #endif
 	board_mmc_power_init();
 
+#ifdef CONFIG_DM_MMC_OPS
+	/* The device has already been probed ready for use */
+#else
 	/* made sure it's not NULL earlier */
 	err = mmc->cfg->ops->init(mmc);
-
 	if (err)
 		return err;
-
+#endif
 	mmc->ddr_mode = 0;
 	mmc_set_bus_width(mmc, 1);
 	mmc_set_clock(mmc, 1);
diff --git a/include/mmc.h b/include/mmc.h
index f383925..8f309f1 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -323,6 +323,58 @@ struct mmc_data {
 /* forward decl. */
 struct mmc;
 
+#ifdef CONFIG_DM_MMC_OPS
+struct dm_mmc_ops {
+	/**
+	 * send_cmd() - Send a command to the MMC device
+	 *
+	 * @dev:	Device to receive the command
+	 * @cmd:	Command to send
+	 * @data:	Additional data to send/receive
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
+			struct mmc_data *data);
+
+	/**
+	 * set_ios() - Set the I/O speed/width for an MMC device
+	 *
+	 * @dev:	Device to update
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_ios)(struct udevice *dev);
+
+	/**
+	 * get_cd() - See whether a card is present
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if not present, 1 if present, -ve on error
+	 */
+	int (*get_cd)(struct udevice *dev);
+
+	/**
+	 * get_wp() - See whether a card has write-protect enabled
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if write-enabled, 1 if write-protected, -ve on error
+	 */
+	int (*get_wp)(struct udevice *dev);
+};
+
+#define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
+
+int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+		    struct mmc_data *data);
+int dm_mmc_set_ios(struct udevice *dev);
+int dm_mmc_get_cd(struct udevice *dev);
+int dm_mmc_get_wp(struct udevice *dev);
+
+/* Transition functions for compatibility */
+int mmc_set_ios(struct mmc *mmc);
+int mmc_getcd(struct mmc *mmc);
+int mmc_getwp(struct mmc *mmc);
+
+#else
 struct mmc_ops {
 	int (*send_cmd)(struct mmc *mmc,
 			struct mmc_cmd *cmd, struct mmc_data *data);
@@ -331,10 +383,13 @@ struct mmc_ops {
 	int (*getcd)(struct mmc *mmc);
 	int (*getwp)(struct mmc *mmc);
 };
+#endif
 
 struct mmc_config {
 	const char *name;
+#ifndef CONFIG_DM_MMC_OPS
 	const struct mmc_ops *ops;
+#endif
 	uint host_caps;
 	uint voltages;
 	uint f_min;
@@ -343,7 +398,12 @@ struct mmc_config {
 	unsigned char part_type;
 };
 
-/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
+/*
+ * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
+ * with mmc_get_mmc_dev().
+ *
+ * TODO struct mmc should be in mmc_private but it's hard to fix right now
+ */
 struct mmc {
 #ifndef CONFIG_BLK
 	struct list_head link;
@@ -446,10 +506,14 @@ void print_mmc_devices(char separator);
 int get_mmc_num(void);
 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode);
+
+#ifndef CONFIG_DM_MMC_OPS
 int mmc_getcd(struct mmc *mmc);
 int board_mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
 int board_mmc_getwp(struct mmc *mmc);
+#endif
+
 int mmc_set_dsr(struct mmc *mmc, u16 val);
 /* Function to change the size of boot partition and rpmb partitions */
 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
-- 
cgit v0.10.2


From 691272fe5236b1b5ac02c7c1a1fb8fe85fd78d97 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:23 -0600
Subject: dm: mmc: dwmmc: Support CONFIG_DM_MMC_OPS

Add support to dwmmc for using driver model for MMC operations.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index af6e04a..2cf7bae 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -181,9 +181,16 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host,
 	return mode;
 }
 
+#ifdef CONFIG_DM_MMC_OPS
+int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+		   struct mmc_data *data)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		struct mmc_data *data)
 {
+#endif
 	struct dwmci_host *host = mmc->priv;
 	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
@@ -373,8 +380,14 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 	return 0;
 }
 
+#ifdef CONFIG_DM_MMC_OPS
+int dwmci_set_ios(struct udevice *dev)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
 static void dwmci_set_ios(struct mmc *mmc)
 {
+#endif
 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 	u32 ctype, regs;
 
@@ -405,6 +418,9 @@ static void dwmci_set_ios(struct mmc *mmc)
 
 	if (host->clksel)
 		host->clksel(host);
+#ifdef CONFIG_DM_MMC_OPS
+	return 0;
+#endif
 }
 
 static int dwmci_init(struct mmc *mmc)
@@ -448,17 +464,34 @@ static int dwmci_init(struct mmc *mmc)
 	return 0;
 }
 
+#ifdef CONFIG_DM_MMC_OPS
+int dwmci_probe(struct udevice *dev)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+	return dwmci_init(mmc);
+}
+
+const struct dm_mmc_ops dm_dwmci_ops = {
+	.send_cmd	= dwmci_send_cmd,
+	.set_ios	= dwmci_set_ios,
+};
+
+#else
 static const struct mmc_ops dwmci_ops = {
 	.send_cmd	= dwmci_send_cmd,
 	.set_ios	= dwmci_set_ios,
 	.init		= dwmci_init,
 };
+#endif
 
 void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 		     uint caps, u32 max_clk, u32 min_clk)
 {
 	cfg->name = name;
+#ifndef CONFIG_DM_MMC_OPS
 	cfg->ops = &dwmci_ops;
+#endif
 	cfg->f_min = min_clk;
 	cfg->f_max = max_clk;
 
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 0199def..6aebe96 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -293,4 +293,13 @@ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 #endif /* !CONFIG_BLK */
 
+#ifdef CONFIG_DM_MMC_OPS
+/* Export the operations to drivers */
+int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+		   struct mmc_data *data);
+int dwmci_set_ios(struct udevice *dev);
+int dwmci_probe(struct udevice *dev);
+extern const struct dm_mmc_ops dm_dwmci_ops;
+#endif
+
 #endif	/* __DWMMC_HW_H */
-- 
cgit v0.10.2


From 42b37d8d469bda1ddb1847596628eb03e1229bb4 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:24 -0600
Subject: dm: mmc: rockchip: Enable CONFIG_DM_MMC_OPS for all boards

Enable this option to move rockchip over to use driver model for MMC
operations.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8004c17..585b408 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -850,6 +850,7 @@ config ARCH_ROCKCHIP
 	select DM_GPIO
 	select DM_I2C
 	select DM_MMC
+	select DM_MMC_OPS
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 7bd850a..691a515 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -111,7 +111,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
 
-	return 0;
+	return dwmci_probe(dev);
 }
 
 static int rockchip_dwmmc_bind(struct udevice *dev)
@@ -136,6 +136,7 @@ U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= rockchip_dwmmc_ids,
 	.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+	.ops		= &dm_dwmci_ops,
 	.bind		= rockchip_dwmmc_bind,
 	.probe		= rockchip_dwmmc_probe,
 	.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
-- 
cgit v0.10.2


From 3649a0fa76e5092821127c38d6475b5cf7fd95b3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:25 -0600
Subject: rockchip: Add MAINTAINER files for kylin_rk3036, evb_rk3036

These boards should have maintainer entries. Add them.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/evb_rk3036/evb_rk3036/MAINTAINERS
index e69de29..152d31c 100644
--- a/board/evb_rk3036/evb_rk3036/MAINTAINERS
+++ b/board/evb_rk3036/evb_rk3036/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3036
+M:      huang lin <hl@rock-chips.com>
+S:      Maintained
+F:      board/evb/evb-rk3036
+F:      include/configs/evb-rk3036.h
+F:      configs/evb-rk3036_defconfig
diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS
index e69de29..f8ee834 100644
--- a/board/kylin/kylin_rk3036/MAINTAINERS
+++ b/board/kylin/kylin_rk3036/MAINTAINERS
@@ -0,0 +1,6 @@
+KYLIN-RK3036
+M:      huang lin <hl@rock-chips.com>
+S:      Maintained
+F:      board/kylin/kylin-rk3036
+F:      include/configs/kylin-rk3036.h
+F:      configs/kylin-rk3036_defconfig
-- 
cgit v0.10.2


From 9a46bd3febd405e2d4b894d9ebae2e9ca88b22d6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:26 -0600
Subject: dm: sandbox: Convert to use CONFIG_CMD_MMC_OPS

Update the sandbox MMC emulation to use driver model for MMC operations.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/Kconfig b/arch/Kconfig
index 566f044..c43787c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -63,6 +63,7 @@ config SANDBOX
 	select DM_I2C
 	select DM_SPI
 	select DM_GPIO
+	select DM_MMC
 
 config SH
 	bool "SuperH architecture"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 94253a6..6a1874a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,5 +1,4 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_BLK=y
 CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
@@ -71,6 +70,7 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -101,7 +101,7 @@ CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_SYSRESET=y
-CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_SANDBOX_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c
index 7da059c..5f1333b 100644
--- a/drivers/mmc/sandbox_mmc.c
+++ b/drivers/mmc/sandbox_mmc.c
@@ -25,7 +25,7 @@ struct sandbox_mmc_plat {
  * This emulate an SD card version 2. Single-block reads result in zero data.
  * Multiple-block reads return a test string.
  */
-static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+static int sandbox_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 				struct mmc_data *data)
 {
 	switch (cmd->cmdidx) {
@@ -85,25 +85,20 @@ static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	return 0;
 }
 
-static void sandbox_mmc_set_ios(struct mmc *mmc)
-{
-}
-
-static int sandbox_mmc_init(struct mmc *mmc)
+static int sandbox_mmc_set_ios(struct udevice *dev)
 {
 	return 0;
 }
 
-static int sandbox_mmc_getcd(struct mmc *mmc)
+static int sandbox_mmc_get_cd(struct udevice *dev)
 {
 	return 1;
 }
 
-static const struct mmc_ops sandbox_mmc_ops = {
+static const struct dm_mmc_ops sandbox_mmc_ops = {
 	.send_cmd = sandbox_mmc_send_cmd,
 	.set_ios = sandbox_mmc_set_ios,
-	.init = sandbox_mmc_init,
-	.getcd = sandbox_mmc_getcd,
+	.get_cd = sandbox_mmc_get_cd,
 };
 
 int sandbox_mmc_probe(struct udevice *dev)
@@ -120,7 +115,6 @@ int sandbox_mmc_bind(struct udevice *dev)
 	int ret;
 
 	cfg->name = dev->name;
-	cfg->ops = &sandbox_mmc_ops;
 	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
 	cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 	cfg->f_min = 1000000;
@@ -150,6 +144,7 @@ U_BOOT_DRIVER(mmc_sandbox) = {
 	.name		= "mmc_sandbox",
 	.id		= UCLASS_MMC,
 	.of_match	= sandbox_mmc_ids,
+	.ops		= &sandbox_mmc_ops,
 	.bind		= sandbox_mmc_bind,
 	.unbind		= sandbox_mmc_unbind,
 	.probe		= sandbox_mmc_probe,
-- 
cgit v0.10.2


From 2a809093f0e2b243565abb27fc37b6d881c4157f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:27 -0600
Subject: dm: mmc: sdhci: Refactor configuration setup to support DM

Move the configuration setting into a separate function which can be used by
the driver-model code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 604f18d..8db7ec8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -9,6 +9,7 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <malloc.h>
 #include <mmc.h>
 #include <sdhci.h>
@@ -479,73 +480,83 @@ static const struct mmc_ops sdhci_ops = {
 	.init		= sdhci_init,
 };
 
-int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
+int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+		    uint caps, u32 max_clk, u32 min_clk, uint version,
+		    uint quirks, uint host_caps)
 {
-	unsigned int caps;
-
-	host->cfg.name = host->name;
-	host->cfg.ops = &sdhci_ops;
-
-	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-#ifdef CONFIG_MMC_SDMA
-	if (!(caps & SDHCI_CAN_DO_SDMA)) {
-		printf("%s: Your controller doesn't support SDMA!!\n",
-		       __func__);
-		return -1;
-	}
+	cfg->name = name;
+#ifndef CONFIG_DM_MMC_OPS
+	cfg->ops = &sdhci_ops;
 #endif
-
 	if (max_clk)
-		host->cfg.f_max = max_clk;
+		cfg->f_max = max_clk;
 	else {
-		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
-			host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
-				>> SDHCI_CLOCK_BASE_SHIFT;
+		if (version >= SDHCI_SPEC_300)
+			cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
+				SDHCI_CLOCK_BASE_SHIFT;
 		else
-			host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
-				>> SDHCI_CLOCK_BASE_SHIFT;
-		host->cfg.f_max *= 1000000;
-	}
-	if (host->cfg.f_max == 0) {
-		printf("%s: Hardware doesn't specify base clock frequency\n",
-		       __func__);
-		return -1;
+			cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
+				SDHCI_CLOCK_BASE_SHIFT;
+		cfg->f_max *= 1000000;
 	}
+	if (cfg->f_max == 0)
+		return -EINVAL;
 	if (min_clk)
-		host->cfg.f_min = min_clk;
+		cfg->f_min = min_clk;
 	else {
-		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
-			host->cfg.f_min = host->cfg.f_max /
-				SDHCI_MAX_DIV_SPEC_300;
+		if (version >= SDHCI_SPEC_300)
+			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 		else
-			host->cfg.f_min = host->cfg.f_max /
-				SDHCI_MAX_DIV_SPEC_200;
+			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 	}
-
-	host->cfg.voltages = 0;
+	cfg->voltages = 0;
 	if (caps & SDHCI_CAN_VDD_330)
-		host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 	if (caps & SDHCI_CAN_VDD_300)
-		host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 	if (caps & SDHCI_CAN_VDD_180)
-		host->cfg.voltages |= MMC_VDD_165_195;
+		cfg->voltages |= MMC_VDD_165_195;
 
-	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
-		host->cfg.voltages |= host->voltages;
-
-	host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
-	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+	cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+	if (version >= SDHCI_SPEC_300) {
 		if (caps & SDHCI_CAN_DO_8BIT)
-			host->cfg.host_caps |= MMC_MODE_8BIT;
+			cfg->host_caps |= MMC_MODE_8BIT;
 	}
 
-	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
-		host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
+	if (quirks & SDHCI_QUIRK_NO_HISPD_BIT)
+		cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
+
+	if (host_caps)
+		cfg->host_caps |= host_caps;
 
-	if (host->host_caps)
-		host->cfg.host_caps |= host->host_caps;
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+	return 0;
+}
+
+int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
+{
+	unsigned int caps;
+
+	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+#ifdef CONFIG_MMC_SDMA
+	if (!(caps & SDHCI_CAN_DO_SDMA)) {
+		printf("%s: Your controller doesn't support SDMA!!\n",
+		       __func__);
+		return -1;
+	}
+#endif
+
+	if (sdhci_setup_cfg(&host->cfg, host->name, host->bus_width, caps,
+			    max_clk, min_clk, SDHCI_GET_VERSION(host),
+			    host->quirks, host->host_caps)) {
+		printf("%s: Hardware doesn't specify base clock frequency\n",
+		       __func__);
+		return -EINVAL;
+	}
+
+	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
+		host->cfg.voltages |= host->voltages;
 
 	sdhci_reset(host, SDHCI_RESET_ALL);
 
-- 
cgit v0.10.2


From ef1e4eda6b4ef2077a943b638b33f95d715062ae Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:28 -0600
Subject: dm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS

Add support for using driver model for block devices and MMC operations in
this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 8db7ec8..de8d8ea 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -130,9 +130,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
 #define SDHCI_READ_STATUS_TIMEOUT		1000
 
+#ifdef CONFIG_DM_MMC_OPS
+static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
+			      struct mmc_data *data)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+#else
 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
-		       struct mmc_data *data)
+			      struct mmc_data *data)
 {
+#endif
 	struct sdhci_host *host = mmc->priv;
 	unsigned int stat = 0;
 	int ret = 0;
@@ -390,8 +398,14 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 }
 
+#ifdef CONFIG_DM_MMC_OPS
+static int sdhci_set_ios(struct udevice *dev)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
 static void sdhci_set_ios(struct mmc *mmc)
 {
+#endif
 	u32 ctrl;
 	struct sdhci_host *host = mmc->priv;
 
@@ -427,6 +441,9 @@ static void sdhci_set_ios(struct mmc *mmc)
 		ctrl &= ~SDHCI_CTRL_HISPD;
 
 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+#ifdef CONFIG_DM_MMC_OPS
+	return 0;
+#endif
 }
 
 static int sdhci_init(struct mmc *mmc)
@@ -473,12 +490,25 @@ static int sdhci_init(struct mmc *mmc)
 	return 0;
 }
 
+#ifdef CONFIG_DM_MMC_OPS
+int sdhci_probe(struct udevice *dev)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+	return sdhci_init(mmc);
+}
 
+const struct dm_mmc_ops sdhci_ops = {
+	.send_cmd	= sdhci_send_command,
+	.set_ios	= sdhci_set_ios,
+};
+#else
 static const struct mmc_ops sdhci_ops = {
 	.send_cmd	= sdhci_send_command,
 	.set_ios	= sdhci_set_ios,
 	.init		= sdhci_init,
 };
+#endif
 
 int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 		    uint caps, u32 max_clk, u32 min_clk, uint version,
@@ -529,11 +559,18 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 	if (host_caps)
 		cfg->host_caps |= host_caps;
 
+
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 	return 0;
 }
 
+#ifdef CONFIG_BLK
+int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+	return mmc_bind(dev, mmc, cfg);
+}
+#else
 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 {
 	unsigned int caps;
@@ -568,3 +605,4 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 
 	return 0;
 }
+#endif
diff --git a/include/sdhci.h b/include/sdhci.h
index e0f6667..c4d3b55 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -338,5 +338,85 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 }
 #endif
 
+#ifdef CONFIG_BLK
+/**
+ * sdhci_setup_cfg() - Set up the configuration for DWMMC
+ *
+ * This is used to set up an SDHCI device when you are using CONFIG_BLK.
+ *
+ * This should be called from your MMC driver's probe() method once you have
+ * the information required.
+ *
+ * Generally your driver will have a platform data structure which holds both
+ * the configuration (struct mmc_config) and the MMC device info (struct mmc).
+ * For example:
+ *
+ * struct msm_sdhc_plat {
+ *	struct mmc_config cfg;
+ *	struct mmc mmc;
+ * };
+ *
+ * ...
+ *
+ * Inside U_BOOT_DRIVER():
+ *	.platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
+ *
+ * To access platform data:
+ *	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+ *
+ * See msm_sdhci.c for an example.
+ *
+ * @cfg:	Configuration structure to fill in (generally &plat->mmc)
+ * @name:	Device name (normally dev->name)
+ * @buswidth:	Bus width (in bits, such as 4 or 8)
+ * @caps:	Host capabilities (MMC_MODE_...)
+ * @max_clk:	Maximum supported clock speed in HZ (0 for default)
+ * @min_clk:	Minimum supported clock speed in HZ (0 for default)
+ * @version:	Host controller version (generally read from the
+ *		SDHCI_HOST_VERSION register)
+ * @quirks:	Quick flags (SDHCI_QUIRK_...)
+ * @host_caps:	Additional host capabilities (0 if none)
+ */
+int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+		    uint caps, u32 max_clk, u32 min_clk, uint version,
+		    uint quirks, uint host_caps);
+
+/**
+ * sdhci_bind() - Set up a new MMC block device
+ *
+ * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
+ * It should be called from your driver's bind() method.
+ *
+ * See msm_sdhci.c for an example.
+ *
+ * @dev:	Device to set up
+ * @mmc:	Pointer to mmc structure (normally &plat->mmc)
+ * @cfg:	Empty configuration structure (generally &plat->cfg). This is
+ *		normally all zeroes at this point. The only purpose of passing
+ *		this in is to set mmc->cfg to it.
+ * @return 0 if OK, -ve if the block device could not be created
+ */
+int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+#else
+
+/**
+ * add_sdhci() - Add a new SDHCI interface
+ *
+ * This is used when you are not using CONFIG_BLK. Convert your driver over!
+ *
+ * @host:	SDHCI host structure
+ * @max_clk:	Maximum supported clock speed in HZ (0 for default)
+ * @min_clk:	Minimum supported clock speed in HZ (0 for default)
+ * @return 0 if OK, -ve on error
+ */
 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
+#endif /* !CONFIG_BLK */
+
+#ifdef CONFIG_DM_MMC_OPS
+/* Export the operations to drivers */
+int sdhci_probe(struct udevice *dev);
+extern const struct dm_mmc_ops sdhci_ops;
+#else
+#endif
+
 #endif /* __SDHCI_HW_H */
-- 
cgit v0.10.2


From 12293f6d367e0832dfa08e3a74aad32671fcc3a3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:29 -0600
Subject: dm: mmc: msm_sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPS

Add support for using driver model for block devices and MMC operations in
this driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 96dcdbe..61d214a 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -36,6 +36,11 @@
 /* Non standard (?) SDHCI register */
 #define SDHCI_VENDOR_SPEC_CAPABILITIES0  0x11c
 
+struct msm_sdhc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
 struct msm_sdhc {
 	struct sdhci_host host;
 	void *base;
@@ -81,9 +86,14 @@ static int msm_sdc_clk_init(struct udevice *dev)
 
 static int msm_sdc_probe(struct udevice *dev)
 {
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+#ifdef CONFIG_BLK
+	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+#endif
 	struct msm_sdhc *prv = dev_get_priv(dev);
 	struct sdhci_host *host = &prv->host;
 	u32 core_version, core_minor, core_major;
+	u32 caps;
 	int ret;
 
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
@@ -127,7 +137,7 @@ static int msm_sdc_probe(struct udevice *dev)
 	 * controller versions and must be explicitly enabled.
 	 */
 	if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
-		u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
+		caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
 		caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
 		writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
 	}
@@ -135,13 +145,26 @@ static int msm_sdc_probe(struct udevice *dev)
 	/* Set host controller version */
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
+#ifdef CONFIG_BLK
+	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+	ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
+			      caps, 0, 0, host->version, host->quirks, 0);
+	host->mmc = &plat->mmc;
+#else
 	/* automatically detect max and min speed */
-	ret =  add_sdhci(host, 0, 0);
+	ret = add_sdhci(host, 0, 0);
+#endif
 	if (ret)
 		return ret;
+	host->mmc->priv = &prv->host;
 	host->mmc->dev = dev;
+	upriv->mmc = host->mmc;
 
+#ifdef CONFIG_DM_MMC_OPS
+	return sdhci_probe(dev);
+#else
 	return 0;
+#endif
 }
 
 static int msm_sdc_remove(struct udevice *dev)
@@ -176,6 +199,20 @@ static int msm_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
+static int msm_sdc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
 static const struct udevice_id msm_mmc_ids[] = {
 	{ .compatible = "qcom,sdhci-msm-v4" },
 	{ }
@@ -186,7 +223,12 @@ U_BOOT_DRIVER(msm_sdc_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= msm_mmc_ids,
 	.ofdata_to_platdata = msm_ofdata_to_platdata,
+#ifdef CONFIG_DM_MMC_OPS
+	.ops		= &sdhci_ops,
+#endif
+	.bind		= msm_sdc_bind,
 	.probe		= msm_sdc_probe,
 	.remove		= msm_sdc_remove,
 	.priv_auto_alloc_size = sizeof(struct msm_sdhc),
+	.platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
 };
-- 
cgit v0.10.2


From 91cbc3f568a49990c5f468453e035166ad10b5d0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:30 -0600
Subject: dm: mmc: Move dragonboard410c to use CONFIG_BLK and CONFIG_DM_MMC_OPS

Update this board to use driver model for block devices and MMC operations.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 37c5ea77..ad2e8b8 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -18,6 +18,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_MSM_GPIO=y
 CONFIG_PM8916_GPIO=y
@@ -25,6 +26,7 @@ CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
 CONFIG_MSM_SDHCI=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PM8916=y
-- 
cgit v0.10.2


From 4b00bdb7a471fc4414c3957726c3cf13c2ca3445 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:31 -0600
Subject: dm: mmc: msmsdhic: Drop old MMC code

Now that we have fully moved to driver model, drop the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index b9662f9..79cf18f 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -27,7 +27,7 @@ config DM_MMC_OPS
 
 config MSM_SDHCI
 	bool "Qualcomm SDHCI controller"
-	depends on DM_MMC
+	depends on DM_MMC && BLK && DM_MMC_OPS
 	help
 	  Enables support for SDHCI 2.0 controller present on some Qualcomm
           Snapdragon devices. This device is compatible with eMMC v4.5 and
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 61d214a..70a8d96 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -87,9 +87,7 @@ static int msm_sdc_clk_init(struct udevice *dev)
 static int msm_sdc_probe(struct udevice *dev)
 {
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-#ifdef CONFIG_BLK
 	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
-#endif
 	struct msm_sdhc *prv = dev_get_priv(dev);
 	struct sdhci_host *host = &prv->host;
 	u32 core_version, core_minor, core_major;
@@ -145,26 +143,17 @@ static int msm_sdc_probe(struct udevice *dev)
 	/* Set host controller version */
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
-#ifdef CONFIG_BLK
 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 	ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
 			      caps, 0, 0, host->version, host->quirks, 0);
 	host->mmc = &plat->mmc;
-#else
-	/* automatically detect max and min speed */
-	ret = add_sdhci(host, 0, 0);
-#endif
 	if (ret)
 		return ret;
 	host->mmc->priv = &prv->host;
 	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
 
-#ifdef CONFIG_DM_MMC_OPS
 	return sdhci_probe(dev);
-#else
-	return 0;
-#endif
 }
 
 static int msm_sdc_remove(struct udevice *dev)
@@ -201,14 +190,12 @@ static int msm_ofdata_to_platdata(struct udevice *dev)
 
 static int msm_sdc_bind(struct udevice *dev)
 {
-#ifdef CONFIG_BLK
 	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
 	int ret;
 
 	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
 	if (ret)
 		return ret;
-#endif
 
 	return 0;
 }
@@ -223,9 +210,7 @@ U_BOOT_DRIVER(msm_sdc_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= msm_mmc_ids,
 	.ofdata_to_platdata = msm_ofdata_to_platdata,
-#ifdef CONFIG_DM_MMC_OPS
 	.ops		= &sdhci_ops,
-#endif
 	.bind		= msm_sdc_bind,
 	.probe		= msm_sdc_probe,
 	.remove		= msm_sdc_remove,
-- 
cgit v0.10.2


From 87bce4e5c0b55452d70830928b2d7b98fa24d4e3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:32 -0600
Subject: dm: spl: mmc: Support CONFIG_BLK in SPL MMC

Update the method of accessing the block device so that it works with
CONFIG_BLK enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index c44f1b5..6b3e9e4 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -184,7 +184,7 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
 	unsigned long count;
 	int ret;
 
-	count = mmc->block_dev.block_read(&mmc->block_dev,
+	count = blk_dread(mmc_get_blk_desc(mmc),
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
 		(void *) CONFIG_SYS_SPL_ARGS_ADDR);
@@ -225,13 +225,13 @@ int spl_mmc_do_fs_boot(struct mmc *mmc)
 
 #ifdef CONFIG_SPL_FAT_SUPPORT
 	if (!spl_start_uboot()) {
-		err = spl_load_image_fat_os(&mmc->block_dev,
+		err = spl_load_image_fat_os(mmc_get_blk_desc(mmc),
 			CONFIG_SYS_MMCSD_FS_BOOT_PARTITION);
 		if (!err)
 			return err;
 	}
 #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
-	err = spl_load_image_fat(&mmc->block_dev,
+	err = spl_load_image_fat(mmc_get_blk_desc(mmc),
 				 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION,
 				 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
 	if (!err)
-- 
cgit v0.10.2


From 797d1b9de118d4d3f6d918e7412c3ff9b7883bf0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 12 Jun 2016 23:30:33 -0600
Subject: dm: dfu: mmc: Support CONFIG_BLK in DFU for MMC

Update the method of accessing the block device so that it works with
CONFIG_BLK enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c
index 78724e4..926ccbd 100644
--- a/drivers/dfu/dfu_mmc.c
+++ b/drivers/dfu/dfu_mmc.c
@@ -49,7 +49,7 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
 	}
 
 	if (dfu->data.mmc.hw_partition >= 0) {
-		part_num_bkp = mmc->block_dev.hwpart;
+		part_num_bkp = mmc_get_blk_desc(mmc)->hwpart;
 		ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
 					       dfu->data.mmc.dev_num,
 					       dfu->data.mmc.hw_partition);
@@ -62,12 +62,11 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
 	      dfu->data.mmc.dev_num, blk_start, blk_count, buf);
 	switch (op) {
 	case DFU_OP_READ:
-		n = mmc->block_dev.block_read(&mmc->block_dev, blk_start,
-					      blk_count, buf);
+		n = blk_dread(mmc_get_blk_desc(mmc), blk_start, blk_count, buf);
 		break;
 	case DFU_OP_WRITE:
-		n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
-					       blk_count, buf);
+		n = blk_dwrite(mmc_get_blk_desc(mmc), blk_start, blk_count,
+			       buf);
 		break;
 	default:
 		error("Operation not supported\n");
@@ -356,7 +355,7 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s)
 
 	} else if (!strcmp(entity_type, "part")) {
 		disk_partition_t partinfo;
-		struct blk_desc *blk_dev = &mmc->block_dev;
+		struct blk_desc *blk_dev = mmc_get_blk_desc(mmc);
 		int mmcdev = second_arg;
 		int mmcpart = third_arg;
 
-- 
cgit v0.10.2


From 4b689f02ffa0aebdfef204b5c5c17134e97459c3 Mon Sep 17 00:00:00 2001
From: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Date: Tue, 14 Jun 2016 10:17:05 +1200
Subject: dm: gpio: MPC85XX GPIO platform data support

Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
  struct mpc85xx_gpio_plat gpio_blocks[] = {
         {
                 .addr = 0x130000,
                 .ngpios = 32,
         },
         {
                 .addr = 0x131000,
                 .ngpios = 32,
         },
  };

  U_BOOT_DEVICES(my_platform_gpios) = {
         { "gpio_mpc85xx", &gpio_blocks[0] },
         { "gpio_mpc85xx", &gpio_blocks[1] },
  };

This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.

Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 41b6677..76faa22 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -18,4 +18,10 @@
 #include <asm/mpc85xx_gpio.h>
 #endif
 
+struct mpc85xx_gpio_plat {
+	ulong addr;
+	unsigned long size;
+	uint ngpios;
+};
+
 #endif
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
index 04773e2..3754a82 100644
--- a/drivers/gpio/mpc85xx_gpio.c
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -163,23 +163,41 @@ static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
 	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
-	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
 	fdt_size_t size;
 
 	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
 						  "reg", 0, &size);
 
-	data->addr = addr;
-	data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+	plat->addr = addr;
+	plat->size = size;
+	plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+						  "ngpios", 32);
 
-	if (!data->base)
+	return 0;
+}
+#endif
+
+static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
+{
+	struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
+	struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
+	unsigned long size = plat->size;
+
+	if (size == 0)
+		size = 0x100;
+
+	priv->addr = plat->addr;
+	priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
+
+	if (!priv->base)
 		return -ENOMEM;
 
-	data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-					  "ngpios", 32);
-	data->dat_shadow = 0;
+	priv->gpio_count = plat->ngpios;
+	priv->dat_shadow = 0;
 
 	return 0;
 }
@@ -190,6 +208,8 @@ static int mpc85xx_gpio_probe(struct udevice *dev)
 	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
 
+	mpc85xx_gpio_platdata_to_priv(dev);
+
 	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
 	str = strdup(name);
 
@@ -221,8 +241,11 @@ U_BOOT_DRIVER(gpio_mpc85xx) = {
 	.name	= "gpio_mpc85xx",
 	.id	= UCLASS_GPIO,
 	.ops	= &gpio_mpc85xx_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 	.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
 	.of_match = mpc85xx_gpio_ids,
+#endif
 	.probe	= mpc85xx_gpio_probe,
 	.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
 };
-- 
cgit v0.10.2


From ec3cde1e832067352532013988f4590c2f2f6c4f Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Wed, 15 Jun 2016 16:56:18 +0800
Subject: common: block: fix compiler error with CONFIG_FASTBOOT_FLASH_MMC_DEV
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This fixes the following compiler error:

common/fb_mmc.c: In function ‘fb_mmc_erase’:
common/fb_mmc.c:209:17: error: ‘struct blk_desc’ has no member named
‘block_erase’

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index c739651..8d0524d 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -191,7 +191,7 @@ void fb_mmc_erase(const char *cmd)
 	printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
 	       blks_start, blks_start + blks_size);
 
-	blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
+	blks = blk_derase(dev_desc, blks_start, blks_size);
 	if (blks != blks_size) {
 		error("failed erasing from device %d", dev_desc->devnum);
 		fastboot_fail("failed erasing from device");
-- 
cgit v0.10.2


From 6cd2602d61fc4bc172fd99dcbe9b930428992331 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 17:33:11 -0600
Subject: x86: fdt: Drop the unused compatible strings in fdtdec

We have drivers for several more devices now, so drop the strings which are
no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index ff1faa5..4e0be2a 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -424,8 +424,6 @@ static void set_spi_speed(void)
 static int lpc_init_extra(struct udevice *dev)
 {
 	struct udevice *pch = dev->parent;
-	const void *blob = gd->fdt_blob;
-	int node;
 
 	debug("pch: lpc_init\n");
 	dm_pci_write_bar32(pch, 0, 0);
@@ -434,10 +432,6 @@ static int lpc_init_extra(struct udevice *dev)
 	dm_pci_write_bar32(pch, 3, 0x800);
 	dm_pci_write_bar32(pch, 4, 0x900);
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
-	if (node < 0)
-		return -ENOENT;
-
 	/* Set the value for PCI command register. */
 	dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 05d70c4..422a155 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -149,14 +149,9 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
 	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
 	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
-	COMPAT_INTEL_PANTHERPOINT_AHCI,	/* Intel Pantherpoint AHCI */
-	COMPAT_INTEL_MODEL_206AX,	/* Intel Model 206AX CPU */
-	COMPAT_INTEL_GMA,		/* Intel Graphics Media Accelerator */
 	COMPAT_AMS_AS3722,		/* AMS AS3722 PMIC */
-	COMPAT_INTEL_ICH_SPI,		/* Intel ICH7/9 SPI controller */
 	COMPAT_INTEL_QRK_MRC,		/* Intel Quark MRC */
 	COMPAT_SOCIONEXT_XHCI,		/* Socionext UniPhier xHCI */
-	COMPAT_INTEL_PCH,		/* Intel PCH */
 	COMPAT_ALTERA_SOCFPGA_DWMAC,	/* SoCFPGA Ethernet controller */
 	COMPAT_ALTERA_SOCFPGA_DWMMC,	/* SoCFPGA DWMMC controller */
 	COMPAT_ALTERA_SOCFPGA_DWC2USB,	/* SoCFPGA DWC2 USB controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0534c0b..b21d615 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -54,14 +54,9 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
-	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
-	COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
-	COMPAT(INTEL_GMA, "intel,gma"),
 	COMPAT(AMS_AS3722, "ams,as3722"),
-	COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
 	COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
 	COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
-	COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
 	COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
 	COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
 	COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
-- 
cgit v0.10.2


From da9e0a9bab7ddcf9888a6211b76860155895169d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 17:33:12 -0600
Subject: fdt: Drop unused exynos compatible strings

A few drivers have moved to driver model, so we can drop these strings.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 422a155..e53d225 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -138,9 +138,7 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS_USB_PHY,	/* Exynos phy controller for usb2.0 */
 	COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
 	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
-	COMPAT_SAMSUNG_EXYNOS_FIMD,	/* Exynos Display controller */
 	COMPAT_SAMSUNG_EXYNOS_MIPI_DSI,	/* Exynos mipi dsi */
-	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
 	COMPAT_SAMSUNG_EXYNOS_DWMMC,	/* Exynos DWMMC controller */
 	COMPAT_SAMSUNG_EXYNOS_MMC,	/* Exynos MMC controller */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b21d615..960f9bb 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -43,9 +43,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
 	COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
 	COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
-	COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
 	COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
-	COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
 	COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
 	COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"),
-- 
cgit v0.10.2


From 01a227dfc890c8e1b6412a7208fb178d9ac22691 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 17:33:13 -0600
Subject: fdt: Add a note to avoid adding new compatible strings

The list is shrinking and we should avoid adding new things. Instead, a
proper driver should be created with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 960f9bb..68f0df7 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -19,6 +19,11 @@ DECLARE_GLOBAL_DATA_PTR;
  * Here are the type we know about. One day we might allow drivers to
  * register. For now we just put them here. The COMPAT macro allows us to
  * turn this into a sparse list later, and keeps the ID with the name.
+ *
+ * NOTE: This list is basically a TODO list for things that need to be
+ * converted to driver model. So don't add new things here unless there is a
+ * good reason why driver-model conversion is infeasible. Examples include
+ * things which are used before driver model is available.
  */
 #define COMPAT(id, name) name
 static const char * const compat_names[COMPAT_COUNT] = {
-- 
cgit v0.10.2


From 39ea0ee925327c329053288724b42bda875b4074 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 17:33:14 -0600
Subject: fdt: x86: Tidy up a few COMPAT string definitions

The 'COMPAT_' part should appear only once so drop the duplicate part. It is
ignored anyway, but let's keep things consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 68f0df7..5e1a98b 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -63,9 +63,9 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
 	COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
 	COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
-	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
-	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
-	COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
+	COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
+	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
cgit v0.10.2


From 920c6965d11137fff45feccee7e1108875b196d0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 17:33:15 -0600
Subject: sandbox: Find keyboard driver using driver model

The cros-ec keyboard is always a child of the cros-ec node. Rather than
searching the device tree, looking at the children. Remove the compat string
which is now unused.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 98f19a6..c4fbca0 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -517,6 +517,7 @@ int cros_ec_probe(struct udevice *dev)
 	struct ec_state *ec = dev->priv;
 	struct cros_ec_dev *cdev = dev->uclass_priv;
 	const void *blob = gd->fdt_blob;
+	struct udevice *keyb_dev;
 	int node;
 	int err;
 
@@ -525,7 +526,15 @@ int cros_ec_probe(struct udevice *dev)
 	if (err)
 		return err;
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
+	node = -1;
+	for (device_find_first_child(dev, &keyb_dev);
+	     keyb_dev;
+	     device_find_next_child(&keyb_dev)) {
+		if (device_get_uclass_id(keyb_dev) == UCLASS_KEYBOARD) {
+			node = keyb_dev->of_offset;
+			break;
+		}
+	}
 	if (node < 0) {
 		debug("%s: No cros_ec keyboard found\n", __func__);
 	} else if (keyscan_read_fdt_matrix(ec, blob, node)) {
diff --git a/include/fdtdec.h b/include/fdtdec.h
index e53d225..151c590 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -134,7 +134,6 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */
 	COMPAT_SAMSUNG_EXYNOS5_SOUND,	/* Exynos Sound */
 	COMPAT_WOLFSON_WM8994_CODEC,	/* Wolfson WM8994 Sound Codec */
-	COMPAT_GOOGLE_CROS_EC_KEYB,	/* Google CROS_EC Keyboard */
 	COMPAT_SAMSUNG_EXYNOS_USB_PHY,	/* Exynos phy controller for usb2.0 */
 	COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
 	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 5e1a98b..c2bcbde 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -44,7 +44,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
 	COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"),
 	COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"),
-	COMPAT(GOOGLE_CROS_EC_KEYB, "google,cros-ec-keyb"),
 	COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
 	COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
 	COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
-- 
cgit v0.10.2


From 6f0e7a36efbb30fb7a100f5a6f421b0310815815 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 22 Jun 2016 02:29:47 -0700
Subject: dm: Sort the uclass id in alphabetical order

Some uclass ids are out of order. Per the comments, sort them
in alphabetical order.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index b768660..c5cdfc7 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -33,7 +33,6 @@ enum uclass_id {
 	UCLASS_CROS_EC,		/* Chrome OS EC */
 	UCLASS_DISPLAY,		/* Display (e.g. DisplayPort, HDMI) */
 	UCLASS_DMA,		/* Direct Memory Access */
-	UCLASS_RAM,		/* RAM controller */
 	UCLASS_ETH,		/* Ethernet device */
 	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
 	UCLASS_I2C,		/* I2C bus */
@@ -56,11 +55,12 @@ enum uclass_id {
 	UCLASS_PCH,		/* x86 platform controller hub */
 	UCLASS_PCI,		/* PCI bus */
 	UCLASS_PCI_GENERIC,	/* Generic PCI bus device */
-	UCLASS_PINCTRL,		/* Pinctrl (pin muxing/configuration) device */
 	UCLASS_PINCONFIG,	/* Pin configuration node device */
+	UCLASS_PINCTRL,		/* Pinctrl (pin muxing/configuration) device */
 	UCLASS_PMIC,		/* PMIC I/O device */
 	UCLASS_PWM,		/* Pulse-width modulator */
 	UCLASS_PWRSEQ,		/* Power sequence device */
+	UCLASS_RAM,		/* RAM controller */
 	UCLASS_REGULATOR,	/* Regulator device */
 	UCLASS_REMOTEPROC,	/* Remote Processor device */
 	UCLASS_RESET,		/* Reset controller device */
-- 
cgit v0.10.2


From e7df218c3b446e02c5549b79dd76b65054d6147d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 26 Jun 2016 23:24:28 -0700
Subject: tools: patman: Use cover_match for 'Cover-letter'

Like other patman tags, use a new variable cover_match to indicate
a match for 'Cover-letter'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 27d031e..2c4efc5 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -150,6 +150,7 @@ class PatchStream:
         # Handle state transition and skipping blank lines
         series_tag_match = re_series_tag.match(line)
         commit_tag_match = re_commit_tag.match(line)
+        cover_match = re_cover.match(line)
         cover_cc_match = re_cover_cc.match(line)
         signoff_match = re_signoff.match(line)
         tag_match = None
@@ -203,7 +204,7 @@ class PatchStream:
             self.skip_blank = False
 
         # Detect the start of a cover letter section
-        elif re_cover.match(line):
+        elif cover_match:
             self.in_section = 'cover'
             self.skip_blank = False
 
-- 
cgit v0.10.2


From 13b98d95bab89bcac75c8a187577e7cc3754d194 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 26 Jun 2016 23:24:29 -0700
Subject: tools: patman: Handle tag sections without an 'END'

'Cover-letter', 'Series-notes' and 'Commit-notes' tags require an
'END' to be put at the end of its section. If we forget to put an
'END' in those sections, and these sections are followed by another
patman tag, patman generates incorrect patches. This adds codes to
handle such scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 2c4efc5..ce8ffb8 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -169,6 +169,26 @@ class PatchStream:
         elif commit_match:
             self.state = STATE_MSG_HEADER
 
+        # If a tag is detected, but we are already in a section,
+        # this means 'END' is missing for that section, fix it up.
+        if series_tag_match or commit_tag_match or \
+           cover_match or cover_cc_match or signoff_match:
+            if self.in_section:
+                self.warn.append("Missing 'END' in section '%s'" % self.in_section)
+                if self.in_section == 'cover':
+                    self.series.cover = self.section
+                elif self.in_section == 'notes':
+                    if self.is_log:
+                        self.series.notes += self.section
+                elif self.in_section == 'commit-notes':
+                    if self.is_log:
+                        self.commit.notes += self.section
+                else:
+                    self.warn.append("Unknown section '%s'" % self.in_section)
+                self.in_section = None
+                self.skip_blank = True
+                self.section = []
+
         # If we are in a section, keep collecting lines until we see END
         if self.in_section:
             if line == 'END':
-- 
cgit v0.10.2


From 0d57718775243c2d2d7ff8c69dad83db08e1030d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 26 Jun 2016 23:24:30 -0700
Subject: tools: patman: Generate cover letter correctly when 'END' is missing

If 'END' is missing in a 'Cover-letter' section, and that section
happens to show up at the very end of the commit message, and the
commit is the last commit of the series, patman fails to generate
cover letter for us. Handle this in CloseCommit of patchstream.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index ce8ffb8..9ae977f 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -112,6 +112,14 @@ class PatchStream:
         if self.commit and self.is_log:
             self.series.AddCommit(self.commit)
             self.commit = None
+        # If 'END' is missing in a 'Cover-letter' section, and that section
+        # happens to show up at the very end of the commit message, this is
+        # the chance for us to fix it up.
+        if self.in_section == 'cover' and self.is_log:
+            self.series.cover = self.section
+            self.in_section = None
+            self.skip_blank = True
+            self.section = []
 
     def ProcessLine(self, line):
         """Process a single line of a patch file or commit log
-- 
cgit v0.10.2


From 57b6b190a8926403dca2444a45c34bed1f62992d Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 26 Jun 2016 23:24:31 -0700
Subject: tools: patman: Handle missing blank line for 'Series-changes'

'Series-changes' uses blank line to indicate its end. If that is
missing, series internal state variable 'in_change' may be wrong.
Correct its state.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 9ae977f..0612612 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -177,10 +177,11 @@ class PatchStream:
         elif commit_match:
             self.state = STATE_MSG_HEADER
 
-        # If a tag is detected, but we are already in a section,
-        # this means 'END' is missing for that section, fix it up.
+        # If a tag is detected
         if series_tag_match or commit_tag_match or \
            cover_match or cover_cc_match or signoff_match:
+            # but we are already in a section, this means 'END' is missing
+            # for that section, fix it up.
             if self.in_section:
                 self.warn.append("Missing 'END' in section '%s'" % self.in_section)
                 if self.in_section == 'cover':
@@ -196,6 +197,11 @@ class PatchStream:
                 self.in_section = None
                 self.skip_blank = True
                 self.section = []
+            # but we are already in a change list, that means a blank line
+            # is missing, fix it up.
+            if self.in_change:
+                self.warn.append("Missing 'blank line' in section 'Series-changes'")
+                self.in_change = 0
 
         # If we are in a section, keep collecting lines until we see END
         if self.in_section:
-- 
cgit v0.10.2


From 94fbd3e37d6bdbf5490a185607ca20f862637220 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sun, 26 Jun 2016 23:24:32 -0700
Subject: tools: patman: Handle missing 'END' in non-last commit of a series

The following python error:

Traceback (most recent call last):
  File "./tools/patman/patman", line 144, in <module>
    series = patchstream.FixPatches(series, args)
  File "./tools/patman/patchstream.py", line 477, in FixPatches
    commit = series.commits[count]
IndexError: list index out of range

is seen when:

- 'END' is missing in those tags
- those tags are put in the last part in a commit message
- the commit is not the last commit of the series

Add testing logic to see if a new commit starts.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 0612612..69d5cfb 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -177,9 +177,10 @@ class PatchStream:
         elif commit_match:
             self.state = STATE_MSG_HEADER
 
-        # If a tag is detected
+        # If a tag is detected, or a new commit starts
         if series_tag_match or commit_tag_match or \
-           cover_match or cover_cc_match or signoff_match:
+           cover_match or cover_cc_match or signoff_match or \
+           self.state == STATE_MSG_HEADER:
             # but we are already in a section, this means 'END' is missing
             # for that section, fix it up.
             if self.in_section:
-- 
cgit v0.10.2


From adde435fa7c03c17c40e9f771eceed127fbbc251 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 24 May 2016 14:59:59 -0700
Subject: video: allow version string to be optional when using LOGO

The CONFIG_HIDE_LOGO_VERSION config can be used to disable putting the
U-Boot version string on top of the logo.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/README b/README
index 26d5ad2..e86934a 100644
--- a/README
+++ b/README
@@ -840,6 +840,9 @@ The following options need to be configured:
 			CONFIG_CONSOLE_EXTRA_INFO
 						additional board info beside
 						the logo
+			CONFIG_HIDE_LOGO_VERSION
+						do not display bootloader
+						version string
 
 		When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
 		a limited number of ANSI escape sequences (cursor control,
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index ef4984b..30b53db 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1929,10 +1929,10 @@ static void plot_logo_or_black(void *screen, int x, int y, int black)
 static void *video_logo(void)
 {
 	char info[128];
-	int space, len;
 	__maybe_unused int y_off = 0;
 	__maybe_unused ulong addr;
 	__maybe_unused char *s;
+	__maybe_unused int len, space;
 
 	splash_get_pos(&video_logo_xpos, &video_logo_ypos);
 
@@ -1978,6 +1978,7 @@ static void *video_logo(void)
 
 	sprintf(info, " %s", version_string);
 
+#ifndef CONFIG_HIDE_LOGO_VERSION
 	space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH;
 	len = strlen(info);
 
@@ -2027,6 +2028,7 @@ static void *video_logo(void)
 		}
 	}
 #endif
+#endif
 
 	return (video_fb_address + video_logo_height * VIDEO_LINE_LEN);
 }
-- 
cgit v0.10.2


From 836efb33e31f2c2567a094073ee1572367693599 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Tue, 28 Jun 2016 19:47:25 +0900
Subject: ARM: exynos4: dts: add the prefix '/' for aliases nodes

It's correct to use '/' as prefix for aliases nodes.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
index 3f87761..26c4d7f 100644
--- a/arch/arm/dts/exynos4210-origen.dts
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -22,7 +22,7 @@
 	aliases {
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc2 = "sdhci@12530000";
+		mmc2 = "/sdhci@12530000";
 	};
 
 	sdhci@12510000 {
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index f3fac80..2ed38f3 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -29,8 +29,8 @@
 		i2c7 = "/i2c@138d0000";
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc0 = "sdhci@12510000";
-		mmc2 = "sdhci@12530000";
+		mmc0 = "/sdhci@12510000";
+		mmc2 = "/sdhci@12530000";
 	};
 
 	fimd@11c00000 {
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index ad3527e..8cac7dd 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -17,8 +17,8 @@
 	aliases {
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc0 = "sdhci@12510000";
-		mmc2 = "sdhci@12530000";
+		mmc0 = "/sdhci@12510000";
+		mmc2 = "/sdhci@12530000";
 	};
 
 	sdhci@12510000 {
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index a63e8ab..188cb93 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -25,8 +25,8 @@
 		i2c7 = "/i2c@138d0000";
 		serial0 = "/serial@13800000";
 		console = "/serial@13810000";
-		mmc2 = "sdhci@12530000";
-		mmc4 = "dwmmc@12550000";
+		mmc2 = "/sdhci@12530000";
+		mmc4 = "/dwmmc@12550000";
 	};
 
 	i2c@13860000 {
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index 2d4e522..1fbcf89 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -29,9 +29,9 @@
 		i2c7 = "/i2c@138d0000";
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc0 = "sdhci@12510000";
-		mmc2 = "sdhci@12530000";
-		mmc4 = "dwmmc@12550000";
+		mmc0 = "/sdhci@12510000";
+		mmc2 = "/sdhci@12530000";
+		mshc0 = "/dwmmc@12550000";
 	};
 
 	i2c@138d0000 {
-- 
cgit v0.10.2


From fb6706cfda976ab0500f7ce7f522d3d8fa913fd4 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Wed, 29 Jun 2016 19:46:14 +0900
Subject: mmc: exynos_dw_mmc: remove the unused function

This function have maintained for supporting Non-FDT.
Now, Almost all SoC are changed to fdt style.
So there are no that this function is called anywhere.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h
index bd997ad..ab8361f 100644
--- a/arch/arm/mach-exynos/include/mach/dwmmc.h
+++ b/arch/arm/mach-exynos/include/mach/dwmmc.h
@@ -28,4 +28,3 @@
 #define DWMCI_DIVRATIO_MASK		0x7
 
 int exynos_dwmmc_init(const void *blob);
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 863bbb3..2b9b3aa 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -122,42 +122,6 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
 	return 0;
 }
 
-/*
- * This function adds the mmc channel to be registered with mmc core.
- * index -	mmc channel number.
- * regbase -	register base address of mmc channel specified in 'index'.
- * bus_width -	operating bus width of mmc channel specified in 'index'.
- * clksel -	value to be written into CLKSEL register in case of FDT.
- *		NULL in case od non-FDT.
- */
-int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
-{
-	struct dwmci_host *host = NULL;
-	struct dwmci_exynos_priv_data *priv;
-
-	host = malloc(sizeof(struct dwmci_host));
-	if (!host) {
-		error("dwmci_host malloc fail!\n");
-		return -ENOMEM;
-	}
-
-	priv = malloc(sizeof(struct dwmci_exynos_priv_data));
-	if (!priv) {
-		error("dwmci_exynos_priv_data malloc fail!\n");
-		return -ENOMEM;
-	}
-
-	host->ioaddr = (void *)regbase;
-	host->buswidth = bus_width;
-
-	if (clksel)
-		priv->sdr_timing = clksel;
-
-	host->priv = priv;
-
-	return exynos_dwmci_core_init(host, index);
-}
-
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
 
-- 
cgit v0.10.2


From f565ea59cbc040bae1d5b49912ba93a2f836ba11 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Wed, 29 Jun 2016 19:46:15 +0900
Subject: mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROL

Removed #ifdef for OF_CONTROL.
It might use 'OF_CONTROL' by default.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 2b9b3aa..80d17ad 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -122,7 +122,6 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
 
 static int do_dwmci_init(struct dwmci_host *host)
@@ -250,4 +249,3 @@ int exynos_dwmmc_init(const void *blob)
 
 	return err;
 }
-#endif
-- 
cgit v0.10.2


From ce757b18fb1ef21de2fd446031f4ad2a554dc1fb Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Wed, 29 Jun 2016 19:46:16 +0900
Subject: mmc: exynos_dw_mmc: add the error control for checking index

PERIPH_ID_SDMMC4(131) is not continous value with PERIPH_ID_SDMMC0(75).
If there is no 'index' property in fdt, then dev_index should be
assigned to dev_id(Peripheral ID).
At this time, dev_index should be "56". It means Exynos SoC has "56"
numbers of DWMMC IP. To prevent this behavior, it needs to check the
maximum device index.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 80d17ad..5860023 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -160,6 +160,11 @@ static int exynos_dwmci_get_config(const void *blob, int node,
 	if (host->dev_index == host->dev_id)
 		host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
 
+	if (host->dev_index > 4) {
+		printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
+		return -EINVAL;
+	}
+
 	/* Get the bus width from the device node */
 	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
 	if (host->buswidth <= 0) {
-- 
cgit v0.10.2


From d956a67ed14e158fd24b5c85cc414bfa14773457 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Wed, 29 Jun 2016 19:46:17 +0900
Subject: mmc: exynos_dw_mmc: clean the unused and unnecessary codes

Clean the unused and unnecessary codse.
This patch is one of them for preparing to use DM.
Because it's easy to maintain and combine DM after cleaning codes.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 5860023..cfbe135 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -80,11 +80,10 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)
 		exynos_dwmci_clksel(host);
 }
 
-static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
+static int exynos_dwmci_core_init(struct dwmci_host *host)
 {
 	unsigned int div;
 	unsigned long freq, sclk;
-	struct dwmci_exynos_priv_data *priv = host->priv;
 
 	if (host->bus_hz)
 		freq = host->bus_hz;
@@ -92,10 +91,10 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
 		freq = DWMMC_MAX_FREQ;
 
 	/* request mmc clock vlaue of 52MHz.  */
-	sclk = get_mmc_clk(index);
+	sclk = get_mmc_clk(host->dev_index);
 	div = DIV_ROUND_UP(sclk, freq);
 	/* set the clock divisor for mmc */
-	set_mmc_clk(index, div);
+	set_mmc_clk(host->dev_index, div);
 
 	host->name = "EXYNOS DWMMC";
 #ifdef CONFIG_EXYNOS5420
@@ -103,20 +102,12 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
 #endif
 	host->board_init = exynos_dwmci_board_init;
 
-	if (!priv->sdr_timing) {
-		if (index == 0)
-			priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
-		else if (index == 2)
-			priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
-	}
-
 	host->caps = MMC_MODE_DDR_52MHz;
 	host->clksel = exynos_dwmci_clksel;
-	host->dev_index = index;
 	host->get_mmc_clk = exynos_dwmci_get_clk;
 	/* Add the mmc channel to be registered with mmc core */
 	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
-		printf("DWMMC%d registration failed\n", index);
+		printf("DWMMC%d registration failed\n", host->dev_index);
 		return -1;
 	}
 	return 0;
@@ -126,18 +117,16 @@ static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
 
 static int do_dwmci_init(struct dwmci_host *host)
 {
-	int index, flag, err;
-
-	index = host->dev_index;
+	int flag, err;
 
 	flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
 	err = exynos_pinmux_config(host->dev_id, flag);
 	if (err) {
-		printf("DWMMC%d not configure\n", index);
+		printf("DWMMC%d not configure\n", host->dev_index);
 		return err;
 	}
 
-	return exynos_dwmci_core_init(host, index);
+	return exynos_dwmci_core_init(host);
 }
 
 static int exynos_dwmci_get_config(const void *blob, int node,
@@ -233,15 +222,13 @@ static int exynos_dwmci_process_node(const void *blob,
 
 int exynos_dwmmc_init(const void *blob)
 {
-	int compat_id;
 	int node_list[DWMMC_MAX_CH_NUM];
 	int boot_dev_node;
 	int err = 0, count;
 
-	compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
-
 	count = fdtdec_find_aliases_for_id(blob, "mmc",
-				compat_id, node_list, DWMMC_MAX_CH_NUM);
+			COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
+			DWMMC_MAX_CH_NUM);
 
 	/* For DWMMC always set boot device as mmc 0 */
 	if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
-- 
cgit v0.10.2


From 70f6d39433d3d597adeac3d4c84b3a58b86cd2d3 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Wed, 29 Jun 2016 19:46:18 +0900
Subject: mmc: exynos_dw_mmc: use the 4bit bus-width by default

If there is not "samsung,bus-width" property, use the 4bit buswidth by
default.
Almost all Exnyos SoCs support at least 4bit buswidth.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index cfbe135..ab0df46 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -154,12 +154,8 @@ static int exynos_dwmci_get_config(const void *blob, int node,
 		return -EINVAL;
 	}
 
-	/* Get the bus width from the device node */
-	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
-	if (host->buswidth <= 0) {
-		printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
-		return -EINVAL;
-	}
+	/* Get the bus width from the device node (Default is 4bit buswidth) */
+	host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
 
 	/* Set the base address from the device node */
 	base = fdtdec_get_addr(blob, node, "reg");
-- 
cgit v0.10.2


From 3537ee879e0428587621a2cafbad2d9982bc082b Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Thu, 30 Jun 2016 20:57:37 +0900
Subject: mmc: exynos_dw_mmc: support the Driver mode for Exynos

This patch support the driver mode for exynos dwmmc controller.
To support the legacy model, maintained the existing code.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index ab0df46..283befc 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -23,8 +23,21 @@
 #define	DWMMC_MMC0_SDR_TIMING_VAL	0x03030001
 #define	DWMMC_MMC2_SDR_TIMING_VAL	0x03020001
 
+#ifdef CONFIG_DM_MMC
+#include <dm.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+struct exynos_mmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+#endif
+
 /* Exynos implmentation specific drver private data */
 struct dwmci_exynos_priv_data {
+#ifdef CONFIG_DM_MMC
+	struct dwmci_host host;
+#endif
 	u32 sdr_timing;
 };
 
@@ -105,11 +118,15 @@ static int exynos_dwmci_core_init(struct dwmci_host *host)
 	host->caps = MMC_MODE_DDR_52MHz;
 	host->clksel = exynos_dwmci_clksel;
 	host->get_mmc_clk = exynos_dwmci_get_clk;
+
+#ifndef CONFIG_DM_MMC
 	/* Add the mmc channel to be registered with mmc core */
 	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
 		printf("DWMMC%d registration failed\n", host->dev_index);
 		return -1;
 	}
+#endif
+
 	return 0;
 }
 
@@ -237,3 +254,58 @@ int exynos_dwmmc_init(const void *blob)
 
 	return err;
 }
+
+#ifdef CONFIG_DM_MMC
+static int exynos_dwmmc_probe(struct udevice *dev)
+{
+	struct exynos_mmc_plat *plat = dev_get_platdata(dev);
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
+	struct dwmci_host *host = &priv->host;
+	int err;
+
+	err = exynos_dwmci_get_config(gd->fdt_blob, dev->of_offset, host);
+	if (err)
+		return err;
+	err = do_dwmci_init(host);
+	if (err)
+		return err;
+
+	dwmci_setup_cfg(&plat->cfg, host->name, host->buswidth, host->caps,
+			DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
+	host->mmc = &plat->mmc;
+	host->mmc->priv = &priv->host;
+	host->priv = dev;
+	upriv->mmc = host->mmc;
+
+	return dwmci_probe(dev);
+}
+
+static int exynos_dwmmc_bind(struct udevice *dev)
+{
+	struct exynos_mmc_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id exynos_dwmmc_ids[] = {
+	{ .compatible = "samsung,exynos4412-dw-mshc" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_dwmmc_drv) = {
+	.name		= "exynos_dwmmc",
+	.id		= UCLASS_MMC,
+	.of_match	= exynos_dwmmc_ids,
+	.bind		= exynos_dwmmc_bind,
+	.ops		= &dm_dwmci_ops,
+	.probe		= exynos_dwmmc_probe,
+	.priv_auto_alloc_size	= sizeof(struct dwmci_exynos_priv_data),
+	.platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
+};
+#endif
-- 
cgit v0.10.2


From b45dd66225dfe60d692efde1e7bd36b5842434b7 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 14 Jun 2016 02:02:38 -0700
Subject: pci: Remove CONFIG_ALWAYS_LOAD_OPROM

This option is defined at nowhere. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 9eb605b..3ae9231 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -41,8 +41,6 @@ __weak bool board_should_run_oprom(struct udevice *dev)
 
 static bool should_load_oprom(struct udevice *dev)
 {
-	if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
-		return 1;
 	if (board_should_run_oprom(dev))
 		return 1;
 
-- 
cgit v0.10.2


From c0aea6ba8b008aa3e28d85d70f7fb11885d560e0 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 14 Jun 2016 02:02:39 -0700
Subject: pci: Make load_oprom and run_oprom independent

At present should_load_oprom() calls board_should_run_oprom() to
determine whether oprom should be loaded. But sometimes we just
want to load oprom without running. Make them independent.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 3ae9231..a168559 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -41,10 +41,7 @@ __weak bool board_should_run_oprom(struct udevice *dev)
 
 static bool should_load_oprom(struct udevice *dev)
 {
-	if (board_should_run_oprom(dev))
-		return 1;
-
-	return 0;
+	return true;
 }
 
 __weak uint32_t board_map_oprom_vendev(uint32_t vendev)
-- 
cgit v0.10.2


From f698baa9d14be89e10f3bc3ae16fb6a084bdee54 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 14 Jun 2016 02:02:40 -0700
Subject: pci: Add board_ prefix to should_load_oprom() and make it weak

For consistency with board_should_run_oprom(), do the same to
should_load_oprom(). Board support codes can provide this one
to override the default weak one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index a168559..399055b 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -39,7 +39,7 @@ __weak bool board_should_run_oprom(struct udevice *dev)
 	return true;
 }
 
-static bool should_load_oprom(struct udevice *dev)
+__weak bool board_should_load_oprom(struct udevice *dev)
 {
 	return true;
 }
@@ -273,7 +273,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
 		return -ENODEV;
 	}
 
-	if (!should_load_oprom(dev))
+	if (!board_should_load_oprom(dev))
 		return -ENXIO;
 
 	ret = pci_rom_probe(dev, &rom);
-- 
cgit v0.10.2


From 377656b2cc3be3e704fc574041669a4a84ea6bb8 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 14 Jun 2016 21:33:23 -0700
Subject: x86: baytrail: Introduce a Kconfig option for the internal UART

There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.

So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
index 407feb2..1c8ac37 100644
--- a/arch/x86/cpu/baytrail/Kconfig
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -7,3 +7,14 @@
 config INTEL_BAYTRAIL
 	bool
 	select HAVE_FSP if !EFI
+
+if INTEL_BAYTRAIL
+config INTERNAL_UART
+	bool "Enable the SoC integrated legacy UART"
+	help
+	  There is a legacy UART integrated into the Bay Trail SoC.
+	  A maximum baud rate of 115200 bps is supported. For this
+	  reason, it is recommended that the UART port be used for
+	  debug purposes only, eg: U-Boot console.
+
+endif
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 9f1d7fb..0a71bb8 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -2,6 +2,7 @@ CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
 CONFIG_TARGET_BAYLEYBAY=y
+CONFIG_INTERNAL_UART=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 28b837d..ba2b7dc 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -2,6 +2,7 @@ CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
 CONFIG_TARGET_MINNOWMAX=y
+CONFIG_INTERNAL_UART=y
 CONFIG_HAVE_INTEL_ME=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
-- 
cgit v0.10.2


From d9703a0725707dc39d58c1de486af26ea3886e56 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 14 Jun 2016 21:33:24 -0700
Subject: x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UART

For any FSP-enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index b05dced..a480361 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -110,7 +110,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
 	struct upd_region *fsp_upd;
 #endif
 
-#ifdef CONFIG_DEBUG_UART
+#ifdef CONFIG_INTERNAL_UART
 	setup_internal_uart(1);
 #endif
 
-- 
cgit v0.10.2


From f2a751bebafed498d216f8d9a49d21f0d8335fe3 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Wed, 15 Jun 2016 14:15:25 +0200
Subject: x86: conga-qeval20-qa3: Add support for internal UART

This patch adds support to enable and use the internal BayTrail UART
instead of the one integrated in the Super IO Winbond chip. For this,
a 2nd defconfig file is added.

This is useful for tests done for the congatec SoM used on baseboards
without such a Super IO chip.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
index 6a946d5..737e610 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -12,6 +12,7 @@
 
 int board_early_init_f(void)
 {
+#ifndef CONFIG_INTERNAL_UART
 	/*
 	 * The FSP enables the BayTrail internal legacy UART (again).
 	 * Disable it again, so that the Winbond one can be used.
@@ -21,6 +22,7 @@ int board_early_init_f(void)
 	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
 	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
 			      UART0_BASE, UART0_IRQ);
+#endif
 
 	return 0;
 }
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
new file mode 100644
index 0000000..26f83ba
--- /dev/null
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -0,0 +1,63 @@
+CONFIG_X86=y
+CONFIG_VENDOR_CONGATEC=y
+CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
+CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
+CONFIG_INTERNAL_UART=y
+CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_WINBOND_W83627=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_USE_PRIVATE_LIBGCC=y
-- 
cgit v0.10.2


From 2047390abc04b921764bd23eeffc0d3e83a2a674 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Fri, 17 Jun 2016 02:13:14 -0700
Subject: x86: baytrail: Introduce ACPI global NVS

This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 5ee4868..fa92d88 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -5,10 +5,14 @@
  */
 
 #include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
 #include <asm/acpi_table.h>
 #include <asm/ioapic.h>
 #include <asm/mpspec.h>
 #include <asm/tables.h>
+#include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
 
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
@@ -161,3 +165,25 @@ u32 acpi_fill_madt(u32 current)
 
 	return current;
 }
+
+void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+	struct udevice *dev;
+	int ret;
+
+	/* at least we have one processor */
+	gnvs->pcnt = 1;
+	/* override the processor count with actual number */
+	ret = uclass_find_first_device(UCLASS_CPU, &dev);
+	if (ret == 0 && dev != NULL) {
+		ret = cpu_get_count(dev);
+		if (ret > 0)
+			gnvs->pcnt = ret;
+	}
+
+	/* determine whether internal uart is on */
+	if (IS_ENABLED(CONFIG_INTERNAL_UART))
+		gnvs->iuart_en = 1;
+	else
+		gnvs->iuart_en = 0;
+}
diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h
new file mode 100644
index 0000000..7f2ffd4
--- /dev/null
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ACPI_GNVS_H_
+#define _ACPI_GNVS_H_
+
+/*
+ * This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and
+ * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
+ * to declare the GNVS OperationRegion, as well as write_acpi_tables()
+ * for the GNVS address runtime fix up.
+ */
+#define ACPI_GNVS_ADDR	0xdeadbeef
+#define ACPI_GNVS_SIZE	0x100
+
+#endif /* _ACPI_GNVS_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl
new file mode 100644
index 0000000..a28d4df
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x00),
+	PCNT, 8,	/* processor count */
+	IURE, 8,	/* internal UART enabled */
+}
diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h
new file mode 100644
index 0000000..56e3626
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+	u8	iuart_en;	/* internal UART enabled */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[254];
+};
+
+#endif /* _GLOBAL_NVS_H_ */
-- 
cgit v0.10.2


From cf7108b320e1851b829d6adc9bd4f4462c5f5072 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Fri, 17 Jun 2016 02:13:15 -0700
Subject: x86: quark: Introduce ACPI global NVS

This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 8f69829..3968f7a 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -9,6 +9,7 @@
 #include <asm/ioapic.h>
 #include <asm/mpspec.h>
 #include <asm/tables.h>
+#include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
 
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
@@ -161,3 +162,9 @@ u32 acpi_fill_madt(u32 current)
 
 	return current;
 }
+
+void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+{
+	/* quark is a uni-processor */
+	gnvs->pcnt = 1;
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl
new file mode 100644
index 0000000..6f0435e
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x00),
+	PCNT, 8,	/* processor count */
+}
diff --git a/arch/x86/include/asm/arch-quark/global_nvs.h b/arch/x86/include/asm/arch-quark/global_nvs.h
new file mode 100644
index 0000000..0231da0
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/global_nvs.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[255];
+};
+
+#endif /* _GLOBAL_NVS_H_ */
-- 
cgit v0.10.2


From 79c2c257cf66da5ac90b5c53954310361e41bb0a Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Fri, 17 Jun 2016 02:13:16 -0700
Subject: x86: acpi: Pack global NVS into ACPI table

Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 56aa282..caff4d8 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -299,6 +299,9 @@ struct acpi_mcfg_mmconfig {
 /* PM1_CNT bit defines */
 #define PM1_CNT_SCI_EN		(1 << 0)
 
+/* ACPI global NVS structure */
+struct acpi_global_nvs;
+
 /* These can be used by the target port */
 
 void acpi_fill_header(struct acpi_table_header *header, char *signature);
@@ -312,4 +315,5 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 			       u8 cpu, u16 flags, u8 lint);
 u32 acpi_fill_madt(u32 current);
+void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
index 6bc82ec..a80d2c0 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -22,6 +22,9 @@ Method(_WAK, 1)
 	Return (Package() {0, 0})
 }
 
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
 /* TODO: add CPU ASL support */
 
 Scope (\_SB)
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
index bd72842..1ecf153 100644
--- a/arch/x86/include/asm/arch-quark/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -22,6 +22,9 @@ Method(_WAK, 1)
 	Return (Package() {0, 0})
 }
 
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
 /* TODO: add CPU ASL support */
 
 Scope (\_SB)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index bb71286..7001e8b 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -11,10 +11,12 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
+#include <asm/acpi/global_nvs.h>
 #include <asm/acpi_table.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/tables.h>
+#include <asm/arch/global_nvs.h>
 
 /*
  * IASL compiles the dsdt entries and writes the hex values
@@ -336,6 +338,7 @@ u32 write_acpi_tables(u32 start)
 	struct acpi_fadt *fadt;
 	struct acpi_mcfg *mcfg;
 	struct acpi_madt *madt;
+	int i;
 
 	current = start;
 
@@ -383,6 +386,25 @@ u32 write_acpi_tables(u32 start)
 	current += dsdt->length - sizeof(struct acpi_table_header);
 	current = ALIGN(current, 16);
 
+	/* Pack GNVS into the ACPI table area */
+	for (i = 0; i < dsdt->length; i++) {
+		u32 *gnvs = (u32 *)((u32)dsdt + i);
+		if (*gnvs == ACPI_GNVS_ADDR) {
+			debug("Fix up global NVS in DSDT to 0x%08x\n", current);
+			*gnvs = current;
+			break;
+		}
+	}
+
+	/* Update DSDT checksum since we patched the GNVS address */
+	dsdt->checksum = 0;
+	dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
+
+	/* Fill in platform-specific global NVS variables */
+	acpi_create_gnvs((struct acpi_global_nvs *)current);
+	current += sizeof(struct acpi_global_nvs);
+	current = ALIGN(current, 16);
+
 	debug("ACPI:    * FADT\n");
 	fadt = (struct acpi_fadt *)current;
 	current += sizeof(struct acpi_fadt);
diff --git a/doc/README.x86 b/doc/README.x86
index a548b54..7d694b1 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -1020,8 +1020,6 @@ Features not supported so far (to make it a complete ACPI solution):
  * S3 (Suspend to RAM), S4 (Suspend to Disk).
 
 Features that are optional:
- * ACPI global NVS support. We may need it to simplify ASL code logic if
-   utilizing NVS variables. Most likely we will need this sooner or later.
  * Dynamic AML bytecodes insertion at run-time. We may need this to support
    SSDT table generation and DSDT fix up.
  * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
-- 
cgit v0.10.2


From 3ff11aaa507aa222e76aa2517efc9786494994ed Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Fri, 17 Jun 2016 02:13:17 -0700
Subject: x86: baytrail: acpi: Hide internal UART per GNVS setting

If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 22f0d68..fe34d32 100644
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -119,17 +119,14 @@ Device (LPCB)
 
 		Method(_STA, 0, Serialized)
 		{
-			/*
-			 * TODO:
-			 *
-			 * Need to hide the internal UART depending on whether
-			 * internal UART is enabled or not so that external
-			 * SuperIO UART can be exposed to system.
-			 */
-			Store(1, UI3E)
-			Store(1, UI4E)
-			Store(1, C1EN)
-			Return (STA_VISIBLE)
+			If (LEqual(IURE, 1)) {
+				Store(1, UI3E)
+				Store(1, UI4E)
+				Store(1, C1EN)
+				Return (STA_VISIBLE)
+			} Else {
+				Return (STA_MISSING)
+			}
 
 		}
 
-- 
cgit v0.10.2


From 215099a522dae18d4682964c6b850d12c45c98a0 Mon Sep 17 00:00:00 2001
From: George McCollister <george.mccollister@gmail.com>
Date: Tue, 21 Jun 2016 12:07:33 -0500
Subject: x86: Add Advantech SOM-DB5800/SOM-6867 support

Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
 - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
   SOM-DB5800.
 - 4x USB 2.0 (EHCI)
 - Video
 - SATA
 - Ethernet
 - PCIe
 - Realtek ALC892 HD Audio
   Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
   HDA_SDI0 is set in DT to enable HD Audio codec.
   Pin defaults for codec pin complexs are not changed.

Not supported:
 - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
 - USB 3.0 (XHCI)
 - TPM

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 29d2307..29d1120 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -8,6 +8,9 @@ choice
 	prompt "Mainboard vendor"
 	default VENDOR_EMULATION
 
+config VENDOR_ADVANTECH
+	bool "advantech"
+
 config VENDOR_CONGATEC
 	bool "congatec"
 
@@ -29,6 +32,7 @@ config VENDOR_INTEL
 endchoice
 
 # board-specific options below
+source "board/advantech/Kconfig"
 source "board/congatec/Kconfig"
 source "board/coreboot/Kconfig"
 source "board/efi/Kconfig"
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 23156bb..4f07f41 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -14,7 +14,8 @@ dtb-y += bayleybay.dtb \
 	minnowmax.dtb \
 	qemu-x86_i440fx.dtb \
 	qemu-x86_q35.dtb \
-	broadwell_som-6896.dtb
+	broadwell_som-6896.dtb \
+	baytrail_som-db5800-som-6867.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
new file mode 100644
index 0000000..64e2e52
--- /dev/null
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Advantech SOM-DB5800-SOM-6867";
+	compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
+
+	aliases {
+		serial0 = &serial;
+		spi0 = &spi;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
+
+		/* HDA_RSTB */
+		soc_gpio_s0_8@0 {
+			pad-offset = <0x220>;
+			mode-func = <2>;
+		};
+
+		/* HDA_SYNC */
+		soc_gpio_s0_9@0 {
+			pad-offset = <0x250>;
+			mode-func = <2>;
+			pull-assign = <1>;
+		};
+
+		/* HDA_CLK */
+		soc_gpio_s0_10@0 {
+			pad-offset = <0x240>;
+			mode-func = <2>;
+		};
+
+		/* HDA_SDO */
+		soc_gpio_s0_11@0 {
+			pad-offset = <0x260>;
+			mode-func = <2>;
+			pull-assign = <1>;
+		};
+
+		/* HDA_SDI0 */
+		soc_gpio_s0_12@0 {
+			pad-offset = <0x270>;
+			mode-func = <2>;
+		};
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <1>;
+			intel,apic-id = <2>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <2>;
+			intel,apic-id = <4>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <3>;
+			intel,apic-id = <6>;
+		};
+
+	};
+
+	pci {
+		compatible = "intel,pci-baytrail", "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "pci8086,0f1c", "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* BayTrail PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 22, 0) INTA PIRQA
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 29, 0) INTA PIRQA
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 1) INTD PIRQD
+					PCI_BDF(0, 30, 2) INTB PIRQB
+					PCI_BDF(0, 30, 3) INTC PIRQC
+					PCI_BDF(0, 30, 4) INTD PIRQD
+					PCI_BDF(0, 30, 5) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "macronix,mx25l6405d",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x006f0000 0x00010000>;
+					};
+				};
+			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x20>;
+				bank-name = "C";
+			};
+
+			gpiod {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x60 0x20>;
+				bank-name = "D";
+			};
+
+			gpioe {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x80 0x20>;
+				bank-name = "E";
+			};
+
+			gpiof {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0xA0 0x20>;
+				bank-name = "F";
+			};
+		};
+	};
+
+	fsp {
+		compatible = "intel,baytrail-fsp";
+		fsp,mrc-init-tseg-size = <0>;
+		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-spd-addr1 = <0xa0>;
+		fsp,mrc-init-spd-addr2 = <0xa2>;
+		fsp,enable-spi;
+		fsp,enable-sata;
+		fsp,sata-mode = <1>;
+		fsp,enable-azalia;
+		fsp,lpss-sio-enable-pci-mode;
+		fsp,enable-dma0;
+		fsp,enable-dma1;
+		fsp,enable-i2c0;
+		fsp,enable-i2c1;
+		fsp,enable-i2c2;
+		fsp,enable-i2c3;
+		fsp,enable-i2c4;
+		fsp,enable-i2c5;
+		fsp,enable-i2c6;
+		fsp,enable-pwm0;
+		fsp,enable-pwm1;
+		fsp,igd-dvmt50-pre-alloc = <2>;
+		fsp,aperture-size = <2>;
+		fsp,gtt-size = <2>;
+		fsp,scc-enable-pci-mode;
+		fsp,os-selection = <4>;
+		fsp,enable-igd;
+		fsp,serial-debug-port-address = <0x3f8>;
+		fsp,serial-debug-port-type = <1>;
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/m0130673325.dtsi"
+		};
+		update@1 {
+#include "microcode/m0130679907.dtsi"
+		};
+	};
+
+};
diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig
new file mode 100644
index 0000000..a8d4969
--- /dev/null
+++ b/board/advantech/Kconfig
@@ -0,0 +1,28 @@
+if VENDOR_ADVANTECH
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_SOM_DB5800_SOM_6867
+	bool "Advantech SOM-DB5800 & SOM-6867"
+	help
+	  Advantech SOM-DB5800 COM Express development board with SOM-6867
+	  installed.
+
+	  SOM-6867 is a COM Express Type 6 Compact Module with either an Intel
+	  Atom E3845 or Celeron N2920 processor.
+
+	  SOM-DB5800 is a COM Express Development board with:
+	    10/100/1000 Ethernet
+	    PCIe slots
+	    4x USB ports
+	    HDMI/DisplayPort/DVI, LVDS, VGA
+	    SATA ports
+	    ALC892 HD Audio Codec
+
+endchoice
+
+source "board/advantech/som-db5800-som-6867/Kconfig"
+
+endif
diff --git a/board/advantech/som-db5800-som-6867/.gitignore b/board/advantech/som-db5800-som-6867/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig
new file mode 100644
index 0000000..f6f3748
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_SOM_DB5800_SOM_6867
+
+config SYS_BOARD
+	default "som-db5800-som-6867"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "som-db5800-som-6867"
+
+config SYS_TEXT_BASE
+	default 0xfff00000 if !EFI_STUB
+	default 0x01110000 if EFI_STUB
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR if !EFI_STUB
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/board/advantech/som-db5800-som-6867/MAINTAINERS b/board/advantech/som-db5800-som-6867/MAINTAINERS
new file mode 100644
index 0000000..92989bf
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/MAINTAINERS
@@ -0,0 +1,7 @@
+Advantech SOM-DB5800-SOM-6867
+M:	George McCollister <george.mccollister@gmail.com>
+S:	Maintained
+F:	board/advantech/som-db5800-som-6867
+F:	include/configs/som-db5800-som-6867.h
+F:	configs/som-db5800-som-6867_defconfig
+F:	arch/x86/dts/baytrail_som-db5800-som-6867.dts
diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile
new file mode 100644
index 0000000..9837aa0
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= som-db5800-som-6867.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/advantech/som-db5800-som-6867/dsdt.asl b/board/advantech/som-db5800-som-6867/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
new file mode 100644
index 0000000..5bed2c1
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int board_early_init_f(void)
+{
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the one on the EC can be used.
+	 */
+	setup_internal_uart(0);
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
new file mode 100644
index 0000000..30e093b
--- /dev/null
+++ b/configs/som-db5800-som-6867_defconfig
@@ -0,0 +1,61 @@
+CONFIG_X86=y
+CONFIG_VENDOR_ADVANTECH=y
+CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
+CONFIG_TARGET_SOM_DB5800_SOM_6867=y
+CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_MMC is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h
new file mode 100644
index 0000000..a4b343e
--- /dev/null
+++ b/include/configs/som-db5800-som-6867.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARCH_MISC_INIT
+
+#define CONFIG_PCI_PNP
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial,usbkbd,vga\0" \
+					"stdout=serial,vga\0" \
+					"stderr=serial,vga\0"
+
+#define CONFIG_SCSI_DEV_LIST		\
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ef000
+
+#endif	/* __CONFIG_H */
-- 
cgit v0.10.2


From 9532fe3b40ddf66ef976dee3d5cf1d8b3396bf4d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 11 Jul 2016 09:30:55 -0600
Subject: x86: link: Correct a failure in DRAM init

With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.

Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 9d9f63d..e0b06b5 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -458,6 +458,11 @@ int dram_init(void)
 	struct udevice *dev, *me_dev;
 	int ret;
 
+	/* We need the pinctrl set up early */
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+	if (ret)
+		return ret;
+
 	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
 	if (ret)
 		return ret;
-- 
cgit v0.10.2


From c1ebf54868359005c32944c1473668d5fcaca158 Mon Sep 17 00:00:00 2001
From: Petr Kulhavy <brain@jikos.cz>
Date: Sun, 12 Jun 2016 13:18:32 +0200
Subject: imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for EXTFS

spl_boot_mode() returned MMCSD_MODE_RAW on MMC if CONFIG_SPL_EXT_SUPPORT
was configured. EXTFS is the default filesystem selected in imx6_spl.h
and the function should return MMCSD_MODE_FS instead.

Fix this and return MMCSD_MODE_FS instead in such cases.

Signed-off-by: Petr Kulhavy <brain@jikos.cz>
CC: Stefano Babic <sbabic@denx.de>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Fabio Estevam <Fabio.Estevam@freescale.com>

diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index bdcda7d..0c1e401 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -76,7 +76,7 @@ u32 spl_boot_mode(const u32 boot_device)
 	/* for MMC return either RAW or FAT mode */
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 		return MMCSD_MODE_FS;
 #elif defined(CONFIG_SUPPORT_EMMC_BOOT)
 		return MMCSD_MODE_EMMCBOOT;
-- 
cgit v0.10.2


From c133c503ac9e037ccbc1b7a37c07c4068b32d802 Mon Sep 17 00:00:00 2001
From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Date: Thu, 16 Jun 2016 14:02:56 +0200
Subject: ARM: board: cm-fx6: fix mmc for old revisions of utilite

Old revisions of Utilite (based on cm-fx6) do not have a dedicated
card detect pin. But the card is removable by the user and card
detection can be realized with polling (e.g. supported by Linux).

Add the broken-cd property to the mmc device tree instead of the
non-removable property to make card detection possible if polling
is supported.

Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index a21e7b0..712057a 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -610,7 +610,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 		fdt_shrink_to_minimum(blob); /* Make room for new properties */
 		nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
 		fdt_delprop(blob, nodeoffset, "cd-gpios");
-		fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable",
+		fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
 				     NULL, 0, 1);
 		fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
 				     NULL, 0, 1);
-- 
cgit v0.10.2


From a32b4a03c717e37561505297a39ed02313e654af Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Mon, 6 Jun 2016 11:14:19 +0200
Subject: pcie_imx: increment timeout for link up

On some boards, the current 20ms timeout
is hit. Increase it to 40mS.

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index c14bb0a..732d59d 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -595,7 +595,7 @@ static int imx_pcie_link_up(void)
 	while (!imx6_pcie_link_up()) {
 		udelay(10);
 		count++;
-		if (count >= 2000) {
+		if (count >= 4000) {
 #ifdef CONFIG_PCI_SCAN_SHOW
 			puts("PCI:   pcie phy link never came up\n");
 #endif
-- 
cgit v0.10.2


From 0750701a3f74e831b6cb0ecc69be2f7eff94e819 Mon Sep 17 00:00:00 2001
From: Hannes Schmelzer <oe5hpm@oevsv.at>
Date: Wed, 22 Jun 2016 12:07:14 +0200
Subject: driver/net/fec: support fixed speed connection

If MAC is directly connected to another MAC (like a switch for example)
we don't need to probe for a phy, autoneogation and so on. We simply
have to setup speed.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc
index ed7e47d..9ca6ac2 100644
--- a/doc/README.fec_mxc
+++ b/doc/README.fec_mxc
@@ -27,6 +27,11 @@ CONFIG_FEC_MXC_PHYADDR
 	Optional, selects the exact phy address that should be connected
 	and function fecmxc_initialize will try to initialize it.
 
+CONFIG_FEC_FIXED_SPEED
+	Optional, selects a fixed speed on the MAC interface without asking some
+	phy. This is usefull if there is a direct MAC <-> MAC connection, for
+	example if the CPU is connected directly via the RGMII interface to a
+	ethernet-switch.
 
 Reading the ethaddr from the SoC eFuses:
 if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 360f8e4..e871b3e 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -233,6 +233,7 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	return ret;
 }
 
+#ifndef CONFIG_FEC_FIXED_SPEED
 static int miiphy_wait_aneg(struct eth_device *dev)
 {
 	uint32_t start;
@@ -260,6 +261,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
 
 	return 0;
 }
+#endif /* CONFIG_FEC_FIXED_SPEED */
 #endif
 
 static int fec_rx_task_enable(struct fec_priv *fec)
@@ -502,6 +504,8 @@ static int fec_open(struct eth_device *edev)
 		}
 		speed = fec->phydev->speed;
 	}
+#elif CONFIG_FEC_FIXED_SPEED
+	speed = CONFIG_FEC_FIXED_SPEED;
 #else
 	miiphy_wait_aneg(edev);
 	speed = miiphy_speed(edev->name, fec->phy_id);
-- 
cgit v0.10.2


From 8be4f40ecfd92257007e82a08e25044b447db18d Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Mon, 6 Jun 2016 11:19:42 +0200
Subject: mx6: add support for el6x board

Custom Board based on MX6 Dual, 1GB RAM and eMMC.

There are two variants of the board with and without
PCIe (ZC5202 and ZC5601).

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 663f970..01117ab 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -178,6 +178,18 @@ config TARGET_XPRESS
 	select DM_THERMAL
 	select SUPPORT_SPL
 
+config TARGET_ZC5202
+	bool "zc5202"
+	select SUPPORT_SPL
+	select DM
+	select DM_THERMAL
+
+config TARGET_ZC5601
+	bool "zc5601"
+	select SUPPORT_SPL
+	select DM
+	select DM_THERMAL
+
 endchoice
 
 config SYS_SOC
@@ -192,6 +204,7 @@ source "board/boundary/nitrogen6x/Kconfig"
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig
new file mode 100644
index 0000000..aa9bf25
--- /dev/null
+++ b/board/el/el6x/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_ZC5202
+
+config SYS_BOARD
+	default "el6x"
+
+config SYS_VENDOR
+	default "el"
+
+config SYS_CONFIG_NAME
+	default "zc5202"
+
+endif
+
+if TARGET_ZC5601
+
+config SYS_BOARD
+	default "el6x"
+
+config SYS_VENDOR
+	default "el"
+
+config SYS_CONFIG_NAME
+	default "zc5601"
+
+endif
diff --git a/board/el/el6x/MAINTAINERS b/board/el/el6x/MAINTAINERS
new file mode 100644
index 0000000..9a40010
--- /dev/null
+++ b/board/el/el6x/MAINTAINERS
@@ -0,0 +1,8 @@
+EL6X BOARD
+M:	Stefano Babic <sbabic@denx.de>
+S:	Maintained
+F:	board/el/el6x/
+F:	include/configs/zc5202.h
+F:	include/configs/zc5601.h
+F:	configs/zc5202_defconfig
+F:	configs/zc5601_defconfig
diff --git a/board/el/el6x/Makefile b/board/el/el6x/Makefile
new file mode 100644
index 0000000..48d5ad9
--- /dev/null
+++ b/board/el/el6x/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) Stefano Babic <sbabic@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := el6x.o
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
new file mode 100644
index 0000000..3b0fb32
--- /dev/null
+++ b/board/el/el6x/el6x.c
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Based on other i.MX6 boards
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <asm/arch/mx6-ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OPEN_PAD_CTRL  (PAD_CTL_ODE  | PAD_CTL_DSE_DISABLE | (0 << 12))
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC	1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define ETH_PHY_RESET	IMX_GPIO_NR(2, 4)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_TARGET_ZC5202
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_GPIO_18__ENET_RX_CLK		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_KEY_COL2__ENET_RX_DATA2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_KEY_COL0__ENET_RX_DATA3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+	MX6_PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO_19__ENET_TX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_KEY_ROW2__ENET_TX_DATA2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__ENET_TX_DATA3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TX_EN__ENET_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RX_ER__ENET_RX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	/* Switch Reset */
+	MX6_PAD_NANDF_D4__GPIO2_IO04		| MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	/* Switch Interrupt */
+	MX6_PAD_NANDF_D5__GPIO2_IO05		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* use CRS and COL pads as GPIOs */
+	MX6_PAD_KEY_COL3__GPIO4_IO12		| MUX_PAD_CTRL(OPEN_PAD_CTRL),
+	MX6_PAD_KEY_ROW1__GPIO4_IO09		| MUX_PAD_CTRL(OPEN_PAD_CTRL),
+
+};
+
+#define BOARD_NAME "EL6x-ZC5202"
+#else
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_NANDF_D4__GPIO2_IO04		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#define BOARD_NAME "EL6x-ZC5601"
+#endif
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+#ifdef CONFIG_TARGET_ZC5202
+	/* set CRS and COL to input */
+	gpio_direction_input(IMX_GPIO_NR(4, 9));
+	gpio_direction_input(IMX_GPIO_NR(4, 12));
+
+	/* Reset Switch */
+	gpio_direction_output(ETH_PHY_RESET , 0);
+	mdelay(2);
+	gpio_set_value(ETH_PHY_RESET, 1);
+#endif
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+#ifdef CONFIG_TARGET_ZC5202
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT15__GPIO5_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi3_pads[] = {
+	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT7__GPIO4_IO28	 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT8__GPIO4_IO29	 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT9__GPIO4_IO30	 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT10__GPIO4_IO31	 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+#endif
+
+iomux_v3_cfg_t const ecspi4_pads[] = {
+	MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D20__GPIO3_IO20  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+		? (IMX_GPIO_NR(3, 20)) : -1;
+}
+
+static void setup_spi(void)
+{
+#ifdef CONFIG_TARGET_ZC5202
+	gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
+	gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
+	gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
+	gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+#endif
+
+	gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
+	gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
+	imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+
+	enable_spi_clk(true, 3);
+}
+#endif
+
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
+		.gp = IMX_GPIO_NR(7, 11)
+	}
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__SD2_CD_B	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = 1; /* eMMC/uSDHC4 is always present */
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+	int ret;
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    SD2
+	 * mmc1                    SD3
+	 * mmc2                    eMMC
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_direction_input(USDHC2_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+#else
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x1:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x3:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+
+}
+#endif
+
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+	enable_enet_clk(1);
+
+	return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+
+	setup_iomux_uart();
+	setup_spi();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Increase VGEN3 from 2.5 to 2.8V */
+	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
+	reg &= ~LDO_VOL_MASK;
+	reg |= LDOB_2_80V;
+	pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+
+	/* Increase VGEN5 from 2.8 to 3V */
+	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
+	reg &= ~LDO_VOL_MASK;
+	reg |= LDOB_3_00V;
+	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	setenv("board_name", BOARD_NAME);
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts(BOARD_NAME "\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 =  0x00020030,
+	.dram_sdclk_1 =  0x00020030,
+	.dram_cas =  0x00020030,
+	.dram_ras =  0x00020030,
+	.dram_reset =  0x00020030,
+	.dram_sdcke0 =  0x00003000,
+	.dram_sdcke1 =  0x00003000,
+	.dram_sdba2 =  0x00000000,
+	.dram_sdodt0 =  0x00003030,
+	.dram_sdodt1 =  0x00003030,
+	.dram_sdqs0 =  0x00000030,
+	.dram_sdqs1 =  0x00000030,
+	.dram_sdqs2 =  0x00000030,
+	.dram_sdqs3 =  0x00000030,
+	.dram_sdqs4 =  0x00000030,
+	.dram_sdqs5 =  0x00000030,
+	.dram_sdqs6 =  0x00000030,
+	.dram_sdqs7 =  0x00000030,
+	.dram_dqm0 =  0x00020030,
+	.dram_dqm1 =  0x00020030,
+	.dram_dqm2 =  0x00020030,
+	.dram_dqm3 =  0x00020030,
+	.dram_dqm4 =  0x00020030,
+	.dram_dqm5 =  0x00020030,
+	.dram_dqm6 =  0x00020030,
+	.dram_dqm7 =  0x00020030,
+};
+
+const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type =  0x000C0000,
+	.grp_ddrmode_ctl =  0x00020000,
+	.grp_ddrpke =  0x00000000,
+	.grp_addds =  0x00000030,
+	.grp_ctlds =  0x00000030,
+	.grp_ddrmode =  0x00020000,
+	.grp_b0ds =  0x00000030,
+	.grp_b1ds =  0x00000030,
+	.grp_b2ds =  0x00000030,
+	.grp_b3ds =  0x00000030,
+	.grp_b4ds =  0x00000030,
+	.grp_b5ds =  0x00000030,
+	.grp_b6ds =  0x00000030,
+	.grp_b7ds =  0x00000030,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x001F001F,
+	.p0_mpwldectrl1 =  0x001F001F,
+	.p1_mpwldectrl0 =  0x00440044,
+	.p1_mpwldectrl1 =  0x00440044,
+	.p0_mpdgctrl0 =  0x434B0350,
+	.p0_mpdgctrl1 =  0x034C0359,
+	.p1_mpdgctrl0 =  0x434B0350,
+	.p1_mpdgctrl1 =  0x03650348,
+	.p0_mprddlctl =  0x4436383B,
+	.p1_mprddlctl =  0x39393341,
+	.p0_mpwrdlctl =  0x35373933,
+	.p1_mpwrdlctl =  0x48254A36,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+/*
+ * This section requires the differentiation between iMX6 Sabre boards, but
+ * for now, it will configure only for the mx6q variant.
+ */
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type = DDR_TYPE_DDR3,
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+#endif
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
new file mode 100644
index 0000000..2ebeec0
--- /dev/null
+++ b/configs/zc5202_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_ZC5202=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
new file mode 100644
index 0000000..a52ae6f
--- /dev/null
+++ b/configs/zc5601_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_ZC5601=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
new file mode 100644
index 0000000..55ef612
--- /dev/null
+++ b/include/configs/el6x_common.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EL6Q_COMMON_CONFIG_H
+#define __EL6Q_COMMON_CONFIG_H
+
+#define CONFIG_BOARD_NAME		EL6Q
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#define CONFIG_IMX_THERMAL
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+#include "imx6_spl.h"
+#endif
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* I2C config */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED			100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* Commands */
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		3
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		20000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONFIG_BAUDRATE             115200
+
+/* Command definition */
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOARD_NAME	EL6Q
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS                                               \
+	"board="__stringify(CONFIG_BOARD_NAME)"\0"                              \
+	"cma_size="__stringify(EL6Q_CMA_SIZE)"\0"                               \
+	"chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0"                     \
+	"console=" CONFIG_CONSOLE_DEV "\0" 					\
+	"fdtfile=undefined\0" \
+	"fdt_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0"                  \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(PXE, PXE, na) \
+	func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+	   "run findfdt; " \
+	   "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10800000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x0
+#endif
+
+#endif                         /* __EL6Q_COMMON_CONFIG_H */
diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h
new file mode 100644
index 0000000..073a42c
--- /dev/null
+++ b/include/configs/zc5202.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EL_ZC5202_H
+#define __EL_ZC5202_H
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc1"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+
+#define CONFIG_DEFAULT_FDT_FILE	"imx6q-zc5202.dtb"
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#include "el6x_common.h"
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE				ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE			MII100
+#define CONFIG_ETHPRIME				"FEC"
+#define CONFIG_FEC_MXC_PHYADDR			0
+#define CONFIG_MV88E6352_SWITCH
+
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+
+#endif                         /*__EL6Q_CONFIG_H */
diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h
new file mode 100644
index 0000000..28b9c6b
--- /dev/null
+++ b/include/configs/zc5601.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EL_ZC5601_H
+#define __EL_ZC5601_H
+
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc1"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p1"
+
+#define CONFIG_DEFAULT_FDT_FILE	"imx6q-zc5601.dtb"
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#include "el6x_common.h"
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE				ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE			RGMII
+#define CONFIG_ETHPRIME				"FEC"
+#define CONFIG_FEC_MXC_PHYADDR			0x10
+#define CONFIG_PHYLIB
+#define CONFIG_FEC_FIXED_SPEED			1000 /* No autoneg, fix Gb */
+
+#endif                         /*__EL6Q_CONFIG_H */
-- 
cgit v0.10.2


From 876a25d289cf9ae6b052ea0dc61b7522e1dec4e1 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 8 Jun 2016 10:50:20 +0200
Subject: mx6: Add Phytec PCM058 i.MX6 Quad

Add Phytec-i.MX6 SOM with NAND

  Support:
   - 1GB RAM
   - Ethernet
   - SPI-NOR Flash
   - NAND (1024 MB)
   - external SD
   - UART

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 01117ab..78383f0 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -148,6 +148,10 @@ config TARGET_PLATINUM_TITANIUM
 	bool "platinum-titanium"
 	select SUPPORT_SPL
 
+config TARGET_PCM058
+	bool "Phytec PCM058 i.MX6 Quad"
+	select SUPPORT_SPL
+
 config TARGET_SECOMX6
 	bool "secomx6 boards"
 
@@ -213,6 +217,7 @@ source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/seco/Kconfig"
diff --git a/board/phytec/pcm058/Kconfig b/board/phytec/pcm058/Kconfig
new file mode 100644
index 0000000..d099275
--- /dev/null
+++ b/board/phytec/pcm058/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PCM058
+
+config SYS_BOARD
+	default "pcm058"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcm058"
+
+endif
diff --git a/board/phytec/pcm058/MAINTAINERS b/board/phytec/pcm058/MAINTAINERS
new file mode 100644
index 0000000..b0ca402
--- /dev/null
+++ b/board/phytec/pcm058/MAINTAINERS
@@ -0,0 +1,6 @@
+PHYTEC PHYBOARD MIRA
+M:	Stefano Babic <sbabic@denx.de>
+S:	Maintained
+F:	board/phytec/pcm058/
+F:	include/configs/pcm058.h
+F:	configs/pcm058_defconfig
diff --git a/board/phytec/pcm058/Makefile b/board/phytec/pcm058/Makefile
new file mode 100644
index 0000000..97733b1
--- /dev/null
+++ b/board/phytec/pcm058/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pcm058.o
diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README
new file mode 100644
index 0000000..3327135
--- /dev/null
+++ b/board/phytec/pcm058/README
@@ -0,0 +1,35 @@
+Board information
+-----------------
+
+The SBC produced by Phytec has a SOM based on a i.MX6Q.
+The SOM is sold in two versions, with eMMC or with NAND. Support
+here is for the SOM with NAND.
+The evaluation board "phyBoard-Mira" is thought to be used
+together with the SOM.
+
+More information on the board can be found on manufacturer's
+website:
+
+http://www.phytec.de/produkt/single-board-computer/phyboard-mira/
+http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf
+
+Building U-Boot
+-------------------------------
+
+$ make pcm058_defconfig
+$ make
+
+This generates the artifacts SPL and u-boot.img.
+The SOM can boot from NAND or from SD-Card, having the SPI-NOR
+as second option.
+The dip switch "DIP-1" on the board let choose between
+NAND and SD.
+
+DIP-1 set to off:	Boot first from NAND, then try SPI
+DIP-1 set to on:	Boot first from SD, then try SPI
+
+The bootloader was tested with DIP-1 set to on. If a SD-card
+is present, then the RBL tries to load SPL from the SD Card, if not,
+RBL loads from SPI-NOR. The SPL tries then to load from the same
+device where SPL was loaded (SD or SPI). Booting from NAND is
+not supported.
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
new file mode 100644
index 0000000..0ba4a2e
--- /dev/null
+++ b/board/phytec/pcm058/pcm058.c
@@ -0,0 +1,582 @@
+/*
+ * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Please note: there are two version of the board
+ * one with NAND and the other with eMMC.
+ * Both NAND and eMMC cannot be set because they share the
+ * same pins (SD4)
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |	\
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(6, 31)
+#define USER_LED	IMX_GPIO_NR(1, 4)
+#define IMX6Q_DRIVE_STRENGTH	0x30
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+void board_turn_off_led(void)
+{
+	gpio_direction_output(USER_LED, 0);
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__GPIO1_IO14	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* NAND */
+static iomux_v3_cfg_t const nfc_pads[] = {
+	MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CS2__NAND_CE2_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CS3__NAND_CE3_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+
+
+/* GPIOS */
+static iomux_v3_cfg_t const gpios_pads[] = {
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{.esdhc_base = USDHC1_BASE_ADDR,
+	.max_bus_width = 4},
+#ifndef CONFIG_CMD_NAND
+	{USDHC4_BASE_ADDR},
+#endif
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+#ifndef CONFIG_CMD_NAND
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = 1; /* eMMC/uSDHC4 is always present */
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+	int ret;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+#ifndef CONFIG_CMD_NAND
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+#endif
+		default:
+			printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+#else
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x0:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+		gpio_direction_input(USDHC1_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		usdhc_cfg[0].max_bus_width = 4;
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	}
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
+	mdelay(10);
+	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+	mdelay(30);
+}
+
+static void setup_spi(void)
+{
+	gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
+	gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+
+	enable_spi_clk(true, 0);
+}
+
+#ifdef CONFIG_CMD_NAND
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+
+	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
+	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable ENFC_CLK_ROOT clock */
+	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus != 0 || (cs != 0))
+		return -EINVAL;
+
+	return IMX_GPIO_NR(3, 19);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+
+	return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	setup_gpmi_nand();
+#endif
+	return 0;
+}
+
+
+#ifdef CONFIG_CMD_BMODE
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ *  BOOT_CFG1[7] = 1 (boot from NAND)
+ *  BOOT_CFG1[5] = 0 - raw NAND
+ *  BOOT_CFG1[4] = 0 - default pad settings
+ *  BOOT_CFG1[3:2] = 00 - devices = 1
+ *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ *  BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+	{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
+	{"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00000030,
+	.dram_sdcke1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type =  0x000C0000,
+	.grp_ddrmode_ctl =  0x00020000,
+	.grp_ddrpke =  0x00000000,
+	.grp_addds = IMX6Q_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6Q_DRIVE_STRENGTH,
+	.grp_ddrmode =  0x00020000,
+	.grp_b0ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6Q_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6Q_DRIVE_STRENGTH,
+};
+
+static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 =  0x00140014,
+	.p0_mpwldectrl1 =  0x000A0015,
+	.p1_mpwldectrl0 =  0x000A001E,
+	.p1_mpwldectrl1 =  0x000A0015,
+	.p0_mpdgctrl0 =  0x43080314,
+	.p0_mpdgctrl1 =  0x02680300,
+	.p1_mpdgctrl0 =  0x430C0318,
+	.p1_mpdgctrl1 =  0x03000254,
+	.p0_mprddlctl =  0x3A323234,
+	.p1_mprddlctl =  0x3E3C3242,
+	.p0_mpwrdlctl =  0x2A2E3632,
+	.p1_mpwrdlctl =  0x3C323E34,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT       = 1,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.ddr_type = DDR_TYPE_DDR3,
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	printf("Boot device %x\n", spl_boot_list[0]);
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_SPI:
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+		spl_boot_list[2] = BOOT_DEVICE_UART;
+		break;
+	default:
+		printf("Boot device %x\n", spl_boot_list[0]);
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_CMD_NAND
+	/* Enable NAND */
+	setup_gpmi_nand();
+#endif
+
+	/* setup clock gating */
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* setup AXI */
+	gpr_init();
+
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	setup_spi();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
new file mode 100644
index 0000000..1576745
--- /dev/null
+++ b/configs/pcm058_defconfig
@@ -0,0 +1,34 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_PCM058=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_HUSH_PARSER=y
+CONFIG_MTD=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=n
+CONFIG_CMD_DFU=n
+CONFIG_CMD_USB_MASS_STORAGE=n
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FIT=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
new file mode 100644
index 0000000..97cbeba
--- /dev/null
+++ b/include/configs/pcm058.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __PCM058_CONFIG_H
+#define __PCM058_CONFIG_H
+
+#include <config_distro_defaults.h>
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_DMA_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#include "imx6_spl.h"
+#endif
+
+#include "mx6_common.h"
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc1"
+
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+
+/* Early setup */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		3
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_KSZ9031
+
+/* SPI Flash */
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		20000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+/* Enable NAND support */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* Filesystem support */
+#define CONFIG_LZO
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT    "nand0=nand"
+#define MTDPARTS_DEFAULT  "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
+
+/* Various command support */
+#define CONFIG_CMD_BMODE         /* set eFUSE shadow for a boot dev and reset */
+#define CONFIG_CMD_HDMIDETECT    /* detect HDMI output device */
+#define CONFIG_CMD_GSC
+#define CONFIG_CMD_EECONFIG      /* Gateworks EEPROM config cmd */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+/* Environment organization */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                (16 * 1024)
+#define CONFIG_ENV_OFFSET		(1024 * SZ_1K)
+#define CONFIG_ENV_SECT_SIZE		(64 * SZ_1K)
+#define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              (0x1E0000)
+#define CONFIG_ENV_SECT_SIZE           (128 * SZ_1K)
+#endif
+
+#endif
-- 
cgit v0.10.2


From 369012e7e96761c1ac4ccb0cd9052c6f56468082 Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Wed, 8 Jun 2016 15:17:54 -0300
Subject: mx6qsabreauto: Avoid hardcoded RAM size

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index d63a979..a3ed4cd 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 6039fc4..200e468 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -13,7 +13,6 @@
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc3"
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"
-#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
 
 /* USB Configs */
 #define CONFIG_USB_EHCI
-- 
cgit v0.10.2


From e355eec79dd150d6f44e52357b5e805aed6ebc4a Mon Sep 17 00:00:00 2001
From: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
Date: Thu, 9 Jun 2016 10:33:27 +0200
Subject: wandboard: enable SATA with imx6q

Signed-off-by: Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 4ce74cd..8340dd1 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -345,6 +345,12 @@ int board_early_init_f(void)
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
+#ifdef CONFIG_CMD_SATA
+	/* Only mx6q wandboard has SATA */
+	if (is_cpu_type(MXC_CPU_MX6Q))
+		setup_sata();
+#endif
+
 	return 0;
 }
 
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 99f5c0c..92af6543 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -28,6 +28,18 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
+/* SATA Configs */
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 /* Command definition */
 #define CONFIG_CMD_BMODE
 
-- 
cgit v0.10.2


From 8259e9c9adc263a3e9619bd4713dfddea19509b8 Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Thu, 9 Jun 2016 15:28:31 -0300
Subject: mx6slevk: Avoid hardcoded RAM size

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 256d602..f978e50 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -61,7 +61,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index d53e416..375aa0e 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -137,7 +137,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			SZ_1G
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-- 
cgit v0.10.2


From 432a8a55478d431e036e695c3f8b9d9e2536f744 Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Thu, 9 Jun 2016 15:28:32 -0300
Subject: mx6sxsabreauto: Avoid hardcoded RAM size

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 886373c..44e6a7d 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -106,7 +106,7 @@ static int port_exp_direction_output(unsigned gpio, int value)
 
 int dram_init(void)
 {
-	gd->ram_size = PHYS_SDRAM_SIZE;
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index d771f9d..439579d 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -103,7 +103,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			SZ_2G
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-- 
cgit v0.10.2


From d6b0c468189fad76addd09e9796e87ab61c227df Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Thu, 9 Jun 2016 15:28:33 -0300
Subject: mx6sxsabresd: Avoid hardcoded RAM size

Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 25e009e..8d95c51 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = PHYS_SDRAM_SIZE;
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 183a759..9281fee 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -132,7 +132,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			SZ_1G
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-- 
cgit v0.10.2


From 303977430983f163c30a8937de737d1d6abe78ba Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Fri, 10 Jun 2016 09:46:12 -0300
Subject: mx7: Place MX7_SEC option in Kconfig

MX7_SEC is an existing configuration option that allows booting the
kernel in secure mode.

Place this option in Kconfig, so that boards can select this option
in their defconfig files.

Selecting this option is necessary when booting a kernel provided by
NXP, such as 3.14_GA and 4.1.15_GA.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Michael Trimarchi <michael@amarulasolutions.com>

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index 1b7da5a..c6b38bc 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -17,3 +17,12 @@ config IMX_BOOTAUX
 	depends on ARCH_MX7 || ARCH_MX6
 	help
 	  bootaux [addr] to boot auxiliary core.
+
+config MX7_SEC
+	bool "Support booting MX7 in secure mode"
+	depends on ARCH_MX7
+	help
+	  NXP kernel requires to boot MX7 in secure mode. Select
+	  this options if you want to boot a NXP kernel. In order
+	  to boot a mainline kernel this option needs to be
+	  unselected.
-- 
cgit v0.10.2


From 618a85356cebe18c8933147fe913a5fe17260332 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Fri, 10 Jun 2016 09:46:13 -0300
Subject: mx7dsabresd: Fix the boot of a NXP kernel

Booting a NXP kernel with mainline U-boot leads to the following kernel
crash:

caam: probe of 30900000.caam failed with error -11
Unable to handle kernel NULL pointer dereference at virtual address 00000004
pgd = 80004000
[00000004] *pgd=00000000
Internal error: Oops: 805 [#1] PREEMPT SMP ARM

This happens because NXP kernel expects MX7 to boot in secure mode,
so introduce mx7dsabresd_secure_defconfig that selects CONFIG_MX7_SEC
and allows booting a NXP provided kernel successfully.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig
new file mode 100644
index 0000000..9e49004
--- /dev/null
+++ b/configs/mx7dsabresd_secure_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_OF_LIBFDT=y
+CONFIG_MX7_SEC=y
-- 
cgit v0.10.2


From 6d7aa51accd3ae19ad25259f46a6043ef3f02ce2 Mon Sep 17 00:00:00 2001
From: Diego Dorta <diego.dorta@nxp.com>
Date: Fri, 10 Jun 2016 12:07:29 -0300
Subject: pico-imx6ul: Add Ethernet support

Pico-imx6ul has a KSZ8081 Ethernet PHY.

Add support for it.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c
index c038d43..fc746ec 100644
--- a/board/technexion/pico-imx6ul/pico-imx6ul.c
+++ b/board/technexion/pico-imx6ul/pico-imx6ul.c
@@ -16,6 +16,8 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/io.h>
 #include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
 #include <fsl_esdhc.h>
 #include <linux/sizes.h>
 #include <usb.h>
@@ -34,6 +36,87 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
+
+static iomux_v3_cfg_t const fec_pads[] = {
+	MX6_PAD_ENET1_TX_EN__ENET2_MDC		| MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO	| MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART4_TX_DATA__GPIO1_IO28	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_fec();
+
+	gpio_direction_output(RMII_PHY_RESET, 0);
+	/*
+	 * According to KSZ8081MNX-RNB manual:
+	 * For warm reset, the reset (RST#) pin should be asserted low for a
+	 * minimum of 500μs.  The strap-in pin values are read and updated
+	 * at the de-assertion of reset.
+	 */
+	udelay(500);
+
+	gpio_direction_output(RMII_PHY_RESET, 1);
+	/*
+	 * According to KSZ8081MNX-RNB manual:
+	 * After the de-assertion of reset, wait a minimum of 100μs before
+	 * starting programming on the MIIM (MDC/MDIO) interface.
+	 */
+	udelay(100);
+
+	return fecmxc_initialize(bis);
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -106,6 +189,7 @@ int board_init(void)
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	setup_fec();
 	setup_usb();
 
 	return 0;
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index d848ead..73e37e1 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -17,6 +17,16 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+/* Network support */
+
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
 
-- 
cgit v0.10.2


From af07d1544e3e61cb311432dc20b24053dc1318aa Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Wed, 15 Jun 2016 12:48:14 -0300
Subject: pico-imx6ul: Add DFU support

DFU is a convenient way to program U-boot binary into the eMMC.

Add support for it.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index ab9c9f1..e202159 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -10,6 +10,7 @@ CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
@@ -21,4 +22,11 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 73e37e1..db78a54 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -28,7 +28,7 @@
 #define CONFIG_PHY_MICREL
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M) /* Increase due to DFU */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
@@ -63,6 +63,11 @@
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
 #define CONFIG_G_DNL_VENDOR_NUM		0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
 #define CONFIG_G_DNL_MANUFACTURER	"FSL"
@@ -86,6 +91,7 @@
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
+	"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-- 
cgit v0.10.2


From dab149345930b9b5bdc55e88d761d8494c692aa2 Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Wed, 15 Jun 2016 12:48:15 -0300
Subject: pico-imx6ul: Add a README file

Add a README file to help users to install U-boot binary into the eMMC.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/technexion/pico-imx6ul/README b/board/technexion/pico-imx6ul/README
new file mode 100644
index 0000000..2f66095
--- /dev/null
+++ b/board/technexion/pico-imx6ul/README
@@ -0,0 +1,57 @@
+How to Update U-Boot on Pico-imx6ul board
+-----------------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+- dfu-util: http://dfu-util.sourceforge.net/releases/
+
+Build U-Boot for Pico:
+
+$ make mrproper
+$ make pico-imx6ul_defconfig
+$ make
+
+This will generate the U-Boot binary called u-boot.imx.
+
+Put pico board in USB download mode (refer to the document
+http://www.wandboard.org/images/hobbit/hobbitboard-imx6ul-reva1.pdf page 15)
+
+Connect a USB to serial adapter between the host PC and pico
+
+Connect a USB cable between the OTG pico port and the host PC
+
+Open a terminal program such as minicom
+
+Copy u-boot.imx to the imx_usb_loader folder.
+
+Load u-boot.imx via USB:
+
+$ sudo ./imx_usb u-boot.imx
+
+Then U-Boot should start and its messages will appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+Run the DFU command:
+=> dfu 0 mmc 0
+
+Transfer u-boot.imx that will be flashed into the eMMC:
+
+$ sudo dfu-util -D u-boot.imx -a boot
+
+Then on the U-Boot prompt the following message should be seen after a
+successful upgrade:
+
+#DOWNLOAD ... OK
+Ctrl+C to exit ...
+
+Remove power from the pico board.
+
+Put pico board into normal boot mode
+
+Power up the board and the new updated U-Boot should boot from eMMC.
-- 
cgit v0.10.2


From d0daec670fc3747f99dce69bc508ef2cfc44e769 Mon Sep 17 00:00:00 2001
From: Diego Dorta <diego.dorta@nxp.com>
Date: Wed, 15 Jun 2016 13:53:41 -0300
Subject: pico-imx6ul: Add NFS boot support

Add script for retrieving the kernel via TFTP and mounting the
rootfs via NFS.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index db78a54..f8fe230 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -102,7 +102,31 @@
 			"bootz ${loadaddr} - ${fdt_addr}; " \
 		"else " \
 			"echo WARN: Cannot load the DT; " \
-		"fi;\0"
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
 
 #define CONFIG_BOOTCOMMAND \
 	   "if mmc rescan; then " \
-- 
cgit v0.10.2


From ca103e09960cb09a0501e558bfa9c921fb61d0bc Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Mon, 13 Jun 2016 13:01:38 -0300
Subject: pico-imx6ul: Add USB Host support

Add USB host support.

Tested by connecting a USB pen drive:

=> usb start
starting USB...
USB0:   Port not available.
USB1:   USB EHCI 1.00
scanning bus 1 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c
index fc746ec..b0b8f05 100644
--- a/board/technexion/pico-imx6ul/pico-imx6ul.c
+++ b/board/technexion/pico-imx6ul/pico-imx6ul.c
@@ -142,6 +142,9 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
 static iomux_v3_cfg_t const usb_otg_pad[] = {
 	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 };
@@ -181,7 +184,26 @@ int board_early_init_f(void)
 
 int board_usb_phy_mode(int port)
 {
-	return USB_INIT_DEVICE;
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return USB_INIT_DEVICE;
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
 }
 
 int board_init(void)
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index f8fe230..f9fc263 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -52,7 +52,7 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS		0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Only OTG1 port enabled */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-- 
cgit v0.10.2


From 225126da99dd9ba1478e32468e298085d1e3fb61 Mon Sep 17 00:00:00 2001
From: Hannes Schmelzer <oe5hpm@oevsv.at>
Date: Wed, 22 Jun 2016 12:07:46 +0200
Subject: arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6 duallite

if we build for an i.mx6 (d)ual(l)ite CONFIC_MX6DL we shall use
MX6DL_PAD instead the common MX6_PAD.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>

diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 4b6bb18..3465205 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -18,7 +18,7 @@ enum {
 #include "mx6q_pins.h"
 #undef MX6_PAD_DECL
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
-	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
+	MX6_PAD_DECLARE(MX6DL_PAD_, name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
 #elif defined(CONFIG_MX6Q)
@@ -30,7 +30,7 @@ enum {
 #elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
-	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+	MX6_PAD_DECLARE(MX6DL_PAD_, name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
 #elif defined(CONFIG_MX6SL)
-- 
cgit v0.10.2


From 1f1756279604c3c77933ef2a7db745dc1d22a95c Mon Sep 17 00:00:00 2001
From: Peng Fan <van.freenix@gmail.com>
Date: Thu, 30 Jun 2016 21:08:00 +0800
Subject: imx6: clock: typo fix

Typo fix, "PPL2 -> PLL2"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ff932aa..9b4b69c 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -281,7 +281,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 	case PLL_BUS:
 		if (!is_mx6ul()) {
 			if (pfd_num == 3) {
-				/* No PFD3 on PPL2 */
+				/* No PFD3 on PLL2 */
 				return 0;
 			}
 		}
-- 
cgit v0.10.2


From 9a45ec3ea0858026d5715f16e3bdb596057f727e Mon Sep 17 00:00:00 2001
From: Andrej Rosano <andrej@inversepath.com>
Date: Mon, 20 Jun 2016 17:21:48 +0200
Subject: usbarmory: switch to using kernel zImage

Switch to using zImage instead of uImage.

Signed-off-by: Andrej Rosano <andrej@inversepath.com>

diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 8568663..c0e093f 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -69,17 +69,19 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_FSL_IIM
 
-/* Linux boot */
+/* U-Boot memory offsets */
 #define CONFIG_LOADADDR		0x72000000
 #define CONFIG_SYS_TEXT_BASE	0x77800000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Linux boot */
 #define CONFIG_HOSTNAME		usbarmory
 #define CONFIG_BOOTCOMMAND						\
 	"run distro_bootcmd; "						\
 	"setenv bootargs console=${console} ${bootargs_default}; "	\
-	"ext2load mmc 0:1 ${kernel_addr_r} /boot/uImage; "		\
+	"ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; "		\
 	"ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; "		\
-	"bootm ${kernel_addr_r} - ${fdt_addr_r}"
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}"
 
 #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
 
-- 
cgit v0.10.2


From a02ab5eaff966ecf746bc4e90696c84efb4b113b Mon Sep 17 00:00:00 2001
From: Andrej Rosano <andrej@inversepath.com>
Date: Mon, 20 Jun 2016 17:21:49 +0200
Subject: usbarmory: Add board_run_command() function

Define a default board_run_command() function. This function contains
the commands needed to boot the board when CLI is disabled (CONFIG_CMDLINE=n).

Signed-off-by: Andrej Rosano <andrej@inversepath.com>

diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index a809039..c875e78 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c
@@ -415,3 +415,34 @@ int checkboard(void)
 	puts("Board: Inverse Path USB armory MkI\n");
 	return 0;
 }
+
+#ifndef CONFIG_CMDLINE
+static char *ext2_argv[] = {
+	"ext2load",
+	"mmc",
+	"0:1",
+	USBARMORY_FIT_ADDR,
+	USBARMORY_FIT_PATH
+};
+
+static char *bootm_argv[] = {
+	"bootm",
+	USBARMORY_FIT_ADDR
+};
+
+int board_run_command(const char *cmdline)
+{
+	printf("%s %s %s %s %s\n", ext2_argv[0], ext2_argv[1], ext2_argv[2],
+	       ext2_argv[3], ext2_argv[4]);
+
+	if (do_ext2load(NULL, 0, 5, ext2_argv) != 0) {
+		udelay(5*1000*1000);
+		return 1;
+	}
+
+	printf("%s %s\n", bootm_argv[0], bootm_argv[1]);
+	do_bootm(NULL, 0, 2, bootm_argv);
+
+	return 1;
+}
+#endif
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index c0e093f..5484204 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -17,16 +17,13 @@
 #define CONFIG_SYS_FSL_CLK
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MXC_GPIO
+#define CONFIG_SYS_NO_FLASH
 
 #include <asm/arch/imx-regs.h>
 
 #include <config_distro_defaults.h>
 
-/* U-Boot commands */
-
 /* U-Boot environment */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_OFFSET	(6 * 64 * 1024)
 #define CONFIG_ENV_SIZE		(8 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
@@ -101,6 +98,12 @@
 	"console=ttymxc0,115200\0"				\
 	BOOTENV
 
+#ifndef CONFIG_CMDLINE
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 root=/dev/mmcblk0p1 rootwait rw"
+#define USBARMORY_FIT_PATH	"/boot/usbarmory.itb"
+#define USBARMORY_FIT_ADDR	"0x70800000"
+#endif
+
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			CSD0_BASE_ADDR
-- 
cgit v0.10.2


From 3a592a1349ac3961b0f4f2db0a8d9f128225d897 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Thu, 14 Jul 2016 17:36:18 -0400
Subject: Revert "armv8: Enable CPUECTLR.SMPEN for coherency"

Upon further review this breaks most other platforms as we need to check
what core we're running on before touching it at all.

This reverts commit d73718f3236c520a92efa401084c658e6cc067f3.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index dfce469..670e323 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,14 +81,6 @@ reset:
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
 
-	/* Enalbe SMPEN bit for coherency.
-	 * This register is not architectural but at the moment
-	 * this bit should be set for A53/A57/A72.
-	 */
-	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
-	orr     x0, x0, #0x40
-	msr     S3_1_c15_c2_1, x0
-
 	/* Apply ARM core specific erratas */
 	bl	apply_core_errata
 
-- 
cgit v0.10.2


From 6b6024eadb96bc471643bd183fe940fb657bef83 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 27 Jun 2016 19:31:05 +0900
Subject: arm64: add better and more generic spin-table support

There are two enable methods supported by ARM64 Linux; psci and
spin-table.  The latter is simpler and helpful for quick SoC bring
up.  My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.

Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:

  - We must hard-code CPU_RELEASE_ADDR so that it matches the
    "cpu-release-addr" property in the DT that comes from the
    kernel tree.

  - The Documentation/arm64/booting.txt in Linux requires that
    the release address must be zero-initialized, but it is not
    cared by the common code in U-Boot.  We must do it in a board
    function.

  - There is no systematic way to protect the spin-table code from
    the kernel.  We are supposed to do it in a board specific manner,
    but it is difficult to predict where the spin-table code will be
    located after the relocation.  So, it also makes difficult to
    hard-code /memreserve/ in the DT of the kernel.

So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 3d19bbf..acf2460 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -3,4 +3,22 @@ if ARM64
 config ARMV8_MULTIENTRY
         boolean "Enable multiple CPUs to enter into U-Boot"
 
+config ARMV8_SPIN_TABLE
+	bool "Support spin-table enable method"
+	depends on ARMV8_MULTIENTRY && OF_LIBFDT
+	help
+	  Say Y here to support "spin-table" enable method for booting Linux.
+
+	  To use this feature, you must do:
+	    - Specify enable-method = "spin-table" in each CPU node in the
+	      Device Tree you are using to boot the kernel
+	    - Let secondary CPUs in U-Boot (in a board specific manner)
+	      before the master CPU jumps to the kernel
+
+	  U-Boot automatically does:
+	    - Set "cpu-release-addr" property of each CPU node
+	      (overwrites it if already exists).
+	    - Reserve the code for the spin-table and the release address
+	      via a /memreserve/ region in the Device Tree.
+
 endif
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index bf8644c..f6eb9f4 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,9 @@ obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 obj-y	+= fwcall.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
+endif
 
 obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c
new file mode 100644
index 0000000..ec1c9b8
--- /dev/null
+++ b/arch/arm/cpu/armv8/spin_table.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <asm/spin_table.h>
+
+int spin_table_update_dt(void *fdt)
+{
+	int cpus_offset, offset;
+	const char *prop;
+	int ret;
+	unsigned long rsv_addr = (unsigned long)&spin_table_reserve_begin;
+	unsigned long rsv_size = &spin_table_reserve_end -
+						&spin_table_reserve_begin;
+
+	cpus_offset = fdt_path_offset(fdt, "/cpus");
+	if (cpus_offset < 0)
+		return -ENODEV;
+
+	for (offset = fdt_first_subnode(fdt, cpus_offset);
+	     offset >= 0;
+	     offset = fdt_next_subnode(fdt, offset)) {
+		prop = fdt_getprop(fdt, offset, "device_type", NULL);
+		if (!prop || strcmp(prop, "cpu"))
+			continue;
+
+		/*
+		 * In the first loop, we check if every CPU node specifies
+		 * spin-table.  Otherwise, just return successfully to not
+		 * disturb other methods, like psci.
+		 */
+		prop = fdt_getprop(fdt, offset, "enable-method", NULL);
+		if (!prop || strcmp(prop, "spin-table"))
+			return 0;
+	}
+
+	for (offset = fdt_first_subnode(fdt, cpus_offset);
+	     offset >= 0;
+	     offset = fdt_next_subnode(fdt, offset)) {
+		prop = fdt_getprop(fdt, offset, "device_type", NULL);
+		if (!prop || strcmp(prop, "cpu"))
+			continue;
+
+		ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr",
+				(unsigned long)&spin_table_cpu_release_addr);
+		if (ret)
+			return -ENOSPC;
+	}
+
+	ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
+	if (ret)
+		return -ENOSPC;
+
+	printf("   Reserved memory region for spin-table: addr=%lx size=%lx\n",
+	       rsv_addr, rsv_size);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/spin_table_v8.S b/arch/arm/cpu/armv8/spin_table_v8.S
new file mode 100644
index 0000000..d7f78a6
--- /dev/null
+++ b/arch/arm/cpu/armv8/spin_table_v8.S
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(spin_table_secondary_jump)
+.globl spin_table_reserve_begin
+spin_table_reserve_begin:
+0:	wfe
+	ldr	x0, spin_table_cpu_release_addr
+	cbz	x0, 0b
+	br	x0
+.globl spin_table_cpu_release_addr
+	.align	3
+spin_table_cpu_release_addr:
+	.quad	0
+.globl spin_table_reserve_end
+spin_table_reserve_end:
+ENDPROC(spin_table_secondary_jump)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..67edf94 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -94,7 +94,11 @@ reset:
 	/* Processor specific initialization */
 	bl	lowlevel_init
 
-#ifdef CONFIG_ARMV8_MULTIENTRY
+#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
+	branch_if_master x0, x1, master_cpu
+	b	spin_table_secondary_jump
+	/* never return */
+#elif defined(CONFIG_ARMV8_MULTIENTRY)
 	branch_if_master x0, x1, master_cpu
 
 	/*
@@ -106,10 +110,8 @@ slave_cpu:
 	ldr	x0, [x1]
 	cbz	x0, slave_cpu
 	br	x0			/* branch to the given address */
-master_cpu:
-	/* On the master CPU */
 #endif /* CONFIG_ARMV8_MULTIENTRY */
-
+master_cpu:
 	bl	_main
 
 #ifdef CONFIG_SYS_RESET_SCTRL
diff --git a/arch/arm/include/asm/spin_table.h b/arch/arm/include/asm/spin_table.h
new file mode 100644
index 0000000..8b57539
--- /dev/null
+++ b/arch/arm/include/asm/spin_table.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_SPIN_TABLE_H__
+#define __ASM_SPIN_TABLE_H__
+
+extern u64 spin_table_cpu_release_addr;
+extern char spin_table_reserve_begin;
+extern char spin_table_reserve_end;
+
+int spin_table_update_dt(void *fdt);
+
+#endif /* __ASM_SPIN_TABLE_H__ */
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 76b75d8..2c0b56a 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -21,6 +21,7 @@
 #include <asm/armv7.h>
 #endif
 #include <asm/psci.h>
+#include <asm/spin_table.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,6 +46,12 @@ int arch_fixup_fdt(void *blob)
 	if (ret)
 		return ret;
 
+#ifdef CONFIG_ARMV8_SPIN_TABLE
+	ret = spin_table_update_dt(blob);
+	if (ret)
+		return ret;
+#endif
+
 #ifdef CONFIG_ARMV7_NONSEC
 	ret = psci_update_dt(blob);
 	if (ret)
-- 
cgit v0.10.2


From ec6f61003b6cda13b20878a990e5f9b70496d0ad Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Mon, 27 Jun 2016 09:19:16 -0500
Subject: arm: cache: add missing dummy functions for when dcache disabled

Adds missing flush_dcache_range and invalidate_dcache_range dummy
(empty) placeholder functions to the #else portion of the #ifndef
CONFIG_SYS_DCACHE_OFF, where full implementations of these functions
are defined.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index dc309da..24fe0c5 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -195,6 +195,14 @@ void flush_dcache_all(void)
 {
 }
 
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
 void arm_init_before_mmu(void)
 {
 }
-- 
cgit v0.10.2


From 51d0638650646e4e2d87600829fe004cd767756e Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Mon, 27 Jun 2016 09:19:17 -0500
Subject: arm: omap-common: add secure smc entry

Add an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible high-security (HS) device variants. While at it, also
perform minor cleanup/alignment without any change in functionality.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 5283135..66a3b3d 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -16,9 +16,10 @@
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
+.arch_extension sec
+
 #ifdef CONFIG_SPL
 ENTRY(save_boot_params)
-
 	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
 	str	r0, [r1]
 	b	save_boot_params_ret
@@ -26,14 +27,40 @@ ENDPROC(save_boot_params)
 #endif
 
 ENTRY(omap_smc1)
-	PUSH	{r4-r12, lr}	@ save registers - ROM code may pollute
+	push	{r4-r12, lr}	@ save registers - ROM code may pollute
 				@ our registers
-	MOV	r12, r0		@ Service
-	MOV	r0, r1		@ Argument
-	DSB
-	DMB
-	.word	0xe1600070	@ SMC #0 - hand assembled for GCC versions
-				@ call ROM Code API for the service requested
+	mov	r12, r0		@ Service
+	mov	r0, r1		@ Argument
 
-	POP	{r4-r12, pc}
+	dsb
+	dmb
+	smc	0		@ SMC #0 to enter monitor mode
+				@ call ROM Code API for the service requested
+	pop	{r4-r12, pc}
 ENDPROC(omap_smc1)
+
+ENTRY(omap_smc_sec)
+	push	{r4-r12, lr}	@ save registers - ROM code may pollute
+				@ our registers
+	mov	r6, #0xFF	@ Indicate new Task call
+	mov	r12, #0x00	@ Secure Service ID in R12
+
+	dsb
+	dmb
+	smc	0		@ SMC #0 to enter monitor mode
+
+	b	omap_smc_sec_end @ exit at end of the service execution
+	nop
+
+	@ In case of IRQ happening in Secure, then ARM will branch here.
+	@ At that moment, IRQ will be pending and ARM will jump to Non Secure
+	@ IRQ handler
+	mov	r12, #0xFE
+
+	dsb
+	dmb
+	smc	0		@ SMC #0 to enter monitor mode
+
+omap_smc_sec_end:
+	pop	{r4-r12, pc}
+ENDPROC(omap_smc_sec)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 07f3848..605c549 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -627,6 +627,12 @@ void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+/*
+ * Low-level helper function used when performing secure ROM calls on high-
+ * security (HS) device variants by doing a specially-formed smc entry.
+ */
+u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+
 void enable_edma3_clocks(void);
 void disable_edma3_clocks(void);
 
-- 
cgit v0.10.2


From d86f7afda4e2c8fc6aad3095959bee9b1f46c48b Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Mon, 27 Jun 2016 09:19:18 -0500
Subject: arm: omap-common: add secure rom call API for secure devices

Adds a generic C-callable API for making secure ROM calls on OMAP and
OMAP-compatible devices. This API provides the important function of
flushing the ROM call arguments to memory from the cache, so that the
secure world will have a coherent view of those arguments. Then is
simply calls the omap_smc_sec routine.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 87a7ac0..3172bae 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,3 +36,5 @@ obj-y	+= boot-common.o
 obj-y	+= lowlevel_init.o
 
 obj-y	+= mem-common.o
+
+obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o
diff --git a/arch/arm/cpu/armv7/omap-common/sec-common.c b/arch/arm/cpu/armv7/omap-common/sec-common.c
new file mode 100644
index 0000000..4ec736f
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/sec-common.c
@@ -0,0 +1,51 @@
+/*
+ *
+ * Common security related functions for OMAP devices
+ *
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Daniel Allred <d-allred@ti.com>
+ * Andreas Dannenberg <dannenberg@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <stdarg.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+
+static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN);
+
+u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...)
+{
+	int i;
+	u32 num_args;
+	va_list ap;
+
+	va_start(ap, flag);
+
+	num_args = va_arg(ap, u32);
+
+	if (num_args > 4)
+		return 1;
+
+	/* Copy args to aligned args structure */
+	for (i = 0; i < num_args; i++)
+		secure_rom_call_args[i + 1] = va_arg(ap, u32);
+
+	secure_rom_call_args[0] = num_args;
+
+	va_end(ap);
+
+	/* if data cache is enabled, flush the aligned args structure */
+	flush_dcache_range(
+		(unsigned int)&secure_rom_call_args[0],
+		(unsigned int)&secure_rom_call_args[0] +
+		roundup(sizeof(secure_rom_call_args), ARCH_DMA_MINALIGN));
+
+	return omap_smc_sec(service, proc_id, flag, secure_rom_call_args);
+}
diff --git a/arch/arm/include/asm/omap_sec_common.h b/arch/arm/include/asm/omap_sec_common.h
new file mode 100644
index 0000000..1f50f83
--- /dev/null
+++ b/arch/arm/include/asm/omap_sec_common.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andreas Dannenberg <dannenberg@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_OMAP_SEC_COMMON_H_
+#define	_OMAP_SEC_COMMON_H_
+
+#include <common.h>
+
+/*
+ * Invoke secure ROM API on high-security (HS) device variants. It formats
+ * the variable argument list into the format expected by the ROM code before
+ * triggering the actual low-level smc entry.
+ */
+u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...);
+
+#endif /* _OMAP_SEC_COMMON_H_ */
-- 
cgit v0.10.2


From 1bb0a21b465427088ad623826fe23066399cb2d9 Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Mon, 27 Jun 2016 09:19:19 -0500
Subject: arm: omap-common: secure ROM signature verify API

Adds an API that verifies a signature attached to an image (binary
blob). This API is basically a entry to a secure ROM service provided by
the device and accessed via an SMC call, using a particular calling
convention.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/sec-common.c b/arch/arm/cpu/armv7/omap-common/sec-common.c
index 4ec736f..246a239 100644
--- a/arch/arm/cpu/armv7/omap-common/sec-common.c
+++ b/arch/arm/cpu/armv7/omap-common/sec-common.c
@@ -17,6 +17,11 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/omap_sec_common.h>
+#include <asm/spl.h>
+#include <spl.h>
+
+/* Index for signature verify ROM API */
+#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX	(0x0000000E)
 
 static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN);
 
@@ -49,3 +54,86 @@ u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...)
 
 	return omap_smc_sec(service, proc_id, flag, secure_rom_call_args);
 }
+
+static u32 find_sig_start(char *image, size_t size)
+{
+	char *image_end = image + size;
+	char *sig_start_magic = "CERT_";
+	int magic_str_len = strlen(sig_start_magic);
+	char *ch;
+
+	while (--image_end > image) {
+		if (*image_end == '_') {
+			ch = image_end - magic_str_len + 1;
+			if (!strncmp(ch, sig_start_magic, magic_str_len))
+				return (u32)ch;
+		}
+	}
+	return 0;
+}
+
+int secure_boot_verify_image(void **image, size_t *size)
+{
+	int result = 1;
+	u32 cert_addr, sig_addr;
+	size_t cert_size;
+
+	/* Perform cache writeback on input buffer */
+	flush_dcache_range(
+		(u32)*image,
+		(u32)*image + roundup(*size, ARCH_DMA_MINALIGN));
+
+	cert_addr = (uint32_t)*image;
+	sig_addr = find_sig_start((char *)*image, *size);
+
+	if (sig_addr == 0) {
+		printf("No signature found in image!\n");
+		result = 1;
+		goto auth_exit;
+	}
+
+	*size = sig_addr - cert_addr;	/* Subtract out the signature size */
+	cert_size = *size;
+
+	/* Check if image load address is 32-bit aligned */
+	if (!IS_ALIGNED(cert_addr, 4)) {
+		printf("Image is not 4-byte aligned!\n");
+		result = 1;
+		goto auth_exit;
+	}
+
+	/* Image size also should be multiple of 4 */
+	if (!IS_ALIGNED(cert_size, 4)) {
+		printf("Image size is not 4-byte aligned!\n");
+		result = 1;
+		goto auth_exit;
+	}
+
+	/* Call ROM HAL API to verify certificate signature */
+	debug("%s: load_addr = %x, size = %x, sig_addr = %x\n", __func__,
+	      cert_addr, cert_size, sig_addr);
+
+	result = secure_rom_call(
+		API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0,
+		4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF);
+auth_exit:
+	if (result != 0) {
+		printf("Authentication failed!\n");
+		printf("Return Value = %08X\n", result);
+		hang();
+	}
+
+	/*
+	 * Output notification of successful authentication as well the name of
+	 * the signing certificate used to re-assure the user that the secure
+	 * code is being processed as expected. However suppress any such log
+	 * output in case of building for SPL and booting via YMODEM. This is
+	 * done to avoid disturbing the YMODEM serial protocol transactions.
+	 */
+	if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
+	      IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
+	      spl_boot_device() == BOOT_DEVICE_UART))
+		printf("Authentication passed: %s\n", (char *)sig_addr);
+
+	return result;
+}
diff --git a/arch/arm/include/asm/omap_sec_common.h b/arch/arm/include/asm/omap_sec_common.h
index 1f50f83..842f2af 100644
--- a/arch/arm/include/asm/omap_sec_common.h
+++ b/arch/arm/include/asm/omap_sec_common.h
@@ -18,4 +18,13 @@
  */
 u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...);
 
+/*
+ * Invoke a secure ROM API on high-secure (HS) device variants that can be used
+ * to verify a secure blob by authenticating and optionally decrypting it. The
+ * exact operation performed depends on how the certificate that was embedded
+ * into the blob during the signing/encryption step when the secure blob was
+ * first created.
+ */
+int secure_boot_verify_image(void **p_image, size_t *p_size);
+
 #endif /* _OMAP_SEC_COMMON_H_ */
-- 
cgit v0.10.2


From bf9ec864f4f5f52afecfdcea1d258ee4072bdd01 Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Mon, 27 Jun 2016 09:19:20 -0500
Subject: arm: omap-common: Update to generate secure U-Boot FIT blob

Adds commands so that when a secure device is in use and the SPL is
built to load a FIT image (with combined U-Boot binary and various
DTBs), these components that get fed into the FIT are all processed to
be signed/encrypted/etc. as per the operations performed by the
secure-binary-image.sh script of the TI SECDEV package. Furthermore,
perform minor comments cleanup to make better use of the available
space.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk
index c7bb101..1122439 100644
--- a/arch/arm/cpu/armv7/omap-common/config_secure.mk
+++ b/arch/arm/cpu/armv7/omap-common/config_secure.mk
@@ -12,8 +12,8 @@ cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 else
 cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
-    $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
-    $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+	$(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 endif
 else
 cmd_mkomapsecimg = echo "WARNING:" \
@@ -25,14 +25,33 @@ cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
 	"variable must be defined for TI secure devices. $@ was NOT created!"
 endif
 
+ifdef CONFIG_SPL_LOAD_FIT
+quiet_cmd_omapsecureimg = SECURE  $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),)
+cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
+	$< $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_omapsecureimg = echo "WARNING:" \
+	"$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
+	"$@ was NOT created!"; cp $< $@
+endif
+else
+cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+	"variable must be defined for TI secure devices." \
+	"$@ was NOT created!"; cp $< $@
+endif
+endif
+
+
 # Standard X-LOADER target (QPSI, NOR flash)
 u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
-# For MLO targets (SD card boot) the final file name
-# that is copied to the SD card fAT partition must
-# be MLO, so we make a copy of the output file to a
-# new file with that name
+# For MLO targets (SD card boot) the final file name that is copied to the SD
+# card FAT partition must be MLO, so we make a copy of the output file to a new
+# file with that name
 u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 	@if [ -f $@ ]; then \
@@ -51,16 +70,44 @@ u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
 u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
-# For SPI flash on AM335x and AM43xx, these
-# require special byte swap handling so we use
-# the SPI_X-LOADER target instead of X-LOADER
-# and let the create-boot-image.sh script handle
-# that
+# For SPI flash on AM335x and AM43xx, these require special byte swap handling
+# so we use the SPI_X-LOADER target instead of X-LOADER and let the
+# create-boot-image.sh script handle that
 u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
-# For supporting single stage XiP QSPI on AM43xx, the
-# image is a full u-boot file, not an SPL. In this case
-# the mkomapsecimg command looks for a u-boot-HS_* prefix
+# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
+# file, not an SPL. In this case the mkomapsecimg command looks for a
+# u-boot-HS_* prefix
 u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
 	$(call if_changed,mkomapsecimg)
+
+# For supporting the SPL loading and interpreting of FIT images whose
+# components are pre-processed before being integrated into the FIT image in
+# order to secure them in some way
+ifdef CONFIG_SPL_LOAD_FIT
+
+MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
+	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+
+OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+$(OF_LIST_TARGETS): dtbs
+
+%_HS.dtb: %.dtb
+	$(call if_changed,omapsecureimg)
+	$(Q)if [ -f $@ ]; then \
+		cp -f $@ $<; \
+	fi
+
+u-boot-nodtb_HS.bin: u-boot-nodtb.bin
+	$(call if_changed,omapsecureimg)
+
+u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS))
+	$(call if_changed,mkimage)
+	$(Q)if [ -f $@ ]; then \
+		cp -f $@ u-boot.img; \
+	fi
+
+endif
-- 
cgit v0.10.2


From da74d1f341e46ecc0ae893b4aa3b771ce9dba9f3 Mon Sep 17 00:00:00 2001
From: Daniel Allred <d-allred@ti.com>
Date: Mon, 27 Jun 2016 09:19:21 -0500
Subject: spl: fit: add support for post-processing of images

The next stage boot loader image and the selected FDT can be post-
processed by board/platform/device-specific code, which can include
modifying the size and altering the starting source address before
copying these binary blobs to their final destination. This might be
desired to do things like strip headers or footers attached to the
images before they were packaged into the FIT, or to perform operations
such as decryption or authentication. Introduce new configuration
option CONFIG_SPL_FIT_IMAGE_POST_PROCESS to allow controlling this
feature. If enabled, a platform-specific post-process function must
be provided.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/Kconfig b/Kconfig
index 3ceff25..2afbaaf 100644
--- a/Kconfig
+++ b/Kconfig
@@ -313,6 +313,20 @@ config SPL_LOAD_FIT
 	  particular it can handle selecting from multiple device tree
 	  and passing the correct one to U-Boot.
 
+config SPL_FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by the SPL"
+	depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from the U-Boot FIT image like stripping off headers or modifying the
+	  size of the blob, verification, authentication, decryption etc. in a
+	  platform or board specific way. In order to use this feature a platform
+	  or board-specific implementation of board_fit_image_post_process() must
+	  be provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).
+
 config SYS_CLK_FREQ
 	depends on ARC || ARCH_SUNXI
 	int "CPU clock frequency"
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 9874708..069e94d 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -132,7 +132,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	int data_offset, data_size;
 	int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
 	int src_sector;
-	void *dst;
+	void *dst, *src;
 
 	/*
 	 * Figure out where the external images start. This is the base for the
@@ -206,8 +206,13 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 		return -EIO;
 	debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
 	      data_size);
-	memcpy(dst, dst + get_aligned_image_overhead(info, data_offset),
-	       data_size);
+	src = dst + get_aligned_image_overhead(info, data_offset);
+
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+	board_fit_image_post_process((void **)&src, (size_t *)&data_size);
+#endif
+
+	memcpy(dst, src, data_size);
 
 	/* Figure out which device tree the board wants to use */
 	fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
@@ -236,8 +241,14 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 */
 	debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset,
 	      fdt_len);
-	memcpy(load_ptr + data_size,
-	       dst + get_aligned_image_overhead(info, fdt_offset), fdt_len);
+	src = dst + get_aligned_image_overhead(info, fdt_offset);
+	dst = load_ptr + data_size;
+
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+	board_fit_image_post_process((void **)&src, (size_t *)&fdt_len);
+#endif
+
+	memcpy(dst, src, fdt_len);
 
 	return 0;
 }
diff --git a/include/image.h b/include/image.h
index d788c26..93d39e1 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1173,4 +1173,21 @@ void android_print_contents(const struct andr_img_hdr *hdr);
  */
 int board_fit_config_name_match(const char *name);
 
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+/**
+ * board_fit_image_post_process() - Do any post-process on FIT binary data
+ *
+ * This is used to do any sort of image manipulation, verification, decryption
+ * etc. in a platform or board specific way. Obviously, anything done here would
+ * need to be comprehended in how the images were prepared before being injected
+ * into the FIT creation (i.e. the binary blobs would have been pre-processed
+ * before being added to the FIT image).
+ *
+ * @image: pointer to the image start pointer
+ * @size: pointer to the image size
+ * @return no return value (failure should be handled internally)
+ */
+void board_fit_image_post_process(void **p_image, size_t *p_size);
+#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
+
 #endif	/* __IMAGE_H__ */
-- 
cgit v0.10.2


From 17c298733612f68ebf7702f28f32ad78c7ef115e Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Mon, 27 Jun 2016 09:19:22 -0500
Subject: arm: omap5: add U-Boot FIT signing and SPL image post-processing

Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS)
device variants to create a secure u-boot_HS.img FIT blob that contains
U-Boot and DTB artifacts signed with a TI-specific process based on the
CONFIG_TI_SECURE_DEVICE config option and the externally-provided image
signing tool.

Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
index a7e55a5..d245572 100644
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -15,5 +15,8 @@ else
 ALL-y	+= MLO
 endif
 else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-y   += u-boot_HS.img
+endif
 ALL-y	+= u-boot.img
 endif
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 08cf14d..927d136 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -13,6 +13,7 @@
 #include <sata.h>
 #include <usb.h>
 #include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <asm/arch/gpio.h>
@@ -750,3 +751,10 @@ int board_fit_config_name_match(const char *name)
 		return -1;
 }
 #endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+#endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 6a4d027..99e8254 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -17,6 +17,8 @@
 #include <asm/gpio.h>
 #include <usb.h>
 #include <linux/usb/gadget.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/dra7xx_iodelay.h>
 #include <asm/emif.h>
@@ -834,3 +836,10 @@ int board_fit_config_name_match(const char *name)
 		return -1;
 }
 #endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+#endif
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index e01e504..01a4701 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -40,4 +40,5 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_LIST="am57xx-beagle-x15"
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 6933ab5..eb01f41 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -58,4 +58,5 @@ CONFIG_G_DNL_PRODUCT_NUM=0xd022
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_LIST="dra7-evm dra72-evm"
-- 
cgit v0.10.2


From e29878fc47f19e2ad6824cd61c69f2c187c5fb8a Mon Sep 17 00:00:00 2001
From: Madan Srinivas <madans@ti.com>
Date: Mon, 27 Jun 2016 09:19:23 -0500
Subject: arm: am4x: add U-Boot FIT signing and SPL image post-processing

Modify the SPL build procedure for AM437x high-security (HS) device
variants to create a secure u-boot_HS.img FIT blob that contains U-Boot
and DTB artifacts signed (and optionally encrypted) with a TI-specific
process based on the CONFIG_TI_SECURE_DEVICE config option and the
externally-provided image signing tool.

Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.

Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 6d95d32..ab94708 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -26,6 +26,7 @@ endif
 else
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+ALL-y	+= u-boot_HS.img
 endif
 ALL-y	+= u-boot.img
 endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f005762..27c311e 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -13,6 +13,7 @@
 #include <asm/errno.h>
 #include <spl.h>
 #include <usb.h>
+#include <asm/omap_sec_common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mux.h>
@@ -862,3 +863,10 @@ int board_fit_config_name_match(const char *name)
 		return -1;
 }
 #endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+#endif
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 4856a19..68dfb6c 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -13,6 +13,7 @@ CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From 8662bea38e2779a45275a6ac13a378f9f989930a Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Mon, 27 Jun 2016 09:19:24 -0500
Subject: doc: Update info on using secure devices from TI

Adds information regarding SPL handling the loading and processing of
secured u-boot images as part of the second stage boot the SPL does.
Introduces the description of a new interface script in the TI SECDEV
Package which handles the creation and prep of secured binary images.

Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.ti-secure b/doc/README.ti-secure
index 7fc9b9b..54c996d 100644
--- a/doc/README.ti-secure
+++ b/doc/README.ti-secure
@@ -19,69 +19,80 @@ control restrictions. Access must be requested and granted by TI before the
 package is viewable and downloadable. Contact TI, either online or by way
 of a local TI representative, to request access.
 
-When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process requires
-the presence and use of these tools in order to create a viable boot image.
-The build process will look for the environment variable TI_SECURE_DEV_PKG,
-which should be the path of the installed SECDEV package. If the
-TI_SECURE_DEV_PKG variable is not defined or if it is defined but doesn't
-point to a valid SECDEV package, a warning is issued during the build to
-indicate that a final secure bootable image was not created.
-
-Within the SECDEV package exists an image creation script:
-
-${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
-
-This is called as part of the SPL/u-boot build process. As the secure boot
-image formats and requirements differ between secure SOC from TI, the
-purpose of this script is to abstract these details as much as possible.
-
-The script is basically the only required interface to the TI SECDEV package
-for secure TI devices.
-
-Invoking the script for AM43xx Secure Devices
-=============================================
-
-create-boot-image.sh <IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
-
-<IMAGE_FLAG> is a value that specifies the type of the image to generate OR
-the action the image generation tool will take. Valid values are:
-	SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
-	XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
-	ISSW - Generates an image for all other boot modes
-
-<INPUT_FILE> is the full path and filename of the public world boot loader
-binary file (depending on the boot media, this is usually either
-u-boot-spl.bin or u-boot.bin).
-
-<OUTPUT_FILE> is the full path and filename of the final secure image. The
-output binary images should be used in place of the standard non-secure
-binary images (see the platform-specific user's guides and releases notes
-for how the non-secure images are typically used)
+Booting of U-Boot SPL
+=====================
+
+	When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process
+	requires the presence and use of these tools in order to create a
+	viable boot image. The build process will look for the environment
+	variable TI_SECURE_DEV_PKG, which should be the path of the installed
+	SECDEV package. If the TI_SECURE_DEV_PKG variable is not defined or
+	if it is defined but doesn't point to a valid SECDEV package, a
+	warning is issued during the build to indicate that a final secure
+	bootable image was not created.
+
+	Within the SECDEV package exists an image creation script:
+
+	${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
+
+	This is called as part of the SPL/u-boot build process. As the secure
+	boot image formats and requirements differ between secure SOC from TI,
+	the purpose of this script is to abstract these details as much as
+	possible.
+
+	The script is basically the only required interface to the TI SECDEV
+	package for creating a bootable SPL image for secure TI devices.
+
+	Invoking the script for AM43xx Secure Devices
+	=============================================
+
+	create-boot-image.sh \
+		<IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
+
+	<IMAGE_FLAG> is a value that specifies the type of the image to
+	generate OR the action the image generation tool will take. Valid
+	values are:
+		SPI_X-LOADER - Generates an image for SPI flash (byte
+			swapped)
+		XIP_X-LOADER - Generates a single stage u-boot for
+			NOR/QSPI XiP
+		ISSW - Generates an image for all other boot modes
+
+	<INPUT_FILE> is the full path and filename of the public world boot
+	loaderbinary file (depending on the boot media, this is usually
+	either u-boot-spl.bin or u-boot.bin).
+
+	<OUTPUT_FILE> is the full path and filename of the final secure
+	image. The output binary images should be used in place of the standard
+	non-secure binary images (see the platform-specific user's guides and
+	releases notes for how the non-secure images are typically used)
 	u-boot-spl_HS_SPI_X-LOADER - byte swapped boot image for SPI flash
 	u-boot_HS_XIP_X-LOADER - boot image for NOR or QSPI flash
 	u-boot-spl_HS_ISSW - boot image for all other boot media
 
-<SPL_LOAD_ADDR> is the address at which SOC ROM should load the <INPUT_FILE>
+	<SPL_LOAD_ADDR> is the address at which SOC ROM should load the
+	<INPUT_FILE>
 
-Invoking the script for DRA7xx/AM57xx Secure Devices
-====================================================
+	Invoking the script for DRA7xx/AM57xx Secure Devices
+	====================================================
 
-create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE>
+	create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE>
 
-<IMAGE_TYPE> is a value that specifies the type of the image to generate OR
-the action the image generation tool will take. Valid values are:
-	X-LOADER - Generates an image for NOR or QSPI boot modes
-	MLO - Generates an image for SD/MMC/eMMC boot modes
-	ULO - Generates an image for USB/UART peripheral boot modes
-	Note: ULO is not yet used by the u-boot build process
+	<IMAGE_TYPE> is a value that specifies the type of the image to
+	generate OR the action the image generation tool will take. Valid
+	values are:
+		X-LOADER - Generates an image for NOR or QSPI boot modes
+		MLO - Generates an image for SD/MMC/eMMC boot modes
+		ULO - Generates an image for USB/UART peripheral boot modes
+		Note: ULO is not yet used by the u-boot build process
 
-<INPUT_FILE> is the full path and filename of the public world boot loader
-binary file (for this platform, this is always u-boot-spl.bin).
+	<INPUT_FILE> is the full path and filename of the public world boot
+	loader binary file (for this platform, this is always u-boot-spl.bin).
 
-<OUTPUT_FILE> is the full path and filename of the final secure image. The
-output binary images should be used in place of the standard non-secure
-binary images (see the platform-specific user's guides and releases notes
-for how the non-secure images are typically used)
+	<OUTPUT_FILE> is the full path and filename of the final secure image.
+	The output binary images should be used in place of the standard
+	non-secure binary images (see the platform-specific user's guides
+	and releases notes for how the non-secure images are typically used)
 	u-boot-spl_HS_MLO - boot image for SD/MMC/eMMC. This image is
 		copied to a file named MLO, which is the name that
 		the device ROM bootloader requires for loading from
@@ -89,3 +100,61 @@ for how the non-secure images are typically used)
 		non-secure devices)
 	u-boot-spl_HS_X-LOADER - boot image for all other flash memories
 		including QSPI and NOR flash
+
+Booting of Primary U-Boot (u-boot.img)
+======================================
+
+	The SPL image is responsible for loading the next stage boot loader,
+	which is the main u-boot image. For secure TI devices, the SPL will
+	be authenticated, as described above, as part of the particular
+	device's ROM boot process. In order to continue the secure boot
+	process, the authenticated SPL must authenticate the main u-boot
+	image that it loads.
+
+	The configurations for secure TI platforms are written to make the boot
+	process use the FIT image format for the u-boot.img (CONFIG_SPL_FRAMEWORK
+	and CONFIG_SPL_LOAD_FIT). With these configurations the binary
+	components that the SPL loads include a specific DTB image and u-boot
+	image. These DTB image may be one of many available to the boot
+	process. In order to secure these components so that they can be
+	authenticated by the SPL as they are loaded from the FIT image,	the
+	build procedure for secure TI devices will secure these images before
+	they are integrated into the FIT image. When those images are extracted
+	from the FIT image at boot time, they are post-processed to verify that
+	they are still secure. The outlined security-related SPL post-processing
+	is enabled through the CONFIG_SPL_FIT_IMAGE_POST_PROCESS option which
+	must be enabled for the secure boot scheme to work. In order to allow
+	verifying proper operation of the secure boot chain in case of successful
+	authentication messages like "Authentication passed: CERT_U-BOOT-NOD" are
+	output by the SPL to the console for each blob that got extracted from the
+	FIT image. Note that the last part of this log message is the (truncated)
+	name of the signing certificate embedded into the blob that got processed.
+
+	The exact details of the how the images are secured is handled by the
+	SECDEV package. Within the SECDEV package exists a script to process
+	an input binary image:
+
+	${TI_SECURE_DEV_PKG}/scripts/secure-binary-image.sh
+
+	This is called as part of the u-boot build process. As the secure
+	image formats and requirements can differ between the various secure
+	SOCs from TI, this script in the SECDEV package abstracts these
+	details. This script is essentially the only required interface to the
+	TI SECDEV package for creating a u-boot.img image for secure TI
+	devices.
+
+	The SPL/u-boot code contains calls to dedicated secure ROM functions
+	to perform the validation on the secured images. The details of the
+	interface to those functions is shown in the code. The summary
+	is that they are accessed by invoking an ARM secure monitor call to
+	the device's secure ROM (fixed read-only-memory that is secure and
+	only accessible when the ARM core is operating in the secure mode).
+
+	Invoking the secure-binary-image script for Secure Devices
+	==========================================================
+
+	secure-binary-image.sh <INPUT_FILE> <OUTPUT_FILE>
+
+	<INPUT_FILE> is the full path and filename of the input binary image
+
+	<OUTPUT_FILE> is the full path and filename of the output secure image.
-- 
cgit v0.10.2


From 95ebc253e6d4a3370e3dab14743bfc99fcd9cf1b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 28 Jun 2016 10:48:40 +0900
Subject: types.h: move and redefine resource_size_t

Currently, this is only defined in arch/arm/include/asm/types.h,
so move it to include/linux/types.h to make it available for all
architectures.

I defined it with phys_addr_t as Linux does.  I needed to surround
the define with #ifdef __KERNEL__ ... #endif to avoid build errors
in tools building.  (Host tools should not include <linux/types.h>
in the first place, but this is already messy in U-Boot...)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index d108915..9af7353 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -71,5 +71,4 @@ typedef u32 dma_addr_t;
 
 #endif /* __KERNEL__ */
 
-typedef unsigned long resource_size_t;
 #endif
diff --git a/include/linux/types.h b/include/linux/types.h
index 6f75be4..416fa66 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -124,6 +124,10 @@ typedef		__UINT64_TYPE__	u_int64_t;
 typedef		__INT64_TYPE__		int64_t;
 #endif
 
+#ifdef __KERNEL__
+typedef phys_addr_t resource_size_t;
+#endif
+
 /*
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.
-- 
cgit v0.10.2


From c74b8fcdd7193cfcaf8b3c6dab9a59c6feb8a49a Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 28 Jun 2016 10:48:41 +0900
Subject: arm, nds32, sh: remove useless ioremap()/iounmap() defines

These defines are valid only when iomem_valid_addr is defined,
but I do not see such defines anywhere.  Remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9d185a6..6121f1d 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -292,40 +292,6 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define readsb(a, d, s)		__raw_readsb((unsigned long)a, d, s)
 
 /*
- * ioremap and friends.
- *
- * ioremap takes a PCI memory address, as specified in
- * linux/Documentation/IO-mapping.txt.  If you want a
- * physical address, use __ioremap instead.
- */
-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
-extern void __iounmap(void *addr);
-
-/*
- * Generic ioremap support.
- *
- * Define:
- *  iomem_valid_addr(off,size)
- *  iomem_to_phys(off)
- */
-#ifdef iomem_valid_addr
-#define __arch_ioremap(off,sz,nocache)					\
- ({									\
-	unsigned long _off = (off), _size = (sz);			\
-	void *_ret = (void *)0;						\
-	if (iomem_valid_addr(_off, _size))				\
-		_ret = __ioremap(iomem_to_phys(_off),_size,nocache);	\
-	_ret;								\
- })
-
-#define __arch_iounmap __iounmap
-#endif
-
-#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
-#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
-#define iounmap(_addr)			__arch_iounmap(_addr)
-
-/*
  * DMA-consistent mapping functions.  These allocate/free a region of
  * uncached, unwrite-buffered mapped memory space for use with DMA
  * devices.  This is the "generic" version.  The PCI specific version
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
index 04708e9..b2c4d0e 100644
--- a/arch/nds32/include/asm/io.h
+++ b/arch/nds32/include/asm/io.h
@@ -344,40 +344,6 @@ static inline void writesl(unsigned int *addr, const void * data, int longlen)
 #define insl_p(port, to, len)		insl(port, to, len)
 
 /*
- * ioremap and friends.
- *
- * ioremap takes a PCI memory address, as specified in
- * linux/Documentation/IO-mapping.txt.  If you want a
- * physical address, use __ioremap instead.
- */
-extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
-extern void __iounmap(void *addr);
-
-/*
- * Generic ioremap support.
- *
- * Define:
- *  iomem_valid_addr(off,size)
- *  iomem_to_phys(off)
- */
-#ifdef iomem_valid_addr
-#define __arch_ioremap(off, sz, nocache)				\
-({									\
-	unsigned long _off = (off), _size = (sz);			\
-	void *_ret = (void *)0;						\
-	if (iomem_valid_addr(_off, _size))				\
-		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
-	_ret;								\
-})
-
-#define __arch_iounmap __iounmap
-#endif
-
-#define ioremap(off, sz)		__arch_ioremap((off), (sz), 0)
-#define ioremap_nocache(off, sz)	__arch_ioremap((off), (sz), 1)
-#define iounmap(_addr)			__arch_iounmap(_addr)
-
-/*
  * DMA-consistent mapping functions.  These allocate/free a region of
  * uncached, unwrite-buffered mapped memory space for use with DMA
  * devices.  This is the "generic" version.  The PCI specific version
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0a00db3..5dc27be 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -128,39 +128,6 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 #define in_8(port)			inb(port)
 #define in_le16(port)		inw(port)
 #define in_le32(port)		inl(port)
-/*
- * ioremap and friends.
- *
- * ioremap takes a PCI memory address, as specified in
- * linux/Documentation/IO-mapping.txt.  If you want a
- * physical address, use __ioremap instead.
- */
-extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
-extern void __iounmap(void *addr);
-
-/*
- * Generic ioremap support.
- *
- * Define:
- *  iomem_valid_addr(off,size)
- *  iomem_to_phys(off)
- */
-#ifdef iomem_valid_addr
-#define __arch_ioremap(off, sz, nocache)				\
-({								\
-	unsigned long _off = (off), _size = (sz);		\
-	void *_ret = (void *)0;					\
-	if (iomem_valid_addr(_off, _size))			\
-		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
-	_ret;							\
-})
-
-#define __arch_iounmap __iounmap
-#endif
-
-#define ioremap(off, sz)			__arch_ioremap((off), (sz), 0)
-#define ioremap_nocache(off, sz)		__arch_ioremap((off), (sz), 1)
-#define iounmap(_addr)			__arch_iounmap(_addr)
 
 /*
  * DMA-consistent mapping functions.  These allocate/free a region of
-- 
cgit v0.10.2


From 9a387128e341debb6d7e32df8e0f72669a3a079b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 28 Jun 2016 10:48:42 +0900
Subject: linux/io.h: add generic ioremap()/iounmap() defines

For most of architectures in U-Boot, virtual address is straight
mapped to physical address.  So, it makes sense to have generic
defines of ioremap and friends in <linux/io.h>.

All of them are just empty and will disappear at compile time, but
they will be helpful to implement drivers which are counterparts of
Linux ones.

I notice MIPS already has its own implementation, so I added a
Kconfig symbol CONFIG_HAVE_ARCH_IOREMAP which MIPS (and maybe
Sandbox as well) can select.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

diff --git a/arch/Kconfig b/arch/Kconfig
index c43787c..92d4b97 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1,6 +1,9 @@
 config CREATE_ARCH_SYMLINK
 	bool
 
+config HAVE_ARCH_IOREMAP
+	bool
+
 choice
 	prompt "Architecture select"
 	default SANDBOX
@@ -33,6 +36,7 @@ config MICROBLAZE
 
 config MIPS
 	bool "MIPS architecture"
+	select HAVE_ARCH_IOREMAP
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 
diff --git a/include/linux/io.h b/include/linux/io.h
index 1b36a22..a104b7e 100644
--- a/include/linux/io.h
+++ b/include/linux/io.h
@@ -5,6 +5,22 @@
 #ifndef _LINUX_IO_H
 #define _LINUX_IO_H
 
+#include <linux/compiler.h>
+#include <linux/types.h>
 #include <asm/io.h>
 
+#ifndef CONFIG_HAVE_ARCH_IOREMAP
+static inline void __iomem *ioremap(resource_size_t offset,
+				    resource_size_t size)
+{
+	return (void __iomem *)(unsigned long)offset;
+}
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+
+#define devm_ioremap(dev, offset, size)		ioremap(offset, size)
+#endif
+
 #endif /* _LINUX_IO_H */
-- 
cgit v0.10.2


From 20deaddd465aeab6f6939fb1b660622d763791a9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:07 -0600
Subject: mkimage: Honour the default image type with auto-fit

The default image type is supposed to be IH_TYPE_KERNEL, as set in the
'params' variable. Honour this with auto-fit also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index ff3024a..53fa8bb 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -272,7 +272,7 @@ static void process_args(int argc, char **argv)
 	 * will always be IH_TYPE_FLATDT in this case).
 	 */
 	if (params.type == IH_TYPE_FLATDT) {
-		params.fit_image_type = type;
+		params.fit_image_type = type ? type : IH_TYPE_KERNEL;
 		if (!params.auto_its)
 			params.datafile = datafile;
 	} else if (type != IH_TYPE_INVALID) {
-- 
cgit v0.10.2


From 3c23c0feacce0f73d7852409a0c634f275cbecfe Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:08 -0600
Subject: mkimage: Explain the auto-fit imagefile special case

There is a special case in the code when auto-fit is used. Add a comment to
make it easier to understand why this is needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 53fa8bb..66d29ab 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -273,6 +273,7 @@ static void process_args(int argc, char **argv)
 	 */
 	if (params.type == IH_TYPE_FLATDT) {
 		params.fit_image_type = type ? type : IH_TYPE_KERNEL;
+		/* For auto_its, datafile is always 'auto' */
 		if (!params.auto_its)
 			params.datafile = datafile;
 	} else if (type != IH_TYPE_INVALID) {
-- 
cgit v0.10.2


From e324a92531e1dc092949b8a00745afd2328e178e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:09 -0600
Subject: mkimage: Require a data file when auto-fit is used

When auto-fit is used, it is not valid to create a FIT without an image
file. Add a check for this to avoid a very confusing error message later
("Can't open (null): Bad address").

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 66d29ab..a36c031 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -276,6 +276,8 @@ static void process_args(int argc, char **argv)
 		/* For auto_its, datafile is always 'auto' */
 		if (!params.auto_its)
 			params.datafile = datafile;
+		else if (!params.datafile)
+			usage("Missing data file for auto-FIT (use -d)");
 	} else if (type != IH_TYPE_INVALID) {
 		params.type = type;
 	}
-- 
cgit v0.10.2


From 63ef31b9efbf33071cad58a185cc616671d2af62 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:10 -0600
Subject: mkimage: Drop premature setting of params.fit_image_type

There is no need to set params.fit_image_type while parsing the arguments.
It is set up later anyway.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index a36c031..76ae09e 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -197,7 +197,6 @@ static void process_args(int argc, char **argv)
 			 * The flattened image tree (FIT) format
 			 * requires a flattened device tree image type
 			 */
-			params.fit_image_type = params.type;
 			params.type = IH_TYPE_FLATDT;
 			params.fflag = 1;
 			break;
-- 
cgit v0.10.2


From 58b22475424276886df9da9c3e081a8c3057ec77 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:11 -0600
Subject: mkimage: Drop blank line before main()

This is not needed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 76ae09e..920d3be 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -285,7 +285,6 @@ static void process_args(int argc, char **argv)
 		usage("Missing output filename");
 }
 
-
 int main(int argc, char **argv)
 {
 	int ifd = -1;
-- 
cgit v0.10.2


From 3a45f38d418eca5f0e515c8b2077c81f4c4012f1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:12 -0600
Subject: image: Correct auto-fit architecture property name

The fit_write_images() function incorrectly uses the long name for the
architecture. This cannot be parsed with the FIT is read. Fix this by using
the short name instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/fit_image.c b/tools/fit_image.c
index 58aa8e2..94229b8 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -195,7 +195,8 @@ static int fit_write_images(struct image_tool_params *params, char *fdt)
 	fdt_begin_node(fdt, str);
 	fdt_property_string(fdt, "description", params->imagename);
 	fdt_property_string(fdt, "type", typename);
-	fdt_property_string(fdt, "arch", genimg_get_arch_name(params->arch));
+	fdt_property_string(fdt, "arch",
+			    genimg_get_arch_short_name(params->arch));
 	fdt_property_string(fdt, "os", genimg_get_os_short_name(params->os));
 	fdt_property_string(fdt, "compression",
 			    genimg_get_comp_short_name(params->comp));
-- 
cgit v0.10.2


From 555f45d8f9168b09b406a241e7cee7980104d902 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:13 -0600
Subject: image: Convert the IH_... values to enums

We need to know the number of values of each category (architecture,
compression, OS and image type). To make this value easier to maintain,
convert all values to enums. The count is then automatic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/image.h b/include/image.h
index 93d39e1..7646dae 100644
--- a/include/image.h
+++ b/include/image.h
@@ -126,59 +126,67 @@ struct lmb;
 /*
  * Operating System Codes
  */
-#define IH_OS_INVALID		0	/* Invalid OS	*/
-#define IH_OS_OPENBSD		1	/* OpenBSD	*/
-#define IH_OS_NETBSD		2	/* NetBSD	*/
-#define IH_OS_FREEBSD		3	/* FreeBSD	*/
-#define IH_OS_4_4BSD		4	/* 4.4BSD	*/
-#define IH_OS_LINUX		5	/* Linux	*/
-#define IH_OS_SVR4		6	/* SVR4		*/
-#define IH_OS_ESIX		7	/* Esix		*/
-#define IH_OS_SOLARIS		8	/* Solaris	*/
-#define IH_OS_IRIX		9	/* Irix		*/
-#define IH_OS_SCO		10	/* SCO		*/
-#define IH_OS_DELL		11	/* Dell		*/
-#define IH_OS_NCR		12	/* NCR		*/
-#define IH_OS_LYNXOS		13	/* LynxOS	*/
-#define IH_OS_VXWORKS		14	/* VxWorks	*/
-#define IH_OS_PSOS		15	/* pSOS		*/
-#define IH_OS_QNX		16	/* QNX		*/
-#define IH_OS_U_BOOT		17	/* Firmware	*/
-#define IH_OS_RTEMS		18	/* RTEMS	*/
-#define IH_OS_ARTOS		19	/* ARTOS	*/
-#define IH_OS_UNITY		20	/* Unity OS	*/
-#define IH_OS_INTEGRITY		21	/* INTEGRITY	*/
-#define IH_OS_OSE		22	/* OSE		*/
-#define IH_OS_PLAN9		23	/* Plan 9	*/
-#define IH_OS_OPENRTOS		24	/* OpenRTOS	*/
+enum {
+	IH_OS_INVALID		= 0,	/* Invalid OS	*/
+	IH_OS_OPENBSD,			/* OpenBSD	*/
+	IH_OS_NETBSD,			/* NetBSD	*/
+	IH_OS_FREEBSD,			/* FreeBSD	*/
+	IH_OS_4_4BSD,			/* 4.4BSD	*/
+	IH_OS_LINUX,			/* Linux	*/
+	IH_OS_SVR4,			/* SVR4		*/
+	IH_OS_ESIX,			/* Esix		*/
+	IH_OS_SOLARIS,			/* Solaris	*/
+	IH_OS_IRIX,			/* Irix		*/
+	IH_OS_SCO,			/* SCO		*/
+	IH_OS_DELL,			/* Dell		*/
+	IH_OS_NCR,			/* NCR		*/
+	IH_OS_LYNXOS,			/* LynxOS	*/
+	IH_OS_VXWORKS,			/* VxWorks	*/
+	IH_OS_PSOS,			/* pSOS		*/
+	IH_OS_QNX,			/* QNX		*/
+	IH_OS_U_BOOT,			/* Firmware	*/
+	IH_OS_RTEMS,			/* RTEMS	*/
+	IH_OS_ARTOS,			/* ARTOS	*/
+	IH_OS_UNITY,			/* Unity OS	*/
+	IH_OS_INTEGRITY,		/* INTEGRITY	*/
+	IH_OS_OSE,			/* OSE		*/
+	IH_OS_PLAN9,			/* Plan 9	*/
+	IH_OS_OPENRTOS,		/* OpenRTOS	*/
+
+	IH_OS_COUNT,
+};
 
 /*
  * CPU Architecture Codes (supported by Linux)
  */
-#define IH_ARCH_INVALID		0	/* Invalid CPU	*/
-#define IH_ARCH_ALPHA		1	/* Alpha	*/
-#define IH_ARCH_ARM		2	/* ARM		*/
-#define IH_ARCH_I386		3	/* Intel x86	*/
-#define IH_ARCH_IA64		4	/* IA64		*/
-#define IH_ARCH_MIPS		5	/* MIPS		*/
-#define IH_ARCH_MIPS64		6	/* MIPS	 64 Bit */
-#define IH_ARCH_PPC		7	/* PowerPC	*/
-#define IH_ARCH_S390		8	/* IBM S390	*/
-#define IH_ARCH_SH		9	/* SuperH	*/
-#define IH_ARCH_SPARC		10	/* Sparc	*/
-#define IH_ARCH_SPARC64		11	/* Sparc 64 Bit */
-#define IH_ARCH_M68K		12	/* M68K		*/
-#define IH_ARCH_MICROBLAZE	14	/* MicroBlaze   */
-#define IH_ARCH_NIOS2		15	/* Nios-II	*/
-#define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
-#define IH_ARCH_AVR32		17	/* AVR32	*/
-#define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
-#define IH_ARCH_SANDBOX		19	/* Sandbox architecture (test only) */
-#define IH_ARCH_NDS32	        20	/* ANDES Technology - NDS32  */
-#define IH_ARCH_OPENRISC        21	/* OpenRISC 1000  */
-#define IH_ARCH_ARM64		22	/* ARM64	*/
-#define IH_ARCH_ARC		23	/* Synopsys DesignWare ARC */
-#define IH_ARCH_X86_64		24	/* AMD x86_64, Intel and Via */
+enum {
+	IH_ARCH_INVALID		= 0,	/* Invalid CPU	*/
+	IH_ARCH_ALPHA,			/* Alpha	*/
+	IH_ARCH_ARM,			/* ARM		*/
+	IH_ARCH_I386,			/* Intel x86	*/
+	IH_ARCH_IA64,			/* IA64		*/
+	IH_ARCH_MIPS,			/* MIPS		*/
+	IH_ARCH_MIPS64,			/* MIPS	 64 Bit */
+	IH_ARCH_PPC,			/* PowerPC	*/
+	IH_ARCH_S390,			/* IBM S390	*/
+	IH_ARCH_SH,			/* SuperH	*/
+	IH_ARCH_SPARC,			/* Sparc	*/
+	IH_ARCH_SPARC64,		/* Sparc 64 Bit */
+	IH_ARCH_M68K,			/* M68K		*/
+	IH_ARCH_MICROBLAZE,		/* MicroBlaze   */
+	IH_ARCH_NIOS2,			/* Nios-II	*/
+	IH_ARCH_BLACKFIN,		/* Blackfin	*/
+	IH_ARCH_AVR32,			/* AVR32	*/
+	IH_ARCH_ST200,			/* STMicroelectronics ST200  */
+	IH_ARCH_SANDBOX,		/* Sandbox architecture (test only) */
+	IH_ARCH_NDS32,			/* ANDES Technology - NDS32  */
+	IH_ARCH_OPENRISC,		/* OpenRISC 1000  */
+	IH_ARCH_ARM64,			/* ARM64	*/
+	IH_ARCH_ARC,			/* Synopsys DesignWare ARC */
+	IH_ARCH_X86_64,			/* AMD x86_64, Intel and Via */
+
+	IH_ARCH_COUNT,
+};
 
 /*
  * Image Types
@@ -219,47 +227,54 @@ struct lmb;
  *	as command interpreter (=> Shell Scripts).
  */
 
-#define IH_TYPE_INVALID		0	/* Invalid Image		*/
-#define IH_TYPE_STANDALONE	1	/* Standalone Program		*/
-#define IH_TYPE_KERNEL		2	/* OS Kernel Image		*/
-#define IH_TYPE_RAMDISK		3	/* RAMDisk Image		*/
-#define IH_TYPE_MULTI		4	/* Multi-File Image		*/
-#define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
-#define IH_TYPE_SCRIPT		6	/* Script file			*/
-#define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
-#define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
-#define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
-#define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
-#define IH_TYPE_UBLIMAGE	11	/* Davinci UBL Image		*/
-#define IH_TYPE_OMAPIMAGE	12	/* TI OMAP Config Header Image	*/
-#define IH_TYPE_AISIMAGE	13	/* TI Davinci AIS Image		*/
-#define IH_TYPE_KERNEL_NOLOAD	14	/* OS Kernel Image, can run from any load address */
-#define IH_TYPE_PBLIMAGE	15	/* Freescale PBL Boot Image	*/
-#define IH_TYPE_MXSIMAGE	16	/* Freescale MXSBoot Image	*/
-#define IH_TYPE_GPIMAGE		17	/* TI Keystone GPHeader Image	*/
-#define IH_TYPE_ATMELIMAGE	18	/* ATMEL ROM bootable Image	*/
-#define IH_TYPE_SOCFPGAIMAGE	19	/* Altera SOCFPGA Preloader	*/
-#define IH_TYPE_X86_SETUP	20	/* x86 setup.bin Image		*/
-#define IH_TYPE_LPC32XXIMAGE	21	/* x86 setup.bin Image		*/
-#define IH_TYPE_LOADABLE	22	/* A list of typeless images	*/
-#define IH_TYPE_RKIMAGE		23	/* Rockchip Boot Image		*/
-#define IH_TYPE_RKSD		24	/* Rockchip SD card		*/
-#define IH_TYPE_RKSPI		25	/* Rockchip SPI image		*/
-#define IH_TYPE_ZYNQIMAGE	26	/* Xilinx Zynq Boot Image */
-#define IH_TYPE_ZYNQMPIMAGE	27	/* Xilinx ZynqMP Boot Image */
-#define IH_TYPE_FPGA		28	/* FPGA Image */
-
-#define IH_TYPE_COUNT		29	/* Number of image types */
+enum {
+	IH_TYPE_INVALID		= 0,	/* Invalid Image		*/
+	IH_TYPE_STANDALONE,		/* Standalone Program		*/
+	IH_TYPE_KERNEL,			/* OS Kernel Image		*/
+	IH_TYPE_RAMDISK,		/* RAMDisk Image		*/
+	IH_TYPE_MULTI,			/* Multi-File Image		*/
+	IH_TYPE_FIRMWARE,		/* Firmware Image		*/
+	IH_TYPE_SCRIPT,			/* Script file			*/
+	IH_TYPE_FILESYSTEM,		/* Filesystem Image (any type)	*/
+	IH_TYPE_FLATDT,			/* Binary Flat Device Tree Blob	*/
+	IH_TYPE_KWBIMAGE,		/* Kirkwood Boot Image		*/
+	IH_TYPE_IMXIMAGE,		/* Freescale IMXBoot Image	*/
+	IH_TYPE_UBLIMAGE,		/* Davinci UBL Image		*/
+	IH_TYPE_OMAPIMAGE,		/* TI OMAP Config Header Image	*/
+	IH_TYPE_AISIMAGE,		/* TI Davinci AIS Image		*/
+	/* OS Kernel Image, can run from any load address */
+	IH_TYPE_KERNEL_NOLOAD,
+	IH_TYPE_PBLIMAGE,		/* Freescale PBL Boot Image	*/
+	IH_TYPE_MXSIMAGE,		/* Freescale MXSBoot Image	*/
+	IH_TYPE_GPIMAGE,		/* TI Keystone GPHeader Image	*/
+	IH_TYPE_ATMELIMAGE,		/* ATMEL ROM bootable Image	*/
+	IH_TYPE_SOCFPGAIMAGE,		/* Altera SOCFPGA Preloader	*/
+	IH_TYPE_X86_SETUP,		/* x86 setup.bin Image		*/
+	IH_TYPE_LPC32XXIMAGE,		/* x86 setup.bin Image		*/
+	IH_TYPE_LOADABLE,		/* A list of typeless images	*/
+	IH_TYPE_RKIMAGE,		/* Rockchip Boot Image		*/
+	IH_TYPE_RKSD,			/* Rockchip SD card		*/
+	IH_TYPE_RKSPI,			/* Rockchip SPI image		*/
+	IH_TYPE_ZYNQIMAGE,		/* Xilinx Zynq Boot Image */
+	IH_TYPE_ZYNQMPIMAGE,		/* Xilinx ZynqMP Boot Image */
+	IH_TYPE_FPGA,			/* FPGA Image */
+
+	IH_TYPE_COUNT,			/* Number of image types */
+};
 
 /*
  * Compression Types
  */
-#define IH_COMP_NONE		0	/*  No	 Compression Used	*/
-#define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
-#define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
-#define IH_COMP_LZMA		3	/* lzma  Compression Used	*/
-#define IH_COMP_LZO		4	/* lzo   Compression Used	*/
-#define IH_COMP_LZ4		5	/* lz4   Compression Used	*/
+enum {
+	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
+	IH_COMP_GZIP,			/* gzip	 Compression Used	*/
+	IH_COMP_BZIP2,			/* bzip2 Compression Used	*/
+	IH_COMP_LZMA,			/* lzma  Compression Used	*/
+	IH_COMP_LZO,			/* lzo   Compression Used	*/
+	IH_COMP_LZ4,			/* lz4   Compression Used	*/
+
+	IH_COMP_COUNT,
+};
 
 #define IH_MAGIC	0x27051956	/* Image Magic Number		*/
 #define IH_NMLEN		32	/* Image Name Length		*/
-- 
cgit v0.10.2


From 56d7ab74767c60c4ec48061864df0c421e4799e7 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:14 -0600
Subject: image: Create a table of information for each category

Add a table that contains the category name, the number of items in each
category and a pointer to the table of items. This will allow us to use
generic code to deal with the categories.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/image.c b/common/image.c
index 0be09e5..4e503b3 100644
--- a/common/image.c
+++ b/common/image.c
@@ -176,6 +176,19 @@ static const table_entry_t uimage_comp[] = {
 	{	-1,		"",		"",			},
 };
 
+struct table_info {
+	const char *desc;
+	int count;
+	const table_entry_t *table;
+};
+
+static const struct table_info table_info[IH_COUNT] = {
+	{ "architecture", IH_ARCH_COUNT, uimage_arch },
+	{ "compression", IH_COMP_COUNT, uimage_comp },
+	{ "operating system", IH_OS_COUNT, uimage_os },
+	{ "image type", IH_TYPE_COUNT, uimage_type },
+};
+
 /*****************************************************************************/
 /* Legacy format routines */
 /*****************************************************************************/
diff --git a/include/image.h b/include/image.h
index 7646dae..5879ebc 100644
--- a/include/image.h
+++ b/include/image.h
@@ -123,6 +123,15 @@ struct lmb;
 # define IMAGE_OF_SYSTEM_SETUP	0
 #endif
 
+enum ih_category {
+	IH_ARCH,
+	IH_COMP,
+	IH_OS,
+	IH_TYPE,
+
+	IH_COUNT,
+};
+
 /*
  * Operating System Codes
  */
-- 
cgit v0.10.2


From 30495bff35d5a5134bc182fa51728acf69420158 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:15 -0600
Subject: image: Add a name for invalid types

At present the name is NULL, which prevents qsort() fromp being used. Use
the name "invalid" instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/image.c b/common/image.c
index 4e503b3..e9095f4 100644
--- a/common/image.c
+++ b/common/image.c
@@ -69,7 +69,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
 #endif
 
 static const table_entry_t uimage_arch[] = {
-	{	IH_ARCH_INVALID,	NULL,		"Invalid ARCH",	},
+	{	IH_ARCH_INVALID,	"invalid",	"Invalid ARCH",	},
 	{	IH_ARCH_ALPHA,		"alpha",	"Alpha",	},
 	{	IH_ARCH_ARM,		"arm",		"ARM",		},
 	{	IH_ARCH_I386,		"x86",		"Intel x86",	},
@@ -97,7 +97,7 @@ static const table_entry_t uimage_arch[] = {
 };
 
 static const table_entry_t uimage_os[] = {
-	{	IH_OS_INVALID,	NULL,		"Invalid OS",		},
+	{	IH_OS_INVALID,	"invalid",	"Invalid OS",		},
 	{	IH_OS_LINUX,	"linux",	"Linux",		},
 #if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
 	{	IH_OS_LYNXOS,	"lynxos",	"LynxOS",		},
@@ -144,7 +144,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_KERNEL_NOLOAD, "kernel_noload",  "Kernel Image (no loading done)", },
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
-	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
+	{	IH_TYPE_INVALID,    "invalid",	  "Invalid Image",	},
 	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
 	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},
 	{	IH_TYPE_PBLIMAGE,   "pblimage",   "Freescale PBL Boot Image",},
-- 
cgit v0.10.2


From 1426220b0e7b09ecc6a0da5f831287776a89a92c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:16 -0600
Subject: image: Add functions to obtain category information

Add generic functions which can look up information about a category:

- the number of items in the category
- the category description
- an item long time
- an item short time

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/image.c b/common/image.c
index e9095f4..af155b2 100644
--- a/common/image.c
+++ b/common/image.c
@@ -583,6 +583,74 @@ const table_entry_t *get_table_entry(const table_entry_t *table, int id)
 	return NULL;
 }
 
+static const char *unknown_msg(enum ih_category category)
+{
+	static char msg[30];
+
+	strcpy(msg, "Unknown ");
+	strcat(msg, table_info[category].desc);
+
+	return msg;
+}
+
+/**
+ * get_cat_table_entry_name - translate entry id to long name
+ * @category: category to look up (enum ih_category)
+ * @id: entry id to be translated
+ *
+ * This will scan the translation table trying to find the entry that matches
+ * the given id.
+ *
+ * @retur long entry name if translation succeeds; error string on failure
+ */
+const char *genimg_get_cat_name(enum ih_category category, uint id)
+{
+	const table_entry_t *entry;
+
+	entry = get_table_entry(table_info[category].table, id);
+	if (!entry)
+		return unknown_msg(category);
+#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
+	return entry->lname;
+#else
+	return entry->lname + gd->reloc_off;
+#endif
+}
+
+/**
+ * get_cat_table_entry_short_name - translate entry id to short name
+ * @category: category to look up (enum ih_category)
+ * @id: entry id to be translated
+ *
+ * This will scan the translation table trying to find the entry that matches
+ * the given id.
+ *
+ * @retur short entry name if translation succeeds; error string on failure
+ */
+const char *genimg_get_cat_short_name(enum ih_category category, uint id)
+{
+	const table_entry_t *entry;
+
+	entry = get_table_entry(table_info[category].table, id);
+	if (!entry)
+		return unknown_msg(category);
+#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
+	return entry->sname;
+#else
+	return entry->sname + gd->reloc_off;
+#endif
+}
+
+int genimg_get_cat_count(enum ih_category category)
+{
+	return table_info[category].count;
+}
+
+const char *genimg_get_cat_desc(enum ih_category category)
+{
+	return table_info[category].desc;
+}
+
 /**
  * get_table_entry_name - translate entry id to long name
  * @table: pointer to a translation table for entries of a specific type
diff --git a/include/image.h b/include/image.h
index 5879ebc..2a5b560 100644
--- a/include/image.h
+++ b/include/image.h
@@ -478,6 +478,40 @@ const char *genimg_get_comp_name(uint8_t comp);
  */
 const char *genimg_get_comp_short_name(uint8_t comp);
 
+/**
+ * genimg_get_cat_name() - Get the name of an item in a category
+ *
+ * @category:	Category of item
+ * @id:		Item ID
+ * @return name of item, or "Unknown ..." if unknown
+ */
+const char *genimg_get_cat_name(enum ih_category category, uint id);
+
+/**
+ * genimg_get_cat_short_name() - Get the short name of an item in a category
+ *
+ * @category:	Category of item
+ * @id:		Item ID
+ * @return short name of item, or "Unknown ..." if unknown
+ */
+const char *genimg_get_cat_short_name(enum ih_category category, uint id);
+
+/**
+ * genimg_get_cat_count() - Get the number of items in a category
+ *
+ * @category:	Category to check
+ * @return the number of items in the category (IH_xxx_COUNT)
+ */
+int genimg_get_cat_count(enum ih_category category);
+
+/**
+ * genimg_get_cat_desc() - Get the description of a category
+ *
+ * @return the description of a category, e.g. "architecture". This
+ * effectively converts the enum to a string.
+ */
+const char *genimg_get_cat_desc(enum ih_category category);
+
 int genimg_get_os_id(const char *name);
 int genimg_get_arch_id(const char *name);
 int genimg_get_type_id(const char *name);
-- 
cgit v0.10.2


From 306642251234f68f14fa9e86b9f5df6a88632817 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:17 -0600
Subject: mkimage: Allow display of a list of any image header category

Add a generic function which can display a list of items in any category.
This will allow displaying of images for the -A, -C, -O and -T flags. At
present only -T is supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 920d3be..d375c2a 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -25,6 +25,49 @@ static struct image_tool_params params = {
 	.imagename2 = "",
 };
 
+static enum ih_category cur_category;
+
+static int h_compare_category_name(const void *vtype1, const void *vtype2)
+{
+	const int *type1 = vtype1;
+	const int *type2 = vtype2;
+	const char *name1 = genimg_get_cat_short_name(cur_category, *type1);
+	const char *name2 = genimg_get_cat_short_name(cur_category, *type2);
+
+	return strcmp(name1, name2);
+}
+
+int show_valid_options(enum ih_category category)
+{
+	int *order;
+	int count;
+	int item;
+	int i;
+
+	count = genimg_get_cat_count(category);
+	order = calloc(count, sizeof(*order));
+	if (!order)
+		return -ENOMEM;
+
+	/* Sort the names in order of short name for easier reading */
+	for (item = 0; item < count; item++)
+		order[item] = item;
+	cur_category = category;
+	qsort(order, count, sizeof(int), h_compare_category_name);
+
+	fprintf(stderr, "\nInvalid %s, supported are:\n",
+		genimg_get_cat_desc(category));
+	for (i = 0; i < count; i++) {
+		item = order[i];
+		fprintf(stderr, "\t%-15s  %s\n",
+			genimg_get_cat_short_name(category, item),
+			genimg_get_cat_name(category, item));
+	}
+	fprintf(stderr, "\n");
+
+	return 0;
+}
+
 static int h_compare_image_name(const void *vtype1, const void *vtype2)
 {
 	const int *type1 = vtype1;
-- 
cgit v0.10.2


From f24e10500ffc7ff4b9c75de0e9b1f3efdd43ef41 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:18 -0600
Subject: mkimage: Use generic code for showing an 'image type' error

The existing error code only displays image types which are claimed by a
particular U_BOOT_IMAGE_TYPE() driver. But this does not seem correct. The
mkimage tool should support all image types, so it makes sense to allow
creation of images of any type with the tool.

When an incorrect image type is provided, use generic code to display the
error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index d375c2a..3cdbb2c 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -37,7 +37,7 @@ static int h_compare_category_name(const void *vtype1, const void *vtype2)
 	return strcmp(name1, name2);
 }
 
-int show_valid_options(enum ih_category category)
+static int show_valid_options(enum ih_category category)
 {
 	int *order;
 	int count;
@@ -68,47 +68,6 @@ int show_valid_options(enum ih_category category)
 	return 0;
 }
 
-static int h_compare_image_name(const void *vtype1, const void *vtype2)
-{
-	const int *type1 = vtype1;
-	const int *type2 = vtype2;
-	const char *name1 = genimg_get_type_short_name(*type1);
-	const char *name2 = genimg_get_type_short_name(*type2);
-
-	return strcmp(name1, name2);
-}
-
-/* Show all image types supported by mkimage */
-static void show_image_types(void)
-{
-	struct image_type_params *tparams;
-	int order[IH_TYPE_COUNT];
-	int count;
-	int type;
-	int i;
-
-	/* Sort the names in order of short name for easier reading */
-	memset(order, '\0', sizeof(order));
-	for (count = 0, type = 0; type < IH_TYPE_COUNT; type++) {
-		tparams = imagetool_get_type(type);
-		if (tparams)
-			order[count++] = type;
-	}
-	qsort(order, count, sizeof(int), h_compare_image_name);
-
-	fprintf(stderr, "\nInvalid image type. Supported image types:\n");
-	for (i = 0; i < count; i++) {
-		type = order[i];
-		tparams = imagetool_get_type(type);
-		if (tparams) {
-			fprintf(stderr, "\t%-15s  %s\n",
-				genimg_get_type_short_name(type),
-				genimg_get_type_name(type));
-		}
-	}
-	fprintf(stderr, "\n");
-}
-
 static void usage(const char *msg)
 {
 	fprintf(stderr, "Error: %s\n", msg);
@@ -286,7 +245,7 @@ static void process_args(int argc, char **argv)
 		case 'T':
 			type = genimg_get_type_id(optarg);
 			if (type < 0) {
-				show_image_types();
+				show_valid_options(IH_TYPE);
 				usage("Invalid image type");
 			}
 			break;
-- 
cgit v0.10.2


From 51f03e6a7596d61a9ae9b1aee030112cc6a795ff Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:19 -0600
Subject: mkimage: Show item lists for all categories

Update the error-handling code for -A, -C and -O to show a list of valid
options when an invalid one is provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Vinoth Eswaran <evinoth1206@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 3cdbb2c..f589a41 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -152,8 +152,10 @@ static void process_args(int argc, char **argv)
 			break;
 		case 'A':
 			params.arch = genimg_get_arch_id(optarg);
-			if (params.arch < 0)
+			if (params.arch < 0) {
+				show_valid_options(IH_ARCH);
 				usage("Invalid architecture");
+			}
 			break;
 		case 'b':
 			if (add_content(IH_TYPE_FLATDT, optarg)) {
@@ -168,8 +170,10 @@ static void process_args(int argc, char **argv)
 			break;
 		case 'C':
 			params.comp = genimg_get_comp_id(optarg);
-			if (params.comp < 0)
+			if (params.comp < 0) {
+				show_valid_options(IH_COMP);
 				usage("Invalid compression type");
+			}
 			break;
 		case 'd':
 			params.datafile = optarg;
@@ -216,8 +220,10 @@ static void process_args(int argc, char **argv)
 			break;
 		case 'O':
 			params.os = genimg_get_os_id(optarg);
-			if (params.os < 0)
+			if (params.os < 0) {
+				show_valid_options(IH_OS);
 				usage("Invalid operating system");
+			}
 			break;
 		case 'p':
 			params.external_offset = strtoull(optarg, &ptr, 16);
-- 
cgit v0.10.2


From 022885cb9ce9b22fb62225a21b4eb017a2e8dab5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 30 Jun 2016 10:52:20 -0600
Subject: tools: Allow building with debug enabled

Sometimes it is useful to build tools with debugging information included so
that line-number information is available when run under gdb. Add a Kconfig
option to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/Kconfig b/Kconfig
index 2afbaaf..ef12f9f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -114,6 +114,15 @@ if EXPERT
 	  Warning:
 	  When disabling this, please check if malloc calls, maybe
 	  should be replaced by calloc - if one expects zeroed memory.
+
+config TOOLS_DEBUG
+	bool "Enable debug information for tools"
+	help
+	  Enable generation of debug information for tools such as mkimage.
+	  This can be used for debugging purposes. With debug information
+	  it is possible to set breakpoints on particular lines, single-step
+	  debug through the source code, etc.
+
 endif
 endmenu		# General setup
 
diff --git a/Makefile b/Makefile
index 88128ec..7eaa392 100644
--- a/Makefile
+++ b/Makefile
@@ -256,7 +256,8 @@ CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
 
 HOSTCC       = cc
 HOSTCXX      = c++
-HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
+HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
+		$(if $(CONFIG_TOOLS_DEBUG),-g)
 HOSTCXXFLAGS = -O2
 
 ifeq ($(HOSTOS),cygwin)
-- 
cgit v0.10.2


From f6349c3c4cd334148637c83bcfb6017b195102f5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:33 -0600
Subject: test: Add a README

Add a few notes about how testing works in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/README b/test/README
new file mode 100644
index 0000000..dfd83d6
--- /dev/null
+++ b/test/README
@@ -0,0 +1,82 @@
+Testing in U-Boot
+=================
+
+U-Boot has a large amount of code. This file describes how this code is
+tested and what tests you should write when adding a new feature.
+
+
+Sandbox
+-------
+U-Boot can be built as a user-space application (e.g. for Linux). This
+allows test to be executed without needing target hardware. The 'sandbox'
+target provides this feature and it is widely used in tests.
+
+
+Pytest Suite
+------------
+
+Many tests are available using the pytest suite, in test/py. This can run
+either on sandbox or on real hardware. It relies on the U-Boot console to
+inject test commands and check the result. It is slower to run than C code,
+but provides the ability to unify lots of test and summarise their results.
+
+You can run the tests on sandbox with:
+
+	./test/py/test.py --bd sandbox --build
+
+This will produce HTML output in build-sandbox/test-log.html
+
+See test/py/README.md for more information about the pytest suite.
+
+
+tbot
+----
+
+Tbot provides a way to execute tests on target hardware. It is intended for
+trying out both U-Boot and Linux (and potentially other software) on a
+number of boards automatically. It can be used to create a continuous test
+environment. See tools/tbot/README for more information.
+
+
+Ad-hoc tests
+------------
+
+There are several ad-hoc tests which run outside the pytest environment:
+
+   test/fs	- File system test (shell script)
+   test/image	- FIT and lagacy image tests (shell script and Python)
+   test/stdint	- A test that stdint.h can be used in U-Boot (shell script)
+   trace	- Test for the tracing feature (shell script)
+   vboot	- Test for verified boot (shell script)
+
+The above should be converted to run as part of the pytest suite.
+
+
+When to write tests
+-------------------
+
+If you add code to U-Boot without a test you are taking a risk. Even if you
+perform thorough manual testing at the time of submission, it may break when
+future changes are made to U-Boot. It may even break when applied to mainline,
+if other changes interact with it. A good mindset is that untested code
+probably doesn't work and should be deleted.
+
+You can assume that the Pytest suite will be run before patches are accepted
+to mainline, so this provides protection against future breakage.
+
+On the other hand there is quite a bit of code that is not covered with tests,
+or is covered sparingly. So here are some suggestions:
+
+- If you are adding a new uclass, add a sandbox driver and a test that uses it
+- If you are modifying code covered by an existing test, add a new test case
+  to cover your changes
+- If the code you are modifying has not tests, consider writing one. Even a
+  very basic test is useful, and may be picked up and enhanced by others. It
+  is much easier to add onto a test - writing a new large test can seem
+  daunting to most contributors.
+
+
+Future work
+-----------
+
+Converting existing shell scripts into pytest tests.
-- 
cgit v0.10.2


From 07f4eadc99b365fa92114f19c02218ff39c45ed9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:34 -0600
Subject: test: Add a simple script to run tests on sandbox

A common check before sending patches is to run all available tests on
sandbox. But everytime I do this I have to look up the README. This presents
quite a barrier to actually doing this.

Add a shell script to help. To run the tests, type:

   test/run

in the U-Boot directory, which should be easy to remember.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/README b/test/README
index dfd83d6..6cfee05 100644
--- a/test/README
+++ b/test/README
@@ -5,6 +5,17 @@ U-Boot has a large amount of code. This file describes how this code is
 tested and what tests you should write when adding a new feature.
 
 
+Running tests
+-------------
+
+To run most tests on sandbox, type this:
+
+    test/run
+
+in the U-Boot directory. Note that only the pytest suite is run using this
+comment.
+
+
 Sandbox
 -------
 U-Boot can be built as a user-space application (e.g. for Linux). This
diff --git a/test/run b/test/run
new file mode 100755
index 0000000..a6dcf8f
--- /dev/null
+++ b/test/run
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+# Run all tests
+./test/py/test.py --bd sandbox --build
-- 
cgit v0.10.2


From b9c771b04c215de981987a92d5e1f016c8dd1921 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:35 -0600
Subject: sandbox: Don't exit when bootm completes

At present sandbox exits when the 'bootm' command completes, since it is not
actually able to run the OS that is loaded. Normally 'bootm' failure is
considered a fatal error in U-Boot.

However this is annoying for tests, which may want to examine the state
after a test is complete. In any case there is a 'reset' command which can
be used to exit, if required.

Change the behaviour to return normally from the 'bootm' command on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
index d49c927..0c9a797 100644
--- a/arch/sandbox/lib/bootm.c
+++ b/arch/sandbox/lib/bootm.c
@@ -56,7 +56,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 		bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 		printf("## Transferring control to Linux (at address %08lx)...\n",
 		       images->ep);
-		reset_cpu(0);
+		printf("sandbox: continuing, as we cannot run Linux\n");
 	}
 
 	return 0;
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 9ec84bd..e3f5a46 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -481,6 +481,7 @@ int boot_selected_os(int argc, char * const argv[], int state,
 
 	/* Stand-alone may return when 'autostart' is 'no' */
 	if (images->os.type == IH_TYPE_STANDALONE ||
+	    IS_ENABLED(CONFIG_SANDBOX) ||
 	    state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
 		return 0;
 	bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
-- 
cgit v0.10.2


From 0671960beee89da3016f40d059df4a14f257d442 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:36 -0600
Subject: test/py: Allow tests to control the sandbox device-tree file

Normally tests will run with the test.dtb file designed for this purpose.
However, the verified boot tests need to run with their own device-tree
file, containing a public key.

Make the device-tree file a config option so that it can be adjusted by
tests. The default is to keep the current behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/py/conftest.py b/test/py/conftest.py
index 449f98b..5b16456 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -179,6 +179,7 @@ def pytest_configure(config):
     ubconfig.board_type = board_type
     ubconfig.board_identity = board_identity
     ubconfig.gdbserver = gdbserver
+    ubconfig.dtb = build_dir + '/arch/sandbox/dts/test.dtb'
 
     env_vars = (
         'board_type',
diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py
index 04654ae..b440497 100644
--- a/test/py/u_boot_console_sandbox.py
+++ b/test/py/u_boot_console_sandbox.py
@@ -46,7 +46,7 @@ class ConsoleSandbox(ConsoleBase):
             self.config.build_dir + '/u-boot',
             '-v',
             '-d',
-            self.config.build_dir + '/arch/sandbox/dts/test.dtb'
+            self.config.dtb
         ]
         return Spawn(cmd, cwd=self.config.source_dir)
 
-- 
cgit v0.10.2


From 3b8d9d977b6dd6d04f0cfe2eb5dce25264fe40f5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:37 -0600
Subject: test/py: Allow RunAndLog() to return the output

Tests may want to look at the output from running a command. Return it so
that this is possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/py/multiplexed_log.py b/test/py/multiplexed_log.py
index 68917eb..02c44df 100644
--- a/test/py/multiplexed_log.py
+++ b/test/py/multiplexed_log.py
@@ -119,7 +119,7 @@ class RunAndLog(object):
                 raised if such problems occur.
 
         Returns:
-            Nothing.
+            The output as a string.
         """
 
         msg = '+' + ' '.join(cmd) + '\n'
@@ -161,6 +161,7 @@ class RunAndLog(object):
             self.chained_file.write(output)
         if exception:
             raise exception
+        return output
 
 class SectionCtxMgr(object):
     """A context manager for Python's "with" statement, which allows a certain
-- 
cgit v0.10.2


From 86845bf38dbba5fa7499db10ac5ee20f72d3f240 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:38 -0600
Subject: test/py: Provide output from exceptions with RunAndLog()

Tests may want to look at the output from running a command, even if it
fails (e.g. with a non-zero return code). Provide a means to obtain this.

Another approach would be to return a class object containing both the
output and the exception, but I'm not sure if that would result in a lot
of refactoring.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/py/multiplexed_log.py b/test/py/multiplexed_log.py
index 02c44df..35a32fb 100644
--- a/test/py/multiplexed_log.py
+++ b/test/py/multiplexed_log.py
@@ -101,6 +101,7 @@ class RunAndLog(object):
         self.logfile = logfile
         self.name = name
         self.chained_file = chained_file
+        self.output = None
 
     def close(self):
         """Clean up any resources managed by this object."""
@@ -109,6 +110,9 @@ class RunAndLog(object):
     def run(self, cmd, cwd=None, ignore_errors=False):
         """Run a command as a sub-process, and log the results.
 
+        The output is available at self.output which can be useful if there is
+        an exception.
+
         Args:
             cmd: The command to execute.
             cwd: The directory to run the command in. Can be None to use the
@@ -159,6 +163,9 @@ class RunAndLog(object):
         self.logfile.write(self, output)
         if self.chained_file:
             self.chained_file.write(output)
+
+        # Store the output so it can be accessed if we raise an exception.
+        self.output = output
         if exception:
             raise exception
         return output
-- 
cgit v0.10.2


From f3d3e95ce5d26777a6a138635f9bb12ca7ccf6fa Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:39 -0600
Subject: test/py: Return output from run_and_log()

It is useful to be able to obtain the output from a command. Return it from
this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index e4765e3..99bad7c 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -165,12 +165,13 @@ def run_and_log(u_boot_console, cmd, ignore_errors=False):
             problems occur.
 
     Returns:
-        Nothing.
+        The output as a string.
     """
 
     runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
-    runner.run(cmd, ignore_errors=ignore_errors)
+    output = runner.run(cmd, ignore_errors=ignore_errors)
     runner.close()
+    return output
 
 ram_base = None
 def find_ram_base(u_boot_console):
-- 
cgit v0.10.2


From 8b304a37df13477f02fca5a6f5eaa3e55d7b4bf1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:40 -0600
Subject: test/py: Add an option to execute a string containing a command

It is sometimes inconvenient to convert a string into a list for execution
with run_and_log(). Provide a helper function to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 99bad7c..ce0bbcf 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -173,6 +173,18 @@ def run_and_log(u_boot_console, cmd, ignore_errors=False):
     runner.close()
     return output
 
+def cmd(u_boot_console, cmd_str):
+    """Run a single command string and log its output.
+
+    Args:
+        u_boot_console: A console connection to U-Boot.
+        cmd: The command to run, as a string.
+
+    Returns:
+        The output as a string.
+    """
+    return run_and_log(u_boot_console, cmd_str.split())
+
 ram_base = None
 def find_ram_base(u_boot_console):
     """Find the running U-Boot's RAM location.
-- 
cgit v0.10.2


From 9e17b0345afe198490689d9f36fab3849e9ef69a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:41 -0600
Subject: test/py: Provide a way to check that a command fails

Sometimes we want to run a command and check that it fails. Add a function
to handle this. It can check the return code and also make sure that the
output contains a given error message.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index ce0bbcf..e358c58 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -185,6 +185,28 @@ def cmd(u_boot_console, cmd_str):
     """
     return run_and_log(u_boot_console, cmd_str.split())
 
+def run_and_log_expect_exception(u_boot_console, cmd, retcode, msg):
+    """Run a command which is expected to fail.
+
+    This runs a command and checks that it fails with the expected return code
+    and exception method. If not, an exception is raised.
+
+    Args:
+        u_boot_console: A console connection to U-Boot.
+        cmd: The command to run, as an array of argv[].
+        retcode: Expected non-zero return code from the command.
+        msg: String which should be contained within the command's output.
+    """
+    try:
+        runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
+        runner.run(cmd)
+    except Exception as e:
+        assert(msg in runner.output)
+    else:
+        raise Exception('Expected exception, but not raised')
+    finally:
+        runner.close()
+
 ram_base = None
 def find_ram_base(u_boot_console):
     """Find the running U-Boot's RAM location.
-- 
cgit v0.10.2


From 73a9054d0f33dc4612a13200c6f3af00d2a1fcda Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:42 -0600
Subject: test/py: Add a helper to run a list of U-Boot commands

Some tests want to execute a sequence of commands. Add a helper for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index 815fa64..b5aad7c 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -216,6 +216,22 @@ class ConsoleBase(object):
             self.cleanup_spawn()
             raise
 
+    def run_command_list(self, cmds):
+        """Run a list of commands.
+
+        This is a helper function to call run_command() with default arguments
+        for each command in a list.
+
+        Args:
+            cmd: List of commands (each a string)
+        Returns:
+            Combined output of all commands, as a string
+        """
+        output = ''
+        for cmd in cmds:
+            output += self.run_command(cmd)
+        return output
+
     def ctrlc(self):
         """Send a CTRL-C character to U-Boot.
 
-- 
cgit v0.10.2


From 655cc69655f058e0354d5db4179c92d2ac0081ba Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:43 -0600
Subject: tools: Add an error code when fit_handle_file() fails

The error code may provide useful information for debugging. Add it to the
error string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/tools/fit_image.c b/tools/fit_image.c
index 94229b8..10fd6d4 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -651,8 +651,8 @@ static int fit_handle_file(struct image_tool_params *params)
 	}
 
 	if (ret) {
-		fprintf(stderr, "%s Can't add hashes to FIT blob\n",
-			params->cmdname);
+		fprintf(stderr, "%s Can't add hashes to FIT blob: %d\n",
+			params->cmdname, ret);
 		goto err_system;
 	}
 
-- 
cgit v0.10.2


From 1152a05ee6593bf3036337cd18edd355589ea3a8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:44 -0600
Subject: tools: Correct error handling in fit_image_process_hash()

We should not be returning -1 as an error code. This can mask a situation
where we run out of space adding things to the FIT. By returning the correct
error in this case (-ENOSPC) it can be handled by the higher-level code.

This may fix the error reported by Tom Van Deun here:

https://www.mail-archive.com/u-boot@lists.denx.de/msg217417.html

although I am not sure as I cannot actually repeat it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Van Deun <tom.vandeun@wapice.com>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>

diff --git a/tools/image-host.c b/tools/image-host.c
index 7effb6c..3e14fdc 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -38,7 +38,7 @@ static int fit_set_hash_value(void *fit, int noffset, uint8_t *value,
 		printf("Can't set hash '%s' property for '%s' node(%s)\n",
 		       FIT_VALUE_PROP, fit_get_name(fit, noffset, NULL),
 		       fdt_strerror(ret));
-		return -1;
+		return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
 	}
 
 	return 0;
@@ -64,25 +64,27 @@ static int fit_image_process_hash(void *fit, const char *image_name,
 	const char *node_name;
 	int value_len;
 	char *algo;
+	int ret;
 
 	node_name = fit_get_name(fit, noffset, NULL);
 
 	if (fit_image_hash_get_algo(fit, noffset, &algo)) {
 		printf("Can't get hash algo property for '%s' hash node in '%s' image node\n",
 		       node_name, image_name);
-		return -1;
+		return -ENOENT;
 	}
 
 	if (calculate_hash(data, size, algo, value, &value_len)) {
 		printf("Unsupported hash algorithm (%s) for '%s' hash node in '%s' image node\n",
 		       algo, node_name, image_name);
-		return -1;
+		return -EPROTONOSUPPORT;
 	}
 
-	if (fit_set_hash_value(fit, noffset, value, value_len)) {
+	ret = fit_set_hash_value(fit, noffset, value, value_len);
+	if (ret) {
 		printf("Can't set hash value for '%s' hash node in '%s' image node\n",
 		       node_name, image_name);
-		return -1;
+		return ret;
 	}
 
 	return 0;
@@ -322,7 +324,7 @@ int fit_image_add_verification_data(const char *keydir, void *keydest,
 				comment, require_keys);
 		}
 		if (ret)
-			return -1;
+			return ret;
 	}
 
 	return 0;
-- 
cgit v0.10.2


From 8729d582595dc0a9a666310f9f6001f815684f73 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 3 Jul 2016 09:40:46 -0600
Subject: test: Convert the vboot test to test/py

Now that we have a suitable test framework we should move all tests into it.
The vboot test is a suitable candidate. Rewrite it in Python and move the
data files into an appropriate directory.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/README b/test/README
index 6cfee05..ee55972 100644
--- a/test/README
+++ b/test/README
@@ -58,7 +58,6 @@ There are several ad-hoc tests which run outside the pytest environment:
    test/image	- FIT and lagacy image tests (shell script and Python)
    test/stdint	- A test that stdint.h can be used in U-Boot (shell script)
    trace	- Test for the tracing feature (shell script)
-   vboot	- Test for verified boot (shell script)
 
 The above should be converted to run as part of the pytest suite.
 
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
new file mode 100644
index 0000000..c779895
--- /dev/null
+++ b/test/py/tests/test_vboot.py
@@ -0,0 +1,185 @@
+# Copyright (c) 2013, Google Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# U-Boot Verified Boot Test
+
+"""
+This tests verified boot in the following ways:
+
+For image verification:
+- Create FIT (unsigned) with mkimage
+- Check that verification shows that no keys are verified
+- Sign image
+- Check that verification shows that a key is now verified
+
+For configuration verification:
+- Corrupt signature and check for failure
+- Create FIT (with unsigned configuration) with mkimage
+- Check that image veriication works
+- Sign the FIT and mark the key as 'required' for verification
+- Check that image verification works
+- Corrupt the signature
+- Check that image verification no-longer works
+
+Tests run with both SHA1 and SHA256 hashing.
+"""
+
+import pytest
+import sys
+import u_boot_utils as util
+
+@pytest.mark.buildconfigspec('fit_signature')
+def test_vboot(u_boot_console):
+    """Test verified boot signing with mkimage and verification with 'bootm'.
+
+    This works using sandbox only as it needs to update the device tree used
+    by U-Boot to hold public keys from the signing process.
+
+    The SHA1 and SHA256 tests are combined into a single test since the
+    key-generation process is quite slow and we want to avoid doing it twice.
+    """
+    def dtc(dts):
+        """Run the device-tree compiler to compile a .dts file
+
+        The output file will be the same as the input file but with a .dtb
+        extension.
+
+        Args:
+            dts: Device tree file to compile.
+        """
+        dtb = dts.replace('.dts', '.dtb')
+        util.cmd(cons, 'dtc %s %s%s -O dtb '
+                       '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
+
+    def run_bootm(test_type, expect_string):
+        """Run a 'bootm' command U-Boot.
+
+        This always starts a fresh U-Boot instance since the device tree may
+        contain a new public key.
+
+        Args:
+            test_type: A string identifying the test type
+            expect_string: A string which is expected in the output
+        """
+        cons.cleanup_spawn()
+        cons.ensure_spawned()
+        cons.log.action('%s: Test Verified Boot Run: %s' % (algo, test_type))
+        output = cons.run_command_list(
+            ['sb load hostfs - 100 %stest.fit' % tmpdir,
+             'fdt addr 100',
+             'bootm 100'])
+        assert(expect_string in output)
+
+    def make_fit(its):
+        """Make a new FIT from the .its source file
+
+        This runs 'mkimage -f' to create a new FIT.
+
+        Args:
+            its: Filename containing .its source
+        """
+        util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
+                                '%s%s' % (datadir, its), fit])
+
+    def sign_fit():
+        """Sign the FIT
+
+        Signs the FIT and writes the signature into it. It also writes the
+        public key into the dtb.
+        """
+        cons.log.action('%s: Sign images' % algo)
+        util.run_and_log(cons, [mkimage, '-F', '-k', tmpdir, '-K', dtb,
+                                '-r', fit])
+
+    def test_with_algo(sha):
+        """Test verified boot with the given hash algorithm
+
+        This is the main part of the test code. The same procedure is followed
+        for both hashing algorithms.
+
+        Args:
+            sha: Either 'sha1' or 'sha256', to select the algorithm to use
+        """
+        global algo
+
+        algo = sha
+
+        # Compile our device tree files for kernel and U-Boot
+        dtc('sandbox-kernel.dts')
+        dtc('sandbox-u-boot.dts')
+
+        # Build the FIT, but don't sign anything yet
+        cons.log.action('%s: Test FIT with signed images' % algo)
+        make_fit('sign-images-%s.its' % algo)
+        run_bootm('unsigned images', 'dev-')
+
+        # Sign images with our dev keys
+        sign_fit()
+        run_bootm('signed images', 'dev+')
+
+        # Create a fresh .dtb without the public keys
+        dtc('sandbox-u-boot.dts')
+
+        cons.log.action('%s: Test FIT with signed configuration' % algo)
+        make_fit('sign-configs-%s.its' % algo)
+        run_bootm('unsigned config', '%s+ OK' % algo)
+
+        # Sign images with our dev keys
+        sign_fit()
+        run_bootm('signed config', 'dev+')
+
+        cons.log.action('%s: Check signed config on the host' % algo)
+
+        util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', tmpdir,
+                                '-k', dtb])
+
+        # Increment the first byte of the signature, which should cause failure
+        sig = util.cmd(cons, 'fdtget -t bx %s %s value' % (fit, sig_node))
+        byte_list = sig.split()
+        byte = int(byte_list[0], 16)
+        byte_list = ['%x' % (byte + 1)] + byte_list[1:]
+        sig = ' '.join(byte_list)
+        util.cmd(cons, 'fdtput -t bx %s %s value %s' % (fit, sig_node, sig))
+
+        run_bootm('Signed config with bad hash', 'Bad Data Hash')
+
+        cons.log.action('%s: Check bad config on the host' % algo)
+        util.run_and_log_expect_exception(cons, [fit_check_sign, '-f', fit,
+                '-k', dtb], 1, 'Failed to verify required signature')
+
+    cons = u_boot_console
+    tmpdir = cons.config.result_dir + '/'
+    tmp = tmpdir + 'vboot.tmp'
+    datadir = 'test/py/tests/vboot/'
+    fit = '%stest.fit' % tmpdir
+    mkimage = cons.config.build_dir + '/tools/mkimage'
+    fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
+    dtc_args = '-I dts -O dtb -i %s' % tmpdir
+    dtb = '%ssandbox-u-boot.dtb' % tmpdir
+    sig_node = '/configurations/conf@1/signature@1'
+
+    # Create an RSA key pair
+    public_exponent = 65537
+    util.cmd(cons, 'openssl genpkey -algorithm RSA -out %sdev.key '
+                   '-pkeyopt rsa_keygen_bits:2048 '
+                   '-pkeyopt rsa_keygen_pubexp:%d '
+                   '2>/dev/null'  % (tmpdir, public_exponent))
+
+    # Create a certificate containing the public key
+    util.cmd(cons, 'openssl req -batch -new -x509 -key %sdev.key -out '
+                   '%sdev.crt' % (tmpdir, tmpdir))
+
+    # Create a number kernel image with zeroes
+    with open('%stest-kernel.bin' % tmpdir, 'w') as fd:
+        fd.write(5000 * chr(0))
+
+    try:
+        # We need to use our own device tree file. Remember to restore it
+        # afterwards.
+        old_dtb = cons.config.dtb
+        cons.config.dtb = dtb
+        test_with_algo('sha1')
+        test_with_algo('sha256')
+    finally:
+        cons.config.dtb = old_dtb
diff --git a/test/py/tests/vboot/sandbox-kernel.dts b/test/py/tests/vboot/sandbox-kernel.dts
new file mode 100644
index 0000000..a1e853c
--- /dev/null
+++ b/test/py/tests/vboot/sandbox-kernel.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+
+/ {
+	model = "Sandbox Verified Boot Test";
+	compatible = "sandbox";
+
+};
diff --git a/test/py/tests/vboot/sandbox-u-boot.dts b/test/py/tests/vboot/sandbox-u-boot.dts
new file mode 100644
index 0000000..63f8f40
--- /dev/null
+++ b/test/py/tests/vboot/sandbox-u-boot.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+/ {
+	model = "Sandbox Verified Boot Test";
+	compatible = "sandbox";
+
+	reset@0 {
+		compatible = "sandbox,reset";
+	};
+};
diff --git a/test/py/tests/vboot/sign-configs-sha1.its b/test/py/tests/vboot/sign-configs-sha1.its
new file mode 100644
index 0000000..db2ed79
--- /dev/null
+++ b/test/py/tests/vboot/sign-configs-sha1.its
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+/ {
+	description = "Chrome OS kernel image with one or more FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			data = /incbin/("test-kernel.bin");
+			type = "kernel_noload";
+			arch = "sandbox";
+			os = "linux";
+			compression = "none";
+			load = <0x4>;
+			entry = <0x8>;
+			kernel-version = <1>;
+			hash@1 {
+				algo = "sha1";
+			};
+		};
+		fdt@1 {
+			description = "snow";
+			data = /incbin/("sandbox-kernel.dtb");
+			type = "flat_dt";
+			arch = "sandbox";
+			compression = "none";
+			fdt-version = <1>;
+			hash@1 {
+				algo = "sha1";
+			};
+		};
+	};
+	configurations {
+		default = "conf@1";
+		conf@1 {
+			kernel = "kernel@1";
+			fdt = "fdt@1";
+			signature@1 {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+				sign-images = "fdt", "kernel";
+			};
+		};
+	};
+};
diff --git a/test/py/tests/vboot/sign-configs-sha256.its b/test/py/tests/vboot/sign-configs-sha256.its
new file mode 100644
index 0000000..1b3432e
--- /dev/null
+++ b/test/py/tests/vboot/sign-configs-sha256.its
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+/ {
+	description = "Chrome OS kernel image with one or more FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			data = /incbin/("test-kernel.bin");
+			type = "kernel_noload";
+			arch = "sandbox";
+			os = "linux";
+			compression = "none";
+			load = <0x4>;
+			entry = <0x8>;
+			kernel-version = <1>;
+			hash@1 {
+				algo = "sha256";
+			};
+		};
+		fdt@1 {
+			description = "snow";
+			data = /incbin/("sandbox-kernel.dtb");
+			type = "flat_dt";
+			arch = "sandbox";
+			compression = "none";
+			fdt-version = <1>;
+			hash@1 {
+				algo = "sha256";
+			};
+		};
+	};
+	configurations {
+		default = "conf@1";
+		conf@1 {
+			kernel = "kernel@1";
+			fdt = "fdt@1";
+			signature@1 {
+				algo = "sha256,rsa2048";
+				key-name-hint = "dev";
+				sign-images = "fdt", "kernel";
+			};
+		};
+	};
+};
diff --git a/test/py/tests/vboot/sign-images-sha1.its b/test/py/tests/vboot/sign-images-sha1.its
new file mode 100644
index 0000000..f69326a
--- /dev/null
+++ b/test/py/tests/vboot/sign-images-sha1.its
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/ {
+	description = "Chrome OS kernel image with one or more FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			data = /incbin/("test-kernel.bin");
+			type = "kernel_noload";
+			arch = "sandbox";
+			os = "linux";
+			compression = "none";
+			load = <0x4>;
+			entry = <0x8>;
+			kernel-version = <1>;
+			signature@1 {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+		fdt@1 {
+			description = "snow";
+			data = /incbin/("sandbox-kernel.dtb");
+			type = "flat_dt";
+			arch = "sandbox";
+			compression = "none";
+			fdt-version = <1>;
+			signature@1 {
+				algo = "sha1,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+	};
+	configurations {
+		default = "conf@1";
+		conf@1 {
+			kernel = "kernel@1";
+			fdt = "fdt@1";
+		};
+	};
+};
diff --git a/test/py/tests/vboot/sign-images-sha256.its b/test/py/tests/vboot/sign-images-sha256.its
new file mode 100644
index 0000000..e6aa9fc
--- /dev/null
+++ b/test/py/tests/vboot/sign-images-sha256.its
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/ {
+	description = "Chrome OS kernel image with one or more FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			data = /incbin/("test-kernel.bin");
+			type = "kernel_noload";
+			arch = "sandbox";
+			os = "linux";
+			compression = "none";
+			load = <0x4>;
+			entry = <0x8>;
+			kernel-version = <1>;
+			signature@1 {
+				algo = "sha256,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+		fdt@1 {
+			description = "snow";
+			data = /incbin/("sandbox-kernel.dtb");
+			type = "flat_dt";
+			arch = "sandbox";
+			compression = "none";
+			fdt-version = <1>;
+			signature@1 {
+				algo = "sha256,rsa2048";
+				key-name-hint = "dev";
+			};
+		};
+	};
+	configurations {
+		default = "conf@1";
+		conf@1 {
+			kernel = "kernel@1";
+			fdt = "fdt@1";
+		};
+	};
+};
diff --git a/test/vboot/.gitignore b/test/vboot/.gitignore
deleted file mode 100644
index 4631242..0000000
--- a/test/vboot/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-/*.dtb
-/test.fit
-/dev-keys
diff --git a/test/vboot/sandbox-kernel.dts b/test/vboot/sandbox-kernel.dts
deleted file mode 100644
index a1e853c..0000000
--- a/test/vboot/sandbox-kernel.dts
+++ /dev/null
@@ -1,7 +0,0 @@
-/dts-v1/;
-
-/ {
-	model = "Sandbox Verified Boot Test";
-	compatible = "sandbox";
-
-};
diff --git a/test/vboot/sandbox-u-boot.dts b/test/vboot/sandbox-u-boot.dts
deleted file mode 100644
index 63f8f40..0000000
--- a/test/vboot/sandbox-u-boot.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-/dts-v1/;
-
-/ {
-	model = "Sandbox Verified Boot Test";
-	compatible = "sandbox";
-
-	reset@0 {
-		compatible = "sandbox,reset";
-	};
-};
diff --git a/test/vboot/sign-configs-sha1.its b/test/vboot/sign-configs-sha1.its
deleted file mode 100644
index db2ed79..0000000
--- a/test/vboot/sign-configs-sha1.its
+++ /dev/null
@@ -1,45 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "Chrome OS kernel image with one or more FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel@1 {
-			data = /incbin/("test-kernel.bin");
-			type = "kernel_noload";
-			arch = "sandbox";
-			os = "linux";
-			compression = "none";
-			load = <0x4>;
-			entry = <0x8>;
-			kernel-version = <1>;
-			hash@1 {
-				algo = "sha1";
-			};
-		};
-		fdt@1 {
-			description = "snow";
-			data = /incbin/("sandbox-kernel.dtb");
-			type = "flat_dt";
-			arch = "sandbox";
-			compression = "none";
-			fdt-version = <1>;
-			hash@1 {
-				algo = "sha1";
-			};
-		};
-	};
-	configurations {
-		default = "conf@1";
-		conf@1 {
-			kernel = "kernel@1";
-			fdt = "fdt@1";
-			signature@1 {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-				sign-images = "fdt", "kernel";
-			};
-		};
-	};
-};
diff --git a/test/vboot/sign-configs-sha256.its b/test/vboot/sign-configs-sha256.its
deleted file mode 100644
index 1b3432e..0000000
--- a/test/vboot/sign-configs-sha256.its
+++ /dev/null
@@ -1,45 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "Chrome OS kernel image with one or more FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel@1 {
-			data = /incbin/("test-kernel.bin");
-			type = "kernel_noload";
-			arch = "sandbox";
-			os = "linux";
-			compression = "none";
-			load = <0x4>;
-			entry = <0x8>;
-			kernel-version = <1>;
-			hash@1 {
-				algo = "sha256";
-			};
-		};
-		fdt@1 {
-			description = "snow";
-			data = /incbin/("sandbox-kernel.dtb");
-			type = "flat_dt";
-			arch = "sandbox";
-			compression = "none";
-			fdt-version = <1>;
-			hash@1 {
-				algo = "sha256";
-			};
-		};
-	};
-	configurations {
-		default = "conf@1";
-		conf@1 {
-			kernel = "kernel@1";
-			fdt = "fdt@1";
-			signature@1 {
-				algo = "sha256,rsa2048";
-				key-name-hint = "dev";
-				sign-images = "fdt", "kernel";
-			};
-		};
-	};
-};
diff --git a/test/vboot/sign-images-sha1.its b/test/vboot/sign-images-sha1.its
deleted file mode 100644
index f69326a..0000000
--- a/test/vboot/sign-images-sha1.its
+++ /dev/null
@@ -1,42 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "Chrome OS kernel image with one or more FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel@1 {
-			data = /incbin/("test-kernel.bin");
-			type = "kernel_noload";
-			arch = "sandbox";
-			os = "linux";
-			compression = "none";
-			load = <0x4>;
-			entry = <0x8>;
-			kernel-version = <1>;
-			signature@1 {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-			};
-		};
-		fdt@1 {
-			description = "snow";
-			data = /incbin/("sandbox-kernel.dtb");
-			type = "flat_dt";
-			arch = "sandbox";
-			compression = "none";
-			fdt-version = <1>;
-			signature@1 {
-				algo = "sha1,rsa2048";
-				key-name-hint = "dev";
-			};
-		};
-	};
-	configurations {
-		default = "conf@1";
-		conf@1 {
-			kernel = "kernel@1";
-			fdt = "fdt@1";
-		};
-	};
-};
diff --git a/test/vboot/sign-images-sha256.its b/test/vboot/sign-images-sha256.its
deleted file mode 100644
index e6aa9fc..0000000
--- a/test/vboot/sign-images-sha256.its
+++ /dev/null
@@ -1,42 +0,0 @@
-/dts-v1/;
-
-/ {
-	description = "Chrome OS kernel image with one or more FDT blobs";
-	#address-cells = <1>;
-
-	images {
-		kernel@1 {
-			data = /incbin/("test-kernel.bin");
-			type = "kernel_noload";
-			arch = "sandbox";
-			os = "linux";
-			compression = "none";
-			load = <0x4>;
-			entry = <0x8>;
-			kernel-version = <1>;
-			signature@1 {
-				algo = "sha256,rsa2048";
-				key-name-hint = "dev";
-			};
-		};
-		fdt@1 {
-			description = "snow";
-			data = /incbin/("sandbox-kernel.dtb");
-			type = "flat_dt";
-			arch = "sandbox";
-			compression = "none";
-			fdt-version = <1>;
-			signature@1 {
-				algo = "sha256,rsa2048";
-				key-name-hint = "dev";
-			};
-		};
-	};
-	configurations {
-		default = "conf@1";
-		conf@1 {
-			kernel = "kernel@1";
-			fdt = "fdt@1";
-		};
-	};
-};
diff --git a/test/vboot/vboot_test.sh b/test/vboot/vboot_test.sh
deleted file mode 100755
index 6d7abb8..0000000
--- a/test/vboot/vboot_test.sh
+++ /dev/null
@@ -1,151 +0,0 @@
-#!/bin/bash
-#
-# Copyright (c) 2013, Google Inc.
-#
-# Simple Verified Boot Test Script
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-set -e
-
-# Run U-Boot and report the result
-# Args:
-#	$1:	Test message
-run_uboot() {
-	echo -n "Test Verified Boot Run: $1: "
-	${uboot} -d sandbox-u-boot.dtb >${tmp} -c '
-sb load hostfs - 100 test.fit;
-fdt addr 100;
-bootm 100;
-reset'
-	if ! grep -q "$2" ${tmp}; then
-		echo
-		echo "Verified boot key check failed, output follows:"
-		cat ${tmp}
-		false
-	else
-		echo "OK"
-	fi
-}
-
-echo "Simple Verified Boot Test"
-echo "========================="
-echo
-echo "Please see doc/uImage.FIT/verified-boot.txt for more information"
-echo
-
-err=0
-tmp=/tmp/vboot_test.$$
-
-dir=$(dirname $0)
-
-if [ -z ${O} ]; then
-	O=.
-fi
-O=$(readlink -f ${O})
-
-dtc="-I dts -O dtb -p 2000"
-uboot="${O}/u-boot"
-mkimage="${O}/tools/mkimage"
-fit_check_sign="${O}/tools/fit_check_sign"
-keys="${dir}/dev-keys"
-echo ${mkimage} -D "${dtc}"
-
-echo "Build keys"
-mkdir -p ${keys}
-
-PUBLIC_EXPONENT=${1}
-
-if [ -z "${PUBLIC_EXPONENT}" ]; then
-	PUBLIC_EXPONENT=65537
-fi
-
-# Create an RSA key pair
-openssl genpkey -algorithm RSA -out ${keys}/dev.key \
-    -pkeyopt rsa_keygen_bits:2048 \
-    -pkeyopt rsa_keygen_pubexp:${PUBLIC_EXPONENT} 2>/dev/null
-
-# Create a certificate containing the public key
-openssl req -batch -new -x509 -key ${keys}/dev.key -out ${keys}/dev.crt
-
-pushd ${dir} >/dev/null
-
-function do_test {
-	echo do $sha test
-	# Compile our device tree files for kernel and U-Boot
-	dtc -p 0x1000 sandbox-kernel.dts -O dtb -o sandbox-kernel.dtb
-	dtc -p 0x1000 sandbox-u-boot.dts -O dtb -o sandbox-u-boot.dtb
-
-	# Create a number kernel image with zeroes
-	head -c 5000 /dev/zero >test-kernel.bin
-
-	# Build the FIT, but don't sign anything yet
-	echo Build FIT with signed images
-	${mkimage} -D "${dtc}" -f sign-images-$sha.its test.fit >${tmp}
-
-	run_uboot "unsigned signatures:" "dev-"
-
-	# Sign images with our dev keys
-	echo Sign images
-	${mkimage} -D "${dtc}" -F -k dev-keys -K sandbox-u-boot.dtb \
-		-r test.fit >${tmp}
-
-	run_uboot "signed images" "dev+"
-
-
-	# Create a fresh .dtb without the public keys
-	dtc -p 0x1000 sandbox-u-boot.dts -O dtb -o sandbox-u-boot.dtb
-
-	echo Build FIT with signed configuration
-	${mkimage} -D "${dtc}" -f sign-configs-$sha.its test.fit >${tmp}
-
-	run_uboot "unsigned config" $sha"+ OK"
-
-	# Sign images with our dev keys
-	echo Sign images
-	${mkimage} -D "${dtc}" -F -k dev-keys -K sandbox-u-boot.dtb \
-		-r test.fit >${tmp}
-
-	run_uboot "signed config" "dev+"
-
-	echo check signed config on the host
-	if ! ${fit_check_sign} -f test.fit -k sandbox-u-boot.dtb >${tmp}; then
-		echo
-		echo "Verified boot key check on host failed, output follows:"
-		cat ${tmp}
-		false
-	else
-		if ! grep -q "dev+" ${tmp}; then
-			echo
-			echo "Verified boot key check failed, output follows:"
-			cat ${tmp}
-			false
-		else
-			echo "OK"
-		fi
-	fi
-
-	run_uboot "signed config" "dev+"
-
-	# Increment the first byte of the signature, which should cause failure
-	sig=$(fdtget -t bx test.fit /configurations/conf@1/signature@1 value)
-	newbyte=$(printf %x $((0x${sig:0:2} + 1)))
-	sig="${newbyte} ${sig:2}"
-	fdtput -t bx test.fit /configurations/conf@1/signature@1 value ${sig}
-
-	run_uboot "signed config with bad hash" "Bad Data Hash"
-}
-
-sha=sha1
-do_test
-sha=sha256
-do_test
-
-popd >/dev/null
-
-echo
-if ${ok}; then
-	echo "Test passed"
-else
-	echo "Test failed"
-fi
-- 
cgit v0.10.2


From 5a6f576663d59cb3e08a619510701b7e1dea6128 Mon Sep 17 00:00:00 2001
From: Ricardo Salveti de Araujo <rsalveti@rsalveti.net>
Date: Sun, 3 Jul 2016 13:59:01 -0300
Subject: dragonboard410c: prefer sdcard boot over emmc
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make the external devices the preferred ones when booting the system
(usb is already the first option). This allows users to easily boot
custom distributions without requiring them to reflash/customize u-boot.

Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Ricardo Salveti <rsalveti@rsalveti.net>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Tested-by: Andreas Färber <afaerber@suse.de>
Acked-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>

diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index 4b00922..74a827d 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -84,8 +84,8 @@
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(USB, usb, 0) \
-	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>
-- 
cgit v0.10.2


From a3e2efcb42be378659a5443346ca5c77317c30b9 Mon Sep 17 00:00:00 2001
From: Ricardo Salveti de Araujo <rsalveti@rsalveti.net>
Date: Sun, 3 Jul 2016 14:16:03 -0300
Subject: dragonboard410c: adding missing default addr for script and pxe boot

Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Ricardo Salveti <rsalveti@rsalveti.net>

diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index 74a827d..1dbe219 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -126,6 +126,8 @@ REFLASH(dragonboard/u-boot.img, 8)\
 	"fdtfile=apq8016-sbc.dtb\0" \
 	"fdt_addr_r=0x83000000\0"\
 	"ramdisk_addr_r=0x84000000\0"\
+	"scriptaddr=0x90000000\0"\
+	"pxefile_addr_r=0x90100000\0"\
 	BOOTENV
 
 #define CONFIG_ENV_IS_NOWHERE
-- 
cgit v0.10.2


From ba0a3c16e0c6697f0254644cc7a9849b77000eb8 Mon Sep 17 00:00:00 2001
From: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
Date: Fri, 8 Jul 2016 01:02:24 +0900
Subject: stm32: clk: Add 200MHz clock configuration for stm32f746 discovery
 board

This patch adds 200MHz clock configuration for stm32f746 discovery board.
This patch is based on STM32F4 and emcraft's[1].

[1]:  https://github.com/EmcraftSystems/u-boot

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 68bdab0..de55ae5 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -64,6 +64,52 @@ enum clock {
 };
 #define STM32_BUS_MASK          0xFFFF0000
 
+struct stm32_rcc_regs {
+	u32 cr;		/* RCC clock control */
+	u32 pllcfgr;	/* RCC PLL configuration */
+	u32 cfgr;	/* RCC clock configuration */
+	u32 cir;	/* RCC clock interrupt */
+	u32 ahb1rstr;	/* RCC AHB1 peripheral reset */
+	u32 ahb2rstr;	/* RCC AHB2 peripheral reset */
+	u32 ahb3rstr;	/* RCC AHB3 peripheral reset */
+	u32 rsv0;
+	u32 apb1rstr;	/* RCC APB1 peripheral reset */
+	u32 apb2rstr;	/* RCC APB2 peripheral reset */
+	u32 rsv1[2];
+	u32 ahb1enr;	/* RCC AHB1 peripheral clock enable */
+	u32 ahb2enr;	/* RCC AHB2 peripheral clock enable */
+	u32 ahb3enr;	/* RCC AHB3 peripheral clock enable */
+	u32 rsv2;
+	u32 apb1enr;	/* RCC APB1 peripheral clock enable */
+	u32 apb2enr;	/* RCC APB2 peripheral clock enable */
+	u32 rsv3[2];
+	u32 ahb1lpenr;	/* RCC AHB1 periph clk enable in low pwr mode */
+	u32 ahb2lpenr;	/* RCC AHB2 periph clk enable in low pwr mode */
+	u32 ahb3lpenr;	/* RCC AHB3 periph clk enable in low pwr mode */
+	u32 rsv4;
+	u32 apb1lpenr;	/* RCC APB1 periph clk enable in low pwr mode */
+	u32 apb2lpenr;	/* RCC APB2 periph clk enable in low pwr mode */
+	u32 rsv5[2];
+	u32 bdcr;	/* RCC Backup domain control */
+	u32 csr;	/* RCC clock control & status */
+	u32 rsv6[2];
+	u32 sscgr;	/* RCC spread spectrum clock generation */
+	u32 plli2scfgr;	/* RCC PLLI2S configuration */
+	u32 pllsaicfgr;
+	u32 dckcfgr;
+};
+#define STM32_RCC		((struct stm32_rcc_regs *)RCC_BASE)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+	u32 cr2;   /* power control register 2 */
+	u32 csr2;  /* power control/status register 2 */
+};
+#define STM32_PWR		((struct stm32_pwr_regs *)PWR_BASE)
+
 int configure_clocks(void);
+unsigned long clock_get(enum clock clck);
+void stm32_flash_latency_cfg(int latency);
 
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile
index 40f1ad3..643d4d9 100644
--- a/arch/arm/mach-stm32/stm32f7/Makefile
+++ b/arch/arm/mach-stm32/stm32f7/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += timer.o clock.o
+obj-y += timer.o clock.o soc.o
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
index 17a715b..78d22d4 100644
--- a/arch/arm/mach-stm32/stm32f7/clock.c
+++ b/arch/arm/mach-stm32/stm32f7/clock.c
@@ -11,6 +11,234 @@
 #include <asm/arch/stm32.h>
 #include <asm/arch/stm32_periph.h>
 
+#define RCC_CR_HSION		(1 << 0)
+#define RCC_CR_HSEON		(1 << 16)
+#define RCC_CR_HSERDY		(1 << 17)
+#define RCC_CR_HSEBYP		(1 << 18)
+#define RCC_CR_CSSON		(1 << 19)
+#define RCC_CR_PLLON		(1 << 24)
+#define RCC_CR_PLLRDY		(1 << 25)
+
+#define RCC_PLLCFGR_PLLM_MASK	0x3F
+#define RCC_PLLCFGR_PLLN_MASK	0x7FC0
+#define RCC_PLLCFGR_PLLP_MASK	0x30000
+#define RCC_PLLCFGR_PLLQ_MASK	0xF000000
+#define RCC_PLLCFGR_PLLSRC	(1 << 22)
+#define RCC_PLLCFGR_PLLM_SHIFT	0
+#define RCC_PLLCFGR_PLLN_SHIFT	6
+#define RCC_PLLCFGR_PLLP_SHIFT	16
+#define RCC_PLLCFGR_PLLQ_SHIFT	24
+
+#define RCC_CFGR_AHB_PSC_MASK	0xF0
+#define RCC_CFGR_APB1_PSC_MASK	0x1C00
+#define RCC_CFGR_APB2_PSC_MASK	0xE000
+#define RCC_CFGR_SW0		(1 << 0)
+#define RCC_CFGR_SW1		(1 << 1)
+#define RCC_CFGR_SW_MASK	0x3
+#define RCC_CFGR_SW_HSI		0
+#define RCC_CFGR_SW_HSE		RCC_CFGR_SW0
+#define RCC_CFGR_SW_PLL		RCC_CFGR_SW1
+#define RCC_CFGR_SWS0		(1 << 2)
+#define RCC_CFGR_SWS1		(1 << 3)
+#define RCC_CFGR_SWS_MASK	0xC
+#define RCC_CFGR_SWS_HSI	0
+#define RCC_CFGR_SWS_HSE	RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL	RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT	4
+#define RCC_CFGR_PPRE1_SHIFT	10
+#define RCC_CFGR_PPRE2_SHIFT	13
+
+#define RCC_APB1ENR_PWREN	(1 << 28)
+
+/*
+ * RCC USART specific definitions
+ */
+#define RCC_ENR_USART1EN		(1 << 4)
+#define RCC_ENR_USART2EN		(1 << 17)
+#define RCC_ENR_USART3EN		(1 << 18)
+#define RCC_ENR_USART6EN		(1 <<  5)
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN		(1 << 16)
+#define PWR_CR1_ODSWEN		(1 << 17)
+#define PWR_CSR1_ODRDY		(1 << 16)
+#define PWR_CSR1_ODSWRDY	(1 << 17)
+
+
+/*
+ * RCC GPIO specific definitions
+ */
+#define RCC_ENR_GPIO_A_EN	(1 << 0)
+#define RCC_ENR_GPIO_B_EN	(1 << 1)
+#define RCC_ENR_GPIO_C_EN	(1 << 2)
+#define RCC_ENR_GPIO_D_EN	(1 << 3)
+#define RCC_ENR_GPIO_E_EN	(1 << 4)
+#define RCC_ENR_GPIO_F_EN	(1 << 5)
+#define RCC_ENR_GPIO_G_EN	(1 << 6)
+#define RCC_ENR_GPIO_H_EN	(1 << 7)
+#define RCC_ENR_GPIO_I_EN	(1 << 8)
+#define RCC_ENR_GPIO_J_EN	(1 << 9)
+#define RCC_ENR_GPIO_K_EN	(1 << 10)
+
+struct pll_psc {
+	u8	pll_m;
+	u16	pll_n;
+	u8	pll_p;
+	u8	pll_q;
+	u8	ahb_psc;
+	u8	apb1_psc;
+	u8	apb2_psc;
+};
+
+#define AHB_PSC_1		0
+#define AHB_PSC_2		0x8
+#define AHB_PSC_4		0x9
+#define AHB_PSC_8		0xA
+#define AHB_PSC_16		0xB
+#define AHB_PSC_64		0xC
+#define AHB_PSC_128		0xD
+#define AHB_PSC_256		0xE
+#define AHB_PSC_512		0xF
+
+#define APB_PSC_1		0
+#define APB_PSC_2		0x4
+#define APB_PSC_4		0x5
+#define APB_PSC_8		0x6
+#define APB_PSC_16		0x7
+
+#if !defined(CONFIG_STM32_HSE_HZ)
+#error "CONFIG_STM32_HSE_HZ not defined!"
+#else
+#if (CONFIG_STM32_HSE_HZ == 25000000)
+#if (CONFIG_SYS_CLK_FREQ == 200000000)
+/* 200 MHz */
+struct pll_psc sys_pll_psc = {
+	.pll_m = 25,
+	.pll_n = 400,
+	.pll_p = 2,
+	.pll_q = 8,
+	.ahb_psc = AHB_PSC_1,
+	.apb1_psc = APB_PSC_4,
+	.apb2_psc = APB_PSC_2
+};
+#endif
+#else
+#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
+#endif
+#endif
+
+int configure_clocks(void)
+{
+	/* Reset RCC configuration */
+	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
+	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
+	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
+		| RCC_CR_PLLON));
+	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
+	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
+	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
+
+	/* Configure for HSE+PLL operation */
+	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
+	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
+		;
+
+	setbits_le32(&STM32_RCC->cfgr, ((
+		sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
+		| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
+		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
+
+	/* Configure the main PLL */
+	uint32_t pllcfgr = 0;
+	pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
+	pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
+	pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
+	pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
+	pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
+	writel(pllcfgr, &STM32_RCC->pllcfgr);
+
+	/* Enable the main PLL */
+	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
+	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
+		;
+
+	/* Enable high performance mode, System frequency up to 200 MHz */
+	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
+	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
+	/* Infinite wait! */
+	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
+		;
+	/* Enable the Over-drive switch */
+	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
+	/* Infinite wait! */
+	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
+		;
+
+	stm32_flash_latency_cfg(5);
+	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
+	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
+
+	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
+			RCC_CFGR_SWS_PLL)
+		;
+
+	return 0;
+}
+
+unsigned long clock_get(enum clock clck)
+{
+	u32 sysclk = 0;
+	u32 shift = 0;
+	/* Prescaler table lookups for clock computation */
+	u8 ahb_psc_table[16] = {
+		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
+	};
+	u8 apb_psc_table[8] = {
+		0, 0, 0, 0, 1, 2, 3, 4
+	};
+
+	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
+			RCC_CFGR_SWS_PLL) {
+		u16 pllm, plln, pllp;
+		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
+			>> RCC_PLLCFGR_PLLN_SHIFT);
+		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
+			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
+		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
+	}
+
+	switch (clck) {
+	case CLOCK_CORE:
+		return sysclk;
+		break;
+	case CLOCK_AHB:
+		shift = ahb_psc_table[(
+			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+			>> RCC_CFGR_HPRE_SHIFT)];
+		return sysclk >>= shift;
+		break;
+	case CLOCK_APB1:
+		shift = apb_psc_table[(
+			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+			>> RCC_CFGR_PPRE1_SHIFT)];
+		return sysclk >>= shift;
+		break;
+	case CLOCK_APB2:
+		shift = apb_psc_table[(
+			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+			>> RCC_CFGR_PPRE2_SHIFT)];
+		return sysclk >>= shift;
+		break;
+	default:
+		return 0;
+		break;
+	}
+}
+
+
 void clock_setup(int peripheral)
 {
 	switch (peripheral) {
diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c
new file mode 100644
index 0000000..6a1e019
--- /dev/null
+++ b/arch/arm/mach-stm32/stm32f7/soc.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+
+u32 get_cpu_rev(void)
+{
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	configure_clocks();
+
+	return 0;
+}
+
+void s_init(void)
+{
+}
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index cfbfab7..592c0bd 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -9,6 +9,7 @@
 #include <dm.h>
 #include <asm/io.h>
 #include <serial.h>
+#include <asm/arch/stm32.h>
 #include <dm/platform_data/serial_stm32x7.h>
 #include "serial_stm32x7.h"
 
@@ -18,7 +19,20 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct stm32x7_serial_platdata *plat = dev->platdata;
 	struct stm32_usart *const usart = plat->base;
-	writel(plat->clock/baudrate, &usart->brr);
+	u32  clock, int_div, frac_div, tmp;
+
+	if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE)
+		clock = clock_get(CLOCK_APB1);
+	else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE)
+		clock = clock_get(CLOCK_APB2);
+	else
+		return -EINVAL;
+
+	int_div = (25 * clock) / (4 * baudrate);
+	tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
+	frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
+	tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
+	writel(tmp, &usart->brr);
 
 	return 0;
 }
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index e544a21..e1140a8 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -42,7 +42,8 @@
 #define CONFIG_STM32_FLASH
 #define CONFIG_STM32X7_SERIAL
 
-#define CONFIG_SYS_CLK_FREQ		16*1000*1000 /* 180 MHz */
+#define CONFIG_STM32_HSE_HZ		25000000
+#define CONFIG_SYS_CLK_FREQ		200000000 /* 200 MHz */
 #define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
 
 #define CONFIG_CMDLINE_TAG
-- 
cgit v0.10.2


From 25c1b1353ce4b8188de6058f9f3b0d5d2dad8230 Mon Sep 17 00:00:00 2001
From: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
Date: Fri, 8 Jul 2016 01:02:25 +0900
Subject: stm32: Add SDRAM support for stm32f746 discovery board

This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's[1].

[1]:  https://github.com/EmcraftSystems/u-boot

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>

diff --git a/arch/arm/cpu/armv7m/config.mk b/arch/arm/cpu/armv7m/config.mk
index 4a53006..db4660e 100644
--- a/arch/arm/cpu/armv7m/config.mk
+++ b/arch/arm/cpu/armv7m/config.mk
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_CPPFLAGS += -march=armv7-m -mthumb
+PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -mno-unaligned-access
diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h
new file mode 100644
index 0000000..7dd5077
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/fmc.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2013
+ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MACH_FMC_H_
+#define _MACH_FMC_H_
+
+struct stm32_fmc_regs {
+	u32 sdcr1;	/* Control register 1 */
+	u32 sdcr2;	/* Control register 2 */
+	u32 sdtr1;	/* Timing register 1 */
+	u32 sdtr2;	/* Timing register 2 */
+	u32 sdcmr;	/* Mode register */
+	u32 sdrtr;	/* Refresh timing register */
+	u32 sdsr;	/* Status register */
+};
+
+/*
+ * FMC registers base
+ */
+#define STM32_SDRAM_FMC_BASE	0xA0000140
+#define STM32_SDRAM_FMC		((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT	13	/* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT	12	/* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT	10	/* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT	9	/* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT	7	/* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT	6	/* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT	4	/* Memory width shift */
+#define FMC_SDCR_NR_SHIFT	2	/* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT	0	/* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT	0	/* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT	4	/* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT	8	/* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT	12	/* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT	16	/* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT	20	/* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT	24	/* Row-to-column delay */
+
+
+#define FMC_SDCMR_NRFS_SHIFT	5
+
+#define FMC_SDCMR_MODE_NORMAL		0
+#define FMC_SDCMR_MODE_START_CLOCK	1
+#define FMC_SDCMR_MODE_PRECHARGE	2
+#define FMC_SDCMR_MODE_AUTOREFRESH	3
+#define FMC_SDCMR_MODE_WRITE_MODE	4
+#define FMC_SDCMR_MODE_SELFREFRESH	5
+#define FMC_SDCMR_MODE_POWERDOWN	6
+
+#define FMC_SDCMR_BANK_1		(1 << 4)
+#define FMC_SDCMR_BANK_2		(1 << 3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT	9
+
+#define FMC_SDSR_BUSY			(1 << 5)
+
+#define FMC_BUSY_WAIT()		do { \
+		__asm__ __volatile__ ("dsb" : : : "memory"); \
+		while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
+			; \
+	} while (0)
+
+
+#endif /* _MACH_FMC_H_ */
diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h
index 200444d..54d8a2b 100644
--- a/arch/arm/include/asm/armv7m.h
+++ b/arch/arm/include/asm/armv7m.h
@@ -51,10 +51,21 @@ struct v7m_mpu {
 #define V7M_MPU_CTRL_ENABLE		(1 << 0)
 #define V7M_MPU_CTRL_HFNMIENA		(1 << 1)
 
+#define V7M_MPU_CTRL_ENABLE		(1 << 0)
+#define V7M_MPU_CTRL_DISABLE		(0 << 0)
+#define V7M_MPU_CTRL_HFNMIENA		(1 << 1)
+
 #define V7M_MPU_RASR_EN			(1 << 0)
 #define V7M_MPU_RASR_SIZE_BITS		1
 #define V7M_MPU_RASR_SIZE_4GB		(31 << V7M_MPU_RASR_SIZE_BITS)
+#define V7M_MPU_RASR_SIZE_8MB		(24 << V7M_MPU_RASR_SIZE_BITS)
+#define V7M_MPU_RASR_TEX_SHIFT	19
+#define V7M_MPU_RASR_S_SHIFT		18
+#define V7M_MPU_RASR_C_SHIFT		17
+#define V7M_MPU_RASR_B_SHIFT		16
 #define V7M_MPU_RASR_AP_RW_RW		(3 << 24)
+#define V7M_MPU_RASR_XN_ENABLE	(0 << 28)
+#define V7M_MPU_RASR_XN_DISABLE (1 << 28)
 
 #endif /* !defined(__ASSEMBLY__) */
 #endif /* ARMV7M_H */
diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c
index 6a1e019..8baee99 100644
--- a/arch/arm/mach-stm32/stm32f7/soc.c
+++ b/arch/arm/mach-stm32/stm32f7/soc.c
@@ -19,6 +19,55 @@ int arch_cpu_init(void)
 {
 	configure_clocks();
 
+	/*
+		* Configure the memory protection unit (MPU)
+		* 0x00000000 - 0xffffffff: Strong-order, Shareable
+		* 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable
+	 */
+
+	 /* Disable MPU */
+	 writel(0, &V7M_MPU->ctrl);
+
+	 writel(
+		 0x00000000 /* address */
+		 | 1 << 4	/* VALID */
+		 | 0 << 0	/* REGION */
+		 , &V7M_MPU->rbar
+	 );
+
+	 /* Strong-order, Shareable */
+	 /* TEX=000, S=1, C=0, B=0*/
+	 writel(
+		 (V7M_MPU_RASR_XN_ENABLE
+			 | V7M_MPU_RASR_AP_RW_RW
+			 | 0x01 << V7M_MPU_RASR_S_SHIFT
+			 | 0x00 << V7M_MPU_RASR_TEX_SHIFT
+			 | V7M_MPU_RASR_SIZE_4GB
+			 | V7M_MPU_RASR_EN)
+		 , &V7M_MPU->rasr
+	 );
+
+	 writel(
+		 0xC0000000 /* address */
+		 | 1 << 4	/* VALID */
+		 | 1 << 0	/* REGION */
+		 , &V7M_MPU->rbar
+	 );
+
+	 /* Normal, Outer and inner Non-cacheable */
+	 /* TEX=001, S=0, C=0, B=0*/
+	 writel(
+		 (V7M_MPU_RASR_XN_ENABLE
+			 | V7M_MPU_RASR_AP_RW_RW
+			 | 0x01 << V7M_MPU_RASR_TEX_SHIFT
+			 | V7M_MPU_RASR_SIZE_8MB
+			 | V7M_MPU_RASR_EN)
+			 , &V7M_MPU->rasr
+	 );
+
+	 /* Enable MPU */
+	 writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+
 	return 0;
 }
 
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 0e04d14..404fdfa 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -10,6 +10,8 @@
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/rcc.h>
+#include <asm/arch/fmc.h>
 #include <dm/platdata.h>
 #include <dm/platform_data/serial_stm32x7.h>
 #include <asm/arch/stm32_periph.h>
@@ -33,6 +35,221 @@ const struct stm32_gpio_ctl gpio_ctl_usart = {
 	.af = STM32_GPIO_AF7
 };
 
+const struct stm32_gpio_ctl gpio_ctl_fmc = {
+	.mode = STM32_GPIO_MODE_AF,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_100M,
+	.pupd = STM32_GPIO_PUPD_NO,
+	.af = STM32_GPIO_AF12
+};
+
+static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
+	/* Chip is LQFP144, see DM00077036.pdf for details */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10},	/* 79, FMC_D15 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9},	/* 78, FMC_D14 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8},	/* 77, FMC_D13 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15},	/* 68, FMC_D12 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14},	/* 67, FMC_D11 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13},	/* 66, FMC_D10 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12},	/* 65, FMC_D9 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11},	/* 64, FMC_D8 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10},	/* 63, FMC_D7 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9},	/* 60, FMC_D6 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8},	/* 59, FMC_D5 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7},	/* 58, FMC_D4 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1},	/* 115, FMC_D3 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0},	/* 114, FMC_D2 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15},	/* 86, FMC_D1 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14},	/* 85, FMC_D0 */
+
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1},	/* 142, FMC_NBL1 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0},	/* 141, FMC_NBL0 */
+
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5},	/* 90, FMC_A15, BA1 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4},	/* 89, FMC_A14, BA0 */
+
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1},	/* 57, FMC_A11 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0},	/* 56, FMC_A10 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15},	/* 55, FMC_A9 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14},	/* 54, FMC_A8 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13},	/* 53, FMC_A7 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12},	/* 50, FMC_A6 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5},	/* 15, FMC_A5 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4},	/* 14, FMC_A4 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3},	/* 13, FMC_A3 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2},	/* 12, FMC_A2 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1},	/* 11, FMC_A1 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0},	/* 10, FMC_A0 */
+
+	{STM32_GPIO_PORT_H, STM32_GPIO_PIN_3},	/* 136, SDRAM_NE */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11},	/* 49, SDRAM_NRAS */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15},	/* 132, SDRAM_NCAS */
+	{STM32_GPIO_PORT_H, STM32_GPIO_PIN_5},	/* 26, SDRAM_NWE */
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_3},	/* 135, SDRAM_CKE */
+
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8},	/* 93, SDRAM_CLK */
+};
+
+static int fmc_setup_gpio(void)
+{
+	int rv = 0;
+	int i;
+
+	clock_setup(GPIO_B_CLOCK_CFG);
+	clock_setup(GPIO_C_CLOCK_CFG);
+	clock_setup(GPIO_D_CLOCK_CFG);
+	clock_setup(GPIO_E_CLOCK_CFG);
+	clock_setup(GPIO_F_CLOCK_CFG);
+	clock_setup(GPIO_G_CLOCK_CFG);
+	clock_setup(GPIO_H_CLOCK_CFG);
+
+	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
+		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
+				&gpio_ctl_fmc);
+		if (rv)
+			goto out;
+	}
+
+out:
+	return rv;
+}
+
+/*
+ * STM32 RCC FMC specific definitions
+ */
+#define RCC_ENR_FMC	(1 << 0)	/* FMC module clock  */
+
+static inline u32 _ns2clk(u32 ns, u32 freq)
+{
+	u32 tmp = freq/1000000;
+	return (tmp * ns) / 1000;
+}
+
+#define NS2CLK(ns) (_ns2clk(ns, freq))
+
+/*
+ * Following are timings for IS42S16400J, from corresponding datasheet
+ */
+#define SDRAM_CAS	3	/* 3 cycles */
+#define SDRAM_NB	1	/* Number of banks */
+#define SDRAM_MWID	1	/* 16 bit memory */
+
+#define SDRAM_NR	0x1	/* 12-bit row */
+#define SDRAM_NC	0x0	/* 8-bit col */
+#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
+#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
+
+#define SDRAM_TRRD	NS2CLK(12)
+#define SDRAM_TRCD	NS2CLK(18)
+#define SDRAM_TRP	NS2CLK(18)
+#define SDRAM_TRAS	NS2CLK(42)
+#define SDRAM_TRC	NS2CLK(60)
+#define SDRAM_TRFC	NS2CLK(60)
+#define SDRAM_TCDL	(1 - 1)
+#define SDRAM_TRDL	NS2CLK(12)
+#define SDRAM_TBDL	(1 - 1)
+#define SDRAM_TREF	(NS2CLK(64000000 / 8192) - 20)
+#define SDRAM_TCCD	(1 - 1)
+
+#define SDRAM_TXSR	SDRAM_TRFC	/* Row cycle time after precharge */
+#define SDRAM_TMRD	1		/* Page 10, Mode Register Set */
+
+
+/* Last data in to row precharge, need also comply ineq on page 1648 */
+#define SDRAM_TWR	max(\
+	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
+	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
+)
+
+
+#define SDRAM_MODE_BL_SHIFT	0
+#define SDRAM_MODE_CAS_SHIFT	4
+#define SDRAM_MODE_BL		0
+#define SDRAM_MODE_CAS		SDRAM_CAS
+
+int dram_init(void)
+{
+	u32 freq;
+	int rv;
+
+	rv = fmc_setup_gpio();
+	if (rv)
+		return rv;
+
+	setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
+
+	/*
+	 * Get frequency for NS2CLK calculation.
+	 */
+	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
+
+	writel(
+		CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
+		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
+		| SDRAM_NB << FMC_SDCR_NB_SHIFT
+		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
+		| SDRAM_NR << FMC_SDCR_NR_SHIFT
+		| SDRAM_NC << FMC_SDCR_NC_SHIFT
+		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
+		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
+		&STM32_SDRAM_FMC->sdcr1);
+
+	writel(
+		SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
+		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
+		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
+		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
+		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
+		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
+		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
+		&STM32_SDRAM_FMC->sdtr1);
+
+	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
+	       &STM32_SDRAM_FMC->sdcmr);
+
+	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
+	       &STM32_SDRAM_FMC->sdcmr);
+
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
+		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
+
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
+		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
+		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
+		&STM32_SDRAM_FMC->sdcmr);
+
+	udelay(100);
+
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
+	       &STM32_SDRAM_FMC->sdcmr);
+
+	FMC_BUSY_WAIT();
+
+	/* Refresh timer */
+	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
+
+	/*
+	 * Fill in global info with description of SRAM configuration
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+
+	gd->ram_size = CONFIG_SYS_RAM_SIZE;
+
+	return rv;
+}
+
 static const struct stm32_gpio_dsc usart_gpio[] = {
 	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
 	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7},	/* RX */
@@ -88,12 +305,3 @@ int board_init(void)
 
 	return 0;
 }
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
-	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
-
-	gd->ram_size = CONFIG_SYS_RAM_SIZE;
-	return 0;
-}
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index e1140a8..4391bff 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -24,13 +24,13 @@
  * Configuration of the external SDRAM memory
  */
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_RAM_SIZE		((64 + 192) << 10)
+#define CONFIG_SYS_RAM_SIZE		(8 * 1024 * 1024)
 #define CONFIG_SYS_RAM_CS		1
 #define CONFIG_SYS_RAM_FREQ_DIV		2
-#define CONFIG_SYS_RAM_BASE		0x20000000
+#define CONFIG_SYS_RAM_BASE		0xC0000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_RAM_BASE
-#define CONFIG_SYS_LOAD_ADDR		0x20000000
-#define CONFIG_LOADADDR			0x20000000
+#define CONFIG_SYS_LOAD_ADDR		0xC0400000
+#define CONFIG_LOADADDR			0xC0400000
 
 #define CONFIG_SYS_MAX_FLASH_SECT	8
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
-- 
cgit v0.10.2


From 4b2fd720a7b2f78c42d1565edf4c67f378c65440 Mon Sep 17 00:00:00 2001
From: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
Date: Fri, 8 Jul 2016 01:02:26 +0900
Subject: stm32: Change USART port to USART6 for stm32f746 discovery board

This change is to remove a halt at about 200KiB
while sending a large(1MiB) binary to a micro controller using USART1.
USART1 is connected to a PC via an on-board ST-Link debugger
that also functions as a USB-Serial converter.
However, it seems to loss some data occasionally.
So I changed the serial port to USART6 and connected it to the PC using
an FTDI USB-Serial cable, therefore the transmission was successfully
completed.

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
index 38adc4e..0bd4695 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -17,11 +17,13 @@
 enum periph_id {
 	UART1_GPIOA_9_10 = 0,
 	UART2_GPIOD_5_6,
+	UART6_GPIOC_6_7,
 };
 
 enum periph_clock {
 	USART1_CLOCK_CFG = 0,
 	USART2_CLOCK_CFG,
+	USART6_CLOCK_CFG,
 	GPIO_A_CLOCK_CFG,
 	GPIO_B_CLOCK_CFG,
 	GPIO_C_CLOCK_CFG,
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
index 78d22d4..ac47850 100644
--- a/arch/arm/mach-stm32/stm32f7/clock.c
+++ b/arch/arm/mach-stm32/stm32f7/clock.c
@@ -245,6 +245,9 @@ void clock_setup(int peripheral)
 	case USART1_CLOCK_CFG:
 		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
 		break;
+	case USART6_CLOCK_CFG:
+		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART6EN);
+		break;
 	case GPIO_A_CLOCK_CFG:
 		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
 		break;
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 404fdfa..47aa058 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -32,7 +32,7 @@ const struct stm32_gpio_ctl gpio_ctl_usart = {
 	.otype = STM32_GPIO_OTYPE_PP,
 	.speed = STM32_GPIO_SPEED_50M,
 	.pupd = STM32_GPIO_PUPD_UP,
-	.af = STM32_GPIO_AF7
+	.af = STM32_GPIO_AF8
 };
 
 const struct stm32_gpio_ctl gpio_ctl_fmc = {
@@ -251,8 +251,8 @@ int dram_init(void)
 }
 
 static const struct stm32_gpio_dsc usart_gpio[] = {
-	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
-	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7},	/* RX */
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_6},	/* TX */
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_7},	/* RX */
 };
 
 int uart_setup_gpio(void)
@@ -260,8 +260,7 @@ int uart_setup_gpio(void)
 	int i;
 	int rv = 0;
 
-	clock_setup(GPIO_A_CLOCK_CFG);
-	clock_setup(GPIO_B_CLOCK_CFG);
+	clock_setup(GPIO_C_CLOCK_CFG);
 	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
 		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
 		if (rv)
@@ -273,7 +272,7 @@ out:
 }
 
 static const struct stm32x7_serial_platdata serial_platdata = {
-	.base = (struct stm32_usart *)USART1_BASE,
+	.base = (struct stm32_usart *)USART6_BASE,
 	.clock = CONFIG_SYS_CLK_FREQ,
 };
 
@@ -292,7 +291,7 @@ int board_early_init_f(void)
 	int res;
 
 	res = uart_setup_gpio();
-	clock_setup(USART1_CLOCK_CFG);
+	clock_setup(USART6_CLOCK_CFG);
 	if (res)
 		return res;
 
-- 
cgit v0.10.2


From 19e8649e59f5632792ecccbf04a2401eddb03e44 Mon Sep 17 00:00:00 2001
From: Hector Palacios <hector.palacios@digi.com>
Date: Mon, 11 Jul 2016 12:34:37 +0200
Subject: bootm: fixup silent Linux out of BOOTM_STATE_LOADOS state

The function fixup_silent_linux() is called in status BOOTM_STATE_LOADOS
to silence Linux if variable 'silent' is set.
Currently only the 'bootm' command state machine contains
BOOTM_STATE_LOADOS, but others like 'booti' or 'bootz' commands do not.
This means silent Linux does not work with these commands.

This patch moves the fixup_silent_linux() call out of the
BOOTM_STATE_LOADOS state and into BOOTM_STATE_OS_PREP, to silence Linux
independently of the used command (booti, bootm or bootz).

Signed-off-by: Hector Palacios <hector.palacios@digi.com>

diff --git a/common/bootm.c b/common/bootm.c
index 2431019..9ed6428 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -635,10 +635,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 			goto err;
 		else if (ret == BOOTM_ERR_OVERLAP)
 			ret = 0;
-#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
-		if (images->os.os == IH_OS_LINUX)
-			fixup_silent_linux();
-#endif
 	}
 
 	/* Relocate the ramdisk */
@@ -678,13 +674,19 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
 		return 1;
 	}
 
+
 	/* Call various other states that are not generally used */
 	if (!ret && (states & BOOTM_STATE_OS_CMDLINE))
 		ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images);
 	if (!ret && (states & BOOTM_STATE_OS_BD_T))
 		ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images);
-	if (!ret && (states & BOOTM_STATE_OS_PREP))
+	if (!ret && (states & BOOTM_STATE_OS_PREP)) {
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
+		if (images->os.os == IH_OS_LINUX)
+			fixup_silent_linux();
+#endif
 		ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images);
+	}
 
 #ifdef CONFIG_TRACE
 	/* Pretend to run the OS, then run a user command */
-- 
cgit v0.10.2


From b6fefa76d02efb5dab47182ae4afc9a0edc4f41e Mon Sep 17 00:00:00 2001
From: Teddy Reed <teddy.reed@gmail.com>
Date: Mon, 11 Jul 2016 22:54:26 -0700
Subject: mkimage: fix missing break for -p switch

Signed-off-by: Teddy Reed <teddy.reed@gmail.com>
Reported-by: Coverity (CID: 150277)
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/mkimage.c b/tools/mkimage.c
index f589a41..d993958 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -232,6 +232,7 @@ static void process_args(int argc, char **argv)
 					params.cmdname, optarg);
 				exit(EXIT_FAILURE);
 			}
+			break;
 		case 'q':
 			params.quiet = 1;
 			break;
-- 
cgit v0.10.2


From 663f6fcaf0eb46999e8398e8fdbb7fdec6c372b8 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 12 Jul 2016 14:47:41 +0530
Subject: ARM: OMAP5+: Enable errata i727

Errata i727 is applicable on all OMAP5 and DRA7 variants but enabled only
on OMAP5 ES1.0. So, enable it on all platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 9a9c764..2b79010 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -37,7 +37,8 @@ void set_lpmode_selfrefresh(u32 base)
 void force_emif_self_refresh()
 {
 	set_lpmode_selfrefresh(EMIF1_BASE);
-	set_lpmode_selfrefresh(EMIF2_BASE);
+	if (!is_dra72x())
+		set_lpmode_selfrefresh(EMIF2_BASE);
 }
 
 inline u32 emif_num(u32 base)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 2f9693f..f317293 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -147,8 +147,7 @@ void early_system_init(void)
 	hw_data_init();
 
 #ifdef CONFIG_SPL_BUILD
-	if (warm_reset() &&
-	    (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
+	if (warm_reset())
 		force_emif_self_refresh();
 #endif
 	watchdog_init();
-- 
cgit v0.10.2


From 0ec807b2d861ae4555bc0d5459a2e97596671b09 Mon Sep 17 00:00:00 2001
From: Sekhar Nori <nsekhar@ti.com>
Date: Tue, 12 Jul 2016 16:24:48 +0530
Subject: configs: da850evm: enable bootz command

Enable bootz command on Texas Instruments DA850 EVM
board. This helps it boot zImage with device-tree
blob passed.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 0e281a5..40ab975 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
 CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
-- 
cgit v0.10.2


From 46d7a3b3d37aed4381765fd6985d06031d0e2a52 Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Mon, 13 Jun 2016 14:24:23 +0200
Subject: board_f: init designware watchdog if CONFIG_DESIGNWARE_WATCHDOG=y

The designware watchdog init is skipped even if CONFIG_DESIGNWARE_WATCHDOG
is enabled. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

diff --git a/common/board_f.c b/common/board_f.c
index d405b5b..05f6026 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -117,6 +117,7 @@ static int init_func_watchdog_init(void)
 # if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \
 	defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
 	defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
+	defined(CONFIG_DESIGNWARE_WATCHDOG) || \
 	defined(CONFIG_IMX_WATCHDOG))
 	hw_watchdog_init();
 # endif
-- 
cgit v0.10.2


From ba169d981f80517f057bf635df7e3dab203b9cea Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Mon, 13 Jun 2016 14:24:24 +0200
Subject: board_f: prevent misleading "Watchdog enabled" output

Output the "Watchdog enabled" message only if hw_watchdog_init()
call really happened.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

diff --git a/common/board_f.c b/common/board_f.c
index 05f6026..8d936cc 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -120,8 +120,8 @@ static int init_func_watchdog_init(void)
 	defined(CONFIG_DESIGNWARE_WATCHDOG) || \
 	defined(CONFIG_IMX_WATCHDOG))
 	hw_watchdog_init();
-# endif
 	puts("       Watchdog enabled\n");
+# endif
 	WATCHDOG_RESET();
 
 	return 0;
-- 
cgit v0.10.2


From 397b5697ad242408979a00dda14138aa1439f52b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 19:43:01 -0600
Subject: arm: Move check_cache_range() into a common place

This code is common, so move it into a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 1e4c214..7244c2e 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -69,23 +69,6 @@ void flush_dcache_all(void)
 	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-	int ok = 1;
-
-	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (!ok)
-		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-			start, stop);
-
-	return ok;
-}
-
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
 	if (!check_cache_range(start, stop))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 2839c86..2119382 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -29,23 +29,6 @@ void flush_dcache_all(void)
 	);
 }
 
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-	int ok = 1;
-
-	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (!ok)
-		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-			start, stop);
-
-	return ok;
-}
-
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
 	if (!check_cache_range(start, stop))
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 24fe0c5..2b63120 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -19,23 +19,6 @@
 void v7_flush_dcache_all(void);
 void v7_invalidate_dcache_all(void);
 
-static int check_cache_range(unsigned long start, unsigned long stop)
-{
-	int ok = 1;
-
-	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
-		ok = 0;
-
-	if (!ok)
-		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-			start, stop);
-
-	return ok;
-}
-
 static u32 get_ccsidr(void)
 {
 	u32 ccsidr;
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 1f63127..16e65c3 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -29,6 +29,8 @@ static inline void invalidate_l2_cache(void)
 }
 #endif
 
+int check_cache_range(unsigned long start, unsigned long stop);
+
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 3bd8710..642a952 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,6 +10,10 @@
 #include <common.h>
 #include <malloc.h>
 
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
 /*
  * Flush range from all levels of d-cache/unified-cache.
  * Affects the range [start, start + size - 1].
@@ -46,6 +50,24 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop)
 	/* An empty stub, real implementation should be in platform code */
 }
 
+int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok) {
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+		      start, stop);
+	}
+
+	return ok;
+}
+
 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 /*
  * Reserve one MMU section worth of address space below the malloc() area that
-- 
cgit v0.10.2


From 6b424611a8dee0444459c0c205a9d72f65f61456 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 19:43:02 -0600
Subject: arm: Don't invalidate unaligned cache regions

At present armv7 will unhappily invalidate a cache region and print an
error message. Make it skip the operation instead, as it does with other
cache operations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 2b63120..52f1856 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -44,27 +44,8 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
 {
 	u32 mva;
 
-	/*
-	 * If start address is not aligned to cache-line do not
-	 * invalidate the first cache-line
-	 */
-	if (start & (line_len - 1)) {
-		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
-			__func__, start);
-		/* move to next cache line */
-		start = (start + line_len - 1) & ~(line_len - 1);
-	}
-
-	/*
-	 * If stop address is not aligned to cache-line do not
-	 * invalidate the last cache-line
-	 */
-	if (stop & (line_len - 1)) {
-		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
-			__func__, stop);
-		/* align to the beginning of this cache line */
-		stop &= ~(line_len - 1);
-	}
+	if (!check_cache_range(start, stop))
+		return;
 
 	for (mva = start; mva < stop; mva = mva + line_len) {
 		/* DCIMVAC - Invalidate data cache by MVA to PoC */
-- 
cgit v0.10.2


From 5e7f74332465f0addc05634d351df8eeaa2015d2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 19:43:03 -0600
Subject: Add comments for debug() and pr_fmt

Add a note to each of these so it is more obvious how they work.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/common.h b/include/common.h
index 3feaae6..1bb8a79 100644
--- a/include/common.h
+++ b/include/common.h
@@ -101,6 +101,7 @@ typedef volatile unsigned char	vu_char;
 #define _DEBUG	0
 #endif
 
+/* Define this at the top of a file to add a prefix to debug messages */
 #ifndef pr_fmt
 #define pr_fmt(fmt) fmt
 #endif
@@ -116,6 +117,7 @@ typedef volatile unsigned char	vu_char;
 			printf(pr_fmt(fmt), ##args);	\
 	} while (0)
 
+/* Show a message if DEBUG is defined in a file */
 #define debug(fmt, args...)			\
 	debug_cond(_DEBUG, fmt, ##args)
 
-- 
cgit v0.10.2


From 982868264e7c61964bd392b10b2370f6757b14dc Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 19:43:04 -0600
Subject: Add warn_non_spl() to show a message in U-Boot proper

SPL tends to be more space-constrained that U-Boot proper. Some error
messages are best suppressed in SPL. Add a macros to make this easy.

warn_non_spl() does nothing when built in SPL code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/common.h b/include/common.h
index 1bb8a79..e9f0dea 100644
--- a/include/common.h
+++ b/include/common.h
@@ -101,6 +101,12 @@ typedef volatile unsigned char	vu_char;
 #define _DEBUG	0
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+#define _SPL_BUILD	1
+#else
+#define _SPL_BUILD	0
+#endif
+
 /* Define this at the top of a file to add a prefix to debug messages */
 #ifndef pr_fmt
 #define pr_fmt(fmt) fmt
@@ -121,6 +127,10 @@ typedef volatile unsigned char	vu_char;
 #define debug(fmt, args...)			\
 	debug_cond(_DEBUG, fmt, ##args)
 
+/* Show a message if not in SPL */
+#define warn_non_spl(fmt, args...)			\
+	debug_cond(!_SPL_BUILD, fmt, ##args)
+
 /*
  * An assertion is run-time check done in debug mode only. If DEBUG is not
  * defined then it is skipped. If DEBUG is defined and the assertion fails,
-- 
cgit v0.10.2


From bcc53bf095893fbdae531a9a7b5d4ef4a125a7fc Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 19:43:05 -0600
Subject: arm: Show cache warnings in U-Boot proper only

Avoid bloating the SPL image size.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 642a952..d330b09 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -61,8 +61,8 @@ int check_cache_range(unsigned long start, unsigned long stop)
 		ok = 0;
 
 	if (!ok) {
-		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
-		      start, stop);
+		warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			     start, stop);
 	}
 
 	return ok;
-- 
cgit v0.10.2


From 36b898b6bea839de7141b65df6ec02a97615c467 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 19 Jun 2016 19:51:00 -0600
Subject: rtc: Tidy up the code style

This code generates lots of checkpatch errors. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/rtc/date.c b/drivers/rtc/date.c
index 8c643a0..bfa2e13 100644
--- a/drivers/rtc/date.c
+++ b/drivers/rtc/date.c
@@ -5,10 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-/*
- * Date & Time support for Philips PCF8563 RTC
- */
-
 #include <common.h>
 #include <command.h>
 #include <errno.h>
@@ -28,53 +24,52 @@ static int month_days[12] = {
 	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 };
 
+static int month_offset[] = {
+	0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
+};
+
 /*
  * This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
  */
 int rtc_calc_weekday(struct rtc_time *tm)
 {
-	int leapsToDate;
-	int lastYear;
+	int leaps_to_date;
+	int last_year;
 	int day;
-	int MonthOffset[] = { 0,31,59,90,120,151,181,212,243,273,304,334 };
 
 	if (tm->tm_year < 1753)
-		return -EINVAL;
-	lastYear=tm->tm_year-1;
+		return -1;
+	last_year = tm->tm_year - 1;
 
-	/*
-	 * Number of leap corrections to apply up to end of last year
-	 */
-	leapsToDate = lastYear/4 - lastYear/100 + lastYear/400;
+	/* Number of leap corrections to apply up to end of last year */
+	leaps_to_date = last_year / 4 - last_year / 100 + last_year / 400;
 
 	/*
 	 * This year is a leap year if it is divisible by 4 except when it is
 	 * divisible by 100 unless it is divisible by 400
 	 *
-	 * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be
+	 * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 is.
 	 */
-	if((tm->tm_year%4==0) &&
-	   ((tm->tm_year%100!=0) || (tm->tm_year%400==0)) &&
-	   (tm->tm_mon>2)) {
-		/*
-		 * We are past Feb. 29 in a leap year
-		 */
-		day=1;
+	if (tm->tm_year % 4 == 0 &&
+	    ((tm->tm_year % 100 != 0) || (tm->tm_year % 400 == 0)) &&
+	    tm->tm_mon > 2) {
+		/* We are past Feb. 29 in a leap year */
+		day = 1;
 	} else {
-		day=0;
+		day = 0;
 	}
 
-	day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + tm->tm_mday;
-
-	tm->tm_wday=day%7;
+	day += last_year * 365 + leaps_to_date + month_offset[tm->tm_mon - 1] +
+			tm->tm_mday;
+	tm->tm_wday = day % 7;
 
 	return 0;
 }
 
 int rtc_to_tm(int tim, struct rtc_time *tm)
 {
-	register int    i;
-	register long   hms, day;
+	register int i;
+	register long hms, day;
 
 	day = tim / SECDAY;
 	hms = tim % SECDAY;
@@ -85,22 +80,19 @@ int rtc_to_tm(int tim, struct rtc_time *tm)
 	tm->tm_sec = (hms % 3600) % 60;
 
 	/* Number of years in days */
-	for (i = STARTOFTIME; day >= days_in_year(i); i++) {
+	for (i = STARTOFTIME; day >= days_in_year(i); i++)
 		day -= days_in_year(i);
-	}
 	tm->tm_year = i;
 
 	/* Number of months in days left */
-	if (leapyear(tm->tm_year)) {
+	if (leapyear(tm->tm_year))
 		days_in_month(FEBRUARY) = 29;
-	}
-	for (i = 1; day >= days_in_month(i); i++) {
+	for (i = 1; day >= days_in_month(i); i++)
 		day -= days_in_month(i);
-	}
 	days_in_month(FEBRUARY) = 28;
 	tm->tm_mon = i;
 
-	/* Days are what is left over (+1) from all that. */
+	/* Days are what is left over (+1) from all that */
 	tm->tm_mday = day + 1;
 
 	/* Zero unused fields */
@@ -113,19 +105,20 @@ int rtc_to_tm(int tim, struct rtc_time *tm)
 	return rtc_calc_weekday(tm);
 }
 
-/* Converts Gregorian date to seconds since 1970-01-01 00:00:00.
+/*
+ * Converts Gregorian date to seconds since 1970-01-01 00:00:00.
  * Assumes input in normal date format, i.e. 1980-12-31 23:59:59
  * => year=1980, mon=12, day=31, hour=23, min=59, sec=59.
  *
  * [For the Julian calendar (which was used in Russia before 1917,
  * Britain & colonies before 1752, anywhere else before 1582,
  * and is still in use by some communities) leave out the
- * -year/100+year/400 terms, and add 10.]
+ * -year / 100 + year / 400 terms, and add 10.]
  *
  * This algorithm was first published by Gauss (I think).
  *
  * WARNING: this function will overflow on 2106-02-07 06:28:16 on
- * machines were long is 32-bit! (However, as time_t is signed, we
+ * machines where long is 32-bit! (However, as time_t is signed, we
  * will already get problems at other places on 2038-01-19 03:14:08)
  */
 unsigned long rtc_mktime(const struct rtc_time *tm)
@@ -135,8 +128,8 @@ unsigned long rtc_mktime(const struct rtc_time *tm)
 	int days, hours;
 
 	mon -= 2;
-	if (0 >= (int)mon) {	/* 1..12 -> 11,12,1..10 */
-		mon += 12;		/* Puts Feb last since it has leap day */
+	if (0 >= (int)mon) {	/* 1..12 -> 11, 12, 1..10 */
+		mon += 12;	/* Puts Feb last since it has leap day */
 		year -= 1;
 	}
 
-- 
cgit v0.10.2


From 7fcdac0ee96fb19013056e7a083e46f74c8dad66 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:41 -0600
Subject: sandbox: Don't print a warning for CONFIG_I2C_COMPAT

Sandbox includes this code to provide build coverage. While we retain this
feature we should have sandbox build it. Sandbox does not in fact use the
I2C compatibility mode. Showing a warning for sandbox is just confusing,
since no conversion is expected.

Drop the warning for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/Makefile b/Makefile
index 88128ec..e5b07d8 100644
--- a/Makefile
+++ b/Makefile
@@ -801,7 +801,7 @@ quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
 all:		$(ALL-y)
-ifeq ($(CONFIG_DM_I2C_COMPAT),y)
+ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "===================== WARNING ======================"
 	@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
 	@echo "(possibly in a subsequent patch in your series)"
-- 
cgit v0.10.2


From 392853260d46e18963be60f97306aab6ce770652 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:42 -0600
Subject: README: Remove CONFIG_SYS_MALLOC_F_LEN comment

This option is now widely available, so remove the comment that it is only
available on ARM and sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/README b/README
index 26d5ad2..e906253 100644
--- a/README
+++ b/README
@@ -3835,9 +3835,6 @@ Configuration Settings:
 		The memory will be freed (or in fact just forgotten) when
 		U-Boot relocates itself.
 
-		Pre-relocation malloc() is only supported on ARM and sandbox
-		at present but is fairly easy to enable for other archs.
-
 - CONFIG_SYS_MALLOC_SIMPLE
 		Provides a simple and small malloc() and calloc() for those
 		boards which do not use the full malloc in SPL (which is
-- 
cgit v0.10.2


From 12c550d4fbfae272793c222c51af77613ffc5963 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:43 -0600
Subject: spl: Drop include of i2c.h

This file does not appear to use I2C, so drop this include.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 840910a..5fbf101 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -13,7 +13,6 @@
 #include <nand.h>
 #include <fat.h>
 #include <version.h>
-#include <i2c.h>
 #include <image.h>
 #include <malloc.h>
 #include <dm/root.h>
-- 
cgit v0.10.2


From 72a7e0760447ed46ca50174cb8798a2e84dedf85 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:44 -0600
Subject: Makefile: Allow the SPL final link rule to be overridden

Overriding the final link rule is possible with U-Boot proper. It us used to
create a sandbox image links with host libraries. To build a sandbox SPL
image we need the same feature for SPL.

To support this, update the SPL link rule so sandbox can override it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 0997fd9..2b5c995 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -241,8 +241,10 @@ cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
 $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
 	$(call if_changed,mksunxiboot)
 
-quiet_cmd_u-boot-spl = LD      $@
-      cmd_u-boot-spl = (cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+# Rule to link u-boot-spl
+# May be overridden by arch/$(ARCH)/config.mk
+quiet_cmd_u-boot-spl ?= LD      $@
+      cmd_u-boot-spl ?= (cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
 		       $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
 		       $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \
 		       $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN))
-- 
cgit v0.10.2


From d4e33f5a72accc891e3600cb2d2bc579004de9e1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:45 -0600
Subject: sandbox: Allow chaining from SPL to U-Boot proper

SPL is expected to load and run U-Boot. This needs to work with sandbox also.
Provide a function to locate the U-Boot image, and another to start it. This
allows SPL to function on sandbox as it does on other archs.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 8a4d719..2d63dd8 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -541,6 +541,57 @@ int os_jump_to_image(const void *dest, int size)
 	return unlink(fname);
 }
 
+int os_find_u_boot(char *fname, int maxlen)
+{
+	struct sandbox_state *state = state_get_current();
+	const char *progname = state->argv[0];
+	int len = strlen(progname);
+	char *p;
+	int fd;
+
+	if (len >= maxlen || len < 4)
+		return -ENOSPC;
+
+	/* Look for 'u-boot' in the same directory as 'u-boot-spl' */
+	strcpy(fname, progname);
+	if (!strcmp(fname + len - 4, "-spl")) {
+		fname[len - 4] = '\0';
+		fd = os_open(fname, O_RDONLY);
+		if (fd >= 0) {
+			close(fd);
+			return 0;
+		}
+	}
+
+	/* Look for 'u-boot' in the parent directory of spl/ */
+	p = strstr(fname, "/spl/");
+	if (p) {
+		strcpy(p, p + 4);
+		fd = os_open(fname, O_RDONLY);
+		if (fd >= 0) {
+			close(fd);
+			return 0;
+		}
+	}
+
+	return -ENOENT;
+}
+
+int os_spl_to_uboot(const char *fname)
+{
+	struct sandbox_state *state = state_get_current();
+	char *argv[state->argc + 1];
+	int ret;
+
+	memcpy(argv, state->argv, sizeof(char *) * (state->argc + 1));
+	argv[0] = (char *)fname;
+	ret = execv(fname, argv);
+	if (ret)
+		return ret;
+
+	return unlink(fname);
+}
+
 void os_localtime(struct rtc_time *rt)
 {
 	time_t t = time(NULL);
diff --git a/include/os.h b/include/os.h
index 954a48c..1782e50 100644
--- a/include/os.h
+++ b/include/os.h
@@ -287,6 +287,31 @@ int os_read_ram_buf(const char *fname);
 int os_jump_to_image(const void *dest, int size);
 
 /**
+ * os_find_u_boot() - Determine the path to U-Boot proper
+ *
+ * This function is intended to be called from within sandbox SPL. It uses
+ * a few heuristics to find U-Boot proper. Normally it is either in the same
+ * directory, or the directory above (since u-boot-spl is normally in an
+ * spl/ subdirectory when built).
+ *
+ * @fname:	Place to put full path to U-Boot
+ * @maxlen:	Maximum size of @fname
+ * @return 0 if OK, -NOSPC if the filename is too large, -ENOENT if not found
+ */
+int os_find_u_boot(char *fname, int maxlen);
+
+/**
+ * os_spl_to_uboot() - Run U-Boot proper
+ *
+ * When called from SPL, this runs U-Boot proper. The filename is obtained by
+ * calling os_find_u_boot().
+ *
+ * @fname:	Full pathname to U-Boot executable
+ * @return 0 if OK, -ve on error
+ */
+int os_spl_to_uboot(const char *fname);
+
+/**
  * Read the current system time
  *
  * This reads the current Local Time and places it into the provided
-- 
cgit v0.10.2


From 4cfc416701e2fb4214dffa78ba2c3f7e2ffed3bb Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:46 -0600
Subject: sandbox: Support building an SPL image

When building an SPL image, override the link flags so that it uses the
system libraries. This is similar to the way the non-SPL image is built.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 16fd6d5..6d62abb 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -20,4 +20,9 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds \
 	-Wl,--start-group $(u-boot-main) -Wl,--end-group \
 	$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
 
+cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
+	-Wl,--start-group $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
+	$(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) -Wl,--end-group \
+	$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)
+
 CONFIG_ARCH_DEVICE_TREE := sandbox
-- 
cgit v0.10.2


From 6e20650425842244603380c275e7d7701305d2a0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:47 -0600
Subject: sandbox: Correct header file order in cpu.c

The dm/ file should go at the end. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 196f3e1..7a622c8 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -4,10 +4,10 @@
  */
 #define DEBUG
 #include <common.h>
-#include <dm/root.h>
 #include <os.h>
 #include <asm/io.h>
 #include <asm/state.h>
+#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
cgit v0.10.2


From f4289cbd8a8d607399b507cb695b46cd771d6c1b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:48 -0600
Subject: sandbox: Add some missing headers in cpu.c

These headers are needed in case they are not transitively included.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 7a622c8..4975eb2 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -4,6 +4,8 @@
  */
 #define DEBUG
 #include <common.h>
+#include <errno.h>
+#include <libfdt.h>
 #include <os.h>
 #include <asm/io.h>
 #include <asm/state.h>
-- 
cgit v0.10.2


From a7d9caecd770684e6e189dfa24240145ba29379e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:49 -0600
Subject: sandbox: Don't use PCI in SPL

PCI is not supported in SPL for sandbox, so avoid using it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 4975eb2..2def722 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -57,7 +57,7 @@ int cleanup_before_linux_select(int flags)
 
 void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 {
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(CONFIG_SPL_BUILD)
 	unsigned long plen = len;
 	void *ptr;
 
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index 96761e2..7820c55 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -8,5 +8,7 @@
 #
 
 obj-y	+= interrupts.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_PCI)	+= pci_io.o
+endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
-- 
cgit v0.10.2


From d0d0746e0c7c9eeddc82106cf7d4c596eb45f6c2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:50 -0600
Subject: sandbox: Don't include the main loop in SPL

SPL does not have a command interface so we should not include the main loop
code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 969618e..6e4ec01 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -73,6 +73,7 @@ static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg)
 }
 SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help");
 
+#ifndef CONFIG_SPL_BUILD
 int sandbox_main_loop_init(void)
 {
 	struct sandbox_state *state = state_get_current();
@@ -97,6 +98,7 @@ int sandbox_main_loop_init(void)
 
 	return 0;
 }
+#endif
 
 static int sandbox_cmdline_cb_boot(struct sandbox_state *state,
 				      const char *arg)
-- 
cgit v0.10.2


From e961a66df91ea4cbf9b6978995f1ba6c8d67aa33 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:51 -0600
Subject: sandbox: Add basic SPL implementation

Add an sandbox implementation for the generic SPL framework. This supports
locating and running U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile
index 1b42fee..db43633 100644
--- a/arch/sandbox/cpu/Makefile
+++ b/arch/sandbox/cpu/Makefile
@@ -8,6 +8,7 @@
 #
 
 obj-y	:= cpu.o os.o start.o state.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
 obj-$(CONFIG_ETH_SANDBOX_RAW)	+= eth-raw-os.o
 obj-$(CONFIG_SANDBOX_SDL)	+= sdl.o
 
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
new file mode 100644
index 0000000..e17c0ed
--- /dev/null
+++ b/arch/sandbox/cpu/spl.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <os.h>
+#include <asm/spl.h>
+#include <asm/state.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong flag)
+{
+	struct sandbox_state *state = state_get_current();
+
+	gd->arch.ram_buf = state->ram_buf;
+	gd->ram_size = state->ram_size;
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_BOARD;
+}
+
+void spl_board_announce_boot_device(void)
+{
+	char fname[256];
+	int ret;
+
+	ret = os_find_u_boot(fname, sizeof(fname));
+	if (ret) {
+		printf("(%s not found, error %d)\n", fname, ret);
+		return;
+	}
+	printf("%s\n", fname);
+}
+
+int spl_board_load_image(void)
+{
+	char fname[256];
+	int ret;
+
+	ret = os_find_u_boot(fname, sizeof(fname));
+	if (ret)
+		return ret;
+
+	/* Hopefully this will not return */
+	return os_spl_to_uboot(fname);
+}
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
new file mode 100644
index 0000000..59f2401
--- /dev/null
+++ b/arch/sandbox/include/asm/spl.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __asm_spl_h
+#define __asm_spl_h
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+/**
+ * Board-specific load method for boards that have a special way of loading
+ * U-Boot, which does not fit with the existing SPL code.
+ *
+ * @return 0 on success, negative errno value on failure.
+ */
+int spl_board_load_image(void);
+
+enum {
+	BOOT_DEVICE_BOARD,
+};
+
+#endif
-- 
cgit v0.10.2


From 1c12bcee70d99fa4f4124a87ea965526ee164d3c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:52 -0600
Subject: sandbox: Don't use IDE and iotrace in SPL

These functions are not supported in SPL, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 23a0c40..4de89f8 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -16,8 +16,10 @@
 
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_IO_TRACE
 #define CONFIG_CMD_IOTRACE
+#endif
 
 #ifndef CONFIG_TIMER
 #define CONFIG_SYS_TIMER_RATE		1000000
@@ -192,6 +194,7 @@
 #define CONFIG_CMD_LZMADEC
 #define CONFIG_CMD_DATE
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_CMD_IDE
 #define CONFIG_SYS_IDE_MAXBUS		1
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0
@@ -201,6 +204,7 @@
 #define CONFIG_SYS_ATA_REG_OFFSET	1
 #define CONFIG_SYS_ATA_ALT_OFFSET	2
 #define CONFIG_SYS_ATA_STRIDE		4
+#endif
 
 #define CONFIG_SCSI
 #define CONFIG_SCSI_AHCI_PLAT
-- 
cgit v0.10.2


From 0110f509c85de1e4bc7fff301a1194fdee4bdc5f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:53 -0600
Subject: sandbox: serial: Don't sync video in SPL

SPL does not support an LCD display so there is no need to sync the video
when there is serial output.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index 58f882b..bcc3465 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -115,7 +115,9 @@ static int sandbox_serial_pending(struct udevice *dev, bool input)
 		return 0;
 
 	os_usleep(100);
+#ifndef CONFIG_SPL_BUILD
 	video_sync_all();
+#endif
 	if (next_index == serial_buf_read)
 		return 1;	/* buffer full */
 
-- 
cgit v0.10.2


From 8797b2cae3ac5ddb005665e4b5cde4783a4f5555 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:54 -0600
Subject: sandbox: Add a new sandbox_spl board

It is useful to be able to build SPL for sandbox. It provides additional
build coverage and allows SPL features to be tested in sandbox. However
it does not need worthwhile to always create an SPL build. It nearly
doubles the build time and the feature is (so far) seldom used.

So for now, create a separate build target for sandbox SPL. This allows
experimentation with this new feature without impacting existing workflows.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index a8a90cb..d4c1ee0 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -10,8 +10,13 @@ config SYS_BOARD
 config SYS_CPU
 	default "sandbox"
 
+config SANDBOX_SPL
+	bool "Enable SPL for sandbox"
+	select SUPPORT_SPL
+
 config SYS_CONFIG_NAME
-	default "sandbox"
+	default "sandbox_spl" if SANDBOX_SPL
+	default "sandbox" if !SANDBOX_SPL
 
 config PCI
 	bool "PCI support"
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
new file mode 100644
index 0000000..7e92b4a
--- /dev/null
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2011-2012 The Chromium OS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+SECTIONS
+{
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	__u_boot_sandbox_option_start = .;
+	_u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
+	__u_boot_sandbox_option_end = .;
+
+	__bss_start = .;
+}
+
+INSERT BEFORE .data;
diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS
index f5db773..4dcbf4b 100644
--- a/board/sandbox/MAINTAINERS
+++ b/board/sandbox/MAINTAINERS
@@ -11,3 +11,10 @@ S:	Maintained
 F:	board/sandbox/
 F:	include/configs/sandbox.h
 F:	configs/sandbox_noblk_defconfig
+
+SANDBOX SPL BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox_spl.h
+F:	configs/sandbox_spl_defconfig
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
new file mode 100644
index 0000000..d92597b
--- /dev/null
+++ b/configs/sandbox_spl_defconfig
@@ -0,0 +1,182 @@
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_MMC=y
+CONFIG_SANDBOX_SPL=y
+CONFIG_PCI=y
+CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_I8042_KEYB=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_FDT=y
+CONFIG_BOOTSTAGE_STASH=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_CONSOLE_RECORD=y
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_LOOPW=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DEMO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_QFW=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_HOSTFILE=y
+CONFIG_NETCONSOLE=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DEVRES=y
+CONFIG_DEBUG_DEVRES=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_ADC=y
+CONFIG_ADC_SANDBOX=y
+CONFIG_BLK=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_DEMO=y
+CONFIG_DM_DEMO_SIMPLE=y
+CONFIG_DM_DEMO_SHAPE=y
+CONFIG_PM8916_GPIO=y
+CONFIG_SANDBOX_GPIO=y
+CONFIG_DM_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_SANDBOX=y
+CONFIG_I2C_MUX=y
+CONFIG_SPL_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
+CONFIG_MISC=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_CROS_EC_SANDBOX=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_SPL_PWRSEQ=y
+CONFIG_SYSRESET=y
+CONFIG_DM_MMC_OPS=y
+CONFIG_SANDBOX_MMC=y
+CONFIG_SPI_FLASH_SANDBOX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_SANDBOX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_PINCTRL_SANDBOX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_PMIC_MAX77686=y
+CONFIG_PMIC_PM8916=y
+CONFIG_PMIC_RK808=y
+CONFIG_PMIC_S2MPS11=y
+CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_S5M8767=y
+CONFIG_PMIC_TPS65090=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_MAX77686=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_DM_REGULATOR_SANDBOX=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_SANDBOX=y
+CONFIG_DM_RESET=y
+CONFIG_SANDBOX_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_SANDBOX_SERIAL=y
+CONFIG_SOUND=y
+CONFIG_SOUND_SANDBOX=y
+CONFIG_SANDBOX_SPI=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
+CONFIG_TIMER=y
+CONFIG_TIMER_EARLY=y
+CONFIG_SANDBOX_TIMER=y
+CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EMUL=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CONSOLE_ROTATION=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_TPM=y
+CONFIG_LZ4=y
+CONFIG_ERRNO_STR=y
+CONFIG_UNIT_TEST=y
+CONFIG_UT_TIME=y
+CONFIG_UT_DM=y
+CONFIG_UT_ENV=y
diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h
new file mode 100644
index 0000000..7b5c3f3
--- /dev/null
+++ b/include/configs/sandbox_spl.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SANDBOX_SPL_CONFIG_H
+#define __SANDBOX_SPL_CONFIG_H
+
+#include <configs/sandbox.h>
+
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#endif
-- 
cgit v0.10.2


From a091a8f084f731953fa77a3da3b5bec72d37ad0f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:55 -0600
Subject: sandbox: Add a test device that uses of-platdata

Start up the test devices. These print out of-platdata contents, providing a
check that the of-platdata feature is working correctly.

The device-tree changes are made to sandbox.dts rather than test.dts. since
the former controls the of-platdata generation.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index e17c0ed..e8349c0 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <os.h>
+#include <spl.h>
 #include <asm/spl.h>
 #include <asm/state.h>
 
@@ -49,3 +50,19 @@ int spl_board_load_image(void)
 	/* Hopefully this will not return */
 	return os_spl_to_uboot(fname);
 }
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	preloader_console_init();
+
+	/*
+	* Scan all the devices so that we can output their platform data. See
+	* sandbox_spl_probe().
+	*/
+	for (uclass_first_device(UCLASS_MISC, &dev);
+	dev;
+	uclass_next_device(&dev))
+		;
+}
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 2ae4014..e6d336f 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -172,6 +172,37 @@
 		};
 	};
 
+	spl-test {
+		u-boot,dm-pre-reloc;
+		compatible = "sandbox,spl-test";
+		boolval;
+		intval = <1>;
+		intarray = <2 3 4>;
+		byteval = [05];
+		bytearray = [06];
+		longbytearray = [09 0a 0b 0c 0d 0e 0f 10 11];
+		stringval = "message";
+		stringarray = "multi-word", "message";
+	};
+
+	spl-test2 {
+		u-boot,dm-pre-reloc;
+		compatible = "sandbox,spl-test";
+		intval = <3>;
+		intarray = <5>;
+		byteval = [08];
+		bytearray = [01 23 34];
+		longbytearray = [09 0a 0b 0c];
+		stringval = "message2";
+		stringarray = "another", "multi-word", "message";
+	};
+
+	spl-test3 {
+		u-boot,dm-pre-reloc;
+		compatible = "sandbox,spl-test";
+		stringarray = "one";
+	};
+
 	square {
 		compatible = "demo-shape";
 		colour = "blue";
diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h
index 7b5c3f3..ffc3098 100644
--- a/include/configs/sandbox_spl.h
+++ b/include/configs/sandbox_spl.h
@@ -8,6 +8,8 @@
 
 #include <configs/sandbox.h>
 
+#define CONFIG_SPL_BOARD_INIT
+
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_FRAMEWORK
-- 
cgit v0.10.2


From d223e0a82255b5fa6049f92556236f8ffd6b745c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:56 -0600
Subject: dm: spl: Don't set up device tree with of-platdata

When this feature is enabled, we should not access the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 5fbf101..59f41a1 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -202,7 +202,7 @@ int spl_init(void)
 	gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
 	gd->malloc_ptr = 0;
 #endif
-	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+	if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
 		ret = fdtdec_setup();
 		if (ret) {
 			debug("fdtdec_setup() returned error %d\n", ret);
-- 
cgit v0.10.2


From 054b3a1e80fcbca02cb0d0728629af02f18517f5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:57 -0600
Subject: dm: Makefile: Build of-platdata before SPL

Since SPL needs the of-platdata structures, build these before starting
to build any SPL components.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/Makefile b/Makefile
index e5b07d8..84bb620 100644
--- a/Makefile
+++ b/Makefile
@@ -1318,7 +1318,8 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 
 spl/u-boot-spl.bin: spl/u-boot-spl
 	@:
-spl/u-boot-spl: tools prepare $(if $(CONFIG_OF_SEPARATE),dts/dt.dtb)
+spl/u-boot-spl: tools prepare \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
 	$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
-- 
cgit v0.10.2


From 29629eb897f8d8119b06477d0ca3c4b424726e51 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:58 -0600
Subject: dm: core: Don't use device tree with of-platdata

When CONFIG_SPL_OF_PLATDATA is enabled we should not access the device
tree. Remove all references to this in the core driver-model code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index f7fb0cc..d8f9d5b 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -608,7 +608,7 @@ const char *dev_get_uclass_name(struct udevice *dev)
 
 fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
 {
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 	fdt_addr_t addr;
 
 	if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 0c27717..6a634e6 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -99,7 +99,7 @@ int device_bind_driver_to_node(struct udevice *parent, const char *drv_name,
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 /**
  * driver_check_compatible() - Check if a driver is compatible with this node
  *
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 95886ad..1587024 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -188,7 +188,7 @@ int dm_scan_platdata(bool pre_reloc_only)
 	return ret;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
 		     bool pre_reloc_only)
 {
@@ -244,7 +244,7 @@ int dm_init_and_scan(bool pre_reloc_only)
 		return ret;
 	}
 
-	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+	if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
 		ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
 		if (ret) {
 			debug("dm_scan_fdt() failed: %d\n", ret);
-- 
cgit v0.10.2


From 3b2a29e0971397085c616c89a3a09f2609f50ca4 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:57:59 -0600
Subject: dm: regmap: Add a dummy implementation for of-platdata

Add a placeholder for now so that this code will compile. It currently does
nothing.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 519832f..7e073cf 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -15,6 +15,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+int regmap_init_mem_platdata(struct udevice *dev, fdt32_t *reg, int size,
+			     struct regmap **mapp)
+{
+	/* TODO(sjg@chromium.org): Implement this when needed */
+	return 0;
+}
+#else
 int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
 {
 	const void *blob = gd->fdt_blob;
@@ -64,6 +72,7 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
 
 	return 0;
 }
+#endif
 
 void *regmap_get_range(struct regmap *map, unsigned int range_num)
 {
diff --git a/include/regmap.h b/include/regmap.h
index eccf770..922b39f 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -56,6 +56,9 @@ int regmap_read(struct regmap *map, uint offset, uint *valp);
  */
 int regmap_init_mem(struct udevice *dev, struct regmap **mapp);
 
+int regmap_init_mem_platdata(struct udevice *dev, fdt32_t *reg, int size,
+			     struct regmap **mapp);
+
 /**
  * regmap_get_range() - Obtain the base memory address of a regmap range
  *
-- 
cgit v0.10.2


From 04ecf36ba60f41f695095226e53310b4acaebf1e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:00 -0600
Subject: dm: syscon: Add support for of-platdata

Provide a new function which can cope with obtaining information from
of-platdata instead of the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index e03f46a..01bd968 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -29,7 +29,20 @@ static int syscon_pre_probe(struct udevice *dev)
 {
 	struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
 
+	/*
+	 * With OF_PLATDATA we really have no way of knowing the format of
+	 * the device-specific platform data. So we assume that it starts with
+	 * a 'reg' member, and this holds a single address and size. Drivers
+	 * using OF_PLATDATA will need to ensure that this is true.
+	 */
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct syscon_base_platdata *plat = dev_get_platdata(dev);
+
+	return regmap_init_mem_platdata(dev, plat->reg, ARRAY_SIZE(plat->reg),
+					&priv->regmap);
+#else
 	return regmap_init_mem(dev, &priv->regmap);
+#endif
 }
 
 int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
diff --git a/include/syscon.h b/include/syscon.h
index 4593b6e..34842aa 100644
--- a/include/syscon.h
+++ b/include/syscon.h
@@ -23,6 +23,17 @@ struct syscon_ops {
 
 #define syscon_get_ops(dev)        ((struct syscon_ops *)(dev)->driver->ops)
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+/*
+ * We don't support 64-bit machines. If they are so resource-contrained that
+ * they need to use OF_PLATDATA, something is horribly wrong with the
+ * education of our hardware engineers.
+ */
+struct syscon_base_platdata {
+	u32 reg[2];
+};
+#endif
+
 /**
  * syscon_get_regmap() - Get access to a register map
  *
-- 
cgit v0.10.2


From bab8233a1d17de222e83e0cbf8eb1d9d691adaf3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:01 -0600
Subject: dm: sandbox: Add a simple driver to test of-platdata

Add a driver which uses of-platdata to obtain its platform data. This can
be used to test the feature in sandbox. It displays the contents of its
platform data.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 066639b..3eac024 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -35,6 +35,11 @@ obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
 obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
 obj-$(CONFIG_STATUS_LED) += status_led.o
 obj-$(CONFIG_SANDBOX) += swap_case.o
+ifdef CONFIG_SPL_OF_PLATDATA
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
+endif
+endif
 obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/spltest_sandbox.c b/drivers/misc/spltest_sandbox.c
new file mode 100644
index 0000000..1fef825
--- /dev/null
+++ b/drivers/misc/spltest_sandbox.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_spl_probe(struct udevice *dev)
+{
+	struct dtd_sandbox_spl_test *plat = dev_get_platdata(dev);
+	int i;
+
+	printf("of-platdata probe:\n");
+	printf("bool %d\n", plat->boolval);
+
+	printf("byte %02x\n", plat->byteval);
+	printf("bytearray");
+	for (i = 0; i < sizeof(plat->bytearray); i++)
+		printf(" %02x", plat->bytearray[i]);
+	printf("\n");
+
+	printf("int %d\n", plat->intval);
+	printf("intarray");
+	for (i = 0; i < ARRAY_SIZE(plat->intarray); i++)
+		printf(" %d", plat->intarray[i]);
+	printf("\n");
+
+	printf("longbytearray");
+	for (i = 0; i < sizeof(plat->longbytearray); i++)
+		printf(" %02x", plat->longbytearray[i]);
+	printf("\n");
+
+	printf("string %s\n", plat->stringval);
+	printf("stringarray");
+	for (i = 0; i < ARRAY_SIZE(plat->stringarray); i++)
+		printf(" \"%s\"", plat->stringarray[i]);
+	printf("\n");
+
+	return 0;
+}
+
+U_BOOT_DRIVER(sandbox_spl_test) = {
+	.name	= "sandbox_spl_test",
+	.id	= UCLASS_MISC,
+	.flags	= DM_FLAG_PRE_RELOC,
+	.probe	= sandbox_spl_probe,
+};
-- 
cgit v0.10.2


From f24770d8124c097b7b57ccc22b67aaf02bb6e850 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:02 -0600
Subject: dm: Add a header that provides access to the of-platdata structs

This header can be included from anywhere, but will only pull in the
of-platdata struct definitions when this feature is enabled (and only in
SPL).

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/include/dt-structs.h b/include/dt-structs.h
new file mode 100644
index 0000000..e13afa6
--- /dev/null
+++ b/include/dt-structs.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_STTUCTS
+#define __DT_STTUCTS
+
+/* These structures may only be used in SPL */
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct phandle_2_cell {
+	const void *node;
+	int id;
+};
+#include <generated/dt-structs.h>
+#endif
+
+#endif
-- 
cgit v0.10.2


From 7423daa60eb30b6613dfc19a51c55de23fd4d703 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:03 -0600
Subject: dm: clk: Add support for of-platdata

Add support for this feature in the core clock code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 6e4d672..e0f8567 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -10,6 +10,7 @@
 #include <clk.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <dt-structs.h>
 #include <errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -21,6 +22,22 @@ static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 #ifdef CONFIG_SPL_BUILD
+# if CONFIG_IS_ENABLED(OF_PLATDATA)
+int clk_get_by_index_platdata(struct udevice *dev, int index,
+			      struct phandle_2_cell *cells, struct clk *clk)
+{
+	int ret;
+
+	if (index != 0)
+		return -ENOSYS;
+	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
+	if (ret)
+		return ret;
+	clk->id = cells[0].id;
+
+	return 0;
+}
+# else
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 {
 	int ret;
@@ -39,6 +56,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 	clk->id = cell[1];
 	return 0;
 }
+# endif /* OF_PLATDATA */
 
 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
 {
@@ -117,8 +135,8 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
 
 	return clk_get_by_index(dev, index, clk);
 }
-#endif
-#endif
+#endif /* CONFIG_SPL_BUILD */
+#endif /* OF_CONTROL */
 
 int clk_request(struct udevice *dev, struct clk *clk)
 {
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 797e537..9c4d2b3 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -30,9 +30,11 @@ const struct clk_ops clk_fixed_rate_ops = {
 
 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	to_clk_fixed_rate(dev)->fixed_rate =
 				fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 					       "clock-frequency", 0);
+#endif
 
 	return 0;
 }
diff --git a/include/clk.h b/include/clk.h
index 2f31cf7..161bc28 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -60,6 +60,10 @@ struct clk {
 };
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+struct phandle_2_cell;
+int clk_get_by_index_platdata(struct udevice *dev, int index,
+			      struct phandle_2_cell *cells, struct clk *clk);
+
 /**
  * clock_get_by_index - Get/request a clock by integer index.
  *
-- 
cgit v0.10.2


From b484b0daefc43bb3a6258a44040b53602060b2af Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:04 -0600
Subject: dm: serial: Add support for of-platdata

When this feature is enabled, we cannot access the device tree to find out
which serial device to use. Just use the first serial driver we find.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 0ce5c44..19f38e1 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -33,7 +33,13 @@ static void serial_find_console_or_panic(void)
 	struct udevice *dev;
 	int node;
 
-	if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
+	if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+		uclass_first_device(UCLASS_SERIAL, &dev);
+		if (dev) {
+			gd->cur_serial_dev = dev;
+			return;
+		}
+	} else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
 		/* Check for a chosen console */
 		node = fdtdec_get_chosen_node(blob, "stdout-path");
 		if (node < 0) {
-- 
cgit v0.10.2


From 7a53a54073e663d79ea0e08818e98f14fde5685a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:05 -0600
Subject: dm: Don't include fdtdec functions when of-platdata is enabled

We cannot access the device tree in this case, so avoid compiling in the
various device-tree helper functions.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/lib/Makefile b/lib/Makefile
index f48d901..f6a8ba1 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -48,11 +48,10 @@ obj-$(CONFIG_$(SPL_)SHA1) += sha1.o
 obj-$(CONFIG_$(SPL_)SHA256) += sha256.o
 
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
-ifdef CONFIG_SPL_OF_CONTROL
-obj-$(CONFIG_OF_LIBFDT) += libfdt/
-endif
+ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy)
 obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
 obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
+endif
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
-- 
cgit v0.10.2


From 2789ddb9d5bc6acd1f7a2822fed08cd7cf2a965e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:06 -0600
Subject: dm: Add an option to enable the of-platdata feature

Add a Kconfig option to enable this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/dts/Kconfig b/dts/Kconfig
index c56c129..4b7d8b1 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -85,4 +85,25 @@ config OF_SPL_REMOVE_PROPS
 	  can be discarded. This option defines the list of properties to
 	  discard.
 
+config SPL_OF_PLATDATA
+	bool "Generate platform data for use in SPL"
+	depends on SPL_OF_CONTROL
+	help
+	  For very constrained SPL environments the overhead of decoding
+	  device tree nodes and converting their contents into platform data
+	  is too large. This overhead includes libfdt code as well as the
+	  device tree contents itself. The latter is fairly compact, but the
+	  former can add 3KB or more to a Thumb 2 Image.
+
+	  This option enables generation of platform data from the device
+	  tree as C code. This code creates devices using U_BOOT_DEVICE()
+	  declarations. The benefit is that it allows driver code to access
+	  the platform data directly in C structures, avoidin the libfdt
+	  overhead.
+
+	  This option works by generating C structure declarations for each
+	  compatible string, then adding platform data and U_BOOT_DEVICE
+	  declarations for each node. See README.platdata for more
+	  information.
+
 endmenu
-- 
cgit v0.10.2


From 39782afb1ae86c15e59b1118278513a1a545652c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:07 -0600
Subject: dm: Add a README for of-platdata

Add documentation on how this works, including the benefits and drawbacks.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/driver-model/of-plat.txt b/doc/driver-model/of-plat.txt
new file mode 100644
index 0000000..96b9b46
--- /dev/null
+++ b/doc/driver-model/of-plat.txt
@@ -0,0 +1,268 @@
+Driver Model Compiled-in Device Tree / Platform Data
+====================================================
+
+
+Introduction
+------------
+
+Device tree is the standard configuration method in U-Boot. It is used to
+define what devices are in the system and provide configuration information
+to these devices.
+
+The overhead of adding device tree access to U-Boot is fairly modest,
+approximately 3KB on Thumb 2 (plus the size of the DT itself). This means
+that in most cases it is best to use device tree for configuration.
+
+However there are some very constrained environments where U-Boot needs to
+work. These include SPL with severe memory limitations. For example, some
+SoCs require a 16KB SPL image which must include a full MMC stack. In this
+case the overhead of device tree access may be too great.
+
+It is possible to create platform data manually by defining C structures
+for it, and referencing that data in a U_BOOT_DEVICE() declaration. This
+bypasses the use of device tree completely, but is an available option for
+SPL.
+
+As an alternative, a new 'of-platdata' feature is provided. This converts
+device tree contents into C code which can be compiled into the SPL binary.
+This saves the 3KB of code overhead and perhaps a few hundred more bytes due
+to more efficient storage of the data.
+
+
+Caveats
+-------
+
+There are many problems with this features. It should only be used when
+stricly necessary. Notable problems include:
+
+   - Device tree does not describe data types but the C code must define a
+        type for each property. Thesee are guessed using heuristics which
+        are wrong in several fairly common cases. For example an 8-byte value
+        is considered to be a 2-item integer array, and is byte-swapped. A
+        boolean value that is not present means 'false', but cannot be
+        included in the structures since there is generally no mention of it
+        in the device tree file.
+
+   - Naming of nodes and properties is automatic. This means that they follow
+        the naming in the device tree, which may result in C identifiers that
+        look a bit strange
+
+   - It is not possible to find a value given a property name. Code must use
+        the associated C member variable directly in the code. This makes
+        the code less robust in the face of device-tree changes. It also
+        makes it very unlikely that your driver code will be useful for more
+        than one SoC. Even if the code is common, each SoC will end up with
+        a different C struct and format for the platform data.
+
+   - The platform data is provided to drivers as a C structure. The driver
+        must use the same structure to access the data. Since a driver
+        normally also supports device tree it must use #ifdef to separate
+        out this code, since the structures are only available in SPL.
+
+
+How it works
+------------
+
+The feature is enabled by CONFIG SPL_OF_PLATDATA. This is only available
+in SPL and should be tested with:
+
+        #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
+
+A new tool called 'dtoc' converts a device tree file either into a set of
+struct declarations, one for each compatible node, or a set of
+U_BOOT_DEVICE() declarations along with the actual platform data for each
+device. As an example, consider this MMC node:
+
+        sdmmc: dwmmc@ff0c0000 {
+                compatible = "rockchip,rk3288-dw-mshc";
+                clock-freq-min-max = <400000 150000000>;
+                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                fifo-depth = <0x100>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                reg = <0xff0c0000 0x4000>;
+                bus-width = <4>;
+                cap-mmc-highspeed;
+                cap-sd-highspeed;
+                card-detect-delay = <200>;
+                disable-wp;
+                num-slots = <1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+                vmmc-supply = <&vcc_sd>;
+                status = "okay";
+                u-boot,dm-pre-reloc;
+        };
+
+
+Some of these properties are dropped by U-Boot under control of the
+CONFIG_OF_SPL_REMOVE_PROPS option. The rest are processed. This will produce
+the following C struct declaration:
+
+struct dtd_rockchip_rk3288_dw_mshc {
+        fdt32_t         bus_width;
+        bool            cap_mmc_highspeed;
+        bool            cap_sd_highspeed;
+        fdt32_t         card_detect_delay;
+        fdt32_t         clock_freq_min_max[2];
+        struct phandle_2_cell clocks[4];
+        bool            disable_wp;
+        fdt32_t         fifo_depth;
+        fdt32_t         interrupts[3];
+        fdt32_t         num_slots;
+        fdt32_t         reg[2];
+        bool            u_boot_dm_pre_reloc;
+        fdt32_t         vmmc_supply;
+};
+
+and the following device declaration:
+
+static struct dtd_rockchip_rk3288_dw_mshc dtv_dwmmc_at_ff0c0000 = {
+        .fifo_depth             = 0x100,
+        .cap_sd_highspeed       = true,
+        .interrupts             = {0x0, 0x20, 0x4},
+        .clock_freq_min_max     = {0x61a80, 0x8f0d180},
+        .vmmc_supply            = 0xb,
+        .num_slots              = 0x1,
+        .clocks                 = {{&dtv_clock_controller_at_ff760000, 456}, {&dtv_clock_controller_at_ff760000, 68}, {&dtv_clock_controller_at_ff760000, 114}, {&dtv_clock_controller_at_ff760000, 118}},
+        .cap_mmc_highspeed      = true,
+        .disable_wp             = true,
+        .bus_width              = 0x4,
+        .u_boot_dm_pre_reloc    = true,
+        .reg                    = {0xff0c0000, 0x4000},
+        .card_detect_delay      = 0xc8,
+};
+U_BOOT_DEVICE(dwmmc_at_ff0c0000) = {
+        .name           = "rockchip_rk3288_dw_mshc",
+        .platdata       = &dtv_dwmmc_at_ff0c0000,
+};
+
+The device is then instantiated at run-time and the platform data can be
+accessed using:
+
+        struct udevice *dev;
+        struct dtd_rockchip_rk3288_dw_mshc *plat = dev_get_platdata(dev);
+
+This avoids the code overhead of converting the device tree data to
+platform data in the driver. The ofdata_to_platdata() method should
+therefore do nothing in such a driver.
+
+
+How to structure your driver
+----------------------------
+
+Drivers should always support device tree as an option. The of-platdata
+feature is intended as a add-on to existing drivers.
+
+Your driver should directly access the platdata struct in its probe()
+method. The existing device tree decoding logic should be kept in the
+ofdata_to_platdata() and wrapped with #ifdef.
+
+For example:
+
+    #include <dt-structs.h>
+
+    struct mmc_platdata {
+    #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
+            /* Put this first */
+            struct dtd_mmc dtplat;
+    #endif
+            /*
+             * Other fields can go here, to be filled in by decoding from
+             * the device tree. They will point to random memory in the
+             * of-plat case.
+             */
+            int fifo_depth;
+    };
+
+    static int mmc_ofdata_to_platdata(struct udevice *dev)
+    {
+    #if !CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
+            struct mmc_platdata *plat = dev_get_platdata(dev);
+            const void *blob = gd->fdt_blob;
+            int node = dev->of_offset;
+
+            plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
+    #endif
+
+            return 0;
+    }
+
+    static int mmc_probe(struct udevice *dev)
+    {
+            struct mmc_platdata *plat = dev_get_platdata(dev);
+    #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
+            struct dtd_mmc *dtplat = &plat->dtplat;
+
+            /* Set up the device from the dtplat data */
+            writel(dtplat->fifo_depth, ...)
+    #else
+            /* Set up the device from the plat data */
+            writel(plat->fifo_depth, ...)
+    #endif
+    }
+
+    static const struct udevice_id mmc_ids[] = {
+            { .compatible = "vendor,mmc" },
+            { }
+    };
+
+    U_BOOT_DRIVER(mmc_drv) = {
+            .name           = "mmc",
+            .id             = UCLASS_MMC,
+            .of_match       = mmc_ids,
+            .ofdata_to_platdata = mmc_ofdata_to_platdata,
+            .probe          = mmc_probe,
+            .priv_auto_alloc_size = sizeof(struct mmc_priv),
+            .platdata_auto_alloc_size = sizeof(struct mmc_platdata),
+    };
+
+
+In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is
+ignored, and the platform data points to the C structure data. In the case
+where device tree is used, the platform data is allocated, and starts
+zeroed. In this case the ofdata_to_platdata() method should set up the
+platform data.
+
+SPL must use either of-platdata or device tree. Drivers cannot use both.
+The device tree becomes in accessible when CONFIG_SPL_OF_PLATDATA is enabled,
+since the device-tree access code is not compiled in.
+
+
+Internals
+---------
+
+The dt-structs.h file includes the generated file
+(include/generated//dt-structs.h) if CONFIG_SPL_OF_PLATDATA is enabled.
+Otherwise (such as in U-Boot proper) these structs are not available. This
+prevents them being used inadvertently.
+
+The dt-platdata.c file contains the device declarations and is is built in
+spl/dt-platdata.c.
+
+Some phandles (thsoe that are recognised as such) are converted into
+points to platform data. This pointer can potentially be used to access the
+referenced device (by searching for the pointer value). This feature is not
+yet implemented, however.
+
+The beginnings of a libfdt Python module are provided. So far this only
+implements a subset of the features.
+
+The 'swig' tool is needed to build the libfdt Python module.
+
+
+Future work
+-----------
+- Add unit tests
+- Add a sandbox_spl functional test
+- Consider programmatically reading binding files instead of device tree
+     contents
+- Drop the device tree data from the SPL image
+- Complete the phandle feature
+- Get this running on a Rockchip board
+- Move to using a full Python libfdt module
+
+--
+Simon Glass <sjg@chromium.org>
+6/6/16
-- 
cgit v0.10.2


From ec564b47dad46e57347cef7b3f7f5bb51a329302 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:08 -0600
Subject: dm: Add a library to provide simple device-tree access

This Python library provides a way to access the contents of the device
tree. It uses fdtget, so is inefficient for larger device tree files.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/dtoc/.gitignore b/tools/dtoc/.gitignore
new file mode 100644
index 0000000..0d20b64
--- /dev/null
+++ b/tools/dtoc/.gitignore
@@ -0,0 +1 @@
+*.pyc
diff --git a/tools/dtoc/fdt_fallback.py b/tools/dtoc/fdt_fallback.py
new file mode 100644
index 0000000..14decf3
--- /dev/null
+++ b/tools/dtoc/fdt_fallback.py
@@ -0,0 +1,207 @@
+#!/usr/bin/python
+#
+# Copyright (C) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+import command
+import fdt_util
+import sys
+
+# This deals with a device tree, presenting it as a list of Node and Prop
+# objects, representing nodes and properties, respectively.
+#
+# This implementation uses the fdtget tool to access the device tree, so it
+# is not very efficient for larger trees. The tool is called once for each
+# node and property in the tree.
+
+class Prop:
+    """A device tree property
+
+    Properties:
+        name: Property name (as per the device tree)
+        value: Property value as a string of bytes, or a list of strings of
+            bytes
+        type: Value type
+    """
+    def __init__(self, name, byte_list_str):
+        self.name = name
+        self.value = None
+        if not byte_list_str.strip():
+            self.type = fdt_util.TYPE_BOOL
+            return
+        bytes = [chr(int(byte, 16)) for byte in byte_list_str.strip().split(' ')]
+        self.type, self.value = fdt_util.BytesToValue(''.join(bytes))
+
+    def GetPhandle(self):
+        """Get a (single) phandle value from a property
+
+        Gets the phandle valuie from a property and returns it as an integer
+        """
+        return fdt_util.fdt32_to_cpu(self.value[:4])
+
+    def Widen(self, newprop):
+        """Figure out which property type is more general
+
+        Given a current property and a new property, this function returns the
+        one that is less specific as to type. The less specific property will
+        be ble to represent the data in the more specific property. This is
+        used for things like:
+
+            node1 {
+                compatible = "fred";
+                value = <1>;
+            };
+            node1 {
+                compatible = "fred";
+                value = <1 2>;
+            };
+
+        He we want to use an int array for 'value'. The first property
+        suggests that a single int is enough, but the second one shows that
+        it is not. Calling this function with these two propertes would
+        update the current property to be like the second, since it is less
+        specific.
+        """
+        if newprop.type < self.type:
+            self.type = newprop.type
+
+        if type(newprop.value) == list and type(self.value) != list:
+            self.value = newprop.value
+
+class Node:
+    """A device tree node
+
+    Properties:
+        name: Device tree node tname
+        path: Full path to node, along with the node name itself
+        _fdt: Device tree object
+        subnodes: A list of subnodes for this node, each a Node object
+        props: A dict of properties for this node, each a Prop object.
+            Keyed by property name
+    """
+    def __init__(self, fdt, name, path):
+        self.name = name
+        self.path = path
+        self._fdt = fdt
+        self.subnodes = []
+        self.props = {}
+
+    def Scan(self):
+        """Scan a node's properties and subnodes
+
+        This fills in the props and subnodes properties, recursively
+        searching into subnodes so that the entire tree is built.
+        """
+        for name, byte_list_str in self._fdt.GetProps(self.path).iteritems():
+            prop = Prop(name, byte_list_str)
+            self.props[name] = prop
+
+        for name in self._fdt.GetSubNodes(self.path):
+            sep = '' if self.path[-1] == '/' else '/'
+            path = self.path + sep + name
+            node = Node(self._fdt, name, path)
+            self.subnodes.append(node)
+
+            node.Scan()
+
+
+class Fdt:
+    """Provides simple access to a flat device tree blob.
+
+    Properties:
+      fname: Filename of fdt
+      _root: Root of device tree (a Node object)
+    """
+
+    def __init__(self, fname):
+        self.fname = fname
+
+    def Scan(self):
+        """Scan a device tree, building up a tree of Node objects
+
+        This fills in the self._root property
+        """
+        self._root = Node(self, '/', '/')
+        self._root.Scan()
+
+    def GetRoot(self):
+        """Get the root Node of the device tree
+
+        Returns:
+            The root Node object
+        """
+        return self._root
+
+    def GetSubNodes(self, node):
+        """Returns a list of sub-nodes of a given node
+
+        Args:
+            node: Node name to return children from
+
+        Returns:
+            List of children in the node (each a string node name)
+
+        Raises:
+            CmdError: if the node does not exist.
+        """
+        out = command.Output('fdtget', self.fname, '-l', node)
+        return out.strip().splitlines()
+
+    def GetProps(self, node, convert_dashes=False):
+        """Get all properties from a node
+
+        Args:
+            node: full path to node name to look in
+            convert_dashes: True to convert - to _ in node names
+
+        Returns:
+            A dictionary containing all the properties, indexed by node name.
+            The entries are simply strings - no decoding of lists or numbers
+            is done.
+
+        Raises:
+            CmdError: if the node does not exist.
+        """
+        out = command.Output('fdtget', self.fname, node, '-p')
+        props = out.strip().splitlines()
+        props_dict = {}
+        for prop in props:
+            name = prop
+            if convert_dashes:
+                prop = re.sub('-', '_', prop)
+            props_dict[prop] = self.GetProp(node, name)
+        return props_dict
+
+    def GetProp(self, node, prop, default=None, typespec=None):
+        """Get a property from a device tree.
+
+        This looks up the given node and property, and returns the value as a
+        string,
+
+        If the node or property does not exist, this will return the default
+        value.
+
+        Args:
+            node: Full path to node to look up.
+            prop: Property name to look up.
+            default: Default value to return if nothing is present in the fdt,
+                or None to raise in this case. This will be converted to a
+                string.
+            typespec: Type character to use (None for default, 's' for string)
+
+        Returns:
+            string containing the property value.
+
+        Raises:
+            CmdError: if the property does not exist and no default is provided.
+        """
+        args = [self.fname, node, prop, '-t', 'bx']
+        if default is not None:
+          args += ['-d', str(default)]
+        if typespec is not None:
+          args += ['-t%s' % typespec]
+        out = command.Output('fdtget', *args)
+        return out.strip()
diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py
new file mode 100644
index 0000000..929b524
--- /dev/null
+++ b/tools/dtoc/fdt_util.py
@@ -0,0 +1,86 @@
+#!/usr/bin/python
+#
+# Copyright (C) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+import struct
+
+# A list of types we support
+(TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL) = range(4)
+
+def BytesToValue(bytes):
+    """Converts a string of bytes into a type and value
+
+    Args:
+        A string containing bytes
+
+    Return:
+        A tuple:
+            Type of data
+            Data, either a single element or a list of elements. Each element
+            is one of:
+                TYPE_STRING: string value from the property
+                TYPE_INT: a byte-swapped integer stored as a 4-byte string
+                TYPE_BYTE: a byte stored as a single-byte string
+    """
+    size = len(bytes)
+    strings = bytes.split('\0')
+    is_string = True
+    count = len(strings) - 1
+    if count > 0 and not strings[-1]:
+        for string in strings[:-1]:
+            if not string:
+                is_string = False
+                break
+            for ch in string:
+                if ch < ' ' or ch > '~':
+                    is_string = False
+                    break
+    else:
+        is_string = False
+    if is_string:
+        if count == 1:
+            return TYPE_STRING, strings[0]
+        else:
+            return TYPE_STRING, strings[:-1]
+    if size % 4:
+        if size == 1:
+            return TYPE_BYTE, bytes[0]
+        else:
+            return TYPE_BYTE, list(bytes)
+    val = []
+    for i in range(0, size, 4):
+        val.append(bytes[i:i + 4])
+    if size == 4:
+        return TYPE_INT, val[0]
+    else:
+        return TYPE_INT, val
+
+def GetEmpty(type):
+    """Get an empty / zero value of the given type
+
+    Returns:
+        A single value of the given type
+    """
+    if type == TYPE_BYTE:
+        return chr(0)
+    elif type == TYPE_INT:
+        return struct.pack('<I', 0);
+    elif type == TYPE_STRING:
+        return ''
+    else:
+        return True
+
+def fdt32_to_cpu(val):
+    """Convert a device tree cell to an integer
+
+    Args:
+        Value to convert (4-character string representing the cell value)
+
+    Return:
+        A native-endian integer value
+    """
+    return struct.unpack(">I", val)[0]
-- 
cgit v0.10.2


From 69f2ed7746c8944b2865c3838c36d97908305586 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:09 -0600
Subject: dm: Add a tool to generate C code from a device tree

This tool can produce C struct definitions and C platform data tables.
This is used to support the of-platdata feature.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/dtoc/dtoc b/tools/dtoc/dtoc
new file mode 120000
index 0000000..896ca44
--- /dev/null
+++ b/tools/dtoc/dtoc
@@ -0,0 +1 @@
+dtoc.py
\ No newline at end of file
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
new file mode 100755
index 0000000..24f3858
--- /dev/null
+++ b/tools/dtoc/dtoc.py
@@ -0,0 +1,391 @@
+#!/usr/bin/python
+#
+# Copyright (C) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+import copy
+from optparse import OptionError, OptionParser
+import os
+import sys
+
+import fdt_util
+
+# Bring in the patman libraries
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '../patman'))
+
+# Bring in either the normal fdt library (which relies on libfdt) or the
+# fallback one (which uses fdtget and is slower). Both provide the same
+# interfface for this file to use.
+try:
+    from fdt import Fdt
+    import fdt
+    have_libfdt = True
+except ImportError:
+    have_libfdt = False
+    from fdt_fallback import Fdt
+    import fdt_fallback as fdt
+
+import struct
+
+# When we see these properties we ignore them - i.e. do not create a structure member
+PROP_IGNORE_LIST = [
+    '#address-cells',
+    '#gpio-cells',
+    '#size-cells',
+    'compatible',
+    'linux,phandle',
+    "status",
+    'phandle',
+]
+
+# C type declarations for the tyues we support
+TYPE_NAMES = {
+    fdt_util.TYPE_INT: 'fdt32_t',
+    fdt_util.TYPE_BYTE: 'unsigned char',
+    fdt_util.TYPE_STRING: 'const char *',
+    fdt_util.TYPE_BOOL: 'bool',
+};
+
+STRUCT_PREFIX = 'dtd_'
+VAL_PREFIX = 'dtv_'
+
+def Conv_name_to_c(name):
+    """Convert a device-tree name to a C identifier
+
+    Args:
+        name:   Name to convert
+    Return:
+        String containing the C version of this name
+    """
+    str = name.replace('@', '_at_')
+    str = str.replace('-', '_')
+    str = str.replace(',', '_')
+    str = str.replace('/', '__')
+    return str
+
+def TabTo(num_tabs, str):
+    if len(str) >= num_tabs * 8:
+        return str + ' '
+    return str + '\t' * (num_tabs - len(str) / 8)
+
+class DtbPlatdata:
+    """Provide a means to convert device tree binary data to platform data
+
+    The output of this process is C structures which can be used in space-
+    constrained encvironments where the ~3KB code overhead of device tree
+    code is not affordable.
+
+    Properties:
+        fdt: Fdt object, referencing the device tree
+        _dtb_fname: Filename of the input device tree binary file
+        _valid_nodes: A list of Node object with compatible strings
+        _options: Command-line options
+        _phandle_node: A dict of nodes indexed by phandle number (1, 2...)
+        _outfile: The current output file (sys.stdout or a real file)
+        _lines: Stashed list of output lines for outputting in the future
+        _phandle_node: A dict of Nodes indexed by phandle (an integer)
+    """
+    def __init__(self, dtb_fname, options):
+        self._dtb_fname = dtb_fname
+        self._valid_nodes = None
+        self._options = options
+        self._phandle_node = {}
+        self._outfile = None
+        self._lines = []
+
+    def SetupOutput(self, fname):
+        """Set up the output destination
+
+        Once this is done, future calls to self.Out() will output to this
+        file.
+
+        Args:
+            fname: Filename to send output to, or '-' for stdout
+        """
+        if fname == '-':
+            self._outfile = sys.stdout
+        else:
+            self._outfile = open(fname, 'w')
+
+    def Out(self, str):
+        """Output a string to the output file
+
+        Args:
+            str: String to output
+        """
+        self._outfile.write(str)
+
+    def Buf(self, str):
+        """Buffer up a string to send later
+
+        Args:
+            str: String to add to our 'buffer' list
+        """
+        self._lines.append(str)
+
+    def GetBuf(self):
+        """Get the contents of the output buffer, and clear it
+
+        Returns:
+            The output buffer, which is then cleared for future use
+        """
+        lines = self._lines
+        self._lines = []
+        return lines
+
+    def GetValue(self, type, value):
+        """Get a value as a C expression
+
+        For integers this returns a byte-swapped (little-endian) hex string
+        For bytes this returns a hex string, e.g. 0x12
+        For strings this returns a literal string enclosed in quotes
+        For booleans this return 'true'
+
+        Args:
+            type: Data type (fdt_util)
+            value: Data value, as a string of bytes
+        """
+        if type == fdt_util.TYPE_INT:
+            return '%#x' % fdt_util.fdt32_to_cpu(value)
+        elif type == fdt_util.TYPE_BYTE:
+            return '%#x' % ord(value[0])
+        elif type == fdt_util.TYPE_STRING:
+            return '"%s"' % value
+        elif type == fdt_util.TYPE_BOOL:
+            return 'true'
+
+    def GetCompatName(self, node):
+        """Get a node's first compatible string as a C identifier
+
+        Args:
+            node: Node object to check
+        Return:
+            C identifier for the first compatible string
+        """
+        compat = node.props['compatible'].value
+        if type(compat) == list:
+            compat = compat[0]
+        return Conv_name_to_c(compat)
+
+    def ScanDtb(self):
+        """Scan the device tree to obtain a tree of notes and properties
+
+        Once this is done, self.fdt.GetRoot() can be called to obtain the
+        device tree root node, and progress from there.
+        """
+        self.fdt = Fdt(self._dtb_fname)
+        self.fdt.Scan()
+
+    def ScanTree(self):
+        """Scan the device tree for useful information
+
+        This fills in the following properties:
+            _phandle_node: A dict of Nodes indexed by phandle (an integer)
+            _valid_nodes: A list of nodes we wish to consider include in the
+                platform data
+        """
+        node_list = []
+        self._phandle_node = {}
+        for node in self.fdt.GetRoot().subnodes:
+            if 'compatible' in node.props:
+                status = node.props.get('status')
+                if (not options.include_disabled and not status or
+                    status.value != 'disabled'):
+                    node_list.append(node)
+                    phandle_prop = node.props.get('phandle')
+                    if phandle_prop:
+                        phandle = phandle_prop.GetPhandle()
+                        self._phandle_node[phandle] = node
+
+        self._valid_nodes = node_list
+
+    def IsPhandle(self, prop):
+        """Check if a node contains phandles
+
+        We have no reliable way of detecting whether a node uses a phandle
+        or not. As an interim measure, use a list of known property names.
+
+        Args:
+            prop: Prop object to check
+        Return:
+            True if the object value contains phandles, else False
+        """
+        if prop.name in ['clocks']:
+            return True
+        return False
+
+    def ScanStructs(self):
+        """Scan the device tree building up the C structures we will use.
+
+        Build a dict keyed by C struct name containing a dict of Prop
+        object for each struct field (keyed by property name). Where the
+        same struct appears multiple times, try to use the 'widest'
+        property, i.e. the one with a type which can express all others.
+
+        Once the widest property is determined, all other properties are
+        updated to match that width.
+        """
+        structs = {}
+        for node in self._valid_nodes:
+            node_name = self.GetCompatName(node)
+            fields = {}
+
+            # Get a list of all the valid properties in this node.
+            for name, prop in node.props.iteritems():
+                if name not in PROP_IGNORE_LIST and name[0] != '#':
+                    fields[name] = copy.deepcopy(prop)
+
+            # If we've seen this node_name before, update the existing struct.
+            if node_name in structs:
+                struct = structs[node_name]
+                for name, prop in fields.iteritems():
+                    oldprop = struct.get(name)
+                    if oldprop:
+                        oldprop.Widen(prop)
+                    else:
+                        struct[name] = prop
+
+            # Otherwise store this as a new struct.
+            else:
+                structs[node_name] = fields
+
+        upto = 0
+        for node in self._valid_nodes:
+            node_name = self.GetCompatName(node)
+            struct = structs[node_name]
+            for name, prop in node.props.iteritems():
+                if name not in PROP_IGNORE_LIST and name[0] != '#':
+                    prop.Widen(struct[name])
+            upto += 1
+        return structs
+
+    def GenerateStructs(self, structs):
+        """Generate struct defintions for the platform data
+
+        This writes out the body of a header file consisting of structure
+        definitions for node in self._valid_nodes. See the documentation in
+        README.of-plat for more information.
+        """
+        self.Out('#include <stdbool.h>\n')
+        self.Out('#include <libfdt.h>\n')
+
+        # Output the struct definition
+        for name in sorted(structs):
+            self.Out('struct %s%s {\n' % (STRUCT_PREFIX, name));
+            for pname in sorted(structs[name]):
+                prop = structs[name][pname]
+                if self.IsPhandle(prop):
+                    # For phandles, include a reference to the target
+                    self.Out('\t%s%s[%d]' % (TabTo(2, 'struct phandle_2_cell'),
+                                             Conv_name_to_c(prop.name),
+                                             len(prop.value) / 2))
+                else:
+                    ptype = TYPE_NAMES[prop.type]
+                    self.Out('\t%s%s' % (TabTo(2, ptype),
+                                         Conv_name_to_c(prop.name)))
+                    if type(prop.value) == list:
+                        self.Out('[%d]' % len(prop.value))
+                self.Out(';\n')
+            self.Out('};\n')
+
+    def GenerateTables(self):
+        """Generate device defintions for the platform data
+
+        This writes out C platform data initialisation data and
+        U_BOOT_DEVICE() declarations for each valid node. See the
+        documentation in README.of-plat for more information.
+        """
+        self.Out('#include <common.h>\n')
+        self.Out('#include <dm.h>\n')
+        self.Out('#include <dt-structs.h>\n')
+        self.Out('\n')
+        node_txt_list = []
+        for node in self._valid_nodes:
+            struct_name = self.GetCompatName(node)
+            var_name = Conv_name_to_c(node.name)
+            self.Buf('static struct %s%s %s%s = {\n' %
+                (STRUCT_PREFIX, struct_name, VAL_PREFIX, var_name))
+            for pname, prop in node.props.iteritems():
+                if pname in PROP_IGNORE_LIST or pname[0] == '#':
+                    continue
+                ptype = TYPE_NAMES[prop.type]
+                member_name = Conv_name_to_c(prop.name)
+                self.Buf('\t%s= ' % TabTo(3, '.' + member_name))
+
+                # Special handling for lists
+                if type(prop.value) == list:
+                    self.Buf('{')
+                    vals = []
+                    # For phandles, output a reference to the platform data
+                    # of the target node.
+                    if self.IsPhandle(prop):
+                        # Process the list as pairs of (phandle, id)
+                        it = iter(prop.value)
+                        for phandle_cell, id_cell in zip(it, it):
+                            phandle = fdt_util.fdt32_to_cpu(phandle_cell)
+                            id = fdt_util.fdt32_to_cpu(id_cell)
+                            target_node = self._phandle_node[phandle]
+                            name = Conv_name_to_c(target_node.name)
+                            vals.append('{&%s%s, %d}' % (VAL_PREFIX, name, id))
+                    else:
+                        for val in prop.value:
+                            vals.append(self.GetValue(prop.type, val))
+                    self.Buf(', '.join(vals))
+                    self.Buf('}')
+                else:
+                    self.Buf(self.GetValue(prop.type, prop.value))
+                self.Buf(',\n')
+            self.Buf('};\n')
+
+            # Add a device declaration
+            self.Buf('U_BOOT_DEVICE(%s) = {\n' % var_name)
+            self.Buf('\t.name\t\t= "%s",\n' % struct_name)
+            self.Buf('\t.platdata\t= &%s%s,\n' % (VAL_PREFIX, var_name))
+            self.Buf('};\n')
+            self.Buf('\n')
+
+            # Output phandle target nodes first, since they may be referenced
+            # by others
+            if 'phandle' in node.props:
+                self.Out(''.join(self.GetBuf()))
+            else:
+                node_txt_list.append(self.GetBuf())
+
+        # Output all the nodes which are not phandle targets themselves, but
+        # may reference them. This avoids the need for forward declarations.
+        for node_txt in node_txt_list:
+            self.Out(''.join(node_txt))
+
+
+if __name__ != "__main__":
+    pass
+
+parser = OptionParser()
+parser.add_option('-d', '--dtb-file', action='store',
+                  help='Specify the .dtb input file')
+parser.add_option('--include-disabled', action='store_true',
+                  help='Include disabled nodes')
+parser.add_option('-o', '--output', action='store', default='-',
+                  help='Select output filename')
+(options, args) = parser.parse_args()
+
+if not args:
+    raise ValueError('Please specify a command: struct, platdata')
+
+plat = DtbPlatdata(options.dtb_file, options)
+plat.ScanDtb()
+plat.ScanTree()
+plat.SetupOutput(options.output)
+structs = plat.ScanStructs()
+
+for cmd in args[0].split(','):
+    if cmd == 'struct':
+        plat.GenerateStructs(structs)
+    elif cmd == 'platdata':
+        plat.GenerateTables()
+    else:
+        raise ValueError("Unknown command '%s': (use: struct, platdata)" % cmd)
-- 
cgit v0.10.2


From dbbe2e6401fc8539f456cab7ef1dd38f9495591d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:10 -0600
Subject: dm: Makefile: Build of-platdata files when the feature is enabled

Update the Makefile to call dtoc to create the C header and source files,
then build these into the image.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 2b5c995..324b03f 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -45,6 +45,7 @@ LDFLAGS_FINAL += --gc-sections
 # FIX ME
 cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
 							$(NOSTDINC_FLAGS)
+c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
 
 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
 
@@ -76,6 +77,9 @@ endif
 
 u-boot-spl-init := $(head-y)
 u-boot-spl-main := $(libs-y)
+ifdef CONFIG_SPL_OF_PLATDATA
+u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
+endif
 
 # Linker Script
 ifdef CONFIG_SPL_LDSCRIPT
@@ -207,6 +211,32 @@ cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 $(obj)/$(SPL_BIN).cfg:	include/config.h FORCE
 	$(call if_changed,cpp_cfg)
 
+pythonpath = PYTHONPATH=tools
+
+quiet_cmd_dtocc = DTOC C  $@
+cmd_dtocc = $(pythonpath) $(srctree)/tools/dtoc/dtoc -d $(obj)/$(SPL_BIN).dtb -o $@ platdata
+
+quiet_cmd_dtoch = DTOC H  $@
+cmd_dtoch = $(pythonpath) $(srctree)/tools/dtoc/dtoc -d $(obj)/$(SPL_BIN).dtb -o $@ struct
+
+quiet_cmd_plat = PLAT    $@
+cmd_plat = $(CC) $(c_flags) -c $< -o $@
+
+$(obj)/dts/dt-platdata.o: $(obj)/dts/dt-platdata.c include/generated/dt-structs.h
+	$(call if_changed,plat)
+
+PHONY += dts_dir
+dts_dir:
+	$(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts)
+
+include/generated/dt-structs.h: $(obj)/$(SPL_BIN).dtb dts_dir dtoc
+	$(call if_changed,dtoch)
+
+$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir dtoc
+	$(call if_changed,dtocc)
+
+dtoc: #$(objtree)/tools/_libfdt.so
+
 ifdef CONFIG_SAMSUNG
 ifdef CONFIG_VAR_SIZE_SPL
 VAR_SIZE_PARAM = --vs
@@ -246,16 +276,19 @@ $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
 quiet_cmd_u-boot-spl ?= LD      $@
       cmd_u-boot-spl ?= (cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
 		       $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
-		       $(patsubst $(obj)/%,%,$(u-boot-spl-main)) --end-group \
+		       $(patsubst $(obj)/%,%,$(u-boot-spl-main))  \
+		       $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
+		       --end-group \
 		       $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN))
 
-$(obj)/$(SPL_BIN): $(u-boot-spl-init) $(u-boot-spl-main) $(obj)/u-boot-spl.lds FORCE
+$(obj)/$(SPL_BIN): $(u-boot-spl-platdata) $(u-boot-spl-init) \
+		$(u-boot-spl-main) $(obj)/u-boot-spl.lds FORCE
 	$(call if_changed,u-boot-spl)
 
 $(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ;
 
 PHONY += $(u-boot-spl-dirs)
-$(u-boot-spl-dirs):
+$(u-boot-spl-dirs): $(u-boot-spl-platdata)
 	$(Q)$(MAKE) $(build)=$@
 
 quiet_cmd_cpp_lds = LDS     $@
-- 
cgit v0.10.2


From 76bce10d2131938fcd5b1bbb0479cdb66daffa29 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:11 -0600
Subject: dm: Add a more efficient libfdt library

Add a Python version of the libfdt library which contains enough features to
support the dtoc tool. This is only a very bare-bones implementation. It
requires the 'swig' to build.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/lib/libfdt/libfdt.swig b/lib/libfdt/libfdt.swig
new file mode 100644
index 0000000..14f583d
--- /dev/null
+++ b/lib/libfdt/libfdt.swig
@@ -0,0 +1,89 @@
+/* File: libfdt.i */
+%module libfdt
+
+%{
+#define SWIG_FILE_WITH_INIT
+#include "libfdt.h"
+%}
+
+%pythoncode %{
+def Raise(errnum):
+    raise ValueError('Error %s' % fdt_strerror(errnum))
+
+def Name(fdt, offset):
+    name, len = fdt_get_name(fdt, offset)
+    return name
+
+def String(fdt, offset):
+    offset = fdt32_to_cpu(offset)
+    name = fdt_string(fdt, offset)
+    return name
+
+def swap32(x):
+    return (((x << 24) & 0xFF000000) |
+            ((x <<  8) & 0x00FF0000) |
+            ((x >>  8) & 0x0000FF00) |
+            ((x >> 24) & 0x000000FF))
+
+def fdt32_to_cpu(x):
+    return swap32(x)
+
+def Data(prop):
+    set_prop(prop)
+    return get_prop_data()
+%}
+
+%include "typemaps.i"
+%include "cstring.i"
+
+%typemap(in) void* = char*;
+
+typedef int fdt32_t;
+
+struct fdt_property {
+        fdt32_t tag;
+        fdt32_t len;
+        fdt32_t nameoff;
+        char data[0];
+};
+
+/*
+ * This is a work-around since I'm not sure of a better way to copy out the
+ * contents of a string. This is used in dtoc/GetProps(). The intent is to
+ * pass in a pointer to a property and access the data field at the end of
+ * it. Ideally the Data() function above would be able to do this directly,
+ * but I'm not sure how to do that.
+ */
+#pragma SWIG nowarn=454
+%inline %{
+    static struct fdt_property *cur_prop;
+
+    void set_prop(struct fdt_property *prop) {
+        cur_prop = prop;
+    }
+%}
+
+%cstring_output_allocate_size(char **s, int *sz, free(*$1));
+%inline %{
+    void get_prop_data(char **s, int *sz) {
+        *sz = fdt32_to_cpu(cur_prop->len);
+        *s = (char *)malloc(*sz);
+        if (!*s)
+            *sz = 0;
+        else
+            memcpy(*s, cur_prop + 1, *sz);
+    }
+%}
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
+int fdt_path_offset(const void *fdt, const char *path);
+int fdt_first_property_offset(const void *fdt, int nodeoffset);
+int fdt_next_property_offset(const void *fdt, int offset);
+const char *fdt_strerror(int errval);
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+                                                      int offset,
+                                                      int *OUTPUT);
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *OUTPUT);
+const char *fdt_string(const void *fdt, int stroffset);
+int fdt_first_subnode(const void *fdt, int offset);
+int fdt_next_subnode(const void *fdt, int offset);
diff --git a/lib/libfdt/setup.py b/lib/libfdt/setup.py
new file mode 100644
index 0000000..62e7bcc
--- /dev/null
+++ b/lib/libfdt/setup.py
@@ -0,0 +1,38 @@
+#!/usr/bin/env python
+
+"""
+setup.py file for SWIG libfdt
+"""
+
+from distutils.core import setup, Extension
+import os
+import sys
+
+# Don't cross-compile - always use the host compiler.
+del os.environ['CROSS_COMPILE']
+del os.environ['CC']
+
+progname = sys.argv[0]
+cflags = sys.argv[1]
+files = sys.argv[2:]
+
+if cflags:
+    cflags = [flag for flag in cflags.split(' ') if flag]
+else:
+    cflags = None
+
+libfdt_module = Extension(
+    '_libfdt',
+    sources = files,
+    extra_compile_args =  cflags
+)
+
+sys.argv = [progname, '--quiet', 'build_ext', '--inplace']
+
+setup (name = 'libfdt',
+       version = '0.1',
+       author      = "SWIG Docs",
+       description = """Simple swig libfdt from docs""",
+       ext_modules = [libfdt_module],
+       py_modules = ["libfdt"],
+       )
diff --git a/lib/libfdt/test_libfdt.py b/lib/libfdt/test_libfdt.py
new file mode 100644
index 0000000..14d0da4
--- /dev/null
+++ b/lib/libfdt/test_libfdt.py
@@ -0,0 +1,14 @@
+#!/usr/bin/python
+
+import os
+import sys
+
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '../../b/sandbox_spl/tools'))
+
+import libfdt
+
+with open('b/sandbox_spl/u-boot.dtb') as fd:
+    fdt = fd.read()
+
+print libfdt.fdt_path_offset(fdt, "/aliases")
diff --git a/scripts/Makefile.host b/scripts/Makefile.host
index bff8b5b..763a699 100644
--- a/scripts/Makefile.host
+++ b/scripts/Makefile.host
@@ -28,12 +28,16 @@ __hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
 # C code
 # Executables compiled from a single .c file
 host-csingle	:= $(foreach m,$(__hostprogs), \
-			$(if $($(m)-objs)$($(m)-cxxobjs),,$(m)))
+			$(if $($(m)-objs)$($(m)-cxxobjs)$($(m)-sharedobjs),,$(m)))
 
 # C executables linked based on several .o files
 host-cmulti	:= $(foreach m,$(__hostprogs),\
 		   $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m))))
 
+# Shared object libraries
+host-shared	:= $(foreach m,$(__hostprogs),\
+		   $(if $($(m)-sharedobjs),$(m))))
+
 # Object (.o) files compiled from .c files
 host-cobjs	:= $(sort $(foreach m,$(__hostprogs),$($(m)-objs)))
 
@@ -59,6 +63,7 @@ host-cmulti	:= $(addprefix $(obj)/,$(host-cmulti))
 host-cobjs	:= $(addprefix $(obj)/,$(host-cobjs))
 host-cxxmulti	:= $(addprefix $(obj)/,$(host-cxxmulti))
 host-cxxobjs	:= $(addprefix $(obj)/,$(host-cxxobjs))
+host-shared	:= $(addprefix $(obj)/,$(host-shared))
 host-objdirs    := $(addprefix $(obj)/,$(host-objdirs))
 
 obj-dirs += $(host-objdirs)
@@ -128,4 +133,4 @@ $(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE
 	$(call if_changed_dep,host-cxxobjs)
 
 targets += $(host-csingle)  $(host-cmulti) $(host-cobjs)\
-	   $(host-cxxmulti) $(host-cxxobjs)
+	   $(host-cxxmulti) $(host-cxxobjs) $(host-shared)
diff --git a/tools/Makefile b/tools/Makefile
index f72294a..2731b7a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -107,6 +107,17 @@ mkimage-objs   := $(dumpimage-mkimage-objs) mkimage.o
 fit_info-objs   := $(dumpimage-mkimage-objs) fit_info.o
 fit_check_sign-objs   := $(dumpimage-mkimage-objs) fit_check_sign.o
 
+hostprogs-$(CONFIG_SPL_OF_PLATDATA) += _libfdt.so
+_libfdt.so-sharedobjs += $(LIBFDT_OBJS)
+libfdt:
+
+tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c
+	python $(srctree)/lib/libfdt/setup.py "$(_hostc_flags)" $^
+	mv _libfdt.so $@
+
+tools/libfdt_wrap.c: $(srctree)/lib/libfdt/libfdt.swig
+	swig -python -o $@ $<
+
 # TODO(sjg@chromium.org): Is this correct on Mac OS?
 
 ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py
new file mode 100644
index 0000000..1d913a9
--- /dev/null
+++ b/tools/dtoc/fdt.py
@@ -0,0 +1,180 @@
+#!/usr/bin/python
+#
+# Copyright (C) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+import fdt_util
+import libfdt
+import sys
+
+# This deals with a device tree, presenting it as a list of Node and Prop
+# objects, representing nodes and properties, respectively.
+#
+# This implementation uses a libfdt Python library to access the device tree,
+# so it is fairly efficient.
+
+class Prop:
+    """A device tree property
+
+    Properties:
+        name: Property name (as per the device tree)
+        value: Property value as a string of bytes, or a list of strings of
+            bytes
+        type: Value type
+    """
+    def __init__(self, name, bytes):
+        self.name = name
+        self.value = None
+        if not bytes:
+            self.type = fdt_util.TYPE_BOOL
+            self.value = True
+            return
+        self.type, self.value = fdt_util.BytesToValue(bytes)
+
+    def GetPhandle(self):
+        """Get a (single) phandle value from a property
+
+        Gets the phandle valuie from a property and returns it as an integer
+        """
+        return fdt_util.fdt32_to_cpu(self.value[:4])
+
+    def Widen(self, newprop):
+        """Figure out which property type is more general
+
+        Given a current property and a new property, this function returns the
+        one that is less specific as to type. The less specific property will
+        be ble to represent the data in the more specific property. This is
+        used for things like:
+
+            node1 {
+                compatible = "fred";
+                value = <1>;
+            };
+            node1 {
+                compatible = "fred";
+                value = <1 2>;
+            };
+
+        He we want to use an int array for 'value'. The first property
+        suggests that a single int is enough, but the second one shows that
+        it is not. Calling this function with these two propertes would
+        update the current property to be like the second, since it is less
+        specific.
+        """
+        if newprop.type < self.type:
+            self.type = newprop.type
+
+        if type(newprop.value) == list and type(self.value) != list:
+            self.value = [self.value]
+
+        if type(self.value) == list and len(newprop.value) > len(self.value):
+            val = fdt_util.GetEmpty(self.type)
+            while len(self.value) < len(newprop.value):
+                self.value.append(val)
+
+
+class Node:
+    """A device tree node
+
+    Properties:
+        offset: Integer offset in the device tree
+        name: Device tree node tname
+        path: Full path to node, along with the node name itself
+        _fdt: Device tree object
+        subnodes: A list of subnodes for this node, each a Node object
+        props: A dict of properties for this node, each a Prop object.
+            Keyed by property name
+    """
+    def __init__(self, fdt, offset, name, path):
+        self.offset = offset
+        self.name = name
+        self.path = path
+        self._fdt = fdt
+        self.subnodes = []
+        self.props = {}
+
+    def Scan(self):
+        """Scan a node's properties and subnodes
+
+        This fills in the props and subnodes properties, recursively
+        searching into subnodes so that the entire tree is built.
+        """
+        self.props = self._fdt.GetProps(self.path)
+
+        offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.offset)
+        while offset >= 0:
+            sep = '' if self.path[-1] == '/' else '/'
+            name = libfdt.Name(self._fdt.GetFdt(), offset)
+            path = self.path + sep + name
+            node = Node(self._fdt, offset, name, path)
+            self.subnodes.append(node)
+
+            node.Scan()
+            offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset)
+
+
+class Fdt:
+    """Provides simple access to a flat device tree blob.
+
+    Properties:
+      fname: Filename of fdt
+      _root: Root of device tree (a Node object)
+    """
+
+    def __init__(self, fname):
+        self.fname = fname
+        with open(fname) as fd:
+            self._fdt = fd.read()
+
+    def GetFdt(self):
+        """Get the contents of the FDT
+
+        Returns:
+            The FDT contents as a string of bytes
+        """
+        return self._fdt
+
+    def Scan(self):
+        """Scan a device tree, building up a tree of Node objects
+
+        This fills in the self._root property
+        """
+        self._root = Node(self, 0, '/', '/')
+        self._root.Scan()
+
+    def GetRoot(self):
+        """Get the root Node of the device tree
+
+        Returns:
+            The root Node object
+        """
+        return self._root
+
+    def GetProps(self, node):
+        """Get all properties from a node.
+
+        Args:
+            node: Full path to node name to look in.
+
+        Returns:
+            A dictionary containing all the properties, indexed by node name.
+            The entries are Prop objects.
+
+        Raises:
+            ValueError: if the node does not exist.
+        """
+        offset = libfdt.fdt_path_offset(self._fdt, node)
+        if offset < 0:
+            libfdt.Raise(offset)
+        props_dict = {}
+        poffset = libfdt.fdt_first_property_offset(self._fdt, offset)
+        while poffset >= 0:
+            dprop, plen = libfdt.fdt_get_property_by_offset(self._fdt, poffset)
+            prop = Prop(libfdt.String(self._fdt, dprop.nameoff), libfdt.Data(dprop))
+            props_dict[prop.name] = prop
+
+            poffset = libfdt.fdt_next_property_offset(self._fdt, poffset)
+        return props_dict
-- 
cgit v0.10.2


From 162a7a421718a2d15716a78ffb7abb1d94f6b03a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:12 -0600
Subject: Only build the libfdt python module if 'swig' is available

When swig is not available, we can still build correctly. So make this
optional. Add a comment about how to enable this build.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/Makefile b/tools/Makefile
index 2731b7a..421414b 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -107,7 +107,10 @@ mkimage-objs   := $(dumpimage-mkimage-objs) mkimage.o
 fit_info-objs   := $(dumpimage-mkimage-objs) fit_info.o
 fit_check_sign-objs   := $(dumpimage-mkimage-objs) fit_check_sign.o
 
-hostprogs-$(CONFIG_SPL_OF_PLATDATA) += _libfdt.so
+# Build a libfdt Python module if swig is available
+# Use 'sudo apt-get install swig libpython-dev' to enable this
+hostprogs-$(CONFIG_SPL_OF_PLATDATA) += \
+	$(if $(shell which swig),_libfdt.so)
 _libfdt.so-sharedobjs += $(LIBFDT_OBJS)
 libfdt:
 
-- 
cgit v0.10.2


From e24091398d50961ece2fcb2924d7c37d329abc09 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:13 -0600
Subject: tiny-printf: Support assert()

At present assert() is not supported with tiny-printf, so when DEBUG is
enabled a build error is generated for each assert().

Add an __assert_fail() function to correct this. It prints a message and
then hangs.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index b334f05..1aa43ab 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -185,3 +185,12 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
 
 	return ret;
 }
+
+void __assert_fail(const char *assertion, const char *file, unsigned line,
+		   const char *function)
+{
+	/* This will not return */
+	printf("%s:%u: %s: Assertion `%s' failed.", file, line, function,
+	       assertion);
+	hang();
+}
-- 
cgit v0.10.2


From 7d23b9cf2b1a5a86f7e89a443e3a2de9dac8a9ad Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:14 -0600
Subject: dm: spl: Bind in all devices in SPL with of-platdata

When CONFIG_OF_PLATDATA is enabled, we cannot use the u-boot,dm-pre-reloc
device tree property since the device tree is not available. However,
dt-platdata.c only includes devices which would have been present in the
device tree, and we can assume that all such devices are needed for SPL.
If they were not needed, they would have been omitted to save space.

So in this case, bind all devices regardless of the u-boot,dm-pre-reloc
setting. This avoids needing to add a DM_FLAG_PRE_RELOC to every driver,
thus affecting U-Boot proper also.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 59f41a1..12aed02 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -210,7 +210,8 @@ int spl_init(void)
 		}
 	}
 	if (IS_ENABLED(CONFIG_SPL_DM)) {
-		ret = dm_init_and_scan(true);
+		/* With CONFIG_OF_PLATDATA, bring in all devices */
+		ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
 		if (ret) {
 			debug("dm_init_and_scan() returned error %d\n", ret);
 			return ret;
-- 
cgit v0.10.2


From fd1c2d9b6a3a9b41ae070ca47361bd6cc6aaaf09 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:15 -0600
Subject: dm: core: Rename DM_NAME_ALLOCED to DM_FLAG_NAME_ALLOCED

This is a flag. Adjust the name to be consistent with the other flags.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 0e56b23..a7f77b4 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -112,7 +112,7 @@ int device_unbind(struct udevice *dev)
 
 	devres_release_all(dev);
 
-	if (dev->flags & DM_NAME_ALLOCED)
+	if (dev->flags & DM_FLAG_NAME_ALLOCED)
 		free((char *)dev->name);
 	free(dev);
 
diff --git a/drivers/core/device.c b/drivers/core/device.c
index d8f9d5b..6967c3d 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -738,7 +738,7 @@ bool device_is_last_sibling(struct udevice *dev)
 
 void device_set_name_alloced(struct udevice *dev)
 {
-	dev->flags |= DM_NAME_ALLOCED;
+	dev->flags |= DM_FLAG_NAME_ALLOCED;
 }
 
 int device_set_name(struct udevice *dev, const char *name)
diff --git a/include/dm/device.h b/include/dm/device.h
index 1bfcf3b..fc35f4d 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -42,7 +42,7 @@ struct driver_info;
 #define DM_FLAG_BOUND			(1 << 6)
 
 /* Device name is allocated and should be freed on unbind() */
-#define DM_NAME_ALLOCED			(1 << 7)
+#define DM_FLAG_NAME_ALLOCED		(1 << 7)
 
 /**
  * struct udevice - An instance of a driver
@@ -553,7 +553,7 @@ int device_set_name(struct udevice *dev, const char *name);
 /**
  * device_set_name_alloced() - note that a device name is allocated
  *
- * This sets the DM_NAME_ALLOCED flag for the device, so that when it is
+ * This sets the DM_FLAG_NAME_ALLOCED flag for the device, so that when it is
  * unbound the name will be freed. This avoids memory leaks.
  *
  * @dev:	Device to update
-- 
cgit v0.10.2


From efefe1221bd779f319b810c5415e577c331edec8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:16 -0600
Subject: dtoc: Ignore the u-boot, dm-pre-reloc property

This property is not useful for of-platdata, so omit it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
index 24f3858..374ad1c 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/dtoc.py
@@ -40,6 +40,7 @@ PROP_IGNORE_LIST = [
     'linux,phandle',
     "status",
     'phandle',
+    'u-boot,dm-pre-reloc',
 ]
 
 # C type declarations for the tyues we support
-- 
cgit v0.10.2


From d22199b166e7064ad68cba52be390b88f2de79c9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:17 -0600
Subject: dm: Don't attach the device tree to SPL with of-platdata

When of-platdata is used in SPL we don't use the device tree. So there is no
point in attaching it. Adjust the Makefile to skip attaching the device tree
when of-platdata is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 324b03f..3ba9742 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -173,7 +173,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 quiet_cmd_copy = COPY    $@
       cmd_copy = cp $< $@
 
-ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE),yy)
+ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy)
 $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \
 		$(obj)/$(SPL_BIN).dtb FORCE
 	$(call if_changed,cat)
-- 
cgit v0.10.2


From 9fa28190091e59b7c9b9ba32e5a81fa432c485b6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:18 -0600
Subject: dm: core: Expand platdata for of-platdata devices

Devices which use of-platdata have their own platdata. However, in many
cases the driver will have its own auto-alloced platdata, for use with the
device tree. The ofdata_to_platdata() method converts the device tree
settings to platdata.

With of-platdata we would not normally allocate the platdata since it is
provided by the U_BOOT_DEVICE() declaration. However this is inconvenient
since the of-platdata struct is closely tied to the device tree properties.
It is unlikely to exactly match the platdata needed by the driver.

In fact a useful approach is to declare platdata in the driver like this:

struct r3288_mmc_platdata {
	struct dtd_rockchip_rk3288_dw_mshc of_platdata;
	/* the 'normal' fields go here */
};

In this case we have dt_platadata available, but the normal fields are not
present, since ofdata_to_platdata() is never called. In fact driver model
doesn't allocate any space for the 'normal' fields, since it sees that there
is already platform data attached to the device.

To make this easier, adjust driver model to allocate the full size of the
struct (i.e. platdata_auto_alloc_size from the driver) and copy in the
of-platdata. This means that when the driver's bind() method is called,
the of-platdata will be present, followed by zero bytes for the empty
'normal field' portion.

A new DM_FLAG_OF_PLATDATA flag is available that indicates that the platdata
came from of-platdata. When the allocation/copy happens, the
DM_FLAG_ALLOC_PDATA flag will be set as well. The dtoc tool is updated to
output the platdata_size field, since U-Boot has no other way of knowing
the size of the of-platdata struct.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6967c3d..5bb1d77 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static int device_bind_common(struct udevice *parent, const struct driver *drv,
 			      const char *name, void *platdata,
 			      ulong driver_data, int of_offset,
-			      struct udevice **devp)
+			      uint of_platdata_size, struct udevice **devp)
 {
 	struct udevice *dev;
 	struct uclass *uc;
@@ -84,12 +84,29 @@ static int device_bind_common(struct udevice *parent, const struct driver *drv,
 		}
 	}
 
-	if (!dev->platdata && drv->platdata_auto_alloc_size) {
-		dev->flags |= DM_FLAG_ALLOC_PDATA;
-		dev->platdata = calloc(1, drv->platdata_auto_alloc_size);
-		if (!dev->platdata) {
-			ret = -ENOMEM;
-			goto fail_alloc1;
+	if (drv->platdata_auto_alloc_size) {
+		bool alloc = !platdata;
+
+		if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+			if (of_platdata_size) {
+				dev->flags |= DM_FLAG_OF_PLATDATA;
+				if (of_platdata_size <
+						drv->platdata_auto_alloc_size)
+					alloc = true;
+			}
+		}
+		if (alloc) {
+			dev->flags |= DM_FLAG_ALLOC_PDATA;
+			dev->platdata = calloc(1,
+					       drv->platdata_auto_alloc_size);
+			if (!dev->platdata) {
+				ret = -ENOMEM;
+				goto fail_alloc1;
+			}
+			if (CONFIG_IS_ENABLED(OF_PLATDATA) && platdata) {
+				memcpy(dev->platdata, platdata,
+				       of_platdata_size);
+			}
 		}
 	}
 
@@ -202,14 +219,14 @@ int device_bind_with_driver_data(struct udevice *parent,
 				 struct udevice **devp)
 {
 	return device_bind_common(parent, drv, name, NULL, driver_data,
-				  of_offset, devp);
+				  of_offset, 0, devp);
 }
 
 int device_bind(struct udevice *parent, const struct driver *drv,
 		const char *name, void *platdata, int of_offset,
 		struct udevice **devp)
 {
-	return device_bind_common(parent, drv, name, platdata, 0, of_offset,
+	return device_bind_common(parent, drv, name, platdata, 0, of_offset, 0,
 				  devp);
 }
 
@@ -217,6 +234,7 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
 			const struct driver_info *info, struct udevice **devp)
 {
 	struct driver *drv;
+	uint platdata_size = 0;
 
 	drv = lists_driver_lookup_name(info->name);
 	if (!drv)
@@ -224,8 +242,11 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
 	if (pre_reloc_only && !(drv->flags & DM_FLAG_PRE_RELOC))
 		return -EPERM;
 
-	return device_bind(parent, drv, info->name, (void *)info->platdata,
-			   -1, devp);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	platdata_size = info->platdata_size;
+#endif
+	return device_bind_common(parent, drv, info->name,
+			(void *)info->platdata, 0, -1, platdata_size, devp);
 }
 
 static void *alloc_priv(int size, uint flags)
diff --git a/include/dm/device.h b/include/dm/device.h
index fc35f4d..c825d47 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -44,6 +44,8 @@ struct driver_info;
 /* Device name is allocated and should be freed on unbind() */
 #define DM_FLAG_NAME_ALLOCED		(1 << 7)
 
+#define DM_FLAG_OF_PLATDATA		(1 << 8)
+
 /**
  * struct udevice - An instance of a driver
  *
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
index 6f4f001..488b2ab 100644
--- a/include/dm/platdata.h
+++ b/include/dm/platdata.h
@@ -22,10 +22,15 @@
  *
  * @name:	Driver name
  * @platdata:	Driver-specific platform data
+ * @platdata_size: Size of platform data structure
+ * @flags:	Platform data flags (DM_FLAG_...)
  */
 struct driver_info {
 	const char *name;
 	const void *platdata;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	uint platdata_size;
+#endif
 };
 
 /**
diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py
index 374ad1c..ec80abe 100755
--- a/tools/dtoc/dtoc.py
+++ b/tools/dtoc/dtoc.py
@@ -346,6 +346,8 @@ class DtbPlatdata:
             self.Buf('U_BOOT_DEVICE(%s) = {\n' % var_name)
             self.Buf('\t.name\t\t= "%s",\n' % struct_name)
             self.Buf('\t.platdata\t= &%s%s,\n' % (VAL_PREFIX, var_name))
+            self.Buf('\t.platdata_size\t= sizeof(%s%s),\n' %
+                     (VAL_PREFIX, var_name))
             self.Buf('};\n')
             self.Buf('\n')
 
-- 
cgit v0.10.2


From 2c9dfb5807bfbf97b60481586d5db3c677cba65b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:19 -0600
Subject: sandbox: Don't bring in the eeprom emulator in SPL

This driver should not be used in SPL since we do not have I2C support
enabled in SPL on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3eac024..fff6f0c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -29,8 +29,10 @@ obj-$(CONFIG_PDSP188x) += pdsp188x.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 ifdef CONFIG_DM_I2C
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
 endif
+endif
 obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
 obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
 obj-$(CONFIG_STATUS_LED) += status_led.o
-- 
cgit v0.10.2


From 3949a413edb2c2be6ad930a5ba4b240bbca53d08 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:20 -0600
Subject: dm: sandbox: Enable of-platdata for sandbox_spl

Enable this feature so that we can use it for testing in sandbox_spl.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index d92597b..0f6dda8 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -64,6 +64,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_HOSTFILE=y
+CONFIG_SPL_OF_PLATDATA=y
 CONFIG_NETCONSOLE=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
-- 
cgit v0.10.2


From a951431e827cfd862a4c095e85e8650a6b8370f7 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:21 -0600
Subject: dm: core: Move regmap allocation into a separate function

We plan to add a new way of creating a regmap for of-platdata. Move the
allocation code into a separate function so that it can be shared.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 7e073cf..dcb1a30 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -15,6 +15,27 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct regmap *regmap_alloc_count(int count)
+{
+	struct regmap *map;
+
+	map = malloc(sizeof(struct regmap));
+	if (!map)
+		return NULL;
+	if (count <= 1) {
+		map->range = &map->base_range;
+	} else {
+		map->range = malloc(count * sizeof(struct regmap_range));
+		if (!map->range) {
+			free(map);
+			return NULL;
+		}
+	}
+	map->range_count = count;
+
+	return map;
+}
+
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 int regmap_init_mem_platdata(struct udevice *dev, fdt32_t *reg, int size,
 			     struct regmap **mapp)
@@ -45,22 +66,11 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
 	if (!cell || !count)
 		return -EINVAL;
 
-	map = malloc(sizeof(struct regmap));
+	map = regmap_alloc_count(count);
 	if (!map)
 		return -ENOMEM;
 
-	if (count <= 1) {
-		map->range = &map->base_range;
-	} else {
-		map->range = malloc(count * sizeof(struct regmap_range));
-		if (!map->range) {
-			free(map);
-			return -ENOMEM;
-		}
-	}
-
 	map->base = fdtdec_get_number(cell, addr_len);
-	map->range_count = count;
 
 	for (range = map->range; count > 0;
 	     count--, cell += both_len, range++) {
-- 
cgit v0.10.2


From 1e6ca1a6ad7285569b22465b8387db242b310553 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:22 -0600
Subject: dm: core: Add an implementation of regmap_init_mem_platdata()

Add an implementation of this function which mirrors the functions of the
automatic device-tree implementation. This can be used with of-platdata to
create regmaps.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index dcb1a30..0299ff0 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -37,10 +37,24 @@ static struct regmap *regmap_alloc_count(int count)
 }
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_platdata(struct udevice *dev, fdt32_t *reg, int size,
+int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count,
 			     struct regmap **mapp)
 {
-	/* TODO(sjg@chromium.org): Implement this when needed */
+	struct regmap_range *range;
+	struct regmap *map;
+
+	map = regmap_alloc_count(count);
+	if (!map)
+		return -ENOMEM;
+
+	map->base = *reg;
+	for (range = map->range; count > 0; reg += 2, range++, count--) {
+		range->start = *reg;
+		range->size = reg[1];
+	}
+
+	*mapp = map;
+
 	return 0;
 }
 #else
diff --git a/include/regmap.h b/include/regmap.h
index 922b39f..1eed94e 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -56,7 +56,20 @@ int regmap_read(struct regmap *map, uint offset, uint *valp);
  */
 int regmap_init_mem(struct udevice *dev, struct regmap **mapp);
 
-int regmap_init_mem_platdata(struct udevice *dev, fdt32_t *reg, int size,
+/**
+ * regmap_init_mem_platdata() - Set up a new memory register map for of-platdata
+ *
+ * This creates a new regmap with a list of regions passed in, rather than
+ * using the device tree. It only supports 32-bit machines.
+ *
+ * Use regmap_uninit() to free it.
+ *
+ * @dev:	Device that uses this map
+ * @reg:	List of address, size pairs
+ * @count:	Number of pairs (e.g. 1 if the regmap has a single entry)
+ * @mapp:	Returns allocated map
+ */
+int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count,
 			     struct regmap **mapp);
 
 /**
-- 
cgit v0.10.2


From b2927fbaa89d2c7f7ac3977bc0cab2a4b7924acd Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:23 -0600
Subject: dm: serial: ns16550: Update to support of-platdata

With of-platdata this driver cannot know the format of the of-platdata
struct, so we cannot use generic code for accessing the of-platdata. Each
SoC that uses this driver will need to set up ns16550's platdata for it.
So don't compile in the generic code.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index c6cb3eb..88fca15 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -347,7 +347,7 @@ int ns16550_serial_probe(struct udevice *dev)
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ns16550_platdata *plat = dev->platdata;
@@ -416,6 +416,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
 	.setbrg = ns16550_serial_setbrg,
 };
 
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 /*
  * Please consider existing compatible strings before adding a new
@@ -452,4 +453,5 @@ U_BOOT_DRIVER(ns16550_serial) = {
 	.flags	= DM_FLAG_PRE_RELOC,
 };
 #endif
+#endif /* !OF_PLATDATA */
 #endif /* CONFIG_DM_SERIAL */
-- 
cgit v0.10.2


From 2fc24d5335a35a4880fdc04cf4d45754d29cd415 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:24 -0600
Subject: rockchip: serial: Add an of-platdata driver for rockchip

Add a driver that works with of-platdata. It sets up the platform data and
calls the standard ns16550 driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 0e38903..9ff7234 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -312,6 +312,15 @@ config SYS_NS16550
 	  be used. It can be a constant or a function to get clock, eg,
 	  get_serial_clock().
 
+config ROCKCHIP_SERIAL
+	bool "Rockchip on-chip UART support"
+	depends on DM_SERIAL && SPL_OF_PLATDATA
+	help
+	  Select this to enable a debug UART for Rockchip devices when using
+	  CONFIG_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
+	  This uses the ns16550 driver, converting the platdata from of-platdata
+	  to the ns16550 format.
+
 config SANDBOX_SERIAL
 	bool "Sandbox UART support"
 	depends on SANDBOX
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 92cbea5..6986d65 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -28,6 +28,9 @@ obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
+endif
 obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
 obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
new file mode 100644
index 0000000..6bac95a
--- /dev/null
+++ b/drivers/serial/serial_rockchip.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/arch/clock.h>
+
+struct rockchip_uart_platdata {
+	struct dtd_rockchip_rk3288_uart dtplat;
+	struct ns16550_platdata plat;
+};
+
+struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
+
+static int rockchip_serial_probe(struct udevice *dev)
+{
+	struct rockchip_uart_platdata *plat = dev_get_platdata(dev);
+
+	/* Create some new platform data for the standard driver */
+	plat->plat.base = plat->dtplat.reg[0];
+	plat->plat.reg_shift = plat->dtplat.reg_shift;
+	plat->plat.clock = plat->dtplat.clock_frequency;
+	dev->platdata = &plat->plat;
+
+	return ns16550_serial_probe(dev);
+}
+
+U_BOOT_DRIVER(rockchip_rk3288_uart) = {
+	.name	= "rockchip_rk3288_uart",
+	.id	= UCLASS_SERIAL,
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata),
+	.probe	= rockchip_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
-- 
cgit v0.10.2


From 9ca7e6720e96e82be1de9ec0ba6bac9f1beeb02f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:25 -0600
Subject: rockchip: Update the sdram-channel property to support of-platdata

Add an extra byte so that this data is not byteswapped. Add a comment to
the code to explain the purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
index aed8d3a..3176d50 100644
--- a/arch/arm/dts/rk3288-firefly.dts
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -30,7 +30,8 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+	/* Add a dummy value to cause of-platdata think this is bytes */
+	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index d3de42d..c9e3001 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -24,6 +24,12 @@ struct rk3288_sdram_channel {
 	u8 row_3_4;
 	u8 cs0_row;
 	u8 cs1_row;
+	/*
+	 * For of-platdata, which would otherwise convert this into two
+	 * byte-swapped integers. With a size of 9 bytes, this struct will
+	 * appear in of-platdata as a byte array.
+	 */
+	u8 dummy;
 };
 
 struct rk3288_sdram_pctl_timing {
-- 
cgit v0.10.2


From 6809b04f48fe02c26127383391d153d18134c77b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:26 -0600
Subject: rockchip: mmc: Move all DT decoding to ofdata_to_platdata()

It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 691a515..7296c5f 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -26,6 +26,9 @@ struct rockchip_mmc_plat {
 struct rockchip_dwmmc_priv {
 	struct clk clk;
 	struct dwmci_host host;
+	int fifo_depth;
+	bool fifo_mode;
+	u32 minmax[2];
 };
 
 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
@@ -61,6 +64,16 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 	else
 		host->dev_index = 1;
 
+	priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				    "fifo-depth", 0);
+	if (priv->fifo_depth < 0)
+		return -EINVAL;
+	priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+					  "fifo-mode");
+	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+				 "clock-freq-min-max", priv->minmax, 2))
+		return -EINVAL;
+
 	return 0;
 }
 
@@ -71,28 +84,17 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
 	struct udevice *pwr_dev __maybe_unused;
-	u32 minmax[2];
 	int ret;
-	int fifo_depth;
 
 	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
 		return ret;
 
-	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
-				 "clock-freq-min-max", minmax, 2))
-		return -EINVAL;
-
-	fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-				    "fifo-depth", 0);
-	if (fifo_depth < 0)
-		return -EINVAL;
-
 	host->fifoth_val = MSIZE(0x2) |
-		RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+		RX_WMARK(priv->fifo_depth / 2 - 1) |
+		TX_WMARK(priv->fifo_depth / 2);
 
-	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode"))
-		host->fifo_mode = true;
+	host->fifo_mode = priv->fifo_mode;
 
 #ifdef CONFIG_PWRSEQ
 	/* Enable power if needed */
@@ -105,7 +107,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	}
 #endif
 	dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
-			minmax[1], minmax[0]);
+			priv->minmax[1], priv->minmax[0]);
 	host->mmc = &plat->mmc;
 	host->mmc->priv = &priv->host;
 	host->mmc->dev = dev;
-- 
cgit v0.10.2


From bfeb443e3d583a5e7bbd98a67175f3a082a5e3d2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:27 -0600
Subject: rockchip: mmc: Update the driver to support of-platdata

Add support for of-platdata with rk3288. This requires decoding the
of-platdata struct and setting up the device from that. Also the driver
needs to be renamed to match the string that of-platdata will search for.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 7296c5f..020a59b 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -7,8 +7,10 @@
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <dt-structs.h>
 #include <dwmmc.h>
 #include <errno.h>
+#include <mapmem.h>
 #include <pwrseq.h>
 #include <syscon.h>
 #include <asm/gpio.h>
@@ -19,6 +21,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct rockchip_mmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3288_dw_mshc dtplat;
+#endif
 	struct mmc_config cfg;
 	struct mmc mmc;
 };
@@ -48,6 +53,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 
 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
 
@@ -73,7 +79,7 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
 				 "clock-freq-min-max", priv->minmax, 2))
 		return -EINVAL;
-
+#endif
 	return 0;
 }
 
@@ -86,10 +92,27 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	struct udevice *pwr_dev __maybe_unused;
 	int ret;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
+
+	host->name = dev->name;
+	host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+	host->buswidth = dtplat->bus_width;
+	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
+	host->priv = dev;
+	host->dev_index = 0;
+	priv->fifo_depth = dtplat->fifo_depth;
+	priv->fifo_mode = 0;
+	memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
+
+	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
+	if (ret < 0)
+		return ret;
+#else
 	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
 		return ret;
-
+#endif
 	host->fifoth_val = MSIZE(0x2) |
 		RX_WMARK(priv->fifo_depth / 2 - 1) |
 		TX_WMARK(priv->fifo_depth / 2);
@@ -134,7 +157,7 @@ static const struct udevice_id rockchip_dwmmc_ids[] = {
 };
 
 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
-	.name		= "rockchip_dwmmc",
+	.name		= "rockchip_rk3288_dw_mshc",
 	.id		= UCLASS_MMC,
 	.of_match	= rockchip_dwmmc_ids,
 	.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
-- 
cgit v0.10.2


From 08fd82cf3e55c0ab7b1038d82a7c744d3193c269 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:28 -0600
Subject: rockchip: clk: Move all DT decoding to ofdata_to_platdata()

It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Also add an error check on grf since if
that fails then we should not use it.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 2285453..1c2bf64 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -783,12 +783,22 @@ static struct clk_ops rk3288_clk_ops = {
 	.set_rate	= rk3288_clk_set_rate,
 };
 
-static int rk3288_clk_probe(struct udevice *dev)
+static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk3288_clk_priv *priv = dev_get_priv(dev);
 
 	priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
+
+	return 0;
+}
+
+static int rk3288_clk_probe(struct udevice *dev)
+{
+	struct rk3288_clk_priv *priv = dev_get_priv(dev);
+
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->grf))
+		return PTR_ERR(priv->grf);
 #ifdef CONFIG_SPL_BUILD
 	rkclk_init(priv->cru, priv->grf);
 #endif
@@ -820,5 +830,6 @@ U_BOOT_DRIVER(clk_rk3288) = {
 	.priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 	.ops		= &rk3288_clk_ops,
 	.bind		= rk3288_clk_bind,
+	.ofdata_to_platdata	= rk3288_clk_ofdata_to_platdata,
 	.probe		= rk3288_clk_probe,
 };
-- 
cgit v0.10.2


From 2d143bd6199c6c7ed6513c6a066569f76b1289f4 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:29 -0600
Subject: rockchip: clk: Update the rk3288 driver to support of-platdata

Add support for of-platdata with rk3288. This requires decoding the
of-platdata struct and setting up the devices from that. Also the driver
needs to be renamed to match the string that of-platdata will search for.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 1c2bf64..679f010 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -7,7 +7,9 @@
 #include <common.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <dt-structs.h>
 #include <errno.h>
+#include <mapmem.h>
 #include <syscon.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -21,6 +23,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct rk3288_clk_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3288_cru dtd;
+#endif
+};
+
 struct rk3288_clk_priv {
 	struct rk3288_grf *grf;
 	struct rk3288_cru *cru;
@@ -785,9 +793,11 @@ static struct clk_ops rk3288_clk_ops = {
 
 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rk3288_clk_priv *priv = dev_get_priv(dev);
 
 	priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
+#endif
 
 	return 0;
 }
@@ -800,6 +810,11 @@ static int rk3288_clk_probe(struct udevice *dev)
 	if (IS_ERR(priv->grf))
 		return PTR_ERR(priv->grf);
 #ifdef CONFIG_SPL_BUILD
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
+
+	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
+#endif
 	rkclk_init(priv->cru, priv->grf);
 #endif
 
@@ -823,11 +838,12 @@ static const struct udevice_id rk3288_clk_ids[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(clk_rk3288) = {
-	.name		= "clk_rk3288",
+U_BOOT_DRIVER(rockchip_rk3288_cru) = {
+	.name		= "rockchip_rk3288_cru",
 	.id		= UCLASS_CLK,
 	.of_match	= rk3288_clk_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
+	.platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 	.ops		= &rk3288_clk_ops,
 	.bind		= rk3288_clk_bind,
 	.ofdata_to_platdata	= rk3288_clk_ofdata_to_platdata,
-- 
cgit v0.10.2


From d95b14ffab33713c3058008bac9c05a792d39a17 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:30 -0600
Subject: rockchip: pinctrl: Update the rk3288 driver to support of-platdata

Add support for of-platdata with rk3288. This requires disabling access to
the device tree and renaming the driver to match the string that of-platdata
will search for.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 1fa1daa..8cb3b82 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -476,6 +476,7 @@ static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 					struct udevice *periph)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	u32 cell[3];
 	int ret;
 
@@ -506,6 +507,7 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 	case 103:
 		return PERIPH_ID_HDMI;
 	}
+#endif
 
 	return -ENOENT;
 }
@@ -664,8 +666,12 @@ static struct pinctrl_ops rk3288_pinctrl_ops = {
 
 static int rk3288_pinctrl_bind(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	return 0;
+#else
 	/* scan child GPIO banks */
 	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+#endif
 }
 
 #ifndef CONFIG_SPL_BUILD
@@ -719,7 +725,7 @@ static const struct udevice_id rk3288_pinctrl_ids[] = {
 };
 
 U_BOOT_DRIVER(pinctrl_rk3288) = {
-	.name		= "pinctrl_rk3288",
+	.name		= "rockchip_rk3288_pinctrl",
 	.id		= UCLASS_PINCTRL,
 	.of_match	= rk3288_pinctrl_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
-- 
cgit v0.10.2


From 6efeeea79c880d3dd262e0dca9da2687f0ab68c9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:31 -0600
Subject: rockchip: Move the MMC setup check earlier

When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 15f1266..d8c9ca7 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -114,7 +114,6 @@ static void configure_l2ctlr(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
-#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288)
 	struct gpio_desc desc;
 	int ret;
 
@@ -144,7 +143,6 @@ static int configure_emmc(struct udevice *pinctrl)
 		debug("gpio value ret=%d\n", ret);
 		return ret;
 	}
-#endif
 
 	return 0;
 }
@@ -247,15 +245,18 @@ void spl_board_init(void)
 		goto err;
 	}
 #ifdef CONFIG_SPL_MMC_SUPPORT
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-	ret = configure_emmc(pinctrl);
-	if (ret) {
-		debug("%s: Failed to set up eMMC\n", __func__);
-		goto err;
+	if (!IS_ENABLED(CONFIG_TARGET_ROCK2) &&
+	    !IS_ENABLED(CONFIG_TARGET_FIREFLY_RK3288)) {
+		ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+		if (ret) {
+			debug("%s: Failed to set up SD card\n", __func__);
+			goto err;
+		}
+		ret = configure_emmc(pinctrl);
+		if (ret) {
+			debug("%s: Failed to set up eMMC\n", __func__);
+			goto err;
+		}
 	}
 #endif
 
-- 
cgit v0.10.2


From 6afc4661e0a2daa655096702171c420518f8c2a8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:32 -0600
Subject: rockchip: Don't use spl_boot_device() with of-platdata

This function cannot look at the device tree when of-platdata is used.
Update the code to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index d8c9ca7..123f58b 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 spl_boot_device(void)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	const void *blob = gd->fdt_blob;
 	struct udevice *dev;
 	const char *bootdev;
@@ -63,6 +64,7 @@ u32 spl_boot_device(void)
 	}
 
 fallback:
+#endif
 	return BOOT_DEVICE_MMC1;
 }
 
-- 
cgit v0.10.2


From 5ce4bb2709cea7bde2196ad5f3af11f8f3aa3375 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:33 -0600
Subject: rockchip: syscon: Update to work with of-platdata

The syscon devices all end up having diffent driver names with of-platdata,
since the driver name comes from the first string in the compatible list.
Add separate device declarations for each one, and add a bind method to set
up driver_data correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
index c9f7c4e..be4b2b0 100644
--- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -23,3 +23,41 @@ U_BOOT_DRIVER(syscon_rk3288) = {
 	.id = UCLASS_SYSCON,
 	.of_match = rk3288_syscon_ids,
 };
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3288_noc) = {
+	.name = "rockchip_rk3288_noc",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids,
+	.bind = rk3288_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3288_grf) = {
+	.name = "rockchip_rk3288_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids + 1,
+	.bind = rk3288_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
+	.name = "rockchip_rk3288_sgrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids + 2,
+	.bind = rk3288_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
+	.name = "rockchip_rk3288_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids + 3,
+	.bind = rk3288_syscon_bind_of_platdata,
+};
+#endif
-- 
cgit v0.10.2


From fb4baf5d58c212f0b78ac125ee2d7c595b6437e9 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:34 -0600
Subject: rockchip: sdram: Move all DT decoding to ofdata_to_platdata()

It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Note that only SPL needs to fiddle with
the SDRAM registers, so decoding the platform data fully is not necessary in
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index c9e3001..e08e28f 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -87,12 +87,4 @@ struct rk3288_base_params {
 	u32 odt;
 };
 
-struct rk3288_sdram_params {
-	struct rk3288_sdram_channel ch[2];
-	struct rk3288_sdram_pctl_timing pctl_timing;
-	struct rk3288_sdram_phy_timing phy_timing;
-	struct rk3288_base_params base;
-	int num_channels;
-};
-
 #endif
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 55ac73e..940ee58 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -41,6 +41,16 @@ struct dram_info {
 	struct rk3288_grf *grf;
 	struct rk3288_sgrf *sgrf;
 	struct rk3288_pmu *pmu;
+	bool is_veyron;
+};
+
+struct rk3288_sdram_params {
+	struct rk3288_sdram_channel ch[2];
+	struct rk3288_sdram_pctl_timing pctl_timing;
+	struct rk3288_sdram_phy_timing phy_timing;
+	struct rk3288_base_params base;
+	int num_channels;
+	struct regmap *map;
 };
 
 #ifdef CONFIG_SPL_BUILD
@@ -703,7 +713,7 @@ static int sdram_init(struct dram_info *dram,
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 size_t sdram_size_mb(struct rk3288_pmu *pmu)
 {
@@ -779,18 +789,35 @@ static int veyron_init(struct dram_info *priv)
 static int setup_sdram(struct udevice *dev)
 {
 	struct dram_info *priv = dev_get_priv(dev);
-	struct rk3288_sdram_params params;
+	struct rk3288_sdram_params *params = dev_get_platdata(dev);
+
+# ifdef CONFIG_ROCKCHIP_FAST_SPL
+	if (priv->is_veyron) {
+		int ret;
+
+		ret = veyron_init(priv);
+		if (ret)
+			return ret;
+	}
+# endif
+
+	return sdram_init(priv, params);
+}
+
+static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk3288_sdram_params *params = dev_get_platdata(dev);
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
 	int i, ret;
 
-	params.num_channels = fdtdec_get_int(blob, node,
-					     "rockchip,num-channels", 1);
-	for (i = 0; i < params.num_channels; i++) {
+	params->num_channels = fdtdec_get_int(blob, node,
+					      "rockchip,num-channels", 1);
+	for (i = 0; i < params->num_channels; i++) {
 		ret = fdtdec_get_byte_array(blob, node,
 					    "rockchip,sdram-channel",
-					    (u8 *)&params.ch[i],
-					    sizeof(params.ch[i]));
+					    (u8 *)&params->ch[i],
+					    sizeof(params->ch[i]));
 		if (ret) {
 			debug("%s: Cannot read rockchip,sdram-channel\n",
 			      __func__);
@@ -798,41 +825,44 @@ static int setup_sdram(struct udevice *dev)
 		}
 	}
 	ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
-				   (u32 *)&params.pctl_timing,
-				   sizeof(params.pctl_timing) / sizeof(u32));
+				   (u32 *)&params->pctl_timing,
+				   sizeof(params->pctl_timing) / sizeof(u32));
 	if (ret) {
 		debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
 		return -EINVAL;
 	}
 	ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
-				   (u32 *)&params.phy_timing,
-				   sizeof(params.phy_timing) / sizeof(u32));
+				   (u32 *)&params->phy_timing,
+				   sizeof(params->phy_timing) / sizeof(u32));
 	if (ret) {
 		debug("%s: Cannot read rockchip,phy-timing\n", __func__);
 		return -EINVAL;
 	}
 	ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
-				   (u32 *)&params.base,
-				   sizeof(params.base) / sizeof(u32));
+				   (u32 *)&params->base,
+				   sizeof(params->base) / sizeof(u32));
 	if (ret) {
 		debug("%s: Cannot read rockchip,sdram-params\n", __func__);
 		return -EINVAL;
 	}
+#ifdef CONFIG_ROCKCHIP_FAST_SPL
+	struct dram_info *priv = dev_get_priv(dev);
 
-# ifdef CONFIG_ROCKCHIP_FAST_SPL
-	if (!fdt_node_check_compatible(blob, 0, "google,veyron")) {
-		ret = veyron_init(priv);
-		if (ret)
-			return ret;
-	}
-# endif
+	priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
+#endif
+	ret = regmap_init_mem(dev, &params->map);
+	if (ret)
+		return ret;
 
-	return sdram_init(priv, &params);
+	return 0;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 static int rk3288_dmc_probe(struct udevice *dev)
 {
+#ifdef CONFIG_SPL_BUILD
+	struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+#endif
 	struct dram_info *priv = dev_get_priv(dev);
 	struct regmap *map;
 	int ret;
@@ -849,14 +879,12 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
 	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 
-	ret = regmap_init_mem(dev, &map);
-	if (ret)
-		return ret;
-	priv->chan[0].pctl = regmap_get_range(map, 0);
-	priv->chan[0].publ = regmap_get_range(map, 1);
-	priv->chan[1].pctl = regmap_get_range(map, 2);
-	priv->chan[1].publ = regmap_get_range(map, 3);
-
+#ifdef CONFIG_SPL_BUILD
+	priv->chan[0].pctl = regmap_get_range(plat->map, 0);
+	priv->chan[0].publ = regmap_get_range(plat->map, 1);
+	priv->chan[1].pctl = regmap_get_range(plat->map, 2);
+	priv->chan[1].publ = regmap_get_range(plat->map, 3);
+#endif
 	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
 	if (ret)
 		return ret;
@@ -902,6 +930,12 @@ U_BOOT_DRIVER(dmc_rk3288) = {
 	.id = UCLASS_RAM,
 	.of_match = rk3288_dmc_ids,
 	.ops = &rk3288_dmc_ops,
+#ifdef CONFIG_SPL_BUILD
+	.ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
+#endif
 	.probe = rk3288_dmc_probe,
 	.priv_auto_alloc_size = sizeof(struct dram_info),
+#ifdef CONFIG_SPL_BUILD
+	.platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
+#endif
 };
-- 
cgit v0.10.2


From 086ec0e26d6117f492bad138b4dbee9318ff61bd Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:35 -0600
Subject: rockchip: sdram: Update the driver to support of-platdata

Add support for of-platdata with rk3288 SDRAM initr. This requires decoding
the of-platdata struct and setting up the device from that. Also the driver
needs to be renamed to match the string that of-platdata will search for.

The platform data is copied from the of-platdata structure to the one used
by the driver. This allows the same code to be used with device tree and
of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 940ee58..b36b6af 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <dt-structs.h>
 #include <errno.h>
 #include <ram.h>
 #include <regmap.h>
@@ -45,6 +46,9 @@ struct dram_info {
 };
 
 struct rk3288_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3288_dmc of_plat;
+#endif
 	struct rk3288_sdram_channel ch[2];
 	struct rk3288_sdram_pctl_timing pctl_timing;
 	struct rk3288_sdram_phy_timing phy_timing;
@@ -806,6 +810,7 @@ static int setup_sdram(struct udevice *dev)
 
 static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rk3288_sdram_params *params = dev_get_platdata(dev);
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
@@ -853,11 +858,39 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 	ret = regmap_init_mem(dev, &params->map);
 	if (ret)
 		return ret;
+#endif
 
 	return 0;
 }
 #endif /* CONFIG_SPL_BUILD */
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+	struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+	struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
+	int i, ret;
+
+	for (i = 0; i < 2; i++) {
+		memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
+		       sizeof(plat->ch[i]));
+	}
+	memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
+	       sizeof(plat->pctl_timing));
+	memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
+	       sizeof(plat->phy_timing));
+	memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
+	plat->num_channels = of_plat->rockchip_num_channels;
+	ret = regmap_init_mem_platdata(dev, of_plat->reg,
+				       ARRAY_SIZE(of_plat->reg) / 2,
+				       &plat->map);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
 static int rk3288_dmc_probe(struct udevice *dev)
 {
 #ifdef CONFIG_SPL_BUILD
@@ -868,6 +901,11 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	int ret;
 	struct udevice *dev_clk;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	ret = conv_of_platdata(dev);
+	if (ret)
+		return ret;
+#endif
 	map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 	if (IS_ERR(map))
 		return PTR_ERR(map);
@@ -926,7 +964,7 @@ static const struct udevice_id rk3288_dmc_ids[] = {
 };
 
 U_BOOT_DRIVER(dmc_rk3288) = {
-	.name = "rk3288_dmc",
+	.name = "rockchip_rk3288_dmc",
 	.id = UCLASS_RAM,
 	.of_match = rk3288_dmc_ids,
 	.ops = &rk3288_dmc_ops,
-- 
cgit v0.10.2


From 97feca3325bb2065a7ef7d30e1f308b74f1fb33c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:36 -0600
Subject: rockchip: Use of-platdata for firefly-rk3288

As an experiment, move this board over to use of-platdata. This means that
its SPL configuration will come from C structures generated at build-time
from the device tree, instead of coming from the device tree at run-time.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 4af9120..bdafc71 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -69,3 +69,6 @@ CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_SPL_OF_PLATDATA=y
+# CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_ROCKCHIP_SERIAL=y
-- 
cgit v0.10.2


From 2fedbaa4aea4f781863c9b11879ae4d43149c447 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:37 -0600
Subject: test/py: Handle testing with the sandbox_spl board

This board can sometimes be used for tests. Handle it the same way as
sandbox.

Note: I plan to drop the sandbox_spl board at some point and merge its
features into sandbox. So this commit may not be necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/conftest.py b/test/py/conftest.py
index 449f98b..050f6e4 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -192,7 +192,7 @@ def pytest_configure(config):
     for v in env_vars:
         os.environ['U_BOOT_' + v.upper()] = getattr(ubconfig, v)
 
-    if board_type == 'sandbox':
+    if board_type.startswith('sandbox'):
         import u_boot_console_sandbox
         console = u_boot_console_sandbox.ConsoleSandbox(log, ubconfig)
     else:
-- 
cgit v0.10.2


From c7f636f59d7d506b89d7fc52aa6509329e9ded1b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:38 -0600
Subject: test/py: Note which console produced unexpected output

At present the SPL and U-Boot consoles both present the same error message
when the expected console output does not appear. Add "SPL" to the SPL error
message to resolve this ambiguity.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index 815fa64..2dcb289 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -329,7 +329,7 @@ class ConsoleBase(object):
                 m = self.p.expect([pattern_u_boot_spl_signon] +
                                   self.bad_patterns)
                 if m != 0:
-                    raise Exception('Bad pattern found on console: ' +
+                    raise Exception('Bad pattern found on SPL console: ' +
                                     self.bad_pattern_ids[m - 1])
             m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns)
             if m != 0:
-- 
cgit v0.10.2


From ebec58fbcb6da7404b535b9d860546d9baef55c2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:39 -0600
Subject: test/py: Provide a way to get early console output

Some tests want to check the console output from SPL or U-Boot proper.
Provide a means to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index 2dcb289..3d2ac44 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -377,6 +377,16 @@ class ConsoleBase(object):
             pass
         self.p = None
 
+    def get_spawn_output(self):
+        """Return the start-up output from U-Boot
+
+        Returns:
+            The output produced by ensure_spawed(), as a string.
+        """
+        if self.p:
+            return self.p.get_expect_output()
+        return None
+
     def validate_version_string_in_text(self, text):
         """Assert that a command's output includes the U-Boot signon message.
 
diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py
index d155173..3a0fbfa 100644
--- a/test/py/u_boot_spawn.py
+++ b/test/py/u_boot_spawn.py
@@ -18,6 +18,9 @@ class Timeout(Exception):
 class Spawn(object):
     """Represents the stdio of a freshly created sub-process. Commands may be
     sent to the process, and responses waited for.
+
+    Members:
+        output: accumulated output from expect()
     """
 
     def __init__(self, args, cwd=None):
@@ -34,6 +37,7 @@ class Spawn(object):
 
         self.waited = False
         self.buf = ''
+        self.output = ''
         self.logfile_read = None
         self.before = ''
         self.after = ''
@@ -154,6 +158,7 @@ class Spawn(object):
                     posafter = earliest_m.end()
                     self.before = self.buf[:pos]
                     self.after = self.buf[pos:posafter]
+                    self.output += self.buf[:posafter]
                     self.buf = self.buf[posafter:]
                     return earliest_pi
                 tnow_s = time.time()
@@ -198,3 +203,11 @@ class Spawn(object):
             if not self.isalive():
                 break
             time.sleep(0.1)
+
+    def get_expect_output(self):
+        """Return the output read by expect()
+
+        Returns:
+            The output processed by expect(), as a string.
+        """
+        return self.output
-- 
cgit v0.10.2


From a811779b174f8c5c687aaa5574dfdea9f3745f98 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:40 -0600
Subject: test/py: Start sandbox SPL when enabled

When sandbox SPL is enabled we want to start that rather than U-Boot proper,
since some tests may rely on running it first.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py
index 04654ae..6bf4653 100644
--- a/test/py/u_boot_console_sandbox.py
+++ b/test/py/u_boot_console_sandbox.py
@@ -39,11 +39,15 @@ class ConsoleSandbox(ConsoleBase):
             A u_boot_spawn.Spawn object that is attached to U-Boot.
         """
 
+        bcfg = self.config.buildconfig
+        config_spl = bcfg.get('config_spl', 'n') == 'y'
+        fname = '/spl/u-boot-spl' if config_spl else '/u-boot'
+        print fname
         cmd = []
         if self.config.gdbserver:
             cmd += ['gdbserver', self.config.gdbserver]
         cmd += [
-            self.config.build_dir + '/u-boot',
+            self.config.build_dir + fname,
             '-v',
             '-d',
             self.config.build_dir + '/arch/sandbox/dts/test.dtb'
-- 
cgit v0.10.2


From b979d3d4c55def30cd0eb1e2c82beefb30fc8e87 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:41 -0600
Subject: dm: Add a test for of-platdata

Add a simple test which checks that the of-platdata system is working
correctly. The sequence is as follows:

- SPL starts up and probes all the UCLASS_MISC drivers
- There are 3 of these in sandbox.dts
- Therefore there should be 3 U_BOOT_DEVICE() declarations in dt-platdata.c
- These should produce 3 sandbox_spl_test devices
- Each device prints out its platform data when probed
- This test checks for this output and compares it against expectations

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py
new file mode 100644
index 0000000..c8b309e
--- /dev/null
+++ b/test/py/tests/test_ofplatdata.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+import pytest
+
+OF_PLATDATA_OUTPUT = '''
+of-platdata probe:
+bool 1
+byte 05
+bytearray 06 00 00
+int 1
+intarray 2 3 4 0
+longbytearray 09 0a 0b 0c 0d 0e 0f 10 11
+string message
+stringarray "multi-word" "message" ""
+of-platdata probe:
+bool 0
+byte 08
+bytearray 01 23 34
+int 3
+intarray 5 0 0 0
+longbytearray 09 00 00 00 00 00 00 00 00
+string message2
+stringarray "another" "multi-word" "message"
+of-platdata probe:
+bool 0
+byte 00
+bytearray 00 00 00
+int 0
+intarray 0 0 0 0
+longbytearray 00 00 00 00 00 00 00 00 00
+string <NULL>
+stringarray "one" "" ""
+'''
+
+@pytest.mark.buildconfigspec('spl')
+def test_ofplatdata(u_boot_console):
+    """Test that of-platdata can be generated and used in sandbox"""
+    cons = u_boot_console
+    output = cons.get_spawn_output().replace('\r', '')
+    assert OF_PLATDATA_OUTPUT in output
-- 
cgit v0.10.2


From 1269625177f120d659f66b18de4b532b16c44561 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 4 Jul 2016 11:58:42 -0600
Subject: dm: Update the of-platdata README for the new features

Revise the content based on the v2 additions. This is kept as a separate
patch to avoid confusing those who have already reviewed the v1 series.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>

diff --git a/doc/driver-model/of-plat.txt b/doc/driver-model/of-plat.txt
index 96b9b46..86e5e25 100644
--- a/doc/driver-model/of-plat.txt
+++ b/doc/driver-model/of-plat.txt
@@ -19,24 +19,28 @@ SoCs require a 16KB SPL image which must include a full MMC stack. In this
 case the overhead of device tree access may be too great.
 
 It is possible to create platform data manually by defining C structures
-for it, and referencing that data in a U_BOOT_DEVICE() declaration. This
-bypasses the use of device tree completely, but is an available option for
-SPL.
+for it, and reference that data in a U_BOOT_DEVICE() declaration. This
+bypasses the use of device tree completely, effectively creating a parallel
+configuration mechanism. But it is an available option for SPL.
 
-As an alternative, a new 'of-platdata' feature is provided. This converts
+As an alternative, a new 'of-platdata' feature is provided. This converts the
 device tree contents into C code which can be compiled into the SPL binary.
 This saves the 3KB of code overhead and perhaps a few hundred more bytes due
 to more efficient storage of the data.
 
+Note: Quite a bit of thought has gone into the design of this feature.
+However it still has many rough edges and comments and suggestions are
+strongly encouraged! Quite possibly there is a much better approach.
+
 
 Caveats
 -------
 
 There are many problems with this features. It should only be used when
-stricly necessary. Notable problems include:
+strictly necessary. Notable problems include:
 
-   - Device tree does not describe data types but the C code must define a
-        type for each property. Thesee are guessed using heuristics which
+   - Device tree does not describe data types. But the C code must define a
+        type for each property. These are guessed using heuristics which
         are wrong in several fairly common cases. For example an 8-byte value
         is considered to be a 2-item integer array, and is byte-swapped. A
         boolean value that is not present means 'false', but cannot be
@@ -45,14 +49,15 @@ stricly necessary. Notable problems include:
 
    - Naming of nodes and properties is automatic. This means that they follow
         the naming in the device tree, which may result in C identifiers that
-        look a bit strange
+        look a bit strange.
 
    - It is not possible to find a value given a property name. Code must use
         the associated C member variable directly in the code. This makes
         the code less robust in the face of device-tree changes. It also
         makes it very unlikely that your driver code will be useful for more
         than one SoC. Even if the code is common, each SoC will end up with
-        a different C struct and format for the platform data.
+        a different C struct name, and a likely a different format for the
+        platform data.
 
    - The platform data is provided to drivers as a C structure. The driver
         must use the same structure to access the data. Since a driver
@@ -112,7 +117,6 @@ struct dtd_rockchip_rk3288_dw_mshc {
         fdt32_t         interrupts[3];
         fdt32_t         num_slots;
         fdt32_t         reg[2];
-        bool            u_boot_dm_pre_reloc;
         fdt32_t         vmmc_supply;
 };
 
@@ -125,7 +129,10 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_dwmmc_at_ff0c0000 = {
         .clock_freq_min_max     = {0x61a80, 0x8f0d180},
         .vmmc_supply            = 0xb,
         .num_slots              = 0x1,
-        .clocks                 = {{&dtv_clock_controller_at_ff760000, 456}, {&dtv_clock_controller_at_ff760000, 68}, {&dtv_clock_controller_at_ff760000, 114}, {&dtv_clock_controller_at_ff760000, 118}},
+        .clocks                 = {{&dtv_clock_controller_at_ff760000, 456},
+                                   {&dtv_clock_controller_at_ff760000, 68},
+                                   {&dtv_clock_controller_at_ff760000, 114},
+                                   {&dtv_clock_controller_at_ff760000, 118}},
         .cap_mmc_highspeed      = true,
         .disable_wp             = true,
         .bus_width              = 0x4,
@@ -136,6 +143,7 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_dwmmc_at_ff0c0000 = {
 U_BOOT_DEVICE(dwmmc_at_ff0c0000) = {
         .name           = "rockchip_rk3288_dw_mshc",
         .platdata       = &dtv_dwmmc_at_ff0c0000,
+        .platdata_size  = sizeof(dtv_dwmmc_at_ff0c0000),
 };
 
 The device is then instantiated at run-time and the platform data can be
@@ -149,15 +157,31 @@ platform data in the driver. The ofdata_to_platdata() method should
 therefore do nothing in such a driver.
 
 
+Converting of-platdata to a useful form
+---------------------------------------
+
+Of course it would be possible use the of-platdata directly in your driver
+whenever configuration information is required. However this meands that the
+driver will not be able to support device tree, since the of-platdata
+structure is not available when device tree is used. It would make no sense
+to use this structure if device tree were available, since the structure has
+all the limitations metioned in caveats above.
+
+Therefore it is recommended that the of-platdata structure should be used
+only in the probe() method of your driver. It cannot be used in the
+ofdata_to_platdata() method since this is not called when platform data is
+already present.
+
+
 How to structure your driver
 ----------------------------
 
 Drivers should always support device tree as an option. The of-platdata
 feature is intended as a add-on to existing drivers.
 
-Your driver should directly access the platdata struct in its probe()
-method. The existing device tree decoding logic should be kept in the
-ofdata_to_platdata() and wrapped with #ifdef.
+Your driver should convert the platdata struct in its probe() method. The
+existing device tree decoding logic should be kept in the
+ofdata_to_platdata() method and wrapped with #if.
 
 For example:
 
@@ -165,13 +189,12 @@ For example:
 
     struct mmc_platdata {
     #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
-            /* Put this first */
+            /* Put this first since driver model will copy the data here */
             struct dtd_mmc dtplat;
     #endif
             /*
              * Other fields can go here, to be filled in by decoding from
-             * the device tree. They will point to random memory in the
-             * of-plat case.
+             * the device tree (or the C structures when of-platdata is used).
              */
             int fifo_depth;
     };
@@ -179,6 +202,7 @@ For example:
     static int mmc_ofdata_to_platdata(struct udevice *dev)
     {
     #if !CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
+            /* Decode the device tree data */
             struct mmc_platdata *plat = dev_get_platdata(dev);
             const void *blob = gd->fdt_blob;
             int node = dev->of_offset;
@@ -192,15 +216,15 @@ For example:
     static int mmc_probe(struct udevice *dev)
     {
             struct mmc_platdata *plat = dev_get_platdata(dev);
+
     #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA)
+            /* Decode the of-platdata from the C structures */
             struct dtd_mmc *dtplat = &plat->dtplat;
 
-            /* Set up the device from the dtplat data */
-            writel(dtplat->fifo_depth, ...)
-    #else
+            plat->fifo_depth = dtplat->fifo_depth;
+    #endif
             /* Set up the device from the plat data */
             writel(plat->fifo_depth, ...)
-    #endif
     }
 
     static const struct udevice_id mmc_ids[] = {
@@ -220,15 +244,26 @@ For example:
 
 
 In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is
-ignored, and the platform data points to the C structure data. In the case
-where device tree is used, the platform data is allocated, and starts
-zeroed. In this case the ofdata_to_platdata() method should set up the
-platform data.
+still used to allocate space for the platform data. This is different from
+the normal behaviour and is triggered by the use of of-platdata (strictly
+speaking it is a non-zero platdata_size which triggers this).
 
-SPL must use either of-platdata or device tree. Drivers cannot use both.
-The device tree becomes in accessible when CONFIG_SPL_OF_PLATDATA is enabled,
-since the device-tree access code is not compiled in.
+The of-platdata struct contents is copied from the C structure data to the
+start of the newly allocated area. In the case where device tree is used,
+the platform data is allocated, and starts zeroed. In this case the
+ofdata_to_platdata() method should still set up the platform data (and the
+of-platdata struct will not be present).
+
+SPL must use either of-platdata or device tree. Drivers cannot use both at
+the same time, but they must support device tree. Supporting of-platdata is
+optional.
 
+The device tree becomes in accessible when CONFIG_SPL_OF_PLATDATA is enabled,
+since the device-tree access code is not compiled in. A corollary is that
+a board can only move to using of-platdata if all the drivers it uses support
+it. There would be little point in having some drivers require the device
+tree data, since then libfdt would still be needed for those drivers and
+there would be no code-size benefit.
 
 Internals
 ---------
@@ -236,7 +271,8 @@ Internals
 The dt-structs.h file includes the generated file
 (include/generated//dt-structs.h) if CONFIG_SPL_OF_PLATDATA is enabled.
 Otherwise (such as in U-Boot proper) these structs are not available. This
-prevents them being used inadvertently.
+prevents them being used inadvertently. All usage must be bracketed with
+#if CONFIG_IS_ENABLED(SPL_OF_PLATDATA).
 
 The dt-platdata.c file contains the device declarations and is is built in
 spl/dt-platdata.c.
@@ -249,20 +285,26 @@ yet implemented, however.
 The beginnings of a libfdt Python module are provided. So far this only
 implements a subset of the features.
 
-The 'swig' tool is needed to build the libfdt Python module.
+The 'swig' tool is needed to build the libfdt Python module. If this is not
+found then the Python model is not used and a fallback is used instead, which
+makes use of fdtget.
+
+
+Credits
+-------
+
+This is an implementation of an idea by Tom Rini <trini@konsulko.com>.
 
 
 Future work
 -----------
-- Add unit tests
-- Add a sandbox_spl functional test
 - Consider programmatically reading binding files instead of device tree
      contents
-- Drop the device tree data from the SPL image
 - Complete the phandle feature
-- Get this running on a Rockchip board
 - Move to using a full Python libfdt module
 
 --
 Simon Glass <sjg@chromium.org>
+Google, Inc
 6/6/16
+Updated Independence Day 2016
-- 
cgit v0.10.2


From 19e99fb4ff73f648f2b316d0ddd8ee3c01496bd4 Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Tue, 7 Jun 2016 14:28:34 +0300
Subject: sunxi: Support booting from SPI flash

Allwinner devices support SPI flash as one of the possible
bootable media type. The SPI flash chip needs to be connected
to SPI0 pins (port C) to make this work. More information is
available at:

    https://linux-sunxi.org/Bootable_SPI_flash

This patch adds the initial support for booting from SPI flash.
The existing SPI frameworks are not used in order to reduce the
SPL code size. Right now the SPL size grows by ~370 bytes when
CONFIG_SPL_SPI_SUNXI option is enabled.

While there are no popular Allwinner devices with SPI flash at
the moment, testing can be done using a SPI flash module (it
can be bought for ~2$ on ebay) and jumper wires with the boards,
which expose relevant pins on the expansion header. The SPI flash
chips themselves are very cheap (some prices are even listed as
low as 4 cents) and should not cost much if somebody decides to
design a development board with an SPI flash chip soldered on
the PCB.

Another nice feature of the SPI flash is that it can be safely
accessed in a device-independent way (since we know that the
boot ROM is already probing these pins during the boot time).
And if, for example, Olimex boards opted to use SPI flash instead
of EEPROM, then they would have been able to have U-Boot installed
in the SPI flash now and boot the rest of the system from the SATA
hard drive. Hopefully we may see new interesting Allwinner based
development boards in the future, now that the software support
for the SPI flash is in a better shape :-)

Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option
in a board defconfig, then building U-Boot and finally flashing
the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with
a help of the sunxi-fel tool:

   sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin

The device needs to be switched into FEL (USB recovery) mode first.
The most suitable boards for testing are Orange Pi PC and Pine64.
Because these boards are cheap, have no built-in NAND/eMMC and
expose SPI0 pins on the Raspberry Pi compatible expansion header.
The A13-OLinuXino-Micro board also can be used.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 1ace548..bff7d14 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -141,6 +141,7 @@ enum sunxi_gpio_number {
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
+#define SUNXI_GPIO_DISABLE	7
 
 #define SUNXI_GPA_EMAC		2
 #define SUN6I_GPA_GMAC		2
@@ -162,8 +163,10 @@ enum sunxi_gpio_number {
 #define SUN50I_GPB_UART0	4
 
 #define SUNXI_GPC_NAND		2
+#define SUNXI_GPC_SPI0		3
 #define SUNXI_GPC_SDC2		3
 #define SUN6I_GPC_SDC3		4
+#define SUN50I_GPC_SPI0		4
 
 #define SUN8I_GPD_SDC1		3
 #define SUNXI_GPD_LCD0		2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 66e028e..3f5116b 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -223,6 +223,11 @@ u32 spl_boot_device(void)
 	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
 		return BOOT_DEVICE_BOARD;
 
+#ifdef CONFIG_SPL_SPI_SUNXI
+	if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_SPI)
+		return BOOT_DEVICE_SPI;
+#endif
+
 	/* The BROM will try to boot from mmc0 first, so try that first. */
 #ifdef CONFIG_MMC
 	mmc_initialize(gd->bd);
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 840910a..0039716 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -270,7 +270,7 @@ struct boot_device_name boot_name_table[] = {
 #ifdef CONFIG_SPL_YMODEM_SUPPORT
 	{ BOOT_DEVICE_UART, "UART" },
 #endif
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
 	{ BOOT_DEVICE_SPI, "SPI" },
 #endif
 #ifdef CONFIG_SPL_ETH_SUPPORT
@@ -346,7 +346,7 @@ static int spl_load_image(u32 boot_device)
 	case BOOT_DEVICE_UART:
 		return spl_ymodem_load_image();
 #endif
-#ifdef CONFIG_SPL_SPI_SUPPORT
+#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
 	case BOOT_DEVICE_SPI:
 		return spl_spi_load_image();
 #endif
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 3f7433c..1f23c8e 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -128,4 +128,16 @@ config SPI_FLASH_MTD
 
 	  If unsure, say N
 
+if SPL
+
+config SPL_SPI_SUNXI
+	bool "Support for SPI Flash on Allwinner SoCs in SPL"
+	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_H3 || MACH_SUN50I
+	---help---
+	Enable support for SPI Flash. This option allows SPL to read from
+	sunxi SPI Flash. It uses the same method as the boot ROM, so does
+	not need any extra configuration.
+
+endif
+
 endmenu # menu "SPI Flash Support"
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c665836..6f47a66 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_SPI_LOAD)	+= spi_spl_load.o
 obj-$(CONFIG_SPL_SPI_BOOT)	+= fsl_espi_spl.o
+obj-$(CONFIG_SPL_SPI_SUNXI)	+= sunxi_spi_spl.o
 endif
 
 obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o
diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c
new file mode 100644
index 0000000..e3ded5b
--- /dev/null
+++ b/drivers/mtd/spi/sunxi_spi_spl.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+#error CONFIG_SPL_OS_BOOT is not supported yet
+#endif
+
+/*
+ * This is a very simple U-Boot image loading implementation, trying to
+ * replicate what the boot ROM is doing when loading the SPL. Because we
+ * know the exact pins where the SPI Flash is connected and also know
+ * that the Read Data Bytes (03h) command is supported, the hardware
+ * configuration is very simple and we don't need the extra flexibility
+ * of the SPI framework. Moreover, we rely on the default settings of
+ * the SPI controler hardware registers and only adjust what needs to
+ * be changed. This is good for the code size and this implementation
+ * adds less than 400 bytes to the SPL.
+ *
+ * There are two variants of the SPI controller in Allwinner SoCs:
+ * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
+ * Both of them are supported.
+ *
+ * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
+ * supported at the moment.
+ */
+
+/*****************************************************************************/
+/* SUN4I variant of the SPI controller                                       */
+/*****************************************************************************/
+
+#define SUN4I_SPI0_CCTL             (0x01C05000 + 0x1C)
+#define SUN4I_SPI0_CTL              (0x01C05000 + 0x08)
+#define SUN4I_SPI0_RX               (0x01C05000 + 0x00)
+#define SUN4I_SPI0_TX               (0x01C05000 + 0x04)
+#define SUN4I_SPI0_FIFO_STA         (0x01C05000 + 0x28)
+#define SUN4I_SPI0_BC               (0x01C05000 + 0x20)
+#define SUN4I_SPI0_TC               (0x01C05000 + 0x24)
+
+#define SUN4I_CTL_ENABLE            BIT(0)
+#define SUN4I_CTL_MASTER            BIT(1)
+#define SUN4I_CTL_TF_RST            BIT(8)
+#define SUN4I_CTL_RF_RST            BIT(9)
+#define SUN4I_CTL_XCH               BIT(10)
+
+/*****************************************************************************/
+/* SUN6I variant of the SPI controller                                       */
+/*****************************************************************************/
+
+#define SUN6I_SPI0_CCTL             (0x01C68000 + 0x24)
+#define SUN6I_SPI0_GCR              (0x01C68000 + 0x04)
+#define SUN6I_SPI0_TCR              (0x01C68000 + 0x08)
+#define SUN6I_SPI0_FIFO_STA         (0x01C68000 + 0x1C)
+#define SUN6I_SPI0_MBC              (0x01C68000 + 0x30)
+#define SUN6I_SPI0_MTC              (0x01C68000 + 0x34)
+#define SUN6I_SPI0_BCC              (0x01C68000 + 0x38)
+#define SUN6I_SPI0_TXD              (0x01C68000 + 0x200)
+#define SUN6I_SPI0_RXD              (0x01C68000 + 0x300)
+
+#define SUN6I_CTL_ENABLE            BIT(0)
+#define SUN6I_CTL_MASTER            BIT(1)
+#define SUN6I_CTL_SRST              BIT(31)
+#define SUN6I_TCR_XCH               BIT(31)
+
+/*****************************************************************************/
+
+#define CCM_AHB_GATING0             (0x01C20000 + 0x60)
+#define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
+#define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
+
+#define AHB_RESET_SPI0_SHIFT        20
+#define AHB_GATE_OFFSET_SPI0        20
+
+#define SPI0_CLK_DIV_BY_2           0x1000
+#define SPI0_CLK_DIV_BY_4           0x1001
+
+/*****************************************************************************/
+
+/*
+ * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
+ * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
+ */
+static void spi0_pinmux_setup(unsigned int pin_function)
+{
+	unsigned int pin;
+
+	for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
+		sunxi_gpio_set_cfgpin(pin, pin_function);
+
+	if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
+		sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
+	else
+		sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
+}
+
+/*
+ * Setup 6 MHz from OSC24M (because the BROM is doing the same).
+ */
+static void spi0_enable_clock(void)
+{
+	/* Deassert SPI0 reset on SUN6I */
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+		setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
+			     (1 << AHB_RESET_SPI0_SHIFT));
+
+	/* Open the SPI0 gate */
+	setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+
+	/* Divide by 4 */
+	writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
+				  SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);
+	/* 24MHz from OSC24M */
+	writel((1 << 31), CCM_SPI0_CLK);
+
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
+		/* Enable SPI in the master mode and do a soft reset */
+		setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
+					     SUN6I_CTL_ENABLE |
+					     SUN6I_CTL_SRST);
+		/* Wait for completion */
+		while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
+			;
+	} else {
+		/* Enable SPI in the master mode and reset FIFO */
+		setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
+					     SUN4I_CTL_ENABLE |
+					     SUN4I_CTL_TF_RST |
+					     SUN4I_CTL_RF_RST);
+	}
+}
+
+static void spi0_disable_clock(void)
+{
+	/* Disable the SPI0 controller */
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+		clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
+					     SUN6I_CTL_ENABLE);
+	else
+		clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
+					     SUN4I_CTL_ENABLE);
+
+	/* Disable the SPI0 clock */
+	writel(0, CCM_SPI0_CLK);
+
+	/* Close the SPI0 gate */
+	clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+
+	/* Assert SPI0 reset on SUN6I */
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+		clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
+			     (1 << AHB_RESET_SPI0_SHIFT));
+}
+
+static int spi0_init(void)
+{
+	unsigned int pin_function = SUNXI_GPC_SPI0;
+	if (IS_ENABLED(CONFIG_MACH_SUN50I))
+		pin_function = SUN50I_GPC_SPI0;
+
+	spi0_pinmux_setup(pin_function);
+	spi0_enable_clock();
+}
+
+static void spi0_deinit(void)
+{
+	/* New SoCs can disable pins, older could only set them as input */
+	unsigned int pin_function = SUNXI_GPIO_INPUT;
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+		pin_function = SUNXI_GPIO_DISABLE;
+
+	spi0_disable_clock();
+	spi0_pinmux_setup(pin_function);
+}
+
+/*****************************************************************************/
+
+#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
+
+static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
+				 u32 spi_ctl_reg,
+				 u32 spi_ctl_xch_bitmask,
+				 u32 spi_fifo_reg,
+				 u32 spi_tx_reg,
+				 u32 spi_rx_reg,
+				 u32 spi_bc_reg,
+				 u32 spi_tc_reg,
+				 u32 spi_bcc_reg)
+{
+	writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
+	writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
+	if (spi_bcc_reg)
+		writel(4, spi_bcc_reg);  /* SUN6I also needs this */
+
+	/* Send the Read Data Bytes (03h) command header */
+	writeb(0x03, spi_tx_reg);
+	writeb((u8)(addr >> 16), spi_tx_reg);
+	writeb((u8)(addr >> 8), spi_tx_reg);
+	writeb((u8)(addr), spi_tx_reg);
+
+	/* Start the data transfer */
+	setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
+
+	/* Wait until everything is received in the RX FIFO */
+	while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
+		;
+
+	/* Skip 4 bytes */
+	readl(spi_rx_reg);
+
+	/* Read the data */
+	while (bufsize-- > 0)
+		*buf++ = readb(spi_rx_reg);
+
+	/* tSHSL time is up to 100 ns in various SPI flash datasheets */
+	udelay(1);
+}
+
+static void spi0_read_data(void *buf, u32 addr, u32 len)
+{
+	u8 *buf8 = buf;
+	u32 chunk_len;
+
+	while (len > 0) {
+		chunk_len = len;
+		if (chunk_len > SPI_READ_MAX_SIZE)
+			chunk_len = SPI_READ_MAX_SIZE;
+
+		if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
+			sunxi_spi0_read_data(buf8, addr, chunk_len,
+					     SUN6I_SPI0_TCR,
+					     SUN6I_TCR_XCH,
+					     SUN6I_SPI0_FIFO_STA,
+					     SUN6I_SPI0_TXD,
+					     SUN6I_SPI0_RXD,
+					     SUN6I_SPI0_MBC,
+					     SUN6I_SPI0_MTC,
+					     SUN6I_SPI0_BCC);
+		} else {
+			sunxi_spi0_read_data(buf8, addr, chunk_len,
+					     SUN4I_SPI0_CTL,
+					     SUN4I_CTL_XCH,
+					     SUN4I_SPI0_FIFO_STA,
+					     SUN4I_SPI0_TX,
+					     SUN4I_SPI0_RX,
+					     SUN4I_SPI0_BC,
+					     SUN4I_SPI0_TC,
+					     0);
+		}
+
+		len  -= chunk_len;
+		buf8 += chunk_len;
+		addr += chunk_len;
+	}
+}
+
+/*****************************************************************************/
+
+int spl_spi_load_image(void)
+{
+	int err;
+	struct image_header *header;
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+
+	spi0_init();
+
+	spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
+	err = spl_parse_image_header(header);
+	if (err)
+		return err;
+
+	spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS,
+		       spl_image.size);
+
+	spi0_deinit();
+	return 0;
+}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 94275a7..6358901 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -137,6 +137,11 @@
 #define CONFIG_SPL_NAND_SUPPORT 1
 #endif
 
+#ifdef CONFIG_SPL_SPI_SUNXI
+#define CONFIG_SPL_SPI_FLASH_SUPPORT	1
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+#endif
+
 /* mmc config */
 #ifdef CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-- 
cgit v0.10.2


From 320e0570e67efbd093d7750655a758c66e9d5528 Mon Sep 17 00:00:00 2001
From: Bernhard Nortmann <bernhard.nortmann@web.de>
Date: Thu, 9 Jun 2016 07:37:35 +0200
Subject: sunxi: FEL - Add the ability to recognize and auto-import uEnv-style
 data

The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot environment.

If parse_spl_header() in the sunxi board.c encounters a non-zero
value in this header field, it will therefore call himport_r() to
merge the string (lines) passed via FEL into the default settings.
Environment vars can be changed this way even before U-Boot will
attempt to autoboot - specifically, this also allows overriding
"bootcmd".

With fel_script_addr set and a zero fel_uEnv_length, U-Boot is
safe to assume that data in .scr format (a mkimage-type script)
was passed at fel_script_addr, and will handle it using the
existing mechanism ("bootcmd_fel").

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index ec73379..5d7ab55 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -51,7 +51,14 @@ struct boot_file_head {
 		uint8_t spl_signature[4];
 	};
 	uint32_t fel_script_address;
-	uint32_t reserved1[3];
+	/*
+	 * If the fel_uEnv_length member below is set to a non-zero value,
+	 * it specifies the size (byte count) of data at fel_script_address.
+	 * At the same time this indicates that the data is in uEnv.txt
+	 * compatible format, ready to be imported via "env import -t".
+	 */
+	uint32_t fel_uEnv_length;
+	uint32_t reserved1[2];
 	uint32_t boot_media;		/* written here by the boot ROM */
 	uint32_t reserved2[5];		/* padding, align to 64 bytes */
 };
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index c8bf316..78dfda5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -573,6 +573,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
 
 #if !defined(CONFIG_SPL_BUILD)
 #include <asm/arch/spl.h>
+#include <environment.h>
 
 /*
  * Check the SPL header for the "sunxi" variant. If found: parse values
@@ -582,17 +583,29 @@ void get_board_serial(struct tag_serialnr *serialnr)
 static void parse_spl_header(const uint32_t spl_addr)
 {
 	struct boot_file_head *spl = (void *)(ulong)spl_addr;
-	if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
-		uint8_t spl_header_version = spl->spl_signature[3];
-		if (spl_header_version == SPL_HEADER_VERSION) {
-			if (spl->fel_script_address)
-				setenv_hex("fel_scriptaddr",
-					   spl->fel_script_address);
-			return;
-		}
+	if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
+		return; /* signature mismatch, no usable header */
+
+	uint8_t spl_header_version = spl->spl_signature[3];
+	if (spl_header_version != SPL_HEADER_VERSION) {
 		printf("sunxi SPL version mismatch: expected %u, got %u\n",
 		       SPL_HEADER_VERSION, spl_header_version);
+		return;
+	}
+	if (!spl->fel_script_address)
+		return;
+
+	if (spl->fel_uEnv_length != 0) {
+		/*
+		 * data is expected in uEnv.txt compatible format, so "env
+		 * import -t" the string(s) at fel_script_address right away.
+		 */
+		himport_r(&env_htab, (char *)spl->fel_script_address,
+			  spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
+		return;
 	}
+	/* otherwise assume .scr format (mkimage-type script) */
+	setenv_hex("fel_scriptaddr", spl->fel_script_address);
 }
 #endif
 
-- 
cgit v0.10.2


From 26c0c15786039fb437925c08205702169462e343 Mon Sep 17 00:00:00 2001
From: Tobias Doerffel <tobias.doerffel@ed-chemnitz.de>
Date: Fri, 8 Jul 2016 12:40:14 +0200
Subject: sunxi: mmc: increase status register polling rate for data transfers

With a recent bunch of SD3.0 cards in our A20-based board we
experienced data transfer rates of about 250 KiB/s instead of 10 MiB/s
with previous cards from the same vendor (both 4 GB/class 10). By
increasing status register polling rate from 1 kHz to 1 MHz we were
able to reach the original transfer rates again. With the old cards
we now even reach about 16 MiB/s.

Signed-off-by: Tobias Doerffel <tobias.doerffel@ed-chemnitz.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index ce2dc4a..3be9a90 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -269,18 +269,18 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 	unsigned i;
 	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 	unsigned byte_cnt = data->blocksize * data->blocks;
-	unsigned timeout_msecs = byte_cnt >> 8;
-	if (timeout_msecs < 2000)
-		timeout_msecs = 2000;
+	unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
+	if (timeout_usecs < 2000000)
+		timeout_usecs = 2000000;
 
 	/* Always read / write data through the CPU */
 	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 
 	for (i = 0; i < (byte_cnt >> 2); i++) {
 		while (readl(&mmchost->reg->status) & status_bit) {
-			if (!timeout_msecs--)
+			if (!timeout_usecs--)
 				return -1;
-			udelay(1000);
+			udelay(1);
 		}
 
 		if (reading)
-- 
cgit v0.10.2


From a29710c525ff43c3031b879e2beac306a09c6944 Mon Sep 17 00:00:00 2001
From: Amit Singh Tomar <amittomer25@gmail.com>
Date: Wed, 6 Jul 2016 17:59:44 +0530
Subject: net: Add EMAC driver for H3/A83T/A64 SoCs.

This patch add EMAC driver support for H3/A83T/A64 SoCs.
Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY).

BIG Thanks to Andre for providing some of the DT code.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
index 549dc15..389c609 100644
--- a/arch/arm/dts/sun50i-a64-pine64-plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -57,3 +57,16 @@
 		reg = <0x40000000 0x40000000>;
 	};
 };
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii";
+	phy = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+	reg = <1>;
+	};
+};
+
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 1bd436f..7d0dc76 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -506,6 +506,25 @@
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+
+			rmii_pins: rmii_pins {
+				allwinner,pins = "PD10", "PD11", "PD13", "PD14",
+						 "PD17", "PD18", "PD19", "PD20",
+						 "PD22", "PD23";
+				allwinner,function = "emac";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			rgmii_pins: rgmii_pins {
+				allwinner,pins = "PD8", "PD9", "PD10", "PD11",
+						 "PD12", "PD13", "PD15",
+						 "PD16", "PD17", "PD18", "PD19",
+						 "PD20", "PD21", "PD22", "PD23";
+				allwinner,function = "emac";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
 		ahb_rst: reset@1c202c0 {
@@ -620,5 +639,19 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
+
+		emac: ethernet@01c30000 {
+			compatible = "allwinner,sun50i-a64-emac";
+			reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
+			reg-names = "emac", "syscon";
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ahb_rst 17>;
+			reset-names = "ahb";
+			clocks = <&bus_gates 17>;
+			clock-names = "ahb";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
index f93f5d1..d3f8f55 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
@@ -184,3 +184,16 @@
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	status = "okay";
 };
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii";
+	phy = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
index 30ccca0..0a74a91 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
@@ -173,3 +173,15 @@
 	/* USB VBUS is always on */
 	status = "okay";
 };
+
+&emac {
+	phy = <&phy1>;
+	phy-mode = "mii";
+	allwinner,use-internal-phy;
+	allwinner,leds-active-low;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index c2f63c5..6ca5e34 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -501,6 +501,17 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			rgmii_pins: rgmii_pins {
+				allwinner,pins = "PD0", "PD1", "PD2", "PD3",
+						 "PD4", "PD5", "PD7",
+						 "PD8", "PD9", "PD10",
+						 "PD12", "PD13", "PD15",
+						 "PD16", "PD17";
+				allwinner,function = "emac";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			uart0_pins_a: uart0@0 {
 				allwinner,pins = "PA4", "PA5";
 				allwinner,function = "uart0";
@@ -616,6 +627,20 @@
 			status = "disabled";
 		};
 
+		emac: ethernet@01c30000 {
+			compatible = "allwinner,sun8i-h3-emac";
+			reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
+			reg-names = "emac", "syscon";
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ahb_rst 17>, <&ahb_rst 66>;
+			reset-names = "ahb", "ephy";
+			clocks = <&bus_gates 17>, <&bus_gates 128>;
+			clock-names = "ahb", "ephy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@01c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index c2e72f5..d4dff1e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -40,7 +40,8 @@ struct sunxi_ccm_reg {
 	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
 	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
 	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
-	u32 reserved9[4];
+	u32 bus_gate4;          /* 0x70 gate 4 module clock gating */
+	u8 res3[0xc];
 	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
 	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
 	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
@@ -387,6 +388,7 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_LCD0		4
 
 /* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_EPHY		2
 #define AHB_RESET_OFFSET_LVDS		0
 
 /* apb2 reset */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index c5e9d88..cd009d7 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -87,7 +87,8 @@
 #define SUNXI_KEYPAD_BASE		0x01c23000
 #define SUNXI_TZPC_BASE			0x01c23400
 
-#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \
+defined(CONFIG_MACH_SUN50I)
 /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
 #define SUNXI_SID_BASE			0x01c14200
 #else
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7eaa795..294f7ab 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -13,3 +13,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SUN8I_EMAC=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0bf79bf..5c97de1 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,3 +10,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_SUN8I_EMAC=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index c1cb689..88d8e83 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -152,6 +152,15 @@ config RTL8169
 	  This driver supports Realtek 8169 series gigabit ethernet family of
 	  PCI/PCIe chipsets/adapters.
 
+config SUN8I_EMAC
+        bool "Allwinner Sun8i Ethernet MAC support"
+        depends on DM_ETH
+        select PHYLIB
+        help
+          This driver supports the  Allwinner based SUN8I/SUN50I Ethernet MAC.
+	  It can be found in H3/A64/A83T based SoCs and compatible with both
+	  External and Internal PHY's.
+
 config XILINX_AXIEMAC
 	depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
 	select PHYLIB
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5702592..a448526 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
 obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
+obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
 obj-$(CONFIG_ENC28J60) += enc28j60.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
 obj-$(CONFIG_ETHOC) += ethoc.o
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
new file mode 100644
index 0000000..4bed50d
--- /dev/null
+++ b/drivers/net/sun8i_emac.c
@@ -0,0 +1,789 @@
+/*
+ * (C) Copyright 2016
+ * Author: Amit Singh Tomar, amittomer25@gmail.com
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ * Ethernet driver for H3/A64/A83T based SoC's
+ *
+ * It is derived from the work done by
+ * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
+ *
+*/
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+
+#define SCTL_EMAC_TX_CLK_SRC_MII	BIT(0)
+#define SCTL_EMAC_EPIT_MII		BIT(2)
+#define SCTL_EMAC_CLK_SEL		BIT(18) /* 25 Mhz */
+
+#define MDIO_CMD_MII_BUSY		BIT(0)
+#define MDIO_CMD_MII_WRITE		BIT(1)
+
+#define MDIO_CMD_MII_PHY_REG_ADDR_MASK	0x000001f0
+#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT	4
+#define MDIO_CMD_MII_PHY_ADDR_MASK	0x0001f000
+#define MDIO_CMD_MII_PHY_ADDR_SHIFT	12
+
+#define CONFIG_TX_DESCR_NUM	32
+#define CONFIG_RX_DESCR_NUM	32
+#define CONFIG_ETH_BUFSIZE	2024
+
+#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+#define H3_EPHY_DEFAULT_VALUE	0x58000
+#define H3_EPHY_DEFAULT_MASK	GENMASK(31, 15)
+#define H3_EPHY_ADDR_SHIFT	20
+#define REG_PHY_ADDR_MASK	GENMASK(4, 0)
+#define H3_EPHY_LED_POL		BIT(17)	/* 1: active low, 0: active high */
+#define H3_EPHY_SHUTDOWN	BIT(16)	/* 1: shutdown, 0: power up */
+#define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
+
+#define SC_RMII_EN		BIT(13)
+#define SC_EPIT			BIT(2) /* 1: RGMII, 0: MII */
+#define SC_ETCS_MASK		GENMASK(1, 0)
+#define SC_ETCS_EXT_GMII	0x1
+#define SC_ETCS_INT_GMII	0x2
+
+#define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
+
+#define AHB_GATE_OFFSET_EPHY	0
+
+#if defined(CONFIG_MACH_SUN8I_H3)
+#define SUN8I_GPD8_GMAC		2
+#else
+#define SUN8I_GPD8_GMAC		4
+#endif
+
+/* H3/A64 EMAC Register's offset */
+#define EMAC_CTL0		0x00
+#define EMAC_CTL1		0x04
+#define EMAC_INT_STA		0x08
+#define EMAC_INT_EN		0x0c
+#define EMAC_TX_CTL0		0x10
+#define EMAC_TX_CTL1		0x14
+#define EMAC_TX_FLOW_CTL	0x1c
+#define EMAC_TX_DMA_DESC	0x20
+#define EMAC_RX_CTL0		0x24
+#define EMAC_RX_CTL1		0x28
+#define EMAC_RX_DMA_DESC	0x34
+#define EMAC_MII_CMD		0x48
+#define EMAC_MII_DATA		0x4c
+#define EMAC_ADDR0_HIGH		0x50
+#define EMAC_ADDR0_LOW		0x54
+#define EMAC_TX_DMA_STA		0xb0
+#define EMAC_TX_CUR_DESC	0xb4
+#define EMAC_TX_CUR_BUF		0xb8
+#define EMAC_RX_DMA_STA		0xc0
+#define EMAC_RX_CUR_DESC	0xc4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum emac_variant {
+	A83T_EMAC = 1,
+	H3_EMAC,
+	A64_EMAC,
+};
+
+struct emac_dma_desc {
+	u32 status;
+	u32 st;
+	u32 buf_addr;
+	u32 next;
+} __aligned(ARCH_DMA_MINALIGN);
+
+struct emac_eth_dev {
+	struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
+	struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
+	char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+	char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+
+	u32 interface;
+	u32 phyaddr;
+	u32 link;
+	u32 speed;
+	u32 duplex;
+	u32 phy_configured;
+	u32 tx_currdescnum;
+	u32 rx_currdescnum;
+	u32 addr;
+	u32 tx_slot;
+	bool use_internal_phy;
+
+	enum emac_variant variant;
+	void *mac_reg;
+	phys_addr_t sysctl_reg;
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+};
+
+static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+	struct emac_eth_dev *priv = bus->priv;
+	ulong start;
+	u32 miiaddr = 0;
+	int timeout = CONFIG_MDIO_TIMEOUT;
+
+	miiaddr &= ~MDIO_CMD_MII_WRITE;
+	miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
+	miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
+		MDIO_CMD_MII_PHY_REG_ADDR_MASK;
+
+	miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
+
+	miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
+		MDIO_CMD_MII_PHY_ADDR_MASK;
+
+	miiaddr |= MDIO_CMD_MII_BUSY;
+
+	writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
+
+	start = get_timer(0);
+	while (get_timer(start) < timeout) {
+		if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
+			return readl(priv->mac_reg + EMAC_MII_DATA);
+		udelay(10);
+	};
+
+	return -1;
+}
+
+static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+			    u16 val)
+{
+	struct emac_eth_dev *priv = bus->priv;
+	ulong start;
+	u32 miiaddr = 0;
+	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+
+	miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
+	miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
+		MDIO_CMD_MII_PHY_REG_ADDR_MASK;
+
+	miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
+	miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
+		MDIO_CMD_MII_PHY_ADDR_MASK;
+
+	miiaddr |= MDIO_CMD_MII_WRITE;
+	miiaddr |= MDIO_CMD_MII_BUSY;
+
+	writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
+	writel(val, priv->mac_reg + EMAC_MII_DATA);
+
+	start = get_timer(0);
+	while (get_timer(start) < timeout) {
+		if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
+					MDIO_CMD_MII_BUSY)) {
+			ret = 0;
+			break;
+		}
+		udelay(10);
+	};
+
+	return ret;
+}
+
+static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
+{
+	u32 macid_lo, macid_hi;
+
+	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
+		(mac_id[3] << 24);
+	macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+	writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
+	writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
+
+	return 0;
+}
+
+static void sun8i_adjust_link(struct emac_eth_dev *priv,
+			      struct phy_device *phydev)
+{
+	u32 v;
+
+	v = readl(priv->mac_reg + EMAC_CTL0);
+
+	if (phydev->duplex)
+		v |= BIT(0);
+	else
+		v &= ~BIT(0);
+
+	v &= ~0x0C;
+
+	switch (phydev->speed) {
+	case 1000:
+		break;
+	case 100:
+		v |= BIT(2);
+		v |= BIT(3);
+		break;
+	case 10:
+		v |= BIT(3);
+		break;
+	}
+	writel(v, priv->mac_reg + EMAC_CTL0);
+}
+
+static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
+{
+	if (priv->use_internal_phy) {
+		/* H3 based SoC's that has an Internal 100MBit PHY
+		 * needs to be configured and powered up before use
+		*/
+		*reg &= ~H3_EPHY_DEFAULT_MASK;
+		*reg |=  H3_EPHY_DEFAULT_VALUE;
+		*reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
+		*reg &= ~H3_EPHY_SHUTDOWN;
+		*reg |= H3_EPHY_SELECT;
+	} else
+		/* This is to select External Gigabit PHY on
+		 * the boards with H3 SoC.
+		*/
+		*reg &= ~H3_EPHY_SELECT;
+
+	return 0;
+}
+
+static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
+{
+	int ret;
+	u32 reg;
+
+	reg = readl(priv->sysctl_reg);
+
+	if (priv->variant == H3_EMAC) {
+		ret = sun8i_emac_set_syscon_ephy(priv, &reg);
+		if (ret)
+			return ret;
+	}
+
+	reg &= ~(SC_ETCS_MASK | SC_EPIT);
+	if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
+		reg &= ~SC_RMII_EN;
+
+	switch (priv->interface) {
+	case PHY_INTERFACE_MODE_MII:
+		/* default */
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+		reg |= SC_EPIT | SC_ETCS_INT_GMII;
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		if (priv->variant == H3_EMAC ||
+		    priv->variant == A64_EMAC) {
+			reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
+		break;
+		}
+		/* RMII not supported on A83T */
+	default:
+		debug("%s: Invalid PHY interface\n", __func__);
+		return -EINVAL;
+	}
+
+	writel(reg, priv->sysctl_reg);
+
+	return 0;
+}
+
+static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
+{
+	struct phy_device *phydev;
+
+	phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
+	if (!phydev)
+		return -ENODEV;
+
+	phy_connect_dev(phydev, dev);
+
+	priv->phydev = phydev;
+	phy_config(priv->phydev);
+
+	return 0;
+}
+
+static void rx_descs_init(struct emac_eth_dev *priv)
+{
+	struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
+	char *rxbuffs = &priv->rxbuffer[0];
+	struct emac_dma_desc *desc_p;
+	u32 idx;
+
+	/* flush Rx buffers */
+	flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
+			RX_TOTAL_BUFSIZE);
+
+	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+		desc_p = &desc_table_p[idx];
+		desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
+			;
+		desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
+		desc_p->st |= CONFIG_ETH_BUFSIZE;
+		desc_p->status = BIT(31);
+	}
+
+	/* Correcting the last pointer of the chain */
+	desc_p->next = (uintptr_t)&desc_table_p[0];
+
+	flush_dcache_range((uintptr_t)priv->rx_chain,
+			   (uintptr_t)priv->rx_chain +
+			sizeof(priv->rx_chain));
+
+	writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
+	priv->rx_currdescnum = 0;
+}
+
+static void tx_descs_init(struct emac_eth_dev *priv)
+{
+	struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
+	char *txbuffs = &priv->txbuffer[0];
+	struct emac_dma_desc *desc_p;
+	u32 idx;
+
+	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+		desc_p = &desc_table_p[idx];
+		desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
+			;
+		desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
+		desc_p->status = (1 << 31);
+		desc_p->st = 0;
+	}
+
+	/* Correcting the last pointer of the chain */
+	desc_p->next =  (uintptr_t)&desc_table_p[0];
+
+	/* Flush all Tx buffer descriptors */
+	flush_dcache_range((uintptr_t)priv->tx_chain,
+			   (uintptr_t)priv->tx_chain +
+			sizeof(priv->tx_chain));
+
+	writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
+	priv->tx_currdescnum = 0;
+}
+
+static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
+{
+	u32 reg, v;
+	int timeout = 100;
+
+	reg = readl((priv->mac_reg + EMAC_CTL1));
+
+	if (!(reg & 0x1)) {
+		/* Soft reset MAC */
+		setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
+		do {
+			reg = readl(priv->mac_reg + EMAC_CTL1);
+		} while ((reg & 0x01) != 0 &&  (--timeout));
+		if (!timeout) {
+			printf("%s: Timeout\n", __func__);
+			return -1;
+		}
+	}
+
+	/* Rewrite mac address after reset */
+	_sun8i_write_hwaddr(priv, enetaddr);
+
+	v = readl(priv->mac_reg + EMAC_TX_CTL1);
+	/* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
+	v |= BIT(1);
+	writel(v, priv->mac_reg + EMAC_TX_CTL1);
+
+	v = readl(priv->mac_reg + EMAC_RX_CTL1);
+	/* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
+	 * complete frame has been written to RX DMA FIFO
+	 */
+	v |= BIT(1);
+	writel(v, priv->mac_reg + EMAC_RX_CTL1);
+
+	/* DMA */
+	writel(8 << 24, priv->mac_reg + EMAC_CTL1);
+
+	/* Initialize rx/tx descriptors */
+	rx_descs_init(priv);
+	tx_descs_init(priv);
+
+	/* PHY Start Up */
+	genphy_parse_link(priv->phydev);
+
+	sun8i_adjust_link(priv, priv->phydev);
+
+	/* Start RX DMA */
+	v = readl(priv->mac_reg + EMAC_RX_CTL1);
+	v |= BIT(30);
+	writel(v, priv->mac_reg + EMAC_RX_CTL1);
+	/* Start TX DMA */
+	v = readl(priv->mac_reg + EMAC_TX_CTL1);
+	v |= BIT(30);
+	writel(v, priv->mac_reg + EMAC_TX_CTL1);
+
+	/* Enable RX/TX */
+	setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
+	setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
+
+	return 0;
+}
+
+static int parse_phy_pins(struct udevice *dev)
+{
+	int offset;
+	const char *pin_name;
+	int drive, pull, i;
+
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+				       "pinctrl-0");
+	if (offset < 0) {
+		printf("WARNING: emac: cannot find pinctrl-0 node\n");
+		return offset;
+	}
+
+	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
+					     "allwinner,drive", 4);
+	pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
+					    "allwinner,pull", 0);
+	for (i = 0; ; i++) {
+		int pin;
+
+		if (fdt_get_string_index(gd->fdt_blob, offset,
+					 "allwinner,pins", i, &pin_name))
+			break;
+		if (pin_name[0] != 'P')
+			continue;
+		pin = (pin_name[1] - 'A') << 5;
+		if (pin >= 26 << 5)
+			continue;
+		pin += simple_strtol(&pin_name[2], NULL, 10);
+
+		sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
+		sunxi_gpio_set_drv(pin, drive);
+		sunxi_gpio_set_pull(pin, pull);
+	}
+
+	if (!i) {
+		printf("WARNING: emac: cannot find allwinner,pins property\n");
+		return -2;
+	}
+
+	return 0;
+}
+
+static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
+{
+	u32 status, desc_num = priv->rx_currdescnum;
+	struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
+	int length = -EAGAIN;
+	int good_packet = 1;
+	uintptr_t desc_start = (uintptr_t)desc_p;
+	uintptr_t desc_end = desc_start +
+		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+
+	ulong data_start = (uintptr_t)desc_p->buf_addr;
+	ulong data_end;
+
+	/* Invalidate entire buffer descriptor */
+	invalidate_dcache_range(desc_start, desc_end);
+
+	status = desc_p->status;
+
+	/* Check for DMA own bit */
+	if (!(status & BIT(31))) {
+		length = (desc_p->status >> 16) & 0x3FFF;
+
+		if (length < 0x40) {
+			good_packet = 0;
+			debug("RX: Bad Packet (runt)\n");
+		}
+
+		data_end = data_start + length;
+		/* Invalidate received data */
+		invalidate_dcache_range(rounddown(data_start,
+						  ARCH_DMA_MINALIGN),
+					roundup(data_end,
+						ARCH_DMA_MINALIGN));
+		if (good_packet) {
+			if (length > CONFIG_ETH_BUFSIZE) {
+				printf("Received packet is too big (len=%d)\n",
+				       length);
+				return -EMSGSIZE;
+			}
+			*packetp = (uchar *)(ulong)desc_p->buf_addr;
+			return length;
+		}
+	}
+
+	return length;
+}
+
+static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
+				int len)
+{
+	u32 v, desc_num = priv->tx_currdescnum;
+	struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
+	uintptr_t desc_start = (uintptr_t)desc_p;
+	uintptr_t desc_end = desc_start +
+		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+
+	uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
+	uintptr_t data_end = data_start +
+		roundup(len, ARCH_DMA_MINALIGN);
+
+	/* Invalidate entire buffer descriptor */
+	invalidate_dcache_range(desc_start, desc_end);
+
+	desc_p->st = len;
+	/* Mandatory undocumented bit */
+	desc_p->st |= BIT(24);
+
+	memcpy((void *)data_start, packet, len);
+
+	/* Flush data to be sent */
+	flush_dcache_range(data_start, data_end);
+
+	/* frame end */
+	desc_p->st |= BIT(30);
+	desc_p->st |= BIT(31);
+
+	/*frame begin */
+	desc_p->st |= BIT(29);
+	desc_p->status = BIT(31);
+
+	/*Descriptors st and status field has changed, so FLUSH it */
+	flush_dcache_range(desc_start, desc_end);
+
+	/* Move to next Descriptor and wrap around */
+	if (++desc_num >= CONFIG_TX_DESCR_NUM)
+		desc_num = 0;
+	priv->tx_currdescnum = desc_num;
+
+	/* Start the DMA */
+	v = readl(priv->mac_reg + EMAC_TX_CTL1);
+	v |= BIT(31);/* mandatory */
+	v |= BIT(30);/* mandatory */
+	writel(v, priv->mac_reg + EMAC_TX_CTL1);
+
+	return 0;
+}
+
+static int sun8i_eth_write_hwaddr(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+
+	return _sun8i_write_hwaddr(priv, pdata->enetaddr);
+}
+
+static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+{
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (priv->use_internal_phy) {
+		/* Set clock gating for ephy */
+		setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
+
+		/* Set Tx clock source as MII with rate 25 MZ */
+		setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
+				SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
+		/* Deassert EPHY */
+		setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
+	}
+
+	/* Set clock gating for emac */
+	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
+
+	/* Set EMAC clock */
+	setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
+
+	/* De-assert EMAC */
+	setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
+}
+
+static int sun8i_mdio_init(const char *name, struct  emac_eth_dev *priv)
+{
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		debug("Failed to allocate MDIO bus\n");
+		return -ENOMEM;
+	}
+
+	bus->read = sun8i_mdio_read;
+	bus->write = sun8i_mdio_write;
+	snprintf(bus->name, sizeof(bus->name), name);
+	bus->priv = (void *)priv;
+
+	return  mdio_register(bus);
+}
+
+static int sun8i_emac_eth_start(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+
+	return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
+}
+
+static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
+{
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+
+	return _sun8i_emac_eth_send(priv, packet, length);
+}
+
+static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+
+	return _sun8i_eth_recv(priv, packetp);
+}
+
+static int _sun8i_free_pkt(struct emac_eth_dev *priv)
+{
+	u32 desc_num = priv->rx_currdescnum;
+	struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
+	uintptr_t desc_start = (uintptr_t)desc_p;
+	uintptr_t desc_end = desc_start +
+		roundup(sizeof(u32), ARCH_DMA_MINALIGN);
+
+	/* Make the current descriptor valid again */
+	desc_p->status |= BIT(31);
+
+	/* Flush Status field of descriptor */
+	flush_dcache_range(desc_start, desc_end);
+
+	/* Move to next desc and wrap-around condition. */
+	if (++desc_num >= CONFIG_RX_DESCR_NUM)
+		desc_num = 0;
+	priv->rx_currdescnum = desc_num;
+
+	return 0;
+}
+
+static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
+			      int length)
+{
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+
+	return _sun8i_free_pkt(priv);
+}
+
+static void sun8i_emac_eth_stop(struct udevice *dev)
+{
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+
+	/* Stop Rx/Tx transmitter */
+	clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
+	clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
+
+	/* Stop TX DMA */
+	clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
+
+	phy_shutdown(priv->phydev);
+}
+
+static int sun8i_emac_eth_probe(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+
+	priv->mac_reg = (void *)pdata->iobase;
+
+	sun8i_emac_board_setup(priv);
+
+	sun8i_mdio_init(dev->name, priv);
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	sun8i_emac_set_syscon(priv);
+
+	return sun8i_phy_init(priv, dev);
+}
+
+static const struct eth_ops sun8i_emac_eth_ops = {
+	.start                  = sun8i_emac_eth_start,
+	.write_hwaddr           = sun8i_eth_write_hwaddr,
+	.send                   = sun8i_emac_eth_send,
+	.recv                   = sun8i_emac_eth_recv,
+	.free_pkt               = sun8i_eth_free_pkt,
+	.stop                   = sun8i_emac_eth_stop,
+};
+
+static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct emac_eth_dev *priv = dev_get_priv(dev);
+	const char *phy_mode;
+	int offset = 0;
+
+	pdata->iobase = dev_get_addr_name(dev, "emac");
+	priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
+
+	pdata->phy_interface = -1;
+	priv->phyaddr = -1;
+	priv->use_internal_phy = false;
+
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+				       "phy");
+	if (offset > 0)
+		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
+					       -1);
+
+	phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+
+	if (phy_mode)
+		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+	printf("phy interface%d\n", pdata->phy_interface);
+
+	if (pdata->phy_interface == -1) {
+		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+		return -EINVAL;
+	}
+
+	priv->variant = dev_get_driver_data(dev);
+
+	if (!priv->variant) {
+		printf("%s: Missing variant '%s'\n", __func__,
+		       (char *)priv->variant);
+		return -EINVAL;
+	}
+
+	if (priv->variant == H3_EMAC) {
+		if (fdt_getprop(gd->fdt_blob, dev->of_offset,
+				"allwinner,use-internal-phy", NULL))
+			priv->use_internal_phy = true;
+	}
+
+	priv->interface = pdata->phy_interface;
+
+	if (!priv->use_internal_phy)
+		parse_phy_pins(dev);
+
+	return 0;
+}
+
+static const struct udevice_id sun8i_emac_eth_ids[] = {
+	{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
+	{.compatible = "allwinner,sun50i-a64-emac",
+		.data = (uintptr_t)A64_EMAC },
+	{.compatible = "allwinner,sun8i-a83t-emac",
+		.data = (uintptr_t)A83T_EMAC },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_sun8i_emac) = {
+	.name   = "eth_sun8i_emac",
+	.id     = UCLASS_ETH,
+	.of_match = sun8i_emac_eth_ids,
+	.ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
+	.probe  = sun8i_emac_eth_probe,
+	.ops    = &sun8i_emac_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
cgit v0.10.2


From f221961e963fcfa5ceab6455c24d6532877ca923 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 26 Jun 2016 13:34:42 +0200
Subject: sunxi: Add support for multiple ethadrr-esses

Currently we fill ethaddr with a fixed unique address based on the SoCs
serial (from the sid) to make sure that boards which use the integrated
emac / gmac get a fixed mac rather then a random one.

On some boards the wifi does not come with a fixed mac either, so we need
to also set eth1addr.

This commit changes the ethaddr setting code to check for ethernet%d
aliases (as fdt_fixup_ethernet does) and set an ethaddr variable for
all present aliases.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 78dfda5..5e48756 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -26,6 +26,7 @@
 #endif
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <libfdt.h>
 #include <nand.h>
 #include <net.h>
 #include <sy8106a.h>
@@ -609,36 +610,42 @@ static void parse_spl_header(const uint32_t spl_addr)
 }
 #endif
 
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
+/*
+ * Note this function gets called multiple times.
+ * It must not make any changes to env variables which already exist.
+ */
+static void setup_environment(const void *fdt)
 {
 	char serial_string[17] = { 0 };
 	unsigned int sid[4];
 	uint8_t mac_addr[6];
-	int ret;
-
-#if !defined(CONFIG_SPL_BUILD)
-	setenv("fel_booted", NULL);
-	setenv("fel_scriptaddr", NULL);
-	/* determine if we are running in FEL mode */
-	if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
-		setenv("fel_booted", "1");
-		parse_spl_header(SPL_ADDR);
-	}
-#endif
+	char ethaddr[16];
+	int i, ret;
 
 	ret = sunxi_get_sid(sid);
 	if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
-		if (!getenv("ethaddr")) {
+		for (i = 0; i < 4; i++) {
+			sprintf(ethaddr, "ethernet%d", i);
+			if (!fdt_get_alias(fdt, ethaddr))
+				continue;
+
+			if (i == 0)
+				strcpy(ethaddr, "ethaddr");
+			else
+				sprintf(ethaddr, "eth%daddr", i);
+
+			if (getenv(ethaddr))
+				continue;
+
 			/* Non OUI / registered MAC address */
-			mac_addr[0] = 0x02;
+			mac_addr[0] = (i << 4) | 0x02;
 			mac_addr[1] = (sid[0] >>  0) & 0xff;
 			mac_addr[2] = (sid[3] >> 24) & 0xff;
 			mac_addr[3] = (sid[3] >> 16) & 0xff;
 			mac_addr[4] = (sid[3] >>  8) & 0xff;
 			mac_addr[5] = (sid[3] >>  0) & 0xff;
 
-			eth_setenv_enetaddr("ethaddr", mac_addr);
+			eth_setenv_enetaddr(ethaddr, mac_addr);
 		}
 
 		if (!getenv("serial#")) {
@@ -648,6 +655,24 @@ int misc_init_r(void)
 			setenv("serial#", serial_string);
 		}
 	}
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	__maybe_unused int ret;
+
+#if !defined(CONFIG_SPL_BUILD)
+	setenv("fel_booted", NULL);
+	setenv("fel_scriptaddr", NULL);
+	/* determine if we are running in FEL mode */
+	if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
+		setenv("fel_booted", "1");
+		parse_spl_header(SPL_ADDR);
+	}
+#endif
+
+	setup_environment(gd->fdt_blob);
 
 #ifndef CONFIG_MACH_SUN9I
 	ret = sunxi_usb_phy_probe();
@@ -664,6 +689,12 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	int __maybe_unused r;
 
+	/*
+	 * Call setup_environment again in case the boot fdt has
+	 * ethernet aliases the u-boot copy does not have.
+	 */
+	setup_environment(blob);
+
 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
 	r = sunxi_simplefb_setup(blob);
 	if (r)
-- 
cgit v0.10.2


From 4a8c7c1f45a25687e08ff98ab27ba664c8fd7b74 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Jul 2016 09:56:56 +0200
Subject: sunxi: Remove some unnecessary #ifdefs

We always define CONFIG_MISC_INIT_R on sunxi and misc_init_r is never
called in the spl, so the linker will optimize it and parse_spl_header(),
of which it is the only caller, away.

On the tests I've done (Orange Pi PC build) the SPL actually becomes
8 bytes smaller with this patch.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 5e48756..320958a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -20,12 +20,14 @@
 #include <asm/arch/dram.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/spl.h>
 #include <asm/arch/usb_phy.h>
 #ifndef CONFIG_ARM64
 #include <asm/armv7.h>
 #endif
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <environment.h>
 #include <libfdt.h>
 #include <nand.h>
 #include <net.h>
@@ -572,10 +574,6 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif
 
-#if !defined(CONFIG_SPL_BUILD)
-#include <asm/arch/spl.h>
-#include <environment.h>
-
 /*
  * Check the SPL header for the "sunxi" variant. If found: parse values
  * that might have been passed by the loader ("fel" utility), and update
@@ -608,7 +606,6 @@ static void parse_spl_header(const uint32_t spl_addr)
 	/* otherwise assume .scr format (mkimage-type script) */
 	setenv_hex("fel_scriptaddr", spl->fel_script_address);
 }
-#endif
 
 /*
  * Note this function gets called multiple times.
@@ -657,12 +654,10 @@ static void setup_environment(const void *fdt)
 	}
 }
 
-#ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
 	__maybe_unused int ret;
 
-#if !defined(CONFIG_SPL_BUILD)
 	setenv("fel_booted", NULL);
 	setenv("fel_scriptaddr", NULL);
 	/* determine if we are running in FEL mode */
@@ -670,7 +665,6 @@ int misc_init_r(void)
 		setenv("fel_booted", "1");
 		parse_spl_header(SPL_ADDR);
 	}
-#endif
 
 	setup_environment(gd->fdt_blob);
 
@@ -683,7 +677,6 @@ int misc_init_r(void)
 
 	return 0;
 }
-#endif
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-- 
cgit v0.10.2


From ef36d9ae1646e5aee7c1425ee507d275699a072e Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Jul 2016 15:31:47 +0200
Subject: sunxi: Use BROM stored boot_media value to determine our boot-source

Now that we know that the BROM stores a value indicating the boot-source
at the beginning of SRAM, use that instead of trying to recreate the
BROM's boot probing.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 3da360b..cb52e64 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -127,5 +127,4 @@ struct sunxi_mmc {
 #define SUNXI_MMC_COMMON_RESET			(1 << 18)
 
 struct mmc *sunxi_mmc_init(int sdc_no);
-int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc);
 #endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 3f5116b..06a1986 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -203,7 +203,8 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 u32 spl_boot_device(void)
 {
-	__maybe_unused struct mmc *mmc0, *mmc1;
+	int boot_source;
+
 	/*
 	 * When booting from the SD card or NAND memory, the "eGON.BT0"
 	 * signature is expected to be found in memory at the address 0x0004
@@ -223,32 +224,19 @@ u32 spl_boot_device(void)
 	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
 		return BOOT_DEVICE_BOARD;
 
-#ifdef CONFIG_SPL_SPI_SUNXI
-	if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_SPI)
-		return BOOT_DEVICE_SPI;
-#endif
-
-	/* The BROM will try to boot from mmc0 first, so try that first. */
-#ifdef CONFIG_MMC
-	mmc_initialize(gd->bd);
-	mmc0 = find_mmc_device(0);
-	if (sunxi_mmc_has_egon_boot_signature(mmc0))
+	boot_source = readb(SPL_ADDR + 0x28);
+	switch (boot_source) {
+	case SUNXI_BOOTED_FROM_MMC0:
 		return BOOT_DEVICE_MMC1;
-#endif
-
-	/* Fallback to booting NAND if enabled. */
-	if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
+	case SUNXI_BOOTED_FROM_NAND:
 		return BOOT_DEVICE_NAND;
-
-#ifdef CONFIG_MMC
-	if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
-		mmc1 = find_mmc_device(1);
-		if (sunxi_mmc_has_egon_boot_signature(mmc1))
-			return BOOT_DEVICE_MMC2;
+	case SUNXI_BOOTED_FROM_MMC2:
+		return BOOT_DEVICE_MMC2;
+	case SUNXI_BOOTED_FROM_SPI:
+		return BOOT_DEVICE_SPI;
 	}
-#endif
 
-	panic("Could not determine boot source\n");
+	panic("Unknown boot source %d\n", boot_source);
 	return -1;		/* Never reached */
 }
 
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 320958a..f6e28b0 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -369,8 +369,7 @@ int board_mmc_init(bd_t *bis)
 	 * are searched there first. Note we only do this for u-boot proper,
 	 * not for the SPL, see spl_boot_device().
 	 */
-	if (!sunxi_mmc_has_egon_boot_signature(mmc0) &&
-	    sunxi_mmc_has_egon_boot_signature(mmc1)) {
+	if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
 		/* Booting from emmc / mmc2, swap */
 		mmc0->block_dev.devnum = 1;
 		mmc1->block_dev.devnum = 0;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 3be9a90..5d8abdc 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -445,23 +445,6 @@ static int sunxi_mmc_getcd(struct mmc *mmc)
 	return !gpio_get_value(cd_pin);
 }
 
-int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc)
-{
-	char *buf = malloc(512);
-	int valid_signature = 0;
-
-	if (buf == NULL)
-		panic("Failed to allocate memory\n");
-
-	if (mmc_getcd(mmc) && mmc_init(mmc) == 0 &&
-	    mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 &&
-	    strncmp(&buf[4], "eGON.BT0", 8) == 0)
-		valid_signature = 1;
-
-	free(buf);
-	return valid_signature;
-}
-
 static const struct mmc_ops sunxi_mmc_ops = {
 	.send_cmd	= sunxi_mmc_send_cmd,
 	.set_ios	= sunxi_mmc_set_ios,
-- 
cgit v0.10.2


From 74fcc927f65d782e4bab769a85acaa553acfe389 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Jul 2016 15:15:12 +0200
Subject: sunxi: orangepi_pc: Add support for eMMC found on the Orange Pi PC
 Plus

The Plus variant of the Orange Pi PC has an eMMC, add support for this.

Note we are using the same u-boot defconfig / dts for both the regular
Orange Pi PC as well as the Orange Pi PC Plus.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 294f7ab..43ec927 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -4,6 +4,8 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-- 
cgit v0.10.2


From fa8a485d06188e38abc9c46fbd1be916fe16fb7a Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Jul 2016 17:31:14 +0200
Subject: sunxi: Sync sun8i-h3-orangepi-plus.dts with upstream

This enables extra USB controllers which enable use of the 3rd USB
port on the new Orange Pi Plus 2E variant.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
index 900ec4f..28f74f6 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts
@@ -40,26 +40,13 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/dts-v1/;
-#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+/* The Orange Pi Plus is an extended version of the Orange Pi 2 */
+#include "sun8i-h3-orangepi-2.dts"
 
 / {
-	model = "Xunlong Orange Pi Plus";
+	model = "Xunlong Orange Pi Plus / Plus 2 / Plus 2E";
 	compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
 
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	reg_usb3_vbus: usb3-vbus {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -71,75 +58,42 @@
 		enable-active-high;
 		gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
 	};
+};
 
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&leds_opc>;
-
-		status_led {
-			label = "status:red:user";
-			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	r_leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&leds_r_opc>;
-
-		tx {
-			label = "pwr:green:user";
-			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-	};
-
-	r_gpio_keys {
-		compatible = "gpio-keys";
-		input-name = "sw4";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&sw_r_opc>;
+&ehci2 {
+	status = "okay";
+};
 
-		sw4@0 {
-			label = "sw4";
-			linux,code = <BTN_0>;
-			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-		};
-	};
+&ehci3 {
+	status = "okay";
 };
 
-&pio {
-	leds_opc: led_pins@0 {
-		allwinner,pins = "PA15";
-		allwinner,function = "gpio_out";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-	};
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
 };
 
-&r_pio {
-	leds_r_opc: led_pins@0 {
-		allwinner,pins = "PL10";
-		allwinner,function = "gpio_out";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-	};
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+	/* eMMC is missing pull-ups */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
 
-	sw_r_opc: key_pins@0 {
-		allwinner,pins = "PL03";
-		allwinner,function = "gpio_in";
-		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-	};
+&ohci1 {
+	status = "okay";
 };
 
-&ehci1 {
+&ohci2 {
 	status = "okay";
 };
 
-&ehci3 {
+&ohci3 {
 	status = "okay";
 };
 
@@ -152,33 +106,6 @@
 	};
 };
 
-&mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
-	vmmc-supply = <&reg_vcc3v3>;
-	bus-width = <4>;
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-	cd-inverted;
-	status = "okay";
-};
-
-&reg_usb1_vbus {
-	gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&usb1_vbus_pin_a {
-	allwinner,pins = "PG13";
-};
-
 &usbphy {
-	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb3_vbus-supply = <&reg_usb3_vbus>;
-	status = "okay";
 };
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index 6ca5e34..72c0920 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -541,6 +541,16 @@
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15", "PC16";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
 		ahb_rst: reset@01c202c0 {
-- 
cgit v0.10.2


From 66ab5286736e47cc4fdec9ceab4cc1b2f24ed066 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sat, 9 Jul 2016 22:20:00 +0200
Subject: sunxi: Add defconfig and dts file for the Orange Pi Lite SBC

The Orange Pi Lite SBC is a small H3 based SBC, with 512MB RAM,
micro-sd slot, HDMI out, 2 USB-A connectors, 1 micro-USB connector,
sdio attached rtl8189ftv wifi and an ir receiver.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ef573ec..acecb7c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -242,6 +242,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-sinovoip-bpi-m3.dtb
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-2.dtb \
+	sun8i-h3-orangepi-lite.dtb \
 	sun8i-h3-orangepi-one.dtb \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-plus.dtb
diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts
new file mode 100644
index 0000000..ac71749
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi Lite";
+	compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3";
+
+	aliases {
+		/* The H3 emac is not used so the wifi is ethernet0 */
+		ethernet1 = &rtl8189ftv;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+		pwr_led {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		status_led {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	r_gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sw_r_opc>;
+
+		sw4 {
+			label = "sw4";
+			linux,code = <BTN_0>;
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ehci2 {
+	status = "okay";
+};
+
+&ir {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ir_pins_a>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	/*
+	 * Explicitly define the sdio device, so that we can add an ethernet
+	 * alias for it (which e.g. makes u-boot set a mac-address).
+	 */
+	rtl8189ftv: sdio_wifi@1 {
+		reg = <1>;
+	};
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ohci2 {
+	status = "okay";
+};
+
+&pio {
+	leds_opc: led_pins@0 {
+		allwinner,pins = "PA15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	leds_r_opc: led_pins@0 {
+		allwinner,pins = "PL10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	sw_r_opc: key_pins@0 {
+		allwinner,pins = "PL3";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	/* USB VBUS is always on */
+	status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index d2dfebe..0dc84f6 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -56,6 +56,7 @@ F:	configs/ga10h_v1_1_defconfig
 F:	configs/gt90h_v4_defconfig
 F:	configs/inet86dz_defconfig
 F:	configs/orangepi_2_defconfig
+F:	configs/orangepi_lite_defconfig
 F:	configs/orangepi_one_defconfig
 F:	configs/orangepi_pc_defconfig
 F:	configs/orangepi_plus_defconfig
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
new file mode 100644
index 0000000..417e4f6
--- /dev/null
+++ b/configs/orangepi_lite_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
-- 
cgit v0.10.2


From b52813239c10d857bd262dc850232ccccdbaa69e Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:31 +0800
Subject: ARM: PSCI: Split out common stack setup code from psci_arch_init

Every platform has the same stack setup code in assembly as part of
psci_arch_init.

Move this out into a common separate function, psci_stack_setup, for
all platforms. This will allow us to move the remaining parts of
psci_arch_init into C code, or drop it entirely.

Also provide a stub no-op psci_arch_init for platforms that don't need
their own specific setup code.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..86116e1f 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -111,16 +111,6 @@ psci_cpu_off:
 1:	wfi
 	b	1b
 
-.globl	psci_arch_init
-psci_arch_init:
-	mov	r6, lr
-
-	bl	psci_get_cpu_id
-	bl	psci_get_cpu_stack_top
-	mov	sp, r0
-
-	bx	r6
-
 	.globl psci_text_end
 psci_text_end:
 	.popsection
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..12cca7c 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -9,22 +9,6 @@
 
 	.arch_extension sec
 
-	@ r1 = target CPU
-	@ r2 = target PC
-
-.globl	psci_arch_init
-psci_arch_init:
-	mov	r6, lr
-
-	bl	psci_get_cpu_id
-	bl	psci_get_cpu_stack_top
-	mov	sp, r0
-
-	bx	r6
-
-	@ r1 = target CPU
-	@ r2 = target PC
-
 .globl psci_cpu_on
 psci_cpu_on:
 	push	{lr}
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index b7563ed..95ce938 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -49,8 +49,13 @@ _secure_monitor:
 	mcr	p15, 0, r5, c12, c0, 1
 	isb
 
-	@ Obtain a secure stack, and configure the PSCI backend
+	@ Obtain a secure stack
+	bl	psci_stack_setup
+
+	@ Configure the PSCI backend
+	push	{r0, r1, r2, ip}
 	bl	psci_arch_init
+	pop	{r0, r1, r2, ip}
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_773022
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index ab40837..46fcf77 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -211,6 +211,24 @@ ENTRY(psci_get_cpu_stack_top)
 	bx	lr
 ENDPROC(psci_get_cpu_stack_top)
 
+@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
+@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
+@ this function.
+ENTRY(psci_stack_setup)
+	mov	r6, lr
+	mov	r7, r0
+	bl	psci_get_cpu_id		@ CPU ID => r0
+	bl	psci_get_cpu_stack_top	@ stack top => r0
+	mov	sp, r0
+	mov	r0, r7
+	bx	r6
+ENDPROC(psci_stack_setup)
+
+ENTRY(psci_arch_init)
+	mov	pc, lr
+ENDPROC(psci_arch_init)
+.weak psci_arch_init
+
 ENTRY(psci_cpu_entry)
 	bl	psci_enable_smp
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_head.S b/arch/arm/cpu/armv7/sunxi/psci_head.S
index 8fa823d..e51db04 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_head.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_head.S
@@ -44,22 +44,8 @@
 #define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
 #define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
 
-@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
-@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
-@ this function.
 ENTRY(psci_arch_init)
-	mov	r6, lr
-	mov	r7, r0
-	bl	psci_get_cpu_id		@ CPU ID => r0
-	bl	psci_get_cpu_stack_top	@ stack top => r0
-	sub	r0, r0, #4		@ Save space for target PC
-	mov	sp, r0
-	mov	r0, r7
-	mov	lr, r6
-
-	push	{r0, r1, r2, ip, lr}
-	bl	sunxi_gic_init
-	pop	{r0, r1, r2, ip, pc}
+	b	sunxi_gic_init
 ENDPROC(psci_arch_init)
 
 ENTRY(psci_text_end)
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index b836da1..75068f3 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -61,9 +61,6 @@ ENTRY(psci_arch_init)
 	ldrne	r7, [r5]
 	mcrne	p15, 0, r7, c14, c0, 0	@ write CNTFRQ to CPU1..3
 
-	bl	psci_get_cpu_stack_top	@ stack top => r0
-	mov	sp, r0
-
 	bx	r6
 ENDPROC(psci_arch_init)
 
-- 
cgit v0.10.2


From 94a389b257039511784b91a263913c845c8146e4 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:32 +0800
Subject: sunxi: Move remaining PSCI assembly code to C

This patch finishes the rewrite of sunxi specific PSCI parts into C
code.

The assembly-only stack setup code has been factored out into a common
function for ARMv7. The GIC setup code can be renamed as psci_arch_init.
And we can use an empty stub function for psci_text_end.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index c208510..b35b9df 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
-obj-$(CONFIG_ARMV7_PSCI)	+= psci_head.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index a118e9d..cd0d944 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -250,7 +250,7 @@ void __secure psci_cpu_off(void)
 		wfi();
 }
 
-void __secure sunxi_gic_init(void)
+void __secure psci_arch_init(void)
 {
 	u32 reg;
 
@@ -271,3 +271,8 @@ void __secure sunxi_gic_init(void)
 	reg &= ~BIT(0); /* Secure mode */
 	cp15_write_scr(reg);
 }
+
+/* dummy entry for end of psci text */
+void __secure psci_text_end(void)
+{
+}
diff --git a/arch/arm/cpu/armv7/sunxi/psci_head.S b/arch/arm/cpu/armv7/sunxi/psci_head.S
deleted file mode 100644
index e51db04..0000000
--- a/arch/arm/cpu/armv7/sunxi/psci_head.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2013 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * Based on code by Carl van Schaik <carl@ok-labs.com>.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-#include <asm/arch-armv7/generictimer.h>
-#include <asm/gic.h>
-#include <asm/macro.h>
-#include <asm/psci.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Memory layout:
- *
- * SECURE_RAM to text_end :
- *	._secure_text section
- * text_end to ALIGN_PAGE(text_end):
- *	nothing
- * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
- *	1kB of stack per CPU (4 CPUs max).
- */
-
-	.pushsection ._secure.text, "ax"
-
-	.arch_extension sec
-
-#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
-#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
-
-ENTRY(psci_arch_init)
-	b	sunxi_gic_init
-ENDPROC(psci_arch_init)
-
-ENTRY(psci_text_end)
-	.popsection
-- 
cgit v0.10.2


From 1e77ce0e8b77c1e4ed516b5f8a46ef6d06921432 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:33 +0800
Subject: sunxi: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for sun7i

sun7i has 2 CPUs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 0dd2902..1c89fdf 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -21,6 +21,7 @@
 #define CONFIG_SUNXI_USB_PHYS	3
 
 #define CONFIG_ARMV7_PSCI		1
+#define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 
 /*
-- 
cgit v0.10.2


From a1274cc94a20a0fc6715522d021ab84969b6bf91 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:34 +0800
Subject: ARM: Page align secure section only when it is executed in situ

Targets that define CONFIG_ARMV7_SECURE_BASE will copy the secure section
to another address before execution.

Since the secure section in the u-boot image is only storage, there's
no reason to page align it and increase the binary image size.

Page align the secure section only when CONFIG_ARMV7_SECURE_BASE is not
defined. And instead of just aligning the __secure_start symbol, align
the whole .__secure_start section. This also makes the section empty,
so we need to add KEEP() to the input entry to prevent the section from
being garbage collected.

Also use ld constant "COMMONPAGESIZE" instead of hardcoded page size.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 1769b6e..ba17778 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -48,16 +48,20 @@ SECTIONS
 
 #ifdef CONFIG_ARMV7_NONSEC
 
+	/* Align the secure section only if we're going to use it in situ */
+	.__secure_start :
+#ifndef CONFIG_ARMV7_SECURE_BASE
+		ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+	{
+		KEEP(*(.__secure_start))
+	}
+
 #ifndef CONFIG_ARMV7_SECURE_BASE
 #define CONFIG_ARMV7_SECURE_BASE
 #define __ARMV7_PSCI_STACK_IN_RAM
 #endif
 
-	.__secure_start : {
-		. = ALIGN(0x1000);
-		*(.__secure_start)
-	}
-
 	.secure_text CONFIG_ARMV7_SECURE_BASE :
 		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
 	{
-- 
cgit v0.10.2


From dbf38aabd9f4d4fd4d9bd4eeeba88e0e47dcb27c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 5 Jul 2016 21:45:05 +0800
Subject: ARM: PSCI: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for PSCI enabled
 platforms

The original PSCI implementation assumed CONFIG_ARMV7_PSCI_NR_CPUS=4.
Add this to platforms that have not defined it, using CONFIG_MAX_CPUS if
it is defined, or the actual number of cores for the given platform.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 953c088..2b172a5 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -61,6 +61,7 @@
 #include "tegra-common-post.h"
 
 #define CONFIG_ARMV7_PSCI			1
+#define CONFIG_ARMV7_PSCI_NR_CPUS		4
 /* Reserve top 1M for secure RAM */
 #define CONFIG_ARMV7_SECURE_BASE		0xfff00000
 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index db684d2..eb444eb 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -10,6 +10,7 @@
 #define CONFIG_LS102XA
 
 #define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
 #define CONFIG_SYS_FSL_CLK
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0fb28ef..616aebb 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -10,6 +10,7 @@
 #define CONFIG_LS102XA
 
 #define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
 #define CONFIG_SYS_FSL_CLK
 
-- 
cgit v0.10.2


From 980d6a55119f757ade4abed88bf4b2b7494c68e6 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:36 +0800
Subject: ARM: Add an empty secure stack section

Until now we've been using memory beyond psci_text_end as stack space
for the secure monitor or PSCI implementation, even if space was not
allocated for it.

This was partially fixed in ("ARM: allocate extra space for PSCI stack
in secure section during link phase"). However, calculating stack space
from psci_text_end in one place, while allocating the space in another
is error prone.

This patch adds a separate empty secure stack section, with space for
CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also
__secure_stack_start and __secure_stack_end symbols. The linker script
handles calculating the correct VMAs for the stack section. For
platforms that relocate/copy the secure monitor before using it, the
space is not allocated in the executable, saving space.

For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page
of stack space for 4 CPUs is allocated, matching the previous behavior.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index ba17778..002706a 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -8,6 +8,7 @@
  */
 
 #include <config.h>
+#include <asm/psci.h>
 
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
@@ -68,18 +69,31 @@ SECTIONS
 		*(._secure.text)
 	}
 
-	. = LOADADDR(.__secure_start) +
-		SIZEOF(.__secure_start) +
-		SIZEOF(.secure_text);
-
+	.secure_stack ALIGN(ADDR(.secure_text) + SIZEOF(.secure_text),
+			    CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
 #ifdef __ARMV7_PSCI_STACK_IN_RAM
-	/* Align to page boundary and skip 2 pages */
-	. = (. & ~ 0xfff) + 0x2000;
-#undef __ARMV7_PSCI_STACK_IN_RAM
+		AT(ADDR(.secure_stack))
+#else
+		AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+#endif
+	{
+		KEEP(*(.__secure_stack_start))
+
+		/* Skip addreses for stack */
+		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+		/* Align end of stack section to page boundary */
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+		KEEP(*(.__secure_stack_end))
+	}
+
+#ifndef __ARMV7_PSCI_STACK_IN_RAM
+	/* Reset VMA but don't allocate space if we have secure SRAM */
+	. = LOADADDR(.secure_stack);
 #endif
 
-	__secure_end_lma = .;
-	.__secure_end : AT(__secure_end_lma) {
+	.__secure_end : AT(ADDR(.__secure_end)) {
 		*(.__secure_end)
 		LONG(0x1d1071c);	/* Must output something to reset LMA */
 	}
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 423fc70..a20702e 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -126,6 +126,8 @@ void _smp_pen(void);
 
 extern char __secure_start[];
 extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
 
 #endif /* CONFIG_ARMV7_NONSEC */
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index bc5edda..dab5769 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -47,6 +47,10 @@
 #define ARM_PSCI_0_2_FN_SYSTEM_OFF		ARM_PSCI_0_2_FN(8)
 #define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
 
+/* 1KB stack per core */
+#define ARM_PSCI_STACK_SHIFT	10
+#define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
+
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
 
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 6a94522..952e8ae 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -27,6 +27,8 @@ char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
 char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
 char __secure_start[0] __attribute__((section(".__secure_start")));
 char __secure_end[0] __attribute__((section(".__secure_end")));
+char __secure_stack_start[0] __attribute__((section(".__secure_stack_start")));
+char __secure_stack_end[0] __attribute__((section(".__secure_stack_end")));
 char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
 char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
 char __efi_runtime_rel_start[0] __attribute__((section(".__efi_runtime_rel_start")));
-- 
cgit v0.10.2


From 8c0ef7fad676827125ad91060361d05ab4b16f44 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:37 +0800
Subject: ARM: PSCI: Allocate PSCI stack in secure stack section

Now that we have a secure stack section that guarantees usable memory,
allocate the PSCI stacks in that section.

Also add a diagram detailing how the stacks are placed in memory.

Reserved space for the target PC remains unchanged. This should be
moved to global variables within a secure data section in the future.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 46fcf77..bfc4475 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,18 +196,28 @@ ENTRY(psci_cpu_off_common)
 	bx	lr
 ENDPROC(psci_cpu_off_common)
 
-@ expects CPU ID in r0 and returns stack top in r0
+@ The stacks are allocated in reverse order, i.e.
+@ the stack for CPU0 has the highest memory address.
+@
+@ --------------------  __secure_stack_end
+@ |  CPU0 target PC  |
+@ |------------------|
+@ |                  |
+@ |    CPU0 stack    |
+@ |                  |
+@ |------------------|  __secure_stack_end - 1KB
+@ |        .         |
+@ |        .         |
+@ |        .         |
+@ |        .         |
+@ --------------------  __secure_stack_start
+@
+@ This expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-	mov	r3, #0x400			@ 1kB of stack per CPU
-	mul	r0, r0, r3
-
-	ldr	r3, =psci_text_end		@ end of monitor text
-	add	r3, r3, #0x2000			@ Skip two pages
-	lsr	r3, r3, #12			@ Align to start of page
-	lsl	r3, r3, #12
-	sub	r3, r3, #4			@ reserve 1 word for target PC
-	sub	r0, r3, r0			@ here's our stack!
-
+	@ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT)
+	ldr	r3, =__secure_stack_end
+	sub	r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT
+	sub	r0, r0, #4		@ Save space for target PC
 	bx	lr
 ENDPROC(psci_get_cpu_stack_top)
 
-- 
cgit v0.10.2


From 28f90357323bc65e7da01c458222b84dc42988bb Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:38 +0800
Subject: ARM: PSCI: Remove unused psci_text_end symbol

psci_text_end was used to calculate the PSCI stack address following the
secure monitor text. Now that we have an explicit secure stack section,
this is no longer used.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 86116e1f..ba043ef 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -111,6 +111,4 @@ psci_cpu_off:
 1:	wfi
 	b	1b
 
-	.globl psci_text_end
-psci_text_end:
 	.popsection
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 12cca7c..d9e9fbf 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -33,6 +33,4 @@ psci_cpu_off:
 1: 	wfi
 	b 1b
 
-	.globl psci_text_end
-psci_text_end:
 	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index cd0d944..c7d97fe 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -271,8 +271,3 @@ void __secure psci_arch_init(void)
 	reg &= ~BIT(0); /* Secure mode */
 	cp15_write_scr(reg);
 }
-
-/* dummy entry for end of psci text */
-void __secure psci_text_end(void)
-{
-}
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index 75068f3..85d5b6b 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -106,6 +106,4 @@ ENTRY(psci_cpu_on)
 	pop	{pc}
 ENDPROC(psci_cpu_on)
 
-	.globl psci_text_end
-psci_text_end:
 	.popsection
-- 
cgit v0.10.2


From 3eff681818e2c858175a7cc4e766f75e95827920 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:39 +0800
Subject: ARM: Add CONFIG_ARMV7_SECURE_MAX_SIZE and check size of secure
 section

As the PSCI implementation grows, we might exceed the size of the secure
memory that holds the firmware.

Add a configurable CONFIG_ARMV7_SECURE_MAX_SIZE so platforms can define
how much secure memory is available. The linker then checks the size of
the whole secure section against this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 002706a..5a65c27 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -86,6 +86,17 @@ SECTIONS
 		. = ALIGN(CONSTANT(COMMONPAGESIZE));
 
 		KEEP(*(.__secure_stack_end))
+
+#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
+		/*
+		 * We are not checking (__secure_end - __secure_start) here,
+		 * as these are the load addresses, and do not include the
+		 * stack section. Instead, use the end of the stack section
+		 * and the start of the text section.
+		 */
+		ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
+		       "Error: secure section exceeds secure memory size");
+#endif
 	}
 
 #ifndef __ARMV7_PSCI_STACK_IN_RAM
-- 
cgit v0.10.2


From 9c4f52b855876862a7a30b63bde4a0d22605c3dc Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:40 +0800
Subject: sunxi: Define CONFIG_ARMV7_SECURE_MAX_SIZE for sun6i/sun7i

Both sun6i and sun7i have 64 KB of secure SRAM.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index 95ccc35..0625502 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -25,6 +25,7 @@
 #define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_PSCI_NR_CPUS	4
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
+#define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */
 
 /*
  * Include common sunxi configuration where most the settings are
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index 1c89fdf..e9074d5 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -23,6 +23,7 @@
 #define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
+#define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */
 
 /*
  * Include common sunxi configuration where most the settings are
-- 
cgit v0.10.2


From afc1f65f504324cd5f87a8cb480bebeb0c61e4e0 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:41 +0800
Subject: ARM: Move __secure definition to common asm/secure.h

sunxi and i.mx7 both define the __secure modifier to put functions in
the secure section. Move this to a common place.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/mx7/psci-mx7.c b/arch/arm/cpu/armv7/mx7/psci-mx7.c
index 9a33047..502552d 100644
--- a/arch/arm/cpu/armv7/mx7/psci-mx7.c
+++ b/arch/arm/cpu/armv7/mx7/psci-mx7.c
@@ -1,9 +1,9 @@
 #include <asm/io.h>
 #include <asm/psci.h>
+#include <asm/secure.h>
 #include <asm/arch/imx-regs.h>
 #include <common.h>
 
-#define __secure __attribute__((section("._secure.text")))
 
 #define GPC_CPU_PGC_SW_PDN_REQ	0xfc
 #define GPC_CPU_PGC_SW_PUP_REQ	0xf0
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index c7d97fe..be3a1fb 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -17,11 +17,11 @@
 #include <asm/gic.h>
 #include <asm/io.h>
 #include <asm/psci.h>
+#include <asm/secure.h>
 #include <asm/system.h>
 
 #include <linux/bitops.h>
 
-#define __secure	__attribute__ ((section ("._secure.text")))
 #define __irq		__attribute__ ((interrupt ("IRQ")))
 
 #define	GICD_BASE	(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index effdb18..6d9088b 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -3,6 +3,8 @@
 
 #include <config.h>
 
+#define __secure __attribute__ ((section ("._secure.text")))
+
 #ifdef CONFIG_ARMV7_SECURE_BASE
 /*
  * Warning, horror ahead.
-- 
cgit v0.10.2


From a5aa7ff33a942ce8ea38006fd5225a800827bb2c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 5 Jul 2016 21:45:06 +0800
Subject: ARM: Add secure section for initialized data

The secure monitor may need to store global or static values within the
secure section of memory, such as target PC or CPU power status.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 9a5a974..8f85862 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -120,8 +120,8 @@ endif
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
-OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j \
-	.got -j .got.plt -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
+		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
 endif
 
 ifdef CONFIG_OF_EMBED
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 5a65c27..36c9fd0 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -69,12 +69,17 @@ SECTIONS
 		*(._secure.text)
 	}
 
-	.secure_stack ALIGN(ADDR(.secure_text) + SIZEOF(.secure_text),
+	.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+	{
+		*(._secure.data)
+	}
+
+	.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
 			    CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
 #ifdef __ARMV7_PSCI_STACK_IN_RAM
 		AT(ADDR(.secure_stack))
 #else
-		AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+		AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
 #endif
 	{
 		KEEP(*(.__secure_stack_start))
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 6d9088b..5a403bc 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -4,6 +4,7 @@
 #include <config.h>
 
 #define __secure __attribute__ ((section ("._secure.text")))
+#define __secure_data __attribute__ ((section ("._secure.data")))
 
 #ifdef CONFIG_ARMV7_SECURE_BASE
 /*
-- 
cgit v0.10.2


From 45c334e6b22bae75ada8662b88000c4347b1361b Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Tue, 5 Jul 2016 21:45:07 +0800
Subject: ARM: PSCI: Add helper functions to access per-CPU target PC storage

Now that we have a data section, add helper functions to save and fetch
per-CPU target PC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ddd8d12..0d4bfbc 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -19,7 +19,7 @@ endif
 endif
 
 obj-$(CONFIG_ARMV7_NONSEC)	+= nonsec_virt.o virt-v7.o virt-dt.o
-obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
+obj-$(CONFIG_ARMV7_PSCI)	+= psci.o psci-common.o
 
 obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c
new file mode 100644
index 0000000..d14b693
--- /dev/null
+++ b/arch/arm/cpu/armv7/psci-common.c
@@ -0,0 +1,39 @@
+/*
+ * Common PSCI functions
+ *
+ * Copyright (C) 2016 Chen-Yu Tsai
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <asm/armv7.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <linux/linkage.h>
+
+static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
+
+void __secure psci_save_target_pc(int cpu, u32 pc)
+{
+	psci_target_pc[cpu] = pc;
+	DSB;
+}
+
+u32 __secure psci_get_target_pc(int cpu)
+{
+	return psci_target_pc[cpu];
+}
+
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index dab5769..a0da023 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -54,6 +54,10 @@
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
 
+/* These 2 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */
+u32 psci_get_target_pc(int cpu);
+void psci_save_target_pc(int cpu, u32 pc);
+
 void psci_cpu_entry(void);
 u32 psci_get_cpu_id(void);
 u32 psci_get_cpu_stack_top(int cpu);
-- 
cgit v0.10.2


From 6e6622de166f53597172687b7269b07cf48844df Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:44 +0800
Subject: ARM: PSCI: Switch to per-CPU target PC storage in secure data section

Now that we have a secure data section and space to store per-CPU target
PC address, switch to it instead of storing the target PC on the stack.

Also save clobbered r4-r7 registers on the stack and restore them on
return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index ba043ef..f9b26b4 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -29,16 +29,16 @@
 	@ r2 = target PC
 .globl	psci_cpu_on
 psci_cpu_on:
-	push	{lr}
+	push	{r4, r5, r6, lr}
 
 	@ Clear and Get the correct CPU number
 	@ r1 = 0xf01
-	and	r1, r1, #0xff
+	and	r4, r1, #0xff
 
-	mov	r0, r1
-	bl	psci_get_cpu_stack_top
-	str	r2, [r0]
-	dsb
+	mov	r0, r4
+	mov	r1, r2
+	bl	psci_save_target_pc
+	mov	r1, r4
 
 	@ Get DCFG base address
 	movw	r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
@@ -101,7 +101,7 @@ holdoff_release:
 	@ Return
 	mov	r0, #ARM_PSCI_RET_SUCCESS
 
-	pop	{lr}
+	pop	{r4, r5, r6, lr}
 	bx	lr
 
 .globl	psci_cpu_off
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index d9e9fbf..96e88d6 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -11,17 +11,20 @@
 
 .globl psci_cpu_on
 psci_cpu_on:
-	push	{lr}
+	push	{r4, r5, lr}
 
+	mov	r4, r0
+	mov	r5, r1
 	mov	r0, r1
-	bl	psci_get_cpu_stack_top
-	str	r2, [r0]
-	dsb
+	mov	r1, r2
+	bl	psci_save_target_pc
 
+	mov	r0, r4
+	mov	r1, r5
 	ldr	r2, =psci_cpu_entry
 	bl	imx_cpu_on
 
-	pop	{pc}
+	pop	{r4, r5, pc}
 
 .globl psci_cpu_off
 psci_cpu_off:
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bfc4475..50dfddb 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -245,8 +245,7 @@ ENTRY(psci_cpu_entry)
 	bl	_nonsec_init
 
 	bl	psci_get_cpu_id			@ CPU ID => r0
-	bl	psci_get_cpu_stack_top		@ stack top => r0
-	ldr	r0, [r0]			@ target PC at stack top
+	bl	psci_get_target_pc		@ target PC => r0
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index be3a1fb..7ac8406 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -209,9 +209,8 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 	u32 cpu = (mpidr & 0x3);
 
-	/* store target PC at target CPU stack top */
-	writel(pc, psci_get_cpu_stack_top(cpu));
-	DSB;
+	/* store target PC */
+	psci_save_target_pc(cpu, pc);
 
 	/* Set secondary core power on PC */
 	writel((u32)&psci_cpu_entry, &cpucfg->priv0);
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index 85d5b6b..645d08f 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -85,12 +85,13 @@ _loop:	wfi
 ENDPROC(psci_cpu_off)
 
 ENTRY(psci_cpu_on)
-	push	{lr}
+	push	{r4, r5, r6, lr}
 
+	mov	r4, r1
 	mov	r0, r1
-	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
-	str	r2, [r0]		@ store target PC at stack top
-	dsb
+	mov	r1, r2
+	bl	psci_save_target_pc	@ store target PC
+	mov	r1, r4
 
 	ldr	r6, =TEGRA_RESET_EXCEPTION_VECTOR
 	ldr	r5, =psci_cpu_entry
@@ -103,7 +104,7 @@ ENTRY(psci_cpu_on)
 	str	r5, [r6, r2]
 
 	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-	pop	{pc}
+	pop	{r4, r5, r6, pc}
 ENDPROC(psci_cpu_on)
 
 	.popsection
-- 
cgit v0.10.2


From b7073965a343fca2bcde4195fbba664c98f309d8 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Sun, 19 Jun 2016 12:38:45 +0800
Subject: ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.S

Now that we have a secure data section for storing variables, there
should be no need for platform code to get the stack address.

Make psci_get_cpu_stack_top a local function, as it should only be
used in armv7/psci.S and only by psci_stack_setup.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 50dfddb..350b75c 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -213,7 +213,7 @@ ENDPROC(psci_cpu_off_common)
 @ --------------------  __secure_stack_start
 @
 @ This expects CPU ID in r0 and returns stack top in r0
-ENTRY(psci_get_cpu_stack_top)
+LENTRY(psci_get_cpu_stack_top)
 	@ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT)
 	ldr	r3, =__secure_stack_end
 	sub	r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index a0da023..7ba7ce3 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -60,7 +60,6 @@ void psci_save_target_pc(int cpu, u32 pc);
 
 void psci_cpu_entry(void);
 u32 psci_get_cpu_id(void);
-u32 psci_get_cpu_stack_top(int cpu);
 void psci_cpu_off_common(void);
 
 int psci_update_dt(void *fdt);
-- 
cgit v0.10.2


From e61a7534e33063a76e105d895e5c6317f2d0cd76 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 24 Jun 2016 16:46:18 -0700
Subject: armv8: Move secure_ram variable out of generic global data

Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/README b/README
index 26d5ad2..af37d41 100644
--- a/README
+++ b/README
@@ -3766,10 +3766,11 @@ Configuration Settings:
 		You only need to set this if address zero isn't writeable
 
 - CONFIG_SYS_MEM_RESERVE_SECURE
+		Only implemented for ARMv8 for now.
 		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
 		is substracted from total RAM and won't be reported to OS.
 		This memory can be used as secure memory. A variable
-		gd->secure_ram is used to track the location. In systems
+		gd->arch.secure_ram is used to track the location. In systems
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106..a397f5d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -289,8 +289,8 @@ static inline int final_secure_ddr(u64 *level0_table,
  * These tables are in DRAM. Sub tables are added to enable cache for
  * QBMan and OCRAM.
  *
- * Put the MMU table in secure memory if gd->secure_ram is valid.
- * OCRAM will be not used for this purpose so gd->secure_ram can't be 0.
+ * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
+ * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
  *
  * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
  * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
@@ -321,13 +321,13 @@ static inline void final_mmu_setup(void)
 
 	if (el == 3) {
 		/*
-		 * Only use gd->secure_ram if the address is recalculated
+		 * Only use gd->arch.secure_ram if the address is recalculated
 		 * Align to 4KB for MMU table
 		 */
-		if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
-			level0_table = (u64 *)(gd->secure_ram & ~0xfff);
+		if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
+			level0_table = (u64 *)(gd->arch.secure_ram & ~0xfff);
 		else
-			printf("MMU warning: gd->secure_ram is not maintained, disabled.\n");
+			printf("MMU warning: gd->arch.secure_ram is not maintained, disabled.\n");
 	}
 #endif
 	level1_table0 = level0_table + 512;
@@ -374,7 +374,7 @@ static inline void final_mmu_setup(void)
 	}
 	/* Set the secure memory to secure in MMU */
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-	if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
+	if (el == 3 && gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 #ifdef CONFIG_FSL_LSCH3
 		level2_table_secure = level2_table1 + 512;
 #elif defined(CONFIG_FSL_LSCH2)
@@ -382,10 +382,10 @@ static inline void final_mmu_setup(void)
 #endif
 		if (!final_secure_ddr(level0_table,
 				      level2_table_secure,
-				      gd->secure_ram & ~0x3)) {
-			gd->secure_ram |= MEM_RESERVE_SECURE_SECURED;
+				      gd->arch.secure_ram & ~0x3)) {
+			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 			debug("Now MMU table is in secured memory at 0x%llx\n",
-			      gd->secure_ram & ~0x3);
+			      gd->arch.secure_ram & ~0x3);
 		} else {
 			printf("MMU warning: Failed to secure DDR\n");
 		}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 77d2653..2d76cd4 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -44,6 +44,20 @@ struct arch_global_data {
 	unsigned long tlb_emerg;
 #endif
 #endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#define MEM_RESERVE_SECURE_SECURED	0x1
+#define MEM_RESERVE_SECURE_MAINTAINED	0x2
+#define MEM_RESERVE_SECURE_ADDR_MASK	(~0x3)
+	/*
+	 * Secure memory addr
+	 * This variable needs maintenance if the RAM base is not zero,
+	 * or if RAM splits into non-consecutive banks. It also has a
+	 * flag indicating the secure memory is marked as secure by MMU.
+	 * Flags used: 0x1 secured
+	 *             0x2 maintained
+	 */
+	phys_addr_t secure_ram;
+#endif
 
 #ifdef CONFIG_OMAP_COMMON
 	u32 omap_boot_device;
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 0fd835d..d4540d0 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -128,7 +128,7 @@ phys_size_t initdram(int board_type)
 void dram_init_banksize(void)
 {
 	/*
-	 * gd->secure_ram tracks the location of secure memory.
+	 * gd->arch.secure_ram tracks the location of secure memory.
 	 * It was set as if the memory starts from 0.
 	 * The address needs to add the offset of its bank.
 	 */
@@ -139,16 +139,17 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[1].start +
-				 gd->secure_ram -
-				 CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+				      gd->arch.secure_ram -
+				      CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	}
 }
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 1e2fd2e..61b1cc4 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -189,7 +189,7 @@ phys_size_t initdram(int board_type)
 void dram_init_banksize(void)
 {
 	/*
-	 * gd->secure_ram tracks the location of secure memory.
+	 * gd->arch.secure_ram tracks the location of secure memory.
 	 * It was set as if the memory starts from 0.
 	 * The address needs to add the offset of its bank.
 	 */
@@ -200,16 +200,17 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[1].start +
-				 gd->secure_ram -
-				 CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+				      gd->arch.secure_ram -
+				      CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	}
 }
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index 1827ddc..e6130ec 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -177,7 +177,7 @@ void dram_init_banksize(void)
 #endif
 
 	/*
-	 * gd->secure_ram tracks the location of secure memory.
+	 * gd->arch.secure_ram tracks the location of secure memory.
 	 * It was set as if the memory starts from 0.
 	 * The address needs to add the offset of its bank.
 	 */
@@ -188,16 +188,17 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[1].start +
-				 gd->secure_ram -
-				 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+				      gd->arch.secure_ram -
+				      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	}
 
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index fcb0366..9c6f477 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -177,7 +177,7 @@ void dram_init_banksize(void)
 #endif
 
 	/*
-	 * gd->secure_ram tracks the location of secure memory.
+	 * gd->arch.secure_ram tracks the location of secure memory.
 	 * It was set as if the memory starts from 0.
 	 * The address needs to add the offset of its bank.
 	 */
@@ -188,16 +188,17 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[1].start +
-				 gd->secure_ram -
-				 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+				      gd->arch.secure_ram -
+				      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	}
 
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index a04d21b..ecd1e71 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -177,7 +177,7 @@ void dram_init_banksize(void)
 #endif
 
 	/*
-	 * gd->secure_ram tracks the location of secure memory.
+	 * gd->arch.secure_ram tracks the location of secure memory.
 	 * It was set as if the memory starts from 0.
 	 * The address needs to add the offset of its bank.
 	 */
@@ -188,16 +188,17 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[1].start +
-				 gd->secure_ram -
-				 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+				      gd->arch.secure_ram -
+				      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-		gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
 	}
 
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 1c4bed9..f2435ab 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -385,9 +385,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 	}
 
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-	if (gd->secure_ram & MEM_RESERVE_SECURE_SECURED) {
+	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
 		print_num("Secure ram",
-			  gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
+			  gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
 	}
 #endif
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
diff --git a/common/board_f.c b/common/board_f.c
index d405b5b..0fc96bd 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -339,7 +339,7 @@ static int setup_dest_addr(void)
 	 * Record secure memory location. Need recalcuate if memory splits
 	 * into banks, or the ram base is not zero.
 	 */
-	gd->secure_ram = gd->ram_size;
+	gd->arch.secure_ram = gd->ram_size;
 #endif
 	/*
 	 * Subtract specified amount of memory to hide so that it won't
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 0abcbe4..a6d1d2a 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -55,20 +55,6 @@ typedef struct global_data {
 
 	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
 	phys_size_t ram_size;	/* RAM size */
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-#define MEM_RESERVE_SECURE_SECURED	0x1
-#define MEM_RESERVE_SECURE_MAINTAINED	0x2
-#define MEM_RESERVE_SECURE_ADDR_MASK	(~0x3)
-	/*
-	 * Secure memory addr
-	 * This variable needs maintenance if the RAM base is not zero,
-	 * or if RAM splits into non-consecutive banks. It also has a
-	 * flag indicating the secure memory is marked as secure by MMU.
-	 * Flags used: 0x1 secured
-	 *             0x2 maintained
-	 */
-	phys_addr_t secure_ram;
-#endif
 	unsigned long mon_len;	/* monitor len */
 	unsigned long irq_sp;		/* irq stack pointer */
 	unsigned long start_addr_sp;	/* start_addr_stackpointer */
-- 
cgit v0.10.2


From 50e93b95653da44b9743357dfa3701e8482fd167 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 24 Jun 2016 16:46:19 -0700
Subject: armv8: Add tlb_allocated to arch global data

When secure ram is used, MMU tables have to be put into secure ram.
To use common MMU code, gd->arch.tlb_addr will be used to host TLB
entry pointer. To save allocated memory for later use, tlb_allocated
variable is added to global data structure.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 2d76cd4..1055017 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -57,6 +57,7 @@ struct arch_global_data {
 	 *             0x2 maintained
 	 */
 	phys_addr_t secure_ram;
+	unsigned long tlb_allocated;
 #endif
 
 #ifdef CONFIG_OMAP_COMMON
diff --git a/common/board_f.c b/common/board_f.c
index 0fc96bd..a1138b0 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -432,6 +432,15 @@ static int reserve_mmu(void)
 	gd->arch.tlb_addr = gd->relocaddr;
 	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
 	      gd->arch.tlb_addr + gd->arch.tlb_size);
+
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+	/*
+	 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
+	 * with location within secure ram.
+	 */
+	gd->arch.tlb_allocated = gd->arch.tlb_addr;
+#endif
+
 	return 0;
 }
 #endif
-- 
cgit v0.10.2


From 252cdb46ee33ff876823d0ce0a0190c3878c76ff Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 24 Jun 2016 16:46:20 -0700
Subject: armv8: mmu: house cleaning

Make setup_pgtages() and get_tcr() available for platform code to
customize MMU tables.
Remove unintentional call of create_table().

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 1615542..b8867a7 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
  *    off:          FFF
  */
 
-static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
+u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
 {
 	u64 max_addr = 0;
 	u64 ips, va_bits;
@@ -349,10 +349,13 @@ __weak u64 get_page_table_size(void)
 	return size;
 }
 
-static void setup_pgtables(void)
+void setup_pgtables(void)
 {
 	int i;
 
+	if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
+		panic("Page table pointer not setup.");
+
 	/*
 	 * Allocate the first level we're on with invalidate entries.
 	 * If the starting level is 0 (va_bits >= 39), then this is our
@@ -363,9 +366,6 @@ static void setup_pgtables(void)
 	/* Now add all MMU table entries one after another to the table */
 	for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
 		add_map(&mem_map[i]);
-
-	/* Create the same thing once more for our emergency page table */
-	create_table();
 }
 
 static void setup_all_pgtables(void)
@@ -527,6 +527,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 	debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
 
+	if (!gd->arch.tlb_emerg)
+		panic("Emergency page table not setup.");
+
 	/*
 	 * We can not modify page tables that we're currently running on,
 	 * so we first need to switch to the "emergency" page tables where
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 0d08ed3..b7b4706 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -141,6 +141,8 @@ struct mm_region {
 };
 
 extern struct mm_region *mem_map;
+void setup_pgtables(void);
+u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
 #endif
 
 #endif /* _ASM_ARMV8_MMU_H_ */
-- 
cgit v0.10.2


From f733d46620d0efb93091f147f81a4bf9588fad3f Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 24 Jun 2016 16:46:21 -0700
Subject: armv8: mmu: split block if necessary

When page tables are created, allow later table to be created on
previous block entry. Splitting block feature is already working
with current code. This patch only rearranges the code order and
adds one condition to call split_block().

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index b8867a7..8604035 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -167,6 +167,37 @@ static void set_pte_table(u64 *pte, u64 *table)
 	*pte = PTE_TYPE_TABLE | (ulong)table;
 }
 
+/* Splits a block PTE into table with subpages spanning the old block */
+static void split_block(u64 *pte, int level)
+{
+	u64 old_pte = *pte;
+	u64 *new_table;
+	u64 i = 0;
+	/* level describes the parent level, we need the child ones */
+	int levelshift = level2shift(level + 1);
+
+	if (pte_type(pte) != PTE_TYPE_BLOCK)
+		panic("PTE %p (%llx) is not a block. Some driver code wants to "
+		      "modify dcache settings for an range not covered in "
+		      "mem_map.", pte, old_pte);
+
+	new_table = create_table();
+	debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
+
+	for (i = 0; i < MAX_PTE_ENTRIES; i++) {
+		new_table[i] = old_pte | (i << levelshift);
+
+		/* Level 3 block PTEs have the table type */
+		if ((level + 1) == 3)
+			new_table[i] |= PTE_TYPE_TABLE;
+
+		debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
+	}
+
+	/* Set the new table into effect */
+	set_pte_table(pte, new_table);
+}
+
 /* Add one mm_region map entry to the page tables */
 static void add_map(struct mm_region *map)
 {
@@ -188,6 +219,8 @@ static void add_map(struct mm_region *map)
 
 		for (level = 1; level < 4; level++) {
 			pte = find_pte(addr, level);
+			if (!pte)
+				panic("pte not found\n");
 			blocksize = 1ULL << level2shift(level);
 			debug("Checking if pte fits for addr=%llx size=%llx "
 			      "blocksize=%llx\n", addr, size, blocksize);
@@ -199,48 +232,21 @@ static void add_map(struct mm_region *map)
 				addr += blocksize;
 				size -= blocksize;
 				break;
-			} else if ((pte_type(pte) == PTE_TYPE_FAULT)) {
+			} else if (pte_type(pte) == PTE_TYPE_FAULT) {
 				/* Page doesn't fit, create subpages */
 				debug("Creating subtable for addr 0x%llx "
 				      "blksize=%llx\n", addr, blocksize);
 				new_table = create_table();
 				set_pte_table(pte, new_table);
+			} else if (pte_type(pte) == PTE_TYPE_BLOCK) {
+				debug("Split block into subtable for addr 0x%llx blksize=0x%llx\n",
+				      addr, blocksize);
+				split_block(pte, level);
 			}
 		}
 	}
 }
 
-/* Splits a block PTE into table with subpages spanning the old block */
-static void split_block(u64 *pte, int level)
-{
-	u64 old_pte = *pte;
-	u64 *new_table;
-	u64 i = 0;
-	/* level describes the parent level, we need the child ones */
-	int levelshift = level2shift(level + 1);
-
-	if (pte_type(pte) != PTE_TYPE_BLOCK)
-		panic("PTE %p (%llx) is not a block. Some driver code wants to "
-		      "modify dcache settings for an range not covered in "
-		      "mem_map.", pte, old_pte);
-
-	new_table = create_table();
-	debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
-
-	for (i = 0; i < MAX_PTE_ENTRIES; i++) {
-		new_table[i] = old_pte | (i << levelshift);
-
-		/* Level 3 block PTEs have the table type */
-		if ((level + 1) == 3)
-			new_table[i] |= PTE_TYPE_TABLE;
-
-		debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
-	}
-
-	/* Set the new table into effect */
-	set_pte_table(pte, new_table);
-}
-
 enum pte_type {
 	PTE_INVAL,
 	PTE_BLOCK,
-- 
cgit v0.10.2


From cd4b0c5feaaa524b44889cde8f58d4b121df8fed Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 24 Jun 2016 16:46:22 -0700
Subject: armv8: mmu: Add support of non-identical mapping

Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 8604035..ac909a1 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -44,7 +44,7 @@ u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
 
 	/* Find the largest address we need to support */
 	for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
-		max_addr = max(max_addr, mem_map[i].base + mem_map[i].size);
+		max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
 
 	/* Calculate the maximum physical (and thus virtual) address */
 	if (max_addr > (1ULL << 44)) {
@@ -202,7 +202,8 @@ static void split_block(u64 *pte, int level)
 static void add_map(struct mm_region *map)
 {
 	u64 *pte;
-	u64 addr = map->base;
+	u64 virt = map->virt;
+	u64 phys = map->phys;
 	u64 size = map->size;
 	u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
 	u64 blocksize;
@@ -210,37 +211,39 @@ static void add_map(struct mm_region *map)
 	u64 *new_table;
 
 	while (size) {
-		pte = find_pte(addr, 0);
+		pte = find_pte(virt, 0);
 		if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
-			debug("Creating table for addr 0x%llx\n", addr);
+			debug("Creating table for virt 0x%llx\n", virt);
 			new_table = create_table();
 			set_pte_table(pte, new_table);
 		}
 
 		for (level = 1; level < 4; level++) {
-			pte = find_pte(addr, level);
+			pte = find_pte(virt, level);
 			if (!pte)
 				panic("pte not found\n");
+
 			blocksize = 1ULL << level2shift(level);
-			debug("Checking if pte fits for addr=%llx size=%llx "
-			      "blocksize=%llx\n", addr, size, blocksize);
-			if (size >= blocksize && !(addr & (blocksize - 1))) {
+			debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
+			      virt, size, blocksize);
+			if (size >= blocksize && !(virt & (blocksize - 1))) {
 				/* Page fits, create block PTE */
-				debug("Setting PTE %p to block addr=%llx\n",
-				      pte, addr);
-				*pte = addr | attrs;
-				addr += blocksize;
+				debug("Setting PTE %p to block virt=%llx\n",
+				      pte, virt);
+				*pte = phys | attrs;
+				virt += blocksize;
+				phys += blocksize;
 				size -= blocksize;
 				break;
 			} else if (pte_type(pte) == PTE_TYPE_FAULT) {
 				/* Page doesn't fit, create subpages */
-				debug("Creating subtable for addr 0x%llx "
-				      "blksize=%llx\n", addr, blocksize);
+				debug("Creating subtable for virt 0x%llx blksize=%llx\n",
+				      virt, blocksize);
 				new_table = create_table();
 				set_pte_table(pte, new_table);
 			} else if (pte_type(pte) == PTE_TYPE_BLOCK) {
-				debug("Split block into subtable for addr 0x%llx blksize=0x%llx\n",
-				      addr, blocksize);
+				debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
+				      virt, blocksize);
 				split_block(pte, level);
 			}
 		}
@@ -271,7 +274,7 @@ static int count_required_pts(u64 addr, int level, u64 maxaddr)
 
 	for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
 		struct mm_region *map = &mem_map[i];
-		u64 start = map->base;
+		u64 start = map->virt;
 		u64 end = start + map->size;
 
 		/* Check if the PTE would overlap with the map */
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index dac12a2..5c97e0e 100644
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -32,24 +32,28 @@ u32 cpu_mask(void)
 
 static struct mm_region s32v234_mem_map[] = {
 	{
-		.base = S32V234_IRAM_BASE,
+		.virt = S32V234_IRAM_BASE,
+		.phys = S32V234_IRAM_BASE,
 		.size = S32V234_IRAM_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
 	}, {
-		.base = S32V234_DRAM_BASE1,
+		.virt = S32V234_DRAM_BASE1,
+		.phys = S32V234_DRAM_BASE1,
 		.size = S32V234_DRAM_SIZE1,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
 	}, {
-		.base = S32V234_PERIPH_BASE,
+		.virt = S32V234_PERIPH_BASE,
+		.phys = S32V234_PERIPH_BASE,
 		.size = S32V234_PERIPH_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE
 			 /* TODO: Do we need these? */
 			 /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
 	}, {
-		.base = S32V234_DRAM_BASE2,
+		.virt = S32V234_DRAM_BASE2,
+		.phys = S32V234_DRAM_BASE2,
 		.size = S32V234_DRAM_SIZE2,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
 			 PTE_BLOCK_OUTER_SHARE
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 509f0aa..b0f1295 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -18,40 +18,47 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct mm_region zynqmp_mem_map[] = {
 	{
-		.base = 0x0UL,
+		.virt = 0x0UL,
+		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-		.base = 0x80000000UL,
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
 		.size = 0x70000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.base = 0xf8000000UL,
+		.virt = 0xf8000000UL,
+		.phys = 0xf8000000UL,
 		.size = 0x07e00000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.base = 0xffe00000UL,
+		.virt = 0xffe00000UL,
+		.phys = 0xffe00000UL,
 		.size = 0x00200000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-		.base = 0x400000000UL,
+		.virt = 0x400000000UL,
+		.phys = 0x400000000UL,
 		.size = 0x200000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.base = 0x600000000UL,
+		.virt = 0x600000000UL,
+		.phys = 0x600000000UL,
 		.size = 0x800000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-		.base = 0xe00000000UL,
+		.virt = 0xe00000000UL,
+		.phys = 0xe00000000UL,
 		.size = 0xf200000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index b7b4706..aa0f3c4 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -135,7 +135,8 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
 }
 
 struct mm_region {
-	u64 base;
+	u64 virt;
+	u64 phys;
 	u64 size;
 	u64 attrs;
 };
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
index ba6d99d..2381422 100644
--- a/arch/arm/mach-exynos/mmu-arm64.c
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -13,21 +13,20 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_EXYNOS7420
 static struct mm_region exynos7420_mem_map[] = {
 	{
-		.base	= 0x10000000UL,
+		.virt	= 0x10000000UL,
+		.phys	= 0x10000000UL,
 		.size	= 0x10000000UL,
 		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 				PTE_BLOCK_NON_SHARE |
 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
 	}, {
-		.base	= 0x40000000UL,
+		.virt	= 0x40000000UL,
+		.phys	= 0x40000000UL,
 		.size	= 0x80000000UL,
 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 				PTE_BLOCK_INNER_SHARE,
 	}, {
 		/* List terminator */
-		.base	= 0,
-		.size	= 0,
-		.attrs	= 0,
 	},
 };
 
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index 64fa3c1..1dd53e2 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -48,12 +48,14 @@ void reset_cpu(ulong addr)
 
 static struct mm_region gxbb_mem_map[] = {
 	{
-		.base = 0x0UL,
+		.virt = 0x0UL,
+		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-		.base = 0x80000000UL,
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c
index ef0db2a..580b9c7 100644
--- a/arch/arm/mach-snapdragon/sysmap-apq8016.c
+++ b/arch/arm/mach-snapdragon/sysmap-apq8016.c
@@ -11,13 +11,15 @@
 
 static struct mm_region apq8016_mem_map[] = {
 	{
-		.base = 0x0UL, /* Peripheral block */
+		.virt = 0x0UL, /* Peripheral block */
+		.phys = 0x0UL, /* Peripheral block */
 		.size = 0x8000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.base = 0x80000000UL, /* DDR */
+		.virt = 0x80000000UL, /* DDR */
+		.phys = 0x80000000UL, /* DDR */
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 66e028e..01bfc93 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -46,13 +46,15 @@ struct fel_stash fel_stash __attribute__((section(".data")));
 static struct mm_region sunxi_mem_map[] = {
 	{
 		/* SRAM, MMIO regions */
-		.base = 0x0UL,
+		.virt = 0x0UL,
+		.phys = 0x0UL,
 		.size = 0x40000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE
 	}, {
 		/* RAM */
-		.base = 0x40000000UL,
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index 501c4f0..7b1d258 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -14,13 +14,15 @@
 
 static struct mm_region tegra_mem_map[] = {
 	{
-		.base = 0x0UL,
+		.virt = 0x0UL,
+		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.base = 0x80000000UL,
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
 		.size = 0xff80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c
index 74ef919..67bc4f1 100644
--- a/arch/arm/mach-uniphier/arm64/mem_map.c
+++ b/arch/arm/mach-uniphier/arm64/mem_map.c
@@ -10,14 +10,16 @@
 
 static struct mm_region uniphier_mem_map[] = {
 	{
-		.base = 0x00000000,
+		.virt = 0x00000000,
+		.phys = 0x00000000,
 		.size = 0x80000000,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{
-		.base = 0x80000000,
+		.virt = 0x80000000,
+		.phys = 0x80000000,
 		.size = 0xc0000000,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 973b579..e34af6c 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -31,13 +31,15 @@ U_BOOT_DEVICE(vexpress_serials) = {
 
 static struct mm_region vexpress64_mem_map[] = {
 	{
-		.base = 0x0UL,
+		.virt = 0x0UL,
+		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.base = 0x80000000UL,
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
 		.size = 0xff80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index 9131a38..960ca53 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -45,16 +45,19 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct mm_region thunderx_mem_map[] = {
 	{
-		.base = 0x000000000000UL,
+		.virt = 0x000000000000UL,
+		.phys = 0x000000000000UL,
 		.size = 0x40000000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
 	}, {
-		.base = 0x800000000000UL,
+		.virt = 0x800000000000UL,
+		.phys = 0x800000000000UL,
 		.size = 0x40000000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE,
 	}, {
-		.base = 0x840000000000UL,
+		.virt = 0x840000000000UL,
+		.phys = 0x840000000000UL,
 		.size = 0x40000000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE,
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 7abc678..72d6334 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -93,12 +93,14 @@ U_BOOT_DEVICE(hikey_seriala) = {
 
 static struct mm_region hikey_mem_map[] = {
 	{
-		.base = 0x0UL,
+		.virt = 0x0UL,
+		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-		.base = 0x80000000UL,
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index c45ddb1..fbfbf6c 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -234,12 +234,14 @@ static const struct rpi_model *model;
 #ifdef CONFIG_ARM64
 static struct mm_region bcm2837_mem_map[] = {
 	{
-		.base = 0x00000000UL,
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
 		.size = 0x3f000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {
-		.base = 0x3f000000UL,
+		.virt = 0x3f000000UL,
+		.phys = 0x3f000000UL,
 		.size = 0x01000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
-- 
cgit v0.10.2


From fc5d54b7fa3fa602e06e2f0863c0b134d6afca70 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 15 Jul 2016 15:30:33 -0400
Subject: configs: Add more CONFIG_ARMV7_PSCI_NR_CPUS entries

The code had assumed 4 CPUS before and now we have this configurable.
For now, set this to the previous default.

Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index b08f341..18e59fc 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -45,6 +45,7 @@
 
 #define CONFIG_S5P_PA_SYSRAM	0x02020000
 #define CONFIG_SMP_PEN_ADDR	CONFIG_S5P_PA_SYSRAM
+#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 
 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
 #define CONFIG_ARM_GIC_BASE_ADDRESS	0x10480000
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index d5888e8..50cd743 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -93,5 +93,6 @@
 /* Misc utility code */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CRC32_VERIFY
+#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 
 #endif /* __BCM_EP_BOARD_H */
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index b509a9c..9583e8c 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -16,5 +16,6 @@
 
 #define CONFIG_SYSFLAGS_ADDR	0x1c010030
 #define CONFIG_SMP_PEN_ADDR	CONFIG_SYSFLAGS_ADDR
+#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 
 #endif
-- 
cgit v0.10.2


From 62a3b7dd086ef8ceba91e99cceb19704efc1b482 Mon Sep 17 00:00:00 2001
From: "Robert P. J. Day" <rpjday@crashcourse.ca>
Date: Fri, 15 Jul 2016 13:44:45 -0400
Subject: Various, unrelated tree-wide typo fixes.

    Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

diff --git a/README b/README
index e906253..3c3b699 100644
--- a/README
+++ b/README
@@ -511,7 +511,7 @@ The following options need to be configured:
 		implemetation.
 
 		CONFIG_SYS_FSL_DDR2
-		Board config to use DDR2. It can be eanbeld for SoCs with
+		Board config to use DDR2. It can be enabled for SoCs with
 		Freescale DDR2 or DDR3 controllers, depending on the board
 		implementation.
 
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index afeaac8..bd6108e 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -21,7 +21,7 @@ config ARMV7_BOOT_SEC_DEFAULT
 	Say Y here to boot in secure mode by default even if non-secure mode
 	is supported. This option is useful to boot kernels which do not
 	suppport booting in non-secure mode. Only set this if you need it.
-	This can be overriden at run-time by setting the bootm_boot_mode env.
+	This can be overridden at run-time by setting the bootm_boot_mode env.
 	variable to "sec" or "nonsec".
 
 config ARMV7_VIRT
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index da5e052..7867c37 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -128,7 +128,7 @@ mcinitcmd:	This environment variable is defined to initiate MC and DPL deploymen
 		during U-boot booting.However the MC, DPC and DPL can be applied from
 		console independently.
 		The variable needs to be set from the console once and then on
-		rebooting the parameters set in the varible will automatically be
+		rebooting the parameters set in the variable will automatically be
 		executed. The commmand is demostrated taking an example of mc boot
 		using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
 
diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
index 58312a7..e10fc31 100644
--- a/arch/arm/cpu/armv8/zynqmp/mp.c
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -128,7 +128,7 @@ static void enable_clock_r5(void)
 	writel(tmp, &crlapb_base->cpu_r5_ctrl);
 
 	/* Give some delay for clock
-	 * to propogate */
+	 * to propagate */
 	udelay(0x500);
 }
 
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
index daf3c7e..9bc56f6 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -212,7 +212,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 			cr_setting++;
 		}
 
-	/* perform default PHY settings (may be overriden by custom settings */
+	/* perform default PHY settings (may be overridden by custom settings */
 	phy_setting = default_phy_settings;
 	while (phy_setting->phy_rnum >= 0) {
 		writel(phy_setting->setting,
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index 783bb3c..a3db7ed 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -20,7 +20,7 @@ void gpio_early_init(void);  /* overrideable GPIO config        */
 /*
  * Hooks to allow boards to set up the pinmux for a specific function.
  * Has to be implemented in the board files as we don't yet support pinmux
- * setup from FTD. If a board file does not implement one of those functions
+ * setup from FDT. If a board file does not implement one of those functions
  * an empty stub function will be called.
  */
 
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index e56031d..7daf8bc 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -324,7 +324,7 @@ enum periph_id clk_id_to_periph_id(int clk_id);
  * @param p post divider(DIVP)
  * @param cpcon base PLL charge pump(CPCON)
  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
- *              be overriden), 1 if PLL is already correct
+ *              be overridden), 1 if PLL is already correct
  */
 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
 
diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h
index ca6644a..c522faa 100644
--- a/arch/arm/include/asm/arch-tegra124/display.h
+++ b/arch/arm/include/asm/arch-tegra124/display.h
@@ -11,7 +11,7 @@
 /**
  * Register a new display based on device tree configuration.
  *
- * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * The frame buffer can be positioned by U-Boot or overridden by the fdt.
  * You should pass in the U-Boot address here, and check the contents of
  * struct fdt_disp_config to see what was actually chosen.
  *
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index c50d56d..36eabc8 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -510,7 +510,7 @@ unsigned clock_get_rate(enum clock_id clkid)
  * @param p post divider(DIVP)
  * @param cpcon base PLL charge pump(CPCON)
  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
- *		be overriden), 1 if PLL is already correct
+ *		be overridden), 1 if PLL is already correct
  */
 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 {
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 88c8e65..0addf84 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -30,7 +30,7 @@ u32 get_my_id()
  */
 int hold_cores_in_reset(int verbose)
 {
-	/* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
+	/* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
 	if (getenv_yesno("mp_holdoff") == 1) {
 		if (verbose) {
 			puts("Secondary cores are being held in reset.\n");
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index b432b18..5647d71 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -144,7 +144,7 @@
 #endif
 
 /*
- * Unless otherwise overriden, enable two 128MB cachable instruction regions
+ * Unless otherwise overridden, enable two 128MB cachable instruction regions
  * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
  * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
  */
diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h
index 4416190..260a831 100644
--- a/arch/powerpc/include/asm/status_led.h
+++ b/arch/powerpc/include/asm/status_led.h
@@ -7,7 +7,7 @@
 #ifndef __ASM_STATUS_LED_H__
 #define __ASM_STATUS_LED_H__
 
-/* if not overriden */
+/* if not overridden */
 #ifndef CONFIG_BOARD_SPECIFIC_LED
 # if defined(CONFIG_8xx)
 #  include <mpc8xx.h>
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index a42f3ec..0829b7f 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -53,7 +53,7 @@ int set_km_env(void)
 	sprintf((char *)buf, "0x%x", pnvramaddr);
 	setenv("pnvramaddr", (char *)buf);
 
-	/* try to read rootfssize (ram image) from envrionment */
+	/* try to read rootfssize (ram image) from environment */
 	p = getenv("rootfssize");
 	if (p != NULL)
 		strict_strtoul(p, 16, &rootfssize);
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
index 34ac697..77af184 100644
--- a/board/keymile/kmp204x/ddr.c
+++ b/board/keymile/kmp204x/ddr.c
@@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	/* we have only one module, half str should be OK */
 	popts->half_strength_driver_enable = 1;
 
-	/* wrlvl values overriden as recommended by ddr init func */
+	/* wrlvl values overridden as recommended by ddr init func */
 	popts->wrlvl_override = 1;
 	popts->wrlvl_sample = 0xf;
 	popts->wrlvl_start = 0x6;
diff --git a/cmd/i2c.c b/cmd/i2c.c
index 18ce789..473153f 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -178,7 +178,7 @@ static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
  * i2c_init_board() - Board-specific I2C bus init
  *
  * This function is the default no-op implementation of I2C bus
- * initialization. This function can be overriden by board-specific
+ * initialization. This function can be overridden by board-specific
  * implementation if needed.
  */
 __weak
diff --git a/common/env_common.c b/common/env_common.c
index 13db7dc..560cad0 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -145,7 +145,7 @@ int set_default_vars(int nvars, char * const vars[])
  * env_aes_cbc_get_key() - Get AES-128-CBC key for the environment
  *
  * This function shall return 16-byte array containing AES-128 key used
- * to encrypt and decrypt the environment. This function must be overriden
+ * to encrypt and decrypt the environment. This function must be overridden
  * by the implementer as otherwise the environment encryption will not
  * work.
  */
diff --git a/doc/README.gpt b/doc/README.gpt
index a6f6de6..3fcd835 100644
--- a/doc/README.gpt
+++ b/doc/README.gpt
@@ -165,7 +165,7 @@ To restore GUID partition table one needs to:
    The fields 'name' and 'size' are mandatory for every partition.
    The field 'start' is optional.
 
-   If field 'size' of the last partition is 0, the partiton is extended
+   If field 'size' of the last partition is 0, the partition is extended
    up to the end of the device.
 
    The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index b7cf62d..200f670 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -3,7 +3,7 @@ while other board support code dies a silent death caused by
 negligence in combination with ordinary bitrot.  Sometimes this goes
 by unnoticed, but often build errors will result.  If nobody cares any
 more to resolve such problems, then the code is really dead and will
-be removed from the U-Boot source tree.  The remainders rest in piece
+be removed from the U-Boot source tree.  The remainders rest in peace
 in the imperishable depths of the git history.  This document tries to
 maintain a list of such former fellows, so archaeologists can check
 easily if there is something they might want to dig for...
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index 4ed30df..b5a70da 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -12,7 +12,7 @@ When:	Release v2013.10
 
 Why:	As the 'mtest' command is no longer default, a number of platforms
 	have not opted to turn the command back on and thus provide unused
-	defines (which are likely to be propogated to new platforms from
+	defines (which are likely to be propagated to new platforms from
 	copy/paste).  Remove these defines when unused.
 
 Who:	Tom Rini <trini@ti.com>
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index 0ba9c0c..c2db121 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -35,7 +35,7 @@
 * Description:  This file includes subroutines which are related to
 *               programmed I/O and memory access. Included in this module
 *               are default functions that do nothing. For real uses these
-*               functions will have to be overriden by the user library.
+*               functions will have to be overridden by the user library.
 *
 ****************************************************************************/
 
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 1ac3a09..081bce5 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -107,7 +107,7 @@
  */
 #define HDR_REVERSE		0x00000800
 
-/* Propogate DNR property to SharedDesc */
+/* Propagate DNR property to SharedDesc */
 #define HDR_PROP_DNR		0x00000800
 
 /* JobDesc/SharedDesc share property */
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 1d5cec6..abd576b 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2212,7 +2212,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
 		 * Write leveling start time
 		 * The value use for the DQS_ADJUST for the first sample
 		 * when write leveling is enabled. It probably needs to be
-		 * overriden per platform.
+		 * overridden per platform.
 		 */
 		wrlvl_start = 0x8;
 		/*
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7e2f3e1..e0fb1b4 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -31,7 +31,7 @@ static void fpga_no_sup(char *fn, char *msg)
 	else if (msg)
 		printf("No support for %s.\n", msg);
 	else
-		printf("No FPGA suport!\n");
+		printf("No FPGA support!\n");
 }
 
 
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 79cf18f..e0adb9b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -10,7 +10,7 @@ config DM_MMC
 	bool "Enable MMC controllers using Driver Model"
 	depends on DM
 	help
-	  This enables the MultiMediaCard (MMC) uclass which suports MMC and
+	  This enables the MultiMediaCard (MMC) uclass which supports MMC and
 	  Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
 	  and non-removable (e.g. eMMC chip) devices are supported. These
 	  appear as block devices in U-Boot and can support filesystems such
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index c90a3a7..94fc5c1 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -976,7 +976,7 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  * counted, so we know the physical geometry. This enables us to make some
  * important configuration decisions.
  *
- * The return value of this function propogates directly back to this driver's
+ * The return value of this function propagates directly back to this driver's
  * call to nand_scan(). Anything other than zero will cause this driver to
  * tear everything down and declare failure.
  */
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 2032f65..38bd7a5 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -884,7 +884,7 @@ static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
  * Decode NAND parameters from the device tree
  *
  * @param blob	Device tree blob
- * @param node	Node containing "nand-flash" compatble node
+ * @param node	Node containing "nand-flash" compatible node
  * @return 0 if ok, -ve on error (FDT_ERR_...)
  */
 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c
index bb7c952..a71db76 100644
--- a/drivers/usb/musb-new/musb_dsps.c
+++ b/drivers/usb/musb-new/musb_dsps.c
@@ -627,7 +627,7 @@ static int __devinit dsps_probe(struct platform_device *pdev)
 	/* get memory resource */
 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iomem) {
-		dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
+		dev_err(&pdev->dev, "failed to get usbss mem resource\n");
 		ret = -ENODEV;
 		goto err1;
 	}
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 217f05f..92214d6 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -251,7 +251,7 @@ static int setup_window(struct disp_ctl_win *win,
 /**
  * Register a new display based on device tree configuration.
  *
- * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * The frame buffer can be positioned by U-Boot or overridden by the fdt.
  * You should pass in the U-Boot address here, and check the contents of
  * struct tegra_lcd_priv to see what was actually chosen.
  *
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 0882d5d..238b16d 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -120,7 +120,7 @@
 #define CONFIG_PL011_CLOCK		24000000
 #define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
 #define CONFIG_CONS_INDEX		0
-/* Default baudrate can be overriden by board! */
+/* Default baudrate can be overridden by board! */
 #ifndef CONFIG_BAUDRATE
 #define CONFIG_BAUDRATE			115200
 #endif
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 28c748d..5ebdf5b 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -55,7 +55,7 @@
 #define SDRAM_TAPDELAY		0x10000000
 
 /*
- * PCI - no suport
+ * PCI - no support
  */
 #undef CONFIG_PCI
 
diff --git a/include/net.h b/include/net.h
index 5ee5929..06320c6 100644
--- a/include/net.h
+++ b/include/net.h
@@ -238,7 +238,7 @@ int eth_getenv_enetaddr(const char *name, uchar *enetaddr);
 int eth_setenv_enetaddr(const char *name, const uchar *enetaddr);
 
 /**
- * eth_setenv_enetaddr_by_index() - set the MAC address envrionment variable
+ * eth_setenv_enetaddr_by_index() - set the MAC address environment variable
  *
  * This sets up an environment variable with the given MAC address (@enetaddr).
  * The environment variable to be set is defined by <@base_name><@index>addr.
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 02b4105..435e2a6 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -822,7 +822,7 @@ int himport_r(struct hsearch_data *htab,
 	 * (CONFIG_ENV_SIZE).  This heuristics will result in
 	 * unreasonably large numbers (and thus memory footprint) for
 	 * big flash environments (>8,000 entries for 64 KB
-	 * envrionment size), so we clip it to a reasonable value.
+	 * environment size), so we clip it to a reasonable value.
 	 * On the other hand we need to add some more entries for free
 	 * space when importing very small buffers. Both boundaries can
 	 * be overwritten in the board config file if needed.
diff --git a/net/eth_internal.h b/net/eth_internal.h
index 6e4753c..a14b208 100644
--- a/net/eth_internal.h
+++ b/net/eth_internal.h
@@ -13,7 +13,7 @@
 void eth_common_init(void);
 
 /**
- * eth_setenv_enetaddr_by_index() - set the MAC address envrionment variable
+ * eth_setenv_enetaddr_by_index() - set the MAC address environment variable
  *
  * This sets up an environment variable with the given MAC address (@enetaddr).
  * The environment variable to be set is defined by <@base_name><@index>addr.
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index 4c9a39b..8a4c56b 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -21,7 +21,7 @@
  *   CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
  *     is tested with a different frame length. Starting with
  *     MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
- *     Defaults to 10 and can be overriden in the board config header.
+ *     Defaults to 10 and can be overridden in the board config header.
  */
 
 #include <post.h>
diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config
index 6f216f9..776e16f 100644
--- a/tools/env/fw_env.config
+++ b/tools/env/fw_env.config
@@ -2,7 +2,7 @@
 # Up to two entries are valid, in this case the redundant
 # environment sector is assumed present.
 # Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
-# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# Futhermore, if the Flash sector size is omitted, this value is assumed to
 # be the same as the Environment size, which is valid for NOR and SPI-dataflash
 
 # NOR example
-- 
cgit v0.10.2


From f60d0603edca472c4458b30956f38c6c1a836d66 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 16 Jul 2016 18:36:44 -0600
Subject: test: Adjust the of-platdata test run condition

This should be spl_of_platdata, since otherwise it will try to run on boards
that don't support of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py
index c8b309e..457c405 100644
--- a/test/py/tests/test_ofplatdata.py
+++ b/test/py/tests/test_ofplatdata.py
@@ -34,7 +34,7 @@ string <NULL>
 stringarray "one" "" ""
 '''
 
-@pytest.mark.buildconfigspec('spl')
+@pytest.mark.buildconfigspec('spl_of_platdata')
 def test_ofplatdata(u_boot_console):
     """Test that of-platdata can be generated and used in sandbox"""
     cons = u_boot_console
-- 
cgit v0.10.2


From 67ff9e11f3971a668a0abd3efbb027ebf985b5b6 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Date: Sat, 9 Jul 2016 15:42:47 +0300
Subject: wandboard: move environment partition farther from u-boot.img

Recently I started to notice that u-boot.img built for Wandboard
by some toolchains becomes so large that it basically overlaps with
U-Boot environment area on SD-card.

According to
http://wiki.wandboard.org/index.php/Boot-process#sdcard_boot_data_layout
Wandboard's SD-card layout is as follows:
------------------------------>8---------------------------
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

==========================================================
1. 0x00000000           Reserved For MBR
2. 0x00000200   512     Secondary Image Table (optional)
3. 0x00000400   1024    uBoot Image (Starting From IVT)
4. 0x00060000   393216  start of uboot env (size:8k)
5. 0x00062000           end of uboot env
6. 0x00100000   1048576 Linux kernel start
7. 0x0076AC00   7777280 start of partition 1
------------------------------>8---------------------------

So for U-Boot we have 383kB (392192 bytes).

But in up to date U-Boot for Wandboard we build separately
 a) SPL
 b) u-boot.img

which gives us a bit more detailed SD-card layout:
------------------------------>8---------------------------
==========================================================
1. 0x00000000           Reserved For MBR
2. 0x00000200   512     Secondary Image Table (optional)
3. 0x00000400   1024    SPL
4. 0x00011400   70656   u-boot.img
5. 0x00060000   393216  start of uboot env (size:8k)
6. 0x00062000           end of uboot env
...
------------------------------>8---------------------------

>From that layout we may calculate amount of space reserved for
u-boot.img. It's just 315kb (322560 bytes).

Now if I build U-Boot with Sourcery CodeBench ARM 2014.05 produced
u-boot.img is already more than we expected
(323840 bytes instead of "< 322560"):
------------------------------>8---------------------------
ls -la u-boot.img
-rw-rw-r-- 1 user user 323840 Jul  5 07:38 u-boot.img
------------------------------>8---------------------------

Funny enough if I rebuild U-Boot with ARM toolchain available in
my Fedora 23 distro u-boot.img becomes a little bit smaller:
------------------------------>8---------------------------
ls -la u-boot.img
-rw-rw-r-- 1 user user 322216 Jul  5 07:39 u-boot.img
------------------------------>8---------------------------

What's worse this problem might not affect people most of the time
because what happens people would just copy u-boot.img on SD-card and
live in happiness with it... well until somebody attempts to save
environment in U-Boot with "saveenv" command which will simply
overwrite the very end of u-boot.img.
That will lead to unusable SD-card until user dd u-boot.img on
SD-card again.

I may foresee this issue in the future to become more visible once we
add more features in U-Boot for Wandboard or just existing code base
becomes bulkier and people will consistently get larger u-boot.img
files produced.

IMHO there's an obvious solution for all that - just move U-Boot's env
to the very end of the gap between U-Boot and the first real partition
on the SD-card. This patch will follow
8fb9eea5653796 ("mx6sabre_common: Fix U-Boot corruption after 'saveenv'").
So env is still not in the very end of the gap (obviously 256kb is way
too much for U-Boot's env) but at least we have now the same
partitioning for i.MX6 boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Peter Korsgaard <peter@korsgaard.com>
Cc: Wolfgang Denk <wd@denx.de>

diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 92af6543..2a00ff4 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -193,7 +193,7 @@
 #define CONFIG_ENV_SIZE			(8 * 1024)
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV		0
 
 #endif			       /* __CONFIG_H * */
-- 
cgit v0.10.2


From 88e4774efdf6ae4bf43969ad95ce67d0f228b91a Mon Sep 17 00:00:00 2001
From: Vanessa Maegima <vanessa.maegima@nxp.com>
Date: Wed, 13 Jul 2016 14:27:32 -0300
Subject: pico-imx6ul: Add PMIC support

Add PMIC support. Tested by command "pmic PFUZE3000 dump".

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c
index b0b8f05..5cbf803 100644
--- a/board/technexion/pico-imx6ul/pico-imx6ul.c
+++ b/board/technexion/pico-imx6ul/pico-imx6ul.c
@@ -14,13 +14,18 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
 #include <linux/sizes.h>
 #include <usb.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../../freescale/common/pfuze.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,6 +37,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
@@ -47,6 +57,23 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
 
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C2 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
 static iomux_v3_cfg_t const fec_pads[] = {
 	MX6_PAD_ENET1_TX_EN__ENET2_MDC		| MUX_PAD_CTRL(MDIO_PAD_CTRL),
 	MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO	| MUX_PAD_CTRL(MDIO_PAD_CTRL),
@@ -182,6 +209,45 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifdef CONFIG_POWER
+#define I2C_PMIC       0
+static struct pmic *pfuze;
+int power_init_board(void)
+{
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	pfuze = pmic_get("PFUZE3000");
+	ret = pmic_probe(pfuze);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
+	reg |= 0x1;
+	pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1B step ramp up time from 2us to 4us/25mV */
+	pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40);
+
+	/* SW1B mode to APS/PFM */
+	pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc);
+
+	/* SW1B standby voltage set to 0.975V */
+	pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb);
+
+	return 0;
+}
+#endif
+
 int board_usb_phy_mode(int port)
 {
 	if (port == 1)
@@ -211,6 +277,10 @@ int board_init(void)
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+	#ifdef CONFIG_SYS_I2C_MXC
+		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	#endif
+
 	setup_fec();
 	setup_usb();
 
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index f9fc263..a1e5f01 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -158,6 +158,18 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-- 
cgit v0.10.2


From f0f6724f86b4e86c8977f33a835a1b77352be7c4 Mon Sep 17 00:00:00 2001
From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Date: Tue, 12 Jul 2016 23:37:34 +0200
Subject: ARM: configs: cm_fx6: improve default environment

Currently, entire script segments have to be changed in the default
environment to change the kernel image location or to append kernel
cmdline parameters. In the later case this has to be changed for
every possible boot device.

Introduce new variables for kernel image locations and boot device
independent kernel parameters to make it easier to change these
settings.

Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Nikita Kiryanov <nikita@compulab.co.il>

diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 1f20ec3..f054ca8 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -69,6 +69,8 @@
 	"stderr=serial,vga\0" \
 	"panel=HDMI\0" \
 	"autoload=no\0" \
+	"uImage=uImage-cm-fx6\0" \
+	"zImage=zImage-cm-fx6\0" \
 	"kernel=uImage-cm-fx6\0" \
 	"script=boot.scr\0" \
 	"dtb=cm-fx6.dtb\0" \
@@ -81,10 +83,10 @@
 	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
 	"doboot=bootm ${loadaddr}\0" \
 	"doloadfdt=false\0" \
-	"setboottypez=setenv kernel zImage-cm-fx6;" \
+	"setboottypez=setenv kernel ${zImage};" \
 		"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
 		"setenv doloadfdt true;\0" \
-	"setboottypem=setenv kernel uImage-cm-fx6;" \
+	"setboottypem=setenv kernel ${uImage};" \
 		"setenv doboot bootm ${loadaddr};" \
 		"setenv doloadfdt false;\0"\
 	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
@@ -92,13 +94,13 @@
 	"nandroot=/dev/mtdblock4 rw\0" \
 	"nandrootfstype=ubifs\0" \
 	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
-		"${video}\0" \
+		"${video} ${extrabootargs}\0" \
 	"sataargs=setenv bootargs console=${console} root=${sataroot} " \
-		"${video}\0" \
+		"${video} ${extrabootargs}\0" \
 	"nandargs=setenv bootargs console=${console} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype} " \
-		"${video}\0" \
+		"${video} ${extrabootargs}\0" \
 	"nandboot=if run nandloadkernel; then " \
 			"run nandloadfdt;" \
 			"run setboottypem;" \
-- 
cgit v0.10.2


From f4ae23a7cd6fff3e0b9d250411b6714c6a1a2930 Mon Sep 17 00:00:00 2001
From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Date: Tue, 12 Jul 2016 23:37:35 +0200
Subject: fdt_support: define stub for fdt_fixup_mtdparts

Define an inline stub for fdt_fixup_mtdparts in the case that
CONFIG_FDT_FIXUP_PARTITIONS is not defined. This avoids the need
to guard every call to this function by a proper #ifdef in board
files.

Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Igor Grinberg <grinberg@compulab.co.il>

diff --git a/include/fdt_support.h b/include/fdt_support.h
index d34e959..7318098 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -172,7 +172,13 @@ int fdt_increase_size(void *fdt, int add_len);
 
 int fdt_fixup_nor_flash_size(void *blob);
 
+#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+#else
+static inline void fdt_fixup_mtdparts(void *fdt, void *node_info,
+					int node_info_size) {}
+#endif
+
 void fdt_del_node_and_alias(void *blob, const char *alias);
 u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr);
 int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
-- 
cgit v0.10.2


From 62d6bac66038163641d6ba43ac47347447fedb82 Mon Sep 17 00:00:00 2001
From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Date: Tue, 12 Jul 2016 23:37:36 +0200
Subject: ARM: board: cm_fx6: fixup mtd partitions in the fdt

The cm-fx6 module has an on-board st,m25p compatible spi flash chip
used for U-Boot (binary & environment). Overwrite the partitions in
the device tree by the partition table provided in the mtdparts
environment variable, if it is set.

This allows to specify a kernel independent partitioning in the
environment and provides a convient way for the user to adapt the
partition table.

Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>

diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 712057a..566c19b 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
+#include <mtd_node.h>
 #include <netdev.h>
 #include <errno.h>
 #include <usb.h>
@@ -28,6 +29,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dm/platform_data/serial_mxc.h>
+#include <jffs2/load_kernel.h>
 #include "common.h"
 #include "../common/eeprom.h"
 #include "../common/common.h"
@@ -581,6 +583,17 @@ int cm_fx6_setup_ecspi(void) { return 0; }
 
 #ifdef CONFIG_OF_BOARD_SETUP
 #define USDHC3_PATH	"/soc/aips-bus@02100000/usdhc@02198000/"
+
+struct node_info nodes[] = {
+	/*
+	 * Both entries target the same flash chip. The st,m25p compatible
+	 * is used in the vendor device trees, while upstream uses (the
+	 * documented) jedec,spi-nor comptatible.
+	 */
+	{ "st,m25p",	MTD_DEV_TYPE_NOR,	},
+	{ "jedec,spi-nor",	MTD_DEV_TYPE_NOR,	},
+};
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	u32 baseboard_rev;
@@ -589,6 +602,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	char baseboard_name[16];
 	int err;
 
+	fdt_shrink_to_minimum(blob); /* Make room for new properties */
+
 	/* MAC addr */
 	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 		fdt_find_and_setprop(blob,
@@ -607,7 +622,6 @@ int ft_board_setup(void *blob, bd_t *bd)
 		return 0; /* Assume not an early revision SB-FX6m baseboard */
 
 	if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
-		fdt_shrink_to_minimum(blob); /* Make room for new properties */
 		nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
 		fdt_delprop(blob, nodeoffset, "cd-gpios");
 		fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
@@ -616,6 +630,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 				     NULL, 0, 1);
 	}
 
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
 	return 0;
 }
 #endif
-- 
cgit v0.10.2


From 63a930937755e97928a75fa3afe2c09f1800188e Mon Sep 17 00:00:00 2001
From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Date: Tue, 12 Jul 2016 23:37:37 +0200
Subject: ARM: configs: cm_fx6: add mtd support

The cm-fx6 module has an on-board spi flash chip. Enable mtd support
and the mtdparts command. Also define a default partitioning, add
it to the default environment, and enable support to overwrite the
partitioning defined in a device tree by it. Finally, probe for the
chip on preboot to register the flash chip and, thus, establish the
connection between the mtd environment settings and the actual device.

These changes move the effective default partitioning from the device
tree shipped with the vendor kernels to U-Boot which becomes the single
point of definition for the partitioning for all device tree based
kernels (in particular, for the upstream Linux kernel which does not
have a default partitioning defined in its device tree).

Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>

diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index f054ca8..c839b03 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -18,6 +18,7 @@
 #define CONFIG_MACH_TYPE		4273
 
 /* CMD */
+#define CONFIG_CMD_MTDPARTS
 
 /* MMC */
 #define CONFIG_SYS_FSL_USDHC_NUM	3
@@ -53,6 +54,20 @@
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 #define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
 
+/* MTD support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_SPI_FLASH_MTD
+#endif
+
+#define MTDIDS_DEFAULT		"nor0=spi0.0"
+#define MTDPARTS_DEFAULT	"mtdparts=spi0.0:" \
+				"768k(uboot)," \
+				"256k(uboot-environment)," \
+				"-(reserved)"
+
 /* Environment */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
@@ -83,6 +98,8 @@
 	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
 	"doboot=bootm ${loadaddr}\0" \
 	"doloadfdt=false\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"setboottypez=setenv kernel ${zImage};" \
 		"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
 		"setenv doloadfdt true;\0" \
@@ -157,7 +174,7 @@
 	"run setupnandboot;" \
 	"run nandboot;"
 
-#define CONFIG_PREBOOT		"usb start"
+#define CONFIG_PREBOOT		"usb start;sf probe"
 
 /* SPI */
 #define CONFIG_SPI
-- 
cgit v0.10.2


From 4beba0668890f23373863dc27230679addd20689 Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Wed, 13 Jul 2016 16:37:01 -0300
Subject: warp7: Remove CONFIG_BOOTDELAY variable

It's not necessary anymore to declare the CONFIG_BOOTDELAY variable,
it's already set by default as 2 seconds.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 102b5b1..ad4fbbf 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -4,7 +4,6 @@ CONFIG_TARGET_WARP7=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
-CONFIG_BOOTDELAY=1
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
-- 
cgit v0.10.2


From 83fd908f28ca94baf095ba64b4b8a116dd473cb7 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 00:25:35 -0700
Subject: dm: imx: serial: Support DTE mode when using driver model

The MXC UART IP can be run in DTE or DCE mode. This depends on the
board wiring and the pinmux used and hence is board specific. This
extends platform data with a new field to choose wheather DTE
mode shall be used.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 1563bb3..1960bbc 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -76,6 +76,7 @@
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 #define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
+#define  UFCR_DCEDTE	 (1<<6)  /* DTE mode select */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 #define  USR1_RTSS	 (1<<14) /* RTS pin status */
@@ -150,6 +151,7 @@ static void mxc_serial_setbrg(void)
 	__REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
 		| (TXTL << UFCR_TXTL_SHF)
 		| (RXTL << UFCR_RXTL_SHF);
+	__REG(UART_PHYS + UFCR) |= UFCR_DCEDTE;
 	__REG(UART_PHYS + UBIR) = 0xf;
 	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
 
@@ -269,8 +271,13 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 	struct mxc_serial_platdata *plat = dev->platdata;
 	struct mxc_uart *const uart = plat->reg;
 	u32 clk = imx_get_uartclk();
+	u32 tmp;
+
+	tmp = 4 << UFCR_RFDIV_SHF;
+	if (plat->use_dte)
+		tmp |= UFCR_DCEDTE;
+	writel(tmp, &uart->fcr);
 
-	writel(4 << 7, &uart->fcr); /* divide input clock by 2 */
 	writel(0xf, &uart->bir);
 	writel(clk / (2 * baudrate), &uart->bmr);
 
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
index 7d3ace2..7bcd280 100644
--- a/include/dm/platform_data/serial_mxc.h
+++ b/include/dm/platform_data/serial_mxc.h
@@ -9,6 +9,7 @@
 /* Information about a serial port */
 struct mxc_serial_platdata {
 	struct mxc_uart *reg;  /* address of registers in physical memory */
+	bool use_dte;
 };
 
 #endif
-- 
cgit v0.10.2


From 2deebe2481c4a193c3c02e0a56b0b43039bcecb7 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 00:25:36 -0700
Subject: usb: move CONFIG_USB_EHCI_MX7 to Kconfig

Create an entry for "config USB_EHCI_MX7" in Kconfig and
switch over to it for all boards.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 09716a7..9dbc9c7 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -29,6 +29,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index ad4fbbf..bd9b5bb 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -22,4 +22,6 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_OF_LIBFDT=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 89580cc..7992cb4 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -74,6 +74,13 @@ config USB_EHCI_MX6
 	---help---
 	  Enables support for the on-chip EHCI controller on i.MX6 SoCs.
 
+config USB_EHCI_MX7
+	bool "Support for i.MX7 on-chip EHCI USB controller"
+	depends on ARCH_MX7
+	default y
+	---help---
+	  Enables support for the on-chip EHCI controller on i.MX7 SoCs.
+
 config USB_EHCI_MSM
 	bool "Support for Qualcomm on-chip EHCI USB controller"
 	depends on DM_USB
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index ece8a03..cfaf59b 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -237,8 +237,6 @@
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
 
 /* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX7
 #define CONFIG_USB_STORAGE
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_HOST_ETHER
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index fc0e51a..af39817 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -114,8 +114,6 @@
 #define CONFIG_MMCROOT			"/dev/mmcblk2p2"
 
 /* USB Configs */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX7
 #define CONFIG_USB_STORAGE
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
-- 
cgit v0.10.2


From 9a88180bfbb6ee7b2fba5516391ff0e611794de5 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 00:25:37 -0700
Subject: usb: ehci-mx6: configure power polarity in usb_power_config

USBNC_n_CTRL1 bit 9 actually controls the power pin polarity.
Rename UCTRL_PM to align reference manual and set the bit in
the appropriate callback usb_power_config.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 069f116..277f461 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -49,7 +49,7 @@
 #define USBNC_OFFSET		0x200
 #define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
 #define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
-#define UCTRL_PM                (1 << 9) /* OTG Power Mask */
+#define UCTRL_PWR_POL		(1 << 9) /* OTG Polarity of Power Pin */
 #define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
 #define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
 
@@ -207,12 +207,16 @@ static void usb_power_config(int index)
 	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 			(0x10000 * index) + USBNC_OFFSET);
 	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
 
 	/*
 	 * Clear the ACAENB to enable usb_otg_id detection,
 	 * otherwise it is the ACA detection enabled.
 	 */
 	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+
+	/* Set power polarity to high active */
+	setbits_le32(ctrl, UCTRL_PWR_POL);
 }
 
 int usb_phy_mode(int port)
@@ -250,11 +254,7 @@ static void usb_oc_config(int index)
 	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
 #endif
 
-#if defined(CONFIG_MX6)
 	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
-#elif defined(CONFIG_MX7)
-	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
-#endif
 }
 
 /**
-- 
cgit v0.10.2


From c4483093f38f20c4122bd27456bffdda518e4d71 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 00:25:38 -0700
Subject: usb: ehci-mx6: introduce config for high active power pin

Add a new config CONFIG_MXC_USB_OTG_HACTIVE which configures the
OTG Power Pin to be high active. Low active is the reset value
of the affected configuration register, hence the config option
is named by the non-reset configuration.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 9dbc9c7..d6dafcd 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -30,6 +30,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index bd9b5bb..3770669 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -24,4 +24,5 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_OF_LIBFDT=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 7992cb4..09db938 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -81,6 +81,15 @@ config USB_EHCI_MX7
 	---help---
 	  Enables support for the on-chip EHCI controller on i.MX7 SoCs.
 
+if USB_EHCI_MX7
+
+config MXC_USB_OTG_HACTIVE
+	bool "USB Power pin high active"
+	---help---
+	  Set the USB Power pin polarity to be high active (PWR_POL)
+
+endif
+
 config USB_EHCI_MSM
 	bool "Support for Qualcomm on-chip EHCI USB controller"
 	depends on DM_USB
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 277f461..8352c2b 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -216,7 +216,11 @@ static void usb_power_config(int index)
 	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
 
 	/* Set power polarity to high active */
+#ifdef CONFIG_MXC_USB_OTG_HACTIVE
 	setbits_le32(ctrl, UCTRL_PWR_POL);
+#else
+	clrbits_le32(ctrl, UCTRL_PWR_POL);
+#endif
 }
 
 int usb_phy_mode(int port)
-- 
cgit v0.10.2


From ec7fde3ebfeb1dc428206bf1afca87dbd86cc29b Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 00:25:39 -0700
Subject: mx7: set soc environment according to exact SoC type

This can be useful if the same U-Boot binary is used for boards
available with a i.MX 7Solo and i.MX 7Dual.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index ef46c92..dead1d3 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -248,6 +248,20 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (is_mx7d())
+		setenv("soc", "imx7d");
+	else
+		setenv("soc", "imx7s");
+#endif
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SERIAL_TAG
 void get_board_serial(struct tag_serialnr *serialnr)
 {
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index fbc6de6..bc2833c 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -28,6 +28,8 @@
 /* Enable iomux-lpsr support */
 #define CONFIG_IOMUX_LPSR
 
+#define CONFIG_ARCH_MISC_INIT
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-- 
cgit v0.10.2


From 47855a5c3bf8aa2ad2bd48016d48c89bc1e2641c Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Wed, 13 Jul 2016 00:25:40 -0700
Subject: mx7_common: Put display board info config into board file

CONFIG_DISPLAY_BOARDINFO should not be placed in mx7_common
because some boards might need a different config such as
CONFIG_DISPLAY_BOARDINFO_LATE. Move it to the board file
instead.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index bc2833c..5dd6207 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -31,7 +31,6 @@
 #define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_LOADADDR                 0x80800000
 #define CONFIG_SYS_TEXT_BASE            0x87800000
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index cfaf59b..822d81f 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -22,6 +22,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 
+#define CONFIG_DISPLAY_BOARDINFO
+
 /* Uncomment to enable secure boot support */
 /* #define CONFIG_SECURE_BOOT */
 #define CONFIG_CSF_SIZE			0x4000
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index af39817..4c6e23c 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -21,6 +21,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 
+#define CONFIG_DISPLAY_BOARDINFO
+
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
 #define CONFIG_SUPPORT_EMMC_BOOT
-- 
cgit v0.10.2


From be1a17ff689b0289bbf900813265e4525949eef7 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 00:25:41 -0700
Subject: mx7_common: use Kconfig for ARMv7 non-secure mode

Use existing Kconfig symbols to let the user configure whether to
build a U-Boot with non-secure mode support or not. This also allows
to enable virtualization extension easily.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index ecfa4a2..dd51384 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -3,6 +3,8 @@ if ARCH_MX7
 config MX7
 	bool
 	select ROM_UNIFIED_SECTIONS
+	select CPU_V7_HAS_VIRT
+	select CPU_V7_HAS_NONSEC
 	default y
 
 config MX7D
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index d6dafcd..b3a708e 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX7=y
 CONFIG_TARGET_MX7DSABRESD=y
+# CONFIG_ARMV7_VIRT is not set
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 3770669..5a68998 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX7=y
 CONFIG_TARGET_WARP7=y
+# CONFIG_ARMV7_VIRT is not set
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 5dd6207..9f80f9f 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -71,15 +71,8 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_MXC_OCOTP
 
-/*
- * Default boot linux kernel in no secure mode.
- * If want to boot kernel in secure mode, please define CONFIG_MX7_SEC
- */
-#ifndef CONFIG_MX7_SEC
-#define CONFIG_ARMV7_NONSEC
 #define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	0x00900000
-#endif
 
 #endif
-- 
cgit v0.10.2


From 8b248c8cdbdfa0f6a7a28b2e4ab0450af51603b2 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan@agner.ch>
Date: Wed, 13 Jul 2016 00:25:42 -0700
Subject: imx_watchdog: add weak attribute to reset_cpu function

This allows to overwrite reset_cpu function in case a board level
reset is preferred (e.g. through PMIC).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index f9f8175..2938d9f 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -39,7 +39,7 @@ void hw_watchdog_init(void)
 }
 #endif
 
-void reset_cpu(ulong addr)
+void __attribute__((weak)) reset_cpu(ulong addr)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-- 
cgit v0.10.2


From 5ad5823d0c71a45f886d0016a74d62a5216abe10 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 24 Jun 2016 16:46:23 -0700
Subject: armv8: layerscape: Convert to use common MMU framework

Drop platform code to create static MMU tables. Use common framework
to create MMU tables on the run. Tested on LS2080ARDB with secure and
non-secure ram scenarios.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index a397f5d..b6ebedc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -26,13 +26,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mm_region layerscape_mem_map[] = {
-	{
-		/* List terminator */
-		0,
-	}
-};
-struct mm_region *mem_map = layerscape_mem_map;
+struct mm_region *mem_map = early_map;
 
 void cpu_name(char *name)
 {
@@ -56,233 +50,35 @@ void cpu_name(char *name)
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-static void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-			u64 memory_type, u64 attribute)
-{
-       u64 value;
-
-       value = section | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
-       value |= PMD_ATTRINDX(memory_type);
-       value |= attribute;
-       page_table[index] = value;
-}
-
-static void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
-{
-       u64 value;
-
-       value = (u64)table_addr | PTE_TYPE_TABLE;
-       page_table[index] = value;
-}
-
-/*
- * Set the block entries according to the information of the table.
- */
-static int set_block_entry(const struct sys_mmu_table *list,
-			   struct table_info *table)
-{
-	u64 block_size = 0, block_shift = 0;
-	u64 block_addr, index;
-	int j;
-
-	if (table->entry_size == BLOCK_SIZE_L1) {
-		block_size = BLOCK_SIZE_L1;
-		block_shift = SECTION_SHIFT_L1;
-	} else if (table->entry_size == BLOCK_SIZE_L2) {
-		block_size = BLOCK_SIZE_L2;
-		block_shift = SECTION_SHIFT_L2;
-	} else {
-		return -EINVAL;
-	}
-
-	block_addr = list->phys_addr;
-	index = (list->virt_addr - table->table_base) >> block_shift;
-
-	for (j = 0; j < (list->size >> block_shift); j++) {
-		set_pgtable_section(table->ptr,
-				    index,
-				    block_addr,
-				    list->memory_type,
-				    list->attribute);
-		block_addr += block_size;
-		index++;
-	}
-
-	return 0;
-}
-
-/*
- * Find the corresponding table entry for the list.
- */
-static int find_table(const struct sys_mmu_table *list,
-		      struct table_info *table, u64 *level0_table)
-{
-	u64 index = 0, level = 0;
-	u64 *level_table = level0_table;
-	u64 temp_base = 0, block_size = 0, block_shift = 0;
-
-	while (level < 3) {
-		if (level == 0) {
-			block_size = BLOCK_SIZE_L0;
-			block_shift = SECTION_SHIFT_L0;
-		} else if (level == 1) {
-			block_size = BLOCK_SIZE_L1;
-			block_shift = SECTION_SHIFT_L1;
-		} else if (level == 2) {
-			block_size = BLOCK_SIZE_L2;
-			block_shift = SECTION_SHIFT_L2;
-		}
-
-		index = 0;
-		while (list->virt_addr >= temp_base) {
-			index++;
-			temp_base += block_size;
-		}
-
-		temp_base -= block_size;
-
-		if ((level_table[index - 1] & PTE_TYPE_MASK) ==
-		    PTE_TYPE_TABLE) {
-			level_table = (u64 *)(level_table[index - 1] &
-				      ~PTE_TYPE_MASK);
-			level++;
-			continue;
-		} else {
-			if (level == 0)
-				return -EINVAL;
-
-			if ((list->phys_addr + list->size) >
-			    (temp_base + block_size * NUM_OF_ENTRY))
-				return -EINVAL;
-
-			/*
-			 * Check the address and size of the list member is
-			 * aligned with the block size.
-			 */
-			if (((list->phys_addr & (block_size - 1)) != 0) ||
-			    ((list->size & (block_size - 1)) != 0))
-				return -EINVAL;
-
-			table->ptr = level_table;
-			table->table_base = temp_base -
-					    ((index - 1) << block_shift);
-			table->entry_size = block_size;
-
-			return 0;
-		}
-	}
-	return -EINVAL;
-}
-
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  * levels of translation tables here to cover 40-bit address space.
  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
- * Level 0 IA[39], table address @0
- * Level 1 IA[38:30], table address @0x1000, 0x2000
- * Level 2 IA[29:21], table address @0x3000, 0x4000
- * Address above 0x5000 is free for other purpose.
+ * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
+ * Note, the debug print in cache_v8.c is not usable for debugging
+ * these early MMU tables because UART is not yet available.
  */
 static inline void early_mmu_setup(void)
 {
-	unsigned int el, i;
-	u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
-	u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
-	u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
-	u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
-	u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
-
-	struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
+	unsigned int el = current_el();
 
-	/* Invalidate all table entries */
-	memset(level0_table, 0, 0x5000);
+	/* global data is already setup, no allocation yet */
+	gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
+	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 
-	/* Fill in the table entries */
-	set_pgtable_table(level0_table, 0, level1_table0);
-	set_pgtable_table(level0_table, 1, level1_table1);
-	set_pgtable_table(level1_table0, 0, level2_table0);
+	/* Create early page tables */
+	setup_pgtables();
 
-#ifdef CONFIG_FSL_LSCH3
-	set_pgtable_table(level1_table0,
-			  CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
-			  level2_table1);
-#elif defined(CONFIG_FSL_LSCH2)
-	set_pgtable_table(level1_table0, 1, level2_table1);
-#endif
-	/* Find the table and fill in the block entries */
-	for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
-		if (find_table(&early_mmu_table[i],
-			       &table, level0_table) == 0) {
-			/*
-			 * If find_table() returns error, it cannot be dealt
-			 * with here. Breakpoint can be added for debugging.
-			 */
-			set_block_entry(&early_mmu_table[i], &table);
-			/*
-			 * If set_block_entry() returns error, it cannot be
-			 * dealt with here too.
-			 */
-		}
-	}
-
-	el = current_el();
-
-	set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
+	/* point TTBR to the new table */
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+			  get_tcr(el, NULL, NULL) &
+			  ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 			  MEMORY_ATTRIBUTES);
-	set_sctlr(get_sctlr() | CR_M);
-}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-/*
- * Called from final mmu setup. The phys_addr is new, non-existing
- * address. A new sub table is created @level2_table_secure to cover
- * size of CONFIG_SYS_MEM_RESERVE_SECURE memory.
- */
-static inline int final_secure_ddr(u64 *level0_table,
-				   u64 *level2_table_secure,
-				   phys_addr_t phys_addr)
-{
-	int ret = -EINVAL;
-	struct table_info table = {};
-	struct sys_mmu_table ddr_entry = {
-		0, 0, BLOCK_SIZE_L1, MT_NORMAL,
-		PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-	};
-	u64 index;
-
-	/* Need to create a new table */
-	ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
-	ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
-	ret = find_table(&ddr_entry, &table, level0_table);
-	if (ret)
-		return ret;
-	index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1;
-	set_pgtable_table(table.ptr, index, level2_table_secure);
-	table.ptr = level2_table_secure;
-	table.table_base = ddr_entry.virt_addr;
-	table.entry_size = BLOCK_SIZE_L2;
-	ret = set_block_entry(&ddr_entry, &table);
-	if (ret) {
-		printf("MMU error: could not fill non-secure ddr block entries\n");
-		return ret;
-	}
-	ddr_entry.virt_addr = phys_addr;
-	ddr_entry.phys_addr = phys_addr;
-	ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE;
-	ddr_entry.attribute = PTE_BLOCK_OUTER_SHARE;
-	ret = find_table(&ddr_entry, &table, level0_table);
-	if (ret) {
-		printf("MMU error: could not find secure ddr table\n");
-		return ret;
-	}
-	ret = set_block_entry(&ddr_entry, &table);
-	if (ret)
-		printf("MMU error: could not set secure ddr block entry\n");
-
-	return ret;
+	set_sctlr(get_sctlr() | CR_M);
 }
-#endif
 
 /*
  * The final tables look similar to early tables, but different in detail.
@@ -291,113 +87,59 @@ static inline int final_secure_ddr(u64 *level0_table,
  *
  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
- *
- * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
- * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
- * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
- *
- * For LSCH3:
- * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
- * For LSCH2:
- * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
- * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
  */
 static inline void final_mmu_setup(void)
 {
+	u64 tlb_addr_save = gd->arch.tlb_addr;
 	unsigned int el = current_el();
-	unsigned int i;
-	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
-	u64 *level1_table0;
-	u64 *level1_table1;
-	u64 *level2_table0;
-	u64 *level2_table1;
-#ifdef CONFIG_FSL_LSCH2
-	u64 *level2_table2;
-#endif
-	struct table_info table = {NULL, 0, BLOCK_SIZE_L0};
-
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-	u64 *level2_table_secure;
-
-	if (el == 3) {
-		/*
-		 * Only use gd->arch.secure_ram if the address is recalculated
-		 * Align to 4KB for MMU table
-		 */
-		if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
-			level0_table = (u64 *)(gd->arch.secure_ram & ~0xfff);
-		else
-			printf("MMU warning: gd->arch.secure_ram is not maintained, disabled.\n");
-	}
-#endif
-	level1_table0 = level0_table + 512;
-	level1_table1 = level1_table0 + 512;
-	level2_table0 = level1_table1 + 512;
-	level2_table1 = level2_table0 + 512;
-#ifdef CONFIG_FSL_LSCH2
-	level2_table2 = level2_table1 + 512;
+	int index;
 #endif
-	table.ptr = level0_table;
 
-	/* Invalidate all table entries */
-	memset(level0_table, 0, PGTABLE_SIZE);
-
-	/* Fill in the table entries */
-	set_pgtable_table(level0_table, 0, level1_table0);
-	set_pgtable_table(level0_table, 1, level1_table1);
-	set_pgtable_table(level1_table0, 0, level2_table0);
-#ifdef CONFIG_FSL_LSCH3
-	set_pgtable_table(level1_table0,
-			  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
-			  level2_table1);
-#elif defined(CONFIG_FSL_LSCH2)
-	set_pgtable_table(level1_table0, 1, level2_table1);
-	set_pgtable_table(level1_table0,
-			  CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
-			  level2_table2);
-#endif
-
-	/* Find the table and fill in the block entries */
-	for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
-		if (find_table(&final_mmu_table[i],
-			       &table, level0_table) == 0) {
-			if (set_block_entry(&final_mmu_table[i],
-					    &table) != 0) {
-				printf("MMU error: could not set block entry for %p\n",
-				       &final_mmu_table[i]);
-			}
+	mem_map = final_map;
 
-		} else {
-			printf("MMU error: could not find the table for %p\n",
-			       &final_mmu_table[i]);
-		}
-	}
-	/* Set the secure memory to secure in MMU */
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-	if (el == 3 && gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
-#ifdef CONFIG_FSL_LSCH3
-		level2_table_secure = level2_table1 + 512;
-#elif defined(CONFIG_FSL_LSCH2)
-		level2_table_secure = level2_table2 + 512;
-#endif
-		if (!final_secure_ddr(level0_table,
-				      level2_table_secure,
-				      gd->arch.secure_ram & ~0x3)) {
+	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
+		if (el == 3) {
+			/*
+			 * Only use gd->arch.secure_ram if the address is
+			 * recalculated. Align to 4KB for MMU table.
+			 */
+			/* put page tables in secure ram */
+			index = ARRAY_SIZE(final_map) - 2;
+			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
+			final_map[index].virt = gd->arch.secure_ram & ~0x3;
+			final_map[index].phys = final_map[index].virt;
+			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
+			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
-			debug("Now MMU table is in secured memory at 0x%llx\n",
-			      gd->arch.secure_ram & ~0x3);
+			tlb_addr_save = gd->arch.tlb_addr;
 		} else {
-			printf("MMU warning: Failed to secure DDR\n");
+			/* Use allocated (board_f.c) memory for TLB */
+			tlb_addr_save = gd->arch.tlb_allocated;
+			gd->arch.tlb_addr = tlb_addr_save;
 		}
 	}
 #endif
 
+	/* Reset the fill ptr */
+	gd->arch.tlb_fillptr = tlb_addr_save;
+
+	/* Create normal system page tables */
+	setup_pgtables();
+
+	/* Create emergency page tables */
+	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
+	gd->arch.tlb_emerg = gd->arch.tlb_addr;
+	setup_pgtables();
+	gd->arch.tlb_addr = tlb_addr_save;
+
 	/* flush new MMU table */
-	flush_dcache_range((ulong)level0_table,
-			   (ulong)level0_table + gd->arch.tlb_size);
+	flush_dcache_range(gd->arch.tlb_addr,
+			   gd->arch.tlb_addr + gd->arch.tlb_size);
 
 	/* point TTBR to the new table */
-	set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 	/*
 	 * MMU is already enabled, just need to invalidate TLB to load the
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 197b0eb..5fd5e87 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -19,29 +19,6 @@ static struct cpu_type cpu_type_list[] = {
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 
-#define SECTION_SHIFT_L0		39UL
-#define SECTION_SHIFT_L1		30UL
-#define SECTION_SHIFT_L2		21UL
-#define BLOCK_SIZE_L0			0x8000000000
-#define BLOCK_SIZE_L1			0x40000000
-#define BLOCK_SIZE_L2			0x200000
-#define NUM_OF_ENTRY			512
-#define TCR_EL2_PS_40BIT		(2 << 16)
-
-#define LAYERSCAPE_VA_BITS		(40)
-#define LAYERSCAPE_TCR		(TCR_TG0_4K		| \
-				TCR_EL2_PS_40BIT	| \
-				TCR_SHARED_NON		| \
-				TCR_ORGN_NC		| \
-				TCR_IRGN_NC		| \
-				TCR_T0SZ(LAYERSCAPE_VA_BITS))
-#define LAYERSCAPE_TCR_FINAL	(TCR_TG0_4K		| \
-				TCR_EL2_PS_40BIT	| \
-				TCR_SHARED_OUTER	| \
-				TCR_ORGN_WBWA		| \
-				TCR_IRGN_WBWA		| \
-				TCR_T0SZ(LAYERSCAPE_VA_BITS))
-
 #ifdef CONFIG_FSL_LSCH3
 #define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
 #define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
@@ -101,174 +78,261 @@ static struct cpu_type cpu_type_list[] = {
 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
 #endif
 
-struct sys_mmu_table {
-	u64 virt_addr;
-	u64 phys_addr;
-	u64 size;
-	u64 memory_type;
-	u64 attribute;
-};
-
-struct table_info {
-	u64 *ptr;
-	u64 table_base;
-	u64 entry_size;
-};
-
-static const struct sys_mmu_table early_mmu_table[] = {
+#define EARLY_PGTABLE_SIZE 0x5000
+static struct mm_region early_map[] = {
 #ifdef CONFIG_FSL_LSCH3
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-	  CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
+	  CONFIG_SYS_FSL_QSPI_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 	/* For IFC Region #1, only the first 4MB is cache-enabled */
 	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE1_1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
-	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 #elif defined(CONFIG_FSL_LSCH2)
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_QSPI_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 #endif
+	{},	/* list terminator */
 };
 
-static const struct sys_mmu_table final_mmu_table[] = {
+static struct mm_region final_map[] = {
 #ifdef CONFIG_FSL_LSCH3
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-	  CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
+	  CONFIG_SYS_FSL_QSPI_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_QSPI_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-	  CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_MC_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-	  CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_NI_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	/* For QBMAN portal, only the first 64MB is cache-enabled */
 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_QBMAN_SIZE_1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
+	},
 	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 #ifdef CONFIG_LS2080A
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE4_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 #endif
 	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-	  CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_WRIOP1_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-	  CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_AIOP1_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-	  CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_PEBUF_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 #elif defined(CONFIG_FSL_LSCH2)
 	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
-	  CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_BOOTROM_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_CCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_DCSR_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_QSPI_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+	  CONFIG_SYS_FSL_IFC_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE1,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-	  CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_FSL_QBMAN_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE2,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
-	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
 	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-	  CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
-	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+	  CONFIG_SYS_FSL_DRAM_SIZE3,
+	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+	},
 #endif
-};
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+	{},	/* space holder for secure mem */
 #endif
+	{},
+};
+#endif	/* !CONFIG_SYS_DCACHE_OFF */
 
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 cpu_mask(void);
-- 
cgit v0.10.2


From 85cdf38e69bbf3b2bb67c8218c8e4cbf28f8759b Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 28 Jun 2016 20:18:12 +0800
Subject: armv8: fsl-layerscape: add i/d-cache enable function to enable_caches

This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.

Define the function mmu_setup() for fsl-layerscape to cover the weak
one.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b6ebedc..bcedf2c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -164,15 +164,21 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+void mmu_setup(void)
+{
+	final_mmu_setup();
+}
+
 /*
- * This function is called from lib/board.c.
- * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
- * There is no need to disable d-cache for this operation.
+ * This function is called from common/board_r.c.
+ * It recreates MMU table in main memory.
  */
 void enable_caches(void)
 {
-	final_mmu_setup();
+	mmu_setup();
 	__asm_invalidate_tlb_all();
+	icache_enable();
+	dcache_enable();
 }
 #endif
 
-- 
cgit v0.10.2


From b45db3b59035735a0479d8df260d2349cdc3c21c Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 28 Jun 2016 20:18:13 +0800
Subject: ARMv8: add the secure monitor firmware framework

This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the 'target exception level'
that is determined by the respective secure firmware.

So far, the framework support only FIT format image, and need to define
the name of which config node should be used in 'configurations' and
the name of property for the raw secure firmware image in that config.
The FIT image should be stored in Byte accessing memory, such as NOR
Flash, or else it should be copied to main memory to use this framework.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index bf8644c..ee9e009 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,7 @@ obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 obj-y	+= fwcall.o
+obj-$(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
 
 obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
new file mode 100644
index 0000000..e21e199
--- /dev/null
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/types.h>
+#include <asm/macro.h>
+#include <asm/armv8/sec_firmware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void c_runtime_cpu_setup(void);
+
+#define SEC_FIRMWARE_LOADED	0x1
+#define SEC_FIRMWARE_RUNNING	0x2
+#define SEC_FIRMWARE_ADDR_MASK	(~0x3)
+	/*
+	 * Secure firmware load addr
+	 * Flags used: 0x1 secure firmware has been loaded to secure memory
+	 *             0x2 secure firmware is running
+	 */
+	phys_addr_t sec_firmware_addr;
+
+static int sec_firmware_get_data(const void *sec_firmware_img,
+				const void **data, size_t *size)
+{
+	int conf_node_off, fw_node_off;
+	char *conf_node_name = NULL;
+	char *desc;
+	int ret;
+
+	conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
+
+	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
+	if (conf_node_off < 0) {
+		printf("SEC Firmware: %s: no such config\n", conf_node_name);
+		return -ENOENT;
+	}
+
+	fw_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
+			SEC_FIRMWARE_FIT_IMAGE);
+	if (fw_node_off < 0) {
+		printf("SEC Firmware: No '%s' in config\n",
+		       SEC_FIRMWARE_FIT_IMAGE);
+		return -ENOLINK;
+	}
+
+	/* Verify secure firmware image */
+	if (!(fit_image_verify(sec_firmware_img, fw_node_off))) {
+		printf("SEC Firmware: Bad firmware image (bad CRC)\n");
+		return -EINVAL;
+	}
+
+	if (fit_image_get_data(sec_firmware_img, fw_node_off, data, size)) {
+		printf("SEC Firmware: Can't get %s subimage data/size",
+		       SEC_FIRMWARE_FIT_IMAGE);
+		return -ENOENT;
+	}
+
+	ret = fit_get_desc(sec_firmware_img, fw_node_off, &desc);
+	if (ret)
+		printf("SEC Firmware: Can't get description\n");
+	else
+		printf("%s\n", desc);
+
+	return ret;
+}
+
+/*
+ * SEC Firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates raw
+ * image address and size values.
+ *
+ * Returns 0 on success and a negative errno on error task fail.
+ */
+static int sec_firmware_parse_image(const void *sec_firmware_img,
+					const void **raw_image_addr,
+					size_t *raw_image_size)
+{
+	int ret;
+
+	ret = sec_firmware_get_data(sec_firmware_img, raw_image_addr,
+					raw_image_size);
+	if (ret)
+		return ret;
+
+	debug("SEC Firmware: raw_image_addr = 0x%p, raw_image_size = 0x%lx\n",
+	      *raw_image_addr, *raw_image_size);
+
+	return 0;
+}
+
+static int sec_firmware_copy_image(const char *title,
+			 u64 image_addr, u32 image_size, u64 sec_firmware)
+{
+	debug("%s copied to address 0x%p\n", title, (void *)sec_firmware);
+	memcpy((void *)sec_firmware, (void *)image_addr, image_size);
+	flush_dcache_range(sec_firmware, sec_firmware + image_size);
+
+	return 0;
+}
+
+/*
+ * This function will parse the SEC Firmware image, and then load it
+ * to secure memory.
+ */
+static int sec_firmware_load_image(const void *sec_firmware_img)
+{
+	const void *raw_image_addr;
+	size_t raw_image_size = 0;
+	int ret;
+
+	/*
+	 * The Excetpion Level must be EL3 to load and initialize
+	 * the SEC Firmware.
+	 */
+	if (current_el() != 3) {
+		ret = -EACCES;
+		goto out;
+	}
+
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+	/*
+	 * The SEC Firmware must be stored in secure memory.
+	 * Append SEC Firmware to secure mmu table.
+	 */
+	if (!(gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED)) {
+		ret = -ENXIO;
+		goto out;
+	}
+
+	sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
+			gd->arch.tlb_size;
+#else
+#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#endif
+
+	/* Align SEC Firmware base address to 4K */
+	sec_firmware_addr = (sec_firmware_addr + 0xfff) & ~0xfff;
+	debug("SEC Firmware: Load address: 0x%llx\n",
+	      sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
+
+	ret = sec_firmware_parse_image(sec_firmware_img, &raw_image_addr,
+			&raw_image_size);
+	if (ret)
+		goto out;
+
+	/* TODO:
+	 * Check if the end addr of SEC Firmware has been extend the secure
+	 * memory.
+	 */
+
+	/* Copy the secure firmware to secure memory */
+	ret = sec_firmware_copy_image("SEC Firmware", (u64)raw_image_addr,
+			raw_image_size, sec_firmware_addr &
+			SEC_FIRMWARE_ADDR_MASK);
+	if (ret)
+		goto out;
+
+	sec_firmware_addr |= SEC_FIRMWARE_LOADED;
+	debug("SEC Firmware: Entry point: 0x%llx\n",
+	      sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
+
+	return 0;
+
+out:
+	printf("SEC Firmware: error (%d)\n", ret);
+	sec_firmware_addr = 0;
+
+	return ret;
+}
+
+static int sec_firmware_entry(u32 *eret_hold_l, u32 *eret_hold_h)
+{
+	const void *entry = (void *)(sec_firmware_addr &
+				SEC_FIRMWARE_ADDR_MASK);
+
+	return _sec_firmware_entry(entry, eret_hold_l, eret_hold_h);
+}
+
+/* Check the secure firmware FIT image */
+__weak bool sec_firmware_is_valid(const void *sec_firmware_img)
+{
+	if (fdt_check_header(sec_firmware_img)) {
+		printf("SEC Firmware: Bad firmware image (not a FIT image)\n");
+		return false;
+	}
+
+	if (!fit_check_format(sec_firmware_img)) {
+		printf("SEC Firmware: Bad firmware image (bad FIT header)\n");
+		return false;
+	}
+
+	return true;
+}
+
+#ifdef CONFIG_ARMV8_PSCI
+/*
+ * The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
+ * v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error
+ * number will be returned according to SMC Calling Conventions. But
+ * when getting the NOT_SUPPORTED error number, we cannot ensure if
+ * the PSCI version is v0.1 or other error occurred. So, PSCI v0.1
+ * won't be supported by this framework.
+ * And if the secure firmware isn't running, return NOT_SUPPORTED.
+ *
+ * The return value on success is PSCI version in format
+ * major[31:16]:minor[15:0].
+ */
+unsigned int sec_firmware_support_psci_version(void)
+{
+	if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
+		return _sec_firmware_support_psci_version();
+
+	return 0xffffffff;
+}
+#endif
+
+/*
+ * sec_firmware_init - Initialize the SEC Firmware
+ * @sec_firmware_img:	the SEC Firmware image address
+ * @eret_hold_l:	the address to hold exception return address low
+ * @eret_hold_h:	the address to hold exception return address high
+ */
+int sec_firmware_init(const void *sec_firmware_img,
+			u32 *eret_hold_l,
+			u32 *eret_hold_h)
+{
+	int ret;
+
+	if (!sec_firmware_is_valid(sec_firmware_img))
+		return -EINVAL;
+
+	ret = sec_firmware_load_image(sec_firmware_img);
+	if (ret) {
+		printf("SEC Firmware: Failed to load image\n");
+		return ret;
+	} else if (sec_firmware_addr & SEC_FIRMWARE_LOADED) {
+		ret = sec_firmware_entry(eret_hold_l, eret_hold_h);
+		if (ret) {
+			printf("SEC Firmware: Failed to initialize\n");
+			return ret;
+		}
+	}
+
+	debug("SEC Firmware: Return from SEC Firmware: current_el = %d\n",
+	      current_el());
+
+	/*
+	 * The PE will be turned into target EL when returned from
+	 * SEC Firmware.
+	 */
+	if (current_el() != SEC_FIRMWARE_TARGET_EL)
+		return -EACCES;
+
+	sec_firmware_addr |= SEC_FIRMWARE_RUNNING;
+
+	/* Set exception table and enable caches if it isn't EL3 */
+	if (current_el() != 3) {
+		c_runtime_cpu_setup();
+		enable_caches();
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S
new file mode 100644
index 0000000..0c6a462
--- /dev/null
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/macro.h>
+
+WEAK(_sec_firmware_entry)
+	/*
+	 * x0: Secure Firmware entry point
+	 * x1: Exception return address Low
+	 * x2: Exception return address High
+	 */
+
+	/* Save stack pointer for EL2 */
+	mov	x3, sp
+	msr	sp_el2, x3
+
+	/* Set exception return address hold pointer */
+        adr	x4, 1f
+        mov	x3, x4
+#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
+        rev	w3, w3
+#endif
+        str	w3, [x1]
+        lsr	x3, x4, #32
+#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT
+        rev	w3, w3
+#endif
+        str	w3, [x2]
+
+	/* Call SEC monitor */
+        br	x0
+
+1:
+        mov	x0, #0
+        ret
+ENDPROC(_sec_firmware_entry)
+
+#ifdef CONFIG_ARMV8_PSCI
+ENTRY(_sec_firmware_support_psci_version)
+	mov	x0, 0x84000000
+	mov	x1, 0x0
+	mov	x2, 0x0
+	mov	x3, 0x0
+	smc	#0
+	ret
+ENDPROC(_sec_firmware_support_psci_version)
+#endif
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
new file mode 100644
index 0000000..39a1333
--- /dev/null
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SEC_FIRMWARE_H_
+#define __SEC_FIRMWARE_H_
+
+int sec_firmware_init(const void *, u32 *, u32 *);
+int _sec_firmware_entry(const void *, u32 *, u32 *);
+bool sec_firmware_is_valid(const void *);
+#ifdef CONFIG_ARMV8_PSCI
+unsigned int sec_firmware_support_psci_version(void);
+unsigned int _sec_firmware_support_psci_version(void);
+#endif
+
+#endif /* __SEC_FIRMWARE_H_ */
-- 
cgit v0.10.2


From f1dd4cadd20c3b6b2454b7f293265caa66f27fee Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 28 Jun 2016 20:18:14 +0800
Subject: ARMv8/layerscape: Add FSL PPA support

The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.

Use the secure firmware framework to integrate FSL PPA into U-Boot.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index eb2cbc3..bcf6b48 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -10,6 +10,7 @@ obj-y += soc.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SPL) += spl.o
+obj-$(CONFIG_FSL_LS_PPA) += ppa.o
 
 ifneq ($(CONFIG_FSL_LSCH3),)
 obj-y += fsl_lsch3_speed.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
new file mode 100644
index 0000000..541b251
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <errno.h>
+#include <asm/system.h>
+#include <asm/types.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#elif defined(CONFIG_FSL_LSCH2)
+#include <asm/arch/immap_lsch2.h>
+#endif
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#include <asm/armv8/sec_firmware.h>
+#endif
+
+int ppa_init(void)
+{
+	const void *ppa_fit_addr;
+	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
+	int ret;
+
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+	ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+#else
+#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+#endif
+
+#ifdef CONFIG_FSL_LSCH3
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	boot_loc_ptr_l = &gur->bootlocptrl;
+	boot_loc_ptr_h = &gur->bootlocptrh;
+#elif defined(CONFIG_FSL_LSCH2)
+	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+	boot_loc_ptr_l = &scfg->scratchrw[1];
+	boot_loc_ptr_h = &scfg->scratchrw[0];
+#endif
+
+	debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
+	      boot_loc_ptr_l, boot_loc_ptr_h);
+	ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
+
+	return ret;
+}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
new file mode 100644
index 0000000..1f1442b
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_PPA_H_
+#define __FSL_PPA_H_
+
+#define SEC_FIRMWARE_FIT_IMAGE		"firmware"
+#define SEC_FIRMEWARE_FIT_CNF_NAME	"config@1"
+#define SEC_FIRMWARE_TARGET_EL		2
+
+int ppa_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index 39a1333..eb68185 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -7,6 +7,10 @@
 #ifndef __SEC_FIRMWARE_H_
 #define __SEC_FIRMWARE_H_
 
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
-- 
cgit v0.10.2


From 032d5bb4aed40f1d0de0698501fcacee594caabc Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 28 Jun 2016 20:18:15 +0800
Subject: ARMv8/Layerscape: switch SMP method accordingly

If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bcedf2c..7a2ec6b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -23,6 +23,9 @@
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#include <asm/armv8/sec_firmware.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -364,6 +367,7 @@ int arch_early_init_r(void)
 {
 #ifdef CONFIG_MP
 	int rv = 1;
+	u32 psci_ver = 0xffffffff;
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
@@ -371,9 +375,15 @@ int arch_early_init_r(void)
 #endif
 
 #ifdef CONFIG_MP
-	rv = fsl_layerscape_wake_seconday_cores();
-	if (rv)
-		printf("Did not wake secondary cores\n");
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+	/* Check the psci version to determine if the psci is supported */
+	psci_ver = sec_firmware_support_psci_version();
+#endif
+	if (psci_ver == 0xffffffff) {
+		rv = fsl_layerscape_wake_seconday_cores();
+		if (rv)
+			printf("Did not wake secondary cores\n");
+	}
 #endif
 
 #ifdef CONFIG_SYS_HAS_SERDES
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index d17227a..40d6a76 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -22,6 +22,9 @@
 #endif
 #include <fsl_sec.h>
 #include <asm/arch-fsl-layerscape/soc.h>
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#include <asm/armv8/sec_firmware.h>
+#endif
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -38,7 +41,37 @@ void ft_fixup_cpu(void *blob)
 	int addr_cells;
 	u64 val, core_id;
 	size_t *boot_code_size = &(__secondary_boot_code_size);
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+	int node;
+	u32 psci_ver;
+
+	/* Check the psci version to determine if the psci is supported */
+	psci_ver = sec_firmware_support_psci_version();
+	if (psci_ver == 0xffffffff) {
+		/* remove psci DT node */
+		node = fdt_path_offset(blob, "/psci");
+		if (node >= 0)
+			goto remove_psci_node;
+
+		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci");
+		if (node >= 0)
+			goto remove_psci_node;
+
+		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2");
+		if (node >= 0)
+			goto remove_psci_node;
 
+		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0");
+		if (node >= 0)
+			goto remove_psci_node;
+
+remove_psci_node:
+		if (node >= 0)
+			fdt_del_node(blob, node);
+	} else {
+		return;
+	}
+#endif
 	off = fdt_path_offset(blob, "/cpus");
 	if (off < 0) {
 		puts("couldn't find /cpus node\n");
-- 
cgit v0.10.2


From 45684ae37bf96b455a1d4a957b80551dc2c85959 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 28 Jun 2016 20:18:16 +0800
Subject: ARMv8/PSCI: Fixup the device tree for PSCI

Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..707dad4 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -26,69 +26,6 @@
 #include <asm/armv7.h>
 #include <asm/psci.h>
 
-static int fdt_psci(void *fdt)
-{
-#ifdef CONFIG_ARMV7_PSCI
-	int nodeoff;
-	int tmp;
-
-	nodeoff = fdt_path_offset(fdt, "/cpus");
-	if (nodeoff < 0) {
-		printf("couldn't find /cpus\n");
-		return nodeoff;
-	}
-
-	/* add 'enable-method = "psci"' to each cpu node */
-	for (tmp = fdt_first_subnode(fdt, nodeoff);
-	     tmp >= 0;
-	     tmp = fdt_next_subnode(fdt, tmp)) {
-		const struct fdt_property *prop;
-		int len;
-
-		prop = fdt_get_property(fdt, tmp, "device_type", &len);
-		if (!prop)
-			continue;
-		if (len < 4)
-			continue;
-		if (strcmp(prop->data, "cpu"))
-			continue;
-
-		fdt_setprop_string(fdt, tmp, "enable-method", "psci");
-	}
-
-	nodeoff = fdt_path_offset(fdt, "/psci");
-	if (nodeoff < 0) {
-		nodeoff = fdt_path_offset(fdt, "/");
-		if (nodeoff < 0)
-			return nodeoff;
-
-		nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
-		if (nodeoff < 0)
-			return nodeoff;
-	}
-
-	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
-	if (tmp)
-		return tmp;
-#endif
-	return 0;
-}
-
 int armv7_apply_memory_carveout(u64 *start, u64 *size)
 {
 #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index ee9e009..33e6db0 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,7 @@ obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 obj-y	+= fwcall.o
+obj-y	+= cpu-dt.o
 obj-$(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
 
 obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
new file mode 100644
index 0000000..9ffb49c
--- /dev/null
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/psci.h>
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#include <asm/armv8/sec_firmware.h>
+#endif
+
+int psci_update_dt(void *fdt)
+{
+#ifdef CONFIG_MP
+#if defined(CONFIG_ARMV8_PSCI)
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+	/*
+	 * If the PSCI in SEC Firmware didn't work, avoid to update the
+	 * device node of PSCI. But still return 0 instead of an error
+	 * number to support detecting PSCI dynamically and then switching
+	 * the SMP boot method between PSCI and spin-table.
+	 */
+	if (sec_firmware_support_psci_version() == 0xffffffff)
+		return 0;
+#endif
+	fdt_psci(fdt);
+#endif
+#endif
+	return 0;
+}
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index bc5edda..f92633b 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -57,6 +57,7 @@ void psci_cpu_off_common(void);
 
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
+int fdt_psci(void *fdt);
 #endif /* ! __ASSEMBLY__ */
 
 #endif /* __ARM_PSCI_H__ */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0e05e87..f406419 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -55,6 +55,8 @@ ifndef CONFIG_ARM64
 obj-y	+= cache-cp15.o
 endif
 
+obj-y	+= psci-dt.o
+
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
 
 # For EABI conformant tool chains, provide eabi_compat()
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 76b75d8..fe5b488 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -45,7 +45,7 @@ int arch_fixup_fdt(void *blob)
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_ARMV7_NONSEC
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
 	ret = psci_update_dt(blob);
 	if (ret)
 		return ret;
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
new file mode 100644
index 0000000..8dc31d4
--- /dev/null
+++ b/arch/arm/lib/psci-dt.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include <linux/kernel.h>
+#include <asm/psci.h>
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#include <asm/armv8/sec_firmware.h>
+#endif
+
+int fdt_psci(void *fdt)
+{
+#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+	int nodeoff;
+	unsigned int psci_ver = 0;
+	char *psci_compt;
+	int tmp;
+
+	nodeoff = fdt_path_offset(fdt, "/cpus");
+	if (nodeoff < 0) {
+		printf("couldn't find /cpus\n");
+		return nodeoff;
+	}
+
+	/* add 'enable-method = "psci"' to each cpu node */
+	for (tmp = fdt_first_subnode(fdt, nodeoff);
+	     tmp >= 0;
+	     tmp = fdt_next_subnode(fdt, tmp)) {
+		const struct fdt_property *prop;
+		int len;
+
+		prop = fdt_get_property(fdt, tmp, "device_type", &len);
+		if (!prop)
+			continue;
+		if (len < 4)
+			continue;
+		if (strcmp(prop->data, "cpu"))
+			continue;
+
+		/*
+		 * Not checking rv here, our approach is to skip over errors in
+		 * individual cpu nodes, hopefully some of the nodes are
+		 * processed correctly and those will boot
+		 */
+		fdt_setprop_string(fdt, tmp, "enable-method", "psci");
+	}
+
+	/*
+	 * The PSCI node might be called "/psci" or might be called something
+	 * else but contain either of the compatible strings
+	 * "arm,psci"/"arm,psci-0.2"
+	 */
+	nodeoff = fdt_path_offset(fdt, "/psci");
+	if (nodeoff >= 0)
+		goto init_psci_node;
+
+	nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci");
+	if (nodeoff >= 0)
+		goto init_psci_node;
+
+	nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci-0.2");
+	if (nodeoff >= 0)
+		goto init_psci_node;
+
+	nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci-1.0");
+	if (nodeoff >= 0)
+		goto init_psci_node;
+
+	nodeoff = fdt_path_offset(fdt, "/");
+	if (nodeoff < 0)
+		return nodeoff;
+
+	nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
+	if (nodeoff < 0)
+		return nodeoff;
+
+init_psci_node:
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+	psci_ver = sec_firmware_support_psci_version();
+#endif
+	switch (psci_ver) {
+	case 0x00010000:
+		psci_compt = "arm,psci-1.0";
+		break;
+	case 0x00000002:
+		psci_compt = "arm,psci-0.2";
+		break;
+	default:
+		psci_compt = "arm,psci";
+		break;
+	}
+
+	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", psci_compt);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
+	if (tmp)
+		return tmp;
+
+#ifdef CONFIG_ARMV7_PSCI
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend",
+				ARM_PSCI_FN_CPU_SUSPEND);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
+	if (tmp)
+		return tmp;
+	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
+	if (tmp)
+		return tmp;
+#endif
+#endif
+	return 0;
+}
-- 
cgit v0.10.2


From 0e68a3694d1f33c69be7d1cec5a4261aa1d3d01d Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 28 Jun 2016 20:18:17 +0800
Subject: ARMv8/ls1043ardb: Integrate FSL PPA

The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 1436520..d3e37b4 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -24,7 +24,9 @@
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
 #endif
-
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +94,10 @@ int board_init(void)
 	enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
 #ifdef CONFIG_U_QE
 	u_qe_init();
 #endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 94ddfb1..44f86fa 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -9,6 +9,17 @@
 
 #include "ls1043a_common.h"
 
+#if defined(CONFIG_FSL_LS_PPA)
+#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+#define SEC_FIRMWARE_ERET_ADDR_REVERT
+#define CONFIG_ARMV8_PSCI
+
+#define CONFIG_SYS_LS_PPA_FW_IN_NOR
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#define	CONFIG_SYS_LS_PPA_FW_ADDR	0x60500000
+#endif
+#endif
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-- 
cgit v0.10.2


From 95cee94bd80c8dfbd5ac3b019782b55f4edebdeb Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Tue, 19 Jul 2016 19:39:45 +0200
Subject: Revert "arch-mx6: fix MX6_PAD_DECLARE macro to work with MX6
 duallite"

This reverts commit 225126da99dd9ba1478e32468e298085d1e3fb61.

Signed-off-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 3465205..4b6bb18 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -18,7 +18,7 @@ enum {
 #include "mx6q_pins.h"
 #undef MX6_PAD_DECL
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
-	MX6_PAD_DECLARE(MX6DL_PAD_, name, pco, mc, mm, sio, si, pc),
+	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
 #elif defined(CONFIG_MX6Q)
@@ -30,7 +30,7 @@ enum {
 #elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
-	MX6_PAD_DECLARE(MX6DL_PAD_, name, pco, mc, mm, sio, si, pc),
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
 #elif defined(CONFIG_MX6SL)
-- 
cgit v0.10.2


From 55edb9d4d521ff733d217ddf47ad7bf4650676be Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 18 Jul 2016 14:10:37 +0200
Subject: mtd: cfi_flash: fix polling for bit XSR.7 on Intel chips

flash_full_status_check() checks bit XSR.7 on Intel chips. This
should be done by only checking bit 7 and not by comparing the
whole status byte or word with 0x80.

This fixes the non-working block erase in the pflash emulation
of Qemu when used with the MIPS Malta board. MIPS Malta uses x32
mode to access the pflash device. In x32 mode Qemu mirrors the
lower 16 bits of the status word into the upper 16 bits. Thus
the CFI driver gets a status word of 0x8080 in x32 mode. If
flash_full_status_check() uses flash_isequal(), then it polls for
XSR.7 by comparing 0x8080 with 0x80 which never becomes true.

Reported-by: Alon Bar-Lev <alon.barlev@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 8ccaff0..33c4a93 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -608,7 +608,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
 	case CFI_CMDSET_INTEL_EXTENDED:
 	case CFI_CMDSET_INTEL_STANDARD:
 		if ((retcode == ERR_OK)
-		    && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
+		    && !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
 			retcode = ERR_INVAL;
 			printf ("Flash %s error at address %lx\n", prompt,
 				info->start[sector]);
-- 
cgit v0.10.2


From 8f2e2f15ffa1bb03b6e6e189312426059f3215d1 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Mon, 18 Jul 2016 10:19:28 -0300
Subject: mx6: clock: Fix the logic for reading axi_alt_sel

According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:

"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "

The current logic is inverted, so fix it to match the reference manual.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 9b4b69c..b3c9dcc 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -433,9 +433,9 @@ static u32 get_axi_clk(void)
 
 	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
-			root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
-		else
 			root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
+		else
+			root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 	} else
 		root_freq = get_periph_clk();
 
-- 
cgit v0.10.2


From 7f25fdc7ffab4f7cf80b34ca35600091cdf79b5d Mon Sep 17 00:00:00 2001
From: Benjamin Kamath <bkamath@spaceflight.com>
Date: Wed, 29 Jun 2016 16:44:38 -0700
Subject: powerpc: MPC8544DS: revert typo in I2C offset value

I2C offset was changed by commit 00f792e0 (added multibus support)
from 0x3100 to 0x3000. This typo leads to error when reading SPD
from DDR DIMMs.

Signed-off-by: Benjamin Kamath <bkamath@spaceflight.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b9d97c1..321f71e 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 
-- 
cgit v0.10.2


From 5d219d46aa6763639eeac5f08813ed4dc6982728 Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Wed, 20 Jul 2016 16:34:34 -0300
Subject: serial_mxc: Remove unconditional DCE setting

Commit 83fd908f28c ("dm: imx: serial: Support DTE mode when using driver
model") breaks the serial output for the imx boards that do not use
the serial driver model.

The reason for the breakage is that it's setting UFCR_DCEDTE
unconditionally for the non-dm case.

So keep the original behavior by removing UFCR_DCEDTE setting in the
non-dm case.

Tested on mx7sabresd and mx6wandboard.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 1960bbc..8545714 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -151,7 +151,6 @@ static void mxc_serial_setbrg(void)
 	__REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
 		| (TXTL << UFCR_TXTL_SHF)
 		| (RXTL << UFCR_RXTL_SHF);
-	__REG(UART_PHYS + UFCR) |= UFCR_DCEDTE;
 	__REG(UART_PHYS + UBIR) = 0xf;
 	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
 
-- 
cgit v0.10.2


From 68b09b891323b6f44e145164dfe3e1cd3322cc36 Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Wed, 20 Jul 2016 16:55:32 -0300
Subject: Revert "imx_common: Return MMCSD_MODE_FS in spl_boot_mode() also for
 EXTFS"

Commit c1ebf54868359005 ("imx_common: Return MMCSD_MODE_FS in spl_boot_mode()
also for EXTFS") causes SPL breakage on wandboard:

ERROR: v7_dcache_inval_range - start address is not aligned - 0x1820006c
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1820086c
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1820006c
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1820086c
** First descriptor is NOT a primary desc on 0:1 **
spl: no partition table found
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

This error is seen when SPL and u-boot.img are stored in the raw SD card
partition.

This reverts commit c1ebf54868359005c32944c1473668d5fcaca158.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index 0c1e401..bdcda7d 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -76,7 +76,7 @@ u32 spl_boot_mode(const u32 boot_device)
 	/* for MMC return either RAW or FAT mode */
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#if defined(CONFIG_SPL_FAT_SUPPORT)
 		return MMCSD_MODE_FS;
 #elif defined(CONFIG_SUPPORT_EMMC_BOOT)
 		return MMCSD_MODE_EMMCBOOT;
-- 
cgit v0.10.2


From ff87b0810753cfaec0e3094aa9fda8b12d6ca569 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Jul 2016 15:16:00 +0900
Subject: image: fix IH_ARCH_... values for uImage compatibility

Commit 555f45d8f916 ("image: Convert the IH_... values to enums")
accidentally changed some IH_ARCH_... values.

Prior to that commit, there existed a gap between IH_ARCH_M68K and
IH_ARCH_MICROBLAZE, like follows.

  #define IH_ARCH_SPARC64         11      /* Sparc 64 Bit */
  #define IH_ARCH_M68K            12      /* M68K         */
  #define IH_ARCH_MICROBLAZE      14      /* MicroBlaze   */
  #define IH_ARCH_NIOS2           15      /* Nios-II      */

The enum conversion broke the compatibility with existing uImage
files.  Reverting 555f45d8f916 will cause build error unfortunately,
so here is a more easy fix.

I dug the git history and figured out the gap was introduced by
commit 1117cbf2adac ("nios: remove nios-32 arch").  So, I revived
IH_ARCH_NIOS just for filling the gap.

I added comments to each enum block.  Once we assign a value to
IH_... it is not allowed to change it.

Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/include/image.h b/include/image.h
index 2a5b560..734def3 100644
--- a/include/image.h
+++ b/include/image.h
@@ -134,6 +134,9 @@ enum ih_category {
 
 /*
  * Operating System Codes
+ *
+ * The following are exposed to uImage header.
+ * Do not change values for backward compatibility.
  */
 enum {
 	IH_OS_INVALID		= 0,	/* Invalid OS	*/
@@ -167,6 +170,9 @@ enum {
 
 /*
  * CPU Architecture Codes (supported by Linux)
+ *
+ * The following are exposed to uImage header.
+ * Do not change values for backward compatibility.
  */
 enum {
 	IH_ARCH_INVALID		= 0,	/* Invalid CPU	*/
@@ -182,6 +188,7 @@ enum {
 	IH_ARCH_SPARC,			/* Sparc	*/
 	IH_ARCH_SPARC64,		/* Sparc 64 Bit */
 	IH_ARCH_M68K,			/* M68K		*/
+	IH_ARCH_NIOS,			/* Nios-32	*/
 	IH_ARCH_MICROBLAZE,		/* MicroBlaze   */
 	IH_ARCH_NIOS2,			/* Nios-II	*/
 	IH_ARCH_BLACKFIN,		/* Blackfin	*/
@@ -234,6 +241,9 @@ enum {
  *	U-Boot's command interpreter; this feature is especially
  *	useful when you configure U-Boot to use a real shell (hush)
  *	as command interpreter (=> Shell Scripts).
+ *
+ * The following are exposed to uImage header.
+ * Do not change values for backward compatibility.
  */
 
 enum {
@@ -273,6 +283,9 @@ enum {
 
 /*
  * Compression Types
+ *
+ * The following are exposed to uImage header.
+ * Do not change values for backward compatibility.
  */
 enum {
 	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
-- 
cgit v0.10.2


From 0388634a6ce9f0167747a3abac29001e2abc3879 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 12:15:03 -0600
Subject: ARM: tegra: fix Tegra186 DT GPIO binding header

Tegra186 uses different GPIO port IDs compared to previous chips. Make
sure the SoC DT file includes the correct GPIO binding header.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index fce34fa6..99d4925 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -1,5 +1,5 @@
 #include "skeleton.dtsi"
-#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/gpio/tegra186-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra-hsp.h>
 
-- 
cgit v0.10.2


From 1f60f0731db2e07eecc41afa92bee4b10e7d9f1f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 12:15:04 -0600
Subject: ARM: tegra: split p2771-0000 build

There are multiple versions of p2771-0000 board. There are SW visible
incompatible differences between the versions, and they are relevant to
U-Boot. Create separate "A02" and "B00" defconfigs (named after the first
and/or only board rev the defconfig supports) so that users can select
which build they want.

With the minimal set of HW currently enabled in U-Boot, the differences
are irrelevant, hence the DT files aren't different. However, that will
change in a future patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index acecb7c..ca8712a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -53,7 +53,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-nyan-big.dtb \
 	tegra124-venice2.dtb \
-	tegra186-p2771-0000.dtb \
+	tegra186-p2771-0000-a02.dtb \
+	tegra186-p2771-0000-b00.dtb \
 	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
diff --git a/arch/arm/dts/tegra186-p2771-0000-a02.dts b/arch/arm/dts/tegra186-p2771-0000-a02.dts
new file mode 100644
index 0000000..70f4326
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000-a02.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "tegra186-p2771-0000.dtsi"
+
+/ {
+	model = "NVIDIA P2771-0000 A02";
+	compatible = "nvidia,p2771-0000-a02", "nvidia,p2771-0000", "nvidia,tegra186";
+};
diff --git a/arch/arm/dts/tegra186-p2771-0000-b00.dts b/arch/arm/dts/tegra186-p2771-0000-b00.dts
new file mode 100644
index 0000000..2384a65
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000-b00.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "tegra186-p2771-0000.dtsi"
+
+/ {
+	model = "NVIDIA P2771-0000 B00";
+	compatible = "nvidia,p2771-0000-b00", "nvidia,p2771-0000", "nvidia,tegra186";
+};
diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts
deleted file mode 100644
index 5f29ee4..0000000
--- a/arch/arm/dts/tegra186-p2771-0000.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-/dts-v1/;
-
-#include "tegra186.dtsi"
-
-/ {
-	model = "NVIDIA P2771-0000";
-	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
-
-	chosen {
-		stdout-path = &uarta;
-	};
-
-	aliases {
-		sdhci0 = "/sdhci@3460000";
-	};
-
-	memory {
-		reg = <0x0 0x80000000 0x0 0x60000000>;
-	};
-
-	sdhci@3460000 {
-		status = "okay";
-		bus-width = <8>;
-	};
-};
diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi
new file mode 100644
index 0000000..87f0427
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000.dtsi
@@ -0,0 +1,23 @@
+#include "tegra186.dtsi"
+
+/ {
+	model = "NVIDIA P2771-0000";
+	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		sdhci0 = "/sdhci@3460000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x60000000>;
+	};
+
+	sdhci@3460000 {
+		status = "okay";
+		bus-width = <8>;
+	};
+};
diff --git a/configs/p2771-0000-a02_defconfig b/configs/p2771-0000-a02_defconfig
new file mode 100644
index 0000000..1fe25f5
--- /dev/null
+++ b/configs/p2771-0000-a02_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-a02"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000 A02) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/p2771-0000-b00_defconfig b/configs/p2771-0000-b00_defconfig
new file mode 100644
index 0000000..552fb6c
--- /dev/null
+++ b/configs/p2771-0000-b00_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_TARGET_P2771_0000=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-b00"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000 B00) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
deleted file mode 100644
index 9f2c418..0000000
--- a/configs/p2771-0000_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TEGRA=y
-CONFIG_TEGRA186=y
-CONFIG_TARGET_P2771_0000=y
-CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
-CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-- 
cgit v0.10.2


From d0f45000babf0c89b75b4c779613afa0a900a608 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 12:15:05 -0600
Subject: ARM: tegra: unify Tegra186 Makefile a bit

Many files in arch/arm/mach-tegra are compiled conditionally based on
Kconfig variables, or applicable to all platforms. We can let the main
Tegra Makefile handle compiling (or not) those files to avoid each SoC-
specific Makefile needing to duplicate entries for those files. This
leaves the SoC-specific Makefiles to compile truly SoC-specific code.

In the future, we'll hopefully add Kconfig variables for all the other
files, and refactor those files, and so reduce the need for SoC-specific
Makefiles and/or ifdefs in the Makefiles.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 12ee1cd..3b8d012 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,23 +15,23 @@ else
 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
 endif
 
-obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-y += ap.o
 obj-y += board.o board2.o
 obj-y += cache.o
 obj-y += clock.o
-obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-y += powergate.o
 obj-y += xusb-padctl-dummy.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-obj-$(CONFIG_TEGRA_GPU) += gpu.o
-obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+endif
 
+obj-$(CONFIG_ARM64) += arm64-mmu.o
+obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+obj-$(CONFIG_TEGRA_GPU) += gpu.o
+obj-y += lowlevel_init.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
 endif
-endif
+obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
 
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_TEGRA30) += tegra30/
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
index ce4610d..188b097 100644
--- a/arch/arm/mach-tegra/tegra186/Makefile
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -2,7 +2,4 @@
 #
 # SPDX-License-Identifier: GPL-2.0
 
-obj-y += ../arm64-mmu.o
 obj-y += ../board186.o
-obj-y += ../lowlevel_init.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
-- 
cgit v0.10.2


From 49626ea801e8bb33c9ee4cbcb69e2fea6b13c330 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 12:17:11 -0600
Subject: ARM: tegra: add IVC protocol implementation

IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter
Processor Communication) framework. Within the context of U-Boot, it is
typically used for communication between the main CPU and various
auxiliary processors. In particular, it will be used to communicate with
the BPMP (Boot and Power Management Processor) on Tegra186 in order to
manipulate clocks and reset signals.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/ivc.h b/arch/arm/include/asm/arch-tegra/ivc.h
new file mode 100644
index 0000000..7f2287a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/ivc.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_TEGRA_IVC_H
+#define _ASM_ARCH_TEGRA_IVC_H
+
+#include <common.h>
+
+/*
+ * Tegra IVC is a communication protocol that transfers fixed-size frames
+ * bi-directionally and in-order between the local CPU and some remote entity.
+ * Communication is via a statically sized and allocated buffer in shared
+ * memory and a notification mechanism.
+ *
+ * This API handles all aspects of the shared memory buffer's metadata, and
+ * leaves all aspects of the frame content to the calling code; frames
+ * typically contain some higher-level protocol. The notification mechanism is
+ * also handled externally to this API, since it can vary from instance to
+ * instance.
+ *
+ * The client model is to first find some free (for TX) or filled (for RX)
+ * frame, process that frame's memory buffer (fill or read it), and then
+ * inform the protocol that the frame has been filled/read, i.e. advance the
+ * write/read pointer. If the channel is full, there may be no available frames
+ * to fill/read. In this case, client code may either poll for an available
+ * frame, or wait for the remote entity to send a notification to the local
+ * CPU.
+ */
+
+/**
+ * struct tegra_ivc - In-memory shared memory layout.
+ *
+ * This is described in detail in ivc.c.
+ */
+struct tegra_ivc_channel_header;
+
+/**
+ * struct tegra_ivc - Software state of an IVC channel.
+ *
+ * This state is internal to the IVC code and should not be accessed directly
+ * by clients. It is public solely so clients can allocate storage for the
+ * structure.
+ */
+struct tegra_ivc {
+	/**
+	 * rx_channel - Pointer to the shared memory region used to receive
+	 * messages from the remote entity.
+	 */
+	struct tegra_ivc_channel_header *rx_channel;
+	/**
+	 * tx_channel - Pointer to the shared memory region used to send
+	 * messages to the remote entity.
+	 */
+	struct tegra_ivc_channel_header *tx_channel;
+	/**
+	 * r_pos - The position in list of frames in rx_channel that we are
+	 * reading from.
+	 */
+	uint32_t r_pos;
+	/**
+	 * w_pos - The position in list of frames in tx_channel that we are
+	 * writing to.
+	 */
+	uint32_t w_pos;
+	/**
+	 * nframes - The number of frames allocated (in each direction) in
+	 * shared memory.
+	 */
+	uint32_t nframes;
+	/**
+	 * frame_size - The size of each frame in shared memory.
+	 */
+	uint32_t frame_size;
+	/**
+	 * notify - Function to call to notify the remote processor of a
+	 * change in channel state.
+	 */
+	void (*notify)(struct tegra_ivc *);
+};
+
+/**
+ * tegra_ivc_read_get_next_frame - Locate the next frame to receive.
+ *
+ * Locate the next frame to be received/processed, return the address of the
+ * frame, and do not remove it from the queue. Repeated calls to this function
+ * will return the same address until tegra_ivc_read_advance() is called.
+ *
+ * @ivc		The IVC channel.
+ * @frame	Pointer to be filled with the address of the frame to receive.
+ *
+ * @return 0 if a frame is available, else a negative error code.
+ */
+int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame);
+
+/**
+ * tegra_ivc_read_advance - Advance the read queue.
+ *
+ * Inform the protocol and remote entity that the frame returned by
+ * tegra_ivc_read_get_next_frame() has been processed. The remote end may then
+ * re-use it to transmit further data. Subsequent to this function returning,
+ * tegra_ivc_read_get_next_frame() will return a different frame.
+ *
+ * @ivc		The IVC channel.
+ *
+ * @return 0 if OK, else a negative error code.
+ */
+int tegra_ivc_read_advance(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit.
+ *
+ * Locate the next frame to be filled for transmit, return the address of the
+ * frame, and do not add it to the queue. Repeated calls to this function
+ * will return the same address until tegra_ivc_read_advance() is called.
+ *
+ * @ivc		The IVC channel.
+ * @frame	Pointer to be filled with the address of the frame to fill.
+ *
+ * @return 0 if a frame is available, else a negative error code.
+ */
+int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame);
+
+/**
+ * tegra_ivc_write_advance - Advance the write queue.
+ *
+ * Inform the protocol and remote entity that the frame returned by
+ * tegra_ivc_write_get_next_frame() has been filled and should be transmitted.
+ * The remote end may then read data from it. Subsequent to this function
+ * returning, tegra_ivc_write_get_next_frame() will return a different frame.
+ *
+ * @ivc		The IVC channel.
+ *
+ * @return 0 if OK, else a negative error code.
+ */
+int tegra_ivc_write_advance(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_channel_notified - handle internal messages
+ *
+ * This function must be called following every notification.
+ *
+ * @ivc		The IVC channel.
+ *
+ * @return 0 if the channel is ready for communication, or -EAGAIN if a
+ * channel reset is in progress.
+ */
+int tegra_ivc_channel_notified(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_channel_reset - initiates a reset of the shared memory state
+ *
+ * This function must be called after a channel is initialized but before it
+ * is used for communication. The channel will be ready for use when a
+ * subsequent call to notify the remote of the channel reset indicates the
+ * reset operation is complete.
+ *
+ * @ivc		The IVC channel.
+ */
+void tegra_ivc_channel_reset(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_init - Initialize a channel's software state.
+ *
+ * @ivc		The IVC channel.
+ * @rx_base	Address of the the RX shared memory buffer.
+ * @tx_base	Address of the the TX shared memory buffer.
+ * @nframes	Number of frames in each shared memory buffer.
+ * @frame_size	Size of each frame.
+ *
+ * @return 0 if OK, else a negative error code.
+ */
+int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base,
+		   uint32_t nframes, uint32_t frame_size,
+		   void (*notify)(struct tegra_ivc *));
+
+#endif
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index f4affa5..85ae3b7 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,5 +1,13 @@
 if TEGRA
 
+config TEGRA_IVC
+	bool "Tegra IVC protocol"
+	help
+	  IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
+	  (Inter Processor Communication) framework. Within the context of
+	  U-Boot, it is typically used for communication between the main CPU
+	  and various auxiliary processors.
+
 config TEGRA_COMMON
 	bool "Tegra common options"
 	select DM
@@ -60,6 +68,7 @@ config TEGRA186
 	select TEGRA186_GPIO
 	select TEGRA_ARMV8_COMMON
 	select TEGRA_HSP
+	select TEGRA_IVC
 
 endchoice
 
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 3b8d012..d0bf5a6 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -27,6 +27,7 @@ endif
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 obj-$(CONFIG_TEGRA_GPU) += gpu.o
+obj-$(CONFIG_TEGRA_IVC) += ivc.o
 obj-y += lowlevel_init.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c
new file mode 100644
index 0000000..cf6626f
--- /dev/null
+++ b/arch/arm/mach-tegra/ivc.c
@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/ivc.h>
+
+#define TEGRA_IVC_ALIGN 64
+
+/*
+ * IVC channel reset protocol.
+ *
+ * Each end uses its tx_channel.state to indicate its synchronization state.
+ */
+enum ivc_state {
+	/*
+	 * This value is zero for backwards compatibility with services that
+	 * assume channels to be initially zeroed. Such channels are in an
+	 * initially valid state, but cannot be asynchronously reset, and must
+	 * maintain a valid state at all times.
+	 *
+	 * The transmitting end can enter the established state from the sync or
+	 * ack state when it observes the receiving endpoint in the ack or
+	 * established state, indicating that has cleared the counters in our
+	 * rx_channel.
+	 */
+	ivc_state_established = 0,
+
+	/*
+	 * If an endpoint is observed in the sync state, the remote endpoint is
+	 * allowed to clear the counters it owns asynchronously with respect to
+	 * the current endpoint. Therefore, the current endpoint is no longer
+	 * allowed to communicate.
+	 */
+	ivc_state_sync,
+
+	/*
+	 * When the transmitting end observes the receiving end in the sync
+	 * state, it can clear the w_count and r_count and transition to the ack
+	 * state. If the remote endpoint observes us in the ack state, it can
+	 * return to the established state once it has cleared its counters.
+	 */
+	ivc_state_ack
+};
+
+/*
+ * This structure is divided into two-cache aligned parts, the first is only
+ * written through the tx_channel pointer, while the second is only written
+ * through the rx_channel pointer. This delineates ownership of the cache lines,
+ * which is critical to performance and necessary in non-cache coherent
+ * implementations.
+ */
+struct tegra_ivc_channel_header {
+	union {
+		/* fields owned by the transmitting end */
+		struct {
+			uint32_t w_count;
+			uint32_t state;
+		};
+		uint8_t w_align[TEGRA_IVC_ALIGN];
+	};
+	union {
+		/* fields owned by the receiving end */
+		uint32_t r_count;
+		uint8_t r_align[TEGRA_IVC_ALIGN];
+	};
+};
+
+static inline void tegra_ivc_invalidate_counter(struct tegra_ivc *ivc,
+					struct tegra_ivc_channel_header *h,
+					ulong offset)
+{
+	ulong base = ((ulong)h) + offset;
+	invalidate_dcache_range(base, base + TEGRA_IVC_ALIGN);
+}
+
+static inline void tegra_ivc_flush_counter(struct tegra_ivc *ivc,
+					   struct tegra_ivc_channel_header *h,
+					   ulong offset)
+{
+	ulong base = ((ulong)h) + offset;
+	flush_dcache_range(base, base + TEGRA_IVC_ALIGN);
+}
+
+static inline ulong tegra_ivc_frame_addr(struct tegra_ivc *ivc,
+					 struct tegra_ivc_channel_header *h,
+					 uint32_t frame)
+{
+	BUG_ON(frame >= ivc->nframes);
+
+	return ((ulong)h) + sizeof(struct tegra_ivc_channel_header) +
+	       (ivc->frame_size * frame);
+}
+
+static inline void *tegra_ivc_frame_pointer(struct tegra_ivc *ivc,
+					    struct tegra_ivc_channel_header *ch,
+					    uint32_t frame)
+{
+	return (void *)tegra_ivc_frame_addr(ivc, ch, frame);
+}
+
+static inline void tegra_ivc_invalidate_frame(struct tegra_ivc *ivc,
+					struct tegra_ivc_channel_header *h,
+					unsigned frame)
+{
+	ulong base = tegra_ivc_frame_addr(ivc, h, frame);
+	invalidate_dcache_range(base, base + ivc->frame_size);
+}
+
+static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc,
+					 struct tegra_ivc_channel_header *h,
+					 unsigned frame)
+{
+	ulong base = tegra_ivc_frame_addr(ivc, h, frame);
+	flush_dcache_range(base, base + ivc->frame_size);
+}
+
+static inline int tegra_ivc_channel_empty(struct tegra_ivc *ivc,
+					  struct tegra_ivc_channel_header *ch)
+{
+	/*
+	 * This function performs multiple checks on the same values with
+	 * security implications, so create snapshots with ACCESS_ONCE() to
+	 * ensure that these checks use the same values.
+	 */
+	uint32_t w_count = ACCESS_ONCE(ch->w_count);
+	uint32_t r_count = ACCESS_ONCE(ch->r_count);
+
+	/*
+	 * Perform an over-full check to prevent denial of service attacks where
+	 * a server could be easily fooled into believing that there's an
+	 * extremely large number of frames ready, since receivers are not
+	 * expected to check for full or over-full conditions.
+	 *
+	 * Although the channel isn't empty, this is an invalid case caused by
+	 * a potentially malicious peer, so returning empty is safer, because it
+	 * gives the impression that the channel has gone silent.
+	 */
+	if (w_count - r_count > ivc->nframes)
+		return 1;
+
+	return w_count == r_count;
+}
+
+static inline int tegra_ivc_channel_full(struct tegra_ivc *ivc,
+					 struct tegra_ivc_channel_header *ch)
+{
+	/*
+	 * Invalid cases where the counters indicate that the queue is over
+	 * capacity also appear full.
+	 */
+	return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >=
+	       ivc->nframes;
+}
+
+static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc)
+{
+	ACCESS_ONCE(ivc->rx_channel->r_count) =
+			ACCESS_ONCE(ivc->rx_channel->r_count) + 1;
+
+	if (ivc->r_pos == ivc->nframes - 1)
+		ivc->r_pos = 0;
+	else
+		ivc->r_pos++;
+}
+
+static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc)
+{
+	ACCESS_ONCE(ivc->tx_channel->w_count) =
+			ACCESS_ONCE(ivc->tx_channel->w_count) + 1;
+
+	if (ivc->w_pos == ivc->nframes - 1)
+		ivc->w_pos = 0;
+	else
+		ivc->w_pos++;
+}
+
+static inline int tegra_ivc_check_read(struct tegra_ivc *ivc)
+{
+	ulong offset;
+
+	/*
+	 * tx_channel->state is set locally, so it is not synchronized with
+	 * state from the remote peer. The remote peer cannot reset its
+	 * transmit counters until we've acknowledged its synchronization
+	 * request, so no additional synchronization is required because an
+	 * asynchronous transition of rx_channel->state to ivc_state_ack is not
+	 * allowed.
+	 */
+	if (ivc->tx_channel->state != ivc_state_established)
+		return -ECONNRESET;
+
+	/*
+	 * Avoid unnecessary invalidations when performing repeated accesses to
+	 * an IVC channel by checking the old queue pointers first.
+	 * Synchronization is only necessary when these pointers indicate empty
+	 * or full.
+	 */
+	if (!tegra_ivc_channel_empty(ivc, ivc->rx_channel))
+		return 0;
+
+	offset = offsetof(struct tegra_ivc_channel_header, w_count);
+	tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
+	return tegra_ivc_channel_empty(ivc, ivc->rx_channel) ? -ENOMEM : 0;
+}
+
+static inline int tegra_ivc_check_write(struct tegra_ivc *ivc)
+{
+	ulong offset;
+
+	if (ivc->tx_channel->state != ivc_state_established)
+		return -ECONNRESET;
+
+	if (!tegra_ivc_channel_full(ivc, ivc->tx_channel))
+		return 0;
+
+	offset = offsetof(struct tegra_ivc_channel_header, r_count);
+	tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset);
+	return tegra_ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0;
+}
+
+static inline uint32_t tegra_ivc_channel_avail_count(struct tegra_ivc *ivc,
+	struct tegra_ivc_channel_header *ch)
+{
+	/*
+	 * This function isn't expected to be used in scenarios where an
+	 * over-full situation can lead to denial of service attacks. See the
+	 * comment in tegra_ivc_channel_empty() for an explanation about
+	 * special over-full considerations.
+	 */
+	return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count);
+}
+
+int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame)
+{
+	int result = tegra_ivc_check_read(ivc);
+	if (result < 0)
+		return result;
+
+	/*
+	 * Order observation of w_pos potentially indicating new data before
+	 * data read.
+	 */
+	mb();
+
+	tegra_ivc_invalidate_frame(ivc, ivc->rx_channel, ivc->r_pos);
+	*frame = tegra_ivc_frame_pointer(ivc, ivc->rx_channel, ivc->r_pos);
+
+	return 0;
+}
+
+int tegra_ivc_read_advance(struct tegra_ivc *ivc)
+{
+	ulong offset;
+	int result;
+
+	/*
+	 * No read barriers or synchronization here: the caller is expected to
+	 * have already observed the channel non-empty. This check is just to
+	 * catch programming errors.
+	 */
+	result = tegra_ivc_check_read(ivc);
+	if (result)
+		return result;
+
+	tegra_ivc_advance_rx(ivc);
+	offset = offsetof(struct tegra_ivc_channel_header, r_count);
+	tegra_ivc_flush_counter(ivc, ivc->rx_channel, offset);
+
+	/*
+	 * Ensure our write to r_pos occurs before our read from w_pos.
+	 */
+	mb();
+
+	offset = offsetof(struct tegra_ivc_channel_header, w_count);
+	tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
+
+	if (tegra_ivc_channel_avail_count(ivc, ivc->rx_channel) ==
+	    ivc->nframes - 1)
+		ivc->notify(ivc);
+
+	return 0;
+}
+
+int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame)
+{
+	int result = tegra_ivc_check_write(ivc);
+	if (result)
+		return result;
+
+	*frame = tegra_ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos);
+
+	return 0;
+}
+
+int tegra_ivc_write_advance(struct tegra_ivc *ivc)
+{
+	ulong offset;
+	int result;
+
+	result = tegra_ivc_check_write(ivc);
+	if (result)
+		return result;
+
+	tegra_ivc_flush_frame(ivc, ivc->tx_channel, ivc->w_pos);
+
+	/*
+	 * Order any possible stores to the frame before update of w_pos.
+	 */
+	mb();
+
+	tegra_ivc_advance_tx(ivc);
+	offset = offsetof(struct tegra_ivc_channel_header, w_count);
+	tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);
+
+	/*
+	 * Ensure our write to w_pos occurs before our read from r_pos.
+	 */
+	mb();
+
+	offset = offsetof(struct tegra_ivc_channel_header, r_count);
+	tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset);
+
+	if (tegra_ivc_channel_avail_count(ivc, ivc->tx_channel) == 1)
+		ivc->notify(ivc);
+
+	return 0;
+}
+
+/*
+ * ===============================================================
+ *  IVC State Transition Table - see tegra_ivc_channel_notified()
+ * ===============================================================
+ *
+ *	local	remote	action
+ *	-----	------	-----------------------------------
+ *	SYNC	EST	<none>
+ *	SYNC	ACK	reset counters; move to EST; notify
+ *	SYNC	SYNC	reset counters; move to ACK; notify
+ *	ACK	EST	move to EST; notify
+ *	ACK	ACK	move to EST; notify
+ *	ACK	SYNC	reset counters; move to ACK; notify
+ *	EST	EST	<none>
+ *	EST	ACK	<none>
+ *	EST	SYNC	reset counters; move to ACK; notify
+ *
+ * ===============================================================
+ */
+int tegra_ivc_channel_notified(struct tegra_ivc *ivc)
+{
+	ulong offset;
+	enum ivc_state peer_state;
+
+	/* Copy the receiver's state out of shared memory. */
+	offset = offsetof(struct tegra_ivc_channel_header, w_count);
+	tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
+	peer_state = ACCESS_ONCE(ivc->rx_channel->state);
+
+	if (peer_state == ivc_state_sync) {
+		/*
+		 * Order observation of ivc_state_sync before stores clearing
+		 * tx_channel.
+		 */
+		mb();
+
+		/*
+		 * Reset tx_channel counters. The remote end is in the SYNC
+		 * state and won't make progress until we change our state,
+		 * so the counters are not in use at this time.
+		 */
+		ivc->tx_channel->w_count = 0;
+		ivc->rx_channel->r_count = 0;
+
+		ivc->w_pos = 0;
+		ivc->r_pos = 0;
+
+		/*
+		 * Ensure that counters appear cleared before new state can be
+		 * observed.
+		 */
+		mb();
+
+		/*
+		 * Move to ACK state. We have just cleared our counters, so it
+		 * is now safe for the remote end to start using these values.
+		 */
+		ivc->tx_channel->state = ivc_state_ack;
+		offset = offsetof(struct tegra_ivc_channel_header, w_count);
+		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);
+
+		/*
+		 * Notify remote end to observe state transition.
+		 */
+		ivc->notify(ivc);
+	} else if (ivc->tx_channel->state == ivc_state_sync &&
+			peer_state == ivc_state_ack) {
+		/*
+		 * Order observation of ivc_state_sync before stores clearing
+		 * tx_channel.
+		 */
+		mb();
+
+		/*
+		 * Reset tx_channel counters. The remote end is in the ACK
+		 * state and won't make progress until we change our state,
+		 * so the counters are not in use at this time.
+		 */
+		ivc->tx_channel->w_count = 0;
+		ivc->rx_channel->r_count = 0;
+
+		ivc->w_pos = 0;
+		ivc->r_pos = 0;
+
+		/*
+		 * Ensure that counters appear cleared before new state can be
+		 * observed.
+		 */
+		mb();
+
+		/*
+		 * Move to ESTABLISHED state. We know that the remote end has
+		 * already cleared its counters, so it is safe to start
+		 * writing/reading on this channel.
+		 */
+		ivc->tx_channel->state = ivc_state_established;
+		offset = offsetof(struct tegra_ivc_channel_header, w_count);
+		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);
+
+		/*
+		 * Notify remote end to observe state transition.
+		 */
+		ivc->notify(ivc);
+	} else if (ivc->tx_channel->state == ivc_state_ack) {
+		/*
+		 * At this point, we have observed the peer to be in either
+		 * the ACK or ESTABLISHED state. Next, order observation of
+		 * peer state before storing to tx_channel.
+		 */
+		mb();
+
+		/*
+		 * Move to ESTABLISHED state. We know that we have previously
+		 * cleared our counters, and we know that the remote end has
+		 * cleared its counters, so it is safe to start writing/reading
+		 * on this channel.
+		 */
+		ivc->tx_channel->state = ivc_state_established;
+		offset = offsetof(struct tegra_ivc_channel_header, w_count);
+		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);
+
+		/*
+		 * Notify remote end to observe state transition.
+		 */
+		ivc->notify(ivc);
+	} else {
+		/*
+		 * There is no need to handle any further action. Either the
+		 * channel is already fully established, or we are waiting for
+		 * the remote end to catch up with our current state. Refer
+		 * to the diagram in "IVC State Transition Table" above.
+		 */
+	}
+
+	if (ivc->tx_channel->state != ivc_state_established)
+		return -EAGAIN;
+
+	return 0;
+}
+
+void tegra_ivc_channel_reset(struct tegra_ivc *ivc)
+{
+	ulong offset;
+
+	ivc->tx_channel->state = ivc_state_sync;
+	offset = offsetof(struct tegra_ivc_channel_header, w_count);
+	tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);
+	ivc->notify(ivc);
+}
+
+static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
+			    uint32_t frame_size)
+{
+	int ret = 0;
+
+	BUG_ON(offsetof(struct tegra_ivc_channel_header, w_count) &
+	       (TEGRA_IVC_ALIGN - 1));
+	BUG_ON(offsetof(struct tegra_ivc_channel_header, r_count) &
+	       (TEGRA_IVC_ALIGN - 1));
+	BUG_ON(sizeof(struct tegra_ivc_channel_header) &
+	       (TEGRA_IVC_ALIGN - 1));
+
+	if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) {
+		error("tegra_ivc: nframes * frame_size overflows\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * The headers must at least be aligned enough for counters
+	 * to be accessed atomically.
+	 */
+	if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) ||
+	    (qbase2 & (TEGRA_IVC_ALIGN - 1))) {
+		error("tegra_ivc: channel start not aligned\n");
+		return -EINVAL;
+	}
+
+	if (frame_size & (TEGRA_IVC_ALIGN - 1)) {
+		error("tegra_ivc: frame size not adequately aligned\n");
+		return -EINVAL;
+	}
+
+	if (qbase1 < qbase2) {
+		if (qbase1 + frame_size * nframes > qbase2)
+			ret = -EINVAL;
+	} else {
+		if (qbase2 + frame_size * nframes > qbase1)
+			ret = -EINVAL;
+	}
+
+	if (ret) {
+		error("tegra_ivc: queue regions overlap\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base,
+		   uint32_t nframes, uint32_t frame_size,
+		   void (*notify)(struct tegra_ivc *))
+{
+	int ret;
+
+	if (!ivc)
+		return -EINVAL;
+
+	ret = check_ivc_params(rx_base, tx_base, nframes, frame_size);
+	if (ret)
+		return ret;
+
+	ivc->rx_channel = (struct tegra_ivc_channel_header *)rx_base;
+	ivc->tx_channel = (struct tegra_ivc_channel_header *)tx_base;
+	ivc->w_pos = 0;
+	ivc->r_pos = 0;
+	ivc->nframes = nframes;
+	ivc->frame_size = frame_size;
+	ivc->notify = notify;
+
+	return 0;
+}
-- 
cgit v0.10.2


From efbb3d491e87935421242396958fdddd87e0fde1 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 13:02:11 -0600
Subject: ARM: tegra: p2371-2180: A03 board PMIC config update

Rev A03 of P2180 requires some PMIC programming adjustments, yet the
PMIC's own OTP has not been updated. Consequently, U-Boot must make
these changes itself.

NVIDIA's syseng team has confirmed that these changes can be enabled on
all board revisions without issue.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c
index 0f587ea..dbdc1b6 100644
--- a/board/nvidia/p2371-2180/p2371-2180.c
+++ b/board/nvidia/p2371-2180/p2371-2180.c
@@ -30,6 +30,28 @@ void pin_mux_mmc(void)
 	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
 	if (ret)
 		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+	/* Disable LDO4 discharge */
+	ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+	if (ret) {
+		printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+	} else {
+		val &= ~BIT(1); /* ADE */
+		ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+	}
+
+	/* Set MBLPD */
+	ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+	if (ret) {
+		printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	} else {
+		val |= BIT(6); /* MBLPD */
+		ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	}
 }
 
 /*
diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h
index 92c3719..39e5501 100644
--- a/board/nvidia/p2571/max77620_init.h
+++ b/board/nvidia/p2571/max77620_init.h
@@ -13,6 +13,8 @@
 #define MAX77620_I2C_ADDR		0x78
 #define MAX77620_I2C_ADDR_7BIT		0x3C
 
+#define MAX77620_CNFGGLBL1_REG		0x00
+
 #define MAX77620_SD0_REG		0x16
 #define MAX77620_SD1_REG		0x17
 #define MAX77620_SD2_REG		0x18
-- 
cgit v0.10.2


From 0e2b5350d9523c9b2dca57b98c89f031691d23e3 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 17:01:50 -0600
Subject: ARM: Add save_boot_params for ARMv8

Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 67edf94..19c771d 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -53,6 +53,11 @@ _bss_end_ofs:
 	.quad	__bss_end - _start
 
 reset:
+	/* Allow the board to save important registers */
+	b	save_boot_params
+.globl	save_boot_params_ret
+save_boot_params_ret:
+
 #ifdef CONFIG_SYS_RESET_SCTRL
 	bl reset_sctrl
 #endif
@@ -282,3 +287,7 @@ ENTRY(c_runtime_cpu_setup)
 
 	ret
 ENDPROC(c_runtime_cpu_setup)
+
+WEAK(save_boot_params)
+	b	save_boot_params_ret	/* back to my caller */
+ENDPROC(save_boot_params)
-- 
cgit v0.10.2


From 2a5f7f20747637cd1f94d4accfd7caa99a7c6035 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 17:01:51 -0600
Subject: ARM: tegra: pick up actual memory size

On Tegra186, U-Boot is booted by the binary firmware as if it were a
Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address
of that DTB, and parse the /memory/reg property to determine the actual
RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use.

Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion
that U-Boot use that DTB as its control DTB. I don't believe that would
work well, so I do not plan to put any effort into this. By default the
FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT
bindings. U-Boot aims to use only upstreamed DT bindings, or as close as
it can get. Replacing this DTB with a DTB using upstream bindings is
physically quite easy; simply replace the content of one of the GPT
partitions on the eMMC. However, the binary FW at least partially relies
on the existence/content of some nodes in the DTB, and that requires the
DTB to be written according to downstream bindings. Equally, if U-Boot
continues to use appended DTBs built from its own source tree, as it does
for all other Tegra platforms, development and deployment is much easier.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
index f4b6152..876ccba 100644
--- a/arch/arm/mach-tegra/board186.c
+++ b/arch/arm/mach-tegra/board186.c
@@ -11,12 +11,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	gd->ram_size = (1.5 * 1024 * 1024 * 1024);
-	return 0;
-}
-
 int board_early_init_f(void)
 {
 	return 0;
@@ -32,12 +26,6 @@ int board_late_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
 void pad_init_mmc(struct mmc_host *host)
 {
 }
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
index 188b097..033d600 100644
--- a/arch/arm/mach-tegra/tegra186/Makefile
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -3,3 +3,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-y += ../board186.o
+obj-y += nvtboot_ll.o
+obj-y += nvtboot_mem.o
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
new file mode 100644
index 0000000..1eab890
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
@@ -0,0 +1,20 @@
+/*
+ * Save nvtboot-related boot-time CPU state
+ *
+ * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+.globl	nvtboot_boot_x0
+nvtboot_boot_x0:
+	.dword 0
+
+ENTRY(save_boot_params)
+	adr	x8, nvtboot_boot_x0
+	str	x0, [x8]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
new file mode 100644
index 0000000..37dd8d4
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <asm/arch/tegra.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern unsigned long nvtboot_boot_x0;
+
+/*
+ * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
+ *
+ * We only support up to two banks since that's all the binary  bootloader
+ * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM  above 4G.
+ * This is all a fairly safe assumption, since the L4T kernel makes  the same
+ * assumptions, so the bootloader is unlikely to change.
+ *
+ * This is written to before relocation, and hence cannot be in .bss, since
+ * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
+ * forces this into .data and avoids this issue. This also has the nice side-
+ * effect of the content being valid after relocation.
+ */
+static struct {
+	u64 start;
+	u64 size;
+} ram_banks[2] = {{1}};
+
+int dram_init(void)
+{
+	unsigned int na, ns;
+	const void *nvtboot_blob = (void *)nvtboot_boot_x0;
+	int node, len, i;
+	const u32 *prop;
+
+	memset(ram_banks, 0, sizeof(ram_banks));
+
+	na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
+	ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
+
+	node = fdt_path_offset(nvtboot_blob, "/memory");
+	if (node < 0) {
+		error("Can't find /memory node in nvtboot DTB");
+		hang();
+	}
+	prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
+	if (!prop) {
+		error("Can't find /memory/reg property in nvtboot DTB");
+		hang();
+	}
+
+	len /= (na + ns);
+	if (len > ARRAY_SIZE(ram_banks))
+		len = ARRAY_SIZE(ram_banks);
+
+	gd->ram_size = 0;
+	for (i = 0; i < len; i++) {
+		ram_banks[i].start = of_read_number(prop, na);
+		prop += na;
+		ram_banks[i].size = of_read_number(prop, ns);
+		prop += ns;
+		gd->ram_size += ram_banks[i].size;
+	}
+
+	return 0;
+}
+
+extern unsigned long nvtboot_boot_x0;
+
+void dram_init_banksize(void)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		gd->bd->bi_dram[i].start = ram_banks[i].start;
+		gd->bd->bi_dram[i].size = ram_banks[i].size;
+	}
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return ram_banks[0].start + ram_banks[0].size;
+}
-- 
cgit v0.10.2


From 16c8c1709dcd5839e9099be44b149cf906a0bac7 Mon Sep 17 00:00:00 2001
From: Kevin Hao <kexin.hao@windriver.com>
Date: Fri, 8 Jul 2016 11:25:14 +0800
Subject: mpc83xx: fix the corruption of u-boot when saveenv

Robert P. J. Day has pointed that the value of SYS_MONITOR_LEN in
MPC8315ERDB.h is smaller than the u-boot.bin. This will cause the
overlap between the code of u-boot and the environment variable.
So when executing saveenv, it will corrupt the code of u-boot and
causes the board not boot. Fix this for all the mpc83xx boards by
reserving a 512K area.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 578325c..e809dcf 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -203,7 +203,7 @@
  */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
 
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 5613a4a..1947cf1 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -241,7 +241,7 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 7ce5f59..5b23f94 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -169,7 +169,7 @@
 /*
  * The reserved memory
  */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 13f954d..6680b59 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -156,7 +156,7 @@
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index fd48260..babbd1a 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -168,7 +168,7 @@
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 288b126..0c44097 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -225,7 +225,7 @@
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 2721255..a7c37e1 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -330,7 +330,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 921d5f3..8bc72d5 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -200,7 +200,7 @@
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 
 /*
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index bb06e89..8962959 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -225,7 +225,7 @@
 #undef	CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
 
 /*
-- 
cgit v0.10.2


From 63865278dae47ad19527d9f9b6e0dad6cb01f401 Mon Sep 17 00:00:00 2001
From: Kevin Hao <kexin.hao@windriver.com>
Date: Fri, 8 Jul 2016 11:25:15 +0800
Subject: mpc83xx: make it bootable with the latest kernel

Due to the blow up of the latest kernel size, the default gnuzip
size (8M) seems too small. The yocto kernel size I built for
mpc8315erdb board is 5294393, and it can't be boot by using the
latest u-boot. So expand gnuzip buffer for all the mpc83xx boards
to fix this issue.

Robert P. J. Day also pointed that the kernel partition on the NAND
flash is also too small, fix it at the same time.

Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index e809dcf..5b80464 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -452,6 +452,7 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 /*
  * Core HID Setup
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 1947cf1..1c4e082 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -268,7 +268,7 @@
 #define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT			"nand0=e2800000.flash"
 #define MTDPARTS_DEFAULT		\
-	"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
+	"mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_CMD_NAND 1
@@ -502,6 +502,7 @@
  */
 				/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 5b23f94..23a2e34 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -241,7 +241,7 @@
 #define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT			"nand0=e0600000.flash"
 #define MTDPARTS_DEFAULT		\
-	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
+	"mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_CMD_NAND			1
@@ -489,6 +489,7 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 /*
  * Core HID Setup
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 6680b59..095c0d8 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -359,6 +359,7 @@
  */
 					/* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 /*
  * Core HID Setup
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index babbd1a..18418e3 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -441,6 +441,7 @@
  */
 					/* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 /*
  * Core HID Setup
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0c44097..a2fa783 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -508,6 +508,7 @@
  */
 				/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index a7c37e1..c11c0cf 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -544,6 +544,7 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 				/* Initial Memory map for Linux*/
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 8bc72d5..b2dc189 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -522,6 +522,7 @@ extern int board_pci_host_broken(void);
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 /*
  * Core HID Setup
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 8962959..8eb87eb 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -533,6 +533,7 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
 /*
  * Core HID Setup
-- 
cgit v0.10.2


From 8f01397ba76d1ee210bedbf031d807e8df34c482 Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Thu, 14 Jul 2016 12:27:51 -0400
Subject: powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL

As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
index 9421f1e..ede8e66 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -239,15 +239,23 @@ int pamu_init(void)
 	spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
 
 	/* Allocate space for Primary PAACT Table */
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR))
+	ppaact = (void *)CONFIG_SPL_PPAACT_ADDR;
+#else
 	ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
 	if (!ppaact)
 		return -1;
+#endif
 	memset(ppaact, 0, ppaact_size);
 
 	/* Allocate space for Secondary PAACT Table */
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR))
+	sec = (void *)CONFIG_SPL_SPAACT_ADDR;
+#else
 	sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
 	if (!sec)
 		return -1;
+#endif
 	memset(sec, 0, spaact_size);
 
 	ppaact_phys = virt_to_phys((void *)ppaact);
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
index 26c5ea4..a8e6f51 100644
--- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -28,6 +28,14 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
 
 	i++;
 #endif
+#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR))
+	tbl->start_addr[i] =
+		(uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR);
+	tbl->size[i] = 256 * 1024; /* 256K CPC flash */
+	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
+
+	i++;
+#endif
 	debug("PAMU address\t\t\tsize\n");
 	for (j = 0; j < i ; j++)
 		debug("%llx \t\t\t%llx\n",  tbl->start_addr[j],  tbl->size[j]);
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 826f9c9..9420021 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -72,6 +72,32 @@
 
 #ifdef CONFIG_CHAIN_OF_TRUST
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_DM			1
+#define CONFIG_SPL_CRYPTO_SUPPORT
+#define CONFIG_SPL_HASH_SUPPORT
+#define CONFIG_SPL_RSA
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+/*
+ * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
+ * due to space crunch on CPC and thus malloc will not work.
+ */
+#define CONFIG_SPL_PPAACT_ADDR		0x2e000000
+#define CONFIG_SPL_SPAACT_ADDR		0x2f000000
+#define CONFIG_SPL_JR0_LIODN_S		454
+#define CONFIG_SPL_JR0_LIODN_NS		458
+/*
+ * Define the key hash for U-Boot here if public/private key pair used to
+ * sign U-boot are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_SPL_UBOOT_KEY_HASH \
+ *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * else leave it defined as NULL
+ */
+
+#define CONFIG_SPL_UBOOT_KEY_HASH	NULL
+#endif /* ifdef CONFIG_SPL_BUILD */
+
 #define CONFIG_CMD_ESBC_VALIDATE
 #define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
@@ -82,7 +108,9 @@
 #define CONFIG_FSL_CAAM
 #endif
 
-/* fsl_setenv_chain_of_trust() must be called from
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsl_setenv_chain_of_trust() must be called from
  * board_late_init()
  */
 #ifndef CONFIG_BOARD_LATE_INIT
@@ -119,5 +147,6 @@
 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
 
 #include <config_fsl_chain_trust.h>
+#endif /* #ifndef CONFIG_SPL_BUILD */
 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 #endif
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index ecfcc82..290536d 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -6,7 +6,17 @@
 
 #include <common.h>
 #include <fsl_validate.h>
+#include <fsl_secboot_err.h>
 #include <fsl_sfp.h>
+#include <dm/root.h>
+
+#ifdef CONFIG_ADDR_MAP
+#include <asm/mmu.h>
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_pamu.h>
+#endif
 
 #ifdef CONFIG_LS102XA
 #include <asm/arch/immap_ls102xa.h>
@@ -52,6 +62,7 @@ int fsl_check_boot_mode_secure(void)
 	return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
 int fsl_setenv_chain_of_trust(void)
 {
 	/* Check Boot Mode
@@ -68,3 +79,48 @@ int fsl_setenv_chain_of_trust(void)
 	setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
+{
+	int res;
+
+	/*
+	 * Check Boot Mode
+	 * If Boot Mode is Non-Secure, skip validation
+	 */
+	if (fsl_check_boot_mode_secure() == 0)
+		return;
+
+	printf("SPL: Validating U-Boot image\n");
+
+#ifdef CONFIG_ADDR_MAP
+	init_addr_map();
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+	if (pamu_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	if (sec_init() < 0)
+		fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
+#endif
+
+/*
+ * dm_init_and_scan() is called as part of common SPL framework, so no
+ * need to call it again but in case of powerpc platforms which currently
+ * do not use common SPL framework, so need to call this function here.
+ */
+#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK))
+	dm_init_and_scan(false);
+#endif
+	res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH,
+				   &img_addr);
+
+	if (res == 0)
+		printf("SPL: Validation of U-boot successful\n");
+}
+#endif /* ifdef CONFIG_SPL_BUILD */
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 510fa4e..4a8cc32 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -599,10 +599,27 @@ int sec_init_idx(uint8_t sec_idx)
 	sec_out32(&sec->mcfgr, mcr);
 
 #ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * For SPL Build, Set the Liodns in SEC JR0 for
+	 * creating PAMU entries corresponding to these.
+	 * For normal build, these are set in set_liodns().
+	 */
+	liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
+	liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
+
+	liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+		 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
+	liodnr = liodnr |
+		 (liodn_ns << JRNSLIODN_SHIFT) |
+		 (liodn_s << JRSLIODN_SHIFT);
+	sec_out32(&sec->jrliodnr[0].ls, liodnr);
+#else
 	liodnr = sec_in32(&sec->jrliodnr[0].ls);
 	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
 	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 #endif
+#endif
 
 	ret = jr_init(sec_idx);
 	if (ret < 0) {
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index cbeb74a..4e49a4e 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -11,6 +11,9 @@
 #include <asm/io.h>
 #include <fsl_ifc.h>
 #include <linux/mtd/nand.h>
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
 
 static inline int is_blank(uchar *addr, int page_size)
 {
@@ -268,6 +271,27 @@ void nand_boot(void)
 	 */
 	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 #endif
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+	/*
+	 * U-Boot header is appended at end of U-boot image, so
+	 * calculate U-boot header address using U-boot header size.
+	 */
+#define CONFIG_U_BOOT_HDR_ADDR \
+		((CONFIG_SYS_NAND_U_BOOT_START + \
+		  CONFIG_SYS_NAND_U_BOOT_SIZE) - \
+		 CONFIG_U_BOOT_HDR_SIZE)
+	spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
+			   CONFIG_SYS_NAND_U_BOOT_START);
+	/*
+	 * In case of failure in validation, spl_validate_uboot would
+	 * not return back in case of Production environment with ITS=1.
+	 * Thus U-Boot will not start.
+	 * In Development environment (ITS=0 and SB_EN=1), the function
+	 * may return back in case of non-fatal failures.
+	 */
+#endif
+
 	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 	uboot();
 }
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
index a71e1ce..c350938 100644
--- a/include/fsl_validate.h
+++ b/include/fsl_validate.h
@@ -254,4 +254,11 @@ int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
 
 int fsl_check_boot_mode_secure(void);
 int fsl_setenv_chain_of_trust(void);
+
+/*
+ * This function is used to validate the main U-boot binary from
+ * SPL just before passing control to it using QorIQ Trust
+ * Architecture header (appended to U-boot image).
+ */
+void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr);
 #endif
-- 
cgit v0.10.2


From aa36c84edfcfd8c7d0348511e7b0fbb43514cd35 Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Thu, 14 Jul 2016 12:27:52 -0400
Subject: powerpc/mpc85xx: T104x: Add nand secure boot target

For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe35f48d830f01a72617207d03ca85b4d
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 61f5639..ace4279 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -439,7 +439,7 @@ ulong cpu_init_f(void)
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
 	struct law_entry law;
 #endif
 #ifdef CONFIG_MPC8548
@@ -459,7 +459,7 @@ ulong cpu_init_f(void)
 	disable_tlb(14);
 	disable_tlb(15);
 
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
 	/* Disable the LAW created for NOR flash by the PBI commands */
 	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 	if (law.index != -1)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4c51225..c3e1234 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1069,17 +1069,23 @@ create_init_ram_area:
 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 	/* create a temp mapping in AS = 1 for Flash mapping
 	 * created by PBL for ISBC code
-	*/
+	 */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
 		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
 		CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
-#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+/*
+ * For Targets without CONFIG_SPL like P3, P5
+ * and for targets with CONFIG_SPL like T1, T2, T4, only for
+ * u-boot-spl i.e. CONFIG_SPL_BUILD
+ */
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
+	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 	/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
 	 * to L3 Address configured by PBL for ISBC code
-	*/
+	 */
 	create_tlb1_entry 15, \
 		1, BOOKE_PAGESZ_1M, \
 		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 9420021..2e2d565 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -35,7 +35,9 @@
 	defined(CONFIG_T104xD4RDB) || \
 	defined(CONFIG_PPC_T1023) || \
 	defined(CONFIG_PPC_T1024)
+#ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_CPC_REINIT_F
+#endif
 #define CONFIG_KEY_REVOCATION
 #undef CONFIG_SYS_INIT_L3_ADDR
 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
@@ -43,7 +45,13 @@
 
 #if defined(CONFIG_RAMBOOT_PBL)
 #undef CONFIG_SYS_INIT_L3_ADDR
-#define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
+#ifdef CONFIG_SYS_INIT_L3_VADDR
+#define CONFIG_SYS_INIT_L3_ADDR	\
+			(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
+					0xbff00000
+#else
+#define CONFIG_SYS_INIT_L3_ADDR		0xbff00000
+#endif
 #endif
 
 #if defined(CONFIG_C29XPCIE)
diff --git a/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/board/freescale/t104xrdb/t104x_pbi_sb.cfg
new file mode 100644
index 0000000..98dc8e4
--- /dev/null
+++ b/board/freescale/t104xrdb/t104x_pbi_sb.cfg
@@ -0,0 +1,38 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 bffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 bffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 bf000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
+090e0200 bffd0000
+091380c0 000FFFFF
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 95c15aa..7c0511e 100644
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -28,7 +28,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+	!defined(CONFIG_SECURE_BOOT)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
@@ -36,6 +37,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
+
+#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
+	 * the physical address of the SRAM is at 0xbffc0000,
+	 * and virtual address is 0xfffc0000
+	 */
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
+		      CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256K, 1),
 #else
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..2e16255
--- /dev/null
+++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,30 @@
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT"
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
+CONFIG_OF_LIBFDT=y
+CONFIG_RSA=y
+CONFIG_DM=y
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index a8f4f74..2ec1962 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -18,7 +18,14 @@
 #include <asm/config_mpc85xx.h>
 
 #ifdef CONFIG_RAMBOOT_PBL
+
+#ifndef CONFIG_SECURE_BOOT
 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_PBI \
+		$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
+#endif
+
 #ifdef CONFIG_T1040RDB
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
 #endif
@@ -62,7 +69,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 
 #ifdef CONFIG_NAND
 #define CONFIG_SPL_NAND_SUPPORT
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image.
+ */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
+					 CONFIG_U_BOOT_HDR_SIZE)
+#else
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#endif
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
@@ -161,6 +178,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 0x800)
 #elif defined(CONFIG_NAND)
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_BOOTSCRIPT_COPY_RAM
+#endif
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			0x2000
@@ -202,8 +223,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+/*
+ * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
+ * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ */
+#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		256 << 10
-#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
-- 
cgit v0.10.2


From ebfc066e6f755da373d503608249f77ac298fb5e Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Thu, 14 Jul 2016 12:27:53 -0400
Subject: doc: SPL: Add README for secure boot support

Adds information regarding SPL handling validation process of main u-boot
image on power/mpc85xx and arm/layerscape platforms.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/doc/SPL/README.spl-secure-boot b/doc/SPL/README.spl-secure-boot
new file mode 100644
index 0000000..f2f8d78
--- /dev/null
+++ b/doc/SPL/README.spl-secure-boot
@@ -0,0 +1,18 @@
+Overview of SPL verified boot on powerpc/mpc85xx & arm/layerscape platforms
+===========================================================================
+
+Introduction
+------------
+
+This document provides an overview of how SPL verified boot works on powerpc/
+mpc85xx & arm/layerscape platforms.
+
+Methodology
+-----------
+
+The SPL image is responsible for loading the next stage boot loader, which is
+the main u-boot image. For secure boot process on these platforms ROM verifies
+SPL image, so to continue chain of trust SPL image verifies U-boot image using
+spl_validate_uboot(). This function uses QorIQ Trust Architecture header
+(appended to U-boot image) to validate the U-boot binary just before passing
+control to it.
-- 
cgit v0.10.2


From b24a4f6247d867f1301edc1c6390aca79ecbe16b Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Tue, 19 Jul 2016 17:52:06 -0500
Subject: powerpc/85xx: Increase fdt address

Loading the fdt at 0xc00000 fails if the uncompressed kernel image is
greater than 12 MiB, which is quite common with modern kernels and
multiplatform defconfigs.  Move fdtaddr to 0x1e00000 which is just under
the ramdiskaddr on most targets.

Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2c3c4ac..5de9bb7 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -830,7 +830,7 @@ unsigned long get_board_ddr_clk(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=b4860qds/b4860qds.dtb\0"				\
 	"bdev=sda3\0"
 
@@ -868,7 +868,7 @@ unsigned long get_board_ddr_clk(void);
  "setenv bootargs root=/dev/ram rw "		\
  "console=$consoledev,$baudrate $othbootargs;"	\
  "setenv ramdiskaddr 0x02000000;"		\
- "setenv fdtaddr 0x00c00000;"			\
+ "setenv fdtaddr 0x01e00000;"			\
  "setenv loadaddr 0x1000000;"			\
  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 0a9d8a6..f2a7c69 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -403,7 +403,7 @@ extern unsigned long get_sdram_size(void);
 	"consoledev=ttyS0\0"				\
 	"ramdiskaddr=2000000\0"			\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
-	"fdtaddr=c00000\0"				\
+	"fdtaddr=1e00000\0"				\
 	"fdtfile=bsc9131rdb.dtb\0"		\
 	"bdev=sda1\0"	\
 	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 756beec..4744f08 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -647,7 +647,7 @@ combinations. this should be removed later
 	"consoledev=ttyS0\0"				\
 	"ramdiskaddr=2000000\0"			\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
-	"fdtaddr=c00000\0"				\
+	"fdtaddr=1e00000\0"				\
 	"fdtfile=bsc9132qds.dtb\0"		\
 	"bdev=sda1\0"	\
 	CONFIG_DEF_HWCONFIG\
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 69a9798..cc5359f 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -530,7 +530,7 @@
 	"consoledev=ttyS0\0"				\
 	"ramdiskaddr=2000000\0"				\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
-	"fdtaddr=c00000\0"				\
+	"fdtaddr=1e00000\0"				\
 	"fdtfile=name/of/device-tree.dtb\0"			\
 	"othbootargs=ramdisk_size=600000\0"		\
 
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 7c19ff8..874261a 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -727,7 +727,7 @@
 "consoledev=ttyS0\0"				\
 "ramdiskaddr=2000000\0"			\
 "ramdiskfile=8536ds/ramdisk.uboot\0"		\
-"fdtaddr=c00000\0"				\
+"fdtaddr=1e00000\0"				\
 "fdtfile=8536ds/mpc8536ds.dtb\0"		\
 "bdev=sda3\0"					\
 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 321f71e..cd10432 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -462,7 +462,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 "consoledev=ttyS0\0"				\
 "ramdiskaddr=2000000\0"			\
 "ramdiskfile=8544ds/ramdisk.uboot\0"		\
-"fdtaddr=c00000\0"				\
+"fdtaddr=1e00000\0"				\
 "fdtfile=8544ds/mpc8544ds.dtb\0"		\
 "bdev=sda3\0"
 
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index e73be48..b81a4ed 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -562,7 +562,7 @@ extern unsigned long get_clock_freq(void);
 	"consoledev=ttyS1\0"			\
 	"ramdiskaddr=2000000\0"			\
 	"ramdiskfile=ramdisk.uboot\0"		\
-	"fdtaddr=c00000\0"			\
+	"fdtaddr=1e00000\0"			\
 	"fdtfile=mpc8548cds.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND						\
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 2e6989f..390b1ef 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -668,7 +668,7 @@
 "consoledev=ttyS0\0"				\
 "ramdiskaddr=2000000\0"			\
 "ramdiskfile=8572ds/ramdisk.uboot\0"		\
-"fdtaddr=c00000\0"				\
+"fdtaddr=1e00000\0"				\
 "fdtfile=8572ds/mpc8572ds.dtb\0"		\
 "bdev=sda3\0"
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 5384584..5b6b4bd 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -862,7 +862,7 @@ extern unsigned long get_sdram_size(void);
 	"consoledev=ttyS0\0"				\
 	"ramdiskaddr=2000000\0"			\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
-	"fdtaddr=c00000\0"				\
+	"fdtaddr=1e00000\0"				\
 	"fdtfile=p1010rdb.dtb\0"		\
 	"bdev=sda1\0"	\
 	"hwconfig=usb1:dr_mode=host,phy_type=utmi\0"	\
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index bdf0323..fe19957 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -731,7 +731,7 @@
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
-	"fdtaddr=c00000\0"	  			      	\
+	"fdtaddr=1e00000\0"	  			      	\
 	"fdtfile=p1022ds.dtb\0"	  				\
 	"bdev=sda3\0"		  			      	\
 	"hwconfig=esdhc;audclk:12\0"
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 07a594d..d044c7b 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -375,7 +375,7 @@ extern unsigned long get_clock_freq(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=p1023rdb.dtb\0"				\
 	"othbootargs=ramdisk_size=600000\0"			\
 	"bdev=sda1\0"						\
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 24e5431..8479410 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -698,7 +698,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 	"usb_dr_mode=host\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=p2041rdb/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=p2041rdb/p2041rdb.dtb\0"			\
 	"bdev=sda3\0"
 
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 06d1d0f..25a0652 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -897,7 +897,7 @@ unsigned long get_board_ddr_clk(void);
 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"bdev=sda3\0"
 
 #define CONFIG_LINUX					\
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 9f5063c..7ce6420 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -770,7 +770,7 @@ unsigned long get_board_ddr_clk(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=t1040qds/t1040qds.dtb\0"			\
 	"bdev=sda3\0"
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 2ec1962..ae1acbd 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -900,7 +900,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=" __stringify(RAMDISKFILE) "\0"		\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=" __stringify(FDTFILE) "\0"			\
 	"bdev=sda3\0"
 
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 1f07a83..6217555 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -840,7 +840,7 @@ unsigned long get_board_ddr_clk(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=t2080qds/t2080qds.dtb\0"			\
 	"bdev=sda3\0"
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 0ded41e..7a7de97 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -792,7 +792,7 @@ unsigned long get_board_ddr_clk(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
 	"bdev=sda3\0"
 
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index f075dfb..85aab18 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -577,7 +577,7 @@ unsigned long get_board_ddr_clk(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=t4240qds/t4240qds.dtb\0"				\
 	"bdev=sda3\0"
 
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 9ba69a1..4133165 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -770,7 +770,7 @@ unsigned long get_board_ddr_clk(void);
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
 	"bdev=sda3\0"
 
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 30c2831..44e115d 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -447,7 +447,7 @@
 	"consoledev=ttyS1\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=controlcenterd.dtb\0"				\
 	"bdev=sda3\0"
 
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 4a770b0..0c99e9f 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -708,7 +708,7 @@
 	"consoledev=ttyS0\0"					\
 	"ramdiskaddr=2000000\0"					\
 	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
-	"fdtaddr=c00000\0"					\
+	"fdtaddr=1e00000\0"					\
 	"fdtfile=p4080ds/p4080ds.dtb\0"				\
 	"bdev=sda3\0"
 
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 708d5f7..da38709 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -520,7 +520,7 @@
 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
 "consoledev=ttyS0\0"					\
 "ramdiskaddr=2000000\0"					\
-"fdtaddr=c00000\0"					\
+"fdtaddr=1e00000\0"					\
 "bdev=sda3\0"
 
 #define CONFIG_HDBOOT					\
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 4f22d12..3d33421 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -989,7 +989,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
 "consoledev=ttyS0\0"	\
 "ramdiskaddr=2000000\0"	\
 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
-"fdtaddr=c00000\0"	\
+"fdtaddr=1e00000\0"	\
 "bdev=sda1\0" \
 "jffs2nor=mtdblock3\0"	\
 "norbootaddr=ef080000\0"	\
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 30bfbf4..79e4991 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -513,7 +513,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 "consoledev=ttyS0\0"	\
 "ramdiskaddr=2000000\0"	\
 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
-"fdtaddr=c00000\0"	\
+"fdtaddr=1e00000\0"	\
 "bdev=sda1\0"	\
 "norbootaddr=ef080000\0"	\
 "norfdtaddr=ef040000\0"	\
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 46766a6..ec9ad45 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -595,7 +595,7 @@
 "consoledev=ttyS0\0"				\
 "ramdiskaddr=2000000\0"			\
 "ramdiskfile=uRamdisk\0"			\
-"fdtaddr=c00000\0"				\
+"fdtaddr=1e00000\0"				\
 "fdtfile=sbc8548.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND						\
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 73c8d5b..bc91714 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -304,7 +304,7 @@ extern void out32(unsigned int, unsigned long);
 	"osfile=/home/user/board.uImage\0"				\
 	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
-	"fdtaddr=c00000\0"						\
+	"fdtaddr=0x1e00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot="CONFIG_PROG_UBOOT"\0"				\
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 9f3158d..eaea33b 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -699,7 +699,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 	"osfile=/home/user/board.uImage\0"				\
 	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
-	"fdtaddr=c00000\0"						\
+	"fdtaddr=0x1e00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index a418fc5..f7cfc9e 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -483,7 +483,7 @@
 	"osfile=/home/user/board.uImage\0"				\
 	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
-	"fdtaddr=c00000\0"						\
+	"fdtaddr=0x1e00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 36df668..3306e44a 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -554,7 +554,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 	"osfile=/home/user/board.uImage\0"				\
 	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
-	"fdtaddr=c00000\0"						\
+	"fdtaddr=0x1e00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 1794ba1..276dde7 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -538,7 +538,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 	"osfile=/home/user/board.uImage\0"				\
 	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
-	"fdtaddr=c00000\0"						\
+	"fdtaddr=0x1e00000\0"						\
 	"osaddr=0x1000000\0"						\
 	"loadaddr=0x1000000\0"						\
 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
-- 
cgit v0.10.2


From 95d52733036af7438a5285d729d53844ec48c63e Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Thu, 21 Jul 2016 15:38:13 -0400
Subject: Revert "stm32: Change USART port to USART6 for stm32f746 discovery
 board"

Per Vikas' request, the problem this commit is supposed to be solving is
something he doesn't see and further this introduces additional hardware
requirements.

This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
index 0bd4695..38adc4e 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -17,13 +17,11 @@
 enum periph_id {
 	UART1_GPIOA_9_10 = 0,
 	UART2_GPIOD_5_6,
-	UART6_GPIOC_6_7,
 };
 
 enum periph_clock {
 	USART1_CLOCK_CFG = 0,
 	USART2_CLOCK_CFG,
-	USART6_CLOCK_CFG,
 	GPIO_A_CLOCK_CFG,
 	GPIO_B_CLOCK_CFG,
 	GPIO_C_CLOCK_CFG,
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
index ac47850..78d22d4 100644
--- a/arch/arm/mach-stm32/stm32f7/clock.c
+++ b/arch/arm/mach-stm32/stm32f7/clock.c
@@ -245,9 +245,6 @@ void clock_setup(int peripheral)
 	case USART1_CLOCK_CFG:
 		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
 		break;
-	case USART6_CLOCK_CFG:
-		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART6EN);
-		break;
 	case GPIO_A_CLOCK_CFG:
 		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
 		break;
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 47aa058..404fdfa 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -32,7 +32,7 @@ const struct stm32_gpio_ctl gpio_ctl_usart = {
 	.otype = STM32_GPIO_OTYPE_PP,
 	.speed = STM32_GPIO_SPEED_50M,
 	.pupd = STM32_GPIO_PUPD_UP,
-	.af = STM32_GPIO_AF8
+	.af = STM32_GPIO_AF7
 };
 
 const struct stm32_gpio_ctl gpio_ctl_fmc = {
@@ -251,8 +251,8 @@ int dram_init(void)
 }
 
 static const struct stm32_gpio_dsc usart_gpio[] = {
-	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_6},	/* TX */
-	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_7},	/* RX */
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
+	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7},	/* RX */
 };
 
 int uart_setup_gpio(void)
@@ -260,7 +260,8 @@ int uart_setup_gpio(void)
 	int i;
 	int rv = 0;
 
-	clock_setup(GPIO_C_CLOCK_CFG);
+	clock_setup(GPIO_A_CLOCK_CFG);
+	clock_setup(GPIO_B_CLOCK_CFG);
 	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
 		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
 		if (rv)
@@ -272,7 +273,7 @@ out:
 }
 
 static const struct stm32x7_serial_platdata serial_platdata = {
-	.base = (struct stm32_usart *)USART6_BASE,
+	.base = (struct stm32_usart *)USART1_BASE,
 	.clock = CONFIG_SYS_CLK_FREQ,
 };
 
@@ -291,7 +292,7 @@ int board_early_init_f(void)
 	int res;
 
 	res = uart_setup_gpio();
-	clock_setup(USART6_CLOCK_CFG);
+	clock_setup(USART1_CLOCK_CFG);
 	if (res)
 		return res;
 
-- 
cgit v0.10.2


From 72d8d5d773b1882508e0db0fa6d516ced170c923 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 21 Jun 2016 14:39:11 +0200
Subject: ARM: zynq/zynqmp: Use the default CONFIG_BOOTDELAY=2

Based on:
"ARM: uniphier: use the default CONFIG_BOOTDELAY=2"
(sha1: 7c8ef0feb97586d35b0296b48903daef8c06ab21)

"I do not insist on CONFIG_BOOTDELAY=3. The default value in Kconfig,
CONFIG_BOOTDELAY=2, is just fine for these boards."

Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 7325f19..fa380ef 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 91af8ce..35226d6 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 3e73312..cc13179 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 2805219..6570348 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 32bea4b..e1fc8b0 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index d7eb8c2..2829029 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 80a59ef..92633d6 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index d88c61b..d0b1ec9 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index aeb1270..3624424 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYS_CONFIG_NAME="zynq_picozed"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index d68ed0e..e1b1fc9 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 8bd9230..63d32d9 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 81f16ec..6ccbb8c 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -7,7 +7,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 271fcfd..e6c646b 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -7,7 +7,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index a9ea971..a8cfeb8 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -7,7 +7,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 56062b1..f2d00ca 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -7,7 +7,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index c70b860..7783eeb 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 624545e..9236c5e 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -6,7 +6,6 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
-CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
-- 
cgit v0.10.2


From 211815784c0e35a274e13054a7966b21098f8a14 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 6 Jun 2016 10:58:40 +0200
Subject: api: Disable api_net when DM is used

When CONFIG_API is selected with DM_ETH this
error is present:
api/api_net.c: In function 'dev_enum_net':
api/api_net.c:61:35: warning: initialization from incompatible pointer
type
  struct eth_device *eth_current = eth_get_dev();
                                   ^
api/api_net.c:68:39: error: dereferencing pointer to incomplete type
  memcpy(di->di_net.hwaddr, eth_current->enetaddr, 6);
                                       ^
Disable api_net functions when ETH_DM is selected.

Signed-off-by: Chris Johns <chrisj@rtems.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/api/api_net.c b/api/api_net.c
index 04e4f4a..67c2916 100644
--- a/api/api_net.c
+++ b/api/api_net.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
 
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
 
 static int dev_valid_net(void *cookie)
 {
-- 
cgit v0.10.2


From 1d405e207bb176c937d44f9a5f87e268022c2416 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Thu, 25 Feb 2016 12:51:50 +0530
Subject: mmc: sdhci: Disable internal clock enable bit

Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index de8d8ea..9fdbed8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -313,7 +313,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 	}
 
 	reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-	reg &= ~SDHCI_CLOCK_CARD_EN;
+	reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
 	sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
 
 	if (clock == 0)
-- 
cgit v0.10.2


From 1eefe14f66c982bf7145e9d3b57fafd1f17fe12f Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 27 Apr 2016 16:07:20 +0200
Subject: spl: Fix compilation warnings for arm64
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make code 64bit aware.

Warnings:
+../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’:
+../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
+../common/spl/spl_fat.c: In function ‘spl_load_image_fat’:
+../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index e428868..c1b8534 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -60,7 +60,7 @@ void __noreturn jump_to_image_linux(void *arg)
 	typedef void (*image_entry_arg_t)(int, int, void *)
 		__attribute__ ((noreturn));
 	image_entry_arg_t image_entry =
-		(image_entry_arg_t) spl_image.entry_point;
+		(image_entry_arg_t)(uintptr_t) spl_image.entry_point;
 	cleanup_before_linux();
 	image_entry(0, machid, arg);
 }
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index db67618..73d33f5 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -88,7 +88,8 @@ int spl_load_image_fat(struct blk_desc *block_dev,
 		if (err)
 			goto end;
 
-		err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+		err = file_fat_read(filename,
+				    (u8 *)(uintptr_t)spl_image.load_addr, 0);
 	}
 
 end:
-- 
cgit v0.10.2


From 1f29738ad13ad178185490db0bb17ad71343e251 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Jul 2016 15:07:54 +0200
Subject: ARM64: zynqmp: Enable CLK and SPL_CLK by default

Serial driver starts to use clk framework that's why
enable it by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 585b408..397981a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -669,6 +669,8 @@ config ARCH_ZYNQMP
 	select OF_CONTROL
 	select DM_SERIAL
 	select SUPPORT_SPL
+	select CLK
+	select SPL_CLK
 
 config TEGRA
 	bool "NVIDIA Tegra"
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index fa380ef..b02ab08 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -42,8 +42,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 35226d6..b115862 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -33,8 +33,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index cc13179..d1e8778 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -33,8 +33,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 6570348..4342e05 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -29,8 +29,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index e1fc8b0..06c07c1 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -28,8 +28,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 2829029..140b800 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -32,8 +32,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 92633d6..727e22c 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -32,8 +32,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
-- 
cgit v0.10.2


From f3d1cc2ff387ffe22ccd1bdcb2a998ec46149c6d Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 15 Jul 2016 08:41:46 +0200
Subject: ARM64: zynqmp: Enable SPL for all zynqmp boards

Compile SPL for all boards even psu_init.c/h files are not in the tree
yet. But this change enables covering SPL issues in mainline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index b02ab08..79f3adc 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -2,11 +2,14 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -40,8 +43,10 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index b115862..51637fc 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -2,11 +2,14 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -31,8 +34,10 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index d1e8778..9fa1562 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -2,11 +2,14 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -31,8 +34,10 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 4342e05..efa7b8c 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -2,10 +2,13 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -27,8 +30,10 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 06c07c1..a6818c1 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -2,10 +2,13 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -27,7 +30,9 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 140b800..b0303f6 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -2,10 +2,13 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -30,8 +33,10 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 727e22c..b2b5208 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -2,10 +2,13 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
+CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
@@ -30,8 +33,10 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
-- 
cgit v0.10.2


From 59da82ef824ec8ef94c362bef79954f02f3345e1 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Jul 2016 14:40:03 +0200
Subject: serial: zynq: Read information about clock from DT

Read information about clock frequency from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>

diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 66d54e3..4f6e7e4 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -5,6 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <clk.h>
 #include <common.h>
 #include <debug_uart.h>
 #include <dm.h>
@@ -108,8 +109,33 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
 int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct zynq_uart_priv *priv = dev_get_priv(dev);
-	unsigned long clock = get_uart_clk(0);
+	unsigned long clock;
 
+#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
+	int ret;
+	struct clk clk;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get clock\n");
+		return ret;
+	}
+
+	clock = clk_get_rate(&clk);
+	if (IS_ERR_VALUE(clock)) {
+		dev_err(dev, "failed to get rate\n");
+		return clock;
+	}
+	debug("%s: CLK %ld\n", __func__, clock);
+
+	ret = clk_enable(&clk);
+	if (ret && ret != -ENOSYS) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
+#else
+	clock = get_uart_clk(0);
+#endif
 	_uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
 
 	return 0;
-- 
cgit v0.10.2


From 23ffd36a5295354af2dee22c00b08addd9c8a2ed Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Jul 2016 14:41:28 +0200
Subject: ARM64: zynqmp: Remove get_uart_clk()

ZynqMP will use reading clock freq directly from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
index 690c72d..f7e5ebf 100644
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ b/arch/arm/cpu/armv8/zynqmp/clk.c
@@ -12,22 +12,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned long get_uart_clk(int dev_id)
-{
-	u32 ver = zynqmp_get_silicon_version();
-
-	switch (ver) {
-	case ZYNQMP_CSU_VERSION_VELOCE:
-		return 48000;
-	case ZYNQMP_CSU_VERSION_EP108:
-		return 25000000;
-	case ZYNQMP_CSU_VERSION_QEMU:
-		return 133000000;
-	}
-
-	return 100000000;
-}
-
 unsigned long zynqmp_get_system_timer_freq(void)
 {
 	u32 ver = zynqmp_get_silicon_version();
diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h
index b18333d..bfd53b5 100644
--- a/arch/arm/include/asm/arch-zynqmp/clk.h
+++ b/arch/arm/include/asm/arch-zynqmp/clk.h
@@ -8,7 +8,6 @@
 #ifndef _ASM_ARCH_CLK_H_
 #define _ASM_ARCH_CLK_H_
 
-unsigned long get_uart_clk(int dev_id);
 unsigned long zynqmp_get_system_timer_freq(void);
 
 #endif /* _ASM_ARCH_CLK_H_ */
-- 
cgit v0.10.2


From 9e0758b7ff399d39cc62f24ab1c790485030834f Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 14 Jul 2016 13:11:37 +0200
Subject: dm: clk: Remove simple version of clk_get_by_index/name()

Simple version of clk_get_by_index() added by:
"dm: clk: Add a simple version of clk_get_by_index()"
(sha1: a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44)
is only working for #clock-cells=<1> but not for
any other values. Fixed clocks is using #clock-cells=<0>
which requires full implementation.

Remove simplified versions of clk_get_by_index() and use full version.
Also remove empty clk_get_by_name() which is failing when it is called
which is useless.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index e0f8567..4d78e3f 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -21,7 +21,6 @@ static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-#ifdef CONFIG_SPL_BUILD
 # if CONFIG_IS_ENABLED(OF_PLATDATA)
 int clk_get_by_index_platdata(struct udevice *dev, int index,
 			      struct phandle_2_cell *cells, struct clk *clk)
@@ -38,31 +37,6 @@ int clk_get_by_index_platdata(struct udevice *dev, int index,
 	return 0;
 }
 # else
-int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
-{
-	int ret;
-	u32 cell[2];
-
-	if (index != 0)
-		return -ENOSYS;
-	assert(clk);
-	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
-	if (ret)
-		return ret;
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
-				   cell, 2);
-	if (ret)
-		return ret;
-	clk->id = cell[1];
-	return 0;
-}
-# endif /* OF_PLATDATA */
-
-int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
-{
-	return -ENOSYS;
-}
-#else
 static int clk_of_xlate_default(struct clk *clk,
 				struct fdtdec_phandle_args *args)
 {
@@ -119,6 +93,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 
 	return clk_request(dev_clk, clk);
 }
+# endif /* OF_PLATDATA */
 
 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
 {
@@ -135,7 +110,6 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
 
 	return clk_get_by_index(dev, index, clk);
 }
-#endif /* CONFIG_SPL_BUILD */
 #endif /* OF_CONTROL */
 
 int clk_request(struct udevice *dev, struct clk *clk)
-- 
cgit v0.10.2


From 91afeb30103aeae3a4c32cc48d07c40a215cbe90 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 21 Jul 2016 13:47:52 +0200
Subject: microblaze: Remove empty ifdef around caches

Code around was removed because of move to Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 93fb166..047e756 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -175,10 +175,6 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MFSL
 
-#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
-#else
-#endif
-
 #if defined(FLASH)
 # define CONFIG_CMD_JFFS2
 # define CONFIG_CMD_UBI
-- 
cgit v0.10.2


From 3bac8303e4840f6902a51f9665696ff3939596f4 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 21 Jul 2016 01:34:00 +0200
Subject: ARM64: zynqmp: Enable AHCI on EP platform

The EP platform also has working AHCI emulation, so I see little reason
not to implement the plumbing for it that enables us to boot from AHCI.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index c5bd5da..44434aa 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -17,6 +17,7 @@
 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ	(CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_AHCI
+#define CONFIG_SATA_CEVA
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
 				 ZYNQMP_USB1_XHCI_BASEADDR}
 
-- 
cgit v0.10.2


From 2cdc778b62e46439dff84560a2def3032099f129 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Fri, 22 Jul 2016 14:51:51 +0530
Subject: usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQ

Add Kconfig entry config option for USB_EHCI_ZYNQ
and update the same to enable for all zynq boards
which supports USB

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index d0b1ec9..8337948 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -37,6 +37,8 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 3624424..6eb8f03 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -27,6 +27,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index e1b1fc9..b9e13f2 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -42,6 +42,8 @@ CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 63d32d9..c13c077 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -38,6 +38,8 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7783eeb..c23e664 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -37,6 +37,8 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 9236c5e..c5884e2 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -40,6 +40,8 @@ CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 89580cc..5092251 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -85,6 +85,13 @@ config USB_EHCI_MSM
 	  This driver supports combination of Chipidea USB controller
 	  and Synapsys USB PHY in host mode only.
 
+config USB_EHCI_ZYNQ
+	bool "Support for Xilinx Zynq on-chip EHCI USB controller"
+	depends on ARCH_ZYNQ
+	default y
+	---help---
+	  Enable support for Zynq on-chip EHCI USB controller
+
 config USB_EHCI_GENERIC
 	bool "Support for generic EHCI USB controller"
 	depends on OF_CONTROL
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 8dbac87..08b7602 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -86,10 +86,8 @@
 # define CONFIG_ZYNQ_SDHCI_MAX_FREQ	52000000
 #endif
 
-#ifdef CONFIG_ZYNQ_USB
-# define CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_USB_STORAGE
-# define CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_EHCI_IS_TDI
 # define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
index ec7bb1c..e66088d 100644
--- a/include/configs/zynq_microzed.h
+++ b/include/configs/zynq_microzed.h
@@ -12,8 +12,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ZYNQ_USB
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_MICROZED_H */
diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h
index adc4d0f..f2598a2 100644
--- a/include/configs/zynq_picozed.h
+++ b/include/configs/zynq_picozed.h
@@ -12,8 +12,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ZYNQ_USB
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_PICOZED_H */
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index 8a04590..a27b49c 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -12,7 +12,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_EEPROM
 
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index 150cb4a..dbb4621 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -12,8 +12,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ZYNQ_USB
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_ZED_H */
diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index 637b1c5..ca3ad9c 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -13,7 +13,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-- 
cgit v0.10.2


From 2ae9fbe00f71b8e48a04a13a71a9f6b42b70f158 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Fri, 22 Jul 2016 15:00:26 +0530
Subject: usb: zynq: Define config USB_STORAGE through defconfig

Define config USB_STORAGE through defconfig for all
respective zynq boards

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 8337948..d6208a4 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -42,6 +42,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 6eb8f03..b0927ca 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -32,6 +32,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index b9e13f2..9ee2e06 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -47,6 +47,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index c13c077..a03f96e 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -43,6 +43,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index c23e664..959a535 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -42,6 +42,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index c5884e2..520d8c7 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -45,6 +45,7 @@ CONFIG_USB_EHCI=y
 CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 08b7602..e59e412 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -87,7 +87,6 @@
 #endif
 
 #ifdef CONFIG_USB_EHCI_ZYNQ
-# define CONFIG_USB_STORAGE
 # define CONFIG_EHCI_IS_TDI
 # define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
-- 
cgit v0.10.2


From 4d25507f3df9b7c06e04b40b6d42f895493c5435 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Tue, 19 Jul 2016 10:42:22 +0530
Subject: Kconfig: Move option CONFIG_SYS_NO_FLASH to Kconfig

Move config option CONFIG_SYS_NO_FLASH as Kconfig
option. All the boards which needs to enable this
option can be done through defconfigs

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/common/Kconfig b/common/Kconfig
index 8adc821..46e7173 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -197,3 +197,9 @@ config CONSOLE_RECORD_IN_SIZE
 	  tstc() and getc() will use this in preference to real device input.
 	  The buffer is allocated immediately after the malloc() region is
 	  ready.
+
+config SYS_NO_FLASH
+	bool "Disable support for parallel NOR flash"
+	default n
+	help
+	  This option is used to disable support for parallel NOR flash.
-- 
cgit v0.10.2


From 05f4cc344f6f2eed6f13094a6687e60ce5e881b2 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Tue, 19 Jul 2016 10:43:42 +0530
Subject: zynq: config: Enable CONFIG_SYS_NO_FLASH through defconfig

Enable config CONFIG_SYS_NO_FLASH through defconfig
for all zynq boards.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index d6208a4..f1589b1 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index b0927ca..0687f59 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 9ee2e06..ba5e16d 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index a03f96e..38ee30a 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 6ccbb8c..2a74894 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index e6c646b..a2a1ac1 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index f2d00ca..d71208c 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 959a535..18213e5 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 520d8c7..679414a 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
index e66088d..53b1287 100644
--- a/include/configs/zynq_microzed.h
+++ b/include/configs/zynq_microzed.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_ZYNQ_MICROZED_H
 #define __CONFIG_ZYNQ_MICROZED_H
 
-#define CONFIG_SYS_NO_FLASH
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_MICROZED_H */
diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h
index f2598a2..119722a 100644
--- a/include/configs/zynq_picozed.h
+++ b/include/configs/zynq_picozed.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_ZYNQ_PICOZED_H
 #define __CONFIG_ZYNQ_PICOZED_H
 
-#define CONFIG_SYS_NO_FLASH
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_PICOZED_H */
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index a27b49c..fc46fec 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_ZYNQ_ZC70X_H
 #define __CONFIG_ZYNQ_ZC70X_H
 
-#define CONFIG_SYS_NO_FLASH
-
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_EEPROM
 
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 35622ae..7c6cf8d 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -10,13 +10,6 @@
 #ifndef __CONFIG_ZYNQ_ZC770_H
 #define __CONFIG_ZYNQ_ZC770_H
 
-#define CONFIG_SYS_NO_FLASH
-
-#if defined(CONFIG_ZC770_XM012)
-# undef CONFIG_SYS_NO_FLASH
-
-#endif
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_ZC770_H */
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index dbb4621..ece0629 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_ZYNQ_ZED_H
 #define __CONFIG_ZYNQ_ZED_H
 
-#define CONFIG_SYS_NO_FLASH
-
 #include <configs/zynq-common.h>
 
 #endif /* __CONFIG_ZYNQ_ZED_H */
diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h
index ca3ad9c..b9ff391 100644
--- a/include/configs/zynq_zybo.h
+++ b/include/configs/zynq_zybo.h
@@ -11,8 +11,6 @@
 #ifndef __CONFIG_ZYNQ_ZYBO_H
 #define __CONFIG_ZYNQ_ZYBO_H
 
-#define CONFIG_SYS_NO_FLASH
-
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_I2C1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-- 
cgit v0.10.2


From 766d2609dd7fbad0faa89c7dff26edc108afa890 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Tue, 19 Jul 2016 10:43:43 +0530
Subject: zynq: defconfig: Remove unnecessary board specific config files

Remove unnecessary board specifc config files for
zynq boards(microzed, picozed, ZC770(all), zed) and point
to zynq common config file.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index f1589b1..bc80057 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_microzed"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_SPL=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 0687f59..8002384 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_picozed"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 2a74894..341204e 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zc770"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
 CONFIG_SPL=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index a2a1ac1..4e9eb3e 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zc770"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
 CONFIG_SPL=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index a8cfeb8..b3a75a6 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zc770"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
 CONFIG_SPL=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index d71208c..98dbbd6 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zc770"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
 CONFIG_SPL=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 18213e5..d5d6223 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="zynq_zed"
+CONFIG_SYS_CONFIG_NAME="zynq-common"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
 CONFIG_SPL=y
diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h
deleted file mode 100644
index 53b1287..0000000
--- a/include/configs/zynq_microzed.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2013 Xilinx, Inc.
- *
- * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
- * See zynq-common.h for Zynq common configs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQ_MICROZED_H
-#define __CONFIG_ZYNQ_MICROZED_H
-
-#include <configs/zynq-common.h>
-
-#endif /* __CONFIG_ZYNQ_MICROZED_H */
diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h
deleted file mode 100644
index 119722a..0000000
--- a/include/configs/zynq_picozed.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2015 Xilinx, Inc.
- *
- * Configuration for PicoZed
- * See zynq-common.h for Zynq common configs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQ_PICOZED_H
-#define __CONFIG_ZYNQ_PICOZED_H
-
-#include <configs/zynq-common.h>
-
-#endif /* __CONFIG_ZYNQ_PICOZED_H */
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
deleted file mode 100644
index 7c6cf8d..0000000
--- a/include/configs/zynq_zc770.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2013 Xilinx, Inc.
- *
- * Configuration settings for the Xilinx Zynq ZC770 board.
- * See zynq-common.h for Zynq common configs
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQ_ZC770_H
-#define __CONFIG_ZYNQ_ZC770_H
-
-#include <configs/zynq-common.h>
-
-#endif /* __CONFIG_ZYNQ_ZC770_H */
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
deleted file mode 100644
index ece0629..0000000
--- a/include/configs/zynq_zed.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2013 Xilinx, Inc.
- *
- * Configuration for Zynq Evaluation and Development Board - ZedBoard
- * See zynq-common.h for Zynq common configs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_ZYNQ_ZED_H
-#define __CONFIG_ZYNQ_ZED_H
-
-#include <configs/zynq-common.h>
-
-#endif /* __CONFIG_ZYNQ_ZED_H */
-- 
cgit v0.10.2


From d7e28918aa3f4bafc15b16c546826d43fbcbe9f6 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 22 Jun 2016 15:14:16 +0200
Subject: i2c_eeprom: Add reading support

This patch implements the reading functionality for the generic I2C
EEPROM driver, which was just a non-functional stub until now.

Since the page size will be of importance for the writing support, we
add suitable members to the private data structure to keep track of it.

Compatibility strings for a range of at24c* chips are added.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 2373037..b84e351 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -144,4 +144,9 @@ config QFW
 	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
 	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
 
+config I2C_EEPROM
+	bool "Enable driver for generic I2C-attached EEPROMs"
+	depends on MISC
+	help
+	  Enable a generic driver for EEPROMs attached via I2C.
 endmenu
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index 814134a..c9f4174 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -13,7 +13,7 @@
 static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf,
 			   int size)
 {
-	return -ENODEV;
+	return dm_i2c_read(dev, offset, buf, size);
 }
 
 static int i2c_eeprom_write(struct udevice *dev, int offset,
@@ -27,23 +27,46 @@ struct i2c_eeprom_ops i2c_eeprom_std_ops = {
 	.write	= i2c_eeprom_write,
 };
 
+static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)
+{
+	struct i2c_eeprom *priv = dev_get_priv(dev);
+	u64 data = dev_get_driver_data(dev);
+
+	/* 6 bit -> page size of up to 2^63 (should be sufficient) */
+	priv->pagewidth = data & 0x3F;
+	priv->pagesize = (1 << priv->pagewidth);
+
+	return 0;
+}
+
 int i2c_eeprom_std_probe(struct udevice *dev)
 {
 	return 0;
 }
 
 static const struct udevice_id i2c_eeprom_std_ids[] = {
-	{ .compatible = "i2c-eeprom" },
+	{ .compatible = "i2c-eeprom", .data = 0 },
+	{ .compatible = "atmel,24c01a", .data = 3 },
+	{ .compatible = "atmel,24c02", .data = 3 },
+	{ .compatible = "atmel,24c04", .data = 4 },
+	{ .compatible = "atmel,24c08a", .data = 4 },
+	{ .compatible = "atmel,24c16a", .data = 4 },
+	{ .compatible = "atmel,24c32", .data = 5 },
+	{ .compatible = "atmel,24c64", .data = 5 },
+	{ .compatible = "atmel,24c128", .data = 6 },
+	{ .compatible = "atmel,24c256", .data = 6 },
+	{ .compatible = "atmel,24c512", .data = 6 },
 	{ }
 };
 
 U_BOOT_DRIVER(i2c_eeprom_std) = {
-	.name		= "i2c_eeprom",
-	.id		= UCLASS_I2C_EEPROM,
-	.of_match	= i2c_eeprom_std_ids,
-	.probe		= i2c_eeprom_std_probe,
-	.priv_auto_alloc_size = sizeof(struct i2c_eeprom),
-	.ops		= &i2c_eeprom_std_ops,
+	.name			= "i2c_eeprom",
+	.id			= UCLASS_I2C_EEPROM,
+	.of_match		= i2c_eeprom_std_ids,
+	.probe			= i2c_eeprom_std_probe,
+	.ofdata_to_platdata	= i2c_eeprom_std_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct i2c_eeprom),
+	.ops			= &i2c_eeprom_std_ops,
 };
 
 UCLASS_DRIVER(i2c_eeprom) = {
diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h
index ea6c962..0452892 100644
--- a/include/i2c_eeprom.h
+++ b/include/i2c_eeprom.h
@@ -14,6 +14,10 @@ struct i2c_eeprom_ops {
 };
 
 struct i2c_eeprom {
+	/* The EEPROM's page size in byte */
+	unsigned long pagesize;
+	/* The EEPROM's page width in bits (pagesize = 2^pagewidth) */
+	unsigned pagewidth;
 };
 
 #endif
-- 
cgit v0.10.2


From 05fc5ef161779ed1b0b479e8d085026d6994731a Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:09 +0200
Subject: mtd: Sort subsystem directories aplhabeticaly in Makefile

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/Makefile b/drivers/Makefile
index 1723958..b3ac8a6 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -19,14 +19,14 @@ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
 obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
 obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
 obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/
 obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
 obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/
-obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
+obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
 obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
-- 
cgit v0.10.2


From e1a89e9358b8cedd98ad346cccd08e1bca669072 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Tue, 12 Jul 2016 20:28:10 +0200
Subject: nand_spl_simple: Add a simple NAND read function

To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 60a7607..55f48d3 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -209,6 +209,68 @@ static int nand_read_page(int block, int page, void *dst)
 }
 #endif
 
+#ifdef CONFIG_SPL_UBI
+/*
+ * Temporary storage for non NAND page aligned and non NAND page sized
+ * reads. Note: This does not support runtime detected FLASH yet, but
+ * that should be reasonably easy to fix by making the buffer large
+ * enough :)
+ */
+static u8 scratch_buf[CONFIG_SYS_NAND_PAGE_SIZE];
+
+/**
+ * nand_spl_read_block - Read data from physical eraseblock into a buffer
+ * @block:	Number of the physical eraseblock
+ * @offset:	Data offset from the start of @peb
+ * @len:	Data size to read
+ * @dst:	Address of the destination buffer
+ *
+ * This could be further optimized if we'd have a subpage read
+ * function in the simple code. On NAND which allows subpage reads
+ * this would spare quite some time to readout e.g. the VID header of
+ * UBI.
+ *
+ * Notes:
+ *	@offset + @len are not allowed to be larger than a physical
+ *	erase block. No sanity check done for simplicity reasons.
+ *
+ * To support runtime detected flash this needs to be extended by
+ * information about the actual flash geometry, but thats beyond the
+ * scope of this effort and for most applications where fast boot is
+ * required it is not an issue anyway.
+ */
+int nand_spl_read_block(int block, int offset, int len, void *dst)
+{
+	int page, read;
+
+	/* Calculate the page number */
+	page = offset / CONFIG_SYS_NAND_PAGE_SIZE;
+
+	/* Offset to the start of a flash page */
+	offset = offset % CONFIG_SYS_NAND_PAGE_SIZE;
+
+	while (len) {
+		/*
+		 * Non page aligned reads go to the scratch buffer.
+		 * Page aligned reads go directly to the destination.
+		 */
+		if (offset || len < CONFIG_SYS_NAND_PAGE_SIZE) {
+			nand_read_page(block, page, scratch_buf);
+			read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset);
+			memcpy(dst, scratch_buf + offset, read);
+			offset = 0;
+		} else {
+			nand_read_page(block, page, dst);
+			read = CONFIG_SYS_NAND_PAGE_SIZE;
+		}
+		page++;
+		len -= read;
+		dst += read;
+	}
+	return 0;
+}
+#endif
+
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
 	unsigned int block, lastblock;
diff --git a/include/nand.h b/include/nand.h
index a4f0f92..627b217 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -122,6 +122,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
 int nand_get_lock_status(struct mtd_info *mtd, loff_t offset);
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
+int nand_spl_read_block(int block, int offset, int len, void *dst);
 void nand_deselect(void);
 
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
-- 
cgit v0.10.2


From 735717d18a012a6f34c74dd98cec8f46bac5c51c Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:11 +0200
Subject: onenand_spl_simple: Add a simple OneNAND read function

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c
index fe6b7d9..1925f41 100644
--- a/drivers/mtd/onenand/onenand_spl.c
+++ b/drivers/mtd/onenand/onenand_spl.c
@@ -93,6 +93,54 @@ static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf,
 	return 0;
 }
 
+#ifdef CONFIG_SPL_UBI
+/* Temporary storage for non page aligned and non page sized reads. */
+static u8 scratch_buf[PAGE_4K];
+
+/**
+ * onenand_spl_read_block - Read data from physical eraseblock into a buffer
+ * @block:	Number of the physical eraseblock
+ * @offset:	Data offset from the start of @peb
+ * @len:	Data size to read
+ * @dst:	Address of the destination buffer
+ *
+ * Notes:
+ *	@offset + @len are not allowed to be larger than a physical
+ *	erase block. No sanity check done for simplicity reasons.
+ */
+int onenand_spl_read_block(int block, int offset, int len, void *dst)
+{
+	int page, read, psize;
+
+	psize = onenand_spl_get_geometry();
+	/* Calculate the page number */
+	page = offset / psize;
+	/* Offset to the start of a flash page */
+	offset = offset % psize;
+
+	while (len) {
+		/*
+		 * Non page aligned reads go to the scratch buffer.
+		 * Page aligned reads go directly to the destination.
+		 */
+		if (offset || len < psize) {
+			onenand_spl_read_page(block, page,
+			                      (uint32_t *)scratch_buf, psize);
+			read = min(len, psize - offset);
+			memcpy(dst, scratch_buf + offset, read);
+			offset = 0;
+		} else {
+			onenand_spl_read_page(block, page, dst, psize);
+			read = psize;
+		}
+		page++;
+		len -= read;
+		dst += read;
+	}
+	return 0;
+}
+#endif
+
 void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst)
 {
 	uint32_t *addr = (uint32_t *)dst;
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index fd01040..d69e0d2 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -49,6 +49,7 @@ extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
 					int boundary, int lock);
 
 /* SPL */
+int onenand_spl_read_block(int block, int offset, int len, void *dst);
 void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
 
 #endif /* __UBOOT_ONENAND_H */
-- 
cgit v0.10.2


From 6f4e7d3c75a81decc20de0218729e9770448ffc0 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Tue, 12 Jul 2016 20:28:12 +0200
Subject: spl: Lightweight UBI and UBI fastmap support

Booting a payload out of NAND FLASH from the SPL is a crux today, as
it requires hard partioned FLASH. Not a brilliant idea with the
reliability of todays NAND FLASH chips.

The upstream UBI + UBI fastmap implementation which is about to
brought to u-boot is too heavy weight for SPLs as it provides way more
functionality than needed for a SPL and does not even fit into the
restricted SPL areas which are loaded from the SoC boot ROM.

So this provides a fast and lightweight implementation of UBI scanning
and UBI fastmap attach. The scan and logical to physical block mapping
code is developed from scratch, while the fastmap implementation is
lifted from the linux kernel source and stripped down to fit the SPL
needs.

The text foot print on the board which I used for development is:

6854	0	0	6854	1abd
drivers/mtd/ubispl/built-in.o

Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are
reserved for the SPL) takes:

In full scan mode:      1172ms
In fastmap mode:          95ms

The code requires quite some storage. The largest and unknown part of
it is the number of fastmap blocks to read. Therefor the data
structure is not put into the BSS. The code requires a pointer to free
memory handed in which is initialized by the UBI attach code itself.

See doc/README.ubispl for further information on how to use it.

This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi
There is no way to share the fastmap code, as UBISPL only utilizes the
slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap()
from the original kernel ubi fastmap implementation.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 9e8f55d..9ecac55 100644
--- a/README
+++ b/README
@@ -3583,6 +3583,10 @@ FIT uImage format:
 		Support for NAND boot using simple NAND drivers that
 		expose the cmd_ctrl() interface.
 
+		CONFIG_SPL_UBI
+		Support for a lightweight UBI (fastmap) scanner and
+		loader
+
 		CONFIG_SPL_MTD_SUPPORT
 		Support for the MTD subsystem within SPL.  Useful for
 		environment on NAND support within SPL.
diff --git a/doc/README.ubispl b/doc/README.ubispl
new file mode 100644
index 0000000..ff008bc
--- /dev/null
+++ b/doc/README.ubispl
@@ -0,0 +1,141 @@
+Lightweight UBI and UBI fastmap support
+
+# Copyright (C) Thomas Gleixner <tglx@linutronix.de>
+#
+# SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+
+Scans the UBI information and loads the requested static volumes into
+memory.
+
+Configuration Options:
+
+   CONFIG_SPL_UBI
+     Enables the SPL UBI support
+
+   CONFIG_SPL_UBI_MAX_VOL_LEBS
+     The maximum number of logical eraseblocks which a static volume
+     to load can contain. Used for sizing the scan data structure
+
+   CONFIG_SPL_UBI_MAX_PEB_SIZE
+     The maximum physical erase block size. Either a compile time
+     constant or runtime detection. Used for sizing the scan data
+     structure
+
+   CONFIG_SPL_UBI_MAX_PEBS
+     The maximum physical erase block count. Either a compile time
+     constant or runtime detection. Used for sizing the scan data
+     structure
+
+   CONFIG_SPL_UBI_VOL_IDS
+     The maximum volume ids which can be loaded. Used for sizing the
+     scan data structure.
+
+Usage notes:
+
+In the board config file define for example:
+
+#define CONFIG_SPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	(256*1024)
+#define CONFIG_SPL_UBI_MAX_PEBS		4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+
+The size requirement is roughly as follows:
+
+    2k for the basic data structure
+  + CONFIG_SPL_UBI_VOL_IDS * CONFIG_SPL_UBI_MAX_VOL_LEBS * 8
+  + CONFIG_SPL_UBI_MAX_PEBS * 64
+  + CONFIG_SPL_UBI_MAX_PEB_SIZE * UBI_FM_MAX_BLOCKS
+
+The last one is big, but I really don't care in that stage. Real world
+implementations only use the first couple of blocks, but the code
+handles up to UBI_FM_MAX_BLOCKS.
+
+Given the above configuration example the requirement is about 5M
+which is usually not a problem to reserve in the RAM along with the
+other areas like the kernel/dts load address.
+
+So something like this will do the trick:
+
+#define SPL_FINFO_ADDR			0x80800000
+#define SPL_DTB_LOAD_ADDR		0x81800000
+#define SPL_KERNEL_LOAD_ADDR		0x82000000
+
+In the board file, implement the following:
+
+static struct ubispl_load myvolumes[] = {
+	{
+		.vol_id		= 0,	/* kernel volume */
+		.load_addr	= (void *)SPL_KERNEL_LOAD_ADDR,
+	},
+	{
+		.vol_id		= 1,	/* DT blob */
+		.load_addr	= (void *)SPL_DTB_LOAD_ADDR,
+	}
+};
+
+int spl_start_uboot(void)
+{
+	struct ubispl_info info;
+
+	info.ubi = (struct ubi_scan_info *) SPL_FINFO_ADDR;
+	info.fastmap = 1;
+	info.read = nand_spl_read_flash;
+
+#if COMPILE_TIME_DEFINED
+	/*
+	 * MY_NAND_NR_SPL_PEBS is the number of physical erase blocks
+	 * in the FLASH which are reserved for the SPL. Think about
+	 * mtd partitions:
+	 *
+	 * part_spl { .start = 0, .end = 4 }
+	 * part_ubi { .start = 4, .end = NR_PEBS }
+	 */
+	info.peb_offset = MY_NAND_NR_SPL_PEBS;
+	info.peb_size = CONFIG_SYS_NAND_BLOCK_SIZE;
+	info.vid_offset = MY_NAND_UBI_VID_OFFS;
+	info.leb_start = MY_NAND_UBI_DATA_OFFS;
+	info.peb_count = MY_NAND_UBI_NUM_PEBS;
+#else
+	get_flash_info(&flash_info);
+	info.peb_offset = MY_NAND_NR_SPL_PEBS;
+	info.peb_size = flash_info.peb_size;
+
+	/*
+	 * The VID and Data offset depend on the capability of the
+	 * FLASH chip to do subpage writes.
+	 *
+	 * If the flash chip supports subpage writes, then the VID
+	 * header starts at the second subpage. So for 2k pages size
+	 * with 4 subpages the VID offset is 512. The DATA offset is 2k.
+	 *
+	 * If the flash chip does not support subpage writes then the
+	 * VID offset is FLASH_PAGE_SIZE and the DATA offset
+	 * 2 * FLASH_PAGE_SIZE
+	 */
+	info.vid_offset = flash_info.vid_offset;
+	info.leb_start = flash_info.data_offset;
+
+	/*
+	 * The flash reports the total number of erase blocks, so
+	 * we need to subtract the number of blocks which are reserved
+	 * for the SPL itself and not managed by UBI.
+	 */
+	info.peb_count = flash_info.peb_count - MY_NAND_NR_SPL_PEBS;
+#endif
+
+	ret = ubispl_load_volumes(&info, myvolumes, ARRAY_SIZE(myvolumes);
+
+	....
+
+}
+
+Note: you can load any payload that way. You can even load u-boot from
+UBI, so the only non UBI managed FLASH area is the one which is
+reserved for the SPL itself and read from the SoC ROM.
+
+And you can do fallback scenarios:
+
+    if (ubispl_load_volumes(&info, volumes0, ARRAY_SIZE(volumes0)))
+        if (ubispl_load_volumes(&info, volumes1, ARRAY_SIZE(volumes1)))
+	    ubispl_load_volumes(&info, vol_uboot, ARRAY_SIZE(vol_uboot));
diff --git a/drivers/Makefile b/drivers/Makefile
index b3ac8a6..ad5cbae 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
 obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
 obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
+obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
 obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
diff --git a/drivers/mtd/ubispl/Makefile b/drivers/mtd/ubispl/Makefile
new file mode 100644
index 0000000..740dbed
--- /dev/null
+++ b/drivers/mtd/ubispl/Makefile
@@ -0,0 +1 @@
+obj-y += ubispl.o ../ubi/crc32.o
diff --git a/drivers/mtd/ubispl/ubi-wrapper.h b/drivers/mtd/ubispl/ubi-wrapper.h
new file mode 100644
index 0000000..72b9dcb
--- /dev/null
+++ b/drivers/mtd/ubispl/ubi-wrapper.h
@@ -0,0 +1,106 @@
+/*
+ * The parts taken from the kernel implementation are:
+ *
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * UBISPL specific defines:
+ *
+ * Copyright (c) Thomas Gleixner <tglx@linutronix.de>
+ *
+ * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+ */
+
+/*
+ * Contains various defines copy&pasted from ubi.h and ubi-user.h to make
+ * the upstream fastboot code happy.
+ */
+#ifndef __UBOOT_UBI_WRAPPER_H
+#define __UBOOT_UBI_WRAPPER_H
+
+/*
+ * Error codes returned by the I/O sub-system.
+ *
+ * UBI_IO_FF: the read region of flash contains only 0xFFs
+ * UBI_IO_FF_BITFLIPS: the same as %UBI_IO_FF, but also also there was a data
+ *                     integrity error reported by the MTD driver
+ *                     (uncorrectable ECC error in case of NAND)
+ * UBI_IO_BAD_HDR: the EC or VID header is corrupted (bad magic or CRC)
+ * UBI_IO_BAD_HDR_EBADMSG: the same as %UBI_IO_BAD_HDR, but also there was a
+ *                         data integrity error reported by the MTD driver
+ *                         (uncorrectable ECC error in case of NAND)
+ * UBI_IO_BITFLIPS: bit-flips were detected and corrected
+ *
+ * UBI_FASTMAP_ANCHOR:  u-boot SPL add on to tell the caller that the fastmap
+ *			anchor block has been found
+ *
+ * Note, it is probably better to have bit-flip and ebadmsg as flags which can
+ * be or'ed with other error code. But this is a big change because there are
+ * may callers, so it does not worth the risk of introducing a bug
+ */
+enum {
+	UBI_IO_FF = 1,
+	UBI_IO_FF_BITFLIPS,
+	UBI_IO_BAD_HDR,
+	UBI_IO_BAD_HDR_EBADMSG,
+	UBI_IO_BITFLIPS,
+	UBI_FASTMAP_ANCHOR,
+};
+
+/*
+ * UBI volume type constants.
+ *
+ * @UBI_DYNAMIC_VOLUME: dynamic volume
+ * @UBI_STATIC_VOLUME:  static volume
+ */
+enum {
+	UBI_DYNAMIC_VOLUME = 3,
+	UBI_STATIC_VOLUME  = 4,
+};
+
+/*
+ * Return codes of the fastmap sub-system
+ *
+ * UBI_NO_FASTMAP: No fastmap super block was found
+ * UBI_BAD_FASTMAP: A fastmap was found but it's unusable
+ */
+enum {
+	UBI_NO_FASTMAP = 1,
+	UBI_BAD_FASTMAP,
+};
+
+/**
+ * struct ubi_fastmap_layout - in-memory fastmap data structure.
+ * @e: PEBs used by the current fastmap
+ * @to_be_tortured: if non-zero tortured this PEB
+ * @used_blocks: number of used PEBs
+ * @max_pool_size: maximal size of the user pool
+ * @max_wl_pool_size: maximal size of the pool used by the WL sub-system
+ */
+struct ubi_fastmap_layout {
+	struct ubi_wl_entry *e[UBI_FM_MAX_BLOCKS];
+	int to_be_tortured[UBI_FM_MAX_BLOCKS];
+	int used_blocks;
+	int max_pool_size;
+	int max_wl_pool_size;
+};
+
+/**
+ * struct ubi_fm_pool - in-memory fastmap pool
+ * @pebs: PEBs in this pool
+ * @used: number of used PEBs
+ * @size: total number of PEBs in this pool
+ * @max_size: maximal size of the pool
+ *
+ * A pool gets filled with up to max_size.
+ * If all PEBs within the pool are used a new fastmap will be written
+ * to the flash and the pool gets refilled with empty PEBs.
+ *
+ */
+struct ubi_fm_pool {
+	int pebs[UBI_FM_MAX_POOL_SIZE];
+	int used;
+	int size;
+	int max_size;
+};
+
+#endif
diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c
new file mode 100644
index 0000000..a81a8e7
--- /dev/null
+++ b/drivers/mtd/ubispl/ubispl.c
@@ -0,0 +1,926 @@
+/*
+ * Copyright (c) Thomas Gleixner <tglx@linutronix.de>
+ *
+ * The parts taken from the kernel implementation are:
+ *
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <ubispl.h>
+
+#include <linux/crc32.h>
+
+#include "ubispl.h"
+
+/**
+ * ubi_calc_fm_size - calculates the fastmap size in bytes for an UBI device.
+ * @ubi: UBI device description object
+ */
+static size_t ubi_calc_fm_size(struct ubi_scan_info *ubi)
+{
+	size_t size;
+
+	size = sizeof(struct ubi_fm_sb) +
+		sizeof(struct ubi_fm_hdr) +
+		sizeof(struct ubi_fm_scan_pool) +
+		sizeof(struct ubi_fm_scan_pool) +
+		(ubi->peb_count * sizeof(struct ubi_fm_ec)) +
+		(sizeof(struct ubi_fm_eba) +
+		(ubi->peb_count * sizeof(__be32))) +
+		sizeof(struct ubi_fm_volhdr) * UBI_MAX_VOLUMES;
+	return roundup(size, ubi->leb_size);
+}
+
+static int ubi_io_read(struct ubi_scan_info *ubi, void *buf, int pnum,
+		       unsigned long from, unsigned long len)
+{
+	return ubi->read(pnum + ubi->peb_offset, from, len, buf);
+}
+
+static int ubi_io_is_bad(struct ubi_scan_info *ubi, int peb)
+{
+	return peb >= ubi->peb_count || peb < 0;
+}
+
+static int ubi_io_read_vid_hdr(struct ubi_scan_info *ubi, int pnum,
+			       struct ubi_vid_hdr *vh, int unused)
+{
+	u32 magic;
+	int res;
+
+	/* No point in rescanning a corrupt block */
+	if (test_bit(pnum, ubi->corrupt))
+		return UBI_IO_BAD_HDR;
+	/*
+	 * If the block has been scanned already, no need to rescan
+	 */
+	if (test_and_set_bit(pnum, ubi->scanned))
+		return 0;
+
+	res = ubi_io_read(ubi, vh, pnum, ubi->vid_offset, sizeof(*vh));
+
+	/*
+	 * Bad block, unrecoverable ECC error, skip the block
+	 */
+	if (res) {
+		ubi_dbg("Skipping bad or unreadable block %d", pnum);
+		vh->magic = 0;
+		generic_set_bit(pnum, ubi->corrupt);
+		return res;
+	}
+
+	/* Magic number available ? */
+	magic = be32_to_cpu(vh->magic);
+	if (magic != UBI_VID_HDR_MAGIC) {
+		generic_set_bit(pnum, ubi->corrupt);
+		if (magic == 0xffffffff)
+			return UBI_IO_FF;
+		ubi_msg("Bad magic in block 0%d %08x", pnum, magic);
+		return UBI_IO_BAD_HDR;
+	}
+
+	/* Header CRC correct ? */
+	if (crc32(UBI_CRC32_INIT, vh, UBI_VID_HDR_SIZE_CRC) !=
+	    be32_to_cpu(vh->hdr_crc)) {
+		ubi_msg("Bad CRC in block 0%d", pnum);
+		generic_set_bit(pnum, ubi->corrupt);
+		return UBI_IO_BAD_HDR;
+	}
+
+	ubi_dbg("RV: pnum: %i sqnum %llu", pnum, be64_to_cpu(vh->sqnum));
+
+	return 0;
+}
+
+static int ubi_rescan_fm_vid_hdr(struct ubi_scan_info *ubi,
+				 struct ubi_vid_hdr *vh,
+				 u32 fm_pnum, u32 fm_vol_id, u32 fm_lnum)
+{
+	int res;
+
+	if (ubi_io_is_bad(ubi, fm_pnum))
+		return -EINVAL;
+
+	res = ubi_io_read_vid_hdr(ubi, fm_pnum, vh, 0);
+	if (!res) {
+		/* Check volume id, volume type and lnum */
+		if (be32_to_cpu(vh->vol_id) == fm_vol_id &&
+		    vh->vol_type == UBI_VID_STATIC &&
+		    be32_to_cpu(vh->lnum) == fm_lnum)
+			return 0;
+		ubi_dbg("RS: PEB %u vol: %u : %u typ %u lnum %u %u",
+			fm_pnum, fm_vol_id, vh->vol_type,
+			be32_to_cpu(vh->vol_id),
+			fm_lnum, be32_to_cpu(vh->lnum));
+	}
+	return res;
+}
+
+/* Insert the logic block into the volume info */
+static int ubi_add_peb_to_vol(struct ubi_scan_info *ubi,
+			      struct ubi_vid_hdr *vh, u32 vol_id,
+			      u32 pnum, u32 lnum)
+{
+	struct ubi_vol_info *vi = ubi->volinfo + vol_id;
+	u32 *ltp;
+
+	/*
+	 * If the volume is larger than expected, yell and give up :(
+	 */
+	if (lnum >= UBI_MAX_VOL_LEBS) {
+		ubi_warn("Vol: %u LEB %d > %d", vol_id, lnum, UBI_MAX_VOL_LEBS);
+		return -EINVAL;
+	}
+
+	ubi_dbg("SC: Add PEB %u to Vol %u as LEB %u fnd %d sc %d",
+		pnum, vol_id, lnum, !!test_bit(lnum, vi->found),
+		!!test_bit(pnum, ubi->scanned));
+
+	/* Points to the translation entry */
+	ltp = vi->lebs_to_pebs + lnum;
+
+	/* If the block is already assigned, check sqnum */
+	if (__test_and_set_bit(lnum, vi->found)) {
+		u32 cur_pnum = *ltp;
+		struct ubi_vid_hdr *cur = ubi->blockinfo + cur_pnum;
+
+		/*
+		 * If the current block hase not yet been scanned, we
+		 * need to do that. The other block might be stale or
+		 * the current block corrupted and the FM not yet
+		 * updated.
+		 */
+		if (!test_bit(cur_pnum, ubi->scanned)) {
+			/*
+			 * If the scan fails, we use the valid block
+			 */
+			if (ubi_rescan_fm_vid_hdr(ubi, cur, cur_pnum, vol_id,
+						  lnum)) {
+				*ltp = pnum;
+				return 0;
+			}
+		}
+
+		/*
+		 * Should not happen ....
+		 */
+		if (test_bit(cur_pnum, ubi->corrupt)) {
+			*ltp = pnum;
+			return 0;
+		}
+
+		ubi_dbg("Vol %u LEB %u PEB %u->sqnum %llu NPEB %u->sqnum %llu",
+			vol_id, lnum, cur_pnum, be64_to_cpu(cur->sqnum), pnum,
+			be64_to_cpu(vh->sqnum));
+
+		/*
+		 * Compare sqnum and take the newer one
+		 */
+		if (be64_to_cpu(cur->sqnum) < be64_to_cpu(vh->sqnum))
+			*ltp = pnum;
+	} else {
+		*ltp = pnum;
+		if (lnum > vi->last_block)
+			vi->last_block = lnum;
+	}
+
+	return 0;
+}
+
+static int ubi_scan_vid_hdr(struct ubi_scan_info *ubi, struct ubi_vid_hdr *vh,
+			    u32 pnum)
+{
+	u32 vol_id, lnum;
+	int res;
+
+	if (ubi_io_is_bad(ubi, pnum))
+		return -EINVAL;
+
+	res = ubi_io_read_vid_hdr(ubi, pnum, vh, 0);
+	if (res)
+		return res;
+
+	/* Get volume id */
+	vol_id = be32_to_cpu(vh->vol_id);
+
+	/* If this is the fastmap anchor, return right away */
+	if (vol_id == UBI_FM_SB_VOLUME_ID)
+		return ubi->fm_enabled ? UBI_FASTMAP_ANCHOR : 0;
+
+	/* We only care about static volumes with an id < UBI_SPL_VOL_IDS */
+	if (vol_id >= UBI_SPL_VOL_IDS || vh->vol_type != UBI_VID_STATIC)
+		return 0;
+
+	/* We are only interested in the volumes to load */
+	if (!test_bit(vol_id, ubi->toload))
+		return 0;
+
+	lnum = be32_to_cpu(vh->lnum);
+	return ubi_add_peb_to_vol(ubi, vh, vol_id, pnum, lnum);
+}
+
+static int assign_aeb_to_av(struct ubi_scan_info *ubi, u32 pnum, u32 lnum,
+			     u32 vol_id, u32 vol_type, u32 used)
+{
+	struct ubi_vid_hdr *vh;
+
+	if (ubi_io_is_bad(ubi, pnum))
+		return -EINVAL;
+
+	ubi->fastmap_pebs++;
+
+	if (vol_id >= UBI_SPL_VOL_IDS || vol_type != UBI_STATIC_VOLUME)
+		return 0;
+
+	/* We are only interested in the volumes to load */
+	if (!test_bit(vol_id, ubi->toload))
+		return 0;
+
+	vh = ubi->blockinfo + pnum;
+
+	return ubi_scan_vid_hdr(ubi, vh, pnum);
+}
+
+static int scan_pool(struct ubi_scan_info *ubi, __be32 *pebs, int pool_size)
+{
+	struct ubi_vid_hdr *vh;
+	u32 pnum;
+	int i;
+
+	ubi_dbg("Scanning pool size: %d", pool_size);
+
+	for (i = 0; i < pool_size; i++) {
+		pnum = be32_to_cpu(pebs[i]);
+
+		if (ubi_io_is_bad(ubi, pnum)) {
+			ubi_err("FM: Bad PEB in fastmap pool! %u", pnum);
+			return UBI_BAD_FASTMAP;
+		}
+
+		vh = ubi->blockinfo + pnum;
+		/*
+		 * We allow the scan to fail here. The loader will notice
+		 * and look for a replacement.
+		 */
+		ubi_scan_vid_hdr(ubi, vh, pnum);
+	}
+	return 0;
+}
+
+/*
+ * Fastmap code is stolen from Linux kernel and this stub structure is used
+ * to make it happy.
+ */
+struct ubi_attach_info {
+	int i;
+};
+
+static int ubi_attach_fastmap(struct ubi_scan_info *ubi,
+			      struct ubi_attach_info *ai,
+			      struct ubi_fastmap_layout *fm)
+{
+	struct ubi_fm_hdr *fmhdr;
+	struct ubi_fm_scan_pool *fmpl1, *fmpl2;
+	struct ubi_fm_ec *fmec;
+	struct ubi_fm_volhdr *fmvhdr;
+	struct ubi_fm_eba *fm_eba;
+	int ret, i, j, pool_size, wl_pool_size;
+	size_t fm_pos = 0, fm_size = ubi->fm_size;
+	void *fm_raw = ubi->fm_buf;
+
+	memset(ubi->fm_used, 0, sizeof(ubi->fm_used));
+
+	fm_pos += sizeof(struct ubi_fm_sb);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+
+	fmhdr = (struct ubi_fm_hdr *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmhdr);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+
+	if (be32_to_cpu(fmhdr->magic) != UBI_FM_HDR_MAGIC) {
+		ubi_err("bad fastmap header magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmhdr->magic), UBI_FM_HDR_MAGIC);
+		goto fail_bad;
+	}
+
+	fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl1);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+	if (be32_to_cpu(fmpl1->magic) != UBI_FM_POOL_MAGIC) {
+		ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmpl1->magic), UBI_FM_POOL_MAGIC);
+		goto fail_bad;
+	}
+
+	fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl2);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+	if (be32_to_cpu(fmpl2->magic) != UBI_FM_POOL_MAGIC) {
+		ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmpl2->magic), UBI_FM_POOL_MAGIC);
+		goto fail_bad;
+	}
+
+	pool_size = be16_to_cpu(fmpl1->size);
+	wl_pool_size = be16_to_cpu(fmpl2->size);
+	fm->max_pool_size = be16_to_cpu(fmpl1->max_size);
+	fm->max_wl_pool_size = be16_to_cpu(fmpl2->max_size);
+
+	if (pool_size > UBI_FM_MAX_POOL_SIZE || pool_size < 0) {
+		ubi_err("bad pool size: %i", pool_size);
+		goto fail_bad;
+	}
+
+	if (wl_pool_size > UBI_FM_MAX_POOL_SIZE || wl_pool_size < 0) {
+		ubi_err("bad WL pool size: %i", wl_pool_size);
+		goto fail_bad;
+	}
+
+	if (fm->max_pool_size > UBI_FM_MAX_POOL_SIZE ||
+	    fm->max_pool_size < 0) {
+		ubi_err("bad maximal pool size: %i", fm->max_pool_size);
+		goto fail_bad;
+	}
+
+	if (fm->max_wl_pool_size > UBI_FM_MAX_POOL_SIZE ||
+	    fm->max_wl_pool_size < 0) {
+		ubi_err("bad maximal WL pool size: %i", fm->max_wl_pool_size);
+		goto fail_bad;
+	}
+
+	/* read EC values from free list */
+	for (i = 0; i < be32_to_cpu(fmhdr->free_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+	}
+
+	/* read EC values from used list */
+	for (i = 0; i < be32_to_cpu(fmhdr->used_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		generic_set_bit(be32_to_cpu(fmec->pnum), ubi->fm_used);
+	}
+
+	/* read EC values from scrub list */
+	for (i = 0; i < be32_to_cpu(fmhdr->scrub_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+	}
+
+	/* read EC values from erase list */
+	for (i = 0; i < be32_to_cpu(fmhdr->erase_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+	}
+
+	/* Iterate over all volumes and read their EBA table */
+	for (i = 0; i < be32_to_cpu(fmhdr->vol_count); i++) {
+		u32 vol_id, vol_type, used, reserved;
+
+		fmvhdr = (struct ubi_fm_volhdr *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmvhdr);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		if (be32_to_cpu(fmvhdr->magic) != UBI_FM_VHDR_MAGIC) {
+			ubi_err("bad fastmap vol header magic: 0x%x, " \
+				"expected: 0x%x",
+				be32_to_cpu(fmvhdr->magic), UBI_FM_VHDR_MAGIC);
+			goto fail_bad;
+		}
+
+		vol_id = be32_to_cpu(fmvhdr->vol_id);
+		vol_type = fmvhdr->vol_type;
+		used = be32_to_cpu(fmvhdr->used_ebs);
+
+		fm_eba = (struct ubi_fm_eba *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fm_eba);
+		fm_pos += (sizeof(__be32) * be32_to_cpu(fm_eba->reserved_pebs));
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		if (be32_to_cpu(fm_eba->magic) != UBI_FM_EBA_MAGIC) {
+			ubi_err("bad fastmap EBA header magic: 0x%x, " \
+				"expected: 0x%x",
+				be32_to_cpu(fm_eba->magic), UBI_FM_EBA_MAGIC);
+			goto fail_bad;
+		}
+
+		reserved = be32_to_cpu(fm_eba->reserved_pebs);
+		ubi_dbg("FA: vol %u used %u res: %u", vol_id, used, reserved);
+		for (j = 0; j < reserved; j++) {
+			int pnum = be32_to_cpu(fm_eba->pnum[j]);
+
+			if ((int)be32_to_cpu(fm_eba->pnum[j]) < 0)
+				continue;
+
+			if (!__test_and_clear_bit(pnum, ubi->fm_used))
+				continue;
+
+			/*
+			 * We only handle static volumes so used_ebs
+			 * needs to be handed in. And we do not assign
+			 * the reserved blocks
+			 */
+			if (j >= used)
+				continue;
+
+			ret = assign_aeb_to_av(ubi, pnum, j, vol_id,
+					       vol_type, used);
+			if (!ret)
+				continue;
+
+			/*
+			 * Nasty: The fastmap claims that the volume
+			 * has one block more than it, but that block
+			 * is always empty and the other blocks have
+			 * the correct number of total LEBs in the
+			 * headers. Deal with it.
+			 */
+			if (ret != UBI_IO_FF && j != used - 1)
+				goto fail_bad;
+			ubi_dbg("FA: Vol: %u Ignoring empty LEB %d of %d",
+				vol_id, j, used);
+		}
+	}
+
+	ret = scan_pool(ubi, fmpl1->pebs, pool_size);
+	if (ret)
+		goto fail;
+
+	ret = scan_pool(ubi, fmpl2->pebs, wl_pool_size);
+	if (ret)
+		goto fail;
+
+#ifdef CHECKME
+	/*
+	 * If fastmap is leaking PEBs (must not happen), raise a
+	 * fat warning and fall back to scanning mode.
+	 * We do this here because in ubi_wl_init() it's too late
+	 * and we cannot fall back to scanning.
+	 */
+	if (WARN_ON(count_fastmap_pebs(ai) != ubi->peb_count -
+		    ai->bad_peb_count - fm->used_blocks))
+		goto fail_bad;
+#endif
+
+	return 0;
+
+fail_bad:
+	ret = UBI_BAD_FASTMAP;
+fail:
+	return ret;
+}
+
+static int ubi_scan_fastmap(struct ubi_scan_info *ubi,
+			    struct ubi_attach_info *ai,
+			    int fm_anchor)
+{
+	struct ubi_fm_sb *fmsb, *fmsb2;
+	struct ubi_vid_hdr *vh;
+	struct ubi_fastmap_layout *fm;
+	int i, used_blocks, pnum, ret = 0;
+	size_t fm_size;
+	__be32 crc, tmp_crc;
+	unsigned long long sqnum = 0;
+
+	fmsb = &ubi->fm_sb;
+	fm = &ubi->fm_layout;
+
+	ret = ubi_io_read(ubi, fmsb, fm_anchor, ubi->leb_start, sizeof(*fmsb));
+	if (ret && ret != UBI_IO_BITFLIPS)
+		goto free_fm_sb;
+	else if (ret == UBI_IO_BITFLIPS)
+		fm->to_be_tortured[0] = 1;
+
+	if (be32_to_cpu(fmsb->magic) != UBI_FM_SB_MAGIC) {
+		ubi_err("bad super block magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmsb->magic), UBI_FM_SB_MAGIC);
+		ret = UBI_BAD_FASTMAP;
+		goto free_fm_sb;
+	}
+
+	if (fmsb->version != UBI_FM_FMT_VERSION) {
+		ubi_err("bad fastmap version: %i, expected: %i",
+			fmsb->version, UBI_FM_FMT_VERSION);
+		ret = UBI_BAD_FASTMAP;
+		goto free_fm_sb;
+	}
+
+	used_blocks = be32_to_cpu(fmsb->used_blocks);
+	if (used_blocks > UBI_FM_MAX_BLOCKS || used_blocks < 1) {
+		ubi_err("number of fastmap blocks is invalid: %i", used_blocks);
+		ret = UBI_BAD_FASTMAP;
+		goto free_fm_sb;
+	}
+
+	fm_size = ubi->leb_size * used_blocks;
+	if (fm_size != ubi->fm_size) {
+		ubi_err("bad fastmap size: %zi, expected: %zi", fm_size,
+			ubi->fm_size);
+		ret = UBI_BAD_FASTMAP;
+		goto free_fm_sb;
+	}
+
+	vh = &ubi->fm_vh;
+
+	for (i = 0; i < used_blocks; i++) {
+		pnum = be32_to_cpu(fmsb->block_loc[i]);
+
+		if (ubi_io_is_bad(ubi, pnum)) {
+			ret = UBI_BAD_FASTMAP;
+			goto free_hdr;
+		}
+
+#ifdef LATER
+		int image_seq;
+		ret = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i EC (PEB: %i)",
+				i, pnum);
+			if (ret > 0)
+				ret = UBI_BAD_FASTMAP;
+			goto free_hdr;
+		} else if (ret == UBI_IO_BITFLIPS)
+			fm->to_be_tortured[i] = 1;
+
+		image_seq = be32_to_cpu(ech->image_seq);
+		if (!ubi->image_seq)
+			ubi->image_seq = image_seq;
+		/*
+		 * Older UBI implementations have image_seq set to zero, so
+		 * we shouldn't fail if image_seq == 0.
+		 */
+		if (image_seq && (image_seq != ubi->image_seq)) {
+			ubi_err("wrong image seq:%d instead of %d",
+				be32_to_cpu(ech->image_seq), ubi->image_seq);
+			ret = UBI_BAD_FASTMAP;
+			goto free_hdr;
+		}
+#endif
+		ret = ubi_io_read_vid_hdr(ubi, pnum, vh, 0);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i (PEB: %i)",
+				i, pnum);
+			goto free_hdr;
+		}
+
+		/*
+		 * Mainline code rescans the anchor header. We've done
+		 * that already so we merily copy it over.
+		 */
+		if (pnum == fm_anchor)
+			memcpy(vh, ubi->blockinfo + pnum, sizeof(*fm));
+
+		if (i == 0) {
+			if (be32_to_cpu(vh->vol_id) != UBI_FM_SB_VOLUME_ID) {
+				ubi_err("bad fastmap anchor vol_id: 0x%x," \
+					" expected: 0x%x",
+					be32_to_cpu(vh->vol_id),
+					UBI_FM_SB_VOLUME_ID);
+				ret = UBI_BAD_FASTMAP;
+				goto free_hdr;
+			}
+		} else {
+			if (be32_to_cpu(vh->vol_id) != UBI_FM_DATA_VOLUME_ID) {
+				ubi_err("bad fastmap data vol_id: 0x%x," \
+					" expected: 0x%x",
+					be32_to_cpu(vh->vol_id),
+					UBI_FM_DATA_VOLUME_ID);
+				ret = UBI_BAD_FASTMAP;
+				goto free_hdr;
+			}
+		}
+
+		if (sqnum < be64_to_cpu(vh->sqnum))
+			sqnum = be64_to_cpu(vh->sqnum);
+
+		ret = ubi_io_read(ubi, ubi->fm_buf + (ubi->leb_size * i), pnum,
+				  ubi->leb_start, ubi->leb_size);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i (PEB: %i, " \
+				"err: %i)", i, pnum, ret);
+			goto free_hdr;
+		}
+	}
+
+	fmsb2 = (struct ubi_fm_sb *)(ubi->fm_buf);
+	tmp_crc = be32_to_cpu(fmsb2->data_crc);
+	fmsb2->data_crc = 0;
+	crc = crc32(UBI_CRC32_INIT, ubi->fm_buf, fm_size);
+	if (crc != tmp_crc) {
+		ubi_err("fastmap data CRC is invalid");
+		ubi_err("CRC should be: 0x%x, calc: 0x%x", tmp_crc, crc);
+		ret = UBI_BAD_FASTMAP;
+		goto free_hdr;
+	}
+
+	fmsb2->sqnum = sqnum;
+
+	fm->used_blocks = used_blocks;
+
+	ret = ubi_attach_fastmap(ubi, ai, fm);
+	if (ret) {
+		if (ret > 0)
+			ret = UBI_BAD_FASTMAP;
+		goto free_hdr;
+	}
+
+	ubi->fm = fm;
+	ubi->fm_pool.max_size = ubi->fm->max_pool_size;
+	ubi->fm_wl_pool.max_size = ubi->fm->max_wl_pool_size;
+	ubi_msg("attached by fastmap %uMB %u blocks",
+		ubi->fsize_mb, ubi->peb_count);
+	ubi_dbg("fastmap pool size: %d", ubi->fm_pool.max_size);
+	ubi_dbg("fastmap WL pool size: %d", ubi->fm_wl_pool.max_size);
+
+out:
+	if (ret)
+		ubi_err("Attach by fastmap failed, doing a full scan!");
+	return ret;
+
+free_hdr:
+free_fm_sb:
+	goto out;
+}
+
+/*
+ * Scan the flash and attempt to attach via fastmap
+ */
+static void ipl_scan(struct ubi_scan_info *ubi)
+{
+	unsigned int pnum;
+	int res;
+
+	/*
+	 * Scan first for the fastmap super block
+	 */
+	for (pnum = 0; pnum < UBI_FM_MAX_START; pnum++) {
+		res = ubi_scan_vid_hdr(ubi, ubi->blockinfo + pnum, pnum);
+		/*
+		 * We ignore errors here as we are meriliy scanning
+		 * the headers.
+		 */
+		if (res != UBI_FASTMAP_ANCHOR)
+			continue;
+
+		/*
+		 * If fastmap is disabled, continue scanning. This
+		 * might happen because the previous attempt failed or
+		 * the caller disabled it right away.
+		 */
+		if (!ubi->fm_enabled)
+			continue;
+
+		/*
+		 * Try to attach the fastmap, if that fails continue
+		 * scanning.
+		 */
+		if (!ubi_scan_fastmap(ubi, NULL, pnum))
+			return;
+		/*
+		 * Fastmap failed. Clear everything we have and start
+		 * over. We are paranoid and do not trust anything.
+		 */
+		memset(ubi->volinfo, 0, sizeof(ubi->volinfo));
+		pnum = 0;
+		break;
+	}
+
+	/*
+	 * Continue scanning, ignore errors, we might find what we are
+	 * looking for,
+	 */
+	for (; pnum < ubi->peb_count; pnum++)
+		ubi_scan_vid_hdr(ubi, ubi->blockinfo + pnum, pnum);
+}
+
+/*
+ * Load a logical block of a volume into memory
+ */
+static int ubi_load_block(struct ubi_scan_info *ubi, uint8_t *laddr,
+			  struct ubi_vol_info *vi, u32 vol_id, u32 lnum,
+			  u32 last)
+{
+	struct ubi_vid_hdr *vh, *vrepl;
+	u32 pnum, crc, dlen;
+
+retry:
+	/*
+	 * If this is a fastmap run, we try to rescan full, otherwise
+	 * we simply give up.
+	 */
+	if (!test_bit(lnum, vi->found)) {
+		ubi_warn("LEB %d of %d is missing", lnum, last);
+		return -EINVAL;
+	}
+
+	pnum = vi->lebs_to_pebs[lnum];
+
+	ubi_dbg("Load vol %u LEB %u PEB %u", vol_id, lnum, pnum);
+
+	if (ubi_io_is_bad(ubi, pnum)) {
+		ubi_warn("Corrupted mapping block %d PB %d\n", lnum, pnum);
+		return -EINVAL;
+	}
+
+	if (test_bit(pnum, ubi->corrupt))
+		goto find_other;
+
+	/*
+	 * Lets try to read that block
+	 */
+	vh = ubi->blockinfo + pnum;
+
+	if (!test_bit(pnum, ubi->scanned)) {
+		ubi_warn("Vol: %u LEB %u PEB %u not yet scanned", vol_id,
+			 lnum, pnum);
+		if (ubi_rescan_fm_vid_hdr(ubi, vh, pnum, vol_id, lnum))
+			goto find_other;
+	}
+
+	/*
+	 * Check, if the total number of blocks is correct
+	 */
+	if (be32_to_cpu(vh->used_ebs) != last) {
+		ubi_dbg("Block count missmatch.");
+		ubi_dbg("vh->used_ebs: %d nrblocks: %d",
+			be32_to_cpu(vh->used_ebs), last);
+		generic_set_bit(pnum, ubi->corrupt);
+		goto find_other;
+	}
+
+	/*
+	 * Get the data length of this block.
+	 */
+	dlen = be32_to_cpu(vh->data_size);
+
+	/*
+	 * Read the data into RAM. We ignore the return value
+	 * here as the only thing which might go wrong are
+	 * bitflips. Try nevertheless.
+	 */
+	ubi_io_read(ubi, laddr, pnum, ubi->leb_start, dlen);
+
+	/* Calculate CRC over the data */
+	crc = crc32(UBI_CRC32_INIT, laddr, dlen);
+
+	if (crc != be32_to_cpu(vh->data_crc)) {
+		ubi_warn("Vol: %u LEB %u PEB %u data CRC failure", vol_id,
+			 lnum, pnum);
+		generic_set_bit(pnum, ubi->corrupt);
+		goto find_other;
+	}
+
+	/* We are good. Return the data length we read */
+	return dlen;
+
+find_other:
+	ubi_dbg("Find replacement for LEB %u PEB %u", lnum, pnum);
+	generic_clear_bit(lnum, vi->found);
+	vrepl = NULL;
+
+	for (pnum = 0; pnum < ubi->peb_count; pnum++) {
+		struct ubi_vid_hdr *tmp = ubi->blockinfo + pnum;
+		u32 t_vol_id = be32_to_cpu(tmp->vol_id);
+		u32 t_lnum = be32_to_cpu(tmp->lnum);
+
+		if (test_bit(pnum, ubi->corrupt))
+			continue;
+
+		if (t_vol_id != vol_id || t_lnum != lnum)
+			continue;
+
+		if (!test_bit(pnum, ubi->scanned)) {
+			ubi_warn("Vol: %u LEB %u PEB %u not yet scanned",
+				 vol_id, lnum, pnum);
+			if (ubi_rescan_fm_vid_hdr(ubi, tmp, pnum, vol_id, lnum))
+				continue;
+		}
+
+		/*
+		 * We found one. If its the first, assign it otherwise
+		 * compare the sqnum
+		 */
+		generic_set_bit(lnum, vi->found);
+
+		if (!vrepl) {
+			vrepl = tmp;
+			continue;
+		}
+
+		if (be64_to_cpu(vrepl->sqnum) < be64_to_cpu(tmp->sqnum))
+			vrepl = tmp;
+	}
+
+	if (vrepl) {
+		/* Update the vi table */
+		pnum = vrepl - ubi->blockinfo;
+		vi->lebs_to_pebs[lnum] = pnum;
+		ubi_dbg("Trying PEB %u for LEB %u", pnum, lnum);
+		vh = vrepl;
+	}
+	goto retry;
+}
+
+/*
+ * Load a volume into RAM
+ */
+static int ipl_load(struct ubi_scan_info *ubi, const u32 vol_id, uint8_t *laddr)
+{
+	struct ubi_vol_info *vi;
+	u32 lnum, last, len;
+
+	if (vol_id >= UBI_SPL_VOL_IDS)
+		return -EINVAL;
+
+	len = 0;
+	vi = ubi->volinfo + vol_id;
+	last = vi->last_block + 1;
+
+	/* Read the blocks to RAM, check CRC */
+	for (lnum = 0 ; lnum < last; lnum++) {
+		int res = ubi_load_block(ubi, laddr, vi, vol_id, lnum, last);
+
+		if (res < 0) {
+			ubi_warn("Failed to load volume %u", vol_id);
+			return res;
+		}
+		/* res is the data length of the read block */
+		laddr += res;
+		len += res;
+	}
+	return len;
+}
+
+int ubispl_load_volumes(struct ubispl_info *info, struct ubispl_load *lvols,
+			int nrvols)
+{
+	struct ubi_scan_info *ubi = info->ubi;
+	int res, i, fastmap = info->fastmap;
+	u32 fsize;
+
+retry:
+	/*
+	 * We do a partial initializiation of @ubi. Cleaning fm_buf is
+	 * not necessary.
+	 */
+	memset(ubi, 0, offsetof(struct ubi_scan_info, fm_buf));
+
+	ubi->read = info->read;
+
+	/* Precalculate the offsets */
+	ubi->vid_offset = info->vid_offset;
+	ubi->leb_start = info->leb_start;
+	ubi->leb_size = info->peb_size - ubi->leb_start;
+	ubi->peb_count = info->peb_count;
+	ubi->peb_offset = info->peb_offset;
+
+	fsize = info->peb_size * info->peb_count;
+	ubi->fsize_mb = fsize >> 20;
+
+	/* Fastmap init */
+	ubi->fm_size = ubi_calc_fm_size(ubi);
+	ubi->fm_enabled = fastmap;
+
+	for (i = 0; i < nrvols; i++) {
+		struct ubispl_load *lv = lvols + i;
+
+		generic_set_bit(lv->vol_id, ubi->toload);
+	}
+
+	ipl_scan(ubi);
+
+	for (i = 0; i < nrvols; i++) {
+		struct ubispl_load *lv = lvols + i;
+
+		ubi_msg("Loading VolId #%d", lv->vol_id);
+		res = ipl_load(ubi, lv->vol_id, lv->load_addr);
+		if (res < 0) {
+			if (fastmap) {
+				fastmap = 0;
+				goto retry;
+			}
+			ubi_warn("Failed");
+			return res;
+		}
+	}
+	return 0;
+}
diff --git a/drivers/mtd/ubispl/ubispl.h b/drivers/mtd/ubispl/ubispl.h
new file mode 100644
index 0000000..9227881
--- /dev/null
+++ b/drivers/mtd/ubispl/ubispl.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) Thomas Gleixner <tglx@linutronix.de>
+ *
+ * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+ */
+
+#ifndef _UBOOT_MTD_UBISPL_H
+#define _UBOOT_MTD_UBISPL_H
+
+#include "../ubi/ubi-media.h"
+#include "ubi-wrapper.h"
+
+/*
+ * The maximum number of volume ids we scan. So you can load volume id
+ * 0 to (CONFIG_SPL_UBI_VOL_ID_MAX - 1)
+ */
+#define UBI_SPL_VOL_IDS		CONFIG_SPL_UBI_VOL_IDS
+/*
+ * The size of the read buffer for the fastmap blocks. In theory up to
+ * UBI_FM_MAX_BLOCKS * CONFIG_SPL_MAX_PEB_SIZE. In practice today
+ * one or two blocks.
+ */
+#define UBI_FM_BUF_SIZE		(UBI_FM_MAX_BLOCKS*CONFIG_SPL_UBI_MAX_PEB_SIZE)
+/*
+ * The size of the bitmaps for the attach/ scan
+ */
+#define UBI_FM_BM_SIZE		((CONFIG_SPL_UBI_MAX_PEBS / BITS_PER_LONG) + 1)
+/*
+ * The maximum number of logical erase blocks per loadable volume
+ */
+#define UBI_MAX_VOL_LEBS	CONFIG_SPL_UBI_MAX_VOL_LEBS
+/*
+ * The bitmap size for the above to denote the found blocks inside the volume
+ */
+#define UBI_VOL_BM_SIZE		((UBI_MAX_VOL_LEBS / BITS_PER_LONG) + 1)
+
+/**
+ * struct ubi_vol_info - UBISPL internal volume represenation
+ * @last_block:		The last block (highest LEB) found for this volume
+ * @found:		Bitmap to mark found LEBS
+ * @lebs_to_pebs:	LEB to PEB translation table
+ */
+struct ubi_vol_info {
+	u32				last_block;
+	unsigned long			found[UBI_VOL_BM_SIZE];
+	u32				lebs_to_pebs[UBI_MAX_VOL_LEBS];
+};
+
+/**
+ * struct ubi_scan_info - UBISPL internal data for FM attach and full scan
+ *
+ * @read:		Read function to access the flash provided by the caller
+ * @peb_count:		Number of physical erase blocks in the UBI FLASH area
+ *			aka MTD partition.
+ * @peb_offset:		Offset of PEB0 in the UBI FLASH area (aka MTD partition)
+ *			to the real start of the FLASH in erase blocks.
+ * @fsize_mb:		Size of the scanned FLASH area in MB (stats only)
+ * @vid_offset:		Offset from the start of a PEB to the VID header
+ * @leb_start:		Offset from the start of a PEB to the data area
+ * @leb_size:		Size of the data area
+ *
+ * @fastmap_pebs:	Counter of PEBs "attached" by fastmap
+ * @fastmap_anchor:	The anchor PEB of the fastmap
+ * @fm_sb:		The fastmap super block data
+ * @fm_vh:		The fastmap VID header
+ * @fm:			Pointer to the fastmap layout
+ * @fm_layout:		The fastmap layout itself
+ * @fm_pool:		The pool of PEBs to scan at fastmap attach time
+ * @fm_wl_pool:		The pool of PEBs scheduled for wearleveling
+ *
+ * @fm_enabled:		Indicator whether fastmap attachment is enabled.
+ * @fm_used:		Bitmap to indicate the PEBS covered by fastmap
+ * @scanned:		Bitmap to indicate the PEBS of which the VID header
+ *			hase been physically scanned.
+ * @corrupt:		Bitmap to indicate corrupt blocks
+ * @toload:		Bitmap to indicate the volumes which should be loaded
+ *
+ * @blockinfo:		The vid headers of the scanned blocks
+ * @volinfo:		The volume information of the interesting (toload)
+ *			volumes
+ *
+ * @fm_buf:		The large fastmap attach buffer
+ */
+struct ubi_scan_info {
+	ubispl_read_flash		read;
+	unsigned int			fsize_mb;
+	unsigned int			peb_count;
+	unsigned int			peb_offset;
+
+	unsigned long			vid_offset;
+	unsigned long			leb_start;
+	unsigned long			leb_size;
+
+	/* Fastmap: The upstream required fields */
+	int				fastmap_pebs;
+	int				fastmap_anchor;
+	size_t				fm_size;
+	struct ubi_fm_sb		fm_sb;
+	struct ubi_vid_hdr		fm_vh;
+	struct ubi_fastmap_layout	*fm;
+	struct ubi_fastmap_layout	fm_layout;
+	struct ubi_fm_pool		fm_pool;
+	struct ubi_fm_pool		fm_wl_pool;
+
+	/* Fastmap: UBISPL specific data */
+	int				fm_enabled;
+	unsigned long			fm_used[UBI_FM_BM_SIZE];
+	unsigned long			scanned[UBI_FM_BM_SIZE];
+	unsigned long			corrupt[UBI_FM_BM_SIZE];
+	unsigned long			toload[UBI_FM_BM_SIZE];
+
+	/* Data for storing the VID and volume information */
+	struct ubi_vol_info		volinfo[UBI_SPL_VOL_IDS];
+	struct ubi_vid_hdr		blockinfo[CONFIG_SPL_UBI_MAX_PEBS];
+
+	/* The large buffer for the fastmap */
+	uint8_t				fm_buf[UBI_FM_BUF_SIZE];
+};
+
+#ifdef CFG_DEBUG
+#define ubi_dbg(fmt, ...) printf("UBI: debug:" fmt "\n", ##__VA_ARGS__)
+#else
+#define ubi_dbg(fmt, ...)
+#endif
+
+#ifdef CONFIG_UBI_SILENCE_MSG
+#define ubi_msg(fmt, ...)
+#else
+#define ubi_msg(fmt, ...) printf("UBI: " fmt "\n", ##__VA_ARGS__)
+#endif
+/* UBI warning messages */
+#define ubi_warn(fmt, ...) printf("UBI warning: " fmt "\n", ##__VA_ARGS__)
+/* UBI error messages */
+#define ubi_err(fmt, ...) printf("UBI error: " fmt "\n", ##__VA_ARGS__)
+
+#endif
diff --git a/include/ubispl.h b/include/ubispl.h
new file mode 100644
index 0000000..944653e
--- /dev/null
+++ b/include/ubispl.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) Thomas Gleixner <tglx@linutronix.de>
+ *
+ * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+ */
+#ifndef __UBOOT_UBISPL_H
+#define __UBOOT_UBISPL_H
+
+/*
+ * The following CONFIG options are relevant for UBISPL
+ *
+ * #define CONFIG_SPL_UBI_MAX_VOL_LEBS		256
+ *
+ * Defines the maximum number of logical erase blocks per loadable
+ * (static) volume to size the ubispl internal arrays.
+ *
+ * #define CONFIG_SPL_UBI_MAX_PEB_SIZE		(256*1024)
+ *
+ * Defines the maximum physical erase block size to size the fastmap
+ * buffer for ubispl.
+ *
+ * #define CONFIG_SPL_UBI_MAX_PEBS		4096
+ *
+ * Define the maximum number of physical erase blocks to size the
+ * ubispl internal arrays.
+ *
+ * #define CONFIG_SPL_UBI_VOL_IDS		8
+ *
+ * Defines the maximum number of volumes in which UBISPL is
+ * interested. Limits the amount of memory for the scan data and
+ * speeds up the scan process as we simply ignore stuff which we dont
+ * want to load from the SPL anyway. So the volumes which can be
+ * loaded in the above example are ids 0 - 7
+ */
+
+/*
+ * The struct definition is in drivers/mtd/ubispl/ubispl.h. It does
+ * not fit into the BSS due to the large buffer requirement of the
+ * upstream fastmap code. So the caller of ubispl_load_volumes needs
+ * to hand in a pointer to a free memory area where ubispl will place
+ * its data. The area is not required to be initialized.
+ */
+struct ubi_scan_info;
+
+typedef int (*ubispl_read_flash)(int pnum, int offset, int len, void *dst);
+
+/**
+ * struct ubispl_info - description structure for fast ubi scan
+ * @ubi:		Pointer to memory space for ubi scan info structure
+ * @peb_size:		Physical erase block size
+ * @vid_offset:		Offset of the VID header
+ * @leb_start:		Start of the logical erase block, i.e. offset of data
+ * @peb_count:		Number of physical erase blocks in the UBI FLASH area
+ *			aka MTD partition.
+ * @peb_offset:		Offset of PEB0 in the UBI FLASH area (aka MTD partition)
+ *			to the real start of the FLASH in erase blocks.
+ * @fastmap:		Enable fastmap attachment
+ * @read:		Read function to access the flash
+ */
+struct ubispl_info {
+	struct ubi_scan_info	*ubi;
+	u32			peb_size;
+	u32			vid_offset;
+	u32			leb_start;
+	u32			peb_count;
+	u32			peb_offset;
+	int			fastmap;
+	ubispl_read_flash	read;
+};
+
+/**
+ * struct ubispl_load - structure to describe a volume to load
+ * @vol_id:	Volume id
+ * @load_addr:	Load address of the volume
+ */
+struct ubispl_load {
+	int		vol_id;
+	void		*load_addr;
+};
+
+/**
+ * ubispl_load_volumes - Scan flash and load volumes
+ * @info:	Pointer to the ubi scan info structure
+ * @lovls:	Pointer to array of volumes to load
+ * @nrvols:	Array size of @lovls
+ */
+int ubispl_load_volumes(struct ubispl_info *info,
+			struct ubispl_load *lvols, int nrvols);
+
+#endif
-- 
cgit v0.10.2


From bf55cd4f3e3bc0ebf92c81bde1921f983e999451 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:13 +0200
Subject: spl: support loading from UBI volumes

Add support for loading from UBI volumes on the top of NAND
and OneNAND.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/common/spl/Makefile b/common/spl/Makefile
index 2e0f695..b15f0f6 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -13,8 +13,11 @@ obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
 obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
 obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+ifndef CONFIG_SPL_UBI
 obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+endif
+obj-$(CONFIG_SPL_UBI) += spl_ubi.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 14320fe..e6a1d79 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -330,6 +330,11 @@ static int spl_load_image(u32 boot_device)
 	case BOOT_DEVICE_MMC2_2:
 		return spl_mmc_load_image(boot_device);
 #endif
+#ifdef CONFIG_SPL_UBI
+	case BOOT_DEVICE_NAND:
+	case BOOT_DEVICE_ONENAND:
+		return spl_ubi_load_image(boot_device);
+#else
 #ifdef CONFIG_SPL_NAND_SUPPORT
 	case BOOT_DEVICE_NAND:
 		return spl_nand_load_image();
@@ -338,6 +343,7 @@ static int spl_load_image(u32 boot_device)
 	case BOOT_DEVICE_ONENAND:
 		return spl_onenand_load_image();
 #endif
+#endif
 #ifdef CONFIG_SPL_NOR_SUPPORT
 	case BOOT_DEVICE_NOR:
 		return spl_nor_load_image();
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
new file mode 100644
index 0000000..f97e1ef
--- /dev/null
+++ b/common/spl/spl_ubi.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl <ladis@linux-mips.org>
+ *
+ * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <config.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <ubispl.h>
+#include <spl.h>
+
+int spl_ubi_load_image(u32 boot_device)
+{
+	struct image_header *header;
+	struct ubispl_info info;
+	struct ubispl_load volumes[2];
+	int ret = 1;
+
+	switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	case BOOT_DEVICE_NAND:
+		nand_init();
+		info.read = nand_spl_read_block;
+		info.peb_size = CONFIG_SYS_NAND_BLOCK_SIZE;
+		break;
+#endif
+#ifdef CONFIG_SPL_ONENAND_SUPPORT
+	case BOOT_DEVICE_ONENAND:
+		info.read = onenand_spl_read_block;
+		info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE;
+		break;
+#endif
+	default:
+		goto out;
+	}
+	info.ubi = (struct ubi_scan_info *)CONFIG_SPL_UBI_INFO_ADDR;
+	info.fastmap = 1;
+
+	info.peb_offset = CONFIG_SPL_UBI_PEB_OFFSET;
+	info.vid_offset = CONFIG_SPL_UBI_VID_OFFSET;
+	info.leb_start = CONFIG_SPL_UBI_LEB_START;
+	info.peb_count = CONFIG_SPL_UBI_MAX_PEBS - info.peb_offset;
+
+#ifdef CONFIG_SPL_OS_BOOT
+	if (!spl_start_uboot()) {
+		volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_KERNEL_ID;
+		volumes[0].load_addr = (void *)CONFIG_SYS_LOAD_ADDR;
+		volumes[1].vol_id = CONFIG_SPL_UBI_LOAD_ARGS_ID;
+		volumes[1].load_addr = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
+
+		ret = ubispl_load_volumes(&info, volumes, 2);
+		if (!ret) {
+			header = (struct image_header *)volumes[0].load_addr;
+			spl_parse_image_header(header);
+			puts("Linux loaded.\n");
+			goto out;
+		}
+		puts("Loading Linux failed, falling back to U-Boot.\n");
+	}
+#endif
+	header = (struct image_header *)
+		(CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+	volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_MONITOR_ID;
+	volumes[0].load_addr = (void *)header;
+
+	ret = ubispl_load_volumes(&info, volumes, 1);
+	if (!ret)
+		spl_parse_image_header(header);
+out:
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	if (boot_device == BOOT_DEVICE_NAND)
+		nand_deselect();
+#endif
+	return ret;
+}
diff --git a/include/spl.h b/include/spl.h
index 2360466..8afa085 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -71,6 +71,7 @@ void spl_set_header_raw_uboot(void);
 int spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
 void spl_board_prepare_for_boot(void);
+int spl_board_ubi_load_image(u32 boot_device);
 void __noreturn jump_to_image_linux(void *arg);
 int spl_start_uboot(void);
 void spl_display_print(void);
@@ -84,6 +85,9 @@ int spl_onenand_load_image(void);
 /* NOR SPL functions */
 int spl_nor_load_image(void);
 
+/* UBI SPL functions */
+int spl_ubi_load_image(u32 boot_device);
+
 /* MMC SPL functions */
 int spl_mmc_load_image(u32 boot_device);
 
-- 
cgit v0.10.2


From 431889d6ad9a39846636716478d504aa7ff976fc Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:14 +0200
Subject: spl: zImage support in Falcon mode

Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f406419..9f71376 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -27,11 +27,13 @@ endif
 obj-$(CONFIG_CPU_V7M) += cmd_boot.o
 obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += zimage.o
 obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
 obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
 else
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
 endif
 obj-$(CONFIG_SEMIHOSTING) += semihosting.o
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 0838d89..c20ef22 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -358,38 +358,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
 	return 0;
 }
 
-#ifdef CONFIG_CMD_BOOTZ
-
-struct zimage_header {
-	uint32_t	code[9];
-	uint32_t	zi_magic;
-	uint32_t	zi_start;
-	uint32_t	zi_end;
-};
-
-#define	LINUX_ARM_ZIMAGE_MAGIC	0x016f2818
-
-int bootz_setup(ulong image, ulong *start, ulong *end)
-{
-	struct zimage_header *zi;
-
-	zi = (struct zimage_header *)map_sysmem(image, 0);
-	if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
-		puts("Bad Linux ARM zImage magic!\n");
-		return 1;
-	}
-
-	*start = zi->zi_start;
-	*end = zi->zi_end;
-
-	printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start,
-	      *end);
-
-	return 0;
-}
-
-#endif	/* CONFIG_CMD_BOOTZ */
-
 #if defined(CONFIG_BOOTM_VXWORKS)
 void boot_prep_vxworks(bootm_headers_t *images)
 {
diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c
new file mode 100644
index 0000000..1e811a8
--- /dev/null
+++ b/arch/arm/lib/zimage.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl <ladis@linux-mips.org>
+ *
+ * bootz code:
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+
+#define	LINUX_ARM_ZIMAGE_MAGIC	0x016f2818
+
+struct arm_z_header {
+	uint32_t	code[9];
+	uint32_t	zi_magic;
+	uint32_t	zi_start;
+	uint32_t	zi_end;
+} __attribute__ ((__packed__));
+
+int bootz_setup(ulong image, ulong *start, ulong *end)
+{
+	struct arm_z_header *zi = (struct arm_z_header *)image;
+
+	if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
+#ifndef CONFIG_SPL_FRAMEWORK
+		puts("Bad Linux ARM zImage magic!\n");
+#endif
+		return 1;
+	}
+
+	*start = zi->zi_start;
+	*end = zi->zi_end;
+#ifndef CONFIG_SPL_FRAMEWORK
+	printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n",
+	       image, *start, *end);
+#endif
+
+	return 0;
+}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index e6a1d79..b7ec333 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -56,6 +56,15 @@ __weak int spl_start_uboot(void)
 	puts("SPL: Direct Linux boot not active!\n");
 	return 1;
 }
+
+/*
+ * Weak default function for arch specific zImage check. Return zero
+ * and fill start and end address if image is recognized.
+ */
+int __weak bootz_setup(ulong image, ulong *start, ulong *end)
+{
+	 return 1;
+}
 #endif
 
 /*
@@ -124,6 +133,20 @@ int spl_parse_image_header(const struct image_header *header)
 		/* Signature not found, proceed to other boot methods. */
 		return -EINVAL;
 #else
+#ifdef CONFIG_SPL_OS_BOOT
+		ulong start, end;
+
+		if (!bootz_setup((ulong)header, &start, &end)) {
+			spl_image.name = "Linux";
+			spl_image.os = IH_OS_LINUX;
+			spl_image.load_addr = CONFIG_SYS_LOAD_ADDR;
+			spl_image.entry_point = CONFIG_SYS_LOAD_ADDR;
+			spl_image.size = end - start;
+			debug("spl: payload zImage, load addr: 0x%x size: %d\n",
+			      spl_image.load_addr, spl_image.size);
+			return 0;
+		}
+#endif
 		/* Signature not found - assume u-boot.bin */
 		debug("mkimage signature not found - ih_magic = %x\n",
 			header->ih_magic);
-- 
cgit v0.10.2


From b1509e3a4aa55b003e814386dd83972858544e55 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:15 +0200
Subject: armv7: add reset timeout to identify_nand_chip

identify_nand_chip hangs forever in loop when NAND is not present.
As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout
to let function fail gracefully allowing caller to know NAND is
not present. On NAND equipped board, reset succeeds on first read,
so 1000 loops seems to be safe timeout.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
index db6de09..26d3aa4 100644
--- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
+++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
@@ -20,29 +20,16 @@
 
 static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
 
-/* nand_command: Send a flash command to the flash chip */
-static void nand_command(u8 command)
-{
-	writeb(command, &gpmc_config->cs[0].nand_cmd);
-
-	if (command == NAND_CMD_RESET) {
-		unsigned char ret_val;
-		writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
-		do {
-			/* Wait until ready */
-			ret_val = readl(&gpmc_config->cs[0].nand_dat);
-		} while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
-	}
-}
-
 /*
  * Many boards will want to know the results of the NAND_CMD_READID command
  * in order to decide what to do about DDR initialization.  This function
  * allows us to do that very early and to pass those results back to the
  * board so it can make whatever decisions need to be made.
  */
-void identify_nand_chip(int *mfr, int *id)
+int identify_nand_chip(int *mfr, int *id)
 {
+	int loops = 1000;
+
 	/* Make sure that we have setup GPMC for NAND correctly. */
 	writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
 	writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
@@ -62,8 +49,15 @@ void identify_nand_chip(int *mfr, int *id)
 	sdelay(2000);
 
 	/* Issue a RESET and then READID */
-	nand_command(NAND_CMD_RESET);
-	nand_command(NAND_CMD_READID);
+	writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd);
+	writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
+	while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY)
+	                                           != NAND_STATUS_READY) {
+		sdelay(100);
+		if (--loops == 0)
+			return 1;
+	}
+	writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd);
 
 	/* Set the address to read to 0x0 */
 	writeb(0x0, &gpmc_config->cs[0].nand_adr);
@@ -71,4 +65,6 @@ void identify_nand_chip(int *mfr, int *id)
 	/* Read off the manufacturer and device id. */
 	*mfr = readb(&gpmc_config->cs[0].nand_dat);
 	*id = readb(&gpmc_config->cs[0].nand_dat);
+
+	return 0;
 }
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 24563c0..1be2b15 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -40,7 +40,7 @@ void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 
 void get_board_mem_timings(struct board_sdrc_timings *timings);
-void identify_nand_chip(int *mfr, int *id);
+int identify_nand_chip(int *mfr, int *id);
 void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-- 
cgit v0.10.2


From 0568dd0663429b00fb77c452e27434c2f4faa14b Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:16 +0200
Subject: armv7: make gpmc_cfg const

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
[trini: Adapt am33xx, duovero, omap_zoom1]
Signed-off-by: Tom Rini <trini@konsulko.com>

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index fc4290c..136a032 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -21,7 +21,7 @@
 #include <command.h>
 #include <linux/mtd/omap_gpmc.h>
 
-struct gpmc *gpmc_cfg;
+const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
 
 #if defined(CONFIG_OMAP34XX)
 /********************************************************
@@ -50,8 +50,8 @@ u32 mem_ok(u32 cs)
 }
 #endif
 
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-			u32 size)
+void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
+				u32 base, u32 size)
 {
 	writel(0, &cs->config7);
 	sdelay(1000);
@@ -75,8 +75,6 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  *****************************************************/
 void gpmc_init(void)
 {
-	/* putting a blanket check on GPMC based on ZeBu for now */
-	gpmc_cfg = (struct gpmc *)GPMC_BASE;
 #if defined(CONFIG_NOR)
 /* configure GPMC for NOR */
 	const u32 gpmc_regs[GPMC_MAX_REG] = {	STNOR_GPMC_CONFIG1,
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 8f573d2..ed1a46c 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -25,9 +25,8 @@ void ddr_pll_config(unsigned int ddrpll_M);
 
 void sdelay(unsigned long);
 
-struct gpmc_cs;
 void gpmc_init(void);
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base,
 			u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
 
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 1be2b15..4c5aa99 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -43,8 +43,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings);
 int identify_nand_chip(int *mfr, int *id);
 void emif4_init(void);
 void gpmc_init(void);
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-			u32 size);
+void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
+				u32 base, u32 size);
 
 void watchdog_init(void);
 void set_muxconf_regs(void);
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
index 9671c5a..3786842 100644
--- a/board/gumstix/duovero/duovero.c
+++ b/board/gumstix/duovero/duovero.c
@@ -128,7 +128,7 @@ void board_mmc_power_init(void)
 #define GPMC_BASEADDR_MASK	0x3F
 #define GPMC_CS_ENABLE		0x1
 
-static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs,
+static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
 		u32 base, u32 size)
 {
 	writel(0, &cs->config7);
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 982619c..2821ee2 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -19,6 +19,7 @@
 #include <ns16550.h>
 #include <netdev.h>
 #include <twl4030.h>
+#include <linux/mtd/omap_gpmc.h>
 #include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
@@ -29,10 +30,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* gpmc_cfg is initialized by gpmc_init and we use it here */
-extern struct gpmc *gpmc_cfg;
-
-/* GPMC definitions for Ethenet Controller LAN9211 */
+/*
+ * gpmc_cfg is initialized by gpmc_init and we use it here.
+ * GPMC definitions for Ethenet Controller LAN9211
+ */
 static const u32 gpmc_lab_enet[] = {
 	ZOOM1_ENET_GPMC_CONF1,
 	ZOOM1_ENET_GPMC_CONF2,
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 67f293d..6e201d6 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -264,7 +264,8 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct omap_nand_info *info = nand_get_controller_data(chip);
-	uint32_t *ptr, val = 0;
+	const uint32_t *ptr;
+	uint32_t val = 0;
 	int8_t i = 0, j;
 
 	switch (info->ecc_scheme) {
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
index 3a75674..f49ea3d 100644
--- a/include/linux/mtd/omap_gpmc.h
+++ b/include/linux/mtd/omap_gpmc.h
@@ -92,6 +92,6 @@ struct gpmc {
 };
 
 /* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
+extern const struct gpmc *gpmc_cfg;
 
 #endif /* __ASM_OMAP_GPMC_H */
-- 
cgit v0.10.2


From 22d6ac490e7509cea6d2293ff9741a990364120b Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:17 +0200
Subject: armv7: armv7: introduce set_gpmc_cs0

Allow boards to runtime detect flash type.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 136a032..d72e82e 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -20,9 +20,20 @@
 #include <asm/arch/sys_proto.h>
 #include <command.h>
 #include <linux/mtd/omap_gpmc.h>
+#include <jffs2/load_kernel.h>
 
 const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
 
+#if defined(CONFIG_NOR)
+char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
+#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
+char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+#elif defined(CONFIG_CMD_ONENAND)
+char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+#else
+char gpmc_cs0_flash = -1;
+#endif
+
 #if defined(CONFIG_OMAP34XX)
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
@@ -68,6 +79,81 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
 	sdelay(2000);
 }
 
+void set_gpmc_cs0(int flash_type)
+{
+	const u32 *gpmc_regs;
+	u32 base, size;
+#if defined(CONFIG_NOR)
+	const u32 gpmc_regs_nor[GPMC_MAX_REG] = {
+		STNOR_GPMC_CONFIG1,
+		STNOR_GPMC_CONFIG2,
+		STNOR_GPMC_CONFIG3,
+		STNOR_GPMC_CONFIG4,
+		STNOR_GPMC_CONFIG5,
+		STNOR_GPMC_CONFIG6,
+		STNOR_GPMC_CONFIG7
+	};
+#endif
+#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
+	const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
+		M_NAND_GPMC_CONFIG1,
+		M_NAND_GPMC_CONFIG2,
+		M_NAND_GPMC_CONFIG3,
+		M_NAND_GPMC_CONFIG4,
+		M_NAND_GPMC_CONFIG5,
+		M_NAND_GPMC_CONFIG6,
+		0
+	};
+#endif
+#if defined(CONFIG_CMD_ONENAND)
+	const u32 gpmc_regs_onenand[GPMC_MAX_REG] = {
+		ONENAND_GPMC_CONFIG1,
+		ONENAND_GPMC_CONFIG2,
+		ONENAND_GPMC_CONFIG3,
+		ONENAND_GPMC_CONFIG4,
+		ONENAND_GPMC_CONFIG5,
+		ONENAND_GPMC_CONFIG6,
+		0
+	};
+#endif
+
+	switch (flash_type) {
+#if defined(CONFIG_NOR)
+	case MTD_DEV_TYPE_NOR:
+		gpmc_regs = gpmc_regs_nor;
+		base = CONFIG_SYS_FLASH_BASE;
+		size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+		      ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+		      ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
+		      ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
+		                                              GPMC_SIZE_16M)));
+		break;
+#endif
+#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
+	case MTD_DEV_TYPE_NAND:
+		gpmc_regs = gpmc_regs_nand;
+		base = CONFIG_SYS_NAND_BASE;
+		size = GPMC_SIZE_16M;
+		break;
+#endif
+#if defined(CONFIG_CMD_ONENAND)
+	case MTD_DEV_TYPE_ONENAND:
+		gpmc_regs = gpmc_regs_onenand;
+		base = CONFIG_SYS_ONENAND_BASE;
+		size = GPMC_SIZE_128M;
+		break;
+#endif
+	default:
+		/* disable the GPMC0 config set by ROM code */
+		writel(0, &gpmc_cfg->cs[0].config7);
+		sdelay(1000);
+		return;
+	}
+
+	/* enable chip-select specific configurations */
+	enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
+}
+
 /*****************************************************
  * gpmc_init(): init gpmc bus
  * Init GPMC for x16, MuxMode (SDRAM in x32).
@@ -75,68 +161,14 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
  *****************************************************/
 void gpmc_init(void)
 {
-#if defined(CONFIG_NOR)
-/* configure GPMC for NOR */
-	const u32 gpmc_regs[GPMC_MAX_REG] = {	STNOR_GPMC_CONFIG1,
-						STNOR_GPMC_CONFIG2,
-						STNOR_GPMC_CONFIG3,
-						STNOR_GPMC_CONFIG4,
-						STNOR_GPMC_CONFIG5,
-						STNOR_GPMC_CONFIG6,
-						STNOR_GPMC_CONFIG7
-						};
-	u32 base = CONFIG_SYS_FLASH_BASE;
-	u32 size =	(CONFIG_SYS_FLASH_SIZE  > 0x08000000) ? GPMC_SIZE_256M :
-	/* > 64MB */	((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
-	/* > 32MB */	((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
-	/* > 16MB */	((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
-	/* min 16MB */	GPMC_SIZE_16M)));
-#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
-/* configure GPMC for NAND */
-	const u32  gpmc_regs[GPMC_MAX_REG] = {	M_NAND_GPMC_CONFIG1,
-						M_NAND_GPMC_CONFIG2,
-						M_NAND_GPMC_CONFIG3,
-						M_NAND_GPMC_CONFIG4,
-						M_NAND_GPMC_CONFIG5,
-						M_NAND_GPMC_CONFIG6,
-						0
-						};
-	u32 base = CONFIG_SYS_NAND_BASE;
-	u32 size = GPMC_SIZE_16M;
-
-#elif defined(CONFIG_CMD_ONENAND)
-	const u32 gpmc_regs[GPMC_MAX_REG] = {	ONENAND_GPMC_CONFIG1,
-						ONENAND_GPMC_CONFIG2,
-						ONENAND_GPMC_CONFIG3,
-						ONENAND_GPMC_CONFIG4,
-						ONENAND_GPMC_CONFIG5,
-						ONENAND_GPMC_CONFIG6,
-						0
-						};
-	u32 size = GPMC_SIZE_128M;
-	u32 base = CONFIG_SYS_ONENAND_BASE;
-#else
-	const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
-	u32 size = 0;
-	u32 base = 0;
-#endif
 	/* global settings */
 	writel(0x00000008, &gpmc_cfg->sysconfig);
 	writel(0x00000000, &gpmc_cfg->irqstatus);
 	writel(0x00000000, &gpmc_cfg->irqenable);
 	/* disable timeout, set a safe reset value */
 	writel(0x00001ff0, &gpmc_cfg->timeout_control);
-#ifdef CONFIG_NOR
-	writel(0x00000200, &gpmc_cfg->config);
-#else
-	writel(0x00000012, &gpmc_cfg->config);
-#endif
-	/*
-	 * Disable the GPMC0 config set by ROM code
-	 */
-	writel(0, &gpmc_cfg->cs[0].config7);
-	sdelay(1000);
-	/* enable chip-select specific configurations */
-	if (base != 0)
-		enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
+	writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ?
+		0x00000200 : 0x00000012, &gpmc_cfg->config);
+
+	set_gpmc_cs0(gpmc_cs0_flash);
 }
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 4c5aa99..5979340 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -45,6 +45,7 @@ void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
 				u32 base, u32 size);
+void set_gpmc_cs0(int flash_type);
 
 void watchdog_init(void);
 void set_muxconf_regs(void);
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
index f49ea3d..be3ce9d 100644
--- a/include/linux/mtd/omap_gpmc.h
+++ b/include/linux/mtd/omap_gpmc.h
@@ -93,5 +93,6 @@ struct gpmc {
 
 /* Used for board specific gpmc initialization */
 extern const struct gpmc *gpmc_cfg;
+extern char gpmc_cs0_flash;
 
 #endif /* __ASM_OMAP_GPMC_H */
-- 
cgit v0.10.2


From 9a9d3946399e91e0ff6de7e4678a3b242b66af74 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:18 +0200
Subject: armv7: simplify identify_nand_chip

Use newly introduced function

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
index 26d3aa4..0e2f0a2 100644
--- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
+++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
@@ -13,13 +13,13 @@
  */
 
 #include <common.h>
+#include <jffs2/load_kernel.h>
 #include <linux/mtd/nand.h>
+#include <linux/mtd/omap_gpmc.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 
-static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
-
 /*
  * Many boards will want to know the results of the NAND_CMD_READID command
  * in order to decide what to do about DDR initialization.  This function
@@ -31,40 +31,27 @@ int identify_nand_chip(int *mfr, int *id)
 	int loops = 1000;
 
 	/* Make sure that we have setup GPMC for NAND correctly. */
-	writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
-	writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
-	writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
-	writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
-	writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
-	writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
-
-	/*
-	 * Enable the config.  The CS size goes in bits 11:8.  We set
-	 * bit 6 to enable the CS and the base address goes into bits 5:0.
-	 */
-	writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
-				((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
-			&gpmc_config->cs[0].config7);
+	set_gpmc_cs0(MTD_DEV_TYPE_NAND);
 
 	sdelay(2000);
 
 	/* Issue a RESET and then READID */
-	writeb(NAND_CMD_RESET, &gpmc_config->cs[0].nand_cmd);
-	writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
-	while ((readl(&gpmc_config->cs[0].nand_dat) & NAND_STATUS_READY)
-	                                           != NAND_STATUS_READY) {
+	writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+	writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+	while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+	                                        != NAND_STATUS_READY) {
 		sdelay(100);
 		if (--loops == 0)
 			return 1;
 	}
-	writeb(NAND_CMD_READID, &gpmc_config->cs[0].nand_cmd);
+	writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
 
 	/* Set the address to read to 0x0 */
-	writeb(0x0, &gpmc_config->cs[0].nand_adr);
+	writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
 
 	/* Read off the manufacturer and device id. */
-	*mfr = readb(&gpmc_config->cs[0].nand_dat);
-	*id = readb(&gpmc_config->cs[0].nand_dat);
+	*mfr = readb(&gpmc_cfg->cs[0].nand_dat);
+	*id = readb(&gpmc_cfg->cs[0].nand_dat);
 
 	return 0;
 }
-- 
cgit v0.10.2


From d9098ee55f6cf6f51e2fbed0336957e2b7156225 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:19 +0200
Subject: mtd: OneNAND: add timeout to wait ready loops

Add timeout to onenand_wait ready loop as it hangs here indefinitely
when chip not present. Once there, do the same for onenand_bbt_wait
as well (note: recent Linux driver code does the same)

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 03deabc..d194d97 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -20,6 +20,7 @@
  */
 
 #include <common.h>
+#include <watchdog.h>
 #include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include "linux/mtd/flashchip.h"
@@ -467,15 +468,18 @@ static int onenand_read_ecc(struct onenand_chip *this)
 static int onenand_wait(struct mtd_info *mtd, int state)
 {
 	struct onenand_chip *this = mtd->priv;
-	unsigned int flags = ONENAND_INT_MASTER;
 	unsigned int interrupt = 0;
 	unsigned int ctrl;
 
-	while (1) {
+	/* Wait at most 20ms ... */
+	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	u32 time_start = get_timer(0);
+	do {
+		WATCHDOG_RESET();
+		if (get_timer(time_start) > timeo)
+			return -EIO;
 		interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
-		if (interrupt & flags)
-			break;
-	}
+	} while ((interrupt & ONENAND_INT_MASTER) == 0);
 
 	ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
 
@@ -1154,15 +1158,18 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from,
 static int onenand_bbt_wait(struct mtd_info *mtd, int state)
 {
 	struct onenand_chip *this = mtd->priv;
-	unsigned int flags = ONENAND_INT_MASTER;
 	unsigned int interrupt;
 	unsigned int ctrl;
 
-	while (1) {
+	/* Wait at most 20ms ... */
+	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	u32 time_start = get_timer(0);
+	do {
+		WATCHDOG_RESET();
+		if (get_timer(time_start) > timeo)
+			return ONENAND_BBT_READ_FATAL_ERROR;
 		interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
-		if (interrupt & flags)
-			break;
-	}
+	} while ((interrupt & ONENAND_INT_MASTER) == 0);
 
 	/* To get correct interrupt status in timeout case */
 	interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
@@ -2536,7 +2543,8 @@ static int onenand_chip_probe(struct mtd_info *mtd)
 	this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
 
 	/* Wait reset */
-	this->wait(mtd, FL_RESETING);
+	if (this->wait(mtd, FL_RESETING))
+		return -ENXIO;
 
 	/* Restore system configuration 1 */
 	this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
-- 
cgit v0.10.2


From 77b93e5e9b28328f76556e0c0b94889df47077d7 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:20 +0200
Subject: mtd: OneNAND: allow board init function fail

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c
index 62eb648..ef892ca 100644
--- a/board/micronas/vct/ebi_onenand.c
+++ b/board/micronas/vct/ebi_onenand.c
@@ -169,7 +169,7 @@ static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
 	return 0;
 }
 
-void onenand_board_init(struct mtd_info *mtd)
+int onenand_board_init(struct mtd_info *mtd)
 {
 	struct onenand_chip *chip = mtd->priv;
 
@@ -181,4 +181,6 @@ void onenand_board_init(struct mtd_info *mtd)
 
 	chip->read_bufferram = ebi_read_bufferram;
 	chip->write_bufferram = ebi_write_bufferram;
+
+	return 0;
 }
diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c
index b74d8e8..cbe1d12f 100644
--- a/board/samsung/goni/onenand.c
+++ b/board/samsung/goni/onenand.c
@@ -11,11 +11,13 @@
 #include <linux/mtd/samsung_onenand.h>
 #include <onenand_uboot.h>
 
-void onenand_board_init(struct mtd_info *mtd)
+int onenand_board_init(struct mtd_info *mtd)
 {
 	struct onenand_chip *this = mtd->priv;
 
 	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
 	this->chip_probe = s5pc110_chip_probe;
+
+	return 0;
 }
diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c
index 577c1a5..994d91d 100644
--- a/board/samsung/smdkc100/onenand.c
+++ b/board/samsung/smdkc100/onenand.c
@@ -16,7 +16,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 
-void onenand_board_init(struct mtd_info *mtd)
+int onenand_board_init(struct mtd_info *mtd)
 {
 	struct onenand_chip *this = mtd->priv;
 	struct s5pc100_clock *clk =
@@ -65,4 +65,6 @@ void onenand_board_init(struct mtd_info *mtd)
 	writel(value, &onenand->int_err_mask);
 
 	s3c_onenand_init(mtd);
+
+	return 0;
 }
diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c
index 28bc811..147a95e 100644
--- a/board/samsung/universal_c210/onenand.c
+++ b/board/samsung/universal_c210/onenand.c
@@ -10,11 +10,13 @@
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/samsung_onenand.h>
 
-void onenand_board_init(struct mtd_info *mtd)
+int onenand_board_init(struct mtd_info *mtd)
 {
 	struct onenand_chip *this = mtd->priv;
 
 	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
 	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
 	this->chip_probe = s5pc210_chip_probe;
+
+	return 0;
 }
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index ae60c3b..c15ec9d 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -24,33 +24,33 @@ static __attribute__((unused)) char dev_name[] = "onenand0";
 
 void onenand_init(void)
 {
+	int err = 0;
 	memset(&onenand_mtd, 0, sizeof(struct mtd_info));
 	memset(&onenand_chip, 0, sizeof(struct onenand_chip));
 
 	onenand_mtd.priv = &onenand_chip;
 
 #ifdef CONFIG_USE_ONENAND_BOARD_INIT
-	/*
-	 * It's used for some board init required
-	 */
-	onenand_board_init(&onenand_mtd);
+	/* It's used for some board init required */
+	err = onenand_board_init(&onenand_mtd);
 #else
 	onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE;
 #endif
 
-	onenand_scan(&onenand_mtd, 1);
+	if (!err && !(onenand_scan(&onenand_mtd, 1))) {
 
-	if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND)
-		puts("Flex-");
-	puts("OneNAND: ");
-	print_size(onenand_chip.chipsize, "\n");
+		if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND)
+			puts("Flex-");
+		puts("OneNAND: ");
 
 #ifdef CONFIG_MTD_DEVICE
-	/*
-	 * Add MTD device so that we can reference it later
-	 * via the mtdcore infrastructure (e.g. ubi).
-	 */
-	onenand_mtd.name = dev_name;
-	add_mtd_device(&onenand_mtd);
+		/*
+		 * Add MTD device so that we can reference it later
+		 * via the mtdcore infrastructure (e.g. ubi).
+		 */
+		onenand_mtd.name = dev_name;
+		add_mtd_device(&onenand_mtd);
 #endif
+	}
+	print_size(onenand_chip.chipsize, "\n");
 }
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
index d69e0d2..995f0aa 100644
--- a/include/onenand_uboot.h
+++ b/include/onenand_uboot.h
@@ -26,7 +26,7 @@ extern struct mtd_info onenand_mtd;
 extern struct onenand_chip onenand_chip;
 
 /* board */
-extern void onenand_board_init(struct mtd_info *);
+extern int onenand_board_init(struct mtd_info *);
 
 /* Functions */
 extern void onenand_init(void);
-- 
cgit v0.10.2


From 52486927e7f0c9ea2c5af32cc21496c908cae661 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:21 +0200
Subject: mtd: OneNAND: initialize mtd->writebufsize to let UBI work

io_init checks this value and fails with "bad write buffer size 0 for
2048 min. I/O unit"

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index d194d97..0e35dc5 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -2657,6 +2657,7 @@ int onenand_probe(struct mtd_info *mtd)
 	mtd->_sync = onenand_sync;
 	mtd->_block_isbad = onenand_block_isbad;
 	mtd->_block_markbad = onenand_block_markbad;
+	mtd->writebufsize = mtd->writesize;
 
 	return 0;
 }
-- 
cgit v0.10.2


From c0ac3339475d3b6afc0cd901f20dd21d5fade17d Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:22 +0200
Subject: cmd: mtdparts: fix mtdparts variable presence confusion in
 mtdparts_init

A private buffer is used to read mtdparts variable from non-relocated
environment. A pointer to that buffer is returned unconditionally,
confusing later test for variable presence in the environment.
Fix it by returning NULL when getenv_f fails.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 44b2c3a..3a88a10 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1720,11 +1720,13 @@ int mtdparts_init(void)
 	 * before the env is relocated, then we need to use our own stack
 	 * buffer.  gd->env_buf will be too small.
 	 */
-	if (gd->flags & GD_FLG_ENV_READY) {
+	if (gd->flags & GD_FLG_ENV_READY)
 		parts = getenv("mtdparts");
-	} else {
-		parts = tmp_parts;
-		getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN);
+	else {
+		if (getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN) != -1)
+			parts = tmp_parts;
+		else
+			parts = NULL;
 	}
 	current_partition = getenv("partition");
 
-- 
cgit v0.10.2


From 06a040a31bcfc2673ab0670ee95fb9b078c4fdda Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:23 +0200
Subject: cmd: mtdparts: fix null pointer dereference in parse_mtdparts

In case there is no mtdparts variable in relocated environment,
NULL is assigned to p, which is later fed to strncpy.
Also function parameter mtdparts is completely ignored, so use it
in case mtdparts variable is not found in environment. This
parameter is checked not to be NULL in caller.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 3a88a10..995cb87 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1524,7 +1524,7 @@ static int spread_partitions(void)
  */
 static int parse_mtdparts(const char *const mtdparts)
 {
-	const char *p = mtdparts;
+	const char *p;
 	struct mtd_device *dev;
 	int err = 1;
 	char tmp_parts[MTDPARTS_MAXLEN];
@@ -1538,20 +1538,25 @@ static int parse_mtdparts(const char *const mtdparts)
 	}
 
 	/* re-read 'mtdparts' variable, mtd_devices_init may be updating env */
-	if (gd->flags & GD_FLG_ENV_READY) {
+	if (gd->flags & GD_FLG_ENV_READY)
 		p = getenv("mtdparts");
-	} else {
-		p = tmp_parts;
-		getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN);
+	else {
+		if (getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN) != -1)
+			p = tmp_parts;
+		else
+			p = NULL;
 	}
 
+	if (!p)
+		p = mtdparts;
+
 	if (strncmp(p, "mtdparts=", 9) != 0) {
 		printf("mtdparts variable doesn't start with 'mtdparts='\n");
 		return err;
 	}
 	p += 9;
 
-	while (p && (*p != '\0')) {
+	while (*p != '\0') {
 		err = 1;
 		if ((device_parse(p, &p, &dev) != 0) || (!dev))
 			break;
@@ -1569,12 +1574,10 @@ static int parse_mtdparts(const char *const mtdparts)
 		list_add_tail(&dev->link, &devices);
 		err = 0;
 	}
-	if (err == 1) {
+	if (err == 1)
 		device_delall(&devices);
-		return 1;
-	}
 
-	return 0;
+	return err;
 }
 
 /**
-- 
cgit v0.10.2


From 1c2a262a9d6132e52108a1b6bd36499ee1f06377 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:24 +0200
Subject: cmd: mtdparts: consolidate mtdparts reading from env

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 995cb87..7860ed9 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1516,6 +1516,23 @@ static int spread_partitions(void)
 #endif /* CONFIG_CMD_MTDPARTS_SPREAD */
 
 /**
+ * The mtdparts variable tends to be long. If we need to access it
+ * before the env is relocated, then we need to use our own stack
+ * buffer.  gd->env_buf will be too small.
+ *
+ * @param buf temporary buffer pointer MTDPARTS_MAXLEN long
+ * @return mtdparts variable string, NULL if not found
+ */
+static const char *getenv_mtdparts(char *buf)
+{
+	if (gd->flags & GD_FLG_ENV_READY)
+		return getenv("mtdparts");
+	if (getenv_f("mtdparts", buf, MTDPARTS_MAXLEN) != -1)
+		return buf;
+	return NULL;
+}
+
+/**
  * Accept character string describing mtd partitions and call device_parse()
  * for each entry. Add created devices to the global devices list.
  *
@@ -1538,15 +1555,7 @@ static int parse_mtdparts(const char *const mtdparts)
 	}
 
 	/* re-read 'mtdparts' variable, mtd_devices_init may be updating env */
-	if (gd->flags & GD_FLG_ENV_READY)
-		p = getenv("mtdparts");
-	else {
-		if (getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN) != -1)
-			p = tmp_parts;
-		else
-			p = NULL;
-	}
-
+	p = getenv_mtdparts(tmp_parts);
 	if (!p)
 		p = mtdparts;
 
@@ -1691,6 +1700,7 @@ static int parse_mtdids(const char *const ids)
 	return 0;
 }
 
+
 /**
  * Parse and initialize global mtdids mapping and create global
  * device/partition list.
@@ -1718,19 +1728,7 @@ int mtdparts_init(void)
 
 	/* get variables */
 	ids = getenv("mtdids");
-	/*
-	 * The mtdparts variable tends to be long. If we need to access it
-	 * before the env is relocated, then we need to use our own stack
-	 * buffer.  gd->env_buf will be too small.
-	 */
-	if (gd->flags & GD_FLG_ENV_READY)
-		parts = getenv("mtdparts");
-	else {
-		if (getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN) != -1)
-			parts = tmp_parts;
-		else
-			parts = NULL;
-	}
+	parts = getenv_mtdparts(tmp_parts);
 	current_partition = getenv("partition");
 
 	/* save it for later parsing, cannot rely on current partition pointer
-- 
cgit v0.10.2


From f8f744a3e8515cae50adefd861e34dab59f9ae6f Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:25 +0200
Subject: cmd: mtdparts: use defaults by default

Boards which are defining default mtdparts often need them early
in boot process (to load environment from UBI volume, for example).
This is currently solved by adding mtdparts and mtdids variable
definitions also to default environment. With this change, default
partitions are used by default unless explicitely deleted or
redefined.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 7860ed9..53074a1 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -142,6 +142,8 @@ static struct list_head devices;
 struct mtd_device *current_mtd_dev = NULL;
 u8 current_mtd_partnum = 0;
 
+u8 use_defaults;
+
 static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part_num);
 
 /* command line only routines */
@@ -1723,6 +1725,7 @@ int mtdparts_init(void)
 		memset(last_ids, 0, MTDIDS_MAXLEN);
 		memset(last_parts, 0, MTDPARTS_MAXLEN);
 		memset(last_partition, 0, PARTITION_MAXLEN);
+		use_defaults = 1;
 		initialized = 1;
 	}
 
@@ -1761,10 +1764,16 @@ int mtdparts_init(void)
 		return 1;
 	}
 
-	/* do no try to use defaults when mtdparts variable is not defined,
-	 * just check the length */
-	if (!parts)
-		printf("mtdparts variable not set, see 'help mtdparts'\n");
+	/* use defaults when mtdparts variable is not defined
+	 * once mtdparts is saved environment, drop use_defaults flag */
+	if (!parts) {
+		if (mtdparts_default && use_defaults) {
+			parts = mtdparts_default;
+			if (setenv("mtdparts", (char *)parts) == 0)
+				use_defaults = 0;
+		} else
+			printf("mtdparts variable not set, see 'help mtdparts'\n");
+	}
 
 	if (parts && (strlen(parts) > MTDPARTS_MAXLEN - 1)) {
 		printf("mtdparts too long (> %d)\n", MTDPARTS_MAXLEN);
@@ -1936,9 +1945,10 @@ static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc,
 {
 	if (argc == 2) {
 		if (strcmp(argv[1], "default") == 0) {
-			setenv("mtdids", (char *)mtdids_default);
-			setenv("mtdparts", (char *)mtdparts_default);
+			setenv("mtdids", NULL);
+			setenv("mtdparts", NULL);
 			setenv("partition", NULL);
+			use_defaults = 1;
 
 			mtdparts_init();
 			return 0;
-- 
cgit v0.10.2


From af32443656b64a9cbe5a2cdd9389225773b8e4d9 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:26 +0200
Subject: cmd: mtdparts: support runtime generated mtdparts

Some CPUs contains boot ROM code capable reading first few blocks
(where SPL resides) of NAND flash and executing it. It is wise to
create separate partition here for SPL. As block size depends on
NAND chip used, we could either use worst case (biggest) partition
size or base its size on actual block size. This patch adds support
for the latter option.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 53074a1..3f4f334 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -109,17 +109,17 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MTD_WRITEABLE_CMD		1
 
 /* default values for mtdids and mtdparts variables */
-#if defined(MTDIDS_DEFAULT)
-static const char *const mtdids_default = MTDIDS_DEFAULT;
-#else
-static const char *const mtdids_default = NULL;
+#if !defined(MTDIDS_DEFAULT)
+#define MTDIDS_DEFAULT NULL
 #endif
-
-#if defined(MTDPARTS_DEFAULT)
-static const char *const mtdparts_default = MTDPARTS_DEFAULT;
-#else
-static const char *const mtdparts_default = NULL;
+#if !defined(MTDPARTS_DEFAULT)
+#define MTDPARTS_DEFAULT NULL
 #endif
+#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
+extern void board_mtdparts_default(const char **mtdids, const char **mtdparts);
+#endif
+static const char *mtdids_default = MTDIDS_DEFAULT;
+static const char *mtdparts_default = MTDPARTS_DEFAULT;
 
 /* copies of last seen 'mtdids', 'mtdparts' and 'partition' env variables */
 #define MTDIDS_MAXLEN		128
@@ -1725,6 +1725,9 @@ int mtdparts_init(void)
 		memset(last_ids, 0, MTDIDS_MAXLEN);
 		memset(last_parts, 0, MTDPARTS_MAXLEN);
 		memset(last_partition, 0, PARTITION_MAXLEN);
+#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
+		board_mtdparts_default(&mtdids_default, &mtdparts_default);
+#endif
 		use_defaults = 1;
 		initialized = 1;
 	}
-- 
cgit v0.10.2


From b7e042d6af8263d03a8770cda999eed308192def Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:27 +0200
Subject: igep00x0: move sysinfo into C file

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index d1a6a6f..0ad5123 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -21,6 +21,24 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+	"IGEPv2",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+	"IGEP COM MODULE/ELECTRON",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
+	"IGEP COM PROTON",
+#endif
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	"ONENAND",
+#else
+	"NAND",
+#endif
+};
+
 #if defined(CONFIG_CMD_NET)
 /* GPMC definitions for LAN9221 chips */
 static const u32 gpmc_lan_config[] = {
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
index 3c7ff9b..e47ee66 100644
--- a/board/isee/igep00x0/igep00x0.h
+++ b/board/isee/igep00x0/igep00x0.h
@@ -7,24 +7,6 @@
 #ifndef _IGEP00X0_H_
 #define _IGEP00X0_H_
 
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-	"IGEPv2",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-	"IGEP COM MODULE/ELECTRON",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
-	"IGEP COM PROTON",
-#endif
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	"ONENAND",
-#else
-	"NAND",
-#endif
-};
-
 static void setup_net_chip(void);
 
 /*
-- 
cgit v0.10.2


From b0c47633cc550f2ded597aa80240a2d09619f827 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:28 +0200
Subject: igep00x0: reorder lan9221 code to remove ifdefs

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 0ad5123..4baaee5 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -39,18 +39,6 @@ const omap3_sysinfo sysinfo = {
 #endif
 };
 
-#if defined(CONFIG_CMD_NET)
-/* GPMC definitions for LAN9221 chips */
-static const u32 gpmc_lan_config[] = {
-	NET_LAN9221_GPMC_CONFIG1,
-	NET_LAN9221_GPMC_CONFIG2,
-	NET_LAN9221_GPMC_CONFIG3,
-	NET_LAN9221_GPMC_CONFIG4,
-	NET_LAN9221_GPMC_CONFIG5,
-	NET_LAN9221_GPMC_CONFIG6,
-};
-#endif
-
 static const struct ns16550_platdata igep_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
@@ -119,7 +107,6 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 #endif
 
 #if defined(CONFIG_CMD_NET)
-
 static void reset_net_chip(int gpio)
 {
 	if (!gpio_request(gpio, "eth nrst")) {
@@ -140,6 +127,14 @@ static void reset_net_chip(int gpio)
 static void setup_net_chip(void)
 {
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+	static const u32 gpmc_lan_config[] = {
+		NET_LAN9221_GPMC_CONFIG1,
+		NET_LAN9221_GPMC_CONFIG2,
+		NET_LAN9221_GPMC_CONFIG3,
+		NET_LAN9221_GPMC_CONFIG4,
+		NET_LAN9221_GPMC_CONFIG5,
+		NET_LAN9221_GPMC_CONFIG6,
+	};
 
 	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
 			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
@@ -154,6 +149,15 @@ static void setup_net_chip(void)
 
 	reset_net_chip(64);
 }
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#else
+	return 0;
+#endif
+}
 #else
 static inline void setup_net_chip(void) {}
 #endif
@@ -219,14 +223,3 @@ void set_muxconf_regs(void)
 	MUX_IGEP0030();
 #endif
 }
-
-#if defined(CONFIG_CMD_NET)
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#else
-	return 0;
-#endif
-}
-#endif
-- 
cgit v0.10.2


From cccdb1965b80c1068fff7d2978f668caa76119df Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:29 +0200
Subject: igep00x0: remove useless setup_net_chip declaration

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
index e47ee66..5698efa 100644
--- a/board/isee/igep00x0/igep00x0.h
+++ b/board/isee/igep00x0/igep00x0.h
@@ -7,8 +7,6 @@
 #ifndef _IGEP00X0_H_
 #define _IGEP00X0_H_
 
-static void setup_net_chip(void);
-
 /*
  * IEN  - Input Enable
  * IDIS - Input Disable
-- 
cgit v0.10.2


From c2d47fa6661c8e51acfd0619603194585fcb5689 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:30 +0200
Subject: igep00x0: remove unused empty function omap_rev_string()

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 4baaee5..5dfb7d2 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -69,14 +69,6 @@ int board_init(void)
 
 #ifdef CONFIG_SPL_BUILD
 /*
- * Routine: omap_rev_string
- * Description: For SPL builds output board rev
- */
-void omap_rev_string(void)
-{
-}
-
-/*
  * Routine: get_board_mem_timings
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
-- 
cgit v0.10.2


From 97ee70606cae6cc7cc300b20ffb5da3c4b547374 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:31 +0200
Subject: igep00x0: runtime flash detection

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 5dfb7d2..b36709c 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -17,6 +17,10 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-types.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/onenand.h>
+#include <jffs2/load_kernel.h>
 #include "igep00x0.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -56,7 +60,25 @@ U_BOOT_DEVICE(igep_uart) = {
  */
 int board_init(void)
 {
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	int loops = 100;
+
+	/* find out flash memory type, assume NAND first */
+	gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+	gpmc_init();
+
+	/* Issue a RESET and then READID */
+	writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+	writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+	while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+	                                        != NAND_STATUS_READY) {
+		udelay(1);
+		if (--loops == 0) {
+			gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+			gpmc_init();	/* reinitialize for OneNAND */
+			break;
+		}
+	}
+
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
@@ -75,29 +97,42 @@ int board_init(void)
  */
 void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-	timings->mr = MICRON_V_MR_165;
-#ifdef CONFIG_BOOT_NAND
-	timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-	timings->ctrla = MICRON_V_ACTIMA_200;
-	timings->ctrlb = MICRON_V_ACTIMB_200;
-	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-#else
-	if (get_cpu_family() == CPU_OMAP34XX) {
-		timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
-		timings->ctrla = NUMONYX_V_ACTIMA_165;
-		timings->ctrlb = NUMONYX_V_ACTIMB_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+	int mfr, id, err = identify_nand_chip(&mfr, &id);
 
-	} else {
-		timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
-		timings->ctrla = NUMONYX_V_ACTIMA_200;
-		timings->ctrlb = NUMONYX_V_ACTIMB_200;
+	timings->mr = MICRON_V_MR_165;
+	if (!err && mfr == NAND_MFR_MICRON) {
+		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_200;
+		timings->ctrlb = MICRON_V_ACTIMB_200;
 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+	} else {
+		if (get_cpu_family() == CPU_OMAP34XX) {
+			timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+			timings->ctrla = NUMONYX_V_ACTIMA_165;
+			timings->ctrlb = NUMONYX_V_ACTIMB_165;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+		} else {
+			timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+			timings->ctrla = NUMONYX_V_ACTIMA_200;
+			timings->ctrlb = NUMONYX_V_ACTIMB_200;
+			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+		}
+		gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 	}
-#endif
 }
 #endif
 
+int onenand_board_init(struct mtd_info *mtd)
+{
+	if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
+		struct onenand_chip *this = mtd->priv;
+		this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+		return 0;
+	}
+	return 1;
+}
+
 #if defined(CONFIG_CMD_NET)
 static void reset_net_chip(int gpio)
 {
-- 
cgit v0.10.2


From 4b9dc7c26b5a7e20c9be697f1ba3bb4ba995c643 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:32 +0200
Subject: igep00x0: UBIize

Convert IGEP board to use UBI volumes for U-Boot, its environment and
kernel. With exception of first four sectors read by SoC boot
ROM whole (One)NAND is UBI managed.
Also merge NAND and OneNAND defconfigs as now one binary can serve
both flashes.
As code is too big now, drop CONFIG_SPL_EXT_SUPPORT to make it fit.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 66dd93f..649dd47 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -2,7 +2,8 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -24,4 +25,5 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_nand_defconfig b/configs/igep0020_nand_defconfig
deleted file mode 100644
index 7535d10..0000000
--- a/configs/igep0020_nand_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 9bd8915..03ffda9 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -10,11 +10,8 @@
 #ifndef __IGEP00X0_H
 #define __IGEP00X0_H
 
-#ifdef CONFIG_BOOT_NAND
-#define CONFIG_NAND
-#endif
-
 #define CONFIG_NR_DRAM_BANKS            2
+#define CONFIG_NAND
 
 #include <configs/ti_omap3_common.h>
 #include <asm/mach-types.h>
@@ -76,9 +73,9 @@
 #define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
 #define CONFIG_USBD_PRODUCT_NAME	"IGEP"
 
-#ifdef CONFIG_BOOT_ONENAND
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
-#endif
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_UBI
 
 #ifndef CONFIG_SPL_BUILD
 
@@ -106,27 +103,6 @@
 #endif
 
 /*
- * FLASH and environment organization
- */
-
-#ifdef CONFIG_BOOT_ONENAND
-#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-
-#define CONFIG_ENV_IS_IN_ONENAND	1
-#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
-#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
-#endif
-
-#ifdef CONFIG_NAND
-#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
-#define CONFIG_ENV_IS_IN_NAND	        1
-#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
-#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
-#endif
-
-/*
  * SMSC911x Ethernet
  */
 #if defined(CONFIG_CMD_NET)
@@ -135,19 +111,18 @@
 #define CONFIG_SMC911X_BASE		0x2C000000
 #endif /* (CONFIG_CMD_NET) */
 
-/* OneNAND boot config */
-#ifdef CONFIG_BOOT_ONENAND
-#define CONFIG_SPL_ONENAND_SUPPORT
-#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
-#define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
-#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
-#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
-	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
 
-#endif
+/* OneNAND config */
+#define CONFIG_SPL_ONENAND_SUPPORT
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+#define CONFIG_SYS_ONENAND_BLOCK_SIZE	(128*1024)
 
-/* NAND boot config */
-#ifdef CONFIG_NAND
+/* NAND config */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
@@ -168,13 +143,29 @@
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_BCH
 
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_CMD_SPL_NAND_OFS		0x240000
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
-#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
-#endif
-#endif
+/* UBI configuration */
+#define CONFIG_SPL_UBI			1
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	(256*1024)
+#define CONFIG_SPL_UBI_MAX_PEBS		4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_LOAD_KERNEL_ID	3
+#define CONFIG_SPL_UBI_LOAD_ARGS_ID	4
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	0x88080000
+
+/* environment organization */
+#define CONFIG_ENV_IS_IN_UBI		1
+#define CONFIG_ENV_UBI_PART		"UBI"
+#define CONFIG_ENV_UBI_VOLUME		"config"
+#define CONFIG_ENV_UBI_VOLUME_REDUND	"config_r"
+#define CONFIG_UBI_SILENCE_MSG		1
+#define CONFIG_UBIFS_SILENCE_MSG	1
+#define CONFIG_ENV_SIZE			(32*1024)
+
+#undef CONFIG_SPL_EXT_SUPPORT
 
 #endif /* __IGEP00X0_H */
-- 
cgit v0.10.2


From a5debaa3920ca1f50896a2cfc25597f4aaca7bf6 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:33 +0200
Subject: igep00x0: generate default mtdparts according NAND chip used

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index b36709c..4c52b36 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -17,6 +17,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-types.h>
+#include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/onenand.h>
@@ -232,6 +233,23 @@ int misc_init_r(void)
 	return 0;
 }
 
+void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+	struct mtd_info *mtd = get_mtd_device(NULL, 0);
+	if (mtd) {
+		static char ids[24];
+		static char parts[48];
+		const char *linux_name = "omap2-nand";
+		if (strncmp(mtd->name, "onenand0", 8) == 0)
+			linux_name = "omap2-onenand";
+		snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
+		snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
+		         linux_name, 4 * mtd->erasesize >> 10);
+		*mtdids = ids;
+		*mtdparts = parts;
+	}
+}
+
 /*
  * Routine: set_muxconf_regs
  * Description: Setting up the configuration Mux registers specific to the
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 03ffda9..e0d2593 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -113,6 +113,7 @@
 
 #define CONFIG_RBTREE
 #define CONFIG_MTD_PARTITIONS
+#define CONFIG_SYS_MTDPARTS_RUNTIME
 
 /* OneNAND config */
 #define CONFIG_SPL_ONENAND_SUPPORT
-- 
cgit v0.10.2


From fe9f6289e1a50d691ad591fa4224b8a3aa250848 Mon Sep 17 00:00:00 2001
From: Ladislav Michl <ladis@linux-mips.org>
Date: Tue, 12 Jul 2016 20:28:34 +0200
Subject: igep00x0: Falcon mode

Implement spl_start_uboot to let Falcon mode work.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 4c52b36..808955e 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -10,6 +10,7 @@
 #include <ns16550.h>
 #include <twl4030.h>
 #include <netdev.h>
+#include <spl.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/mem.h>
@@ -122,6 +123,17 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 		gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
 	}
 }
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
 #endif
 
 int onenand_board_init(struct mtd_info *mtd)
-- 
cgit v0.10.2


From 28f0014bde9993354223ed250df22ba97d381565 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 21 Jul 2016 01:31:56 +0200
Subject: iso: Fix part info command

Partitions on the iso el torito partition table interpreter
only start from partition 1. So when printing out the tables,
let's also start counting at 1.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/disk/part_iso.c b/disk/part_iso.c
index 9f5c50c..f9a741d 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -233,13 +233,13 @@ static void part_print_iso(struct blk_desc *dev_desc)
 	disk_partition_t info;
 	int i;
 
-	if (part_get_info_iso_verb(dev_desc, 0, &info, 0) == -1) {
+	if (part_get_info_iso_verb(dev_desc, 1, &info, 0) == -1) {
 		printf("** No boot partition found on device %d **\n",
 		       dev_desc->devnum);
 		return;
 	}
 	printf("Part   Start     Sect x Size Type\n");
-	i=0;
+	i=1;
 	do {
 		printf(" %2d " LBAFU " " LBAFU " %6ld %.32s\n",
 		       i, info.start, info.size, info.blksz, info.type);
-- 
cgit v0.10.2


From 14fb5b252ac21c81e24fa734c3f66e9d6c3a0932 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 17:14:37 -0700
Subject: tools/env: complete environment device config early

Currently flash_read completes a crucial part of the environment
device configuration, the device type (mtd_type). This is rather
confusing as flash_io calls flash_read conditionally, and one might
think flash_write, which also makes use of mtd_type, gets called
before flash_read. But since flash_io is always called with O_RDONLY
first, this is not actually the case in reality.

However, it is much cleaner to complete and verify the config early
in parse_config. This also prepares the code for further extension.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Andreas Fenkart

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 692abda..06d6865 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1021,41 +1021,10 @@ static int flash_write (int fd_current, int fd_target, int dev_target)
 
 static int flash_read (int fd)
 {
-	struct mtd_info_user mtdinfo;
-	struct stat st;
 	int rc;
 
-	rc = fstat(fd, &st);
-	if (rc < 0) {
-		fprintf(stderr, "Cannot stat the file %s\n",
-			DEVNAME(dev_current));
-		return -1;
-	}
-
-	if (S_ISCHR(st.st_mode)) {
-		rc = ioctl(fd, MEMGETINFO, &mtdinfo);
-		if (rc < 0) {
-			fprintf(stderr, "Cannot get MTD information for %s\n",
-				DEVNAME(dev_current));
-			return -1;
-		}
-		if (mtdinfo.type != MTD_NORFLASH &&
-		    mtdinfo.type != MTD_NANDFLASH &&
-		    mtdinfo.type != MTD_DATAFLASH &&
-		    mtdinfo.type != MTD_UBIVOLUME) {
-			fprintf (stderr, "Unsupported flash type %u on %s\n",
-				 mtdinfo.type, DEVNAME(dev_current));
-			return -1;
-		}
-	} else {
-		memset(&mtdinfo, 0, sizeof(mtdinfo));
-		mtdinfo.type = MTD_ABSENT;
-	}
-
-	DEVTYPE(dev_current) = mtdinfo.type;
-
 	rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
-			     DEVOFFSET (dev_current), mtdinfo.type);
+			    DEVOFFSET(dev_current), DEVTYPE(dev_current));
 	if (rc != CUR_ENVSIZE)
 		return -1;
 
@@ -1328,10 +1297,55 @@ int fw_env_open(struct env_opts *opts)
 	return 0;
 }
 
+static int check_device_config(int dev)
+{
+	struct stat st;
+	int fd, rc = 0;
+
+	fd = open(DEVNAME(dev), O_RDONLY);
+	if (fd < 0) {
+		fprintf(stderr,
+			"Cannot open %s: %s\n",
+			DEVNAME(dev), strerror(errno));
+		return -1;
+	}
+
+	rc = fstat(fd, &st);
+	if (rc < 0) {
+		fprintf(stderr, "Cannot stat the file %s\n",
+			DEVNAME(dev));
+		goto err;
+	}
+
+	if (S_ISCHR(st.st_mode)) {
+		struct mtd_info_user mtdinfo;
+		rc = ioctl(fd, MEMGETINFO, &mtdinfo);
+		if (rc < 0) {
+			fprintf(stderr, "Cannot get MTD information for %s\n",
+				DEVNAME(dev));
+			goto err;
+		}
+		if (mtdinfo.type != MTD_NORFLASH &&
+		    mtdinfo.type != MTD_NANDFLASH &&
+		    mtdinfo.type != MTD_DATAFLASH &&
+		    mtdinfo.type != MTD_UBIVOLUME) {
+			fprintf(stderr, "Unsupported flash type %u on %s\n",
+				mtdinfo.type, DEVNAME(dev));
+			goto err;
+		}
+		DEVTYPE(dev) = mtdinfo.type;
+	} else {
+		DEVTYPE(dev) = MTD_ABSENT;
+	}
+
+err:
+	close(fd);
+	return rc;
+}
 
 static int parse_config(struct env_opts *opts)
 {
-	struct stat st;
+	int rc;
 
 	if (!opts)
 		opts = &default_opts;
@@ -1375,25 +1389,21 @@ static int parse_config(struct env_opts *opts)
 	HaveRedundEnv = 1;
 #endif
 #endif
-	if (stat (DEVNAME (0), &st)) {
-		fprintf (stderr,
-			"Cannot access MTD device %s: %s\n",
-			DEVNAME (0), strerror (errno));
-		return -1;
-	}
+	rc = check_device_config(0);
+	if (rc < 0)
+		return rc;
 
-	if (HaveRedundEnv && stat (DEVNAME (1), &st)) {
-		fprintf (stderr,
-			"Cannot access MTD device %s: %s\n",
-			DEVNAME (1), strerror (errno));
-		return -1;
-	}
+	if (HaveRedundEnv) {
+		rc = check_device_config(1);
+		if (rc < 0)
+			return rc;
 
-	if (HaveRedundEnv && ENVSIZE(0) != ENVSIZE(1)) {
-		ENVSIZE(0) = ENVSIZE(1) = min(ENVSIZE(0), ENVSIZE(1));
-		fprintf(stderr,
-			"Redundant environments have inequal size, set to 0x%08lx\n",
-			ENVSIZE(1));
+		if (ENVSIZE(0) != ENVSIZE(1)) {
+			ENVSIZE(0) = ENVSIZE(1) = min(ENVSIZE(0), ENVSIZE(1));
+			fprintf(stderr,
+				"Redundant environments have inequal size, set to 0x%08lx\n",
+				ENVSIZE(1));
+		}
 	}
 
 	usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
-- 
cgit v0.10.2


From f4742ca0fb94e531b8dcddd1ac0799ee4c9c2605 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 13 Jul 2016 17:14:38 -0700
Subject: tools/env: allow negative offsets

A negative value for the offset is treated as a backwards offset for
from the end of the device/partition for block devices. This aligns
the behavior of the config file with the syntax of CONFIG_ENV_OFFSET
where the functionality has been introduced with
commit 5c088ee841f9 ("env_mmc: allow negative CONFIG_ENV_OFFSET").

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 06d6865..be338a5b 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -14,6 +14,7 @@
 #include <errno.h>
 #include <env_flags.h>
 #include <fcntl.h>
+#include <linux/fs.h>
 #include <linux/stringify.h>
 #include <ctype.h>
 #include <stdio.h>
@@ -51,7 +52,7 @@ struct env_opts default_opts = {
 
 struct envdev_s {
 	const char *devname;		/* Device name */
-	ulong devoff;			/* Device offset */
+	long long devoff;		/* Device offset */
 	ulong env_size;			/* environment size */
 	ulong erase_size;		/* device erase size */
 	ulong env_sectors;		/* number of environment sectors */
@@ -994,7 +995,7 @@ static int flash_write (int fd_current, int fd_target, int dev_target)
 	}
 
 #ifdef DEBUG
-	fprintf(stderr, "Writing new environment at 0x%lx on %s\n",
+	fprintf(stderr, "Writing new environment at 0x%llx on %s\n",
 		DEVOFFSET (dev_target), DEVNAME (dev_target));
 #endif
 
@@ -1010,7 +1011,7 @@ static int flash_write (int fd_current, int fd_target, int dev_target)
 			offsetof (struct env_image_redundant, flags);
 #ifdef DEBUG
 		fprintf(stderr,
-			"Setting obsolete flag in environment at 0x%lx on %s\n",
+			"Setting obsolete flag in environment at 0x%llx on %s\n",
 			DEVOFFSET (dev_current), DEVNAME (dev_current));
 #endif
 		flash_flag_obsolete (dev_current, fd_current, offset);
@@ -1335,7 +1336,27 @@ static int check_device_config(int dev)
 		}
 		DEVTYPE(dev) = mtdinfo.type;
 	} else {
+		uint64_t size;
 		DEVTYPE(dev) = MTD_ABSENT;
+
+		/*
+		 * Check for negative offsets, treat it as backwards offset
+		 * from the end of the block device
+		 */
+		if (DEVOFFSET(dev) < 0) {
+			rc = ioctl(fd, BLKGETSIZE64, &size);
+			if (rc < 0) {
+				fprintf(stderr, "Could not get block device size on %s\n",
+					DEVNAME(dev));
+				goto err;
+			}
+
+			DEVOFFSET(dev) = DEVOFFSET(dev) + size;
+#ifdef DEBUG
+			fprintf(stderr, "Calculated device offset 0x%llx on %s\n",
+				DEVOFFSET(dev), DEVNAME(dev));
+#endif
+		}
 	}
 
 err:
@@ -1434,12 +1455,12 @@ static int get_config (char *fname)
 		if (dump[0] == '#')
 			continue;
 
-		rc = sscanf (dump, "%ms %lx %lx %lx %lx",
-			     &devname,
-			     &DEVOFFSET (i),
-			     &ENVSIZE (i),
-			     &DEVESIZE (i),
-			     &ENVSECTORS (i));
+		rc = sscanf(dump, "%ms %lli %lx %lx %lx",
+			    &devname,
+			    &DEVOFFSET(i),
+			    &ENVSIZE(i),
+			    &DEVESIZE(i),
+			    &ENVSECTORS(i));
 
 		if (rc < 3)
 			continue;
diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config
index 776e16f..7916ebd 100644
--- a/tools/env/fw_env.config
+++ b/tools/env/fw_env.config
@@ -4,6 +4,7 @@
 # Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
 # Futhermore, if the Flash sector size is omitted, this value is assumed to
 # be the same as the Environment size, which is valid for NOR and SPI-dataflash
+# Device offset must be prefixed with 0x to be parsed as a hexadecimal value.
 
 # NOR example
 # MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
@@ -18,8 +19,12 @@
 # NAND example
 #/dev/mtd0		0x4000		0x4000		0x20000			2
 
+# On a block device a negative offset is treated as a backwards offset from the
+# end of the device/partition, rather than a forwards offset from the start.
+
 # Block device example
 #/dev/mmcblk0		0xc0000		0x20000
+#/dev/mmcblk0		-0x20000	0x20000
 
 # VFAT example
 #/boot/uboot.env	0x0000          0x4000
-- 
cgit v0.10.2


From 473c0abe6290aaf1471ce8129a67e3c2fbfc2597 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Fri, 15 Jul 2016 15:51:40 -0400
Subject: gdsys: Drop print_fpga_state function

On most platforms the print_fpga_state function is never called.  Only
on dlvision-10g do we, so in that case inline it.  Drop it from
everywhere else to avoid extra strings.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Acked-by: Dirk Eibach <dirk.eibach@gdsys.cc>

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 426dc05..35fa06a 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -31,14 +31,6 @@ int get_fpga_state(unsigned dev)
 	return gd->arch.fpga_state[dev];
 }
 
-void print_fpga_state(unsigned dev)
-{
-	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
-		puts("       Waiting for FPGA-DONE timed out.\n");
-	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
-		puts("       FPGA reflection test failed.\n");
-}
-
 int board_early_init_f(void)
 {
 	unsigned k;
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index 54c7eb3..e400d19 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -109,7 +109,10 @@ static void print_fpga_info(unsigned dev)
 	    && !((hardware_version == HWVER_101)
 		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
 		puts("not available\n");
-		print_fpga_state(dev);
+		if (fpga_state & FPGA_STATE_DONE_FAILED)
+			puts("       Waiting for FPGA-DONE timed out.\n");
+		if (fpga_state & FPGA_STATE_REFLECTION_FAILED)
+			puts("       FPGA reflection test failed.\n");
 		return;
 	}
 
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index c1a583f..9e1c57f 100644
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -24,14 +24,6 @@ int get_fpga_state(unsigned dev)
 	return gd->arch.fpga_state[dev];
 }
 
-void print_fpga_state(unsigned dev)
-{
-	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
-		puts("       Waiting for FPGA-DONE timed out.\n");
-	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
-		puts("       FPGA reflection test failed.\n");
-}
-
 int board_early_init_f(void)
 {
 	u32 val;
diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c
index 4338a33..1b8e035 100644
--- a/board/gdsys/mpc8308/mpc8308.c
+++ b/board/gdsys/mpc8308/mpc8308.c
@@ -31,14 +31,6 @@ int get_fpga_state(unsigned dev)
 	return gd->arch.fpga_state[dev];
 }
 
-void print_fpga_state(unsigned dev)
-{
-	if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
-		puts("       Waiting for FPGA-DONE timed out.\n");
-	if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
-		puts("       FPGA reflection test failed.\n");
-}
-
 int board_early_init_f(void)
 {
 	unsigned k;
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index e1b9c64..bb8e144 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -17,7 +17,6 @@ enum {
 };
 
 int get_fpga_state(unsigned dev);
-void print_fpga_state(unsigned dev);
 
 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
-- 
cgit v0.10.2


From fd4e3280e50983aa4d646f2c8fc93b38cc1dddf9 Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Sat, 16 Jul 2016 17:06:13 +0200
Subject: tools/env: kernel-doc for fw_printenv, fw_getenv and fw_parse_script

there are two groups of functions:
- application ready tools: fw_setenv/fw_getenv/fw_parse_script
these are used, when creating a single binary containing multiple
tools (busybox like)
- file access like: open/read/write/close
above functions are implemented on top of these. applications
can use those to modify several variables without creating a
temporary batch script file
tested with "./scripts/kernel-doc -html -v tools/env/fw_env.h"

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index be338a5b..1dad1ce 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -484,7 +484,7 @@ int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 	valc = argc - 1;
 
 	if (env_flags_validate_env_set_params(name, valv, valc) < 0)
-		return 1;
+		return -1;
 
 	len = 0;
 	for (i = 0; i < valc; ++i) {
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index dac964d..436eca9 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -67,12 +67,125 @@ struct env_opts {
 
 int parse_aes_key(char *key, uint8_t *bin_key);
 
+/**
+ * fw_printenv() - print one or several environment variables
+ *
+ * @argc: number of variables names to be printed, prints all if 0
+ * @argv: array of variable names to be printed, if argc != 0
+ * @value_only: do not repeat the variable name, print the bare value,
+ *          only one variable allowed with this option, argc must be 1
+ * @opts: encryption key, configuration file, defaults are used if NULL
+ *
+ * Description:
+ *  Uses fw_env_open, fw_getenv
+ *
+ * Return:
+ *  0 on success, -1 on failure (modifies errno)
+ */
 int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts);
-char *fw_getenv(char *name);
+
+/**
+ * fw_setenv() - adds or removes one variable to the environment
+ *
+ * @argc: number of strings in argv, argv[0] is variable name,
+ *          argc==1 means erase variable, argc > 1 means add a variable
+ * @argv: argv[0] is variable name, argv[1..argc-1] are concatenated separated
+ *           by single blank and set as the new value of the variable
+ * @opts: how to retrieve environment from flash, defaults are used if NULL
+ *
+ * Description:
+ *  Uses fw_env_open, fw_env_write, fw_env_close
+ *
+ * Return:
+ *  0 on success, -1 on failure (modifies errno)
+ *
+ * ERRORS:
+ *  EROFS - some variables ("ethaddr", "serial#") cannot be modified
+ */
 int fw_setenv(int argc, char *argv[], struct env_opts *opts);
+
+/**
+ * fw_parse_script() - adds or removes multiple variables with a batch script
+ *
+ * @fname: batch script file name
+ * @opts: encryption key, configuration file, defaults are used if NULL
+ *
+ * Description:
+ *  Uses fw_env_open, fw_env_write, fw_env_close
+ *
+ * Return:
+ *  0 success, -1 on failure (modifies errno)
+ *
+ * Script Syntax:
+ *
+ *  key [ [space]+ value]
+ *
+ *  lines starting with '#' treated as comment
+ *
+ *  A variable without value will be deleted. Any number of spaces are allowed
+ *  between key and value. The value starts with the first non-space character
+ *  and ends with newline. No comments allowed on these lines.  Spaces inside
+ *  the value are preserved verbatim.
+ *
+ * Script Example:
+ *
+ *  netdev         eth0
+ *
+ *  kernel_addr    400000
+ *
+ *  foo            spaces           are copied verbatim
+ *
+ *  # delete variable bar
+ *
+ *  bar
+ */
 int fw_parse_script(char *fname, struct env_opts *opts);
+
+
+/**
+ * fw_env_open() - read enviroment from flash into RAM cache
+ *
+ * @opts: encryption key, configuration file, defaults are used if NULL
+ *
+ * Return:
+ *  0 on success, -1 on failure (modifies errno)
+ */
 int fw_env_open(struct env_opts *opts);
+
+/**
+ * fw_getenv() - lookup variable in the RAM cache
+ *
+ * @name: variable to be searched
+ * Return:
+ *  pointer to start of value, NULL if not found
+ */
+char *fw_getenv(char *name);
+
+/**
+ * fw_env_write() - modify a variable held in the RAM cache
+ *
+ * @name: variable
+ * @value: delete variable if NULL, otherwise create or overwrite the variable
+ *
+ * This is called in sequence to update the environment in RAM without updating
+ * the copy in flash after each set
+ *
+ * Return:
+ *  0 on success, -1 on failure (modifies errno)
+ *
+ * ERRORS:
+ *  EROFS - some variables ("ethaddr", "serial#") cannot be modified
+ */
 int fw_env_write(char *name, char *value);
+
+/**
+ * fw_env_close - write the environment from RAM cache back to flash
+ *
+ * @opts: encryption key, configuration file, defaults are used if NULL
+ *
+ * Return:
+ *  0 on success, -1 on failure (modifies errno)
+ */
 int fw_env_close(struct env_opts *opts);
 
 unsigned long crc32(unsigned long, const unsigned char *, unsigned);
-- 
cgit v0.10.2


From 1b7427cd2ab6aae150559ee2edc8965fda113fdf Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Sat, 16 Jul 2016 17:06:14 +0200
Subject: tools/env: move envmatch further up in file to avoid forward
 declarations

forward declaration not needed when re-ordered

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 1dad1ce..faba9a9 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -122,7 +122,6 @@ static unsigned char obsolete_flag = 0;
 #include <env_default.h>
 
 static int flash_io (int mode);
-static char *envmatch (char * s1, char * s2);
 static int parse_config(struct env_opts *opts);
 
 #if defined(CONFIG_FILE)
@@ -148,6 +147,24 @@ static char *skip_blanks(char *s)
 }
 
 /*
+ * s1 is either a simple 'name', or a 'name=value' pair.
+ * s2 is a 'name=value' pair.
+ * If the names match, return the value of s2, else NULL.
+ */
+static char *envmatch(char *s1, char *s2)
+{
+	if (s1 == NULL || s2 == NULL)
+		return NULL;
+
+	while (*s1 == *s2++)
+		if (*s1++ == '=')
+			return s2;
+	if (*s1 == '\0' && *(s2 - 1) == '=')
+		return s2;
+	return NULL;
+}
+
+/**
  * Search the environment for a variable.
  * Return the value, if found, or NULL, if not found.
  */
@@ -1091,25 +1108,6 @@ exit:
 }
 
 /*
- * s1 is either a simple 'name', or a 'name=value' pair.
- * s2 is a 'name=value' pair.
- * If the names match, return the value of s2, else NULL.
- */
-
-static char *envmatch (char * s1, char * s2)
-{
-	if (s1 == NULL || s2 == NULL)
-		return NULL;
-
-	while (*s1 == *s2++)
-		if (*s1++ == '=')
-			return s2;
-	if (*s1 == '\0' && *(s2 - 1) == '=')
-		return s2;
-	return NULL;
-}
-
-/*
  * Prevent confusion if running from erased flash memory
  */
 int fw_env_open(struct env_opts *opts)
-- 
cgit v0.10.2


From c5c41c45b1025aa951c794bb8add9c7c806496ee Mon Sep 17 00:00:00 2001
From: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Date: Sat, 16 Jul 2016 17:06:15 +0200
Subject: tools/env: reuse fw_getenv in fw_printenv function

Try to avoid adhoc iteration of the environment. Reuse fw_getenv
to find the variables that should be printed. Only use open-coded
iteration when printing all variables.
For backwards compatibility, keep emitting a newline when
printing with value_only.

Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index faba9a9..34ceebd 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -250,9 +250,14 @@ int parse_aes_key(char *key, uint8_t *bin_key)
  */
 int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 {
-	char *env, *nxt;
 	int i, rc = 0;
 
+	if (value_only && argc != 1) {
+		fprintf(stderr,
+			"## Error: `-n' option requires exactly one argument\n");
+		return -1;
+	}
+
 	if (!opts)
 		opts = &default_opts;
 
@@ -260,6 +265,7 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 		return -1;
 
 	if (argc == 0) {		/* Print all env variables  */
+		char *env, *nxt;
 		for (env = environment.data; *env; env = nxt + 1) {
 			for (nxt = env; *nxt; ++nxt) {
 				if (nxt >= &environment.data[ENV_SIZE]) {
@@ -274,39 +280,23 @@ int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 		return 0;
 	}
 
-	if (value_only && argc != 1) {
-		fprintf(stderr,
-			"## Error: `-n' option requires exactly one argument\n");
-		return -1;
-	}
-
-	for (i = 0; i < argc; ++i) {	/* print single env variables   */
+	for (i = 0; i < argc; ++i) {	/* print a subset of env variables */
 		char *name = argv[i];
 		char *val = NULL;
 
-		for (env = environment.data; *env; env = nxt + 1) {
-
-			for (nxt = env; *nxt; ++nxt) {
-				if (nxt >= &environment.data[ENV_SIZE]) {
-					fprintf (stderr, "## Error: "
-						"environment not terminated\n");
-					return -1;
-				}
-			}
-			val = envmatch (name, env);
-			if (val) {
-				if (!value_only) {
-					fputs (name, stdout);
-					putc ('=', stdout);
-				}
-				puts (val);
-				break;
-			}
-		}
+		val = fw_getenv(name);
 		if (!val) {
 			fprintf (stderr, "## Error: \"%s\" not defined\n", name);
 			rc = -1;
+			continue;
 		}
+
+		if (value_only) {
+			puts(val);
+			break;
+		}
+
+		printf("%s=%s\n", name, val);
 	}
 
 	return rc;
-- 
cgit v0.10.2


From c933ed94bc866606f2edae8b4a914880e7e1f501 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Sun, 17 Jul 2016 06:57:11 +0200
Subject: efi_loader: Add debug output for efi_add_memory_map()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Tracing the arguments has been helpful for pinpointing overflows.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>

diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index df2381e..df3547c 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -130,6 +130,9 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 	bool carve_again;
 	uint64_t carved_pages = 0;
 
+	debug("%s: 0x%" PRIx64 " 0x%" PRIx64 " %d %s\n", __func__,
+	      start, pages, memory_type, overlap_only_ram ? "yes" : "no");
+
 	if (!pages)
 		return start;
 
-- 
cgit v0.10.2


From b8cb51d0de9457c270e63e876712213c5cbbf5dc Mon Sep 17 00:00:00 2001
From: Jeremy Hunt <Jeremy.Hunt@DEShawResearch.com>
Date: Mon, 18 Jul 2016 12:01:02 -0400
Subject: armv8: spl: Call board_init_r from crt0_64 in SPL

As part of the startup process for boards using the SPL, the
meaning of board_init_f changed such that it should return normally
rather than calling board_init_r directly. (see
db910353a126d84fe8dff7a694ea792f50fcfb6a )
This was fixed in 32-bit arm, but broke when SPL was added to
64 bit arm. This fixes crt0_64 so that it calls board_init_r
during the SPL and removes the direct call from board_init_f
from the arm SPL example.

Signed-off-by: Jeremy Hunt <Jeremy.Hunt@DEShawResearch.com>

Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index cad22c7..91b19e0 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -108,6 +108,7 @@ relocation_return:
  * Set up final (full) environment
  */
 	bl	c_runtime_cpu_setup		/* still call old routine */
+#endif /* !CONFIG_SPL_BUILD */
 
 /* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */
 
@@ -130,6 +131,4 @@ clear_loop:
 
 	/* NOTREACHED - board_init_r() does not return */
 
-#endif /* !CONFIG_SPL_BUILD */
-
 ENDPROC(_main)
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index c1b8534..3587ad6 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -25,22 +25,20 @@ gd_t gdata __attribute__ ((section(".data")));
 #endif
 
 /*
- * In the context of SPL, board_init_f must ensure that any clocks/etc for
- * DDR are enabled, ensure that the stack pointer is valid, clear the BSS
- * and call board_init_r.  We provide this version by default but mark it
- * as __weak to allow for platforms to do this in their own way if needed.
+ * In the context of SPL, board_init_f() prepares the hardware for execution
+ * from system RAM (DRAM, DDR...). As system RAM may not be available yet,
+ * board_init_f() must use the current GD to store any data which must be
+ * passed on to later stages. These data include the relocation destination,
+ * the future stack, and the future GD location. BSS is cleared after this
+ * function (and therefore must be accessible).
+ *
+ * We provide this version by default but mark it as __weak to allow for
+ * platforms to do this in their own way if needed. Please see the top
+ * level U-Boot README "Board Initialization Flow" section for info on what
+ * to put in this function.
  */
 void __weak board_init_f(ulong dummy)
 {
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-#ifndef CONFIG_SPL_DM
-	/* TODO: Remove settings of the global data pointer here */
-	gd = &gdata;
-#endif
-
-	board_init_r(NULL, 0);
 }
 
 /*
-- 
cgit v0.10.2


From c9ba60c4385bfbc10dc452a8f79c6db04bf18161 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 18 Jul 2016 10:07:25 -0600
Subject: test/py: use absolute dts path in vboot test

Without this, the test fails if the test is run with a cwd other than the
root of the U-Boot source tree.

Fixes: 8729d582595d ("test: Convert the vboot test to test/py")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index c779895..25a7832 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -151,7 +151,7 @@ def test_vboot(u_boot_console):
     cons = u_boot_console
     tmpdir = cons.config.result_dir + '/'
     tmp = tmpdir + 'vboot.tmp'
-    datadir = 'test/py/tests/vboot/'
+    datadir = cons.config.source_dir + '/test/py/tests/vboot/'
     fit = '%stest.fit' % tmpdir
     mkimage = cons.config.build_dir + '/tools/mkimage'
     fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
-- 
cgit v0.10.2


From c236ebd2fa04e872bb248c363e558961e1d138f0 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Tue, 19 Jul 2016 11:07:06 +0200
Subject: tools: Fix return code of fit_image_process_sig()

When signing images, we repeatedly call fit_add_file_data() with
successively increasing size values to include the keys in the DTB.

Unfortunately, if large keys are used (such as 4096 bit RSA keys), this
process fails sometimes, and mkimage needs to be called repeatedly to
integrate the keys into the DTB.

This is because fit_add_file_data actually returns the wrong error
code, and the loop terminates prematurely, instead of trying again with
a larger size value.

This patch corrects the return value and also removes a error message,
which is misleading, since we actually allow the function to fail. A
(hopefully helpful) comment is also added to explain the lack of error
message.

This is probably related to 1152a05 ("tools: Correct error handling in
fit_image_process_hash()") and the corresponding error reported here:

https://www.mail-archive.com/u-boot@lists.denx.de/msg217417.html

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/tools/image-host.c b/tools/image-host.c
index 3e14fdc..399ec94 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -238,12 +238,13 @@ static int fit_image_process_sig(const char *keydir, void *keydest,
 	/* Get keyname again, as FDT has changed and invalidated our pointer */
 	info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
 
-	/* Write the public key into the supplied FDT file */
-	if (keydest && info.algo->add_verify_data(&info, keydest)) {
-		printf("Failed to add verification data for '%s' signature node in '%s' image node\n",
-		       node_name, image_name);
-		return -1;
-	}
+	ret = info.algo->add_verify_data(&info, keydest);
+
+	/* Write the public key into the supplied FDT file; this might fail
+	 * several times, since we try signing with successively increasing
+	 * size values */
+	if (keydest && ret)
+		return ret;
 
 	return 0;
 }
-- 
cgit v0.10.2


From 2b9ec762c4fb5c0f933f5b3380ef9f5c353d0eef Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Tue, 19 Jul 2016 11:07:07 +0200
Subject: rsa: Fix return value and masked error

When signing images, we repeatedly call fit_add_file_data() with
successively increasing size values to include the keys in the DTB.

Unfortunately, if large keys are used (such as 4096 bit RSA keys), this
process fails sometimes, and mkimage needs to be called repeatedly to
integrate the keys into the DTB.

This is because fit_add_file_data actually returns the wrong error
code, and the loop terminates prematurely, instead of trying again with
a larger size value.

This patch corrects the return value by fixing the return value of
fdt_add_bignum, fixes a case where an error is masked by a unconditional
setting of a return value variable, and also removes a error message,
which is misleading, since we actually allow the function to fail. A
(hopefully helpful) comment is also added to explain the lack of error
message.

This is probably related to 1152a05 ("tools: Correct error handling in
fit_image_process_hash()") and the corresponding error reported here:

https://www.mail-archive.com/u-boot@lists.denx.de/msg217417.html

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 5d9716f..d4a1a5e 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -420,11 +420,11 @@ static int fdt_add_bignum(void *blob, int noffset, const char *prop_name,
 		BN_rshift(num, num, 32); /*  N = N/B */
 	}
 
+	/* We try signing with successively increasing size values, so this
+	 * might fail several times */
 	ret = fdt_setprop(blob, noffset, prop_name, buf, size);
-	if (ret) {
-		fprintf(stderr, "Failed to write public key to FIT\n");
-		return -ENOSPC;
-	}
+	if (ret)
+		return -FDT_ERR_NOSPACE;
 	free(buf);
 	BN_free(tmp);
 	BN_free(big2);
@@ -508,7 +508,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest)
 		ret = fdt_setprop_string(keydest, node, FIT_ALGO_PROP,
 					 info->algo->name);
 	}
-	if (info->require_keys) {
+	if (!ret && info->require_keys) {
 		ret = fdt_setprop_string(keydest, node, "required",
 					 info->require_keys);
 	}
-- 
cgit v0.10.2


From 3cc1f380e518999e68fa64d200d19063f31cb023 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Tue, 19 Jul 2016 14:56:14 +0530
Subject: spl: fit: Fix the number of bytes read in raw mode

In raw mode a full sector is to be read even if image covers part of
a sector. Number of sectors are calculated as ROUND_UP(size)/sec_size by FIT
framework. This calculation assumes that image is at the 0th offset of a sector,
which is not true always in FIT case. So, include the image offset while
calculating number of sectors.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 069e94d..be86072 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -115,8 +115,10 @@ static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
 static int get_aligned_image_size(struct spl_load_info *info, int data_size,
 				  int offset)
 {
+	data_size = data_size + get_aligned_image_overhead(info, offset);
+
 	if (info->filename)
-		return data_size + get_aligned_image_overhead(info, offset);
+		return data_size;
 
 	return (data_size + info->bl_len - 1) / info->bl_len;
 }
-- 
cgit v0.10.2


From 90211f772b674d463f6622fb9982329cf4d6ec37 Mon Sep 17 00:00:00 2001
From: yeongjun Kim <iam.yeongjunkim@gmail.com>
Date: Wed, 20 Jul 2016 22:56:12 +0900
Subject: fixing typo error in README file. CPU15 -> CP15

It looks typo error.
Not CPU15, CP15(CoProcessor15)

Signed-off-by: yeongjun Kim <iam.yeongjunkim@gmail.com>

diff --git a/README b/README
index 9ecac55..ecbd07f 100644
--- a/README
+++ b/README
@@ -4811,7 +4811,7 @@ Low Level (hardware related) configuration options:
 
 - CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 		[ARM926EJ-S only] This allows just the call to lowlevel_init()
-		to be skipped. The normal CPU15 init (such as enabling the
+		to be skipped. The normal CP15 init (such as enabling the
 		instruction cache) is still performed.
 
 - CONFIG_SPL_BUILD
-- 
cgit v0.10.2


From 8b76d23ebdc915faf155aafcb2a221b4923ba18a Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Wed, 20 Jul 2016 13:55:58 -0500
Subject: arm: am4x: fix build dependency for secure devices

Commit e29878f introduces an undesired dependency on CONFIG_SPL_LOAD_FIT
when building U-Boot for AM43xx high-security (HS) devices that causes the
build to break when that option is not active. Fix this issue by only
building the u-boot_HS.img target when building U-Boot into an actual
FIT image.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index ab94708..d4eb21c 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -26,7 +26,7 @@ endif
 else
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
-ALL-y	+= u-boot_HS.img
+ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
 endif
 ALL-y	+= u-boot.img
 endif
-- 
cgit v0.10.2


From 38d592fc33803892298df2d7c60aaab52a55d8fa Mon Sep 17 00:00:00 2001
From: Andreas Dannenberg <dannenberg@ti.com>
Date: Wed, 20 Jul 2016 13:55:59 -0500
Subject: arm: omap5: fix build dependency for secure devices

Commit 17c2987 introduces an undesired dependency on CONFIG_SPL_LOAD_FIT
when building U-Boot for AM57xx and DRA7xx high-security (HS) devices that
causes the build to break when that option is not active. Fix this issue
by only building the u-boot_HS.img target when building U-Boot into an
actual FIT image.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
index d245572..286ca86 100644
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -16,7 +16,7 @@ ALL-y	+= MLO
 endif
 else
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ALL-y   += u-boot_HS.img
+ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
 endif
 ALL-y	+= u-boot.img
 endif
-- 
cgit v0.10.2


From 04a4786c7c3907a8e0cf271c02a437858a3ea96d Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 18 Jul 2016 08:49:08 +0200
Subject: test/py: vboot can be run only at Sandbox

Getting this error:
Zynq> sb load hostfs - 100
/home/monstr/data/disk/u-boot/build-zynq_zc706/test.fit
Unknown command 'sb' - try 'help'

because sb command is present only for Sandbox
obj-$(CONFIG_SANDBOX) += host.o

that's why mark this test to be run only at Sandbox

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index 25a7832..14ec85b 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -29,6 +29,7 @@ import pytest
 import sys
 import u_boot_utils as util
 
+@pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('fit_signature')
 def test_vboot(u_boot_console):
     """Test verified boot signing with mkimage and verification with 'bootm'.
-- 
cgit v0.10.2


From fe8dc1fac70ce9a5672923957c116686c0929433 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 6 Jul 2016 19:24:09 +0900
Subject: ARM: dts: uniphier: renumber serial aliases for Gentil/Vodka boards

On these two boards, the serial0 is used for inter-chip connection,
so cannot be used for login console.  The serial2 is used instead
for them, but it is tedious to use because upper level deployment
projects must switch login console per board.

[ Linux commit: 2a4a2aadbaad9dffdb564a2895348f3d8e825416 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index 61f6164..1175703 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -19,13 +19,13 @@
 	};
 
 	chosen {
-		stdout-path = "serial2:115200n8";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-		serial2 = &serial2;
+		serial0 = &serial2;
+		serial1 = &serial0;
+		serial2 = &serial1;
 		i2c0 = &i2c0;
 		i2c2 = &i2c2;
 		i2c4 = &i2c4;
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
index 3d5b300..928a092 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -19,13 +19,13 @@
 	};
 
 	chosen {
-		stdout-path = "serial2:115200n8";
+		stdout-path = "serial0:115200n8";
 	};
 
 	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-		serial2 = &serial2;
+		serial0 = &serial2;
+		serial1 = &serial0;
+		serial2 = &serial1;
 		i2c0 = &i2c0;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
-- 
cgit v0.10.2


From b7c4d25d26ed021f8c167e0f2ef08d6ab5798f32 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Sun, 17 Jul 2016 01:38:21 +0900
Subject: ARM: uniphier: select CONFIG_ARMV8_SPIN_TABLE

This is needed when booting Linux without ARM Trusted Firmware.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index e256eeb..e39ced6 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -12,6 +12,7 @@ config ARCH_UNIPHIER_64BIT
 	select ARM64
 	select SPL_SEPARATE_BSS
 	select ARMV8_MULTIENTRY
+	select ARMV8_SPIN_TABLE
 
 choice
         prompt "UniPhier SoC select"
-- 
cgit v0.10.2


From 72a64348ef937daaca0553e9d8d75b5774555e57 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 19 Jul 2016 11:36:53 +0900
Subject: ARM: uniphier: fix doubled tftpboot commands

This downloads the same file twice for nothing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 4ebaf84..169c197 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -226,7 +226,6 @@
 		"run boot_common\0" \
 	"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
 		"tftpboot $fdt_addr_r $fdt_file &&" \
-		"tftpboot $fdt_addr_r $fdt_file &&" \
 		"setenv ramdisk_addr_r - &&" \
 		"run boot_common\0"
 #endif
-- 
cgit v0.10.2


From 4e3d84066e09c9ab6cee2102db7a2c51090962a4 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 19 Jul 2016 21:56:13 +0900
Subject: ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()

This does not have much impact on behavior, but makes code look more
more like Linux.  The use of devm_ioremap() often helps to delete
.remove callbacks entirely.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
index 607f96a..f18595d 100644
--- a/arch/arm/mach-uniphier/arm64/arm-cci500.c
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -1,13 +1,12 @@
 /*
  * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
  *
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -28,13 +27,13 @@ void cci500_init(unsigned int nr_slaves)
 		void __iomem *base;
 		u32 tmp;
 
-		base = map_sysmem(slave_base, SZ_4K);
+		base = ioremap(slave_base, SZ_4K);
 
 		tmp = readl(base);
 		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
 		writel(tmp, base);
 
-		unmap_sysmem(base);
+		iounmap(base);
 
 		slave_base += CCI500_SLAVE_OFFSET;
 	}
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 5971ad2..4f08963 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
 
@@ -18,11 +17,11 @@ void uniphier_smp_kick_all_cpus(void)
 {
 	void __iomem *rom_boot_rsv0;
 
-	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
+	rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
 
 	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
 
-	unmap_sysmem(rom_boot_rsv0);
+	iounmap(rom_boot_rsv0);
 
 	uniphier_smp_setup();
 
diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c
index 4beab9d..c10903a 100644
--- a/arch/arm/mach-uniphier/arm64/timer.c
+++ b/arch/arm/mach-uniphier/arm64/timer.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -21,7 +20,7 @@ int timer_init(void)
 	void __iomem *base;
 	u32 tmp;
 
-	base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
+	base = ioremap(CNT_CONTROL_BASE, SZ_4K);
 
 	/*
 	 * Note:
@@ -32,7 +31,7 @@ int timer_init(void)
 	tmp |= CNTCR_EN;
 	writel(tmp, base + CNTCR);
 
-	unmap_sysmem(base);
+	iounmap(base);
 
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
index 7a9f76c..0a5a73d 100644
--- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014      Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <mapmem.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
 
@@ -51,7 +52,7 @@ static void dump_loop(unsigned long *base,
 	int p, dx;
 
 	for (p = 0; *base; base++, p++) {
-		phy = map_sysmem(*base, SZ_4K);
+		phy = ioremap(*base, SZ_4K);
 
 		for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
 			printf("PHY%dDX%d:", p, dx);
@@ -59,7 +60,7 @@ static void dump_loop(unsigned long *base,
 			printf("\n");
 		}
 
-		unmap_sysmem(phy);
+		iounmap(phy);
 	}
 }
 
@@ -172,7 +173,7 @@ static void reg_dump(unsigned long *base)
 	printf("\n--- DDR PHY registers ---\n");
 
 	for (p = 0; *base; base++, p++) {
-		phy = map_sysmem(*base, SZ_4K);
+		phy = ioremap(*base, SZ_4K);
 
 		printf("== PHY%d (base: %p) ==\n", p, phy);
 		printf(" No: Name      : Address  : Data\n");
@@ -206,7 +207,7 @@ static void reg_dump(unsigned long *base)
 		REG_DUMP(dx[1].gcr);
 		REG_DUMP(dx[1].gtr);
 
-		unmap_sysmem(phy);
+		iounmap(phy);
 	}
 }
 
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 2f5d4d8..a91924e 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -1,11 +1,11 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -137,7 +137,7 @@ int uniphier_clk_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->base = map_sysmem(addr, SZ_4K);
+	priv->base = devm_ioremap(dev, addr, SZ_4K);
 	if (!priv->base)
 		return -ENOMEM;
 
@@ -145,12 +145,3 @@ int uniphier_clk_probe(struct udevice *dev)
 
 	return 0;
 }
-
-int uniphier_clk_remove(struct udevice *dev)
-{
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
-
-	unmap_sysmem(priv->base);
-
-	return 0;
-}
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 2dd3fc0..2eea5eb 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -179,7 +180,6 @@ U_BOOT_DRIVER(uniphier_mio_clk) = {
 	.id = UCLASS_CLK,
 	.of_match = uniphier_mio_clk_match,
 	.probe = uniphier_clk_probe,
-	.remove = uniphier_clk_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
 	.ops = &uniphier_clk_ops,
 };
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 560b3f8..18aa888 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -52,6 +53,5 @@ struct uniphier_clk_priv {
 
 extern const struct clk_ops uniphier_clk_ops;
 int uniphier_clk_probe(struct udevice *dev);
-int uniphier_clk_remove(struct udevice *dev);
 
 #endif /* __CLK_UNIPHIER_H__ */
diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c
index bde51ea..afb27a3 100644
--- a/drivers/gpio/gpio-uniphier.c
+++ b/drivers/gpio/gpio-uniphier.c
@@ -1,12 +1,12 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <dm/device.h>
-#include <mapmem.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -99,7 +99,7 @@ static int uniphier_gpio_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->base = map_sysmem(addr, SZ_8);
+	priv->base = devm_ioremap(dev, addr, SZ_8);
 	if (!priv->base)
 		return -ENOMEM;
 
@@ -119,15 +119,6 @@ static int uniphier_gpio_probe(struct udevice *dev)
 	return 0;
 }
 
-static int uniphier_gpio_remove(struct udevice *dev)
-{
-	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
-
-	unmap_sysmem(priv->base);
-
-	return 0;
-}
-
 /* .data = the number of GPIO banks */
 static const struct udevice_id uniphier_gpio_match[] = {
 	{ .compatible = "socionext,uniphier-gpio" },
@@ -139,7 +130,6 @@ U_BOOT_DRIVER(uniphier_gpio) = {
 	.id	= UCLASS_GPIO,
 	.of_match = uniphier_gpio_match,
 	.probe	= uniphier_gpio_probe,
-	.remove	= uniphier_gpio_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
 	.ops	= &uniphier_gpio_ops,
 };
diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index aebdcfc..a56e058 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014      Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -13,7 +15,6 @@
 #include <dm/root.h>
 #include <i2c.h>
 #include <fdtdec.h>
-#include <mapmem.h>
 
 struct uniphier_fi2c_regs {
 	u32 cr;				/* control register */
@@ -118,7 +119,7 @@ static int uniphier_fi2c_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->regs = map_sysmem(addr, SZ_128);
+	priv->regs = devm_ioremap(dev, addr, SZ_128);
 	if (!priv->regs)
 		return -ENOMEM;
 
@@ -134,15 +135,6 @@ static int uniphier_fi2c_probe(struct udevice *dev)
 	return 0;
 }
 
-static int uniphier_fi2c_remove(struct udevice *dev)
-{
-	struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
-
-	unmap_sysmem(priv->regs);
-
-	return 0;
-}
-
 static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
 			bool *stop)
 {
@@ -359,7 +351,6 @@ U_BOOT_DRIVER(uniphier_fi2c) = {
 	.id = UCLASS_I2C,
 	.of_match = uniphier_fi2c_of_match,
 	.probe = uniphier_fi2c_probe,
-	.remove = uniphier_fi2c_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
 	.ops = &uniphier_fi2c_ops,
 };
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
index f8221da..39a3ebd 100644
--- a/drivers/i2c/i2c-uniphier.c
+++ b/drivers/i2c/i2c-uniphier.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014      Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -13,7 +15,6 @@
 #include <dm/root.h>
 #include <i2c.h>
 #include <fdtdec.h>
-#include <mapmem.h>
 
 struct uniphier_i2c_regs {
 	u32 dtrm;			/* data transmission */
@@ -53,7 +54,7 @@ static int uniphier_i2c_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->regs = map_sysmem(addr, SZ_64);
+	priv->regs = devm_ioremap(dev, addr, SZ_64);
 	if (!priv->regs)
 		return -ENOMEM;
 
@@ -65,15 +66,6 @@ static int uniphier_i2c_probe(struct udevice *dev)
 	return 0;
 }
 
-static int uniphier_i2c_remove(struct udevice *dev)
-{
-	struct uniphier_i2c_dev *priv = dev_get_priv(dev);
-
-	unmap_sysmem(priv->regs);
-
-	return 0;
-}
-
 static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm)
 {
 	writel(dtrm, &dev->regs->dtrm);
@@ -220,7 +212,6 @@ U_BOOT_DRIVER(uniphier_i2c) = {
 	.id = UCLASS_I2C,
 	.of_match = uniphier_i2c_of_match,
 	.probe = uniphier_i2c_probe,
-	.remove = uniphier_i2c_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev),
 	.ops = &uniphier_i2c_ops,
 };
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 152e987..02df809 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,7 +8,6 @@
 #include <common.h>
 #include <clk.h>
 #include <fdtdec.h>
-#include <mapmem.h>
 #include <mmc.h>
 #include <dm/device.h>
 #include <linux/compat.h>
@@ -660,7 +660,7 @@ int uniphier_sd_probe(struct udevice *dev)
 	if (base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->regbase = map_sysmem(base, SZ_2K);
+	priv->regbase = devm_ioremap(dev, base, SZ_2K);
 	if (!priv->regbase)
 		return -ENOMEM;
 
@@ -735,7 +735,6 @@ int uniphier_sd_remove(struct udevice *dev)
 {
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 
-	unmap_sysmem(priv->regbase);
 	mmc_destroy(priv->mmc);
 
 	return 0;
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 225a05c..3f891f1 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
-#include <mapmem.h>
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/sizes.h>
@@ -188,7 +187,7 @@ int uniphier_pinctrl_probe(struct udevice *dev,
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->base = map_sysmem(addr, SZ_4K);
+	priv->base = devm_ioremap(dev, addr, SZ_4K);
 	if (!priv->base)
 		return -ENOMEM;
 
@@ -196,12 +195,3 @@ int uniphier_pinctrl_probe(struct udevice *dev,
 
 	return 0;
 }
-
-int uniphier_pinctrl_remove(struct udevice *dev)
-{
-	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
-
-	unmap_sysmem(priv->base);
-
-	return 0;
-}
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index e95870f..e42602b 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -101,7 +101,6 @@ U_BOOT_DRIVER(uniphier_ld11_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_ld11_pinctrl_match),
 	.probe = uniphier_ld11_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index e903196..d6ae512 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -115,7 +115,6 @@ U_BOOT_DRIVER(uniphier_ld20_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_ld20_pinctrl_match),
 	.probe = uniphier_ld20_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index dbb9499..955858a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -135,7 +136,6 @@ U_BOOT_DRIVER(uniphier_ld4_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_ld4_pinctrl_match),
 	.probe = uniphier_ld4_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 8b40801..5f9407e 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -135,7 +136,6 @@ U_BOOT_DRIVER(uniphier_ld6b_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_ld6b_pinctrl_match),
 	.probe = uniphier_ld6b_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index dace726..6f349dc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -143,7 +144,6 @@ U_BOOT_DRIVER(uniphier_pro4_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_pro4_pinctrl_match),
 	.probe = uniphier_pro4_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 50b41cc..268cdea 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -134,7 +135,6 @@ U_BOOT_DRIVER(uniphier_pro5_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_pro5_pinctrl_match),
 	.probe = uniphier_pro5_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index 9223eeb..b534274 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -147,7 +148,6 @@ U_BOOT_DRIVER(uniphier_pxs2_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_pxs2_pinctrl_match),
 	.probe = uniphier_pxs2_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index cee0eb1..a85e055 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -143,7 +144,6 @@ U_BOOT_DRIVER(uniphier_sld8_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(uniphier_sld8_pinctrl_match),
 	.probe = uniphier_sld8_pinctrl_probe,
-	.remove = uniphier_pinctrl_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
 	.ops = &uniphier_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 4bb8932..4de5b03 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -119,6 +120,4 @@ extern const struct pinctrl_ops uniphier_pinctrl_ops;
 int uniphier_pinctrl_probe(struct udevice *dev,
 			   struct uniphier_pinctrl_socdata *socdata);
 
-int uniphier_pinctrl_remove(struct udevice *dev);
-
 #endif /* __PINCTRL_UNIPHIER_H__ */
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 525f0a4..ab607b7 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,7 +11,6 @@
 #include <linux/sizes.h>
 #include <asm/errno.h>
 #include <dm/device.h>
-#include <mapmem.h>
 #include <serial.h>
 #include <fdtdec.h>
 
@@ -98,7 +99,7 @@ static int uniphier_serial_probe(struct udevice *dev)
 	if (base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	port = map_sysmem(base, SZ_64);
+	port = devm_ioremap(dev, base, SZ_64);
 	if (!port)
 		return -ENOMEM;
 
@@ -115,13 +116,6 @@ static int uniphier_serial_probe(struct udevice *dev)
 	return 0;
 }
 
-static int uniphier_serial_remove(struct udevice *dev)
-{
-	unmap_sysmem(uniphier_serial_port(dev));
-
-	return 0;
-}
-
 static const struct udevice_id uniphier_uart_of_match[] = {
 	{ .compatible = "socionext,uniphier-uart" },
 	{ /* sentinel */ }
@@ -139,7 +133,6 @@ U_BOOT_DRIVER(uniphier_serial) = {
 	.id = UCLASS_SERIAL,
 	.of_match = uniphier_uart_of_match,
 	.probe = uniphier_serial_probe,
-	.remove = uniphier_serial_remove,
 	.priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data),
 	.ops = &uniphier_serial_ops,
 };
-- 
cgit v0.10.2


From ebab100a988e62a27ccde0372487daeeb8cb3050 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 22 Jul 2016 13:38:30 +0900
Subject: ARM: uniphier: clear notification flag before L2 operation

Clear the flag immediately before cache operation to not depend on
the previous state.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm32/cache_uniphier.c b/arch/arm/mach-uniphier/arm32/cache_uniphier.c
index 4398114..3d984a7 100644
--- a/arch/arm/mach-uniphier/arm32/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/arm32/cache_uniphier.c
@@ -19,6 +19,9 @@ static void uniphier_cache_sync(void)
 
 static void uniphier_cache_maint_all(u32 operation)
 {
+	/* clear the complete notification flag */
+	writel(SSCOLPQS_EF, SSCOLPQS);
+
 	/* try until the command is successfully set */
 	do {
 		writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
@@ -28,9 +31,6 @@ static void uniphier_cache_maint_all(u32 operation)
 	while (readl(SSCOLPQS) != SSCOLPQS_EF)
 		;
 
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-
 	uniphier_cache_sync();
 }
 
@@ -46,6 +46,9 @@ void v7_outer_cache_inval_all(void)
 
 static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
 {
+	/* clear the complete notification flag */
+	writel(SSCOLPQS_EF, SSCOLPQS);
+
 	/* try until the command is successfully set */
 	do {
 		writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
@@ -57,9 +60,6 @@ static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
 	/* wait until the operation is completed */
 	while (readl(SSCOLPQS) != SSCOLPQS_EF)
 		;
-
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
 }
 
 static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
-- 
cgit v0.10.2


From 4bab70a77d062582db89946b3e3a75f6e27a92ee Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 22 Jul 2016 13:38:31 +0900
Subject: ARM: uniphier: rename outer-cache register macros

Sync register macros with Linux code.  This will be helpful to
develop the counterpart of Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile
index 376c06b..5074ebd 100644
--- a/arch/arm/mach-uniphier/arm32/Makefile
+++ b/arch/arm/mach-uniphier/arm32/Makefile
@@ -7,7 +7,7 @@ obj-y += lowlevel_init.o
 obj-$(CONFIG_DEBUG_LL) += debug_ll.o
 else
 obj-y += late_lowlevel_init.o
-obj-y += cache_uniphier.o
+obj-y += cache-uniphier.o
 endif
 
 obj-y += timer.o
diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
new file mode 100644
index 0000000..76fe5eb
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <asm/armv7.h>
+
+#include "ssc-regs.h"
+
+#ifdef CONFIG_UNIPHIER_L2CACHE_ON
+static void uniphier_cache_sync(void)
+{
+	/* drain internal buffers */
+	writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
+	/* need a read back to confirm */
+	readl(UNIPHIER_SSCOPE);
+}
+
+static void uniphier_cache_maint_all(u32 operation)
+{
+	/* clear the complete notification flag */
+	writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
+
+	/* try until the command is successfully set */
+	do {
+		writel(UNIPHIER_SSCOQM_S_ALL | UNIPHIER_SSCOQM_CE | operation,
+		       UNIPHIER_SSCOQM);
+	} while (readl(UNIPHIER_SSCOPPQSEF) &
+		 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
+
+	/* wait until the operation is completed */
+	while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
+		;
+
+	uniphier_cache_sync();
+}
+
+void v7_outer_cache_flush_all(void)
+{
+	uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
+}
+
+void v7_outer_cache_inval_all(void)
+{
+	uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
+}
+
+static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
+{
+	/* clear the complete notification flag */
+	writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
+
+	/* try until the command is successfully set */
+	do {
+		writel(UNIPHIER_SSCOQM_S_RANGE | UNIPHIER_SSCOQM_CE | operation,
+		       UNIPHIER_SSCOQM);
+		writel(start, UNIPHIER_SSCOQAD);
+		writel(size, UNIPHIER_SSCOQSZ);
+
+	} while (readl(UNIPHIER_SSCOPPQSEF) &
+		 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
+
+	/* wait until the operation is completed */
+	while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
+		;
+}
+
+static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
+{
+	u32 size;
+
+	/*
+	 * If start address is not aligned to cache-line,
+	 * do cache operation for the first cache-line
+	 */
+	start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
+
+	size = end - start;
+
+	if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
+		/* this means cache operation for all range */
+		uniphier_cache_maint_all(operation);
+		return;
+	}
+
+	/*
+	 * If end address is not aligned to cache-line,
+	 * do cache operation for the last cache-line
+	 */
+	size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
+
+	while (size) {
+		u32 chunk_size = size > UNIPHIER_SSC_RANGE_OP_MAX_SIZE ?
+					UNIPHIER_SSC_RANGE_OP_MAX_SIZE : size;
+		__uniphier_cache_maint_range(start, chunk_size, operation);
+
+		start += chunk_size;
+		size -= chunk_size;
+	}
+
+	uniphier_cache_sync();
+}
+
+void v7_outer_cache_flush_range(u32 start, u32 end)
+{
+	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH);
+}
+
+void v7_outer_cache_inval_range(u32 start, u32 end)
+{
+	if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
+		start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
+		__uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE,
+					     UNIPHIER_SSCOQM_CM_FLUSH);
+		start += UNIPHIER_SSC_LINE_SIZE;
+	}
+
+	if (start >= end) {
+		uniphier_cache_sync();
+		return;
+	}
+
+	if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
+		end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
+		__uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE,
+					     UNIPHIER_SSCOQM_CM_FLUSH);
+	}
+
+	if (start >= end) {
+		uniphier_cache_sync();
+		return;
+	}
+
+	uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV);
+}
+
+void v7_outer_cache_enable(void)
+{
+	u32 tmp;
+
+	writel(U32_MAX, UNIPHIER_SSCLPDAWCR);	/* activate all ways */
+	tmp = readl(UNIPHIER_SSCC);
+	tmp |= UNIPHIER_SSCC_ON;
+	writel(tmp, UNIPHIER_SSCC);
+}
+#endif
+
+void v7_outer_cache_disable(void)
+{
+	u32 tmp;
+
+	tmp = readl(UNIPHIER_SSCC);
+	tmp &= ~UNIPHIER_SSCC_ON;
+	writel(tmp, UNIPHIER_SSCC);
+}
+
+void enable_caches(void)
+{
+	dcache_enable();
+}
diff --git a/arch/arm/mach-uniphier/arm32/cache_uniphier.c b/arch/arm/mach-uniphier/arm32/cache_uniphier.c
deleted file mode 100644
index 3d984a7..0000000
--- a/arch/arm/mach-uniphier/arm32/cache_uniphier.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <asm/armv7.h>
-
-#include "ssc-regs.h"
-
-#ifdef CONFIG_UNIPHIER_L2CACHE_ON
-static void uniphier_cache_sync(void)
-{
-	writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
-	readl(SSCOPE); /* need a read back to confirm */
-}
-
-static void uniphier_cache_maint_all(u32 operation)
-{
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-
-	/* try until the command is successfully set */
-	do {
-		writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
-	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
-	/* wait until the operation is completed */
-	while (readl(SSCOLPQS) != SSCOLPQS_EF)
-		;
-
-	uniphier_cache_sync();
-}
-
-void v7_outer_cache_flush_all(void)
-{
-	uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_all(void)
-{
-	uniphier_cache_maint_all(SSCOQM_CM_INV);
-}
-
-static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
-{
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-
-	/* try until the command is successfully set */
-	do {
-		writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
-		writel(start, SSCOQAD);
-		writel(size, SSCOQSZ);
-
-	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
-	/* wait until the operation is completed */
-	while (readl(SSCOLPQS) != SSCOLPQS_EF)
-		;
-}
-
-static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
-{
-	u32 size;
-
-	/*
-	 * If start address is not aligned to cache-line,
-	 * do cache operation for the first cache-line
-	 */
-	start = start & ~(SSC_LINE_SIZE - 1);
-
-	size = end - start;
-
-	if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) {
-		/* this means cache operation for all range */
-		uniphier_cache_maint_all(operation);
-		return;
-	}
-
-	/*
-	 * If end address is not aligned to cache-line,
-	 * do cache operation for the last cache-line
-	 */
-	size = ALIGN(size, SSC_LINE_SIZE);
-
-	while (size) {
-		u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
-						SSC_RANGE_OP_MAX_SIZE : size;
-		__uniphier_cache_maint_range(start, chunk_size, operation);
-
-		start += chunk_size;
-		size -= chunk_size;
-	}
-
-	uniphier_cache_sync();
-}
-
-void v7_outer_cache_flush_range(u32 start, u32 end)
-{
-	uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_range(u32 start, u32 end)
-{
-	if (start & (SSC_LINE_SIZE - 1)) {
-		start &= ~(SSC_LINE_SIZE - 1);
-		__uniphier_cache_maint_range(start, SSC_LINE_SIZE,
-					     SSCOQM_CM_WB_INV);
-		start += SSC_LINE_SIZE;
-	}
-
-	if (start >= end) {
-		uniphier_cache_sync();
-		return;
-	}
-
-	if (end & (SSC_LINE_SIZE - 1)) {
-		end &= ~(SSC_LINE_SIZE - 1);
-		__uniphier_cache_maint_range(end, SSC_LINE_SIZE,
-					     SSCOQM_CM_WB_INV);
-	}
-
-	if (start >= end) {
-		uniphier_cache_sync();
-		return;
-	}
-
-	uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
-}
-
-void v7_outer_cache_enable(void)
-{
-	u32 tmp;
-
-	writel(U32_MAX, SSCLPDAWCR);	/* activate all ways */
-	tmp = readl(SSCC);
-	tmp |= SSCC_ON;
-	writel(tmp, SSCC);
-}
-#endif
-
-void v7_outer_cache_disable(void)
-{
-	u32 tmp;
-	tmp = readl(SSCC);
-	tmp &= ~SSCC_ON;
-	writel(tmp, SSCC);
-}
-
-void enable_caches(void)
-{
-	dcache_enable();
-}
diff --git a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
index cce91df..001d732 100644
--- a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S
@@ -10,9 +10,9 @@
 #include "ssc-regs.h"
 
 ENTRY(lowlevel_init)
-	ldr	r1, = SSCC
+	ldr	r1, = UNIPHIER_SSCC
 	ldr	r0, [r1]
-	bic	r0, r0, #SSCC_ON	@ L2 disable
+	bic	r0, r0, #UNIPHIER_SSCC_ON	@ L2 disable
 	str	r0, [r1]
 	mov	pc, lr
 ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index cc34116..8e32b35 100644
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -94,26 +96,26 @@ ENTRY(setup_init_ram)
 	 */
 0:
 	/*
-	 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
+	 * set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order
 	 */
 	ldr	r0, = 0x00408006	@ touch to zero with address range
-	ldr	r1, = SSCOQM
+	ldr	r1, = UNIPHIER_SSCOQM
 	str	r0, [r1]
 	ldr	r0, = BOOT_RAM_BASE
-	ldr	r1, = SSCOQAD
+	ldr	r1, = UNIPHIER_SSCOQAD
 	str	r0, [r1]
 	ldr	r0, = BOOT_RAM_SIZE
-	ldr	r1, = SSCOQSZ
+	ldr	r1, = UNIPHIER_SSCOQSZ
 	str	r0, [r1]
 	ldr	r0, = BOOT_WAY_BITS
-	ldr	r1, = SSCOQWN
+	ldr	r1, = UNIPHIER_SSCOQWN
 	str	r0, [r1]
-	ldr	r1, = SSCOPPQSEF
+	ldr	r1, = UNIPHIER_SSCOPPQSEF
 	ldr	r0, [r1]
 	cmp	r0, #0			@ check if the command is successfully set
 	bne	0b			@ try again if an error occurs
 
-	ldr	r1, = SSCOLPQS
+	ldr	r1, = UNIPHIER_SSCOLPQS
 1:
 	ldr	r0, [r1]
 	cmp	r0, #0x4
diff --git a/arch/arm/mach-uniphier/arm32/ssc-regs.h b/arch/arm/mach-uniphier/arm32/ssc-regs.h
index 02fca3b..8f423e9 100644
--- a/arch/arm/mach-uniphier/arm32/ssc-regs.h
+++ b/arch/arm/mach-uniphier/arm32/ssc-regs.h
@@ -2,6 +2,7 @@
  * UniPhier System Cache (L2 Cache) registers
  *
  * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2016      Socionext Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,57 +10,59 @@
 #ifndef ARCH_SSC_REGS_H
 #define ARCH_SSC_REGS_H
 
-#define SSCC			0x500c0000
-#define SSCC_BST		(0x1 << 20)
-#define SSCC_ACT		(0x1 << 19)
-#define SSCC_WTG		(0x1 << 18)
-#define SSCC_PRD		(0x1 << 17)
-#define SSCC_WBWA		(0x1 << 16)
-#define SSCC_EX			(0x1 << 13)
-#define SSCC_ON			(0x1 <<  0)
+/* control registers */
+#define UNIPHIER_SSCC		0x500c0000	/* Control Register */
+#define    UNIPHIER_SSCC_BST			(0x1 << 20)	/* UCWG burst read */
+#define    UNIPHIER_SSCC_ACT			(0x1 << 19)	/* Inst-Data separate */
+#define    UNIPHIER_SSCC_WTG			(0x1 << 18)	/* WT gathering on */
+#define    UNIPHIER_SSCC_PRD			(0x1 << 17)	/* enable pre-fetch */
+#define    UNIPHIER_SSCC_ON			(0x1 <<  0)	/* enable cache */
+#define UNIPHIER_SSCLPDAWCR	0x500c0030	/* Unified/Data Active Way Control */
+#define UNIPHIER_SSCLPIAWCR	0x500c0034	/* Instruction Active Way Control */
 
-#define SSCLPDAWCR		0x500c0030
+/* revision registers */
+#define UNIPHIER_SSCID		0x503c0100	/* ID Register */
 
-#define SSCOPE			0x506c0244
-#define SSCOPE_CM_SYNC		0x00000008
+/* operation registers */
+#define UNIPHIER_SSCOPE		0x506c0244	/* Cache Operation Primitive Entry */
+#define    UNIPHIER_SSCOPE_CM_INV		0x0	/* invalidate */
+#define    UNIPHIER_SSCOPE_CM_CLEAN		0x1	/* clean */
+#define    UNIPHIER_SSCOPE_CM_FLUSH		0x2	/* flush */
+#define    UNIPHIER_SSCOPE_CM_SYNC		0x8	/* sync (drain bufs) */
+#define    UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH	0x9	/* flush p-fetch buf */
+#define UNIPHIER_SSCOQM		0x506c0248
+#define    UNIPHIER_SSCOQM_TID_MASK		(0x3 << 21)
+#define    UNIPHIER_SSCOQM_TID_LRU_DATA		(0x0 << 21)
+#define    UNIPHIER_SSCOQM_TID_LRU_INST		(0x1 << 21)
+#define    UNIPHIER_SSCOQM_TID_WAY		(0x2 << 21)
+#define    UNIPHIER_SSCOQM_S_MASK		(0x3 << 17)
+#define    UNIPHIER_SSCOQM_S_RANGE		(0x0 << 17)
+#define    UNIPHIER_SSCOQM_S_ALL		(0x1 << 17)
+#define    UNIPHIER_SSCOQM_S_WAY		(0x2 << 17)
+#define    UNIPHIER_SSCOQM_CE			(0x1 << 15)	/* notify completion */
+#define    UNIPHIER_SSCOQM_CW			(0x1 << 14)
+#define    UNIPHIER_SSCOQM_CM_MASK		(0x7)
+#define    UNIPHIER_SSCOQM_CM_INV		0x0	/* invalidate */
+#define    UNIPHIER_SSCOQM_CM_CLEAN		0x1	/* clean */
+#define    UNIPHIER_SSCOQM_CM_FLUSH		0x2	/* flush */
+#define    UNIPHIER_SSCOQM_CM_PREFETCH		0x3	/* prefetch to cache */
+#define    UNIPHIER_SSCOQM_CM_PREFETCH_BUF	0x4	/* prefetch to pf-buf */
+#define    UNIPHIER_SSCOQM_CM_TOUCH		0x5	/* touch */
+#define    UNIPHIER_SSCOQM_CM_TOUCH_ZERO	0x6	/* touch to zero */
+#define    UNIPHIER_SSCOQM_CM_TOUCH_DIRTY	0x7	/* touch with dirty */
+#define UNIPHIER_SSCOQAD	0x506c024c	/* Cache Operation Queue Address */
+#define UNIPHIER_SSCOQSZ	0x506c0250	/* Cache Operation Queue Size */
+#define UNIPHIER_SSCOQMASK	0x506c0254	/* Cache Operation Queue Address Mask */
+#define UNIPHIER_SSCOQWN	0x506c0258	/* Cache Operation Queue Way Number */
+#define UNIPHIER_SSCOPPQSEF	0x506c025c	/* Cache Operation Queue Set Complete */
+#define    UNIPHIER_SSCOPPQSEF_FE		(0x1 << 1)
+#define    UNIPHIER_SSCOPPQSEF_OE		(0x1 << 0)
+#define UNIPHIER_SSCOLPQS	0x506c0260	/* Cache Operation Queue Status */
+#define    UNIPHIER_SSCOLPQS_EF			(0x1 << 2)
+#define    UNIPHIER_SSCOLPQS_EST		(0x1 << 1)
+#define    UNIPHIER_SSCOLPQS_QST		(0x1 << 0)
 
-#define SSCOQM			0x506c0248
-#define SSCOQM_TID_MASK		(0x3 << 21)
-#define SSCOQM_TID_BY_WAY	(0x2 << 21)
-#define SSCOQM_TID_BY_INST_WAY	(0x1 << 21)
-#define SSCOQM_TID_BY_DATA_WAY	(0x0 << 21)
-#define SSCOQM_S_MASK		(0x3 << 17)
-#define SSCOQM_S_WAY		(0x2 << 17)
-#define SSCOQM_S_ALL		(0x1 << 17)
-#define SSCOQM_S_ADDRESS	(0x0 << 17)
-#define SSCOQM_CE		(0x1 << 15)
-#define SSCOQM_CW		(0x1 << 14)
-#define SSCOQM_CM_MASK		(0x7)
-#define SSCOQM_CM_DIRT_TOUCH	(0x7)
-#define SSCOQM_CM_ZERO_TOUCH	(0x6)
-#define SSCOQM_CM_NORM_TOUCH	(0x5)
-#define SSCOQM_CM_PREF_FETCH	(0x4)
-#define SSCOQM_CM_SSC_FETCH	(0x3)
-#define SSCOQM_CM_WB_INV	(0x2)
-#define SSCOQM_CM_WB		(0x1)
-#define SSCOQM_CM_INV		(0x0)
-
-#define SSCOQAD			0x506c024c
-#define SSCOQSZ			0x506c0250
-#define SSCOQWN			0x506c0258
-
-#define SSCOPPQSEF		0x506c025c
-#define SSCOPPQSEF_FE		(0x1 << 1)
-#define SSCOPPQSEF_OE		(0x1 << 0)
-
-#define SSCOLPQS		0x506c0260
-#define SSCOLPQS_EF		(0x1 << 2)
-#define SSCOLPQS_EST		(0x1 << 1)
-#define SSCOLPQS_QST		(0x1 << 0)
-
-#define SSCOQCE0		0x506c0270
-
-#define SSC_LINE_SIZE		128
-#define SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (SSC_LINE_SIZE))
+#define UNIPHIER_SSC_LINE_SIZE		128
+#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
 
 #endif  /* ARCH_SSC_REGS_H */
-- 
cgit v0.10.2


From a74c28a0f2a6bfdc75d0547b804dc578844e49b1 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 22 Jul 2016 13:38:32 +0900
Subject: ARM: uniphier: introduce flags to uniphier_board_data structure

I need to add more board attributes, so the "flags" member will be
handier than separate boolean ones.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index ed308f3..47e303e 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -38,7 +39,6 @@ static const struct uniphier_board_data uniphier_sld3_data = {
 static const struct uniphier_board_data uniphier_ld4_data = {
 	.dram_freq = 1600,
 	.dram_nr_ch = 2,
-	.dram_ddr3plus = true,
 	.dram_ch[0] = {
 		.base = 0x80000000,
 		.size = 0x10000000,
@@ -49,6 +49,7 @@ static const struct uniphier_board_data uniphier_ld4_data = {
 		.size = 0x10000000,
 		.width = 16,
 	},
+	.flags = UNIPHIER_BD_DDR3PLUS,
 };
 #endif
 
@@ -90,7 +91,6 @@ static const struct uniphier_board_data uniphier_pro4_2g_data = {
 static const struct uniphier_board_data uniphier_sld8_data = {
 	.dram_freq = 1333,
 	.dram_nr_ch = 2,
-	.dram_ddr3plus = true,
 	.dram_ch[0] = {
 		.base = 0x80000000,
 		.size = 0x10000000,
@@ -101,6 +101,7 @@ static const struct uniphier_board_data uniphier_sld8_data = {
 		.size = 0x10000000,
 		.width = 16,
 	},
+	.flags = UNIPHIER_BD_DDR3PLUS,
 };
 #endif
 
diff --git a/arch/arm/mach-uniphier/dram/umc-ld4.c b/arch/arm/mach-uniphier/dram/umc-ld4.c
index fc75864..1ea6193 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld4.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -175,7 +177,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd)
 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 				  bd->dram_ch[ch].size,
-				  bd->dram_ddr3plus, ch);
+				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);
 			return ret;
diff --git a/arch/arm/mach-uniphier/dram/umc-pro4.c b/arch/arm/mach-uniphier/dram/umc-pro4.c
index 853f561..f6c2d7f 100644
--- a/arch/arm/mach-uniphier/dram/umc-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-pro4.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -170,7 +172,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 				  bd->dram_ch[ch].size,
 				  bd->dram_ch[ch].width,
-				  bd->dram_ddr3plus);
+				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS));
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);
 			return ret;
diff --git a/arch/arm/mach-uniphier/dram/umc-sld8.c b/arch/arm/mach-uniphier/dram/umc-sld8.c
index e831766..61b1dc1 100644
--- a/arch/arm/mach-uniphier/dram/umc-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-sld8.c
@@ -1,5 +1,7 @@
 /*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -178,7 +180,7 @@ int uniphier_sld8_umc_init(const struct uniphier_board_data *bd)
 	for (ch = 0; ch < DRAM_CH_NR; ch++) {
 		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
 				  bd->dram_ch[ch].size,
-				  bd->dram_ddr3plus, ch);
+				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch);
 		if (ret) {
 			pr_err("failed to initialize UMC ch%d\n", ch);
 			return ret;
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index cba0bc9..31da605 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -20,8 +21,9 @@ struct uniphier_dram_ch {
 struct uniphier_board_data {
 	unsigned int dram_freq;
 	unsigned int dram_nr_ch;
-	bool dram_ddr3plus;
 	struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
+	unsigned int flags;
+#define UNIPHIER_BD_DDR3PLUS		BIT(2)
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void);
-- 
cgit v0.10.2


From be44a4679feed5a416cdce9b06514473ff82ce95 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 22 Jul 2016 13:38:33 +0900
Subject: ARM: uniphier: add PH1-LD21 board data

This has the same silicon die as PH1-LD20, but includes DRAM chips
in its package.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 47e303e..20093d8 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -203,6 +203,22 @@ static const struct uniphier_board_data uniphier_ld20_data = {
 		.width = 32,
 	},
 };
+
+static const struct uniphier_board_data uniphier_ld21_data = {
+	.dram_freq = 1866,
+	.dram_nr_ch = 2,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[1] = {
+		.base = 0xc0000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.flags = UNIPHIER_BD_PACKAGE_LD21,
+};
 #endif
 
 struct uniphier_board_id {
@@ -238,6 +254,7 @@ static const struct uniphier_board_id uniphier_boards[] = {
 	{ "socionext,ph1-ld11", &uniphier_ld11_data, },
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	{ "socionext,ph1-ld21", &uniphier_ld21_data, },
 	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
 #endif
 };
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 31da605..db80074 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -24,6 +24,8 @@ struct uniphier_board_data {
 	struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
 	unsigned int flags;
 #define UNIPHIER_BD_DDR3PLUS		BIT(2)
+#define UNIPHIER_BD_PACKAGE_LD21	1
+#define UNIPHIER_BD_PACKAGE_TYPE(f)	((f) & 0x3)
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void);
-- 
cgit v0.10.2


From 29d63a59eaf1c9f3b37e249cda2a97e5e4f183f8 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 22 Jul 2016 20:20:11 +0900
Subject: ARM: uniphier: add clock/reset settings for xHCI of ProXstream2

Deassert resets and enable clock signals of xHCI blocks if the
corresponding CONFIG is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index 76bf856..0d92405 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitops.h>
 #include <linux/io.h>
 
 #include "../init.h"
@@ -32,12 +33,16 @@ void uniphier_pxs2_clk_init(void)
 	tmp |= SC_RSTCTRL2_NRST_USB3B1;
 	writel(tmp, SC_RSTCTRL2);
 	readl(SC_RSTCTRL2); /* dummy read */
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= 0x37;
+	writel(tmp, SC_RSTCTRL6);
 #endif
 
 	/* provide clocks */
 	tmp = readl(SC_CLKCTRL);
 #ifdef CONFIG_USB_XHCI_UNIPHIER
-	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+	tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
 		SC_CLKCTRL_CEN_GIO;
 #endif
 #ifdef CONFIG_UNIPHIER_ETH
diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index a095589..ad58e10 100644
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -1,7 +1,9 @@
 /*
  * UniPhier SC (System Control) block registers
  *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -68,6 +70,10 @@
 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
 
+#define SC_RSTCTRL5			(SC_BASE_ADDR | 0x2010)
+
+#define SC_RSTCTRL6			(SC_BASE_ADDR | 0x2014)
+
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */
-- 
cgit v0.10.2


From 2dc3c483a9f7c8215b4523183dc74e8692253404 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 10:42:18 +0200
Subject: cmd, nand: add an option to disable the verification when writing in
 raw mode

Modern NANDs do not guarantee that data written in raw mode will not
contain bitflips just after writing them. This is fine since the number
of bitflips should be rather low and thus fixable by the ECC engine,
but since we are reading data in raw mode to verify if they match the
input data we cannot prevent failures if some bits are flipped.

The option of using standard mode to verify the data is not acceptable
either, since one of the usage of raw mode is to allow flashing images
that do not respect the standard NAND page layout or the default ECC
config (this is the case on Allwinner platforms, where the ROM code
tests several hardcoded configs, which are not necessarily matching the
NAND characteristics).

Add an extension to the nand write.raw command allowing one to disable
the verification step.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/nand.c b/cmd/nand.c
index ffdeea4..e10349a 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -306,7 +306,7 @@ static void nand_print_and_set_info(int idx)
 }
 
 static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
-		      ulong count, int read)
+		      ulong count, int read, int no_verify)
 {
 	int ret = 0;
 
@@ -324,7 +324,7 @@ static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
 			ret = mtd_read_oob(mtd, off, &ops);
 		} else {
 			ret = mtd_write_oob(mtd, off, &ops);
-			if (!ret)
+			if (!ret && !no_verify)
 				ret = nand_verify_page_oob(mtd, &ops, off);
 		}
 
@@ -546,6 +546,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		ulong pagecount = 1;
 		int read;
 		int raw = 0;
+		int no_verify = 0;
 
 		if (argc < 4)
 			goto usage;
@@ -557,9 +558,12 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		s = strchr(cmd, '.');
 
-		if (s && !strcmp(s, ".raw")) {
+		if (s && !strncmp(s, ".raw", 4)) {
 			raw = 1;
 
+			if (!strcmp(s, ".raw.noverify"))
+				no_verify = 1;
+
 			if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
 					MTD_DEV_TYPE_NAND,
 					nand_info[dev]->size))
@@ -633,7 +637,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			else
 				ret = mtd_write_oob(mtd, off, &ops);
 		} else if (raw) {
-			ret = raw_access(mtd, addr, off, pagecount, read);
+			ret = raw_access(mtd, addr, off, pagecount, read,
+					 no_verify);
 		} else {
 			printf("Unknown nand command suffix '%s'.\n", s);
 			return 1;
@@ -786,7 +791,7 @@ static char nand_help_text[] =
 	"    read/write 'size' bytes starting at offset 'off'\n"
 	"    to/from memory address 'addr', skipping bad blocks.\n"
 	"nand read.raw - addr off|partition [count]\n"
-	"nand write.raw - addr off|partition [count]\n"
+	"nand write.raw[.noverify] - addr off|partition [count]\n"
 	"    Use read.raw/write.raw to avoid ECC and access the flash as-is.\n"
 #ifdef CONFIG_CMD_NAND_TRIMFFS
 	"nand write.trimffs - addr off|partition size\n"
-- 
cgit v0.10.2


From 8df375b445c506f61722e20379ce645ce133e5de Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:21 +0200
Subject: sunxi: Add missing macros to configure the NAND controller clk

We need some macros to manipulate the NAND controller clock.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 0088bb9..d1c5ad0 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -269,6 +269,11 @@ struct sunxi_ccm_reg {
 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
 
+#define CCM_NAND_CTRL_M(x)		((x) - 1)
+#define CCM_NAND_CTRL_N(x)		((x) << 16)
+#define CCM_NAND_CTRL_OSCM24		(0x0 << 24)
+#define CCM_NAND_CTRL_PLL6		(0x1 << 24)
+#define CCM_NAND_CTRL_PLL5		(0x2 << 24)
 #define CCM_NAND_CTRL_ENABLE		(0x1 << 31)
 
 #define CCM_MMC_CTRL_M(x)		((x) - 1)
-- 
cgit v0.10.2


From 42bd19ce6c7bffef402ad6dd639c33686f485d29 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Wed, 15 Jun 2016 21:09:22 +0200
Subject: mtd: nand: add common DT init code

These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.

If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().

The original commit has been slightly reworked to use the fdtdec_xxx()
helpers (instead of the of_xxxx() ones).

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 6897167..4cf4518 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -29,6 +29,9 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <common.h>
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+#include <fdtdec.h>
+#endif
 #include <malloc.h>
 #include <watchdog.h>
 #include <linux/err.h>
@@ -3763,6 +3766,66 @@ ident_done:
 	return type;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+DECLARE_GLOBAL_DATA_PTR;
+
+static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
+{
+	int ret, ecc_mode = -1, ecc_strength, ecc_step;
+	const void *blob = gd->fdt_blob;
+	const char *str;
+
+	ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
+	if (ret == 16)
+		chip->options |= NAND_BUSWIDTH_16;
+
+	if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
+		chip->bbt_options |= NAND_BBT_USE_FLASH;
+
+	str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
+	if (str) {
+		if (!strcmp(str, "none"))
+			ecc_mode = NAND_ECC_NONE;
+		else if (!strcmp(str, "soft"))
+			ecc_mode = NAND_ECC_SOFT;
+		else if (!strcmp(str, "hw"))
+			ecc_mode = NAND_ECC_HW;
+		else if (!strcmp(str, "hw_syndrome"))
+			ecc_mode = NAND_ECC_HW_SYNDROME;
+		else if (!strcmp(str, "hw_oob_first"))
+			ecc_mode = NAND_ECC_HW_OOB_FIRST;
+		else if (!strcmp(str, "soft_bch"))
+			ecc_mode = NAND_ECC_SOFT_BCH;
+	}
+
+
+	ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
+	ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
+
+	if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
+	    (!(ecc_step >= 0) && ecc_strength >= 0)) {
+		pr_err("must set both strength and step size in DT\n");
+		return -EINVAL;
+	}
+
+	if (ecc_mode >= 0)
+		chip->ecc.mode = ecc_mode;
+
+	if (ecc_strength >= 0)
+		chip->ecc.strength = ecc_strength;
+
+	if (ecc_step > 0)
+		chip->ecc.size = ecc_step;
+
+	return 0;
+}
+#else
+static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
+{
+	return 0;
+}
+#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+
 /**
  * nand_scan_ident - [NAND Interface] Scan for the NAND device
  * @mtd: MTD device structure
@@ -3779,6 +3842,13 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
 	int i, nand_maf_id, nand_dev_id;
 	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_flash_dev *type;
+	int ret;
+
+	if (chip->flash_node) {
+		ret = nand_dt_init(mtd, chip, chip->flash_node);
+		if (ret)
+			return ret;
+	}
 
 	/* Set the default functions */
 	nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index b5a02c3..29aae43 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -590,6 +590,7 @@ struct nand_buffers {
  *			flash device
  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
  *			flash device.
+ * @flash_node:		[BOARDSPECIFIC] device node describing this instance
  * @read_byte:		[REPLACEABLE] read one byte from the chip
  * @read_word:		[REPLACEABLE] read one word from the chip
  * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
@@ -689,6 +690,8 @@ struct nand_chip {
 	void __iomem *IO_ADDR_R;
 	void __iomem *IO_ADDR_W;
 
+	int flash_node;
+
 	uint8_t (*read_byte)(struct mtd_info *mtd);
 	u16 (*read_word)(struct mtd_info *mtd);
 	void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
-- 
cgit v0.10.2


From 4ccae81cdadce39e925f3e8c96567fd911568000 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:23 +0200
Subject: mtd: nand: Add the sunxi NAND controller driver

We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.

The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f6e28b0..36cf963 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -136,7 +136,7 @@ int dram_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NAND_SUNXI)
 static void nand_pinmux_setup(void)
 {
 	unsigned int pin;
@@ -173,6 +173,9 @@ void board_nand_init(void)
 {
 	nand_pinmux_setup();
 	nand_clock_setup();
+#ifndef CONFIG_SPL_BUILD
+	sunxi_nand_init();
+#endif
 }
 #endif
 
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8c46a2f..5ce7d6d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -64,12 +64,14 @@ config NAND_PXA3XX
 	  PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
 
 config NAND_SUNXI
-	bool "Support for NAND on Allwinner SoCs in SPL"
+	bool "Support for NAND on Allwinner SoCs"
 	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	select SYS_NAND_SELF_INIT
 	---help---
-	Enable support for NAND. This option allows SPL to read from
-	sunxi NAND using DMA transfers.
+	Enable support for NAND. This option enables the standard and
+	SPL drivers.
+	The SPL driver only supports reading from the NAND using DMA
+	transfers.
 
 config NAND_ARASAN
 	bool "Configure Arasan Nand"
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 837d397..1df9273 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
+obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
new file mode 100644
index 0000000..c4e2cd7
--- /dev/null
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -0,0 +1,1845 @@
+/*
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
+ * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
+ *
+ * Derived from:
+ *	https://github.com/yuq/sunxi-nfc-mtd
+ *	Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
+ *
+ *	https://github.com/hno/Allwinner-Info
+ *	Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
+ *
+ *	Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
+ *	Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <memalign.h>
+#include <nand.h>
+
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/io.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NFC_REG_CTL		0x0000
+#define NFC_REG_ST		0x0004
+#define NFC_REG_INT		0x0008
+#define NFC_REG_TIMING_CTL	0x000C
+#define NFC_REG_TIMING_CFG	0x0010
+#define NFC_REG_ADDR_LOW	0x0014
+#define NFC_REG_ADDR_HIGH	0x0018
+#define NFC_REG_SECTOR_NUM	0x001C
+#define NFC_REG_CNT		0x0020
+#define NFC_REG_CMD		0x0024
+#define NFC_REG_RCMD_SET	0x0028
+#define NFC_REG_WCMD_SET	0x002C
+#define NFC_REG_IO_DATA		0x0030
+#define NFC_REG_ECC_CTL		0x0034
+#define NFC_REG_ECC_ST		0x0038
+#define NFC_REG_DEBUG		0x003C
+#define NFC_REG_ECC_ERR_CNT(x)	((0x0040 + (x)) & ~0x3)
+#define NFC_REG_USER_DATA(x)	(0x0050 + ((x) * 4))
+#define NFC_REG_SPARE_AREA	0x00A0
+#define NFC_REG_PAT_ID		0x00A4
+#define NFC_RAM0_BASE		0x0400
+#define NFC_RAM1_BASE		0x0800
+
+/* define bit use in NFC_CTL */
+#define NFC_EN			BIT(0)
+#define NFC_RESET		BIT(1)
+#define NFC_BUS_WIDTH_MSK	BIT(2)
+#define NFC_BUS_WIDTH_8		(0 << 2)
+#define NFC_BUS_WIDTH_16	(1 << 2)
+#define NFC_RB_SEL_MSK		BIT(3)
+#define NFC_RB_SEL(x)		((x) << 3)
+#define NFC_CE_SEL_MSK		(0x7 << 24)
+#define NFC_CE_SEL(x)		((x) << 24)
+#define NFC_CE_CTL		BIT(6)
+#define NFC_PAGE_SHIFT_MSK	(0xf << 8)
+#define NFC_PAGE_SHIFT(x)	(((x) < 10 ? 0 : (x) - 10) << 8)
+#define NFC_SAM			BIT(12)
+#define NFC_RAM_METHOD		BIT(14)
+#define NFC_DEBUG_CTL		BIT(31)
+
+/* define bit use in NFC_ST */
+#define NFC_RB_B2R		BIT(0)
+#define NFC_CMD_INT_FLAG	BIT(1)
+#define NFC_DMA_INT_FLAG	BIT(2)
+#define NFC_CMD_FIFO_STATUS	BIT(3)
+#define NFC_STA			BIT(4)
+#define NFC_NATCH_INT_FLAG	BIT(5)
+#define NFC_RB_STATE(x)		BIT(x + 8)
+
+/* define bit use in NFC_INT */
+#define NFC_B2R_INT_ENABLE	BIT(0)
+#define NFC_CMD_INT_ENABLE	BIT(1)
+#define NFC_DMA_INT_ENABLE	BIT(2)
+#define NFC_INT_MASK		(NFC_B2R_INT_ENABLE | \
+				 NFC_CMD_INT_ENABLE | \
+				 NFC_DMA_INT_ENABLE)
+
+/* define bit use in NFC_TIMING_CTL */
+#define NFC_TIMING_CTL_EDO	BIT(8)
+
+/* define NFC_TIMING_CFG register layout */
+#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)		\
+	(((tWB) & 0x3) | (((tADL) & 0x3) << 2) |		\
+	(((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |		\
+	(((tCAD) & 0x7) << 8))
+
+/* define bit use in NFC_CMD */
+#define NFC_CMD_LOW_BYTE_MSK	0xff
+#define NFC_CMD_HIGH_BYTE_MSK	(0xff << 8)
+#define NFC_CMD(x)		(x)
+#define NFC_ADR_NUM_MSK		(0x7 << 16)
+#define NFC_ADR_NUM(x)		(((x) - 1) << 16)
+#define NFC_SEND_ADR		BIT(19)
+#define NFC_ACCESS_DIR		BIT(20)
+#define NFC_DATA_TRANS		BIT(21)
+#define NFC_SEND_CMD1		BIT(22)
+#define NFC_WAIT_FLAG		BIT(23)
+#define NFC_SEND_CMD2		BIT(24)
+#define NFC_SEQ			BIT(25)
+#define NFC_DATA_SWAP_METHOD	BIT(26)
+#define NFC_ROW_AUTO_INC	BIT(27)
+#define NFC_SEND_CMD3		BIT(28)
+#define NFC_SEND_CMD4		BIT(29)
+#define NFC_CMD_TYPE_MSK	(0x3 << 30)
+#define NFC_NORMAL_OP		(0 << 30)
+#define NFC_ECC_OP		(1 << 30)
+#define NFC_PAGE_OP		(2 << 30)
+
+/* define bit use in NFC_RCMD_SET */
+#define NFC_READ_CMD_MSK	0xff
+#define NFC_RND_READ_CMD0_MSK	(0xff << 8)
+#define NFC_RND_READ_CMD1_MSK	(0xff << 16)
+
+/* define bit use in NFC_WCMD_SET */
+#define NFC_PROGRAM_CMD_MSK	0xff
+#define NFC_RND_WRITE_CMD_MSK	(0xff << 8)
+#define NFC_READ_CMD0_MSK	(0xff << 16)
+#define NFC_READ_CMD1_MSK	(0xff << 24)
+
+/* define bit use in NFC_ECC_CTL */
+#define NFC_ECC_EN		BIT(0)
+#define NFC_ECC_PIPELINE	BIT(3)
+#define NFC_ECC_EXCEPTION	BIT(4)
+#define NFC_ECC_BLOCK_SIZE_MSK	BIT(5)
+#define NFC_ECC_BLOCK_512	(1 << 5)
+#define NFC_RANDOM_EN		BIT(9)
+#define NFC_RANDOM_DIRECTION	BIT(10)
+#define NFC_ECC_MODE_MSK	(0xf << 12)
+#define NFC_ECC_MODE(x)		((x) << 12)
+#define NFC_RANDOM_SEED_MSK	(0x7fff << 16)
+#define NFC_RANDOM_SEED(x)	((x) << 16)
+
+/* define bit use in NFC_ECC_ST */
+#define NFC_ECC_ERR(x)		BIT(x)
+#define NFC_ECC_PAT_FOUND(x)	BIT(x + 16)
+#define NFC_ECC_ERR_CNT(b, x)	(((x) >> ((b) * 8)) & 0xff)
+
+#define NFC_DEFAULT_TIMEOUT_MS	1000
+
+#define NFC_SRAM_SIZE		1024
+
+#define NFC_MAX_CS		7
+
+/*
+ * Ready/Busy detection type: describes the Ready/Busy detection modes
+ *
+ * @RB_NONE:	no external detection available, rely on STATUS command
+ *		and software timeouts
+ * @RB_NATIVE:	use sunxi NAND controller Ready/Busy support. The Ready/Busy
+ *		pin of the NAND flash chip must be connected to one of the
+ *		native NAND R/B pins (those which can be muxed to the NAND
+ *		Controller)
+ * @RB_GPIO:	use a simple GPIO to handle Ready/Busy status. The Ready/Busy
+ *		pin of the NAND flash chip must be connected to a GPIO capable
+ *		pin.
+ */
+enum sunxi_nand_rb_type {
+	RB_NONE,
+	RB_NATIVE,
+	RB_GPIO,
+};
+
+/*
+ * Ready/Busy structure: stores information related to Ready/Busy detection
+ *
+ * @type:	the Ready/Busy detection mode
+ * @info:	information related to the R/B detection mode. Either a gpio
+ *		id or a native R/B id (those supported by the NAND controller).
+ */
+struct sunxi_nand_rb {
+	enum sunxi_nand_rb_type type;
+	union {
+		struct gpio_desc gpio;
+		int nativeid;
+	} info;
+};
+
+/*
+ * Chip Select structure: stores information related to NAND Chip Select
+ *
+ * @cs:		the NAND CS id used to communicate with a NAND Chip
+ * @rb:		the Ready/Busy description
+ */
+struct sunxi_nand_chip_sel {
+	u8 cs;
+	struct sunxi_nand_rb rb;
+};
+
+/*
+ * sunxi HW ECC infos: stores information related to HW ECC support
+ *
+ * @mode:	the sunxi ECC mode field deduced from ECC requirements
+ * @layout:	the OOB layout depending on the ECC requirements and the
+ *		selected ECC mode
+ */
+struct sunxi_nand_hw_ecc {
+	int mode;
+	struct nand_ecclayout layout;
+};
+
+/*
+ * NAND chip structure: stores NAND chip device related information
+ *
+ * @node:		used to store NAND chips into a list
+ * @nand:		base NAND chip structure
+ * @mtd:		base MTD structure
+ * @clk_rate:		clk_rate required for this NAND chip
+ * @timing_cfg		TIMING_CFG register value for this NAND chip
+ * @selected:		current active CS
+ * @nsels:		number of CS lines required by the NAND chip
+ * @sels:		array of CS lines descriptions
+ */
+struct sunxi_nand_chip {
+	struct list_head node;
+	struct nand_chip nand;
+	unsigned long clk_rate;
+	u32 timing_cfg;
+	u32 timing_ctl;
+	int selected;
+	int addr_cycles;
+	u32 addr[2];
+	int cmd_cycles;
+	u8 cmd[2];
+	int nsels;
+	struct sunxi_nand_chip_sel sels[0];
+};
+
+static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
+{
+	return container_of(nand, struct sunxi_nand_chip, nand);
+}
+
+/*
+ * NAND Controller structure: stores sunxi NAND controller information
+ *
+ * @controller:		base controller structure
+ * @dev:		parent device (used to print error messages)
+ * @regs:		NAND controller registers
+ * @ahb_clk:		NAND Controller AHB clock
+ * @mod_clk:		NAND Controller mod clock
+ * @assigned_cs:	bitmask describing already assigned CS lines
+ * @clk_rate:		NAND controller current clock rate
+ * @chips:		a list containing all the NAND chips attached to
+ *			this NAND controller
+ * @complete:		a completion object used to wait for NAND
+ *			controller events
+ */
+struct sunxi_nfc {
+	struct nand_hw_control controller;
+	struct device *dev;
+	void __iomem *regs;
+	struct clk *ahb_clk;
+	struct clk *mod_clk;
+	unsigned long assigned_cs;
+	unsigned long clk_rate;
+	struct list_head chips;
+};
+
+static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
+{
+	return container_of(ctrl, struct sunxi_nfc, controller);
+}
+
+static void sunxi_nfc_set_clk_rate(unsigned long hz)
+{
+	struct sunxi_ccm_reg *const ccm =
+	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int div_m, div_n;
+
+	div_m = (clock_get_pll6() + hz - 1) / hz;
+	for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
+		if (div_m % 2)
+			div_m++;
+		div_m >>= 1;
+	}
+	if (div_m > 16)
+		div_m = 16;
+
+	/* config mod clock */
+	writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
+	       CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
+	       &ccm->nand0_clk_cfg);
+
+	/* gate on nand clock */
+	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
+#ifdef CONFIG_MACH_SUN9I
+	setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
+#else
+	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
+#endif
+}
+
+static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
+			      unsigned int timeout_ms)
+{
+	unsigned int timeout_ticks;
+	u32 time_start, status;
+	int ret = -ETIMEDOUT;
+
+	if (!timeout_ms)
+		timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
+
+	timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
+
+	time_start = get_timer(0);
+
+	do {
+		status = readl(nfc->regs + NFC_REG_ST);
+		if ((status & flags) == flags) {
+			ret = 0;
+			break;
+		}
+
+		udelay(1);
+	} while (get_timer(time_start) < timeout_ticks);
+
+	writel(status & flags, nfc->regs + NFC_REG_ST);
+
+	return ret;
+}
+
+static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
+{
+	unsigned long timeout = (CONFIG_SYS_HZ *
+				 NFC_DEFAULT_TIMEOUT_MS) / 1000;
+	u32 time_start;
+
+	time_start = get_timer(0);
+	do {
+		if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
+			return 0;
+	} while (get_timer(time_start) < timeout);
+
+	dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
+	return -ETIMEDOUT;
+}
+
+static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
+{
+	unsigned long timeout = (CONFIG_SYS_HZ *
+				 NFC_DEFAULT_TIMEOUT_MS) / 1000;
+	u32 time_start;
+
+	writel(0, nfc->regs + NFC_REG_ECC_CTL);
+	writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
+
+	time_start = get_timer(0);
+	do {
+		if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
+			return 0;
+	} while (get_timer(time_start) < timeout);
+
+	dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
+	return -ETIMEDOUT;
+}
+
+static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+	struct sunxi_nand_rb *rb;
+	unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
+	int ret;
+
+	if (sunxi_nand->selected < 0)
+		return 0;
+
+	rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
+
+	switch (rb->type) {
+	case RB_NATIVE:
+		ret = !!(readl(nfc->regs + NFC_REG_ST) &
+			 NFC_RB_STATE(rb->info.nativeid));
+		if (ret)
+			break;
+
+		sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
+		ret = !!(readl(nfc->regs + NFC_REG_ST) &
+			 NFC_RB_STATE(rb->info.nativeid));
+		break;
+	case RB_GPIO:
+		ret = dm_gpio_get_value(&rb->info.gpio);
+		break;
+	case RB_NONE:
+	default:
+		ret = 0;
+		dev_err(nfc->dev, "cannot check R/B NAND status!\n");
+		break;
+	}
+
+	return ret;
+}
+
+static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+	struct sunxi_nand_chip_sel *sel;
+	u32 ctl;
+
+	if (chip > 0 && chip >= sunxi_nand->nsels)
+		return;
+
+	if (chip == sunxi_nand->selected)
+		return;
+
+	ctl = readl(nfc->regs + NFC_REG_CTL) &
+	      ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
+
+	if (chip >= 0) {
+		sel = &sunxi_nand->sels[chip];
+
+		ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
+		       NFC_PAGE_SHIFT(nand->page_shift - 10);
+		if (sel->rb.type == RB_NONE) {
+			nand->dev_ready = NULL;
+		} else {
+			nand->dev_ready = sunxi_nfc_dev_ready;
+			if (sel->rb.type == RB_NATIVE)
+				ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
+		}
+
+		writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
+
+		if (nfc->clk_rate != sunxi_nand->clk_rate) {
+			sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
+			nfc->clk_rate = sunxi_nand->clk_rate;
+		}
+	}
+
+	writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
+	writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
+	writel(ctl, nfc->regs + NFC_REG_CTL);
+
+	sunxi_nand->selected = chip;
+}
+
+static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+	int ret;
+	int cnt;
+	int offs = 0;
+	u32 tmp;
+
+	while (len > offs) {
+		cnt = min(len - offs, NFC_SRAM_SIZE);
+
+		ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
+		if (ret)
+			break;
+
+		writel(cnt, nfc->regs + NFC_REG_CNT);
+		tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
+		writel(tmp, nfc->regs + NFC_REG_CMD);
+
+		ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+		if (ret)
+			break;
+
+		if (buf)
+			memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
+				      cnt);
+		offs += cnt;
+	}
+}
+
+static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
+				int len)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+	int ret;
+	int cnt;
+	int offs = 0;
+	u32 tmp;
+
+	while (len > offs) {
+		cnt = min(len - offs, NFC_SRAM_SIZE);
+
+		ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
+		if (ret)
+			break;
+
+		writel(cnt, nfc->regs + NFC_REG_CNT);
+		memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
+		tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
+		      NFC_ACCESS_DIR;
+		writel(tmp, nfc->regs + NFC_REG_CMD);
+
+		ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+		if (ret)
+			break;
+
+		offs += cnt;
+	}
+}
+
+static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
+{
+	uint8_t ret;
+
+	sunxi_nfc_read_buf(mtd, &ret, 1);
+
+	return ret;
+}
+
+static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
+			       unsigned int ctrl)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+	int ret;
+	u32 tmp;
+
+	ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
+	if (ret)
+		return;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		tmp = readl(nfc->regs + NFC_REG_CTL);
+		if (ctrl & NAND_NCE)
+			tmp |= NFC_CE_CTL;
+		else
+			tmp &= ~NFC_CE_CTL;
+		writel(tmp, nfc->regs + NFC_REG_CTL);
+	}
+
+	if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
+	    !(ctrl & (NAND_CLE | NAND_ALE))) {
+		u32 cmd = 0;
+
+		if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
+			return;
+
+		if (sunxi_nand->cmd_cycles--)
+			cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
+
+		if (sunxi_nand->cmd_cycles--) {
+			cmd |= NFC_SEND_CMD2;
+			writel(sunxi_nand->cmd[1],
+			       nfc->regs + NFC_REG_RCMD_SET);
+		}
+
+		sunxi_nand->cmd_cycles = 0;
+
+		if (sunxi_nand->addr_cycles) {
+			cmd |= NFC_SEND_ADR |
+			       NFC_ADR_NUM(sunxi_nand->addr_cycles);
+			writel(sunxi_nand->addr[0],
+			       nfc->regs + NFC_REG_ADDR_LOW);
+		}
+
+		if (sunxi_nand->addr_cycles > 4)
+			writel(sunxi_nand->addr[1],
+			       nfc->regs + NFC_REG_ADDR_HIGH);
+
+		writel(cmd, nfc->regs + NFC_REG_CMD);
+		sunxi_nand->addr[0] = 0;
+		sunxi_nand->addr[1] = 0;
+		sunxi_nand->addr_cycles = 0;
+		sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+	}
+
+	if (ctrl & NAND_CLE) {
+		sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
+	} else if (ctrl & NAND_ALE) {
+		sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
+				dat << ((sunxi_nand->addr_cycles % 4) * 8);
+		sunxi_nand->addr_cycles++;
+	}
+}
+
+/* These seed values have been extracted from Allwinner's BSP */
+static const u16 sunxi_nfc_randomizer_page_seeds[] = {
+	0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
+	0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
+	0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
+	0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
+	0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
+	0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
+	0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
+	0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
+	0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
+	0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
+	0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
+	0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
+	0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
+	0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
+	0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
+	0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
+};
+
+/*
+ * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
+ * have been generated using
+ * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
+ * the randomizer engine does internally before de/scrambling OOB data.
+ *
+ * Those tables are statically defined to avoid calculating randomizer state
+ * at runtime.
+ */
+static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
+	0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
+	0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
+	0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
+	0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
+	0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
+	0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
+	0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
+	0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
+	0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
+	0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
+	0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
+	0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
+	0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
+	0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
+	0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
+	0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
+};
+
+static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
+	0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
+	0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
+	0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
+	0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
+	0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
+	0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
+	0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
+	0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
+	0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
+	0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
+	0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
+	0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
+	0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
+	0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
+	0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
+	0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
+};
+
+static u16 sunxi_nfc_randomizer_step(u16 state, int count)
+{
+	state &= 0x7fff;
+
+	/*
+	 * This loop is just a simple implementation of a Fibonacci LFSR using
+	 * the x16 + x15 + 1 polynomial.
+	 */
+	while (count--)
+		state = ((state >> 1) |
+			 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
+
+	return state;
+}
+
+static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
+{
+	const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
+	int mod = mtd->erasesize / mtd->writesize;
+
+	if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
+		mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
+
+	if (ecc) {
+		if (mtd->ecc_step_size == 512)
+			seeds = sunxi_nfc_randomizer_ecc512_seeds;
+		else
+			seeds = sunxi_nfc_randomizer_ecc1024_seeds;
+	}
+
+	return seeds[page % mod];
+}
+
+static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
+					int page, bool ecc)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+	u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
+	u16 state;
+
+	if (!(nand->options & NAND_NEED_SCRAMBLING))
+		return;
+
+	ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
+	state = sunxi_nfc_randomizer_state(mtd, page, ecc);
+	ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
+	writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
+}
+
+static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+
+	if (!(nand->options & NAND_NEED_SCRAMBLING))
+		return;
+
+	writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
+	       nfc->regs + NFC_REG_ECC_CTL);
+}
+
+static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+
+	if (!(nand->options & NAND_NEED_SCRAMBLING))
+		return;
+
+	writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
+	       nfc->regs + NFC_REG_ECC_CTL);
+}
+
+static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
+{
+	u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
+
+	bbm[0] ^= state;
+	bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
+}
+
+static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
+					   const uint8_t *buf, int len,
+					   bool ecc, int page)
+{
+	sunxi_nfc_randomizer_config(mtd, page, ecc);
+	sunxi_nfc_randomizer_enable(mtd);
+	sunxi_nfc_write_buf(mtd, buf, len);
+	sunxi_nfc_randomizer_disable(mtd);
+}
+
+static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
+					  int len, bool ecc, int page)
+{
+	sunxi_nfc_randomizer_config(mtd, page, ecc);
+	sunxi_nfc_randomizer_enable(mtd);
+	sunxi_nfc_read_buf(mtd, buf, len);
+	sunxi_nfc_randomizer_disable(mtd);
+}
+
+static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+	struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
+	u32 ecc_ctl;
+
+	ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
+	ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
+		     NFC_ECC_BLOCK_SIZE_MSK);
+	ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
+
+	if (nand->ecc.size == 512)
+		ecc_ctl |= NFC_ECC_BLOCK_512;
+
+	writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
+}
+
+static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+
+	writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
+	       nfc->regs + NFC_REG_ECC_CTL);
+}
+
+static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
+{
+	buf[0] = user_data;
+	buf[1] = user_data >> 8;
+	buf[2] = user_data >> 16;
+	buf[3] = user_data >> 24;
+}
+
+static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
+				       u8 *data, int data_off,
+				       u8 *oob, int oob_off,
+				       int *cur_off,
+				       unsigned int *max_bitflips,
+				       bool bbm, int page)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+	struct nand_ecc_ctrl *ecc = &nand->ecc;
+	int raw_mode = 0;
+	u32 status;
+	int ret;
+
+	if (*cur_off != data_off)
+		nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
+
+	sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
+
+	if (data_off + ecc->size != oob_off)
+		nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
+
+	ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
+	if (ret)
+		return ret;
+
+	sunxi_nfc_randomizer_enable(mtd);
+	writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
+	       nfc->regs + NFC_REG_CMD);
+
+	ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+	sunxi_nfc_randomizer_disable(mtd);
+	if (ret)
+		return ret;
+
+	*cur_off = oob_off + ecc->bytes + 4;
+
+	status = readl(nfc->regs + NFC_REG_ECC_ST);
+	if (status & NFC_ECC_PAT_FOUND(0)) {
+		u8 pattern = 0xff;
+
+		if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
+			pattern = 0x0;
+
+		memset(data, pattern, ecc->size);
+		memset(oob, pattern, ecc->bytes + 4);
+
+		return 1;
+	}
+
+	ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
+
+	memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
+
+	nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
+	sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
+
+	if (status & NFC_ECC_ERR(0)) {
+		/*
+		 * Re-read the data with the randomizer disabled to identify
+		 * bitflips in erased pages.
+		 */
+		if (nand->options & NAND_NEED_SCRAMBLING) {
+			nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
+			nand->read_buf(mtd, data, ecc->size);
+			nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
+			nand->read_buf(mtd, oob, ecc->bytes + 4);
+		}
+
+		ret = nand_check_erased_ecc_chunk(data,	ecc->size,
+						  oob, ecc->bytes + 4,
+						  NULL, 0, ecc->strength);
+		if (ret >= 0)
+			raw_mode = 1;
+	} else {
+		/*
+		 * The engine protects 4 bytes of OOB data per chunk.
+		 * Retrieve the corrected OOB bytes.
+		 */
+		sunxi_nfc_user_data_to_buf(readl(nfc->regs +
+						 NFC_REG_USER_DATA(0)),
+					   oob);
+
+		/* De-randomize the Bad Block Marker. */
+		if (bbm && nand->options & NAND_NEED_SCRAMBLING)
+			sunxi_nfc_randomize_bbm(mtd, page, oob);
+	}
+
+	if (ret < 0) {
+		mtd->ecc_stats.failed++;
+	} else {
+		mtd->ecc_stats.corrected += ret;
+		*max_bitflips = max_t(unsigned int, *max_bitflips, ret);
+	}
+
+	return raw_mode;
+}
+
+static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
+					    u8 *oob, int *cur_off,
+					    bool randomize, int page)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct nand_ecc_ctrl *ecc = &nand->ecc;
+	int offset = ((ecc->bytes + 4) * ecc->steps);
+	int len = mtd->oobsize - offset;
+
+	if (len <= 0)
+		return;
+
+	if (*cur_off != offset)
+		nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
+			      offset + mtd->writesize, -1);
+
+	if (!randomize)
+		sunxi_nfc_read_buf(mtd, oob + offset, len);
+	else
+		sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
+					      false, page);
+
+	*cur_off = mtd->oobsize + mtd->writesize;
+}
+
+static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
+{
+	return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
+}
+
+static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
+					const u8 *data, int data_off,
+					const u8 *oob, int oob_off,
+					int *cur_off, bool bbm,
+					int page)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+	struct nand_ecc_ctrl *ecc = &nand->ecc;
+	int ret;
+
+	if (data_off != *cur_off)
+		nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
+
+	sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
+
+	/* Fill OOB data in */
+	if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
+		u8 user_data[4];
+
+		memcpy(user_data, oob, 4);
+		sunxi_nfc_randomize_bbm(mtd, page, user_data);
+		writel(sunxi_nfc_buf_to_user_data(user_data),
+		       nfc->regs + NFC_REG_USER_DATA(0));
+	} else {
+		writel(sunxi_nfc_buf_to_user_data(oob),
+		       nfc->regs + NFC_REG_USER_DATA(0));
+	}
+
+	if (data_off + ecc->size != oob_off)
+		nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
+
+	ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
+	if (ret)
+		return ret;
+
+	sunxi_nfc_randomizer_enable(mtd);
+	writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
+	       NFC_ACCESS_DIR | NFC_ECC_OP,
+	       nfc->regs + NFC_REG_CMD);
+
+	ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+	sunxi_nfc_randomizer_disable(mtd);
+	if (ret)
+		return ret;
+
+	*cur_off = oob_off + ecc->bytes + 4;
+
+	return 0;
+}
+
+static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
+					     u8 *oob, int *cur_off,
+					     int page)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct nand_ecc_ctrl *ecc = &nand->ecc;
+	int offset = ((ecc->bytes + 4) * ecc->steps);
+	int len = mtd->oobsize - offset;
+
+	if (len <= 0)
+		return;
+
+	if (*cur_off != offset)
+		nand->cmdfunc(mtd, NAND_CMD_RNDIN,
+			      offset + mtd->writesize, -1);
+
+	sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
+
+	*cur_off = mtd->oobsize + mtd->writesize;
+}
+
+static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
+				      struct nand_chip *chip, uint8_t *buf,
+				      int oob_required, int page)
+{
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	unsigned int max_bitflips = 0;
+	int ret, i, cur_off = 0;
+	bool raw_mode = false;
+
+	sunxi_nfc_hw_ecc_enable(mtd);
+
+	for (i = 0; i < ecc->steps; i++) {
+		int data_off = i * ecc->size;
+		int oob_off = i * (ecc->bytes + 4);
+		u8 *data = buf + data_off;
+		u8 *oob = chip->oob_poi + oob_off;
+
+		ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
+						  oob_off + mtd->writesize,
+						  &cur_off, &max_bitflips,
+						  !i, page);
+		if (ret < 0)
+			return ret;
+		else if (ret)
+			raw_mode = true;
+	}
+
+	if (oob_required)
+		sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
+						!raw_mode, page);
+
+	sunxi_nfc_hw_ecc_disable(mtd);
+
+	return max_bitflips;
+}
+
+static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
+					 struct nand_chip *chip,
+					 uint32_t data_offs, uint32_t readlen,
+					 uint8_t *bufpoi, int page)
+{
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int ret, i, cur_off = 0;
+	unsigned int max_bitflips = 0;
+
+	sunxi_nfc_hw_ecc_enable(mtd);
+
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+	for (i = data_offs / ecc->size;
+	     i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
+		int data_off = i * ecc->size;
+		int oob_off = i * (ecc->bytes + 4);
+		u8 *data = bufpoi + data_off;
+		u8 *oob = chip->oob_poi + oob_off;
+
+		ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
+			oob, oob_off + mtd->writesize,
+			&cur_off, &max_bitflips, !i, page);
+		if (ret < 0)
+			return ret;
+	}
+
+	sunxi_nfc_hw_ecc_disable(mtd);
+
+	return max_bitflips;
+}
+
+static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
+				       struct nand_chip *chip,
+				       const uint8_t *buf, int oob_required,
+				       int page)
+{
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int ret, i, cur_off = 0;
+
+	sunxi_nfc_hw_ecc_enable(mtd);
+
+	for (i = 0; i < ecc->steps; i++) {
+		int data_off = i * ecc->size;
+		int oob_off = i * (ecc->bytes + 4);
+		const u8 *data = buf + data_off;
+		const u8 *oob = chip->oob_poi + oob_off;
+
+		ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
+						   oob_off + mtd->writesize,
+						   &cur_off, !i, page);
+		if (ret)
+			return ret;
+	}
+
+	if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
+		sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
+						 &cur_off, page);
+
+	sunxi_nfc_hw_ecc_disable(mtd);
+
+	return 0;
+}
+
+static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
+					  struct nand_chip *chip,
+					  u32 data_offs, u32 data_len,
+					  const u8 *buf, int oob_required,
+					  int page)
+{
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int ret, i, cur_off = 0;
+
+	sunxi_nfc_hw_ecc_enable(mtd);
+
+	for (i = data_offs / ecc->size;
+	     i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
+		int data_off = i * ecc->size;
+		int oob_off = i * (ecc->bytes + 4);
+		const u8 *data = buf + data_off;
+		const u8 *oob = chip->oob_poi + oob_off;
+
+		ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
+						   oob_off + mtd->writesize,
+						   &cur_off, !i, page);
+		if (ret)
+			return ret;
+	}
+
+	sunxi_nfc_hw_ecc_disable(mtd);
+
+	return 0;
+}
+
+static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
+					       struct nand_chip *chip,
+					       uint8_t *buf, int oob_required,
+					       int page)
+{
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	unsigned int max_bitflips = 0;
+	int ret, i, cur_off = 0;
+	bool raw_mode = false;
+
+	sunxi_nfc_hw_ecc_enable(mtd);
+
+	for (i = 0; i < ecc->steps; i++) {
+		int data_off = i * (ecc->size + ecc->bytes + 4);
+		int oob_off = data_off + ecc->size;
+		u8 *data = buf + (i * ecc->size);
+		u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
+
+		ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
+						  oob_off, &cur_off,
+						  &max_bitflips, !i, page);
+		if (ret < 0)
+			return ret;
+		else if (ret)
+			raw_mode = true;
+	}
+
+	if (oob_required)
+		sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
+						!raw_mode, page);
+
+	sunxi_nfc_hw_ecc_disable(mtd);
+
+	return max_bitflips;
+}
+
+static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
+						struct nand_chip *chip,
+						const uint8_t *buf,
+						int oob_required, int page)
+{
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+	int ret, i, cur_off = 0;
+
+	sunxi_nfc_hw_ecc_enable(mtd);
+
+	for (i = 0; i < ecc->steps; i++) {
+		int data_off = i * (ecc->size + ecc->bytes + 4);
+		int oob_off = data_off + ecc->size;
+		const u8 *data = buf + (i * ecc->size);
+		const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
+
+		ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
+						   oob, oob_off, &cur_off,
+						   false, page);
+		if (ret)
+			return ret;
+	}
+
+	if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
+		sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
+						 &cur_off, page);
+
+	sunxi_nfc_hw_ecc_disable(mtd);
+
+	return 0;
+}
+
+static const s32 tWB_lut[] = {6, 12, 16, 20};
+static const s32 tRHW_lut[] = {4, 8, 12, 20};
+
+static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
+		u32 clk_period)
+{
+	u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
+	int i;
+
+	for (i = 0; i < lut_size; i++) {
+		if (clk_cycles <= lut[i])
+			return i;
+	}
+
+	/* Doesn't fit */
+	return -EINVAL;
+}
+
+#define sunxi_nand_lookup_timing(l, p, c) \
+			_sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
+
+static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
+				       const struct nand_sdr_timings *timings)
+{
+	u32 min_clk_period = 0;
+	s32 tWB, tADL, tWHR, tRHW, tCAD;
+
+	/* T1 <=> tCLS */
+	if (timings->tCLS_min > min_clk_period)
+		min_clk_period = timings->tCLS_min;
+
+	/* T2 <=> tCLH */
+	if (timings->tCLH_min > min_clk_period)
+		min_clk_period = timings->tCLH_min;
+
+	/* T3 <=> tCS */
+	if (timings->tCS_min > min_clk_period)
+		min_clk_period = timings->tCS_min;
+
+	/* T4 <=> tCH */
+	if (timings->tCH_min > min_clk_period)
+		min_clk_period = timings->tCH_min;
+
+	/* T5 <=> tWP */
+	if (timings->tWP_min > min_clk_period)
+		min_clk_period = timings->tWP_min;
+
+	/* T6 <=> tWH */
+	if (timings->tWH_min > min_clk_period)
+		min_clk_period = timings->tWH_min;
+
+	/* T7 <=> tALS */
+	if (timings->tALS_min > min_clk_period)
+		min_clk_period = timings->tALS_min;
+
+	/* T8 <=> tDS */
+	if (timings->tDS_min > min_clk_period)
+		min_clk_period = timings->tDS_min;
+
+	/* T9 <=> tDH */
+	if (timings->tDH_min > min_clk_period)
+		min_clk_period = timings->tDH_min;
+
+	/* T10 <=> tRR */
+	if (timings->tRR_min > (min_clk_period * 3))
+		min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
+
+	/* T11 <=> tALH */
+	if (timings->tALH_min > min_clk_period)
+		min_clk_period = timings->tALH_min;
+
+	/* T12 <=> tRP */
+	if (timings->tRP_min > min_clk_period)
+		min_clk_period = timings->tRP_min;
+
+	/* T13 <=> tREH */
+	if (timings->tREH_min > min_clk_period)
+		min_clk_period = timings->tREH_min;
+
+	/* T14 <=> tRC */
+	if (timings->tRC_min > (min_clk_period * 2))
+		min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
+
+	/* T15 <=> tWC */
+	if (timings->tWC_min > (min_clk_period * 2))
+		min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
+
+	/* T16 - T19 + tCAD */
+	tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
+					min_clk_period);
+	if (tWB < 0) {
+		dev_err(nfc->dev, "unsupported tWB\n");
+		return tWB;
+	}
+
+	tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
+	if (tADL > 3) {
+		dev_err(nfc->dev, "unsupported tADL\n");
+		return -EINVAL;
+	}
+
+	tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
+	if (tWHR > 3) {
+		dev_err(nfc->dev, "unsupported tWHR\n");
+		return -EINVAL;
+	}
+
+	tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
+					min_clk_period);
+	if (tRHW < 0) {
+		dev_err(nfc->dev, "unsupported tRHW\n");
+		return tRHW;
+	}
+
+	/*
+	 * TODO: according to ONFI specs this value only applies for DDR NAND,
+	 * but Allwinner seems to set this to 0x7. Mimic them for now.
+	 */
+	tCAD = 0x7;
+
+	/* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
+	chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
+
+	/*
+	 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
+	 * output cycle timings shall be used if the host drives tRC less than
+	 * 30 ns.
+	 */
+	chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
+
+	/* Convert min_clk_period from picoseconds to nanoseconds */
+	min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
+
+	/*
+	 * Convert min_clk_period into a clk frequency, then get the
+	 * appropriate rate for the NAND controller IP given this formula
+	 * (specified in the datasheet):
+	 * nand clk_rate = min_clk_rate
+	 */
+	chip->clk_rate = 1000000000L / min_clk_period;
+
+	return 0;
+}
+
+static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
+{
+	struct mtd_info *mtd = nand_to_mtd(&chip->nand);
+	const struct nand_sdr_timings *timings;
+	int ret;
+	int mode;
+
+	mode = onfi_get_async_timing_mode(&chip->nand);
+	if (mode == ONFI_TIMING_MODE_UNKNOWN) {
+		mode = chip->nand.onfi_timing_mode_default;
+	} else {
+		uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
+		int i;
+
+		mode = fls(mode) - 1;
+		if (mode < 0)
+			mode = 0;
+
+		feature[0] = mode;
+		for (i = 0; i < chip->nsels; i++) {
+			chip->nand.select_chip(mtd, i);
+			ret = chip->nand.onfi_set_features(mtd,
+						&chip->nand,
+						ONFI_FEATURE_ADDR_TIMING_MODE,
+						feature);
+			chip->nand.select_chip(mtd, -1);
+			if (ret)
+				return ret;
+		}
+	}
+
+	timings = onfi_async_timing_mode_to_sdr_timings(mode);
+	if (IS_ERR(timings))
+		return PTR_ERR(timings);
+
+	return sunxi_nand_chip_set_timings(chip, timings);
+}
+
+static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
+					      struct nand_ecc_ctrl *ecc)
+{
+	static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
+	struct sunxi_nand_hw_ecc *data;
+	struct nand_ecclayout *layout;
+	int nsectors;
+	int ret;
+	int i;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	if (ecc->size != 512 && ecc->size != 1024)
+		return -EINVAL;
+
+	/* Prefer 1k ECC chunk over 512 ones */
+	if (ecc->size == 512 && mtd->writesize > 512) {
+		ecc->size = 1024;
+		ecc->strength *= 2;
+	}
+
+	/* Add ECC info retrieval from DT */
+	for (i = 0; i < ARRAY_SIZE(strengths); i++) {
+		if (ecc->strength <= strengths[i])
+			break;
+	}
+
+	if (i >= ARRAY_SIZE(strengths)) {
+		dev_err(nfc->dev, "unsupported strength\n");
+		ret = -ENOTSUPP;
+		goto err;
+	}
+
+	data->mode = i;
+
+	/* HW ECC always request ECC bytes for 1024 bytes blocks */
+	ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
+
+	/* HW ECC always work with even numbers of ECC bytes */
+	ecc->bytes = ALIGN(ecc->bytes, 2);
+
+	layout = &data->layout;
+	nsectors = mtd->writesize / ecc->size;
+
+	if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	layout->eccbytes = (ecc->bytes * nsectors);
+
+	ecc->layout = layout;
+	ecc->priv = data;
+
+	return 0;
+
+err:
+	kfree(data);
+
+	return ret;
+}
+
+#ifndef __UBOOT__
+static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
+{
+	kfree(ecc->priv);
+}
+#endif /* __UBOOT__ */
+
+static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
+				       struct nand_ecc_ctrl *ecc)
+{
+	struct nand_ecclayout *layout;
+	int nsectors;
+	int i, j;
+	int ret;
+
+	ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
+	if (ret)
+		return ret;
+
+	ecc->read_page = sunxi_nfc_hw_ecc_read_page;
+	ecc->write_page = sunxi_nfc_hw_ecc_write_page;
+	ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
+	ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
+	layout = ecc->layout;
+	nsectors = mtd->writesize / ecc->size;
+
+	for (i = 0; i < nsectors; i++) {
+		if (i) {
+			layout->oobfree[i].offset =
+				layout->oobfree[i - 1].offset +
+				layout->oobfree[i - 1].length +
+				ecc->bytes;
+			layout->oobfree[i].length = 4;
+		} else {
+			/*
+			 * The first 2 bytes are used for BB markers, hence we
+			 * only have 2 bytes available in the first user data
+			 * section.
+			 */
+			layout->oobfree[i].length = 2;
+			layout->oobfree[i].offset = 2;
+		}
+
+		for (j = 0; j < ecc->bytes; j++)
+			layout->eccpos[(ecc->bytes * i) + j] =
+					layout->oobfree[i].offset +
+					layout->oobfree[i].length + j;
+	}
+
+	if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
+		layout->oobfree[nsectors].offset =
+				layout->oobfree[nsectors - 1].offset +
+				layout->oobfree[nsectors - 1].length +
+				ecc->bytes;
+		layout->oobfree[nsectors].length = mtd->oobsize -
+				((ecc->bytes + 4) * nsectors);
+	}
+
+	return 0;
+}
+
+static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
+						struct nand_ecc_ctrl *ecc)
+{
+	struct nand_ecclayout *layout;
+	int nsectors;
+	int i;
+	int ret;
+
+	ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
+	if (ret)
+		return ret;
+
+	ecc->prepad = 4;
+	ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
+	ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
+
+	layout = ecc->layout;
+	nsectors = mtd->writesize / ecc->size;
+
+	for (i = 0; i < (ecc->bytes * nsectors); i++)
+		layout->eccpos[i] = i;
+
+	layout->oobfree[0].length = mtd->oobsize - i;
+	layout->oobfree[0].offset = i;
+
+	return 0;
+}
+
+#ifndef __UBOOT__
+static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
+{
+	switch (ecc->mode) {
+	case NAND_ECC_HW:
+	case NAND_ECC_HW_SYNDROME:
+		sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
+		break;
+	case NAND_ECC_NONE:
+		kfree(ecc->layout);
+	default:
+		break;
+	}
+}
+#endif /* __UBOOT__ */
+
+static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
+{
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	int ret;
+
+	if (!ecc->size) {
+		ecc->size = nand->ecc_step_ds;
+		ecc->strength = nand->ecc_strength_ds;
+	}
+
+	if (!ecc->size || !ecc->strength)
+		return -EINVAL;
+
+	switch (ecc->mode) {
+	case NAND_ECC_SOFT_BCH:
+		break;
+	case NAND_ECC_HW:
+		ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
+		if (ret)
+			return ret;
+		break;
+	case NAND_ECC_HW_SYNDROME:
+		ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
+		if (ret)
+			return ret;
+		break;
+	case NAND_ECC_NONE:
+		ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
+		if (!ecc->layout)
+			return -ENOMEM;
+		ecc->layout->oobfree[0].length = mtd->oobsize;
+	case NAND_ECC_SOFT:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
+{
+	const struct nand_sdr_timings *timings;
+	const void *blob = gd->fdt_blob;
+	struct sunxi_nand_chip *chip;
+	struct mtd_info *mtd;
+	struct nand_chip *nand;
+	int nsels;
+	int ret;
+	int i;
+	u32 cs[8], rb[8];
+
+	if (!fdt_getprop(blob, node, "reg", &nsels))
+		return -EINVAL;
+
+	nsels /= sizeof(u32);
+	if (!nsels || nsels > 8) {
+		dev_err(dev, "invalid reg property size\n");
+		return -EINVAL;
+	}
+
+	chip = kzalloc(sizeof(*chip) +
+		       (nsels * sizeof(struct sunxi_nand_chip_sel)),
+		       GFP_KERNEL);
+	if (!chip) {
+		dev_err(dev, "could not allocate chip\n");
+		return -ENOMEM;
+	}
+
+	chip->nsels = nsels;
+	chip->selected = -1;
+
+	for (i = 0; i < nsels; i++) {
+		cs[i] = -1;
+		rb[i] = -1;
+	}
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
+	if (ret) {
+		dev_err(dev, "could not retrieve reg property: %d\n", ret);
+		return ret;
+	}
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
+				   nsels);
+	if (ret) {
+		dev_err(dev, "could not retrieve reg property: %d\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < nsels; i++) {
+		int tmp = cs[i];
+
+		if (tmp > NFC_MAX_CS) {
+			dev_err(dev,
+				"invalid reg value: %u (max CS = 7)\n",
+				tmp);
+			return -EINVAL;
+		}
+
+		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
+			dev_err(dev, "CS %d already assigned\n", tmp);
+			return -EINVAL;
+		}
+
+		chip->sels[i].cs = tmp;
+
+		tmp = rb[i];
+		if (tmp >= 0 && tmp < 2) {
+			chip->sels[i].rb.type = RB_NATIVE;
+			chip->sels[i].rb.info.nativeid = tmp;
+		} else {
+			ret = gpio_request_by_name_nodev(blob, node,
+						"rb-gpios", i,
+						&chip->sels[i].rb.info.gpio,
+						GPIOD_IS_IN);
+			if (ret)
+				chip->sels[i].rb.type = RB_GPIO;
+			else
+				chip->sels[i].rb.type = RB_NONE;
+		}
+	}
+
+	timings = onfi_async_timing_mode_to_sdr_timings(0);
+	if (IS_ERR(timings)) {
+		ret = PTR_ERR(timings);
+		dev_err(dev,
+			"could not retrieve timings for ONFI mode 0: %d\n",
+			ret);
+		return ret;
+	}
+
+	ret = sunxi_nand_chip_set_timings(chip, timings);
+	if (ret) {
+		dev_err(dev, "could not configure chip timings: %d\n", ret);
+		return ret;
+	}
+
+	nand = &chip->nand;
+	/* Default tR value specified in the ONFI spec (chapter 4.15.1) */
+	nand->chip_delay = 200;
+	nand->controller = &nfc->controller;
+	/*
+	 * Set the ECC mode to the default value in case nothing is specified
+	 * in the DT.
+	 */
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->flash_node = node;
+	nand->select_chip = sunxi_nfc_select_chip;
+	nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
+	nand->read_buf = sunxi_nfc_read_buf;
+	nand->write_buf = sunxi_nfc_write_buf;
+	nand->read_byte = sunxi_nfc_read_byte;
+
+	mtd = nand_to_mtd(nand);
+	ret = nand_scan_ident(mtd, nsels, NULL);
+	if (ret)
+		return ret;
+
+	if (nand->bbt_options & NAND_BBT_USE_FLASH)
+		nand->bbt_options |= NAND_BBT_NO_OOB;
+
+	if (nand->options & NAND_NEED_SCRAMBLING)
+		nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+	nand->options |= NAND_SUBPAGE_READ;
+
+	ret = sunxi_nand_chip_init_timings(chip);
+	if (ret) {
+		dev_err(dev, "could not configure chip timings: %d\n", ret);
+		return ret;
+	}
+
+	ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
+	if (ret) {
+		dev_err(dev, "ECC init failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = nand_scan_tail(mtd);
+	if (ret) {
+		dev_err(dev, "nand_scan_tail failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = nand_register(devnum, mtd);
+	if (ret) {
+		dev_err(dev, "failed to register mtd device: %d\n", ret);
+		return ret;
+	}
+
+	list_add_tail(&chip->node, &nfc->chips);
+
+	return 0;
+}
+
+static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
+{
+	const void *blob = gd->fdt_blob;
+	int nand_node;
+	int ret, i = 0;
+
+	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
+	     nand_node = fdt_next_subnode(blob, nand_node))
+		i++;
+
+	if (i > 8) {
+		dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
+		return -EINVAL;
+	}
+
+	i = 0;
+	for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
+	     nand_node = fdt_next_subnode(blob, nand_node)) {
+		ret = sunxi_nand_chip_init(nand_node, nfc, i++);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifndef __UBOOT__
+static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
+{
+	struct sunxi_nand_chip *chip;
+
+	while (!list_empty(&nfc->chips)) {
+		chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
+					node);
+		nand_release(&chip->mtd);
+		sunxi_nand_ecc_cleanup(&chip->nand.ecc);
+		list_del(&chip->node);
+		kfree(chip);
+	}
+}
+#endif /* __UBOOT__ */
+
+void sunxi_nand_init(void)
+{
+	const void *blob = gd->fdt_blob;
+	struct sunxi_nfc *nfc;
+	fdt_addr_t regs;
+	int node;
+	int ret;
+
+	nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
+	if (!nfc)
+		return;
+
+	spin_lock_init(&nfc->controller.lock);
+	init_waitqueue_head(&nfc->controller.wq);
+	INIT_LIST_HEAD(&nfc->chips);
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
+	if (node < 0) {
+		pr_err("unable to find nfc node in device tree\n");
+		goto err;
+	}
+
+	if (!fdtdec_get_is_enabled(blob, node)) {
+		pr_err("nfc disabled in device tree\n");
+		goto err;
+	}
+
+	regs = fdtdec_get_addr(blob, node, "reg");
+	if (regs == FDT_ADDR_T_NONE) {
+		pr_err("unable to find nfc address in device tree\n");
+		goto err;
+	}
+
+	nfc->regs = (void *)regs;
+
+	ret = sunxi_nfc_rst(nfc);
+	if (ret)
+		goto err;
+
+	ret = sunxi_nand_chips_init(node, nfc);
+	if (ret) {
+		dev_err(dev, "failed to init nand chips\n");
+		goto err;
+	}
+
+	return;
+
+err:
+	kfree(nfc);
+}
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Boris BREZILLON");
+MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 6358901..f551926 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -135,6 +135,8 @@
 
 #ifdef CONFIG_NAND_SUNXI
 #define CONFIG_SPL_NAND_SUPPORT 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 8
 #endif
 
 #ifdef CONFIG_SPL_SPI_SUNXI
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 151c590..70ea0bf 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,7 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
+	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
 
 	COMPAT_COUNT,
 };
diff --git a/include/nand.h b/include/nand.h
index 627b217..b6eb223 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -142,3 +142,6 @@ __attribute__((noreturn)) void nand_boot(void);
 int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result);
 #endif
 int spl_nand_erase_one(int block, int page);
+
+/* platform specific init functions */
+void sunxi_nand_init(void);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c2bcbde..462a24f 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -65,6 +65,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
+	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
cgit v0.10.2


From 32b18435dec8a5d1fbf1eae74b09e28e9dd92b72 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:24 +0200
Subject: sun5i: Add NAND controller to the sun5i DTSI

Add the NAND controller definition to sun5i.dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi
index 59a9426..87e5353 100644
--- a/arch/arm/dts/sun5i.dtsi
+++ b/arch/arm/dts/sun5i.dtsi
@@ -356,6 +356,17 @@
 			#dma-cells = <2>;
 		};
 
+		nfc: nand@01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <37>;
+			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		spi0: spi@01c05000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
@@ -548,6 +559,44 @@
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
 
+			nand_pins_a: nand_base0@0 {
+				allwinner,pins = "PC0", "PC1", "PC2",
+						"PC5", "PC8", "PC9", "PC10",
+						"PC11", "PC12", "PC13", "PC14",
+						"PC15";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs0_pins_a: nand_cs@0 {
+				allwinner,pins = "PC4";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_cs1_pins_a: nand_cs@1 {
+				allwinner,pins = "PC3";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_rb0_pins_a: nand_rb@0 {
+				allwinner,pins = "PC6";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			nand_rb1_pins_a: nand_rb@1 {
+				allwinner,pins = "PC7";
+				allwinner,function = "nand0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
 			uart3_pins_a: uart3@0 {
 				allwinner,pins = "PG9", "PG10";
 				allwinner,function = "uart3";
-- 
cgit v0.10.2


From cd7f5e1cdfae1d4cd73cfc16ae6bcddfeb752727 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:25 +0200
Subject: =?UTF-8?q?mtd:=20nand:=20Add=20a=20full-id=20entry=20for=20the=20?=
 =?UTF-8?q?H27QCG8T2E5R=E2=80=90BCF=20NAND?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 561d2cd..ce0a14e 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -62,6 +62,10 @@ struct nand_flash_dev nand_flash_ids[] = {
 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
 		  NAND_ECC_INFO(40, SZ_1K), 4 },
+	{"H27QCG8T2E5R‐BCF 64G 3.3V 8-bit",
+		{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
+		  SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
+		  NAND_ECC_INFO(56, SZ_1K), 1 },
 
 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
-- 
cgit v0.10.2


From c1fe6b5b5e540e8c94a1be4e1119ee17ad5af5e7 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:26 +0200
Subject: mtd: nand: Increase the max OOB size

Some NANDs are now exposing 1664 OOB bytes per page. Adjust the
NAND_MAX_OOBSIZE value accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 29aae43..87d72db 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -48,7 +48,7 @@ extern void nand_wait_ready(struct mtd_info *mtd);
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE       1216
+#define NAND_MAX_OOBSIZE       1664
 #define NAND_MAX_PAGESIZE      16384
 
 /*
-- 
cgit v0.10.2


From a0dfa88b4e12c00414a4058823e0eec8c216f1d7 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:27 +0200
Subject: sunxi: nand: Increase CONFIG_SYS_NAND_MAX_ECCPOS value

On some sunxi boards we have NANDs exposing 1664 OOB bytes per page.
Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index f551926..b9aa62b 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -134,6 +134,7 @@
 #define CONFIG_SERIAL_TAG
 
 #ifdef CONFIG_NAND_SUNXI
+#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
 #define CONFIG_SPL_NAND_SUPPORT 1
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_MAX_NAND_DEVICE 8
-- 
cgit v0.10.2


From c1aa7d629eb9f0ed7836061170461abb04d34111 Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Wed, 15 Jun 2016 21:09:28 +0200
Subject: sunxi: Enable NAND controller on the CHIP

Enable the NAND controller in the sun5i-r8-chip.dts.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi
index bddd0de..a5f8855 100644
--- a/arch/arm/dts/sun5i-a10s.dtsi
+++ b/arch/arm/dts/sun5i-a10s.dtsi
@@ -241,6 +241,20 @@
 		allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
+
+	nand_cs2_pins_a: nand_cs@2 {
+		allwinner,pins = "PC17";
+		allwinner,function = "nand0";
+		allwinner,drive = <0>;
+		allwinner,pull = <0>;
+	};
+
+	nand_cs3_pins_a: nand_cs@3 {
+		allwinner,pins = "PC18";
+		allwinner,function = "nand0";
+		allwinner,drive = <0>;
+		allwinner,pull = <0>;
+	};
 };
 
 &sram_a {
diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts b/arch/arm/dts/sun5i-a13-olinuxino.dts
index b3c234c..30e069a 100644
--- a/arch/arm/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/dts/sun5i-a13-olinuxino.dts
@@ -155,6 +155,21 @@
 	status = "okay";
 };
 
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+	status = "okay";
+
+	nand@0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-mode = "hw";
+		allwinner,randomize;
+	};
+};
+
 &ohci0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
index 6ad19e2..b1b62d5 100644
--- a/arch/arm/dts/sun5i-r8-chip.dts
+++ b/arch/arm/dts/sun5i-r8-chip.dts
@@ -142,6 +142,21 @@
 	status = "okay";
 };
 
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+	status = "okay";
+
+	nand@0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-mode = "hw";
+		nand-on-flash-bbt;
+	};
+};
+
 &ohci0 {
 	status = "okay";
 };
-- 
cgit v0.10.2


From ebb7febc92fc628d1f37b96616a1bb21b646d072 Mon Sep 17 00:00:00 2001
From: Hector Palacios <hector.palacios@digi.com>
Date: Mon, 18 Jul 2016 09:37:41 +0200
Subject: mtd: nand: fix bug writing 1 byte less than page size

nand_do_write_ops() determines if it is writing a partial page with the
formula:
	part_pagewr = (column || writelen < (mtd->writesize - 1))

When 'writelen' is exactly 1 byte less than the NAND page size the formula
equates to zero, so the code doesn't process it as a partial write, although
it should.
As a consequence the function remains in the while(1) loop with 'writelen'
becoming 0xffffffff and iterating until the watchdog timeout triggers.

To reproduce the issue on a NAND with 2K page (0x800):
	=> nand erase.part <partition>
	=> nand write $loadaddr <partition> 7ff

Signed-off-by: Hector Palacios <hector.palacios@digi.com>

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 4cf4518..d1287bc 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2414,7 +2414,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 		int cached = writelen > bytes && page != blockmask;
 		uint8_t *wbuf = buf;
 		int use_bufpoi;
-		int part_pagewr = (column || writelen < (mtd->writesize - 1));
+		int part_pagewr = (column || writelen < mtd->writesize);
 
 		if (part_pagewr)
 			use_bufpoi = 1;
-- 
cgit v0.10.2


From 59441ac3c135c412c679bdd1c82c8f2a9b805bbc Mon Sep 17 00:00:00 2001
From: Steve Rae <steve.rae@raedomain.com>
Date: Wed, 29 Jun 2016 13:50:59 -0700
Subject: mtd: fix compiler warnings

- add missing declaration
- update debug output format specifiers

Signed-off-by: Steve Rae <steve.rae@raedomain.com>

diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index 3f4f334..b9b160d 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -1493,7 +1493,7 @@ static int spread_partitions(void)
 			part = list_entry(pentry, struct part_info, link);
 
 			debug("spread_partitions: device = %s%d, partition %d ="
-				" (%s) 0x%08x@0x%08x\n",
+				" (%s) 0x%08llx@0x%08llx\n",
 				MTD_DEV_TYPE(dev->id->type), dev->id->num,
 				part_num, part->name, part->size,
 				part->offset);
@@ -2025,7 +2025,7 @@ static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc,
 
 		if (!strcmp(&argv[1][3], ".spread")) {
 			spread_partition(mtd, p, &next_offset);
-			debug("increased %s to %d bytes\n", p->name, p->size);
+			debug("increased %s to %llu bytes\n", p->name, p->size);
 		}
 #endif
 
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index cf20674..779eea0 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -500,5 +500,10 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
 int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
 		     loff_t *size, loff_t *maxsize, int devtype,
 		     uint64_t chipsize);
+
+/* drivers/mtd/mtdcore.c */
+void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+			  const uint64_t length, uint64_t *len_incl_bad,
+			  int *truncated);
 #endif
 #endif /* __MTD_MTD_H__ */
-- 
cgit v0.10.2


From c4974632e2af6765f8d9590f1cba1afd0c6ffedf Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Tue, 19 Jul 2016 16:20:13 +0200
Subject: cmd: misc: Add support for fractions in sleep

A feasible way to communicate certain errors for devices that have no
other way of signalling besides LEDs is to flash these LEDs. For errors
in U-Boot, a script that utilizes the led and sleep commands would be a
practicable way, but currently the sleep command can only delay for an
integral amount of seconds, which is too slow to create an easily
noticeable pattern for flashing LEDs.

Therefore, this patch adds support for fractions (down to .001 seconds)
to the sleep command.

The parsing is kept minimal, simplistic and as robust as possible: After
converting the passed string using simple_strtoul and multiplying it
with 1000, we search for the first dot, convert the three characters
after that into a number (if they are not numbers, we ignore the
fractional part and just use the delay we got from simple_strtoul), and
add this number to the delay.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/cmd/misc.c b/cmd/misc.c
index 39d8683..efcbb90 100644
--- a/cmd/misc.c
+++ b/cmd/misc.c
@@ -15,13 +15,31 @@
 static int do_sleep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong start = get_timer(0);
+	ulong mdelay = 0;
 	ulong delay;
+	char *frpart;
 
 	if (argc != 2)
 		return CMD_RET_USAGE;
 
 	delay = simple_strtoul(argv[1], NULL, 10) * CONFIG_SYS_HZ;
 
+	frpart = strchr(argv[1], '.');
+
+	if (frpart) {
+		uint mult = CONFIG_SYS_HZ / 10;
+		for (frpart++; *frpart != '\0' && mult > 0; frpart++) {
+			if (*frpart < '0' || *frpart > '9') {
+				mdelay = 0;
+				break;
+			}
+			mdelay += (*frpart - '0') * mult;
+			mult /= 10;
+		}
+	}
+
+	delay += mdelay;
+
 	while (get_timer(start) < delay) {
 		if (ctrlc())
 			return (-1);
@@ -36,7 +54,8 @@ U_BOOT_CMD(
 	sleep ,    2,    1,     do_sleep,
 	"delay execution for some time",
 	"N\n"
-	"    - delay execution for N seconds (N is _decimal_ !!!)"
+	"    - delay execution for N seconds (N is _decimal_ and can be\n"
+	"      fractional)"
 );
 
 #ifdef CONFIG_CMD_TIMER
-- 
cgit v0.10.2


From bcdc1c8376c55fcc8b8fdd7f27f117eff0bf715d Mon Sep 17 00:00:00 2001
From: "Karicheri, Muralidharan" <m-karicheri2@ti.com>
Date: Tue, 19 Jul 2016 14:39:14 -0400
Subject: keystone: k2h/e/l: Fix DMA coherency for QM PDSP

commit 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid
left under a macro KS2_MSMC_SEGMENT_QM_PDSP which is no longer valid.
This, in effect disabled DMA coherency for QM PDSP.

Given that msmc_k2hkle_common_setup is valid for all K2H/K/L/E SoCs,
the #ifdef should been removed in the first place. Do the same.

Fixes: 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery")
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 3b6d5ef..6e5a1e1 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -101,9 +101,7 @@ static void msmc_k2hkle_common_setup(void)
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
-#ifdef KS2_MSMC_SEGMENT_QM_PDSP
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
-#endif
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 }
-- 
cgit v0.10.2


From e8fb4358c2ea3b5629f004f7d0d5624c860d7e70 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Wed, 20 Jul 2016 08:32:50 +0200
Subject: common: fit: Allow U-Boot images to be booted

In certain circumstances it comes in handy to be able to boot into a second
U-Boot. But as of now it is not possible to boot a U-Boot binary that is inside
a FIT image, which is problematic for projects that e.g. need to guarantee a
unbroken chain of trust from SOC all the way into the OS, since the FIT signing
mechanism cannot be used.

This patch adds the capability to load such FIT images.

An example .its snippet (utilizing signature verification) might look
like the following:

images {
	firmware@1 {
		description = "2nd stage U-Boot image";
		data = /incbin/("u-boot-dtb.img.gz");
		type = "firmware";
		arch = "arm";
		os = "u-boot";
		compression = "gzip";
		load = <0x8FFFC0>;
		entry = <0x900000>;
		signature@1 {
			algo = "sha256,rsa4096";
			key-name-hint = "key";
		};
	};
};

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/common/image-fit.c b/common/image-fit.c
index 6f920da..73ad34e 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1684,12 +1684,13 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
 	bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
 	type_ok = fit_image_check_type(fit, noffset, image_type) ||
-		(image_type == IH_TYPE_KERNEL &&
-			fit_image_check_type(fit, noffset,
-					     IH_TYPE_KERNEL_NOLOAD));
+		  fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) ||
+		  (image_type == IH_TYPE_KERNEL &&
+		   fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD));
 
 	os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA ||
 		fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
+		fit_image_check_os(fit, noffset, IH_OS_U_BOOT) ||
 		fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
 
 	/*
-- 
cgit v0.10.2


From 492716662fbdc08e254dda2c209b320e2bf6c837 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 21 Jul 2016 01:44:46 +0200
Subject: efi_loader: Make exposed image loader path absolute

When loading an efi image, we pass it the location it was loaded from.

On file system backends, there are no relative paths, so we should always
pass in absolute ones. For network paths, we may be relative.

This fixes distro booting with grub2 for me when it fetches the grub2 config
file from the loader partition.

Reported-by: york sun <york.sun@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 011f62c..d66892e 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -290,6 +290,11 @@ void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
 
 	/* Patch bootefi_image_path to the target file path */
 	memset(bootefi_image_path[0].str, 0, sizeof(bootefi_image_path[0].str));
-	snprintf(devname, sizeof(devname), "%s", path);
+	if (strcmp(dev, "Net")) {
+		/* Add leading / to fs paths, because they're absolute */
+		snprintf(devname, sizeof(devname), "/%s", path);
+	} else {
+		snprintf(devname, sizeof(devname), "%s", path);
+	}
 	ascii2unicode(bootefi_image_path[0].str, devname);
 }
-- 
cgit v0.10.2


From 3325b06556b78a2afdaaa781765b505f7d1f8ae4 Mon Sep 17 00:00:00 2001
From: Russ Dill <Russ.Dill@ti.com>
Date: Thu, 21 Jul 2016 04:28:31 -0700
Subject: ARM: am33xx: Fix DDR init delay placement

The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.

Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 888cf1f..ef1fc4d 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -120,12 +120,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+	/* Wait 1ms because of L3 timeout error */
+	udelay(1000);
+
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 
 	/* Perform hardware leveling for DDR3 */
 	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
-		udelay(1000);
 		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
 		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
-- 
cgit v0.10.2


From 335b4e53c9c5310c36f5178d2f66a13c4b1c8592 Mon Sep 17 00:00:00 2001
From: Russ Dill <Russ.Dill@ti.com>
Date: Thu, 21 Jul 2016 04:28:32 -0700
Subject: ARM: am33xx: Always inhibit init/refresh during DDR phy init

A couple of commits have modified the am33xx/am437x ddr2/ddr3
initialization path to fix certain issues, but have had the side effect
of causing L3 noc errors during initialization. The two commits are:

69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
fc46ba "arm: am437x: Enable hardware leveling for EMIF"

The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
platforms. This delays initialization and refresh until a later stage.
The 500us timer can be programmed for platforms that require it
and for platforms that don't require it. It is currently hardcoded
for 400MHz systems. For systems with a higher memory frequency
this needs to be a larger value, and for systems with a lower
memory frequency this can be a lower value. This can be
considered a separate issue and corrected in a later commit.

Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index ef1fc4d..6acf30c 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -292,19 +292,14 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
 void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
 	/*
-	 * Disable initialization and refreshes for now until we
-	 * finish programming EMIF regs.
-	 * Also set time between rising edge of DDR_RESET to rising
-	 * edge of DDR_CKE to > 500us per memory spec.
+	 * Disable initialization and refreshes for now until we finish
+	 * programming EMIF regs and set time between rising edge of
+	 * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
+	 * We currently hardcode a value based on a max expected frequency
+	 * of 400MHz.
 	 */
-#ifndef CONFIG_AM43XX
-	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
-		     EMIF_REG_INITREF_DIS_MASK);
-#endif
-	if (regs->zq_config)
-		/* Set time between rising edge of DDR_RESET to rising
-		 * edge of DDR_CKE to > 500us per memory spec. */
-		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
+		&emif_reg[nr]->emif_sdram_ref_ctrl);
 
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
-- 
cgit v0.10.2


From 713fb2dcb24537073171fc84528044a3ba081817 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Fri, 22 Jul 2016 08:58:40 +0200
Subject: tools, rsa: Further minor cleanups on top of c236ebd and 2b9ec7

[NOTE: I took v1 of these patches in, and then v2 came out, this commit
is squashing the minor deltas from v1 -> v2 of updates to c236ebd and
2b9ec76 into this commit - trini]

- Added an additional NULL check, as suggested by Simon Glass to
  fit_image_process_sig
- Re-formatted the comment blocks

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
[For merging the chnages from v2 back onto v1]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index d4a1a5e..c26f741 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -420,8 +420,10 @@ static int fdt_add_bignum(void *blob, int noffset, const char *prop_name,
 		BN_rshift(num, num, 32); /*  N = N/B */
 	}
 
-	/* We try signing with successively increasing size values, so this
-	 * might fail several times */
+	/*
+	 * We try signing with successively increasing size values, so this
+	 * might fail several times
+	 */
 	ret = fdt_setprop(blob, noffset, prop_name, buf, size);
 	if (ret)
 		return -FDT_ERR_NOSPACE;
diff --git a/tools/image-host.c b/tools/image-host.c
index 399ec94..1104695 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -238,11 +238,16 @@ static int fit_image_process_sig(const char *keydir, void *keydest,
 	/* Get keyname again, as FDT has changed and invalidated our pointer */
 	info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
 
-	ret = info.algo->add_verify_data(&info, keydest);
+	if (keydest)
+		ret = info.algo->add_verify_data(&info, keydest);
+	else
+		return -1;
 
-	/* Write the public key into the supplied FDT file; this might fail
+	/*
+	 * Write the public key into the supplied FDT file; this might fail
 	 * several times, since we try signing with successively increasing
-	 * size values */
+	 * size values
+	 */
 	if (keydest && ret)
 		return ret;
 
-- 
cgit v0.10.2


From 5923c843ba0e06a90e0c0c5cc6894ac8641377e1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 22 Jul 2016 09:22:45 -0600
Subject: sandbox: Add instructions about building on 32-bit machines

Sandbox is built with 64-bit ints by default. This doesn't work properly on
32-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index 9fe3bf1..ed820d3 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -44,6 +44,9 @@ Note:
       make sandbox_defconfig all NO_SDL=1
       ./u-boot
 
+   If you are building on a 32-bit machine you may get errors from __ffs.h
+   about shifting more than the machine word size. Edit the config file
+   include/configs/sandbox.h and change CONFIG_SANDBOX_BITS_PER_LONG to 32.
 
 U-Boot will start on your computer, showing a sandbox emulation of the serial
 console:
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 4de89f8..197d8bb 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -27,7 +27,10 @@
 
 #define CONFIG_SYS_STDIO_DEREGISTER
 
-/* Number of bits in a C 'long' on this architecture */
+/*
+ * Number of bits in a C 'long' on this architecture. Set this to 32 when
+ * building on a 32-bit machine.
+ */
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
 
 #define CONFIG_LMB
-- 
cgit v0.10.2


From 1bb718cdabc0f581e2b3ca1134883ee57d3a910d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 22 Jul 2016 09:22:46 -0600
Subject: lzmadec: Use the same type as the lzma call

With sandbox on 32-bit the size_t type can be a little inconsistent. Use
the same type as the caller expects to avoid a compiler warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/cmd/lzmadec.c b/cmd/lzmadec.c
index 1ad9ed6..c78df82 100644
--- a/cmd/lzmadec.c
+++ b/cmd/lzmadec.c
@@ -20,7 +20,7 @@
 static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	unsigned long src, dst;
-	unsigned long src_len = ~0UL, dst_len = ~0UL;
+	SizeT src_len = ~0UL, dst_len = ~0UL;
 	int ret;
 
 	switch (argc) {
@@ -40,7 +40,8 @@ static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 
 	if (ret != SZ_OK)
 		return 1;
-	printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len);
+	printf("Uncompressed size: %ld = %#lX\n", (ulong)src_len,
+	       (ulong)src_len);
 	setenv_hex("filesize", src_len);
 
 	return 0;
-- 
cgit v0.10.2


From 5afb8d151f5249914152dfdc7919a3a46b6b6a76 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 22 Jul 2016 09:22:47 -0600
Subject: part_efi: Fix compiler warning on 32-bit sandbox

This fixes a mismatch between the %zu format and the type used on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/disk/part_efi.c b/disk/part_efi.c
index 0af1e92..01f71be 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -886,9 +886,10 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
 	count = le32_to_cpu(pgpt_head->num_partition_entries) *
 		le32_to_cpu(pgpt_head->sizeof_partition_entry);
 
-	debug("%s: count = %u * %u = %zu\n", __func__,
+	debug("%s: count = %u * %u = %lu\n", __func__,
 	      (u32) le32_to_cpu(pgpt_head->num_partition_entries),
-	      (u32) le32_to_cpu(pgpt_head->sizeof_partition_entry), count);
+	      (u32) le32_to_cpu(pgpt_head->sizeof_partition_entry),
+	      (ulong)count);
 
 	/* Allocate memory for PTE, remember to FREE */
 	if (count != 0) {
@@ -897,9 +898,8 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
 	}
 
 	if (count == 0 || pte == NULL) {
-		printf("%s: ERROR: Can't allocate 0x%zX "
-		       "bytes for GPT Entries\n",
-			__func__, count);
+		printf("%s: ERROR: Can't allocate %#lX bytes for GPT Entries\n",
+		       __func__, (ulong)count);
 		return NULL;
 	}
 
-- 
cgit v0.10.2


From c55d02b2aca9b477dcf4c81062cc8e301d8c89d8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 22 Jul 2016 09:22:48 -0600
Subject: hashtable: Fix compiler warning on 32-bit sandbox

This fixes a mismatch between the %zu format and the type used on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/lib/hashtable.c b/lib/hashtable.c
index 435e2a6..4e52b36 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -602,8 +602,8 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, int flag,
 		return (-1);
 	}
 
-	debug("EXPORT  table = %p, htab.size = %d, htab.filled = %d, "
-		"size = %zu\n", htab, htab->size, htab->filled, size);
+	debug("EXPORT  table = %p, htab.size = %d, htab.filled = %d, size = %lu\n",
+	      htab, htab->size, htab->filled, (ulong)size);
 	/*
 	 * Pass 1:
 	 * search used entries,
@@ -657,8 +657,8 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, int flag,
 	/* Check if the user supplied buffer size is sufficient */
 	if (size) {
 		if (size < totlen + 1) {	/* provided buffer too small */
-			printf("Env export buffer too small: %zu, "
-				"but need %zu\n", size, totlen + 1);
+			printf("Env export buffer too small: %lu, but need %lu\n",
+			       (ulong)size, (ulong)totlen + 1);
 			__set_errno(ENOMEM);
 			return (-1);
 		}
@@ -790,7 +790,7 @@ int himport_r(struct hsearch_data *htab,
 
 	/* we allocate new space to make sure we can write to the array */
 	if ((data = malloc(size + 1)) == NULL) {
-		debug("himport_r: can't malloc %zu bytes\n", size + 1);
+		debug("himport_r: can't malloc %lu bytes\n", (ulong)size + 1);
 		__set_errno(ENOMEM);
 		return 0;
 	}
-- 
cgit v0.10.2


From d6a33918fb50fe2f3917b400cb84220b1d7e4392 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 22 Jul 2016 09:22:49 -0600
Subject: dtoc: Correct the type widening code in fdt_fallback

This code does not match the fdt version in fdt.py. When dtoc is unable to
use the Python libfdt library, it uses the fallback version, which does not
widen arrays correctly.

Fix this to avoid a warning 'excess elements in array initialize' in
dt-platdata.c which happens on some platforms.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com>

diff --git a/tools/dtoc/fdt_fallback.py b/tools/dtoc/fdt_fallback.py
index 14decf3..9ed11e4 100644
--- a/tools/dtoc/fdt_fallback.py
+++ b/tools/dtoc/fdt_fallback.py
@@ -71,6 +71,12 @@ class Prop:
         if type(newprop.value) == list and type(self.value) != list:
             self.value = newprop.value
 
+        if type(self.value) == list and len(newprop.value) > len(self.value):
+            val = fdt_util.GetEmpty(self.type)
+            while len(self.value) < len(newprop.value):
+                self.value.append(val)
+
+
 class Node:
     """A device tree node
 
-- 
cgit v0.10.2


From e312e745db7bcde95c759986d218e8ab5259f64f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 25 Jul 2016 22:06:08 +0900
Subject: arm64: thunderx_88xx_defconfig: remove unneeded
 CONFIG_SYS_EXTRA_OPTIONS

ARM64 is correctly select'ed in arch/arm/Kconfig, so this line in
the defconfig is unneeded.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index 4a8655f..28797f9 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_TARGET_THUNDERX_88XX=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
-CONFIG_SYS_EXTRA_OPTIONS="ARM64"
 CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ThunderX_88XX> "
-- 
cgit v0.10.2


From b60038ccabff484172bd39098afc7f7af3b9b3c0 Mon Sep 17 00:00:00 2001
From: Scott Wood <oss@buserror.net>
Date: Tue, 19 Jul 2016 16:26:21 -0500
Subject: powerpc/86xx: Pass -mcpu=7400 to GCC

Without this, GCC uses the toolchain default, which may be incompatible
with -maltivec.

Signed-off-by: Scott Wood <oss@buserror.net>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk
index 69a0b96..aefb0f1 100644
--- a/arch/powerpc/cpu/mpc86xx/config.mk
+++ b/arch/powerpc/cpu/mpc86xx/config.mk
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float
+PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float
-- 
cgit v0.10.2


From d7b60fbfa63431eedccac17674311f0055f323fe Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Date: Fri, 1 Jul 2016 22:47:36 +0300
Subject: splash: Accommodate DM_USB in splash_init_usb()

Current implementation of splash_init_usb() requires usb_stor_scan()
which doesn't exist in case of DM_USB simply because real probing
happens right in usb_init().

So disable usage of usb_stor_scan() in case of DM_USB.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Robert Winkler <robert.winkler@boundarydevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/common/splash_source.c b/common/splash_source.c
index 914f12f..230b2db 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -146,7 +146,11 @@ static int splash_init_usb(void)
 	if (err)
 		return err;
 
-	return usb_stor_scan(1) < 0 ? -ENODEV : 0;
+#ifndef CONFIG_DM_USB
+	err = usb_stor_scan(1) < 0 ? -ENODEV : 0;
+#endif
+
+	return err;
 }
 #else
 static inline int splash_init_usb(void)
-- 
cgit v0.10.2


From 6a056c442f74bca70d6964612912f4a811177957 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 25 Jul 2016 18:18:15 -0400
Subject: sandbox: Migrate CONFIG_I2C_EEPROM

Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago,
but sandbox was skipped.  Leave it off for sandbox_spl where it does not
build, but does not need to be either.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 6a1874a..89ebe92 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -101,6 +101,7 @@ CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_SYSRESET=y
+CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC_OPS=y
 CONFIG_SANDBOX_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 197d8bb..94e024b 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -85,7 +85,6 @@
 #define CONFIG_CMD_SF_TEST
 
 #define CONFIG_I2C_EDID
-#define CONFIG_I2C_EEPROM
 
 /* Memory things - we don't really want a memory test */
 #define CONFIG_SYS_LOAD_ADDR		0x00000000
-- 
cgit v0.10.2


From 4579720412744dd13266a3505bb38ce2da819b4f Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 25 Jul 2016 22:25:52 -0400
Subject: Prepare v2016.09-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/Makefile b/Makefile
index 7ce933c..bccfbaa 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
 #
 
 VERSION = 2016
-PATCHLEVEL = 07
+PATCHLEVEL = 09
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
-- 
cgit v0.10.2


From b47ea79219f1de43fa21456c6c60c8390b8755d2 Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Tue, 12 Jul 2016 19:09:49 +0800
Subject: rockchip: add option to change method of loading u-boot

If we would like to boot from SD card, we have to implement mmc driver
in SPL stage, and get a slightly large SPL binary. Rockchip SoC's
bootrom code has the ability to load spl and u-boot, then boot.

If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to
bootrom in board_init_f(), then bootrom loads u-boot binary.

Loading sequence after rework:
bootrom ==> spl ==> bootrom ==> u-boot

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip:
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c49cc19..cf718fa 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -17,6 +17,14 @@ config ROCKCHIP_RK3036
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+config ROCKCHIP_SPL_BACK_TO_BROM
+	bool "SPL returns to bootrom"
+	default y if ROCKCHIP_RK3036
+	help
+	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
+          SPL will return to the boot rom, which will then load the U-Boot
+          binary to keep going on.
+
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 55567cb..c08d61b 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -7,6 +7,7 @@
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o
 else
 obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
 endif
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 816540e..b07e073 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -10,12 +10,45 @@
 #include <ram.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+	struct udevice *pinctrl;
+	int ret;
+
+    /*
+     * We need to implement sdcard iomux here for the further
+     * initlization, otherwise, it'll hit sdcard command sending
+     * timeout exception.
+     */
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto err;
+	}
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+	if (ret) {
+		debug("%s: Failed to set up SD card\n", __func__);
+		goto err;
+	}
+
+	return 0;
+err:
+	printf("board_init: Error %d\n", ret);
+
+	/* No way to report error here */
+	hang();
+
+	return -1;
+#else
 	return 0;
+#endif
 }
 
 int dram_init(void)
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile
index 97d299d..6095777 100644
--- a/arch/arm/mach-rockchip/rk3036/Makefile
+++ b/arch/arm/mach-rockchip/rk3036/Makefile
@@ -10,4 +10,3 @@ obj-y += syscon_rk3036.o
 endif
 
 obj-y += sdram_rk3036.o
-obj-y += save_boot_param.o
diff --git a/arch/arm/mach-rockchip/rk3036/save_boot_param.S b/arch/arm/mach-rockchip/rk3036/save_boot_param.S
deleted file mode 100644
index 778ec83..0000000
--- a/arch/arm/mach-rockchip/rk3036/save_boot_param.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <linux/linkage.h>
-
-.globl	SAVE_SP_ADDR
-SAVE_SP_ADDR:
-	.word 0
-
-/*
- * void save_boot_params
- *
- * Save sp, lr, r1~r12
- */
-ENTRY(save_boot_params)
-	push	{r1-r12, lr}
-	ldr	r0, =SAVE_SP_ADDR
-	str	sp, [r0]
-	b	save_boot_params_ret		@ back to my caller
-ENDPROC(save_boot_params)
-
-
-.globl back_to_bootrom
-ENTRY(back_to_bootrom)
-	ldr	r0, =SAVE_SP_ADDR
-	ldr	sp, [r0]
-	mov	r0, #0
-	pop	{r1-r12, pc}
-ENDPROC(back_to_bootrom)
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 123f58b..08152aa 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -149,7 +149,7 @@ static int configure_emmc(struct udevice *pinctrl)
 	return 0;
 }
 #endif
-
+extern void back_to_bootrom(void);
 void board_init_f(ulong dummy)
 {
 	struct udevice *pinctrl;
@@ -204,6 +204,9 @@ void board_init_f(ulong dummy)
 		debug("DRAM init failed: %d\n", ret);
 		return;
 	}
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+	back_to_bootrom();
+#endif
 }
 
 static int setup_led(void)
diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S
new file mode 100644
index 0000000..85b407b
--- /dev/null
+++ b/arch/arm/mach-rockchip/save_boot_param.S
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+.globl	SAVE_SP_ADDR
+SAVE_SP_ADDR:
+	.word 0
+
+/*
+ * void save_boot_params
+ *
+ * Save sp, lr, r1~r12
+ */
+ENTRY(save_boot_params)
+	push	{r1-r12, lr}
+	ldr	r0, =SAVE_SP_ADDR
+	str	sp, [r0]
+	b	save_boot_params_ret		@ back to my caller
+ENDPROC(save_boot_params)
+
+
+.globl back_to_bootrom
+ENTRY(back_to_bootrom)
+	ldr	r0, =SAVE_SP_ADDR
+	ldr	sp, [r0]
+	mov	r0, #0
+	pop	{r1-r12, pc}
+ENDPROC(back_to_bootrom)
diff --git a/doc/README.rockchip b/doc/README.rockchip
index e0572c8..182e3ae 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -119,6 +119,20 @@ something like:
    Hit any key to stop autoboot:  0
    =>
 
+The rockchip bootrom can load and boot an initial spl, then continue to
+load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom.
+Therefore RK3288 has another loading sequence like RK3036. The option of
+U-Boot is controlled with this setting in U-Boot:
+
+	#define CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+
+You can create the image via the following operations:
+
+   ./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
+	firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
+   cat firefly-rk3288/u-boot-dtb.bin >> out && \
+   sudo dd if=out of=/dev/sdc seek=64
+
 If you have an HDMI cable attached you should see a video console.
 
 For evb_rk3036 board:
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 8adc26f..90473bf 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -33,7 +33,12 @@
 #define CONFIG_SYS_NS16550_MEM32
 #define CONFIG_SPL_BOARD_INIT
 
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* Bootrom will load u-boot binary to 0x0 once return from SPL */
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x00100000
+#endif
 #define CONFIG_SYS_INIT_SP_ADDR		0x00100000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff718000
-- 
cgit v0.10.2


From 744368d6ae3ea5cf73407c24d8e44b2a83b7f659 Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Tue, 5 Jul 2016 18:06:30 +0800
Subject: rockchip: add basic support for evb-rk3288 board

evb-3288 board RK3288-based development board with 2 USB ports, HDMI,
VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes
on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to
display pins, I2C, SPI, UART and GPIOs. This add some basic files
required to allow the board to output serial messaged and can run
command(mmc info etc).

evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ca8712a..88741e5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-firefly.dtb \
 	rk3288-jerry.dtb \
 	rk3288-rock2-square.dtb \
+	rk3288-evb.dtb \
 	rk3036-sdk.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxbb-odroidc2.dtb
diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
new file mode 100644
index 0000000..caf24ee
--- /dev/null
+++ b/arch/arm/dts/rk3288-evb.dts
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-evb.dtsi"
+
+/ {
+	model = "Evb-RK3288";
+	compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&dmc {
+	rockchip,num-channels = <2>;
+	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+		0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+		0x8 0x1f4>;
+	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+		0x0 0xc3 0x6 0x2>;
+	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe>;
+	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	reg-shift = <2>;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi
new file mode 100644
index 0000000..cb7d03e
--- /dev/null
+++ b/arch/arm/dts/rk3288-evb.dtsi
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ X11
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+	memory {
+		reg = <0 0x80000000>;
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		button@0 {
+			gpio-key,wakeup = <1>;
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Power";
+			linux,code = <116>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwr_key>;
+		};
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_5v: usb-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_host_5v: usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&vcc_5v>;
+	};
+
+	vcc_otg_5v: usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		regulator-name = "vcc_otg_5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&vcc_5v>;
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+	broken-cd;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_flash>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c5>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	vdd_cpu: syr827@40 {
+		compatible = "silergy,syr827";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x40>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x41>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		interrupt-parent = <&gpio7>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_hold>;
+		system-power-controller;
+
+		regulators {
+			vcc_ddr: REG1 {
+				regulator-name = "vcc_ddr";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			vcc_io: REG2 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd_log: REG3 {
+				regulator-name = "vdd_log";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			vcc_20: REG4 {
+				regulator-name = "vcc_20";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+			};
+
+			vccio_sd: REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd10_lcd: REG6 {
+				regulator-name = "vdd10_lcd";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vcca_codec: REG7 {
+				regulator-name = "vcca_codec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vcc_tp: REG8 {
+				regulator-name = "vcca_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vccio_pmu: REG9 {
+				regulator-name = "vccio_pmu";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vdd_10: REG10 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vcc_18: REG11 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			vcc18_lcd: REG12 {
+				regulator-name = "vcc18_lcd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pinctrl {
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	act8846 {
+		pwr_hold: pwr-hold {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	hym8563 {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	keys {
+		pwr_key: pwr-key {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_host {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_otg {
+		otg_vbus_drv: otg-vbus-drv {
+			rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+&sdio0 {
+	broken-cd;
+	bus-width = <4>;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>;
+	vmmc-supply = <&vcc_18>;
+	status = "disabled";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	vmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&usb_host1 {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 08152aa..d82115f 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -251,7 +251,8 @@ void spl_board_init(void)
 	}
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	if (!IS_ENABLED(CONFIG_TARGET_ROCK2) &&
-	    !IS_ENABLED(CONFIG_TARGET_FIREFLY_RK3288)) {
+	    !IS_ENABLED(CONFIG_TARGET_FIREFLY_RK3288) &&
+	    !IS_ENABLED(CONFIG_TARGET_EVB_RK3288)) {
 		ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
 		if (ret) {
 			debug("%s: Failed to set up SD card\n", __func__);
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 7215624..031dbfc 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -8,6 +8,14 @@ config TARGET_FIREFLY_RK3288
 	  also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
 	  provide access to display pins, I2C, SPI, UART and GPIOs.
 
+config TARGET_EVB_RK3288
+	bool "Evb-RK3288"
+	help
+	  EVB-RK3288 is a RK3288-based development board with 2 USB ports,
+	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
+	  also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
 config TARGET_CHROMEBOOK_JERRY
 	bool "Google/Rockchip Veyron-Jerry Chromebook"
 	help
@@ -45,4 +53,6 @@ source "board/firefly/firefly-rk3288/Kconfig"
 
 source "board/radxa/rock2/Kconfig"
 
+source "board/evb-rk3288/evb-rk3288/Kconfig"
+
 endif
diff --git a/board/evb-rk3288/evb-rk3288/Kconfig b/board/evb-rk3288/evb-rk3288/Kconfig
new file mode 100644
index 0000000..b201acb
--- /dev/null
+++ b/board/evb-rk3288/evb-rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3288
+
+config SYS_BOARD
+	default "evb-rk3288"
+
+config SYS_VENDOR
+	default "evb-rk3288"
+
+config SYS_CONFIG_NAME
+	default "evb-rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/evb-rk3288/evb-rk3288/MAINTAINERS b/board/evb-rk3288/evb-rk3288/MAINTAINERS
new file mode 100644
index 0000000..222c254
--- /dev/null
+++ b/board/evb-rk3288/evb-rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/evb-rk3288/evb-rk3288
+F:	include/configs/evb-rk3288.h
+F:	configs/evb-rk3288_defconfig
diff --git a/board/evb-rk3288/evb-rk3288/Makefile b/board/evb-rk3288/evb-rk3288/Makefile
new file mode 100644
index 0000000..c11b657
--- /dev/null
+++ b/board/evb-rk3288/evb-rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3288.o
diff --git a/board/evb-rk3288/evb-rk3288/evb-rk3288.c b/board/evb-rk3288/evb-rk3288/evb-rk3288.c
new file mode 100644
index 0000000..a82f0ae
--- /dev/null
+++ b/board/evb-rk3288/evb-rk3288/evb-rk3288.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* eMMC prior to sdcard. */
+	spl_boot_list[0] = BOOT_DEVICE_MMC2;
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
new file mode 100644
index 0000000..41cfedd
--- /dev/null
+++ b/configs/evb-rk3288_defconfig
@@ -0,0 +1,67 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_EVB_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_DM_MMC=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 182e3ae..3fc2582 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -36,11 +36,12 @@ You will need:
 Building
 ========
 
-At present three RK3288 boards are supported:
+At present four RK3288 boards are supported:
 
    - Firefly RK3288 - use firefly-rk3288 configuration
    - Radxa Rock 2 - use rock2 configuration
    - Hisense Chromebook - use chromebook_jerry configuration
+   - EVB RK3288 - use evb-rk3288 configuration
 
 Two RK3036 board are supported:
 
diff --git a/include/configs/evb-rk3288.h b/include/configs/evb-rk3288.h
new file mode 100644
index 0000000..342557f
--- /dev/null
+++ b/include/configs/evb-rk3288.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
-- 
cgit v0.10.2


From c418addfa9e758b05531eb37498c6fa0317d2c64 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 8 Jul 2016 11:30:58 +0800
Subject: board: move all the rockchip board in one folder

The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them
to 'rockchip' which is a real _vendor_ name, and meet the architecure
'board/<vendor>/<board-name>/'.

More boards from rockchip like evb_rk3288, evb_rk3399 will comes later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>

diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index cc038088..f7562bd 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -15,7 +15,7 @@ config SYS_MALLOC_F_LEN
 config ROCKCHIP_COMMON
 	bool "Support rk common fuction"
 
-source "board/evb_rk3036/evb_rk3036/Kconfig"
-source "board/kylin/kylin_rk3036/Kconfig"
+source "board/rockchip/evb_rk3036/Kconfig"
+source "board/rockchip/kylin_rk3036/Kconfig"
 
 endif
diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/evb_rk3036/evb_rk3036/Kconfig
deleted file mode 100644
index ae2a9eb..0000000
--- a/board/evb_rk3036/evb_rk3036/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_EVB_RK3036
-
-config SYS_BOARD
-	default "evb_rk3036"
-
-config SYS_VENDOR
-	default "evb_rk3036"
-
-config SYS_CONFIG_NAME
-	default "evb_rk3036"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/evb_rk3036/evb_rk3036/MAINTAINERS
deleted file mode 100644
index 152d31c..0000000
--- a/board/evb_rk3036/evb_rk3036/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EVB-RK3036
-M:      huang lin <hl@rock-chips.com>
-S:      Maintained
-F:      board/evb/evb-rk3036
-F:      include/configs/evb-rk3036.h
-F:      configs/evb-rk3036_defconfig
diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/evb_rk3036/evb_rk3036/Makefile
deleted file mode 100644
index 0403836..0000000
--- a/board/evb_rk3036/evb_rk3036/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Google, Inc
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= evb_rk3036.o
diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/evb_rk3036/evb_rk3036/evb_rk3036.c
deleted file mode 100644
index f5758b1..0000000
--- a/board/evb_rk3036/evb_rk3036/evb_rk3036.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/sdram_rk3036.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void get_ddr_config(struct rk3036_ddr_config *config)
-{
-	/* K4B4G1646Q config */
-	config->ddr_type = 3;
-	config->rank = 2;
-	config->cs0_row = 15;
-	config->cs1_row = 15;
-
-	/* 8bank */
-	config->bank = 3;
-	config->col = 10;
-
-	/* 16bit bw */
-	config->bw = 1;
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/kylin/kylin_rk3036/Kconfig
deleted file mode 100644
index 5d75c1f..0000000
--- a/board/kylin/kylin_rk3036/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_KYLIN_RK3036
-
-config SYS_BOARD
-	default "kylin_rk3036"
-
-config SYS_VENDOR
-	default "kylin"
-
-config SYS_CONFIG_NAME
-	default "kylin_rk3036"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS
deleted file mode 100644
index f8ee834..0000000
--- a/board/kylin/kylin_rk3036/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KYLIN-RK3036
-M:      huang lin <hl@rock-chips.com>
-S:      Maintained
-F:      board/kylin/kylin-rk3036
-F:      include/configs/kylin-rk3036.h
-F:      configs/kylin-rk3036_defconfig
diff --git a/board/kylin/kylin_rk3036/Makefile b/board/kylin/kylin_rk3036/Makefile
deleted file mode 100644
index 0663270..0000000
--- a/board/kylin/kylin_rk3036/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Google, Inc
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= kylin_rk3036.o
diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/kylin/kylin_rk3036/kylin_rk3036.c
deleted file mode 100644
index 2a25871..0000000
--- a/board/kylin/kylin_rk3036/kylin_rk3036.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <asm/arch-rockchip/grf_rk3036.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define GRF_BASE	0x20008000
-
-void get_ddr_config(struct rk3036_ddr_config *config)
-{
-	/* K4B4G1646Q config */
-	config->ddr_type = 3;
-	config->rank = 1;
-	config->cs0_row = 15;
-	config->cs1_row = 15;
-
-	/* 8bank */
-	config->bank = 3;
-	config->col = 10;
-
-	/* 16bit bw */
-	config->bw = 1;
-}
-
-#define FASTBOOT_KEY_GPIO 93
-
-int fastboot_key_pressed(void)
-{
-	gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
-	gpio_direction_input(FASTBOOT_KEY_GPIO);
-	return !gpio_get_value(FASTBOOT_KEY_GPIO);
-}
-
-#define ROCKCHIP_BOOT_MODE_FASTBOOT	0x5242C309
-
-int board_late_init(void)
-{
-	struct rk3036_grf * const grf = (void *)GRF_BASE;
-	int boot_mode = readl(&grf->os_reg[4]);
-
-	/* Clear boot mode */
-	writel(0, &grf->os_reg[4]);
-
-	if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
-	    fastboot_key_pressed()) {
-		printf("enter fastboot!\n");
-		setenv("preboot", "setenv preboot; fastboot usb0");
-	}
-
-	return 0;
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/board/rockchip/evb_rk3036/Kconfig b/board/rockchip/evb_rk3036/Kconfig
new file mode 100644
index 0000000..ef45f62
--- /dev/null
+++ b/board/rockchip/evb_rk3036/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3036
+
+config SYS_BOARD
+	default "evb_rk3036"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3036"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3036/MAINTAINERS
new file mode 100644
index 0000000..152d31c
--- /dev/null
+++ b/board/rockchip/evb_rk3036/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3036
+M:      huang lin <hl@rock-chips.com>
+S:      Maintained
+F:      board/evb/evb-rk3036
+F:      include/configs/evb-rk3036.h
+F:      configs/evb-rk3036_defconfig
diff --git a/board/rockchip/evb_rk3036/Makefile b/board/rockchip/evb_rk3036/Makefile
new file mode 100644
index 0000000..0403836
--- /dev/null
+++ b/board/rockchip/evb_rk3036/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rk3036.o
diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c
new file mode 100644
index 0000000..f5758b1
--- /dev/null
+++ b/board/rockchip/evb_rk3036/evb_rk3036.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/sdram_rk3036.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void get_ddr_config(struct rk3036_ddr_config *config)
+{
+	/* K4B4G1646Q config */
+	config->ddr_type = 3;
+	config->rank = 2;
+	config->cs0_row = 15;
+	config->cs1_row = 15;
+
+	/* 8bank */
+	config->bank = 3;
+	config->col = 10;
+
+	/* 16bit bw */
+	config->bw = 1;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = sdram_size();
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/board/rockchip/kylin_rk3036/Kconfig b/board/rockchip/kylin_rk3036/Kconfig
new file mode 100644
index 0000000..8d35b4e
--- /dev/null
+++ b/board/rockchip/kylin_rk3036/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KYLIN_RK3036
+
+config SYS_BOARD
+	default "kylin_rk3036"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "kylin_rk3036"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/kylin_rk3036/MAINTAINERS b/board/rockchip/kylin_rk3036/MAINTAINERS
new file mode 100644
index 0000000..f8ee834
--- /dev/null
+++ b/board/rockchip/kylin_rk3036/MAINTAINERS
@@ -0,0 +1,6 @@
+KYLIN-RK3036
+M:      huang lin <hl@rock-chips.com>
+S:      Maintained
+F:      board/kylin/kylin-rk3036
+F:      include/configs/kylin-rk3036.h
+F:      configs/kylin-rk3036_defconfig
diff --git a/board/rockchip/kylin_rk3036/Makefile b/board/rockchip/kylin_rk3036/Makefile
new file mode 100644
index 0000000..0663270
--- /dev/null
+++ b/board/rockchip/kylin_rk3036/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= kylin_rk3036.o
diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c
new file mode 100644
index 0000000..2a25871
--- /dev/null
+++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
+#include <asm/arch/sdram_rk3036.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE	0x20008000
+
+void get_ddr_config(struct rk3036_ddr_config *config)
+{
+	/* K4B4G1646Q config */
+	config->ddr_type = 3;
+	config->rank = 1;
+	config->cs0_row = 15;
+	config->cs1_row = 15;
+
+	/* 8bank */
+	config->bank = 3;
+	config->col = 10;
+
+	/* 16bit bw */
+	config->bw = 1;
+}
+
+#define FASTBOOT_KEY_GPIO 93
+
+int fastboot_key_pressed(void)
+{
+	gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
+	gpio_direction_input(FASTBOOT_KEY_GPIO);
+	return !gpio_get_value(FASTBOOT_KEY_GPIO);
+}
+
+#define ROCKCHIP_BOOT_MODE_FASTBOOT	0x5242C309
+
+int board_late_init(void)
+{
+	struct rk3036_grf * const grf = (void *)GRF_BASE;
+	int boot_mode = readl(&grf->os_reg[4]);
+
+	/* Clear boot mode */
+	writel(0, &grf->os_reg[4]);
+
+	if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
+	    fastboot_key_pressed()) {
+		printf("enter fastboot!\n");
+		setenv("preboot", "setenv preboot; fastboot usb0");
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = sdram_size();
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
-- 
cgit v0.10.2


From e0f5dbcb4b8cfe277d06acc0cdc0ba22c0d3d3d0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Thu, 14 Jul 2016 05:09:26 +0200
Subject: rockchip: Clean up CPU selection
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In preparation for RK3368 and RK3399, which need to select ARM64, don't
select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 397981a..5c19924 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -843,7 +843,6 @@ config ARCH_ROCKCHIP
 	select SUPPORT_SPL
 	select SPL
 	select OF_CONTROL
-	select CPU_V7
 	select BLK
 	select DM
 	select SPL_DM
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index cf718fa..86b77f8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -2,6 +2,7 @@ if ARCH_ROCKCHIP
 
 config ROCKCHIP_RK3288
 	bool "Support Rockchip RK3288"
+	select CPU_V7
 	help
 	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
 	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
@@ -11,6 +12,7 @@ config ROCKCHIP_RK3288
 
 config ROCKCHIP_RK3036
 	bool "Support Rockchip RK3036"
+	select CPU_V7
 	help
 	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
 	  including NEON and GPU, Mali-400 graphics, several DDR3 options
-- 
cgit v0.10.2


From 5f30bf764ba496ca9921d4242715dfd8d761f4cf Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Thu, 14 Jul 2016 11:51:05 +0800
Subject: mkimage: rockchip: add suport for rk33 serial

Add support for rockchip rk33 series Soc like rk3368 and rk3399

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 72621fd..9ec7eb2 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -56,6 +56,7 @@ struct spl_info {
 static struct spl_info spl_infos[] = {
 	{ "rk3036", "RK30", 0x1000 },
 	{ "rk3288", "RK32", 0x8000 },
+	{ "rk33xx", "RK33", 0x20000 },
 };
 
 static unsigned char rc4_key[16] = {
-- 
cgit v0.10.2


From ad8fe6b96432d17aca224167338c68dc2f0cf2ae Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Thu, 14 Jul 2016 06:22:09 +0200
Subject: rockchip: Exclude rk_timer for ARM64
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

It conflicts with the generic_timer.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c08d61b..6763af4 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o
 else
 obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
 endif
+ifndef CONFIG_ARM64
 obj-y += rk_timer.o
+endif
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
-- 
cgit v0.10.2


From fab3357916096d4c61a5e2fe5d28f5aeb78c6957 Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Thu, 14 Jul 2016 14:52:32 +0800
Subject: usb: rockchip-phy: implement USB2.0 phy control

So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and
Innosilicon. This patch applys dwc2 usb driver framework to implement
phy_init() and phy_off() methods for Synopsys phy on Rockchip platform.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 93d147e..4e548c2 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_TWL4030_USB) += twl4030.o
 obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
+obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c
new file mode 100644
index 0000000..1958478
--- /dev/null
+++ b/drivers/usb/phy/rockchip_usb2_phy.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <libfdt.h>
+
+#include "../gadget/dwc2_udc_otg_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT_WRITEABLE_SHIFT	16
+
+struct usb2phy_reg {
+	unsigned int offset;
+	unsigned int bitend;
+	unsigned int bitstart;
+	unsigned int disable;
+	unsigned int enable;
+};
+
+/**
+ * struct rockchip_usb2_phy_cfg: usb-phy port configuration
+ * @port_reset: usb otg per-port reset register
+ * @soft_con: software control usb otg register
+ * @suspend: phy suspend register
+ */
+struct rockchip_usb2_phy_cfg {
+	struct usb2phy_reg port_reset;
+	struct usb2phy_reg soft_con;
+	struct usb2phy_reg suspend;
+};
+
+struct rockchip_usb2_phy_dt_id {
+	char		compatible[128];
+	const void	*data;
+};
+
+static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
+	.port_reset     = {0x00, 12, 12, 0, 1},
+	.soft_con       = {0x08, 2, 2, 0, 1},
+	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
+};
+
+static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
+	{}
+};
+
+static void property_enable(struct dwc2_plat_otg_data *pdata,
+				  const struct usb2phy_reg *reg, bool en)
+{
+	unsigned int val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	writel(val, pdata->regs_phy + reg->offset);
+}
+
+
+void otg_phy_init(struct dwc2_udc *dev)
+{
+	struct dwc2_plat_otg_data *pdata = dev->pdata;
+	struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
+	struct rockchip_usb2_phy_dt_id *of_id;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
+		of_id = &rockchip_usb2_phy_dt_ids[i];
+		if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node,
+					      of_id->compatible) == 0) {
+			phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
+			break;
+		}
+	}
+	if (!phy_cfg) {
+		debug("Can't find device platform data\n");
+
+		hang();
+		return;
+	}
+	pdata->priv = phy_cfg;
+	/* disable software control */
+	property_enable(pdata, &phy_cfg->soft_con, false);
+
+	/* reset otg port */
+	property_enable(pdata, &phy_cfg->port_reset, true);
+	mdelay(1);
+	property_enable(pdata, &phy_cfg->port_reset, false);
+	udelay(1);
+}
+
+void otg_phy_off(struct dwc2_udc *dev)
+{
+	struct dwc2_plat_otg_data *pdata = dev->pdata;
+	struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
+
+	/* enable software control */
+	property_enable(pdata, &phy_cfg->soft_con, true);
+	/* enter suspend */
+	property_enable(pdata, &phy_cfg->suspend, true);
+}
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index 302e9a3..3ce43f8 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -12,6 +12,8 @@
 #define PHY0_SLEEP              (1 << 5)
 
 struct dwc2_plat_otg_data {
+	void		*priv;
+	int		phy_of_node;
 	int		(*phy_control)(int on);
 	unsigned int	regs_phy;
 	unsigned int	regs_otg;
-- 
cgit v0.10.2


From 47117882671fbfb5ffa20cd25ec29da5b7143009 Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Thu, 14 Jul 2016 14:52:33 +0800
Subject: usb: dwc2-otg: adjust fifo size via platform data

The total FIFO size of some SoCs may be different from the existen, this
patch supports fifo size setting from platform data.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index a23278d..029927f 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -403,6 +403,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	int i;
 	unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
 	uint32_t dflt_gusbcfg;
+	uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
 
 	debug("Reseting OTG controller\n");
 
@@ -467,18 +468,27 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	/* 10. Unmask device IN EP common interrupts*/
 	writel(DIEPMSK_INIT, &reg->diepmsk);
 
+	rx_fifo_sz = RX_FIFO_SIZE;
+	np_tx_fifo_sz = NPTX_FIFO_SIZE;
+	tx_fifo_sz = PTX_FIFO_SIZE;
+
+	if (dev->pdata->rx_fifo_sz)
+		rx_fifo_sz = dev->pdata->rx_fifo_sz;
+	if (dev->pdata->np_tx_fifo_sz)
+		np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
+	if (dev->pdata->tx_fifo_sz)
+		tx_fifo_sz = dev->pdata->tx_fifo_sz;
+
 	/* 11. Set Rx FIFO Size (in 32-bit words) */
-	writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
+	writel(rx_fifo_sz, &reg->grxfsiz);
 
 	/* 12. Set Non Periodic Tx FIFO Size */
-	writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
+	writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
 	       &reg->gnptxfsiz);
 
 	for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
-		writel((PTX_FIFO_SIZE >> 2) << 16 |
-		       ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
-			 PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
-		       &reg->dieptxf[i-1]);
+		writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
+			tx_fifo_sz << 16, &reg->dieptxf[i-1]);
 
 	/* Flush the RX FIFO */
 	writel(RX_FIFO_FLUSH, &reg->grstctl);
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index 78ec90e..c94396a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -130,9 +130,9 @@ struct dwc2_usbotg_reg {
 #define HIGH_SPEED_CONTROL_PKT_SIZE	64
 #define HIGH_SPEED_BULK_PKT_SIZE	512
 
-#define RX_FIFO_SIZE			(1024*4)
-#define NPTX_FIFO_SIZE			(1024*4)
-#define PTX_FIFO_SIZE			(1536*1)
+#define RX_FIFO_SIZE			(1024)
+#define NPTX_FIFO_SIZE			(1024)
+#define PTX_FIFO_SIZE			(384)
 
 #define DEPCTL_TXFNUM_0		(0x0<<22)
 #define DEPCTL_TXFNUM_1		(0x1<<22)
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index 3ce43f8..7324d8a 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -20,6 +20,9 @@ struct dwc2_plat_otg_data {
 	unsigned int    usb_phy_ctrl;
 	unsigned int    usb_flags;
 	unsigned int	usb_gusbcfg;
+	unsigned int	rx_fifo_sz;
+	unsigned int	np_tx_fifo_sz;
+	unsigned int	tx_fifo_sz;
 };
 
 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata);
-- 
cgit v0.10.2


From 9424f1418377bfb0c95ed36a8854e7fe53436229 Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Thu, 14 Jul 2016 14:52:35 +0800
Subject: usb: dwc2 : invalidate dcache before starting DMA

Invalidate dcache before starting the DMA to ensure coherency. In case
there are any dirty lines from the DMA buffer in the cache, subsequent
cache-line replacements may corrupt the buffer in memory while the DMA
is still going on. Cache-line replacement can happen if the CPU tries to
bring some other memory locations into the cache while the DMA is going
on.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 12f5c85..0d6d2fb 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -110,6 +110,9 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
 
 	ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 
+	invalidate_dcache_range((unsigned long) ep->dma_buf,
+				(unsigned long) ep->dma_buf + ep->len);
+
 	writel((unsigned int) ep->dma_buf, &reg->out_endp[ep_num].doepdma);
 	writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 	       &reg->out_endp[ep_num].doeptsiz);
-- 
cgit v0.10.2


From 266c8fad51c20c8c8a641696ac1d8d8dea58d700 Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Fri, 15 Jul 2016 00:26:59 +0800
Subject: rockchip: rk3288: add fastboot support

Enable fastboot feature on rk3288.

This path doesn't support the fastboot flash function command entirely.
We will hit "cannot find partition" assertion without specified
partition environment. Define gpt partition layout in specified board
such as firefly-rk3288, then enjoy it!

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 3dab0fc..bcf051a 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -454,6 +454,7 @@
 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_OTG0>;
 		clock-names = "otg";
+		dr_mode = "otg";
 		phys = <&usbphy0>;
 		phy-names = "usb2-phy";
 		status = "disabled";
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index b07e073..f662b26 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -85,6 +85,78 @@ void lowlevel_init(void)
 {
 }
 
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3288_otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node, phy_node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+	u32 grf_phy_offset;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3288-usb");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+					"rockchip,rk3288-usb");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	node = fdtdec_lookup_phandle(blob, node, "phys");
+	if (node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	phy_node = fdt_parent_offset(blob, node);
+	if (phy_node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	rk3288_otg_data.phy_of_node = phy_node;
+	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
+
+	/* find the grf node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3288-grf");
+	if (node <= 0) {
+		debug("Not found grf device\n");
+		return -ENODEV;
+	}
+	rk3288_otg_data.regs_phy = grf_phy_offset +
+				fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&rk3288_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
+
 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 90473bf..2a36c17 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -84,6 +84,32 @@
 #define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_ROCKCHIP_USB2_PHY
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+
+/* fastboot  */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	1	/* eMMC */
+/* stroe safely fastboot buffer data to the middle of bank */
+#define CONFIG_FASTBOOT_BUF_ADDR	(CONFIG_SYS_SDRAM_BASE \
+					+ SDRAM_BANK_SIZE / 2)
+#define CONFIG_FASTBOOT_BUF_SIZE	0x08000000
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER	"Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM		0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM	0x320a
+
+/* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
-- 
cgit v0.10.2


From 9f862ec717dd1087c8ccc282d231a3b3bcd608e2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>
Date: Sat, 16 Jul 2016 00:17:13 +0200
Subject: cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming

The rk3288 pinctrl is very specific to this soc, so should
not hog the generic rockchip naming.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index d5bc515..fd5314a 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -53,7 +53,7 @@ CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK808=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index bdafc71..4122000 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -46,7 +46,7 @@ CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 3e16b80..3b6d7d9 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -44,7 +44,7 @@ CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 89ebe92..2067f87 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -120,7 +120,7 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 60c7339..2928da4 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -112,7 +112,7 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1785e3b..85dddd3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -123,12 +123,12 @@ config QCA953X_PINCTRL
 	  both the GPIO definitions and pin control functions for each
 	  available multiplex function.
 
-config ROCKCHIP_PINCTRL
+config ROCKCHIP_RK3288_PINCTRL
 	bool "Rockchip pin control driver"
 	depends on DM
 	help
-	  Support pin multiplexing control on Rockchip SoCs. The driver is
-	  controlled by a device tree node which contains both the GPIO
+	  Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
+	  is controlled by a device tree node which contains both the GPIO
 	  definitions and pin control functions for each available multiplex
 	  function.
 
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 6fa7d00..6a84961 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,5 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
 obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o
-- 
cgit v0.10.2


From 23c3042b106f6f5f92f4b5ec11b3d07eaf35bc06 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>
Date: Sat, 16 Jul 2016 00:17:14 +0200
Subject: cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming

Rockchip socs are always named rkxxxx in all places, as also shown
by the naming of the rk3036 pinctrl file itself.
Therefore also name the config symbol according to this scheme.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 9894fff..2d5e5e0 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -32,7 +32,7 @@ CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
 CONFIG_RAM=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_DEBUG_UART=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 0ff6c6b..51196aa 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -32,7 +32,7 @@ CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
 CONFIG_RAM=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 2067f87..29e6d85 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -121,7 +121,7 @@ CONFIG_PCI_SANDBOX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_ROCKCHIP_RK3288_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 2928da4..503845b 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -113,7 +113,7 @@ CONFIG_PCI_SANDBOX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_ROCKCHIP_RK3288_PINCTRL=y
-CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_RK3036_PINCTRL=y
 CONFIG_PINCTRL_SANDBOX=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 85dddd3..951a922 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -132,7 +132,7 @@ config ROCKCHIP_RK3288_PINCTRL
 	  definitions and pin control functions for each available multiplex
 	  function.
 
-config ROCKCHIP_3036_PINCTRL
+config ROCKCHIP_RK3036_PINCTRL
 	bool "Rockchip rk3036 pin control driver"
 	depends on DM
 	help
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 6a84961..0b2e95e 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -6,4 +6,4 @@
 #
 
 obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
-obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
-- 
cgit v0.10.2


From 041cdb5f3d0fe778546bcf5b8b69e6b774db1d9e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>
Date: Sat, 16 Jul 2016 00:17:15 +0200
Subject: cosmetic: rockchip: sort socs according to numbers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 86b77f8..a3faafe 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -1,5 +1,14 @@
 if ARCH_ROCKCHIP
 
+config ROCKCHIP_RK3036
+	bool "Support Rockchip RK3036"
+	select CPU_V7
+	help
+	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
+	  including NEON and GPU, Mali-400 graphics, several DDR3 options
+	  and video codec support. Peripherals include Gigabit Ethernet,
+	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
 config ROCKCHIP_RK3288
 	bool "Support Rockchip RK3288"
 	select CPU_V7
@@ -10,15 +19,6 @@ config ROCKCHIP_RK3288
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
 
-config ROCKCHIP_RK3036
-	bool "Support Rockchip RK3036"
-	select CPU_V7
-	help
-	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
-	  including NEON and GPU, Mali-400 graphics, several DDR3 options
-	  and video codec support. Peripherals include Gigabit Ethernet,
-	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
-
 config ROCKCHIP_SPL_BACK_TO_BROM
 	bool "SPL returns to bootrom"
 	default y if ROCKCHIP_RK3036
@@ -27,6 +27,6 @@ config ROCKCHIP_SPL_BACK_TO_BROM
           SPL will return to the boot rom, which will then load the U-Boot
           binary to keep going on.
 
-source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3288/Kconfig"
 endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 6763af4..722b582 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -5,8 +5,8 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
 obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o
 else
 obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
@@ -14,5 +14,5 @@ endif
 ifndef CONFIG_ARM64
 obj-y += rk_timer.o
 endif
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 951a922..2972dba 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -123,21 +123,21 @@ config QCA953X_PINCTRL
 	  both the GPIO definitions and pin control functions for each
 	  available multiplex function.
 
-config ROCKCHIP_RK3288_PINCTRL
-	bool "Rockchip pin control driver"
+config ROCKCHIP_RK3036_PINCTRL
+	bool "Rockchip rk3036 pin control driver"
 	depends on DM
 	help
-	  Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
-	  is controlled by a device tree node which contains both the GPIO
+	  Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
+	  controlled by a device tree node which contains both the GPIO
 	  definitions and pin control functions for each available multiplex
 	  function.
 
-config ROCKCHIP_RK3036_PINCTRL
-	bool "Rockchip rk3036 pin control driver"
+config ROCKCHIP_RK3288_PINCTRL
+	bool "Rockchip pin control driver"
 	depends on DM
 	help
-	  Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
-	  controlled by a device tree node which contains both the GPIO
+	  Support pin multiplexing control on Rockchip rk3288 SoCs. The driver
+	  is controlled by a device tree node which contains both the GPIO
 	  definitions and pin control functions for each available multiplex
 	  function.
 
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 0b2e95e..64e9587 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,5 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
-- 
cgit v0.10.2


From b339b5dbca4c776a4c138b852082fad2df826410 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>
Date: Sat, 16 Jul 2016 00:17:16 +0200
Subject: cosmetic: rockchip: rk3288: rename rkclk_configure_cpu

The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 317e512..4bebd62 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -65,6 +65,6 @@ void *rockchip_get_cru(void);
 struct rk3288_cru;
 struct rk3288_grf;
 
-void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
 
 #endif
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index b36b6af..fc0f2f3 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -784,7 +784,7 @@ static int veyron_init(struct dram_info *priv)
 		return ret;
 	udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
 
-	rkclk_configure_cpu(priv->cru, priv->grf);
+	rk3288_clk_configure_cpu(priv->cru, priv->grf);
 
 	return 0;
 }
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 679f010..dece4bc 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -447,7 +447,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 }
 #endif
 
-void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 {
 	/* pll enter slow-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
-- 
cgit v0.10.2


From c3f03ffbe31ae886f0eb670edf47fc208d667c19 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>
Date: Sat, 16 Jul 2016 00:17:17 +0200
Subject: rockchip: rk3288: fix FREF_MIN_HZ constant

According to the TRM the minimum FREF frequency is 269kHz not MHz.
Adapt the constant accordingly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index dece4bc..a41cf8b 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -47,7 +47,7 @@ enum {
 	OUTPUT_MAX_HZ	= 2200U * 1000000,
 	OUTPUT_MIN_HZ	= 27500000,
 	FREF_MAX_HZ	= 2200U * 1000000,
-	FREF_MIN_HZ	= 269 * 1000000,
+	FREF_MIN_HZ	= 269 * 1000,
 };
 
 enum {
-- 
cgit v0.10.2


From c57f806bf2e745c4273dc33c9827781cff46427c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 17 Jul 2016 15:23:15 -0600
Subject: dm: core: Add a way to find a device by its driver

Some SoCs have a single clock device. Provide a way to find it given its
driver name. This is handled by the linker so will fail if the name is not
found, avoiding strange errors when names change and do not match. It is
also faster than a string comparison.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 1141ce1..de602ae 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -311,6 +311,26 @@ static int uclass_find_device_by_phandle(enum uclass_id id,
 }
 #endif
 
+int uclass_get_device_by_driver(enum uclass_id id,
+				const struct driver *find_drv,
+				struct udevice **devp)
+{
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
+
+	ret = uclass_get(id, &uc);
+	if (ret)
+		return ret;
+
+	list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+		if (dev->driver == find_drv)
+			return uclass_get_device_tail(dev, 0, devp);
+	}
+
+	return -ENODEV;
+}
+
 int uclass_get_device_tail(struct udevice *dev, int ret,
 				  struct udevice **devp)
 {
diff --git a/include/dm/device.h b/include/dm/device.h
index c825d47..705849b 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -207,6 +207,10 @@ struct driver {
 #define U_BOOT_DRIVER(__name)						\
 	ll_entry_declare(struct driver, __name, driver)
 
+/* Get a pointer to a given driver */
+#define DM_GET_DRIVER(__name)						\
+	ll_entry_get(struct driver, __name, driver)
+
 /**
  * dev_get_platdata() - Get the platform data for a device
  *
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index fd368b6..84f05bc 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -38,6 +38,7 @@ struct uclass {
 	struct list_head sibling_node;
 };
 
+struct driver;
 struct udevice;
 
 /* Members of this uclass sequence themselves with aliases */
@@ -194,6 +195,23 @@ int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,
 				 const char *name, struct udevice **devp);
 
 /**
+ * uclass_get_device_by_driver() - Get a uclass device for a driver
+ *
+ * This searches the devices in the uclass for one that uses the given
+ * driver. Use DM_GET_DRIVER(name) for the @drv argument, where 'name' is
+ * the driver name - as used in U_BOOT_DRIVER(name).
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @drv: Driver to look for
+ * @devp: Returns pointer to the first device with that driver
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv,
+				struct udevice **devp);
+
+/**
  * uclass_first_device() - Get the first device in a uclass
  *
  * The device returned is probed if necessary, and ready for use
-- 
cgit v0.10.2


From a617c5d3e2c22355ee9abc455bbb0b36e124a00a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 17 Jul 2016 15:23:16 -0600
Subject: rockchip: Add a way to obtain the main clock device

On Rockchip SoCs we typically have a main clock device that uses the Soc
clock driver. There is also a fixed clock for the oscillator. Add a function
to obtain the core clock.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 4bebd62..21edbc2 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -67,4 +67,6 @@ struct rk3288_grf;
 
 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
 
+int rockchip_get_clk(struct udevice **devp);
+
 #endif
diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile
index 6f62375..82b00a1 100644
--- a/arch/arm/mach-rockchip/rk3288/Makefile
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -4,6 +4,7 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+obj-y += clk_rk3288.o
 obj-y += reset_rk3288.o
 obj-y += sdram_rk3288.o
 obj-y += syscon_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
new file mode 100644
index 0000000..2099e34
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(rockchip_rk3288_cru), devp);
+}
-- 
cgit v0.10.2


From c3aad6f65b3fb574e1a73c686d8793dee00c5819 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 17 Jul 2016 15:23:17 -0600
Subject: rockchip: Use rockchip_get_clk() to obtain the SoC clock

The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.

Fix this by calling rockchip_get_clk() instead.

Fixes: 135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>

diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index f662b26..bec756d 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -178,7 +178,7 @@ static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 	int ret, i;
 	struct udevice *dev;
 
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	ret = rockchip_get_clk(&dev);
 	if (ret) {
 		printf("clk-uclass not found\n");
 		return 0;
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index d82115f..ed14023 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -187,7 +187,7 @@ void board_init_f(ulong dummy)
 	rockchip_timer_init();
 	configure_l2ctlr();
 
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	ret = rockchip_get_clk(&dev);
 	if (ret) {
 		debug("CLK init failed: %d\n", ret);
 		return;
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index fc0f2f3..4364d5a 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -923,7 +923,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	priv->chan[1].pctl = regmap_get_range(plat->map, 2);
 	priv->chan[1].publ = regmap_get_range(plat->map, 3);
 #endif
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
+	ret = rockchip_get_clk(&dev_clk);
 	if (ret)
 		return ret;
 	priv->ddr_clk.id = CLK_DDR;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index a41cf8b..e00feb0 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -145,7 +145,7 @@ void *rockchip_get_cru(void)
 	struct udevice *dev;
 	int ret;
 
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	ret = rockchip_get_clk(&dev);
 	if (ret)
 		return ERR_PTR(ret);
 
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index cc26f19..c6d88d9 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -238,7 +238,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 		return ret;
 	}
 
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
+	ret = rockchip_get_clk(&dev_clk);
 	if (!ret) {
 		clk.id = DCLK_VOP0 + remote_vop_id;
 		ret = clk_request(dev_clk, &clk);
-- 
cgit v0.10.2


From 9191090e34d036ef103931beaa05fa6401390beb Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 18 Jul 2016 09:35:26 +0800
Subject: mkimage: rockchip: add suport for rk33 serial

Add support for rockchip rk33 series Soc like rk3368 and rk3399

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 9ec7eb2..0a072aa 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -56,7 +56,7 @@ struct spl_info {
 static struct spl_info spl_infos[] = {
 	{ "rk3036", "RK30", 0x1000 },
 	{ "rk3288", "RK32", 0x8000 },
-	{ "rk33xx", "RK33", 0x20000 },
+	{ "rk3399", "RK33", 0x20000 },
 };
 
 static unsigned char rc4_key[16] = {
-- 
cgit v0.10.2


From a16e2e06809ad23afeda69edcc1a99182fa9d8fd Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Mon, 18 Jul 2016 09:56:46 +0800
Subject: rockchip: update fastboot usage

Introduce how to use fastboot feature on rk3288.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 3fc2582..c218a8b 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -144,6 +144,32 @@ For evb_rk3036 board:
 Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the
       debug uart must be disabled
 
+Using fastboot on rk3288
+========================
+- Define GPT partition layout like kylin_rk3036(see include/configs/kylin_rk3036.h)
+- Write GPT partition layout to mmc device which fastboot want to use it to
+store the image
+
+        => gpt write mmc 1 $partitions
+
+- Invoke fastboot command to prepare
+
+        => fastboot 1
+
+- Start fastboot request on PC
+
+        fastboot -i 0x2207 flash loader evb-rk3288/spl/u-boot-spl-dtb.bin
+
+You should see something like:
+
+        => fastboot 1
+        WARNING: unknown variable: partition-type:loader
+        Starting download of 357796 bytes
+        ..
+        downloading of 357796 bytes finished
+        Flashing Raw Image
+        ........ wrote 357888 bytes to 'loader'
+
 Booting from SPI
 ================
 
-- 
cgit v0.10.2


From 777c834fd476af37340a1e4b15597669e8a0ca31 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Tue, 19 Jul 2016 21:16:58 +0800
Subject: dts: add support for Rockchip rk3399 soc

These files are from kernel upstream:
"649a371 Add linux-next specific files for 20160616"
with some modification need by U-Boot:
- chosen with stdout-path to uart2.
- add clock-frequency for uart2

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 88741e5..c97e3f6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,7 +32,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-jerry.dtb \
 	rk3288-rock2-square.dtb \
 	rk3288-evb.dtb \
-	rk3036-sdk.dtb
+	rk3036-sdk.dtb \
+	rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxbb-odroidc2.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
new file mode 100644
index 0000000..bbcfcd0
--- /dev/null
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "Rockchip RK3399 Evaluation Board";
+	compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
+		     "google,rk3399evb-rev2";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	vdd_center: vdd-center {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 25000 0>;
+		regulator-name = "vdd_center";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+		status = "okay";
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins =
+				<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
new file mode 100644
index 0000000..fb5af54
--- /dev/null
+++ b/arch/arm/dts/rk3399.dtsi
@@ -0,0 +1,1028 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/rk3399-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	compatible = "rockchip,rk3399";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu_l0>;
+				};
+				core1 {
+					cpu = <&cpu_l1>;
+				};
+				core2 {
+					cpu = <&cpu_l2>;
+				};
+				core3 {
+					cpu = <&cpu_l3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu_b0>;
+				};
+				core1 {
+					cpu = <&cpu_b1>;
+				};
+			};
+		};
+
+		cpu_l0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			#cooling-cells = <2>; /* min followed by max */
+			clocks = <&cru ARMCLKL>;
+		};
+
+		cpu_l1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			clocks = <&cru ARMCLKL>;
+		};
+
+		cpu_l2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			clocks = <&cru ARMCLKL>;
+		};
+
+		cpu_l3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			clocks = <&cru ARMCLKL>;
+		};
+
+		cpu_b0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			#cooling-cells = <2>; /* min followed by max */
+			clocks = <&cru ARMCLKB>;
+		};
+
+		cpu_b1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+			clocks = <&cru ARMCLKB>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	xin24m: xin24m {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0>;
+	};
+
+	amba {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dmac_bus: dma-controller@ff6d0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x0 0xff6d0000 0x0 0x4000>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMAC0_PERILP>;
+			clock-names = "apb_pclk";
+		};
+
+		dmac_peri: dma-controller@ff6e0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x0 0xff6e0000 0x0 0x4000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMAC1_PERILP>;
+			clock-names = "apb_pclk";
+		};
+	};
+
+	sdio0: dwmmc@fe310000 {
+		compatible = "rockchip,rk3399-dw-mshc",
+			     "rockchip,rk3288-dw-mshc";
+		reg = <0x0 0xfe310000 0x0 0x4000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		clock-freq-min-max = <400000 150000000>;
+		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		status = "disabled";
+	};
+
+	sdmmc: dwmmc@fe320000 {
+		compatible = "rockchip,rk3399-dw-mshc",
+			     "rockchip,rk3288-dw-mshc";
+		reg = <0x0 0xfe320000 0x0 0x4000>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		clock-freq-min-max = <400000 150000000>;
+		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		status = "disabled";
+	};
+
+	sdhci: sdhci@fe330000 {
+		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+		reg = <0x0 0xfe330000 0x0 0x10000>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru SCLK_EMMC>;
+		assigned-clock-rates = <200000000>;
+		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+		clock-names = "clk_xin", "clk_ahb";
+		phys = <&emmc_phy>;
+		phy-names = "phy_arasan";
+		status = "disabled";
+	};
+
+	usb_host0_ehci: usb@fe380000 {
+		compatible = "generic-ehci";
+		reg = <0x0 0xfe380000 0x0 0x20000>;
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
+		clock-names = "hclk_host0", "hclk_host0_arb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@fe3a0000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xfe3a0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
+		clock-names = "hclk_host0", "hclk_host0_arb";
+		status = "disabled";
+	};
+
+	usb_host1_ehci: usb@fe3c0000 {
+		compatible = "generic-ehci";
+		reg = <0x0 0xfe3c0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
+		clock-names = "hclk_host1", "hclk_host1_arb";
+		status = "disabled";
+	};
+
+	usb_host1_ohci: usb@fe3e0000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xfe3e0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
+		clock-names = "hclk_host1", "hclk_host1_arb";
+		status = "disabled";
+	};
+
+	gic: interrupt-controller@fee00000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+
+		reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
+		      <0x0 0xfef00000 0 0xc0000>, /* GICR */
+		      <0x0 0xfff00000 0 0x10000>, /* GICC */
+		      <0x0 0xfff10000 0 0x10000>, /* GICH */
+		      <0x0 0xfff20000 0 0x10000>; /* GICV */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		its: interrupt-controller@fee20000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xfee20000 0x0 0x20000>;
+		};
+	};
+
+	uart0: serial@ff180000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff180000 0x0 0x100>;
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart0_xfer>;
+		status = "disabled";
+	};
+
+	uart1: serial@ff190000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff190000 0x0 0x100>;
+		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart1_xfer>;
+		status = "disabled";
+	};
+
+	uart2: serial@ff1a0000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff1a0000 0x0 0x100>;
+		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <24000000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2c_xfer>;
+		status = "disabled";
+	};
+
+	uart3: serial@ff1b0000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff1b0000 0x0 0x100>;
+		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart3_xfer>;
+		status = "disabled";
+	};
+
+	spi0: spi@ff1c0000 {
+		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+		reg = <0x0 0xff1c0000 0x0 0x1000>;
+		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+		clock-names = "spiclk", "apb_pclk";
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi1: spi@ff1d0000 {
+		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+		reg = <0x0 0xff1d0000 0x0 0x1000>;
+		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+		clock-names = "spiclk", "apb_pclk";
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi2: spi@ff1e0000 {
+		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+		reg = <0x0 0xff1e0000 0x0 0x1000>;
+		clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
+		clock-names = "spiclk", "apb_pclk";
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi4: spi@ff1f0000 {
+		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+		reg = <0x0 0xff1f0000 0x0 0x1000>;
+		clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
+		clock-names = "spiclk", "apb_pclk";
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi5: spi@ff200000 {
+		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+		reg = <0x0 0xff200000 0x0 0x1000>;
+		clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
+		clock-names = "spiclk", "apb_pclk";
+		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	pmugrf: syscon@ff320000 {
+		compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
+		reg = <0x0 0xff320000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pmu_io_domains: io-domains {
+			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
+			status = "disabled";
+		};
+	};
+
+	spi3: spi@ff350000 {
+		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+		reg = <0x0 0xff350000 0x0 0x1000>;
+		clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
+		clock-names = "spiclk", "apb_pclk";
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	uart4: serial@ff370000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff370000 0x0 0x100>;
+		clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart4_xfer>;
+		status = "disabled";
+	};
+
+	pwm0: pwm@ff420000 {
+		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+		reg = <0x0 0xff420000 0x0 0x10>;
+		#pwm-cells = <3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm0_pin>;
+		clocks = <&pmucru PCLK_RKPWM_PMU>;
+		clock-names = "pwm";
+		status = "disabled";
+	};
+
+	pwm1: pwm@ff420010 {
+		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+		reg = <0x0 0xff420010 0x0 0x10>;
+		#pwm-cells = <3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm1_pin>;
+		clocks = <&pmucru PCLK_RKPWM_PMU>;
+		clock-names = "pwm";
+		status = "disabled";
+	};
+
+	pwm2: pwm@ff420020 {
+		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+		reg = <0x0 0xff420020 0x0 0x10>;
+		#pwm-cells = <3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm2_pin>;
+		clocks = <&pmucru PCLK_RKPWM_PMU>;
+		clock-names = "pwm";
+		status = "disabled";
+	};
+
+	pwm3: pwm@ff420030 {
+		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+		reg = <0x0 0xff420030 0x0 0x10>;
+		#pwm-cells = <3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm3a_pin>;
+		clocks = <&pmucru PCLK_RKPWM_PMU>;
+		clock-names = "pwm";
+		status = "disabled";
+	};
+
+	pmucru: pmu-clock-controller@ff750000 {
+		compatible = "rockchip,rk3399-pmucru";
+		reg = <0x0 0xff750000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		assigned-clocks = <&pmucru PLL_PPLL>;
+		assigned-clock-rates = <676000000>;
+	};
+
+	cru: clock-controller@ff760000 {
+		compatible = "rockchip,rk3399-cru";
+		reg = <0x0 0xff760000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		assigned-clocks =
+			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
+			<&cru PLL_NPLL>,
+			<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
+			<&cru PCLK_PERIHP>,
+			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
+			<&cru PCLK_PERILP0>,
+			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+		assigned-clock-rates =
+			 <594000000>,  <800000000>,
+			<1000000000>,
+			 <150000000>,   <75000000>,
+			  <37500000>,
+			 <100000000>,  <100000000>,
+			  <50000000>,
+			 <100000000>,   <50000000>;
+	};
+
+	grf: syscon@ff770000 {
+		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+		reg = <0x0 0xff770000 0x0 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		io_domains: io-domains {
+			compatible = "rockchip,rk3399-io-voltage-domain";
+			status = "disabled";
+		};
+
+		emmc_phy: phy@f780 {
+			compatible = "rockchip,rk3399-emmc-phy";
+			reg = <0xf780 0x24>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	watchdog@ff840000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x0 0xff840000 0x0 0x100>;
+		clocks = <&cru PCLK_WDT>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	spdif: spdif@ff870000 {
+		compatible = "rockchip,rk3399-spdif";
+		reg = <0x0 0xff870000 0x0 0x1000>;
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 7>;
+		dma-names = "tx";
+		clock-names = "mclk", "hclk";
+		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spdif_bus>;
+		status = "disabled";
+	};
+
+	i2s0: i2s@ff880000 {
+		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff880000 0x0 0x1000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_clk", "i2s_hclk";
+		clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_8ch_bus>;
+		status = "disabled";
+	};
+
+	i2s1: i2s@ff890000 {
+		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff890000 0x0 0x1000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 2>, <&dmac_bus 3>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_clk", "i2s_hclk";
+		clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s1_2ch_bus>;
+		status = "disabled";
+	};
+
+	i2s2: i2s@ff8a0000 {
+		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff8a0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 4>, <&dmac_bus 5>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_clk", "i2s_hclk";
+		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
+		status = "disabled";
+	};
+
+	pinctrl: pinctrl {
+		compatible = "rockchip,rk3399-pinctrl";
+		rockchip,grf = <&grf>;
+		rockchip,pmu = <&pmugrf>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gpio0: gpio0@ff720000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xff720000 0x0 0x100>;
+			clocks = <&pmucru PCLK_GPIO0_PMU>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpio1: gpio1@ff730000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xff730000 0x0 0x100>;
+			clocks = <&pmucru PCLK_GPIO1_PMU>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpio2: gpio2@ff780000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xff780000 0x0 0x100>;
+			clocks = <&cru PCLK_GPIO2>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpio3: gpio3@ff788000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xff788000 0x0 0x100>;
+			clocks = <&cru PCLK_GPIO3>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpio4: gpio4@ff790000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x0 0xff790000 0x0 0x100>;
+			clocks = <&cru PCLK_GPIO4>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		pcfg_pull_up: pcfg-pull-up {
+			bias-pull-up;
+		};
+
+		pcfg_pull_down: pcfg-pull-down {
+			bias-pull-down;
+		};
+
+		pcfg_pull_none: pcfg-pull-none {
+			bias-disable;
+		};
+
+		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+			bias-disable;
+			drive-strength = <12>;
+		};
+
+		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+			bias-pull-up;
+			drive-strength = <8>;
+		};
+
+		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
+			bias-pull-down;
+			drive-strength = <4>;
+		};
+
+		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		pcfg_pull_down_12ma: pcfg-pull-down-12ma {
+			bias-pull-down;
+			drive-strength = <12>;
+		};
+
+		pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+			bias-disable;
+			drive-strength = <13>;
+		};
+
+		i2c0 {
+			i2c0_xfer: i2c0-xfer {
+				rockchip,pins =
+					<1 15 RK_FUNC_2 &pcfg_pull_none>,
+					<1 16 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		i2c1 {
+			i2c1_xfer: i2c1-xfer {
+				rockchip,pins =
+					<4 2 RK_FUNC_1 &pcfg_pull_none>,
+					<4 1 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2c2 {
+			i2c2_xfer: i2c2-xfer {
+				rockchip,pins =
+					<2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
+					<2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
+			};
+		};
+
+		i2c3 {
+			i2c3_xfer: i2c3-xfer {
+				rockchip,pins =
+					<4 17 RK_FUNC_1 &pcfg_pull_none>,
+					<4 16 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2c4 {
+			i2c4_xfer: i2c4-xfer {
+				rockchip,pins =
+					<1 12 RK_FUNC_1 &pcfg_pull_none>,
+					<1 11 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2c5 {
+			i2c5_xfer: i2c5-xfer {
+				rockchip,pins =
+					<3 11 RK_FUNC_2 &pcfg_pull_none>,
+					<3 10 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		i2c6 {
+			i2c6_xfer: i2c6-xfer {
+				rockchip,pins =
+					<2 10 RK_FUNC_2 &pcfg_pull_none>,
+					<2 9 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		i2c7 {
+			i2c7_xfer: i2c7-xfer {
+				rockchip,pins =
+					<2 8 RK_FUNC_2 &pcfg_pull_none>,
+					<2 7 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		i2c8 {
+			i2c8_xfer: i2c8-xfer {
+				rockchip,pins =
+					<1 21 RK_FUNC_1 &pcfg_pull_none>,
+					<1 20 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2s0 {
+			i2s0_8ch_bus: i2s0-8ch-bus {
+				rockchip,pins =
+					<3 24 RK_FUNC_1 &pcfg_pull_none>,
+					<3 25 RK_FUNC_1 &pcfg_pull_none>,
+					<3 26 RK_FUNC_1 &pcfg_pull_none>,
+					<3 27 RK_FUNC_1 &pcfg_pull_none>,
+					<3 28 RK_FUNC_1 &pcfg_pull_none>,
+					<3 29 RK_FUNC_1 &pcfg_pull_none>,
+					<3 30 RK_FUNC_1 &pcfg_pull_none>,
+					<3 31 RK_FUNC_1 &pcfg_pull_none>,
+					<4 0 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2s1 {
+			i2s1_2ch_bus: i2s1-2ch-bus {
+				rockchip,pins =
+					<4 3 RK_FUNC_1 &pcfg_pull_none>,
+					<4 4 RK_FUNC_1 &pcfg_pull_none>,
+					<4 5 RK_FUNC_1 &pcfg_pull_none>,
+					<4 6 RK_FUNC_1 &pcfg_pull_none>,
+					<4 7 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		spdif {
+			spdif_bus: spdif-bus {
+				rockchip,pins =
+					<4 21 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		spi0 {
+			spi0_clk: spi0-clk {
+				rockchip,pins =
+					<3 6 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi0_cs0: spi0-cs0 {
+				rockchip,pins =
+					<3 7 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi0_cs1: spi0-cs1 {
+				rockchip,pins =
+					<3 8 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi0_tx: spi0-tx {
+				rockchip,pins =
+					<3 5 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi0_rx: spi0-rx {
+				rockchip,pins =
+					<3 4 RK_FUNC_2 &pcfg_pull_up>;
+			};
+		};
+
+		spi1 {
+			spi1_clk: spi1-clk {
+				rockchip,pins =
+					<1 9 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi1_cs0: spi1-cs0 {
+				rockchip,pins =
+					<1 10 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi1_rx: spi1-rx {
+				rockchip,pins =
+					<1 7 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi1_tx: spi1-tx {
+				rockchip,pins =
+					<1 8 RK_FUNC_2 &pcfg_pull_up>;
+			};
+		};
+
+		spi2 {
+			spi2_clk: spi2-clk {
+				rockchip,pins =
+					<2 11 RK_FUNC_1 &pcfg_pull_up>;
+			};
+			spi2_cs0: spi2-cs0 {
+				rockchip,pins =
+					<2 12 RK_FUNC_1 &pcfg_pull_up>;
+			};
+			spi2_rx: spi2-rx {
+				rockchip,pins =
+					<2 9 RK_FUNC_1 &pcfg_pull_up>;
+			};
+			spi2_tx: spi2-tx {
+				rockchip,pins =
+					<2 10 RK_FUNC_1 &pcfg_pull_up>;
+			};
+		};
+
+		spi3 {
+			spi3_clk: spi3-clk {
+				rockchip,pins =
+					<1 17 RK_FUNC_1 &pcfg_pull_up>;
+			};
+			spi3_cs0: spi3-cs0 {
+				rockchip,pins =
+					<1 18 RK_FUNC_1 &pcfg_pull_up>;
+			};
+			spi3_rx: spi3-rx {
+				rockchip,pins =
+					<1 15 RK_FUNC_1 &pcfg_pull_up>;
+			};
+			spi3_tx: spi3-tx {
+				rockchip,pins =
+					<1 16 RK_FUNC_1 &pcfg_pull_up>;
+			};
+		};
+
+		spi4 {
+			spi4_clk: spi4-clk {
+				rockchip,pins =
+					<3 2 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi4_cs0: spi4-cs0 {
+				rockchip,pins =
+					<3 3 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi4_rx: spi4-rx {
+				rockchip,pins =
+					<3 0 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi4_tx: spi4-tx {
+				rockchip,pins =
+					<3 1 RK_FUNC_2 &pcfg_pull_up>;
+			};
+		};
+
+		spi5 {
+			spi5_clk: spi5-clk {
+				rockchip,pins =
+					<2 22 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi5_cs0: spi5-cs0 {
+				rockchip,pins =
+					<2 23 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi5_rx: spi5-rx {
+				rockchip,pins =
+					<2 20 RK_FUNC_2 &pcfg_pull_up>;
+			};
+			spi5_tx: spi5-tx {
+				rockchip,pins =
+					<2 21 RK_FUNC_2 &pcfg_pull_up>;
+			};
+		};
+
+		uart0 {
+			uart0_xfer: uart0-xfer {
+				rockchip,pins =
+					<2 16 RK_FUNC_1 &pcfg_pull_up>,
+					<2 17 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			uart0_cts: uart0-cts {
+				rockchip,pins =
+					<2 18 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			uart0_rts: uart0-rts {
+				rockchip,pins =
+					<2 19 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		uart1 {
+			uart1_xfer: uart1-xfer {
+				rockchip,pins =
+					<3 12 RK_FUNC_2 &pcfg_pull_up>,
+					<3 13 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		uart2a {
+			uart2a_xfer: uart2a-xfer {
+				rockchip,pins =
+					<4 8 RK_FUNC_2 &pcfg_pull_up>,
+					<4 9 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		uart2b {
+			uart2b_xfer: uart2b-xfer {
+				rockchip,pins =
+					<4 16 RK_FUNC_2 &pcfg_pull_up>,
+					<4 17 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		uart2c {
+			uart2c_xfer: uart2c-xfer {
+				rockchip,pins =
+					<4 19 RK_FUNC_1 &pcfg_pull_up>,
+					<4 20 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		uart3 {
+			uart3_xfer: uart3-xfer {
+				rockchip,pins =
+					<3 14 RK_FUNC_2 &pcfg_pull_up>,
+					<3 15 RK_FUNC_2 &pcfg_pull_none>;
+			};
+
+			uart3_cts: uart3-cts {
+				rockchip,pins =
+					<3 18 RK_FUNC_2 &pcfg_pull_none>;
+			};
+
+			uart3_rts: uart3-rts {
+				rockchip,pins =
+					<3 19 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		uart4 {
+			uart4_xfer: uart4-xfer {
+				rockchip,pins =
+					<1 7 RK_FUNC_1 &pcfg_pull_up>,
+					<1 8 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		uarthdcp {
+			uarthdcp_xfer: uarthdcp-xfer {
+				rockchip,pins =
+					<4 21 RK_FUNC_2 &pcfg_pull_up>,
+					<4 22 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		pwm0 {
+			pwm0_pin: pwm0-pin {
+				rockchip,pins =
+					<4 18 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			vop0_pwm_pin: vop0-pwm-pin {
+				rockchip,pins =
+					<4 18 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		pwm1 {
+			pwm1_pin: pwm1-pin {
+				rockchip,pins =
+					<4 22 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			vop1_pwm_pin: vop1-pwm-pin {
+				rockchip,pins =
+					<4 18 RK_FUNC_3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm2 {
+			pwm2_pin: pwm2-pin {
+				rockchip,pins =
+					<1 19 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		pwm3a {
+			pwm3a_pin: pwm3a-pin {
+				rockchip,pins =
+					<0 6 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		pwm3b {
+			pwm3b_pin: pwm3b-pin {
+				rockchip,pins =
+					<1 14 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
new file mode 100644
index 0000000..0a86aec
--- /dev/null
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -0,0 +1,746 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+
+/* core clocks */
+#define PLL_APLLL			1
+#define PLL_APLLB			2
+#define PLL_DPLL			3
+#define PLL_CPLL			4
+#define PLL_GPLL			5
+#define PLL_NPLL			6
+#define PLL_VPLL			7
+#define ARMCLKL				8
+#define ARMCLKB				9
+
+/* sclk gates (special clocks) */
+#define SCLK_I2C1			65
+#define SCLK_I2C2			66
+#define SCLK_I2C3			67
+#define SCLK_I2C5			68
+#define SCLK_I2C6			69
+#define SCLK_I2C7			70
+#define SCLK_SPI0			71
+#define SCLK_SPI1			72
+#define SCLK_SPI2			73
+#define SCLK_SPI4			74
+#define SCLK_SPI5			75
+#define SCLK_SDMMC			76
+#define SCLK_SDIO			77
+#define SCLK_EMMC			78
+#define SCLK_TSADC			79
+#define SCLK_SARADC			80
+#define SCLK_UART0			81
+#define SCLK_UART1			82
+#define SCLK_UART2			83
+#define SCLK_UART3			84
+#define SCLK_SPDIF_8CH			85
+#define SCLK_I2S0_8CH			86
+#define SCLK_I2S1_8CH			87
+#define SCLK_I2S2_8CH			88
+#define SCLK_I2S_8CH_OUT		89
+#define SCLK_TIMER00			90
+#define SCLK_TIMER01			91
+#define SCLK_TIMER02			92
+#define SCLK_TIMER03			93
+#define SCLK_TIMER04			94
+#define SCLK_TIMER05			95
+#define SCLK_TIMER06			96
+#define SCLK_TIMER07			97
+#define SCLK_TIMER08			98
+#define SCLK_TIMER09			99
+#define SCLK_TIMER10			100
+#define SCLK_TIMER11			101
+#define SCLK_MACREF			102
+#define SCLK_MAC_RX			103
+#define SCLK_MAC_TX			104
+#define SCLK_MAC			105
+#define SCLK_MACREF_OUT			106
+#define SCLK_VOP0_PWM			107
+#define SCLK_VOP1_PWM			108
+#define SCLK_RGA_CORE			109
+#define SCLK_ISP0			110
+#define SCLK_ISP1			111
+#define SCLK_HDMI_CEC			112
+#define SCLK_HDMI_SFR			113
+#define SCLK_DP_CORE			114
+#define SCLK_PVTM_CORE_L		115
+#define SCLK_PVTM_CORE_B		116
+#define SCLK_PVTM_GPU			117
+#define SCLK_PVTM_DDR			118
+#define SCLK_MIPIDPHY_REF		119
+#define SCLK_MIPIDPHY_CFG		120
+#define SCLK_HSICPHY			121
+#define SCLK_USBPHY480M			122
+#define SCLK_USB2PHY0_REF		123
+#define SCLK_USB2PHY1_REF		124
+#define SCLK_UPHY0_TCPDPHY_REF		125
+#define SCLK_UPHY0_TCPDCORE		126
+#define SCLK_UPHY1_TCPDPHY_REF		127
+#define SCLK_UPHY1_TCPDCORE		128
+#define SCLK_USB3OTG0_REF		129
+#define SCLK_USB3OTG1_REF		130
+#define SCLK_USB3OTG0_SUSPEND		131
+#define SCLK_USB3OTG1_SUSPEND		132
+#define SCLK_CRYPTO0			133
+#define SCLK_CRYPTO1			134
+#define SCLK_CCI_TRACE			135
+#define SCLK_CS				136
+#define SCLK_CIF_OUT			137
+#define SCLK_PCIEPHY_REF		138
+#define SCLK_PCIE_CORE			139
+#define SCLK_M0_PERILP			140
+#define SCLK_M0_PERILP_DEC		141
+#define SCLK_CM0S			142
+#define SCLK_DBG_NOC			143
+#define SCLK_DBG_PD_CORE_B		144
+#define SCLK_DBG_PD_CORE_L		145
+#define SCLK_DFIMON0_TIMER		146
+#define SCLK_DFIMON1_TIMER		147
+#define SCLK_INTMEM0			148
+#define SCLK_INTMEM1			149
+#define SCLK_INTMEM2			150
+#define SCLK_INTMEM3			151
+#define SCLK_INTMEM4			152
+#define SCLK_INTMEM5			153
+#define SCLK_SDMMC_DRV			154
+#define SCLK_SDMMC_SAMPLE		155
+#define SCLK_SDIO_DRV			156
+#define SCLK_SDIO_SAMPLE		157
+#define SCLK_VDU_CORE			158
+#define SCLK_VDU_CA			159
+#define SCLK_PCIE_PM			160
+#define SCLK_SPDIF_REC_DPTX		161
+#define SCLK_DPHY_PLL			162
+#define SCLK_DPHY_TX0_CFG		163
+#define SCLK_DPHY_TX1RX1_CFG		164
+#define SCLK_DPHY_RX0_CFG		165
+#define SCLK_RMII_SRC			166
+#define SCLK_PCIEPHY_REF100M		167
+
+#define DCLK_VOP0			180
+#define DCLK_VOP1			181
+#define DCLK_VOP0_DIV			182
+#define DCLK_VOP1_DIV			183
+#define DCLK_M0_PERILP			184
+
+#define FCLK_CM0S			190
+
+/* aclk gates */
+#define ACLK_PERIHP			192
+#define ACLK_PERIHP_NOC			193
+#define ACLK_PERILP0			194
+#define ACLK_PERILP0_NOC		195
+#define ACLK_PERF_PCIE			196
+#define ACLK_PCIE			197
+#define ACLK_INTMEM			198
+#define ACLK_TZMA			199
+#define ACLK_DCF			200
+#define ACLK_CCI			201
+#define ACLK_CCI_NOC0			202
+#define ACLK_CCI_NOC1			203
+#define ACLK_CCI_GRF			204
+#define ACLK_CENTER			205
+#define ACLK_CENTER_MAIN_NOC		206
+#define ACLK_CENTER_PERI_NOC		207
+#define ACLK_GPU			208
+#define ACLK_PERF_GPU			209
+#define ACLK_GPU_GRF			210
+#define ACLK_DMAC0_PERILP		211
+#define ACLK_DMAC1_PERILP		212
+#define ACLK_GMAC			213
+#define ACLK_GMAC_NOC			214
+#define ACLK_PERF_GMAC			215
+#define ACLK_VOP0_NOC			216
+#define ACLK_VOP0			217
+#define ACLK_VOP1_NOC			218
+#define ACLK_VOP1			219
+#define ACLK_RGA			220
+#define ACLK_RGA_NOC			221
+#define ACLK_HDCP			222
+#define ACLK_HDCP_NOC			223
+#define ACLK_HDCP22			224
+#define ACLK_IEP			225
+#define ACLK_IEP_NOC			226
+#define ACLK_VIO			227
+#define ACLK_VIO_NOC			228
+#define ACLK_ISP0			229
+#define ACLK_ISP1			230
+#define ACLK_ISP0_NOC			231
+#define ACLK_ISP1_NOC			232
+#define ACLK_ISP0_WRAPPER		233
+#define ACLK_ISP1_WRAPPER		234
+#define ACLK_VCODEC			235
+#define ACLK_VCODEC_NOC			236
+#define ACLK_VDU			237
+#define ACLK_VDU_NOC			238
+#define ACLK_PERI			239
+#define ACLK_EMMC			240
+#define ACLK_EMMC_CORE			241
+#define ACLK_EMMC_NOC			242
+#define ACLK_EMMC_GRF			243
+#define ACLK_USB3			244
+#define ACLK_USB3_NOC			245
+#define ACLK_USB3OTG0			246
+#define ACLK_USB3OTG1			247
+#define ACLK_USB3_RKSOC_AXI_PERF	248
+#define ACLK_USB3_GRF			249
+#define ACLK_GIC			250
+#define ACLK_GIC_NOC			251
+#define ACLK_GIC_ADB400_CORE_L_2_GIC	252
+#define ACLK_GIC_ADB400_CORE_B_2_GIC	253
+#define ACLK_GIC_ADB400_GIC_2_CORE_L	254
+#define ACLK_GIC_ADB400_GIC_2_CORE_B	255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L		258
+#define ACLK_ADB400M_PD_CORE_B		259
+#define ACLK_PERF_CORE_L		260
+#define ACLK_PERF_CORE_B		261
+#define ACLK_GIC_PRE			262
+#define ACLK_VOP0_PRE			263
+#define ACLK_VOP1_PRE			264
+
+/* pclk gates */
+#define PCLK_PERIHP			320
+#define PCLK_PERIHP_NOC			321
+#define PCLK_PERILP0			322
+#define PCLK_PERILP1			323
+#define PCLK_PERILP1_NOC		324
+#define PCLK_PERILP_SGRF		325
+#define PCLK_PERIHP_GRF			326
+#define PCLK_PCIE			327
+#define PCLK_SGRF			328
+#define PCLK_INTR_ARB			329
+#define PCLK_CENTER_MAIN_NOC		330
+#define PCLK_CIC			331
+#define PCLK_COREDBG_B			332
+#define PCLK_COREDBG_L			333
+#define PCLK_DBG_CXCS_PD_CORE_B		334
+#define PCLK_DCF			335
+#define PCLK_GPIO2			336
+#define PCLK_GPIO3			337
+#define PCLK_GPIO4			338
+#define PCLK_GRF			339
+#define PCLK_HSICPHY			340
+#define PCLK_I2C1			341
+#define PCLK_I2C2			342
+#define PCLK_I2C3			343
+#define PCLK_I2C5			344
+#define PCLK_I2C6			345
+#define PCLK_I2C7			346
+#define PCLK_SPI0			347
+#define PCLK_SPI1			348
+#define PCLK_SPI2			349
+#define PCLK_SPI4			350
+#define PCLK_SPI5			351
+#define PCLK_UART0			352
+#define PCLK_UART1			353
+#define PCLK_UART2			354
+#define PCLK_UART3			355
+#define PCLK_TSADC			356
+#define PCLK_SARADC			357
+#define PCLK_GMAC			358
+#define PCLK_GMAC_NOC			359
+#define PCLK_TIMER0			360
+#define PCLK_TIMER1			361
+#define PCLK_EDP			362
+#define PCLK_EDP_NOC			363
+#define PCLK_EDP_CTRL			364
+#define PCLK_VIO			365
+#define PCLK_VIO_NOC			366
+#define PCLK_VIO_GRF			367
+#define PCLK_MIPI_DSI0			368
+#define PCLK_MIPI_DSI1			369
+#define PCLK_HDCP			370
+#define PCLK_HDCP_NOC			371
+#define PCLK_HDMI_CTRL			372
+#define PCLK_DP_CTRL			373
+#define PCLK_HDCP22			374
+#define PCLK_GASKET			375
+#define PCLK_DDR			376
+#define PCLK_DDR_MON			377
+#define PCLK_DDR_SGRF			378
+#define PCLK_ISP1_WRAPPER		379
+#define PCLK_WDT			380
+#define PCLK_EFUSE1024NS		381
+#define PCLK_EFUSE1024S			382
+#define PCLK_PMU_INTR_ARB		383
+#define PCLK_MAILBOX0			384
+#define PCLK_USBPHY_MUX_G		385
+#define PCLK_UPHY0_TCPHY_G		386
+#define PCLK_UPHY0_TCPD_G		387
+#define PCLK_UPHY1_TCPHY_G		388
+#define PCLK_UPHY1_TCPD_G		389
+#define PCLK_ALIVE			390
+
+/* hclk gates */
+#define HCLK_PERIHP			448
+#define HCLK_PERILP0			449
+#define HCLK_PERILP1			450
+#define HCLK_PERILP0_NOC		451
+#define HCLK_PERILP1_NOC		452
+#define HCLK_M0_PERILP			453
+#define HCLK_M0_PERILP_NOC		454
+#define HCLK_AHB1TOM			455
+#define HCLK_HOST0			456
+#define HCLK_HOST0_ARB			457
+#define HCLK_HOST1			458
+#define HCLK_HOST1_ARB			459
+#define HCLK_HSIC			460
+#define HCLK_SD				461
+#define HCLK_SDMMC			462
+#define HCLK_SDMMC_NOC			463
+#define HCLK_M_CRYPTO0			464
+#define HCLK_M_CRYPTO1			465
+#define HCLK_S_CRYPTO0			466
+#define HCLK_S_CRYPTO1			467
+#define HCLK_I2S0_8CH			468
+#define HCLK_I2S1_8CH			469
+#define HCLK_I2S2_8CH			470
+#define HCLK_SPDIF			471
+#define HCLK_VOP0_NOC			472
+#define HCLK_VOP0			473
+#define HCLK_VOP1_NOC			474
+#define HCLK_VOP1			475
+#define HCLK_ROM			476
+#define HCLK_IEP			477
+#define HCLK_IEP_NOC			478
+#define HCLK_ISP0			479
+#define HCLK_ISP1			480
+#define HCLK_ISP0_NOC			481
+#define HCLK_ISP1_NOC			482
+#define HCLK_ISP0_WRAPPER		483
+#define HCLK_ISP1_WRAPPER		484
+#define HCLK_RGA			485
+#define HCLK_RGA_NOC			486
+#define HCLK_HDCP			487
+#define HCLK_HDCP_NOC			488
+#define HCLK_HDCP22			489
+#define HCLK_VCODEC			490
+#define HCLK_VCODEC_NOC			491
+#define HCLK_VDU			492
+#define HCLK_VDU_NOC			493
+#define HCLK_SDIO			494
+#define HCLK_SDIO_NOC			495
+#define HCLK_SDIOAUDIO_NOC		496
+
+#define CLK_NR_CLKS			(HCLK_SDIOAUDIO_NOC + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_PPLL			1
+
+#define SCLK_32K_SUSPEND_PMU		2
+#define SCLK_SPI3_PMU			3
+#define SCLK_TIMER12_PMU		4
+#define SCLK_TIMER13_PMU		5
+#define SCLK_UART4_PMU			6
+#define SCLK_PVTM_PMU			7
+#define SCLK_WIFI_PMU			8
+#define SCLK_I2C0_PMU			9
+#define SCLK_I2C4_PMU			10
+#define SCLK_I2C8_PMU			11
+
+#define PCLK_SRC_PMU			19
+#define PCLK_PMU			20
+#define PCLK_PMUGRF_PMU			21
+#define PCLK_INTMEM1_PMU		22
+#define PCLK_GPIO0_PMU			23
+#define PCLK_GPIO1_PMU			24
+#define PCLK_SGRF_PMU			25
+#define PCLK_NOC_PMU			26
+#define PCLK_I2C0_PMU			27
+#define PCLK_I2C4_PMU			28
+#define PCLK_I2C8_PMU			29
+#define PCLK_RKPWM_PMU			30
+#define PCLK_SPI3_PMU			31
+#define PCLK_TIMER_PMU			32
+#define PCLK_MAILBOX_PMU		33
+#define PCLK_UART4_PMU			34
+#define PCLK_WDT_M0_PMU			35
+
+#define FCLK_CM0S_SRC_PMU		44
+#define FCLK_CM0S_PMU			45
+#define SCLK_CM0S_PMU			46
+#define HCLK_CM0S_PMU			47
+#define DCLK_CM0S_PMU			48
+#define PCLK_INTR_ARB_PMU		49
+#define HCLK_NOC_PMU			50
+
+#define CLKPMU_NR_CLKS			(HCLK_NOC_PMU + 1)
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE_L0			0
+#define SRST_CORE_B0			1
+#define SRST_CORE_PO_L0			2
+#define SRST_CORE_PO_B0			3
+#define SRST_L2_L			4
+#define SRST_L2_B			5
+#define SRST_ADB_L			6
+#define SRST_ADB_B			7
+#define SRST_A_CCI			8
+#define SRST_A_CCIM0_NOC		9
+#define SRST_A_CCIM1_NOC		10
+#define SRST_DBG_NOC			11
+
+/* cru_softrst_con1 */
+#define SRST_CORE_L0_T			16
+#define SRST_CORE_L1			17
+#define SRST_CORE_L2			18
+#define SRST_CORE_L3			19
+#define SRST_CORE_PO_L0_T		20
+#define SRST_CORE_PO_L1			21
+#define SRST_CORE_PO_L2			22
+#define SRST_CORE_PO_L3			23
+#define SRST_A_ADB400_GIC2COREL		24
+#define SRST_A_ADB400_COREL2GIC		25
+#define SRST_P_DBG_L			26
+#define SRST_L2_L_T			28
+#define SRST_ADB_L_T			29
+#define SRST_A_RKPERF_L			30
+#define SRST_PVTM_CORE_L		31
+
+/* cru_softrst_con2 */
+#define SRST_CORE_B0_T			32
+#define SRST_CORE_B1			33
+#define SRST_CORE_PO_B0_T		36
+#define SRST_CORE_PO_B1			37
+#define SRST_A_ADB400_GIC2COREB		40
+#define SRST_A_ADB400_COREB2GIC		41
+#define SRST_P_DBG_B			42
+#define SRST_L2_B_T			43
+#define SRST_ADB_B_T			45
+#define SRST_A_RKPERF_B			46
+#define SRST_PVTM_CORE_B		47
+
+/* cru_softrst_con3 */
+#define SRST_A_CCI_T			50
+#define SRST_A_CCIM0_NOC_T		51
+#define SRST_A_CCIM1_NOC_T		52
+#define SRST_A_ADB400M_PD_CORE_B_T	53
+#define SRST_A_ADB400M_PD_CORE_L_T	54
+#define SRST_DBG_NOC_T			55
+#define SRST_DBG_CXCS			56
+#define SRST_CCI_TRACE			57
+#define SRST_P_CCI_GRF			58
+
+/* cru_softrst_con4 */
+#define SRST_A_CENTER_MAIN_NOC		64
+#define SRST_A_CENTER_PERI_NOC		65
+#define SRST_P_CENTER_MAIN		66
+#define SRST_P_DDRMON			67
+#define SRST_P_CIC			68
+#define SRST_P_CENTER_SGRF		69
+#define SRST_DDR0_MSCH			70
+#define SRST_DDRCFG0_MSCH		71
+#define SRST_DDR0			72
+#define SRST_DDRPHY0			73
+#define SRST_DDR1_MSCH			74
+#define SRST_DDRCFG1_MSCH		75
+#define SRST_DDR1			76
+#define SRST_DDRPHY1			77
+#define SRST_DDR_CIC			78
+#define SRST_PVTM_DDR			79
+
+/* cru_softrst_con5 */
+#define SRST_A_VCODEC_NOC		80
+#define SRST_A_VCODEC			81
+#define SRST_H_VCODEC_NOC		82
+#define SRST_H_VCODEC			83
+#define SRST_A_VDU_NOC			88
+#define SRST_A_VDU			89
+#define SRST_H_VDU_NOC			90
+#define SRST_H_VDU			91
+#define SRST_VDU_CORE			92
+#define SRST_VDU_CA			93
+
+/* cru_softrst_con6 */
+#define SRST_A_IEP_NOC			96
+#define SRST_A_VOP_IEP			97
+#define SRST_A_IEP			98
+#define SRST_H_IEP_NOC			99
+#define SRST_H_IEP			100
+#define SRST_A_RGA_NOC			102
+#define SRST_A_RGA			103
+#define SRST_H_RGA_NOC			104
+#define SRST_H_RGA			105
+#define SRST_RGA_CORE			106
+#define SRST_EMMC_NOC			108
+#define SRST_EMMC			109
+#define SRST_EMMC_GRF			110
+
+/* cru_softrst_con7 */
+#define SRST_A_PERIHP_NOC		112
+#define SRST_P_PERIHP_GRF		113
+#define SRST_H_PERIHP_NOC		114
+#define SRST_USBHOST0			115
+#define SRST_HOSTC0_AUX			116
+#define SRST_HOST0_ARB			117
+#define SRST_USBHOST1			118
+#define SRST_HOSTC1_AUX			119
+#define SRST_HOST1_ARB			120
+#define SRST_SDIO0			121
+#define SRST_SDMMC			122
+#define SRST_HSIC			123
+#define SRST_HSIC_AUX			124
+#define SRST_AHB1TOM			125
+#define SRST_P_PERIHP_NOC		126
+#define SRST_HSICPHY			127
+
+/* cru_softrst_con8 */
+#define SRST_A_PCIE			128
+#define SRST_P_PCIE			129
+#define SRST_PCIE_CORE			130
+#define SRST_PCIE_MGMT			131
+#define SRST_PCIE_MGMT_STICKY		132
+#define SRST_PCIE_PIPE			133
+#define SRST_PCIE_PM			134
+#define SRST_PCIEPHY			135
+#define SRST_A_GMAC_NOC			136
+#define SRST_A_GMAC			137
+#define SRST_P_GMAC_NOC			138
+#define SRST_P_GMAC_GRF			140
+#define SRST_HSICPHY_POR		142
+#define SRST_HSICPHY_UTMI		143
+
+/* cru_softrst_con9 */
+#define SRST_USB2PHY0_POR		144
+#define SRST_USB2PHY0_UTMI_PORT0	145
+#define SRST_USB2PHY0_UTMI_PORT1	146
+#define SRST_USB2PHY0_EHCIPHY		147
+#define SRST_UPHY0_PIPE_L00		148
+#define SRST_UPHY0			149
+#define SRST_UPHY0_TCPDPWRUP		150
+#define SRST_USB2PHY1_POR		152
+#define SRST_USB2PHY1_UTMI_PORT0	153
+#define SRST_USB2PHY1_UTMI_PORT1	154
+#define SRST_USB2PHY1_EHCIPHY		155
+#define SRST_UPHY1_PIPE_L00		156
+#define SRST_UPHY1			157
+#define SRST_UPHY1_TCPDPWRUP		158
+
+/* cru_softrst_con10 */
+#define SRST_A_PERILP0_NOC		160
+#define SRST_A_DCF			161
+#define SRST_GIC500			162
+#define SRST_DMAC0_PERILP0		163
+#define SRST_DMAC1_PERILP0		164
+#define SRST_TZMA			165
+#define SRST_INTMEM			166
+#define SRST_ADB400_MST0		167
+#define SRST_ADB400_MST1		168
+#define SRST_ADB400_SLV0		169
+#define SRST_ADB400_SLV1		170
+#define SRST_H_PERILP0			171
+#define SRST_H_PERILP0_NOC		172
+#define SRST_ROM			173
+#define SRST_CRYPTO_S			174
+#define SRST_CRYPTO_M			175
+
+/* cru_softrst_con11 */
+#define SRST_P_DCF			176
+#define SRST_CM0S_NOC			177
+#define SRST_CM0S			178
+#define SRST_CM0S_DBG			179
+#define SRST_CM0S_PO			180
+#define SRST_CRYPTO			181
+#define SRST_P_PERILP1_SGRF		182
+#define SRST_P_PERILP1_GRF		183
+#define SRST_CRYPTO1_S			184
+#define SRST_CRYPTO1_M			185
+#define SRST_CRYPTO1			186
+#define SRST_GIC_NOC			188
+#define SRST_SD_NOC			189
+#define SRST_SDIOAUDIO_BRG		190
+
+/* cru_softrst_con12 */
+#define SRST_H_PERILP1			192
+#define SRST_H_PERILP1_NOC		193
+#define SRST_H_I2S0_8CH			194
+#define SRST_H_I2S1_8CH			195
+#define SRST_H_I2S2_8CH			196
+#define SRST_H_SPDIF_8CH		197
+#define SRST_P_PERILP1_NOC		198
+#define SRST_P_EFUSE_1024		199
+#define SRST_P_EFUSE_1024S		200
+#define SRST_P_I2C0			201
+#define SRST_P_I2C1			202
+#define SRST_P_I2C2			203
+#define SRST_P_I2C3			204
+#define SRST_P_I2C4			205
+#define SRST_P_I2C5			206
+#define SRST_P_MAILBOX0			207
+
+/* cru_softrst_con13 */
+#define SRST_P_UART0			208
+#define SRST_P_UART1			209
+#define SRST_P_UART2			210
+#define SRST_P_UART3			211
+#define SRST_P_SARADC			212
+#define SRST_P_TSADC			213
+#define SRST_P_SPI0			214
+#define SRST_P_SPI1			215
+#define SRST_P_SPI2			216
+#define SRST_P_SPI3			217
+#define SRST_P_SPI4			218
+#define SRST_SPI0			219
+#define SRST_SPI1			220
+#define SRST_SPI2			221
+#define SRST_SPI3			222
+#define SRST_SPI4			223
+
+/* cru_softrst_con14 */
+#define SRST_I2S0_8CH			224
+#define SRST_I2S1_8CH			225
+#define SRST_I2S2_8CH			226
+#define SRST_SPDIF_8CH			227
+#define SRST_UART0			228
+#define SRST_UART1			229
+#define SRST_UART2			230
+#define SRST_UART3			231
+#define SRST_TSADC			232
+#define SRST_I2C0			233
+#define SRST_I2C1			234
+#define SRST_I2C2			235
+#define SRST_I2C3			236
+#define SRST_I2C4			237
+#define SRST_I2C5			238
+#define SRST_SDIOAUDIO_NOC		239
+
+/* cru_softrst_con15 */
+#define SRST_A_VIO_NOC			240
+#define SRST_A_HDCP_NOC			241
+#define SRST_A_HDCP			242
+#define SRST_H_HDCP_NOC			243
+#define SRST_H_HDCP			244
+#define SRST_P_HDCP_NOC			245
+#define SRST_P_HDCP			246
+#define SRST_P_HDMI_CTRL		247
+#define SRST_P_DP_CTRL			248
+#define SRST_S_DP_CTRL			249
+#define SRST_C_DP_CTRL			250
+#define SRST_P_MIPI_DSI0		251
+#define SRST_P_MIPI_DSI1		252
+#define SRST_DP_CORE			253
+#define SRST_DP_I2S			254
+
+/* cru_softrst_con16 */
+#define SRST_GASKET			256
+#define SRST_VIO_GRF			258
+#define SRST_DPTX_SPDIF_REC		259
+#define SRST_HDMI_CTRL			260
+#define SRST_HDCP_CTRL			261
+#define SRST_A_ISP0_NOC			262
+#define SRST_A_ISP1_NOC			263
+#define SRST_H_ISP0_NOC			266
+#define SRST_H_ISP1_NOC			267
+#define SRST_H_ISP0			268
+#define SRST_H_ISP1			269
+#define SRST_ISP0			270
+#define SRST_ISP1			271
+
+/* cru_softrst_con17 */
+#define SRST_A_VOP0_NOC			272
+#define SRST_A_VOP1_NOC			273
+#define SRST_A_VOP0			274
+#define SRST_A_VOP1			275
+#define SRST_H_VOP0_NOC			276
+#define SRST_H_VOP1_NOC			277
+#define SRST_H_VOP0			278
+#define SRST_H_VOP1			279
+#define SRST_D_VOP0			280
+#define SRST_D_VOP1			281
+#define SRST_VOP0_PWM			282
+#define SRST_VOP1_PWM			283
+#define SRST_P_EDP_NOC			284
+#define SRST_P_EDP_CTRL			285
+
+/* cru_softrst_con18 */
+#define SRST_A_GPU			288
+#define SRST_A_GPU_NOC			289
+#define SRST_A_GPU_GRF			290
+#define SRST_PVTM_GPU			291
+#define SRST_A_USB3_NOC			292
+#define SRST_A_USB3_OTG0		293
+#define SRST_A_USB3_OTG1		294
+#define SRST_A_USB3_GRF			295
+#define SRST_PMU			296
+
+/* cru_softrst_con19 */
+#define SRST_P_TIMER0_5			304
+#define SRST_TIMER0			305
+#define SRST_TIMER1			306
+#define SRST_TIMER2			307
+#define SRST_TIMER3			308
+#define SRST_TIMER4			309
+#define SRST_TIMER5			310
+#define SRST_P_TIMER6_11		311
+#define SRST_TIMER6			312
+#define SRST_TIMER7			313
+#define SRST_TIMER8			314
+#define SRST_TIMER9			315
+#define SRST_TIMER10			316
+#define SRST_TIMER11			317
+#define SRST_P_INTR_ARB_PMU		318
+#define SRST_P_ALIVE_SGRF		319
+
+/* cru_softrst_con20 */
+#define SRST_P_GPIO2			320
+#define SRST_P_GPIO3			321
+#define SRST_P_GPIO4			322
+#define SRST_P_GRF			323
+#define SRST_P_ALIVE_NOC		324
+#define SRST_P_WDT0			325
+#define SRST_P_WDT1			326
+#define SRST_P_INTR_ARB			327
+#define SRST_P_UPHY0_DPTX		328
+#define SRST_P_UPHY0_APB		330
+#define SRST_P_UPHY0_TCPHY		332
+#define SRST_P_UPHY1_TCPHY		333
+#define SRST_P_UPHY0_TCPDCTRL		334
+#define SRST_P_UPHY1_TCPDCTRL		335
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_P_NOC			0
+#define SRST_P_INTMEM			1
+#define SRST_H_CM0S			2
+#define SRST_H_CM0S_NOC			3
+#define SRST_DBG_CM0S			4
+#define SRST_PO_CM0S			5
+#define SRST_P_SPI6			6
+#define SRST_SPI6			7
+#define SRST_P_TIMER_0_1		8
+#define SRST_P_TIMER_0			9
+#define SRST_P_TIMER_1			10
+#define SRST_P_UART4			11
+#define SRST_UART4			12
+#define SRST_P_WDT			13
+
+/* pmu_cru_softrst_con1 */
+#define SRST_P_I2C6			16
+#define SRST_P_I2C7			17
+#define SRST_P_I2C8			18
+#define SRST_P_MAILBOX			19
+#define SRST_P_RKPWM			20
+#define SRST_P_PMUGRF			21
+#define SRST_P_SGRF			22
+#define SRST_P_GPIO0			23
+#define SRST_P_GPIO1			24
+#define SRST_P_CRU			25
+#define SRST_P_INTR			26
+#define SRST_PVTM			27
+#define SRST_I2C6			28
+#define SRST_I2C7			29
+#define SRST_I2C8			30
+
+#endif
-- 
cgit v0.10.2


From a381bcf529ff8c33867500cc9a68a100cfe6d22e Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Tue, 19 Jul 2016 21:16:59 +0800
Subject: ARM64: rockchip: add support for rk3399 SoC based evb

RK3399 is a SoC from Rockchip with dual-core Cortex-A72
and quad-core Cortex-A53 CPU. It supports two USB3.0
type-C ports and two USB2.0 EHCI ports. Other interfaces
are very much like RK3288, the DRAM are 32bit width address
and support address from 0 to 4GB-128MB range.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5c19924..4a62d4b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -840,14 +840,12 @@ config STM32
 
 config ARCH_ROCKCHIP
 	bool "Support Rockchip SoCs"
-	select SUPPORT_SPL
-	select SPL
 	select OF_CONTROL
 	select BLK
 	select DM
-	select SPL_DM
+	select SPL_DM if SPL
 	select SYS_MALLOC_F
-	select SPL_SYS_MALLOC_SIMPLE
+	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select DM_GPIO
 	select DM_I2C
 	select DM_MMC
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a3faafe..1aac3c8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -3,6 +3,8 @@ if ARCH_ROCKCHIP
 config ROCKCHIP_RK3036
 	bool "Support Rockchip RK3036"
 	select CPU_V7
+	select SUPPORT_SPL
+	select SPL
 	help
 	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
 	  including NEON and GPU, Mali-400 graphics, several DDR3 options
@@ -12,6 +14,8 @@ config ROCKCHIP_RK3036
 config ROCKCHIP_RK3288
 	bool "Support Rockchip RK3288"
 	select CPU_V7
+	select SUPPORT_SPL
+	select SPL
 	help
 	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
 	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
@@ -19,6 +23,17 @@ config ROCKCHIP_RK3288
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3399
+	bool "Support Rockchip RK3399"
+	select ARM64
+	help
+	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
+	  and quad-core Cortex-A53.
+	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+	  video interfaces supporting HDMI and eDP, several DDR3 options
+	  and video codec support. Peripherals include Gigabit Ethernet,
+	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
 config ROCKCHIP_SPL_BACK_TO_BROM
 	bool "SPL returns to bootrom"
 	default y if ROCKCHIP_RK3036
@@ -29,4 +44,5 @@ config ROCKCHIP_SPL_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
+source "arch/arm/mach-rockchip/rk3399/Kconfig"
 endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 722b582..157d42f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -16,3 +16,4 @@ obj-y += rk_timer.o
 endif
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
+obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
new file mode 100644
index 0000000..83bd04a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -0,0 +1,23 @@
+if ROCKCHIP_RK3399
+
+choice
+	prompt "RK3399 board select"
+
+config TARGET_EVB_RK3399
+	bool "RK3399 evaluation board"
+	help
+	  RK3399evb is a evaluation board for Rockchp rk3399,
+	  with full function and phisical connectors support like type-C ports,
+	  usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+
+endchoice
+
+config SYS_SOC
+	default "rockchip"
+
+config SYS_MALLOC_F_LEN
+	default 0x0800
+
+source "board/rockchip/evb_rk3399/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile
new file mode 100644
index 0000000..3f219ac
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += rk3399.o
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
new file mode 100644
index 0000000..b9d7629
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region rk3399_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xf0000000UL,
+		.phys = 0xf0000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = rk3399_mem_map;
diff --git a/board/rockchip/evb_rk3399/Kconfig b/board/rockchip/evb_rk3399/Kconfig
new file mode 100644
index 0000000..412b81c
--- /dev/null
+++ b/board/rockchip/evb_rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3399
+
+config SYS_BOARD
+	default "evb_rk3399"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
new file mode 100644
index 0000000..e69de29
diff --git a/board/rockchip/evb_rk3399/Makefile b/board/rockchip/evb_rk3399/Makefile
new file mode 100644
index 0000000..aaa51c2
--- /dev/null
+++ b/board/rockchip/evb_rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3399.o
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
new file mode 100644
index 0000000..dffacd0
--- /dev/null
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x80000000;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = 0;
+	gd->bd->bi_dram[0].size = 0x80000000;
+}
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
new file mode 100644
index 0000000..047850a
--- /dev/null
+++ b/include/configs/evb_rk3399.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __EVB_RK3399_H
+#define __EVB_RK3399_H
+
+#include <configs/rk3399_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+/*
+ * SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
new file mode 100644
index 0000000..6ce1aa7
--- /dev/null
+++ b/include/configs/rk3399_common.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3399_COMMON_H
+#define __CONFIG_RK3399_COMMON_H
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_BAUDRATE			1500000
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE		0x00200000
+#define CONFIG_SYS_INIT_SP_ADDR		0x00300000
+#define CONFIG_SYS_LOAD_ADDR		0x00800800
+
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* 64M */
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ	200000000
+
+#define CONFIG_FAT_WRITE
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	256
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(128 << 10)
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x00000000\0" \
+	"pxefile_addr_r=0x00100000\0" \
+	"fdt_addr_r=0x01f00000\0" \
+	"kernel_addr_r=0x02000000\0" \
+	"ramdisk_addr_r=0x04000000\0"
+
+/* First try to boot from SD (index 0), then eMMC (index 1) */
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV
+
+#endif
+
+#endif
-- 
cgit v0.10.2


From 7e243496985d6c69e6cc875a72d6509cbd7820de Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Tue, 19 Jul 2016 21:17:00 +0800
Subject: config: add config file for evb-rk3399

This patch add basic config option for evb-rk3399 board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
new file mode 100644
index 0000000..3f9b47e
--- /dev/null
+++ b/configs/evb-rk3399_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_FIT=y
+CONFIG_SYSRESET=y
+CONFIG_DM_MMC=y
+CONFIG_ROCKCHIP_SDHCI=y
+CONFIG_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_SYS_NS16550=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
-- 
cgit v0.10.2


From d26f375ae467ec633ac4f8ab31ad6337893c0fd3 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Tue, 19 Jul 2016 21:17:01 +0800
Subject: ARM64: evb-rk3399: add a README for this board setup

Add a README to guide people flash the ATF and U-Boot
with Rockchip tools to bring up to board.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README
new file mode 100644
index 0000000..fb8bb19
--- /dev/null
+++ b/board/rockchip/evb_rk3399/README
@@ -0,0 +1,73 @@
+Introduction
+============
+
+RK3399 key features we might use in U-Boot:
+* CPU: ARMv8 64bit Big-Little architecture,
+*      Big: dual-core Cortex-A72
+*      Little: quad-core Cortex-A53
+* IRAM: 200KB
+* DRAM: 4GB-128MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB3.0 typc-C port *2 with dwc3 controller
+*      USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we need to use the
+miniloader from rockchip which:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3399.
+
+Get the Source and prebuild binary
+==================================
+
+  > mkdir ~/evb_rk3399
+  > cd ~/evb_rk3399
+  > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+  > git clone https://github.com/rockchip-linux/rkbin
+  > git clone https://github.com/rockchip-linux/rkflashtool
+
+Compile the ATF
+===============
+
+  > cd arm-trusted-firmware
+  > make realclean
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+
+Compile the U-Boot
+==================
+
+  > cd ../u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3399_defconfig all
+
+Compile the rkflashtool
+=======================
+
+  > cd ../rkflashtool
+  > make
+
+Package the image for miniloader
+================================
+  > cd ..
+  > cp arm-trusted-firmware/build/rk3399/release/bl31.bin rkbin/rk33
+  > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini
+  > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+  > mkdir image
+  > mv trust.img ./image/
+  > mv uboot.img ./image/rk3399evb-uboot.bin
+
+Flash the image
+===============
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+
+  > ./rkflashtool/rkflashloader rk3399evb
+
+You should be able to get U-Boot log message in console/UART2 now.
-- 
cgit v0.10.2


From 79c830653bab23bb0b6ce34793659b459cbacaa0 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 18 Jul 2016 17:00:58 +0800
Subject: mmc: rockchip: add SDHCI driver support for rockchip soc

Rockchip rk3399 using arasan sdhci-5.1 controller.
This patch add the controller support to enable mmc device
with full driver-model support, tested on rk3399 evb board.

According to my test result, this driver should be OK,
the command "part list mmc 0" can result in a right output,
but all the mmc command failed like this:
	=> mmc info
	No MMC device available
	Command failed, result=1

The result of get_mmc_num in cmd/mmc.c is always 0?

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index e0adb9b..dc8f2b6 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -61,6 +61,12 @@ config ZYNQ_SDHCI
 	help
 	  Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
 
+config ROCKCHIP_SDHCI
+	bool "Arasan SDHCI controller for Rockchip support"
+	depends on DM_MMC && BLK && DM_MMC_OPS
+	help
+	  Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform
+
 config MMC_UNIPHIER
 	bool "UniPhier SD/MMC Host Controller support"
 	depends on ARCH_UNIPHIER
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index b44a12e..18351fb 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
 obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
new file mode 100644
index 0000000..023c29b
--- /dev/null
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Rockchip SD Host Controller Interface
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+/* 400KHz is max freq for card ID etc. Use that as min */
+#define EMMC_MIN_FREQ	400000
+
+struct rockchip_sdhc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+struct rockchip_sdhc {
+	struct sdhci_host host;
+	void *base;
+};
+
+static int arasan_sdhci_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
+	struct rockchip_sdhc *prv = dev_get_priv(dev);
+	struct sdhci_host *host = &prv->host;
+	int ret;
+	u32 caps;
+
+	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
+
+	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+	ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
+			caps, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, EMMC_MIN_FREQ,
+			host->version, host->quirks, 0);
+
+	host->mmc = &plat->mmc;
+	if (ret)
+		return ret;
+	host->mmc->priv = &prv->host;
+	host->mmc->dev = dev;
+	upriv->mmc = host->mmc;
+
+	return sdhci_probe(dev);
+}
+
+static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sdhci_host *host = dev_get_priv(dev);
+
+	host->name = dev->name;
+	host->ioaddr = dev_get_addr_ptr(dev);
+
+	return 0;
+}
+
+static int rockchip_sdhci_bind(struct udevice *dev)
+{
+	struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id arasan_sdhci_ids[] = {
+	{ .compatible = "arasan,sdhci-5.1" },
+	{ }
+};
+
+U_BOOT_DRIVER(arasan_sdhci_drv) = {
+	.name		= "arasan_sdhci",
+	.id		= UCLASS_MMC,
+	.of_match	= arasan_sdhci_ids,
+	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
+	.ops		= &sdhci_ops,
+	.bind		= rockchip_sdhci_bind,
+	.probe		= arasan_sdhci_probe,
+	.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
+	.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
+};
-- 
cgit v0.10.2


From c482c60a14e5fa44a62e13bab4d07c52c37915dc Mon Sep 17 00:00:00 2001
From: John Keeping <john@metanate.com>
Date: Fri, 15 Jul 2016 17:33:23 +0100
Subject: rockchip: sdram: Fix register layout for Linux

The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects
the bootloader to store the necessary information there.  We're using
the same register to pass the same information between the SPL and
U-Boot but in a slightly different format.

Change this to use the format expected by the Linux DMC driver so that
the system doesn't hang in Linux by misconfiguring the RAM.

This is almost the same as commit b5788dc ("rockchip: rk3288: correct
sdram setting") which was reverted in commit b525556 ("Revert "rockchip:
rk3288: correct sdram setting"") but parenthese have been added to apply
the mask correctly when reading the "bw" setting and a couple of minor
style issues have been fixed to keep check_patch.pl happy.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 4364d5a..cf9ef2e 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -575,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram,
 			&sdram_params->ch[chan];
 
 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-		sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
+		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-		sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
+		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-		sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
-		sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
+		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 
 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 	}
@@ -734,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 		rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 			SYS_REG_RANK_MASK);
 		col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-		bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
+		bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
 		cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 				SYS_REG_CS0_ROW_MASK);
 		cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 				SYS_REG_CS1_ROW_MASK);
-		bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-			SYS_REG_BW_MASK;
+		bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+			SYS_REG_BW_MASK));
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
 
-- 
cgit v0.10.2


From 81c878dd3c75c9056e4755ece89f45d056735d75 Mon Sep 17 00:00:00 2001
From: Marcin Niestroj <m.niestroj@grinn-global.com>
Date: Fri, 6 May 2016 14:58:29 +0200
Subject: tools: env: Fix format warnings in debug

Format warnings (-Wformat) were shown in printf() calls after defining
DEBUG macro.

Update format string and explicitly cast variables to suppress all
warnings.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 34ceebd..6b0dcaa 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -661,8 +661,8 @@ static int flash_bad_block (int fd, uint8_t mtd_type, loff_t *blockstart)
 
 		if (badblock) {
 #ifdef DEBUG
-			fprintf (stderr, "Bad block at 0x%llx, "
-				 "skipping\n", *blockstart);
+			fprintf (stderr, "Bad block at 0x%llx, skipping\n",
+				(unsigned long long) *blockstart);
 #endif
 			return badblock;
 		}
@@ -749,7 +749,8 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count,
 		}
 #ifdef DEBUG
 		fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
-			 rc, blockstart + block_seek, DEVNAME(dev));
+			rc, (unsigned long long) blockstart + block_seek,
+			DEVNAME(dev));
 #endif
 		processed += readlen;
 		readlen = min (blocklen, count - processed);
@@ -847,8 +848,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count,
 		if (block_seek + count != write_total) {
 			if (block_seek != 0)
 				fprintf(stderr, " and ");
-			fprintf(stderr, "0x%lx - 0x%x",
-				block_seek + count, write_total - 1);
+			fprintf(stderr, "0x%lx - 0x%lx",
+				(unsigned long) block_seek + count,
+				(unsigned long) write_total - 1);
 		}
 		fprintf(stderr, "\n");
 #endif
@@ -911,8 +913,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count,
 		}
 
 #ifdef DEBUG
-		fprintf(stderr, "Write 0x%x bytes at 0x%llx\n", erasesize,
-			blockstart);
+		fprintf(stderr, "Write 0x%llx bytes at 0x%llx\n",
+			(unsigned long long) erasesize,
+			(unsigned long long) blockstart);
 #endif
 		if (write (fd, data + processed, erasesize) != erasesize) {
 			fprintf (stderr, "Write error on %s: %s\n",
-- 
cgit v0.10.2


From 3465f807d4b90378d86b3904ce2db196462ddd4e Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:10:56 +0530
Subject: omap4: i2c: correct register offset for sync register

The register offset of i2c_sysc offset is not correct as per
omap4 TRM [1], correct the offsets as per the documentation.

[1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
index adc8eb2..463e979 100644
--- a/arch/arm/include/asm/arch-omap4/i2c.h
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -14,9 +14,9 @@ struct i2c {
 	unsigned short revnb_lo;	/* 0x00 */
 	unsigned short res1;
 	unsigned short revnb_hi;	/* 0x04 */
-	unsigned short res2[13];
-	unsigned short sysc;		/* 0x20 */
-	unsigned short res3;
+	unsigned short res2[5];
+	unsigned short sysc;		/* 0x10 */
+	unsigned short res3[9];
 	unsigned short irqstatus_raw;	/* 0x24 */
 	unsigned short res4;
 	unsigned short stat;		/* 0x28 */
-- 
cgit v0.10.2


From 7fb825f5b112713f572917fa7e89aac2b5b9c7b4 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:10:57 +0530
Subject: omap5/dra7: i2c: correct register offset for sync register

The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.

[1] - http://www.ti.com/lit/pdf/swpu249
[2] - http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
index d875cfe..2b55edf 100644
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -14,9 +14,9 @@ struct i2c {
 	unsigned short revnb_lo;	/* 0x00 */
 	unsigned short res1;
 	unsigned short revnb_hi;	/* 0x04 */
-	unsigned short res2[13];
-	unsigned short sysc;		/* 0x20 */
-	unsigned short res3;
+	unsigned short res2[5];
+	unsigned short sysc;		/* 0x10 */
+	unsigned short res3[9];
 	unsigned short irqstatus_raw;	/* 0x24 */
 	unsigned short res4;
 	unsigned short stat;		/* 0x28 */
-- 
cgit v0.10.2


From 5142ac791608a5e166f3f1b76b19adcd01aceabc Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:10:58 +0530
Subject: drivers: i2c: uclass: parse dt parameters only when CONFIG_OF_CONTROL
 is enable

parse dt parameter of i2c devices only when CONFIG_OF_CONTROL
is enabled.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 50b99ea..20b30ff 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -467,6 +467,7 @@ int i2c_deblock(struct udevice *bus)
 	return ops->deblock(bus);
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 int i2c_chip_ofdata_to_platdata(const void *blob, int node,
 				struct dm_i2c_chip *chip)
 {
@@ -482,31 +483,44 @@ int i2c_chip_ofdata_to_platdata(const void *blob, int node,
 
 	return 0;
 }
+#endif
 
 static int i2c_post_probe(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 	struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
 
 	i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 				     "clock-frequency", 100000);
 
 	return dm_i2c_set_bus_speed(dev, i2c->speed_hz);
+#else
+	return 0;
+#endif
 }
 
 static int i2c_post_bind(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 	/* Scan the bus for devices */
 	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+#else
+	return 0;
+#endif
 }
 
 static int i2c_child_post_bind(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 	struct dm_i2c_chip *plat = dev_get_parent_platdata(dev);
 
 	if (dev->of_offset == -1)
 		return 0;
 
 	return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
+#else
+	return 0;
+#endif
 }
 
 UCLASS_DRIVER(i2c) = {
-- 
cgit v0.10.2


From eff6b7731b03f3a387d83a2a5b7b78a3037e74b0 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:10:59 +0530
Subject: ti_armv7_common: i2c: do not define DM_I2C for spl

Since omap's spl doesn't support DM currently, do not define
DM_I2C for spl build.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index ba7cf15..b996f35 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -108,6 +108,14 @@
 /* Timer information. */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 
+/*
+ * Disable DM_* for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_I2C
+#endif
+
 /* I2C IP block */
 #define CONFIG_I2C
 #define CONFIG_SYS_I2C
-- 
cgit v0.10.2


From be243e4113b6c3c302ee03050726358714f40ffe Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:00 +0530
Subject: drivers: i2c: omap24xx_i2c: prepare driver for DM conversion

Prepare the driver for DM conversion.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index a7f3fb4..8dea5fa 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -53,10 +53,6 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Absolutely safe for status update at 100 kHz I2C: */
 #define I2C_WAIT	200
 
-static int wait_for_bb(struct i2c_adapter *adap);
-static struct i2c *omap24_get_base(struct i2c_adapter *adap);
-static u16 wait_for_event(struct i2c_adapter *adap);
-static void flush_fifo(struct i2c_adapter *adap);
 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 {
 	unsigned int sampleclk, prescaler;
@@ -90,9 +86,96 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 	}
 	return -1;
 }
-static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+
+/*
+ * Wait for the bus to be free by checking the Bus Busy (BB)
+ * bit to become clear
+ */
+static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
+{
+	int timeout = I2C_TIMEOUT;
+	u16 stat;
+
+	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
+#else
+	/* Read RAW status */
+	while ((stat = readw(&i2c_base->irqstatus_raw) &
+		I2C_STAT_BB) && timeout--) {
+#endif
+		writew(stat, &i2c_base->stat);
+		udelay(waitdelay);
+	}
+
+	if (timeout <= 0) {
+		printf("Timed out in wait_for_bb: status=%04x\n",
+		       stat);
+		return 1;
+	}
+	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
+	return 0;
+}
+
+/*
+ * Wait for the I2C controller to complete current action
+ * and update status
+ */
+static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
+{
+	u16 status;
+	int timeout = I2C_TIMEOUT;
+
+	do {
+		udelay(waitdelay);
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+		status = readw(&i2c_base->stat);
+#else
+		/* Read RAW status */
+		status = readw(&i2c_base->irqstatus_raw);
+#endif
+	} while (!(status &
+		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
+		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
+		    I2C_STAT_AL)) && timeout--);
+
+	if (timeout <= 0) {
+		printf("Timed out in wait_for_event: status=%04x\n",
+		       status);
+		/*
+		 * If status is still 0 here, probably the bus pads have
+		 * not been configured for I2C, and/or pull-ups are missing.
+		 */
+		printf("Check if pads/pull-ups of bus are properly configured\n");
+		writew(0xFFFF, &i2c_base->stat);
+		status = 0;
+	}
+
+	return status;
+}
+
+static void flush_fifo(struct i2c *i2c_base)
+{
+	u16 stat;
+
+	/*
+	 * note: if you try and read data when its not there or ready
+	 * you get a bus error
+	 */
+	while (1) {
+		stat = readw(&i2c_base->stat);
+		if (stat == I2C_STAT_RRDY) {
+			readb(&i2c_base->data);
+			writew(I2C_STAT_RRDY, &i2c_base->stat);
+			udelay(1000);
+		} else
+			break;
+	}
+}
+
+static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
+				 int *waitdelay)
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
 	int psc, fsscll = 0, fssclh = 0;
 	int hsscll = 0, hssclh = 0;
 	u32 scll = 0, sclh = 0;
@@ -142,8 +225,7 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 		}
 	}
 
-	adap->speed	= speed;
-	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+	*waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
 	writew(0, &i2c_base->con);
 	writew(psc, &i2c_base->psc);
 	writew(scll, &i2c_base->scll);
@@ -154,9 +236,8 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 	return 0;
 }
 
-static void omap24_i2c_deblock(struct i2c_adapter *adap)
+static void omap24_i2c_deblock(struct i2c *i2c_base)
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
 	int i;
 	u16 systest;
 	u16 orgsystest;
@@ -200,9 +281,9 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap)
 	writew(orgsystest, &i2c_base->systest);
 }
 
-static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
+			      int *waitdelay)
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
 	int timeout = I2C_TIMEOUT;
 	int deblock = 1;
 
@@ -224,7 +305,7 @@ retry:
 		udelay(1000);
 	}
 
-	if (0 != omap24_i2c_setspeed(adap, speed)) {
+	if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
 		printf("ERROR: failed to setup I2C bus-speed!\n");
 		return;
 	}
@@ -241,45 +322,24 @@ retry:
 	       I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
 #endif
 	udelay(1000);
-	flush_fifo(adap);
+	flush_fifo(i2c_base);
 	writew(0xFFFF, &i2c_base->stat);
 
 	/* Handle possible failed I2C state */
-	if (wait_for_bb(adap))
+	if (wait_for_bb(i2c_base, *waitdelay))
 		if (deblock == 1) {
-			omap24_i2c_deblock(adap);
+			omap24_i2c_deblock(i2c_base);
 			deblock = 0;
 			goto retry;
 		}
 }
 
-static void flush_fifo(struct i2c_adapter *adap)
-{
-	struct i2c *i2c_base = omap24_get_base(adap);
-	u16 stat;
-
-	/*
-	 * note: if you try and read data when its not there or ready
-	 * you get a bus error
-	 */
-	while (1) {
-		stat = readw(&i2c_base->stat);
-		if (stat == I2C_STAT_RRDY) {
-			readb(&i2c_base->data);
-			writew(I2C_STAT_RRDY, &i2c_base->stat);
-			udelay(1000);
-		} else
-			break;
-	}
-}
-
 /*
  * i2c_probe: Use write access. Allows to identify addresses that are
  *            write-only (like the config register of dual-port EEPROMs)
  */
-static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
+static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
 	u16 status;
 	int res = 1; /* default = fail */
 
@@ -287,7 +347,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 		return res;
 
 	/* Wait until bus is free */
-	if (wait_for_bb(adap))
+	if (wait_for_bb(i2c_base, waitdelay))
 		return res;
 
 	/* No data transfer, slave addr only */
@@ -296,7 +356,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 	       I2C_CON_STP, &i2c_base->con);
 
-	status = wait_for_event(adap);
+	status = wait_for_event(i2c_base, waitdelay);
 
 	if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
 		/*
@@ -306,8 +366,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 		 * following 'if' section:
 		 */
 		if (status == I2C_STAT_XRDY)
-			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
-			       adap->hwadapnr, status);
+			printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
+			       status);
 
 		goto pr_exit;
 	}
@@ -315,7 +375,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 	/* Check for ACK (!NAK) */
 	if (!(status & I2C_STAT_NACK)) {
 		res = 0;				/* Device found */
-		udelay(adap->waitdelay);/* Required by AM335X in SPL */
+		udelay(waitdelay);/* Required by AM335X in SPL */
 		/* Abort transfer (force idle state) */
 		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
 		udelay(1000);
@@ -323,7 +383,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 		       I2C_CON_STP, &i2c_base->con);		/* STP */
 	}
 pr_exit:
-	flush_fifo(adap);
+	flush_fifo(i2c_base);
 	writew(0xFFFF, &i2c_base->stat);
 	return res;
 }
@@ -341,10 +401,9 @@ pr_exit:
  *           or that do not need a register address at all (such as some clock
  *           distributors).
  */
-static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
-			   int alen, uchar *buffer, int len)
+static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
+			     uint addr, int alen, uchar *buffer, int len)
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
 	int i2c_error = 0;
 	u16 status;
 
@@ -389,7 +448,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 #endif
 
 	/* Wait until bus not busy */
-	if (wait_for_bb(adap))
+	if (wait_for_bb(i2c_base, waitdelay))
 		return 1;
 
 	/* Zero, one or two bytes reg address (offset) */
@@ -410,12 +469,12 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 #endif
 		/* Send register offset */
 		while (1) {
-			status = wait_for_event(adap);
+			status = wait_for_event(i2c_base, waitdelay);
 			/* Try to identify bus that is not padconf'd for I2C */
 			if (status == I2C_STAT_XRDY) {
 				i2c_error = 2;
-				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
-				       adap->hwadapnr, status);
+				printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
+				       status);
 				goto rd_exit;
 			}
 			if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -450,7 +509,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 
 	/* Receive data */
 	while (1) {
-		status = wait_for_event(adap);
+		status = wait_for_event(i2c_base, waitdelay);
 		/*
 		 * Try to identify bus that is not padconf'd for I2C. This
 		 * state could be left over from previous transactions if
@@ -458,8 +517,8 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 		 */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
-			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
-			       adap->hwadapnr, status);
+			printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
+			       status);
 			goto rd_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -477,16 +536,15 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 	}
 
 rd_exit:
-	flush_fifo(adap);
+	flush_fifo(i2c_base);
 	writew(0xFFFF, &i2c_base->stat);
 	return i2c_error;
 }
 
 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
-static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
-			    int alen, uchar *buffer, int len)
+static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
+			      uint addr, int alen, uchar *buffer, int len)
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
 	int i;
 	u16 status;
 	int i2c_error = 0;
@@ -536,7 +594,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 #endif
 
 	/* Wait until bus not busy */
-	if (wait_for_bb(adap))
+	if (wait_for_bb(i2c_base, waitdelay))
 		return 1;
 
 	/* Start address phase - will write regoffset + len bytes data */
@@ -549,12 +607,12 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 
 	while (alen) {
 		/* Must write reg offset (one or two bytes) */
-		status = wait_for_event(adap);
+		status = wait_for_event(i2c_base, waitdelay);
 		/* Try to identify bus that is not padconf'd for I2C */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
-			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
-			       adap->hwadapnr, status);
+			printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
+			       status);
 			goto wr_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -576,7 +634,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	}
 	/* Address phase is over, now write data */
 	for (i = 0; i < len; i++) {
-		status = wait_for_event(adap);
+		status = wait_for_event(i2c_base, waitdelay);
 		if (status == 0 || (status & I2C_STAT_NACK)) {
 			i2c_error = 1;
 			printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
@@ -598,87 +656,21 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	 * transferred on the bus.
 	 */
 	do {
-		status = wait_for_event(adap);
+		status = wait_for_event(i2c_base, waitdelay);
 	} while (!(status & I2C_STAT_ARDY) && timeout--);
 	if (timeout <= 0)
 		printf("i2c_write: timed out writig last byte!\n");
 
 wr_exit:
-	flush_fifo(adap);
+	flush_fifo(i2c_base);
 	writew(0xFFFF, &i2c_base->stat);
 	return i2c_error;
 }
 
 /*
- * Wait for the bus to be free by checking the Bus Busy (BB)
- * bit to become clear
- */
-static int wait_for_bb(struct i2c_adapter *adap)
-{
-	struct i2c *i2c_base = omap24_get_base(adap);
-	int timeout = I2C_TIMEOUT;
-	u16 stat;
-
-	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
-	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
-#else
-	/* Read RAW status */
-	while ((stat = readw(&i2c_base->irqstatus_raw) &
-		I2C_STAT_BB) && timeout--) {
-#endif
-		writew(stat, &i2c_base->stat);
-		udelay(adap->waitdelay);
-	}
-
-	if (timeout <= 0) {
-		printf("Timed out in wait_for_bb: status=%04x\n",
-		       stat);
-		return 1;
-	}
-	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
-	return 0;
-}
-
-/*
- * Wait for the I2C controller to complete current action
- * and update status
+ * The legacy I2C functions. These need to get removed once
+ * all users of this driver are converted to DM.
  */
-static u16 wait_for_event(struct i2c_adapter *adap)
-{
-	struct i2c *i2c_base = omap24_get_base(adap);
-	u16 status;
-	int timeout = I2C_TIMEOUT;
-
-	do {
-		udelay(adap->waitdelay);
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
-		status = readw(&i2c_base->stat);
-#else
-		/* Read RAW status */
-		status = readw(&i2c_base->irqstatus_raw);
-#endif
-	} while (!(status &
-		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
-		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
-		    I2C_STAT_AL)) && timeout--);
-
-	if (timeout <= 0) {
-		printf("Timed out in wait_for_event: status=%04x\n",
-		       status);
-		/*
-		 * If status is still 0 here, probably the bus pads have
-		 * not been configured for I2C, and/or pull-ups are missing.
-		 */
-		printf("Check if pads/pull-ups of bus %d are properly configured\n",
-		       adap->hwadapnr);
-		writew(0xFFFF, &i2c_base->stat);
-		status = 0;
-	}
-
-	return status;
-}
-
 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
 {
 	switch (adap->hwadapnr) {
@@ -710,6 +702,56 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap)
 	return NULL;
 }
 
+
+static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			   int alen, uchar *buffer, int len)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+
+	return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
+				 alen, buffer, len);
+}
+
+
+static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			    int alen, uchar *buffer, int len)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+
+	return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
+				  alen, buffer, len);
+}
+
+static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+	int ret;
+
+	ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
+	if (ret) {
+		error("%s: set i2c speed failed\n", __func__);
+		return ret;
+	}
+
+	adap->speed = speed;
+
+	return 0;
+}
+
+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+
+	return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
+}
+
+static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+	struct i2c *i2c_base = omap24_get_base(adap);
+
+	return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
+}
+
 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
 #endif
-- 
cgit v0.10.2


From daa69ffe3d4d603ccb7dfca92c33f19d9e1c2313 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:01 +0530
Subject: drivers: i2c: omap24xx_i2c: adopt omap_i2c driver to driver model

Convert omap i2c driver to adopt i2c driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 8dea5fa..0006343 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -39,6 +39,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <i2c.h>
 
 #include <asm/arch/i2c.h>
@@ -53,6 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Absolutely safe for status update at 100 kHz I2C: */
 #define I2C_WAIT	200
 
+struct omap_i2c {
+	struct udevice *clk;
+	struct i2c *regs;
+	unsigned int speed;
+	int waitdelay;
+	int clk_id;
+};
+
 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 {
 	unsigned int sampleclk, prescaler;
@@ -667,6 +676,7 @@ wr_exit:
 	return i2c_error;
 }
 
+#ifndef CONFIG_DM_I2C
 /*
  * The legacy I2C functions. These need to get removed once
  * all users of this driver are converted to DM.
@@ -811,3 +821,92 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
 #endif
 #endif
 #endif
+
+#else /* CONFIG_DM_I2C */
+
+static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct omap_i2c *priv = dev_get_priv(bus);
+	int ret;
+
+	debug("i2c_xfer: %d messages\n", nmsgs);
+	for (; nmsgs > 0; nmsgs--, msg++) {
+		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+		if (msg->flags & I2C_M_RD) {
+			ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
+						msg->addr, 0, 0, msg->buf,
+						msg->len);
+		} else {
+			ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
+						 msg->addr, 0, 0, msg->buf,
+						 msg->len);
+		}
+		if (ret) {
+			debug("i2c_write: error sending\n");
+			return -EREMOTEIO;
+		}
+	}
+
+	return 0;
+}
+
+static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	struct omap_i2c *priv = dev_get_priv(bus);
+
+	priv->speed = speed;
+
+	return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
+}
+
+static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+				     uint chip_flags)
+{
+	struct omap_i2c *priv = dev_get_priv(bus);
+
+	return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
+}
+
+static int omap_i2c_probe(struct udevice *bus)
+{
+	struct omap_i2c *priv = dev_get_priv(bus);
+
+	__omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
+
+	return 0;
+}
+
+static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+	struct omap_i2c *priv = dev_get_priv(bus);
+
+	priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *),
+				 MAP_NOCACHE);
+	priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
+
+	return 0;
+}
+
+static const struct dm_i2c_ops omap_i2c_ops = {
+	.xfer		= omap_i2c_xfer,
+	.probe_chip	= omap_i2c_probe_chip,
+	.set_bus_speed	= omap_i2c_set_bus_speed,
+};
+
+static const struct udevice_id omap_i2c_ids[] = {
+	{ .compatible = "ti,omap4-i2c" },
+	{ }
+};
+
+U_BOOT_DRIVER(i2c_omap) = {
+	.name	= "i2c_omap",
+	.id	= UCLASS_I2C,
+	.of_match = omap_i2c_ids,
+	.ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
+	.probe	= omap_i2c_probe,
+	.priv_auto_alloc_size = sizeof(struct omap_i2c),
+	.ops	= &omap_i2c_ops,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
+
+#endif /* CONFIG_DM_I2C */
-- 
cgit v0.10.2


From c50f2610b5cc672cd2ff6e160e5c9e99f1052c32 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:02 +0530
Subject: defconfig: am335x_boneblack_vboot: enable i2c driver model

Enable i2c driver model for am335x_boneblack_vboot as omap i2c
supports driver model. Also enable CONFIG_DM_I2C_COMPAT for
legacy drivers of i2c devices.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 903f518..c2f09cb 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -49,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_DM_I2C=y
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index b996f35..9f947ee 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -118,7 +118,15 @@
 
 /* I2C IP block */
 #define CONFIG_I2C
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
+#else
+/*
+ * Enable CONFIG_DM_I2C_COMPAT temporarily until all the i2c client
+ * devices are adopted to DM
+ */
+#define CONFIG_DM_I2C_COMPAT
+#endif
 
 /* MMC/SD IP block */
 #define CONFIG_MMC
-- 
cgit v0.10.2


From c438d0117632bd207e9c04a73cd95ae6b229871b Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:03 +0530
Subject: defconfig: am335x_evm: enable i2c driver model

Enable i2c driver model for am335x_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 696024c..6885230 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -49,3 +49,4 @@ CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From 081fbeaa9d8f3b003d32e95bd837fe9ed2274ff4 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:04 +0530
Subject: defconfig: am43xx_evm: enable i2c driver model

Enable i2c driver model for am43xx_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index cb3de11..0eab4ad 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -54,3 +54,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_SPL_OF_LIBFDT=y
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From dc6b17a04e58aaa21443d211ce0cb2e13632f051 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:05 +0530
Subject: defconfig: am43xx_hs_evm: enable i2c driver model

Enable i2c driver model for am43xx_hs_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 68dfb6c..c8ce723 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -58,3 +58,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
 CONFIG_SPL_OF_LIBFDT=y
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From 70ad98c085f591f1439f51b39a6413d4b5de5193 Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:06 +0530
Subject: defconfig: dra7xx_evm: enable i2c driver model

Enable i2c driver model for dra7xx_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 756af63..1d27e52 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -57,3 +57,4 @@ CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From efe7898bffa04f4c56f12078849f46ed8b13fb5f Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:07 +0530
Subject: defconfig: dra7xx_hs_evm: enable i2c driver model

Enable i2c driver model for dra7xx_hs_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index eb01f41..faf9cd5 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -60,3 +60,4 @@ CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From 9aa5874a7698cbcbbb07143121dd1ffed51ba6ed Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:08 +0530
Subject: defconfig: am57xx_evm: enable i2c driver model

Enable i2c driver model for am57xx_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index c29a05a..8a8a4c9 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -40,3 +40,4 @@ CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From c9433a48145e57622c077b026886644eef7a9baf Mon Sep 17 00:00:00 2001
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Mon, 18 Jul 2016 15:11:09 +0530
Subject: defconfig: am57xx_hs_evm: enable i2c driver model

Enable i2c driver model for am57xx_hs_evm as omap i2c
supports driver model.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 01a4701..2ccb332 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -42,3 +42,4 @@ CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_LIST="am57xx-beagle-x15"
+CONFIG_DM_I2C=y
-- 
cgit v0.10.2


From b6de2cd7ee5af536ae67ab5522b69e5c4925f5f2 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Date: Fri, 1 Jul 2016 22:48:16 +0300
Subject: splash: Introduce default_splash_locations

This change introduces default_splash_locations which
simplifies splash recovery from the first partition of
USB/MMC/SATA drive.

Given usual mapping of the first partition of external media for
basic boot stuff like uImage/zImage, .dtb etc it looks quite
obvious option to put there splash.bmp as well.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Anatolij Gustschin <agust@denx.de>

diff --git a/common/splash.c b/common/splash.c
index 561d35b..89af437 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -24,9 +24,37 @@
 #include <splash.h>
 #include <lcd.h>
 
+static struct splash_location default_splash_locations[] = {
+	{
+		.name = "sf",
+		.storage = SPLASH_STORAGE_SF,
+		.flags = SPLASH_STORAGE_RAW,
+		.offset = 0x0,
+	},
+	{
+		.name = "mmc_fs",
+		.storage = SPLASH_STORAGE_MMC,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+	{
+		.name = "usb_fs",
+		.storage = SPLASH_STORAGE_USB,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+	{
+		.name = "sata_fs",
+		.storage = SPLASH_STORAGE_SATA,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+};
+
 __weak int splash_screen_prepare(void)
 {
-	return 0;
+	return splash_source_load(default_splash_locations,
+				  ARRAY_SIZE(default_splash_locations));
 }
 
 #ifdef CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/include/splash.h b/include/splash.h
index 25df1cf..136eac7 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -47,7 +47,16 @@ struct splash_location {
 	char *ubivol;	/* UBI volume-name for ubifsmount */
 };
 
+#ifdef CONFIG_SPLASH_SOURCE
 int splash_source_load(struct splash_location *locations, uint size);
+#else
+static inline int splash_source_load(struct splash_location *locations,
+				     uint size)
+{
+	return 0;
+}
+#endif
+
 int splash_screen_prepare(void);
 
 #ifdef CONFIG_SPLASH_SCREEN_ALIGN
-- 
cgit v0.10.2


From 9ec43b0c3fb0ee65772001b84db9ada2af7e104d Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:01 +0200
Subject: i2c: mvtwsi: Fix style violations

This patch fixes seven style violations: Six superfluous spaces after
casts, and one logical continuation violation.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index bf44432..e9e7c47 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -110,27 +110,27 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
 	switch (adap->hwadapnr) {
 #ifdef CONFIG_I2C_MVTWSI_BASE0
 	case 0:
-		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
+		return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
 #endif
 #ifdef CONFIG_I2C_MVTWSI_BASE1
 	case 1:
-		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
+		return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
 #endif
 #ifdef CONFIG_I2C_MVTWSI_BASE2
 	case 2:
-		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
+		return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
 #endif
 #ifdef CONFIG_I2C_MVTWSI_BASE3
 	case 3:
-		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
+		return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
 #endif
 #ifdef CONFIG_I2C_MVTWSI_BASE4
 	case 4:
-		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
+		return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
 #endif
 #ifdef CONFIG_I2C_MVTWSI_BASE5
 	case 5:
-		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5;
+		return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
 #endif
 	default:
 		printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
@@ -312,8 +312,8 @@ static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 	for (n = 0; n < 8; n++) {
 		for (m = 0; m < 16; m++) {
 			tmp_speed = twsi_calc_freq(n, m);
-			if ((tmp_speed <= requested_speed)
-			 && (tmp_speed > highest_speed)) {
+			if ((tmp_speed <= requested_speed) &&
+			    (tmp_speed > highest_speed)) {
 				highest_speed = tmp_speed;
 				baud = (m << 3) | n;
 			}
-- 
cgit v0.10.2


From dfc3958cd3cce33e16cefec36f670d6202e50e4f Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:02 +0200
Subject: i2c: mvtwsi: Streamline code and add documentation

Convert groups of logically connected preprocessor defines into proper
enums, one macro into an inline function, and add documentation
to/extend existing documentation of these items.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index e9e7c47..93bb88b 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -62,15 +62,23 @@ struct  mvtwsi_registers {
 #endif
 
 /*
- * Control register fields
+ * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
+ * register
  */
-
-#define	MVTWSI_CONTROL_ACK	0x00000004
-#define	MVTWSI_CONTROL_IFLG	0x00000008
-#define	MVTWSI_CONTROL_STOP	0x00000010
-#define	MVTWSI_CONTROL_START	0x00000020
-#define	MVTWSI_CONTROL_TWSIEN	0x00000040
-#define	MVTWSI_CONTROL_INTEN	0x00000080
+enum mvtwsi_ctrl_register_fields {
+	/* Acknowledge bit */
+	MVTWSI_CONTROL_ACK	= 0x00000004,
+	/* Interrupt flag */
+	MVTWSI_CONTROL_IFLG	= 0x00000008,
+	/* Stop bit */
+	MVTWSI_CONTROL_STOP	= 0x00000010,
+	/* Start bit */
+	MVTWSI_CONTROL_START	= 0x00000020,
+	/* I2C enable */
+	MVTWSI_CONTROL_TWSIEN	= 0x00000040,
+	/* Interrupt enable */
+	MVTWSI_CONTROL_INTEN	= 0x00000080,
+};
 
 /*
  * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1,
@@ -84,22 +92,36 @@ struct  mvtwsi_registers {
 #endif
 
 /*
- * Status register values -- only those expected in normal master
- * operation on non-10-bit-address devices; whatever status we don't
- * expect in nominal conditions (bus errors, arbitration losses,
- * missing ACKs...) we just pass back to the caller as an error
+ * enum mvstwsi_status_values - Possible values of I2C controller's status
+ * register
+ *
+ * Only those statuses expected in normal master operation on
+ * non-10-bit-address devices are specified.
+ *
+ * Every status that's unexpected during normal operation (bus errors,
+ * arbitration losses, missing ACKs...) is passed back to the caller as an error
  * code.
  */
-
-#define	MVTWSI_STATUS_START		0x08
-#define	MVTWSI_STATUS_REPEATED_START	0x10
-#define	MVTWSI_STATUS_ADDR_W_ACK	0x18
-#define	MVTWSI_STATUS_DATA_W_ACK	0x28
-#define	MVTWSI_STATUS_ADDR_R_ACK	0x40
-#define	MVTWSI_STATUS_ADDR_R_NAK	0x48
-#define	MVTWSI_STATUS_DATA_R_ACK	0x50
-#define	MVTWSI_STATUS_DATA_R_NAK	0x58
-#define	MVTWSI_STATUS_IDLE		0xF8
+enum mvstwsi_status_values {
+	/* START condition transmitted */
+	MVTWSI_STATUS_START		= 0x08,
+	/* Repeated START condition transmitted */
+	MVTWSI_STATUS_REPEATED_START	= 0x10,
+	/* Address + write bit transmitted, ACK received */
+	MVTWSI_STATUS_ADDR_W_ACK	= 0x18,
+	/* Data transmitted, ACK received */
+	MVTWSI_STATUS_DATA_W_ACK	= 0x28,
+	/* Address + read bit transmitted, ACK received */
+	MVTWSI_STATUS_ADDR_R_ACK	= 0x40,
+	/* Address + read bit transmitted, ACK not received */
+	MVTWSI_STATUS_ADDR_R_NAK	= 0x48,
+	/* Data received, ACK transmitted */
+	MVTWSI_STATUS_DATA_R_ACK	= 0x50,
+	/* Data received, ACK not transmitted */
+	MVTWSI_STATUS_DATA_R_NAK	= 0x58,
+	/* No relevant status */
+	MVTWSI_STATUS_IDLE		= 0xF8,
+};
 
 /*
  * MVTWSI controller base
@@ -141,20 +163,35 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
 }
 
 /*
- * Returned statuses are 0 for success and nonzero otherwise.
- * Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
- * Thus to ease debugging, the return status contains some debug info:
- * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
- * - bits 23..16 are the last value of the control register.
- * - bits 15..8 are the last value of the status register.
- * - bits 7..0 are the expected value of the status register.
+ * enum mvtwsi_error_class - types of I2C errors
  */
+enum mvtwsi_error_class {
+	/* The controller returned a different status than expected */
+	MVTWSI_ERROR_WRONG_STATUS       = 0x01,
+	/* The controller timed out */
+	MVTWSI_ERROR_TIMEOUT            = 0x02,
+};
 
-#define MVTWSI_ERROR_WRONG_STATUS	0x01
-#define MVTWSI_ERROR_TIMEOUT		0x02
-
-#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
-	((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))
+/*
+ * mvtwsi_error() - Build I2C return code from error information
+ *
+ * For debugging purposes, this function packs some information of an occurred
+ * error into a return code. These error codes are returned from I2C API
+ * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
+ *
+ * @ec:		The error class of the error (enum mvtwsi_error_class).
+ * @lc:		The last value of the control register.
+ * @ls:		The last value of the status register.
+ * @es:		The expected value of the status register.
+ * @return The generated error code.
+ */
+inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
+{
+	return ((ec << 24) & 0xFF000000)
+	       | ((lc << 16) & 0x00FF0000)
+	       | ((ls << 8) & 0x0000FF00)
+	       | (es & 0xFF);
+}
 
 /*
  * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
@@ -173,15 +210,15 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status)
 			if (status == expected_status)
 				return 0;
 			else
-				return MVTWSI_ERROR(
+				return mvtwsi_error(
 					MVTWSI_ERROR_WRONG_STATUS,
 					control, status, expected_status);
 		}
 		udelay(10); /* one clock cycle at 100 kHz */
 	} while (timeout--);
 	status = readl(&twsi->status);
-	return MVTWSI_ERROR(
-		MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
+	return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
+			    expected_status);
 }
 
 /*
@@ -265,7 +302,7 @@ static int twsi_stop(struct i2c_adapter *adap, int status)
 	control = readl(&twsi->control);
 	if (stop_status != MVTWSI_STATUS_IDLE)
 		if (status == 0)
-			status = MVTWSI_ERROR(
+			status = mvtwsi_error(
 				MVTWSI_ERROR_TIMEOUT,
 				control, status, MVTWSI_STATUS_IDLE);
 	return status;
-- 
cgit v0.10.2


From 49c801bf352933b6285873d3d3ca6b315c60710f Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:03 +0200
Subject: i2c: mvtwsi: Improve and fix comments

This patch fixes only comments/documentation: Streamline capitalization
and improve grammar/punctuation.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 93bb88b..7b2c611 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -14,8 +14,8 @@
 #include <asm/io.h>
 
 /*
- * include a file that will provide CONFIG_I2C_MVTWSI_BASE*
- * and possibly other settings
+ * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
+ * settings
  */
 
 #if defined(CONFIG_ORION5X)
@@ -51,8 +51,8 @@ struct  mvtwsi_registers {
 	u32 data;
 	u32 control;
 	union {
-		u32 status;	/* when reading */
-		u32 baudrate;	/* when writing */
+		u32 status;	/* When reading */
+		u32 baudrate;	/* When writing */
 	};
 	u32 xtnd_slave_addr;
 	u32 reserved[2];
@@ -81,8 +81,8 @@ enum mvtwsi_ctrl_register_fields {
 };
 
 /*
- * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1,
- * on other platforms it is a normal r/w bit which is cleared by writing 0.
+ * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
+ * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
  */
 
 #ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -194,8 +194,8 @@ inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
 }
 
 /*
- * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
- * return 0 (ok) or return 'wrong status'.
+ * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
+ * expected, return 0 (ok) or 'wrong status' otherwise.
  */
 static int twsi_wait(struct i2c_adapter *adap, int expected_status)
 {
@@ -214,7 +214,7 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status)
 					MVTWSI_ERROR_WRONG_STATUS,
 					control, status, expected_status);
 		}
-		udelay(10); /* one clock cycle at 100 kHz */
+		udelay(10); /* One clock cycle at 100 kHz */
 	} while (timeout--);
 	status = readl(&twsi->status);
 	return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
@@ -229,12 +229,12 @@ static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
-	/* globally set TWSIEN in case it was not */
+	/* Set TWSIEN */
 	*flags |= MVTWSI_CONTROL_TWSIEN;
-	/* assert START */
+	/* Assert START */
 	writel(*flags | MVTWSI_CONTROL_START |
-				    MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
-	/* wait for controller to process START */
+	       MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	/* Wait for controller to process START */
 	return twsi_wait(adap, expected_status);
 }
 
@@ -246,42 +246,40 @@ static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
-	/* put byte in data register for sending */
+	/* Write byte to data register for sending */
 	writel(byte, &twsi->data);
-	/* clear any pending interrupt -- that'll cause sending */
+	/* Clear any pending interrupt -- that will cause sending */
 	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
-	/* wait for controller to receive byte and check ACK */
+	/* Wait for controller to receive byte, and check ACK */
 	return twsi_wait(adap, expected_status);
 }
 
 /*
  * Receive a byte.
- * Global mvtwsi_control_flags variable says if we should ack or nak.
  */
 static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int expected_status, status;
 
-	/* compute expected status based on ACK bit in global control flags */
+	/* Compute expected status based on ACK bit in passed control flags */
 	if (*flags & MVTWSI_CONTROL_ACK)
 		expected_status = MVTWSI_STATUS_DATA_R_ACK;
 	else
 		expected_status = MVTWSI_STATUS_DATA_R_NAK;
-	/* acknowledge *previous state* and launch receive */
+	/* Acknowledge *previous state*, and launch receive */
 	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
-	/* wait for controller to receive byte and assert ACK or NAK */
+	/* Wait for controller to receive byte, and assert ACK or NAK */
 	status = twsi_wait(adap, expected_status);
-	/* if we did receive expected byte then store it */
+	/* If we did receive the expected byte, store it */
 	if (status == 0)
 		*byte = readl(&twsi->data);
-	/* return status */
 	return status;
 }
 
 /*
  * Assert the STOP condition.
- * This is also used to force the bus back in idle (SDA=SCL=1).
+ * This is also used to force the bus back to idle (SDA = SCL = 1).
  */
 static int twsi_stop(struct i2c_adapter *adap, int status)
 {
@@ -289,15 +287,15 @@ static int twsi_stop(struct i2c_adapter *adap, int status)
 	int control, stop_status;
 	int timeout = 1000;
 
-	/* assert STOP */
+	/* Assert STOP */
 	control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
 	writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
-	/* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
+	/* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
 	do {
 		stop_status = readl(&twsi->status);
 		if (stop_status == MVTWSI_STATUS_IDLE)
 			break;
-		udelay(10); /* one clock cycle at 100 kHz */
+		udelay(10); /* One clock cycle at 100 kHz */
 	} while (timeout--);
 	control = readl(&twsi->control);
 	if (stop_status != MVTWSI_STATUS_IDLE)
@@ -326,26 +324,26 @@ static void twsi_reset(struct i2c_adapter *adap)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
-	/* reset controller */
+	/* Reset controller */
 	writel(0, &twsi->soft_reset);
-	/* wait 2 ms -- this is what the Marvell LSP does */
+	/* Wait 2 ms -- this is what the Marvell LSP does */
 	udelay(20000);
 }
 
 /*
- * I2C init called by cmd_i2c when doing 'i2c reset'.
- * Sets baud to the highest possible value not exceeding requested one.
+ * Sets baud to the highest possible value not exceeding the requested one.
  */
 static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 					   unsigned int requested_speed)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	unsigned int tmp_speed, highest_speed, n, m;
-	unsigned int baud = 0x44; /* baudrate at controller reset */
+	unsigned int baud = 0x44; /* Baud rate after controller reset */
 
-	/* use actual speed to collect progressively higher values */
 	highest_speed = 0;
-	/* compute m, n setting for highest speed not above requested speed */
+	/* Successively try m, n combinations, and use the combination
+	 * resulting in the largest speed that's not above the requested
+	 * speed */
 	for (n = 0; n < 8; n++) {
 		for (m = 0; m < 16; m++) {
 			tmp_speed = twsi_calc_freq(n, m);
@@ -364,20 +362,19 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
-	/* reset controller */
+	/* Reset controller */
 	twsi_reset(adap);
-	/* set speed */
+	/* Set speed */
 	twsi_i2c_set_bus_speed(adap, speed);
-	/* set slave address even though we don't use it */
+	/* Set slave address; even though we don't use it */
 	writel(slaveadd, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
-	/* assert STOP but don't care for the result */
+	/* Assert STOP, but don't care for the result */
 	(void) twsi_stop(adap, 0);
 }
 
 /*
  * Begin I2C transaction with expected start status, at given address.
- * Common to i2c_probe, i2c_read and i2c_write.
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
 static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
@@ -385,23 +382,23 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 {
 	int status, expected_addr_status;
 
-	/* compute expected address status from direction bit in addr */
-	if (addr & 1) /* reading */
+	/* Compute the expected address status from the direction bit in
+	 * the address byte */
+	if (addr & 1) /* Reading */
 		expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
-	else /* writing */
+	else /* Writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
-	/* assert START */
+	/* Assert START */
 	status = twsi_start(adap, expected_start_status, flags);
-	/* send out the address if the start went well */
+	/* Send out the address if the start went well */
 	if (status == 0)
 		status = twsi_send(adap, addr, expected_addr_status,
 				   flags);
-	/* return ok or status of first failure to caller */
+	/* Return 0, or the status of the first failure */
 	return status;
 }
 
 /*
- * I2C probe called by cmd_i2c when doing 'i2c probe'.
  * Begin read, nak data byte, end.
  */
 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
@@ -410,26 +407,24 @@ static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 	u8 flags = 0;
 	int status;
 
-	/* begin i2c read */
+	/* Begin i2c read */
 	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
-	/* dummy read was accepted: receive byte but NAK it. */
+	/* Dummy read was accepted: receive byte, but NAK it. */
 	if (status == 0)
 		status = twsi_recv(adap, &dummy_byte, &flags);
 	/* Stop transaction */
 	twsi_stop(adap, 0);
-	/* return 0 or status of first failure */
+	/* Return 0, or the status of the first failure */
 	return status;
 }
 
 /*
- * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
  * Begin write, send address byte(s), begin read, receive data bytes, end.
  *
- * NOTE: some EEPROMS want a stop right before the second start, while
- * some will choke if it is there. Deciding which we should do is eeprom
- * stuff, not i2c, but at the moment the APIs won't let us put it in
- * cmd_eeprom, so we have to choose here, and for the moment that'll be
- * a repeated start without a preceding stop.
+ * NOTE: Some devices want a stop right before the second start, while some
+ * will choke if it is there. Since deciding this is not yet supported in
+ * higher level APIs, we need to make a decision here, and for the moment that
+ * will be a repeated start without a preceding stop.
  */
 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
@@ -437,35 +432,34 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 	int status;
 	u8 flags = 0;
 
-	/* begin i2c write to send the address bytes */
+	/* Begin i2c write to send the address bytes */
 	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
-	/* send addr bytes */
+	/* Send address bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
 			MVTWSI_STATUS_DATA_W_ACK, &flags);
-	/* begin i2c read to receive eeprom data bytes */
+	/* Begin i2c read to receive data bytes */
 	if (status == 0)
 		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
 				   (chip << 1) | 1, &flags);
-	/* prepare ACK if at least one byte must be received */
+	/* Prepare ACK if at least one byte must be received */
 	if (length > 0)
 		flags |= MVTWSI_CONTROL_ACK;
-	/* now receive actual bytes */
+	/* Receive actual data bytes */
 	while ((status == 0) && length--) {
-		/* reset NAK if we if no more to read now */
+		/* Set NAK if we if we have nothing more to read */
 		if (length == 0)
 			flags &= ~MVTWSI_CONTROL_ACK;
-		/* read current byte */
+		/* Read current byte */
 		status = twsi_recv(adap, data++, &flags);
 	}
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
-	/* return 0 or status of first failure */
+	/* Return 0, or the status of the first failure */
 	return status;
 }
 
 /*
- * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
  * Begin write, send address byte(s), send data bytes, end.
  */
 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
@@ -474,19 +468,20 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	int status;
 	u8 flags = 0;
 
-	/* begin i2c write to send the eeprom adress bytes then data bytes */
+	/* Begin i2c write to send first the address bytes, then the
+	 * data bytes */
 	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
-	/* send addr bytes */
+	/* Send address bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
 			MVTWSI_STATUS_DATA_W_ACK, &flags);
-	/* send data bytes */
+	/* Send data bytes */
 	while ((status == 0) && (length-- > 0))
 		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
 				   &flags);
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
-	/* return 0 or status of first failure */
+	/* Return 0, or the status of the first failure */
 	return status;
 }
 
-- 
cgit v0.10.2


From 670514f52479cd1e0ae7952f45fef5779719aef2 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:04 +0200
Subject: i2c: mvtwsi: Eliminate flags parameter

Due to breaking boots from NOR flashes, commit d6b7757 ("i2c: mvtwsi:
Eliminate twsi_control_flags") removed the static global
twsi_control_flags variable, which kept a set of default flags that were
always or'd to the control register when writing. It was replaced with a
flags parameter, which was passed around between the functions that
needed it.

Since the twsi_control_flags variable was used just for the purposes of
a) setting the MVTWSI_CONTROL_TWSIEN on every control register write,
   and
b) setting the MVTWSI_CONTROL_ACK from twsi_i2c_read if needed,
anyway, the added overhead of another variable being passed around is no
longer justified, and we are better off implementing this flag setting
logic locally in the functions that actually write to the control
register.

Therefore, this patch sets MVTWSI_CONTROL_TWSIEN on every control
register write, replaces the twsi_i2c_read's flags parameter with a
ack_flag parameter, which tells the function whether to acknowledge the
read or not, and removes every other instance of the flags variable.
This has the added benefit that now every notion of "global default
flags" is gone, and it's much easier to see which control flags are
actually set at which point in time.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 7b2c611..4a34eab 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -124,6 +124,17 @@ enum mvstwsi_status_values {
 };
 
 /*
+ * enum mvstwsi_ack_flags - Determine whether a read byte should be
+ * acknowledged or not.
+ */
+enum mvtwsi_ack_flags {
+	/* Send NAK after received byte */
+	MVTWSI_READ_NAK = 0,
+	/* Send ACK after received byte */
+	MVTWSI_READ_ACK = 1,
+};
+
+/*
  * MVTWSI controller base
  */
 
@@ -225,14 +236,12 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status)
  * Assert the START condition, either in a single I2C transaction
  * or inside back-to-back ones (repeated starts).
  */
-static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
+static int twsi_start(struct i2c_adapter *adap, int expected_status)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
-	/* Set TWSIEN */
-	*flags |= MVTWSI_CONTROL_TWSIEN;
 	/* Assert START */
-	writel(*flags | MVTWSI_CONTROL_START |
+	writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
 	       MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* Wait for controller to process START */
 	return twsi_wait(adap, expected_status);
@@ -241,15 +250,15 @@ static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
 /*
  * Send a byte (i2c address or data).
  */
-static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
-		     u8 *flags)
+static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
 	/* Write byte to data register for sending */
 	writel(byte, &twsi->data);
 	/* Clear any pending interrupt -- that will cause sending */
-	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
+	       &twsi->control);
 	/* Wait for controller to receive byte, and check ACK */
 	return twsi_wait(adap, expected_status);
 }
@@ -257,18 +266,18 @@ static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
 /*
  * Receive a byte.
  */
-static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
+static int twsi_recv(struct i2c_adapter *adap, u8 *byte, int ack_flag)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	int expected_status, status;
+	int expected_status, status, control;
 
-	/* Compute expected status based on ACK bit in passed control flags */
-	if (*flags & MVTWSI_CONTROL_ACK)
-		expected_status = MVTWSI_STATUS_DATA_R_ACK;
-	else
-		expected_status = MVTWSI_STATUS_DATA_R_NAK;
+	/* Compute expected status based on passed ACK flag */
+	expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
+			  MVTWSI_STATUS_DATA_R_NAK;
 	/* Acknowledge *previous state*, and launch receive */
-	writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+	control = MVTWSI_CONTROL_TWSIEN;
+	control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
+	writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* Wait for controller to receive byte, and assert ACK or NAK */
 	status = twsi_wait(adap, expected_status);
 	/* If we did receive the expected byte, store it */
@@ -378,7 +387,7 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
 static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
-		     u8 addr, u8 *flags)
+		     u8 addr)
 {
 	int status, expected_addr_status;
 
@@ -389,11 +398,10 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 	else /* Writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 	/* Assert START */
-	status = twsi_start(adap, expected_start_status, flags);
+	status = twsi_start(adap, expected_start_status);
 	/* Send out the address if the start went well */
 	if (status == 0)
-		status = twsi_send(adap, addr, expected_addr_status,
-				   flags);
+		status = twsi_send(adap, addr, expected_addr_status);
 	/* Return 0, or the status of the first failure */
 	return status;
 }
@@ -404,14 +412,13 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	u8 dummy_byte;
-	u8 flags = 0;
 	int status;
 
 	/* Begin i2c read */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
 	/* Dummy read was accepted: receive byte, but NAK it. */
 	if (status == 0)
-		status = twsi_recv(adap, &dummy_byte, &flags);
+		status = twsi_recv(adap, &dummy_byte, MVTWSI_READ_NAK);
 	/* Stop transaction */
 	twsi_stop(adap, 0);
 	/* Return 0, or the status of the first failure */
@@ -430,29 +437,23 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
 {
 	int status;
-	u8 flags = 0;
 
 	/* Begin i2c write to send the address bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
 	/* Send address bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK, &flags);
+			MVTWSI_STATUS_DATA_W_ACK);
 	/* Begin i2c read to receive data bytes */
 	if (status == 0)
 		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
-				   (chip << 1) | 1, &flags);
-	/* Prepare ACK if at least one byte must be received */
-	if (length > 0)
-		flags |= MVTWSI_CONTROL_ACK;
-	/* Receive actual data bytes */
-	while ((status == 0) && length--) {
-		/* Set NAK if we if we have nothing more to read */
-		if (length == 0)
-			flags &= ~MVTWSI_CONTROL_ACK;
-		/* Read current byte */
-		status = twsi_recv(adap, data++, &flags);
-	}
+				   (chip << 1) | 1);
+	/* Receive actual data bytes; set NAK if we if we have nothing more to
+	 * read */
+	while ((status == 0) && length--)
+		status = twsi_recv(adap, data++,
+				   length > 0 ?
+				   MVTWSI_READ_ACK : MVTWSI_READ_NAK);
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
 	/* Return 0, or the status of the first failure */
@@ -466,19 +467,17 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
 {
 	int status;
-	u8 flags = 0;
 
 	/* Begin i2c write to send first the address bytes, then the
 	 * data bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
 	/* Send address bytes */
 	while ((status == 0) && alen--)
 		status = twsi_send(adap, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK, &flags);
+			MVTWSI_STATUS_DATA_W_ACK);
 	/* Send data bytes */
 	while ((status == 0) && (length-- > 0))
-		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
-				   &flags);
+		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
 	/* Stop transaction */
 	status = twsi_stop(adap, status);
 	/* Return 0, or the status of the first failure */
-- 
cgit v0.10.2


From 059fce9f61fd81ab67555b9ba87e12cc4b8db8f6 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:05 +0200
Subject: i2c: mvtwsi: Get rid of status parameter

The twsi_stop function contains a parameter "status," which is used to
pass in the current exit status of the function calling twsi_stop, and
either return this status unchanged if it indicates an error, or return
twsi_stop's exit status if it does not indicate an error.

While not massively complicated, this adds another purpose to the
twsi_stop function, which should have the sole purpose of asserting a
STOP condition on the bus (and not manage the exit status of its
caller).

Therefore, we move the exit status management into the caller functions
by introducing a "stop_status" variable and returning either the status
before the twsi_stop call (kept in the "status" variable), or the status
from the twsi_stop call, depending on which indicates an error.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 4a34eab..d0e3c3f 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -290,10 +290,11 @@ static int twsi_recv(struct i2c_adapter *adap, u8 *byte, int ack_flag)
  * Assert the STOP condition.
  * This is also used to force the bus back to idle (SDA = SCL = 1).
  */
-static int twsi_stop(struct i2c_adapter *adap, int status)
+static int twsi_stop(struct i2c_adapter *adap)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int control, stop_status;
+	int status = 0;
 	int timeout = 1000;
 
 	/* Assert STOP */
@@ -308,10 +309,8 @@ static int twsi_stop(struct i2c_adapter *adap, int status)
 	} while (timeout--);
 	control = readl(&twsi->control);
 	if (stop_status != MVTWSI_STATUS_IDLE)
-		if (status == 0)
-			status = mvtwsi_error(
-				MVTWSI_ERROR_TIMEOUT,
-				control, status, MVTWSI_STATUS_IDLE);
+		status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
+				      control, status, MVTWSI_STATUS_IDLE);
 	return status;
 }
 
@@ -379,7 +378,7 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 	writel(slaveadd, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
 	/* Assert STOP, but don't care for the result */
-	(void) twsi_stop(adap, 0);
+	(void) twsi_stop(adap);
 }
 
 /*
@@ -420,7 +419,7 @@ static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 	if (status == 0)
 		status = twsi_recv(adap, &dummy_byte, MVTWSI_READ_NAK);
 	/* Stop transaction */
-	twsi_stop(adap, 0);
+	twsi_stop(adap);
 	/* Return 0, or the status of the first failure */
 	return status;
 }
@@ -436,7 +435,8 @@ static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
 {
-	int status;
+	int status = 0;
+	int stop_status;
 
 	/* Begin i2c write to send the address bytes */
 	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
@@ -455,9 +455,9 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 				   length > 0 ?
 				   MVTWSI_READ_ACK : MVTWSI_READ_NAK);
 	/* Stop transaction */
-	status = twsi_stop(adap, status);
+	stop_status = twsi_stop(adap);
 	/* Return 0, or the status of the first failure */
-	return status;
+	return status != 0 ? status : stop_status;
 }
 
 /*
@@ -466,7 +466,7 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			int alen, uchar *data, int length)
 {
-	int status;
+	int status, stop_status;
 
 	/* Begin i2c write to send first the address bytes, then the
 	 * data bytes */
@@ -479,9 +479,9 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	while ((status == 0) && (length-- > 0))
 		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
 	/* Stop transaction */
-	status = twsi_stop(adap, status);
+	stop_status = twsi_stop(adap);
 	/* Return 0, or the status of the first failure */
-	return status;
+	return status != 0 ? status : stop_status;
 }
 
 #ifdef CONFIG_I2C_MVTWSI_BASE0
-- 
cgit v0.10.2


From e075828128d961d873484bb02ac8101bc733a1d7 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:06 +0200
Subject: i2c: mvtwsi: Use 'uint' instead of 'unsigned int'

Since some additional parameters will be added in the course of this
patch series (especially with the addition of DM support), we replace
the longer "unsigned int" declarations with "uint" declarations to keep
the parameter lists more readable.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index d0e3c3f..9ddd3ee 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -314,7 +314,7 @@ static int twsi_stop(struct i2c_adapter *adap)
 	return status;
 }
 
-static unsigned int twsi_calc_freq(const int n, const int m)
+static uint twsi_calc_freq(const int n, const int m)
 {
 #ifdef CONFIG_SUNXI
 	return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
@@ -341,12 +341,12 @@ static void twsi_reset(struct i2c_adapter *adap)
 /*
  * Sets baud to the highest possible value not exceeding the requested one.
  */
-static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
-					   unsigned int requested_speed)
+static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
+				   uint requested_speed)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	unsigned int tmp_speed, highest_speed, n, m;
-	unsigned int baud = 0x44; /* Baud rate after controller reset */
+	uint tmp_speed, highest_speed, n, m;
+	uint baud = 0x44; /* Baud rate after controller reset */
 
 	highest_speed = 0;
 	/* Successively try m, n combinations, and use the combination
-- 
cgit v0.10.2


From 61bc02b2608722204c1f16a74cd8851db5ee311d Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:07 +0200
Subject: i2c: mvtwsi: Add compatibility functions

To prepare for the DM conversion, we add a layer of compatibility
functions to be used by both the legacy and the DM functions.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 9ddd3ee..f1bfd5d 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -341,8 +341,8 @@ static void twsi_reset(struct i2c_adapter *adap)
 /*
  * Sets baud to the highest possible value not exceeding the requested one.
  */
-static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
-				   uint requested_speed)
+static uint __twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
+				     uint requested_speed)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	uint tmp_speed, highest_speed, n, m;
@@ -366,14 +366,14 @@ static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 	return 0;
 }
 
-static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 
 	/* Reset controller */
 	twsi_reset(adap);
 	/* Set speed */
-	twsi_i2c_set_bus_speed(adap, speed);
+	__twsi_i2c_set_bus_speed(adap, speed);
 	/* Set slave address; even though we don't use it */
 	writel(slaveadd, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
@@ -408,7 +408,7 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 /*
  * Begin read, nak data byte, end.
  */
-static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
+static int __twsi_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 {
 	u8 dummy_byte;
 	int status;
@@ -432,8 +432,8 @@ static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
  * higher level APIs, we need to make a decision here, and for the moment that
  * will be a repeated start without a preceding stop.
  */
-static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
-			int alen, uchar *data, int length)
+static int __twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			   int alen, uchar *data, int length)
 {
 	int status = 0;
 	int stop_status;
@@ -463,8 +463,8 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 /*
  * Begin write, send address byte(s), send data bytes, end.
  */
-static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
-			int alen, uchar *data, int length)
+static int __twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			    int alen, uchar *data, int length)
 {
 	int status, stop_status;
 
@@ -484,6 +484,35 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	return status != 0 ? status : stop_status;
 }
 
+static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
+			  int slaveadd)
+{
+	__twsi_i2c_init(adap, speed, slaveadd);
+}
+
+static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
+				   uint requested_speed)
+{
+	return __twsi_i2c_set_bus_speed(adap, requested_speed);
+}
+
+static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+	return __twsi_i2c_probe_chip(adap, chip);
+}
+
+static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+			 int alen, uchar *data, int length)
+{
+	return __twsi_i2c_read(adap, chip, addr, alen, data, length);
+}
+
+static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+			  int alen, uchar *data, int length)
+{
+	return __twsi_i2c_write(adap, chip, addr, alen, data, length);
+}
+
 #ifdef CONFIG_I2C_MVTWSI_BASE0
 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
 			 twsi_i2c_read, twsi_i2c_write,
-- 
cgit v0.10.2


From 3c4db636ac918a35c4c6671e8d060e3a72ba7c94 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:08 +0200
Subject: i2c: mvtwsi: Factor out adap parameter

To be able to use the compatibility layer from the DM functions, we
factor the adap parameter out of all functions, and pass the actual
register base instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index f1bfd5d..688efc2 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -208,9 +208,8 @@ inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
  * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
  * expected, return 0 (ok) or 'wrong status' otherwise.
  */
-static int twsi_wait(struct i2c_adapter *adap, int expected_status)
+static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int control, status;
 	int timeout = 1000;
 
@@ -236,39 +235,35 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status)
  * Assert the START condition, either in a single I2C transaction
  * or inside back-to-back ones (repeated starts).
  */
-static int twsi_start(struct i2c_adapter *adap, int expected_status)
+static int twsi_start(struct mvtwsi_registers *twsi, int expected_status)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-
 	/* Assert START */
 	writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
 	       MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* Wait for controller to process START */
-	return twsi_wait(adap, expected_status);
+	return twsi_wait(twsi, expected_status);
 }
 
 /*
  * Send a byte (i2c address or data).
  */
-static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
+static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
+		     int expected_status)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-
 	/* Write byte to data register for sending */
 	writel(byte, &twsi->data);
 	/* Clear any pending interrupt -- that will cause sending */
 	writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
 	       &twsi->control);
 	/* Wait for controller to receive byte, and check ACK */
-	return twsi_wait(adap, expected_status);
+	return twsi_wait(twsi, expected_status);
 }
 
 /*
  * Receive a byte.
  */
-static int twsi_recv(struct i2c_adapter *adap, u8 *byte, int ack_flag)
+static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int expected_status, status, control;
 
 	/* Compute expected status based on passed ACK flag */
@@ -279,7 +274,7 @@ static int twsi_recv(struct i2c_adapter *adap, u8 *byte, int ack_flag)
 	control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
 	writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* Wait for controller to receive byte, and assert ACK or NAK */
-	status = twsi_wait(adap, expected_status);
+	status = twsi_wait(twsi, expected_status);
 	/* If we did receive the expected byte, store it */
 	if (status == 0)
 		*byte = readl(&twsi->data);
@@ -290,9 +285,8 @@ static int twsi_recv(struct i2c_adapter *adap, u8 *byte, int ack_flag)
  * Assert the STOP condition.
  * This is also used to force the bus back to idle (SDA = SCL = 1).
  */
-static int twsi_stop(struct i2c_adapter *adap)
+static int twsi_stop(struct mvtwsi_registers *twsi)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int control, stop_status;
 	int status = 0;
 	int timeout = 1000;
@@ -328,10 +322,8 @@ static uint twsi_calc_freq(const int n, const int m)
  * Controller reset also resets the baud rate and slave address, so
  * they must be re-established afterwards.
  */
-static void twsi_reset(struct i2c_adapter *adap)
+static void twsi_reset(struct mvtwsi_registers *twsi)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-
 	/* Reset controller */
 	writel(0, &twsi->soft_reset);
 	/* Wait 2 ms -- this is what the Marvell LSP does */
@@ -341,10 +333,9 @@ static void twsi_reset(struct i2c_adapter *adap)
 /*
  * Sets baud to the highest possible value not exceeding the requested one.
  */
-static uint __twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
+static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
 				     uint requested_speed)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	uint tmp_speed, highest_speed, n, m;
 	uint baud = 0x44; /* Baud rate after controller reset */
 
@@ -366,26 +357,25 @@ static uint __twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 	return 0;
 }
 
-static void __twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
+			  int slaveadd)
 {
-	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-
 	/* Reset controller */
-	twsi_reset(adap);
+	twsi_reset(twsi);
 	/* Set speed */
-	__twsi_i2c_set_bus_speed(adap, speed);
+	__twsi_i2c_set_bus_speed(twsi, speed);
 	/* Set slave address; even though we don't use it */
 	writel(slaveadd, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
 	/* Assert STOP, but don't care for the result */
-	(void) twsi_stop(adap);
+	(void) twsi_stop(twsi);
 }
 
 /*
  * Begin I2C transaction with expected start status, at given address.
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
-static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
+static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
 		     u8 addr)
 {
 	int status, expected_addr_status;
@@ -397,10 +387,10 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 	else /* Writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 	/* Assert START */
-	status = twsi_start(adap, expected_start_status);
+	status = twsi_start(twsi, expected_start_status);
 	/* Send out the address if the start went well */
 	if (status == 0)
-		status = twsi_send(adap, addr, expected_addr_status);
+		status = twsi_send(twsi, addr, expected_addr_status);
 	/* Return 0, or the status of the first failure */
 	return status;
 }
@@ -408,18 +398,18 @@ static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
 /*
  * Begin read, nak data byte, end.
  */
-static int __twsi_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip)
 {
 	u8 dummy_byte;
 	int status;
 
 	/* Begin i2c read */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
+	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1);
 	/* Dummy read was accepted: receive byte, but NAK it. */
 	if (status == 0)
-		status = twsi_recv(adap, &dummy_byte, MVTWSI_READ_NAK);
+		status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK);
 	/* Stop transaction */
-	twsi_stop(adap);
+	twsi_stop(twsi);
 	/* Return 0, or the status of the first failure */
 	return status;
 }
@@ -432,30 +422,30 @@ static int __twsi_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
  * higher level APIs, we need to make a decision here, and for the moment that
  * will be a repeated start without a preceding stop.
  */
-static int __twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
-			   int alen, uchar *data, int length)
+static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
+			   uint addr, int alen, uchar *data, int length)
 {
 	int status = 0;
 	int stop_status;
 
 	/* Begin i2c write to send the address bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
 	/* Send address bytes */
 	while ((status == 0) && alen--)
-		status = twsi_send(adap, addr >> (8*alen),
+		status = twsi_send(twsi, addr >> (8*alen),
 			MVTWSI_STATUS_DATA_W_ACK);
 	/* Begin i2c read to receive data bytes */
 	if (status == 0)
-		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
+		status = i2c_begin(twsi, MVTWSI_STATUS_REPEATED_START,
 				   (chip << 1) | 1);
 	/* Receive actual data bytes; set NAK if we if we have nothing more to
 	 * read */
 	while ((status == 0) && length--)
-		status = twsi_recv(adap, data++,
+		status = twsi_recv(twsi, data++,
 				   length > 0 ?
 				   MVTWSI_READ_ACK : MVTWSI_READ_NAK);
 	/* Stop transaction */
-	stop_status = twsi_stop(adap);
+	stop_status = twsi_stop(twsi);
 	/* Return 0, or the status of the first failure */
 	return status != 0 ? status : stop_status;
 }
@@ -463,23 +453,23 @@ static int __twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 /*
  * Begin write, send address byte(s), send data bytes, end.
  */
-static int __twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
-			    int alen, uchar *data, int length)
+static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
+			    uint addr, int alen, uchar *data, int length)
 {
 	int status, stop_status;
 
 	/* Begin i2c write to send first the address bytes, then the
 	 * data bytes */
-	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
 	/* Send address bytes */
 	while ((status == 0) && alen--)
-		status = twsi_send(adap, addr >> (8*alen),
+		status = twsi_send(twsi, addr >> (8*alen),
 			MVTWSI_STATUS_DATA_W_ACK);
 	/* Send data bytes */
 	while ((status == 0) && (length-- > 0))
-		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK);
 	/* Stop transaction */
-	stop_status = twsi_stop(adap);
+	stop_status = twsi_stop(twsi);
 	/* Return 0, or the status of the first failure */
 	return status != 0 ? status : stop_status;
 }
@@ -487,30 +477,35 @@ static int __twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
 			  int slaveadd)
 {
-	__twsi_i2c_init(adap, speed, slaveadd);
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+	__twsi_i2c_init(twsi, speed, slaveadd);
 }
 
 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 				   uint requested_speed)
 {
-	return __twsi_i2c_set_bus_speed(adap, requested_speed);
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+	return __twsi_i2c_set_bus_speed(twsi, requested_speed);
 }
 
 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
-	return __twsi_i2c_probe_chip(adap, chip);
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+	return __twsi_i2c_probe_chip(twsi, chip);
 }
 
 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			 int alen, uchar *data, int length)
 {
-	return __twsi_i2c_read(adap, chip, addr, alen, data, length);
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+	return __twsi_i2c_read(twsi, chip, addr, alen, data, length);
 }
 
 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			  int alen, uchar *data, int length)
 {
-	return __twsi_i2c_write(adap, chip, addr, alen, data, length);
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+	return __twsi_i2c_write(twsi, chip, addr, alen, data, length);
 }
 
 #ifdef CONFIG_I2C_MVTWSI_BASE0
-- 
cgit v0.10.2


From f8a10ed1fd9986362a39f2b18d89429dfdb078cb Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:09 +0200
Subject: i2c: mvtwsi: Make address length variable

The length of the address parameter of the __twsi_i2c_read and
__twsi_i2c_write functions is fixed to four bytes.

As a final step in the preparation of the DM conversion, we make the
length of this parameter variable by turning it into an array of bytes,
and convert the 32 bit value that's passed to the legacy functions into
a four-byte-array on the fly.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 688efc2..3325c4b 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -423,7 +423,7 @@ static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip)
  * will be a repeated start without a preceding stop.
  */
 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
-			   uint addr, int alen, uchar *data, int length)
+			   u8 *addr, int alen, uchar *data, int length)
 {
 	int status = 0;
 	int stop_status;
@@ -432,8 +432,7 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
 	/* Send address bytes */
 	while ((status == 0) && alen--)
-		status = twsi_send(twsi, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK);
 	/* Begin i2c read to receive data bytes */
 	if (status == 0)
 		status = i2c_begin(twsi, MVTWSI_STATUS_REPEATED_START,
@@ -454,7 +453,7 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
  * Begin write, send address byte(s), send data bytes, end.
  */
 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
-			    uint addr, int alen, uchar *data, int length)
+			    u8 *addr, int alen, uchar *data, int length)
 {
 	int status, stop_status;
 
@@ -462,9 +461,8 @@ static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
 	 * data bytes */
 	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
 	/* Send address bytes */
-	while ((status == 0) && alen--)
-		status = twsi_send(twsi, addr >> (8*alen),
-			MVTWSI_STATUS_DATA_W_ACK);
+	while ((status == 0) && (alen-- > 0))
+		status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK);
 	/* Send data bytes */
 	while ((status == 0) && (length-- > 0))
 		status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK);
@@ -498,14 +496,28 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			 int alen, uchar *data, int length)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	return __twsi_i2c_read(twsi, chip, addr, alen, data, length);
+	u8 addr_bytes[4];
+
+	addr_bytes[0] = (addr >> 0) & 0xFF;
+	addr_bytes[1] = (addr >> 8) & 0xFF;
+	addr_bytes[2] = (addr >> 16) & 0xFF;
+	addr_bytes[3] = (addr >> 24) & 0xFF;
+
+	return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length);
 }
 
 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			  int alen, uchar *data, int length)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	return __twsi_i2c_write(twsi, chip, addr, alen, data, length);
+	u8 addr_bytes[4];
+
+	addr_bytes[0] = (addr >> 0) & 0xFF;
+	addr_bytes[1] = (addr >> 8) & 0xFF;
+	addr_bytes[2] = (addr >> 16) & 0xFF;
+	addr_bytes[3] = (addr >> 24) & 0xFF;
+
+	return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length);
 }
 
 #ifdef CONFIG_I2C_MVTWSI_BASE0
-- 
cgit v0.10.2


From 14a6ff2c4f22010e5d67f25508f09e3b53a1f1c4 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:10 +0200
Subject: i2c: mvtwsi: Add compatibility to DM

This patch adds the necessary functions and Kconfig entry to make the
MVTWSI I2C driver compatible with the driver model.

A possible device tree entry might look like this:

i2c@11100 {
	compatible = "marvell,mv64xxx-i2c";
	reg = <0x11000 0x20>;
	clock-frequency = <100000>;
	u-boot,i2c-slave-addr = <0x0>;
};

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 6e22bba..b3e8405 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -154,6 +154,13 @@ config SYS_I2C_UNIPHIER_F
 	  Support for UniPhier FIFO-builtin I2C controller driver.
 	  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
 
+config SYS_I2C_MVTWSI
+	bool "Marvell I2C driver"
+	depends on DM_I2C
+	help
+	  Support for Marvell I2C controllers as used on the orion5x and
+	  kirkwood SoC families.
+
 source "drivers/i2c/muxes/Kconfig"
 
 endmenu
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 3325c4b..f694527 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -12,12 +12,18 @@
 #include <i2c.h>
 #include <asm/errno.h>
 #include <asm/io.h>
+#ifdef CONFIG_DM_I2C
+#include <dm.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
  * settings
  */
 
+#ifndef CONFIG_DM_I2C
 #if defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
@@ -27,6 +33,7 @@
 #else
 #error Driver mvtwsi not supported by SoC or board
 #endif
+#endif /* CONFIG_DM_I2C */
 
 /*
  * TWSI register structure
@@ -61,6 +68,19 @@ struct  mvtwsi_registers {
 
 #endif
 
+#ifdef CONFIG_DM_I2C
+struct mvtwsi_i2c_dev {
+	/* TWSI Register base for the device */
+	struct mvtwsi_registers *base;
+	/* Number of the device (determined from cell-index property) */
+	int index;
+	/* The I2C slave address for the device */
+	u8 slaveadd;
+	/* The configured I2C speed in Hz */
+	uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+
 /*
  * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
  * register
@@ -134,6 +154,7 @@ enum mvtwsi_ack_flags {
 	MVTWSI_READ_ACK = 1,
 };
 
+#ifndef CONFIG_DM_I2C
 /*
  * MVTWSI controller base
  */
@@ -172,6 +193,7 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
 
 	return NULL;
 }
+#endif
 
 /*
  * enum mvtwsi_error_class - types of I2C errors
@@ -358,7 +380,7 @@ static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
 }
 
 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
-			  int slaveadd)
+			    int slaveadd)
 {
 	/* Reset controller */
 	twsi_reset(twsi);
@@ -472,6 +494,7 @@ static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
 	return status != 0 ? status : stop_status;
 }
 
+#ifndef CONFIG_DM_I2C
 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
 			  int slaveadd)
 {
@@ -561,3 +584,89 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
 			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
 
 #endif
+#else /* CONFIG_DM_I2C */
+
+static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+				 u32 chip_flags)
+{
+	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
+	return __twsi_i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
+{
+	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
+	return __twsi_i2c_set_bus_speed(dev->base, speed);
+}
+
+static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
+
+	dev->base = dev_get_addr_ptr(bus);
+
+	if (!dev->base)
+		return -ENOMEM;
+
+	dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				    "cell-index", -1);
+	dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				       "u-boot,i2c-slave-addr", 0x0);
+	dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+				    "clock-frequency", 100000);
+	return 0;
+}
+
+static int mvtwsi_i2c_probe(struct udevice *bus)
+{
+	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
+	__twsi_i2c_init(dev->base, dev->speed, dev->slaveadd);
+	return 0;
+}
+
+static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
+	/* We expect either two messages (one with an offset and one with the
+	 * actual data) or one message (just data or offset/data combined) */
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported.", __func__);
+		return -1;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	if (dmsg->flags & I2C_M_RD)
+		return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
+				       omsg->len, dmsg->buf, dmsg->len);
+	else
+		return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
+					omsg->len, dmsg->buf, dmsg->len);
+}
+
+static const struct dm_i2c_ops mvtwsi_i2c_ops = {
+	.xfer		= mvtwsi_i2c_xfer,
+	.probe_chip	= mvtwsi_i2c_probe_chip,
+	.set_bus_speed	= mvtwsi_i2c_set_bus_speed,
+};
+
+static const struct udevice_id mvtwsi_i2c_ids[] = {
+	{ .compatible = "marvell,mv64xxx-i2c", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_mvtwsi) = {
+	.name = "i2c_mvtwsi",
+	.id = UCLASS_I2C,
+	.of_match = mvtwsi_i2c_ids,
+	.probe = mvtwsi_i2c_probe,
+	.ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
+	.ops = &mvtwsi_i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
-- 
cgit v0.10.2


From 24f9c6bbc7d5e5e276dea32a81ade71f0e6b56ae Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:11 +0200
Subject: i2c: mvtwsi: Handle zero-length offsets properly

Zero-length offsets are not properly handled by the driver. When a read
operation with a zero-length offset is started, a START condition is
asserted, and since no offset bytes are transferred, a repeated START is
issued immediately after, which confuses the controller.

To fix this, we send the first START only if any address bytes need to
be sent, and keep track of the expected start status accordingly.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index f694527..8552fba 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -449,16 +449,21 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 {
 	int status = 0;
 	int stop_status;
-
-	/* Begin i2c write to send the address bytes */
-	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
-	/* Send address bytes */
-	while ((status == 0) && alen--)
-		status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK);
+	int expected_start = MVTWSI_STATUS_START;
+
+	if (alen > 0) {
+		/* Begin i2c write to send the address bytes */
+		status = i2c_begin(twsi, expected_start, (chip << 1));
+		/* Send address bytes */
+		while ((status == 0) && alen--)
+			status = twsi_send(twsi, *(addr++),
+					   MVTWSI_STATUS_DATA_W_ACK);
+		/* Send repeated STARTs after the initial START */
+		expected_start = MVTWSI_STATUS_REPEATED_START;
+	}
 	/* Begin i2c read to receive data bytes */
 	if (status == 0)
-		status = i2c_begin(twsi, MVTWSI_STATUS_REPEATED_START,
-				   (chip << 1) | 1);
+		status = i2c_begin(twsi, expected_start, (chip << 1) | 1);
 	/* Receive actual data bytes; set NAK if we if we have nothing more to
 	 * read */
 	while ((status == 0) && length--)
-- 
cgit v0.10.2


From c68c624320e315ec79e78fef1d7baaaa3c64b790 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:12 +0200
Subject: i2c: mvtwsi: Make delay times frequency-dependent

Some devices using the MVTWSI driver have the option to run at speeds
faster than Standard Mode (100kHZ). On the Armada 38x controllers, this
is actually necessary, since due to erratum FE-8471889, a timing
violation concerning repeated starts prevents the controller from
working correctly in Standard Mode. One of the workarounds recommended
in the erratum is to set the bus to Fast Mode (400kHZ) operation and
ensure all connected devices are set to Fast Mode.

In the current version of the driver, however, the delay times are
hard-coded to 10ms, corresponding to Standard Mode operation. To take
full advantage of the faster modes, we would need to either keep the
currently configured I2C speed in a globally accessible variable, or
pass it to the necessary functions as a parameter. For DM, the first
option is not a problem, and we can simply keep the speed in the private
data of the driver. For the legacy interface, however, we would need to
introduce a static variable, which would cause problems with boots from
NOR flashes; see commit d6b7757 "i2c: mvtwsi: Eliminate
twsi_control_flags."

As to not clutter the interface with yet another parameter, we therefore
keep the default 10ms delays for the legacy functions.

In DM mode, we make the delay time dependant on the frequency to allow
taking full advantage of faster modes of operation (tested with up to
1MHZ frequency on Armada MV88F6820).

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 8552fba..f060cd1 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -12,6 +12,7 @@
 #include <i2c.h>
 #include <asm/errno.h>
 #include <asm/io.h>
+#include <linux/compat.h>
 #ifdef CONFIG_DM_I2C
 #include <dm.h>
 #endif
@@ -78,6 +79,8 @@ struct mvtwsi_i2c_dev {
 	u8 slaveadd;
 	/* The configured I2C speed in Hz */
 	uint speed;
+	/* The current length of a clock period (depending on speed) */
+	uint tick;
 };
 #endif /* CONFIG_DM_I2C */
 
@@ -154,7 +157,15 @@ enum mvtwsi_ack_flags {
 	MVTWSI_READ_ACK = 1,
 };
 
+inline uint calc_tick(uint speed)
+{
+	/* One tick = the duration of a period at the specified speed in ns (we
+	 * add 100 ns to be on the safe side) */
+	return (1000000000u / speed) + 100;
+}
+
 #ifndef CONFIG_DM_I2C
+
 /*
  * MVTWSI controller base
  */
@@ -230,7 +241,8 @@ inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
  * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
  * expected, return 0 (ok) or 'wrong status' otherwise.
  */
-static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status)
+static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
+		     uint tick)
 {
 	int control, status;
 	int timeout = 1000;
@@ -246,7 +258,7 @@ static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status)
 					MVTWSI_ERROR_WRONG_STATUS,
 					control, status, expected_status);
 		}
-		udelay(10); /* One clock cycle at 100 kHz */
+		ndelay(tick); /* One clock cycle */
 	} while (timeout--);
 	status = readl(&twsi->status);
 	return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
@@ -257,20 +269,21 @@ static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status)
  * Assert the START condition, either in a single I2C transaction
  * or inside back-to-back ones (repeated starts).
  */
-static int twsi_start(struct mvtwsi_registers *twsi, int expected_status)
+static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
+		      uint tick)
 {
 	/* Assert START */
 	writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
 	       MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* Wait for controller to process START */
-	return twsi_wait(twsi, expected_status);
+	return twsi_wait(twsi, expected_status, tick);
 }
 
 /*
  * Send a byte (i2c address or data).
  */
 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
-		     int expected_status)
+		     int expected_status, uint tick)
 {
 	/* Write byte to data register for sending */
 	writel(byte, &twsi->data);
@@ -278,13 +291,14 @@ static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
 	writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
 	       &twsi->control);
 	/* Wait for controller to receive byte, and check ACK */
-	return twsi_wait(twsi, expected_status);
+	return twsi_wait(twsi, expected_status, tick);
 }
 
 /*
  * Receive a byte.
  */
-static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag)
+static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
+		     uint tick)
 {
 	int expected_status, status, control;
 
@@ -296,7 +310,7 @@ static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag)
 	control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
 	writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 	/* Wait for controller to receive byte, and assert ACK or NAK */
-	status = twsi_wait(twsi, expected_status);
+	status = twsi_wait(twsi, expected_status, tick);
 	/* If we did receive the expected byte, store it */
 	if (status == 0)
 		*byte = readl(&twsi->data);
@@ -307,7 +321,7 @@ static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag)
  * Assert the STOP condition.
  * This is also used to force the bus back to idle (SDA = SCL = 1).
  */
-static int twsi_stop(struct mvtwsi_registers *twsi)
+static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
 {
 	int control, stop_status;
 	int status = 0;
@@ -321,7 +335,7 @@ static int twsi_stop(struct mvtwsi_registers *twsi)
 		stop_status = readl(&twsi->status);
 		if (stop_status == MVTWSI_STATUS_IDLE)
 			break;
-		udelay(10); /* One clock cycle at 100 kHz */
+		ndelay(tick); /* One clock cycle */
 	} while (timeout--);
 	control = readl(&twsi->control);
 	if (stop_status != MVTWSI_STATUS_IDLE)
@@ -376,21 +390,32 @@ static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
 		}
 	}
 	writel(baud, &twsi->baudrate);
-	return 0;
+
+	/* Wait for controller for one tick */
+#ifdef CONFIG_DM_I2C
+	ndelay(calc_tick(highest_speed));
+#else
+	ndelay(10000);
+#endif
+	return highest_speed;
 }
 
 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
-			    int slaveadd)
+			    int slaveadd, uint *actual_speed)
 {
 	/* Reset controller */
 	twsi_reset(twsi);
 	/* Set speed */
-	__twsi_i2c_set_bus_speed(twsi, speed);
+	*actual_speed = __twsi_i2c_set_bus_speed(twsi, speed);
 	/* Set slave address; even though we don't use it */
 	writel(slaveadd, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
 	/* Assert STOP, but don't care for the result */
-	(void) twsi_stop(twsi);
+#ifdef CONFIG_DM_I2C
+	(void) twsi_stop(twsi, calc_tick(*actual_speed));
+#else
+	(void) twsi_stop(twsi, 10000);
+#endif
 }
 
 /*
@@ -398,7 +423,7 @@ static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
-		     u8 addr)
+		     u8 addr, uint tick)
 {
 	int status, expected_addr_status;
 
@@ -409,10 +434,10 @@ static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
 	else /* Writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 	/* Assert START */
-	status = twsi_start(twsi, expected_start_status);
+	status = twsi_start(twsi, expected_start_status, tick);
 	/* Send out the address if the start went well */
 	if (status == 0)
-		status = twsi_send(twsi, addr, expected_addr_status);
+		status = twsi_send(twsi, addr, expected_addr_status, tick);
 	/* Return 0, or the status of the first failure */
 	return status;
 }
@@ -420,18 +445,19 @@ static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
 /*
  * Begin read, nak data byte, end.
  */
-static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip)
+static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
+				 uint tick)
 {
 	u8 dummy_byte;
 	int status;
 
 	/* Begin i2c read */
-	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1);
+	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
 	/* Dummy read was accepted: receive byte, but NAK it. */
 	if (status == 0)
-		status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK);
+		status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
 	/* Stop transaction */
-	twsi_stop(twsi);
+	twsi_stop(twsi, tick);
 	/* Return 0, or the status of the first failure */
 	return status;
 }
@@ -445,7 +471,8 @@ static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip)
  * will be a repeated start without a preceding stop.
  */
 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
-			   u8 *addr, int alen, uchar *data, int length)
+			   u8 *addr, int alen, uchar *data, int length,
+			   uint tick)
 {
 	int status = 0;
 	int stop_status;
@@ -453,25 +480,25 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 
 	if (alen > 0) {
 		/* Begin i2c write to send the address bytes */
-		status = i2c_begin(twsi, expected_start, (chip << 1));
+		status = i2c_begin(twsi, expected_start, (chip << 1), tick);
 		/* Send address bytes */
 		while ((status == 0) && alen--)
 			status = twsi_send(twsi, *(addr++),
-					   MVTWSI_STATUS_DATA_W_ACK);
+					   MVTWSI_STATUS_DATA_W_ACK, tick);
 		/* Send repeated STARTs after the initial START */
 		expected_start = MVTWSI_STATUS_REPEATED_START;
 	}
 	/* Begin i2c read to receive data bytes */
 	if (status == 0)
-		status = i2c_begin(twsi, expected_start, (chip << 1) | 1);
+		status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
 	/* Receive actual data bytes; set NAK if we if we have nothing more to
 	 * read */
 	while ((status == 0) && length--)
 		status = twsi_recv(twsi, data++,
 				   length > 0 ?
-				   MVTWSI_READ_ACK : MVTWSI_READ_NAK);
+				   MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
 	/* Stop transaction */
-	stop_status = twsi_stop(twsi);
+	stop_status = twsi_stop(twsi, tick);
 	/* Return 0, or the status of the first failure */
 	return status != 0 ? status : stop_status;
 }
@@ -480,21 +507,24 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
  * Begin write, send address byte(s), send data bytes, end.
  */
 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
-			    u8 *addr, int alen, uchar *data, int length)
+			    u8 *addr, int alen, uchar *data, int length,
+			    uint tick)
 {
 	int status, stop_status;
 
 	/* Begin i2c write to send first the address bytes, then the
 	 * data bytes */
-	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
 	/* Send address bytes */
 	while ((status == 0) && (alen-- > 0))
-		status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK,
+				   tick);
 	/* Send data bytes */
 	while ((status == 0) && (length-- > 0))
-		status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
+				   tick);
 	/* Stop transaction */
-	stop_status = twsi_stop(twsi);
+	stop_status = twsi_stop(twsi, tick);
 	/* Return 0, or the status of the first failure */
 	return status != 0 ? status : stop_status;
 }
@@ -504,20 +534,21 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
 			  int slaveadd)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	__twsi_i2c_init(twsi, speed, slaveadd);
+	__twsi_i2c_init(twsi, speed, slaveadd, NULL);
 }
 
 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 				   uint requested_speed)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	return __twsi_i2c_set_bus_speed(twsi, requested_speed);
+	__twsi_i2c_set_bus_speed(twsi, requested_speed);
+	return 0;
 }
 
 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
 	struct mvtwsi_registers *twsi = twsi_get_base(adap);
-	return __twsi_i2c_probe_chip(twsi, chip);
+	return __twsi_i2c_probe_chip(twsi, chip, 10000);
 }
 
 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
@@ -531,7 +562,8 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 	addr_bytes[2] = (addr >> 16) & 0xFF;
 	addr_bytes[3] = (addr >> 24) & 0xFF;
 
-	return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length);
+	return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
+			       10000);
 }
 
 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
@@ -545,7 +577,8 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	addr_bytes[2] = (addr >> 16) & 0xFF;
 	addr_bytes[3] = (addr >> 24) & 0xFF;
 
-	return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length);
+	return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
+				10000);
 }
 
 #ifdef CONFIG_I2C_MVTWSI_BASE0
@@ -595,13 +628,17 @@ static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 				 u32 chip_flags)
 {
 	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
-	return __twsi_i2c_probe_chip(dev->base, chip_addr);
+	return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
 }
 
 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
 {
 	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
-	return __twsi_i2c_set_bus_speed(dev->base, speed);
+
+	dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
+	dev->tick = calc_tick(dev->speed);
+
+	return 0;
 }
 
 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
@@ -625,7 +662,11 @@ static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
 static int mvtwsi_i2c_probe(struct udevice *bus)
 {
 	struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
-	__twsi_i2c_init(dev->base, dev->speed, dev->slaveadd);
+	uint actual_speed;
+
+	__twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
+	dev->speed = actual_speed;
+	dev->tick = calc_tick(dev->speed);
 	return 0;
 }
 
@@ -648,10 +689,12 @@ static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 
 	if (dmsg->flags & I2C_M_RD)
 		return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
-				       omsg->len, dmsg->buf, dmsg->len);
+				       omsg->len, dmsg->buf, dmsg->len,
+				       dev->tick);
 	else
 		return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
-					omsg->len, dmsg->buf, dmsg->len);
+					omsg->len, dmsg->buf, dmsg->len,
+					dev->tick);
 }
 
 static const struct dm_i2c_ops mvtwsi_i2c_ops = {
-- 
cgit v0.10.2


From 6e677caf8cf0cc1a2310f2e4e9f27b81c674bc95 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Thu, 21 Jul 2016 11:57:13 +0200
Subject: i2c: mvtwsi: Add documentation

Add full documentation to all driver functions.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index f060cd1..ab7481a 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -157,6 +157,12 @@ enum mvtwsi_ack_flags {
 	MVTWSI_READ_ACK = 1,
 };
 
+/*
+ * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
+ *
+ * @speed:	The speed in Hz to calculate the clock cycle duration for.
+ * @return The duration of a clock cycle in ns.
+ */
 inline uint calc_tick(uint speed)
 {
 	/* One tick = the duration of a period at the specified speed in ns (we
@@ -167,9 +173,11 @@ inline uint calc_tick(uint speed)
 #ifndef CONFIG_DM_I2C
 
 /*
- * MVTWSI controller base
+ * twsi_get_base() - Get controller register base for specified adapter
+ *
+ * @adap:	Adapter to get the register base for.
+ * @return Register base for the specified adapter.
  */
-
 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
 {
 	switch (adap->hwadapnr) {
@@ -238,8 +246,10 @@ inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
 }
 
 /*
- * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
- * expected, return 0 (ok) or 'wrong status' otherwise.
+ * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
+ *
+ * @return Zero if status is as expected, or a non-zero code if either a time
+ *	   out occurred, or the status was not the expected one.
  */
 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
 		     uint tick)
@@ -266,8 +276,17 @@ static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
 }
 
 /*
- * Assert the START condition, either in a single I2C transaction
- * or inside back-to-back ones (repeated starts).
+ * twsi_start() - Assert a START condition on the bus.
+ *
+ * This function is used in both single I2C transactions and inside
+ * back-to-back transactions (repeated starts).
+ *
+ * @twsi:		The MVTWSI register structure to use.
+ * @expected_status:	The I2C bus status expected to be asserted after the
+ *			operation completion.
+ * @tick:		The duration of a clock cycle at the current I2C speed.
+ * @return Zero if status is as expected, or a non-zero code if either a time
+ *	   out occurred or the status was not the expected one.
  */
 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
 		      uint tick)
@@ -280,7 +299,17 @@ static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
 }
 
 /*
- * Send a byte (i2c address or data).
+ * twsi_send() - Send a byte on the I2C bus.
+ *
+ * The byte may be part of an address byte or data.
+ *
+ * @twsi:		The MVTWSI register structure to use.
+ * @byte:		The byte to send.
+ * @expected_status:	The I2C bus status expected to be asserted after the
+ *			operation completion.
+ * @tick:		The duration of a clock cycle at the current I2C speed.
+ * @return Zero if status is as expected, or a non-zero code if either a time
+ *	   out occurred or the status was not the expected one.
  */
 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
 		     int expected_status, uint tick)
@@ -295,7 +324,17 @@ static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
 }
 
 /*
- * Receive a byte.
+ * twsi_recv() - Receive a byte on the I2C bus.
+ *
+ * The static variable mvtwsi_control_flags controls whether we ack or nak.
+ *
+ * @twsi:		The MVTWSI register structure to use.
+ * @byte:		The byte to send.
+ * @ack_flag:		Flag that determines whether the received byte should
+ *			be acknowledged by the controller or not (sent ACK/NAK).
+ * @tick:		The duration of a clock cycle at the current I2C speed.
+ * @return Zero if status is as expected, or a non-zero code if either a time
+ *	   out occurred or the status was not the expected one.
  */
 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
 		     uint tick)
@@ -318,8 +357,15 @@ static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
 }
 
 /*
- * Assert the STOP condition.
- * This is also used to force the bus back to idle (SDA = SCL = 1).
+ * twsi_stop() - Assert a STOP condition on the bus.
+ *
+ * This function is also used to force the bus back to idle state (SDA =
+ * SCL = 1).
+ *
+ * @twsi:	The MVTWSI register structure to use.
+ * @tick:	The duration of a clock cycle at the current I2C speed.
+ * @return Zero if the operation succeeded, or a non-zero code if a time out
+ *	   occurred.
  */
 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
 {
@@ -344,6 +390,13 @@ static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
 	return status;
 }
 
+/*
+ * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
+ *
+ * @n:		Parameter 'n' for the frequency calculation algorithm.
+ * @m:		Parameter 'm' for the frequency calculation algorithm.
+ * @return The I2C frequency corresponding to the passed m and n parameters.
+ */
 static uint twsi_calc_freq(const int n, const int m)
 {
 #ifdef CONFIG_SUNXI
@@ -354,9 +407,12 @@ static uint twsi_calc_freq(const int n, const int m)
 }
 
 /*
- * Reset controller.
- * Controller reset also resets the baud rate and slave address, so
- * they must be re-established afterwards.
+ * twsi_reset() - Reset the I2C controller.
+ *
+ * Resetting the controller also resets the baud rate and slave address, hence
+ * they must be re-established after the reset.
+ *
+ * @twsi:	The MVTWSI register structure to use.
  */
 static void twsi_reset(struct mvtwsi_registers *twsi)
 {
@@ -367,7 +423,15 @@ static void twsi_reset(struct mvtwsi_registers *twsi)
 }
 
 /*
- * Sets baud to the highest possible value not exceeding the requested one.
+ * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
+ *
+ * This function sets baud rate to the highest possible value that does not
+ * exceed the requested rate.
+ *
+ * @twsi:		The MVTWSI register structure to use.
+ * @requested_speed:	The desired frequency the controller should run at
+ *			in Hz.
+ * @return The actual frequency the controller was configured to.
  */
 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
 				     uint requested_speed)
@@ -400,6 +464,18 @@ static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
 	return highest_speed;
 }
 
+/*
+ * __twsi_i2c_init() - Initialize the I2C controller.
+ *
+ * @twsi:		The MVTWSI register structure to use.
+ * @speed:		The initial frequency the controller should run at
+ *			in Hz.
+ * @slaveadd:		The I2C address to be set for the I2C master.
+ * @actual_speed:	A output parameter that receives the actual frequency
+ *			in Hz the controller was set to by the function.
+ * @return Zero if the operation succeeded, or a non-zero code if a time out
+ *	   occurred.
+ */
 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
 			    int slaveadd, uint *actual_speed)
 {
@@ -419,8 +495,21 @@ static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
 }
 
 /*
- * Begin I2C transaction with expected start status, at given address.
- * Expected address status will derive from direction bit (bit 0) in addr.
+ * i2c_begin() - Start a I2C transaction.
+ *
+ * Begin a I2C transaction with a given expected start status and chip address.
+ * A START is asserted, and the address byte is sent to the I2C controller. The
+ * expected address status will be derived from the direction bit (bit 0) of
+ * the address byte.
+ *
+ * @twsi:			The MVTWSI register structure to use.
+ * @expected_start_status:	The I2C status the controller is expected to
+ *				assert after the address byte was sent.
+ * @addr:			The address byte to be sent.
+ * @tick:			The duration of a clock cycle at the current
+ *				I2C speed.
+ * @return Zero if the operation succeeded, or a non-zero code if a time out or
+ *	   unexpected I2C status occurred.
  */
 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
 		     u8 addr, uint tick)
@@ -443,7 +532,16 @@ static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
 }
 
 /*
- * Begin read, nak data byte, end.
+ * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
+ *
+ * This function begins a I2C read transaction, does a dummy read and NAKs; if
+ * the procedure succeeds, the chip is considered to be present.
+ *
+ * @twsi:	The MVTWSI register structure to use.
+ * @chip:	The chip address to probe.
+ * @tick:	The duration of a clock cycle at the current I2C speed.
+ * @return Zero if the operation succeeded, or a non-zero code if a time out or
+ *	   unexpected I2C status occurred.
  */
 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
 				 uint tick)
@@ -463,12 +561,26 @@ static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
 }
 
 /*
- * Begin write, send address byte(s), begin read, receive data bytes, end.
+ * __twsi_i2c_read() - Read data from a I2C chip.
+ *
+ * This function begins a I2C write transaction, and transmits the address
+ * bytes; then begins a I2C read transaction, and receives the data bytes.
  *
  * NOTE: Some devices want a stop right before the second start, while some
  * will choke if it is there. Since deciding this is not yet supported in
  * higher level APIs, we need to make a decision here, and for the moment that
  * will be a repeated start without a preceding stop.
+ *
+ * @twsi:	The MVTWSI register structure to use.
+ * @chip:	The chip address to read from.
+ * @addr:	The address bytes to send.
+ * @alen:	The length of the address bytes in bytes.
+ * @data:	The buffer to receive the data read from the chip (has to have
+ *		a size of at least 'length' bytes).
+ * @length:	The amount of data to be read from the chip in bytes.
+ * @tick:	The duration of a clock cycle at the current I2C speed.
+ * @return Zero if the operation succeeded, or a non-zero code if a time out or
+ *	   unexpected I2C status occurred.
  */
 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 			   u8 *addr, int alen, uchar *data, int length,
@@ -504,7 +616,20 @@ static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 }
 
 /*
- * Begin write, send address byte(s), send data bytes, end.
+ * __twsi_i2c_write() - Send data to a I2C chip.
+ *
+ * This function begins a I2C write transaction, and transmits the address
+ * bytes; then begins a new I2C write transaction, and sends the data bytes.
+ *
+ * @twsi:	The MVTWSI register structure to use.
+ * @chip:	The chip address to read from.
+ * @addr:	The address bytes to send.
+ * @alen:	The length of the address bytes in bytes.
+ * @data:	The buffer containing the data to be sent to the chip.
+ * @length:	The length of data to be sent to the chip in bytes.
+ * @tick:	The duration of a clock cycle at the current I2C speed.
+ * @return Zero if the operation succeeded, or a non-zero code if a time out or
+ *	   unexpected I2C status occurred.
  */
 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
 			    u8 *addr, int alen, uchar *data, int length,
-- 
cgit v0.10.2


From 27059c3e4d99c134d050be62601afe43171173b3 Mon Sep 17 00:00:00 2001
From: "mario.six@gdsys.cc" <mario.six@gdsys.cc>
Date: Mon, 23 May 2016 10:12:11 +0200
Subject: i2c: fsl: Fix driver initialization

Due to a oversight in testing, the initialization of the recently
introduced Freescale I2C DM driver works only for 36 bit mode of e.g.
the MPC85XX SoCs (specifically, if the physical addresses are 64 bit
wide and the DT addresses 32 bit wide).

This patch corrects the initialization so that it will work in a more
general setting.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index b8cc647..407c4a7 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -583,12 +583,11 @@ static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
 {
 	struct fsl_i2c_dev *dev = dev_get_priv(bus);
-	u64 reg;
-	u32 addr, size;
+	fdt_addr_t addr;
+	fdt_size_t size;
 
-	reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg");
-	addr = reg >> 32;
-	size = reg & 0xFFFFFFFF;
+	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset,
+						  "reg", 0, &size);
 
 	dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
 
-- 
cgit v0.10.2


From 9729dc9565c9c1812efbb630e1db4d54f580363c Mon Sep 17 00:00:00 2001
From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Date: Tue, 7 Jun 2016 18:59:34 +0530
Subject: include: usb: Rename USB controller base address mapping

Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8b8a7c1..87507c7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -31,9 +31,9 @@
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3ad46eb..7e39e92 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -52,8 +52,8 @@
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
 
-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 04abec4..67a4311 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -35,13 +35,11 @@
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
-#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS102XA_USB1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
-#define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
 #define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 253eddf..199f366 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -51,22 +51,18 @@ struct fsl_xhci {
 	struct dwc3 *dwc3_reg;
 };
 
-#if defined(CONFIG_LS102XA)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #elif defined(CONFIG_LS2080A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
-#elif defined(CONFIG_LS1012A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 586d32a..882aed4 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -160,7 +160,7 @@
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR	0
 #elif defined(CONFIG_LS102XA)
-#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
 
-- 
cgit v0.10.2


From 7f0a0e4c58e9099016eda6f1f24507c2e6173c8a Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Tue, 14 Jun 2016 13:52:37 -0400
Subject: DM: crypto/fsl: Enable rsa DM driver usage before relocation

Enable rsa signature verification in SPL framework before relocation for
verification of main u-boot.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c
index cf1c4c1..5471504 100644
--- a/drivers/crypto/fsl/fsl_rsa.c
+++ b/drivers/crypto/fsl/fsl_rsa.c
@@ -53,6 +53,7 @@ U_BOOT_DRIVER(fsl_rsa_mod_exp) = {
 	.name	= "fsl_rsa_mod_exp",
 	.id	= UCLASS_MOD_EXP,
 	.ops	= &fsl_mod_exp_ops,
+	.flags  = DM_FLAG_PRE_RELOC,
 };
 
 U_BOOT_DEVICE(fsl_rsa) = {
-- 
cgit v0.10.2


From 028ac8c73355ab1340ed7ce179f08cbbae841034 Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Tue, 14 Jun 2016 13:52:38 -0400
Subject: SECURE_BOOT: Enable chain of trust in SPL framework

Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define macros in SPL framework to enable crypto operations.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 53cd755..3f76c9a 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -17,8 +17,6 @@
 
 #ifdef CONFIG_CHAIN_OF_TRUST
 #define CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_CMD_BLOB
-#define CONFIG_CMD_HASH
 #define CONFIG_FSL_SEC_MON
 #define CONFIG_SHA_HW_ACCEL
 #define CONFIG_SHA_PROG_HW_ACCEL
@@ -28,6 +26,28 @@
 #define CONFIG_FSL_CAAM
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_DM			1
+#define CONFIG_SPL_CRYPTO_SUPPORT
+#define CONFIG_SPL_HASH_SUPPORT
+#define CONFIG_SPL_RSA
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+/*
+ * Define the key hash for U-Boot here if public/private key pair used to
+ * sign U-boot are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_SPL_UBOOT_KEY_HASH \
+ *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * else leave it defined as NULL
+ */
+
+#define CONFIG_SPL_UBOOT_KEY_HASH	NULL
+#endif /* ifdef CONFIG_SPL_BUILD */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_BLOB
+#define CONFIG_CMD_HASH
 #define CONFIG_KEY_REVOCATION
 #ifndef CONFIG_SYS_RAMBOOT
 /* The key used for verification of next level images
@@ -92,5 +112,6 @@
 #endif
 
 #include <config_fsl_chain_trust.h>
+#endif /* #ifndef CONFIG_SPL_BUILD */
 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 #endif
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 290536d..dea231b 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -10,6 +10,10 @@
 #include <fsl_sfp.h>
 #include <dm/root.h>
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
+#include <spl.h>
+#endif
+
 #ifdef CONFIG_ADDR_MAP
 #include <asm/mmu.h>
 #endif
@@ -115,7 +119,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
  * do not use common SPL framework, so need to call this function here.
  */
 #if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK))
-	dm_init_and_scan(false);
+	dm_init_and_scan(true);
 #endif
 	res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH,
 				   &img_addr);
@@ -123,4 +127,32 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
 	if (res == 0)
 		printf("SPL: Validation of U-boot successful\n");
 }
+
+#ifdef CONFIG_SPL_FRAMEWORK
+/* Override weak funtion defined in SPL framework to enable validation
+ * of main u-boot image before jumping to u-boot image.
+ */
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+	uint32_t hdr_addr;
+
+	image_entry_noargs_t image_entry =
+		(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+
+	hdr_addr = (spl_image->entry_point + spl_image->size -
+			CONFIG_U_BOOT_HDR_SIZE);
+	spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point);
+	/*
+	 * In case of failure in validation, spl_validate_uboot would
+	 * not return back in case of Production environment with ITS=1.
+	 * Thus U-Boot will not start.
+	 * In Development environment (ITS=0 and SB_EN=1), the function
+	 * may return back in case of non-fatal failures.
+	 */
+
+	debug("image entry point: 0x%X\n", spl_image->entry_point);
+	image_entry();
+}
+#endif /* ifdef CONFIG_SPL_FRAMEWORK */
 #endif /* ifdef CONFIG_SPL_BUILD */
-- 
cgit v0.10.2


From 69d4b48c84b9c2b762066c5a68406a53e49ea2f3 Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Tue, 14 Jun 2016 13:52:39 -0400
Subject: SECURE_BOOT: Enable SD as a source for bootscript

Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR flash.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 3f76c9a..b35c271 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -78,37 +78,52 @@
 	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
 #else
 #define CONFIG_EXTRA_ENV \
-	"setenv fdt_high 0xcfffffff;"	\
-	"setenv initrd_high 0xcfffffff;"	\
+	"setenv fdt_high 0xffffffff;"	\
+	"setenv initrd_high 0xffffffff;"	\
 	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
 #endif
 
 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
  * Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
+	defined(CONFIG_SD_BOOT)
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif
-/* The address needs to be modified according to NOR and DDR memory map */
+/* The address needs to be modified according to NOR, NAND, SD and
+ * DDR memory map
+ */
 #ifdef CONFIG_LS2080A
-#define CONFIG_BS_HDR_ADDR_FLASH	0x583920000
-#define CONFIG_BS_ADDR_FLASH		0x583900000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x583920000
+#define CONFIG_BS_ADDR_DEVICE		0x583900000
 #define CONFIG_BS_HDR_ADDR_RAM		0xa3920000
 #define CONFIG_BS_ADDR_RAM		0xa3900000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#define CONFIG_BS_SIZE			0x00001000
+#else
+#ifdef CONFIG_SD_BOOT
+/* For SD boot address and size are assigned in terms of sector
+ * offset and no. of sectors respectively.
+ */
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x00000800
+#define CONFIG_BS_ADDR_DEVICE		0x00000840
+#define CONFIG_BS_HDR_SIZE		0x00000010
+#define CONFIG_BS_SIZE			0x00000008
 #else
-#define CONFIG_BS_HDR_ADDR_FLASH	0x600a0000
-#define CONFIG_BS_ADDR_FLASH		0x60060000
-#define CONFIG_BS_HDR_ADDR_RAM		0xa0060000
-#define CONFIG_BS_ADDR_RAM		0xa0060000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x600a0000
+#define CONFIG_BS_ADDR_DEVICE		0x60060000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#define CONFIG_BS_SIZE			0x00001000
+#endif /* #ifdef CONFIG_SD_BOOT */
+#define CONFIG_BS_HDR_ADDR_RAM		0x81000000
+#define CONFIG_BS_ADDR_RAM		0x81020000
 #endif
 
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
-#define CONFIG_BS_HDR_SIZE		0x00002000
 #define CONFIG_BOOTSCRIPT_ADDR		CONFIG_BS_ADDR_RAM
-#define CONFIG_BS_SIZE			0x00001000
 #else
-#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_FLASH
-/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_DEVICE
+/* BOOTSCRIPT_ADDR is not required */
 #endif
 
 #include <config_fsl_chain_trust.h>
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 2e2d565..2e937f0 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -128,10 +128,10 @@
 /* If Boot Script is not on NOR and is required to be copied on RAM */
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 #define CONFIG_BS_HDR_ADDR_RAM		0x00010000
-#define CONFIG_BS_HDR_ADDR_FLASH	0x00800000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x00800000
 #define CONFIG_BS_HDR_SIZE		0x00002000
 #define CONFIG_BS_ADDR_RAM		0x00012000
-#define CONFIG_BS_ADDR_FLASH		0x00802000
+#define CONFIG_BS_ADDR_DEVICE		0x00802000
 #define CONFIG_BS_SIZE			0x00001000
 
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h
index 566fd80..eb45e98 100644
--- a/include/config_fsl_chain_trust.h
+++ b/include/config_fsl_chain_trust.h
@@ -74,23 +74,27 @@
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 #define CONFIG_BS_COPY_ENV \
 	"setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
-	"setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \
+	"setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \
 	"setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
 	"setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
-	"setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
+	"setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \
 	"setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
 
 /* For secure boot flow, default environment used will be used */
 #if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_NAND)
 #define CONFIG_BS_COPY_CMD \
-	"nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
-	"nand read $bs_ram $bs_flash $bs_size ;"
+	"nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
+	"nand read $bs_ram $bs_device $bs_size ;"
 #endif /* CONFIG_RAMBOOT_NAND */
-#else
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BS_COPY_CMD \
+	"mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
+	"mmc read $bs_ram $bs_device $bs_size ;"
+#else /* CONFIG_SD_BOOT */
 #define CONFIG_BS_COPY_CMD \
-	"cp.b $bs_hdr_flash $bs_hdr_ram  $bs_hdr_size ;" \
-	"cp.b $bs_flash $bs_ram  $bs_size ;"
+	"cp.b $bs_hdr_device $bs_hdr_ram  $bs_hdr_size ;" \
+	"cp.b $bs_device $bs_ram  $bs_size ;"
 #endif
 #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
 
-- 
cgit v0.10.2


From e7e720c2cef046f67f23db0a54bd65f8b662531e Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Tue, 14 Jun 2016 13:52:40 -0400
Subject: arm: ls1021atwr: Add SD secure boot target

Add SD secure boot target for ls1021atwr.
Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU. Change the u-boot size defined by a
macro for copying the main U-Boot by SPL to also include the u-boot
Secure Boot header size as header is appended to u-boot image. So header
will also be copied from SD to DDR.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index c69c9cb..77482a9 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -503,6 +503,13 @@ int board_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+	ls102xa_smmu_stream_id_init();
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..c735d6d
--- /dev/null
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
+CONFIG_SPL=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_RSA=y
+CONFIG_DM=y
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 616aebb..c588fdd 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -124,7 +124,18 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xe8
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image.
+ */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		(0x400 + \
+		(CONFIG_U_BOOT_HDR_SIZE / 512)
+#else
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x400
+#endif /* ifdef CONFIG_SECURE_BOOT */
 
 #define CONFIG_SPL_TEXT_BASE		0x10000000
 #define CONFIG_SPL_MAX_SIZE		0x1a000
@@ -137,7 +148,18 @@
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#ifdef CONFIG_U_BOOT_HDR_SIZE
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(0x80000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
 #define CONFIG_SYS_MONITOR_LEN		0x80000
+#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 #endif
 
 #ifdef CONFIG_QSPI_BOOT
-- 
cgit v0.10.2


From 0c14c4d65b1af8216d704644c730d208c371ddc6 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 1 Jul 2016 07:40:39 -0700
Subject: armv8: ls2080aqds: Update MAINTAINERS

Add ls2080aqds_qspi_defconfig to file list.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 0765326..8f78b67 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -6,6 +6,7 @@ F:	board/freescale/ls2080a/ls2080aqds.c
 F:	include/configs/ls2080aqds.h
 F:	configs/ls2080aqds_defconfig
 F:	configs/ls2080aqds_nand_defconfig
+F:	configs/ls2080aqds_qspi_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
-- 
cgit v0.10.2


From dbb9d04fbd4c65243ddff1b1ccd0b50274ad777b Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 1 Jul 2016 07:40:40 -0700
Subject: armv8: ls1043aqds: Update MAINTAINERS

Add ls1043aqds_lpuart_defconfig to file list.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS
index 65a0af1..992c54c 100644
--- a/board/freescale/ls1043aqds/MAINTAINERS
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -9,3 +9,4 @@ F:	configs/ls1043aqds_nand_defconfig
 F:	configs/ls1043aqds_sdcard_ifc_defconfig
 F:	configs/ls1043aqds_sdcard_qspi_defconfig
 F:	configs/ls1043aqds_qspi_defconfig
+F:	configs/ls1043aqds_lpuart_defconfig
-- 
cgit v0.10.2


From 79119a4d1930468c47da5d000c41751a92bcaa62 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Tue, 5 Jul 2016 16:01:52 +0800
Subject: armv8: fsl-layerscape: Add A72 core detection

Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 7a2ec6b..eaff166 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -309,7 +309,8 @@ int print_cpuinfo(void)
 		printf("CPU%d(%s):%-4s MHz  ", core,
 		       type == TY_ITYP_VER_A7 ? "A7 " :
 		       (type == TY_ITYP_VER_A53 ? "A53" :
-			(type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+		       (type == TY_ITYP_VER_A57 ? "A57" :
+		       (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 		       strmhz(buf, sysinfo.freq_processor[core]));
 	}
 	printf("\n       Bus:      %-4s MHz  ",
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 87507c7..97136a0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -94,6 +94,7 @@
 #define TY_ITYP_VER_A7          0x1
 #define TY_ITYP_VER_A53         0x2
 #define TY_ITYP_VER_A57         0x3
+#define TY_ITYP_VER_A72		0x4
 
 #define TP_CLUSTER_EOC		0xc0000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7e39e92..93e26c1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -156,6 +156,7 @@
 #define TY_ITYP_VER_A7		0x1
 #define TY_ITYP_VER_A53		0x2
 #define TY_ITYP_VER_A57		0x3
+#define TY_ITYP_VER_A72		0x4
 
 #define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
 #define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
-- 
cgit v0.10.2


From 86336e60c5bb23e4ec52584827ce743845bc519f Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Tue, 5 Jul 2016 16:01:53 +0800
Subject: armv8: fsl-layerscape: Consolidate the LSCH2 common defines

Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 44fe0c0..7116f9d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -149,43 +149,43 @@
 #define CONFIG_ARM_ERRATA_833471
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
-#elif defined(CONFIG_LS1043A)
-#define CONFIG_MAX_CPUS				4
+#elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_CACHELINE_SIZE		64
-#define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_NUM_FMAN			1
-#define CONFIG_SYS_NUM_FM1_DTSEC		7
-#define CONFIG_SYS_NUM_FM1_10GEC		1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
 #define CONFIG_NUM_DDR_CONTROLLERS		1
-#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
-#define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
 
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_PEX_LUT_BE
+#define CONFIG_SYS_FSL_SEC_BE
+
+#define CONFIG_SYS_FSL_SRDS_1
+/* SoC related */
+#ifdef CONFIG_LS1043A
+#define CONFIG_MAX_CPUS				4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN			1
+#define CONFIG_SYS_NUM_FM1_DTSEC		7
+#define CONFIG_SYS_NUM_FM1_10GEC		1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE		0x6000UL
 #define MAX_QE_RISC		1
 #define QE_NUM_OF_SNUM		28
 
-#define SRDS_MAX_LANES		4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
-
+#define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION
@@ -205,32 +205,13 @@
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_LS1012A)
 #define CONFIG_MAX_CPUS                         1
-#define CONFIG_SYS_CACHELINE_SIZE		64
-#define CONFIG_NUM_DDR_CONTROLLERS		1
-#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
-#define CONFIG_SYS_FSL_SEC_COMPAT		5
 #undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
-
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
-
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
-#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
-#define CONFIG_SYS_FSL_PEX_LUT_BE
-
-#define SRDS_MAX_LANES		4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif
+#endif
 
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
-- 
cgit v0.10.2


From da4d620c90eb6dd9466a89837ab8667048d856e3 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Tue, 5 Jul 2016 16:01:54 +0800
Subject: armv8: fsl_lsch2: Add SerDes 2 support

New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index fe3444a..f73092a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
 
 int is_serdes_configured(enum srds_prtcl device)
 {
@@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	ret |= serdes1_prtcl_map[device];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	ret |= serdes2_prtcl_map[device];
+#endif
 
 	return !!ret;
 }
@@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 		cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 		break;
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	case FSL_SRDS_2:
+		cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+		break;
+#endif
 	default:
 		printf("invalid SerDes%d\n", sd);
 		break;
@@ -114,4 +126,11 @@ void fsl_serdes_init(void)
 		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
 		    serdes1_prtcl_map);
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	serdes_init(FSL_SRDS_2,
+		    CONFIG_SYS_FSL_SERDES_ADDR,
+		    FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
+		    FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
+		    serdes2_prtcl_map);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 487cba8..1f33404 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -140,6 +140,7 @@ enum srds_prtcl {
 
 enum srds {
 	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
 };
 
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 97136a0..95a4293 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -228,6 +228,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK	0xffff0000
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT	16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK	0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT	0
 #define RCW_SB_EN_REG_INDEX	7
 #define RCW_SB_EN_MASK		0x00200000
 
-- 
cgit v0.10.2


From b528b9377df0e738c6904a639a1e78810936f825 Mon Sep 17 00:00:00 2001
From: Mingkai Hu <mingkai.hu@nxp.com>
Date: Tue, 5 Jul 2016 16:01:55 +0800
Subject: armv8: fsl_lsch2: Add LS1046A SoC support

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index bcf6b48..8c1317f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -33,3 +33,7 @@ endif
 ifneq ($(CONFIG_LS1012A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1046A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index 8eee016..f7b949a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -3,6 +3,7 @@ SoC overview
 	1. LS1043A
 	2. LS2080A
 	3. LS1012A
+	4. LS1046A
 
 LS1043A
 ---------
@@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features:
     - Two WatchDog timers
     - ARM generic timer
  - QorIQ platform's trust architecture 2.1
+
+LS1046A
+--------
+The LS1046A integrated multicore processor combines four ARM Cortex-A72
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1046A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A72 CPUs
+ - 2 MB unified L2 Cache
+ - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Two Configurable x4 SerDes
+   - Two PLLs per four-lane SerDes
+   - Support for 10G operation
+ - Ethernet interfaces by FMan
+   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+   - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
+   - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
+   - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
+   - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
+ - High-speed peripheral interfaces
+   - Three PCIe 3.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC) supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index d0dc58d..8922197 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
 	case 3:
 		sys_info->freq_fman[0] = freq_c_pll[0] / 3;
 		break;
+	case 4:
+		sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+		break;
+	case 5:
+		sys_info->freq_fman[0] = sys_info->freq_systembus;
+		break;
 	case 6:
 		sys_info->freq_fman[0] = freq_c_pll[1] / 2;
 		break;
@@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
-	rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
-	sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+	switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+	case 1:
+		sys_info->freq_sdhc = freq_c_pll[1];
+		break;
+	case 2:
+		sys_info->freq_sdhc = freq_c_pll[1] / 2;
+		break;
+	case 3:
+		sys_info->freq_sdhc = freq_c_pll[1] / 3;
+		break;
+	case 6:
+		sys_info->freq_sdhc = freq_c_pll[0] / 2;
+		break;
+	default:
+		printf("Error: Unknown ESDHC clock select!\n");
+		break;
+	}
 #else
 	sys_info->freq_sdhc = sys_info->freq_systembus;
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
new file mode 100644
index 0000000..1da6b71
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+		  SGMII_FM1_DTSEC6} },
+	{0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
+		  SGMII_FM1_DTSEC6} },
+	{0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+		  SGMII_FM1_DTSEC6} },
+	{0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+		  SGMII_FM1_DTSEC6} },
+	{0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
+		  SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
+	{0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
+	{0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
+	{0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
+		  SGMII_FM1_DTSEC6} },
+	{0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
+		  SGMII_FM1_DTSEC6} },
+	{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
+		  SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{}
+};
+
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
+	{0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
+	{0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
+	{0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
+	{0x0506, {NONE, PCIE2, NONE, PCIE3} },
+	{0x0559, {NONE, PCIE2, PCIE3, SATA1} },
+	{0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
+	{0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 7116f9d..b0ad4b4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -209,6 +209,33 @@
 
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
+#elif defined(CONFIG_LS1046A)
+#define CONFIG_MAX_CPUS				4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN			1
+#define CONFIG_SYS_NUM_FM1_DTSEC		8
+#define CONFIG_SYS_NUM_FM1_10GEC		2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE		0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE		0x01410000
+#define GICC_BASE		0x01420000
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 5fd5e87..e2d96a1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -13,6 +13,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
 	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
 };
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 1f33404..e1b3f44 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -151,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 int is_serdes_prtcl_valid(int serdes, u32 prtcl);
 
-#ifdef	CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
 const char *serdes_clock_to_string(u32 clock);
 int get_serdes_protocol(void);
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 39e8c7a..8d4a7ad 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -44,6 +44,8 @@ struct cpu_type {
 #define SVR_LS1012A		0x870400
 #define SVR_LS1043A		0x879200
 #define SVR_LS1023A		0x879208
+#define SVR_LS1046A		0x870700
+#define SVR_LS1026A		0x870708
 #define SVR_LS2045A		0x870120
 #define SVR_LS2080A		0x870110
 #define SVR_LS2085A		0x870100
-- 
cgit v0.10.2


From 9d3b8bd166e6c23ab83d0dcd49d81c6f0bf39e17 Mon Sep 17 00:00:00 2001
From: Mingkai Hu <mingkai.hu@nxp.com>
Date: Tue, 5 Jul 2016 16:01:56 +0800
Subject: drivers: net/fm: Add Fman support for LS1046A

The Fman module on LS1046A is similiar with that on LS1043A but
LS1046A has one more XFI (10GbE) interface.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344fbe2 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
 obj-$(CONFIG_LS1043A)	+= ls1043.o
+obj-$(CONFIG_LS1046A)	+= ls1046.o
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
new file mode 100644
index 0000000..bf55554
--- /dev/null
+++ b/drivers/net/fm/ls1046.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+#define FSL_CHASSIS2_RCWSR13_EC1		0xe0000000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO		0x20000000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM		0xa0000000
+#define FSL_CHASSIS2_RCWSR13_EC2		0x1c000000 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO		0x04000000
+#define FSL_CHASSIS2_RCWSR13_EC2_1588		0x08000000
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM		0x14000000
+
+u32 port_to_devdisr[] = {
+	[FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+	[FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+	[FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+	[FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+	[FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+	[FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+	[FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+	[FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+	[FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+	[FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+	[FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+	[FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 devdisr2 = in_be32(&gur->devdisr2);
+
+	return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+	if (is_device_disabled(port))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if (port == FM1_DTSEC3)
+		if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+				FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+
+	if (port == FM1_DTSEC4)
+		if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+				FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+
+	/* handle SGMII, only MAC 2/5/6/9/10 available */
+	switch (port) {
+	case FM1_DTSEC2:
+	case FM1_DTSEC5:
+	case FM1_DTSEC6:
+	case FM1_DTSEC9:
+	case FM1_DTSEC10:
+		if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
+			return PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		break;
+	}
+
+	/* handle 2.5G SGMII, only MAC 5/9/10 available */
+	switch (port) {
+	case FM1_DTSEC5:
+	case FM1_DTSEC9:
+	case FM1_DTSEC10:
+		if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
+					 port - FM1_DTSEC5))
+			return PHY_INTERFACE_MODE_SGMII_2500;
+		break;
+	default:
+		break;
+	}
+
+	/* handle QSGMII, only MAC 1/5/6/10 available */
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC5:
+	case FM1_DTSEC6:
+	case FM1_DTSEC10:
+		if (is_serdes_configured(QSGMII_FM1_A))
+			return PHY_INTERFACE_MODE_QSGMII;
+		break;
+	default:
+		break;
+	}
+
+	return PHY_INTERFACE_MODE_NONE;
+}
-- 
cgit v0.10.2


From 116339d460f79911d1b87fa65753d966aaf8b7b9 Mon Sep 17 00:00:00 2001
From: Hongbo Zhang <hongbo.zhang@nxp.com>
Date: Thu, 21 Jul 2016 18:09:36 +0800
Subject: ARMv7: PSCI: add PSCI v1.0 functions skeleton

This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 350b75c..f80f6e2 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,20 +46,62 @@ ENTRY(default_psci_vector)
 ENDPROC(default_psci_vector)
 .weak default_psci_vector
 
+ENTRY(psci_version)
 ENTRY(psci_cpu_suspend)
 ENTRY(psci_cpu_off)
 ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
 ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
 	mov	r0, #ARM_PSCI_RET_NI	@ Return -1 (Not Implemented)
 	mov	pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
 ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
 ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
 .weak psci_cpu_suspend
 .weak psci_cpu_off
 .weak psci_cpu_on
+.weak psci_affinity_info
 .weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
 
 _psci_table:
 	.word	ARM_PSCI_FN_CPU_SUSPEND
@@ -70,6 +112,42 @@ _psci_table:
 	.word	psci_cpu_on
 	.word	ARM_PSCI_FN_MIGRATE
 	.word	psci_migrate
+	.word	ARM_PSCI_0_2_FN_PSCI_VERSION
+	.word	psci_version
+	.word	ARM_PSCI_0_2_FN_CPU_SUSPEND
+	.word	psci_cpu_suspend
+	.word	ARM_PSCI_0_2_FN_CPU_OFF
+	.word	psci_cpu_off
+	.word	ARM_PSCI_0_2_FN_CPU_ON
+	.word	psci_cpu_on
+	.word	ARM_PSCI_0_2_FN_AFFINITY_INFO
+	.word	psci_affinity_info
+	.word	ARM_PSCI_0_2_FN_MIGRATE
+	.word	psci_migrate
+	.word	ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
+	.word	psci_migrate_info_type
+	.word	ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
+	.word	psci_migrate_info_up_cpu
+	.word	ARM_PSCI_0_2_FN_SYSTEM_OFF
+	.word	psci_system_off
+	.word	ARM_PSCI_0_2_FN_SYSTEM_RESET
+	.word	psci_system_reset
+	.word	ARM_PSCI_1_0_FN_PSCI_FEATURES
+	.word	psci_features
+	.word	ARM_PSCI_1_0_FN_CPU_FREEZE
+	.word	psci_cpu_freeze
+	.word	ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+	.word	psci_cpu_default_suspend
+	.word	ARM_PSCI_1_0_FN_NODE_HW_STATE
+	.word	psci_node_hw_state
+	.word	ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+	.word	psci_system_suspend
+	.word	ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+	.word	psci_set_suspend_mode
+	.word	ARM_PSCI_1_0_FN_STAT_RESIDENCY
+	.word	psi_stat_residency
+	.word	ARM_PSCI_1_0_FN_STAT_COUNT
+	.word	psci_stat_count
 	.word	0
 	.word	0
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index e76ecb2..25ea44d 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -31,6 +31,12 @@
 #define ARM_PSCI_RET_NI			(-1)
 #define ARM_PSCI_RET_INVAL		(-2)
 #define ARM_PSCI_RET_DENIED		(-3)
+#define ARM_PSCI_RET_ALREADY_ON		(-4)
+#define ARM_PSCI_RET_ON_PENDING		(-5)
+#define ARM_PSCI_RET_INTERNAL_FAILURE	(-6)
+#define ARM_PSCI_RET_NOT_PRESENT	(-7)
+#define ARM_PSCI_RET_DISABLED		(-8)
+#define ARM_PSCI_RET_INVALID_ADDRESS	(-9)
 
 /* PSCI 0.2 interface */
 #define ARM_PSCI_0_2_FN_BASE			0x84000000
@@ -47,6 +53,16 @@
 #define ARM_PSCI_0_2_FN_SYSTEM_OFF		ARM_PSCI_0_2_FN(8)
 #define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
 
+/* PSCI 1.0 interface */
+#define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
+#define ARM_PSCI_1_0_FN_CPU_FREEZE		ARM_PSCI_0_2_FN(11)
+#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND	ARM_PSCI_0_2_FN(12)
+#define ARM_PSCI_1_0_FN_NODE_HW_STATE		ARM_PSCI_0_2_FN(13)
+#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND		ARM_PSCI_0_2_FN(14)
+#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE	ARM_PSCI_0_2_FN(15)
+#define ARM_PSCI_1_0_FN_STAT_RESIDENCY		ARM_PSCI_0_2_FN(16)
+#define ARM_PSCI_1_0_FN_STAT_COUNT		ARM_PSCI_0_2_FN(17)
+
 /* 1KB stack per core */
 #define ARM_PSCI_STACK_SHIFT	10
 #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
-- 
cgit v0.10.2


From 7e742c276dea455d9439caa3f6bc3f4e9a1b5796 Mon Sep 17 00:00:00 2001
From: Hongbo Zhang <hongbo.zhang@nxp.com>
Date: Thu, 21 Jul 2016 18:09:37 +0800
Subject: ARMv7: PSCI: ls102xa: check target CPU ID before further operations

The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index f9b26b4..cba9c1e 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,36 @@
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
+@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
+@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
+@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
+LENTRY(psci_check_target_cpu_id)
+	@ Get the real CPU number
+	and	r4, r1, #0xff
+	mov	r0, #ARM_PSCI_RET_INVAL
+
+	@ Bit[31:24], bits must be zero.
+	tst	r1, #0xff000000
+	bxne	lr
+
+	@ Affinity level 2 - Cluster: only one cluster in LS1021xa.
+	tst	r1, #0xff0000
+	bxne	lr
+
+	@ Affinity level 1 - Processors: should be in 0xf00 format.
+	lsr	r1, r1, #8
+	teq	r1, #0xf
+	bxne	lr
+
+	@ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
+	cmp	r4, #2
+	bxge	lr
+
+	mov	r0, #ARM_PSCI_RET_SUCCESS
+	bx	lr
+ENDPROC(psci_check_target_cpu_id)
+
 	@ r1 = target CPU
 	@ r2 = target PC
 .globl	psci_cpu_on
@@ -33,7 +63,9 @@ psci_cpu_on:
 
 	@ Clear and Get the correct CPU number
 	@ r1 = 0xf01
-	and	r4, r1, #0xff
+	bl	psci_check_target_cpu_id
+	cmp	r0, #ARM_PSCI_RET_INVAL
+	beq	out_psci_cpu_on
 
 	mov	r0, r4
 	mov	r1, r2
@@ -101,6 +133,7 @@ holdoff_release:
 	@ Return
 	mov	r0, #ARM_PSCI_RET_SUCCESS
 
+out_psci_cpu_on:
 	pop	{r4, r5, r6, lr}
 	bx	lr
 
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 25ea44d..8aefaa7 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -67,6 +67,11 @@
 #define ARM_PSCI_STACK_SHIFT	10
 #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
 
+/* PSCI affinity level state returned by AFFINITY_INFO */
+#define PSCI_AFFINITY_LEVEL_ON		0
+#define PSCI_AFFINITY_LEVEL_OFF		1
+#define PSCI_AFFINITY_LEVEL_ON_PENDING	2
+
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
 
-- 
cgit v0.10.2


From aeb901f2a6c19e399354345ad1acd67420401a10 Mon Sep 17 00:00:00 2001
From: Hongbo Zhang <hongbo.zhang@nxp.com>
Date: Thu, 21 Jul 2016 18:09:38 +0800
Subject: ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention

This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
    psci_version,
    psci_features,
    psci_cpu_suspend,
    psci_affinity_info,
    psci_system_reset,
    psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index cba9c1e..8f38680 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
 #include <asm/arch-armv7/generictimer.h>
 #include <asm/psci.h>
 
+#define RCPM_TWAITSR		0x04C
+
 #define SCFG_CORE0_SFT_RST      0x130
 #define SCFG_CORESRENCR         0x204
 
-#define DCFG_CCSR_BRR           0x0E4
-#define DCFG_CCSR_SCRATCHRW1    0x200
+#define DCFG_CCSR_RSTCR			0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ	0x2
+#define DCFG_CCSR_BRR			0x0E4
+#define DCFG_CCSR_SCRATCHRW1		0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK	0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK		0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
 	.arch_extension sec
 
+	.align	5
+
 #define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
+.globl	psci_version
+psci_version:
+	movw	r0, #0
+	movt	r0, #1
+
+	bx	lr
+
+_ls102x_psci_supported_table:
+	.word	ARM_PSCI_0_2_FN_PSCI_VERSION
+	.word	PSCI_FN_PSCI_VERSION_FEATURE_MASK
+	.word	ARM_PSCI_0_2_FN_CPU_SUSPEND
+	.word	PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+	.word	ARM_PSCI_0_2_FN_CPU_OFF
+	.word	PSCI_FN_CPU_OFF_FEATURE_MASK
+	.word	ARM_PSCI_0_2_FN_CPU_ON
+	.word	PSCI_FN_CPU_ON_FEATURE_MASK
+	.word	ARM_PSCI_0_2_FN_AFFINITY_INFO
+	.word	PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+	.word	ARM_PSCI_0_2_FN_SYSTEM_OFF
+	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+	.word	ARM_PSCI_0_2_FN_SYSTEM_RESET
+	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+	.word	0
+	.word	ARM_PSCI_RET_NI
+
+.globl	psci_features
+psci_features:
+	adr	r2, _ls102x_psci_supported_table
+1:	ldr	r3, [r2]
+	cmp	r3, #0
+	beq	out_psci_features
+	cmp	r1, r3
+	addne	r2, r2, #8
+	bne	1b
+
+out_psci_features:
+	ldr	r0, [r2, #4]
+	bx	lr
+
 @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
@@ -144,4 +197,50 @@ psci_cpu_off:
 1:	wfi
 	b	1b
 
+.globl	psci_affinity_info
+psci_affinity_info:
+	push	{lr}
+
+	mov	r0, #ARM_PSCI_RET_INVAL
+
+	@ Verify Affinity level
+	cmp	r2, #0
+	bne	out_affinity_info
+
+	bl	psci_check_target_cpu_id
+	cmp	r0, #ARM_PSCI_RET_INVAL
+	beq	out_affinity_info
+	mov	r1, r4
+
+	@ Get RCPM base address
+	movw	r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
+	movt	r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+	mov	r0, #PSCI_AFFINITY_LEVEL_ON
+
+	@ Detect target CPU state
+	ldr	r2, [r4, #RCPM_TWAITSR]
+	rev	r2, r2
+	lsr	r2, r2, r1
+	ands	r2, r2, #1
+	beq	out_affinity_info
+
+	mov	r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+	pop	{pc}
+
+.globl	psci_system_reset
+psci_system_reset:
+	@ Get DCFG base address
+	movw	r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
+	movt	r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+	mov	r2, #DCFG_CCSR_RSTCR_RESET_REQ
+	rev	r2, r2
+	str	r2, [r1, #DCFG_CCSR_RSTCR]
+
+1:	wfi
+	b	1b
+
 	.popsection
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 67a4311..e0b1185 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -32,6 +32,7 @@
 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index ab02344..f0390c1 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -8,3 +8,4 @@ obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
 obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S
new file mode 100644
index 0000000..598168c
--- /dev/null
+++ b/board/freescale/ls1021aqds/psci.S
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+	@ Get QIXIS base address
+	movw	r1, #(QIXIS_BASE & 0xffff)
+	movt	r1, #(QIXIS_BASE >> 16)
+
+	ldrb	r2, [r1, #QIXIS_PWR_CTL]
+	orr	r2, r2, #QIXIS_PWR_CTL_POWEROFF
+	strb	r2, [r1, #QIXIS_PWR_CTL]
+
+1:	wfi
+	b	1b
+
+	.popsection
diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
index 01296c0..5238b15 100644
--- a/board/freescale/ls1021atwr/Makefile
+++ b/board/freescale/ls1021atwr/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += ls1021atwr.o
 obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S
new file mode 100644
index 0000000..bec7356
--- /dev/null
+++ b/board/freescale/ls1021atwr/psci.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+1:	wfi
+	b	1b
+
+	.popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index eb444eb..ba3331f 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -10,6 +10,7 @@
 #define CONFIG_LS102XA
 
 #define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
 #define CONFIG_SYS_FSL_CLK
@@ -280,6 +281,8 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_PWR_CTL			0x21
+#define QIXIS_PWR_CTL_POWEROFF		0x80
 #define QIXIS_RST_CTL_RESET		0x44
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index c588fdd..5b6e0a5 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -10,6 +10,7 @@
 #define CONFIG_LS102XA
 
 #define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
 #define CONFIG_SYS_FSL_CLK
-- 
cgit v0.10.2


From 3288628a8d23681c865e91e65a341d48eb5fed73 Mon Sep 17 00:00:00 2001
From: Hongbo Zhang <hongbo.zhang@nxp.com>
Date: Thu, 21 Jul 2016 18:09:39 +0800
Subject: ARMv7: PSCI: ls102xa: move secure text section into OCRAM

LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index e0b1185..d408fe4 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE		64
 
 #define OCRAM_BASE_ADDR				0x10000000
-#define OCRAM_SIZE				0x00020000
+#define OCRAM_SIZE				0x00010000
 #define OCRAM_BASE_S_ADDR			0x10010000
 #define OCRAM_S_SIZE				0x00010000
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index ba3331f..47180f9 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -13,6 +13,8 @@
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 5b6e0a5..2f19950 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -13,6 +13,8 @@
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_DISPLAY_CPUINFO
-- 
cgit v0.10.2


From ed7a3943d580f4cf72e5ef8a20c43fa93e889d14 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 22 Jul 2016 10:52:23 -0700
Subject: armv8: fsl-layerscape: mmu: Fix enabling MMU

MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index eaff166..e12b773 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -145,11 +145,14 @@ static inline void final_mmu_setup(void)
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 	/*
-	 * MMU is already enabled, just need to invalidate TLB to load the
+	 * EL3 MMU is already enabled, just need to invalidate TLB to load the
 	 * new table. The new table is compatible with the current table, if
 	 * MMU somehow walks through the new table before invalidation TLB,
 	 * it still works. So we don't need to turn off MMU here.
+	 * When EL2 MMU table is created by calling this function, MMU needs
+	 * to be enabled.
 	 */
+	set_sctlr(get_sctlr() | CR_M);
 }
 
 u64 get_page_table_size(void)
-- 
cgit v0.10.2


From 716d6677cbe96fa21438da6e6d2580a7093c99d9 Mon Sep 17 00:00:00 2001
From: Wenbin Song <wenbin.song@nxp.com>
Date: Thu, 21 Jul 2016 18:31:23 +0800
Subject: ARMv8/ls1046a: Cleanup the environment variables

Cleanup the variables: "kernel_addr","ramdisk_addr",
"ramdisk_size","console".

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index b0d4a8d..a651130 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -245,15 +245,12 @@
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"loadaddr=0x80100000\0"			\
-	"kernel_addr=0x100000\0"		\
-	"ramdisk_addr=0x800000\0"		\
-	"ramdisk_size=0x2000000\0"		\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x61100000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
-	"console=ttyAMA0,38400n8\0"
+	"console=ttyS0,115200\0"
 
 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
 					"earlycon=uart8250,mmio,0x21c0500"
-- 
cgit v0.10.2


From dbe18f16d852216a45f632f0d3cf41f12b55d1ec Mon Sep 17 00:00:00 2001
From: Wenbin Song <wenbin.song@nxp.com>
Date: Thu, 21 Jul 2016 18:55:16 +0800
Subject: armv8/ls1043a: Add MTD partition scheme

Add and share the the MTD partition scheme with kernel by default
bootargs. And add the "mtdparts" env.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index a651130..0ad5261 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -241,6 +241,21 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
+			"5m(kernel),1m(dtb),9m(file_system)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
+			"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
+			"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
+			"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
+			"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
+			"40m(nor_bank4_fit);7e800000.flash:" \
+			"1m(nand_uboot),1m(nand_uboot_env)," \
+			"20m(nand_fit);spi0.0:1m(uboot)," \
+			"5m(kernel),1m(dtb),9m(file_system)"
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
@@ -250,10 +265,13 @@
 	"kernel_start=0x61100000\0"		\
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
-	"console=ttyS0,115200\0"
+	"console=ttyS0,115200\0"                \
+	"mtdparts=" MTDPARTS_DEFAULT "\0"
 
 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
-					"earlycon=uart8250,mmio,0x21c0500"
+					"earlycon=uart8250,mmio,0x21c0500 "    \
+					MTDPARTS_DEFAULT
+
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
 					"e0000 f00000 && bootm $kernel_load"
-- 
cgit v0.10.2


From 8401c7103d73b4010df95bf8bc79a60f378f1e50 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Thu, 21 Jul 2016 12:39:27 +0800
Subject: armv8: ls1043aqds: add IFC fixup in case QSPI is enabled

QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index b7e9c21..941dfbc 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -327,6 +327,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
+	u8 reg;
 
 	/* fixup DT for the two DDR banks */
 	base[0] = gd->bd->bi_dram[0].start;
@@ -341,6 +342,15 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_fman_ethernet(blob);
 	fdt_fixup_board_enet(blob);
 #endif
+
+	reg = QIXIS_READ(brdcfg[0]);
+	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	/* Disable IFC if QSPI is enabled */
+	if (reg == 0xF)
+		do_fixup_by_compat(blob, "fsl,ifc",
+				   "status", "disabled", 8 + 1, 1);
+
 	return 0;
 }
 #endif
-- 
cgit v0.10.2


From 2a5adc5b3c1f532dc9ec6638e6696316c078b619 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Tue, 26 Jul 2016 17:47:16 +0200
Subject: sunxi: Add defconfig and dts file for the Orange Pi PC Plus SBC

There is a new Orange Pi PC *Plus* version available now,
this is an extended version of the regular Orange Pi PC
with sdio wifi and an eMMC.

The upstream kernel devs have decided that they want a separate
dts for the PC Plus rather then sharing a single dts between the
regular PC and the PC Plus. So add a new orangepi_pc_plus_defconfig
to match.

The added dts file matches the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ca8712a..1c3b705 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -246,6 +246,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-lite.dtb \
 	sun8i-h3-orangepi-one.dtb \
 	sun8i-h3-orangepi-pc.dtb \
+	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
new file mode 100644
index 0000000..9a8cdd4
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* The Orange Pi PC Plus is an extended version of the regular PC */
+#include "sun8i-h3-orangepi-pc.dts"
+
+/ {
+	model = "Xunlong Orange Pi PC / PC Plus";
+
+	aliases {
+		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+		ethernet1 = &rtl8189ftv;
+	};
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	/*
+	 * Explicitly define the sdio device, so that we can add an ethernet
+	 * alias for it (which e.g. makes u-boot set a mac-address).
+	 */
+	rtl8189ftv: sdio_wifi@1 {
+		reg = <1>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+	/* eMMC is missing pull-ups */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 0dc84f6..de719cd 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -59,6 +59,7 @@ F:	configs/orangepi_2_defconfig
 F:	configs/orangepi_lite_defconfig
 F:	configs/orangepi_one_defconfig
 F:	configs/orangepi_pc_defconfig
+F:	configs/orangepi_pc_plus_defconfig
 F:	configs/orangepi_plus_defconfig
 F:	configs/polaroid_mid2407pxe03_defconfig
 F:	configs/polaroid_mid2809pxe04_defconfig
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 43ec927..2281aed 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -5,7 +5,6 @@ CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC0_CD_PIN="PF6"
-CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
new file mode 100644
index 0000000..c78aec3
--- /dev/null
+++ b/configs/orangepi_pc_plus_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y
-- 
cgit v0.10.2


From 6d7b22a5d83ca5ea507d9a644c368771463aa070 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 22 Jul 2016 18:16:08 +0800
Subject: sunxi: Add EMAC ethernet0 alias for H3 dtsi

The sunxi ethernet address generation code looks for ethernet[0-3]
aliases to find ethernet controllers to generate MAC addresses for.

Without a valid address, the driver fails to register.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index 72c0920..84e52b9 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -48,6 +48,10 @@
 / {
 	interrupt-parent = <&gic>;
 
+	aliases {
+		ethernet0 = <&emac>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-- 
cgit v0.10.2


From 687284483c15b569da25f4727b3449e1e1d0dc17 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 22 Jul 2016 18:16:09 +0800
Subject: net: sun8i_emac: Do not configure AHB2 clock

The sun8i_emac driver erroneously configures the AHB2 clock when it
assumes it is configuring the AXI gates, which is not even documented
or ever appeared in either the WiP kernel driver or Allwinner's original
driver.

As a result, AHB2 clock mux is set to an invalid setting, making the
EPHY unusable.

Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 4bed50d..508fbfe 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -599,9 +599,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 	/* Set clock gating for emac */
 	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
 
-	/* Set EMAC clock */
-	setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
-
 	/* De-assert EMAC */
 	setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
 }
-- 
cgit v0.10.2


From a85ba87dbe24816f2119e7475e255cc08b30934b Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 22 Jul 2016 18:16:10 +0800
Subject: net: sun8i_emac: Drop redundant and incorrect setting of syscon
 register

In sun8i_emac_board_setup, the driver partially configures the syscon
register for H3 EPHY. However, the settings are incomplete, and
completely unusable. The correct settings are later set in
sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists.

It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not
have a 25 MHz clock the EPHY can use.

This patch removes the setting of the syscon register in board_setup,
and also moves set_syscon above mdio_init. While mdio_init does not
access the PHY, it is better to have the PHY parameters setup before
the MDIO bus is registered.

Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 508fbfe..7c088c3 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -22,10 +22,6 @@
 #include <miiphy.h>
 #include <net.h>
 
-#define SCTL_EMAC_TX_CLK_SRC_MII	BIT(0)
-#define SCTL_EMAC_EPIT_MII		BIT(2)
-#define SCTL_EMAC_CLK_SEL		BIT(18) /* 25 Mhz */
-
 #define MDIO_CMD_MII_BUSY		BIT(0)
 #define MDIO_CMD_MII_WRITE		BIT(1)
 
@@ -589,9 +585,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 		/* Set clock gating for ephy */
 		setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
 
-		/* Set Tx clock source as MII with rate 25 MZ */
-		setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
-				SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
 		/* Deassert EPHY */
 		setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
 	}
@@ -693,12 +686,11 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
 	priv->mac_reg = (void *)pdata->iobase;
 
 	sun8i_emac_board_setup(priv);
+	sun8i_emac_set_syscon(priv);
 
 	sun8i_mdio_init(dev->name, priv);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
 
-	sun8i_emac_set_syscon(priv);
-
 	return sun8i_phy_init(priv, dev);
 }
 
-- 
cgit v0.10.2


From 4fd92db8dbf6d9275a921e8e9f2b6aeeba7e5002 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 27 Jul 2016 03:47:58 +0900
Subject: ARM: uniphier: move CONFIG_I2C_EEPROM to defconfig

We already have the entry for this option in Kconfig, so let's
migrate to it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index ffcac79..57b9c07 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_UNIPHIER_SERIAL=y
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index cbc65dd..e6aa525 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 22615a6..47b577a 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -22,6 +22,8 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index 18f4caf..e156ec5 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index cf6d3e4..f943516 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -22,6 +22,8 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 0965019..598cde2 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -21,6 +21,8 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
 CONFIG_MMC_UNIPHIER=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 169c197..e485583 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_UNIPHIER_COMMON_H__
 #define __CONFIG_UNIPHIER_COMMON_H__
 
-#define CONFIG_I2C_EEPROM
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
 
 #define CONFIG_SMC911X
-- 
cgit v0.10.2


From 2eb1ff3b5b61352dcf43ca48f2b6470ec312b8d7 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Tue, 26 Jul 2016 22:26:39 +0200
Subject: sunxi: Disable sun8i emac driver

Disable the sun8i emac driver for now, there are 2 issues with it:

1) It is causing issues with network connectivity under the kernel driver,
when booting the kernel with v2 of Corentin's sun8i-h3 emac driver, I get
the connection status bouncing between connected at 100mbps full-duplex
and being down every second.

The second issue is that when trying to use it from u-boot
I get a number of unaligned cache flush errors:

=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 2281aed..366fa08 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -14,4 +14,3 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_SUN8I_EMAC=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 5c97de1..0bf79bf 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,4 +10,3 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-CONFIG_SUN8I_EMAC=y
-- 
cgit v0.10.2


From dec0242be7b5544c3c4f9a7ead46fa5eeadd6222 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Tue, 28 Jun 2016 15:52:20 +0900
Subject: dm: mmc: dwmmc: fix the wrong explanation for clock values

This e,g is wrong. Maximum/minimum e.g values are swapped each other.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/include/dwmmc.h b/include/dwmmc.h
index 6aebe96..164d1dc 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -256,8 +256,8 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
  * @name:	Device name (normally dev->name)
  * @buswidth:	Bus width (in bits, such as 4 or 8)
  * @caps:	Host capabilities (MMC_MODE_...)
- * @max_clk:	Maximum supported clock speed in HZ (e.g. 400000)
- * @min_clk:	Minimum supported clock speed in HZ (e.g. 150000000)
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
  */
 void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 		     uint caps, u32 max_clk, u32 min_clk);
@@ -286,8 +286,8 @@ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  * This is used when you are not using CONFIG_BLK. Convert your driver over!
  *
  * @host:	DWMMC host structure
- * @max_clk:	Maximum supported clock speed in HZ (e.g. 400000)
- * @min_clk:	Minimum supported clock speed in HZ (e.g. 150000000)
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
  * @return 0 if OK, -ve on error
  */
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
-- 
cgit v0.10.2


From 5628347f59e1672f381b8113e85e47529770ab47 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Tue, 28 Jun 2016 15:52:21 +0900
Subject: dm: mmc: dwmmc: use the callback functions as static

There are no places to call these functions.
It should be used the callback function.
Then it can be used as static functions.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 2cf7bae..fe2147a 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -182,7 +182,7 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host,
 }
 
 #ifdef CONFIG_DM_MMC_OPS
-int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 		   struct mmc_data *data)
 {
 	struct mmc *mmc = mmc_get_mmc_dev(dev);
@@ -381,7 +381,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 }
 
 #ifdef CONFIG_DM_MMC_OPS
-int dwmci_set_ios(struct udevice *dev)
+static int dwmci_set_ios(struct udevice *dev)
 {
 	struct mmc *mmc = mmc_get_mmc_dev(dev);
 #else
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 164d1dc..d18ec84 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -295,9 +295,6 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 
 #ifdef CONFIG_DM_MMC_OPS
 /* Export the operations to drivers */
-int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
-		   struct mmc_data *data);
-int dwmci_set_ios(struct udevice *dev);
 int dwmci_probe(struct udevice *dev);
 extern const struct dm_mmc_ops dm_dwmci_ops;
 #endif
-- 
cgit v0.10.2


From cc7f66f70cc2c59fe8ebf9011658447815278894 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:08 -0600
Subject: dm: core: Add a function to bind child devices

We currently use dm_scan_fdt_node() to bind devices. It is an internal
function and it requires the caller to know whether we are pre- or post-
relocation.

This requirement has become quite common in drivers, so the current function
is not ideal.

Add a new function with fewer arguments, that does not require internal
headers. This can be used directly as a post_bind() method if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 1587024..33dc9c0 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -218,6 +218,15 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
 	return ret;
 }
 
+int dm_scan_fdt_dev(struct udevice *dev)
+{
+	if (dev->of_offset == -1)
+		return 0;
+
+	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,
+				gd->flags & GD_FLG_RELOC ? false : true);
+}
+
 int dm_scan_fdt(const void *blob, bool pre_reloc_only)
 {
 	return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only);
diff --git a/include/dm/device.h b/include/dm/device.h
index 705849b..babf8ac 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -612,6 +612,22 @@ static inline bool device_is_on_pci_bus(struct udevice *dev)
 #define device_foreach_child_safe(pos, next, parent)	\
 	list_for_each_entry_safe(pos, next, &parent->child_head, sibling_node)
 
+/**
+ * dm_scan_fdt_dev() - Bind child device in a the device tree
+ *
+ * This handles device which have sub-nodes in the device tree. It scans all
+ * sub-nodes and binds drivers for each node where a driver can be found.
+ *
+ * If this is called prior to relocation, only pre-relocation devices will be
+ * bound (those marked with u-boot,dm-pre-reloc in the device tree, or where
+ * the driver has the DM_FLAG_PRE_RELOC flag set). Otherwise, all devices will
+ * be bound.
+ *
+ * @dev:	Device to scan
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt_dev(struct udevice *dev);
+
 /* device resource management */
 typedef void (*dr_release_t)(struct udevice *dev, void *res);
 typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data);
-- 
cgit v0.10.2


From 2e3f1ff63f50f36e74d46f939823241856ebf1bd Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:09 -0600
Subject: dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()

This new function is more convenient for callers, and handles pre-relocation
situations automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c
index c6e8f73..b8254ff 100644
--- a/arch/x86/lib/lpc-uclass.c
+++ b/arch/x86/lib/lpc-uclass.c
@@ -7,7 +7,6 @@
 
 #include <common.h>
 #include <dm.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -19,8 +18,7 @@ static int lpc_uclass_post_bind(struct udevice *bus)
 	 * Before relocation, only bind devices marked for pre-relocation
 	 * use.
 	 */
-	return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
-				gd->flags & GD_FLG_RELOC ? false : true);
+	return dm_scan_fdt_dev(bus);
 }
 
 UCLASS_DRIVER(lpc) = {
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 0f39c9f..26ee13e 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -36,7 +36,6 @@
 #include <asm/state.h>
 #endif
 #include <asm/unaligned.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -758,7 +757,7 @@ int usb_hub_scan(struct udevice *hub)
 static int usb_hub_post_bind(struct udevice *dev)
 {
 	/* Scan the bus for devices */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 static int usb_hub_post_probe(struct udevice *dev)
diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
index 1a9c864..5c955da 100644
--- a/drivers/core/simple-bus.c
+++ b/drivers/core/simple-bus.c
@@ -6,7 +6,6 @@
 
 #include <common.h>
 #include <dm.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,7 +40,7 @@ static int simple_bus_post_bind(struct udevice *dev)
 		plat->size = cell[2];
 	}
 
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 UCLASS_DRIVER(simple_bus) = {
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 20b30ff..16447b8 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -12,7 +12,6 @@
 #include <malloc.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -503,7 +502,7 @@ static int i2c_post_bind(struct udevice *dev)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 	/* Scan the bus for devices */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+        return dm_scan_fdt_dev(dev);
 #else
 	return 0;
 #endif
diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c
index 2c84c41..4696a1a 100644
--- a/drivers/i2c/sandbox_i2c.c
+++ b/drivers/i2c/sandbox_i2c.c
@@ -14,7 +14,6 @@
 #include <asm/test.h>
 #include <dm/lists.h>
 #include <dm/device-internal.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,8 +32,7 @@ static int get_emul(struct udevice *dev, struct udevice **devp,
 	*opsp = NULL;
 	plat = dev_get_parent_platdata(dev);
 	if (!plat->emul) {
-		ret = dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,
-				       false);
+		ret = dm_scan_fdt_dev(dev);
 		if (ret)
 			return ret;
 
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index e3229ef..f50e73f 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -26,7 +26,6 @@
 #include <asm/io.h>
 #include <asm-generic/gpio.h>
 #include <dm/device-internal.h>
-#include <dm/root.h>
 #include <dm/uclass-internal.h>
 
 #ifdef DEBUG_TRACE
@@ -1453,7 +1452,7 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 int cros_ec_post_bind(struct udevice *dev)
 {
 	/* Scan for available EC devices (e.g. I2C tunnel) */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 U_BOOT_CMD(
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index 7216660..5b2fa1f 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <dm.h>
 #include <pch.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,8 +62,7 @@ static int pch_uclass_post_bind(struct udevice *bus)
 	 * Before relocation, only bind devices marked for pre-relocation
 	 * use.
 	 */
-	return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
-				gd->flags & GD_FLG_RELOC ? false : true);
+	return dm_scan_fdt_dev(bus);
 }
 
 UCLASS_DRIVER(pch) = {
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 32590ce..230d181 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -13,7 +13,6 @@
 #include <pci.h>
 #include <asm/io.h>
 #include <dm/lists.h>
-#include <dm/root.h>
 #include <dm/device-internal.h>
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 #include <asm/fsp/fsp_support.h>
@@ -756,13 +755,6 @@ error:
 static int pci_uclass_post_bind(struct udevice *bus)
 {
 	/*
-	 * If there is no pci device listed in the device tree,
-	 * don't bother scanning the device tree.
-	 */
-	if (bus->of_offset == -1)
-		return 0;
-
-	/*
 	 * Scan the device tree for devices. This does not probe the PCI bus,
 	 * as this is not permitted while binding. It just finds devices
 	 * mentioned in the device tree.
@@ -770,8 +762,7 @@ static int pci_uclass_post_bind(struct udevice *bus)
 	 * Before relocation, only bind devices marked for pre-relocation
 	 * use.
 	 */
-	return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
-				gd->flags & GD_FLG_RELOC ? false : true);
+	return dm_scan_fdt_dev(bus);
 }
 
 static int decode_regions(struct pci_controller *hose, const void *blob,
diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c
index 6de5130..b562813 100644
--- a/drivers/pci/pci_sandbox.c
+++ b/drivers/pci/pci_sandbox.c
@@ -10,7 +10,6 @@
 #include <fdtdec.h>
 #include <inttypes.h>
 #include <pci.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,7 +54,7 @@ static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn,
 static int sandbox_pci_child_post_bind(struct udevice *dev)
 {
 	/* Attach an emulator if we can */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 static const struct dm_pci_ops sandbox_pci_ops = {
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
index 5cf97ec..5636f8f 100644
--- a/drivers/pinctrl/pinctrl_pic32.c
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -10,7 +10,6 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <dm/pinctrl.h>
-#include <dm/root.h>
 #include <mach/pic32.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -344,7 +343,7 @@ static int pic32_pinctrl_probe(struct udevice *dev)
 static int pic32_pinctrl_bind(struct udevice *dev)
 {
 	/* scan child GPIO banks */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 static const struct udevice_id pic32_pinctrl_ids[] = {
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 1f78bf8..3648678 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -15,7 +15,6 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/periph.h>
 #include <dm/pinctrl.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -256,7 +255,7 @@ static struct pinctrl_ops rk3036_pinctrl_ops = {
 static int rk3036_pinctrl_bind(struct udevice *dev)
 {
 	/* scan child GPIO banks */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 static int rk3036_pinctrl_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 8cb3b82..4650066 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -17,7 +17,6 @@
 #include <asm/arch/periph.h>
 #include <asm/arch/pmu_rk3288.h>
 #include <dm/pinctrl.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -669,8 +668,7 @@ static int rk3288_pinctrl_bind(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	return 0;
 #else
-	/* scan child GPIO banks */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 #endif
 }
 
diff --git a/drivers/power/pmic/pm8916.c b/drivers/power/pmic/pm8916.c
index d4c7d4a..6f5608e 100644
--- a/drivers/power/pmic/pm8916.c
+++ b/drivers/power/pmic/pm8916.c
@@ -7,7 +7,6 @@
  */
 #include <common.h>
 #include <dm.h>
-#include <dm/root.h>
 #include <power/pmic.h>
 #include <spmi/spmi.h>
 
@@ -82,7 +81,7 @@ static int pm8916_probe(struct udevice *dev)
 
 static int pm8916_bind(struct udevice *dev)
 {
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 U_BOOT_DRIVER(pmic_pm8916) = {
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 465ff3f..17f22dd 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -13,7 +13,7 @@ config DM_REGULATOR
 	- 'drivers/power/pmic/regulator-uclass.c'
 	It's important to call the device_bind() with the proper node offset,
 	when binding the regulator devices. The pmic_bind_childs() can be used
-	for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node()
+	for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev()
 	otherwise. Detailed information can be found in the header file.
 
 config SPL_DM_REGULATOR
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 8003f9b..3d3005c 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -12,7 +12,6 @@
 #include <spi.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
-#include <dm/root.h>
 #include <dm/lists.h>
 #include <dm/util.h>
 
@@ -112,7 +111,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 static int spi_post_bind(struct udevice *dev)
 {
 	/* Scan the bus for devices */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 static int spi_child_post_bind(struct udevice *dev)
diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c
index 4ddd51b..9fa330b 100644
--- a/drivers/spmi/spmi-uclass.c
+++ b/drivers/spmi/spmi-uclass.c
@@ -9,7 +9,6 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <dm/root.h>
 #include <spmi/spmi.h>
 #include <linux/ctype.h>
 
@@ -38,7 +37,7 @@ int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
 
 static int spmi_post_bind(struct udevice *dev)
 {
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 UCLASS_DRIVER(spmi) = {
diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c
index ee7ea5a..da91d04 100644
--- a/drivers/usb/emul/usb-emul-uclass.c
+++ b/drivers/usb/emul/usb-emul-uclass.c
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <dm.h>
 #include <usb.h>
-#include <dm/root.h>
 #include <dm/device-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -268,7 +267,7 @@ int usb_emul_setup_device(struct udevice *dev, int maxpacketsize,
 int usb_emul_post_bind(struct udevice *dev)
 {
 	/* Scan the bus for devices */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 void usb_emul_reset(struct udevice *dev)
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 69c9a50..070e271 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -14,7 +14,6 @@
 #include <usb.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
-#include <dm/root.h>
 #include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -351,8 +350,7 @@ struct usb_device *usb_get_dev_index(struct udevice *bus, int index)
 
 int usb_post_bind(struct udevice *dev)
 {
-	/* Scan the bus for devices */
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
diff --git a/include/power/regulator.h b/include/power/regulator.h
index 63c0814..9bcd728 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -54,7 +54,7 @@
  * which does the scan on the device node, for the 'regulator-name' constraint.
  * If the parent is not a PMIC device, and the child is not bind by function:
  * 'pmic_bind_childs()', then it's recommended to bind the device by call to
- * dm_scan_fdt_node() - this is usually done automatically for bus devices,
+ * dm_scan_fdt_dev() - this is usually done automatically for bus devices,
  * as a post bind method.
  *
  * Regulator get:
diff --git a/test/dm/bus.c b/test/dm/bus.c
index 3b5a23b..d94dcf7 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <dm.h>
 #include <dm/device-internal.h>
-#include <dm/root.h>
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
 #include <dm/util.h>
@@ -30,7 +29,7 @@ static struct dm_test_state *test_state;
 
 static int testbus_drv_probe(struct udevice *dev)
 {
-	return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+	return dm_scan_fdt_dev(dev);
 }
 
 static int testbus_child_post_bind(struct udevice *dev)
-- 
cgit v0.10.2


From 911954859d6dece49c3e4835faea004cfe392506 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:10 -0600
Subject: dm: Use dm_scan_fdt_dev() directly where possible

Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c
index b8254ff..eb033e6 100644
--- a/arch/x86/lib/lpc-uclass.c
+++ b/arch/x86/lib/lpc-uclass.c
@@ -10,19 +10,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int lpc_uclass_post_bind(struct udevice *bus)
-{
-	/*
-	 * Scan the device tree for devices
-	 *
-	 * Before relocation, only bind devices marked for pre-relocation
-	 * use.
-	 */
-	return dm_scan_fdt_dev(bus);
-}
-
 UCLASS_DRIVER(lpc) = {
 	.id		= UCLASS_LPC,
 	.name		= "lpc",
-	.post_bind	= lpc_uclass_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 };
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 26ee13e..ff9cd50 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -754,12 +754,6 @@ int usb_hub_scan(struct udevice *hub)
 	return usb_hub_configure(udev);
 }
 
-static int usb_hub_post_bind(struct udevice *dev)
-{
-	/* Scan the bus for devices */
-	return dm_scan_fdt_dev(dev);
-}
-
 static int usb_hub_post_probe(struct udevice *dev)
 {
 	debug("%s\n", __func__);
@@ -781,7 +775,7 @@ U_BOOT_DRIVER(usb_generic_hub) = {
 UCLASS_DRIVER(usb_hub) = {
 	.id		= UCLASS_USB_HUB,
 	.name		= "usb_hub",
-	.post_bind	= usb_hub_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 	.post_probe	= usb_hub_post_probe,
 	.child_pre_probe	= usb_child_pre_probe,
 	.per_child_auto_alloc_size = sizeof(struct usb_device),
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 16447b8..dbd3789 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -498,16 +498,6 @@ static int i2c_post_probe(struct udevice *dev)
 #endif
 }
 
-static int i2c_post_bind(struct udevice *dev)
-{
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	/* Scan the bus for devices */
-        return dm_scan_fdt_dev(dev);
-#else
-	return 0;
-#endif
-}
-
 static int i2c_child_post_bind(struct udevice *dev)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
@@ -526,7 +516,9 @@ UCLASS_DRIVER(i2c) = {
 	.id		= UCLASS_I2C,
 	.name		= "i2c",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
-	.post_bind	= i2c_post_bind,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	.post_bind	= dm_scan_fdt_dev,
+#endif
 	.post_probe	= i2c_post_probe,
 	.per_device_auto_alloc_size = sizeof(struct dm_i2c_bus),
 	.per_child_platdata_auto_alloc_size = sizeof(struct dm_i2c_chip),
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index f50e73f..aea8d61 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1449,12 +1449,6 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return ret;
 }
 
-int cros_ec_post_bind(struct udevice *dev)
-{
-	/* Scan for available EC devices (e.g. I2C tunnel) */
-	return dm_scan_fdt_dev(dev);
-}
-
 U_BOOT_CMD(
 	crosec,	6,	1,	do_cros_ec,
 	"CROS-EC utility command",
@@ -1481,5 +1475,5 @@ UCLASS_DRIVER(cros_ec) = {
 	.id		= UCLASS_CROS_EC,
 	.name		= "cros_ec",
 	.per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
-	.post_bind	= cros_ec_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 };
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index 5b2fa1f..af794eb 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -54,19 +54,8 @@ int pch_get_io_base(struct udevice *dev, u32 *iobasep)
 	return ops->get_io_base(dev, iobasep);
 }
 
-static int pch_uclass_post_bind(struct udevice *bus)
-{
-	/*
-	 * Scan the device tree for devices
-	 *
-	 * Before relocation, only bind devices marked for pre-relocation
-	 * use.
-	 */
-	return dm_scan_fdt_dev(bus);
-}
-
 UCLASS_DRIVER(pch) = {
 	.id		= UCLASS_PCH,
 	.name		= "pch",
-	.post_bind	= pch_uclass_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 };
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 230d181..342b78c 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -752,19 +752,6 @@ error:
 	return ret;
 }
 
-static int pci_uclass_post_bind(struct udevice *bus)
-{
-	/*
-	 * Scan the device tree for devices. This does not probe the PCI bus,
-	 * as this is not permitted while binding. It just finds devices
-	 * mentioned in the device tree.
-	 *
-	 * Before relocation, only bind devices marked for pre-relocation
-	 * use.
-	 */
-	return dm_scan_fdt_dev(bus);
-}
-
 static int decode_regions(struct pci_controller *hose, const void *blob,
 			  int parent_node, int node)
 {
@@ -1245,7 +1232,7 @@ UCLASS_DRIVER(pci) = {
 	.id		= UCLASS_PCI,
 	.name		= "pci",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
-	.post_bind	= pci_uclass_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 	.pre_probe	= pci_uclass_pre_probe,
 	.post_probe	= pci_uclass_post_probe,
 	.child_post_bind = pci_uclass_child_post_bind,
diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c
index b562813..6a84ee3 100644
--- a/drivers/pci/pci_sandbox.c
+++ b/drivers/pci/pci_sandbox.c
@@ -51,12 +51,6 @@ static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn,
 	return ops->read_config(emul, offset, valuep, size);
 }
 
-static int sandbox_pci_child_post_bind(struct udevice *dev)
-{
-	/* Attach an emulator if we can */
-	return dm_scan_fdt_dev(dev);
-}
-
 static const struct dm_pci_ops sandbox_pci_ops = {
 	.read_config = sandbox_pci_read_config,
 	.write_config = sandbox_pci_write_config,
@@ -72,7 +66,9 @@ U_BOOT_DRIVER(pci_sandbox) = {
 	.id	= UCLASS_PCI,
 	.of_match = sandbox_pci_ids,
 	.ops	= &sandbox_pci_ops,
-	.child_post_bind = sandbox_pci_child_post_bind,
+
+	/* Attach an emulator if we can */
+	.child_post_bind = dm_scan_fdt_dev,
 	.per_child_platdata_auto_alloc_size =
 			sizeof(struct pci_child_platdata),
 };
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
index 5636f8f..9acac29 100644
--- a/drivers/pinctrl/pinctrl_pic32.c
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -340,12 +340,6 @@ static int pic32_pinctrl_probe(struct udevice *dev)
 	return 0;
 }
 
-static int pic32_pinctrl_bind(struct udevice *dev)
-{
-	/* scan child GPIO banks */
-	return dm_scan_fdt_dev(dev);
-}
-
 static const struct udevice_id pic32_pinctrl_ids[] = {
 	{ .compatible = "microchip,pic32mzda-pinctrl" },
 	{ }
@@ -357,6 +351,6 @@ U_BOOT_DRIVER(pinctrl_pic32) = {
 	.of_match	= pic32_pinctrl_ids,
 	.ops		= &pic32_pinctrl_ops,
 	.probe		= pic32_pinctrl_probe,
-	.bind		= pic32_pinctrl_bind,
+	.bind		= dm_scan_fdt_dev,
 	.priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv),
 };
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 3648678..6aea856 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -252,12 +252,6 @@ static struct pinctrl_ops rk3036_pinctrl_ops = {
 	.get_periph_id	= rk3036_pinctrl_get_periph_id,
 };
 
-static int rk3036_pinctrl_bind(struct udevice *dev)
-{
-	/* scan child GPIO banks */
-	return dm_scan_fdt_dev(dev);
-}
-
 static int rk3036_pinctrl_probe(struct udevice *dev)
 {
 	struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
@@ -278,6 +272,6 @@ U_BOOT_DRIVER(pinctrl_rk3036) = {
 	.of_match	= rk3036_pinctrl_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
 	.ops		= &rk3036_pinctrl_ops,
-	.bind		= rk3036_pinctrl_bind,
+	.bind		= dm_scan_fdt_dev,
 	.probe		= rk3036_pinctrl_probe,
 };
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 4650066..ae8a4f1 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -663,15 +663,6 @@ static struct pinctrl_ops rk3288_pinctrl_ops = {
 	.get_periph_id	= rk3288_pinctrl_get_periph_id,
 };
 
-static int rk3288_pinctrl_bind(struct udevice *dev)
-{
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	return 0;
-#else
-	return dm_scan_fdt_dev(dev);
-#endif
-}
-
 #ifndef CONFIG_SPL_BUILD
 static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
 				       struct rockchip_pin_bank *banks,
@@ -728,6 +719,8 @@ U_BOOT_DRIVER(pinctrl_rk3288) = {
 	.of_match	= rk3288_pinctrl_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 	.ops		= &rk3288_pinctrl_ops,
-	.bind		= rk3288_pinctrl_bind,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.bind		= dm_scan_fdt_dev,
+#endif
 	.probe		= rk3288_pinctrl_probe,
 };
diff --git a/drivers/power/pmic/pm8916.c b/drivers/power/pmic/pm8916.c
index 6f5608e..2b65c69 100644
--- a/drivers/power/pmic/pm8916.c
+++ b/drivers/power/pmic/pm8916.c
@@ -78,17 +78,11 @@ static int pm8916_probe(struct udevice *dev)
 	return 0;
 }
 
-
-static int pm8916_bind(struct udevice *dev)
-{
-	return dm_scan_fdt_dev(dev);
-}
-
 U_BOOT_DRIVER(pmic_pm8916) = {
 	.name = "pmic_pm8916",
 	.id = UCLASS_PMIC,
 	.of_match = pm8916_ids,
-	.bind = pm8916_bind,
+	.bind = dm_scan_fdt_dev,
 	.probe = pm8916_probe,
 	.ops = &pm8916_ops,
 	.priv_auto_alloc_size = sizeof(struct pm8916_priv),
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 3d3005c..247abfa 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -108,12 +108,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
 }
 
-static int spi_post_bind(struct udevice *dev)
-{
-	/* Scan the bus for devices */
-	return dm_scan_fdt_dev(dev);
-}
-
 static int spi_child_post_bind(struct udevice *dev)
 {
 	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
@@ -445,7 +439,7 @@ UCLASS_DRIVER(spi) = {
 	.id		= UCLASS_SPI,
 	.name		= "spi",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
-	.post_bind	= spi_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 	.post_probe	= spi_post_probe,
 	.child_pre_probe = spi_child_pre_probe,
 	.per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c
index 9fa330b..6edece2 100644
--- a/drivers/spmi/spmi-uclass.c
+++ b/drivers/spmi/spmi-uclass.c
@@ -35,13 +35,8 @@ int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
 	return ops->write(dev, usid, pid, reg, value);
 }
 
-static int spmi_post_bind(struct udevice *dev)
-{
-	return dm_scan_fdt_dev(dev);
-}
-
 UCLASS_DRIVER(spmi) = {
 	.id		= UCLASS_SPMI,
 	.name		= "spmi",
-	.post_bind	= spmi_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 };
diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c
index da91d04..6e03c1e 100644
--- a/drivers/usb/emul/usb-emul-uclass.c
+++ b/drivers/usb/emul/usb-emul-uclass.c
@@ -264,12 +264,6 @@ int usb_emul_setup_device(struct udevice *dev, int maxpacketsize,
 	return 0;
 }
 
-int usb_emul_post_bind(struct udevice *dev)
-{
-	/* Scan the bus for devices */
-	return dm_scan_fdt_dev(dev);
-}
-
 void usb_emul_reset(struct udevice *dev)
 {
 	struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);
@@ -281,7 +275,7 @@ void usb_emul_reset(struct udevice *dev)
 UCLASS_DRIVER(usb_emul) = {
 	.id		= UCLASS_USB_EMUL,
 	.name		= "usb_emul",
-	.post_bind	= usb_emul_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 	.per_child_auto_alloc_size = sizeof(struct usb_device),
 	.per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata),
 };
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
index 070e271..be114fc 100644
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -348,11 +348,6 @@ struct usb_device *usb_get_dev_index(struct udevice *bus, int index)
 }
 #endif
 
-int usb_post_bind(struct udevice *dev)
-{
-	return dm_scan_fdt_dev(dev);
-}
-
 int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
 {
 	struct usb_platdata *plat;
@@ -766,7 +761,7 @@ UCLASS_DRIVER(usb) = {
 	.id		= UCLASS_USB,
 	.name		= "usb",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
-	.post_bind	= usb_post_bind,
+	.post_bind	= dm_scan_fdt_dev,
 	.priv_auto_alloc_size = sizeof(struct usb_uclass_priv),
 	.per_child_auto_alloc_size = sizeof(struct usb_device),
 	.per_device_auto_alloc_size = sizeof(struct usb_bus_priv),
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
index 23d612e..e2688bf 100644
--- a/test/dm/i2c.c
+++ b/test/dm/i2c.c
@@ -31,8 +31,8 @@ static int dm_test_i2c_find(struct unit_test_state *uts)
 						       false, &bus));
 
 	/*
-	 * i2c_post_bind() will bind devices to chip selects. Check this then
-	 * remove the emulation and the slave device.
+	 * The post_bind() method will bind devices to chip selects. Check
+	 * this then remove the emulation and the slave device.
 	 */
 	ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
 	ut_assertok(dm_i2c_probe(bus, chip, 0, &dev));
diff --git a/test/dm/spi.c b/test/dm/spi.c
index 2e27da7..5733096 100644
--- a/test/dm/spi.c
+++ b/test/dm/spi.c
@@ -30,8 +30,8 @@ static int dm_test_spi_find(struct unit_test_state *uts)
 						       false, &bus));
 
 	/*
-	 * spi_post_bind() will bind devices to chip selects. Check this then
-	 * remove the emulation and the slave device.
+	 * The post_bind() method will bind devices to chip selects. Check
+	 * this then remove the emulation and the slave device.
 	 */
 	ut_asserteq(0, uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus));
 	ut_assertok(spi_cs_info(bus, cs, &info));
-- 
cgit v0.10.2


From 7f7ddf2a882c13e9a64eae80d1539cc05632a402 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:11 -0600
Subject: arm: Show early-malloc() usage in bdinfo

This is useful information to show how close we are to the limit. At present
it is only available by enabling DEBUG in board_r.c.

Make it available with the 'bdinfo' command also.

Note that this affects ARM only. The bdinfo command is different for each
architecture. Rather than duplicating the code it would be better to
refactor it (as was done with global_data).

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index f2435ab..1fb66c4 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -416,6 +416,11 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 #ifdef CONFIG_BOARD_TYPES
 	printf("Board Type  = %ld\n", gd->board_type);
 #endif
+#ifdef CONFIG_SYS_MALLOC_F
+	printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
+	       CONFIG_SYS_MALLOC_F_LEN);
+#endif
+
 	return 0;
 }
 
-- 
cgit v0.10.2


From fbfa1aba9181161fe5b38a180f20440a0511c051 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:12 -0600
Subject: net: phy: marvell: Add a missing errno.h header

This corrects a build error on zynqmp.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 58d287b..4eeb0f6 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -8,6 +8,7 @@
  */
 #include <config.h>
 #include <common.h>
+#include <errno.h>
 #include <phy.h>
 
 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
-- 
cgit v0.10.2


From 04e38905d72e4b35fade1be4b83100a257d465a5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:13 -0600
Subject: zynq: Increase the early malloc() size

This is needed to support driver-model conversion of USB and block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 6c71d78..ed3305d 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -20,4 +20,8 @@ config SYS_CONFIG_NAME
 config ZYNQMP_USB
 	bool "Configure ZynqMP USB"
 
+config SYS_MALLOC_F_LEN
+	default 0x600
+
+
 endif
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index db3c579..a982320 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -17,4 +17,7 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.
 
+config SYS_MALLOC_F_LEN
+	default 0x600
+
 endif
-- 
cgit v0.10.2


From dec49e862ef9e74654fad3595fda5be99d33711a Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:14 -0600
Subject: dm: zynq: usb: Convert to CONFIG_DM_USB

Convert zynq USB to driver model. Note this is tested on zynq-zybo only.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4a62d4b..9a7ebed 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -661,6 +661,7 @@ config ARCH_ZYNQ
 	select DM_SERIAL
 	select DM_SPI_FLASH
 	select SPL_SEPARATE_BSS if SPL
+	select DM_USB if USB
 
 config ARCH_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
@@ -671,6 +672,7 @@ config ARCH_ZYNQMP
 	select SUPPORT_SPL
 	select CLK
 	select SPL_CLK
+	select DM_USB if USB
 
 config TEGRA
 	bool "NVIDIA Tegra"
diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c
index 37a7935..76642cd 100644
--- a/drivers/usb/host/ehci-zynq.c
+++ b/drivers/usb/host/ehci-zynq.c
@@ -7,55 +7,48 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <usb.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
-#include <usb.h>
 #include <usb/ehci-ci.h>
 #include <usb/ulpi.h>
 
 #include "ehci.h"
 
-#define ZYNQ_USB_USBCMD_RST			0x0000002
-#define ZYNQ_USB_USBCMD_STOP			0x0000000
-#define ZYNQ_USB_NUM_MIO			12
+struct zynq_ehci_priv {
+	struct ehci_ctrl ehcictrl;
+	struct usb_ehci *ehci;
+};
 
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index,  enum usb_init_type init, struct ehci_hccr **hccr,
-		  struct ehci_hcor **hcor)
+static int ehci_zynq_ofdata_to_platdata(struct udevice *dev)
 {
-	struct usb_ehci *ehci;
+	struct zynq_ehci_priv *priv = dev_get_priv(dev);
+
+	priv->ehci = (struct usb_ehci *)dev_get_addr_ptr(dev);
+	if (!priv->ehci)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int ehci_zynq_probe(struct udevice *dev)
+{
+	struct usb_platdata *plat = dev_get_platdata(dev);
+	struct zynq_ehci_priv *priv = dev_get_priv(dev);
+	struct ehci_hccr *hccr;
+	struct ehci_hcor *hcor;
 	struct ulpi_viewport ulpi_vp;
-	int ret, mio_usb;
 	/* Used for writing the ULPI data address */
 	struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+	int ret;
 
-	if (!index) {
-		mio_usb = zynq_slcr_get_mio_pin_status("usb0");
-		if (mio_usb != ZYNQ_USB_NUM_MIO) {
-			printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb,
-			       index);
-			return -1;
-		}
-		ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
-	} else {
-		mio_usb = zynq_slcr_get_mio_pin_status("usb1");
-		if (mio_usb != ZYNQ_USB_NUM_MIO) {
-			printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb,
-			       index);
-			return -1;
-		}
-		ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
-	}
-
-	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+	hccr = (struct ehci_hccr *)((uint32_t)&priv->ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
-	ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
+	ulpi_vp.viewport_addr = (u32)&priv->ehci->ulpi_viewpoint;
 	ulpi_vp.port_num = 0;
 
 	ret = ulpi_init(&ulpi_vp);
@@ -77,28 +70,34 @@ int ehci_hcd_init(int index,  enum usb_init_type init, struct ehci_hccr **hccr,
 	ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
 		   ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-	return 0;
+	return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
 }
 
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
+static int ehci_zynq_remove(struct udevice *dev)
 {
-	struct usb_ehci *ehci;
-
-	if (!index)
-		ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
-	else
-		ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
+	int ret;
 
-	/* Stop controller */
-	writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd);
-	udelay(1000);
-
-	/* Initiate controller reset */
-	writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd);
+	ret = ehci_deregister(dev);
+	if (ret)
+		return ret;
 
 	return 0;
 }
+
+static const struct udevice_id ehci_zynq_ids[] = {
+	{ .compatible = "xlnx,zynq-usb-2.20a" },
+	{ }
+};
+
+U_BOOT_DRIVER(ehci_zynq) = {
+	.name	= "ehci_zynq",
+	.id	= UCLASS_USB,
+	.of_match = ehci_zynq_ids,
+	.ofdata_to_platdata = ehci_zynq_ofdata_to_platdata,
+	.probe = ehci_zynq_probe,
+	.remove = ehci_zynq_remove,
+	.ops	= &ehci_usb_ops,
+	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
+	.priv_auto_alloc_size = sizeof(struct zynq_ehci_priv),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
cgit v0.10.2


From 329a449f2c289b4de8f892fca1d9379ce5fd81b8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:15 -0600
Subject: dm: mmc: zynq: Convert zynq to use driver model for MMC

Move zynq to the latest driver model support by enabling CONFIG_DM_MMC,
CONFIG_DM_MMC_OPS and CONFIG_BLK.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9a7ebed..6de734f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -657,11 +657,13 @@ config ARCH_ZYNQ
 	select DM_GPIO
 	select SPL_DM if SPL
 	select DM_MMC
+	select DM_MMC_OPS
 	select DM_SPI
 	select DM_SERIAL
 	select DM_SPI_FLASH
 	select SPL_SEPARATE_BSS if SPL
 	select DM_USB if USB
+	select BLK
 
 config ARCH_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
@@ -673,6 +675,9 @@ config ARCH_ZYNQMP
 	select CLK
 	select SPL_CLK
 	select DM_USB if USB
+	select DM_MMC
+	select DM_MMC_OPS
+	select BLK
 
 config TEGRA
 	bool "NVIDIA Tegra"
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index d405929..bcd154a 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -17,10 +17,18 @@
 # define CONFIG_ZYNQ_SDHCI_MIN_FREQ	0
 #endif
 
+struct arasan_sdhci_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
 static int arasan_sdhci_probe(struct udevice *dev)
 {
+	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct sdhci_host *host = dev_get_priv(dev);
+	u32 caps;
+	int ret;
 
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 		       SDHCI_QUIRK_BROKEN_R1B;
@@ -31,13 +39,19 @@ static int arasan_sdhci_probe(struct udevice *dev)
 
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
-	add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
-		  CONFIG_ZYNQ_SDHCI_MIN_FREQ);
-
-	upriv->mmc = host->mmc;
+	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+	ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
+			      caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
+			      CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version,
+			      host->quirks, 0);
+	host->mmc = &plat->mmc;
+	if (ret)
+		return ret;
+	host->mmc->priv = host;
 	host->mmc->dev = dev;
+	upriv->mmc = host->mmc;
 
-	return 0;
+	return sdhci_probe(dev);
 }
 
 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
@@ -50,6 +64,18 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
+static int arasan_sdhci_bind(struct udevice *dev)
+{
+	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static const struct udevice_id arasan_sdhci_ids[] = {
 	{ .compatible = "arasan,sdhci-8.9a" },
 	{ }
@@ -60,6 +86,9 @@ U_BOOT_DRIVER(arasan_sdhci_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= arasan_sdhci_ids,
 	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
+	.ops		= &sdhci_ops,
+	.bind		= arasan_sdhci_bind,
 	.probe		= arasan_sdhci_probe,
 	.priv_auto_alloc_size = sizeof(struct sdhci_host),
+	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
 };
-- 
cgit v0.10.2


From f1a485aa404bf4483ecc5eae4423fb334ca68bd3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:16 -0600
Subject: dm: socfpga: mmc: Support CONFIG_BLK

Update the driver to support using driver model for block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 6a0e971..8a96302 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -22,6 +22,11 @@ static const struct socfpga_clock_manager *clock_manager_base =
 static const struct socfpga_system_manager *system_manager_base =
 		(void *)SOCFPGA_SYSMGR_ADDRESS;
 
+struct socfpga_dwmci_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
 /* socfpga implmentation specific driver private data */
 struct dwmci_socfpga_priv_data {
 	struct dwmci_host	host;
@@ -98,21 +103,45 @@ static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
 
 static int socfpga_dwmmc_probe(struct udevice *dev)
 {
+#ifdef CONFIG_BLK
+	struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
+#endif
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
+
+#ifdef CONFIG_BLK
+	dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
+			host->bus_hz, 400000);
+	host->mmc = &plat->mmc;
+#else
 	int ret;
 
 	ret = add_dwmci(host, host->bus_hz, 400000);
 	if (ret)
 		return ret;
-
+#endif
+	host->mmc->priv = &priv->host;
 	upriv->mmc = host->mmc;
 	host->mmc->dev = dev;
 
 	return 0;
 }
 
+static int socfpga_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+	struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
 static const struct udevice_id socfpga_dwmmc_ids[] = {
 	{ .compatible = "altr,socfpga-dw-mshc" },
 	{ }
@@ -123,6 +152,7 @@ U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= socfpga_dwmmc_ids,
 	.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+	.bind		= socfpga_dwmmc_bind,
 	.probe		= socfpga_dwmmc_probe,
 	.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
 };
-- 
cgit v0.10.2


From c9f3c5f9c36127c4221bec7d790d44503d4da5a3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:17 -0600
Subject: dm: usb: Use blk_dread/write() instead of direct calls

Update the USB mass storage code to allow it to work with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index b05913a..86398fc 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -22,7 +22,7 @@ static int ums_read_sector(struct ums *ums_dev,
 	struct blk_desc *block_dev = &ums_dev->block_dev;
 	lbaint_t blkstart = start + ums_dev->start_sector;
 
-	return block_dev->block_read(block_dev, blkstart, blkcnt, buf);
+	return blk_dread(block_dev, blkstart, blkcnt, buf);
 }
 
 static int ums_write_sector(struct ums *ums_dev,
@@ -31,7 +31,7 @@ static int ums_write_sector(struct ums *ums_dev,
 	struct blk_desc *block_dev = &ums_dev->block_dev;
 	lbaint_t blkstart = start + ums_dev->start_sector;
 
-	return block_dev->block_write(block_dev, blkstart, blkcnt, buf);
+	return blk_dwrite(block_dev, blkstart, blkcnt, buf);
 }
 
 static struct ums *ums;
-- 
cgit v0.10.2


From 1e2b3ef8653417f296ee23f32c28abfc086529dd Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Tue, 5 Jul 2016 17:10:18 -0600
Subject: dm: spl: mmc: Support raw partitions with CONFIG_BLK

Fix up the call in mmc_load_image_raw_partition() to use the correct
function to obtain the MMC device, so that this code can support driver
model.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 6b3e9e4..7c7f329 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -155,7 +155,7 @@ static int mmc_load_image_raw_partition(struct mmc *mmc, int partition)
 	disk_partition_t info;
 	int err;
 
-	err = part_get_info(&mmc->block_dev, partition, &info);
+	err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
 	if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		puts("spl: partition error\n");
-- 
cgit v0.10.2


From 61f5ddcb7a997f7b7bca3680cd6f67e60e616841 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 13 Jul 2016 13:45:31 -0600
Subject: Add a power domain framework/uclass

Many SoCs allow power to be applied to or removed from portions of the SoC
(power domains). This may be used to save power. This API provides the
means to control such power management hardware.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/Makefile b/Makefile
index bccfbaa..99cc8cf 100644
--- a/Makefile
+++ b/Makefile
@@ -638,6 +638,7 @@ libs-y += drivers/net/
 libs-y += drivers/net/phy/
 libs-y += drivers/pci/
 libs-y += drivers/power/ \
+	drivers/power/domain/ \
 	drivers/power/fuel_gauge/ \
 	drivers/power/mfd/ \
 	drivers/power/pmic/ \
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9e46f9e..fff175d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -262,6 +262,16 @@
 		};
 	};
 
+	pwrdom: power-domain {
+		compatible = "sandbox,power-domain";
+		#power-domain-cells = <1>;
+	};
+
+	power-domain-test {
+		compatible = "sandbox,power-domain-test";
+		power-domains = <&pwrdom 2>;
+	};
+
 	ram {
 		compatible = "sandbox,ram";
 	};
diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h
new file mode 100644
index 0000000..cad3885
--- /dev/null
+++ b/arch/sandbox/include/asm/power-domain.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_POWER_DOMAIN_H
+#define __SANDBOX_POWER_DOMAIN_H
+
+#include <common.h>
+
+struct udevice;
+
+int sandbox_power_domain_query(struct udevice *dev, unsigned long id);
+
+int sandbox_power_domain_test_get(struct udevice *dev);
+int sandbox_power_domain_test_on(struct udevice *dev);
+int sandbox_power_domain_test_off(struct udevice *dev);
+int sandbox_power_domain_test_free(struct udevice *dev);
+
+#endif
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 29e6d85..887d83a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -176,3 +176,5 @@ CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_SANDBOX_POWER_DOMAIN=y
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3c44167..b422703 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -1,5 +1,7 @@
 menu "Power"
 
+source "drivers/power/domain/Kconfig"
+
 source "drivers/power/pmic/Kconfig"
 
 source "drivers/power/regulator/Kconfig"
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
new file mode 100644
index 0000000..b904097
--- /dev/null
+++ b/drivers/power/domain/Kconfig
@@ -0,0 +1,20 @@
+menu "Power Domain Support"
+
+config POWER_DOMAIN
+	bool "Enable power domain support using Driver Model"
+	depends on DM && OF_CONTROL
+	help
+	  Enable support for the power domain driver class. Many SoCs allow
+	  power to be applied to or removed from portions of the SoC (power
+	  domains). This may be used to save power. This API provides the
+	  means to control such power management hardware.
+
+config SANDBOX_POWER_DOMAIN
+	bool "Enable the sandbox power domain test driver"
+	depends on POWER_DOMAIN && SANDBOX
+	help
+	  Enable support for a test power domain driver implementation, which
+	  simply accepts requests to power on/off various HW modules without
+	  actually doing anything beyond a little error checking.
+
+endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
new file mode 100644
index 0000000..c18292f
--- /dev/null
+++ b/drivers/power/domain/Makefile
@@ -0,0 +1,7 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_POWER_DOMAIN) += power-domain-uclass.o
+obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
+obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c
new file mode 100644
index 0000000..1bb6262
--- /dev/null
+++ b/drivers/power/domain/power-domain-uclass.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <power-domain.h>
+#include <power-domain-uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev)
+{
+	return (struct power_domain_ops *)dev->driver->ops;
+}
+
+static int power_domain_of_xlate_default(struct power_domain *power_domain,
+				       struct fdtdec_phandle_args *args)
+{
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	if (args->args_count != 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	power_domain->id = args->args[0];
+
+	return 0;
+}
+
+int power_domain_get(struct udevice *dev, struct power_domain *power_domain)
+{
+	struct fdtdec_phandle_args args;
+	int ret;
+	struct udevice *dev_power_domain;
+	struct power_domain_ops *ops;
+
+	debug("%s(dev=%p, power_domain=%p)\n", __func__, dev, power_domain);
+
+	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+					     "power-domains",
+					     "#power-domain-cells", 0, 0,
+					     &args);
+	if (ret) {
+		debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_POWER_DOMAIN, args.node,
+					     &dev_power_domain);
+	if (ret) {
+		debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+	ops = power_domain_dev_ops(dev_power_domain);
+
+	power_domain->dev = dev_power_domain;
+	if (ops->of_xlate)
+		ret = ops->of_xlate(power_domain, &args);
+	else
+		ret = power_domain_of_xlate_default(power_domain, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ops->request(power_domain);
+	if (ret) {
+		debug("ops->request() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int power_domain_free(struct power_domain *power_domain)
+{
+	struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev);
+
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	return ops->free(power_domain);
+}
+
+int power_domain_on(struct power_domain *power_domain)
+{
+	struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev);
+
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	return ops->on(power_domain);
+}
+
+int power_domain_off(struct power_domain *power_domain)
+{
+	struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev);
+
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	return ops->off(power_domain);
+}
+
+UCLASS_DRIVER(power_domain) = {
+	.id		= UCLASS_POWER_DOMAIN,
+	.name		= "power_domain",
+};
diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c
new file mode 100644
index 0000000..92a3a2a
--- /dev/null
+++ b/drivers/power/domain/sandbox-power-domain-test.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power-domain.h>
+#include <asm/io.h>
+#include <asm/power-domain.h>
+
+struct sandbox_power_domain_test {
+	struct power_domain pd;
+};
+
+int sandbox_power_domain_test_get(struct udevice *dev)
+{
+	struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
+
+	return power_domain_get(dev, &sbrt->pd);
+}
+
+int sandbox_power_domain_test_on(struct udevice *dev)
+{
+	struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
+
+	return power_domain_on(&sbrt->pd);
+}
+
+int sandbox_power_domain_test_off(struct udevice *dev)
+{
+	struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
+
+	return power_domain_off(&sbrt->pd);
+}
+
+int sandbox_power_domain_test_free(struct udevice *dev)
+{
+	struct sandbox_power_domain_test *sbrt = dev_get_priv(dev);
+
+	return power_domain_free(&sbrt->pd);
+}
+
+static const struct udevice_id sandbox_power_domain_test_ids[] = {
+	{ .compatible = "sandbox,power-domain-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_power_domain_test) = {
+	.name = "sandbox_power_domain_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_power_domain_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_power_domain_test),
+};
diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c
new file mode 100644
index 0000000..9071346
--- /dev/null
+++ b/drivers/power/domain/sandbox-power-domain.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power-domain-uclass.h>
+#include <asm/io.h>
+#include <asm/power-domain.h>
+
+#define SANDBOX_POWER_DOMAINS 3
+
+struct sandbox_power_domain {
+	bool on[SANDBOX_POWER_DOMAINS];
+};
+
+static int sandbox_power_domain_request(struct power_domain *power_domain)
+{
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	if (power_domain->id >= SANDBOX_POWER_DOMAINS)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sandbox_power_domain_free(struct power_domain *power_domain)
+{
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	return 0;
+}
+
+static int sandbox_power_domain_on(struct power_domain *power_domain)
+{
+	struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev);
+
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	sbr->on[power_domain->id] = true;
+
+	return 0;
+}
+
+static int sandbox_power_domain_off(struct power_domain *power_domain)
+{
+	struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev);
+
+	debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+	sbr->on[power_domain->id] = false;
+
+	return 0;
+}
+
+static int sandbox_power_domain_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int sandbox_power_domain_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_power_domain_ids[] = {
+	{ .compatible = "sandbox,power-domain" },
+	{ }
+};
+
+struct power_domain_ops sandbox_power_domain_ops = {
+	.request = sandbox_power_domain_request,
+	.free = sandbox_power_domain_free,
+	.on = sandbox_power_domain_on,
+	.off = sandbox_power_domain_off,
+};
+
+U_BOOT_DRIVER(sandbox_power_domain) = {
+	.name = "sandbox_power_domain",
+	.id = UCLASS_POWER_DOMAIN,
+	.of_match = sandbox_power_domain_ids,
+	.bind = sandbox_power_domain_bind,
+	.probe = sandbox_power_domain_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_power_domain),
+	.ops = &sandbox_power_domain_ops,
+};
+
+int sandbox_power_domain_query(struct udevice *dev, unsigned long id)
+{
+	struct sandbox_power_domain *sbr = dev_get_priv(dev);
+
+	debug("%s(dev=%p, id=%ld)\n", __func__, dev, id);
+
+	if (id >= SANDBOX_POWER_DOMAINS)
+		return -EINVAL;
+
+	return sbr->on[id];
+}
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index c5cdfc7..eb78c4d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -59,6 +59,7 @@ enum uclass_id {
 	UCLASS_PINCTRL,		/* Pinctrl (pin muxing/configuration) device */
 	UCLASS_PMIC,		/* PMIC I/O device */
 	UCLASS_PWM,		/* Pulse-width modulator */
+	UCLASS_POWER_DOMAIN,	/* (SoC) Power domains */
 	UCLASS_PWRSEQ,		/* Power sequence device */
 	UCLASS_RAM,		/* RAM controller */
 	UCLASS_REGULATOR,	/* Regulator device */
diff --git a/include/power-domain-uclass.h b/include/power-domain-uclass.h
new file mode 100644
index 0000000..5878021
--- /dev/null
+++ b/include/power-domain-uclass.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _POWER_DOMAIN_UCLASS_H
+#define _POWER_DOMAIN_UCLASS_H
+
+/* See power-domain.h for background documentation. */
+
+#include <power-domain.h>
+
+struct udevice;
+
+/**
+ * struct power_domain_ops - The functions that a power domain controller driver
+ * must implement.
+ */
+struct power_domain_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) power domain
+	 * specifier.
+	 *
+	 * The power domain core calls this function as the first step in
+	 * implementing a client's power_domain_get() call.
+	 *
+	 * If this function pointer is set to NULL, the power domain core will
+	 * use a default implementation, which assumes #power-domain-cells =
+	 * <1>, and that the DT cell contains a simple integer power domain ID.
+	 *
+	 * At present, the power domain API solely supports device-tree. If
+	 * this changes, other xxx_xlate() functions may be added to support
+	 * those other mechanisms.
+	 *
+	 * @power_domain:	The power domain struct to hold the
+	 *			translation result.
+	 * @args:		The power domain specifier values from device
+	 *			tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct power_domain *power_domain,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated power domain.
+	 *
+	 * The power domain core calls this function as the second step in
+	 * implementing a client's power_domain_get() call, following a
+	 * successful xxx_xlate() call.
+	 *
+	 * @power_domain:	The power domain to request; this has been
+	 *			filled in by a previous xxx_xlate() function
+	 *			call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct power_domain *power_domain);
+	/**
+	 * free - Free a previously requested power domain.
+	 *
+	 * This is the implementation of the client power_domain_free() API.
+	 *
+	 * @power_domain:	The power domain to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct power_domain *power_domain);
+	/**
+	 * on - Power on a power domain.
+	 *
+	 * @power_domain:	The power domain to turn on.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*on)(struct power_domain *power_domain);
+	/**
+	 * off - Power off a power domain.
+	 *
+	 * @power_domain:	The power domain to turn off.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*off)(struct power_domain *power_domain);
+};
+
+#endif
diff --git a/include/power-domain.h b/include/power-domain.h
new file mode 100644
index 0000000..1099979
--- /dev/null
+++ b/include/power-domain.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _POWER_DOMAIN_H
+#define _POWER_DOMAIN_H
+
+/**
+ * A power domain is a portion of an SoC or chip that is powered by a
+ * switchable source of power. In many cases, software has control over the
+ * power domain, and can turn the power source on or off. This is typically
+ * done to save power by powering off unused devices, or to enable software
+ * sequencing of initial powerup at boot. This API provides a means for
+ * drivers to turn power domains on and off.
+ *
+ * A driver that implements UCLASS_POWER_DOMAIN is a power domain controller or
+ * provider. A controller will often implement multiple separate power domains,
+ * since the hardware it manages often has this capability.
+ * power-domain-uclass.h describes the interface which power domain controllers
+ * must implement.
+ *
+ * Depending on the power domain controller hardware, changing the state of a
+ * power domain may require performing related operations on other resources.
+ * For example, some power domains may require certain clocks to be enabled
+ * whenever the power domain is powered on, or during the time when the power
+ * domain is transitioning state. These details are implementation-specific
+ * and should ideally be encapsulated entirely within the provider driver, or
+ * configured through mechanisms (e.g. device tree) that do not require client
+ * drivers to provide extra configuration information.
+ *
+ * Power domain consumers/clients are the drivers for HW modules within the
+ * power domain. This header file describes the API used by those drivers.
+ *
+ * In many cases, a single complex IO controller (e.g. a PCIe controller) will
+ * be the sole logic contained within a power domain. In such cases, it is
+ * logical for the relevant device driver to directly control that power
+ * domain. In other cases, multiple controllers, each with their own driver,
+ * may be contained in a single power domain. Any logic require to co-ordinate
+ * between drivers for these multiple controllers is beyond the scope of this
+ * API at present. Equally, this API does not define or implement any policy
+ * by which power domains are managed.
+ */
+
+struct udevice;
+
+/**
+ * struct power_domain - A handle to (allowing control of) a single power domain.
+ *
+ * Clients provide storage for power domain handles. The content of the
+ * structure is managed solely by the power domain API and power domain
+ * drivers. A power domain struct is initialized by "get"ing the power domain
+ * struct. The power domain struct is passed to all other power domain APIs to
+ * identify which power domain to operate upon.
+ *
+ * @dev: The device which implements the power domain.
+ * @id: The power domain ID within the provider.
+ *
+ * Currently, the power domain API assumes that a single integer ID is enough
+ * to identify and configure any power domain for any power domain provider. If
+ * this assumption becomes invalid in the future, the struct could be expanded
+ * to either (a) add more fields to allow power domain providers to store
+ * additional information, or (b) replace the id field with an opaque pointer,
+ * which the provider would dynamically allocate during its .of_xlate op, and
+ * process during is .request op. This may require the addition of an extra op
+ * to clean up the allocation.
+ */
+struct power_domain {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+/**
+ * power_domain_get - Get/request the power domain for a device.
+ *
+ * This looks up and requests a power domain. Each device is assumed to have
+ * a single (or, at least one) power domain associated with it somehow, and
+ * that domain, or the first/default domain. The mapping of client device to
+ * provider power domain may be via device-tree properties, board-provided
+ * mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @power_domain	A pointer to a power domain struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int power_domain_get(struct udevice *dev, struct power_domain *power_domain);
+
+/**
+ * power_domain_free - Free a previously requested power domain.
+ *
+ * @power_domain:	A power domain struct that was previously successfully
+ *		requested by power_domain_get().
+ * @return 0 if OK, or a negative error code.
+ */
+int power_domain_free(struct power_domain *power_domain);
+
+/**
+ * power_domain_on - Enable power to a power domain.
+ *
+ * @power_domain:	A power domain struct that was previously successfully
+ *		requested by power_domain_get().
+ * @return 0 if OK, or a negative error code.
+ */
+int power_domain_on(struct power_domain *power_domain);
+
+/**
+ * power_domain_off - Disable power ot a power domain.
+ *
+ * @power_domain:	A power domain struct that was previously successfully
+ *		requested by power_domain_get().
+ * @return 0 if OK, or a negative error code.
+ */
+int power_domain_off(struct power_domain *power_domain);
+
+#endif
diff --git a/test/dm/Makefile b/test/dm/Makefile
index cad3374..1885e17 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_LED) += led.o
 obj-$(CONFIG_DM_MAILBOX) += mailbox.o
 obj-$(CONFIG_DM_MMC) += mmc.o
 obj-$(CONFIG_DM_PCI) += pci.o
+obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
 obj-$(CONFIG_REMOTEPROC) += remoteproc.o
diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
new file mode 100644
index 0000000..379a8fa
--- /dev/null
+++ b/test/dm/power-domain.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <asm/power-domain.h>
+#include <test/ut.h>
+
+/* This must match the specifier for power-domains in the DT node */
+#define TEST_POWER_DOMAIN 2
+
+static int dm_test_power_domain(struct unit_test_state *uts)
+{
+	struct udevice *dev_power_domain;
+	struct udevice *dev_test;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN,
+					      "power-domain",
+					      &dev_power_domain));
+	ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0));
+	ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
+						  TEST_POWER_DOMAIN));
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test",
+					      &dev_test));
+	ut_assertok(sandbox_power_domain_test_get(dev_test));
+
+	ut_assertok(sandbox_power_domain_test_on(dev_test));
+	ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0));
+	ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
+						  TEST_POWER_DOMAIN));
+
+	ut_assertok(sandbox_power_domain_test_off(dev_test));
+	ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, 0));
+	ut_asserteq(0, sandbox_power_domain_query(dev_power_domain,
+						  TEST_POWER_DOMAIN));
+
+	ut_assertok(sandbox_power_domain_test_free(dev_test));
+
+	return 0;
+}
+DM_TEST(dm_test_power_domain, DM_TESTF_SCAN_FDT);
-- 
cgit v0.10.2


From 02ebd42cf19e523593d8e4e8f3d02083299fcdbb Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Tue, 19 Jul 2016 09:38:22 +0800
Subject: mmc: dw_mmc: reduce timeout detection cycle

It's no need to speed 10 seconds to wait the mmc device out from busy
status. 500 milliseconds enough.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index fe2147a..b58c282 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -195,7 +195,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 	int ret = 0, flags = 0, i;
-	unsigned int timeout = 100000;
+	unsigned int timeout = 500;
 	u32 retry = 100000;
 	u32 mask, ctrl;
 	ulong start = get_timer(0);
-- 
cgit v0.10.2


From 64992b782b95d05f205a987d2c2d8d44b1995796 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 20 Jul 2016 17:52:53 +0200
Subject: Fix build for mx7dsabresd (secure config)

After moving CONFIG_USB_EHCI_MX7 to Kconfig,
the flag must be set in defconfig for mx7dsabresd.
It is already for the not secure config, it is
missing in the secure configuration.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig
index 9e49004..0a3930e 100644
--- a/configs/mx7dsabresd_secure_defconfig
+++ b/configs/mx7dsabresd_secure_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MX7DSABRESD=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
@@ -28,6 +29,8 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-- 
cgit v0.10.2


From a5ad8ec9207cd30a6e1ddb5f4e334a295fc0d2e8 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 20 Jul 2016 17:53:56 +0200
Subject: mx6: wandboard: fix warning due to missing prototype

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 8340dd1..10cad3f 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -19,6 +19,7 @@
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/video.h>
+#include <asm/imx-common/sata.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
-- 
cgit v0.10.2


From d2c4c6bcfa5c9e36a6e00b1c7b997cd06eb09a6c Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 20 Jul 2016 17:54:07 +0200
Subject: pico-imx6ul: drop warning due to redefined

USB gadget configuration is set in defconfig and
must be removed from pico-imx6ul.h.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index a1e5f01..ca3c30b 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -54,13 +54,9 @@
 #define CONFIG_MXC_USB_FLAGS		0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET
 
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 #define CONFIG_USB_FUNCTION_DFU
@@ -68,14 +64,6 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"FSL"
-
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"FSL"
-
 #define CONFIG_DEFAULT_FDT_FILE		"imx6ul-pico-hobbit.dtb"
 
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
-- 
cgit v0.10.2


From 5c392017f5d9ff52bd822880abd81ca2843ffdca Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Fri, 22 Jul 2016 15:21:12 -0300
Subject: mx7dsabresd_secure_defconfig: Use CONFIG_ARMV7_BOOT_SEC_DEFAULT

There is no need for introducing MX7_SEC, as there is the
CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose.

Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of
MX7_SEC.

Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig
target.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig
index c6b38bc..1b7da5a 100644
--- a/arch/arm/imx-common/Kconfig
+++ b/arch/arm/imx-common/Kconfig
@@ -17,12 +17,3 @@ config IMX_BOOTAUX
 	depends on ARCH_MX7 || ARCH_MX6
 	help
 	  bootaux [addr] to boot auxiliary core.
-
-config MX7_SEC
-	bool "Support booting MX7 in secure mode"
-	depends on ARCH_MX7
-	help
-	  NXP kernel requires to boot MX7 in secure mode. Select
-	  this options if you want to boot a NXP kernel. In order
-	  to boot a mainline kernel this option needs to be
-	  unselected.
diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig
index 0a3930e..aa92a38 100644
--- a/configs/mx7dsabresd_secure_defconfig
+++ b/configs/mx7dsabresd_secure_defconfig
@@ -38,4 +38,4 @@ CONFIG_G_DNL_MANUFACTURER="FSL"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
-CONFIG_MX7_SEC=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
-- 
cgit v0.10.2


From 5a08ad6fdc43cc756ef1ebe046bbfd4290204fbe Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 17 Jun 2016 06:10:41 -0700
Subject: imx: ventana: add dt fixup for GW16082 irq mapping

The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI
bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned
in the reverse order according to the PCI spec.

If the TI bridge is found on the Ventana PCI bus, add device-tree nodes
according to bus enumeration explicitly defining the interrupt mapping
to override the default PCI mapping in the Linux kernel. This allows
the GW16082 to work with upstream kernels that support device-tree
irq parsing.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 70395ac..7d569ad 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -491,14 +491,54 @@ int imx6_pcie_toggle_reset(void)
  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  * properly and assert reset for 100ms.
  */
+#define MAX_PCI_DEVS	32
+struct pci_dev {
+	pci_dev_t devfn;
+	unsigned short vendor;
+	unsigned short device;
+	unsigned short class;
+	unsigned short busno; /* subbordinate busno */
+	struct pci_dev *ppar;
+};
+struct pci_dev pci_devs[MAX_PCI_DEVS];
+int pci_devno;
+int pci_bridgeno;
+
 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 			 unsigned short vendor, unsigned short device,
 			 unsigned short class)
 {
+	int i;
 	u32 dw;
+	struct pci_dev *pdev = &pci_devs[pci_devno++];
 
 	debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 	      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+
+	/* store array of devs for later use in device-tree fixup */
+	pdev->devfn = dev;
+	pdev->vendor = vendor;
+	pdev->device = device;
+	pdev->class = class;
+	pdev->ppar = NULL;
+	if (class == PCI_CLASS_BRIDGE_PCI)
+		pdev->busno = ++pci_bridgeno;
+	else
+		pdev->busno = 0;
+
+	/* fixup RC - it should be 00:00.0 not 00:01.0 */
+	if (PCI_BUS(dev) == 0)
+		pdev->devfn = 0;
+
+	/* find dev's parent */
+	for (i = 0; i < pci_devno; i++) {
+		if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
+			pdev->ppar = &pci_devs[i];
+			break;
+		}
+	}
+
+	/* assert downstream PERST# */
 	if (vendor == PCI_VENDOR_ID_PLX &&
 	    (device & 0xfff0) == 0x8600 &&
 	    PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
@@ -802,6 +842,189 @@ static inline void ft_delprop_path(void *blob, const char *path,
 	}
 }
 
+#if defined(CONFIG_CMD_PCI)
+#define PCI_ID(x) ( \
+	(PCI_BUS(x->devfn)<<16)| \
+	(PCI_DEV(x->devfn)<<11)| \
+	(PCI_FUNC(x->devfn)<<8) \
+	)
+#define PCIE_PATH	"/soc/pcie@0x01000000"
+int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
+{
+	uint32_t reg[5];
+	char node[32];
+	int np;
+
+	sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
+		PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
+
+	np = fdt_subnode_offset(blob, par, node);
+	if (np >= 0)
+		return np;
+	np = fdt_add_subnode(blob, par, node);
+	if (np < 0) {
+		printf("   %s failed: no space\n", __func__);
+		return np;
+	}
+
+	memset(reg, 0, sizeof(reg));
+	reg[0] = cpu_to_fdt32(PCI_ID(dev));
+	fdt_setprop(blob, np, "reg", reg, sizeof(reg));
+
+	return np;
+}
+
+/* build a path of nested PCI devs for all bridges passed through */
+int fdt_add_pci_path(void *blob, struct pci_dev *dev)
+{
+	struct pci_dev *bridges[MAX_PCI_DEVS];
+	int k, np;
+
+	/* build list of parents */
+	np = fdt_path_offset(blob, PCIE_PATH);
+	if (np < 0)
+		return np;
+
+	k = 0;
+	while (dev) {
+		bridges[k++] = dev;
+		dev = dev->ppar;
+	};
+
+	/* now add them the to DT in reverse order */
+	while (k--) {
+		np = fdt_add_pci_node(blob, np, bridges[k]);
+		if (np < 0)
+			break;
+	}
+
+	return np;
+}
+
+/*
+ * The GW16082 has a hardware errata errata such that it's
+ * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
+ * of this normal PCI interrupt swizzling will not work so we will
+ * provide an irq-map via device-tree.
+ */
+int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
+{
+	int len;
+	int host;
+	uint32_t imap_new[8*4*4];
+	const uint32_t *imap;
+	uint32_t irq[4];
+	uint32_t reg[4];
+	int i;
+
+	/* build irq-map based on host controllers map */
+	host = fdt_path_offset(blob, PCIE_PATH);
+	if (host < 0) {
+		printf("   %s failed: missing host\n", __func__);
+		return host;
+	}
+
+	/* use interrupt data from root complex's node */
+	imap = fdt_getprop(blob, host, "interrupt-map", &len);
+	if (!imap || len != 128) {
+		printf("   %s failed: invalid interrupt-map\n",
+		       __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	/* obtain irq's of host controller in pin order */
+	for (i = 0; i < 4; i++)
+		irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
+
+	/*
+	 * determine number of swizzles necessary:
+	 *   For each bridge we pass through we need to swizzle
+	 *   the number of the slot we are on.
+	 */
+	struct pci_dev *d;
+	int b;
+	b = 0;
+	d = dev->ppar;
+	while(d && d->ppar) {
+		b += PCI_DEV(d->devfn);
+		d = d->ppar;
+	}
+
+	/* create new irq mappings for slots12-15
+	 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
+	 * J3    AD28    12     INTD      INTA
+	 * J4    AD29    13     INTC      INTD
+	 * J5    AD30    14     INTB      INTC
+	 * J2    AD31    15     INTA      INTB
+	 */
+	for (i = 0; i < 4; i++) {
+		/* addr matches bus:dev:func */
+		u32 addr = dev->busno << 16 | (12+i) << 11;
+
+		/* default cells from root complex */
+		memcpy(&imap_new[i*32], imap, 128);
+		/* first cell is PCI device address (BDF) */
+		imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
+		imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
+		imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
+		imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
+		/* third cell is pin */
+		imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
+		imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
+		imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
+		imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
+		/* sixth cell is relative interrupt */
+		imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
+		imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
+		imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
+		imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
+	}
+	fdt_setprop(blob, np, "interrupt-map", imap_new,
+		    sizeof(imap_new));
+	reg[0] = cpu_to_fdt32(0xfff00);
+	reg[1] = 0;
+	reg[2] = 0;
+	reg[3] = cpu_to_fdt32(0x7);
+	fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
+	fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
+	fdt_setprop_string(blob, np, "device_type", "pci");
+	fdt_setprop_cell(blob, np, "#address-cells", 3);
+	fdt_setprop_cell(blob, np, "#size-cells", 2);
+	printf("   Added custom interrupt-map for GW16082\n");
+
+	return 0;
+}
+
+/*
+ * PCI DT nodes must be nested therefore if we need to apply a DT fixup
+ * we will walk the PCI bus and add bridge nodes up to the device receiving
+ * the fixup.
+ */
+void ft_board_pci_fixup(void *blob, bd_t *bd)
+{
+	int i, np;
+	struct pci_dev *dev;
+
+	for (i = 0; i < pci_devno; i++) {
+		dev = &pci_devs[i];
+
+		/*
+		 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
+		 * an EEPROM at i2c1-0x50.
+		 */
+		if ((dev->vendor == PCI_VENDOR_ID_TI) &&
+		    (dev->device == 0x8240) &&
+		    (i2c_set_bus_num(1) == 0) &&
+		    (i2c_probe(0x50) == 0))
+		{
+			np = fdt_add_pci_path(blob, dev);
+			if (np > 0)
+				fdt_fixup_gw16082(blob, np, dev);
+		}
+	}
+}
+#endif /* if defined(CONFIG_CMD_PCI) */
+
 /*
  * called prior to booting kernel or by 'fdt boardsetup' command
  *
@@ -976,6 +1199,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 				"no-1-8-v");
 	}
 
+#if defined(CONFIG_CMD_PCI)
+	if (!getenv("nopcifixup"))
+		ft_board_pci_fixup(blob, bd);
+#endif
+
 	/*
 	 * Peripheral Config:
 	 *  remove nodes by alias path if EEPROM config tells us the
-- 
cgit v0.10.2


From 5c34c2abb86a8e74234390300e4c852603b11621 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 17 Jun 2016 06:10:42 -0700
Subject: imx: ventana: add dt fixup for eth1 mac-address

Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to
be placed in a DT node in order for the mainline linux driver to obtain it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 7d569ad..b3390a1 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -995,6 +995,32 @@ int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 	return 0;
 }
 
+/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
+int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
+{
+	char *tmp, *end;
+	char mac[16];
+	unsigned char mac_addr[6];
+	int j;
+
+	sprintf(mac, "eth1addr");
+	tmp = getenv(mac);
+	if (tmp) {
+		for (j = 0; j < 6; j++) {
+			mac_addr[j] = tmp ?
+				      simple_strtoul(tmp, &end,16) : 0;
+			if (tmp)
+				tmp = (*end) ? end+1 : end;
+		}
+		fdt_setprop(blob, np, "local-mac-address", mac_addr,
+			    sizeof(mac_addr));
+		printf("   Added mac addr for eth1\n");
+		return 0;
+	}
+
+	return -1;
+}
+
 /*
  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  * we will walk the PCI bus and add bridge nodes up to the device receiving
@@ -1021,6 +1047,15 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
 			if (np > 0)
 				fdt_fixup_gw16082(blob, np, dev);
 		}
+
+		/* ethernet1 mac address */
+		else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
+		         (dev->device == 0x4380))
+		{
+			np = fdt_add_pci_path(blob, dev);
+			if (np > 0)
+				fdt_fixup_sky2(blob, np, dev);
+		}
 	}
 }
 #endif /* if defined(CONFIG_CMD_PCI) */
-- 
cgit v0.10.2


From ec21aee653a32a72909450c2e66b26668d5f3242 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 17 Jun 2016 06:20:25 -0700
Subject: pci: allow disabling of pci init/enum via env

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4b73a0f..6b36c18 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -458,6 +458,10 @@ void pci_init(void)
 {
 	hose_head = NULL;
 
+	/* allow env to disable pci init/enum */
+	if (getenv("pcidisable") != NULL)
+		return;
+
 	/* now call board specific pci_init()... */
 	pci_init_board();
 }
-- 
cgit v0.10.2


From f4416579d31d884305e383f7370ee2262c0f8a7d Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 17 Jun 2016 06:20:26 -0700
Subject: imx: ventana: default pci to disabled

The IMX6 PCIe host controller does not have a proper reset and as such there
are several issues that can arise if PCI is enabled in the bootloader follwed
by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices.

For now, the best approach seems to default to disabling PCI by defaulting
pciedisable=1. This can be overridden by the user if they need PCI in the
bootloader, for example:
 - GW552x needing ethernet access in bootloader
 - GW16082 expansion board needing a device-tree fixup for irq mapping

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 982ddba..4acfca6 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -274,6 +274,7 @@
 	"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
 
 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"pcidisable=1\0" \
 	"usb_pgood_delay=2000\0" \
 	"console=ttymxc1\0" \
 	"bootdevs=usb mmc sata flash\0" \
-- 
cgit v0.10.2


From 6eab98a02eae688a3d37a2a1806e92e858d08327 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 29 Jun 2016 08:58:00 -0700
Subject: imx: ventana: re-enable late board info display

3b1f681131149b5f62602f582a7e60b0185a2a49 caused a regression that removes
board info dispaly for Gateworks Ventana boards because it made the invalid
assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as
CONFIG_DISPLAY_BOARDINFO.

Ventana needs to call show_board_info in late init because we need to have
the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE
to allow that to happen.

Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 4acfca6..343f3c5 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -33,6 +33,8 @@
 #include "imx6_spl.h"                  /* common IMX6 SPL configuration */
 #include "mx6_common.h"
 #undef CONFIG_SPL_EXT_SUPPORT
+#undef CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 
 #define CONFIG_MACH_TYPE	4520   /* Gateworks Ventana Platform */
 
-- 
cgit v0.10.2


From e49621b357b1ea86170eacd3de8f03af422743e6 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 15 Jul 2016 07:14:22 -0700
Subject: imx: ventana: make RS232 enable board specific

Not all Ventana boards have an RS232 transceiver, make it board specific.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 929dde9..9546f31 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -132,14 +132,14 @@ void setup_ventana_i2c(void)
 
 /* common to add baseboards */
 static iomux_v3_cfg_t const gw_gpio_pads[] = {
-	/* RS232_EN# */
-	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* SD3_VSELECT */
 	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 };
 
 /* prototype */
 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* PANLEDG# */
 	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 	/* PANLEDR# */
@@ -183,6 +183,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* MSATA_EN */
 	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* PANLEDG# */
@@ -214,6 +216,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* MSATA_EN */
 	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* CAN_STBY */
@@ -245,6 +249,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* MSATA_EN */
 	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 	/* CAN_STBY */
@@ -468,6 +474,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.usb_sel = IMX_GPIO_NR(1, 2),
 		.wdis = IMX_GPIO_NR(7, 12),
 		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
 	},
 
 	/* GW53xx */
@@ -513,6 +520,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.vidin_en = IMX_GPIO_NR(3, 31),
 		.wdis = IMX_GPIO_NR(7, 12),
 		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
 	},
 
 	/* GW54xx */
@@ -560,6 +568,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.pcie_sson = IMX_GPIO_NR(1, 20),
 		.wdis = IMX_GPIO_NR(5, 17),
 		.msata_en = GP_MSATA_SEL,
+		.rs232_en = GP_RS232_EN,
 	},
 
 	/* GW551x */
@@ -682,10 +691,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 	gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
 	gpio_direction_output(GP_USB_OTG_PWR, 0);
 
-	/* RS232_EN# */
-	gpio_request(GP_RS232_EN, "rs232_en");
-	gpio_direction_output(GP_RS232_EN, 0);
-
 	if (board >= GW_UNKNOWN)
 		return;
 
@@ -693,6 +698,12 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 	imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
 					 gpio_cfg[board].num_pads);
 
+	/* RS232_EN# */
+	if (gpio_cfg[board].rs232_en) {
+		gpio_request(gpio_cfg[board].rs232_en, "rs232_en");
+		gpio_direction_output(gpio_cfg[board].rs232_en, 0);
+	}
+
 	/* GW522x Uses GPIO3_IO23 for PCIE_RST# */
 	if (board == GW52xx && info->model[4] == '2')
 		gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
@@ -788,7 +799,10 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 		return;
 
 	/* RS232_EN# */
-	gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
+	if (gpio_cfg[board].rs232_en) {
+		gpio_direction_output(gpio_cfg[board].rs232_en,
+				      (hwconfig("rs232")) ? 0 : 1);
+	}
 
 	/* MSATA Enable */
 	if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
@@ -851,8 +865,10 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 			printf("MSATA: %s\n", (hwconfig("msata") ?
 			       "enabled" : "disabled"));
 		}
-		printf("RS232: %s\n", (hwconfig("rs232")) ?
-		       "enabled" : "disabled");
+		if (gpio_cfg[board].rs232_en) {
+			printf("RS232: %s\n", (hwconfig("rs232")) ?
+			       "enabled" : "disabled");
+		}
 	}
 }
 
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index d037767..389d3aa 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -78,6 +78,8 @@ struct ventana {
 	int usb_sel;
 	int wdis;
 	int msata_en;
+	int rs232_en;
+	/* various features */
 	bool usd_vsel;
 };
 
-- 
cgit v0.10.2


From 1800ffa83e3fe4a3178606a2254d902503b7c80d Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 15 Jul 2016 07:14:23 -0700
Subject: imx: ventana: make number of digital I/O's dynamic

Replace the static list of board-specific digital I/O's with a dynamic list.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 9546f31..59e3ff8 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -338,6 +338,183 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
 	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 };
 
+/* Digital I/O */
+struct dio_cfg gw51xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+		IMX_GPIO_NR(1, 18),
+		{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+		4
+	},
+};
+
+struct dio_cfg gw52xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw53xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw54xx_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
+		IMX_GPIO_NR(1, 9),
+		{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
+		1
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
+		IMX_GPIO_NR(2, 9),
+		{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
+		IMX_GPIO_NR(2, 10),
+		{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
+		4
+	},
+};
+
+struct dio_cfg gw551x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+};
+
+struct dio_cfg gw552x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw553x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+		IMX_GPIO_NR(1, 18),
+		{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+		4
+	},
+};
 
 /*
  * Board Specific GPIO
@@ -347,33 +524,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw54xx_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
-				IMX_GPIO_NR(1, 9),
-				{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
-				1
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
-				IMX_GPIO_NR(2, 9),
-				{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
-				IMX_GPIO_NR(2, 10),
-				{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
-				4
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw54xx_dio,
+		.dio_num = ARRAY_SIZE(gw54xx_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 6),
 			IMX_GPIO_NR(4, 10),
@@ -391,33 +543,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw51xx_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
-				IMX_GPIO_NR(1, 16),
-				{ 0, 0 },
-				0
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
-				IMX_GPIO_NR(1, 17),
-				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
-				IMX_GPIO_NR(1, 18),
-				{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
-				4
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw51xx_dio,
+		.dio_num = ARRAY_SIZE(gw51xx_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 6),
 			IMX_GPIO_NR(4, 10),
@@ -434,33 +561,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw52xx_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
-				IMX_GPIO_NR(1, 16),
-				{ 0, 0 },
-				0
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
-				IMX_GPIO_NR(1, 17),
-				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
-				IMX_GPIO_NR(1, 20),
-				{ 0, 0 },
-				0
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw52xx_dio,
+		.dio_num = ARRAY_SIZE(gw52xx_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 6),
 			IMX_GPIO_NR(4, 7),
@@ -481,33 +583,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw53xx_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
-				IMX_GPIO_NR(1, 16),
-				{ 0, 0 },
-				0
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
-				IMX_GPIO_NR(1, 17),
-				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
-				IMX_GPIO_NR(1, 20),
-				{ 0, 0 },
-				0
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw53xx_dio,
+		.dio_num = ARRAY_SIZE(gw53xx_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 6),
 			IMX_GPIO_NR(4, 7),
@@ -527,33 +604,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw54xx_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
-				IMX_GPIO_NR(1, 9),
-				{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
-				1
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
-				IMX_GPIO_NR(2, 9),
-				{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
-				IMX_GPIO_NR(2, 10),
-				{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
-				4
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw54xx_dio,
+		.dio_num = ARRAY_SIZE(gw54xx_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 6),
 			IMX_GPIO_NR(4, 7),
@@ -575,21 +627,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw551x_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
-				IMX_GPIO_NR(1, 17),
-				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
-				3
-			},
-		},
-		.num_gpios = 2,
+		.dio_cfg = gw551x_dio,
+		.dio_num = ARRAY_SIZE(gw551x_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 7),
 		},
@@ -601,33 +640,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw552x_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
-				IMX_GPIO_NR(1, 16),
-				{ 0, 0 },
-				0
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
-				IMX_GPIO_NR(1, 17),
-				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
-				IMX_GPIO_NR(1, 20),
-				{ 0, 0 },
-				0
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw552x_dio,
+		.dio_num = ARRAY_SIZE(gw552x_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 6),
 			IMX_GPIO_NR(4, 7),
@@ -643,33 +657,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 	{
 		.gpio_pads = gw553x_gpio_pads,
 		.num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
-		.dio_cfg = {
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
-				IMX_GPIO_NR(1, 16),
-				{ 0, 0 },
-				0
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
-				IMX_GPIO_NR(1, 19),
-				{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
-				2
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
-				IMX_GPIO_NR(1, 17),
-				{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
-				3
-			},
-			{
-				{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
-				IMX_GPIO_NR(1, 18),
-				{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
-				4
-			},
-		},
-		.num_gpios = 4,
+		.dio_cfg = gw553x_dio,
+		.dio_num = ARRAY_SIZE(gw553x_dio),
 		.leds = {
 			IMX_GPIO_NR(4, 10),
 			IMX_GPIO_NR(4, 11),
@@ -820,7 +809,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 	 * Configure DIO pinmux/padctl registers
 	 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
 	 */
-	for (i = 0; i < gpio_cfg[board].num_gpios; i++) {
+	for (i = 0; i < gpio_cfg[board].dio_num; i++) {
 		struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
 		iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
 		unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 389d3aa..3d7aff1 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -48,8 +48,8 @@
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
 /*
- * each baseboard has 4 user configurable Digital IO lines which can
- * be pinmuxed as a GPIO or in some cases a PWM
+ * each baseboard has an optional set user configurable Digital IO lines which
+ * can be pinmuxed as a GPIO or in some cases a PWM
  */
 struct dio_cfg {
 	iomux_v3_cfg_t gpio_padmux[2];
@@ -63,8 +63,8 @@ struct ventana {
 	iomux_v3_cfg_t const *gpio_pads;
 	int num_pads;
 	/* DIO pinmux/val */
-	struct dio_cfg dio_cfg[4];
-	int num_gpios;
+	struct dio_cfg *dio_cfg;
+	int dio_num;
 	/* various gpios (0 if non-existent) */
 	int leds[3];
 	int pcie_rst;
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index b3390a1..930cec8 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1209,7 +1209,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	}
 
 	/* Configure DIO */
-	for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
+	for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 		struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
 		char arg[10];
 
-- 
cgit v0.10.2


From e86b7adfa3cfe8d87ecb67bc0f02789c51293f51 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 15 Jul 2016 07:14:24 -0700
Subject: imx: ventana: add extra DIO's for GW5520

The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana
product family.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 59e3ff8..4065c56 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -487,6 +487,42 @@ struct dio_cfg gw552x_dio[] = {
 		{ 0, 0 },
 		0
 	},
+	{
+		{IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
+		IMX_GPIO_NR(5, 18),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
+		IMX_GPIO_NR(5, 20),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
+		IMX_GPIO_NR(5, 21),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
+		IMX_GPIO_NR(5, 22),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
+		IMX_GPIO_NR(5, 23),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
+		IMX_GPIO_NR(5, 25),
+		{ 0, 0 },
+		0
+	},
 };
 
 struct dio_cfg gw553x_dio[] = {
-- 
cgit v0.10.2


From 5911c0924f403561d8f1f2f437fd9a6efc5ad82a Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 15 Jul 2016 07:14:25 -0700
Subject: imx: ventana: make hwconfig initialize based on board configuration

The hwconfig env var allows user to control hardware specific configuration
of board specific features but not all Ventana boards have the same features.

We will use the magic default value of "_UNKNOWN_" to signify that the
bootloader should create this based on detected board model.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 930cec8..588ea85 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -700,13 +700,14 @@ static const struct boot_mode board_boot_modes[] = {
 int misc_init_r(void)
 {
 	struct ventana_board_info *info = &ventana_info;
+	char buf[256];
+	int i;
 
 	/* set env vars based on EEPROM data */
 	if (ventana_info.model[0]) {
 		char str[16], fdt[36];
 		char *p;
 		const char *cputype = "";
-		int i;
 
 		/*
 		 * FDT name will be prefixed with CPU type.  Three versions
@@ -769,6 +770,19 @@ int misc_init_r(void)
 		setenv("mem_mb", str);
 	}
 
+	/* Set a non-initialized hwconfig based on board configuration */
+	if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
+		sprintf(buf, "hwconfig=");
+		if (gpio_cfg[board_type].rs232_en)
+			strcat(buf, "rs232;");
+		for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
+			char buf1[32];
+			sprintf(buf1, "dio%d:mode=gpio;", i);
+			if (strlen(buf) + strlen(buf1) < sizeof(buf))
+				strcat(buf, buf1);
+		}
+		setenv("hwconfig", buf);
+	}
 
 	/* setup baseboard specific GPIO based on board and env */
 	setup_board_gpio(board_type, info);
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 343f3c5..1bd13fe 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -271,16 +271,13 @@
 /* Environment */
 #define CONFIG_IPADDR             192.168.1.1
 #define CONFIG_SERVERIP           192.168.1.146
-#define HWCONFIG_DEFAULT \
-	"hwconfig=rs232;" \
-	"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
 
 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
 	"pcidisable=1\0" \
 	"usb_pgood_delay=2000\0" \
 	"console=ttymxc1\0" \
 	"bootdevs=usb mmc sata flash\0" \
-	HWCONFIG_DEFAULT \
+	"hwconfig=_UNKNOWN_\0" \
 	"video=\0" \
 	\
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
-- 
cgit v0.10.2


From 966fe02ee64106721c7301641e86e5784a5f47b2 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 15 Jul 2016 07:16:28 -0700
Subject: imx: ventana: refactor board-specific dt fixups (no functional
 change)

Re-factor the board-specific dt fixups so that they are easier to follow
and extend in the future:
 - use defines for DT paths
 - use switch/case per board
 - order models numerically

There is no functional change in the code

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 588ea85..bb792c2 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1083,6 +1083,9 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
  *  - board (full model from EEPROM)
  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
  */
+#define UART1_PATH	"/soc/aips-bus@02100000/serial@021ec000"
+#define WDOG1_PATH	"/soc/aips-bus@02000000/wdog@020bc000"
+#define GPIO3_PATH	"/soc/aips-bus@02000000/gpio@020a4000"
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	struct ventana_board_info *info = &ventana_info;
@@ -1136,90 +1139,107 @@ int ft_board_setup(void *blob, bd_t *bd)
 	ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
 
 	/*
-	 * disable serial2 node for GW54xx for compatibility with older
-	 * 3.10.x kernel that improperly had this node enabled in the DT
+	 * Board model specific fixups
 	 */
-	if (board_type == GW54xx) {
-		i = fdt_path_offset(blob,
-				    "/soc/aips-bus@02100000/serial@021ec000");
-		if (i)
-			fdt_del_node(blob, i);
-	}
-
-	/*
-	 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
-	 * errata causing wdog timer to be unreliable.
-	 */
-	if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
-		i = fdt_path_offset(blob,
-				    "/soc/aips-bus@02000000/wdog@020bc000");
-		if (i)
-			fdt_status_disabled(blob, i);
-	}
-
-	/* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
-	else if (board_type == GW52xx && info->model[4] == '2') {
-		u32 handle = 0;
-		u32 *range = NULL;
+	switch (board_type) {
+	case GW51xx:
+		/*
+		 * disable wdog node for GW51xx-A/B to work around
+		 * errata causing wdog timer to be unreliable.
+		 */
+		if (rev >= 'A' && rev < 'C') {
+			i = fdt_path_offset(blob, WDOG1_PATH);
+			if (i)
+				fdt_status_disabled(blob, i);
+		}
+		break;
 
-		i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
-		if (i)
-			range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
-						   NULL);
+	case GW52xx:
+		/* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
+		if (info->model[4] == '2') {
+			u32 handle = 0;
+			u32 *range = NULL;
 
-		if (range) {
-			i = fdt_path_offset(blob,
-					    "/soc/aips-bus@02000000/gpio@020a4000");
+			i = fdt_node_offset_by_compatible(blob, -1,
+							  "fsl,imx6q-pcie");
 			if (i)
-				handle = fdt_get_phandle(blob, i);
-			if (handle) {
-				range[0] = cpu_to_fdt32(handle);
-				range[1] = cpu_to_fdt32(23);
+				range = (u32 *)fdt_getprop(blob, i,
+							   "reset-gpio", NULL);
+
+			if (range) {
+				i = fdt_path_offset(blob, GPIO3_PATH);
+				if (i)
+					handle = fdt_get_phandle(blob, i);
+				if (handle) {
+					range[0] = cpu_to_fdt32(handle);
+					range[1] = cpu_to_fdt32(23);
+				}
 			}
-		}
 
-		/* these have broken usd_vsel */
-		if (strstr((const char *)info->model, "SP318-B") ||
-		    strstr((const char *)info->model, "SP331-B"))
-			gpio_cfg[board_type].usd_vsel = 0;
-	}
+			/* these have broken usd_vsel */
+			if (strstr((const char *)info->model, "SP318-B") ||
+			    strstr((const char *)info->model, "SP331-B"))
+				gpio_cfg[board_type].usd_vsel = 0;
+		}
+		break;
 
-	/*
-	 * isolate CSI0_DATA_EN for GW551x below revB to work around
-	 * errata causing non functional digital video in (it is not hooked up)
-	 */
-	else if (board_type == GW551x && rev == 'A') {
-		u32 *range = NULL;
-		int len;
-		const u32 *handle = NULL;
+	case GW53xx:
+		break;
 
-		i = fdt_node_offset_by_compatible(blob, -1,
-						  "fsl,imx-tda1997x-video");
-		if (i)
-			handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
-		if (handle)
-			i = fdt_node_offset_by_phandle(blob,
-						       fdt32_to_cpu(*handle));
+	case GW54xx:
+		/*
+		 * disable serial2 node for GW54xx for compatibility with older
+		 * 3.10.x kernel that improperly had this node enabled in the DT
+		 */
+		i = fdt_path_offset(blob, UART1_PATH);
 		if (i)
-			range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
-		if (range) {
-			len /= sizeof(u32);
-			for (i = 0; i < len; i += 6) {
-				u32 mux_reg = fdt32_to_cpu(range[i+0]);
-				u32 conf_reg = fdt32_to_cpu(range[i+1]);
-				/* mux PAD_CSI0_DATA_EN to GPIO */
-				if (is_cpu_type(MXC_CPU_MX6Q) &&
-				    mux_reg == 0x260 && conf_reg == 0x630)
-					range[i+3] = cpu_to_fdt32(0x5);
-				else if (!is_cpu_type(MXC_CPU_MX6Q) &&
-				    mux_reg == 0x08c && conf_reg == 0x3a0)
-					range[i+3] = cpu_to_fdt32(0x5);
+			fdt_del_node(blob, i);
+		break;
+
+	case GW551x:
+		/*
+		 * isolate CSI0_DATA_EN for GW551x-A to work around errata
+		 * causing non functional digital video in (it is not hooked up)
+		 */
+		if (rev == 'A') {
+			u32 *range = NULL;
+			int len;
+			const u32 *handle = NULL;
+
+			i = fdt_node_offset_by_compatible(blob, -1,
+						"fsl,imx-tda1997x-video");
+			if (i)
+				handle = fdt_getprop(blob, i, "pinctrl-0",
+						     NULL);
+			if (handle)
+				i = fdt_node_offset_by_phandle(blob,
+							fdt32_to_cpu(*handle));
+			if (i)
+				range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
+							   &len);
+			if (range) {
+				len /= sizeof(u32);
+				for (i = 0; i < len; i += 6) {
+					u32 mux_reg = fdt32_to_cpu(range[i+0]);
+					u32 conf_reg = fdt32_to_cpu(range[i+1]);
+					/* mux PAD_CSI0_DATA_EN to GPIO */
+					if (is_cpu_type(MXC_CPU_MX6Q) &&
+					    mux_reg == 0x260 &&
+					    conf_reg == 0x630)
+						range[i+3] = cpu_to_fdt32(0x5);
+					else if (!is_cpu_type(MXC_CPU_MX6Q) &&
+						 mux_reg == 0x08c &&
+						 conf_reg == 0x3a0)
+						range[i+3] = cpu_to_fdt32(0x5);
+				}
+				fdt_setprop_inplace(blob, i, "fsl,pins", range,
+						    len);
 			}
-			fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
-		}
 
-		/* set BT656 video format */
-		ft_sethdmiinfmt(blob, "yuv422bt656");
+			/* set BT656 video format */
+			ft_sethdmiinfmt(blob, "yuv422bt656");
+		}
+		break;
 	}
 
 	/* Configure DIO */
-- 
cgit v0.10.2


From a5bfb4ff9ee5f97adf91af8fba148b3fae48acde Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 15 Jul 2016 07:16:29 -0700
Subject: imx: ventana: add dt fixup for watchdog external reset

Added removal of the fsl,ext-reset-output property in the wdog node for board
revisions that pre-date the addition of the external watchdog reset signal.

This property is a recent addition to mainline linux kernel in order to
specify that the IMX watchdog external reset should be used instead of the
internal chip-level reset.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index bb792c2..5d871ce 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1085,6 +1085,7 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
  */
 #define UART1_PATH	"/soc/aips-bus@02100000/serial@021ec000"
 #define WDOG1_PATH	"/soc/aips-bus@02000000/wdog@020bc000"
+#define WDOG2_PATH	"/soc/aips-bus@02000000/wdog@020c0000"
 #define GPIO3_PATH	"/soc/aips-bus@02000000/gpio@020a4000"
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -1152,6 +1153,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 			if (i)
 				fdt_status_disabled(blob, i);
 		}
+
+		/* GW51xx-E adds WDOG1_B external reset */
+		if (rev < 'E')
+			ft_delprop_path(blob, WDOG1_PATH,
+					"fsl,ext-reset-output");
 		break;
 
 	case GW52xx:
@@ -1180,10 +1186,24 @@ int ft_board_setup(void *blob, bd_t *bd)
 			if (strstr((const char *)info->model, "SP318-B") ||
 			    strstr((const char *)info->model, "SP331-B"))
 				gpio_cfg[board_type].usd_vsel = 0;
+
+			/* GW520x-E adds WDOG1_B external reset */
+			if (info->model[4] == '0' && rev < 'E')
+				ft_delprop_path(blob, WDOG1_PATH,
+						"fsl,ext-reset-output");
+
+			/* GW522x-B adds WDOG1_B external reset */
+			if (info->model[4] == '2' && rev < 'B')
+				ft_delprop_path(blob, WDOG1_PATH,
+						"fsl,ext-reset-output");
 		}
 		break;
 
 	case GW53xx:
+		/* GW53xx-E adds WDOG1_B external reset */
+		if (rev < 'E')
+			ft_delprop_path(blob, WDOG1_PATH,
+					"fsl,ext-reset-output");
 		break;
 
 	case GW54xx:
@@ -1194,6 +1214,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 		i = fdt_path_offset(blob, UART1_PATH);
 		if (i)
 			fdt_del_node(blob, i);
+
+		/* GW54xx-E adds WDOG2_B external reset */
+		if (rev < 'E')
+			ft_delprop_path(blob, WDOG2_PATH,
+					"fsl,ext-reset-output");
 		break;
 
 	case GW551x:
@@ -1239,6 +1264,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 			/* set BT656 video format */
 			ft_sethdmiinfmt(blob, "yuv422bt656");
 		}
+
+		/* GW551x-C adds WDOG1_B external reset */
+		if (rev < 'C')
+			ft_delprop_path(blob, WDOG1_PATH,
+					"fsl,ext-reset-output");
 		break;
 	}
 
-- 
cgit v0.10.2


From 98b040c9889bc23a7a0007853d52ebb07e28de76 Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Fri, 22 Jul 2016 09:11:02 -0300
Subject: wandboard: Replace is_cpu_type() for macro

It's not necessary to use the is_cpu_type function, there is a macro in
sys_proto.h already implemented.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 10cad3f..1de1e0b 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -391,7 +391,7 @@ int board_late_init(void)
 #endif
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
 	else
 		setenv("board_rev", "MX6DL");
@@ -410,7 +410,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	if (is_mx6dq())
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-- 
cgit v0.10.2


From 4a2f9014e82e73caeb09b39e4bf02f1460279882 Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Fri, 22 Jul 2016 09:11:30 -0300
Subject: mx6cuboxi: Replace is_mx6q() for macro

It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index bcc9729..cafa348 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -367,14 +367,6 @@ int checkboard(void)
 	return 0;
 }
 
-static bool is_mx6q(void)
-{
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
-		return true;
-	else
-		return false;
-}
-
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -383,7 +375,7 @@ int board_late_init(void)
 	else
 		setenv("board_name", "CUBOXI");
 
-	if (is_mx6q())
+	if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
 	else
 		setenv("board_rev", "MX6DL");
@@ -615,7 +607,7 @@ static void spl_dram_init(int width)
 		.ddr_type = DDR_TYPE_DDR3,
 	};
 
-	if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
+	if (is_mx6dq())
 		mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 	else
 		mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
-- 
cgit v0.10.2


From 68c276019a6ede6dbb099af7e3e2756579e3b23e Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Fri, 22 Jul 2016 09:12:12 -0300
Subject: cgtqmx6eval: Replace is_mx6q() for macro

It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 225de7c..3fbd3d2 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -678,14 +678,6 @@ int overwrite_console(void)
 	return 1;
 }
 
-static bool is_mx6q(void)
-{
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
-		return true;
-	else
-		return false;
-}
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -703,7 +695,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 
-	if (is_mx6q())
+	if (is_mx6dq())
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
@@ -760,7 +752,7 @@ int misc_init_r(void)
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (is_mx6q())
+	if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
 	else
 		setenv("board_rev", "MX6DL");
@@ -1053,7 +1045,7 @@ static void spl_dram_init(int width)
 		return;
 	}
 
-	if (is_mx6q()) {
+	if (is_mx6dq()) {
 		mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 		mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
 	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
-- 
cgit v0.10.2


From ae440ab02d31179a5a4b23e7411fe1baf052e816 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Wed, 20 Jul 2016 21:27:49 -0700
Subject: colibri_imx7: add Colibri iMX7S/iMX7D module support

This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index dd51384..5fdc8dd 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -27,12 +27,19 @@ config TARGET_WARP7
 	select DM
 	select DM_THERMAL
 
+config TARGET_COLIBRI_IMX7
+	bool "Support Colibri iMX7S/iMX7D modules"
+	select DM
+	select DM_SERIAL
+	select DM_THERMAL
+
 endchoice
 
 config SYS_SOC
 	default "mx7"
 
 source "board/freescale/mx7dsabresd/Kconfig"
+source "board/toradex/colibri_imx7/Kconfig"
 source "board/warp7/Kconfig"
 
 endif
diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig
new file mode 100644
index 0000000..7bba26b
--- /dev/null
+++ b/board/toradex/colibri_imx7/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_COLIBRI_IMX7
+
+config SYS_BOARD
+	default "colibri_imx7"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "colibri_imx7"
+
+config COLIBRI_IMX7_EXT_PHYCLK
+	bool "External oscillator for Ethernet PHY clock provided"
+	help
+	  Select this if your module provides a external Ethernet PHY
+	  clock source.
+	default y
+
+
+endif
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
new file mode 100644
index 0000000..5ffb241
--- /dev/null
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -0,0 +1,6 @@
+Colibri iMX7
+M:	Stefan Agner <stefan.agner@toradex.com>
+S:	Maintained
+F:	board/toradex/colibri_imx7/
+F:	include/configs/colibri_imx7.h
+F:	configs/colibri_imx7_defconfig
diff --git a/board/toradex/colibri_imx7/Makefile b/board/toradex/colibri_imx7/Makefile
new file mode 100644
index 0000000..ea597de
--- /dev/null
+++ b/board/toradex/colibri_imx7/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Toradex AG
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := colibri_imx7.o
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
new file mode 100644
index 0000000..8eedd65
--- /dev/null
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2016 Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
+		.gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
+		.gp = IMX_GPIO_NR(1, 4),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
+		.gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
+		.gp = IMX_GPIO_NR(1, 5),
+	},
+};
+/* I2C4 for Colibri I2C */
+static struct i2c_pads_info i2c_pad_info4 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
+		.gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
+		.gp = IMX_GPIO_NR(7, 8),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
+		.gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
+		.gp = IMX_GPIO_NR(7, 9),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	/* NAND_USDHC_BUS_CLK is set in rom */
+	set_clk_nand();
+}
+#endif
+
+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight On */
+	MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Backlight PWM<A> (multiplexed pin) */
+	MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
+#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
+
+static int setup_lcd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
+
+	/* Set BL_ON */
+	gpio_request(GPIO_BL_ON, "BL_ON");
+	gpio_direction_output(GPIO_BL_ON, 1);
+
+	/* Set PWM<A> to full brightness (assuming inversed polarity) */
+	gpio_request(GPIO_PWM_A, "PWM<A>");
+	gpio_direction_output(GPIO_PWM_A, 0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
+	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
+#else
+	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+#endif
+	MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 0)
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/* USDHC1 is mmc0 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	setup_iomux_fec();
+
+	ret = fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
+	/*
+	 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
+	 * and output it on the pin
+	 */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
+#else
+	/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
+#endif
+
+	return set_clk_enet(ENET_50MHz);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
+	{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
+	{NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Model: Toradex Colibri iMX7%c\n",
+	       is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+static iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		if (is_cpu_type(MXC_CPU_MX7S))
+			return -ENODEV;
+
+		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+						 ARRAY_SIZE(usb_otg2_pads));
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+#endif
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
+	.use_dte = true,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+	.name = "serial_mxc",
+	.platdata = &mxc_serial_plat,
+};
diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg
new file mode 100644
index 0000000..d891e82
--- /dev/null
+++ b/board/toradex/colibri_imx7/imximage.cfg
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *               2015 Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* IOMUXC_GPR_GPR1 */
+DATA 4 0x30340004 0x4F400005
+
+/* DDR3L */
+/* assuming MEMC_FREQ_RATIO = 2 */
+/* SRC_DDRC_RCR */
+DATA 4 0x30391000 0x00000002
+/* DDRC_MSTR */
+DATA 4 0x307a0000 0x01040001
+/* DDRC_DFIUPD0 */
+DATA 4 0x307a01a0 0x80400003
+/* DDRC_DFIUPD1 */
+DATA 4 0x307a01a4 0x00100020
+/* DDRC_DFIUPD2 */
+DATA 4 0x307a01a8 0x80100004
+/* DDRC_RFSHTMG */
+DATA 4 0x307a0064 0x00400045
+/* DDRC_MP_PCTRL_0 */
+DATA 4 0x307a0490 0x00000001
+/* DDRC_INIT0 */
+DATA 4 0x307a00d0 0x00020083
+/* DDRC_INIT1 */
+DATA 4 0x307a00d4 0x00690000
+/* DDRC_INIT3 MR0/MR1 */
+DATA 4 0x307a00dc 0x09300004
+/* DDRC_INIT4 MR2/MR3 */
+DATA 4 0x307a00e0 0x04480000
+/* DDRC_INIT5 */
+DATA 4 0x307a00e4 0x00100004
+/* DDRC_RANKCTL */
+DATA 4 0x307a00f4 0x0000033f
+/* DDRC_DRAMTMG0 */
+DATA 4 0x307a0100 0x090b090a
+/* DDRC_DRAMTMG1 */
+DATA 4 0x307a0104 0x000d020d
+/* DDRC_DRAMTMG2 */
+DATA 4 0x307a0108 0x03040307
+/* DDRC_DRAMTMG3 */
+DATA 4 0x307a010c 0x00002006
+/* DDRC_DRAMTMG4 */
+DATA 4 0x307a0110 0x04020205
+/* DDRC_DRAMTMG5 */
+DATA 4 0x307a0114 0x03030202
+/* DDRC_DRAMTMG8 */
+DATA 4 0x307a0120 0x00000803
+/* DDRC_ZQCTL0 */
+DATA 4 0x307a0180 0x00800020
+/* DDRC_ZQCTL1 */
+DATA 4 0x307a0184 0x02001000
+/* DDRC_DFITMG0 */
+DATA 4 0x307a0190 0x02098204
+/* DDRC_DFITMG1 */
+DATA 4 0x307a0194 0x00030303
+/* DDRC_ADDRMAP0 */
+DATA 4 0x307a0200 0x0000001f
+/* DDRC_ADDRMAP1 */
+DATA 4 0x307a0204 0x00080808
+/* DDRC_ADDRMAP5 */
+DATA 4 0x307a0214 0x07070707
+/* DDRC_ADDRMAP6 */
+DATA 4 0x307a0218 0x07070707
+/* DDRC_ODTCFG */
+DATA 4 0x307a0240 0x06000601
+/* DDRC_ODTMAP */
+DATA 4 0x307a0244 0x00000011
+/* SRC_DDRC_RCR */
+DATA 4 0x30391000 0x00000000
+/* DDR_PHY_PHY_CON0 */
+DATA 4 0x30790000 0x17420f40
+/* DDR_PHY_PHY_CON1 */
+DATA 4 0x30790004 0x10210100
+/* DDR_PHY_PHY_CON4 */
+DATA 4 0x30790010 0x00060807
+/* DDR_PHY_MDLL_CON0 */
+DATA 4 0x307900b0 0x1010007e
+/* DDR_PHY_DRVDS_CON0 */
+DATA 4 0x3079009c 0x00000d6e
+/* DDR_PHY_OFFSET_RD_CON0 */
+DATA 4 0x30790020 0x08080808
+/* DDR_PHY_OFFSET_WR_CON0 */
+DATA 4 0x30790030 0x08080808
+/* DDR_PHY_CMD_SDLL_CON0 */
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+/* DDR_PHY_ZQ_CON0 */
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+/* DDR_PHY_ZQ_CON1 */
+CHECK_BITS_SET 4 0x307900c4 0x1
+/* DDR_PHY_ZQ_CON0 */
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+/* CCM_CCGRn */
+DATA 4 0x30384130 0x00000000
+/* IOMUXC_GPR_GPR8 */
+DATA 4 0x30340020 0x00000178
+/* CCM_CCGRn */
+DATA 4 0x30384130 0x00000002
+/* DDR_PHY_LP_CON0 */
+DATA 4 0x30790018 0x0000000f
+
+/* DDRC_STAT */
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
new file mode 100644
index 0000000..50c1201
--- /dev/null
+++ b/configs/colibri_imx7_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_TARGET_COLIBRI_IMX7=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
+CONFIG_BOOTDELAY=1
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Colibri iMX7 # "
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x4020
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
new file mode 100644
index 0000000..9da219c
--- /dev/null
+++ b/include/configs/colibri_imx7.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * Configuration settings for the Colibri iMX7 module.
+ *
+ * based on mx7dsabresd.h:
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __COLIBRI_IMX7_CONFIG_H
+#define __COLIBRI_IMX7_CONFIG_H
+
+#include "mx7_common.h"
+
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
+/*#define CONFIG_DBG_MONITOR*/
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+/* Uncomment to enable secure boot support */
+/* #define CONFIG_SECURE_BOOT */
+#define CONFIG_CSF_SIZE			0x4000
+
+#define CONFIG_CMD_BMODE
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE		16384
+
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+#define SD_BOOTCMD \
+	"sdargs=root=/dev/mmcblk0p2 rw rootwait\0"	\
+	"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
+	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+	"run m4boot && " \
+	"load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
+	"load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0"	\
+	"nfsboot=run setup; " \
+		"setenv bootargs ${defargs} ${nfsargs} " \
+		"${setupargs} ${vidargs}; echo Booting from NFS...;" \
+		"dhcp ${kernel_addr_r} && "	\
+		"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD	\
+	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
+		"ubi.fm_autoconvert=1\0" \
+	"ubiboot=run setup; " \
+		"setenv bootargs ${defargs} ${ubiargs} " \
+		"${setupargs} ${vidargs}; echo Booting from NAND...; " \
+		"ubi part ubi && run m4boot && " \
+		"ubi read ${kernel_addr_r} kernel && " \
+		"ubi read ${fdt_addr_r} dtb && " \
+		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	UBI_BOOTCMD \
+	"console=ttymxc0\0" \
+	"defargs=\0" \
+	"fdt_board=eval-v3\0" \
+	"fdt_fixup=;\0" \
+	"m4boot=;\0" \
+	"ip_dyn=yes\0" \
+	"kernel_file=zImage\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+		"${board}/flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=mmc rescan && setenv interface mmc && " \
+		"fatload ${interface} 0:1 ${loadaddr} " \
+		"${board}/flash_blk.img && source ${loadaddr}\0" \
+	"setup=setenv setupargs " \
+		"console=tty1 console=${console}" \
+		",${baudrate}n8 ${memargs} consoleblank=0 ${mtdparts}\0" \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb && " \
+		"fatload ${interface} 0:1 ${loadaddr} " \
+		"${board}/flash_blk.img && source ${loadaddr}\0" \
+	"splashpos=m,m\0" \
+	"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x0c000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET		(4 * 1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#endif
+
+#define CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
+#define CONFIG_CMD_NAND_TORTURE
+
+/* UBI stuff */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_CMD_UBIFS	/* increases size by almost 60 KB */
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS	/* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT	"mtdparts=gpmi-nand:"		\
+				"512k(mx7-bcb),"		\
+				"3584k(u-boot)ro,"		\
+				"512k(u-boot-env),"		\
+				"-(ubi)"
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* USB Configs */
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+/* USB Device Firmware Update support */
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#endif
-- 
cgit v0.10.2


From 71813dcb56737707d12b697d5158ee96b48d7091 Mon Sep 17 00:00:00 2001
From: Breno Lima <breno.lima@nxp.com>
Date: Fri, 22 Jul 2016 15:29:30 -0300
Subject: warp7: Move some USB configuration options to defconfig

Currently it's recommended to move some configuration options to the
defconfig file.

Move some USB related options to the defconfig file.

Signed-off-by: Breno Lima <breno.lima@nxp.com>

diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 5a68998..617e0a0 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -24,6 +24,12 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_OF_LIBFDT=y
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 4c6e23c..e59b16c 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -125,18 +125,9 @@
 
 #define CONFIG_IMX_THERMAL
 
-#define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
 
-#define CONFIG_USB_GADGET
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
-
-#define CONFIG_G_DNL_VENDOR_NUM		0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER	"FSL"
 
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
-- 
cgit v0.10.2


From a13d3757f7df25d0f017e85551b899d598ad1bdb Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 23 Jul 2016 13:23:38 -0300
Subject: warp: Use imx_ddr_size() for calculating the DDR size

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/warp/warp.c b/board/warp/warp.c
index 49dfdb6..0bc0a6a 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 4a8e270..12c7c38 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -43,7 +43,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			SZ_512M
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-- 
cgit v0.10.2


From 84c51687a79c4bac514c43c0c3a0118015e6b13c Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 23 Jul 2016 13:23:39 -0300
Subject: aristainetos: Use imx_ddr_size() for calculating the DDR size

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>

diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index e95ec81..d1e6850 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -102,7 +102,7 @@ iomux_v3_cfg_t const usdhc1_pads[] = {
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index d87d40c..640227b 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -17,7 +17,6 @@
 
 #define CONFIG_MACH_TYPE	4501
 #define CONFIG_MMCROOT		"/dev/mmcblk0p1"
-#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(64 * SZ_1M)
-- 
cgit v0.10.2


From c6a51bab174ecb4c6bebfada951ac556ffc13fcd Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 23 Jul 2016 13:23:40 -0300
Subject: bx50v3: Use imx_ddr_size() for calculating the DDR size

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index d45ed44..e9729f8 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = imx_ddr_size();
 
 	return 0;
 }
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 4de2460..7a54546 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -32,8 +32,6 @@
 #define CONFIG_MXC_UART_BASE	UART3_BASE
 #define CONFIG_CONSOLE_DEV	"ttymxc2"
 
-#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
-
 #define CONFIG_SUPPORT_EMMC_BOOT
 
 
-- 
cgit v0.10.2


From 10ced52242e26c5a1b7e4d86c8273dfd89304841 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 23 Jul 2016 13:23:41 -0300
Subject: novena: Remove uneeded PHYS_SDRAM_SIZE

novena uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.

Remove the unneeded definition.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/include/configs/novena.h b/include/configs/novena.h
index 2382951..57d8c3e 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -57,7 +57,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			0xF0000000
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-- 
cgit v0.10.2


From 63326e6f0b48616ec708faec5fab55887fa8bf51 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sat, 23 Jul 2016 13:23:42 -0300
Subject: cgtqmx6eval: Remove uneeded PHYS_SDRAM_SIZE

cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.

Remove the unneeded definition.

Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index dd03936..127a28a 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -251,7 +251,6 @@
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS	       1
 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
 
 #define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-- 
cgit v0.10.2


From ec1935a243fcb4368fd8b537872d01d6b967b90f Mon Sep 17 00:00:00 2001
From: Diego Dorta <diego.dorta@nxp.com>
Date: Mon, 25 Jul 2016 13:45:30 -0300
Subject: mx6ul_14x14_evk: Remove unused define

Remove unused define constant.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 92c9211..66d6795 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -60,9 +60,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
-	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
 #define IOX_SDI IMX_GPIO_NR(5, 10)
 #define IOX_STCP IMX_GPIO_NR(5, 7)
 #define IOX_SHCP IMX_GPIO_NR(5, 11)
-- 
cgit v0.10.2


From 7626ba488ed4d465902d97da9b163e0e4e054b75 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Mon, 25 Jul 2016 22:57:47 -0700
Subject: mx7_common: initialize generic timer on all CPU's

Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize
the generic timer on all CPU's. This allows to make use of the timer
freuquency register also on other CPU than the start CPU which is
important for KVM.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 9f80f9f..7295fa6 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -21,6 +21,7 @@
 #define CONFIG_MXC_GPT_HCLK
 #define CONFIG_SYSCOUNTER_TIMER
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_BOOTM_LEN	0x1000000
-- 
cgit v0.10.2


From 4c97077ce781d192ac20853d36d1df60dd271699 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Tue, 26 Jul 2016 21:08:58 -0300
Subject: mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfig

Add an entry for the mx7dsabresd_secure_defconfig target.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS
index b96642a..c7a22fc 100644
--- a/board/freescale/mx7dsabresd/MAINTAINERS
+++ b/board/freescale/mx7dsabresd/MAINTAINERS
@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/freescale/mx7dsabresd
 F:	include/configs/mx7dsabresd.h
 F:	configs/mx7dsabresd_defconfig
+F:	configs/mx7dsabresd_secure_defconfig
-- 
cgit v0.10.2


From 77cbd3a14184c61d55d7fcddd88fa4e96efc9901 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Tue, 26 Jul 2016 21:27:49 -0300
Subject: MAINTAINERS: i.MX: Add board/freescale/*mx* path

Pass the board/freescale/*mx*/ path as files maintained by Stefano
Babic.

While this is not ideal and does not cover all the i.MX board cases,
it gives at least a better hint for the /scripts/get_maintainer.pl
tool.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 1db8243..1225ce2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -102,6 +102,7 @@ F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/imx-common/
+F:	board/freescale/*mx*/
 
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>
-- 
cgit v0.10.2


From 6bde34f1ae2a3fd253b0bc9b51686e30649ba7d8 Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Thu, 14 Jul 2016 16:22:39 -0700
Subject: spi: Add support for N25Q016A

This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index c577d9e..76affdd 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -84,6 +84,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"M25P64",	   0x202017, 0x0,       64 * 1024,   128, RD_NORM,			  0},
 	{"M25P128",	   0x202018, 0x0,      256 * 1024,    64, RD_NORM,			  0},
 	{"M25PX64",	   0x207117, 0x0,       64 * 1024,   128, RD_NORM,		    SECT_4K},
+	{"N25Q016A",       0x20bb15, 0x0,	64 * 1024,    32, RD_NORM,                  SECT_4K},
 	{"N25Q32",	   0x20ba16, 0x0,       64 * 1024,    64, RD_FULL,	   WR_QPP | SECT_4K},
 	{"N25Q32A",	   0x20bb16, 0x0,       64 * 1024,    64, RD_FULL,	   WR_QPP | SECT_4K},
 	{"N25Q64",	   0x20ba17, 0x0,       64 * 1024,   128, RD_FULL,	   WR_QPP | SECT_4K},
-- 
cgit v0.10.2


From 69eeefaa060a848cd6acd8c94d1c43c9022adf53 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Fri, 22 Jul 2016 10:55:48 +0530
Subject: spi: ti_qspi: Fix failure on multiple READ_ID cmd

Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 9a372ad..a850aa2 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -247,13 +247,12 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
 			debug("tx done, status %08x\n", status);
 		}
 		if (rxp) {
-			priv->cmd |= QSPI_RD_SNGL;
 			debug("rx cmd %08x dc %08x\n",
-			      priv->cmd, priv->dc);
+			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 			#ifdef CONFIG_DRA7XX
 				udelay(500);
 			#endif
-			writel(priv->cmd, &priv->base->cmd);
+			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 			status = readl(&priv->base->status);
 			timeout = QSPI_TIMEOUT;
 			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
-- 
cgit v0.10.2


From c595a2853099657ac97ccc7154a03e4d759fb909 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Fri, 22 Jul 2016 10:55:49 +0530
Subject: spi: ti_qspi: Fix compiler warning when DEBUG macro is set

clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index a850aa2..56ae29a 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -110,13 +110,13 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 {
 	uint clk_div;
 
-	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
-
 	if (!hz)
 		clk_div = 0;
 	else
 		clk_div = (QSPI_FCLK / hz) - 1;
 
+	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+
 	/* disable SCLK */
 	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 	       &priv->base->clk_ctrl);
-- 
cgit v0.10.2


From fee3b6af903c0e24b662694427b62658f40c7d4b Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Fri, 22 Jul 2016 10:55:50 +0530
Subject: spi: ti_qspi: Remove delay in read path for dra7xx

As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 56ae29a..fa7ee22 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -249,9 +249,6 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
 		if (rxp) {
 			debug("rx cmd %08x dc %08x\n",
 			      ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
-			#ifdef CONFIG_DRA7XX
-				udelay(500);
-			#endif
 			writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 			status = readl(&priv->base->status);
 			timeout = QSPI_TIMEOUT;
-- 
cgit v0.10.2


From b302669f46ebfd7cbc8ee1cdf48d87a68b1cc720 Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Tue, 5 Jul 2016 13:17:12 +0800
Subject: sf: sf_params: Add AT25DF321 flash support

Add AT25DF321 flash support.
Fix AT25DF321A device name.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 76affdd..70ca236 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -22,7 +22,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"AT45DB161D",	   0x1f2600, 0x0,	64 * 1024,    32, RD_NORM,		    SECT_4K},
 	{"AT45DB321D",	   0x1f2700, 0x0,	64 * 1024,    64, RD_NORM,		    SECT_4K},
 	{"AT45DB641D",	   0x1f2800, 0x0,	64 * 1024,   128, RD_NORM,		    SECT_4K},
-	{"AT25DF321",      0x1f4701, 0x0,	64 * 1024,    64, RD_NORM,		    SECT_4K},
+	{"AT25DF321A",     0x1f4701, 0x0,	64 * 1024,    64, RD_NORM,		    SECT_4K},
+	{"AT25DF321",      0x1f4700, 0x0,	64 * 1024,    64, RD_NORM,		    SECT_4K},
 	{"AT26DF081A",     0x1f4501, 0x0,	64 * 1024,    16, RD_NORM,		    SECT_4K},
 #endif
 #ifdef CONFIG_SPI_FLASH_EON		/* EON */
-- 
cgit v0.10.2


From 4d790788ce009909842290e85d3e57db36935ad4 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 25 Jul 2016 15:45:44 +0530
Subject: ARM: dra7xx: Change DPLL_PER_HS13 divider value

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 62dd275..a83f68c 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -160,7 +160,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 26 MHz   */
-- 
cgit v0.10.2


From a6f56ad1eee1fe7ae1a46e022427a001eda4ce16 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Mon, 25 Jul 2016 15:45:45 +0530
Subject: spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index fa7ee22..bb72cb0 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
-#define QSPI_FCLK                       192000000
+#define QSPI_FCLK			192000000
+#define QSPI_DRA7XX_FCLK                76800000
 /* clock control */
 #define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
@@ -101,6 +102,7 @@ struct ti_qspi_priv {
 #endif
 	struct ti_qspi_regs *base;
 	void *ctrl_mod_mmap;
+	ulong fclk;
 	unsigned int mode;
 	u32 cmd;
 	u32 dc;
@@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 	if (!hz)
 		clk_div = 0;
 	else
-		clk_div = (QSPI_FCLK / hz) - 1;
+		clk_div = (priv->fclk / hz) - 1;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
@@ -366,8 +368,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+	priv->fclk = QSPI_DRA7XX_FCLK;
 #else
 	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+	priv->fclk = QSPI_FCLK;
 #endif
 
 	ti_spi_set_speed(priv, max_hz);
@@ -520,7 +524,10 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 
 static int ti_qspi_probe(struct udevice *bus)
 {
-	/* Nothing to do in probe */
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+	priv->fclk = dev_get_driver_data(bus);
+
 	return 0;
 }
 
@@ -572,8 +579,8 @@ static const struct dm_spi_ops ti_qspi_ops = {
 };
 
 static const struct udevice_id ti_qspi_ids[] = {
-	{ .compatible = "ti,dra7xxx-qspi" },
-	{ .compatible = "ti,am4372-qspi" },
+	{ .compatible = "ti,dra7xxx-qspi",	.data = QSPI_DRA7XX_FCLK},
+	{ .compatible = "ti,am4372-qspi",	.data = QSPI_FCLK},
 	{ }
 };
 
-- 
cgit v0.10.2


From b9612bb2dee788c71ee0411bf776e7e1f9f9ddbc Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Mon, 25 Jul 2016 15:45:46 +0530
Subject: configs: dra7xx: Update QSPI speed to 76.8MHz

Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0d51aeb..0b78ada 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -157,7 +157,7 @@
 /* SPI */
 #undef	CONFIG_OMAP3_SPI
 #define CONFIG_TI_SPI_MMAP
-#define CONFIG_SF_DEFAULT_SPEED                64000000
+#define CONFIG_SF_DEFAULT_SPEED                76800000
 #define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_0
 #define CONFIG_QSPI_QUAD_SUPPORT
 
-- 
cgit v0.10.2


From 70ebdd775b35d8711a80cee27a6ade697afb25d5 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Mon, 25 Jul 2016 15:45:47 +0530
Subject: ARM: dts: dra7xx: Update spi-max-frequency for QSPI

According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index 429b9ed..8b77a76 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -491,7 +491,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <64000000>;
+	spi-max-frequency = <76800000>;
 	m25p80@0 {
 		compatible = "s25fl256s1","spi-flash";
 		spi-max-frequency = <64000000>;
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index ced2f11..c7c5d40 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -603,7 +603,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <64000000>;
+	spi-max-frequency = <76800000>;
 	m25p80@0 {
 		compatible = "s25fl256s1","spi-flash";
 		spi-max-frequency = <64000000>;
-- 
cgit v0.10.2


From 2ae94221458fc70ae3ccac291450511d4bb7074a Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Thu, 28 Jul 2016 17:27:57 +0530
Subject: configs: am43xx_evm_defconfig: Enable CONFIG_SPI_FLASH_BAR

AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 0eab4ad..b3fe269 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -37,6 +37,7 @@ CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
-- 
cgit v0.10.2


From 9af6ce42484ec4a1be4898ca7423ff93ac2ce2c5 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Fri, 29 Jul 2016 14:22:31 +0530
Subject: ARM: dts: am57xx-idk-common: Enable support for QSPI

AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi
index 2805b68..a5bcd25 100644
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -300,3 +300,52 @@
 	ti,non-removable;
 	max-frequency = <96000000>;
 };
+
+&qspi {
+	status = "okay";
+
+	spi-max-frequency = <76800000>;
+	m25p80@0 {
+		compatible = "s25fl256s1","spi-flash";
+		spi-max-frequency = <76800000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first four physical blocks
+		 * for a valid file to boot and the flash here is
+		 * 64KiB block size.
+		 */
+		partition@0 {
+			label = "QSPI.SPL";
+			reg = <0x00000000 0x000040000>;
+		};
+		partition@1 {
+			label = "QSPI.u-boot";
+			reg = <0x00040000 0x00100000>;
+		};
+		partition@2 {
+			label = "QSPI.u-boot-spl-os";
+			reg = <0x00140000 0x00080000>;
+		};
+		partition@3 {
+			label = "QSPI.u-boot-env";
+			reg = <0x001c0000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.u-boot-env.backup1";
+			reg = <0x001d0000 0x0010000>;
+		};
+		partition@5 {
+			label = "QSPI.kernel";
+			reg = <0x001e0000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.file-system";
+			reg = <0x009e0000 0x01620000>;
+		};
+	};
+};
-- 
cgit v0.10.2


From 08887ed4505ec14ee94ab32c482dc4dec5ddc1e4 Mon Sep 17 00:00:00 2001
From: Vignesh R <vigneshr@ti.com>
Date: Fri, 29 Jul 2016 14:22:30 +0530
Subject: ARM: am57xx_evm: Enable QSPI support

AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 8a8a4c9..c95f45a 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -41,3 +41,8 @@ CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
 CONFIG_DM_I2C=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_TI_QSPI=y
+CONFIG_CMD_SF=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 4c5a0de..f518e6f 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -26,3 +26,8 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_TI_QSPI=y
+CONFIG_CMD_SF=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 2ccb332..a4bfdd5 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -43,3 +43,8 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_LIST="am57xx-beagle-x15"
 CONFIG_DM_I2C=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_TI_QSPI=y
+CONFIG_CMD_SF=y
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 2db199d..083886b 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -86,4 +86,40 @@
 #define CONFIG_EEPROM_CHIP_ADDRESS 0x50
 #define CONFIG_EEPROM_BUS_ADDRESS 0
 
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
+ * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
+ * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
+ * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
+ * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
+ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
+ * 0x9E0000 - 0x2000000 : USERLAND
+ */
+#define CONFIG_SYS_SPI_KERNEL_OFFS      0x1E0000
+#define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE        0x80000
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE             (256 << 10) /* 256 KiB */
+#endif
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_DMA_SUPPORT
+#define CONFIG_TI_EDMA3
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
+
+/* SPI */
+#undef	CONFIG_OMAP3_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_SPEED                76800000
+#define CONFIG_SF_DEFAULT_MODE                 SPI_MODE_0
+#define CONFIG_QSPI_QUAD_SUPPORT
+
 #endif /* __CONFIG_AM57XX_EVM_H */
-- 
cgit v0.10.2


From 5c928d02044345b843202f23540c3765468c1d6f Mon Sep 17 00:00:00 2001
From: Angelo Dureghello <angelo@sysam.it>
Date: Sun, 22 May 2016 00:14:29 +0200
Subject: m68k: code reformatting for all start.S files

This patch is style-related only, to reformat all the start.S code,
actually not following a coherent style inside single files and
between different cpu start.S files.

Linux format has been respected, as
  - max line width at 80 columns
  - one 8 cols tab between asm instructions and operands
  - inline comments, where any, fixed at col 41

Signed-off-by: Angelo Dureghello <angelo@sysam.it>

diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index 13c036f..b5d51bd 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -28,52 +28,37 @@
 	rte;
 
 #if defined(CONFIG_CF_SBF)
-#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
-#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
 #endif
 
 .text
+
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
-
 #if defined(CONFIG_CF_SBF)
-INITSP:		.long	0		/* Initial SP	*/
-INITPC:		.long	ASM_DRAMINIT	/* Initial PC 	*/
+INITSP:	.long	0			/* Initial SP	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
 #else
-INITSP:		.long	0	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC 		*/
+INITSP:	.long	0			/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC 	*/
 #endif
 
-vector02:	.long	_FAULT	/* Access Error		*/
-vector03:	.long	_FAULT	/* Address Error	*/
-vector04:	.long	_FAULT	/* Illegal Instruction	*/
-vector05:	.long	_FAULT	/* Reserved		*/
-vector06:	.long	_FAULT	/* Reserved		*/
-vector07:	.long	_FAULT	/* Reserved		*/
-vector08:	.long	_FAULT	/* Privilege Violation	*/
-vector09:	.long	_FAULT	/* Trace		*/
-vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
-vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
-vector0C:	.long	_FAULT	/* Debug Interrupt	*/
-vector0D:	.long	_FAULT	/* Reserved		*/
-vector0E:	.long	_FAULT	/* Format Error		*/
-vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* Reserved */
 vector10_17:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-vector18:	.long	_FAULT	/* Spurious Interrupt	*/
-vector19:	.long	_FAULT	/* Autovector Level 1	*/
-vector1A:	.long	_FAULT	/* Autovector Level 2	*/
-vector1B:	.long	_FAULT	/* Autovector Level 3	*/
-vector1C:	.long	_FAULT	/* Autovector Level 4	*/
-vector1D:	.long	_FAULT	/* Autovector Level 5	*/
-vector1E:	.long	_FAULT	/* Autovector Level 6	*/
-vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 #if !defined(CONFIG_CF_SBF)
 /* TRAP #0 - #15 */
@@ -120,15 +105,16 @@ vector192_255:
 #if defined(CONFIG_CF_SBF)
 	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
 asm_sbf_img_hdr:
-	.long	0x00000000	/* checksum, not yet implemented */
-	.long	0x00020000	/* image length */
+	.long	0x00000000		/* checksum, not yet implemented */
+	.long	0x00020000		/* image length */
 	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
 
 asm_dram_init:
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
-	movec	%d0, %RAMBAR1	/* init Rambar */
+	movec	%d0, %RAMBAR1		/* init Rambar */
+
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	clr.l	%sp@-
 
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
@@ -142,7 +128,6 @@ asm_dram_init:
 	 * Dram Initialization
 	 * a1, a2, and d0
 	 */
-	/* mscr sdram */
 	move.l	#0xFC0A4074, %a1
 	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
 	nop
@@ -336,15 +321,15 @@ asm_dspi_rd_status:
 
 	move.b	(%a3), %d1
 	rts
-#endif			/* CONFIG_CF_SBF */
+#endif /* CONFIG_CF_SBF */
 
-	.text
+.text
 	. = 0x400
-	.globl	_start
+.globl _start
 _start:
 	nop
 	nop
-	move.w #0x2700,%sr		/* Mask off Interrupt */
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
 #if defined(CONFIG_CF_SBF)
@@ -366,17 +351,17 @@ _start:
 	movec	%d0, %ACR1
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
@@ -386,20 +371,23 @@ _start:
 	bsr	board_init_f_alloc_reserve
 
 	/* update stack and frame-pointers */
-	move.l  %d0, %sp
-	move.l  %sp, %fp
+	move.l	%d0, %sp
+	move.l	%sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
-	bsr     board_init_f_init_reserve
+	move.l	%d0, -(%sp)
+	bsr	board_init_f_init_reserve
+
+	/* run low-level CPU init code (from flash) */
+	bsr	cpu_init_f
+	clr.l	%sp@-
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	clr.l   %sp@-
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level board init code (from flash) */
+	bsr	board_init_f
 
 	/* board_init_f() does not return */
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -412,23 +400,23 @@ _start:
  * r5 = length in bytes
  * r6 = cachelinesize
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
 
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
 
 	/* copy the code to RAM */
 1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -458,7 +446,7 @@ clear_bss:
 	 */
 	move.l	%a0, %a1
 	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a1,%a5			/* * fix got pointer register a5 */
+	move.l	%a1,%a5			/* fix got pointer register a5 */
 
 	move.l	%a0, %a2
 	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
@@ -472,39 +460,40 @@ clear_bss:
 	bne	7b
 
 	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
 	jsr	(%a1)
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
-	bra _fault
-	.globl	_exc_handler
+	bra	_fault
 
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
-	.globl	version_string
+.globl version_string
 version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-	.align 4
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 3aa4dd6..c4f6082 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -28,41 +28,25 @@
 	rte;
 
 .text
+
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
+INITSP:	.long	0x00000000		/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC	*/
 
-INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC		*/
-vector02:	.long	_FAULT	/* Access Error		*/
-vector03:	.long	_FAULT	/* Address Error	*/
-vector04:	.long	_FAULT	/* Illegal Instruction	*/
-vector05:	.long	_FAULT	/* Reserved		*/
-vector06:	.long	_FAULT	/* Reserved		*/
-vector07:	.long	_FAULT	/* Reserved		*/
-vector08:	.long	_FAULT	/* Privilege Violation	*/
-vector09:	.long	_FAULT	/* Trace		*/
-vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
-vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
-vector0C:	.long	_FAULT	/* Debug Interrupt	*/
-vector0D:	.long	_FAULT	/* Reserved		*/
-vector0E:	.long	_FAULT	/* Format Error		*/
-vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* Reserved */
 vector10_17:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-vector18:	.long	_FAULT	/* Spurious Interrupt	*/
-vector19:	.long	_FAULT	/* Autovector Level 1	*/
-vector1A:	.long	_FAULT	/* Autovector Level 2	*/
-vector1B:	.long	_FAULT	/* Autovector Level 3	*/
-vector1C:	.long	_FAULT	/* Autovector Level 4	*/
-vector1D:	.long	_FAULT	/* Autovector Level 5	*/
-vector1E:	.long	_FAULT	/* Autovector Level 6	*/
-vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* TRAP #0 - #15 */
 vector20_2F:
@@ -104,13 +88,13 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-	.text
+.text
 
-	.globl	_start
+.globl _start
 _start:
 	nop
 	nop
-	move.w #0x2700,%sr	/* Mask off Interrupt */
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
@@ -120,22 +104,22 @@ _start:
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
-	move.l	#CF_CACR_CINV, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#CF_CACR_CINV, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
 	nop
 	move.l	#0, %d0
 	movec	%d0, %ACR0
 	movec	%d0, %ACR1
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
 	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
@@ -149,25 +133,26 @@ _start:
 	jsr	(%a1)
 
 	/* update stack and frame-pointers */
-	move.l  %d0, %sp
-	move.l  %sp, %fp
+	move.l	%d0, %sp
+	move.l	%sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
+	move.l	%d0, -(%sp)
 	move.l	#board_init_f_init_reserve, %a1
 	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
-	move.l #cpu_init_f, %a1
-	jsr (%a1)
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
 	/* run low-level board init code (from flash) */
-	clr.l   %sp@-
-	move.l #board_init_f, %a1
-	jsr (%a1)
+	clr.l	%sp@-
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
 
 	/* board_init_f() does not return */
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -180,23 +165,23 @@ _start:
  * r5 = length in bytes
  * r6 = cachelinesize
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
 
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
 
 	/* copy the code to RAM */
 1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -240,39 +225,40 @@ clear_bss:
 	bne	7b
 
 	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
 	jsr	(%a1)
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
-	bra _fault
-	.globl	_exc_handler
+	bra	_fault
 
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
-	.globl	version_string
+.globl version_string
 version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-	.align 4
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index a048884..9837c41 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -34,12 +34,12 @@
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 
 .text
+
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
-
 .long	0x00000000		/* Flash offset is 0 until we setup CS0 */
 #if defined(CONFIG_M5282) && (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
 .long	_start - CONFIG_SYS_TEXT_BASE
@@ -85,24 +85,24 @@ _vectors:
 
 #endif
 
-	.text
-
+.text
 
 #if defined(CONFIG_SYS_INT_FLASH_BASE) && \
     (defined(CONFIG_M5282) || defined(CONFIG_M5281))
-	#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-		.long	0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
-		.long	0xFFFFFFFF /* all sectors protected */
-		.long	0x00000000 /* supervisor/User restriction */
-		.long	0x00000000 /* programm/data space restriction */
-		.long	0x00000000 /* Flash security */
-	#endif
+#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+.long	0x55AA55AA,0xAA55AA55		/* CFM Backdoorkey */
+.long	0xFFFFFFFF			/* all sectors protected */
+.long	0x00000000			/* supervisor/User restriction */
+.long	0x00000000			/* programm/data space restriction */
+.long	0x00000000			/* Flash security */
 #endif
-	.globl	_start
+#endif
+
+.globl _start
 _start:
 	nop
 	nop
-	move.w #0x2700,%sr
+	move.w	#0x2700,%sr
 
 #if defined(CONFIG_M5208)
 	/* Initialize RAMBAR: locate SRAM and validate it */
@@ -111,22 +111,24 @@ _start:
 #endif
 
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set MBAR address + valid flag */
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
 	move.c	%d0, %MBAR
 
 	/*** The 5249 has MBAR2 as well ***/
 #ifdef CONFIG_SYS_MBAR2
-	move.l	#(CONFIG_SYS_MBAR2 + 1), %d0	        /* Get MBAR2 address */
-	movec	%d0, #0xc0e		        /* Set MBAR2 */
+	/* Get MBAR2 address */
+	move.l	#(CONFIG_SYS_MBAR2 + 1), %d0
+	 /* Set MBAR2 */
+	movec	%d0, #0xc0e
 #endif
-
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
 	movec	%d0, %RAMBAR0
 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
 
 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
-	/* Initialize IPSBAR */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
 	move.l	%d0, 0x40000000
 
 	/* Initialize RAMBAR1: locate SRAM and validate it */
@@ -135,22 +137,24 @@ _start:
 
 #if defined(CONFIG_M5282)
 #if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
-
-	move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
-	move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
+	/*
+	 * Setup code in SRAM to initialize FLASHBAR,
+	 * if start from internal Flash
+	 */
+	move.l	#(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
+	move.l	#(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR), %a2
 _copy_flash:
-	move.l (%a0)+, (%a2)+
-	cmp.l %a0, %a1
-	bgt.s _copy_flash
-	jmp CONFIG_SYS_INIT_RAM_ADDR
+	move.l	(%a0)+, (%a2)+
+	cmp.l	%a0, %a1
+	bgt.s	_copy_flash
+	jmp	CONFIG_SYS_INIT_RAM_ADDR
 
 _flashbar_setup:
 	/* Initialize FLASHBAR: locate internal Flash and validate it */
 	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
 	movec	%d0, %FLASHBAR
-	jmp _after_flashbar_copy.L	/* Force jump to absolute address */
+	jmp	_after_flashbar_copy.L	/* Force jump to absolute address */
 _flashbar_setup_end:
 	nop
 _after_flashbar_copy:
@@ -162,7 +166,8 @@ _after_flashbar_copy:
 
 #endif
 #endif
-	/* if we come from a pre-loader we have no exception table and
+	/*
+	 * if we come from a pre-loader we have no exception table and
 	 * therefore no VBR to set
 	 */
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
@@ -175,8 +180,8 @@ _after_flashbar_copy:
 #endif
 
 #ifdef CONFIG_M5275
-	/* Initialize IPSBAR */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
+	/* set MBAR address + valid flag */
+	move.l	#(CONFIG_SYS_MBAR + 1), %d0
 	move.l	%d0, 0x40000000
 /*	movec	%d0, %MBAR */
 
@@ -186,17 +191,17 @@ _after_flashbar_copy:
 #endif
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
@@ -204,28 +209,29 @@ _after_flashbar_copy:
 	 */
 	move.l	%sp, -(%sp)
 	move.l	#board_init_f_alloc_reserve, %a1
-	jsr (%a1)
+	jsr	(%a1)
 
 	/* update stack and frame-pointers */
-	move.l  %d0, %sp
-	move.l  %sp, %fp
+	move.l	%d0, %sp
+	move.l	%sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
+	move.l	%d0, -(%sp)
 	move.l	#board_init_f_init_reserve, %a1
-	jsr (%a1)
+	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
-	move.l #cpu_init_f, %a1
-	jsr (%a1)
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
 	/* run low-level board init code (from flash) */
-	clr.l   %sp@-
-	move.l #board_init_f, %a1
-	jsr (%a1)
+	clr.l	%sp@-
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
 
 	/* board_init_f() does not return */
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -238,22 +244,22 @@ _after_flashbar_copy:
  * r5 = length in bytes
  * r6 = cachelinesize
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
 
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
 	/* copy the code to RAM */
 1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -283,7 +289,7 @@ clear_bss:
 	 */
 	move.l	%a0, %a1
 	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a1,%a5		/* * fix got pointer register a5 */
+	move.l	%a1,%a5			/* fix got pointer register a5 */
 
 	move.l	%a0, %a2
 	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
@@ -297,43 +303,44 @@ clear_bss:
 	bne	7b
 
 	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
 #if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
     defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
 	halt
 #endif
 	jsr	(%a1)
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
-	bra _fault
+	bra	_fault
 
-	.globl	_exc_handler
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
-	.globl	version_string
+.globl version_string
 version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-	.align 4
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index ca8bb32..da41c9a 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -36,12 +36,12 @@
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 
 .text
+
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
-
 /* Flash offset is 0 until we setup CS0 */
 .long	0x00000000
 #if defined(CONFIG_M5307) && \
@@ -89,12 +89,13 @@ _vectors:
 
 #endif
 
-	.text
-	.globl	_start
+.text
+
+.globl _start
 _start:
 	nop
 	nop
-	move.w  #0x2700,%sr
+	move.w	#0x2700,%sr
 
 	/* set MBAR address + valid flag */
 	move.l	#(CONFIG_SYS_MBAR + 1), %d0
@@ -104,11 +105,11 @@ _start:
 	move.c	%d0, %RAMBAR
 
 	/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
-        move.l  #CF_CACR_CINVA, %d0
-        movec   %d0, %CACR
-        move.l  #0, %d0
-        movec   %d0, %ACR0
-        movec   %d0, %ACR1
+        move.l	#CF_CACR_CINVA, %d0
+        movec	%d0, %CACR
+        move.l	#0, %d0
+        movec	%d0, %ACR0
+        movec	%d0, %ACR1
 
 	/*
 	 * if we come from a pre-loader we have no exception table and
@@ -127,10 +128,10 @@ _start:
 	move.l	%d0, (%a2)
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
@@ -140,23 +141,23 @@ _start:
 	bsr	board_init_f_alloc_reserve
 
 	/* update stack and frame-pointers */
-	move.l  %d0, %sp
-	move.l  %sp, %fp
+	move.l	%d0, %sp
+	move.l	%sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
-	bsr     board_init_f_init_reserve
+	move.l	%d0, -(%sp)
+	bsr	board_init_f_init_reserve
 
 	/* run low-level CPU init code (from flash) */
-	bsr cpu_init_f
+	bsr	cpu_init_f
 
 	/* run low-level board init code (from flash) */
-	clr.l   %sp@-
-	bsr board_init_f
+	clr.l	%sp@-
+	bsr	board_init_f
 
 	/* board_init_f() does not return */
 
-/*--------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -165,7 +166,7 @@ _start:
  * after relocating the monitor code.
  *
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
 	link.w	%a6,#0
 	move.l	8(%a6), %sp	/* set new stack pointer */
@@ -209,7 +210,8 @@ clear_bss:
 	 */
 	move.l	%a0, %a1
 	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE), %a1
-	/* * fix got pointer register a5 */
+
+	/* fix got pointer register a5 */
 	move.l	%a1,%a5
 
 	move.l	%a0, %a2
@@ -236,33 +238,34 @@ clear_bss:
 #endif
 	jsr	(%a1)
 
-/*--------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
 	bra	_fault
 
-	.globl	_exc_handler
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr 	exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr 	int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*--------------------------------------------------------------------------*/
+/******************************************************************************/
 
-	.globl	version_string
+.globl version_string
 version_string:
-	.ascii	U_BOOT_VERSION
-	.ascii	" (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
-	.ascii	CONFIG_IDENT_STRING, "\0"
-	.align	4
+.ascii	U_BOOT_VERSION
+.ascii	" (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+.ascii	CONFIG_IDENT_STRING, "\0"
+.align	4
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index f25bc54..302fca5 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -31,42 +31,27 @@
 	rte;
 
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
+
 .text
+
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
+INITSP:	.long	0x00000000		/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC		*/
 
-INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC		*/
-vector02:	.long	_FAULT	/* Access Error		*/
-vector03:	.long	_FAULT	/* Address Error	*/
-vector04:	.long	_FAULT	/* Illegal Instruction	*/
-vector05:	.long	_FAULT	/* Reserved		*/
-vector06:	.long	_FAULT	/* Reserved		*/
-vector07:	.long	_FAULT	/* Reserved		*/
-vector08:	.long	_FAULT	/* Privilege Violation	*/
-vector09:	.long	_FAULT	/* Trace		*/
-vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
-vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
-vector0C:	.long	_FAULT	/* Debug Interrupt	*/
-vector0D:	.long	_FAULT	/* Reserved		*/
-vector0E:	.long	_FAULT	/* Format Error		*/
-vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* Reserved */
 vector10_17:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-vector18:	.long	_FAULT	/* Spurious Interrupt	*/
-vector19:	.long	_FAULT	/* Autovector Level 1	*/
-vector1A:	.long	_FAULT	/* Autovector Level 2	*/
-vector1B:	.long	_FAULT	/* Autovector Level 3	*/
-vector1C:	.long	_FAULT	/* Autovector Level 4	*/
-vector1D:	.long	_FAULT	/* Autovector Level 5	*/
-vector1E:	.long	_FAULT	/* Autovector Level 6	*/
-vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* TRAP #0 - #15 */
 vector20_2F:
@@ -109,13 +94,13 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
 
-	.text
+.text
 
-	.globl	_start
+.globl _start
 _start:
 	nop
 	nop
-	move.w #0x2700,%sr	/* Mask off Interrupt */
+	move.w	#0x2700,%sr	/* Mask off Interrupt */
 
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	/* Set vector base register at the beginning of the Flash */
@@ -142,14 +127,14 @@ _start:
 #endif
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
 	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
@@ -167,13 +152,14 @@ _start:
 	move.l  %sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
+	move.l	%d0, -(%sp)
 	move.l	#board_init_f_init_reserve, %a1
 	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
-	move.l #cpu_init_f, %a1
-	jsr (%a1)
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
 	/* run low-level board init code (from flash) */
 	clr.l   %sp@-
 	move.l #board_init_f, %a1
@@ -181,7 +167,7 @@ _start:
 
 	/* board_init_f() does not return */
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -194,23 +180,23 @@ _start:
  * r5 = length in bytes
  * r6 = cachelinesize
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
 
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
 
 	/* copy the code to RAM */
 1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -240,7 +226,7 @@ clear_bss:
 	 */
 	move.l	%a0, %a1
 	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a1,%a5		/* * fix got pointer register a5 */
+	move.l	%a1,%a5			/* fix got pointer register a5 */
 
 	move.l	%a0, %a2
 	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
@@ -254,38 +240,40 @@ clear_bss:
 	bne	7b
 
 	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
 	jsr	(%a1)
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
 	bra _fault
-	.globl	_exc_handler
 
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*------------------------------------------------------------------------------*/
-	.globl	version_string
+/******************************************************************************/
+
+.globl version_string
 version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-	.align 4
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index ba38678..bc48ca0 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -33,62 +33,47 @@
 	rte;
 
 #if defined(CONFIG_SERIAL_BOOT)
-#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
 #define ASM_DRAMINIT_N	(asm_dram_init - CONFIG_SYS_TEXT_BASE)
-#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
+	CONFIG_SYS_INIT_RAM_ADDR)
 #endif
 
 .text
 
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
 #if defined(CONFIG_SERIAL_BOOT)
 
-INITSP:	.long	0		/* Initial SP	*/
+INITSP:	.long	0			/* Initial SP	*/
 #ifdef CONFIG_CF_SBF
-INITPC:	.long	ASM_DRAMINIT	/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
 #endif
 #ifdef CONFIG_SYS_NAND_BOOT
-INITPC:	.long	ASM_DRAMINIT_N	/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC 	*/
 #endif
 
 #else
 
-INITSP:		.long	0	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC 		*/
+INITSP:	.long	0			/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC 	*/
 
 #endif
 
-vector02:	.long	_FAULT	/* Access Error		*/
-vector03:	.long	_FAULT	/* Address Error	*/
-vector04:	.long	_FAULT	/* Illegal Instruction	*/
-vector05:	.long	_FAULT	/* Reserved		*/
-vector06:	.long	_FAULT	/* Reserved		*/
-vector07:	.long	_FAULT	/* Reserved		*/
-vector08:	.long	_FAULT	/* Privilege Violation	*/
-vector09:	.long	_FAULT	/* Trace		*/
-vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
-vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
-vector0C:	.long	_FAULT	/* Debug Interrupt	*/
-vector0D:	.long	_FAULT	/* Reserved		*/
-vector0E:	.long	_FAULT	/* Format Error		*/
-vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* Reserved */
 vector10_17:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-vector18:	.long	_FAULT	/* Spurious Interrupt	*/
-vector19:	.long	_FAULT	/* Autovector Level 1	*/
-vector1A:	.long	_FAULT	/* Autovector Level 2	*/
-vector1B:	.long	_FAULT	/* Autovector Level 3	*/
-vector1C:	.long	_FAULT	/* Autovector Level 4	*/
-vector1D:	.long	_FAULT	/* Autovector Level 5	*/
-vector1E:	.long	_FAULT	/* Autovector Level 6	*/
-vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 #if !defined(CONFIG_SERIAL_BOOT)
 
@@ -136,12 +121,12 @@ vector192_255:
 #if defined(CONFIG_SERIAL_BOOT)
 	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
 asm_sbf_img_hdr:
-	.long	0x00000000	/* checksum, not yet implemented */
-	.long	0x00040000	/* image length */
+	.long	0x00000000		/* checksum, not yet implemented */
+	.long	0x00040000		/* image length */
 	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
 
 asm_dram_init:
-	move.w #0x2700,%sr		/* Mask off Interrupt */
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 #ifdef CONFIG_SYS_NAND_BOOT
 	/* for assembly stack */
@@ -149,7 +134,7 @@ asm_dram_init:
 	movec	%d0, %RAMBAR1
 
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	clr.l	%sp@-
 #endif
 
 #ifdef CONFIG_CF_SBF
@@ -160,11 +145,11 @@ asm_dram_init:
 	movec	%d0, %RAMBAR1
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* dcache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* invalidate and disable cache */
 	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
@@ -176,7 +161,7 @@ asm_dram_init:
 	movec	%d0, %ACR3
 
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
+	clr.l	%sp@-
 
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
@@ -185,7 +170,7 @@ asm_dram_init:
 	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
 	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
-#endif			/* CONFIG_CF_SBF */
+#endif /* CONFIG_CF_SBF */
 
 #ifdef CONFIG_MCF5441x
 	/* TC: enable all peripherals,
@@ -193,9 +178,9 @@ asm_dram_init:
 	move.l	#0xFC04002D, %a1
 
 #if defined(CONFIG_CF_SBF)
-	move.b	#23, (%a1)	/* dspi */
+	move.b	#23, (%a1)		/* dspi */
 #endif
-	move.b	#46, (%a1)	/* DDR */
+	move.b	#46, (%a1)		/* DDR */
 
 	/* slew settings */
 	move.l	#0xEC094060, %a1
@@ -365,7 +350,7 @@ dramsz_loop:
 
 	move.l	#2000, %d1
 	jsr	asm_delay
-#endif		/* CONFIG_MCF5445x */
+#endif /* CONFIG_MCF5445x */
 
 #ifdef CONFIG_CF_SBF
 	/*
@@ -484,7 +469,7 @@ asm_dspi_rd_status:
 
 	move.b	(%a3), %d1
 	rts
-#endif			/* CONFIG_CF_SBF */
+#endif /* CONFIG_CF_SBF */
 
 #ifdef CONFIG_SYS_NAND_BOOT
 	/* copy 4 boot pages to dram as soon as possible */
@@ -509,13 +494,13 @@ asm_nand_init:
 	move.l	%d1, (%a1)
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(CACR_STATUS), %a1	/* CACR */
-	move.l #(ICACHE_STATUS), %a2	/* icache */
-	move.l #(DCACHE_STATUS), %a3	/* dcache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
-	move.l %d0, (%a3)
+	move.l	#0, %d0
+	move.l	#(CACR_STATUS), %a1	/* CACR */
+	move.l	#(ICACHE_STATUS), %a2	/* icache */
+	move.l	#(DCACHE_STATUS), %a3	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a3)
 
 	/* invalidate and disable cache */
 	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
@@ -571,7 +556,7 @@ asm_nand_init:
 	move.l	#4, %d2			/* start at 4 */
 	move.l  #0xFC0FFF04, %a0	/* cmd2 */
 	move.l  #0xFC0FFF0C, %a1	/* rar */
-	move.l	#(CONFIG_SYS_TEXT_BASE + 0xF80), %a2	/* dst */
+	move.l	#(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
 
 asm_nand_read:
 	move.l	#0x11000000, %d0	/* rar */
@@ -621,14 +606,14 @@ asm_delay:
 	rts
 #endif			/* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
 
-	.text
+.text
 	. = 0x400
-	.globl	_start
+.globl _start
 _start:
 #if !defined(CONFIG_SERIAL_BOOT)
 	nop
 	nop
-	move.w #0x2700,%sr		/* Mask off Interrupt */
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
@@ -638,11 +623,11 @@ _start:
 	movec	%d0, %RAMBAR1
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* dcache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* dcache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* invalidate and disable cache */
 	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
@@ -658,10 +643,10 @@ _start:
 #endif
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
@@ -672,25 +657,26 @@ _start:
 	jsr	(%a1)
 
 	/* update stack and frame-pointers */
-	move.l  %d0, %sp
-	move.l  %sp, %fp
+	move.l	%d0, %sp
+	move.l	%sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
+	move.l	%d0, -(%sp)
 	move.l	#board_init_f_init_reserve, %a1
 	jsr	(%a1)
 
 	/* run low-level CPU init code (from flash) */
-	move.l #cpu_init_f, %a1
-	jsr (%a1)
+	move.l	#cpu_init_f, %a1
+	jsr	(%a1)
+
 	/* run low-level board init code (from flash) */
 	clr.l   %sp@-
-	move.l #board_init_f, %a1
-	jsr (%a1)
+	move.l	#board_init_f, %a1
+	jsr	(%a1)
 
 	/* board_init_f() does not return */
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -703,23 +689,23 @@ _start:
  * r5 = length in bytes
  * r6 = cachelinesize
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
 
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
 
 	/* copy the code to RAM */
 1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -749,7 +735,7 @@ clear_bss:
 	 */
 	move.l	%a0, %a1
 	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a1,%a5			/* * fix got pointer register a5 */
+	move.l	%a1,%a5			/* fix got pointer register a5 */
 
 	move.l	%a0, %a2
 	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
@@ -763,39 +749,40 @@ clear_bss:
 	bne	7b
 
 	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
 	jsr	(%a1)
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
-	bra _fault
-	.globl	_exc_handler
+	bra	_fault
 
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
-	.globl	version_string
+.globl version_string
 version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-	.align 4
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index 9a87a0d..fecf253 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -28,41 +28,25 @@
 	rte;
 
 .text
+
 /*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
+ * Vector table. This is used for initial platform startup.
+ * These vectors are to catch any un-intended traps.
  */
 _vectors:
+INITSP:	.long	0x00000000		/* Initial SP	*/
+INITPC:	.long	_START			/* Initial PC	*/
 
-INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC		*/
-vector02:	.long	_FAULT	/* Access Error		*/
-vector03:	.long	_FAULT	/* Address Error	*/
-vector04:	.long	_FAULT	/* Illegal Instruction	*/
-vector05:	.long	_FAULT	/* Reserved		*/
-vector06:	.long	_FAULT	/* Reserved		*/
-vector07:	.long	_FAULT	/* Reserved		*/
-vector08:	.long	_FAULT	/* Privilege Violation	*/
-vector09:	.long	_FAULT	/* Trace		*/
-vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
-vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
-vector0C:	.long	_FAULT	/* Debug Interrupt	*/
-vector0D:	.long	_FAULT	/* Reserved		*/
-vector0E:	.long	_FAULT	/* Format Error		*/
-vector0F:	.long	_FAULT	/* Unitialized Int.	*/
+vector02_0F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* Reserved */
 vector10_17:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-vector18:	.long	_FAULT	/* Spurious Interrupt	*/
-vector19:	.long	_FAULT	/* Autovector Level 1	*/
-vector1A:	.long	_FAULT	/* Autovector Level 2	*/
-vector1B:	.long	_FAULT	/* Autovector Level 3	*/
-vector1C:	.long	_FAULT	/* Autovector Level 4	*/
-vector1D:	.long	_FAULT	/* Autovector Level 5	*/
-vector1E:	.long	_FAULT	/* Autovector Level 6	*/
-vector1F:	.long	_FAULT	/* Autovector Level 7	*/
+vector18_1F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
 /* TRAP #0 - #15 */
 vector20_2F:
@@ -104,13 +88,13 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 
-	.text
+.text
 
-	.globl	_start
+.globl _start
 _start:
 	nop
 	nop
-	move.w #0x2700,%sr		/* Mask off Interrupt */
+	move.w	#0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
@@ -122,7 +106,7 @@ _start:
 	move.l	#(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
-	move.l	#CONFIG_SYS_MBAR, %d0		/* set MBAR address */
+	move.l	#CONFIG_SYS_MBAR, %d0	/* set MBAR address */
 	move.c	%d0, %MBAR
 
 	/* invalidate and disable cache */
@@ -135,17 +119,17 @@ _start:
 	movec	%d0, %ACR3
 
 	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
+	move.l	#0, %d0
+	move.l	#(ICACHE_STATUS), %a1	/* icache */
+	move.l	#(DCACHE_STATUS), %a2	/* icache */
+	move.l	%d0, (%a1)
+	move.l	%d0, (%a2)
 
 	/* put relocation table address to a5 */
-	move.l #__got_start, %a5
+	move.l	#__got_start, %a5
 
 	/* setup stack initially on top of internal static ram  */
-	move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
 
 	/*
 	 * if configured, malloc_f arena will be reserved first,
@@ -159,16 +143,19 @@ _start:
 	move.l  %sp, %fp
 
 	/* initialize reserved area */
-	move.l  %d0, -(%sp)
-	bsr     board_init_f_init_reserve
+	move.l	%d0, -(%sp)
+	bsr	board_init_f_init_reserve
+
+	/* run low-level CPU init code (from flash) */
+	jbsr	cpu_init_f
 
-	jbsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	clr.l   %sp@-
-	jbsr board_init_f		/* run low-level board init code (from flash) */
+	/* run low-level board init code (from flash) */
+	clr.l	%sp@-
+	jbsr	board_init_f
 
 	/* board_init_f() does not return */
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
@@ -181,23 +168,23 @@ _start:
  * r5 = length in bytes
  * r6 = cachelinesize
  */
-	.globl	relocate_code
+.globl relocate_code
 relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
+	link.w	%a6,#0
+	move.l	8(%a6), %sp		/* set new stack pointer */
 
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+	move.l	12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l	16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
+	move.l	#CONFIG_SYS_MONITOR_BASE, %a1
+	move.l	#__init_end, %a2
+	move.l	%a0, %a3
 
 	/* copy the code to RAM */
 1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
+	move.l	(%a1)+, (%a3)+
+	cmp.l	%a1,%a2
+	bgt.s	1b
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -227,7 +214,7 @@ clear_bss:
 	 */
 	move.l	%a0, %a1
 	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a1,%a5		/* * fix got pointer register a5 */
+	move.l	%a1,%a5			/* fix got pointer register a5 */
 
 	move.l	%a0, %a2
 	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
@@ -241,39 +228,40 @@ clear_bss:
 	bne	7b
 
 	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+	move.l	%a0, %a1
+	add.l	#(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
+	move.l	%a0,-(%sp)		/* dest_addr */
+	move.l	%d0,-(%sp)		/* gd */
 	jsr	(%a1)
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
+
 /* exception code */
-	.globl _fault
+.globl _fault
 _fault:
-	bra _fault
-	.globl	_exc_handler
+	bra	_fault
 
+.globl _exc_handler
 _exc_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr exc_handler
+	bsr	exc_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-	.globl	_int_handler
+.globl _int_handler
 _int_handler:
 	SAVE_ALL
 	movel	%sp,%sp@-
-	bsr int_handler
+	bsr	int_handler
 	addql	#4,%sp
 	RESTORE_ALL
 
-/*------------------------------------------------------------------------------*/
+/******************************************************************************/
 
-	.globl	version_string
+.globl version_string
 version_string:
-	.ascii U_BOOT_VERSION_STRING, "\0"
-	.align 4
+.ascii U_BOOT_VERSION_STRING, "\0"
+.align 4
-- 
cgit v0.10.2


From 46683f3da191a4c2156d5473c23b9923c461912c Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 22 Jul 2016 17:22:50 +0800
Subject: mmc-uclass: correct the device number

Not like the mmc-legacy which the devnum starts from 1, it starts from 0
in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 38ced41..f262c6e 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -111,18 +111,18 @@ struct mmc *find_mmc_device(int dev_num)
 
 int get_mmc_num(void)
 {
-	return max(blk_find_max_devnum(IF_TYPE_MMC), 0);
+	return max((blk_find_max_devnum(IF_TYPE_MMC) + 1), 0);
 }
 
 int mmc_get_next_devnum(void)
 {
 	int ret;
 
-	ret = get_mmc_num();
+	ret = blk_find_max_devnum(IF_TYPE_MMC);
 	if (ret < 0)
 		return ret;
 
-	return ret + 1;
+	return ret;
 }
 
 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
diff --git a/include/mmc.h b/include/mmc.h
index 8f309f1..dd47f34 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -503,6 +503,12 @@ void mmc_set_clock(struct mmc *mmc, uint clock);
 struct mmc *find_mmc_device(int dev_num);
 int mmc_set_dev(int dev_num);
 void print_mmc_devices(char separator);
+
+/**
+ * get_mmc_num() - get the total MMC device number
+ *
+ * @return 0 if there is no MMC device, else the number of devices
+ */
 int get_mmc_num(void);
 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 		      enum mmc_hwpart_conf_mode mode);
-- 
cgit v0.10.2


From 22948e1015140913b47b2886cfb08322b2538849 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 22 Jul 2016 17:41:37 +0800
Subject: configs: rockchip: remove no use MACRO

The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now,
remove them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index f7562bd..0804714 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -12,9 +12,6 @@ config SYS_SOC
 config SYS_MALLOC_F_LEN
 	default 0x400
 
-config ROCKCHIP_COMMON
-	bool "Support rk common fuction"
-
 source "board/rockchip/evb_rk3036/Kconfig"
 source "board/rockchip/kylin_rk3036/Kconfig"
 
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index ae4b101..b003baa 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -40,8 +40,6 @@
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(4 << 10)
 #define CONFIG_ROCKCHIP_CHIP_TAG	"RK30"
 
-#define CONFIG_ROCKCHIP_COMMON
-
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 2a36c17..be6dba0 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -44,9 +44,6 @@
 #define CONFIG_SPL_STACK		0xff718000
 #define CONFIG_SPL_TEXT_BASE		0xff704004
 
-#define CONFIG_ROCKCHIP_COMMON
-#define CONFIG_SPL_ROCKCHIP_COMMON
-
 #define CONFIG_SILENT_CONSOLE
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_SYS_CONSOLE_IS_IN_ENV
-- 
cgit v0.10.2


From b357a7f7525160daa36b1814760ff57be9bb720d Mon Sep 17 00:00:00 2001
From: Xu Ziyuan <xzy.xu@rock-chips.com>
Date: Sat, 23 Jul 2016 15:09:28 +0800
Subject: rockchip: rk3036: update MAINTAINER file

Update MAINTAINER files for kylin_rk3036, evb_rk3036.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/board/rockchip/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3036/MAINTAINERS
index 152d31c..91f8a83 100644
--- a/board/rockchip/evb_rk3036/MAINTAINERS
+++ b/board/rockchip/evb_rk3036/MAINTAINERS
@@ -1,6 +1,6 @@
 EVB-RK3036
 M:      huang lin <hl@rock-chips.com>
 S:      Maintained
-F:      board/evb/evb-rk3036
-F:      include/configs/evb-rk3036.h
+F:      board/rockchip/evb_rk3036
+F:      include/configs/evb_rk3036.h
 F:      configs/evb-rk3036_defconfig
diff --git a/board/rockchip/kylin_rk3036/MAINTAINERS b/board/rockchip/kylin_rk3036/MAINTAINERS
index f8ee834..5453e7d 100644
--- a/board/rockchip/kylin_rk3036/MAINTAINERS
+++ b/board/rockchip/kylin_rk3036/MAINTAINERS
@@ -1,6 +1,6 @@
 KYLIN-RK3036
 M:      huang lin <hl@rock-chips.com>
 S:      Maintained
-F:      board/kylin/kylin-rk3036
-F:      include/configs/kylin-rk3036.h
+F:      board/rockchip/kylin_rk3036
+F:      include/configs/kylin_rk3036.h
 F:      configs/kylin-rk3036_defconfig
-- 
cgit v0.10.2


From 633fdab0cb95a274a17108cd14ceafab1d4b7430 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 25 Jul 2016 11:45:54 +0800
Subject: rk3399: Reserve space for ARM Trust Firmware

RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index dffacd0..cb2d97d 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -21,6 +21,7 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = 0;
+	/* Reserve 0x200000 for ATF bl31 */
+	gd->bd->bi_dram[0].start = 0x200000;
 	gd->bd->bi_dram[0].size = 0x80000000;
 }
-- 
cgit v0.10.2


From 2b51784aef46523ed70916b09de125bc5fbefa25 Mon Sep 17 00:00:00 2001
From: John Keeping <john@metanate.com>
Date: Mon, 25 Jul 2016 10:02:05 +0100
Subject: rockchip: rk3288: Fix pinctrl for GPIO bank 0

Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers.  In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.

Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed.  The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index ae8a4f1..0322264 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -588,6 +588,7 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 	struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 	uint shift, ind = index;
 	uint mask;
+	uint value;
 	u32 *addr;
 	int ret;
 
@@ -596,7 +597,18 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 					  &mask);
 	if (ret)
 		return ret;
-	rk_clrsetreg(addr, mask << shift, muxval << shift);
+
+	/*
+	 * PMU_GPIO0 registers cannot be selectively written so we cannot use
+	 * rk_clrsetreg() here.  However, the upper 16 bits are reserved and
+	 * are ignored when written, so we can use the same code as for the
+	 * other GPIO banks providing that we preserve the value of the other
+	 * bits.
+	 */
+	value = readl(addr);
+	value &= ~(mask << shift);
+	value |= (mask << (shift + 16)) | (muxval << shift);
+	writel(value, addr);
 
 	/* Handle pullup/pulldown */
 	if (flags) {
@@ -614,7 +626,12 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 			addr = &priv->grf->gpio1_p[banknum - 1][ind];
 		debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 		      shift);
-		rk_clrsetreg(addr, 3 << shift, val << shift);
+
+		/* As above, rk_clrsetreg() cannot be used here. */
+		value = readl(addr);
+		value &= ~(mask << shift);
+		value |= (3 << (shift + 16)) | (val << shift);
+		writel(value, addr);
 	}
 
 	return 0;
-- 
cgit v0.10.2


From 8a632ac135fbdc89c70de86137a3bc0632b7032b Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:21 +0800
Subject: rockchip: add a dummy byte for the sdram-channel property

Add an extra byte so that this data is not byteswapped.

Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts
index caf24ee..3e1ee58 100644
--- a/arch/arm/dts/rk3288-evb.dts
+++ b/arch/arm/dts/rk3288-evb.dts
@@ -25,7 +25,8 @@
 		0x8 0x1f4>;
 	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
 		0x0 0xc3 0x6 0x2>;
-	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe>;
+	/* Add a dummy value to cause of-platdata think this is bytes */
+	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
 	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
 };
 
-- 
cgit v0.10.2


From 194a241a6ed873ec8de6848e850ff29b4b789e74 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:22 +0800
Subject: cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming

Revise config to CONFIG_ROCKCHIP_RK3288_PINCTRL.

Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 41cfedd..93be4a5 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -46,7 +46,7 @@ CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_REGULATOR=y
-- 
cgit v0.10.2


From 5051a77b2dc2c8dc1f7454ed900b94d228ad4bd5 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:23 +0800
Subject: Revert "rockchip: Move the MMC setup check earlier"

Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to
setup sdmmc gpio, otherwise we will hit an error below:

=>mmc info
blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1
   - -1 0
   - found
uclass_find_device_by_seq: 0 1
   - -1 -1
   - -1 0
   - not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
Buswidth = 1, clock: 0
Buswidth = 1, clock: 400000
Sending CMD0
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy

This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index ed14023..1b74173 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -116,6 +116,9 @@ static void configure_l2ctlr(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
+#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288) && \
+	!defined(CONFIG_TARGET_EVB_RK3288)
+
 	struct gpio_desc desc;
 	int ret;
 
@@ -145,7 +148,7 @@ static int configure_emmc(struct udevice *pinctrl)
 		debug("gpio value ret=%d\n", ret);
 		return ret;
 	}
-
+#endif
 	return 0;
 }
 #endif
@@ -249,20 +252,17 @@ void spl_board_init(void)
 		debug("%s: Cannot find pinctrl device\n", __func__);
 		goto err;
 	}
+
 #ifdef CONFIG_SPL_MMC_SUPPORT
-	if (!IS_ENABLED(CONFIG_TARGET_ROCK2) &&
-	    !IS_ENABLED(CONFIG_TARGET_FIREFLY_RK3288) &&
-	    !IS_ENABLED(CONFIG_TARGET_EVB_RK3288)) {
-		ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-		if (ret) {
-			debug("%s: Failed to set up SD card\n", __func__);
-			goto err;
-		}
-		ret = configure_emmc(pinctrl);
-		if (ret) {
-			debug("%s: Failed to set up eMMC\n", __func__);
-			goto err;
-		}
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+	if (ret) {
+		debug("%s: Failed to set up SD card\n", __func__);
+		goto err;
+	}
+	ret = configure_emmc(pinctrl);
+	if (ret) {
+		debug("%s: Failed to set up eMMC\n", __func__);
+		goto err;
 	}
 #endif
 
-- 
cgit v0.10.2


From 1743d0bafc5ffc36ba8993badf0ba687e126e189 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:24 +0800
Subject: rockchip: rk3288: disable fastboot in SPL stage

Reduce compilation time for SPL.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index be6dba0..9f2dd3f 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -81,6 +81,7 @@
 #define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
+#ifndef CONFIG_SPL_BUILD
 /* usb otg */
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_DUALSPEED
@@ -107,7 +108,6 @@
 #define CONFIG_CMD_GPT
 #define CONFIG_EFI_PARTITION
 
-#ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
 #define ENV_MEM_LAYOUT_SETTINGS \
-- 
cgit v0.10.2


From 77337c1c7a0d5e2bc15db4c6d237550c8af26942 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:25 +0800
Subject: rockchip: remove the duplicated macro config

CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in
config_distro_defaults.h, and we don't need them in SPL stage.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
index b16c03f..e8ca76d 100644
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@@ -26,7 +26,6 @@
 /* Enable gpt partition table */
 #define CONFIG_CMD_GPT
 #define CONFIG_RANDOM_UUID
-#define CONFIG_EFI_PARTITION
 #define PARTS_DEFAULT \
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name=loader,start=32K,size=4000K,uuid=${uuid_gpt_loader};" \
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index b003baa..ffcaa6f 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -46,7 +46,6 @@
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
-#define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 9f2dd3f..0b7d723 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -56,7 +56,6 @@
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
-#define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
@@ -106,7 +105,6 @@
 
 /* Enable gpt partition table */
 #define CONFIG_CMD_GPT
-#define CONFIG_EFI_PARTITION
 
 #include <config_distro_defaults.h>
 
-- 
cgit v0.10.2


From f75711aae72e6331fc5bb6c6b094869182fb200c Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:26 +0800
Subject: rockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDR

CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for
fastboot.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 0b7d723..814116c 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -93,9 +93,7 @@
 #define CONFIG_USB_FUNCTION_FASTBOOT
 #define CONFIG_FASTBOOT_FLASH
 #define CONFIG_FASTBOOT_FLASH_MMC_DEV	1	/* eMMC */
-/* stroe safely fastboot buffer data to the middle of bank */
-#define CONFIG_FASTBOOT_BUF_ADDR	(CONFIG_SYS_SDRAM_BASE \
-					+ SDRAM_BANK_SIZE / 2)
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE	0x08000000
 
 #define CONFIG_USB_GADGET_DOWNLOAD
-- 
cgit v0.10.2


From cba6bb1b74133060207192fba55e650d5744ed39 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:27 +0800
Subject: rockchip: rk3288: move evb board to rockchip folder

The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is
the real vendor name.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 031dbfc..67f29d2 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -53,6 +53,6 @@ source "board/firefly/firefly-rk3288/Kconfig"
 
 source "board/radxa/rock2/Kconfig"
 
-source "board/evb-rk3288/evb-rk3288/Kconfig"
+source "board/rockchip/evb_rk3288/Kconfig"
 
 endif
diff --git a/board/evb-rk3288/evb-rk3288/Kconfig b/board/evb-rk3288/evb-rk3288/Kconfig
deleted file mode 100644
index b201acb..0000000
--- a/board/evb-rk3288/evb-rk3288/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_EVB_RK3288
-
-config SYS_BOARD
-	default "evb-rk3288"
-
-config SYS_VENDOR
-	default "evb-rk3288"
-
-config SYS_CONFIG_NAME
-	default "evb-rk3288"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
diff --git a/board/evb-rk3288/evb-rk3288/MAINTAINERS b/board/evb-rk3288/evb-rk3288/MAINTAINERS
deleted file mode 100644
index 222c254..0000000
--- a/board/evb-rk3288/evb-rk3288/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-EVB-RK3288
-M:	Lin Huang <hl@rock-chips.com>
-S:	Maintained
-F:	board/evb-rk3288/evb-rk3288
-F:	include/configs/evb-rk3288.h
-F:	configs/evb-rk3288_defconfig
diff --git a/board/evb-rk3288/evb-rk3288/Makefile b/board/evb-rk3288/evb-rk3288/Makefile
deleted file mode 100644
index c11b657..0000000
--- a/board/evb-rk3288/evb-rk3288/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= evb-rk3288.o
diff --git a/board/evb-rk3288/evb-rk3288/evb-rk3288.c b/board/evb-rk3288/evb-rk3288/evb-rk3288.c
deleted file mode 100644
index a82f0ae..0000000
--- a/board/evb-rk3288/evb-rk3288/evb-rk3288.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard. */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/evb_rk3288/Kconfig b/board/rockchip/evb_rk3288/Kconfig
new file mode 100644
index 0000000..8ab07f4
--- /dev/null
+++ b/board/rockchip/evb_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3288
+
+config SYS_BOARD
+	default "evb_rk3288"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3288/MAINTAINERS b/board/rockchip/evb_rk3288/MAINTAINERS
new file mode 100644
index 0000000..8a4f127
--- /dev/null
+++ b/board/rockchip/evb_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/evb_rk3288
+F:	include/configs/evb_rk3288.h
+F:	configs/evb-rk3288_defconfig
diff --git a/board/rockchip/evb_rk3288/Makefile b/board/rockchip/evb_rk3288/Makefile
new file mode 100644
index 0000000..c11b657
--- /dev/null
+++ b/board/rockchip/evb_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3288.o
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c
new file mode 100644
index 0000000..a82f0ae
--- /dev/null
+++ b/board/rockchip/evb_rk3288/evb-rk3288.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* eMMC prior to sdcard. */
+	spl_boot_list[0] = BOOT_DEVICE_MMC2;
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
diff --git a/include/configs/evb-rk3288.h b/include/configs/evb-rk3288.h
deleted file mode 100644
index 342557f..0000000
--- a/include/configs/evb-rk3288.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define ROCKCHIP_DEVICE_SETTINGS
-#include <configs/rk3288_common.h>
-
-#define CONFIG_SPL_MMC_SUPPORT
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1
-/* SPL @ 32k for ~36k
- * ENV @ 96k
- * u-boot @ 128K
- */
-#define CONFIG_ENV_OFFSET (96 * 1024)
-
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES		10
-
-#endif
diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h
new file mode 100644
index 0000000..342557f
--- /dev/null
+++ b/include/configs/evb_rk3288.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
-- 
cgit v0.10.2


From d7ca67b7cdd67f79637a8a0097277a68294fa3d8 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:29 +0800
Subject: rockchip: add basic support for fennec-rk3288 board

Fennec is a RK3288-based development board with 2 USB ports, HDMI,
micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes
on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access
to display pins, I2C, SPI, UART and GPIOs.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7e21083..cc0d6df 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-jerry.dtb \
 	rk3288-rock2-square.dtb \
 	rk3288-evb.dtb \
+	rk3288-fennec.dtb \
 	rk3036-sdk.dtb \
 	rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts
new file mode 100644
index 0000000..36e9f3d
--- /dev/null
+++ b/arch/arm/dts/rk3288-fennec.dts
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-fennec.dtsi"
+
+/ {
+	model = "Rockchip RK3288 Fennec Board";
+	compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&dmc {
+	rockchip,num-channels = <2>;
+	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+		0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+		0x8 0x1f4>;
+	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+		0x0 0xc3 0x6 0x2>;
+	/* Add a dummy value to cause of-platdata think this is bytes */
+	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
+	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	reg-shift = <2>;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-fennec.dtsi b/arch/arm/dts/rk3288-fennec.dtsi
new file mode 100644
index 0000000..f61252c
--- /dev/null
+++ b/arch/arm/dts/rk3288-fennec.dtsi
@@ -0,0 +1,421 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+	memory {
+		reg = <0x0 0x80000000>;
+		device_type = "memory";
+	};
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	status = "okay";
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int &global_pwroff>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_io>;
+		vcc9-supply = <&vcc_io>;
+		vcc10-supply = <&vcc_io>;
+		vcc11-supply = <&vcc_io>;
+		vcc12-supply = <&vcc_io>;
+		vddio-supply = <&vcc_io>;
+
+		regulators {
+			vdd_cpu: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_arm";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1250000>;
+				regulator-name = "vdd_gpu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_io";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_pmu: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_33: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcca_33";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd_10";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_wl: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_wl";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd10_lcd: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_lcd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_18: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_18";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_lcd: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_lcd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_sd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_lan: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_lan";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+		drive-strength = <8>;
+	};
+
+	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	gmac {
+		phy_int: phy-int {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rst: phy-rst {
+			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+		};
+
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usbphy {
+		host_drv: host-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&host_drv>;
+	vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host1 {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
+
+&usb_hsic {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 1b74173..e0d92a6 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -116,8 +116,7 @@ static void configure_l2ctlr(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
-#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288) && \
-	!defined(CONFIG_TARGET_EVB_RK3288)
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
 
 	struct gpio_desc desc;
 	int ret;
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 67f29d2..4bfd78b 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,6 +16,14 @@ config TARGET_EVB_RK3288
 	  also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
 	  provide access to display pins, I2C, SPI, UART and GPIOs.
 
+config TARGET_FENNEC_RK3288
+	bool "Fennec-RK3288"
+	help
+	  Fennec is a RK3288-based development board with 2 USB ports,
+	  HDMI, micro-SD card, audio, WiFi and Gigabit Ethernet. It also
+	  includes on-board eMMC and 2GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
 config TARGET_CHROMEBOOK_JERRY
 	bool "Google/Rockchip Veyron-Jerry Chromebook"
 	help
@@ -55,4 +63,6 @@ source "board/radxa/rock2/Kconfig"
 
 source "board/rockchip/evb_rk3288/Kconfig"
 
+source "board/rockchip/fennec_rk3288/Kconfig"
+
 endif
diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig
new file mode 100644
index 0000000..1dcfcf0
--- /dev/null
+++ b/board/rockchip/fennec_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_FENNEC_RK3288
+
+config SYS_BOARD
+	default "fennec_rk3288"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "fennec_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/fennec_rk3288/MAINTAINERS b/board/rockchip/fennec_rk3288/MAINTAINERS
new file mode 100644
index 0000000..78a389b
--- /dev/null
+++ b/board/rockchip/fennec_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+FENNEC-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/fennec_rk3288
+F:	include/configs/fennec_rk3288.h
+F:	configs/fennec-rk3288_defconfig
diff --git a/board/rockchip/fennec_rk3288/Makefile b/board/rockchip/fennec_rk3288/Makefile
new file mode 100644
index 0000000..b287db6
--- /dev/null
+++ b/board/rockchip/fennec_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= fennec-rk3288.o
diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c
new file mode 100644
index 0000000..aad74ef
--- /dev/null
+++ b/board/rockchip/fennec_rk3288/fennec-rk3288.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* eMMC prior to sdcard */
+	spl_boot_list[0] = BOOT_DEVICE_MMC2;
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
new file mode 100644
index 0000000..bcd6ebf
--- /dev/null
+++ b/configs/fennec-rk3288_defconfig
@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_FENNEC_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SYSRESET=y
+CONFIG_DM_MMC=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK808=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_SPL_SIMPLE_BUS is not set
diff --git a/doc/README.rockchip b/doc/README.rockchip
index c218a8b..1e44917 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -36,12 +36,13 @@ You will need:
 Building
 ========
 
-At present four RK3288 boards are supported:
+At present five RK3288 boards are supported:
 
    - Firefly RK3288 - use firefly-rk3288 configuration
    - Radxa Rock 2 - use rock2 configuration
    - Hisense Chromebook - use chromebook_jerry configuration
    - EVB RK3288 - use evb-rk3288 configuration
+   - Fennec RK3288 - use fennec-rk3288 configuration
 
 Two RK3036 board are supported:
 
diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h
new file mode 100644
index 0000000..342557f
--- /dev/null
+++ b/include/configs/fennec_rk3288.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
-- 
cgit v0.10.2


From dd63fbc70a5fa59677c86695ebad341834fec172 Mon Sep 17 00:00:00 2001
From: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Date: Tue, 26 Jul 2016 18:28:30 +0800
Subject: rockchip: add support for rk3288 PopMetal board

PopMetal is a rockchip rk3288 based board made by ChipSpark, which has
many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and
Gigabit Ethernet.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cc0d6df..639c06d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-rock2-square.dtb \
 	rk3288-evb.dtb \
 	rk3288-fennec.dtb \
+	rk3288-popmetal.dtb \
 	rk3036-sdk.dtb \
 	rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts
new file mode 100644
index 0000000..3f61a61
--- /dev/null
+++ b/arch/arm/dts/rk3288-popmetal.dts
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-popmetal.dtsi"
+
+/ {
+	model = "PopMetal-RK3288";
+	compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&dmc {
+	rockchip,num-channels = <2>;
+	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+		0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+		0x5 0x0>;
+	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+		0xa60 0x40 0x10 0x0>;
+	/* Add a dummy value to cause of-platdata think this is bytes */
+	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
+	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	reg-shift = <2>;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+	u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi
new file mode 100644
index 0000000..f3bd468
--- /dev/null
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -0,0 +1,520 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+	memory{
+		device_type = "memory";
+		reg = <0 0x80000000>;
+	};
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		power {
+			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,input-type = <1>;
+			wakeup-source;
+			debounce-interval = <100>;
+		};
+	};
+
+	io_domains: io-domains {
+		compatible = "rockchip,rk3288-io-voltage-domain";
+		rockchip,grf = <&grf>;
+
+		audio-supply = <&vcca_33>;
+		bb-supply = <&vcc_io>;
+		dvp-supply = <&vcc18_dvp>;
+		flash0-supply = <&vcc_flash>;
+		flash1-supply = <&vcc_lan>;
+		gpio30-supply = <&vcc_io>;
+		gpio1830-supply = <&vcc_io>;
+		lcdc-supply = <&vcc_io>;
+		sdcard-supply = <&vccio_sd>;
+		wifi-supply = <&vccio_wl>;
+	};
+
+	ir: ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_int>;
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	/*
+	 * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled
+	 * by the dvp_pwr pin.
+	 */
+	vcc18_dvp: vcc18-dvp-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc18-dvp";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc28_dvp>;
+	};
+
+	vcc28_dvp: vcc28-dvp-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&dvp_pwr>;
+		regulator-name = "vcc28_dvp";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		regulator-always-on;
+		vin-supply = <&vcc_io>;
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_flash>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&gmac {
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio4 7 0>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "ok";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c5>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int &global_pwroff>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_18>;
+		vcc9-supply = <&vcc_io>;
+		vcc10-supply = <&vcc_io>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc_io>;
+		vddio-supply = <&vcc_io>;
+
+		regulators {
+			vdd_cpu: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_arm";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1250000>;
+				regulator-name = "vdd_gpu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_io";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_lan: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_lan";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_sd: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd_10";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc18_lcd: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_lcd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			ldo5: LDO_REG5 {
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "ldo5";
+			};
+
+			vdd10_lcd: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_lcd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_18: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_18";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_33: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcca_33";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_wl: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vccio_wl";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_lcd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_lcd";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	ak8963: ak8963@0d {
+		compatible = "asahi-kasei,ak8975";
+		reg = <0x0d>;
+		interrupt-parent = <&gpio8>;
+		interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&comp_int>;
+	};
+
+	l3g4200d: l3g4200d@68 {
+		compatible = "st,l3g4200d-gyro";
+		st,drdy-int-pin = <2>;
+		reg = <0x6b>;
+	};
+
+	mma8452: mma8452@1d {
+		compatible = "fsl,mma8452";
+		reg = <0x1d>;
+		interrupt-parent = <&gpio8>;
+		interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gsensor_int>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pinctrl {
+	ak8963 {
+		comp_int: comp-int {
+			rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	dvp {
+		dvp_pwr: dvp-pwr {
+			rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	mma8452 {
+		gsensor_int: gsensor-int {
+			rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 4bfd78b..8ec1920 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -24,6 +24,15 @@ config TARGET_FENNEC_RK3288
 	  includes on-board eMMC and 2GB of SDRAM. Expansion connectors
 	  provide access to display pins, I2C, SPI, UART and GPIOs.
 
+config TARGET_POPMETAL_RK3288
+	bool "PopMetal-RK3288"
+	help
+	  PopMetal is a RK3288-based development board with 3 USB host ports,
+	  1 micro USB OTG port, HDMI, VGA, micro-SD card, audio, WiFi, Gigabit
+	  Ethernet and lots of sensors. It also includes on-board 8 GeMMC and
+	  2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
+	  GPIOs and display interface.
+
 config TARGET_CHROMEBOOK_JERRY
 	bool "Google/Rockchip Veyron-Jerry Chromebook"
 	help
@@ -65,4 +74,6 @@ source "board/rockchip/evb_rk3288/Kconfig"
 
 source "board/rockchip/fennec_rk3288/Kconfig"
 
+source "board/chipspark/popmetal_rk3288/Kconfig"
+
 endif
diff --git a/board/chipspark/popmetal_rk3288/Kconfig b/board/chipspark/popmetal_rk3288/Kconfig
new file mode 100644
index 0000000..a5f4043
--- /dev/null
+++ b/board/chipspark/popmetal_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POPMETAL_RK3288
+
+config SYS_BOARD
+	default "popmetal_rk3288"
+
+config SYS_VENDOR
+	default "chipspark"
+
+config SYS_CONFIG_NAME
+	default "popmetal_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/chipspark/popmetal_rk3288/MAINTAINERS b/board/chipspark/popmetal_rk3288/MAINTAINERS
new file mode 100644
index 0000000..1a6a1bb
--- /dev/null
+++ b/board/chipspark/popmetal_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+POPMETAL-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/chipspark/popmetal_rk3288
+F:	include/configs/popmetal_rk3288.h
+F:	configs/popmetal-rk3288_defconfig
diff --git a/board/chipspark/popmetal_rk3288/Makefile b/board/chipspark/popmetal_rk3288/Makefile
new file mode 100644
index 0000000..86d66b0
--- /dev/null
+++ b/board/chipspark/popmetal_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= popmetal-rk3288.o
diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
new file mode 100644
index 0000000..aad74ef
--- /dev/null
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* eMMC prior to sdcard */
+	spl_boot_list[0] = BOOT_DEVICE_MMC2;
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
new file mode 100644
index 0000000..653bfed
--- /dev/null
+++ b/configs/popmetal-rk3288_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_POPMETAL_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SYSRESET=y
+CONFIG_DM_MMC=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK808=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 1e44917..1b3a602 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -36,13 +36,14 @@ You will need:
 Building
 ========
 
-At present five RK3288 boards are supported:
+At present six RK3288 boards are supported:
 
    - Firefly RK3288 - use firefly-rk3288 configuration
    - Radxa Rock 2 - use rock2 configuration
    - Hisense Chromebook - use chromebook_jerry configuration
    - EVB RK3288 - use evb-rk3288 configuration
    - Fennec RK3288 - use fennec-rk3288 configuration
+   - PopMetal RK3288 - use popmetal-rk3288 configuration
 
 Two RK3036 board are supported:
 
diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h
new file mode 100644
index 0000000..342557f
--- /dev/null
+++ b/include/configs/popmetal_rk3288.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
-- 
cgit v0.10.2


From 4694dc56e974eac94d6a4aa07c3d4071bf64e28c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 22 Jul 2016 16:12:59 +0800
Subject: sunxi: gpio: Add .xlate function for gpio phandle resolution

sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.

Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.

Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver
		      model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 94abbeb..e8accaa 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -215,12 +216,27 @@ static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
 		return GPIOF_FUNC;
 }
 
+static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+			    struct fdtdec_phandle_args *args)
+{
+	int ret;
+
+	ret = device_get_child(dev, args->args[0], &desc->dev);
+	if (ret)
+		return ret;
+	desc->offset = args->args[1];
+	desc->flags = args->args[2] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
 static const struct dm_gpio_ops gpio_sunxi_ops = {
 	.direction_input	= sunxi_gpio_direction_input,
 	.direction_output	= sunxi_gpio_direction_output,
 	.get_value		= sunxi_gpio_get_value,
 	.set_value		= sunxi_gpio_set_value,
 	.get_function		= sunxi_gpio_get_function,
+	.xlate			= sunxi_gpio_xlate,
 };
 
 /**
-- 
cgit v0.10.2


From 3e5e274aed347cfcbf7cb7772fcd51d513f59402 Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Fri, 22 Jul 2016 16:13:00 +0800
Subject: sunxi: Hummingbird_A31_defconfig: Drop MACPWR option

MACPWR was used to bring the Ethernet PHY out of reset. The designware
driver now supports the phy reset gpio binding, so this is no longer
needed. In fact in requesting the same GPIO, it makes the designware
driver fail to probe.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 02bcdbf..3b0c439 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -9,7 +9,7 @@ CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
-- 
cgit v0.10.2


From 97322c3e074d49b1e2c6d98c7e69e5da3093636f Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 27 Jul 2016 17:58:06 +0200
Subject: sunxi: Ensure that the NIC specific bytes of the mac are not all 0

On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.

This commits adds a check to ensure this does not happen.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 36cf963..ef3fe26 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -623,6 +623,10 @@ static void setup_environment(const void *fdt)
 
 	ret = sunxi_get_sid(sid);
 	if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
+		/* Ensure the NIC specific bytes of the mac are not all 0 */
+		if ((sid[3] & 0xffffff) == 0)
+			sid[3] |= 0x800000;
+
 		for (i = 0; i < 4; i++) {
 			sprintf(ethaddr, "ethernet%d", i);
 			if (!fdt_get_alias(fdt, ethaddr))
-- 
cgit v0.10.2


From 3f8ea3b06eaf7c9e2456058bcbde32461e73aeb7 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 29 Jul 2016 11:47:03 +0200
Subject: sunxi: On newer SoCs use words 1-3 instead of just word 3 from the
 SID

It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,

This commits switches to using the crc32 of words 1 - 3 to get a
more unique value for the mac-address / serialnr.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index ef3fe26..209fb1c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -27,6 +27,7 @@
 #endif
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <crc.h>
 #include <environment.h>
 #include <libfdt.h>
 #include <nand.h>
@@ -622,7 +623,24 @@ static void setup_environment(const void *fdt)
 	int i, ret;
 
 	ret = sunxi_get_sid(sid);
-	if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
+	if (ret == 0 && sid[0] != 0) {
+		/*
+		 * The single words 1 - 3 of the SID have quite a few bits
+		 * which are the same on many models, so we take a crc32
+		 * of all 3 words, to get a more unique value.
+		 *
+		 * Note we only do this on newer SoCs as we cannot change
+		 * the algorithm on older SoCs since those have been using
+		 * fixed mac-addresses based on only using word 3 for a
+		 * long time and changing a fixed mac-address with an
+		 * u-boot update is not good.
+		 */
+#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
+    !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
+    !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
+		sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
+#endif
+
 		/* Ensure the NIC specific bytes of the mac are not all 0 */
 		if ((sid[3] & 0xffffff) == 0)
 			sid[3] |= 0x800000;
-- 
cgit v0.10.2


From 4069437dfbb2f70b92a84af7ce2d5cfba27247b9 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 27 Jul 2016 17:31:17 +0200
Subject: net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers

This fixes the following CACHE warnings when using sun8i_emac:

=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)

Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 7c088c3..4c149e1 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -32,7 +32,14 @@
 
 #define CONFIG_TX_DESCR_NUM	32
 #define CONFIG_RX_DESCR_NUM	32
-#define CONFIG_ETH_BUFSIZE	2024
+#define CONFIG_ETH_BUFSIZE	2048 /* Note must be dma aligned */
+
+/*
+ * The datasheet says that each descriptor can transfers up to 4096 bytes
+ * But later, the register documentation reduces that value to 2048,
+ * using 2048 cause strange behaviours and even BSP driver use 2047
+ */
+#define CONFIG_ETH_RXSIZE	2044 /* Note must fit in ETH_BUFSIZE */
 
 #define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
 #define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
@@ -324,7 +331,7 @@ static void rx_descs_init(struct emac_eth_dev *priv)
 		desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
 			;
 		desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
-		desc_p->st |= CONFIG_ETH_BUFSIZE;
+		desc_p->st |= CONFIG_ETH_RXSIZE;
 		desc_p->status = BIT(31);
 	}
 
@@ -506,7 +513,7 @@ static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
 					roundup(data_end,
 						ARCH_DMA_MINALIGN));
 		if (good_packet) {
-			if (length > CONFIG_ETH_BUFSIZE) {
+			if (length > CONFIG_ETH_RXSIZE) {
 				printf("Received packet is too big (len=%d)\n",
 				       length);
 				return -EMSGSIZE;
-- 
cgit v0.10.2


From fcada3b05e56c9b22bf5f92ba94fa80449452e76 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 27 Jul 2016 18:06:35 +0200
Subject: sunxi: Re-enable h3 emac support

With the recent bug fixes for the sun8i_emac driver all known issues
are resolved, so we can re-enable the driver.

While at it, also enable the emac on the Orange Pi One.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts
index 0adf932..8df5c74 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts
@@ -94,6 +94,17 @@
 	status = "okay";
 };
 
+&emac {
+	phy = <&phy1>;
+	phy-mode = "mii";
+	allwinner,use-internal-phy;
+	allwinner,leds-active-low;
+	status = "okay";
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index be8afca..81299e6 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -13,3 +13,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SUN8I_EMAC=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 366fa08..2281aed 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -14,3 +14,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SUN8I_EMAC=y
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index c78aec3..3ec6dac 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -15,3 +15,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_SUN8I_EMAC=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0bf79bf..5c97de1 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,3 +10,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_SUN8I_EMAC=y
-- 
cgit v0.10.2


From f3dbf1f0c9101bf303cb5f52bca6ba02aebc1e45 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Mon, 1 Aug 2016 09:00:13 -0700
Subject: powerpc/mpc85xx: Update erratum workaround for A006379

Update erratum workaround for A006379 to set register CPCHDBCR0
with value 0x001e0000, replacing the old value 0x003c0000.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Dave Liu <dave.liu@nxp.com>

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c045a24..7a878be 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1579,7 +1579,7 @@ typedef struct cpc_corenet {
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
-#define CPC_HDBCR0_SPLRU_LEVEL_EN	0x003c0000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN	0x001e0000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
-- 
cgit v0.10.2


From 04e5c6d9cca668845f9f4b702f587c4dcc0ea4bd Mon Sep 17 00:00:00 2001
From: Yunhui Cui <yunhui.cui@nxp.com>
Date: Wed, 13 Jul 2016 10:46:27 +0800
Subject: driver: spi: fsl-qspi: remove compile Warnings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 75cbab2..2144fca 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -386,6 +386,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 {
 	struct fsl_qspi_regs *regs = priv->regs;
 	u32 mcr_reg;
+	void *rx_addr = NULL;
 
 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 
@@ -393,8 +394,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 		     QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 		     QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 
+	rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 	/* Read out the data directly from the AHB buffer. */
-	memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
+	memcpy(rxbuf, rx_addr, len);
 
 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
-- 
cgit v0.10.2


From 7fe1d6a41092da00e0a1b94ae0e996cf89e81e28 Mon Sep 17 00:00:00 2001
From: Sumit Garg <sumit.garg@nxp.com>
Date: Thu, 14 Jul 2016 13:27:50 -0400
Subject: crypto/fsl: Update blob cmd to accept 64bit addresses

Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/cmd/blob.c b/cmd/blob.c
index ac8b268..bdd4cfd 100644
--- a/cmd/blob.c
+++ b/cmd/blob.c
@@ -54,7 +54,7 @@ __weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
  */
 static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-	uint32_t key_addr, src_addr, dst_addr, len;
+	ulong key_addr, src_addr, dst_addr, len;
 	uint8_t *km_ptr, *src_ptr, *dst_ptr;
 	int enc, ret = 0;
 
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index 8b25921..d24b8fc 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -18,7 +18,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	int ret, i = 0;
 	u32 *desc;
 
-	printf("\nDecapsulating data to form blob\n");
+	printf("\nDecapsulating blob to get data\n");
 	desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
 	if (!desc) {
 		debug("Not enough memory for descriptor allocation\n");
@@ -27,12 +27,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 
 	inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
 
+	debug("Descriptor dump:\n");
 	for (i = 0; i < 14; i++)
-		printf("%x\n", *(desc + i));
+		debug("Word[%d]: %08x\n", i, *(desc + i));
 	ret = run_descriptor_jr(desc);
 
 	if (ret)
 		printf("Error in Decapsulation %d\n", ret);
+	else
+		printf("Decapsulation Success\n");
 
 	free(desc);
 	return ret;
@@ -51,12 +54,16 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	}
 
 	inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
+
+	debug("Descriptor dump:\n");
 	for (i = 0; i < 14; i++)
-		printf("%x\n", *(desc + i));
+		debug("Word[%d]: %08x\n", i, *(desc + i));
 	ret = run_descriptor_jr(desc);
 
 	if (ret)
 		printf("Error in Encapsulation %d\n", ret);
+	else
+		printf("Encapsulation Success\n");
 
 	free(desc);
 	return ret;
-- 
cgit v0.10.2


From 3b4dbd37dcd0b851f39dda1ff212d6ef902d4db7 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Tue, 19 Jul 2016 14:05:47 +0530
Subject: board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET

qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define
inverse value QIXIS_LBMAP_MASK.

Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
as 0b11 i.e. PORESET during qixis_reset

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index fcf402c..6e31ca0 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -28,11 +28,11 @@
 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_BRDCFG_REG		0x04
 #define QIXIS_LBMAP_SWITCH		6
-#define QIXIS_LBMAP_MASK		0xf7
+#define QIXIS_LBMAP_MASK		0x08
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x08
-#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RST_CTL_RESET		0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-- 
cgit v0.10.2


From 9c3fca2a79be3d9d67d7766bbd85efc941bcb237 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Tue, 19 Jul 2016 15:54:22 +0530
Subject: armv8: ls1012a: Enable DDR row-bank-column decoding

Enable DDR row-bank-column decoding to decode DDR address as
row-bank-column instead of bank-row-column for improving
performance of serial data transfers.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
index 281a819..833696b 100644
--- a/include/fsl_mmdc.h
+++ b/include/fsl_mmdc.h
@@ -12,7 +12,7 @@
 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1	0xff328f64
 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2	0x01ff00db
 
-#define CONFIG_SYS_MMDC_CORE_MISC		0x00000680
+#define CONFIG_SYS_MMDC_CORE_MISC		0x00001680
 #define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT	0x00000800
 #define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY	0x00002000
 #define CONFIG_SYS_MMDC_PHY_ODT_CTRL		0x0000022a
-- 
cgit v0.10.2


From 37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Tue, 19 Jul 2016 15:54:33 +0530
Subject: armv8: ls1012a: Update Refresh cycle for DDR

Refresh cycle value must be selected based on the frequency
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
value should be 0x0f3c8000.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
index 833696b..a939d89 100644
--- a/include/fsl_mmdc.h
+++ b/include/fsl_mmdc.h
@@ -43,7 +43,7 @@
 
 #define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT	0x00001067
 
-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL	0x103e8000
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL	0x0f3c8000
 
 #define START_REFRESH				0x00000001
 
-- 
cgit v0.10.2


From 6ffc490541cd464ac3340742fa278c13ac7b9d13 Mon Sep 17 00:00:00 2001
From: Wenbin Song <wenbin.song@nxp.com>
Date: Fri, 15 Jul 2016 17:17:46 +0800
Subject: armv8: ls1043a: enable pxe commands

Enable pxe command for ls1043ardb and ls1043aqds.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 0ad5261..e55fcb2 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -175,6 +175,8 @@
 
 /* Command line configuration */
 #define CONFIG_CMD_ENV
+#define CONFIG_MENU
+#define CONFIG_CMD_PXE
 
 /*  MMC  */
 #define CONFIG_MMC
-- 
cgit v0.10.2


From 473af36a889d3a7e6faad1ec95b926a21c834bf8 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 29 Jul 2016 08:46:49 -0700
Subject: board/freescale: Update MAINTAINERS files

Update maintainers for secure boot targets.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
index ac02bb7..97304c5 100644
--- a/board/freescale/b4860qds/MAINTAINERS
+++ b/board/freescale/b4860qds/MAINTAINERS
@@ -12,6 +12,6 @@ F:	configs/B4860QDS_SPIFLASH_defconfig
 F:	configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
 
 B4860QDS_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/B4860QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS
index 3de62d3..c58fc50 100644
--- a/board/freescale/bsc9132qds/MAINTAINERS
+++ b/board/freescale/bsc9132qds/MAINTAINERS
@@ -13,7 +13,7 @@ F:	configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
 F:	configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
 
 BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
 F:	configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 73b0553..708e812 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -30,7 +30,7 @@ F:	configs/P5040DS_SPIFLASH_defconfig
 F:	configs/P5040DS_SECURE_BOOT_defconfig
 
 CORENET_DS_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
 F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index b997bb0..06d888f 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -9,3 +9,7 @@ F:	configs/ls1021atwr_nor_lpuart_defconfig
 F:	configs/ls1021atwr_sdcard_ifc_defconfig
 F:	configs/ls1021atwr_sdcard_qspi_defconfig
 F:	configs/ls1021atwr_qspi_defconfig
+
+M:	Sumit Garg <sumit.garg@nxp.com>
+S:	Maintained
+F:	configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
index 84ffb63..0503a3f 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -9,6 +9,6 @@ F:	configs/ls1043ardb_nand_defconfig
 F:	configs/ls1043ardb_sdcard_defconfig
 
 LS1043A_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/ls1043ardb_SECURE_BOOT_defconfig
diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS
index 640538f..fb3565a 100644
--- a/board/freescale/t1040qds/MAINTAINERS
+++ b/board/freescale/t1040qds/MAINTAINERS
@@ -7,6 +7,6 @@ F:	configs/T1040QDS_defconfig
 F:	configs/T1040QDS_DDR4_defconfig
 
 T1040QDS_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/T1040QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 7597800..0578989 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -26,9 +26,13 @@ F:	configs/T1042D4RDB_SDCARD_defconfig
 F:	configs/T1042RDB_PI_SDCARD_defconfig
 
 T1040RDB_SECURE_BOOT BOARD
-M:	Aneesh Bansal  <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/T1040RDB_SECURE_BOOT_defconfig
 F:	configs/T1040D4RDB_SECURE_BOOT_defconfig
 F:	configs/T1042RDB_SECURE_BOOT_defconfig
 F:	configs/T1042D4RDB_SECURE_BOOT_defconfig
+
+M:	Sumit Garg <sumit.garg@nxp.com>
+S:	Maintained
+F:	configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
index d747de3..790b009 100644
--- a/board/freescale/t208xqds/MAINTAINERS
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -15,6 +15,6 @@ F:	configs/T2081QDS_SPIFLASH_defconfig
 F:	configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
 
 T2080QDS_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/T2080QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index ccbfbab..f894f77 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -10,6 +10,6 @@ F:	configs/T2080RDB_SPIFLASH_defconfig
 F:	configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
 
 T2080RDB_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
index b159113..b288571 100644
--- a/board/freescale/t4qds/MAINTAINERS
+++ b/board/freescale/t4qds/MAINTAINERS
@@ -12,7 +12,7 @@ F:	configs/T4240QDS_SDCARD_defconfig
 F:	configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
 
 T4160QDS_SECURE_BOOT BOARD
-M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/T4160QDS_SECURE_BOOT_defconfig
 F:	configs/T4240QDS_SECURE_BOOT_defconfig
-- 
cgit v0.10.2


From 8936691ba69bc322201c62e977e2803cfe67fc40 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Fri, 29 Jul 2016 09:02:29 -0700
Subject: driver/ddr/fsl: Fix timing_cfg_2

Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index abd576b..24fd366 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 18)
+		| (((wr_lat & 0x10) >> 4) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)
-- 
cgit v0.10.2


From 388aabc85d4c6a0e603e45421e7e2edadd9f24ac Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Fri, 29 Jul 2016 18:26:35 +0800
Subject: arm/PSCI: Removed unused code

Identify the PSCI node only by its name, so removed the code finding
it by compatible string.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index 8dc31d4..bcd92e7 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -51,27 +51,10 @@ int fdt_psci(void *fdt)
 		fdt_setprop_string(fdt, tmp, "enable-method", "psci");
 	}
 
-	/*
-	 * The PSCI node might be called "/psci" or might be called something
-	 * else but contain either of the compatible strings
-	 * "arm,psci"/"arm,psci-0.2"
-	 */
 	nodeoff = fdt_path_offset(fdt, "/psci");
 	if (nodeoff >= 0)
 		goto init_psci_node;
 
-	nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci");
-	if (nodeoff >= 0)
-		goto init_psci_node;
-
-	nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci-0.2");
-	if (nodeoff >= 0)
-		goto init_psci_node;
-
-	nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci-1.0");
-	if (nodeoff >= 0)
-		goto init_psci_node;
-
 	nodeoff = fdt_path_offset(fdt, "/");
 	if (nodeoff < 0)
 		return nodeoff;
-- 
cgit v0.10.2


From 2c774165449ebb180060b8596764140cfb00a1e1 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Fri, 29 Jul 2016 18:26:36 +0800
Subject: arm/PSCI: Fixed the backward compatiblity issue

Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT only for psci version 0.1, including cpu_on, cpu_off,
cpu_suspend, migrate.

Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 8aefaa7..5b8ce4d 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,6 +18,9 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
+#define ARM_PSCI_VER_1_0		(0x00010000)
+#define ARM_PSCI_VER_0_2		(0x00000002)
+
 /* PSCI 0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
 #define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index bcd92e7..af49c24 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -19,7 +19,6 @@ int fdt_psci(void *fdt)
 #if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
 	int nodeoff;
 	unsigned int psci_ver = 0;
-	char *psci_compt;
 	int tmp;
 
 	nodeoff = fdt_path_offset(fdt, "/cpus");
@@ -68,39 +67,49 @@ init_psci_node:
 	psci_ver = sec_firmware_support_psci_version();
 #endif
 	switch (psci_ver) {
-	case 0x00010000:
-		psci_compt = "arm,psci-1.0";
-		break;
-	case 0x00000002:
-		psci_compt = "arm,psci-0.2";
-		break;
+	case ARM_PSCI_VER_1_0:
+		tmp = fdt_setprop_string(fdt, nodeoff,
+				"compatible", "arm,psci-1.0");
+		if (tmp)
+			return tmp;
+	case ARM_PSCI_VER_0_2:
+		tmp = fdt_appendprop_string(fdt, nodeoff,
+				"compatible", "arm,psci-0.2");
+		if (tmp)
+			return tmp;
 	default:
-		psci_compt = "arm,psci";
+	/*
+	 * The Secure firmware framework isn't able to support PSCI version 0.1.
+	 */
+#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+		tmp = fdt_appendprop_string(fdt, nodeoff,
+				"compatible", "arm,psci");
+		if (tmp)
+			return tmp;
+		tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend",
+				ARM_PSCI_FN_CPU_SUSPEND);
+		if (tmp)
+			return tmp;
+		tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off",
+				ARM_PSCI_FN_CPU_OFF);
+		if (tmp)
+			return tmp;
+		tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on",
+				ARM_PSCI_FN_CPU_ON);
+		if (tmp)
+			return tmp;
+		tmp = fdt_setprop_u32(fdt, nodeoff, "migrate",
+				ARM_PSCI_FN_MIGRATE);
+		if (tmp)
+			return tmp;
+#endif
 		break;
 	}
 
-	tmp = fdt_setprop_string(fdt, nodeoff, "compatible", psci_compt);
-	if (tmp)
-		return tmp;
 	tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
 	if (tmp)
 		return tmp;
 
-#ifdef CONFIG_ARMV7_PSCI
-	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend",
-				ARM_PSCI_FN_CPU_SUSPEND);
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
-	if (tmp)
-		return tmp;
-	tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
-	if (tmp)
-		return tmp;
-#endif
 #endif
 	return 0;
 }
-- 
cgit v0.10.2


From bded21895d4e58e7770579fc5d7905ec34cc06a9 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Fri, 29 Jul 2016 18:26:37 +0800
Subject: arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT node

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index af49c24..baf6d70 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -65,6 +65,8 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 	psci_ver = sec_firmware_support_psci_version();
+#elif defined(CONFIG_ARMV7_PSCI_1_0)
+	psci_ver = ARM_PSCI_VER_1_0;
 #endif
 	switch (psci_ver) {
 	case ARM_PSCI_VER_1_0:
-- 
cgit v0.10.2


From ab01ef5fa617444fd95543ee04ea53ccda273269 Mon Sep 17 00:00:00 2001
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Fri, 29 Jul 2016 19:26:34 +0800
Subject: ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP

The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index 541b251..f54ac3f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -24,7 +24,7 @@ int ppa_init(void)
 	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
 	int ret;
 
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 	ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
 #else
 #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 44f86fa..857ad7b 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -14,8 +14,8 @@
 #define SEC_FIRMWARE_ERET_ADDR_REVERT
 #define CONFIG_ARMV8_PSCI
 
-#define CONFIG_SYS_LS_PPA_FW_IN_NOR
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
 #define	CONFIG_SYS_LS_PPA_FW_ADDR	0x60500000
 #endif
 #endif
-- 
cgit v0.10.2